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kvm: x86: vmx: move some vmx setting from vmx_init() to hardware_setup()
[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 108 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
b4a2d31d
RK		 128#define KVM_VMX_DEFAULT_PLE_GAP 128
129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
131#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
132#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
133 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
134
4b8d54f9
ZE		 135static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
136module_param(ple_gap, int, S_IRUGO);
137
138static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
139module_param(ple_window, int, S_IRUGO);
140
b4a2d31d
RK		 141/* Default doubles per-vcpu window every exit. */
142static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
143module_param(ple_window_grow, int, S_IRUGO);
144
145/* Default resets per-vcpu window every exit to ple_window. */
146static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
147module_param(ple_window_shrink, int, S_IRUGO);
148
149/* Default is to compute the maximum so we can never overflow. */
150static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
151static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
152module_param(ple_window_max, int, S_IRUGO);
153
83287ea4
AK		 154extern const ulong vmx_return;
155
8bf00a52 156#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 157#define VMCS02_POOL_SIZE 1
61d2ef2c 158
a2fa3e9f
GH		 159struct vmcs {
160 u32 revision_id;
161 u32 abort;
162 char data[0];
163};
164
d462b819
NHE		 165/*
166 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
167 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
168 * loaded on this CPU (so we can clear them if the CPU goes down).
169 */
170struct loaded_vmcs {
171 struct vmcs *vmcs;
172 int cpu;
173 int launched;
174 struct list_head loaded_vmcss_on_cpu_link;
175};
176
26bb0981
AK		 177struct shared_msr_entry {
178 unsigned index;
179 u64 data;
d5696725 180 u64 mask;
26bb0981
AK		 181};
182
a9d30f33
NHE		 183/*
184 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
185 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
186 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
187 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
188 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
189 * More than one of these structures may exist, if L1 runs multiple L2 guests.
190 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
191 * underlying hardware which will be used to run L2.
192 * This structure is packed to ensure that its layout is identical across
193 * machines (necessary for live migration).
194 * If there are changes in this struct, VMCS12_REVISION must be changed.
195 */
22bd0358 196typedef u64 natural_width;
a9d30f33
NHE		 197struct __packed vmcs12 {
198 /* According to the Intel spec, a VMCS region must start with the
199 * following two fields. Then follow implementation-specific data.
200 */
201 u32 revision_id;
202 u32 abort;
22bd0358 203
27d6c865
NHE		 204 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
205 u32 padding[7]; /* room for future expansion */
206
22bd0358
NHE		 207 u64 io_bitmap_a;
208 u64 io_bitmap_b;
209 u64 msr_bitmap;
210 u64 vm_exit_msr_store_addr;
211 u64 vm_exit_msr_load_addr;
212 u64 vm_entry_msr_load_addr;
213 u64 tsc_offset;
214 u64 virtual_apic_page_addr;
215 u64 apic_access_addr;
216 u64 ept_pointer;
217 u64 guest_physical_address;
218 u64 vmcs_link_pointer;
219 u64 guest_ia32_debugctl;
220 u64 guest_ia32_pat;
221 u64 guest_ia32_efer;
222 u64 guest_ia32_perf_global_ctrl;
223 u64 guest_pdptr0;
224 u64 guest_pdptr1;
225 u64 guest_pdptr2;
226 u64 guest_pdptr3;
36be0b9d 227 u64 guest_bndcfgs;
22bd0358
NHE		 228 u64 host_ia32_pat;
229 u64 host_ia32_efer;
230 u64 host_ia32_perf_global_ctrl;
231 u64 padding64[8]; /* room for future expansion */
232 /*
233 * To allow migration of L1 (complete with its L2 guests) between
234 * machines of different natural widths (32 or 64 bit), we cannot have
235 * unsigned long fields with no explict size. We use u64 (aliased
236 * natural_width) instead. Luckily, x86 is little-endian.
237 */
238 natural_width cr0_guest_host_mask;
239 natural_width cr4_guest_host_mask;
240 natural_width cr0_read_shadow;
241 natural_width cr4_read_shadow;
242 natural_width cr3_target_value0;
243 natural_width cr3_target_value1;
244 natural_width cr3_target_value2;
245 natural_width cr3_target_value3;
246 natural_width exit_qualification;
247 natural_width guest_linear_address;
248 natural_width guest_cr0;
249 natural_width guest_cr3;
250 natural_width guest_cr4;
251 natural_width guest_es_base;
252 natural_width guest_cs_base;
253 natural_width guest_ss_base;
254 natural_width guest_ds_base;
255 natural_width guest_fs_base;
256 natural_width guest_gs_base;
257 natural_width guest_ldtr_base;
258 natural_width guest_tr_base;
259 natural_width guest_gdtr_base;
260 natural_width guest_idtr_base;
261 natural_width guest_dr7;
262 natural_width guest_rsp;
263 natural_width guest_rip;
264 natural_width guest_rflags;
265 natural_width guest_pending_dbg_exceptions;
266 natural_width guest_sysenter_esp;
267 natural_width guest_sysenter_eip;
268 natural_width host_cr0;
269 natural_width host_cr3;
270 natural_width host_cr4;
271 natural_width host_fs_base;
272 natural_width host_gs_base;
273 natural_width host_tr_base;
274 natural_width host_gdtr_base;
275 natural_width host_idtr_base;
276 natural_width host_ia32_sysenter_esp;
277 natural_width host_ia32_sysenter_eip;
278 natural_width host_rsp;
279 natural_width host_rip;
280 natural_width paddingl[8]; /* room for future expansion */
281 u32 pin_based_vm_exec_control;
282 u32 cpu_based_vm_exec_control;
283 u32 exception_bitmap;
284 u32 page_fault_error_code_mask;
285 u32 page_fault_error_code_match;
286 u32 cr3_target_count;
287 u32 vm_exit_controls;
288 u32 vm_exit_msr_store_count;
289 u32 vm_exit_msr_load_count;
290 u32 vm_entry_controls;
291 u32 vm_entry_msr_load_count;
292 u32 vm_entry_intr_info_field;
293 u32 vm_entry_exception_error_code;
294 u32 vm_entry_instruction_len;
295 u32 tpr_threshold;
296 u32 secondary_vm_exec_control;
297 u32 vm_instruction_error;
298 u32 vm_exit_reason;
299 u32 vm_exit_intr_info;
300 u32 vm_exit_intr_error_code;
301 u32 idt_vectoring_info_field;
302 u32 idt_vectoring_error_code;
303 u32 vm_exit_instruction_len;
304 u32 vmx_instruction_info;
305 u32 guest_es_limit;
306 u32 guest_cs_limit;
307 u32 guest_ss_limit;
308 u32 guest_ds_limit;
309 u32 guest_fs_limit;
310 u32 guest_gs_limit;
311 u32 guest_ldtr_limit;
312 u32 guest_tr_limit;
313 u32 guest_gdtr_limit;
314 u32 guest_idtr_limit;
315 u32 guest_es_ar_bytes;
316 u32 guest_cs_ar_bytes;
317 u32 guest_ss_ar_bytes;
318 u32 guest_ds_ar_bytes;
319 u32 guest_fs_ar_bytes;
320 u32 guest_gs_ar_bytes;
321 u32 guest_ldtr_ar_bytes;
322 u32 guest_tr_ar_bytes;
323 u32 guest_interruptibility_info;
324 u32 guest_activity_state;
325 u32 guest_sysenter_cs;
326 u32 host_ia32_sysenter_cs;
0238ea91
JK		 327 u32 vmx_preemption_timer_value;
328 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 329 u16 virtual_processor_id;
330 u16 guest_es_selector;
331 u16 guest_cs_selector;
332 u16 guest_ss_selector;
333 u16 guest_ds_selector;
334 u16 guest_fs_selector;
335 u16 guest_gs_selector;
336 u16 guest_ldtr_selector;
337 u16 guest_tr_selector;
338 u16 host_es_selector;
339 u16 host_cs_selector;
340 u16 host_ss_selector;
341 u16 host_ds_selector;
342 u16 host_fs_selector;
343 u16 host_gs_selector;
344 u16 host_tr_selector;
a9d30f33
NHE		 345};
346
347/*
348 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
349 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
350 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
351 */
352#define VMCS12_REVISION 0x11e57ed0
353
354/*
355 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
356 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
357 * current implementation, 4K are reserved to avoid future complications.
358 */
359#define VMCS12_SIZE 0x1000
360
ff2f6fe9
NHE		 361/* Used to remember the last vmcs02 used for some recently used vmcs12s */
362struct vmcs02_list {
363 struct list_head list;
364 gpa_t vmptr;
365 struct loaded_vmcs vmcs02;
366};
367
ec378aee
NHE		 368/*
369 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
370 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
371 */
372struct nested_vmx {
373 /* Has the level1 guest done vmxon? */
374 bool vmxon;
3573e22c 375 gpa_t vmxon_ptr;
a9d30f33
NHE		 376
377 /* The guest-physical address of the current VMCS L1 keeps for L2 */
378 gpa_t current_vmptr;
379 /* The host-usable pointer to the above */
380 struct page *current_vmcs12_page;
381 struct vmcs12 *current_vmcs12;
8de48833 382 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 383 /*
384 * Indicates if the shadow vmcs must be updated with the
385 * data hold by vmcs12
386 */
387 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 388
389 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
390 struct list_head vmcs02_pool;
391 int vmcs02_num;
fe3ef05c 392 u64 vmcs01_tsc_offset;
644d711a
NHE		 393 /* L2 must run next, and mustn't decide to exit to L1. */
394 bool nested_run_pending;
fe3ef05c
NHE		 395 /*
396 * Guest pages referred to in vmcs02 with host-physical pointers, so
397 * we must keep them pinned while L2 runs.
398 */
399 struct page *apic_access_page;
a7c0b07d 400 struct page *virtual_apic_page;
b3897a49 401 u64 msr_ia32_feature_control;
f4124500
JK		 402
403 struct hrtimer preemption_timer;
404 bool preemption_timer_expired;
2996fca0
JK		 405
406 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
407 u64 vmcs01_debugctl;
ec378aee
NHE		 408};
409
01e439be
YZ		 410#define POSTED_INTR_ON 0
411/* Posted-Interrupt Descriptor */
412struct pi_desc {
413 u32 pir[8]; /* Posted interrupt requested */
414 u32 control; /* bit 0 of control is outstanding notification bit */
415 u32 rsvd[7];
416} __aligned(64);
417
a20ed54d
YZ		 418static bool pi_test_and_set_on(struct pi_desc *pi_desc)
419{
420 return test_and_set_bit(POSTED_INTR_ON,
421 (unsigned long *)&pi_desc->control);
422}
423
424static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
425{
426 return test_and_clear_bit(POSTED_INTR_ON,
427 (unsigned long *)&pi_desc->control);
428}
429
430static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
431{
432 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
433}
434
a2fa3e9f 435struct vcpu_vmx {
fb3f0f51 436 struct kvm_vcpu vcpu;
313dbd49 437 unsigned long host_rsp;
29bd8a78 438 u8 fail;
9d58b931 439 bool nmi_known_unmasked;
51aa01d1 440 u32 exit_intr_info;
1155f76a 441 u32 idt_vectoring_info;
6de12732 442 ulong rflags;
26bb0981 443 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 444 int nmsrs;
445 int save_nmsrs;
a547c6db 446 unsigned long host_idt_base;
a2fa3e9f 447#ifdef CONFIG_X86_64
44ea2b17
AK		 448 u64 msr_host_kernel_gs_base;
449 u64 msr_guest_kernel_gs_base;
a2fa3e9f 450#endif
2961e876
GN		 451 u32 vm_entry_controls_shadow;
452 u32 vm_exit_controls_shadow;
d462b819
NHE		 453 /*
454 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
455 * non-nested (L1) guest, it always points to vmcs01. For a nested
456 * guest (L2), it points to a different VMCS.
457 */
458 struct loaded_vmcs vmcs01;
459 struct loaded_vmcs *loaded_vmcs;
460 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 461 struct msr_autoload {
462 unsigned nr;
463 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
464 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
465 } msr_autoload;
a2fa3e9f
GH		 466 struct {
467 int loaded;
468 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 469#ifdef CONFIG_X86_64
470 u16 ds_sel, es_sel;
471#endif
152d3f2f
LV		 472 int gs_ldt_reload_needed;
473 int fs_reload_needed;
da8999d3 474 u64 msr_host_bndcfgs;
d974baa3 475 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 476 } host_state;
9c8cba37 477 struct {
7ffd92c5 478 int vm86_active;
78ac8b47 479 ulong save_rflags;
f5f7b2fe
AK		 480 struct kvm_segment segs[8];
481 } rmode;
482 struct {
483 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 484 struct kvm_save_segment {
485 u16 selector;
486 unsigned long base;
487 u32 limit;
488 u32 ar;
f5f7b2fe 489 } seg[8];
2fb92db1 490 } segment_cache;
2384d2b3 491 int vpid;
04fa4d32 492 bool emulation_required;
3b86cd99
JK		 493
494 /* Support for vnmi-less CPUs */
495 int soft_vnmi_blocked;
496 ktime_t entry_time;
497 s64 vnmi_blocked_time;
a0861c02 498 u32 exit_reason;
4e47c7a6
SY		 499
500 bool rdtscp_enabled;
ec378aee 501
01e439be
YZ		 502 /* Posted interrupt descriptor */
503 struct pi_desc pi_desc;
504
ec378aee
NHE		 505 /* Support for a guest hypervisor (nested VMX) */
506 struct nested_vmx nested;
a7653ecd
RK		 507
508 /* Dynamic PLE window. */
509 int ple_window;
510 bool ple_window_dirty;
a2fa3e9f
GH		 511};
512
2fb92db1
AK		 513enum segment_cache_field {
514 SEG_FIELD_SEL = 0,
515 SEG_FIELD_BASE = 1,
516 SEG_FIELD_LIMIT = 2,
517 SEG_FIELD_AR = 3,
518
519 SEG_FIELD_NR = 4
520};
521
a2fa3e9f
GH		 522static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
523{
fb3f0f51 524 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 525}
526
22bd0358
NHE		 527#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
528#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
529#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
530 [number##_HIGH] = VMCS12_OFFSET(name)+4
531
4607c2d7 532
fe2b201b 533static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 534 /*
535 * We do NOT shadow fields that are modified when L0
536 * traps and emulates any vmx instruction (e.g. VMPTRLD,
537 * VMXON...) executed by L1.
538 * For example, VM_INSTRUCTION_ERROR is read
539 * by L1 if a vmx instruction fails (part of the error path).
540 * Note the code assumes this logic. If for some reason
541 * we start shadowing these fields then we need to
542 * force a shadow sync when L0 emulates vmx instructions
543 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
544 * by nested_vmx_failValid)
545 */
546 VM_EXIT_REASON,
547 VM_EXIT_INTR_INFO,
548 VM_EXIT_INSTRUCTION_LEN,
549 IDT_VECTORING_INFO_FIELD,
550 IDT_VECTORING_ERROR_CODE,
551 VM_EXIT_INTR_ERROR_CODE,
552 EXIT_QUALIFICATION,
553 GUEST_LINEAR_ADDRESS,
554 GUEST_PHYSICAL_ADDRESS
555};
fe2b201b 556static int max_shadow_read_only_fields =
4607c2d7
AG		 557 ARRAY_SIZE(shadow_read_only_fields);
558
fe2b201b 559static unsigned long shadow_read_write_fields[] = {
a7c0b07d 560 TPR_THRESHOLD,
4607c2d7
AG		 561 GUEST_RIP,
562 GUEST_RSP,
563 GUEST_CR0,
564 GUEST_CR3,
565 GUEST_CR4,
566 GUEST_INTERRUPTIBILITY_INFO,
567 GUEST_RFLAGS,
568 GUEST_CS_SELECTOR,
569 GUEST_CS_AR_BYTES,
570 GUEST_CS_LIMIT,
571 GUEST_CS_BASE,
572 GUEST_ES_BASE,
36be0b9d 573 GUEST_BNDCFGS,
4607c2d7
AG		 574 CR0_GUEST_HOST_MASK,
575 CR0_READ_SHADOW,
576 CR4_READ_SHADOW,
577 TSC_OFFSET,
578 EXCEPTION_BITMAP,
579 CPU_BASED_VM_EXEC_CONTROL,
580 VM_ENTRY_EXCEPTION_ERROR_CODE,
581 VM_ENTRY_INTR_INFO_FIELD,
582 VM_ENTRY_INSTRUCTION_LEN,
583 VM_ENTRY_EXCEPTION_ERROR_CODE,
584 HOST_FS_BASE,
585 HOST_GS_BASE,
586 HOST_FS_SELECTOR,
587 HOST_GS_SELECTOR
588};
fe2b201b 589static int max_shadow_read_write_fields =
4607c2d7
AG		 590 ARRAY_SIZE(shadow_read_write_fields);
591
772e0318 592static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 593 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
594 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
595 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
596 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
597 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
598 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
599 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
600 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
601 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
602 FIELD(HOST_ES_SELECTOR, host_es_selector),
603 FIELD(HOST_CS_SELECTOR, host_cs_selector),
604 FIELD(HOST_SS_SELECTOR, host_ss_selector),
605 FIELD(HOST_DS_SELECTOR, host_ds_selector),
606 FIELD(HOST_FS_SELECTOR, host_fs_selector),
607 FIELD(HOST_GS_SELECTOR, host_gs_selector),
608 FIELD(HOST_TR_SELECTOR, host_tr_selector),
609 FIELD64(IO_BITMAP_A, io_bitmap_a),
610 FIELD64(IO_BITMAP_B, io_bitmap_b),
611 FIELD64(MSR_BITMAP, msr_bitmap),
612 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
613 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
614 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
615 FIELD64(TSC_OFFSET, tsc_offset),
616 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
617 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
618 FIELD64(EPT_POINTER, ept_pointer),
619 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
620 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
621 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
622 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
623 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
624 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
625 FIELD64(GUEST_PDPTR0, guest_pdptr0),
626 FIELD64(GUEST_PDPTR1, guest_pdptr1),
627 FIELD64(GUEST_PDPTR2, guest_pdptr2),
628 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 629 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 630 FIELD64(HOST_IA32_PAT, host_ia32_pat),
631 FIELD64(HOST_IA32_EFER, host_ia32_efer),
632 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
633 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
634 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
635 FIELD(EXCEPTION_BITMAP, exception_bitmap),
636 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
637 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
638 FIELD(CR3_TARGET_COUNT, cr3_target_count),
639 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
640 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
641 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
642 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
643 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
644 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
645 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
646 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
647 FIELD(TPR_THRESHOLD, tpr_threshold),
648 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
649 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
650 FIELD(VM_EXIT_REASON, vm_exit_reason),
651 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
652 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
653 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
654 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
655 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
656 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
657 FIELD(GUEST_ES_LIMIT, guest_es_limit),
658 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
659 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
660 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
661 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
662 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
663 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
664 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
665 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
666 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
667 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
668 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
669 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
670 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
671 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
672 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
673 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
674 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
675 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
676 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
677 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
678 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 679 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 680 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
681 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
682 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
683 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
684 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
685 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
686 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
687 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
688 FIELD(EXIT_QUALIFICATION, exit_qualification),
689 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
690 FIELD(GUEST_CR0, guest_cr0),
691 FIELD(GUEST_CR3, guest_cr3),
692 FIELD(GUEST_CR4, guest_cr4),
693 FIELD(GUEST_ES_BASE, guest_es_base),
694 FIELD(GUEST_CS_BASE, guest_cs_base),
695 FIELD(GUEST_SS_BASE, guest_ss_base),
696 FIELD(GUEST_DS_BASE, guest_ds_base),
697 FIELD(GUEST_FS_BASE, guest_fs_base),
698 FIELD(GUEST_GS_BASE, guest_gs_base),
699 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
700 FIELD(GUEST_TR_BASE, guest_tr_base),
701 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
702 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
703 FIELD(GUEST_DR7, guest_dr7),
704 FIELD(GUEST_RSP, guest_rsp),
705 FIELD(GUEST_RIP, guest_rip),
706 FIELD(GUEST_RFLAGS, guest_rflags),
707 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
708 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
709 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
710 FIELD(HOST_CR0, host_cr0),
711 FIELD(HOST_CR3, host_cr3),
712 FIELD(HOST_CR4, host_cr4),
713 FIELD(HOST_FS_BASE, host_fs_base),
714 FIELD(HOST_GS_BASE, host_gs_base),
715 FIELD(HOST_TR_BASE, host_tr_base),
716 FIELD(HOST_GDTR_BASE, host_gdtr_base),
717 FIELD(HOST_IDTR_BASE, host_idtr_base),
718 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
719 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
720 FIELD(HOST_RSP, host_rsp),
721 FIELD(HOST_RIP, host_rip),
722};
723static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
724
725static inline short vmcs_field_to_offset(unsigned long field)
726{
727 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
728 return -1;
729 return vmcs_field_to_offset_table[field];
730}
731
a9d30f33
NHE		 732static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
733{
734 return to_vmx(vcpu)->nested.current_vmcs12;
735}
736
737static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
738{
739 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 740 if (is_error_page(page))
a9d30f33 741 return NULL;
32cad84f 742
a9d30f33
NHE		 743 return page;
744}
745
746static void nested_release_page(struct page *page)
747{
748 kvm_release_page_dirty(page);
749}
750
751static void nested_release_page_clean(struct page *page)
752{
753 kvm_release_page_clean(page);
754}
755
bfd0a56b 756static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 757static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 758static void kvm_cpu_vmxon(u64 addr);
759static void kvm_cpu_vmxoff(void);
93c4adc7 760static bool vmx_mpx_supported(void);
776e58ea 761static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 762static void vmx_set_segment(struct kvm_vcpu *vcpu,
763 struct kvm_segment *var, int seg);
764static void vmx_get_segment(struct kvm_vcpu *vcpu,
765 struct kvm_segment *var, int seg);
d99e4152
GN		 766static bool guest_state_valid(struct kvm_vcpu *vcpu);
767static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 768static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 769static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 770static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 771static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 772
6aa8b732
AK		 773static DEFINE_PER_CPU(struct vmcs *, vmxarea);
774static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 775/*
776 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
777 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
778 */
779static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 780static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 781
3e7c73e9
AK		 782static unsigned long *vmx_io_bitmap_a;
783static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 784static unsigned long *vmx_msr_bitmap_legacy;
785static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 786static unsigned long *vmx_msr_bitmap_legacy_x2apic;
787static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 788static unsigned long *vmx_vmread_bitmap;
789static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 790
110312c8 791static bool cpu_has_load_ia32_efer;
8bf00a52 792static bool cpu_has_load_perf_global_ctrl;
110312c8 793
2384d2b3
SY		 794static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
795static DEFINE_SPINLOCK(vmx_vpid_lock);
796
1c3d14fe 797static struct vmcs_config {
6aa8b732
AK		 798 int size;
799 int order;
800 u32 revision_id;
1c3d14fe
YS		 801 u32 pin_based_exec_ctrl;
802 u32 cpu_based_exec_ctrl;
f78e0e2e 803 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 804 u32 vmexit_ctrl;
805 u32 vmentry_ctrl;
806} vmcs_config;
6aa8b732 807
efff9e53 808static struct vmx_capability {
d56f546d
SY		 809 u32 ept;
810 u32 vpid;
811} vmx_capability;
812
6aa8b732
AK		 813#define VMX_SEGMENT_FIELD(seg) \
814 [VCPU_SREG_##seg] = { \
815 .selector = GUEST_##seg##_SELECTOR, \
816 .base = GUEST_##seg##_BASE, \
817 .limit = GUEST_##seg##_LIMIT, \
818 .ar_bytes = GUEST_##seg##_AR_BYTES, \
819 }
820
772e0318 821static const struct kvm_vmx_segment_field {
6aa8b732
AK		 822 unsigned selector;
823 unsigned base;
824 unsigned limit;
825 unsigned ar_bytes;
826} kvm_vmx_segment_fields[] = {
827 VMX_SEGMENT_FIELD(CS),
828 VMX_SEGMENT_FIELD(DS),
829 VMX_SEGMENT_FIELD(ES),
830 VMX_SEGMENT_FIELD(FS),
831 VMX_SEGMENT_FIELD(GS),
832 VMX_SEGMENT_FIELD(SS),
833 VMX_SEGMENT_FIELD(TR),
834 VMX_SEGMENT_FIELD(LDTR),
835};
836
26bb0981
AK		 837static u64 host_efer;
838
6de4f3ad
AK		 839static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
840
4d56c8a7 841/*
8c06585d 842 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 843 * away by decrementing the array size.
844 */
6aa8b732 845static const u32 vmx_msr_index[] = {
05b3e0c2 846#ifdef CONFIG_X86_64
44ea2b17 847 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 848#endif
8c06585d 849 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 850};
6aa8b732 851
31299944 852static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 853{
854 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
855 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 856 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 857}
858
31299944 859static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 860{
861 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
862 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 863 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 864}
865
31299944 866static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 867{
868 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
869 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 870 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 871}
872
31299944 873static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 874{
875 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
876 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
877}
878
31299944 879static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 880{
881 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
882 INTR_INFO_VALID_MASK)) ==
883 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
884}
885
31299944 886static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 887{
04547156 888 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 889}
890
31299944 891static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 892{
04547156 893 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 894}
895
31299944 896static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 897{
04547156 898 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 899}
900
31299944 901static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 902{
04547156
SY		 903 return vmcs_config.cpu_based_exec_ctrl &
904 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 905}
906
774ead3a 907static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 908{
04547156
SY		 909 return vmcs_config.cpu_based_2nd_exec_ctrl &
910 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
911}
912
8d14695f
YZ		 913static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
914{
915 return vmcs_config.cpu_based_2nd_exec_ctrl &
916 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
917}
918
83d4c286
YZ		 919static inline bool cpu_has_vmx_apic_register_virt(void)
920{
921 return vmcs_config.cpu_based_2nd_exec_ctrl &
922 SECONDARY_EXEC_APIC_REGISTER_VIRT;
923}
924
c7c9c56c
YZ		 925static inline bool cpu_has_vmx_virtual_intr_delivery(void)
926{
927 return vmcs_config.cpu_based_2nd_exec_ctrl &
928 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
929}
930
01e439be
YZ		 931static inline bool cpu_has_vmx_posted_intr(void)
932{
933 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
934}
935
936static inline bool cpu_has_vmx_apicv(void)
937{
938 return cpu_has_vmx_apic_register_virt() &&
939 cpu_has_vmx_virtual_intr_delivery() &&
940 cpu_has_vmx_posted_intr();
941}
942
04547156
SY		 943static inline bool cpu_has_vmx_flexpriority(void)
944{
945 return cpu_has_vmx_tpr_shadow() &&
946 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 947}
948
e799794e
MT		 949static inline bool cpu_has_vmx_ept_execute_only(void)
950{
31299944 951 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 952}
953
954static inline bool cpu_has_vmx_eptp_uncacheable(void)
955{
31299944 956 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 957}
958
959static inline bool cpu_has_vmx_eptp_writeback(void)
960{
31299944 961 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 962}
963
964static inline bool cpu_has_vmx_ept_2m_page(void)
965{
31299944 966 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 967}
968
878403b7
SY		 969static inline bool cpu_has_vmx_ept_1g_page(void)
970{
31299944 971 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 972}
973
4bc9b982
SY		 974static inline bool cpu_has_vmx_ept_4levels(void)
975{
976 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
977}
978
83c3a331
XH		 979static inline bool cpu_has_vmx_ept_ad_bits(void)
980{
981 return vmx_capability.ept & VMX_EPT_AD_BIT;
982}
983
31299944 984static inline bool cpu_has_vmx_invept_context(void)
d56f546d 985{
31299944 986 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 987}
988
31299944 989static inline bool cpu_has_vmx_invept_global(void)
d56f546d 990{
31299944 991 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 992}
993
518c8aee
GJ		 994static inline bool cpu_has_vmx_invvpid_single(void)
995{
996 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
997}
998
b9d762fa
GJ		 999static inline bool cpu_has_vmx_invvpid_global(void)
1000{
1001 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1002}
1003
31299944 1004static inline bool cpu_has_vmx_ept(void)
d56f546d 1005{
04547156
SY		 1006 return vmcs_config.cpu_based_2nd_exec_ctrl &
1007 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1008}
1009
31299944 1010static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1011{
1012 return vmcs_config.cpu_based_2nd_exec_ctrl &
1013 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1014}
1015
31299944 1016static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1017{
1018 return vmcs_config.cpu_based_2nd_exec_ctrl &
1019 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1020}
1021
31299944 1022static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1023{
6d3e435e 1024 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1025}
1026
31299944 1027static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1028{
04547156
SY		 1029 return vmcs_config.cpu_based_2nd_exec_ctrl &
1030 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1031}
1032
31299944 1033static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1034{
1035 return vmcs_config.cpu_based_2nd_exec_ctrl &
1036 SECONDARY_EXEC_RDTSCP;
1037}
1038
ad756a16
MJ		 1039static inline bool cpu_has_vmx_invpcid(void)
1040{
1041 return vmcs_config.cpu_based_2nd_exec_ctrl &
1042 SECONDARY_EXEC_ENABLE_INVPCID;
1043}
1044
31299944 1045static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1046{
1047 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1048}
1049
f5f48ee1
SY		 1050static inline bool cpu_has_vmx_wbinvd_exit(void)
1051{
1052 return vmcs_config.cpu_based_2nd_exec_ctrl &
1053 SECONDARY_EXEC_WBINVD_EXITING;
1054}
1055
abc4fc58
AG		 1056static inline bool cpu_has_vmx_shadow_vmcs(void)
1057{
1058 u64 vmx_msr;
1059 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1060 /* check if the cpu supports writing r/o exit information fields */
1061 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1062 return false;
1063
1064 return vmcs_config.cpu_based_2nd_exec_ctrl &
1065 SECONDARY_EXEC_SHADOW_VMCS;
1066}
1067
04547156
SY		 1068static inline bool report_flexpriority(void)
1069{
1070 return flexpriority_enabled;
1071}
1072
fe3ef05c
NHE		 1073static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1074{
1075 return vmcs12->cpu_based_vm_exec_control & bit;
1076}
1077
1078static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1079{
1080 return (vmcs12->cpu_based_vm_exec_control &
1081 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1082 (vmcs12->secondary_vm_exec_control & bit);
1083}
1084
f5c4368f 1085static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1086{
1087 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1088}
1089
f4124500
JK		 1090static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1091{
1092 return vmcs12->pin_based_vm_exec_control &
1093 PIN_BASED_VMX_PREEMPTION_TIMER;
1094}
1095
155a97a3
NHE		 1096static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1097{
1098 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1099}
1100
644d711a
NHE		 1101static inline bool is_exception(u32 intr_info)
1102{
1103 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1104 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1105}
1106
533558bc
JK		 1107static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1108 u32 exit_intr_info,
1109 unsigned long exit_qualification);
7c177938
NHE		 1110static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1111 struct vmcs12 *vmcs12,
1112 u32 reason, unsigned long qualification);
1113
8b9cf98c 1114static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1115{
1116 int i;
1117
a2fa3e9f 1118 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1119 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1120 return i;
1121 return -1;
1122}
1123
2384d2b3
SY		 1124static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1125{
1126 struct {
1127 u64 vpid : 16;
1128 u64 rsvd : 48;
1129 u64 gva;
1130 } operand = { vpid, 0, gva };
1131
4ecac3fd 1132 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1133 /* CF==1 or ZF==1 --> rc = -1 */
1134 "; ja 1f ; ud2 ; 1:"
1135 : : "a"(&operand), "c"(ext) : "cc", "memory");
1136}
1137
1439442c
SY		 1138static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1139{
1140 struct {
1141 u64 eptp, gpa;
1142 } operand = {eptp, gpa};
1143
4ecac3fd 1144 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1145 /* CF==1 or ZF==1 --> rc = -1 */
1146 "; ja 1f ; ud2 ; 1:\n"
1147 : : "a" (&operand), "c" (ext) : "cc", "memory");
1148}
1149
26bb0981 1150static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1151{
1152 int i;
1153
8b9cf98c 1154 i = __find_msr_index(vmx, msr);
a75beee6 1155 if (i >= 0)
a2fa3e9f 1156 return &vmx->guest_msrs[i];
8b6d44c7 1157 return NULL;
7725f0ba
AK		 1158}
1159
6aa8b732
AK		 1160static void vmcs_clear(struct vmcs *vmcs)
1161{
1162 u64 phys_addr = __pa(vmcs);
1163 u8 error;
1164
4ecac3fd 1165 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1166 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1167 : "cc", "memory");
1168 if (error)
1169 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1170 vmcs, phys_addr);
1171}
1172
d462b819
NHE		 1173static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1174{
1175 vmcs_clear(loaded_vmcs->vmcs);
1176 loaded_vmcs->cpu = -1;
1177 loaded_vmcs->launched = 0;
1178}
1179
7725b894
DX		 1180static void vmcs_load(struct vmcs *vmcs)
1181{
1182 u64 phys_addr = __pa(vmcs);
1183 u8 error;
1184
1185 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1186 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1187 : "cc", "memory");
1188 if (error)
2844d849 1189 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1190 vmcs, phys_addr);
1191}
1192
8f536b76
ZY		 1193#ifdef CONFIG_KEXEC
1194/*
1195 * This bitmap is used to indicate whether the vmclear
1196 * operation is enabled on all cpus. All disabled by
1197 * default.
1198 */
1199static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1200
1201static inline void crash_enable_local_vmclear(int cpu)
1202{
1203 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1204}
1205
1206static inline void crash_disable_local_vmclear(int cpu)
1207{
1208 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1209}
1210
1211static inline int crash_local_vmclear_enabled(int cpu)
1212{
1213 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1214}
1215
1216static void crash_vmclear_local_loaded_vmcss(void)
1217{
1218 int cpu = raw_smp_processor_id();
1219 struct loaded_vmcs *v;
1220
1221 if (!crash_local_vmclear_enabled(cpu))
1222 return;
1223
1224 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1225 loaded_vmcss_on_cpu_link)
1226 vmcs_clear(v->vmcs);
1227}
1228#else
1229static inline void crash_enable_local_vmclear(int cpu) { }
1230static inline void crash_disable_local_vmclear(int cpu) { }
1231#endif /* CONFIG_KEXEC */
1232
d462b819 1233static void __loaded_vmcs_clear(void *arg)
6aa8b732 1234{
d462b819 1235 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1236 int cpu = raw_smp_processor_id();
6aa8b732 1237
d462b819
NHE		 1238 if (loaded_vmcs->cpu != cpu)
1239 return; /* vcpu migration can race with cpu offline */
1240 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1241 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1242 crash_disable_local_vmclear(cpu);
d462b819 1243 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1244
1245 /*
1246 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1247 * is before setting loaded_vmcs->vcpu to -1 which is done in
1248 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1249 * then adds the vmcs into percpu list before it is deleted.
1250 */
1251 smp_wmb();
1252
d462b819 1253 loaded_vmcs_init(loaded_vmcs);
8f536b76 1254 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1255}
1256
d462b819 1257static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1258{
e6c7d321
XG		 1259 int cpu = loaded_vmcs->cpu;
1260
1261 if (cpu != -1)
1262 smp_call_function_single(cpu,
1263 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1264}
1265
1760dd49 1266static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1267{
1268 if (vmx->vpid == 0)
1269 return;
1270
518c8aee
GJ		 1271 if (cpu_has_vmx_invvpid_single())
1272 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1273}
1274
b9d762fa
GJ		 1275static inline void vpid_sync_vcpu_global(void)
1276{
1277 if (cpu_has_vmx_invvpid_global())
1278 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1279}
1280
1281static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1282{
1283 if (cpu_has_vmx_invvpid_single())
1760dd49 1284 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1285 else
1286 vpid_sync_vcpu_global();
1287}
1288
1439442c
SY		 1289static inline void ept_sync_global(void)
1290{
1291 if (cpu_has_vmx_invept_global())
1292 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1293}
1294
1295static inline void ept_sync_context(u64 eptp)
1296{
089d034e 1297 if (enable_ept) {
1439442c
SY		 1298 if (cpu_has_vmx_invept_context())
1299 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1300 else
1301 ept_sync_global();
1302 }
1303}
1304
96304217 1305static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1306{
5e520e62 1307 unsigned long value;
6aa8b732 1308
5e520e62
AK		 1309 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1310 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1311 return value;
1312}
1313
96304217 1314static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1315{
1316 return vmcs_readl(field);
1317}
1318
96304217 1319static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1320{
1321 return vmcs_readl(field);
1322}
1323
96304217 1324static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1325{
05b3e0c2 1326#ifdef CONFIG_X86_64
6aa8b732
AK		 1327 return vmcs_readl(field);
1328#else
1329 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1330#endif
1331}
1332
e52de1b8
AK		 1333static noinline void vmwrite_error(unsigned long field, unsigned long value)
1334{
1335 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1336 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1337 dump_stack();
1338}
1339
6aa8b732
AK		 1340static void vmcs_writel(unsigned long field, unsigned long value)
1341{
1342 u8 error;
1343
4ecac3fd 1344 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1345 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1346 if (unlikely(error))
1347 vmwrite_error(field, value);
6aa8b732
AK		 1348}
1349
1350static void vmcs_write16(unsigned long field, u16 value)
1351{
1352 vmcs_writel(field, value);
1353}
1354
1355static void vmcs_write32(unsigned long field, u32 value)
1356{
1357 vmcs_writel(field, value);
1358}
1359
1360static void vmcs_write64(unsigned long field, u64 value)
1361{
6aa8b732 1362 vmcs_writel(field, value);
7682f2d0 1363#ifndef CONFIG_X86_64
6aa8b732
AK		 1364 asm volatile ("");
1365 vmcs_writel(field+1, value >> 32);
1366#endif
1367}
1368
2ab455cc
AL		 1369static void vmcs_clear_bits(unsigned long field, u32 mask)
1370{
1371 vmcs_writel(field, vmcs_readl(field) & ~mask);
1372}
1373
1374static void vmcs_set_bits(unsigned long field, u32 mask)
1375{
1376 vmcs_writel(field, vmcs_readl(field) | mask);
1377}
1378
2961e876
GN		 1379static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1380{
1381 vmcs_write32(VM_ENTRY_CONTROLS, val);
1382 vmx->vm_entry_controls_shadow = val;
1383}
1384
1385static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1386{
1387 if (vmx->vm_entry_controls_shadow != val)
1388 vm_entry_controls_init(vmx, val);
1389}
1390
1391static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1392{
1393 return vmx->vm_entry_controls_shadow;
1394}
1395
1396
1397static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1398{
1399 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1400}
1401
1402static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1403{
1404 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1405}
1406
1407static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1408{
1409 vmcs_write32(VM_EXIT_CONTROLS, val);
1410 vmx->vm_exit_controls_shadow = val;
1411}
1412
1413static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1414{
1415 if (vmx->vm_exit_controls_shadow != val)
1416 vm_exit_controls_init(vmx, val);
1417}
1418
1419static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1420{
1421 return vmx->vm_exit_controls_shadow;
1422}
1423
1424
1425static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1426{
1427 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1428}
1429
1430static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1431{
1432 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1433}
1434
2fb92db1
AK		 1435static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1436{
1437 vmx->segment_cache.bitmask = 0;
1438}
1439
1440static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1441 unsigned field)
1442{
1443 bool ret;
1444 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1445
1446 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1447 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1448 vmx->segment_cache.bitmask = 0;
1449 }
1450 ret = vmx->segment_cache.bitmask & mask;
1451 vmx->segment_cache.bitmask |= mask;
1452 return ret;
1453}
1454
1455static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1456{
1457 u16 *p = &vmx->segment_cache.seg[seg].selector;
1458
1459 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1460 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1461 return *p;
1462}
1463
1464static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1465{
1466 ulong *p = &vmx->segment_cache.seg[seg].base;
1467
1468 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1469 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1470 return *p;
1471}
1472
1473static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1474{
1475 u32 *p = &vmx->segment_cache.seg[seg].limit;
1476
1477 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1478 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1479 return *p;
1480}
1481
1482static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1483{
1484 u32 *p = &vmx->segment_cache.seg[seg].ar;
1485
1486 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1487 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1488 return *p;
1489}
1490
abd3f2d6
AK		 1491static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1492{
1493 u32 eb;
1494
fd7373cc
JK		 1495 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1496 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1497 if ((vcpu->guest_debug &
1498 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1499 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1500 eb |= 1u << BP_VECTOR;
7ffd92c5 1501 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1502 eb = ~0;
089d034e 1503 if (enable_ept)
1439442c 1504 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1505 if (vcpu->fpu_active)
1506 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1507
1508 /* When we are running a nested L2 guest and L1 specified for it a
1509 * certain exception bitmap, we must trap the same exceptions and pass
1510 * them to L1. When running L2, we will only handle the exceptions
1511 * specified above if L1 did not want them.
1512 */
1513 if (is_guest_mode(vcpu))
1514 eb |= get_vmcs12(vcpu)->exception_bitmap;
1515
abd3f2d6
AK		 1516 vmcs_write32(EXCEPTION_BITMAP, eb);
1517}
1518
2961e876
GN		 1519static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1520 unsigned long entry, unsigned long exit)
8bf00a52 1521{
2961e876
GN		 1522 vm_entry_controls_clearbit(vmx, entry);
1523 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1524}
1525
61d2ef2c
AK		 1526static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1527{
1528 unsigned i;
1529 struct msr_autoload *m = &vmx->msr_autoload;
1530
8bf00a52
GN		 1531 switch (msr) {
1532 case MSR_EFER:
1533 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1534 clear_atomic_switch_msr_special(vmx,
1535 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1536 VM_EXIT_LOAD_IA32_EFER);
1537 return;
1538 }
1539 break;
1540 case MSR_CORE_PERF_GLOBAL_CTRL:
1541 if (cpu_has_load_perf_global_ctrl) {
2961e876 1542 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1543 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1544 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1545 return;
1546 }
1547 break;
110312c8
AK		 1548 }
1549
61d2ef2c
AK		 1550 for (i = 0; i < m->nr; ++i)
1551 if (m->guest[i].index == msr)
1552 break;
1553
1554 if (i == m->nr)
1555 return;
1556 --m->nr;
1557 m->guest[i] = m->guest[m->nr];
1558 m->host[i] = m->host[m->nr];
1559 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1560 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1561}
1562
2961e876
GN		 1563static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1564 unsigned long entry, unsigned long exit,
1565 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1566 u64 guest_val, u64 host_val)
8bf00a52
GN		 1567{
1568 vmcs_write64(guest_val_vmcs, guest_val);
1569 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1570 vm_entry_controls_setbit(vmx, entry);
1571 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1572}
1573
61d2ef2c
AK		 1574static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1575 u64 guest_val, u64 host_val)
1576{
1577 unsigned i;
1578 struct msr_autoload *m = &vmx->msr_autoload;
1579
8bf00a52
GN		 1580 switch (msr) {
1581 case MSR_EFER:
1582 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1583 add_atomic_switch_msr_special(vmx,
1584 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1585 VM_EXIT_LOAD_IA32_EFER,
1586 GUEST_IA32_EFER,
1587 HOST_IA32_EFER,
1588 guest_val, host_val);
1589 return;
1590 }
1591 break;
1592 case MSR_CORE_PERF_GLOBAL_CTRL:
1593 if (cpu_has_load_perf_global_ctrl) {
2961e876 1594 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1595 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1596 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1597 GUEST_IA32_PERF_GLOBAL_CTRL,
1598 HOST_IA32_PERF_GLOBAL_CTRL,
1599 guest_val, host_val);
1600 return;
1601 }
1602 break;
110312c8
AK		 1603 }
1604
61d2ef2c
AK		 1605 for (i = 0; i < m->nr; ++i)
1606 if (m->guest[i].index == msr)
1607 break;
1608
e7fc6f93 1609 if (i == NR_AUTOLOAD_MSRS) {
60266204 1610 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1611 "Can't add msr %x\n", msr);
1612 return;
1613 } else if (i == m->nr) {
61d2ef2c
AK		 1614 ++m->nr;
1615 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1616 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1617 }
1618
1619 m->guest[i].index = msr;
1620 m->guest[i].value = guest_val;
1621 m->host[i].index = msr;
1622 m->host[i].value = host_val;
1623}
1624
33ed6329
AK		 1625static void reload_tss(void)
1626{
33ed6329
AK		 1627 /*
1628 * VT restores TR but not its size. Useless.
1629 */
89cbc767 1630 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1631 struct desc_struct *descs;
33ed6329 1632
d359192f 1633 descs = (void *)gdt->address;
33ed6329
AK		 1634 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1635 load_TR_desc();
33ed6329
AK		 1636}
1637
92c0d900 1638static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1639{
3a34a881 1640 u64 guest_efer;
51c6cf66
AK		 1641 u64 ignore_bits;
1642
f6801dff 1643 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1644
51c6cf66 1645 /*
0fa06071 1646 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1647 * outside long mode
1648 */
1649 ignore_bits = EFER_NX | EFER_SCE;
1650#ifdef CONFIG_X86_64
1651 ignore_bits |= EFER_LMA | EFER_LME;
1652 /* SCE is meaningful only in long mode on Intel */
1653 if (guest_efer & EFER_LMA)
1654 ignore_bits &= ~(u64)EFER_SCE;
1655#endif
51c6cf66
AK		 1656 guest_efer &= ~ignore_bits;
1657 guest_efer |= host_efer & ignore_bits;
26bb0981 1658 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1659 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1660
1661 clear_atomic_switch_msr(vmx, MSR_EFER);
1662 /* On ept, can't emulate nx, and must switch nx atomically */
1663 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1664 guest_efer = vmx->vcpu.arch.efer;
1665 if (!(guest_efer & EFER_LMA))
1666 guest_efer &= ~EFER_LME;
1667 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1668 return false;
1669 }
1670
26bb0981 1671 return true;
51c6cf66
AK		 1672}
1673
2d49ec72
GN		 1674static unsigned long segment_base(u16 selector)
1675{
89cbc767 1676 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1677 struct desc_struct *d;
1678 unsigned long table_base;
1679 unsigned long v;
1680
1681 if (!(selector & ~3))
1682 return 0;
1683
d359192f 1684 table_base = gdt->address;
2d49ec72
GN		 1685
1686 if (selector & 4) { /* from ldt */
1687 u16 ldt_selector = kvm_read_ldt();
1688
1689 if (!(ldt_selector & ~3))
1690 return 0;
1691
1692 table_base = segment_base(ldt_selector);
1693 }
1694 d = (struct desc_struct *)(table_base + (selector & ~7));
1695 v = get_desc_base(d);
1696#ifdef CONFIG_X86_64
1697 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1698 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1699#endif
1700 return v;
1701}
1702
1703static inline unsigned long kvm_read_tr_base(void)
1704{
1705 u16 tr;
1706 asm("str %0" : "=g"(tr));
1707 return segment_base(tr);
1708}
1709
04d2cc77 1710static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1711{
04d2cc77 1712 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1713 int i;
04d2cc77 1714
a2fa3e9f 1715 if (vmx->host_state.loaded)
33ed6329
AK		 1716 return;
1717
a2fa3e9f 1718 vmx->host_state.loaded = 1;
33ed6329
AK		 1719 /*
1720 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1721 * allow segment selectors with cpl > 0 or ti == 1.
1722 */
d6e88aec 1723 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1724 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1725 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1726 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1727 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1728 vmx->host_state.fs_reload_needed = 0;
1729 } else {
33ed6329 1730 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1731 vmx->host_state.fs_reload_needed = 1;
33ed6329 1732 }
9581d442 1733 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1734 if (!(vmx->host_state.gs_sel & 7))
1735 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1736 else {
1737 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1738 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1739 }
1740
b2da15ac
AK		 1741#ifdef CONFIG_X86_64
1742 savesegment(ds, vmx->host_state.ds_sel);
1743 savesegment(es, vmx->host_state.es_sel);
1744#endif
1745
33ed6329
AK		 1746#ifdef CONFIG_X86_64
1747 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1748 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1749#else
a2fa3e9f
GH		 1750 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1751 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1752#endif
707c0874
AK		 1753
1754#ifdef CONFIG_X86_64
c8770e7b
AK		 1755 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1756 if (is_long_mode(&vmx->vcpu))
44ea2b17 1757 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1758#endif
da8999d3
LJ		 1759 if (boot_cpu_has(X86_FEATURE_MPX))
1760 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1761 for (i = 0; i < vmx->save_nmsrs; ++i)
1762 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1763 vmx->guest_msrs[i].data,
1764 vmx->guest_msrs[i].mask);
33ed6329
AK		 1765}
1766
a9b21b62 1767static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1768{
a2fa3e9f 1769 if (!vmx->host_state.loaded)
33ed6329
AK		 1770 return;
1771
e1beb1d3 1772 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1773 vmx->host_state.loaded = 0;
c8770e7b
AK		 1774#ifdef CONFIG_X86_64
1775 if (is_long_mode(&vmx->vcpu))
1776 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1777#endif
152d3f2f 1778 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1779 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1780#ifdef CONFIG_X86_64
9581d442 1781 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1782#else
1783 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1784#endif
33ed6329 1785 }
0a77fe4c
AK		 1786 if (vmx->host_state.fs_reload_needed)
1787 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1788#ifdef CONFIG_X86_64
1789 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1790 loadsegment(ds, vmx->host_state.ds_sel);
1791 loadsegment(es, vmx->host_state.es_sel);
1792 }
b2da15ac 1793#endif
152d3f2f 1794 reload_tss();
44ea2b17 1795#ifdef CONFIG_X86_64
c8770e7b 1796 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1797#endif
da8999d3
LJ		 1798 if (vmx->host_state.msr_host_bndcfgs)
1799 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1800 /*
1801 * If the FPU is not active (through the host task or
1802 * the guest vcpu), then restore the cr0.TS bit.
1803 */
1804 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1805 stts();
89cbc767 1806 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1807}
1808
a9b21b62
AK		 1809static void vmx_load_host_state(struct vcpu_vmx *vmx)
1810{
1811 preempt_disable();
1812 __vmx_load_host_state(vmx);
1813 preempt_enable();
1814}
1815
6aa8b732
AK		 1816/*
1817 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1818 * vcpu mutex is already taken.
1819 */
15ad7146 1820static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1821{
a2fa3e9f 1822 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1823 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1824
4610c9cc
DX		 1825 if (!vmm_exclusive)
1826 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1827 else if (vmx->loaded_vmcs->cpu != cpu)
1828 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1829
d462b819
NHE		 1830 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1831 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1832 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1833 }
1834
d462b819 1835 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1836 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1837 unsigned long sysenter_esp;
1838
a8eeb04a 1839 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1840 local_irq_disable();
8f536b76 1841 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1842
1843 /*
1844 * Read loaded_vmcs->cpu should be before fetching
1845 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1846 * See the comments in __loaded_vmcs_clear().
1847 */
1848 smp_rmb();
1849
d462b819
NHE		 1850 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1851 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1852 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1853 local_irq_enable();
1854
6aa8b732
AK		 1855 /*
1856 * Linux uses per-cpu TSS and GDT, so set these when switching
1857 * processors.
1858 */
d6e88aec 1859 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1860 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1861
1862 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1863 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1864 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1865 }
6aa8b732
AK		 1866}
1867
1868static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1869{
a9b21b62 1870 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1871 if (!vmm_exclusive) {
d462b819
NHE		 1872 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1873 vcpu->cpu = -1;
4610c9cc
DX		 1874 kvm_cpu_vmxoff();
1875 }
6aa8b732
AK		 1876}
1877
5fd86fcf
AK		 1878static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1879{
81231c69
AK		 1880 ulong cr0;
1881
5fd86fcf
AK		 1882 if (vcpu->fpu_active)
1883 return;
1884 vcpu->fpu_active = 1;
81231c69
AK		 1885 cr0 = vmcs_readl(GUEST_CR0);
1886 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1887 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1888 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1889 update_exception_bitmap(vcpu);
edcafe3c 1890 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1891 if (is_guest_mode(vcpu))
1892 vcpu->arch.cr0_guest_owned_bits &=
1893 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1894 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1895}
1896
edcafe3c
AK		 1897static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1898
fe3ef05c
NHE		 1899/*
1900 * Return the cr0 value that a nested guest would read. This is a combination
1901 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1902 * its hypervisor (cr0_read_shadow).
1903 */
1904static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1905{
1906 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1907 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1908}
1909static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1910{
1911 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1912 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1913}
1914
5fd86fcf
AK		 1915static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1916{
36cf24e0
NHE		 1917 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1918 * set this *before* calling this function.
1919 */
edcafe3c 1920 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1921 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1922 update_exception_bitmap(vcpu);
edcafe3c
AK		 1923 vcpu->arch.cr0_guest_owned_bits = 0;
1924 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1925 if (is_guest_mode(vcpu)) {
1926 /*
1927 * L1's specified read shadow might not contain the TS bit,
1928 * so now that we turned on shadowing of this bit, we need to
1929 * set this bit of the shadow. Like in nested_vmx_run we need
1930 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1931 * up-to-date here because we just decached cr0.TS (and we'll
1932 * only update vmcs12->guest_cr0 on nested exit).
1933 */
1934 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1935 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1936 (vcpu->arch.cr0 & X86_CR0_TS);
1937 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1938 } else
1939 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1940}
1941
6aa8b732
AK		 1942static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1943{
78ac8b47 1944 unsigned long rflags, save_rflags;
345dcaa8 1945
6de12732
AK		 1946 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1947 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1948 rflags = vmcs_readl(GUEST_RFLAGS);
1949 if (to_vmx(vcpu)->rmode.vm86_active) {
1950 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1951 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1952 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1953 }
1954 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1955 }
6de12732 1956 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1957}
1958
1959static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1960{
6de12732
AK		 1961 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1962 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1963 if (to_vmx(vcpu)->rmode.vm86_active) {
1964 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1965 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1966 }
6aa8b732
AK		 1967 vmcs_writel(GUEST_RFLAGS, rflags);
1968}
1969
37ccdcbe 1970static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1971{
1972 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1973 int ret = 0;
1974
1975 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1976 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1977 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1978 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1979
37ccdcbe 1980 return ret;
2809f5d2
GC		 1981}
1982
1983static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1984{
1985 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1986 u32 interruptibility = interruptibility_old;
1987
1988 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1989
48005f64 1990 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1991 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1992 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1993 interruptibility |= GUEST_INTR_STATE_STI;
1994
1995 if ((interruptibility != interruptibility_old))
1996 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1997}
1998
6aa8b732
AK		 1999static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2000{
2001 unsigned long rip;
6aa8b732 2002
5fdbf976 2003 rip = kvm_rip_read(vcpu);
6aa8b732 2004 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2005 kvm_rip_write(vcpu, rip);
6aa8b732 2006
2809f5d2
GC		 2007 /* skipping an emulated instruction also counts */
2008 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2009}
2010
0b6ac343
NHE		 2011/*
2012 * KVM wants to inject page-faults which it got to the guest. This function
2013 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2014 */
e011c663 2015static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2016{
2017 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2018
e011c663 2019 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2020 return 0;
2021
533558bc
JK		 2022 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2023 vmcs_read32(VM_EXIT_INTR_INFO),
2024 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2025 return 1;
2026}
2027
298101da 2028static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2029 bool has_error_code, u32 error_code,
2030 bool reinject)
298101da 2031{
77ab6db0 2032 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2033 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2034
e011c663
GN		 2035 if (!reinject && is_guest_mode(vcpu) &&
2036 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2037 return;
2038
8ab2d2e2 2039 if (has_error_code) {
77ab6db0 2040 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2041 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2042 }
77ab6db0 2043
7ffd92c5 2044 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2045 int inc_eip = 0;
2046 if (kvm_exception_is_soft(nr))
2047 inc_eip = vcpu->arch.event_exit_inst_len;
2048 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2049 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2050 return;
2051 }
2052
66fd3f7f
GN		 2053 if (kvm_exception_is_soft(nr)) {
2054 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2055 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2056 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2057 } else
2058 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2059
2060 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2061}
2062
4e47c7a6
SY		 2063static bool vmx_rdtscp_supported(void)
2064{
2065 return cpu_has_vmx_rdtscp();
2066}
2067
ad756a16
MJ		 2068static bool vmx_invpcid_supported(void)
2069{
2070 return cpu_has_vmx_invpcid() && enable_ept;
2071}
2072
a75beee6
ED		 2073/*
2074 * Swap MSR entry in host/guest MSR entry array.
2075 */
8b9cf98c 2076static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2077{
26bb0981 2078 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2079
2080 tmp = vmx->guest_msrs[to];
2081 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2082 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2083}
2084
8d14695f
YZ		 2085static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2086{
2087 unsigned long *msr_bitmap;
2088
2089 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2090 if (is_long_mode(vcpu))
2091 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2092 else
2093 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2094 } else {
2095 if (is_long_mode(vcpu))
2096 msr_bitmap = vmx_msr_bitmap_longmode;
2097 else
2098 msr_bitmap = vmx_msr_bitmap_legacy;
2099 }
2100
2101 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2102}
2103
e38aea3e
AK		 2104/*
2105 * Set up the vmcs to automatically save and restore system
2106 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2107 * mode, as fiddling with msrs is very expensive.
2108 */
8b9cf98c 2109static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2110{
26bb0981 2111 int save_nmsrs, index;
e38aea3e 2112
a75beee6
ED		 2113 save_nmsrs = 0;
2114#ifdef CONFIG_X86_64
8b9cf98c 2115 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2116 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2117 if (index >= 0)
8b9cf98c
RR		 2118 move_msr_up(vmx, index, save_nmsrs++);
2119 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2120 if (index >= 0)
8b9cf98c
RR		 2121 move_msr_up(vmx, index, save_nmsrs++);
2122 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2123 if (index >= 0)
8b9cf98c 2124 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2125 index = __find_msr_index(vmx, MSR_TSC_AUX);
2126 if (index >= 0 && vmx->rdtscp_enabled)
2127 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2128 /*
8c06585d 2129 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2130 * if efer.sce is enabled.
2131 */
8c06585d 2132 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2133 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2134 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2135 }
2136#endif
92c0d900
AK		 2137 index = __find_msr_index(vmx, MSR_EFER);
2138 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2139 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2140
26bb0981 2141 vmx->save_nmsrs = save_nmsrs;
5897297b 2142
8d14695f
YZ		 2143 if (cpu_has_vmx_msr_bitmap())
2144 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2145}
2146
6aa8b732
AK		 2147/*
2148 * reads and returns guest's timestamp counter "register"
2149 * guest_tsc = host_tsc + tsc_offset -- 21.3
2150 */
2151static u64 guest_read_tsc(void)
2152{
2153 u64 host_tsc, tsc_offset;
2154
2155 rdtscll(host_tsc);
2156 tsc_offset = vmcs_read64(TSC_OFFSET);
2157 return host_tsc + tsc_offset;
2158}
2159
d5c1785d
NHE		 2160/*
2161 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2162 * counter, even if a nested guest (L2) is currently running.
2163 */
48d89b92 2164static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2165{
886b470c 2166 u64 tsc_offset;
d5c1785d 2167
d5c1785d
NHE		 2168 tsc_offset = is_guest_mode(vcpu) ?
2169 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2170 vmcs_read64(TSC_OFFSET);
2171 return host_tsc + tsc_offset;
2172}
2173
4051b188 2174/*
cc578287
ZA		 2175 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2176 * software catchup for faster rates on slower CPUs.
4051b188 2177 */
cc578287 2178static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2179{
cc578287
ZA		 2180 if (!scale)
2181 return;
2182
2183 if (user_tsc_khz > tsc_khz) {
2184 vcpu->arch.tsc_catchup = 1;
2185 vcpu->arch.tsc_always_catchup = 1;
2186 } else
2187 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2188}
2189
ba904635
WA		 2190static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2191{
2192 return vmcs_read64(TSC_OFFSET);
2193}
2194
6aa8b732 2195/*
99e3e30a 2196 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2197 */
99e3e30a 2198static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2199{
27fc51b2 2200 if (is_guest_mode(vcpu)) {
7991825b 2201 /*
27fc51b2
NHE		 2202 * We're here if L1 chose not to trap WRMSR to TSC. According
2203 * to the spec, this should set L1's TSC; The offset that L1
2204 * set for L2 remains unchanged, and still needs to be added
2205 * to the newly set TSC to get L2's TSC.
7991825b 2206 */
27fc51b2
NHE		 2207 struct vmcs12 *vmcs12;
2208 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2209 /* recalculate vmcs02.TSC_OFFSET: */
2210 vmcs12 = get_vmcs12(vcpu);
2211 vmcs_write64(TSC_OFFSET, offset +
2212 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2213 vmcs12->tsc_offset : 0));
2214 } else {
489223ed
YY		 2215 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2216 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2217 vmcs_write64(TSC_OFFSET, offset);
2218 }
6aa8b732
AK		 2219}
2220
f1e2b260 2221static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2222{
2223 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2224
e48672fa 2225 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2226 if (is_guest_mode(vcpu)) {
2227 /* Even when running L2, the adjustment needs to apply to L1 */
2228 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2229 } else
2230 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2231 offset + adjustment);
e48672fa
ZA		 2232}
2233
857e4099
JR		 2234static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2235{
2236 return target_tsc - native_read_tsc();
2237}
2238
801d3424
NHE		 2239static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2240{
2241 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2242 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2243}
2244
2245/*
2246 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2247 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2248 * all guests if the "nested" module option is off, and can also be disabled
2249 * for a single guest by disabling its VMX cpuid bit.
2250 */
2251static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2252{
2253 return nested && guest_cpuid_has_vmx(vcpu);
2254}
2255
b87a51ae
NHE		 2256/*
2257 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2258 * returned for the various VMX controls MSRs when nested VMX is enabled.
2259 * The same values should also be used to verify that vmcs12 control fields are
2260 * valid during nested entry from L1 to L2.
2261 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2262 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2263 * bit in the high half is on if the corresponding bit in the control field
2264 * may be on. See also vmx_control_verify().
2265 * TODO: allow these variables to be modified (downgraded) by module options
2266 * or other means.
2267 */
2268static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2269static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2270static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2271static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2272static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2273static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2274static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2275static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2276static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2277static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2278static __init void nested_vmx_setup_ctls_msrs(void)
2279{
2280 /*
2281 * Note that as a general rule, the high half of the MSRs (bits in
2282 * the control fields which may be 1) should be initialized by the
2283 * intersection of the underlying hardware's MSR (i.e., features which
2284 * can be supported) and the list of features we want to expose -
2285 * because they are known to be properly supported in our code.
2286 * Also, usually, the low half of the MSRs (bits which must be 1) can
2287 * be set to 0, meaning that L1 may turn off any of these bits. The
2288 * reason is that if one of these bits is necessary, it will appear
2289 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2290 * fields of vmcs01 and vmcs02, will turn these bits off - and
2291 * nested_vmx_exit_handled() will not pass related exits to L1.
2292 * These rules have exceptions below.
2293 */
2294
2295 /* pin-based controls */
eabeaacc
JK		 2296 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2297 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2298 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2299 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2300 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2301 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2302 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2303
3dbcd8da 2304 /* exit controls */
c0dfee58
ACL		 2305 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2306 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2307 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2308
c0dfee58 2309 nested_vmx_exit_ctls_high &=
b87a51ae 2310#ifdef CONFIG_X86_64
c0dfee58 2311 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2312#endif
f4124500
JK		 2313 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2314 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2315 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2316 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2317
36be0b9d
PB		 2318 if (vmx_mpx_supported())
2319 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2320
2996fca0
JK		 2321 /* We support free control of debug control saving. */
2322 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2323 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2324
b87a51ae
NHE		 2325 /* entry controls */
2326 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2327 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2328 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2329 nested_vmx_entry_ctls_high &=
57435349
JK		 2330#ifdef CONFIG_X86_64
2331 VM_ENTRY_IA32E_MODE |
2332#endif
2333 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2334 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2335 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2336 if (vmx_mpx_supported())
2337 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2338
2996fca0
JK		 2339 /* We support free control of debug control loading. */
2340 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2341 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2342
b87a51ae
NHE		 2343 /* cpu-based controls */
2344 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2345 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2346 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2347 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2348 CPU_BASED_VIRTUAL_INTR_PENDING |
2349 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2350 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2351 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2352 CPU_BASED_CR3_STORE_EXITING |
2353#ifdef CONFIG_X86_64
2354 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2355#endif
2356 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2357 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2358 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2359 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2360 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2361 /*
2362 * We can allow some features even when not supported by the
2363 * hardware. For example, L1 can specify an MSR bitmap - and we
2364 * can use it to avoid exits to L1 - even when L0 runs L2
2365 * without MSR bitmaps.
2366 */
560b7ee1
JK		 2367 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2368 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2369
3dcdf3ec
JK		 2370 /* We support free control of CR3 access interception. */
2371 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2372 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2373
b87a51ae
NHE		 2374 /* secondary cpu-based controls */
2375 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2376 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2377 nested_vmx_secondary_ctls_low = 0;
2378 nested_vmx_secondary_ctls_high &=
d6851fbe 2379 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2380 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2381 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2382
afa61f75
NHE		 2383 if (enable_ept) {
2384 /* nested EPT: emulate EPT also to L1 */
2385 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2386 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2387 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2388 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2389 nested_vmx_ept_caps &= vmx_capability.ept;
2390 /*
4b855078
BD		 2391 * For nested guests, we don't do anything specific
2392 * for single context invalidation. Hence, only advertise
2393 * support for global context invalidation.
afa61f75 2394 */
4b855078 2395 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2396 } else
2397 nested_vmx_ept_caps = 0;
2398
c18911a2
JK		 2399 /* miscellaneous data */
2400 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2401 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2402 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2403 VMX_MISC_ACTIVITY_HLT;
c18911a2 2404 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2405}
2406
2407static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2408{
2409 /*
2410 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2411 */
2412 return ((control & high) | low) == control;
2413}
2414
2415static inline u64 vmx_control_msr(u32 low, u32 high)
2416{
2417 return low | ((u64)high << 32);
2418}
2419
cae50139 2420/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2421static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2422{
b87a51ae 2423 switch (msr_index) {
b87a51ae
NHE		 2424 case MSR_IA32_VMX_BASIC:
2425 /*
2426 * This MSR reports some information about VMX support. We
2427 * should return information about the VMX we emulate for the
2428 * guest, and the VMCS structure we give it - not about the
2429 * VMX support of the underlying hardware.
2430 */
3dbcd8da 2431 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2432 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2433 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2434 break;
2435 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2436 case MSR_IA32_VMX_PINBASED_CTLS:
2437 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2438 nested_vmx_pinbased_ctls_high);
2439 break;
2440 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2441 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2442 nested_vmx_procbased_ctls_high);
2443 break;
b87a51ae
NHE		 2444 case MSR_IA32_VMX_PROCBASED_CTLS:
2445 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2446 nested_vmx_procbased_ctls_high);
2447 break;
2448 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2449 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2450 nested_vmx_exit_ctls_high);
2451 break;
b87a51ae
NHE		 2452 case MSR_IA32_VMX_EXIT_CTLS:
2453 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2454 nested_vmx_exit_ctls_high);
2455 break;
2456 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2457 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2458 nested_vmx_entry_ctls_high);
2459 break;
b87a51ae
NHE		 2460 case MSR_IA32_VMX_ENTRY_CTLS:
2461 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2462 nested_vmx_entry_ctls_high);
2463 break;
2464 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2465 *pdata = vmx_control_msr(nested_vmx_misc_low,
2466 nested_vmx_misc_high);
b87a51ae
NHE		 2467 break;
2468 /*
2469 * These MSRs specify bits which the guest must keep fixed (on or off)
2470 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2471 * We picked the standard core2 setting.
2472 */
2473#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2474#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2475 case MSR_IA32_VMX_CR0_FIXED0:
2476 *pdata = VMXON_CR0_ALWAYSON;
2477 break;
2478 case MSR_IA32_VMX_CR0_FIXED1:
2479 *pdata = -1ULL;
2480 break;
2481 case MSR_IA32_VMX_CR4_FIXED0:
2482 *pdata = VMXON_CR4_ALWAYSON;
2483 break;
2484 case MSR_IA32_VMX_CR4_FIXED1:
2485 *pdata = -1ULL;
2486 break;
2487 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2488 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2489 break;
2490 case MSR_IA32_VMX_PROCBASED_CTLS2:
2491 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2492 nested_vmx_secondary_ctls_high);
2493 break;
2494 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2495 /* Currently, no nested vpid support */
2496 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2497 break;
2498 default:
b87a51ae 2499 return 1;
b3897a49
NHE		 2500 }
2501
b87a51ae
NHE		 2502 return 0;
2503}
2504
6aa8b732
AK		 2505/*
2506 * Reads an msr value (of 'msr_index') into 'pdata'.
2507 * Returns 0 on success, non-0 otherwise.
2508 * Assumes vcpu_load() was already called.
2509 */
2510static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2511{
2512 u64 data;
26bb0981 2513 struct shared_msr_entry *msr;
6aa8b732
AK		 2514
2515 if (!pdata) {
2516 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2517 return -EINVAL;
2518 }
2519
2520 switch (msr_index) {
05b3e0c2 2521#ifdef CONFIG_X86_64
6aa8b732
AK		 2522 case MSR_FS_BASE:
2523 data = vmcs_readl(GUEST_FS_BASE);
2524 break;
2525 case MSR_GS_BASE:
2526 data = vmcs_readl(GUEST_GS_BASE);
2527 break;
44ea2b17
AK		 2528 case MSR_KERNEL_GS_BASE:
2529 vmx_load_host_state(to_vmx(vcpu));
2530 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2531 break;
26bb0981 2532#endif
6aa8b732 2533 case MSR_EFER:
3bab1f5d 2534 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2535 case MSR_IA32_TSC:
6aa8b732
AK		 2536 data = guest_read_tsc();
2537 break;
2538 case MSR_IA32_SYSENTER_CS:
2539 data = vmcs_read32(GUEST_SYSENTER_CS);
2540 break;
2541 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2542 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2543 break;
2544 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2545 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2546 break;
0dd376e7 2547 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2548 if (!vmx_mpx_supported())
2549 return 1;
0dd376e7
LJ		 2550 data = vmcs_read64(GUEST_BNDCFGS);
2551 break;
cae50139
JK		 2552 case MSR_IA32_FEATURE_CONTROL:
2553 if (!nested_vmx_allowed(vcpu))
2554 return 1;
2555 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2556 break;
2557 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2558 if (!nested_vmx_allowed(vcpu))
2559 return 1;
2560 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2561 case MSR_TSC_AUX:
2562 if (!to_vmx(vcpu)->rdtscp_enabled)
2563 return 1;
2564 /* Otherwise falls through */
6aa8b732 2565 default:
8b9cf98c 2566 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2567 if (msr) {
2568 data = msr->data;
2569 break;
6aa8b732 2570 }
3bab1f5d 2571 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2572 }
2573
2574 *pdata = data;
2575 return 0;
2576}
2577
cae50139
JK		 2578static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2579
6aa8b732
AK		 2580/*
2581 * Writes msr value into into the appropriate "register".
2582 * Returns 0 on success, non-0 otherwise.
2583 * Assumes vcpu_load() was already called.
2584 */
8fe8ab46 2585static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2586{
a2fa3e9f 2587 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2588 struct shared_msr_entry *msr;
2cc51560 2589 int ret = 0;
8fe8ab46
WA		 2590 u32 msr_index = msr_info->index;
2591 u64 data = msr_info->data;
2cc51560 2592
6aa8b732 2593 switch (msr_index) {
3bab1f5d 2594 case MSR_EFER:
8fe8ab46 2595 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2596 break;
16175a79 2597#ifdef CONFIG_X86_64
6aa8b732 2598 case MSR_FS_BASE:
2fb92db1 2599 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2600 vmcs_writel(GUEST_FS_BASE, data);
2601 break;
2602 case MSR_GS_BASE:
2fb92db1 2603 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2604 vmcs_writel(GUEST_GS_BASE, data);
2605 break;
44ea2b17
AK		 2606 case MSR_KERNEL_GS_BASE:
2607 vmx_load_host_state(vmx);
2608 vmx->msr_guest_kernel_gs_base = data;
2609 break;
6aa8b732
AK		 2610#endif
2611 case MSR_IA32_SYSENTER_CS:
2612 vmcs_write32(GUEST_SYSENTER_CS, data);
2613 break;
2614 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2615 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2616 break;
2617 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2618 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2619 break;
0dd376e7 2620 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2621 if (!vmx_mpx_supported())
2622 return 1;
0dd376e7
LJ		 2623 vmcs_write64(GUEST_BNDCFGS, data);
2624 break;
af24a4e4 2625 case MSR_IA32_TSC:
8fe8ab46 2626 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2627 break;
468d472f
SY		 2628 case MSR_IA32_CR_PAT:
2629 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2630 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2631 return 1;
468d472f
SY		 2632 vmcs_write64(GUEST_IA32_PAT, data);
2633 vcpu->arch.pat = data;
2634 break;
2635 }
8fe8ab46 2636 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2637 break;
ba904635
WA		 2638 case MSR_IA32_TSC_ADJUST:
2639 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2640 break;
cae50139
JK		 2641 case MSR_IA32_FEATURE_CONTROL:
2642 if (!nested_vmx_allowed(vcpu) ||
2643 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2644 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2645 return 1;
2646 vmx->nested.msr_ia32_feature_control = data;
2647 if (msr_info->host_initiated && data == 0)
2648 vmx_leave_nested(vcpu);
2649 break;
2650 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2651 return 1; /* they are read-only */
4e47c7a6
SY		 2652 case MSR_TSC_AUX:
2653 if (!vmx->rdtscp_enabled)
2654 return 1;
2655 /* Check reserved bit, higher 32 bits should be zero */
2656 if ((data >> 32) != 0)
2657 return 1;
2658 /* Otherwise falls through */
6aa8b732 2659 default:
8b9cf98c 2660 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2661 if (msr) {
8b3c3104 2662 u64 old_msr_data = msr->data;
3bab1f5d 2663 msr->data = data;
2225fd56
AK		 2664 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2665 preempt_disable();
8b3c3104
AH		 2666 ret = kvm_set_shared_msr(msr->index, msr->data,
2667 msr->mask);
2225fd56 2668 preempt_enable();
8b3c3104
AH		 2669 if (ret)
2670 msr->data = old_msr_data;
2225fd56 2671 }
3bab1f5d 2672 break;
6aa8b732 2673 }
8fe8ab46 2674 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2675 }
2676
2cc51560 2677 return ret;
6aa8b732
AK		 2678}
2679
5fdbf976 2680static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2681{
5fdbf976
MT		 2682 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2683 switch (reg) {
2684 case VCPU_REGS_RSP:
2685 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2686 break;
2687 case VCPU_REGS_RIP:
2688 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2689 break;
6de4f3ad
AK		 2690 case VCPU_EXREG_PDPTR:
2691 if (enable_ept)
2692 ept_save_pdptrs(vcpu);
2693 break;
5fdbf976
MT		 2694 default:
2695 break;
2696 }
6aa8b732
AK		 2697}
2698
6aa8b732
AK		 2699static __init int cpu_has_kvm_support(void)
2700{
6210e37b 2701 return cpu_has_vmx();
6aa8b732
AK		 2702}
2703
2704static __init int vmx_disabled_by_bios(void)
2705{
2706 u64 msr;
2707
2708 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2709 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2710 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2711 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2712 && tboot_enabled())
2713 return 1;
23f3e991 2714 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2715 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2716 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2717 && !tboot_enabled()) {
2718 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2719 "activate TXT before enabling KVM\n");
cafd6659 2720 return 1;
f9335afe 2721 }
23f3e991
JC		 2722 /* launched w/o TXT and VMX disabled */
2723 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2724 && !tboot_enabled())
2725 return 1;
cafd6659
SW		 2726 }
2727
2728 return 0;
6aa8b732
AK		 2729}
2730
7725b894
DX		 2731static void kvm_cpu_vmxon(u64 addr)
2732{
2733 asm volatile (ASM_VMX_VMXON_RAX
2734 : : "a"(&addr), "m"(addr)
2735 : "memory", "cc");
2736}
2737
13a34e06 2738static int hardware_enable(void)
6aa8b732
AK		 2739{
2740 int cpu = raw_smp_processor_id();
2741 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2742 u64 old, test_bits;
6aa8b732 2743
10474ae8
AG		 2744 if (read_cr4() & X86_CR4_VMXE)
2745 return -EBUSY;
2746
d462b819 2747 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2748
2749 /*
2750 * Now we can enable the vmclear operation in kdump
2751 * since the loaded_vmcss_on_cpu list on this cpu
2752 * has been initialized.
2753 *
2754 * Though the cpu is not in VMX operation now, there
2755 * is no problem to enable the vmclear operation
2756 * for the loaded_vmcss_on_cpu list is empty!
2757 */
2758 crash_enable_local_vmclear(cpu);
2759
6aa8b732 2760 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2761
2762 test_bits = FEATURE_CONTROL_LOCKED;
2763 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2764 if (tboot_enabled())
2765 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2766
2767 if ((old & test_bits) != test_bits) {
6aa8b732 2768 /* enable and lock */
cafd6659
SW		 2769 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2770 }
66aee91a 2771 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2772
4610c9cc
DX		 2773 if (vmm_exclusive) {
2774 kvm_cpu_vmxon(phys_addr);
2775 ept_sync_global();
2776 }
10474ae8 2777
89cbc767 2778 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2779
10474ae8 2780 return 0;
6aa8b732
AK		 2781}
2782
d462b819 2783static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2784{
2785 int cpu = raw_smp_processor_id();
d462b819 2786 struct loaded_vmcs *v, *n;
543e4243 2787
d462b819
NHE		 2788 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2789 loaded_vmcss_on_cpu_link)
2790 __loaded_vmcs_clear(v);
543e4243
AK		 2791}
2792
710ff4a8
EH		 2793
2794/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2795 * tricks.
2796 */
2797static void kvm_cpu_vmxoff(void)
6aa8b732 2798{
4ecac3fd 2799 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2800}
2801
13a34e06 2802static void hardware_disable(void)
710ff4a8 2803{
4610c9cc 2804 if (vmm_exclusive) {
d462b819 2805 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2806 kvm_cpu_vmxoff();
2807 }
7725b894 2808 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2809}
2810
1c3d14fe 2811static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2812 u32 msr, u32 *result)
1c3d14fe
YS		 2813{
2814 u32 vmx_msr_low, vmx_msr_high;
2815 u32 ctl = ctl_min | ctl_opt;
2816
2817 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2818
2819 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2820 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2821
2822 /* Ensure minimum (required) set of control bits are supported. */
2823 if (ctl_min & ~ctl)
002c7f7c 2824 return -EIO;
1c3d14fe
YS		 2825
2826 *result = ctl;
2827 return 0;
2828}
2829
110312c8
AK		 2830static __init bool allow_1_setting(u32 msr, u32 ctl)
2831{
2832 u32 vmx_msr_low, vmx_msr_high;
2833
2834 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2835 return vmx_msr_high & ctl;
2836}
2837
002c7f7c 2838static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2839{
2840 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2841 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2842 u32 _pin_based_exec_control = 0;
2843 u32 _cpu_based_exec_control = 0;
f78e0e2e 2844 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2845 u32 _vmexit_control = 0;
2846 u32 _vmentry_control = 0;
2847
10166744 2848 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2849#ifdef CONFIG_X86_64
2850 CPU_BASED_CR8_LOAD_EXITING |
2851 CPU_BASED_CR8_STORE_EXITING |
2852#endif
d56f546d
SY		 2853 CPU_BASED_CR3_LOAD_EXITING |
2854 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2855 CPU_BASED_USE_IO_BITMAPS |
2856 CPU_BASED_MOV_DR_EXITING |
a7052897 2857 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2858 CPU_BASED_MWAIT_EXITING |
2859 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2860 CPU_BASED_INVLPG_EXITING |
2861 CPU_BASED_RDPMC_EXITING;
443381a8 2862
f78e0e2e 2863 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2864 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2865 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2866 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2867 &_cpu_based_exec_control) < 0)
002c7f7c 2868 return -EIO;
6e5d865c
YS		 2869#ifdef CONFIG_X86_64
2870 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2871 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2872 ~CPU_BASED_CR8_STORE_EXITING;
2873#endif
f78e0e2e 2874 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2875 min2 = 0;
2876 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2877 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2878 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2879 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2880 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2881 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2882 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2883 SECONDARY_EXEC_RDTSCP |
83d4c286 2884 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2885 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2886 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2887 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2888 if (adjust_vmx_controls(min2, opt2,
2889 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2890 &_cpu_based_2nd_exec_control) < 0)
2891 return -EIO;
2892 }
2893#ifndef CONFIG_X86_64
2894 if (!(_cpu_based_2nd_exec_control &
2895 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2896 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2897#endif
83d4c286
YZ		 2898
2899 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2900 _cpu_based_2nd_exec_control &= ~(
8d14695f 2901 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2902 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2903 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2904
d56f546d 2905 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2906 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2907 enabled */
5fff7d27
GN		 2908 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2909 CPU_BASED_CR3_STORE_EXITING |
2910 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2911 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2912 vmx_capability.ept, vmx_capability.vpid);
2913 }
1c3d14fe 2914
81908bf4 2915 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2916#ifdef CONFIG_X86_64
2917 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2918#endif
a547c6db 2919 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2920 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2921 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2922 &_vmexit_control) < 0)
002c7f7c 2923 return -EIO;
1c3d14fe 2924
01e439be
YZ		 2925 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2926 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2927 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2928 &_pin_based_exec_control) < 0)
2929 return -EIO;
2930
2931 if (!(_cpu_based_2nd_exec_control &
2932 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2933 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2934 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2935
c845f9c6 2936 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2937 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2938 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2939 &_vmentry_control) < 0)
002c7f7c 2940 return -EIO;
6aa8b732 2941
c68876fd 2942 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2943
2944 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2945 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2946 return -EIO;
1c3d14fe
YS		 2947
2948#ifdef CONFIG_X86_64
2949 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2950 if (vmx_msr_high & (1u<<16))
002c7f7c 2951 return -EIO;
1c3d14fe
YS		 2952#endif
2953
2954 /* Require Write-Back (WB) memory type for VMCS accesses. */
2955 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2956 return -EIO;
1c3d14fe 2957
002c7f7c
YS		 2958 vmcs_conf->size = vmx_msr_high & 0x1fff;
2959 vmcs_conf->order = get_order(vmcs_config.size);
2960 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2961
002c7f7c
YS		 2962 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2963 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2964 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2965 vmcs_conf->vmexit_ctrl = _vmexit_control;
2966 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2967
110312c8
AK		 2968 cpu_has_load_ia32_efer =
2969 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2970 VM_ENTRY_LOAD_IA32_EFER)
2971 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2972 VM_EXIT_LOAD_IA32_EFER);
2973
8bf00a52
GN		 2974 cpu_has_load_perf_global_ctrl =
2975 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2976 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2977 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2978 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2979
2980 /*
2981 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2982 * but due to arrata below it can't be used. Workaround is to use
2983 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2984 *
2985 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2986 *
2987 * AAK155 (model 26)
2988 * AAP115 (model 30)
2989 * AAT100 (model 37)
2990 * BC86,AAY89,BD102 (model 44)
2991 * BA97 (model 46)
2992 *
2993 */
2994 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2995 switch (boot_cpu_data.x86_model) {
2996 case 26:
2997 case 30:
2998 case 37:
2999 case 44:
3000 case 46:
3001 cpu_has_load_perf_global_ctrl = false;
3002 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3003 "does not work properly. Using workaround\n");
3004 break;
3005 default:
3006 break;
3007 }
3008 }
3009
1c3d14fe 3010 return 0;
c68876fd 3011}
6aa8b732
AK		 3012
3013static struct vmcs *alloc_vmcs_cpu(int cpu)
3014{
3015 int node = cpu_to_node(cpu);
3016 struct page *pages;
3017 struct vmcs *vmcs;
3018
6484eb3e 3019 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3020 if (!pages)
3021 return NULL;
3022 vmcs = page_address(pages);
1c3d14fe
YS		 3023 memset(vmcs, 0, vmcs_config.size);
3024 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3025 return vmcs;
3026}
3027
3028static struct vmcs *alloc_vmcs(void)
3029{
d3b2c338 3030 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3031}
3032
3033static void free_vmcs(struct vmcs *vmcs)
3034{
1c3d14fe 3035 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3036}
3037
d462b819
NHE		 3038/*
3039 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3040 */
3041static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3042{
3043 if (!loaded_vmcs->vmcs)
3044 return;
3045 loaded_vmcs_clear(loaded_vmcs);
3046 free_vmcs(loaded_vmcs->vmcs);
3047 loaded_vmcs->vmcs = NULL;
3048}
3049
39959588 3050static void free_kvm_area(void)
6aa8b732
AK		 3051{
3052 int cpu;
3053
3230bb47 3054 for_each_possible_cpu(cpu) {
6aa8b732 3055 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3056 per_cpu(vmxarea, cpu) = NULL;
3057 }
6aa8b732
AK		 3058}
3059
fe2b201b
BD		 3060static void init_vmcs_shadow_fields(void)
3061{
3062 int i, j;
3063
3064 /* No checks for read only fields yet */
3065
3066 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3067 switch (shadow_read_write_fields[i]) {
3068 case GUEST_BNDCFGS:
3069 if (!vmx_mpx_supported())
3070 continue;
3071 break;
3072 default:
3073 break;
3074 }
3075
3076 if (j < i)
3077 shadow_read_write_fields[j] =
3078 shadow_read_write_fields[i];
3079 j++;
3080 }
3081 max_shadow_read_write_fields = j;
3082
3083 /* shadowed fields guest access without vmexit */
3084 for (i = 0; i < max_shadow_read_write_fields; i++) {
3085 clear_bit(shadow_read_write_fields[i],
3086 vmx_vmwrite_bitmap);
3087 clear_bit(shadow_read_write_fields[i],
3088 vmx_vmread_bitmap);
3089 }
3090 for (i = 0; i < max_shadow_read_only_fields; i++)
3091 clear_bit(shadow_read_only_fields[i],
3092 vmx_vmread_bitmap);
3093}
3094
6aa8b732
AK		 3095static __init int alloc_kvm_area(void)
3096{
3097 int cpu;
3098
3230bb47 3099 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3100 struct vmcs *vmcs;
3101
3102 vmcs = alloc_vmcs_cpu(cpu);
3103 if (!vmcs) {
3104 free_kvm_area();
3105 return -ENOMEM;
3106 }
3107
3108 per_cpu(vmxarea, cpu) = vmcs;
3109 }
3110 return 0;
3111}
3112
14168786
GN		 3113static bool emulation_required(struct kvm_vcpu *vcpu)
3114{
3115 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3116}
3117
91b0aa2c 3118static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3119 struct kvm_segment *save)
6aa8b732 3120{
d99e4152
GN		 3121 if (!emulate_invalid_guest_state) {
3122 /*
3123 * CS and SS RPL should be equal during guest entry according
3124 * to VMX spec, but in reality it is not always so. Since vcpu
3125 * is in the middle of the transition from real mode to
3126 * protected mode it is safe to assume that RPL 0 is a good
3127 * default value.
3128 */
3129 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3130 save->selector &= ~SELECTOR_RPL_MASK;
3131 save->dpl = save->selector & SELECTOR_RPL_MASK;
3132 save->s = 1;
6aa8b732 3133 }
d99e4152 3134 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3135}
3136
3137static void enter_pmode(struct kvm_vcpu *vcpu)
3138{
3139 unsigned long flags;
a89a8fb9 3140 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3141
d99e4152
GN		 3142 /*
3143 * Update real mode segment cache. It may be not up-to-date if sement
3144 * register was written while vcpu was in a guest mode.
3145 */
3146 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3147 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3148 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3149 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3150 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3151 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3152
7ffd92c5 3153 vmx->rmode.vm86_active = 0;
6aa8b732 3154
2fb92db1
AK		 3155 vmx_segment_cache_clear(vmx);
3156
f5f7b2fe 3157 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3158
3159 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3160 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3161 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3162 vmcs_writel(GUEST_RFLAGS, flags);
3163
66aee91a
RR		 3164 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3165 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3166
3167 update_exception_bitmap(vcpu);
3168
91b0aa2c
GN		 3169 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3170 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3171 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3172 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3173 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3174 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3175}
3176
f5f7b2fe 3177static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3178{
772e0318 3179 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3180 struct kvm_segment var = *save;
3181
3182 var.dpl = 0x3;
3183 if (seg == VCPU_SREG_CS)
3184 var.type = 0x3;
3185
3186 if (!emulate_invalid_guest_state) {
3187 var.selector = var.base >> 4;
3188 var.base = var.base & 0xffff0;
3189 var.limit = 0xffff;
3190 var.g = 0;
3191 var.db = 0;
3192 var.present = 1;
3193 var.s = 1;
3194 var.l = 0;
3195 var.unusable = 0;
3196 var.type = 0x3;
3197 var.avl = 0;
3198 if (save->base & 0xf)
3199 printk_once(KERN_WARNING "kvm: segment base is not "
3200 "paragraph aligned when entering "
3201 "protected mode (seg=%d)", seg);
3202 }
6aa8b732 3203
d99e4152
GN		 3204 vmcs_write16(sf->selector, var.selector);
3205 vmcs_write32(sf->base, var.base);
3206 vmcs_write32(sf->limit, var.limit);
3207 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3208}
3209
3210static void enter_rmode(struct kvm_vcpu *vcpu)
3211{
3212 unsigned long flags;
a89a8fb9 3213 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3214
f5f7b2fe
AK		 3215 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3216 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3217 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3218 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3219 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3220 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3221 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3222
7ffd92c5 3223 vmx->rmode.vm86_active = 1;
6aa8b732 3224
776e58ea
GN		 3225 /*
3226 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3227 * vcpu. Warn the user that an update is overdue.
776e58ea 3228 */
4918c6ca 3229 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3230 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3231 "called before entering vcpu\n");
776e58ea 3232
2fb92db1
AK		 3233 vmx_segment_cache_clear(vmx);
3234
4918c6ca 3235 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3236 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3237 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3238
3239 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3240 vmx->rmode.save_rflags = flags;
6aa8b732 3241
053de044 3242 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3243
3244 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3245 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3246 update_exception_bitmap(vcpu);
3247
d99e4152
GN		 3248 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3249 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3250 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3251 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3252 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3253 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3254
8668a3c4 3255 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3256}
3257
401d10de
AS		 3258static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3259{
3260 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3261 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3262
3263 if (!msr)
3264 return;
401d10de 3265
44ea2b17
AK		 3266 /*
3267 * Force kernel_gs_base reloading before EFER changes, as control
3268 * of this msr depends on is_long_mode().
3269 */
3270 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3271 vcpu->arch.efer = efer;
401d10de 3272 if (efer & EFER_LMA) {
2961e876 3273 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3274 msr->data = efer;
3275 } else {
2961e876 3276 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3277
3278 msr->data = efer & ~EFER_LME;
3279 }
3280 setup_msrs(vmx);
3281}
3282
05b3e0c2 3283#ifdef CONFIG_X86_64
6aa8b732
AK		 3284
3285static void enter_lmode(struct kvm_vcpu *vcpu)
3286{
3287 u32 guest_tr_ar;
3288
2fb92db1
AK		 3289 vmx_segment_cache_clear(to_vmx(vcpu));
3290
6aa8b732
AK		 3291 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3292 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3293 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3294 __func__);
6aa8b732
AK		 3295 vmcs_write32(GUEST_TR_AR_BYTES,
3296 (guest_tr_ar & ~AR_TYPE_MASK)
3297 | AR_TYPE_BUSY_64_TSS);
3298 }
da38f438 3299 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3300}
3301
3302static void exit_lmode(struct kvm_vcpu *vcpu)
3303{
2961e876 3304 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3305 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3306}
3307
3308#endif
3309
2384d2b3
SY		 3310static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3311{
b9d762fa 3312 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3313 if (enable_ept) {
3314 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3315 return;
4e1096d2 3316 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3317 }
2384d2b3
SY		 3318}
3319
e8467fda
AK		 3320static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3321{
3322 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3323
3324 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3325 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3326}
3327
aff48baa
AK		 3328static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3329{
3330 if (enable_ept && is_paging(vcpu))
3331 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3332 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3333}
3334
25c4c276 3335static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3336{
fc78f519
AK		 3337 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3338
3339 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3340 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3341}
3342
1439442c
SY		 3343static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3344{
d0d538b9
GN		 3345 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3346
6de4f3ad
AK		 3347 if (!test_bit(VCPU_EXREG_PDPTR,
3348 (unsigned long *)&vcpu->arch.regs_dirty))
3349 return;
3350
1439442c 3351 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3352 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3353 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3354 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3355 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3356 }
3357}
3358
8f5d549f
AK		 3359static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3360{
d0d538b9
GN		 3361 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3362
8f5d549f 3363 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3364 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3365 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3366 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3367 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3368 }
6de4f3ad
AK		 3369
3370 __set_bit(VCPU_EXREG_PDPTR,
3371 (unsigned long *)&vcpu->arch.regs_avail);
3372 __set_bit(VCPU_EXREG_PDPTR,
3373 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3374}
3375
5e1746d6 3376static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3377
3378static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3379 unsigned long cr0,
3380 struct kvm_vcpu *vcpu)
3381{
5233dd51
MT		 3382 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3383 vmx_decache_cr3(vcpu);
1439442c
SY		 3384 if (!(cr0 & X86_CR0_PG)) {
3385 /* From paging/starting to nonpaging */
3386 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3387 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3388 (CPU_BASED_CR3_LOAD_EXITING |
3389 CPU_BASED_CR3_STORE_EXITING));
3390 vcpu->arch.cr0 = cr0;
fc78f519 3391 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3392 } else if (!is_paging(vcpu)) {
3393 /* From nonpaging to paging */
3394 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3395 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3396 ~(CPU_BASED_CR3_LOAD_EXITING |
3397 CPU_BASED_CR3_STORE_EXITING));
3398 vcpu->arch.cr0 = cr0;
fc78f519 3399 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3400 }
95eb84a7
SY		 3401
3402 if (!(cr0 & X86_CR0_WP))
3403 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3404}
3405
6aa8b732
AK		 3406static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3407{
7ffd92c5 3408 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3409 unsigned long hw_cr0;
3410
5037878e 3411 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3412 if (enable_unrestricted_guest)
5037878e 3413 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3414 else {
5037878e 3415 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3416
218e763f
GN		 3417 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3418 enter_pmode(vcpu);
6aa8b732 3419
218e763f
GN		 3420 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3421 enter_rmode(vcpu);
3422 }
6aa8b732 3423
05b3e0c2 3424#ifdef CONFIG_X86_64
f6801dff 3425 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3426 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3427 enter_lmode(vcpu);
707d92fa 3428 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3429 exit_lmode(vcpu);
3430 }
3431#endif
3432
089d034e 3433 if (enable_ept)
1439442c
SY		 3434 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3435
02daab21 3436 if (!vcpu->fpu_active)
81231c69 3437 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3438
6aa8b732 3439 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3440 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3441 vcpu->arch.cr0 = cr0;
14168786
GN		 3442
3443 /* depends on vcpu->arch.cr0 to be set to a new value */
3444 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3445}
3446
1439442c
SY		 3447static u64 construct_eptp(unsigned long root_hpa)
3448{
3449 u64 eptp;
3450
3451 /* TODO write the value reading from MSR */
3452 eptp = VMX_EPT_DEFAULT_MT |
3453 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3454 if (enable_ept_ad_bits)
3455 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3456 eptp |= (root_hpa & PAGE_MASK);
3457
3458 return eptp;
3459}
3460
6aa8b732
AK		 3461static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3462{
1439442c
SY		 3463 unsigned long guest_cr3;
3464 u64 eptp;
3465
3466 guest_cr3 = cr3;
089d034e 3467 if (enable_ept) {
1439442c
SY		 3468 eptp = construct_eptp(cr3);
3469 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3470 if (is_paging(vcpu) || is_guest_mode(vcpu))
3471 guest_cr3 = kvm_read_cr3(vcpu);
3472 else
3473 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3474 ept_load_pdptrs(vcpu);
1439442c
SY		 3475 }
3476
2384d2b3 3477 vmx_flush_tlb(vcpu);
1439442c 3478 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3479}
3480
5e1746d6 3481static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3482{
7ffd92c5 3483 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3484 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3485
5e1746d6
NHE		 3486 if (cr4 & X86_CR4_VMXE) {
3487 /*
3488 * To use VMXON (and later other VMX instructions), a guest
3489 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3490 * So basically the check on whether to allow nested VMX
3491 * is here.
3492 */
3493 if (!nested_vmx_allowed(vcpu))
3494 return 1;
1a0d74e6
JK		 3495 }
3496 if (to_vmx(vcpu)->nested.vmxon &&
3497 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3498 return 1;
3499
ad312c7c 3500 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3501 if (enable_ept) {
3502 if (!is_paging(vcpu)) {
3503 hw_cr4 &= ~X86_CR4_PAE;
3504 hw_cr4 |= X86_CR4_PSE;
c08800a5 3505 /*
e1e746b3
FW		 3506 * SMEP/SMAP is disabled if CPU is in non-paging mode
3507 * in hardware. However KVM always uses paging mode to
c08800a5 3508 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3509 * To emulate this behavior, SMEP/SMAP needs to be
3510 * manually disabled when guest switches to non-paging
3511 * mode.
c08800a5 3512 */
e1e746b3 3513 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3514 } else if (!(cr4 & X86_CR4_PAE)) {
3515 hw_cr4 &= ~X86_CR4_PAE;
3516 }
3517 }
1439442c
SY		 3518
3519 vmcs_writel(CR4_READ_SHADOW, cr4);
3520 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3521 return 0;
6aa8b732
AK		 3522}
3523
6aa8b732
AK		 3524static void vmx_get_segment(struct kvm_vcpu *vcpu,
3525 struct kvm_segment *var, int seg)
3526{
a9179499 3527 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3528 u32 ar;
3529
c6ad1153 3530 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3531 *var = vmx->rmode.segs[seg];
a9179499 3532 if (seg == VCPU_SREG_TR
2fb92db1 3533 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3534 return;
1390a28b
AK		 3535 var->base = vmx_read_guest_seg_base(vmx, seg);
3536 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3537 return;
a9179499 3538 }
2fb92db1
AK		 3539 var->base = vmx_read_guest_seg_base(vmx, seg);
3540 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3541 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3542 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3543 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3544 var->type = ar & 15;
3545 var->s = (ar >> 4) & 1;
3546 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3547 /*
3548 * Some userspaces do not preserve unusable property. Since usable
3549 * segment has to be present according to VMX spec we can use present
3550 * property to amend userspace bug by making unusable segment always
3551 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3552 * segment as unusable.
3553 */
3554 var->present = !var->unusable;
6aa8b732
AK		 3555 var->avl = (ar >> 12) & 1;
3556 var->l = (ar >> 13) & 1;
3557 var->db = (ar >> 14) & 1;
3558 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3559}
3560
a9179499
AK		 3561static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3562{
a9179499
AK		 3563 struct kvm_segment s;
3564
3565 if (to_vmx(vcpu)->rmode.vm86_active) {
3566 vmx_get_segment(vcpu, &s, seg);
3567 return s.base;
3568 }
2fb92db1 3569 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3570}
3571
b09408d0 3572static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3573{
b09408d0
MT		 3574 struct vcpu_vmx *vmx = to_vmx(vcpu);
3575
ae9fedc7 3576 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3577 return 0;
ae9fedc7
PB		 3578 else {
3579 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3580 return AR_DPL(ar);
69c73028 3581 }
69c73028
AK		 3582}
3583
653e3108 3584static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3585{
6aa8b732
AK		 3586 u32 ar;
3587
f0495f9b 3588 if (var->unusable || !var->present)
6aa8b732
AK		 3589 ar = 1 << 16;
3590 else {
3591 ar = var->type & 15;
3592 ar |= (var->s & 1) << 4;
3593 ar |= (var->dpl & 3) << 5;
3594 ar |= (var->present & 1) << 7;
3595 ar |= (var->avl & 1) << 12;
3596 ar |= (var->l & 1) << 13;
3597 ar |= (var->db & 1) << 14;
3598 ar |= (var->g & 1) << 15;
3599 }
653e3108
AK		 3600
3601 return ar;
3602}
3603
3604static void vmx_set_segment(struct kvm_vcpu *vcpu,
3605 struct kvm_segment *var, int seg)
3606{
7ffd92c5 3607 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3608 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3609
2fb92db1
AK		 3610 vmx_segment_cache_clear(vmx);
3611
1ecd50a9
GN		 3612 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3613 vmx->rmode.segs[seg] = *var;
3614 if (seg == VCPU_SREG_TR)
3615 vmcs_write16(sf->selector, var->selector);
3616 else if (var->s)
3617 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3618 goto out;
653e3108 3619 }
1ecd50a9 3620
653e3108
AK		 3621 vmcs_writel(sf->base, var->base);
3622 vmcs_write32(sf->limit, var->limit);
3623 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3624
3625 /*
3626 * Fix the "Accessed" bit in AR field of segment registers for older
3627 * qemu binaries.
3628 * IA32 arch specifies that at the time of processor reset the
3629 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3630 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3631 * state vmexit when "unrestricted guest" mode is turned on.
3632 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3633 * tree. Newer qemu binaries with that qemu fix would not need this
3634 * kvm hack.
3635 */
3636 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3637 var->type |= 0x1; /* Accessed */
3a624e29 3638
f924d66d 3639 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3640
3641out:
98eb2f8b 3642 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3643}
3644
6aa8b732
AK		 3645static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3646{
2fb92db1 3647 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3648
3649 *db = (ar >> 14) & 1;
3650 *l = (ar >> 13) & 1;
3651}
3652
89a27f4d 3653static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3654{
89a27f4d
GN		 3655 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3656 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3657}
3658
89a27f4d 3659static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3660{
89a27f4d
GN		 3661 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3662 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3663}
3664
89a27f4d 3665static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3666{
89a27f4d
GN		 3667 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3668 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3669}
3670
89a27f4d 3671static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3672{
89a27f4d
GN		 3673 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3674 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3675}
3676
648dfaa7
MG		 3677static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3678{
3679 struct kvm_segment var;
3680 u32 ar;
3681
3682 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3683 var.dpl = 0x3;
0647f4aa
GN		 3684 if (seg == VCPU_SREG_CS)
3685 var.type = 0x3;
648dfaa7
MG		 3686 ar = vmx_segment_access_rights(&var);
3687
3688 if (var.base != (var.selector << 4))
3689 return false;
89efbed0 3690 if (var.limit != 0xffff)
648dfaa7 3691 return false;
07f42f5f 3692 if (ar != 0xf3)
648dfaa7
MG		 3693 return false;
3694
3695 return true;
3696}
3697
3698static bool code_segment_valid(struct kvm_vcpu *vcpu)
3699{
3700 struct kvm_segment cs;
3701 unsigned int cs_rpl;
3702
3703 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3704 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3705
1872a3f4
AK		 3706 if (cs.unusable)
3707 return false;
648dfaa7
MG		 3708 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3709 return false;
3710 if (!cs.s)
3711 return false;
1872a3f4 3712 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3713 if (cs.dpl > cs_rpl)
3714 return false;
1872a3f4 3715 } else {
648dfaa7
MG		 3716 if (cs.dpl != cs_rpl)
3717 return false;
3718 }
3719 if (!cs.present)
3720 return false;
3721
3722 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3723 return true;
3724}
3725
3726static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3727{
3728 struct kvm_segment ss;
3729 unsigned int ss_rpl;
3730
3731 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3732 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3733
1872a3f4
AK		 3734 if (ss.unusable)
3735 return true;
3736 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3737 return false;
3738 if (!ss.s)
3739 return false;
3740 if (ss.dpl != ss_rpl) /* DPL != RPL */
3741 return false;
3742 if (!ss.present)
3743 return false;
3744
3745 return true;
3746}
3747
3748static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3749{
3750 struct kvm_segment var;
3751 unsigned int rpl;
3752
3753 vmx_get_segment(vcpu, &var, seg);
3754 rpl = var.selector & SELECTOR_RPL_MASK;
3755
1872a3f4
AK		 3756 if (var.unusable)
3757 return true;
648dfaa7
MG		 3758 if (!var.s)
3759 return false;
3760 if (!var.present)
3761 return false;
3762 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3763 if (var.dpl < rpl) /* DPL < RPL */
3764 return false;
3765 }
3766
3767 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3768 * rights flags
3769 */
3770 return true;
3771}
3772
3773static bool tr_valid(struct kvm_vcpu *vcpu)
3774{
3775 struct kvm_segment tr;
3776
3777 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3778
1872a3f4
AK		 3779 if (tr.unusable)
3780 return false;
648dfaa7
MG		 3781 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3782 return false;
1872a3f4 3783 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3784 return false;
3785 if (!tr.present)
3786 return false;
3787
3788 return true;
3789}
3790
3791static bool ldtr_valid(struct kvm_vcpu *vcpu)
3792{
3793 struct kvm_segment ldtr;
3794
3795 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3796
1872a3f4
AK		 3797 if (ldtr.unusable)
3798 return true;
648dfaa7
MG		 3799 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3800 return false;
3801 if (ldtr.type != 2)
3802 return false;
3803 if (!ldtr.present)
3804 return false;
3805
3806 return true;
3807}
3808
3809static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3810{
3811 struct kvm_segment cs, ss;
3812
3813 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3814 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3815
3816 return ((cs.selector & SELECTOR_RPL_MASK) ==
3817 (ss.selector & SELECTOR_RPL_MASK));
3818}
3819
3820/*
3821 * Check if guest state is valid. Returns true if valid, false if
3822 * not.
3823 * We assume that registers are always usable
3824 */
3825static bool guest_state_valid(struct kvm_vcpu *vcpu)
3826{
c5e97c80
GN		 3827 if (enable_unrestricted_guest)
3828 return true;
3829
648dfaa7 3830 /* real mode guest state checks */
f13882d8 3831 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3832 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3833 return false;
3834 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3835 return false;
3836 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3837 return false;
3838 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3839 return false;
3840 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3841 return false;
3842 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3843 return false;
3844 } else {
3845 /* protected mode guest state checks */
3846 if (!cs_ss_rpl_check(vcpu))
3847 return false;
3848 if (!code_segment_valid(vcpu))
3849 return false;
3850 if (!stack_segment_valid(vcpu))
3851 return false;
3852 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3853 return false;
3854 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3855 return false;
3856 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3857 return false;
3858 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3859 return false;
3860 if (!tr_valid(vcpu))
3861 return false;
3862 if (!ldtr_valid(vcpu))
3863 return false;
3864 }
3865 /* TODO:
3866 * - Add checks on RIP
3867 * - Add checks on RFLAGS
3868 */
3869
3870 return true;
3871}
3872
d77c26fc 3873static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3874{
40dcaa9f 3875 gfn_t fn;
195aefde 3876 u16 data = 0;
1f755a82 3877 int idx, r;
6aa8b732 3878
40dcaa9f 3879 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3880 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3881 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3882 if (r < 0)
10589a46 3883 goto out;
195aefde 3884 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3885 r = kvm_write_guest_page(kvm, fn++, &data,
3886 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3887 if (r < 0)
10589a46 3888 goto out;
195aefde
IE		 3889 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3890 if (r < 0)
10589a46 3891 goto out;
195aefde
IE		 3892 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3893 if (r < 0)
10589a46 3894 goto out;
195aefde 3895 data = ~0;
10589a46
MT		 3896 r = kvm_write_guest_page(kvm, fn, &data,
3897 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3898 sizeof(u8));
10589a46 3899out:
40dcaa9f 3900 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3901 return r;
6aa8b732
AK		 3902}
3903
b7ebfb05
SY		 3904static int init_rmode_identity_map(struct kvm *kvm)
3905{
f51770ed 3906 int i, idx, r = 0;
b7ebfb05
SY		 3907 pfn_t identity_map_pfn;
3908 u32 tmp;
3909
089d034e 3910 if (!enable_ept)
f51770ed 3911 return 0;
a255d479
TC		 3912
3913 /* Protect kvm->arch.ept_identity_pagetable_done. */
3914 mutex_lock(&kvm->slots_lock);
3915
f51770ed 3916 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 3917 goto out2;
a255d479 3918
b927a3ce 3919 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 3920
3921 r = alloc_identity_pagetable(kvm);
f51770ed 3922 if (r < 0)
a255d479
TC		 3923 goto out2;
3924
40dcaa9f 3925 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3926 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3927 if (r < 0)
3928 goto out;
3929 /* Set up identity-mapping pagetable for EPT in real mode */
3930 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3931 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3932 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3933 r = kvm_write_guest_page(kvm, identity_map_pfn,
3934 &tmp, i * sizeof(tmp), sizeof(tmp));
3935 if (r < 0)
3936 goto out;
3937 }
3938 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 3939
b7ebfb05 3940out:
40dcaa9f 3941 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 3942
3943out2:
3944 mutex_unlock(&kvm->slots_lock);
f51770ed 3945 return r;
b7ebfb05
SY		 3946}
3947
6aa8b732
AK		 3948static void seg_setup(int seg)
3949{
772e0318 3950 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3951 unsigned int ar;
6aa8b732
AK		 3952
3953 vmcs_write16(sf->selector, 0);
3954 vmcs_writel(sf->base, 0);
3955 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3956 ar = 0x93;
3957 if (seg == VCPU_SREG_CS)
3958 ar |= 0x08; /* code segment */
3a624e29
NK		 3959
3960 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3961}
3962
f78e0e2e
SY		 3963static int alloc_apic_access_page(struct kvm *kvm)
3964{
4484141a 3965 struct page *page;
f78e0e2e
SY		 3966 struct kvm_userspace_memory_region kvm_userspace_mem;
3967 int r = 0;
3968
79fac95e 3969 mutex_lock(&kvm->slots_lock);
c24ae0dc 3970 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 3971 goto out;
3972 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3973 kvm_userspace_mem.flags = 0;
73a6d941 3974 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 3975 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3976 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3977 if (r)
3978 goto out;
72dc67a6 3979
73a6d941 3980 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 3981 if (is_error_page(page)) {
3982 r = -EFAULT;
3983 goto out;
3984 }
3985
c24ae0dc
TC		 3986 /*
3987 * Do not pin the page in memory, so that memory hot-unplug
3988 * is able to migrate it.
3989 */
3990 put_page(page);
3991 kvm->arch.apic_access_page_done = true;
f78e0e2e 3992out:
79fac95e 3993 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3994 return r;
3995}
3996
b7ebfb05
SY		 3997static int alloc_identity_pagetable(struct kvm *kvm)
3998{
a255d479
TC		 3999 /* Called with kvm->slots_lock held. */
4000
b7ebfb05
SY		 4001 struct kvm_userspace_memory_region kvm_userspace_mem;
4002 int r = 0;
4003
a255d479
TC		 4004 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4005
b7ebfb05
SY		 4006 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4007 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4008 kvm_userspace_mem.guest_phys_addr =
4009 kvm->arch.ept_identity_map_addr;
b7ebfb05 4010 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4011 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4012
b7ebfb05
SY		 4013 return r;
4014}
4015
2384d2b3
SY		 4016static void allocate_vpid(struct vcpu_vmx *vmx)
4017{
4018 int vpid;
4019
4020 vmx->vpid = 0;
919818ab 4021 if (!enable_vpid)
2384d2b3
SY		 4022 return;
4023 spin_lock(&vmx_vpid_lock);
4024 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4025 if (vpid < VMX_NR_VPIDS) {
4026 vmx->vpid = vpid;
4027 __set_bit(vpid, vmx_vpid_bitmap);
4028 }
4029 spin_unlock(&vmx_vpid_lock);
4030}
4031
cdbecfc3
LJ		 4032static void free_vpid(struct vcpu_vmx *vmx)
4033{
4034 if (!enable_vpid)
4035 return;
4036 spin_lock(&vmx_vpid_lock);
4037 if (vmx->vpid != 0)
4038 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4039 spin_unlock(&vmx_vpid_lock);
4040}
4041
8d14695f
YZ		 4042#define MSR_TYPE_R 1
4043#define MSR_TYPE_W 2
4044static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4045 u32 msr, int type)
25c5f225 4046{
3e7c73e9 4047 int f = sizeof(unsigned long);
25c5f225
SY		 4048
4049 if (!cpu_has_vmx_msr_bitmap())
4050 return;
4051
4052 /*
4053 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4054 * have the write-low and read-high bitmap offsets the wrong way round.
4055 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4056 */
25c5f225 4057 if (msr <= 0x1fff) {
8d14695f
YZ		 4058 if (type & MSR_TYPE_R)
4059 /* read-low */
4060 __clear_bit(msr, msr_bitmap + 0x000 / f);
4061
4062 if (type & MSR_TYPE_W)
4063 /* write-low */
4064 __clear_bit(msr, msr_bitmap + 0x800 / f);
4065
25c5f225
SY		 4066 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4067 msr &= 0x1fff;
8d14695f
YZ		 4068 if (type & MSR_TYPE_R)
4069 /* read-high */
4070 __clear_bit(msr, msr_bitmap + 0x400 / f);
4071
4072 if (type & MSR_TYPE_W)
4073 /* write-high */
4074 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4075
4076 }
4077}
4078
4079static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4080 u32 msr, int type)
4081{
4082 int f = sizeof(unsigned long);
4083
4084 if (!cpu_has_vmx_msr_bitmap())
4085 return;
4086
4087 /*
4088 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4089 * have the write-low and read-high bitmap offsets the wrong way round.
4090 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4091 */
4092 if (msr <= 0x1fff) {
4093 if (type & MSR_TYPE_R)
4094 /* read-low */
4095 __set_bit(msr, msr_bitmap + 0x000 / f);
4096
4097 if (type & MSR_TYPE_W)
4098 /* write-low */
4099 __set_bit(msr, msr_bitmap + 0x800 / f);
4100
4101 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4102 msr &= 0x1fff;
4103 if (type & MSR_TYPE_R)
4104 /* read-high */
4105 __set_bit(msr, msr_bitmap + 0x400 / f);
4106
4107 if (type & MSR_TYPE_W)
4108 /* write-high */
4109 __set_bit(msr, msr_bitmap + 0xc00 / f);
4110
25c5f225 4111 }
25c5f225
SY		 4112}
4113
5897297b
AK		 4114static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4115{
4116 if (!longmode_only)
8d14695f
YZ		 4117 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4118 msr, MSR_TYPE_R | MSR_TYPE_W);
4119 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4120 msr, MSR_TYPE_R | MSR_TYPE_W);
4121}
4122
4123static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4124{
4125 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4126 msr, MSR_TYPE_R);
4127 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4128 msr, MSR_TYPE_R);
4129}
4130
4131static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4132{
4133 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4134 msr, MSR_TYPE_R);
4135 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4136 msr, MSR_TYPE_R);
4137}
4138
4139static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4140{
4141 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4142 msr, MSR_TYPE_W);
4143 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4144 msr, MSR_TYPE_W);
5897297b
AK		 4145}
4146
01e439be
YZ		 4147static int vmx_vm_has_apicv(struct kvm *kvm)
4148{
4149 return enable_apicv && irqchip_in_kernel(kvm);
4150}
4151
a20ed54d
YZ		 4152/*
4153 * Send interrupt to vcpu via posted interrupt way.
4154 * 1. If target vcpu is running(non-root mode), send posted interrupt
4155 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4156 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4157 * interrupt from PIR in next vmentry.
4158 */
4159static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4160{
4161 struct vcpu_vmx *vmx = to_vmx(vcpu);
4162 int r;
4163
4164 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4165 return;
4166
4167 r = pi_test_and_set_on(&vmx->pi_desc);
4168 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4169#ifdef CONFIG_SMP
a20ed54d
YZ		 4170 if (!r && (vcpu->mode == IN_GUEST_MODE))
4171 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4172 POSTED_INTR_VECTOR);
4173 else
6ffbbbba 4174#endif
a20ed54d
YZ		 4175 kvm_vcpu_kick(vcpu);
4176}
4177
4178static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4179{
4180 struct vcpu_vmx *vmx = to_vmx(vcpu);
4181
4182 if (!pi_test_and_clear_on(&vmx->pi_desc))
4183 return;
4184
4185 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4186}
4187
4188static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4189{
4190 return;
4191}
4192
a3a8ff8e
NHE		 4193/*
4194 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4195 * will not change in the lifetime of the guest.
4196 * Note that host-state that does change is set elsewhere. E.g., host-state
4197 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4198 */
a547c6db 4199static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4200{
4201 u32 low32, high32;
4202 unsigned long tmpl;
4203 struct desc_ptr dt;
d974baa3 4204 unsigned long cr4;
a3a8ff8e 4205
b1a74bf8 4206 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4207 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4208
d974baa3
AL		 4209 /* Save the most likely value for this task's CR4 in the VMCS. */
4210 cr4 = read_cr4();
4211 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4212 vmx->host_state.vmcs_host_cr4 = cr4;
4213
a3a8ff8e 4214 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4215#ifdef CONFIG_X86_64
4216 /*
4217 * Load null selectors, so we can avoid reloading them in
4218 * __vmx_load_host_state(), in case userspace uses the null selectors
4219 * too (the expected case).
4220 */
4221 vmcs_write16(HOST_DS_SELECTOR, 0);
4222 vmcs_write16(HOST_ES_SELECTOR, 0);
4223#else
a3a8ff8e
NHE		 4224 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4225 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4226#endif
a3a8ff8e
NHE		 4227 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4228 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4229
4230 native_store_idt(&dt);
4231 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4232 vmx->host_idt_base = dt.address;
a3a8ff8e 4233
83287ea4 4234 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4235
4236 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4237 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4238 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4239 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4240
4241 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4242 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4243 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4244 }
4245}
4246
bf8179a0
NHE		 4247static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4248{
4249 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4250 if (enable_ept)
4251 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4252 if (is_guest_mode(&vmx->vcpu))
4253 vmx->vcpu.arch.cr4_guest_owned_bits &=
4254 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4255 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4256}
4257
01e439be
YZ		 4258static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4259{
4260 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4261
4262 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4263 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4264 return pin_based_exec_ctrl;
4265}
4266
bf8179a0
NHE		 4267static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4268{
4269 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4270
4271 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4272 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4273
bf8179a0
NHE		 4274 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4275 exec_control &= ~CPU_BASED_TPR_SHADOW;
4276#ifdef CONFIG_X86_64
4277 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4278 CPU_BASED_CR8_LOAD_EXITING;
4279#endif
4280 }
4281 if (!enable_ept)
4282 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4283 CPU_BASED_CR3_LOAD_EXITING |
4284 CPU_BASED_INVLPG_EXITING;
4285 return exec_control;
4286}
4287
4288static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4289{
4290 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4291 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4292 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4293 if (vmx->vpid == 0)
4294 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4295 if (!enable_ept) {
4296 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4297 enable_unrestricted_guest = 0;
ad756a16
MJ		 4298 /* Enable INVPCID for non-ept guests may cause performance regression. */
4299 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4300 }
4301 if (!enable_unrestricted_guest)
4302 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4303 if (!ple_gap)
4304 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4305 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4306 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4307 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4308 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4309 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4310 (handle_vmptrld).
4311 We can NOT enable shadow_vmcs here because we don't have yet
4312 a current VMCS12
4313 */
4314 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4315 return exec_control;
4316}
4317
ce88decf
XG		 4318static void ept_set_mmio_spte_mask(void)
4319{
4320 /*
4321 * EPT Misconfigurations can be generated if the value of bits 2:0
4322 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4323 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4324 * spte.
4325 */
885032b9 4326 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4327}
4328
6aa8b732
AK		 4329/*
4330 * Sets up the vmcs for emulated real mode.
4331 */
8b9cf98c 4332static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4333{
2e4ce7f5 4334#ifdef CONFIG_X86_64
6aa8b732 4335 unsigned long a;
2e4ce7f5 4336#endif
6aa8b732 4337 int i;
6aa8b732 4338
6aa8b732 4339 /* I/O */
3e7c73e9
AK		 4340 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4341 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4342
4607c2d7
AG		 4343 if (enable_shadow_vmcs) {
4344 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4345 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4346 }
25c5f225 4347 if (cpu_has_vmx_msr_bitmap())
5897297b 4348 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4349
6aa8b732
AK		 4350 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4351
6aa8b732 4352 /* Control */
01e439be 4353 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4354
bf8179a0 4355 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4356
83ff3b9d 4357 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4358 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4359 vmx_secondary_exec_control(vmx));
83ff3b9d 4360 }
f78e0e2e 4361
01e439be 4362 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4363 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4364 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4365 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4366 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4367
4368 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4369
4370 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4371 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4372 }
4373
4b8d54f9
ZE		 4374 if (ple_gap) {
4375 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4376 vmx->ple_window = ple_window;
4377 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4378 }
4379
c3707958
XG		 4380 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4381 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4382 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4383
9581d442
AK		 4384 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4385 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4386 vmx_set_constant_host_state(vmx);
05b3e0c2 4387#ifdef CONFIG_X86_64
6aa8b732
AK		 4388 rdmsrl(MSR_FS_BASE, a);
4389 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4390 rdmsrl(MSR_GS_BASE, a);
4391 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4392#else
4393 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4394 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4395#endif
4396
2cc51560
ED		 4397 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4398 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4399 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4400 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4401 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4402
468d472f 4403 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4404 u32 msr_low, msr_high;
4405 u64 host_pat;
468d472f
SY		 4406 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4407 host_pat = msr_low | ((u64) msr_high << 32);
4408 /* Write the default value follow host pat */
4409 vmcs_write64(GUEST_IA32_PAT, host_pat);
4410 /* Keep arch.pat sync with GUEST_IA32_PAT */
4411 vmx->vcpu.arch.pat = host_pat;
4412 }
4413
03916db9 4414 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4415 u32 index = vmx_msr_index[i];
4416 u32 data_low, data_high;
a2fa3e9f 4417 int j = vmx->nmsrs;
6aa8b732
AK		 4418
4419 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4420 continue;
432bd6cb
AK		 4421 if (wrmsr_safe(index, data_low, data_high) < 0)
4422 continue;
26bb0981
AK		 4423 vmx->guest_msrs[j].index = i;
4424 vmx->guest_msrs[j].data = 0;
d5696725 4425 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4426 ++vmx->nmsrs;
6aa8b732 4427 }
6aa8b732 4428
2961e876
GN		 4429
4430 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4431
4432 /* 22.2.1, 20.8.1 */
2961e876 4433 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4434
e00c8cf2 4435 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4436 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4437
4438 return 0;
4439}
4440
57f252f2 4441static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4442{
4443 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4444 struct msr_data apic_base_msr;
e00c8cf2 4445
7ffd92c5 4446 vmx->rmode.vm86_active = 0;
e00c8cf2 4447
3b86cd99
JK		 4448 vmx->soft_vnmi_blocked = 0;
4449
ad312c7c 4450 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4451 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4452 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4453 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4454 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4455 apic_base_msr.host_initiated = true;
4456 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4457
2fb92db1
AK		 4458 vmx_segment_cache_clear(vmx);
4459
5706be0d 4460 seg_setup(VCPU_SREG_CS);
66450a21 4461 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4462 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4463
4464 seg_setup(VCPU_SREG_DS);
4465 seg_setup(VCPU_SREG_ES);
4466 seg_setup(VCPU_SREG_FS);
4467 seg_setup(VCPU_SREG_GS);
4468 seg_setup(VCPU_SREG_SS);
4469
4470 vmcs_write16(GUEST_TR_SELECTOR, 0);
4471 vmcs_writel(GUEST_TR_BASE, 0);
4472 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4473 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4474
4475 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4476 vmcs_writel(GUEST_LDTR_BASE, 0);
4477 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4478 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4479
4480 vmcs_write32(GUEST_SYSENTER_CS, 0);
4481 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4482 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4483
4484 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4485 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4486
e00c8cf2
AK		 4487 vmcs_writel(GUEST_GDTR_BASE, 0);
4488 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4489
4490 vmcs_writel(GUEST_IDTR_BASE, 0);
4491 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4492
443381a8 4493 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4494 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4495 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4496
e00c8cf2
AK		 4497 /* Special registers */
4498 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4499
4500 setup_msrs(vmx);
4501
6aa8b732
AK		 4502 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4503
f78e0e2e
SY		 4504 if (cpu_has_vmx_tpr_shadow()) {
4505 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4506 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4507 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4508 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4509 vmcs_write32(TPR_THRESHOLD, 0);
4510 }
4511
a73896cb 4512 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4513
01e439be
YZ		 4514 if (vmx_vm_has_apicv(vcpu->kvm))
4515 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4516
2384d2b3
SY		 4517 if (vmx->vpid != 0)
4518 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4519
fa40052c 4520 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4521 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4522 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4523 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4524 vmx_fpu_activate(&vmx->vcpu);
4525 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4526
b9d762fa 4527 vpid_sync_context(vmx);
6aa8b732
AK		 4528}
4529
b6f1250e
NHE		 4530/*
4531 * In nested virtualization, check if L1 asked to exit on external interrupts.
4532 * For most existing hypervisors, this will always return true.
4533 */
4534static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4535{
4536 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4537 PIN_BASED_EXT_INTR_MASK;
4538}
4539
77b0f5d6
BD		 4540/*
4541 * In nested virtualization, check if L1 has set
4542 * VM_EXIT_ACK_INTR_ON_EXIT
4543 */
4544static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4545{
4546 return get_vmcs12(vcpu)->vm_exit_controls &
4547 VM_EXIT_ACK_INTR_ON_EXIT;
4548}
4549
ea8ceb83
JK		 4550static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4551{
4552 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4553 PIN_BASED_NMI_EXITING;
4554}
4555
c9a7953f 4556static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4557{
4558 u32 cpu_based_vm_exec_control;
730dca42 4559
3b86cd99
JK		 4560 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4561 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4562 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4563}
4564
c9a7953f 4565static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4566{
4567 u32 cpu_based_vm_exec_control;
4568
c9a7953f
JK		 4569 if (!cpu_has_virtual_nmis() ||
4570 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4571 enable_irq_window(vcpu);
4572 return;
4573 }
3b86cd99
JK		 4574
4575 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4576 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4577 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4578}
4579
66fd3f7f 4580static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4581{
9c8cba37 4582 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4583 uint32_t intr;
4584 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4585
229456fc 4586 trace_kvm_inj_virq(irq);
2714d1d3 4587
fa89a817 4588 ++vcpu->stat.irq_injections;
7ffd92c5 4589 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4590 int inc_eip = 0;
4591 if (vcpu->arch.interrupt.soft)
4592 inc_eip = vcpu->arch.event_exit_inst_len;
4593 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4594 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4595 return;
4596 }
66fd3f7f
GN		 4597 intr = irq | INTR_INFO_VALID_MASK;
4598 if (vcpu->arch.interrupt.soft) {
4599 intr |= INTR_TYPE_SOFT_INTR;
4600 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4601 vmx->vcpu.arch.event_exit_inst_len);
4602 } else
4603 intr |= INTR_TYPE_EXT_INTR;
4604 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4605}
4606
f08864b4
SY		 4607static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4608{
66a5a347
JK		 4609 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610
0b6ac343
NHE		 4611 if (is_guest_mode(vcpu))
4612 return;
4613
3b86cd99
JK		 4614 if (!cpu_has_virtual_nmis()) {
4615 /*
4616 * Tracking the NMI-blocked state in software is built upon
4617 * finding the next open IRQ window. This, in turn, depends on
4618 * well-behaving guests: They have to keep IRQs disabled at
4619 * least as long as the NMI handler runs. Otherwise we may
4620 * cause NMI nesting, maybe breaking the guest. But as this is
4621 * highly unlikely, we can live with the residual risk.
4622 */
4623 vmx->soft_vnmi_blocked = 1;
4624 vmx->vnmi_blocked_time = 0;
4625 }
4626
487b391d 4627 ++vcpu->stat.nmi_injections;
9d58b931 4628 vmx->nmi_known_unmasked = false;
7ffd92c5 4629 if (vmx->rmode.vm86_active) {
71f9833b 4630 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4631 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4632 return;
4633 }
f08864b4
SY		 4634 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4635 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4636}
4637
3cfc3092
JK		 4638static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4639{
4640 if (!cpu_has_virtual_nmis())
4641 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4642 if (to_vmx(vcpu)->nmi_known_unmasked)
4643 return false;
c332c83a 4644 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4645}
4646
4647static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4648{
4649 struct vcpu_vmx *vmx = to_vmx(vcpu);
4650
4651 if (!cpu_has_virtual_nmis()) {
4652 if (vmx->soft_vnmi_blocked != masked) {
4653 vmx->soft_vnmi_blocked = masked;
4654 vmx->vnmi_blocked_time = 0;
4655 }
4656 } else {
9d58b931 4657 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4658 if (masked)
4659 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4660 GUEST_INTR_STATE_NMI);
4661 else
4662 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4663 GUEST_INTR_STATE_NMI);
4664 }
4665}
4666
2505dc9f
JK		 4667static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4668{
b6b8a145
JK		 4669 if (to_vmx(vcpu)->nested.nested_run_pending)
4670 return 0;
ea8ceb83 4671
2505dc9f
JK		 4672 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4673 return 0;
4674
4675 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4676 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4677 | GUEST_INTR_STATE_NMI));
4678}
4679
78646121
GN		 4680static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4681{
b6b8a145
JK		 4682 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4683 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4684 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4685 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4686}
4687
cbc94022
IE		 4688static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4689{
4690 int ret;
4691 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4692 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4693 .guest_phys_addr = addr,
4694 .memory_size = PAGE_SIZE * 3,
4695 .flags = 0,
4696 };
4697
47ae31e2 4698 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4699 if (ret)
4700 return ret;
bfc6d222 4701 kvm->arch.tss_addr = addr;
1f755a82 4702 return init_rmode_tss(kvm);
cbc94022
IE		 4703}
4704
0ca1b4f4 4705static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4706{
77ab6db0 4707 switch (vec) {
77ab6db0 4708 case BP_VECTOR:
c573cd22
JK		 4709 /*
4710 * Update instruction length as we may reinject the exception
4711 * from user space while in guest debugging mode.
4712 */
4713 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4714 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4715 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4716 return false;
4717 /* fall through */
4718 case DB_VECTOR:
4719 if (vcpu->guest_debug &
4720 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4721 return false;
d0bfb940
JK		 4722 /* fall through */
4723 case DE_VECTOR:
77ab6db0
JK		 4724 case OF_VECTOR:
4725 case BR_VECTOR:
4726 case UD_VECTOR:
4727 case DF_VECTOR:
4728 case SS_VECTOR:
4729 case GP_VECTOR:
4730 case MF_VECTOR:
0ca1b4f4
GN		 4731 return true;
4732 break;
77ab6db0 4733 }
0ca1b4f4
GN		 4734 return false;
4735}
4736
4737static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4738 int vec, u32 err_code)
4739{
4740 /*
4741 * Instruction with address size override prefix opcode 0x67
4742 * Cause the #SS fault with 0 error code in VM86 mode.
4743 */
4744 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4745 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4746 if (vcpu->arch.halt_request) {
4747 vcpu->arch.halt_request = 0;
4748 return kvm_emulate_halt(vcpu);
4749 }
4750 return 1;
4751 }
4752 return 0;
4753 }
4754
4755 /*
4756 * Forward all other exceptions that are valid in real mode.
4757 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4758 * the required debugging infrastructure rework.
4759 */
4760 kvm_queue_exception(vcpu, vec);
4761 return 1;
6aa8b732
AK		 4762}
4763
a0861c02
AK		 4764/*
4765 * Trigger machine check on the host. We assume all the MSRs are already set up
4766 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4767 * We pass a fake environment to the machine check handler because we want
4768 * the guest to be always treated like user space, no matter what context
4769 * it used internally.
4770 */
4771static void kvm_machine_check(void)
4772{
4773#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4774 struct pt_regs regs = {
4775 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4776 .flags = X86_EFLAGS_IF,
4777 };
4778
4779 do_machine_check(&regs, 0);
4780#endif
4781}
4782
851ba692 4783static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4784{
4785 /* already handled by vcpu_run */
4786 return 1;
4787}
4788
851ba692 4789static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4790{
1155f76a 4791 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4792 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4793 u32 intr_info, ex_no, error_code;
42dbaa5a 4794 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4795 u32 vect_info;
4796 enum emulation_result er;
4797
1155f76a 4798 vect_info = vmx->idt_vectoring_info;
88786475 4799 intr_info = vmx->exit_intr_info;
6aa8b732 4800
a0861c02 4801 if (is_machine_check(intr_info))
851ba692 4802 return handle_machine_check(vcpu);
a0861c02 4803
e4a41889 4804 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4805 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4806
4807 if (is_no_device(intr_info)) {
5fd86fcf 4808 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4809 return 1;
4810 }
4811
7aa81cc0 4812 if (is_invalid_opcode(intr_info)) {
51d8b661 4813 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4814 if (er != EMULATE_DONE)
7ee5d940 4815 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4816 return 1;
4817 }
4818
6aa8b732 4819 error_code = 0;
2e11384c 4820 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4821 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4822
4823 /*
4824 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4825 * MMIO, it is better to report an internal error.
4826 * See the comments in vmx_handle_exit.
4827 */
4828 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4829 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4830 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4831 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4832 vcpu->run->internal.ndata = 2;
4833 vcpu->run->internal.data[0] = vect_info;
4834 vcpu->run->internal.data[1] = intr_info;
4835 return 0;
4836 }
4837
6aa8b732 4838 if (is_page_fault(intr_info)) {
1439442c 4839 /* EPT won't cause page fault directly */
cf3ace79 4840 BUG_ON(enable_ept);
6aa8b732 4841 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4842 trace_kvm_page_fault(cr2, error_code);
4843
3298b75c 4844 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4845 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4846 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4847 }
4848
d0bfb940 4849 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4850
4851 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4852 return handle_rmode_exception(vcpu, ex_no, error_code);
4853
42dbaa5a
JK		 4854 switch (ex_no) {
4855 case DB_VECTOR:
4856 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4857 if (!(vcpu->guest_debug &
4858 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4859 vcpu->arch.dr6 &= ~15;
6f43ed01 4860 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 4861 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4862 skip_emulated_instruction(vcpu);
4863
42dbaa5a
JK		 4864 kvm_queue_exception(vcpu, DB_VECTOR);
4865 return 1;
4866 }
4867 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4868 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4869 /* fall through */
4870 case BP_VECTOR:
c573cd22
JK		 4871 /*
4872 * Update instruction length as we may reinject #BP from
4873 * user space while in guest debugging mode. Reading it for
4874 * #DB as well causes no harm, it is not used in that case.
4875 */
4876 vmx->vcpu.arch.event_exit_inst_len =
4877 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4878 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4879 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4880 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4881 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4882 break;
4883 default:
d0bfb940
JK		 4884 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4885 kvm_run->ex.exception = ex_no;
4886 kvm_run->ex.error_code = error_code;
42dbaa5a 4887 break;
6aa8b732 4888 }
6aa8b732
AK		 4889 return 0;
4890}
4891
851ba692 4892static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4893{
1165f5fe 4894 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4895 return 1;
4896}
4897
851ba692 4898static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4899{
851ba692 4900 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4901 return 0;
4902}
6aa8b732 4903
851ba692 4904static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4905{
bfdaab09 4906 unsigned long exit_qualification;
34c33d16 4907 int size, in, string;
039576c0 4908 unsigned port;
6aa8b732 4909
bfdaab09 4910 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4911 string = (exit_qualification & 16) != 0;
cf8f70bf 4912 in = (exit_qualification & 8) != 0;
e70669ab 4913
cf8f70bf 4914 ++vcpu->stat.io_exits;
e70669ab 4915
cf8f70bf 4916 if (string || in)
51d8b661 4917 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4918
cf8f70bf
GN		 4919 port = exit_qualification >> 16;
4920 size = (exit_qualification & 7) + 1;
e93f36bc 4921 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4922
4923 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4924}
4925
102d8325
IM		 4926static void
4927vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4928{
4929 /*
4930 * Patch in the VMCALL instruction:
4931 */
4932 hypercall[0] = 0x0f;
4933 hypercall[1] = 0x01;
4934 hypercall[2] = 0xc1;
102d8325
IM		 4935}
4936
92fbc7b1
JK		 4937static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4938{
4939 unsigned long always_on = VMXON_CR0_ALWAYSON;
4940
4941 if (nested_vmx_secondary_ctls_high &
4942 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4943 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4944 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4945 return (val & always_on) == always_on;
4946}
4947
0fa06071 4948/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4949static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4950{
eeadf9e7 4951 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4952 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4953 unsigned long orig_val = val;
4954
eeadf9e7
NHE		 4955 /*
4956 * We get here when L2 changed cr0 in a way that did not change
4957 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4958 * but did change L0 shadowed bits. So we first calculate the
4959 * effective cr0 value that L1 would like to write into the
4960 * hardware. It consists of the L2-owned bits from the new
4961 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4962 */
1a0d74e6
JK		 4963 val = (val & ~vmcs12->cr0_guest_host_mask) |
4964 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4965
92fbc7b1 4966 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4967 return 1;
1a0d74e6
JK		 4968
4969 if (kvm_set_cr0(vcpu, val))
4970 return 1;
4971 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4972 return 0;
1a0d74e6
JK		 4973 } else {
4974 if (to_vmx(vcpu)->nested.vmxon &&
4975 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4976 return 1;
eeadf9e7 4977 return kvm_set_cr0(vcpu, val);
1a0d74e6 4978 }
eeadf9e7
NHE		 4979}
4980
4981static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4982{
4983 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4984 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4985 unsigned long orig_val = val;
4986
4987 /* analogously to handle_set_cr0 */
4988 val = (val & ~vmcs12->cr4_guest_host_mask) |
4989 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4990 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4991 return 1;
1a0d74e6 4992 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4993 return 0;
4994 } else
4995 return kvm_set_cr4(vcpu, val);
4996}
4997
4998/* called to set cr0 as approriate for clts instruction exit. */
4999static void handle_clts(struct kvm_vcpu *vcpu)
5000{
5001 if (is_guest_mode(vcpu)) {
5002 /*
5003 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5004 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5005 * just pretend it's off (also in arch.cr0 for fpu_activate).
5006 */
5007 vmcs_writel(CR0_READ_SHADOW,
5008 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5009 vcpu->arch.cr0 &= ~X86_CR0_TS;
5010 } else
5011 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5012}
5013
851ba692 5014static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5015{
229456fc 5016 unsigned long exit_qualification, val;
6aa8b732
AK		 5017 int cr;
5018 int reg;
49a9b07e 5019 int err;
6aa8b732 5020
bfdaab09 5021 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5022 cr = exit_qualification & 15;
5023 reg = (exit_qualification >> 8) & 15;
5024 switch ((exit_qualification >> 4) & 3) {
5025 case 0: /* mov to cr */
1e32c079 5026 val = kvm_register_readl(vcpu, reg);
229456fc 5027 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5028 switch (cr) {
5029 case 0:
eeadf9e7 5030 err = handle_set_cr0(vcpu, val);
db8fcefa 5031 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5032 return 1;
5033 case 3:
2390218b 5034 err = kvm_set_cr3(vcpu, val);
db8fcefa 5035 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5036 return 1;
5037 case 4:
eeadf9e7 5038 err = handle_set_cr4(vcpu, val);
db8fcefa 5039 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5040 return 1;
0a5fff19
GN		 5041 case 8: {
5042 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5043 u8 cr8 = (u8)val;
eea1cff9 5044 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5045 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5046 if (irqchip_in_kernel(vcpu->kvm))
5047 return 1;
5048 if (cr8_prev <= cr8)
5049 return 1;
851ba692 5050 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5051 return 0;
5052 }
4b8073e4 5053 }
6aa8b732 5054 break;
25c4c276 5055 case 2: /* clts */
eeadf9e7 5056 handle_clts(vcpu);
4d4ec087 5057 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5058 skip_emulated_instruction(vcpu);
6b52d186 5059 vmx_fpu_activate(vcpu);
25c4c276 5060 return 1;
6aa8b732
AK		 5061 case 1: /*mov from cr*/
5062 switch (cr) {
5063 case 3:
9f8fe504
AK		 5064 val = kvm_read_cr3(vcpu);
5065 kvm_register_write(vcpu, reg, val);
5066 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5067 skip_emulated_instruction(vcpu);
5068 return 1;
5069 case 8:
229456fc
MT		 5070 val = kvm_get_cr8(vcpu);
5071 kvm_register_write(vcpu, reg, val);
5072 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5073 skip_emulated_instruction(vcpu);
5074 return 1;
5075 }
5076 break;
5077 case 3: /* lmsw */
a1f83a74 5078 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5079 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5080 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5081
5082 skip_emulated_instruction(vcpu);
5083 return 1;
5084 default:
5085 break;
5086 }
851ba692 5087 vcpu->run->exit_reason = 0;
a737f256 5088 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5089 (int)(exit_qualification >> 4) & 3, cr);
5090 return 0;
5091}
5092
851ba692 5093static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5094{
bfdaab09 5095 unsigned long exit_qualification;
16f8a6f9
NA		 5096 int dr, dr7, reg;
5097
5098 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5099 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5100
5101 /* First, if DR does not exist, trigger UD */
5102 if (!kvm_require_dr(vcpu, dr))
5103 return 1;
6aa8b732 5104
f2483415 5105 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5106 if (!kvm_require_cpl(vcpu, 0))
5107 return 1;
16f8a6f9
NA		 5108 dr7 = vmcs_readl(GUEST_DR7);
5109 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5110 /*
5111 * As the vm-exit takes precedence over the debug trap, we
5112 * need to emulate the latter, either for the host or the
5113 * guest debugging itself.
5114 */
5115 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5116 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5117 vcpu->run->debug.arch.dr7 = dr7;
851ba692 5118 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5119 vmcs_readl(GUEST_CS_BASE) +
5120 vmcs_readl(GUEST_RIP);
851ba692
AK		 5121 vcpu->run->debug.arch.exception = DB_VECTOR;
5122 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5123 return 0;
5124 } else {
6f43ed01 5125 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5126 kvm_queue_exception(vcpu, DB_VECTOR);
5127 return 1;
5128 }
5129 }
5130
81908bf4
PB		 5131 if (vcpu->guest_debug == 0) {
5132 u32 cpu_based_vm_exec_control;
5133
5134 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5135 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5136 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5137
5138 /*
5139 * No more DR vmexits; force a reload of the debug registers
5140 * and reenter on this instruction. The next vmexit will
5141 * retrieve the full state of the debug registers.
5142 */
5143 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5144 return 1;
5145 }
5146
42dbaa5a
JK		 5147 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5148 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5149 unsigned long val;
4c4d563b
JK		 5150
5151 if (kvm_get_dr(vcpu, dr, &val))
5152 return 1;
5153 kvm_register_write(vcpu, reg, val);
020df079 5154 } else
5777392e 5155 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5156 return 1;
5157
6aa8b732
AK		 5158 skip_emulated_instruction(vcpu);
5159 return 1;
5160}
5161
73aaf249
JK		 5162static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5163{
5164 return vcpu->arch.dr6;
5165}
5166
5167static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5168{
5169}
5170
81908bf4
PB		 5171static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5172{
5173 u32 cpu_based_vm_exec_control;
5174
5175 get_debugreg(vcpu->arch.db[0], 0);
5176 get_debugreg(vcpu->arch.db[1], 1);
5177 get_debugreg(vcpu->arch.db[2], 2);
5178 get_debugreg(vcpu->arch.db[3], 3);
5179 get_debugreg(vcpu->arch.dr6, 6);
5180 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5181
5182 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5183
5184 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5185 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5186 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5187}
5188
020df079
GN		 5189static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5190{
5191 vmcs_writel(GUEST_DR7, val);
5192}
5193
851ba692 5194static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5195{
06465c5a
AK		 5196 kvm_emulate_cpuid(vcpu);
5197 return 1;
6aa8b732
AK		 5198}
5199
851ba692 5200static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5201{
ad312c7c 5202 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5203 u64 data;
5204
5205 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5206 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5207 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5208 return 1;
5209 }
5210
229456fc 5211 trace_kvm_msr_read(ecx, data);
2714d1d3 5212
6aa8b732 5213 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5214 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5215 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5216 skip_emulated_instruction(vcpu);
5217 return 1;
5218}
5219
851ba692 5220static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5221{
8fe8ab46 5222 struct msr_data msr;
ad312c7c
ZX		 5223 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5224 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5225 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5226
8fe8ab46
WA		 5227 msr.data = data;
5228 msr.index = ecx;
5229 msr.host_initiated = false;
854e8bb1 5230 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5231 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5232 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5233 return 1;
5234 }
5235
59200273 5236 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5237 skip_emulated_instruction(vcpu);
5238 return 1;
5239}
5240
851ba692 5241static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5242{
3842d135 5243 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5244 return 1;
5245}
5246
851ba692 5247static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5248{
85f455f7
ED		 5249 u32 cpu_based_vm_exec_control;
5250
5251 /* clear pending irq */
5252 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5253 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5254 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5255
3842d135
AK		 5256 kvm_make_request(KVM_REQ_EVENT, vcpu);
5257
a26bf12a 5258 ++vcpu->stat.irq_window_exits;
2714d1d3 5259
c1150d8c
DL		 5260 /*
5261 * If the user space waits to inject interrupts, exit as soon as
5262 * possible
5263 */
8061823a 5264 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5265 vcpu->run->request_interrupt_window &&
8061823a 5266 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5267 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5268 return 0;
5269 }
6aa8b732
AK		 5270 return 1;
5271}
5272
851ba692 5273static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5274{
5275 skip_emulated_instruction(vcpu);
d3bef15f 5276 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5277}
5278
851ba692 5279static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5280{
510043da 5281 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5282 kvm_emulate_hypercall(vcpu);
5283 return 1;
c21415e8
IM		 5284}
5285
ec25d5e6
GN		 5286static int handle_invd(struct kvm_vcpu *vcpu)
5287{
51d8b661 5288 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5289}
5290
851ba692 5291static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5292{
f9c617f6 5293 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5294
5295 kvm_mmu_invlpg(vcpu, exit_qualification);
5296 skip_emulated_instruction(vcpu);
5297 return 1;
5298}
5299
fee84b07
AK		 5300static int handle_rdpmc(struct kvm_vcpu *vcpu)
5301{
5302 int err;
5303
5304 err = kvm_rdpmc(vcpu);
5305 kvm_complete_insn_gp(vcpu, err);
5306
5307 return 1;
5308}
5309
851ba692 5310static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5311{
5312 skip_emulated_instruction(vcpu);
f5f48ee1 5313 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5314 return 1;
5315}
5316
2acf923e
DC		 5317static int handle_xsetbv(struct kvm_vcpu *vcpu)
5318{
5319 u64 new_bv = kvm_read_edx_eax(vcpu);
5320 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5321
5322 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5323 skip_emulated_instruction(vcpu);
5324 return 1;
5325}
5326
851ba692 5327static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5328{
58fbbf26
KT		 5329 if (likely(fasteoi)) {
5330 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5331 int access_type, offset;
5332
5333 access_type = exit_qualification & APIC_ACCESS_TYPE;
5334 offset = exit_qualification & APIC_ACCESS_OFFSET;
5335 /*
5336 * Sane guest uses MOV to write EOI, with written value
5337 * not cared. So make a short-circuit here by avoiding
5338 * heavy instruction emulation.
5339 */
5340 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5341 (offset == APIC_EOI)) {
5342 kvm_lapic_set_eoi(vcpu);
5343 skip_emulated_instruction(vcpu);
5344 return 1;
5345 }
5346 }
51d8b661 5347 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5348}
5349
c7c9c56c
YZ		 5350static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5351{
5352 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5353 int vector = exit_qualification & 0xff;
5354
5355 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5356 kvm_apic_set_eoi_accelerated(vcpu, vector);
5357 return 1;
5358}
5359
83d4c286
YZ		 5360static int handle_apic_write(struct kvm_vcpu *vcpu)
5361{
5362 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5363 u32 offset = exit_qualification & 0xfff;
5364
5365 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5366 kvm_apic_write_nodecode(vcpu, offset);
5367 return 1;
5368}
5369
851ba692 5370static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5371{
60637aac 5372 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5373 unsigned long exit_qualification;
e269fb21
JK		 5374 bool has_error_code = false;
5375 u32 error_code = 0;
37817f29 5376 u16 tss_selector;
7f3d35fd 5377 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5378
5379 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5380 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5381 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5382
5383 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5384
5385 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5386 if (reason == TASK_SWITCH_GATE && idt_v) {
5387 switch (type) {
5388 case INTR_TYPE_NMI_INTR:
5389 vcpu->arch.nmi_injected = false;
654f06fc 5390 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5391 break;
5392 case INTR_TYPE_EXT_INTR:
66fd3f7f 5393 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5394 kvm_clear_interrupt_queue(vcpu);
5395 break;
5396 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5397 if (vmx->idt_vectoring_info &
5398 VECTORING_INFO_DELIVER_CODE_MASK) {
5399 has_error_code = true;
5400 error_code =
5401 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5402 }
5403 /* fall through */
64a7ec06
GN		 5404 case INTR_TYPE_SOFT_EXCEPTION:
5405 kvm_clear_exception_queue(vcpu);
5406 break;
5407 default:
5408 break;
5409 }
60637aac 5410 }
37817f29
IE		 5411 tss_selector = exit_qualification;
5412
64a7ec06
GN		 5413 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5414 type != INTR_TYPE_EXT_INTR &&
5415 type != INTR_TYPE_NMI_INTR))
5416 skip_emulated_instruction(vcpu);
5417
7f3d35fd
KW		 5418 if (kvm_task_switch(vcpu, tss_selector,
5419 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5420 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5421 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5422 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5423 vcpu->run->internal.ndata = 0;
42dbaa5a 5424 return 0;
acb54517 5425 }
42dbaa5a
JK		 5426
5427 /* clear all local breakpoint enable flags */
0e8a0996 5428 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
42dbaa5a
JK		 5429
5430 /*
5431 * TODO: What about debug traps on tss switch?
5432 * Are we supposed to inject them and update dr6?
5433 */
5434
5435 return 1;
37817f29
IE		 5436}
5437
851ba692 5438static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5439{
f9c617f6 5440 unsigned long exit_qualification;
1439442c 5441 gpa_t gpa;
4f5982a5 5442 u32 error_code;
1439442c 5443 int gla_validity;
1439442c 5444
f9c617f6 5445 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5446
1439442c
SY		 5447 gla_validity = (exit_qualification >> 7) & 0x3;
5448 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5449 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5450 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5451 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5452 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5453 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5454 (long unsigned int)exit_qualification);
851ba692
AK		 5455 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5456 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5457 return 0;
1439442c
SY		 5458 }
5459
0be9c7a8
GN		 5460 /*
5461 * EPT violation happened while executing iret from NMI,
5462 * "blocked by NMI" bit has to be set before next VM entry.
5463 * There are errata that may cause this bit to not be set:
5464 * AAK134, BY25.
5465 */
bcd1c294
GN		 5466 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5467 cpu_has_virtual_nmis() &&
5468 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5469 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5470
1439442c 5471 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5472 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5473
5474 /* It is a write fault? */
5475 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5476 /* It is a fetch fault? */
5477 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5478 /* ept page table is present? */
5479 error_code |= (exit_qualification >> 3) & 0x1;
5480
25d92081
YZ		 5481 vcpu->arch.exit_qualification = exit_qualification;
5482
4f5982a5 5483 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5484}
5485
68f89400
MT		 5486static u64 ept_rsvd_mask(u64 spte, int level)
5487{
5488 int i;
5489 u64 mask = 0;
5490
5491 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5492 mask |= (1ULL << i);
5493
a32e8459 5494 if (level == 4)
68f89400
MT		 5495 /* bits 7:3 reserved */
5496 mask |= 0xf8;
a32e8459
WL		 5497 else if (spte & (1ULL << 7))
5498 /*
5499 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5500 * level == 1 if the hypervisor is using the ignored bit 7.
5501 */
5502 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5503 else if (level > 1)
5504 /* bits 6:3 reserved */
5505 mask |= 0x78;
68f89400
MT		 5506
5507 return mask;
5508}
5509
5510static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5511 int level)
5512{
5513 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5514
5515 /* 010b (write-only) */
5516 WARN_ON((spte & 0x7) == 0x2);
5517
5518 /* 110b (write/execute) */
5519 WARN_ON((spte & 0x7) == 0x6);
5520
5521 /* 100b (execute-only) and value not supported by logical processor */
5522 if (!cpu_has_vmx_ept_execute_only())
5523 WARN_ON((spte & 0x7) == 0x4);
5524
5525 /* not 000b */
5526 if ((spte & 0x7)) {
5527 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5528
5529 if (rsvd_bits != 0) {
5530 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5531 __func__, rsvd_bits);
5532 WARN_ON(1);
5533 }
5534
a32e8459
WL		 5535 /* bits 5:3 are _not_ reserved for large page or leaf page */
5536 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5537 u64 ept_mem_type = (spte & 0x38) >> 3;
5538
5539 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5540 ept_mem_type == 7) {
5541 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5542 __func__, ept_mem_type);
5543 WARN_ON(1);
5544 }
5545 }
5546 }
5547}
5548
851ba692 5549static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5550{
5551 u64 sptes[4];
ce88decf 5552 int nr_sptes, i, ret;
68f89400
MT		 5553 gpa_t gpa;
5554
5555 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5556 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5557 skip_emulated_instruction(vcpu);
5558 return 1;
5559 }
68f89400 5560
ce88decf 5561 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5562 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5563 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5564 EMULATE_DONE;
f8f55942
XG		 5565
5566 if (unlikely(ret == RET_MMIO_PF_INVALID))
5567 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5568
b37fbea6 5569 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5570 return 1;
5571
5572 /* It is the real ept misconfig */
68f89400
MT		 5573 printk(KERN_ERR "EPT: Misconfiguration.\n");
5574 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5575
5576 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5577
5578 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5579 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5580
851ba692
AK		 5581 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5582 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5583
5584 return 0;
5585}
5586
851ba692 5587static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5588{
5589 u32 cpu_based_vm_exec_control;
5590
5591 /* clear pending NMI */
5592 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5593 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5594 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5595 ++vcpu->stat.nmi_window_exits;
3842d135 5596 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5597
5598 return 1;
5599}
5600
80ced186 5601static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5602{
8b3079a5
AK		 5603 struct vcpu_vmx *vmx = to_vmx(vcpu);
5604 enum emulation_result err = EMULATE_DONE;
80ced186 5605 int ret = 1;
49e9d557
AK		 5606 u32 cpu_exec_ctrl;
5607 bool intr_window_requested;
b8405c18 5608 unsigned count = 130;
49e9d557
AK		 5609
5610 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5611 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5612
98eb2f8b 5613 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5614 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5615 return handle_interrupt_window(&vmx->vcpu);
5616
de87dcdd
AK		 5617 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5618 return 1;
5619
991eebf9 5620 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5621
ac0a48c3 5622 if (err == EMULATE_USER_EXIT) {
94452b9e 5623 ++vcpu->stat.mmio_exits;
80ced186
MG		 5624 ret = 0;
5625 goto out;
5626 }
1d5a4d9b 5627
de5f70e0
AK		 5628 if (err != EMULATE_DONE) {
5629 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5630 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5631 vcpu->run->internal.ndata = 0;
6d77dbfc 5632 return 0;
de5f70e0 5633 }
ea953ef0 5634
8d76c49e
GN		 5635 if (vcpu->arch.halt_request) {
5636 vcpu->arch.halt_request = 0;
5637 ret = kvm_emulate_halt(vcpu);
5638 goto out;
5639 }
5640
ea953ef0 5641 if (signal_pending(current))
80ced186 5642 goto out;
ea953ef0
MG		 5643 if (need_resched())
5644 schedule();
5645 }
5646
80ced186
MG		 5647out:
5648 return ret;
ea953ef0
MG		 5649}
5650
b4a2d31d
RK		 5651static int __grow_ple_window(int val)
5652{
5653 if (ple_window_grow < 1)
5654 return ple_window;
5655
5656 val = min(val, ple_window_actual_max);
5657
5658 if (ple_window_grow < ple_window)
5659 val *= ple_window_grow;
5660 else
5661 val += ple_window_grow;
5662
5663 return val;
5664}
5665
5666static int __shrink_ple_window(int val, int modifier, int minimum)
5667{
5668 if (modifier < 1)
5669 return ple_window;
5670
5671 if (modifier < ple_window)
5672 val /= modifier;
5673 else
5674 val -= modifier;
5675
5676 return max(val, minimum);
5677}
5678
5679static void grow_ple_window(struct kvm_vcpu *vcpu)
5680{
5681 struct vcpu_vmx *vmx = to_vmx(vcpu);
5682 int old = vmx->ple_window;
5683
5684 vmx->ple_window = __grow_ple_window(old);
5685
5686 if (vmx->ple_window != old)
5687 vmx->ple_window_dirty = true;
7b46268d
RK		 5688
5689 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5690}
5691
5692static void shrink_ple_window(struct kvm_vcpu *vcpu)
5693{
5694 struct vcpu_vmx *vmx = to_vmx(vcpu);
5695 int old = vmx->ple_window;
5696
5697 vmx->ple_window = __shrink_ple_window(old,
5698 ple_window_shrink, ple_window);
5699
5700 if (vmx->ple_window != old)
5701 vmx->ple_window_dirty = true;
7b46268d
RK		 5702
5703 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5704}
5705
5706/*
5707 * ple_window_actual_max is computed to be one grow_ple_window() below
5708 * ple_window_max. (See __grow_ple_window for the reason.)
5709 * This prevents overflows, because ple_window_max is int.
5710 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5711 * this process.
5712 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5713 */
5714static void update_ple_window_actual_max(void)
5715{
5716 ple_window_actual_max =
5717 __shrink_ple_window(max(ple_window_max, ple_window),
5718 ple_window_grow, INT_MIN);
5719}
5720
f2c7648d
TC		 5721static __init int hardware_setup(void)
5722{
34a1cd60
TC		 5723 int r = -ENOMEM, i, msr;
5724
5725 rdmsrl_safe(MSR_EFER, &host_efer);
5726
5727 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5728 kvm_define_shared_msr(i, vmx_msr_index[i]);
5729
5730 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5731 if (!vmx_io_bitmap_a)
5732 return r;
5733
5734 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5735 if (!vmx_io_bitmap_b)
5736 goto out;
5737
5738 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5739 if (!vmx_msr_bitmap_legacy)
5740 goto out1;
5741
5742 vmx_msr_bitmap_legacy_x2apic =
5743 (unsigned long *)__get_free_page(GFP_KERNEL);
5744 if (!vmx_msr_bitmap_legacy_x2apic)
5745 goto out2;
5746
5747 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5748 if (!vmx_msr_bitmap_longmode)
5749 goto out3;
5750
5751 vmx_msr_bitmap_longmode_x2apic =
5752 (unsigned long *)__get_free_page(GFP_KERNEL);
5753 if (!vmx_msr_bitmap_longmode_x2apic)
5754 goto out4;
5755 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5756 if (!vmx_vmread_bitmap)
5757 goto out5;
5758
5759 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5760 if (!vmx_vmwrite_bitmap)
5761 goto out6;
5762
5763 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5764 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5765
5766 /*
5767 * Allow direct access to the PC debug port (it is often used for I/O
5768 * delays, but the vmexits simply slow things down).
5769 */
5770 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5771 clear_bit(0x80, vmx_io_bitmap_a);
5772
5773 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5774
5775 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5776 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
5777
5778 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
5779 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
5780 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
5781 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
5782 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
5783 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
5784 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
5785
5786 memcpy(vmx_msr_bitmap_legacy_x2apic,
5787 vmx_msr_bitmap_legacy, PAGE_SIZE);
5788 memcpy(vmx_msr_bitmap_longmode_x2apic,
5789 vmx_msr_bitmap_longmode, PAGE_SIZE);
5790
5791 if (enable_apicv) {
5792 for (msr = 0x800; msr <= 0x8ff; msr++)
5793 vmx_disable_intercept_msr_read_x2apic(msr);
5794
5795 /* According SDM, in x2apic mode, the whole id reg is used.
5796 * But in KVM, it only use the highest eight bits. Need to
5797 * intercept it */
5798 vmx_enable_intercept_msr_read_x2apic(0x802);
5799 /* TMCCT */
5800 vmx_enable_intercept_msr_read_x2apic(0x839);
5801 /* TPR */
5802 vmx_disable_intercept_msr_write_x2apic(0x808);
5803 /* EOI */
5804 vmx_disable_intercept_msr_write_x2apic(0x80b);
5805 /* SELF-IPI */
5806 vmx_disable_intercept_msr_write_x2apic(0x83f);
5807 }
5808
5809 if (enable_ept) {
5810 kvm_mmu_set_mask_ptes(0ull,
5811 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
5812 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
5813 0ull, VMX_EPT_EXECUTABLE_MASK);
5814 ept_set_mmio_spte_mask();
5815 kvm_enable_tdp();
5816 } else
5817 kvm_disable_tdp();
5818
5819 update_ple_window_actual_max();
5820
5821 if (setup_vmcs_config(&vmcs_config) < 0) {
5822 r = -EIO;
5823 goto out7;
5824 }
f2c7648d
TC		 5825
5826 if (boot_cpu_has(X86_FEATURE_NX))
5827 kvm_enable_efer_bits(EFER_NX);
5828
5829 if (!cpu_has_vmx_vpid())
5830 enable_vpid = 0;
5831 if (!cpu_has_vmx_shadow_vmcs())
5832 enable_shadow_vmcs = 0;
5833 if (enable_shadow_vmcs)
5834 init_vmcs_shadow_fields();
5835
5836 if (!cpu_has_vmx_ept() ||
5837 !cpu_has_vmx_ept_4levels()) {
5838 enable_ept = 0;
5839 enable_unrestricted_guest = 0;
5840 enable_ept_ad_bits = 0;
5841 }
5842
5843 if (!cpu_has_vmx_ept_ad_bits())
5844 enable_ept_ad_bits = 0;
5845
5846 if (!cpu_has_vmx_unrestricted_guest())
5847 enable_unrestricted_guest = 0;
5848
5849 if (!cpu_has_vmx_flexpriority()) {
5850 flexpriority_enabled = 0;
5851
5852 /*
5853 * set_apic_access_page_addr() is used to reload apic access
5854 * page upon invalidation. No need to do anything if the
5855 * processor does not have the APIC_ACCESS_ADDR VMCS field.
5856 */
5857 kvm_x86_ops->set_apic_access_page_addr = NULL;
5858 }
5859
5860 if (!cpu_has_vmx_tpr_shadow())
5861 kvm_x86_ops->update_cr8_intercept = NULL;
5862
5863 if (enable_ept && !cpu_has_vmx_ept_2m_page())
5864 kvm_disable_largepages();
5865
5866 if (!cpu_has_vmx_ple())
5867 ple_gap = 0;
5868
5869 if (!cpu_has_vmx_apicv())
5870 enable_apicv = 0;
5871
5872 if (enable_apicv)
5873 kvm_x86_ops->update_cr8_intercept = NULL;
5874 else {
5875 kvm_x86_ops->hwapic_irr_update = NULL;
5876 kvm_x86_ops->deliver_posted_interrupt = NULL;
5877 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
5878 }
5879
5880 if (nested)
5881 nested_vmx_setup_ctls_msrs();
5882
5883 return alloc_kvm_area();
34a1cd60
TC		 5884
5885out7:
5886 free_page((unsigned long)vmx_vmwrite_bitmap);
5887out6:
5888 free_page((unsigned long)vmx_vmread_bitmap);
5889out5:
5890 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5891out4:
5892 free_page((unsigned long)vmx_msr_bitmap_longmode);
5893out3:
5894 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5895out2:
5896 free_page((unsigned long)vmx_msr_bitmap_legacy);
5897out1:
5898 free_page((unsigned long)vmx_io_bitmap_b);
5899out:
5900 free_page((unsigned long)vmx_io_bitmap_a);
5901
5902 return r;
f2c7648d
TC		 5903}
5904
5905static __exit void hardware_unsetup(void)
5906{
34a1cd60
TC		 5907 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5908 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5909 free_page((unsigned long)vmx_msr_bitmap_legacy);
5910 free_page((unsigned long)vmx_msr_bitmap_longmode);
5911 free_page((unsigned long)vmx_io_bitmap_b);
5912 free_page((unsigned long)vmx_io_bitmap_a);
5913 free_page((unsigned long)vmx_vmwrite_bitmap);
5914 free_page((unsigned long)vmx_vmread_bitmap);
5915
f2c7648d
TC		 5916 free_kvm_area();
5917}
5918
4b8d54f9
ZE		 5919/*
5920 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5921 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5922 */
9fb41ba8 5923static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5924{
b4a2d31d
RK		 5925 if (ple_gap)
5926 grow_ple_window(vcpu);
5927
4b8d54f9
ZE		 5928 skip_emulated_instruction(vcpu);
5929 kvm_vcpu_on_spin(vcpu);
5930
5931 return 1;
5932}
5933
87c00572 5934static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5935{
87c00572 5936 skip_emulated_instruction(vcpu);
59708670
SY		 5937 return 1;
5938}
5939
87c00572
GS		 5940static int handle_mwait(struct kvm_vcpu *vcpu)
5941{
5942 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5943 return handle_nop(vcpu);
5944}
5945
5946static int handle_monitor(struct kvm_vcpu *vcpu)
5947{
5948 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5949 return handle_nop(vcpu);
5950}
5951
ff2f6fe9
NHE		 5952/*
5953 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5954 * We could reuse a single VMCS for all the L2 guests, but we also want the
5955 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5956 * allows keeping them loaded on the processor, and in the future will allow
5957 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5958 * every entry if they never change.
5959 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5960 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5961 *
5962 * The following functions allocate and free a vmcs02 in this pool.
5963 */
5964
5965/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5966static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5967{
5968 struct vmcs02_list *item;
5969 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5970 if (item->vmptr == vmx->nested.current_vmptr) {
5971 list_move(&item->list, &vmx->nested.vmcs02_pool);
5972 return &item->vmcs02;
5973 }
5974
5975 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5976 /* Recycle the least recently used VMCS. */
5977 item = list_entry(vmx->nested.vmcs02_pool.prev,
5978 struct vmcs02_list, list);
5979 item->vmptr = vmx->nested.current_vmptr;
5980 list_move(&item->list, &vmx->nested.vmcs02_pool);
5981 return &item->vmcs02;
5982 }
5983
5984 /* Create a new VMCS */
0fa24ce3 5985 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5986 if (!item)
5987 return NULL;
5988 item->vmcs02.vmcs = alloc_vmcs();
5989 if (!item->vmcs02.vmcs) {
5990 kfree(item);
5991 return NULL;
5992 }
5993 loaded_vmcs_init(&item->vmcs02);
5994 item->vmptr = vmx->nested.current_vmptr;
5995 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5996 vmx->nested.vmcs02_num++;
5997 return &item->vmcs02;
5998}
5999
6000/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6001static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6002{
6003 struct vmcs02_list *item;
6004 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6005 if (item->vmptr == vmptr) {
6006 free_loaded_vmcs(&item->vmcs02);
6007 list_del(&item->list);
6008 kfree(item);
6009 vmx->nested.vmcs02_num--;
6010 return;
6011 }
6012}
6013
6014/*
6015 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6016 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6017 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6018 */
6019static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6020{
6021 struct vmcs02_list *item, *n;
4fa7734c
PB		 6022
6023 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6024 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6025 /*
6026 * Something will leak if the above WARN triggers. Better than
6027 * a use-after-free.
6028 */
6029 if (vmx->loaded_vmcs == &item->vmcs02)
6030 continue;
6031
6032 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6033 list_del(&item->list);
6034 kfree(item);
4fa7734c 6035 vmx->nested.vmcs02_num--;
ff2f6fe9 6036 }
ff2f6fe9
NHE		 6037}
6038
0658fbaa
ACL		 6039/*
6040 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6041 * set the success or error code of an emulated VMX instruction, as specified
6042 * by Vol 2B, VMX Instruction Reference, "Conventions".
6043 */
6044static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6045{
6046 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6047 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6048 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6049}
6050
6051static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6052{
6053 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6054 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6055 X86_EFLAGS_SF | X86_EFLAGS_OF))
6056 | X86_EFLAGS_CF);
6057}
6058
145c28dd 6059static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6060 u32 vm_instruction_error)
6061{
6062 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6063 /*
6064 * failValid writes the error number to the current VMCS, which
6065 * can't be done there isn't a current VMCS.
6066 */
6067 nested_vmx_failInvalid(vcpu);
6068 return;
6069 }
6070 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6071 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6072 X86_EFLAGS_SF | X86_EFLAGS_OF))
6073 | X86_EFLAGS_ZF);
6074 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6075 /*
6076 * We don't need to force a shadow sync because
6077 * VM_INSTRUCTION_ERROR is not shadowed
6078 */
6079}
145c28dd 6080
f4124500
JK		 6081static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6082{
6083 struct vcpu_vmx *vmx =
6084 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6085
6086 vmx->nested.preemption_timer_expired = true;
6087 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6088 kvm_vcpu_kick(&vmx->vcpu);
6089
6090 return HRTIMER_NORESTART;
6091}
6092
19677e32
BD		 6093/*
6094 * Decode the memory-address operand of a vmx instruction, as recorded on an
6095 * exit caused by such an instruction (run by a guest hypervisor).
6096 * On success, returns 0. When the operand is invalid, returns 1 and throws
6097 * #UD or #GP.
6098 */
6099static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6100 unsigned long exit_qualification,
6101 u32 vmx_instruction_info, gva_t *ret)
6102{
6103 /*
6104 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6105 * Execution", on an exit, vmx_instruction_info holds most of the
6106 * addressing components of the operand. Only the displacement part
6107 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6108 * For how an actual address is calculated from all these components,
6109 * refer to Vol. 1, "Operand Addressing".
6110 */
6111 int scaling = vmx_instruction_info & 3;
6112 int addr_size = (vmx_instruction_info >> 7) & 7;
6113 bool is_reg = vmx_instruction_info & (1u << 10);
6114 int seg_reg = (vmx_instruction_info >> 15) & 7;
6115 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6116 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6117 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6118 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6119
6120 if (is_reg) {
6121 kvm_queue_exception(vcpu, UD_VECTOR);
6122 return 1;
6123 }
6124
6125 /* Addr = segment_base + offset */
6126 /* offset = base + [index * scale] + displacement */
6127 *ret = vmx_get_segment_base(vcpu, seg_reg);
6128 if (base_is_valid)
6129 *ret += kvm_register_read(vcpu, base_reg);
6130 if (index_is_valid)
6131 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6132 *ret += exit_qualification; /* holds the displacement */
6133
6134 if (addr_size == 1) /* 32 bit */
6135 *ret &= 0xffffffff;
6136
6137 /*
6138 * TODO: throw #GP (and return 1) in various cases that the VM*
6139 * instructions require it - e.g., offset beyond segment limit,
6140 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6141 * address, and so on. Currently these are not checked.
6142 */
6143 return 0;
6144}
6145
3573e22c
BD		 6146/*
6147 * This function performs the various checks including
6148 * - if it's 4KB aligned
6149 * - No bits beyond the physical address width are set
6150 * - Returns 0 on success or else 1
4291b588 6151 * (Intel SDM Section 30.3)
3573e22c 6152 */
4291b588
BD		 6153static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6154 gpa_t *vmpointer)
3573e22c
BD		 6155{
6156 gva_t gva;
6157 gpa_t vmptr;
6158 struct x86_exception e;
6159 struct page *page;
6160 struct vcpu_vmx *vmx = to_vmx(vcpu);
6161 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6162
6163 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6164 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6165 return 1;
6166
6167 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6168 sizeof(vmptr), &e)) {
6169 kvm_inject_page_fault(vcpu, &e);
6170 return 1;
6171 }
6172
6173 switch (exit_reason) {
6174 case EXIT_REASON_VMON:
6175 /*
6176 * SDM 3: 24.11.5
6177 * The first 4 bytes of VMXON region contain the supported
6178 * VMCS revision identifier
6179 *
6180 * Note - IA32_VMX_BASIC[48] will never be 1
6181 * for the nested case;
6182 * which replaces physical address width with 32
6183 *
6184 */
bc39c4db 6185 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6186 nested_vmx_failInvalid(vcpu);
6187 skip_emulated_instruction(vcpu);
6188 return 1;
6189 }
6190
6191 page = nested_get_page(vcpu, vmptr);
6192 if (page == NULL ||
6193 *(u32 *)kmap(page) != VMCS12_REVISION) {
6194 nested_vmx_failInvalid(vcpu);
6195 kunmap(page);
6196 skip_emulated_instruction(vcpu);
6197 return 1;
6198 }
6199 kunmap(page);
6200 vmx->nested.vmxon_ptr = vmptr;
6201 break;
4291b588 6202 case EXIT_REASON_VMCLEAR:
bc39c4db 6203 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6204 nested_vmx_failValid(vcpu,
6205 VMXERR_VMCLEAR_INVALID_ADDRESS);
6206 skip_emulated_instruction(vcpu);
6207 return 1;
6208 }
6209
6210 if (vmptr == vmx->nested.vmxon_ptr) {
6211 nested_vmx_failValid(vcpu,
6212 VMXERR_VMCLEAR_VMXON_POINTER);
6213 skip_emulated_instruction(vcpu);
6214 return 1;
6215 }
6216 break;
6217 case EXIT_REASON_VMPTRLD:
bc39c4db 6218 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6219 nested_vmx_failValid(vcpu,
6220 VMXERR_VMPTRLD_INVALID_ADDRESS);
6221 skip_emulated_instruction(vcpu);
6222 return 1;
6223 }
3573e22c 6224
4291b588
BD		 6225 if (vmptr == vmx->nested.vmxon_ptr) {
6226 nested_vmx_failValid(vcpu,
6227 VMXERR_VMCLEAR_VMXON_POINTER);
6228 skip_emulated_instruction(vcpu);
6229 return 1;
6230 }
6231 break;
3573e22c
BD		 6232 default:
6233 return 1; /* shouldn't happen */
6234 }
6235
4291b588
BD		 6236 if (vmpointer)
6237 *vmpointer = vmptr;
3573e22c
BD		 6238 return 0;
6239}
6240
ec378aee
NHE		 6241/*
6242 * Emulate the VMXON instruction.
6243 * Currently, we just remember that VMX is active, and do not save or even
6244 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6245 * do not currently need to store anything in that guest-allocated memory
6246 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6247 * argument is different from the VMXON pointer (which the spec says they do).
6248 */
6249static int handle_vmon(struct kvm_vcpu *vcpu)
6250{
6251 struct kvm_segment cs;
6252 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6253 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6254 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6255 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6256
6257 /* The Intel VMX Instruction Reference lists a bunch of bits that
6258 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6259 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6260 * Otherwise, we should fail with #UD. We test these now:
6261 */
6262 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6263 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6264 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6265 kvm_queue_exception(vcpu, UD_VECTOR);
6266 return 1;
6267 }
6268
6269 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6270 if (is_long_mode(vcpu) && !cs.l) {
6271 kvm_queue_exception(vcpu, UD_VECTOR);
6272 return 1;
6273 }
6274
6275 if (vmx_get_cpl(vcpu)) {
6276 kvm_inject_gp(vcpu, 0);
6277 return 1;
6278 }
3573e22c 6279
4291b588 6280 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6281 return 1;
6282
145c28dd
AG		 6283 if (vmx->nested.vmxon) {
6284 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6285 skip_emulated_instruction(vcpu);
6286 return 1;
6287 }
b3897a49
NHE		 6288
6289 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6290 != VMXON_NEEDED_FEATURES) {
6291 kvm_inject_gp(vcpu, 0);
6292 return 1;
6293 }
6294
8de48833
AG		 6295 if (enable_shadow_vmcs) {
6296 shadow_vmcs = alloc_vmcs();
6297 if (!shadow_vmcs)
6298 return -ENOMEM;
6299 /* mark vmcs as shadow */
6300 shadow_vmcs->revision_id |= (1u << 31);
6301 /* init shadow vmcs */
6302 vmcs_clear(shadow_vmcs);
6303 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6304 }
ec378aee 6305
ff2f6fe9
NHE		 6306 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6307 vmx->nested.vmcs02_num = 0;
6308
f4124500
JK		 6309 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6310 HRTIMER_MODE_REL);
6311 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6312
ec378aee
NHE		 6313 vmx->nested.vmxon = true;
6314
6315 skip_emulated_instruction(vcpu);
a25eb114 6316 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6317 return 1;
6318}
6319
6320/*
6321 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6322 * for running VMX instructions (except VMXON, whose prerequisites are
6323 * slightly different). It also specifies what exception to inject otherwise.
6324 */
6325static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6326{
6327 struct kvm_segment cs;
6328 struct vcpu_vmx *vmx = to_vmx(vcpu);
6329
6330 if (!vmx->nested.vmxon) {
6331 kvm_queue_exception(vcpu, UD_VECTOR);
6332 return 0;
6333 }
6334
6335 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6336 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6337 (is_long_mode(vcpu) && !cs.l)) {
6338 kvm_queue_exception(vcpu, UD_VECTOR);
6339 return 0;
6340 }
6341
6342 if (vmx_get_cpl(vcpu)) {
6343 kvm_inject_gp(vcpu, 0);
6344 return 0;
6345 }
6346
6347 return 1;
6348}
6349
e7953d7f
AG		 6350static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6351{
8a1b9dd0 6352 u32 exec_control;
9a2a05b9
PB		 6353 if (vmx->nested.current_vmptr == -1ull)
6354 return;
6355
6356 /* current_vmptr and current_vmcs12 are always set/reset together */
6357 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6358 return;
6359
012f83cb 6360 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6361 /* copy to memory all shadowed fields in case
6362 they were modified */
6363 copy_shadow_to_vmcs12(vmx);
6364 vmx->nested.sync_shadow_vmcs = false;
6365 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6366 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6367 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6368 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6369 }
e7953d7f
AG		 6370 kunmap(vmx->nested.current_vmcs12_page);
6371 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6372 vmx->nested.current_vmptr = -1ull;
6373 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6374}
6375
ec378aee
NHE		 6376/*
6377 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6378 * just stops using VMX.
6379 */
6380static void free_nested(struct vcpu_vmx *vmx)
6381{
6382 if (!vmx->nested.vmxon)
6383 return;
9a2a05b9 6384
ec378aee 6385 vmx->nested.vmxon = false;
9a2a05b9 6386 nested_release_vmcs12(vmx);
e7953d7f
AG		 6387 if (enable_shadow_vmcs)
6388 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6389 /* Unpin physical memory we referred to in current vmcs02 */
6390 if (vmx->nested.apic_access_page) {
6391 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6392 vmx->nested.apic_access_page = NULL;
fe3ef05c 6393 }
a7c0b07d
WL		 6394 if (vmx->nested.virtual_apic_page) {
6395 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6396 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6397 }
ff2f6fe9
NHE		 6398
6399 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6400}
6401
6402/* Emulate the VMXOFF instruction */
6403static int handle_vmoff(struct kvm_vcpu *vcpu)
6404{
6405 if (!nested_vmx_check_permission(vcpu))
6406 return 1;
6407 free_nested(to_vmx(vcpu));
6408 skip_emulated_instruction(vcpu);
a25eb114 6409 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6410 return 1;
6411}
6412
27d6c865
NHE		 6413/* Emulate the VMCLEAR instruction */
6414static int handle_vmclear(struct kvm_vcpu *vcpu)
6415{
6416 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6417 gpa_t vmptr;
6418 struct vmcs12 *vmcs12;
6419 struct page *page;
27d6c865
NHE		 6420
6421 if (!nested_vmx_check_permission(vcpu))
6422 return 1;
6423
4291b588 6424 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6425 return 1;
27d6c865 6426
9a2a05b9 6427 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6428 nested_release_vmcs12(vmx);
27d6c865
NHE		 6429
6430 page = nested_get_page(vcpu, vmptr);
6431 if (page == NULL) {
6432 /*
6433 * For accurate processor emulation, VMCLEAR beyond available
6434 * physical memory should do nothing at all. However, it is
6435 * possible that a nested vmx bug, not a guest hypervisor bug,
6436 * resulted in this case, so let's shut down before doing any
6437 * more damage:
6438 */
6439 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6440 return 1;
6441 }
6442 vmcs12 = kmap(page);
6443 vmcs12->launch_state = 0;
6444 kunmap(page);
6445 nested_release_page(page);
6446
6447 nested_free_vmcs02(vmx, vmptr);
6448
6449 skip_emulated_instruction(vcpu);
6450 nested_vmx_succeed(vcpu);
6451 return 1;
6452}
6453
cd232ad0
NHE		 6454static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6455
6456/* Emulate the VMLAUNCH instruction */
6457static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6458{
6459 return nested_vmx_run(vcpu, true);
6460}
6461
6462/* Emulate the VMRESUME instruction */
6463static int handle_vmresume(struct kvm_vcpu *vcpu)
6464{
6465
6466 return nested_vmx_run(vcpu, false);
6467}
6468
49f705c5
NHE		 6469enum vmcs_field_type {
6470 VMCS_FIELD_TYPE_U16 = 0,
6471 VMCS_FIELD_TYPE_U64 = 1,
6472 VMCS_FIELD_TYPE_U32 = 2,
6473 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6474};
6475
6476static inline int vmcs_field_type(unsigned long field)
6477{
6478 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6479 return VMCS_FIELD_TYPE_U32;
6480 return (field >> 13) & 0x3 ;
6481}
6482
6483static inline int vmcs_field_readonly(unsigned long field)
6484{
6485 return (((field >> 10) & 0x3) == 1);
6486}
6487
6488/*
6489 * Read a vmcs12 field. Since these can have varying lengths and we return
6490 * one type, we chose the biggest type (u64) and zero-extend the return value
6491 * to that size. Note that the caller, handle_vmread, might need to use only
6492 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6493 * 64-bit fields are to be returned).
6494 */
6495static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6496 unsigned long field, u64 *ret)
6497{
6498 short offset = vmcs_field_to_offset(field);
6499 char *p;
6500
6501 if (offset < 0)
6502 return 0;
6503
6504 p = ((char *)(get_vmcs12(vcpu))) + offset;
6505
6506 switch (vmcs_field_type(field)) {
6507 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6508 *ret = *((natural_width *)p);
6509 return 1;
6510 case VMCS_FIELD_TYPE_U16:
6511 *ret = *((u16 *)p);
6512 return 1;
6513 case VMCS_FIELD_TYPE_U32:
6514 *ret = *((u32 *)p);
6515 return 1;
6516 case VMCS_FIELD_TYPE_U64:
6517 *ret = *((u64 *)p);
6518 return 1;
6519 default:
6520 return 0; /* can never happen. */
6521 }
6522}
6523
20b97fea
AG		 6524
6525static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6526 unsigned long field, u64 field_value){
6527 short offset = vmcs_field_to_offset(field);
6528 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6529 if (offset < 0)
6530 return false;
6531
6532 switch (vmcs_field_type(field)) {
6533 case VMCS_FIELD_TYPE_U16:
6534 *(u16 *)p = field_value;
6535 return true;
6536 case VMCS_FIELD_TYPE_U32:
6537 *(u32 *)p = field_value;
6538 return true;
6539 case VMCS_FIELD_TYPE_U64:
6540 *(u64 *)p = field_value;
6541 return true;
6542 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6543 *(natural_width *)p = field_value;
6544 return true;
6545 default:
6546 return false; /* can never happen. */
6547 }
6548
6549}
6550
16f5b903
AG		 6551static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6552{
6553 int i;
6554 unsigned long field;
6555 u64 field_value;
6556 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6557 const unsigned long *fields = shadow_read_write_fields;
6558 const int num_fields = max_shadow_read_write_fields;
16f5b903 6559
282da870
JK		 6560 preempt_disable();
6561
16f5b903
AG		 6562 vmcs_load(shadow_vmcs);
6563
6564 for (i = 0; i < num_fields; i++) {
6565 field = fields[i];
6566 switch (vmcs_field_type(field)) {
6567 case VMCS_FIELD_TYPE_U16:
6568 field_value = vmcs_read16(field);
6569 break;
6570 case VMCS_FIELD_TYPE_U32:
6571 field_value = vmcs_read32(field);
6572 break;
6573 case VMCS_FIELD_TYPE_U64:
6574 field_value = vmcs_read64(field);
6575 break;
6576 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6577 field_value = vmcs_readl(field);
6578 break;
6579 }
6580 vmcs12_write_any(&vmx->vcpu, field, field_value);
6581 }
6582
6583 vmcs_clear(shadow_vmcs);
6584 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6585
6586 preempt_enable();
16f5b903
AG		 6587}
6588
c3114420
AG		 6589static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6590{
c2bae893
MK		 6591 const unsigned long *fields[] = {
6592 shadow_read_write_fields,
6593 shadow_read_only_fields
c3114420 6594 };
c2bae893 6595 const int max_fields[] = {
c3114420
AG		 6596 max_shadow_read_write_fields,
6597 max_shadow_read_only_fields
6598 };
6599 int i, q;
6600 unsigned long field;
6601 u64 field_value = 0;
6602 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6603
6604 vmcs_load(shadow_vmcs);
6605
c2bae893 6606 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6607 for (i = 0; i < max_fields[q]; i++) {
6608 field = fields[q][i];
6609 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6610
6611 switch (vmcs_field_type(field)) {
6612 case VMCS_FIELD_TYPE_U16:
6613 vmcs_write16(field, (u16)field_value);
6614 break;
6615 case VMCS_FIELD_TYPE_U32:
6616 vmcs_write32(field, (u32)field_value);
6617 break;
6618 case VMCS_FIELD_TYPE_U64:
6619 vmcs_write64(field, (u64)field_value);
6620 break;
6621 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6622 vmcs_writel(field, (long)field_value);
6623 break;
6624 }
6625 }
6626 }
6627
6628 vmcs_clear(shadow_vmcs);
6629 vmcs_load(vmx->loaded_vmcs->vmcs);
6630}
6631
49f705c5
NHE		 6632/*
6633 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6634 * used before) all generate the same failure when it is missing.
6635 */
6636static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6637{
6638 struct vcpu_vmx *vmx = to_vmx(vcpu);
6639 if (vmx->nested.current_vmptr == -1ull) {
6640 nested_vmx_failInvalid(vcpu);
6641 skip_emulated_instruction(vcpu);
6642 return 0;
6643 }
6644 return 1;
6645}
6646
6647static int handle_vmread(struct kvm_vcpu *vcpu)
6648{
6649 unsigned long field;
6650 u64 field_value;
6651 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6652 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6653 gva_t gva = 0;
6654
6655 if (!nested_vmx_check_permission(vcpu) ||
6656 !nested_vmx_check_vmcs12(vcpu))
6657 return 1;
6658
6659 /* Decode instruction info and find the field to read */
27e6fb5d 6660 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6661 /* Read the field, zero-extended to a u64 field_value */
6662 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6663 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6664 skip_emulated_instruction(vcpu);
6665 return 1;
6666 }
6667 /*
6668 * Now copy part of this value to register or memory, as requested.
6669 * Note that the number of bits actually copied is 32 or 64 depending
6670 * on the guest's mode (32 or 64 bit), not on the given field's length.
6671 */
6672 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6673 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6674 field_value);
6675 } else {
6676 if (get_vmx_mem_address(vcpu, exit_qualification,
6677 vmx_instruction_info, &gva))
6678 return 1;
6679 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6680 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6681 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6682 }
6683
6684 nested_vmx_succeed(vcpu);
6685 skip_emulated_instruction(vcpu);
6686 return 1;
6687}
6688
6689
6690static int handle_vmwrite(struct kvm_vcpu *vcpu)
6691{
6692 unsigned long field;
6693 gva_t gva;
6694 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6695 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6696 /* The value to write might be 32 or 64 bits, depending on L1's long
6697 * mode, and eventually we need to write that into a field of several
6698 * possible lengths. The code below first zero-extends the value to 64
6699 * bit (field_value), and then copies only the approriate number of
6700 * bits into the vmcs12 field.
6701 */
6702 u64 field_value = 0;
6703 struct x86_exception e;
6704
6705 if (!nested_vmx_check_permission(vcpu) ||
6706 !nested_vmx_check_vmcs12(vcpu))
6707 return 1;
6708
6709 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6710 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6711 (((vmx_instruction_info) >> 3) & 0xf));
6712 else {
6713 if (get_vmx_mem_address(vcpu, exit_qualification,
6714 vmx_instruction_info, &gva))
6715 return 1;
6716 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6717 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6718 kvm_inject_page_fault(vcpu, &e);
6719 return 1;
6720 }
6721 }
6722
6723
27e6fb5d 6724 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6725 if (vmcs_field_readonly(field)) {
6726 nested_vmx_failValid(vcpu,
6727 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6728 skip_emulated_instruction(vcpu);
6729 return 1;
6730 }
6731
20b97fea 6732 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6733 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6734 skip_emulated_instruction(vcpu);
6735 return 1;
6736 }
6737
6738 nested_vmx_succeed(vcpu);
6739 skip_emulated_instruction(vcpu);
6740 return 1;
6741}
6742
63846663
NHE		 6743/* Emulate the VMPTRLD instruction */
6744static int handle_vmptrld(struct kvm_vcpu *vcpu)
6745{
6746 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6747 gpa_t vmptr;
8a1b9dd0 6748 u32 exec_control;
63846663
NHE		 6749
6750 if (!nested_vmx_check_permission(vcpu))
6751 return 1;
6752
4291b588 6753 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6754 return 1;
63846663
NHE		 6755
6756 if (vmx->nested.current_vmptr != vmptr) {
6757 struct vmcs12 *new_vmcs12;
6758 struct page *page;
6759 page = nested_get_page(vcpu, vmptr);
6760 if (page == NULL) {
6761 nested_vmx_failInvalid(vcpu);
6762 skip_emulated_instruction(vcpu);
6763 return 1;
6764 }
6765 new_vmcs12 = kmap(page);
6766 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6767 kunmap(page);
6768 nested_release_page_clean(page);
6769 nested_vmx_failValid(vcpu,
6770 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6771 skip_emulated_instruction(vcpu);
6772 return 1;
6773 }
63846663 6774
9a2a05b9 6775 nested_release_vmcs12(vmx);
63846663
NHE		 6776 vmx->nested.current_vmptr = vmptr;
6777 vmx->nested.current_vmcs12 = new_vmcs12;
6778 vmx->nested.current_vmcs12_page = page;
012f83cb 6779 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6780 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6781 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6782 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6783 vmcs_write64(VMCS_LINK_POINTER,
6784 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6785 vmx->nested.sync_shadow_vmcs = true;
6786 }
63846663
NHE		 6787 }
6788
6789 nested_vmx_succeed(vcpu);
6790 skip_emulated_instruction(vcpu);
6791 return 1;
6792}
6793
6a4d7550
NHE		 6794/* Emulate the VMPTRST instruction */
6795static int handle_vmptrst(struct kvm_vcpu *vcpu)
6796{
6797 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6798 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6799 gva_t vmcs_gva;
6800 struct x86_exception e;
6801
6802 if (!nested_vmx_check_permission(vcpu))
6803 return 1;
6804
6805 if (get_vmx_mem_address(vcpu, exit_qualification,
6806 vmx_instruction_info, &vmcs_gva))
6807 return 1;
6808 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6809 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6810 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6811 sizeof(u64), &e)) {
6812 kvm_inject_page_fault(vcpu, &e);
6813 return 1;
6814 }
6815 nested_vmx_succeed(vcpu);
6816 skip_emulated_instruction(vcpu);
6817 return 1;
6818}
6819
bfd0a56b
NHE		 6820/* Emulate the INVEPT instruction */
6821static int handle_invept(struct kvm_vcpu *vcpu)
6822{
6823 u32 vmx_instruction_info, types;
6824 unsigned long type;
6825 gva_t gva;
6826 struct x86_exception e;
6827 struct {
6828 u64 eptp, gpa;
6829 } operand;
bfd0a56b
NHE		 6830
6831 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6832 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6833 kvm_queue_exception(vcpu, UD_VECTOR);
6834 return 1;
6835 }
6836
6837 if (!nested_vmx_check_permission(vcpu))
6838 return 1;
6839
6840 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6841 kvm_queue_exception(vcpu, UD_VECTOR);
6842 return 1;
6843 }
6844
6845 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 6846 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b
NHE		 6847
6848 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6849
6850 if (!(types & (1UL << type))) {
6851 nested_vmx_failValid(vcpu,
6852 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6853 return 1;
6854 }
6855
6856 /* According to the Intel VMX instruction reference, the memory
6857 * operand is read even if it isn't needed (e.g., for type==global)
6858 */
6859 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6860 vmx_instruction_info, &gva))
6861 return 1;
6862 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6863 sizeof(operand), &e)) {
6864 kvm_inject_page_fault(vcpu, &e);
6865 return 1;
6866 }
6867
6868 switch (type) {
bfd0a56b
NHE		 6869 case VMX_EPT_EXTENT_GLOBAL:
6870 kvm_mmu_sync_roots(vcpu);
77c3913b 6871 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 6872 nested_vmx_succeed(vcpu);
6873 break;
6874 default:
4b855078 6875 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6876 BUG_ON(1);
6877 break;
6878 }
6879
6880 skip_emulated_instruction(vcpu);
6881 return 1;
6882}
6883
a642fc30
PM		 6884static int handle_invvpid(struct kvm_vcpu *vcpu)
6885{
6886 kvm_queue_exception(vcpu, UD_VECTOR);
6887 return 1;
6888}
6889
6aa8b732
AK		 6890/*
6891 * The exit handlers return 1 if the exit was handled fully and guest execution
6892 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6893 * to be done to userspace and return 0.
6894 */
772e0318 6895static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6896 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6897 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6898 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6899 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6900 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6901 [EXIT_REASON_CR_ACCESS] = handle_cr,
6902 [EXIT_REASON_DR_ACCESS] = handle_dr,
6903 [EXIT_REASON_CPUID] = handle_cpuid,
6904 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6905 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6906 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6907 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6908 [EXIT_REASON_INVD] = handle_invd,
a7052897 6909 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6910 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6911 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6912 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6913 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6914 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6915 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6916 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6917 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6918 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6919 [EXIT_REASON_VMOFF] = handle_vmoff,
6920 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6921 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6922 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6923 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6924 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6925 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6926 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6927 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6928 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6929 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6930 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6931 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 6932 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6933 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 6934 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 6935 [EXIT_REASON_INVVPID] = handle_invvpid,
6aa8b732
AK		 6936};
6937
6938static const int kvm_vmx_max_exit_handlers =
50a3485c 6939 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6940
908a7bdd
JK		 6941static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6942 struct vmcs12 *vmcs12)
6943{
6944 unsigned long exit_qualification;
6945 gpa_t bitmap, last_bitmap;
6946 unsigned int port;
6947 int size;
6948 u8 b;
6949
908a7bdd 6950 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6951 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6952
6953 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6954
6955 port = exit_qualification >> 16;
6956 size = (exit_qualification & 7) + 1;
6957
6958 last_bitmap = (gpa_t)-1;
6959 b = -1;
6960
6961 while (size > 0) {
6962 if (port < 0x8000)
6963 bitmap = vmcs12->io_bitmap_a;
6964 else if (port < 0x10000)
6965 bitmap = vmcs12->io_bitmap_b;
6966 else
6967 return 1;
6968 bitmap += (port & 0x7fff) / 8;
6969
6970 if (last_bitmap != bitmap)
6971 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6972 return 1;
6973 if (b & (1 << (port & 7)))
6974 return 1;
6975
6976 port++;
6977 size--;
6978 last_bitmap = bitmap;
6979 }
6980
6981 return 0;
6982}
6983
644d711a
NHE		 6984/*
6985 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6986 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6987 * disinterest in the current event (read or write a specific MSR) by using an
6988 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6989 */
6990static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6991 struct vmcs12 *vmcs12, u32 exit_reason)
6992{
6993 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6994 gpa_t bitmap;
6995
cbd29cb6 6996 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6997 return 1;
6998
6999 /*
7000 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7001 * for the four combinations of read/write and low/high MSR numbers.
7002 * First we need to figure out which of the four to use:
7003 */
7004 bitmap = vmcs12->msr_bitmap;
7005 if (exit_reason == EXIT_REASON_MSR_WRITE)
7006 bitmap += 2048;
7007 if (msr_index >= 0xc0000000) {
7008 msr_index -= 0xc0000000;
7009 bitmap += 1024;
7010 }
7011
7012 /* Then read the msr_index'th bit from this bitmap: */
7013 if (msr_index < 1024*8) {
7014 unsigned char b;
bd31a7f5
JK		 7015 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7016 return 1;
644d711a
NHE		 7017 return 1 & (b >> (msr_index & 7));
7018 } else
7019 return 1; /* let L1 handle the wrong parameter */
7020}
7021
7022/*
7023 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7024 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7025 * intercept (via guest_host_mask etc.) the current event.
7026 */
7027static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7028 struct vmcs12 *vmcs12)
7029{
7030 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7031 int cr = exit_qualification & 15;
7032 int reg = (exit_qualification >> 8) & 15;
1e32c079 7033 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7034
7035 switch ((exit_qualification >> 4) & 3) {
7036 case 0: /* mov to cr */
7037 switch (cr) {
7038 case 0:
7039 if (vmcs12->cr0_guest_host_mask &
7040 (val ^ vmcs12->cr0_read_shadow))
7041 return 1;
7042 break;
7043 case 3:
7044 if ((vmcs12->cr3_target_count >= 1 &&
7045 vmcs12->cr3_target_value0 == val) ||
7046 (vmcs12->cr3_target_count >= 2 &&
7047 vmcs12->cr3_target_value1 == val) ||
7048 (vmcs12->cr3_target_count >= 3 &&
7049 vmcs12->cr3_target_value2 == val) ||
7050 (vmcs12->cr3_target_count >= 4 &&
7051 vmcs12->cr3_target_value3 == val))
7052 return 0;
7053 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7054 return 1;
7055 break;
7056 case 4:
7057 if (vmcs12->cr4_guest_host_mask &
7058 (vmcs12->cr4_read_shadow ^ val))
7059 return 1;
7060 break;
7061 case 8:
7062 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7063 return 1;
7064 break;
7065 }
7066 break;
7067 case 2: /* clts */
7068 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7069 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7070 return 1;
7071 break;
7072 case 1: /* mov from cr */
7073 switch (cr) {
7074 case 3:
7075 if (vmcs12->cpu_based_vm_exec_control &
7076 CPU_BASED_CR3_STORE_EXITING)
7077 return 1;
7078 break;
7079 case 8:
7080 if (vmcs12->cpu_based_vm_exec_control &
7081 CPU_BASED_CR8_STORE_EXITING)
7082 return 1;
7083 break;
7084 }
7085 break;
7086 case 3: /* lmsw */
7087 /*
7088 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7089 * cr0. Other attempted changes are ignored, with no exit.
7090 */
7091 if (vmcs12->cr0_guest_host_mask & 0xe &
7092 (val ^ vmcs12->cr0_read_shadow))
7093 return 1;
7094 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7095 !(vmcs12->cr0_read_shadow & 0x1) &&
7096 (val & 0x1))
7097 return 1;
7098 break;
7099 }
7100 return 0;
7101}
7102
7103/*
7104 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7105 * should handle it ourselves in L0 (and then continue L2). Only call this
7106 * when in is_guest_mode (L2).
7107 */
7108static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7109{
644d711a
NHE		 7110 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7111 struct vcpu_vmx *vmx = to_vmx(vcpu);
7112 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7113 u32 exit_reason = vmx->exit_reason;
644d711a 7114
542060ea
JK		 7115 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7116 vmcs_readl(EXIT_QUALIFICATION),
7117 vmx->idt_vectoring_info,
7118 intr_info,
7119 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7120 KVM_ISA_VMX);
7121
644d711a
NHE		 7122 if (vmx->nested.nested_run_pending)
7123 return 0;
7124
7125 if (unlikely(vmx->fail)) {
bd80158a
JK		 7126 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7127 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 7128 return 1;
7129 }
7130
7131 switch (exit_reason) {
7132 case EXIT_REASON_EXCEPTION_NMI:
7133 if (!is_exception(intr_info))
7134 return 0;
7135 else if (is_page_fault(intr_info))
7136 return enable_ept;
e504c909 7137 else if (is_no_device(intr_info) &&
ccf9844e 7138 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 7139 return 0;
644d711a
NHE		 7140 return vmcs12->exception_bitmap &
7141 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7142 case EXIT_REASON_EXTERNAL_INTERRUPT:
7143 return 0;
7144 case EXIT_REASON_TRIPLE_FAULT:
7145 return 1;
7146 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7147 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7148 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7149 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 7150 case EXIT_REASON_TASK_SWITCH:
7151 return 1;
7152 case EXIT_REASON_CPUID:
bc613494
MT		 7153 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7154 return 0;
644d711a
NHE		 7155 return 1;
7156 case EXIT_REASON_HLT:
7157 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7158 case EXIT_REASON_INVD:
7159 return 1;
7160 case EXIT_REASON_INVLPG:
7161 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7162 case EXIT_REASON_RDPMC:
7163 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7164 case EXIT_REASON_RDTSC:
7165 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7166 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7167 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7168 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7169 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7170 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7171 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7172 /*
7173 * VMX instructions trap unconditionally. This allows L1 to
7174 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7175 */
7176 return 1;
7177 case EXIT_REASON_CR_ACCESS:
7178 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7179 case EXIT_REASON_DR_ACCESS:
7180 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7181 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7182 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7183 case EXIT_REASON_MSR_READ:
7184 case EXIT_REASON_MSR_WRITE:
7185 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7186 case EXIT_REASON_INVALID_STATE:
7187 return 1;
7188 case EXIT_REASON_MWAIT_INSTRUCTION:
7189 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7190 case EXIT_REASON_MONITOR_INSTRUCTION:
7191 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7192 case EXIT_REASON_PAUSE_INSTRUCTION:
7193 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7194 nested_cpu_has2(vmcs12,
7195 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7196 case EXIT_REASON_MCE_DURING_VMENTRY:
7197 return 0;
7198 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7199 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7200 case EXIT_REASON_APIC_ACCESS:
7201 return nested_cpu_has2(vmcs12,
7202 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7203 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7204 /*
7205 * L0 always deals with the EPT violation. If nested EPT is
7206 * used, and the nested mmu code discovers that the address is
7207 * missing in the guest EPT table (EPT12), the EPT violation
7208 * will be injected with nested_ept_inject_page_fault()
7209 */
7210 return 0;
644d711a 7211 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7212 /*
7213 * L2 never uses directly L1's EPT, but rather L0's own EPT
7214 * table (shadow on EPT) or a merged EPT table that L0 built
7215 * (EPT on EPT). So any problems with the structure of the
7216 * table is L0's fault.
7217 */
644d711a
NHE		 7218 return 0;
7219 case EXIT_REASON_WBINVD:
7220 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7221 case EXIT_REASON_XSETBV:
7222 return 1;
7223 default:
7224 return 1;
7225 }
7226}
7227
586f9607
AK		 7228static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7229{
7230 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7231 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7232}
7233
6aa8b732
AK		 7234/*
7235 * The guest has exited. See if we can fix it or if we need userspace
7236 * assistance.
7237 */
851ba692 7238static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7239{
29bd8a78 7240 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7241 u32 exit_reason = vmx->exit_reason;
1155f76a 7242 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7243
80ced186 7244 /* If guest state is invalid, start emulating */
14168786 7245 if (vmx->emulation_required)
80ced186 7246 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7247
644d711a 7248 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7249 nested_vmx_vmexit(vcpu, exit_reason,
7250 vmcs_read32(VM_EXIT_INTR_INFO),
7251 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7252 return 1;
7253 }
7254
5120702e
MG		 7255 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7256 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7257 vcpu->run->fail_entry.hardware_entry_failure_reason
7258 = exit_reason;
7259 return 0;
7260 }
7261
29bd8a78 7262 if (unlikely(vmx->fail)) {
851ba692
AK		 7263 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7264 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7265 = vmcs_read32(VM_INSTRUCTION_ERROR);
7266 return 0;
7267 }
6aa8b732 7268
b9bf6882
XG		 7269 /*
7270 * Note:
7271 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7272 * delivery event since it indicates guest is accessing MMIO.
7273 * The vm-exit can be triggered again after return to guest that
7274 * will cause infinite loop.
7275 */
d77c26fc 7276 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7277 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7278 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7279 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7280 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7281 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7282 vcpu->run->internal.ndata = 2;
7283 vcpu->run->internal.data[0] = vectoring_info;
7284 vcpu->run->internal.data[1] = exit_reason;
7285 return 0;
7286 }
3b86cd99 7287
644d711a
NHE		 7288 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7289 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7290 get_vmcs12(vcpu))))) {
c4282df9 7291 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7292 vmx->soft_vnmi_blocked = 0;
3b86cd99 7293 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7294 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7295 /*
7296 * This CPU don't support us in finding the end of an
7297 * NMI-blocked window if the guest runs with IRQs
7298 * disabled. So we pull the trigger after 1 s of
7299 * futile waiting, but inform the user about this.
7300 */
7301 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7302 "state on VCPU %d after 1 s timeout\n",
7303 __func__, vcpu->vcpu_id);
7304 vmx->soft_vnmi_blocked = 0;
3b86cd99 7305 }
3b86cd99
JK		 7306 }
7307
6aa8b732
AK		 7308 if (exit_reason < kvm_vmx_max_exit_handlers
7309 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7310 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7311 else {
2bc19dc3
MT		 7312 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7313 kvm_queue_exception(vcpu, UD_VECTOR);
7314 return 1;
6aa8b732 7315 }
6aa8b732
AK		 7316}
7317
95ba8273 7318static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7319{
a7c0b07d
WL		 7320 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7321
7322 if (is_guest_mode(vcpu) &&
7323 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7324 return;
7325
95ba8273 7326 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7327 vmcs_write32(TPR_THRESHOLD, 0);
7328 return;
7329 }
7330
95ba8273 7331 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7332}
7333
8d14695f
YZ		 7334static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7335{
7336 u32 sec_exec_control;
7337
7338 /*
7339 * There is not point to enable virtualize x2apic without enable
7340 * apicv
7341 */
c7c9c56c
YZ		 7342 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7343 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7344 return;
7345
7346 if (!vm_need_tpr_shadow(vcpu->kvm))
7347 return;
7348
7349 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7350
7351 if (set) {
7352 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7353 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7354 } else {
7355 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7356 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7357 }
7358 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7359
7360 vmx_set_msr_bitmap(vcpu);
7361}
7362
38b99173
TC		 7363static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7364{
7365 struct vcpu_vmx *vmx = to_vmx(vcpu);
7366
7367 /*
7368 * Currently we do not handle the nested case where L2 has an
7369 * APIC access page of its own; that page is still pinned.
7370 * Hence, we skip the case where the VCPU is in guest mode _and_
7371 * L1 prepared an APIC access page for L2.
7372 *
7373 * For the case where L1 and L2 share the same APIC access page
7374 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7375 * in the vmcs12), this function will only update either the vmcs01
7376 * or the vmcs02. If the former, the vmcs02 will be updated by
7377 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7378 * the next L2->L1 exit.
7379 */
7380 if (!is_guest_mode(vcpu) ||
7381 !nested_cpu_has2(vmx->nested.current_vmcs12,
7382 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7383 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7384}
7385
c7c9c56c
YZ		 7386static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7387{
7388 u16 status;
7389 u8 old;
7390
7391 if (!vmx_vm_has_apicv(kvm))
7392 return;
7393
7394 if (isr == -1)
7395 isr = 0;
7396
7397 status = vmcs_read16(GUEST_INTR_STATUS);
7398 old = status >> 8;
7399 if (isr != old) {
7400 status &= 0xff;
7401 status |= isr << 8;
7402 vmcs_write16(GUEST_INTR_STATUS, status);
7403 }
7404}
7405
7406static void vmx_set_rvi(int vector)
7407{
7408 u16 status;
7409 u8 old;
7410
7411 status = vmcs_read16(GUEST_INTR_STATUS);
7412 old = (u8)status & 0xff;
7413 if ((u8)vector != old) {
7414 status &= ~0xff;
7415 status |= (u8)vector;
7416 vmcs_write16(GUEST_INTR_STATUS, status);
7417 }
7418}
7419
7420static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7421{
7422 if (max_irr == -1)
7423 return;
7424
963fee16
WL		 7425 /*
7426 * If a vmexit is needed, vmx_check_nested_events handles it.
7427 */
7428 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
7429 return;
7430
7431 if (!is_guest_mode(vcpu)) {
7432 vmx_set_rvi(max_irr);
7433 return;
7434 }
7435
7436 /*
7437 * Fall back to pre-APICv interrupt injection since L2
7438 * is run without virtual interrupt delivery.
7439 */
7440 if (!kvm_event_needs_reinjection(vcpu) &&
7441 vmx_interrupt_allowed(vcpu)) {
7442 kvm_queue_interrupt(vcpu, max_irr, false);
7443 vmx_inject_irq(vcpu);
7444 }
c7c9c56c
YZ		 7445}
7446
7447static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7448{
3d81bc7e
YZ		 7449 if (!vmx_vm_has_apicv(vcpu->kvm))
7450 return;
7451
c7c9c56c
YZ		 7452 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7453 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7454 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7455 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7456}
7457
51aa01d1 7458static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7459{
00eba012
AK		 7460 u32 exit_intr_info;
7461
7462 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7463 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7464 return;
7465
c5ca8e57 7466 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7467 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7468
7469 /* Handle machine checks before interrupts are enabled */
00eba012 7470 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7471 kvm_machine_check();
7472
20f65983 7473 /* We need to handle NMIs before interrupts are enabled */
00eba012 7474 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7475 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7476 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7477 asm("int $2");
ff9d07a0
ZY		 7478 kvm_after_handle_nmi(&vmx->vcpu);
7479 }
51aa01d1 7480}
20f65983 7481
a547c6db
YZ		 7482static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7483{
7484 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7485
7486 /*
7487 * If external interrupt exists, IF bit is set in rflags/eflags on the
7488 * interrupt stack frame, and interrupt will be enabled on a return
7489 * from interrupt handler.
7490 */
7491 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7492 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7493 unsigned int vector;
7494 unsigned long entry;
7495 gate_desc *desc;
7496 struct vcpu_vmx *vmx = to_vmx(vcpu);
7497#ifdef CONFIG_X86_64
7498 unsigned long tmp;
7499#endif
7500
7501 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7502 desc = (gate_desc *)vmx->host_idt_base + vector;
7503 entry = gate_offset(*desc);
7504 asm volatile(
7505#ifdef CONFIG_X86_64
7506 "mov %%" _ASM_SP ", %[sp]\n\t"
7507 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7508 "push $%c[ss]\n\t"
7509 "push %[sp]\n\t"
7510#endif
7511 "pushf\n\t"
7512 "orl $0x200, (%%" _ASM_SP ")\n\t"
7513 __ASM_SIZE(push) " $%c[cs]\n\t"
7514 "call *%[entry]\n\t"
7515 :
7516#ifdef CONFIG_X86_64
7517 [sp]"=&r"(tmp)
7518#endif
7519 :
7520 [entry]"r"(entry),
7521 [ss]"i"(__KERNEL_DS),
7522 [cs]"i"(__KERNEL_CS)
7523 );
7524 } else
7525 local_irq_enable();
7526}
7527
da8999d3
LJ		 7528static bool vmx_mpx_supported(void)
7529{
7530 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7531 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7532}
7533
51aa01d1
AK		 7534static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7535{
c5ca8e57 7536 u32 exit_intr_info;
51aa01d1
AK		 7537 bool unblock_nmi;
7538 u8 vector;
7539 bool idtv_info_valid;
7540
7541 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7542
cf393f75 7543 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7544 if (vmx->nmi_known_unmasked)
7545 return;
c5ca8e57
AK		 7546 /*
7547 * Can't use vmx->exit_intr_info since we're not sure what
7548 * the exit reason is.
7549 */
7550 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7551 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7552 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7553 /*
7b4a25cb 7554 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7555 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7556 * a guest IRET fault.
7b4a25cb
GN		 7557 * SDM 3: 23.2.2 (September 2008)
7558 * Bit 12 is undefined in any of the following cases:
7559 * If the VM exit sets the valid bit in the IDT-vectoring
7560 * information field.
7561 * If the VM exit is due to a double fault.
cf393f75 7562 */
7b4a25cb
GN		 7563 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7564 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7565 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7566 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7567 else
7568 vmx->nmi_known_unmasked =
7569 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7570 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7571 } else if (unlikely(vmx->soft_vnmi_blocked))
7572 vmx->vnmi_blocked_time +=
7573 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7574}
7575
3ab66e8a 7576static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7577 u32 idt_vectoring_info,
7578 int instr_len_field,
7579 int error_code_field)
51aa01d1 7580{
51aa01d1
AK		 7581 u8 vector;
7582 int type;
7583 bool idtv_info_valid;
7584
7585 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7586
3ab66e8a
JK		 7587 vcpu->arch.nmi_injected = false;
7588 kvm_clear_exception_queue(vcpu);
7589 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7590
7591 if (!idtv_info_valid)
7592 return;
7593
3ab66e8a 7594 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7595
668f612f
AK		 7596 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7597 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7598
64a7ec06 7599 switch (type) {
37b96e98 7600 case INTR_TYPE_NMI_INTR:
3ab66e8a 7601 vcpu->arch.nmi_injected = true;
668f612f 7602 /*
7b4a25cb 7603 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7604 * Clear bit "block by NMI" before VM entry if a NMI
7605 * delivery faulted.
668f612f 7606 */
3ab66e8a 7607 vmx_set_nmi_mask(vcpu, false);
37b96e98 7608 break;
37b96e98 7609 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7610 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7611 /* fall through */
7612 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7613 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7614 u32 err = vmcs_read32(error_code_field);
851eb667 7615 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7616 } else
851eb667 7617 kvm_requeue_exception(vcpu, vector);
37b96e98 7618 break;
66fd3f7f 7619 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7620 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7621 /* fall through */
37b96e98 7622 case INTR_TYPE_EXT_INTR:
3ab66e8a 7623 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7624 break;
7625 default:
7626 break;
f7d9238f 7627 }
cf393f75
AK		 7628}
7629
83422e17
AK		 7630static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7631{
3ab66e8a 7632 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7633 VM_EXIT_INSTRUCTION_LEN,
7634 IDT_VECTORING_ERROR_CODE);
7635}
7636
b463a6f7
AK		 7637static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7638{
3ab66e8a 7639 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7640 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7641 VM_ENTRY_INSTRUCTION_LEN,
7642 VM_ENTRY_EXCEPTION_ERROR_CODE);
7643
7644 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7645}
7646
d7cd9796
GN		 7647static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7648{
7649 int i, nr_msrs;
7650 struct perf_guest_switch_msr *msrs;
7651
7652 msrs = perf_guest_get_msrs(&nr_msrs);
7653
7654 if (!msrs)
7655 return;
7656
7657 for (i = 0; i < nr_msrs; i++)
7658 if (msrs[i].host == msrs[i].guest)
7659 clear_atomic_switch_msr(vmx, msrs[i].msr);
7660 else
7661 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7662 msrs[i].host);
7663}
7664
a3b5ba49 7665static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7666{
a2fa3e9f 7667 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 7668 unsigned long debugctlmsr, cr4;
104f226b
AK		 7669
7670 /* Record the guest's net vcpu time for enforced NMI injections. */
7671 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7672 vmx->entry_time = ktime_get();
7673
7674 /* Don't enter VMX if guest state is invalid, let the exit handler
7675 start emulation until we arrive back to a valid state */
14168786 7676 if (vmx->emulation_required)
104f226b
AK		 7677 return;
7678
a7653ecd
RK		 7679 if (vmx->ple_window_dirty) {
7680 vmx->ple_window_dirty = false;
7681 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7682 }
7683
012f83cb
AG		 7684 if (vmx->nested.sync_shadow_vmcs) {
7685 copy_vmcs12_to_shadow(vmx);
7686 vmx->nested.sync_shadow_vmcs = false;
7687 }
7688
104f226b
AK		 7689 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7690 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7691 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7692 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7693
d974baa3
AL		 7694 cr4 = read_cr4();
7695 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
7696 vmcs_writel(HOST_CR4, cr4);
7697 vmx->host_state.vmcs_host_cr4 = cr4;
7698 }
7699
104f226b
AK		 7700 /* When single-stepping over STI and MOV SS, we must clear the
7701 * corresponding interruptibility bits in the guest state. Otherwise
7702 * vmentry fails as it then expects bit 14 (BS) in pending debug
7703 * exceptions being set, but that's not correct for the guest debugging
7704 * case. */
7705 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7706 vmx_set_interrupt_shadow(vcpu, 0);
7707
d7cd9796 7708 atomic_switch_perf_msrs(vmx);
2a7921b7 7709 debugctlmsr = get_debugctlmsr();
d7cd9796 7710
d462b819 7711 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7712 asm(
6aa8b732 7713 /* Store host registers */
b188c81f
AK		 7714 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7715 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7716 "push %%" _ASM_CX " \n\t"
7717 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7718 "je 1f \n\t"
b188c81f 7719 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7720 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7721 "1: \n\t"
d3edefc0 7722 /* Reload cr2 if changed */
b188c81f
AK		 7723 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7724 "mov %%cr2, %%" _ASM_DX " \n\t"
7725 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7726 "je 2f \n\t"
b188c81f 7727 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7728 "2: \n\t"
6aa8b732 7729 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7730 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7731 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7732 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7733 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7734 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7735 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7736 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7737 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7738#ifdef CONFIG_X86_64
e08aa78a
AK		 7739 "mov %c[r8](%0), %%r8 \n\t"
7740 "mov %c[r9](%0), %%r9 \n\t"
7741 "mov %c[r10](%0), %%r10 \n\t"
7742 "mov %c[r11](%0), %%r11 \n\t"
7743 "mov %c[r12](%0), %%r12 \n\t"
7744 "mov %c[r13](%0), %%r13 \n\t"
7745 "mov %c[r14](%0), %%r14 \n\t"
7746 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7747#endif
b188c81f 7748 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7749
6aa8b732 7750 /* Enter guest mode */
83287ea4 7751 "jne 1f \n\t"
4ecac3fd 7752 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7753 "jmp 2f \n\t"
7754 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7755 "2: "
6aa8b732 7756 /* Save guest registers, load host registers, keep flags */
b188c81f 7757 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7758 "pop %0 \n\t"
b188c81f
AK		 7759 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7760 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7761 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7762 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7763 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7764 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7765 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7766#ifdef CONFIG_X86_64
e08aa78a
AK		 7767 "mov %%r8, %c[r8](%0) \n\t"
7768 "mov %%r9, %c[r9](%0) \n\t"
7769 "mov %%r10, %c[r10](%0) \n\t"
7770 "mov %%r11, %c[r11](%0) \n\t"
7771 "mov %%r12, %c[r12](%0) \n\t"
7772 "mov %%r13, %c[r13](%0) \n\t"
7773 "mov %%r14, %c[r14](%0) \n\t"
7774 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7775#endif
b188c81f
AK		 7776 "mov %%cr2, %%" _ASM_AX " \n\t"
7777 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7778
b188c81f 7779 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7780 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7781 ".pushsection .rodata \n\t"
7782 ".global vmx_return \n\t"
7783 "vmx_return: " _ASM_PTR " 2b \n\t"
7784 ".popsection"
e08aa78a 7785 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7786 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7787 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7788 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7789 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7790 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7791 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7792 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7793 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7794 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7795 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7796#ifdef CONFIG_X86_64
ad312c7c
ZX		 7797 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7798 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7799 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7800 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7801 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7802 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7803 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7804 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7805#endif
40712fae
AK		 7806 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7807 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7808 : "cc", "memory"
7809#ifdef CONFIG_X86_64
b188c81f 7810 , "rax", "rbx", "rdi", "rsi"
c2036300 7811 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7812#else
7813 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7814#endif
7815 );
6aa8b732 7816
2a7921b7
GN		 7817 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7818 if (debugctlmsr)
7819 update_debugctlmsr(debugctlmsr);
7820
aa67f609
AK		 7821#ifndef CONFIG_X86_64
7822 /*
7823 * The sysexit path does not restore ds/es, so we must set them to
7824 * a reasonable value ourselves.
7825 *
7826 * We can't defer this to vmx_load_host_state() since that function
7827 * may be executed in interrupt context, which saves and restore segments
7828 * around it, nullifying its effect.
7829 */
7830 loadsegment(ds, __USER_DS);
7831 loadsegment(es, __USER_DS);
7832#endif
7833
6de4f3ad 7834 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7835 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7836 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7837 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7838 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7839 vcpu->arch.regs_dirty = 0;
7840
1155f76a
AK		 7841 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7842
d462b819 7843 vmx->loaded_vmcs->launched = 1;
1b6269db 7844
51aa01d1 7845 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7846 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7847
e0b890d3
GN		 7848 /*
7849 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7850 * we did not inject a still-pending event to L1 now because of
7851 * nested_run_pending, we need to re-enable this bit.
7852 */
7853 if (vmx->nested.nested_run_pending)
7854 kvm_make_request(KVM_REQ_EVENT, vcpu);
7855
7856 vmx->nested.nested_run_pending = 0;
7857
51aa01d1
AK		 7858 vmx_complete_atomic_exit(vmx);
7859 vmx_recover_nmi_blocking(vmx);
cf393f75 7860 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7861}
7862
4fa7734c
PB		 7863static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7864{
7865 struct vcpu_vmx *vmx = to_vmx(vcpu);
7866 int cpu;
7867
7868 if (vmx->loaded_vmcs == &vmx->vmcs01)
7869 return;
7870
7871 cpu = get_cpu();
7872 vmx->loaded_vmcs = &vmx->vmcs01;
7873 vmx_vcpu_put(vcpu);
7874 vmx_vcpu_load(vcpu, cpu);
7875 vcpu->cpu = cpu;
7876 put_cpu();
7877}
7878
6aa8b732
AK		 7879static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7880{
fb3f0f51
RR		 7881 struct vcpu_vmx *vmx = to_vmx(vcpu);
7882
cdbecfc3 7883 free_vpid(vmx);
4fa7734c
PB		 7884 leave_guest_mode(vcpu);
7885 vmx_load_vmcs01(vcpu);
26a865f4 7886 free_nested(vmx);
4fa7734c 7887 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7888 kfree(vmx->guest_msrs);
7889 kvm_vcpu_uninit(vcpu);
a4770347 7890 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7891}
7892
fb3f0f51 7893static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7894{
fb3f0f51 7895 int err;
c16f862d 7896 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7897 int cpu;
6aa8b732 7898
a2fa3e9f 7899 if (!vmx)
fb3f0f51
RR		 7900 return ERR_PTR(-ENOMEM);
7901
2384d2b3
SY		 7902 allocate_vpid(vmx);
7903
fb3f0f51
RR		 7904 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7905 if (err)
7906 goto free_vcpu;
965b58a5 7907
a2fa3e9f 7908 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 7909 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7910 > PAGE_SIZE);
0123be42 7911
be6d05cf 7912 err = -ENOMEM;
fb3f0f51 7913 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7914 goto uninit_vcpu;
7915 }
965b58a5 7916
d462b819
NHE		 7917 vmx->loaded_vmcs = &vmx->vmcs01;
7918 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7919 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7920 goto free_msrs;
d462b819
NHE		 7921 if (!vmm_exclusive)
7922 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7923 loaded_vmcs_init(vmx->loaded_vmcs);
7924 if (!vmm_exclusive)
7925 kvm_cpu_vmxoff();
a2fa3e9f 7926
15ad7146
AK		 7927 cpu = get_cpu();
7928 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7929 vmx->vcpu.cpu = cpu;
8b9cf98c 7930 err = vmx_vcpu_setup(vmx);
fb3f0f51 7931 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7932 put_cpu();
fb3f0f51
RR		 7933 if (err)
7934 goto free_vmcs;
a63cb560 7935 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7936 err = alloc_apic_access_page(kvm);
7937 if (err)
5e4a0b3c 7938 goto free_vmcs;
a63cb560 7939 }
fb3f0f51 7940
b927a3ce
SY		 7941 if (enable_ept) {
7942 if (!kvm->arch.ept_identity_map_addr)
7943 kvm->arch.ept_identity_map_addr =
7944 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 7945 err = init_rmode_identity_map(kvm);
7946 if (err)
93ea5388 7947 goto free_vmcs;
b927a3ce 7948 }
b7ebfb05 7949
a9d30f33
NHE		 7950 vmx->nested.current_vmptr = -1ull;
7951 vmx->nested.current_vmcs12 = NULL;
7952
fb3f0f51
RR		 7953 return &vmx->vcpu;
7954
7955free_vmcs:
5f3fbc34 7956 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7957free_msrs:
fb3f0f51
RR		 7958 kfree(vmx->guest_msrs);
7959uninit_vcpu:
7960 kvm_vcpu_uninit(&vmx->vcpu);
7961free_vcpu:
cdbecfc3 7962 free_vpid(vmx);
a4770347 7963 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7964 return ERR_PTR(err);
6aa8b732
AK		 7965}
7966
002c7f7c
YS		 7967static void __init vmx_check_processor_compat(void *rtn)
7968{
7969 struct vmcs_config vmcs_conf;
7970
7971 *(int *)rtn = 0;
7972 if (setup_vmcs_config(&vmcs_conf) < 0)
7973 *(int *)rtn = -EIO;
7974 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7975 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7976 smp_processor_id());
7977 *(int *)rtn = -EIO;
7978 }
7979}
7980
67253af5
SY		 7981static int get_ept_level(void)
7982{
7983 return VMX_EPT_DEFAULT_GAW + 1;
7984}
7985
4b12f0de 7986static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7987{
4b12f0de
SY		 7988 u64 ret;
7989
522c68c4
SY		 7990 /* For VT-d and EPT combination
7991 * 1. MMIO: always map as UC
7992 * 2. EPT with VT-d:
7993 * a. VT-d without snooping control feature: can't guarantee the
7994 * result, try to trust guest.
7995 * b. VT-d with snooping control feature: snooping control feature of
7996 * VT-d engine can guarantee the cache correctness. Just set it
7997 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7998 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7999 * consistent with host MTRR
8000 */
4b12f0de
SY		 8001 if (is_mmio)
8002 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 8003 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 8004 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8005 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 8006 else
522c68c4 8007 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 8008 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 8009
8010 return ret;
64d4d521
SY		 8011}
8012
17cc3935 8013static int vmx_get_lpage_level(void)
344f414f 8014{
878403b7
SY		 8015 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8016 return PT_DIRECTORY_LEVEL;
8017 else
8018 /* For shadow and EPT supported 1GB page */
8019 return PT_PDPE_LEVEL;
344f414f
JR		 8020}
8021
0e851880
SY		 8022static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8023{
4e47c7a6
SY		 8024 struct kvm_cpuid_entry2 *best;
8025 struct vcpu_vmx *vmx = to_vmx(vcpu);
8026 u32 exec_control;
8027
8028 vmx->rdtscp_enabled = false;
8029 if (vmx_rdtscp_supported()) {
8030 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8031 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8032 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8033 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8034 vmx->rdtscp_enabled = true;
8035 else {
8036 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8037 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8038 exec_control);
8039 }
8040 }
8041 }
ad756a16 8042
ad756a16
MJ		 8043 /* Exposing INVPCID only when PCID is exposed */
8044 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8045 if (vmx_invpcid_supported() &&
4f977045 8046 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8047 guest_cpuid_has_pcid(vcpu)) {
29282fde 8048 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8049 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8050 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8051 exec_control);
8052 } else {
29282fde
TI		 8053 if (cpu_has_secondary_exec_ctrls()) {
8054 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8055 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8056 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8057 exec_control);
8058 }
ad756a16 8059 if (best)
4f977045 8060 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8061 }
0e851880
SY		 8062}
8063
d4330ef2
JR		 8064static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8065{
7b8050f5
NHE		 8066 if (func == 1 && nested)
8067 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8068}
8069
25d92081
YZ		 8070static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8071 struct x86_exception *fault)
8072{
533558bc
JK		 8073 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8074 u32 exit_reason;
25d92081
YZ		 8075
8076 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8077 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8078 else
533558bc
JK		 8079 exit_reason = EXIT_REASON_EPT_VIOLATION;
8080 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8081 vmcs12->guest_physical_address = fault->address;
8082}
8083
155a97a3
NHE		 8084/* Callbacks for nested_ept_init_mmu_context: */
8085
8086static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8087{
8088 /* return the page table to be shadowed - in our case, EPT12 */
8089 return get_vmcs12(vcpu)->ept_pointer;
8090}
8091
8a3c1a33 8092static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8093{
8a3c1a33 8094 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 8095 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
8096
8097 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8098 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8099 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8100
8101 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8102}
8103
8104static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8105{
8106 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8107}
8108
feaf0c7d
GN		 8109static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8110 struct x86_exception *fault)
8111{
8112 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8113
8114 WARN_ON(!is_guest_mode(vcpu));
8115
8116 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
8117 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 8118 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8119 vmcs_read32(VM_EXIT_INTR_INFO),
8120 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8121 else
8122 kvm_inject_page_fault(vcpu, fault);
8123}
8124
a2bcba50
WL		 8125static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8126 struct vmcs12 *vmcs12)
8127{
8128 struct vcpu_vmx *vmx = to_vmx(vcpu);
8129
8130 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 8131 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 8132 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 8133 return false;
8134
8135 /*
8136 * Translate L1 physical address to host physical
8137 * address for vmcs02. Keep the page pinned, so this
8138 * physical address remains valid. We keep a reference
8139 * to it so we can release it later.
8140 */
8141 if (vmx->nested.apic_access_page) /* shouldn't happen */
8142 nested_release_page(vmx->nested.apic_access_page);
8143 vmx->nested.apic_access_page =
8144 nested_get_page(vcpu, vmcs12->apic_access_addr);
8145 }
a7c0b07d
WL		 8146
8147 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8148 /* TODO: Also verify bits beyond physical address width are 0 */
8149 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8150 return false;
8151
8152 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8153 nested_release_page(vmx->nested.virtual_apic_page);
8154 vmx->nested.virtual_apic_page =
8155 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8156
8157 /*
8158 * Failing the vm entry is _not_ what the processor does
8159 * but it's basically the only possibility we have.
8160 * We could still enter the guest if CR8 load exits are
8161 * enabled, CR8 store exits are enabled, and virtualize APIC
8162 * access is disabled; in this case the processor would never
8163 * use the TPR shadow and we could simply clear the bit from
8164 * the execution control. But such a configuration is useless,
8165 * so let's keep the code simple.
8166 */
8167 if (!vmx->nested.virtual_apic_page)
8168 return false;
8169 }
8170
a2bcba50
WL		 8171 return true;
8172}
8173
f4124500
JK		 8174static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8175{
8176 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8177 struct vcpu_vmx *vmx = to_vmx(vcpu);
8178
8179 if (vcpu->arch.virtual_tsc_khz == 0)
8180 return;
8181
8182 /* Make sure short timeouts reliably trigger an immediate vmexit.
8183 * hrtimer_start does not guarantee this. */
8184 if (preemption_timeout <= 1) {
8185 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8186 return;
8187 }
8188
8189 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8190 preemption_timeout *= 1000000;
8191 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8192 hrtimer_start(&vmx->nested.preemption_timer,
8193 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8194}
8195
fe3ef05c
NHE		 8196/*
8197 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8198 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 8199 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 8200 * guest in a way that will both be appropriate to L1's requests, and our
8201 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8202 * function also has additional necessary side-effects, like setting various
8203 * vcpu->arch fields.
8204 */
8205static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8206{
8207 struct vcpu_vmx *vmx = to_vmx(vcpu);
8208 u32 exec_control;
8209
8210 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8211 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8212 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8213 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8214 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8215 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8216 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8217 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8218 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8219 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8220 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8221 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8222 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8223 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8224 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8225 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8226 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8227 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8228 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8229 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8230 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8231 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8232 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8233 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8234 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8235 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8236 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8237 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8238 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8239 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8240 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8241 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8242 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8243 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8244 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8245 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8246
2996fca0
JK		 8247 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8248 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8249 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8250 } else {
8251 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8252 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8253 }
fe3ef05c
NHE		 8254 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8255 vmcs12->vm_entry_intr_info_field);
8256 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8257 vmcs12->vm_entry_exception_error_code);
8258 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8259 vmcs12->vm_entry_instruction_len);
8260 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8261 vmcs12->guest_interruptibility_info);
fe3ef05c 8262 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8263 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8264 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8265 vmcs12->guest_pending_dbg_exceptions);
8266 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8267 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8268
8269 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8270
f4124500
JK		 8271 exec_control = vmcs12->pin_based_vm_exec_control;
8272 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8273 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8274 PIN_BASED_POSTED_INTR);
f4124500 8275 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8276
f4124500
JK		 8277 vmx->nested.preemption_timer_expired = false;
8278 if (nested_cpu_has_preemption_timer(vmcs12))
8279 vmx_start_preemption_timer(vcpu);
0238ea91 8280
fe3ef05c
NHE		 8281 /*
8282 * Whether page-faults are trapped is determined by a combination of
8283 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8284 * If enable_ept, L0 doesn't care about page faults and we should
8285 * set all of these to L1's desires. However, if !enable_ept, L0 does
8286 * care about (at least some) page faults, and because it is not easy
8287 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8288 * to exit on each and every L2 page fault. This is done by setting
8289 * MASK=MATCH=0 and (see below) EB.PF=1.
8290 * Note that below we don't need special code to set EB.PF beyond the
8291 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8292 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8293 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8294 *
8295 * A problem with this approach (when !enable_ept) is that L1 may be
8296 * injected with more page faults than it asked for. This could have
8297 * caused problems, but in practice existing hypervisors don't care.
8298 * To fix this, we will need to emulate the PFEC checking (on the L1
8299 * page tables), using walk_addr(), when injecting PFs to L1.
8300 */
8301 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8302 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8303 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8304 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8305
8306 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8307 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8308 if (!vmx->rdtscp_enabled)
8309 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8310 /* Take the following fields only from vmcs12 */
696dfd95
PB		 8311 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8312 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8313 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 8314 if (nested_cpu_has(vmcs12,
8315 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8316 exec_control |= vmcs12->secondary_vm_exec_control;
8317
8318 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 8319 /*
8320 * If translation failed, no matter: This feature asks
8321 * to exit when accessing the given address, and if it
8322 * can never be accessed, this feature won't do
8323 * anything anyway.
8324 */
8325 if (!vmx->nested.apic_access_page)
8326 exec_control &=
8327 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8328 else
8329 vmcs_write64(APIC_ACCESS_ADDR,
8330 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 8331 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8332 exec_control |=
8333 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 8334 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 8335 }
8336
8337 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8338 }
8339
8340
8341 /*
8342 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8343 * Some constant fields are set here by vmx_set_constant_host_state().
8344 * Other fields are different per CPU, and will be set later when
8345 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8346 */
a547c6db 8347 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8348
8349 /*
8350 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8351 * entry, but only if the current (host) sp changed from the value
8352 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8353 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8354 * here we just force the write to happen on entry.
8355 */
8356 vmx->host_rsp = 0;
8357
8358 exec_control = vmx_exec_control(vmx); /* L0's desires */
8359 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8360 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8361 exec_control &= ~CPU_BASED_TPR_SHADOW;
8362 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 8363
8364 if (exec_control & CPU_BASED_TPR_SHADOW) {
8365 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8366 page_to_phys(vmx->nested.virtual_apic_page));
8367 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8368 }
8369
fe3ef05c
NHE		 8370 /*
8371 * Merging of IO and MSR bitmaps not currently supported.
8372 * Rather, exit every time.
8373 */
8374 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8375 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8376 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8377
8378 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8379
8380 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8381 * bitwise-or of what L1 wants to trap for L2, and what we want to
8382 * trap. Note that CR0.TS also needs updating - we do this later.
8383 */
8384 update_exception_bitmap(vcpu);
8385 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8386 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8387
8049d651
NHE		 8388 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8389 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8390 * bits are further modified by vmx_set_efer() below.
8391 */
f4124500 8392 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8393
8394 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8395 * emulated by vmx_set_efer(), below.
8396 */
2961e876 8397 vm_entry_controls_init(vmx,
8049d651
NHE		 8398 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8399 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8400 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8401
44811c02 8402 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8403 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8404 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8405 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8406 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8407
8408
8409 set_cr4_guest_host_mask(vmx);
8410
36be0b9d
PB		 8411 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8412 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8413
27fc51b2
NHE		 8414 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8415 vmcs_write64(TSC_OFFSET,
8416 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8417 else
8418 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8419
8420 if (enable_vpid) {
8421 /*
8422 * Trivially support vpid by letting L2s share their parent
8423 * L1's vpid. TODO: move to a more elaborate solution, giving
8424 * each L2 its own vpid and exposing the vpid feature to L1.
8425 */
8426 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8427 vmx_flush_tlb(vcpu);
8428 }
8429
155a97a3
NHE		 8430 if (nested_cpu_has_ept(vmcs12)) {
8431 kvm_mmu_unload(vcpu);
8432 nested_ept_init_mmu_context(vcpu);
8433 }
8434
fe3ef05c
NHE		 8435 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8436 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8437 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8438 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8439 else
8440 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8441 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8442 vmx_set_efer(vcpu, vcpu->arch.efer);
8443
8444 /*
8445 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8446 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8447 * The CR0_READ_SHADOW is what L2 should have expected to read given
8448 * the specifications by L1; It's not enough to take
8449 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8450 * have more bits than L1 expected.
8451 */
8452 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8453 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8454
8455 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8456 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8457
8458 /* shadow page tables on either EPT or shadow page tables */
8459 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8460 kvm_mmu_reset_context(vcpu);
8461
feaf0c7d
GN		 8462 if (!enable_ept)
8463 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8464
3633cfc3
NHE		 8465 /*
8466 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8467 */
8468 if (enable_ept) {
8469 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8470 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8471 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8472 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8473 }
8474
fe3ef05c
NHE		 8475 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8476 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8477}
8478
cd232ad0
NHE		 8479/*
8480 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8481 * for running an L2 nested guest.
8482 */
8483static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8484{
8485 struct vmcs12 *vmcs12;
8486 struct vcpu_vmx *vmx = to_vmx(vcpu);
8487 int cpu;
8488 struct loaded_vmcs *vmcs02;
384bb783 8489 bool ia32e;
cd232ad0
NHE		 8490
8491 if (!nested_vmx_check_permission(vcpu) ||
8492 !nested_vmx_check_vmcs12(vcpu))
8493 return 1;
8494
8495 skip_emulated_instruction(vcpu);
8496 vmcs12 = get_vmcs12(vcpu);
8497
012f83cb
AG		 8498 if (enable_shadow_vmcs)
8499 copy_shadow_to_vmcs12(vmx);
8500
7c177938
NHE		 8501 /*
8502 * The nested entry process starts with enforcing various prerequisites
8503 * on vmcs12 as required by the Intel SDM, and act appropriately when
8504 * they fail: As the SDM explains, some conditions should cause the
8505 * instruction to fail, while others will cause the instruction to seem
8506 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8507 * To speed up the normal (success) code path, we should avoid checking
8508 * for misconfigurations which will anyway be caught by the processor
8509 * when using the merged vmcs02.
8510 */
8511 if (vmcs12->launch_state == launch) {
8512 nested_vmx_failValid(vcpu,
8513 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8514 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8515 return 1;
8516 }
8517
6dfacadd
JK		 8518 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8519 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8520 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8521 return 1;
8522 }
8523
7c177938 8524 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8525 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8526 /*TODO: Also verify bits beyond physical address width are 0*/
8527 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8528 return 1;
8529 }
8530
a2bcba50 8531 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 8532 /*TODO: Also verify bits beyond physical address width are 0*/
8533 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8534 return 1;
8535 }
8536
8537 if (vmcs12->vm_entry_msr_load_count > 0 ||
8538 vmcs12->vm_exit_msr_load_count > 0 ||
8539 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8540 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8541 __func__);
7c177938
NHE		 8542 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8543 return 1;
8544 }
8545
8546 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8547 nested_vmx_true_procbased_ctls_low,
8548 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8549 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8550 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8551 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8552 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8553 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 8554 nested_vmx_true_exit_ctls_low,
8555 nested_vmx_exit_ctls_high) ||
7c177938 8556 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 8557 nested_vmx_true_entry_ctls_low,
8558 nested_vmx_entry_ctls_high))
7c177938
NHE		 8559 {
8560 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8561 return 1;
8562 }
8563
8564 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8565 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8566 nested_vmx_failValid(vcpu,
8567 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8568 return 1;
8569 }
8570
92fbc7b1 8571 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8572 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8573 nested_vmx_entry_failure(vcpu, vmcs12,
8574 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8575 return 1;
8576 }
8577 if (vmcs12->vmcs_link_pointer != -1ull) {
8578 nested_vmx_entry_failure(vcpu, vmcs12,
8579 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8580 return 1;
8581 }
8582
384bb783 8583 /*
cb0c8cda 8584 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8585 * are performed on the field for the IA32_EFER MSR:
8586 * - Bits reserved in the IA32_EFER MSR must be 0.
8587 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8588 * the IA-32e mode guest VM-exit control. It must also be identical
8589 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8590 * CR0.PG) is 1.
8591 */
8592 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8593 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8594 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8595 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8596 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8597 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8598 nested_vmx_entry_failure(vcpu, vmcs12,
8599 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8600 return 1;
8601 }
8602 }
8603
8604 /*
8605 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8606 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8607 * the values of the LMA and LME bits in the field must each be that of
8608 * the host address-space size VM-exit control.
8609 */
8610 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8611 ia32e = (vmcs12->vm_exit_controls &
8612 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8613 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8614 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8615 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8616 nested_vmx_entry_failure(vcpu, vmcs12,
8617 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8618 return 1;
8619 }
8620 }
8621
7c177938
NHE		 8622 /*
8623 * We're finally done with prerequisite checking, and can start with
8624 * the nested entry.
8625 */
8626
cd232ad0
NHE		 8627 vmcs02 = nested_get_current_vmcs02(vmx);
8628 if (!vmcs02)
8629 return -ENOMEM;
8630
8631 enter_guest_mode(vcpu);
8632
8633 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8634
2996fca0
JK		 8635 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8636 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8637
cd232ad0
NHE		 8638 cpu = get_cpu();
8639 vmx->loaded_vmcs = vmcs02;
8640 vmx_vcpu_put(vcpu);
8641 vmx_vcpu_load(vcpu, cpu);
8642 vcpu->cpu = cpu;
8643 put_cpu();
8644
36c3cc42
JK		 8645 vmx_segment_cache_clear(vmx);
8646
cd232ad0
NHE		 8647 vmcs12->launch_state = 1;
8648
8649 prepare_vmcs02(vcpu, vmcs12);
8650
6dfacadd
JK		 8651 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8652 return kvm_emulate_halt(vcpu);
8653
7af40ad3
JK		 8654 vmx->nested.nested_run_pending = 1;
8655
cd232ad0
NHE		 8656 /*
8657 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8658 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8659 * returned as far as L1 is concerned. It will only return (and set
8660 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8661 */
8662 return 1;
8663}
8664
4704d0be
NHE		 8665/*
8666 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8667 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8668 * This function returns the new value we should put in vmcs12.guest_cr0.
8669 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8670 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8671 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8672 * didn't trap the bit, because if L1 did, so would L0).
8673 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8674 * been modified by L2, and L1 knows it. So just leave the old value of
8675 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8676 * isn't relevant, because if L0 traps this bit it can set it to anything.
8677 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8678 * changed these bits, and therefore they need to be updated, but L0
8679 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8680 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8681 */
8682static inline unsigned long
8683vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8684{
8685 return
8686 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8687 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8688 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8689 vcpu->arch.cr0_guest_owned_bits));
8690}
8691
8692static inline unsigned long
8693vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8694{
8695 return
8696 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8697 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8698 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8699 vcpu->arch.cr4_guest_owned_bits));
8700}
8701
5f3d5799
JK		 8702static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8703 struct vmcs12 *vmcs12)
8704{
8705 u32 idt_vectoring;
8706 unsigned int nr;
8707
851eb667 8708 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8709 nr = vcpu->arch.exception.nr;
8710 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8711
8712 if (kvm_exception_is_soft(nr)) {
8713 vmcs12->vm_exit_instruction_len =
8714 vcpu->arch.event_exit_inst_len;
8715 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8716 } else
8717 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8718
8719 if (vcpu->arch.exception.has_error_code) {
8720 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8721 vmcs12->idt_vectoring_error_code =
8722 vcpu->arch.exception.error_code;
8723 }
8724
8725 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8726 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8727 vmcs12->idt_vectoring_info_field =
8728 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8729 } else if (vcpu->arch.interrupt.pending) {
8730 nr = vcpu->arch.interrupt.nr;
8731 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8732
8733 if (vcpu->arch.interrupt.soft) {
8734 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8735 vmcs12->vm_entry_instruction_len =
8736 vcpu->arch.event_exit_inst_len;
8737 } else
8738 idt_vectoring |= INTR_TYPE_EXT_INTR;
8739
8740 vmcs12->idt_vectoring_info_field = idt_vectoring;
8741 }
8742}
8743
b6b8a145
JK		 8744static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8745{
8746 struct vcpu_vmx *vmx = to_vmx(vcpu);
8747
f4124500
JK		 8748 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8749 vmx->nested.preemption_timer_expired) {
8750 if (vmx->nested.nested_run_pending)
8751 return -EBUSY;
8752 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8753 return 0;
8754 }
8755
b6b8a145 8756 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8757 if (vmx->nested.nested_run_pending ||
8758 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8759 return -EBUSY;
8760 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8761 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8762 INTR_INFO_VALID_MASK, 0);
8763 /*
8764 * The NMI-triggered VM exit counts as injection:
8765 * clear this one and block further NMIs.
8766 */
8767 vcpu->arch.nmi_pending = 0;
8768 vmx_set_nmi_mask(vcpu, true);
8769 return 0;
8770 }
8771
8772 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8773 nested_exit_on_intr(vcpu)) {
8774 if (vmx->nested.nested_run_pending)
8775 return -EBUSY;
8776 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8777 }
8778
8779 return 0;
8780}
8781
f4124500
JK		 8782static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8783{
8784 ktime_t remaining =
8785 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8786 u64 value;
8787
8788 if (ktime_to_ns(remaining) <= 0)
8789 return 0;
8790
8791 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8792 do_div(value, 1000000);
8793 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8794}
8795
4704d0be
NHE		 8796/*
8797 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8798 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8799 * and this function updates it to reflect the changes to the guest state while
8800 * L2 was running (and perhaps made some exits which were handled directly by L0
8801 * without going back to L1), and to reflect the exit reason.
8802 * Note that we do not have to copy here all VMCS fields, just those that
8803 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8804 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8805 * which already writes to vmcs12 directly.
8806 */
533558bc
JK		 8807static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8808 u32 exit_reason, u32 exit_intr_info,
8809 unsigned long exit_qualification)
4704d0be
NHE		 8810{
8811 /* update guest state fields: */
8812 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8813 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8814
4704d0be
NHE		 8815 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8816 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8817 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8818
8819 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8820 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8821 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8822 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8823 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8824 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8825 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8826 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8827 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8828 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8829 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8830 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8831 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8832 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8833 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8834 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8835 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8836 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8837 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8838 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8839 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8840 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8841 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8842 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8843 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8844 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8845 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8846 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8847 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8848 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8849 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8850 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8851 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8852 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8853 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8854 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8855
4704d0be
NHE		 8856 vmcs12->guest_interruptibility_info =
8857 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8858 vmcs12->guest_pending_dbg_exceptions =
8859 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8860 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8861 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8862 else
8863 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8864
f4124500
JK		 8865 if (nested_cpu_has_preemption_timer(vmcs12)) {
8866 if (vmcs12->vm_exit_controls &
8867 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8868 vmcs12->vmx_preemption_timer_value =
8869 vmx_get_preemption_timer_value(vcpu);
8870 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8871 }
7854cbca 8872
3633cfc3
NHE		 8873 /*
8874 * In some cases (usually, nested EPT), L2 is allowed to change its
8875 * own CR3 without exiting. If it has changed it, we must keep it.
8876 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8877 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8878 *
8879 * Additionally, restore L2's PDPTR to vmcs12.
8880 */
8881 if (enable_ept) {
8882 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8883 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8884 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8885 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8886 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8887 }
8888
c18911a2
JK		 8889 vmcs12->vm_entry_controls =
8890 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8891 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8892
2996fca0
JK		 8893 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8894 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8895 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8896 }
8897
4704d0be
NHE		 8898 /* TODO: These cannot have changed unless we have MSR bitmaps and
8899 * the relevant bit asks not to trap the change */
b8c07d55 8900 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8901 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8902 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8903 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8904 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8905 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8906 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8907 if (vmx_mpx_supported())
8908 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8909
8910 /* update exit information fields: */
8911
533558bc
JK		 8912 vmcs12->vm_exit_reason = exit_reason;
8913 vmcs12->exit_qualification = exit_qualification;
4704d0be 8914
533558bc 8915 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8916 if ((vmcs12->vm_exit_intr_info &
8917 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8918 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8919 vmcs12->vm_exit_intr_error_code =
8920 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8921 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8922 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8923 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8924
5f3d5799
JK		 8925 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8926 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8927 * instead of reading the real value. */
4704d0be 8928 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8929
8930 /*
8931 * Transfer the event that L0 or L1 may wanted to inject into
8932 * L2 to IDT_VECTORING_INFO_FIELD.
8933 */
8934 vmcs12_save_pending_event(vcpu, vmcs12);
8935 }
8936
8937 /*
8938 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8939 * preserved above and would only end up incorrectly in L1.
8940 */
8941 vcpu->arch.nmi_injected = false;
8942 kvm_clear_exception_queue(vcpu);
8943 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8944}
8945
8946/*
8947 * A part of what we need to when the nested L2 guest exits and we want to
8948 * run its L1 parent, is to reset L1's guest state to the host state specified
8949 * in vmcs12.
8950 * This function is to be called not only on normal nested exit, but also on
8951 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8952 * Failures During or After Loading Guest State").
8953 * This function should be called when the active VMCS is L1's (vmcs01).
8954 */
733568f9
JK		 8955static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8956 struct vmcs12 *vmcs12)
4704d0be 8957{
21feb4eb
ACL		 8958 struct kvm_segment seg;
8959
4704d0be
NHE		 8960 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8961 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8962 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8963 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8964 else
8965 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8966 vmx_set_efer(vcpu, vcpu->arch.efer);
8967
8968 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8969 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8970 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8971 /*
8972 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8973 * actually changed, because it depends on the current state of
8974 * fpu_active (which may have changed).
8975 * Note that vmx_set_cr0 refers to efer set above.
8976 */
9e3e4dbf 8977 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8978 /*
8979 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8980 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8981 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8982 */
8983 update_exception_bitmap(vcpu);
8984 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8985 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8986
8987 /*
8988 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8989 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8990 */
8991 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8992 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8993
29bf08f1 8994 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8995
4704d0be
NHE		 8996 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8997 kvm_mmu_reset_context(vcpu);
8998
feaf0c7d
GN		 8999 if (!enable_ept)
9000 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9001
4704d0be
NHE		 9002 if (enable_vpid) {
9003 /*
9004 * Trivially support vpid by letting L2s share their parent
9005 * L1's vpid. TODO: move to a more elaborate solution, giving
9006 * each L2 its own vpid and exposing the vpid feature to L1.
9007 */
9008 vmx_flush_tlb(vcpu);
9009 }
9010
9011
9012 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9013 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9014 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9015 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9016 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 9017
36be0b9d
PB		 9018 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9019 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9020 vmcs_write64(GUEST_BNDCFGS, 0);
9021
44811c02 9022 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 9023 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 9024 vcpu->arch.pat = vmcs12->host_ia32_pat;
9025 }
4704d0be
NHE		 9026 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9027 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9028 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 9029
21feb4eb
ACL		 9030 /* Set L1 segment info according to Intel SDM
9031 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9032 seg = (struct kvm_segment) {
9033 .base = 0,
9034 .limit = 0xFFFFFFFF,
9035 .selector = vmcs12->host_cs_selector,
9036 .type = 11,
9037 .present = 1,
9038 .s = 1,
9039 .g = 1
9040 };
9041 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9042 seg.l = 1;
9043 else
9044 seg.db = 1;
9045 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9046 seg = (struct kvm_segment) {
9047 .base = 0,
9048 .limit = 0xFFFFFFFF,
9049 .type = 3,
9050 .present = 1,
9051 .s = 1,
9052 .db = 1,
9053 .g = 1
9054 };
9055 seg.selector = vmcs12->host_ds_selector;
9056 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9057 seg.selector = vmcs12->host_es_selector;
9058 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9059 seg.selector = vmcs12->host_ss_selector;
9060 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9061 seg.selector = vmcs12->host_fs_selector;
9062 seg.base = vmcs12->host_fs_base;
9063 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9064 seg.selector = vmcs12->host_gs_selector;
9065 seg.base = vmcs12->host_gs_base;
9066 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9067 seg = (struct kvm_segment) {
205befd9 9068 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 9069 .limit = 0x67,
9070 .selector = vmcs12->host_tr_selector,
9071 .type = 11,
9072 .present = 1
9073 };
9074 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9075
503cd0c5
JK		 9076 kvm_set_dr(vcpu, 7, 0x400);
9077 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 9078}
9079
9080/*
9081 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9082 * and modify vmcs12 to make it see what it would expect to see there if
9083 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9084 */
533558bc
JK		 9085static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9086 u32 exit_intr_info,
9087 unsigned long exit_qualification)
4704d0be
NHE		 9088{
9089 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 9090 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9091
5f3d5799
JK		 9092 /* trying to cancel vmlaunch/vmresume is a bug */
9093 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9094
4704d0be 9095 leave_guest_mode(vcpu);
533558bc
JK		 9096 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9097 exit_qualification);
4704d0be 9098
f3380ca5
WL		 9099 vmx_load_vmcs01(vcpu);
9100
77b0f5d6
BD		 9101 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9102 && nested_exit_intr_ack_set(vcpu)) {
9103 int irq = kvm_cpu_get_interrupt(vcpu);
9104 WARN_ON(irq < 0);
9105 vmcs12->vm_exit_intr_info = irq |
9106 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9107 }
9108
542060ea
JK		 9109 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9110 vmcs12->exit_qualification,
9111 vmcs12->idt_vectoring_info_field,
9112 vmcs12->vm_exit_intr_info,
9113 vmcs12->vm_exit_intr_error_code,
9114 KVM_ISA_VMX);
4704d0be 9115
2961e876
GN		 9116 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
9117 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 9118 vmx_segment_cache_clear(vmx);
9119
4704d0be
NHE		 9120 /* if no vmcs02 cache requested, remove the one we used */
9121 if (VMCS02_POOL_SIZE == 0)
9122 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
9123
9124 load_vmcs12_host_state(vcpu, vmcs12);
9125
27fc51b2 9126 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 9127 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9128
9129 /* This is needed for same reason as it was needed in prepare_vmcs02 */
9130 vmx->host_rsp = 0;
9131
9132 /* Unpin physical memory we referred to in vmcs02 */
9133 if (vmx->nested.apic_access_page) {
9134 nested_release_page(vmx->nested.apic_access_page);
48d89b92 9135 vmx->nested.apic_access_page = NULL;
4704d0be 9136 }
a7c0b07d
WL		 9137 if (vmx->nested.virtual_apic_page) {
9138 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 9139 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 9140 }
4704d0be 9141
38b99173
TC		 9142 /*
9143 * We are now running in L2, mmu_notifier will force to reload the
9144 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9145 */
9146 kvm_vcpu_reload_apic_access_page(vcpu);
9147
4704d0be
NHE		 9148 /*
9149 * Exiting from L2 to L1, we're now back to L1 which thinks it just
9150 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9151 * success or failure flag accordingly.
9152 */
9153 if (unlikely(vmx->fail)) {
9154 vmx->fail = 0;
9155 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
9156 } else
9157 nested_vmx_succeed(vcpu);
012f83cb
AG		 9158 if (enable_shadow_vmcs)
9159 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 9160
9161 /* in case we halted in L2 */
9162 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 9163}
9164
42124925
JK		 9165/*
9166 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9167 */
9168static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9169{
9170 if (is_guest_mode(vcpu))
533558bc 9171 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 9172 free_nested(to_vmx(vcpu));
9173}
9174
7c177938
NHE		 9175/*
9176 * L1's failure to enter L2 is a subset of a normal exit, as explained in
9177 * 23.7 "VM-entry failures during or after loading guest state" (this also
9178 * lists the acceptable exit-reason and exit-qualification parameters).
9179 * It should only be called before L2 actually succeeded to run, and when
9180 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9181 */
9182static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9183 struct vmcs12 *vmcs12,
9184 u32 reason, unsigned long qualification)
9185{
9186 load_vmcs12_host_state(vcpu, vmcs12);
9187 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9188 vmcs12->exit_qualification = qualification;
9189 nested_vmx_succeed(vcpu);
012f83cb
AG		 9190 if (enable_shadow_vmcs)
9191 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 9192}
9193
8a76d7f2
JR		 9194static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9195 struct x86_instruction_info *info,
9196 enum x86_intercept_stage stage)
9197{
9198 return X86EMUL_CONTINUE;
9199}
9200
48d89b92 9201static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 9202{
b4a2d31d
RK		 9203 if (ple_gap)
9204 shrink_ple_window(vcpu);
ae97a3b8
RK		 9205}
9206
cbdd1bea 9207static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 9208 .cpu_has_kvm_support = cpu_has_kvm_support,
9209 .disabled_by_bios = vmx_disabled_by_bios,
9210 .hardware_setup = hardware_setup,
9211 .hardware_unsetup = hardware_unsetup,
002c7f7c 9212 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 9213 .hardware_enable = hardware_enable,
9214 .hardware_disable = hardware_disable,
04547156 9215 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 9216
9217 .vcpu_create = vmx_create_vcpu,
9218 .vcpu_free = vmx_free_vcpu,
04d2cc77 9219 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 9220
04d2cc77 9221 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 9222 .vcpu_load = vmx_vcpu_load,
9223 .vcpu_put = vmx_vcpu_put,
9224
c8639010 9225 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 9226 .get_msr = vmx_get_msr,
9227 .set_msr = vmx_set_msr,
9228 .get_segment_base = vmx_get_segment_base,
9229 .get_segment = vmx_get_segment,
9230 .set_segment = vmx_set_segment,
2e4d2653 9231 .get_cpl = vmx_get_cpl,
6aa8b732 9232 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 9233 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 9234 .decache_cr3 = vmx_decache_cr3,
25c4c276 9235 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 9236 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 9237 .set_cr3 = vmx_set_cr3,
9238 .set_cr4 = vmx_set_cr4,
6aa8b732 9239 .set_efer = vmx_set_efer,
6aa8b732
AK		 9240 .get_idt = vmx_get_idt,
9241 .set_idt = vmx_set_idt,
9242 .get_gdt = vmx_get_gdt,
9243 .set_gdt = vmx_set_gdt,
73aaf249
JK		 9244 .get_dr6 = vmx_get_dr6,
9245 .set_dr6 = vmx_set_dr6,
020df079 9246 .set_dr7 = vmx_set_dr7,
81908bf4 9247 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 9248 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 9249 .get_rflags = vmx_get_rflags,
9250 .set_rflags = vmx_set_rflags,
02daab21 9251 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 9252
9253 .tlb_flush = vmx_flush_tlb,
6aa8b732 9254
6aa8b732 9255 .run = vmx_vcpu_run,
6062d012 9256 .handle_exit = vmx_handle_exit,
6aa8b732 9257 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 9258 .set_interrupt_shadow = vmx_set_interrupt_shadow,
9259 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 9260 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 9261 .set_irq = vmx_inject_irq,
95ba8273 9262 .set_nmi = vmx_inject_nmi,
298101da 9263 .queue_exception = vmx_queue_exception,
b463a6f7 9264 .cancel_injection = vmx_cancel_injection,
78646121 9265 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 9266 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 9267 .get_nmi_mask = vmx_get_nmi_mask,
9268 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 9269 .enable_nmi_window = enable_nmi_window,
9270 .enable_irq_window = enable_irq_window,
9271 .update_cr8_intercept = update_cr8_intercept,
8d14695f 9272 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 9273 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 9274 .vm_has_apicv = vmx_vm_has_apicv,
9275 .load_eoi_exitmap = vmx_load_eoi_exitmap,
9276 .hwapic_irr_update = vmx_hwapic_irr_update,
9277 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 9278 .sync_pir_to_irr = vmx_sync_pir_to_irr,
9279 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 9280
cbc94022 9281 .set_tss_addr = vmx_set_tss_addr,
67253af5 9282 .get_tdp_level = get_ept_level,
4b12f0de 9283 .get_mt_mask = vmx_get_mt_mask,
229456fc 9284
586f9607 9285 .get_exit_info = vmx_get_exit_info,
586f9607 9286
17cc3935 9287 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 9288
9289 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 9290
9291 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 9292 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 9293
9294 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 9295
9296 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 9297
4051b188 9298 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 9299 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 9300 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 9301 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 9302 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 9303 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 9304
9305 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 9306
9307 .check_intercept = vmx_check_intercept,
a547c6db 9308 .handle_external_intr = vmx_handle_external_intr,
da8999d3 9309 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 9310
9311 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 9312
9313 .sched_in = vmx_sched_in,
6aa8b732
AK		 9314};
9315
9316static int __init vmx_init(void)
9317{
34a1cd60
TC		 9318 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9319 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9320 if (r)
34a1cd60 9321 return r;
25c5f225 9322
8f536b76
ZY		 9323#ifdef CONFIG_KEXEC
9324 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9325 crash_vmclear_local_loaded_vmcss);
9326#endif
9327
fdef3ad1 9328 return 0;
6aa8b732
AK		 9329}
9330
9331static void __exit vmx_exit(void)
9332{
8f536b76 9333#ifdef CONFIG_KEXEC
3b63a43f 9334 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 9335 synchronize_rcu();
9336#endif
9337
cb498ea2 9338 kvm_exit();
6aa8b732
AK		 9339}
9340
9341module_init(vmx_init)
9342module_exit(vmx_exit)
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