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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
00b27a3e | 21 | #include "cpuid.h" |
d62caabb | 22 | #include "lapic.h" |
e495606d | 23 | |
edf88417 | 24 | #include <linux/kvm_host.h> |
6aa8b732 | 25 | #include <linux/module.h> |
9d8f549d | 26 | #include <linux/kernel.h> |
6aa8b732 AK |
27 | #include <linux/mm.h> |
28 | #include <linux/highmem.h> | |
e8edc6e0 | 29 | #include <linux/sched.h> |
c7addb90 | 30 | #include <linux/moduleparam.h> |
e9bda3b3 | 31 | #include <linux/mod_devicetable.h> |
af658dca | 32 | #include <linux/trace_events.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
cafd6659 | 34 | #include <linux/tboot.h> |
f4124500 | 35 | #include <linux/hrtimer.h> |
c207aee4 | 36 | #include <linux/frame.h> |
5fdbf976 | 37 | #include "kvm_cache_regs.h" |
35920a35 | 38 | #include "x86.h" |
e495606d | 39 | |
28b835d6 | 40 | #include <asm/cpu.h> |
6aa8b732 | 41 | #include <asm/io.h> |
3b3be0d1 | 42 | #include <asm/desc.h> |
13673a90 | 43 | #include <asm/vmx.h> |
6210e37b | 44 | #include <asm/virtext.h> |
a0861c02 | 45 | #include <asm/mce.h> |
952f07ec | 46 | #include <asm/fpu/internal.h> |
d7cd9796 | 47 | #include <asm/perf_event.h> |
81908bf4 | 48 | #include <asm/debugreg.h> |
8f536b76 | 49 | #include <asm/kexec.h> |
dab2087d | 50 | #include <asm/apic.h> |
efc64404 | 51 | #include <asm/irq_remapping.h> |
d6e41f11 | 52 | #include <asm/mmu_context.h> |
6aa8b732 | 53 | |
229456fc | 54 | #include "trace.h" |
25462f7f | 55 | #include "pmu.h" |
229456fc | 56 | |
4ecac3fd | 57 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
5e520e62 AK |
58 | #define __ex_clear(x, reg) \ |
59 | ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) | |
4ecac3fd | 60 | |
6aa8b732 AK |
61 | MODULE_AUTHOR("Qumranet"); |
62 | MODULE_LICENSE("GPL"); | |
63 | ||
e9bda3b3 JT |
64 | static const struct x86_cpu_id vmx_cpu_id[] = { |
65 | X86_FEATURE_MATCH(X86_FEATURE_VMX), | |
66 | {} | |
67 | }; | |
68 | MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); | |
69 | ||
476bc001 | 70 | static bool __read_mostly enable_vpid = 1; |
736caefe | 71 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 72 | |
476bc001 | 73 | static bool __read_mostly flexpriority_enabled = 1; |
736caefe | 74 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 75 | |
476bc001 | 76 | static bool __read_mostly enable_ept = 1; |
736caefe | 77 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 78 | |
476bc001 | 79 | static bool __read_mostly enable_unrestricted_guest = 1; |
3a624e29 NK |
80 | module_param_named(unrestricted_guest, |
81 | enable_unrestricted_guest, bool, S_IRUGO); | |
82 | ||
83c3a331 XH |
83 | static bool __read_mostly enable_ept_ad_bits = 1; |
84 | module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); | |
85 | ||
a27685c3 | 86 | static bool __read_mostly emulate_invalid_guest_state = true; |
c1f8bc04 | 87 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 88 | |
476bc001 | 89 | static bool __read_mostly fasteoi = 1; |
58fbbf26 KT |
90 | module_param(fasteoi, bool, S_IRUGO); |
91 | ||
5a71785d | 92 | static bool __read_mostly enable_apicv = 1; |
01e439be | 93 | module_param(enable_apicv, bool, S_IRUGO); |
83d4c286 | 94 | |
abc4fc58 AG |
95 | static bool __read_mostly enable_shadow_vmcs = 1; |
96 | module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); | |
801d3424 NHE |
97 | /* |
98 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
99 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
100 | * use VMX instructions. | |
101 | */ | |
476bc001 | 102 | static bool __read_mostly nested = 0; |
801d3424 NHE |
103 | module_param(nested, bool, S_IRUGO); |
104 | ||
20300099 WL |
105 | static u64 __read_mostly host_xss; |
106 | ||
843e4330 KH |
107 | static bool __read_mostly enable_pml = 1; |
108 | module_param_named(pml, enable_pml, bool, S_IRUGO); | |
109 | ||
64903d61 HZ |
110 | #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL |
111 | ||
64672c95 YJ |
112 | /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ |
113 | static int __read_mostly cpu_preemption_timer_multi; | |
114 | static bool __read_mostly enable_preemption_timer = 1; | |
115 | #ifdef CONFIG_X86_64 | |
116 | module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); | |
117 | #endif | |
118 | ||
5037878e GN |
119 | #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD) |
120 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE) | |
cdc0e244 AK |
121 | #define KVM_VM_CR0_ALWAYS_ON \ |
122 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
123 | #define KVM_CR4_GUEST_OWNED_BITS \ |
124 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
fd8cb433 | 125 | | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) |
4c38609a | 126 | |
cdc0e244 AK |
127 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
128 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
129 | ||
78ac8b47 AK |
130 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
131 | ||
f4124500 JK |
132 | #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 |
133 | ||
16c2aec6 JD |
134 | /* |
135 | * Hyper-V requires all of these, so mark them as supported even though | |
136 | * they are just treated the same as all-context. | |
137 | */ | |
138 | #define VMX_VPID_EXTENT_SUPPORTED_MASK \ | |
139 | (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \ | |
140 | VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \ | |
141 | VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \ | |
142 | VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT) | |
143 | ||
4b8d54f9 ZE |
144 | /* |
145 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
146 | * ple_gap: upper bound on the amount of time between two successive | |
147 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 148 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
149 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
150 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
151 | * less than 2^12 cycles | |
152 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
153 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
154 | */ | |
b4a2d31d RK |
155 | #define KVM_VMX_DEFAULT_PLE_GAP 128 |
156 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 | |
157 | #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2 | |
158 | #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0 | |
159 | #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \ | |
160 | INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW | |
161 | ||
4b8d54f9 ZE |
162 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; |
163 | module_param(ple_gap, int, S_IRUGO); | |
164 | ||
165 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
166 | module_param(ple_window, int, S_IRUGO); | |
167 | ||
b4a2d31d RK |
168 | /* Default doubles per-vcpu window every exit. */ |
169 | static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW; | |
170 | module_param(ple_window_grow, int, S_IRUGO); | |
171 | ||
172 | /* Default resets per-vcpu window every exit to ple_window. */ | |
173 | static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK; | |
174 | module_param(ple_window_shrink, int, S_IRUGO); | |
175 | ||
176 | /* Default is to compute the maximum so we can never overflow. */ | |
177 | static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
178 | static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
179 | module_param(ple_window_max, int, S_IRUGO); | |
180 | ||
83287ea4 AK |
181 | extern const ulong vmx_return; |
182 | ||
8bf00a52 | 183 | #define NR_AUTOLOAD_MSRS 8 |
ff2f6fe9 | 184 | #define VMCS02_POOL_SIZE 1 |
61d2ef2c | 185 | |
a2fa3e9f GH |
186 | struct vmcs { |
187 | u32 revision_id; | |
188 | u32 abort; | |
189 | char data[0]; | |
190 | }; | |
191 | ||
d462b819 NHE |
192 | /* |
193 | * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also | |
194 | * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs | |
195 | * loaded on this CPU (so we can clear them if the CPU goes down). | |
196 | */ | |
197 | struct loaded_vmcs { | |
198 | struct vmcs *vmcs; | |
355f4fb1 | 199 | struct vmcs *shadow_vmcs; |
d462b819 | 200 | int cpu; |
4c4a6f79 PB |
201 | bool launched; |
202 | bool nmi_known_unmasked; | |
44889942 LP |
203 | unsigned long vmcs_host_cr3; /* May not match real cr3 */ |
204 | unsigned long vmcs_host_cr4; /* May not match real cr4 */ | |
d462b819 NHE |
205 | struct list_head loaded_vmcss_on_cpu_link; |
206 | }; | |
207 | ||
26bb0981 AK |
208 | struct shared_msr_entry { |
209 | unsigned index; | |
210 | u64 data; | |
d5696725 | 211 | u64 mask; |
26bb0981 AK |
212 | }; |
213 | ||
a9d30f33 NHE |
214 | /* |
215 | * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a | |
216 | * single nested guest (L2), hence the name vmcs12. Any VMX implementation has | |
217 | * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is | |
218 | * stored in guest memory specified by VMPTRLD, but is opaque to the guest, | |
219 | * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. | |
220 | * More than one of these structures may exist, if L1 runs multiple L2 guests. | |
221 | * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the | |
222 | * underlying hardware which will be used to run L2. | |
223 | * This structure is packed to ensure that its layout is identical across | |
224 | * machines (necessary for live migration). | |
225 | * If there are changes in this struct, VMCS12_REVISION must be changed. | |
226 | */ | |
22bd0358 | 227 | typedef u64 natural_width; |
a9d30f33 NHE |
228 | struct __packed vmcs12 { |
229 | /* According to the Intel spec, a VMCS region must start with the | |
230 | * following two fields. Then follow implementation-specific data. | |
231 | */ | |
232 | u32 revision_id; | |
233 | u32 abort; | |
22bd0358 | 234 | |
27d6c865 NHE |
235 | u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ |
236 | u32 padding[7]; /* room for future expansion */ | |
237 | ||
22bd0358 NHE |
238 | u64 io_bitmap_a; |
239 | u64 io_bitmap_b; | |
240 | u64 msr_bitmap; | |
241 | u64 vm_exit_msr_store_addr; | |
242 | u64 vm_exit_msr_load_addr; | |
243 | u64 vm_entry_msr_load_addr; | |
244 | u64 tsc_offset; | |
245 | u64 virtual_apic_page_addr; | |
246 | u64 apic_access_addr; | |
705699a1 | 247 | u64 posted_intr_desc_addr; |
27c42a1b | 248 | u64 vm_function_control; |
22bd0358 | 249 | u64 ept_pointer; |
608406e2 WV |
250 | u64 eoi_exit_bitmap0; |
251 | u64 eoi_exit_bitmap1; | |
252 | u64 eoi_exit_bitmap2; | |
253 | u64 eoi_exit_bitmap3; | |
41ab9372 | 254 | u64 eptp_list_address; |
81dc01f7 | 255 | u64 xss_exit_bitmap; |
22bd0358 NHE |
256 | u64 guest_physical_address; |
257 | u64 vmcs_link_pointer; | |
c5f983f6 | 258 | u64 pml_address; |
22bd0358 NHE |
259 | u64 guest_ia32_debugctl; |
260 | u64 guest_ia32_pat; | |
261 | u64 guest_ia32_efer; | |
262 | u64 guest_ia32_perf_global_ctrl; | |
263 | u64 guest_pdptr0; | |
264 | u64 guest_pdptr1; | |
265 | u64 guest_pdptr2; | |
266 | u64 guest_pdptr3; | |
36be0b9d | 267 | u64 guest_bndcfgs; |
22bd0358 NHE |
268 | u64 host_ia32_pat; |
269 | u64 host_ia32_efer; | |
270 | u64 host_ia32_perf_global_ctrl; | |
271 | u64 padding64[8]; /* room for future expansion */ | |
272 | /* | |
273 | * To allow migration of L1 (complete with its L2 guests) between | |
274 | * machines of different natural widths (32 or 64 bit), we cannot have | |
275 | * unsigned long fields with no explict size. We use u64 (aliased | |
276 | * natural_width) instead. Luckily, x86 is little-endian. | |
277 | */ | |
278 | natural_width cr0_guest_host_mask; | |
279 | natural_width cr4_guest_host_mask; | |
280 | natural_width cr0_read_shadow; | |
281 | natural_width cr4_read_shadow; | |
282 | natural_width cr3_target_value0; | |
283 | natural_width cr3_target_value1; | |
284 | natural_width cr3_target_value2; | |
285 | natural_width cr3_target_value3; | |
286 | natural_width exit_qualification; | |
287 | natural_width guest_linear_address; | |
288 | natural_width guest_cr0; | |
289 | natural_width guest_cr3; | |
290 | natural_width guest_cr4; | |
291 | natural_width guest_es_base; | |
292 | natural_width guest_cs_base; | |
293 | natural_width guest_ss_base; | |
294 | natural_width guest_ds_base; | |
295 | natural_width guest_fs_base; | |
296 | natural_width guest_gs_base; | |
297 | natural_width guest_ldtr_base; | |
298 | natural_width guest_tr_base; | |
299 | natural_width guest_gdtr_base; | |
300 | natural_width guest_idtr_base; | |
301 | natural_width guest_dr7; | |
302 | natural_width guest_rsp; | |
303 | natural_width guest_rip; | |
304 | natural_width guest_rflags; | |
305 | natural_width guest_pending_dbg_exceptions; | |
306 | natural_width guest_sysenter_esp; | |
307 | natural_width guest_sysenter_eip; | |
308 | natural_width host_cr0; | |
309 | natural_width host_cr3; | |
310 | natural_width host_cr4; | |
311 | natural_width host_fs_base; | |
312 | natural_width host_gs_base; | |
313 | natural_width host_tr_base; | |
314 | natural_width host_gdtr_base; | |
315 | natural_width host_idtr_base; | |
316 | natural_width host_ia32_sysenter_esp; | |
317 | natural_width host_ia32_sysenter_eip; | |
318 | natural_width host_rsp; | |
319 | natural_width host_rip; | |
320 | natural_width paddingl[8]; /* room for future expansion */ | |
321 | u32 pin_based_vm_exec_control; | |
322 | u32 cpu_based_vm_exec_control; | |
323 | u32 exception_bitmap; | |
324 | u32 page_fault_error_code_mask; | |
325 | u32 page_fault_error_code_match; | |
326 | u32 cr3_target_count; | |
327 | u32 vm_exit_controls; | |
328 | u32 vm_exit_msr_store_count; | |
329 | u32 vm_exit_msr_load_count; | |
330 | u32 vm_entry_controls; | |
331 | u32 vm_entry_msr_load_count; | |
332 | u32 vm_entry_intr_info_field; | |
333 | u32 vm_entry_exception_error_code; | |
334 | u32 vm_entry_instruction_len; | |
335 | u32 tpr_threshold; | |
336 | u32 secondary_vm_exec_control; | |
337 | u32 vm_instruction_error; | |
338 | u32 vm_exit_reason; | |
339 | u32 vm_exit_intr_info; | |
340 | u32 vm_exit_intr_error_code; | |
341 | u32 idt_vectoring_info_field; | |
342 | u32 idt_vectoring_error_code; | |
343 | u32 vm_exit_instruction_len; | |
344 | u32 vmx_instruction_info; | |
345 | u32 guest_es_limit; | |
346 | u32 guest_cs_limit; | |
347 | u32 guest_ss_limit; | |
348 | u32 guest_ds_limit; | |
349 | u32 guest_fs_limit; | |
350 | u32 guest_gs_limit; | |
351 | u32 guest_ldtr_limit; | |
352 | u32 guest_tr_limit; | |
353 | u32 guest_gdtr_limit; | |
354 | u32 guest_idtr_limit; | |
355 | u32 guest_es_ar_bytes; | |
356 | u32 guest_cs_ar_bytes; | |
357 | u32 guest_ss_ar_bytes; | |
358 | u32 guest_ds_ar_bytes; | |
359 | u32 guest_fs_ar_bytes; | |
360 | u32 guest_gs_ar_bytes; | |
361 | u32 guest_ldtr_ar_bytes; | |
362 | u32 guest_tr_ar_bytes; | |
363 | u32 guest_interruptibility_info; | |
364 | u32 guest_activity_state; | |
365 | u32 guest_sysenter_cs; | |
366 | u32 host_ia32_sysenter_cs; | |
0238ea91 JK |
367 | u32 vmx_preemption_timer_value; |
368 | u32 padding32[7]; /* room for future expansion */ | |
22bd0358 | 369 | u16 virtual_processor_id; |
705699a1 | 370 | u16 posted_intr_nv; |
22bd0358 NHE |
371 | u16 guest_es_selector; |
372 | u16 guest_cs_selector; | |
373 | u16 guest_ss_selector; | |
374 | u16 guest_ds_selector; | |
375 | u16 guest_fs_selector; | |
376 | u16 guest_gs_selector; | |
377 | u16 guest_ldtr_selector; | |
378 | u16 guest_tr_selector; | |
608406e2 | 379 | u16 guest_intr_status; |
c5f983f6 | 380 | u16 guest_pml_index; |
22bd0358 NHE |
381 | u16 host_es_selector; |
382 | u16 host_cs_selector; | |
383 | u16 host_ss_selector; | |
384 | u16 host_ds_selector; | |
385 | u16 host_fs_selector; | |
386 | u16 host_gs_selector; | |
387 | u16 host_tr_selector; | |
a9d30f33 NHE |
388 | }; |
389 | ||
390 | /* | |
391 | * VMCS12_REVISION is an arbitrary id that should be changed if the content or | |
392 | * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and | |
393 | * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. | |
394 | */ | |
395 | #define VMCS12_REVISION 0x11e57ed0 | |
396 | ||
397 | /* | |
398 | * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region | |
399 | * and any VMCS region. Although only sizeof(struct vmcs12) are used by the | |
400 | * current implementation, 4K are reserved to avoid future complications. | |
401 | */ | |
402 | #define VMCS12_SIZE 0x1000 | |
403 | ||
ff2f6fe9 NHE |
404 | /* Used to remember the last vmcs02 used for some recently used vmcs12s */ |
405 | struct vmcs02_list { | |
406 | struct list_head list; | |
407 | gpa_t vmptr; | |
408 | struct loaded_vmcs vmcs02; | |
409 | }; | |
410 | ||
ec378aee NHE |
411 | /* |
412 | * The nested_vmx structure is part of vcpu_vmx, and holds information we need | |
413 | * for correct emulation of VMX (i.e., nested VMX) on this vcpu. | |
414 | */ | |
415 | struct nested_vmx { | |
416 | /* Has the level1 guest done vmxon? */ | |
417 | bool vmxon; | |
3573e22c | 418 | gpa_t vmxon_ptr; |
c5f983f6 | 419 | bool pml_full; |
a9d30f33 NHE |
420 | |
421 | /* The guest-physical address of the current VMCS L1 keeps for L2 */ | |
422 | gpa_t current_vmptr; | |
4f2777bc DM |
423 | /* |
424 | * Cache of the guest's VMCS, existing outside of guest memory. | |
425 | * Loaded from guest memory during VMPTRLD. Flushed to guest | |
8ca44e88 | 426 | * memory during VMCLEAR and VMPTRLD. |
4f2777bc DM |
427 | */ |
428 | struct vmcs12 *cached_vmcs12; | |
012f83cb AG |
429 | /* |
430 | * Indicates if the shadow vmcs must be updated with the | |
431 | * data hold by vmcs12 | |
432 | */ | |
433 | bool sync_shadow_vmcs; | |
ff2f6fe9 NHE |
434 | |
435 | /* vmcs02_list cache of VMCSs recently used to run L2 guests */ | |
436 | struct list_head vmcs02_pool; | |
437 | int vmcs02_num; | |
dccbfcf5 | 438 | bool change_vmcs01_virtual_x2apic_mode; |
644d711a NHE |
439 | /* L2 must run next, and mustn't decide to exit to L1. */ |
440 | bool nested_run_pending; | |
fe3ef05c NHE |
441 | /* |
442 | * Guest pages referred to in vmcs02 with host-physical pointers, so | |
443 | * we must keep them pinned while L2 runs. | |
444 | */ | |
445 | struct page *apic_access_page; | |
a7c0b07d | 446 | struct page *virtual_apic_page; |
705699a1 WV |
447 | struct page *pi_desc_page; |
448 | struct pi_desc *pi_desc; | |
449 | bool pi_pending; | |
450 | u16 posted_intr_nv; | |
f4124500 | 451 | |
d048c098 RK |
452 | unsigned long *msr_bitmap; |
453 | ||
f4124500 JK |
454 | struct hrtimer preemption_timer; |
455 | bool preemption_timer_expired; | |
2996fca0 JK |
456 | |
457 | /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ | |
458 | u64 vmcs01_debugctl; | |
b9c237bb | 459 | |
5c614b35 WL |
460 | u16 vpid02; |
461 | u16 last_vpid; | |
462 | ||
0115f9cb DM |
463 | /* |
464 | * We only store the "true" versions of the VMX capability MSRs. We | |
465 | * generate the "non-true" versions by setting the must-be-1 bits | |
466 | * according to the SDM. | |
467 | */ | |
b9c237bb WV |
468 | u32 nested_vmx_procbased_ctls_low; |
469 | u32 nested_vmx_procbased_ctls_high; | |
b9c237bb WV |
470 | u32 nested_vmx_secondary_ctls_low; |
471 | u32 nested_vmx_secondary_ctls_high; | |
472 | u32 nested_vmx_pinbased_ctls_low; | |
473 | u32 nested_vmx_pinbased_ctls_high; | |
474 | u32 nested_vmx_exit_ctls_low; | |
475 | u32 nested_vmx_exit_ctls_high; | |
b9c237bb WV |
476 | u32 nested_vmx_entry_ctls_low; |
477 | u32 nested_vmx_entry_ctls_high; | |
b9c237bb WV |
478 | u32 nested_vmx_misc_low; |
479 | u32 nested_vmx_misc_high; | |
480 | u32 nested_vmx_ept_caps; | |
99b83ac8 | 481 | u32 nested_vmx_vpid_caps; |
62cc6b9d DM |
482 | u64 nested_vmx_basic; |
483 | u64 nested_vmx_cr0_fixed0; | |
484 | u64 nested_vmx_cr0_fixed1; | |
485 | u64 nested_vmx_cr4_fixed0; | |
486 | u64 nested_vmx_cr4_fixed1; | |
487 | u64 nested_vmx_vmcs_enum; | |
27c42a1b | 488 | u64 nested_vmx_vmfunc_controls; |
ec378aee NHE |
489 | }; |
490 | ||
01e439be | 491 | #define POSTED_INTR_ON 0 |
ebbfc765 FW |
492 | #define POSTED_INTR_SN 1 |
493 | ||
01e439be YZ |
494 | /* Posted-Interrupt Descriptor */ |
495 | struct pi_desc { | |
496 | u32 pir[8]; /* Posted interrupt requested */ | |
6ef1522f FW |
497 | union { |
498 | struct { | |
499 | /* bit 256 - Outstanding Notification */ | |
500 | u16 on : 1, | |
501 | /* bit 257 - Suppress Notification */ | |
502 | sn : 1, | |
503 | /* bit 271:258 - Reserved */ | |
504 | rsvd_1 : 14; | |
505 | /* bit 279:272 - Notification Vector */ | |
506 | u8 nv; | |
507 | /* bit 287:280 - Reserved */ | |
508 | u8 rsvd_2; | |
509 | /* bit 319:288 - Notification Destination */ | |
510 | u32 ndst; | |
511 | }; | |
512 | u64 control; | |
513 | }; | |
514 | u32 rsvd[6]; | |
01e439be YZ |
515 | } __aligned(64); |
516 | ||
a20ed54d YZ |
517 | static bool pi_test_and_set_on(struct pi_desc *pi_desc) |
518 | { | |
519 | return test_and_set_bit(POSTED_INTR_ON, | |
520 | (unsigned long *)&pi_desc->control); | |
521 | } | |
522 | ||
523 | static bool pi_test_and_clear_on(struct pi_desc *pi_desc) | |
524 | { | |
525 | return test_and_clear_bit(POSTED_INTR_ON, | |
526 | (unsigned long *)&pi_desc->control); | |
527 | } | |
528 | ||
529 | static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) | |
530 | { | |
531 | return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); | |
532 | } | |
533 | ||
ebbfc765 FW |
534 | static inline void pi_clear_sn(struct pi_desc *pi_desc) |
535 | { | |
536 | return clear_bit(POSTED_INTR_SN, | |
537 | (unsigned long *)&pi_desc->control); | |
538 | } | |
539 | ||
540 | static inline void pi_set_sn(struct pi_desc *pi_desc) | |
541 | { | |
542 | return set_bit(POSTED_INTR_SN, | |
543 | (unsigned long *)&pi_desc->control); | |
544 | } | |
545 | ||
ad361091 PB |
546 | static inline void pi_clear_on(struct pi_desc *pi_desc) |
547 | { | |
548 | clear_bit(POSTED_INTR_ON, | |
549 | (unsigned long *)&pi_desc->control); | |
550 | } | |
551 | ||
ebbfc765 FW |
552 | static inline int pi_test_on(struct pi_desc *pi_desc) |
553 | { | |
554 | return test_bit(POSTED_INTR_ON, | |
555 | (unsigned long *)&pi_desc->control); | |
556 | } | |
557 | ||
558 | static inline int pi_test_sn(struct pi_desc *pi_desc) | |
559 | { | |
560 | return test_bit(POSTED_INTR_SN, | |
561 | (unsigned long *)&pi_desc->control); | |
562 | } | |
563 | ||
a2fa3e9f | 564 | struct vcpu_vmx { |
fb3f0f51 | 565 | struct kvm_vcpu vcpu; |
313dbd49 | 566 | unsigned long host_rsp; |
29bd8a78 | 567 | u8 fail; |
51aa01d1 | 568 | u32 exit_intr_info; |
1155f76a | 569 | u32 idt_vectoring_info; |
6de12732 | 570 | ulong rflags; |
26bb0981 | 571 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
572 | int nmsrs; |
573 | int save_nmsrs; | |
a547c6db | 574 | unsigned long host_idt_base; |
a2fa3e9f | 575 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
576 | u64 msr_host_kernel_gs_base; |
577 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f | 578 | #endif |
2961e876 GN |
579 | u32 vm_entry_controls_shadow; |
580 | u32 vm_exit_controls_shadow; | |
80154d77 PB |
581 | u32 secondary_exec_control; |
582 | ||
d462b819 NHE |
583 | /* |
584 | * loaded_vmcs points to the VMCS currently used in this vcpu. For a | |
585 | * non-nested (L1) guest, it always points to vmcs01. For a nested | |
586 | * guest (L2), it points to a different VMCS. | |
587 | */ | |
588 | struct loaded_vmcs vmcs01; | |
589 | struct loaded_vmcs *loaded_vmcs; | |
590 | bool __launched; /* temporary, used in vmx_vcpu_run */ | |
61d2ef2c AK |
591 | struct msr_autoload { |
592 | unsigned nr; | |
593 | struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; | |
594 | struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; | |
595 | } msr_autoload; | |
a2fa3e9f GH |
596 | struct { |
597 | int loaded; | |
598 | u16 fs_sel, gs_sel, ldt_sel; | |
b2da15ac AK |
599 | #ifdef CONFIG_X86_64 |
600 | u16 ds_sel, es_sel; | |
601 | #endif | |
152d3f2f LV |
602 | int gs_ldt_reload_needed; |
603 | int fs_reload_needed; | |
da8999d3 | 604 | u64 msr_host_bndcfgs; |
d77c26fc | 605 | } host_state; |
9c8cba37 | 606 | struct { |
7ffd92c5 | 607 | int vm86_active; |
78ac8b47 | 608 | ulong save_rflags; |
f5f7b2fe AK |
609 | struct kvm_segment segs[8]; |
610 | } rmode; | |
611 | struct { | |
612 | u32 bitmask; /* 4 bits per segment (1 bit per field) */ | |
7ffd92c5 AK |
613 | struct kvm_save_segment { |
614 | u16 selector; | |
615 | unsigned long base; | |
616 | u32 limit; | |
617 | u32 ar; | |
f5f7b2fe | 618 | } seg[8]; |
2fb92db1 | 619 | } segment_cache; |
2384d2b3 | 620 | int vpid; |
04fa4d32 | 621 | bool emulation_required; |
3b86cd99 | 622 | |
a0861c02 | 623 | u32 exit_reason; |
4e47c7a6 | 624 | |
01e439be YZ |
625 | /* Posted interrupt descriptor */ |
626 | struct pi_desc pi_desc; | |
627 | ||
ec378aee NHE |
628 | /* Support for a guest hypervisor (nested VMX) */ |
629 | struct nested_vmx nested; | |
a7653ecd RK |
630 | |
631 | /* Dynamic PLE window. */ | |
632 | int ple_window; | |
633 | bool ple_window_dirty; | |
843e4330 KH |
634 | |
635 | /* Support for PML */ | |
636 | #define PML_ENTITY_NUM 512 | |
637 | struct page *pml_pg; | |
2680d6da | 638 | |
64672c95 YJ |
639 | /* apic deadline value in host tsc */ |
640 | u64 hv_deadline_tsc; | |
641 | ||
2680d6da | 642 | u64 current_tsc_ratio; |
1be0e61c | 643 | |
1be0e61c | 644 | u32 host_pkru; |
3b84080b | 645 | |
37e4c997 HZ |
646 | /* |
647 | * Only bits masked by msr_ia32_feature_control_valid_bits can be set in | |
648 | * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included | |
649 | * in msr_ia32_feature_control_valid_bits. | |
650 | */ | |
3b84080b | 651 | u64 msr_ia32_feature_control; |
37e4c997 | 652 | u64 msr_ia32_feature_control_valid_bits; |
a2fa3e9f GH |
653 | }; |
654 | ||
2fb92db1 AK |
655 | enum segment_cache_field { |
656 | SEG_FIELD_SEL = 0, | |
657 | SEG_FIELD_BASE = 1, | |
658 | SEG_FIELD_LIMIT = 2, | |
659 | SEG_FIELD_AR = 3, | |
660 | ||
661 | SEG_FIELD_NR = 4 | |
662 | }; | |
663 | ||
a2fa3e9f GH |
664 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
665 | { | |
fb3f0f51 | 666 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
667 | } |
668 | ||
efc64404 FW |
669 | static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu) |
670 | { | |
671 | return &(to_vmx(vcpu)->pi_desc); | |
672 | } | |
673 | ||
22bd0358 NHE |
674 | #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x) |
675 | #define FIELD(number, name) [number] = VMCS12_OFFSET(name) | |
676 | #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \ | |
677 | [number##_HIGH] = VMCS12_OFFSET(name)+4 | |
678 | ||
4607c2d7 | 679 | |
fe2b201b | 680 | static unsigned long shadow_read_only_fields[] = { |
4607c2d7 AG |
681 | /* |
682 | * We do NOT shadow fields that are modified when L0 | |
683 | * traps and emulates any vmx instruction (e.g. VMPTRLD, | |
684 | * VMXON...) executed by L1. | |
685 | * For example, VM_INSTRUCTION_ERROR is read | |
686 | * by L1 if a vmx instruction fails (part of the error path). | |
687 | * Note the code assumes this logic. If for some reason | |
688 | * we start shadowing these fields then we need to | |
689 | * force a shadow sync when L0 emulates vmx instructions | |
690 | * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified | |
691 | * by nested_vmx_failValid) | |
692 | */ | |
693 | VM_EXIT_REASON, | |
694 | VM_EXIT_INTR_INFO, | |
695 | VM_EXIT_INSTRUCTION_LEN, | |
696 | IDT_VECTORING_INFO_FIELD, | |
697 | IDT_VECTORING_ERROR_CODE, | |
698 | VM_EXIT_INTR_ERROR_CODE, | |
699 | EXIT_QUALIFICATION, | |
700 | GUEST_LINEAR_ADDRESS, | |
701 | GUEST_PHYSICAL_ADDRESS | |
702 | }; | |
fe2b201b | 703 | static int max_shadow_read_only_fields = |
4607c2d7 AG |
704 | ARRAY_SIZE(shadow_read_only_fields); |
705 | ||
fe2b201b | 706 | static unsigned long shadow_read_write_fields[] = { |
a7c0b07d | 707 | TPR_THRESHOLD, |
4607c2d7 AG |
708 | GUEST_RIP, |
709 | GUEST_RSP, | |
710 | GUEST_CR0, | |
711 | GUEST_CR3, | |
712 | GUEST_CR4, | |
713 | GUEST_INTERRUPTIBILITY_INFO, | |
714 | GUEST_RFLAGS, | |
715 | GUEST_CS_SELECTOR, | |
716 | GUEST_CS_AR_BYTES, | |
717 | GUEST_CS_LIMIT, | |
718 | GUEST_CS_BASE, | |
719 | GUEST_ES_BASE, | |
36be0b9d | 720 | GUEST_BNDCFGS, |
4607c2d7 AG |
721 | CR0_GUEST_HOST_MASK, |
722 | CR0_READ_SHADOW, | |
723 | CR4_READ_SHADOW, | |
724 | TSC_OFFSET, | |
725 | EXCEPTION_BITMAP, | |
726 | CPU_BASED_VM_EXEC_CONTROL, | |
727 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
728 | VM_ENTRY_INTR_INFO_FIELD, | |
729 | VM_ENTRY_INSTRUCTION_LEN, | |
730 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
731 | HOST_FS_BASE, | |
732 | HOST_GS_BASE, | |
733 | HOST_FS_SELECTOR, | |
734 | HOST_GS_SELECTOR | |
735 | }; | |
fe2b201b | 736 | static int max_shadow_read_write_fields = |
4607c2d7 AG |
737 | ARRAY_SIZE(shadow_read_write_fields); |
738 | ||
772e0318 | 739 | static const unsigned short vmcs_field_to_offset_table[] = { |
22bd0358 | 740 | FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id), |
705699a1 | 741 | FIELD(POSTED_INTR_NV, posted_intr_nv), |
22bd0358 NHE |
742 | FIELD(GUEST_ES_SELECTOR, guest_es_selector), |
743 | FIELD(GUEST_CS_SELECTOR, guest_cs_selector), | |
744 | FIELD(GUEST_SS_SELECTOR, guest_ss_selector), | |
745 | FIELD(GUEST_DS_SELECTOR, guest_ds_selector), | |
746 | FIELD(GUEST_FS_SELECTOR, guest_fs_selector), | |
747 | FIELD(GUEST_GS_SELECTOR, guest_gs_selector), | |
748 | FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector), | |
749 | FIELD(GUEST_TR_SELECTOR, guest_tr_selector), | |
608406e2 | 750 | FIELD(GUEST_INTR_STATUS, guest_intr_status), |
c5f983f6 | 751 | FIELD(GUEST_PML_INDEX, guest_pml_index), |
22bd0358 NHE |
752 | FIELD(HOST_ES_SELECTOR, host_es_selector), |
753 | FIELD(HOST_CS_SELECTOR, host_cs_selector), | |
754 | FIELD(HOST_SS_SELECTOR, host_ss_selector), | |
755 | FIELD(HOST_DS_SELECTOR, host_ds_selector), | |
756 | FIELD(HOST_FS_SELECTOR, host_fs_selector), | |
757 | FIELD(HOST_GS_SELECTOR, host_gs_selector), | |
758 | FIELD(HOST_TR_SELECTOR, host_tr_selector), | |
759 | FIELD64(IO_BITMAP_A, io_bitmap_a), | |
760 | FIELD64(IO_BITMAP_B, io_bitmap_b), | |
761 | FIELD64(MSR_BITMAP, msr_bitmap), | |
762 | FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr), | |
763 | FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr), | |
764 | FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr), | |
765 | FIELD64(TSC_OFFSET, tsc_offset), | |
766 | FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), | |
767 | FIELD64(APIC_ACCESS_ADDR, apic_access_addr), | |
705699a1 | 768 | FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr), |
27c42a1b | 769 | FIELD64(VM_FUNCTION_CONTROL, vm_function_control), |
22bd0358 | 770 | FIELD64(EPT_POINTER, ept_pointer), |
608406e2 WV |
771 | FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0), |
772 | FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1), | |
773 | FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2), | |
774 | FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3), | |
41ab9372 | 775 | FIELD64(EPTP_LIST_ADDRESS, eptp_list_address), |
81dc01f7 | 776 | FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap), |
22bd0358 NHE |
777 | FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), |
778 | FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), | |
c5f983f6 | 779 | FIELD64(PML_ADDRESS, pml_address), |
22bd0358 NHE |
780 | FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), |
781 | FIELD64(GUEST_IA32_PAT, guest_ia32_pat), | |
782 | FIELD64(GUEST_IA32_EFER, guest_ia32_efer), | |
783 | FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl), | |
784 | FIELD64(GUEST_PDPTR0, guest_pdptr0), | |
785 | FIELD64(GUEST_PDPTR1, guest_pdptr1), | |
786 | FIELD64(GUEST_PDPTR2, guest_pdptr2), | |
787 | FIELD64(GUEST_PDPTR3, guest_pdptr3), | |
36be0b9d | 788 | FIELD64(GUEST_BNDCFGS, guest_bndcfgs), |
22bd0358 NHE |
789 | FIELD64(HOST_IA32_PAT, host_ia32_pat), |
790 | FIELD64(HOST_IA32_EFER, host_ia32_efer), | |
791 | FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), | |
792 | FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), | |
793 | FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), | |
794 | FIELD(EXCEPTION_BITMAP, exception_bitmap), | |
795 | FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask), | |
796 | FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match), | |
797 | FIELD(CR3_TARGET_COUNT, cr3_target_count), | |
798 | FIELD(VM_EXIT_CONTROLS, vm_exit_controls), | |
799 | FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count), | |
800 | FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count), | |
801 | FIELD(VM_ENTRY_CONTROLS, vm_entry_controls), | |
802 | FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count), | |
803 | FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field), | |
804 | FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code), | |
805 | FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len), | |
806 | FIELD(TPR_THRESHOLD, tpr_threshold), | |
807 | FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control), | |
808 | FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error), | |
809 | FIELD(VM_EXIT_REASON, vm_exit_reason), | |
810 | FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info), | |
811 | FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code), | |
812 | FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field), | |
813 | FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code), | |
814 | FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len), | |
815 | FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info), | |
816 | FIELD(GUEST_ES_LIMIT, guest_es_limit), | |
817 | FIELD(GUEST_CS_LIMIT, guest_cs_limit), | |
818 | FIELD(GUEST_SS_LIMIT, guest_ss_limit), | |
819 | FIELD(GUEST_DS_LIMIT, guest_ds_limit), | |
820 | FIELD(GUEST_FS_LIMIT, guest_fs_limit), | |
821 | FIELD(GUEST_GS_LIMIT, guest_gs_limit), | |
822 | FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit), | |
823 | FIELD(GUEST_TR_LIMIT, guest_tr_limit), | |
824 | FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit), | |
825 | FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit), | |
826 | FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes), | |
827 | FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes), | |
828 | FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes), | |
829 | FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes), | |
830 | FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes), | |
831 | FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes), | |
832 | FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes), | |
833 | FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes), | |
834 | FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info), | |
835 | FIELD(GUEST_ACTIVITY_STATE, guest_activity_state), | |
836 | FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs), | |
837 | FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs), | |
0238ea91 | 838 | FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value), |
22bd0358 NHE |
839 | FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask), |
840 | FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask), | |
841 | FIELD(CR0_READ_SHADOW, cr0_read_shadow), | |
842 | FIELD(CR4_READ_SHADOW, cr4_read_shadow), | |
843 | FIELD(CR3_TARGET_VALUE0, cr3_target_value0), | |
844 | FIELD(CR3_TARGET_VALUE1, cr3_target_value1), | |
845 | FIELD(CR3_TARGET_VALUE2, cr3_target_value2), | |
846 | FIELD(CR3_TARGET_VALUE3, cr3_target_value3), | |
847 | FIELD(EXIT_QUALIFICATION, exit_qualification), | |
848 | FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address), | |
849 | FIELD(GUEST_CR0, guest_cr0), | |
850 | FIELD(GUEST_CR3, guest_cr3), | |
851 | FIELD(GUEST_CR4, guest_cr4), | |
852 | FIELD(GUEST_ES_BASE, guest_es_base), | |
853 | FIELD(GUEST_CS_BASE, guest_cs_base), | |
854 | FIELD(GUEST_SS_BASE, guest_ss_base), | |
855 | FIELD(GUEST_DS_BASE, guest_ds_base), | |
856 | FIELD(GUEST_FS_BASE, guest_fs_base), | |
857 | FIELD(GUEST_GS_BASE, guest_gs_base), | |
858 | FIELD(GUEST_LDTR_BASE, guest_ldtr_base), | |
859 | FIELD(GUEST_TR_BASE, guest_tr_base), | |
860 | FIELD(GUEST_GDTR_BASE, guest_gdtr_base), | |
861 | FIELD(GUEST_IDTR_BASE, guest_idtr_base), | |
862 | FIELD(GUEST_DR7, guest_dr7), | |
863 | FIELD(GUEST_RSP, guest_rsp), | |
864 | FIELD(GUEST_RIP, guest_rip), | |
865 | FIELD(GUEST_RFLAGS, guest_rflags), | |
866 | FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions), | |
867 | FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp), | |
868 | FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip), | |
869 | FIELD(HOST_CR0, host_cr0), | |
870 | FIELD(HOST_CR3, host_cr3), | |
871 | FIELD(HOST_CR4, host_cr4), | |
872 | FIELD(HOST_FS_BASE, host_fs_base), | |
873 | FIELD(HOST_GS_BASE, host_gs_base), | |
874 | FIELD(HOST_TR_BASE, host_tr_base), | |
875 | FIELD(HOST_GDTR_BASE, host_gdtr_base), | |
876 | FIELD(HOST_IDTR_BASE, host_idtr_base), | |
877 | FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp), | |
878 | FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip), | |
879 | FIELD(HOST_RSP, host_rsp), | |
880 | FIELD(HOST_RIP, host_rip), | |
881 | }; | |
22bd0358 NHE |
882 | |
883 | static inline short vmcs_field_to_offset(unsigned long field) | |
884 | { | |
a2ae9df7 PB |
885 | BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX); |
886 | ||
887 | if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) || | |
888 | vmcs_field_to_offset_table[field] == 0) | |
889 | return -ENOENT; | |
890 | ||
22bd0358 NHE |
891 | return vmcs_field_to_offset_table[field]; |
892 | } | |
893 | ||
a9d30f33 NHE |
894 | static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
895 | { | |
4f2777bc | 896 | return to_vmx(vcpu)->nested.cached_vmcs12; |
a9d30f33 NHE |
897 | } |
898 | ||
995f00a6 | 899 | static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu); |
bfd0a56b | 900 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu); |
995f00a6 | 901 | static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa); |
f53cd63c | 902 | static bool vmx_xsaves_supported(void); |
b246dd5d OW |
903 | static void vmx_set_segment(struct kvm_vcpu *vcpu, |
904 | struct kvm_segment *var, int seg); | |
905 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
906 | struct kvm_segment *var, int seg); | |
d99e4152 GN |
907 | static bool guest_state_valid(struct kvm_vcpu *vcpu); |
908 | static u32 vmx_segment_access_rights(struct kvm_segment *var); | |
16f5b903 | 909 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx); |
b96fb439 PB |
910 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); |
911 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); | |
912 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, | |
913 | u16 error_code); | |
75880a01 | 914 | |
6aa8b732 AK |
915 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
916 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
d462b819 NHE |
917 | /* |
918 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
919 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
920 | */ | |
921 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
6aa8b732 | 922 | |
bf9f6ac8 FW |
923 | /* |
924 | * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we | |
925 | * can find which vCPU should be waken up. | |
926 | */ | |
927 | static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); | |
928 | static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); | |
929 | ||
23611332 RK |
930 | enum { |
931 | VMX_IO_BITMAP_A, | |
932 | VMX_IO_BITMAP_B, | |
933 | VMX_MSR_BITMAP_LEGACY, | |
934 | VMX_MSR_BITMAP_LONGMODE, | |
935 | VMX_MSR_BITMAP_LEGACY_X2APIC_APICV, | |
936 | VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV, | |
937 | VMX_MSR_BITMAP_LEGACY_X2APIC, | |
938 | VMX_MSR_BITMAP_LONGMODE_X2APIC, | |
939 | VMX_VMREAD_BITMAP, | |
940 | VMX_VMWRITE_BITMAP, | |
941 | VMX_BITMAP_NR | |
942 | }; | |
943 | ||
944 | static unsigned long *vmx_bitmap[VMX_BITMAP_NR]; | |
945 | ||
946 | #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A]) | |
947 | #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B]) | |
948 | #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY]) | |
949 | #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE]) | |
950 | #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV]) | |
951 | #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV]) | |
952 | #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC]) | |
953 | #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC]) | |
954 | #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP]) | |
955 | #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP]) | |
fdef3ad1 | 956 | |
110312c8 | 957 | static bool cpu_has_load_ia32_efer; |
8bf00a52 | 958 | static bool cpu_has_load_perf_global_ctrl; |
110312c8 | 959 | |
2384d2b3 SY |
960 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
961 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
962 | ||
1c3d14fe | 963 | static struct vmcs_config { |
6aa8b732 AK |
964 | int size; |
965 | int order; | |
9ac7e3e8 | 966 | u32 basic_cap; |
6aa8b732 | 967 | u32 revision_id; |
1c3d14fe YS |
968 | u32 pin_based_exec_ctrl; |
969 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 970 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
971 | u32 vmexit_ctrl; |
972 | u32 vmentry_ctrl; | |
973 | } vmcs_config; | |
6aa8b732 | 974 | |
efff9e53 | 975 | static struct vmx_capability { |
d56f546d SY |
976 | u32 ept; |
977 | u32 vpid; | |
978 | } vmx_capability; | |
979 | ||
6aa8b732 AK |
980 | #define VMX_SEGMENT_FIELD(seg) \ |
981 | [VCPU_SREG_##seg] = { \ | |
982 | .selector = GUEST_##seg##_SELECTOR, \ | |
983 | .base = GUEST_##seg##_BASE, \ | |
984 | .limit = GUEST_##seg##_LIMIT, \ | |
985 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
986 | } | |
987 | ||
772e0318 | 988 | static const struct kvm_vmx_segment_field { |
6aa8b732 AK |
989 | unsigned selector; |
990 | unsigned base; | |
991 | unsigned limit; | |
992 | unsigned ar_bytes; | |
993 | } kvm_vmx_segment_fields[] = { | |
994 | VMX_SEGMENT_FIELD(CS), | |
995 | VMX_SEGMENT_FIELD(DS), | |
996 | VMX_SEGMENT_FIELD(ES), | |
997 | VMX_SEGMENT_FIELD(FS), | |
998 | VMX_SEGMENT_FIELD(GS), | |
999 | VMX_SEGMENT_FIELD(SS), | |
1000 | VMX_SEGMENT_FIELD(TR), | |
1001 | VMX_SEGMENT_FIELD(LDTR), | |
1002 | }; | |
1003 | ||
26bb0981 AK |
1004 | static u64 host_efer; |
1005 | ||
6de4f3ad AK |
1006 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
1007 | ||
4d56c8a7 | 1008 | /* |
8c06585d | 1009 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
1010 | * away by decrementing the array size. |
1011 | */ | |
6aa8b732 | 1012 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 1013 | #ifdef CONFIG_X86_64 |
44ea2b17 | 1014 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 1015 | #endif |
8c06585d | 1016 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 1017 | }; |
6aa8b732 | 1018 | |
5bb16016 | 1019 | static inline bool is_exception_n(u32 intr_info, u8 vector) |
6aa8b732 AK |
1020 | { |
1021 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1022 | INTR_INFO_VALID_MASK)) == | |
5bb16016 JK |
1023 | (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK); |
1024 | } | |
1025 | ||
6f05485d JK |
1026 | static inline bool is_debug(u32 intr_info) |
1027 | { | |
1028 | return is_exception_n(intr_info, DB_VECTOR); | |
1029 | } | |
1030 | ||
1031 | static inline bool is_breakpoint(u32 intr_info) | |
1032 | { | |
1033 | return is_exception_n(intr_info, BP_VECTOR); | |
1034 | } | |
1035 | ||
5bb16016 JK |
1036 | static inline bool is_page_fault(u32 intr_info) |
1037 | { | |
1038 | return is_exception_n(intr_info, PF_VECTOR); | |
6aa8b732 AK |
1039 | } |
1040 | ||
31299944 | 1041 | static inline bool is_no_device(u32 intr_info) |
2ab455cc | 1042 | { |
5bb16016 | 1043 | return is_exception_n(intr_info, NM_VECTOR); |
2ab455cc AL |
1044 | } |
1045 | ||
31299944 | 1046 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 | 1047 | { |
5bb16016 | 1048 | return is_exception_n(intr_info, UD_VECTOR); |
7aa81cc0 AL |
1049 | } |
1050 | ||
31299944 | 1051 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
1052 | { |
1053 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1054 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1055 | } | |
1056 | ||
31299944 | 1057 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
1058 | { |
1059 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1060 | INTR_INFO_VALID_MASK)) == | |
1061 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
1062 | } | |
1063 | ||
31299944 | 1064 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 1065 | { |
04547156 | 1066 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
1067 | } |
1068 | ||
31299944 | 1069 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 1070 | { |
04547156 | 1071 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
1072 | } |
1073 | ||
35754c98 | 1074 | static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) |
6e5d865c | 1075 | { |
35754c98 | 1076 | return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); |
6e5d865c YS |
1077 | } |
1078 | ||
31299944 | 1079 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 1080 | { |
04547156 SY |
1081 | return vmcs_config.cpu_based_exec_ctrl & |
1082 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
1083 | } |
1084 | ||
774ead3a | 1085 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 1086 | { |
04547156 SY |
1087 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1088 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1089 | } | |
1090 | ||
8d14695f YZ |
1091 | static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) |
1092 | { | |
1093 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1094 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
1095 | } | |
1096 | ||
83d4c286 YZ |
1097 | static inline bool cpu_has_vmx_apic_register_virt(void) |
1098 | { | |
1099 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1100 | SECONDARY_EXEC_APIC_REGISTER_VIRT; | |
1101 | } | |
1102 | ||
c7c9c56c YZ |
1103 | static inline bool cpu_has_vmx_virtual_intr_delivery(void) |
1104 | { | |
1105 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1106 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; | |
1107 | } | |
1108 | ||
64672c95 YJ |
1109 | /* |
1110 | * Comment's format: document - errata name - stepping - processor name. | |
1111 | * Refer from | |
1112 | * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp | |
1113 | */ | |
1114 | static u32 vmx_preemption_cpu_tfms[] = { | |
1115 | /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ | |
1116 | 0x000206E6, | |
1117 | /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ | |
1118 | /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ | |
1119 | /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1120 | 0x00020652, | |
1121 | /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1122 | 0x00020655, | |
1123 | /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ | |
1124 | /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ | |
1125 | /* | |
1126 | * 320767.pdf - AAP86 - B1 - | |
1127 | * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile | |
1128 | */ | |
1129 | 0x000106E5, | |
1130 | /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ | |
1131 | 0x000106A0, | |
1132 | /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ | |
1133 | 0x000106A1, | |
1134 | /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ | |
1135 | 0x000106A4, | |
1136 | /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ | |
1137 | /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ | |
1138 | /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ | |
1139 | 0x000106A5, | |
1140 | }; | |
1141 | ||
1142 | static inline bool cpu_has_broken_vmx_preemption_timer(void) | |
1143 | { | |
1144 | u32 eax = cpuid_eax(0x00000001), i; | |
1145 | ||
1146 | /* Clear the reserved bits */ | |
1147 | eax &= ~(0x3U << 14 | 0xfU << 28); | |
03f6a22a | 1148 | for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) |
64672c95 YJ |
1149 | if (eax == vmx_preemption_cpu_tfms[i]) |
1150 | return true; | |
1151 | ||
1152 | return false; | |
1153 | } | |
1154 | ||
1155 | static inline bool cpu_has_vmx_preemption_timer(void) | |
1156 | { | |
64672c95 YJ |
1157 | return vmcs_config.pin_based_exec_ctrl & |
1158 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1159 | } | |
1160 | ||
01e439be YZ |
1161 | static inline bool cpu_has_vmx_posted_intr(void) |
1162 | { | |
d6a858d1 PB |
1163 | return IS_ENABLED(CONFIG_X86_LOCAL_APIC) && |
1164 | vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; | |
01e439be YZ |
1165 | } |
1166 | ||
1167 | static inline bool cpu_has_vmx_apicv(void) | |
1168 | { | |
1169 | return cpu_has_vmx_apic_register_virt() && | |
1170 | cpu_has_vmx_virtual_intr_delivery() && | |
1171 | cpu_has_vmx_posted_intr(); | |
1172 | } | |
1173 | ||
04547156 SY |
1174 | static inline bool cpu_has_vmx_flexpriority(void) |
1175 | { | |
1176 | return cpu_has_vmx_tpr_shadow() && | |
1177 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
1178 | } |
1179 | ||
e799794e MT |
1180 | static inline bool cpu_has_vmx_ept_execute_only(void) |
1181 | { | |
31299944 | 1182 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
1183 | } |
1184 | ||
e799794e MT |
1185 | static inline bool cpu_has_vmx_ept_2m_page(void) |
1186 | { | |
31299944 | 1187 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
1188 | } |
1189 | ||
878403b7 SY |
1190 | static inline bool cpu_has_vmx_ept_1g_page(void) |
1191 | { | |
31299944 | 1192 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
1193 | } |
1194 | ||
4bc9b982 SY |
1195 | static inline bool cpu_has_vmx_ept_4levels(void) |
1196 | { | |
1197 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
1198 | } | |
1199 | ||
42aa53b4 DH |
1200 | static inline bool cpu_has_vmx_ept_mt_wb(void) |
1201 | { | |
1202 | return vmx_capability.ept & VMX_EPTP_WB_BIT; | |
1203 | } | |
1204 | ||
855feb67 YZ |
1205 | static inline bool cpu_has_vmx_ept_5levels(void) |
1206 | { | |
1207 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT; | |
1208 | } | |
1209 | ||
83c3a331 XH |
1210 | static inline bool cpu_has_vmx_ept_ad_bits(void) |
1211 | { | |
1212 | return vmx_capability.ept & VMX_EPT_AD_BIT; | |
1213 | } | |
1214 | ||
31299944 | 1215 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 1216 | { |
31299944 | 1217 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
1218 | } |
1219 | ||
31299944 | 1220 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 1221 | { |
31299944 | 1222 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
1223 | } |
1224 | ||
518c8aee GJ |
1225 | static inline bool cpu_has_vmx_invvpid_single(void) |
1226 | { | |
1227 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
1228 | } | |
1229 | ||
b9d762fa GJ |
1230 | static inline bool cpu_has_vmx_invvpid_global(void) |
1231 | { | |
1232 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
1233 | } | |
1234 | ||
08d839c4 WL |
1235 | static inline bool cpu_has_vmx_invvpid(void) |
1236 | { | |
1237 | return vmx_capability.vpid & VMX_VPID_INVVPID_BIT; | |
1238 | } | |
1239 | ||
31299944 | 1240 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 1241 | { |
04547156 SY |
1242 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1243 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
1244 | } |
1245 | ||
31299944 | 1246 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
1247 | { |
1248 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1249 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
1250 | } | |
1251 | ||
31299944 | 1252 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
1253 | { |
1254 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1255 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
1256 | } | |
1257 | ||
9ac7e3e8 JD |
1258 | static inline bool cpu_has_vmx_basic_inout(void) |
1259 | { | |
1260 | return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT); | |
1261 | } | |
1262 | ||
35754c98 | 1263 | static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) |
f78e0e2e | 1264 | { |
35754c98 | 1265 | return flexpriority_enabled && lapic_in_kernel(vcpu); |
f78e0e2e SY |
1266 | } |
1267 | ||
31299944 | 1268 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 1269 | { |
04547156 SY |
1270 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1271 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
1272 | } |
1273 | ||
31299944 | 1274 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
1275 | { |
1276 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1277 | SECONDARY_EXEC_RDTSCP; | |
1278 | } | |
1279 | ||
ad756a16 MJ |
1280 | static inline bool cpu_has_vmx_invpcid(void) |
1281 | { | |
1282 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1283 | SECONDARY_EXEC_ENABLE_INVPCID; | |
1284 | } | |
1285 | ||
f5f48ee1 SY |
1286 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
1287 | { | |
1288 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1289 | SECONDARY_EXEC_WBINVD_EXITING; | |
1290 | } | |
1291 | ||
abc4fc58 AG |
1292 | static inline bool cpu_has_vmx_shadow_vmcs(void) |
1293 | { | |
1294 | u64 vmx_msr; | |
1295 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
1296 | /* check if the cpu supports writing r/o exit information fields */ | |
1297 | if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) | |
1298 | return false; | |
1299 | ||
1300 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1301 | SECONDARY_EXEC_SHADOW_VMCS; | |
1302 | } | |
1303 | ||
843e4330 KH |
1304 | static inline bool cpu_has_vmx_pml(void) |
1305 | { | |
1306 | return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; | |
1307 | } | |
1308 | ||
64903d61 HZ |
1309 | static inline bool cpu_has_vmx_tsc_scaling(void) |
1310 | { | |
1311 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1312 | SECONDARY_EXEC_TSC_SCALING; | |
1313 | } | |
1314 | ||
2a499e49 BD |
1315 | static inline bool cpu_has_vmx_vmfunc(void) |
1316 | { | |
1317 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1318 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
1319 | } | |
1320 | ||
04547156 SY |
1321 | static inline bool report_flexpriority(void) |
1322 | { | |
1323 | return flexpriority_enabled; | |
1324 | } | |
1325 | ||
c7c2c709 JM |
1326 | static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu) |
1327 | { | |
1328 | return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low); | |
1329 | } | |
1330 | ||
fe3ef05c NHE |
1331 | static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) |
1332 | { | |
1333 | return vmcs12->cpu_based_vm_exec_control & bit; | |
1334 | } | |
1335 | ||
1336 | static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) | |
1337 | { | |
1338 | return (vmcs12->cpu_based_vm_exec_control & | |
1339 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && | |
1340 | (vmcs12->secondary_vm_exec_control & bit); | |
1341 | } | |
1342 | ||
f5c4368f | 1343 | static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12) |
644d711a NHE |
1344 | { |
1345 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS; | |
1346 | } | |
1347 | ||
f4124500 JK |
1348 | static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) |
1349 | { | |
1350 | return vmcs12->pin_based_vm_exec_control & | |
1351 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1352 | } | |
1353 | ||
155a97a3 NHE |
1354 | static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) |
1355 | { | |
1356 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); | |
1357 | } | |
1358 | ||
81dc01f7 WL |
1359 | static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) |
1360 | { | |
3db13480 | 1361 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); |
81dc01f7 WL |
1362 | } |
1363 | ||
c5f983f6 BD |
1364 | static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12) |
1365 | { | |
1366 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML); | |
1367 | } | |
1368 | ||
f2b93280 WV |
1369 | static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) |
1370 | { | |
1371 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); | |
1372 | } | |
1373 | ||
5c614b35 WL |
1374 | static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) |
1375 | { | |
1376 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); | |
1377 | } | |
1378 | ||
82f0dd4b WV |
1379 | static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) |
1380 | { | |
1381 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); | |
1382 | } | |
1383 | ||
608406e2 WV |
1384 | static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) |
1385 | { | |
1386 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
1387 | } | |
1388 | ||
705699a1 WV |
1389 | static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) |
1390 | { | |
1391 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; | |
1392 | } | |
1393 | ||
27c42a1b BD |
1394 | static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12) |
1395 | { | |
1396 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC); | |
1397 | } | |
1398 | ||
41ab9372 BD |
1399 | static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12) |
1400 | { | |
1401 | return nested_cpu_has_vmfunc(vmcs12) && | |
1402 | (vmcs12->vm_function_control & | |
1403 | VMX_VMFUNC_EPTP_SWITCHING); | |
1404 | } | |
1405 | ||
ef85b673 | 1406 | static inline bool is_nmi(u32 intr_info) |
644d711a NHE |
1407 | { |
1408 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
ef85b673 | 1409 | == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK); |
644d711a NHE |
1410 | } |
1411 | ||
533558bc JK |
1412 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
1413 | u32 exit_intr_info, | |
1414 | unsigned long exit_qualification); | |
7c177938 NHE |
1415 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, |
1416 | struct vmcs12 *vmcs12, | |
1417 | u32 reason, unsigned long qualification); | |
1418 | ||
8b9cf98c | 1419 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
1420 | { |
1421 | int i; | |
1422 | ||
a2fa3e9f | 1423 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 1424 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
1425 | return i; |
1426 | return -1; | |
1427 | } | |
1428 | ||
2384d2b3 SY |
1429 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
1430 | { | |
1431 | struct { | |
1432 | u64 vpid : 16; | |
1433 | u64 rsvd : 48; | |
1434 | u64 gva; | |
1435 | } operand = { vpid, 0, gva }; | |
1436 | ||
4ecac3fd | 1437 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
1438 | /* CF==1 or ZF==1 --> rc = -1 */ |
1439 | "; ja 1f ; ud2 ; 1:" | |
1440 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
1441 | } | |
1442 | ||
1439442c SY |
1443 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
1444 | { | |
1445 | struct { | |
1446 | u64 eptp, gpa; | |
1447 | } operand = {eptp, gpa}; | |
1448 | ||
4ecac3fd | 1449 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
1450 | /* CF==1 or ZF==1 --> rc = -1 */ |
1451 | "; ja 1f ; ud2 ; 1:\n" | |
1452 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
1453 | } | |
1454 | ||
26bb0981 | 1455 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
1456 | { |
1457 | int i; | |
1458 | ||
8b9cf98c | 1459 | i = __find_msr_index(vmx, msr); |
a75beee6 | 1460 | if (i >= 0) |
a2fa3e9f | 1461 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 1462 | return NULL; |
7725f0ba AK |
1463 | } |
1464 | ||
6aa8b732 AK |
1465 | static void vmcs_clear(struct vmcs *vmcs) |
1466 | { | |
1467 | u64 phys_addr = __pa(vmcs); | |
1468 | u8 error; | |
1469 | ||
4ecac3fd | 1470 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 1471 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
1472 | : "cc", "memory"); |
1473 | if (error) | |
1474 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
1475 | vmcs, phys_addr); | |
1476 | } | |
1477 | ||
d462b819 NHE |
1478 | static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
1479 | { | |
1480 | vmcs_clear(loaded_vmcs->vmcs); | |
355f4fb1 JM |
1481 | if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) |
1482 | vmcs_clear(loaded_vmcs->shadow_vmcs); | |
d462b819 NHE |
1483 | loaded_vmcs->cpu = -1; |
1484 | loaded_vmcs->launched = 0; | |
1485 | } | |
1486 | ||
7725b894 DX |
1487 | static void vmcs_load(struct vmcs *vmcs) |
1488 | { | |
1489 | u64 phys_addr = __pa(vmcs); | |
1490 | u8 error; | |
1491 | ||
1492 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
16d8f72f | 1493 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
1494 | : "cc", "memory"); |
1495 | if (error) | |
2844d849 | 1496 | printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n", |
7725b894 DX |
1497 | vmcs, phys_addr); |
1498 | } | |
1499 | ||
2965faa5 | 1500 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
1501 | /* |
1502 | * This bitmap is used to indicate whether the vmclear | |
1503 | * operation is enabled on all cpus. All disabled by | |
1504 | * default. | |
1505 | */ | |
1506 | static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; | |
1507 | ||
1508 | static inline void crash_enable_local_vmclear(int cpu) | |
1509 | { | |
1510 | cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1511 | } | |
1512 | ||
1513 | static inline void crash_disable_local_vmclear(int cpu) | |
1514 | { | |
1515 | cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1516 | } | |
1517 | ||
1518 | static inline int crash_local_vmclear_enabled(int cpu) | |
1519 | { | |
1520 | return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1521 | } | |
1522 | ||
1523 | static void crash_vmclear_local_loaded_vmcss(void) | |
1524 | { | |
1525 | int cpu = raw_smp_processor_id(); | |
1526 | struct loaded_vmcs *v; | |
1527 | ||
1528 | if (!crash_local_vmclear_enabled(cpu)) | |
1529 | return; | |
1530 | ||
1531 | list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), | |
1532 | loaded_vmcss_on_cpu_link) | |
1533 | vmcs_clear(v->vmcs); | |
1534 | } | |
1535 | #else | |
1536 | static inline void crash_enable_local_vmclear(int cpu) { } | |
1537 | static inline void crash_disable_local_vmclear(int cpu) { } | |
2965faa5 | 1538 | #endif /* CONFIG_KEXEC_CORE */ |
8f536b76 | 1539 | |
d462b819 | 1540 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 1541 | { |
d462b819 | 1542 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 1543 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 1544 | |
d462b819 NHE |
1545 | if (loaded_vmcs->cpu != cpu) |
1546 | return; /* vcpu migration can race with cpu offline */ | |
1547 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 1548 | per_cpu(current_vmcs, cpu) = NULL; |
8f536b76 | 1549 | crash_disable_local_vmclear(cpu); |
d462b819 | 1550 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
5a560f8b XG |
1551 | |
1552 | /* | |
1553 | * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link | |
1554 | * is before setting loaded_vmcs->vcpu to -1 which is done in | |
1555 | * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist | |
1556 | * then adds the vmcs into percpu list before it is deleted. | |
1557 | */ | |
1558 | smp_wmb(); | |
1559 | ||
d462b819 | 1560 | loaded_vmcs_init(loaded_vmcs); |
8f536b76 | 1561 | crash_enable_local_vmclear(cpu); |
6aa8b732 AK |
1562 | } |
1563 | ||
d462b819 | 1564 | static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 1565 | { |
e6c7d321 XG |
1566 | int cpu = loaded_vmcs->cpu; |
1567 | ||
1568 | if (cpu != -1) | |
1569 | smp_call_function_single(cpu, | |
1570 | __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
1571 | } |
1572 | ||
dd5f5341 | 1573 | static inline void vpid_sync_vcpu_single(int vpid) |
2384d2b3 | 1574 | { |
dd5f5341 | 1575 | if (vpid == 0) |
2384d2b3 SY |
1576 | return; |
1577 | ||
518c8aee | 1578 | if (cpu_has_vmx_invvpid_single()) |
dd5f5341 | 1579 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0); |
2384d2b3 SY |
1580 | } |
1581 | ||
b9d762fa GJ |
1582 | static inline void vpid_sync_vcpu_global(void) |
1583 | { | |
1584 | if (cpu_has_vmx_invvpid_global()) | |
1585 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
1586 | } | |
1587 | ||
dd5f5341 | 1588 | static inline void vpid_sync_context(int vpid) |
b9d762fa GJ |
1589 | { |
1590 | if (cpu_has_vmx_invvpid_single()) | |
dd5f5341 | 1591 | vpid_sync_vcpu_single(vpid); |
b9d762fa GJ |
1592 | else |
1593 | vpid_sync_vcpu_global(); | |
1594 | } | |
1595 | ||
1439442c SY |
1596 | static inline void ept_sync_global(void) |
1597 | { | |
f5f51586 | 1598 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); |
1439442c SY |
1599 | } |
1600 | ||
1601 | static inline void ept_sync_context(u64 eptp) | |
1602 | { | |
0e1252dc DH |
1603 | if (cpu_has_vmx_invept_context()) |
1604 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
1605 | else | |
1606 | ept_sync_global(); | |
1439442c SY |
1607 | } |
1608 | ||
8a86aea9 PB |
1609 | static __always_inline void vmcs_check16(unsigned long field) |
1610 | { | |
1611 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1612 | "16-bit accessor invalid for 64-bit field"); | |
1613 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1614 | "16-bit accessor invalid for 64-bit high field"); | |
1615 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1616 | "16-bit accessor invalid for 32-bit high field"); | |
1617 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1618 | "16-bit accessor invalid for natural width field"); | |
1619 | } | |
1620 | ||
1621 | static __always_inline void vmcs_check32(unsigned long field) | |
1622 | { | |
1623 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1624 | "32-bit accessor invalid for 16-bit field"); | |
1625 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1626 | "32-bit accessor invalid for natural width field"); | |
1627 | } | |
1628 | ||
1629 | static __always_inline void vmcs_check64(unsigned long field) | |
1630 | { | |
1631 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1632 | "64-bit accessor invalid for 16-bit field"); | |
1633 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1634 | "64-bit accessor invalid for 64-bit high field"); | |
1635 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1636 | "64-bit accessor invalid for 32-bit field"); | |
1637 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1638 | "64-bit accessor invalid for natural width field"); | |
1639 | } | |
1640 | ||
1641 | static __always_inline void vmcs_checkl(unsigned long field) | |
1642 | { | |
1643 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1644 | "Natural width accessor invalid for 16-bit field"); | |
1645 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1646 | "Natural width accessor invalid for 64-bit field"); | |
1647 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1648 | "Natural width accessor invalid for 64-bit high field"); | |
1649 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1650 | "Natural width accessor invalid for 32-bit field"); | |
1651 | } | |
1652 | ||
1653 | static __always_inline unsigned long __vmcs_readl(unsigned long field) | |
6aa8b732 | 1654 | { |
5e520e62 | 1655 | unsigned long value; |
6aa8b732 | 1656 | |
5e520e62 AK |
1657 | asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
1658 | : "=a"(value) : "d"(field) : "cc"); | |
6aa8b732 AK |
1659 | return value; |
1660 | } | |
1661 | ||
96304217 | 1662 | static __always_inline u16 vmcs_read16(unsigned long field) |
6aa8b732 | 1663 | { |
8a86aea9 PB |
1664 | vmcs_check16(field); |
1665 | return __vmcs_readl(field); | |
6aa8b732 AK |
1666 | } |
1667 | ||
96304217 | 1668 | static __always_inline u32 vmcs_read32(unsigned long field) |
6aa8b732 | 1669 | { |
8a86aea9 PB |
1670 | vmcs_check32(field); |
1671 | return __vmcs_readl(field); | |
6aa8b732 AK |
1672 | } |
1673 | ||
96304217 | 1674 | static __always_inline u64 vmcs_read64(unsigned long field) |
6aa8b732 | 1675 | { |
8a86aea9 | 1676 | vmcs_check64(field); |
05b3e0c2 | 1677 | #ifdef CONFIG_X86_64 |
8a86aea9 | 1678 | return __vmcs_readl(field); |
6aa8b732 | 1679 | #else |
8a86aea9 | 1680 | return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32); |
6aa8b732 AK |
1681 | #endif |
1682 | } | |
1683 | ||
8a86aea9 PB |
1684 | static __always_inline unsigned long vmcs_readl(unsigned long field) |
1685 | { | |
1686 | vmcs_checkl(field); | |
1687 | return __vmcs_readl(field); | |
1688 | } | |
1689 | ||
e52de1b8 AK |
1690 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
1691 | { | |
1692 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
1693 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1694 | dump_stack(); | |
1695 | } | |
1696 | ||
8a86aea9 | 1697 | static __always_inline void __vmcs_writel(unsigned long field, unsigned long value) |
6aa8b732 AK |
1698 | { |
1699 | u8 error; | |
1700 | ||
4ecac3fd | 1701 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 1702 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
1703 | if (unlikely(error)) |
1704 | vmwrite_error(field, value); | |
6aa8b732 AK |
1705 | } |
1706 | ||
8a86aea9 | 1707 | static __always_inline void vmcs_write16(unsigned long field, u16 value) |
6aa8b732 | 1708 | { |
8a86aea9 PB |
1709 | vmcs_check16(field); |
1710 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1711 | } |
1712 | ||
8a86aea9 | 1713 | static __always_inline void vmcs_write32(unsigned long field, u32 value) |
6aa8b732 | 1714 | { |
8a86aea9 PB |
1715 | vmcs_check32(field); |
1716 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1717 | } |
1718 | ||
8a86aea9 | 1719 | static __always_inline void vmcs_write64(unsigned long field, u64 value) |
6aa8b732 | 1720 | { |
8a86aea9 PB |
1721 | vmcs_check64(field); |
1722 | __vmcs_writel(field, value); | |
7682f2d0 | 1723 | #ifndef CONFIG_X86_64 |
6aa8b732 | 1724 | asm volatile (""); |
8a86aea9 | 1725 | __vmcs_writel(field+1, value >> 32); |
6aa8b732 AK |
1726 | #endif |
1727 | } | |
1728 | ||
8a86aea9 | 1729 | static __always_inline void vmcs_writel(unsigned long field, unsigned long value) |
2ab455cc | 1730 | { |
8a86aea9 PB |
1731 | vmcs_checkl(field); |
1732 | __vmcs_writel(field, value); | |
2ab455cc AL |
1733 | } |
1734 | ||
8a86aea9 | 1735 | static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask) |
2ab455cc | 1736 | { |
8a86aea9 PB |
1737 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1738 | "vmcs_clear_bits does not support 64-bit fields"); | |
1739 | __vmcs_writel(field, __vmcs_readl(field) & ~mask); | |
2ab455cc AL |
1740 | } |
1741 | ||
8a86aea9 | 1742 | static __always_inline void vmcs_set_bits(unsigned long field, u32 mask) |
2ab455cc | 1743 | { |
8a86aea9 PB |
1744 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1745 | "vmcs_set_bits does not support 64-bit fields"); | |
1746 | __vmcs_writel(field, __vmcs_readl(field) | mask); | |
2ab455cc AL |
1747 | } |
1748 | ||
8391ce44 PB |
1749 | static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx) |
1750 | { | |
1751 | vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS); | |
1752 | } | |
1753 | ||
2961e876 GN |
1754 | static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val) |
1755 | { | |
1756 | vmcs_write32(VM_ENTRY_CONTROLS, val); | |
1757 | vmx->vm_entry_controls_shadow = val; | |
1758 | } | |
1759 | ||
1760 | static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1761 | { | |
1762 | if (vmx->vm_entry_controls_shadow != val) | |
1763 | vm_entry_controls_init(vmx, val); | |
1764 | } | |
1765 | ||
1766 | static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx) | |
1767 | { | |
1768 | return vmx->vm_entry_controls_shadow; | |
1769 | } | |
1770 | ||
1771 | ||
1772 | static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1773 | { | |
1774 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val); | |
1775 | } | |
1776 | ||
1777 | static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1778 | { | |
1779 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val); | |
1780 | } | |
1781 | ||
8391ce44 PB |
1782 | static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx) |
1783 | { | |
1784 | vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS); | |
1785 | } | |
1786 | ||
2961e876 GN |
1787 | static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val) |
1788 | { | |
1789 | vmcs_write32(VM_EXIT_CONTROLS, val); | |
1790 | vmx->vm_exit_controls_shadow = val; | |
1791 | } | |
1792 | ||
1793 | static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1794 | { | |
1795 | if (vmx->vm_exit_controls_shadow != val) | |
1796 | vm_exit_controls_init(vmx, val); | |
1797 | } | |
1798 | ||
1799 | static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx) | |
1800 | { | |
1801 | return vmx->vm_exit_controls_shadow; | |
1802 | } | |
1803 | ||
1804 | ||
1805 | static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1806 | { | |
1807 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val); | |
1808 | } | |
1809 | ||
1810 | static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1811 | { | |
1812 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val); | |
1813 | } | |
1814 | ||
2fb92db1 AK |
1815 | static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
1816 | { | |
1817 | vmx->segment_cache.bitmask = 0; | |
1818 | } | |
1819 | ||
1820 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, | |
1821 | unsigned field) | |
1822 | { | |
1823 | bool ret; | |
1824 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
1825 | ||
1826 | if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { | |
1827 | vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); | |
1828 | vmx->segment_cache.bitmask = 0; | |
1829 | } | |
1830 | ret = vmx->segment_cache.bitmask & mask; | |
1831 | vmx->segment_cache.bitmask |= mask; | |
1832 | return ret; | |
1833 | } | |
1834 | ||
1835 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
1836 | { | |
1837 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
1838 | ||
1839 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
1840 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
1841 | return *p; | |
1842 | } | |
1843 | ||
1844 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
1845 | { | |
1846 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
1847 | ||
1848 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
1849 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
1850 | return *p; | |
1851 | } | |
1852 | ||
1853 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
1854 | { | |
1855 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
1856 | ||
1857 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
1858 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
1859 | return *p; | |
1860 | } | |
1861 | ||
1862 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
1863 | { | |
1864 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
1865 | ||
1866 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
1867 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
1868 | return *p; | |
1869 | } | |
1870 | ||
abd3f2d6 AK |
1871 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
1872 | { | |
1873 | u32 eb; | |
1874 | ||
fd7373cc | 1875 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
bd7e5b08 | 1876 | (1u << DB_VECTOR) | (1u << AC_VECTOR); |
fd7373cc JK |
1877 | if ((vcpu->guest_debug & |
1878 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
1879 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
1880 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 1881 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 1882 | eb = ~0; |
089d034e | 1883 | if (enable_ept) |
1439442c | 1884 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
36cf24e0 NHE |
1885 | |
1886 | /* When we are running a nested L2 guest and L1 specified for it a | |
1887 | * certain exception bitmap, we must trap the same exceptions and pass | |
1888 | * them to L1. When running L2, we will only handle the exceptions | |
1889 | * specified above if L1 did not want them. | |
1890 | */ | |
1891 | if (is_guest_mode(vcpu)) | |
1892 | eb |= get_vmcs12(vcpu)->exception_bitmap; | |
1893 | ||
abd3f2d6 AK |
1894 | vmcs_write32(EXCEPTION_BITMAP, eb); |
1895 | } | |
1896 | ||
2961e876 GN |
1897 | static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1898 | unsigned long entry, unsigned long exit) | |
8bf00a52 | 1899 | { |
2961e876 GN |
1900 | vm_entry_controls_clearbit(vmx, entry); |
1901 | vm_exit_controls_clearbit(vmx, exit); | |
8bf00a52 GN |
1902 | } |
1903 | ||
61d2ef2c AK |
1904 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
1905 | { | |
1906 | unsigned i; | |
1907 | struct msr_autoload *m = &vmx->msr_autoload; | |
1908 | ||
8bf00a52 GN |
1909 | switch (msr) { |
1910 | case MSR_EFER: | |
1911 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1912 | clear_atomic_switch_msr_special(vmx, |
1913 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1914 | VM_EXIT_LOAD_IA32_EFER); |
1915 | return; | |
1916 | } | |
1917 | break; | |
1918 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1919 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1920 | clear_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1921 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1922 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
1923 | return; | |
1924 | } | |
1925 | break; | |
110312c8 AK |
1926 | } |
1927 | ||
61d2ef2c AK |
1928 | for (i = 0; i < m->nr; ++i) |
1929 | if (m->guest[i].index == msr) | |
1930 | break; | |
1931 | ||
1932 | if (i == m->nr) | |
1933 | return; | |
1934 | --m->nr; | |
1935 | m->guest[i] = m->guest[m->nr]; | |
1936 | m->host[i] = m->host[m->nr]; | |
1937 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1938 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1939 | } | |
1940 | ||
2961e876 GN |
1941 | static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1942 | unsigned long entry, unsigned long exit, | |
1943 | unsigned long guest_val_vmcs, unsigned long host_val_vmcs, | |
1944 | u64 guest_val, u64 host_val) | |
8bf00a52 GN |
1945 | { |
1946 | vmcs_write64(guest_val_vmcs, guest_val); | |
1947 | vmcs_write64(host_val_vmcs, host_val); | |
2961e876 GN |
1948 | vm_entry_controls_setbit(vmx, entry); |
1949 | vm_exit_controls_setbit(vmx, exit); | |
8bf00a52 GN |
1950 | } |
1951 | ||
61d2ef2c AK |
1952 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
1953 | u64 guest_val, u64 host_val) | |
1954 | { | |
1955 | unsigned i; | |
1956 | struct msr_autoload *m = &vmx->msr_autoload; | |
1957 | ||
8bf00a52 GN |
1958 | switch (msr) { |
1959 | case MSR_EFER: | |
1960 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1961 | add_atomic_switch_msr_special(vmx, |
1962 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1963 | VM_EXIT_LOAD_IA32_EFER, |
1964 | GUEST_IA32_EFER, | |
1965 | HOST_IA32_EFER, | |
1966 | guest_val, host_val); | |
1967 | return; | |
1968 | } | |
1969 | break; | |
1970 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1971 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1972 | add_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1973 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1974 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, | |
1975 | GUEST_IA32_PERF_GLOBAL_CTRL, | |
1976 | HOST_IA32_PERF_GLOBAL_CTRL, | |
1977 | guest_val, host_val); | |
1978 | return; | |
1979 | } | |
1980 | break; | |
7099e2e1 RK |
1981 | case MSR_IA32_PEBS_ENABLE: |
1982 | /* PEBS needs a quiescent period after being disabled (to write | |
1983 | * a record). Disabling PEBS through VMX MSR swapping doesn't | |
1984 | * provide that period, so a CPU could write host's record into | |
1985 | * guest's memory. | |
1986 | */ | |
1987 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
110312c8 AK |
1988 | } |
1989 | ||
61d2ef2c AK |
1990 | for (i = 0; i < m->nr; ++i) |
1991 | if (m->guest[i].index == msr) | |
1992 | break; | |
1993 | ||
e7fc6f93 | 1994 | if (i == NR_AUTOLOAD_MSRS) { |
60266204 | 1995 | printk_once(KERN_WARNING "Not enough msr switch entries. " |
e7fc6f93 GN |
1996 | "Can't add msr %x\n", msr); |
1997 | return; | |
1998 | } else if (i == m->nr) { | |
61d2ef2c AK |
1999 | ++m->nr; |
2000 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
2001 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
2002 | } | |
2003 | ||
2004 | m->guest[i].index = msr; | |
2005 | m->guest[i].value = guest_val; | |
2006 | m->host[i].index = msr; | |
2007 | m->host[i].value = host_val; | |
2008 | } | |
2009 | ||
92c0d900 | 2010 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 2011 | { |
844a5fe2 PB |
2012 | u64 guest_efer = vmx->vcpu.arch.efer; |
2013 | u64 ignore_bits = 0; | |
2014 | ||
2015 | if (!enable_ept) { | |
2016 | /* | |
2017 | * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing | |
2018 | * host CPUID is more efficient than testing guest CPUID | |
2019 | * or CR4. Host SMEP is anyway a requirement for guest SMEP. | |
2020 | */ | |
2021 | if (boot_cpu_has(X86_FEATURE_SMEP)) | |
2022 | guest_efer |= EFER_NX; | |
2023 | else if (!(guest_efer & EFER_NX)) | |
2024 | ignore_bits |= EFER_NX; | |
2025 | } | |
3a34a881 | 2026 | |
51c6cf66 | 2027 | /* |
844a5fe2 | 2028 | * LMA and LME handled by hardware; SCE meaningless outside long mode. |
51c6cf66 | 2029 | */ |
844a5fe2 | 2030 | ignore_bits |= EFER_SCE; |
51c6cf66 AK |
2031 | #ifdef CONFIG_X86_64 |
2032 | ignore_bits |= EFER_LMA | EFER_LME; | |
2033 | /* SCE is meaningful only in long mode on Intel */ | |
2034 | if (guest_efer & EFER_LMA) | |
2035 | ignore_bits &= ~(u64)EFER_SCE; | |
2036 | #endif | |
84ad33ef AK |
2037 | |
2038 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
f6577a5f AL |
2039 | |
2040 | /* | |
2041 | * On EPT, we can't emulate NX, so we must switch EFER atomically. | |
2042 | * On CPUs that support "load IA32_EFER", always switch EFER | |
2043 | * atomically, since it's faster than switching it manually. | |
2044 | */ | |
2045 | if (cpu_has_load_ia32_efer || | |
2046 | (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { | |
84ad33ef AK |
2047 | if (!(guest_efer & EFER_LMA)) |
2048 | guest_efer &= ~EFER_LME; | |
54b98bff AL |
2049 | if (guest_efer != host_efer) |
2050 | add_atomic_switch_msr(vmx, MSR_EFER, | |
2051 | guest_efer, host_efer); | |
84ad33ef | 2052 | return false; |
844a5fe2 PB |
2053 | } else { |
2054 | guest_efer &= ~ignore_bits; | |
2055 | guest_efer |= host_efer & ignore_bits; | |
2056 | ||
2057 | vmx->guest_msrs[efer_offset].data = guest_efer; | |
2058 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; | |
84ad33ef | 2059 | |
844a5fe2 PB |
2060 | return true; |
2061 | } | |
51c6cf66 AK |
2062 | } |
2063 | ||
e28baead AL |
2064 | #ifdef CONFIG_X86_32 |
2065 | /* | |
2066 | * On 32-bit kernels, VM exits still load the FS and GS bases from the | |
2067 | * VMCS rather than the segment table. KVM uses this helper to figure | |
2068 | * out the current bases to poke them into the VMCS before entry. | |
2069 | */ | |
2d49ec72 GN |
2070 | static unsigned long segment_base(u16 selector) |
2071 | { | |
8c2e41f7 | 2072 | struct desc_struct *table; |
2d49ec72 GN |
2073 | unsigned long v; |
2074 | ||
8c2e41f7 | 2075 | if (!(selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
2076 | return 0; |
2077 | ||
45fc8757 | 2078 | table = get_current_gdt_ro(); |
2d49ec72 | 2079 | |
8c2e41f7 | 2080 | if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { |
2d49ec72 GN |
2081 | u16 ldt_selector = kvm_read_ldt(); |
2082 | ||
8c2e41f7 | 2083 | if (!(ldt_selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
2084 | return 0; |
2085 | ||
8c2e41f7 | 2086 | table = (struct desc_struct *)segment_base(ldt_selector); |
2d49ec72 | 2087 | } |
8c2e41f7 | 2088 | v = get_desc_base(&table[selector >> 3]); |
2d49ec72 GN |
2089 | return v; |
2090 | } | |
e28baead | 2091 | #endif |
2d49ec72 | 2092 | |
04d2cc77 | 2093 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 2094 | { |
04d2cc77 | 2095 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 2096 | int i; |
04d2cc77 | 2097 | |
a2fa3e9f | 2098 | if (vmx->host_state.loaded) |
33ed6329 AK |
2099 | return; |
2100 | ||
a2fa3e9f | 2101 | vmx->host_state.loaded = 1; |
33ed6329 AK |
2102 | /* |
2103 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
2104 | * allow segment selectors with cpl > 0 or ti == 1. | |
2105 | */ | |
d6e88aec | 2106 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 2107 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 2108 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 2109 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 2110 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
2111 | vmx->host_state.fs_reload_needed = 0; |
2112 | } else { | |
33ed6329 | 2113 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 2114 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 2115 | } |
9581d442 | 2116 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
2117 | if (!(vmx->host_state.gs_sel & 7)) |
2118 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
2119 | else { |
2120 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 2121 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
2122 | } |
2123 | ||
b2da15ac AK |
2124 | #ifdef CONFIG_X86_64 |
2125 | savesegment(ds, vmx->host_state.ds_sel); | |
2126 | savesegment(es, vmx->host_state.es_sel); | |
2127 | #endif | |
2128 | ||
33ed6329 AK |
2129 | #ifdef CONFIG_X86_64 |
2130 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
2131 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
2132 | #else | |
a2fa3e9f GH |
2133 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
2134 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 2135 | #endif |
707c0874 AK |
2136 | |
2137 | #ifdef CONFIG_X86_64 | |
c8770e7b AK |
2138 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
2139 | if (is_long_mode(&vmx->vcpu)) | |
44ea2b17 | 2140 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
707c0874 | 2141 | #endif |
da8999d3 LJ |
2142 | if (boot_cpu_has(X86_FEATURE_MPX)) |
2143 | rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
26bb0981 AK |
2144 | for (i = 0; i < vmx->save_nmsrs; ++i) |
2145 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
2146 | vmx->guest_msrs[i].data, |
2147 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
2148 | } |
2149 | ||
a9b21b62 | 2150 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 2151 | { |
a2fa3e9f | 2152 | if (!vmx->host_state.loaded) |
33ed6329 AK |
2153 | return; |
2154 | ||
e1beb1d3 | 2155 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 2156 | vmx->host_state.loaded = 0; |
c8770e7b AK |
2157 | #ifdef CONFIG_X86_64 |
2158 | if (is_long_mode(&vmx->vcpu)) | |
2159 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
2160 | #endif | |
152d3f2f | 2161 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 2162 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 2163 | #ifdef CONFIG_X86_64 |
9581d442 | 2164 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
2165 | #else |
2166 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 2167 | #endif |
33ed6329 | 2168 | } |
0a77fe4c AK |
2169 | if (vmx->host_state.fs_reload_needed) |
2170 | loadsegment(fs, vmx->host_state.fs_sel); | |
b2da15ac AK |
2171 | #ifdef CONFIG_X86_64 |
2172 | if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) { | |
2173 | loadsegment(ds, vmx->host_state.ds_sel); | |
2174 | loadsegment(es, vmx->host_state.es_sel); | |
2175 | } | |
b2da15ac | 2176 | #endif |
b7ffc44d | 2177 | invalidate_tss_limit(); |
44ea2b17 | 2178 | #ifdef CONFIG_X86_64 |
c8770e7b | 2179 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 2180 | #endif |
da8999d3 LJ |
2181 | if (vmx->host_state.msr_host_bndcfgs) |
2182 | wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
45fc8757 | 2183 | load_fixmap_gdt(raw_smp_processor_id()); |
33ed6329 AK |
2184 | } |
2185 | ||
a9b21b62 AK |
2186 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
2187 | { | |
2188 | preempt_disable(); | |
2189 | __vmx_load_host_state(vmx); | |
2190 | preempt_enable(); | |
2191 | } | |
2192 | ||
28b835d6 FW |
2193 | static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) |
2194 | { | |
2195 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2196 | struct pi_desc old, new; | |
2197 | unsigned int dest; | |
2198 | ||
31afb2ea PB |
2199 | /* |
2200 | * In case of hot-plug or hot-unplug, we may have to undo | |
2201 | * vmx_vcpu_pi_put even if there is no assigned device. And we | |
2202 | * always keep PI.NDST up to date for simplicity: it makes the | |
2203 | * code easier, and CPU migration is not a fast path. | |
2204 | */ | |
2205 | if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) | |
28b835d6 FW |
2206 | return; |
2207 | ||
31afb2ea PB |
2208 | /* |
2209 | * First handle the simple case where no cmpxchg is necessary; just | |
2210 | * allow posting non-urgent interrupts. | |
2211 | * | |
2212 | * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change | |
2213 | * PI.NDST: pi_post_block will do it for us and the wakeup_handler | |
2214 | * expects the VCPU to be on the blocked_vcpu_list that matches | |
2215 | * PI.NDST. | |
2216 | */ | |
2217 | if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || | |
2218 | vcpu->cpu == cpu) { | |
2219 | pi_clear_sn(pi_desc); | |
28b835d6 | 2220 | return; |
31afb2ea | 2221 | } |
28b835d6 | 2222 | |
31afb2ea | 2223 | /* The full case. */ |
28b835d6 FW |
2224 | do { |
2225 | old.control = new.control = pi_desc->control; | |
2226 | ||
31afb2ea | 2227 | dest = cpu_physical_id(cpu); |
28b835d6 | 2228 | |
31afb2ea PB |
2229 | if (x2apic_enabled()) |
2230 | new.ndst = dest; | |
2231 | else | |
2232 | new.ndst = (dest << 8) & 0xFF00; | |
28b835d6 | 2233 | |
28b835d6 | 2234 | new.sn = 0; |
c0a1666b PB |
2235 | } while (cmpxchg64(&pi_desc->control, old.control, |
2236 | new.control) != old.control); | |
28b835d6 | 2237 | } |
1be0e61c | 2238 | |
c95ba92a PF |
2239 | static void decache_tsc_multiplier(struct vcpu_vmx *vmx) |
2240 | { | |
2241 | vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio; | |
2242 | vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); | |
2243 | } | |
2244 | ||
6aa8b732 AK |
2245 | /* |
2246 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
2247 | * vcpu mutex is already taken. | |
2248 | */ | |
15ad7146 | 2249 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 2250 | { |
a2fa3e9f | 2251 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b80c76ec | 2252 | bool already_loaded = vmx->loaded_vmcs->cpu == cpu; |
6aa8b732 | 2253 | |
b80c76ec | 2254 | if (!already_loaded) { |
fe0e80be | 2255 | loaded_vmcs_clear(vmx->loaded_vmcs); |
92fe13be | 2256 | local_irq_disable(); |
8f536b76 | 2257 | crash_disable_local_vmclear(cpu); |
5a560f8b XG |
2258 | |
2259 | /* | |
2260 | * Read loaded_vmcs->cpu should be before fetching | |
2261 | * loaded_vmcs->loaded_vmcss_on_cpu_link. | |
2262 | * See the comments in __loaded_vmcs_clear(). | |
2263 | */ | |
2264 | smp_rmb(); | |
2265 | ||
d462b819 NHE |
2266 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
2267 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
8f536b76 | 2268 | crash_enable_local_vmclear(cpu); |
92fe13be | 2269 | local_irq_enable(); |
b80c76ec JM |
2270 | } |
2271 | ||
2272 | if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { | |
2273 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; | |
2274 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
2275 | } | |
2276 | ||
2277 | if (!already_loaded) { | |
59c58ceb | 2278 | void *gdt = get_current_gdt_ro(); |
b80c76ec JM |
2279 | unsigned long sysenter_esp; |
2280 | ||
2281 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
92fe13be | 2282 | |
6aa8b732 AK |
2283 | /* |
2284 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
e0c23063 | 2285 | * processors. See 22.2.4. |
6aa8b732 | 2286 | */ |
e0c23063 AL |
2287 | vmcs_writel(HOST_TR_BASE, |
2288 | (unsigned long)this_cpu_ptr(&cpu_tss)); | |
59c58ceb | 2289 | vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ |
6aa8b732 | 2290 | |
b7ffc44d AL |
2291 | /* |
2292 | * VM exits change the host TR limit to 0x67 after a VM | |
2293 | * exit. This is okay, since 0x67 covers everything except | |
2294 | * the IO bitmap and have have code to handle the IO bitmap | |
2295 | * being lost after a VM exit. | |
2296 | */ | |
2297 | BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67); | |
2298 | ||
6aa8b732 AK |
2299 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); |
2300 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
ff2c3a18 | 2301 | |
d462b819 | 2302 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 2303 | } |
28b835d6 | 2304 | |
2680d6da OH |
2305 | /* Setup TSC multiplier */ |
2306 | if (kvm_has_tsc_control && | |
c95ba92a PF |
2307 | vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) |
2308 | decache_tsc_multiplier(vmx); | |
2680d6da | 2309 | |
28b835d6 | 2310 | vmx_vcpu_pi_load(vcpu, cpu); |
1be0e61c | 2311 | vmx->host_pkru = read_pkru(); |
28b835d6 FW |
2312 | } |
2313 | ||
2314 | static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) | |
2315 | { | |
2316 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2317 | ||
2318 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
2319 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
2320 | !kvm_vcpu_apicv_active(vcpu)) | |
28b835d6 FW |
2321 | return; |
2322 | ||
2323 | /* Set SN when the vCPU is preempted */ | |
2324 | if (vcpu->preempted) | |
2325 | pi_set_sn(pi_desc); | |
6aa8b732 AK |
2326 | } |
2327 | ||
2328 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
2329 | { | |
28b835d6 FW |
2330 | vmx_vcpu_pi_put(vcpu); |
2331 | ||
a9b21b62 | 2332 | __vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
2333 | } |
2334 | ||
f244deed WL |
2335 | static bool emulation_required(struct kvm_vcpu *vcpu) |
2336 | { | |
2337 | return emulate_invalid_guest_state && !guest_state_valid(vcpu); | |
2338 | } | |
2339 | ||
edcafe3c AK |
2340 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
2341 | ||
fe3ef05c NHE |
2342 | /* |
2343 | * Return the cr0 value that a nested guest would read. This is a combination | |
2344 | * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by | |
2345 | * its hypervisor (cr0_read_shadow). | |
2346 | */ | |
2347 | static inline unsigned long nested_read_cr0(struct vmcs12 *fields) | |
2348 | { | |
2349 | return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | | |
2350 | (fields->cr0_read_shadow & fields->cr0_guest_host_mask); | |
2351 | } | |
2352 | static inline unsigned long nested_read_cr4(struct vmcs12 *fields) | |
2353 | { | |
2354 | return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | | |
2355 | (fields->cr4_read_shadow & fields->cr4_guest_host_mask); | |
2356 | } | |
2357 | ||
6aa8b732 AK |
2358 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
2359 | { | |
78ac8b47 | 2360 | unsigned long rflags, save_rflags; |
345dcaa8 | 2361 | |
6de12732 AK |
2362 | if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
2363 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); | |
2364 | rflags = vmcs_readl(GUEST_RFLAGS); | |
2365 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
2366 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2367 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
2368 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2369 | } | |
2370 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 | 2371 | } |
6de12732 | 2372 | return to_vmx(vcpu)->rflags; |
6aa8b732 AK |
2373 | } |
2374 | ||
2375 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
2376 | { | |
f244deed WL |
2377 | unsigned long old_rflags = vmx_get_rflags(vcpu); |
2378 | ||
6de12732 AK |
2379 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
2380 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 AK |
2381 | if (to_vmx(vcpu)->rmode.vm86_active) { |
2382 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 2383 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 2384 | } |
6aa8b732 | 2385 | vmcs_writel(GUEST_RFLAGS, rflags); |
f244deed WL |
2386 | |
2387 | if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM) | |
2388 | to_vmx(vcpu)->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
2389 | } |
2390 | ||
37ccdcbe | 2391 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
2392 | { |
2393 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2394 | int ret = 0; | |
2395 | ||
2396 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 2397 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 2398 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 2399 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 | 2400 | |
37ccdcbe | 2401 | return ret; |
2809f5d2 GC |
2402 | } |
2403 | ||
2404 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
2405 | { | |
2406 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2407 | u32 interruptibility = interruptibility_old; | |
2408 | ||
2409 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
2410 | ||
48005f64 | 2411 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 2412 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 2413 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
2414 | interruptibility |= GUEST_INTR_STATE_STI; |
2415 | ||
2416 | if ((interruptibility != interruptibility_old)) | |
2417 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
2418 | } | |
2419 | ||
6aa8b732 AK |
2420 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
2421 | { | |
2422 | unsigned long rip; | |
6aa8b732 | 2423 | |
5fdbf976 | 2424 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 2425 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 2426 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 2427 | |
2809f5d2 GC |
2428 | /* skipping an emulated instruction also counts */ |
2429 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
2430 | } |
2431 | ||
b96fb439 PB |
2432 | static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu, |
2433 | unsigned long exit_qual) | |
2434 | { | |
2435 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2436 | unsigned int nr = vcpu->arch.exception.nr; | |
2437 | u32 intr_info = nr | INTR_INFO_VALID_MASK; | |
2438 | ||
2439 | if (vcpu->arch.exception.has_error_code) { | |
2440 | vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code; | |
2441 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; | |
2442 | } | |
2443 | ||
2444 | if (kvm_exception_is_soft(nr)) | |
2445 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; | |
2446 | else | |
2447 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2448 | ||
2449 | if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) && | |
2450 | vmx_get_nmi_mask(vcpu)) | |
2451 | intr_info |= INTR_INFO_UNBLOCK_NMI; | |
2452 | ||
2453 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual); | |
2454 | } | |
2455 | ||
0b6ac343 NHE |
2456 | /* |
2457 | * KVM wants to inject page-faults which it got to the guest. This function | |
2458 | * checks whether in a nested guest, we need to inject them to L1 or L2. | |
0b6ac343 | 2459 | */ |
bfcf83b1 | 2460 | static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual) |
0b6ac343 NHE |
2461 | { |
2462 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
adfe20fb | 2463 | unsigned int nr = vcpu->arch.exception.nr; |
0b6ac343 | 2464 | |
b96fb439 PB |
2465 | if (nr == PF_VECTOR) { |
2466 | if (vcpu->arch.exception.nested_apf) { | |
bfcf83b1 | 2467 | *exit_qual = vcpu->arch.apf.nested_apf_token; |
b96fb439 PB |
2468 | return 1; |
2469 | } | |
2470 | /* | |
2471 | * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception. | |
2472 | * The fix is to add the ancillary datum (CR2 or DR6) to structs | |
2473 | * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 | |
2474 | * can be written only when inject_pending_event runs. This should be | |
2475 | * conditional on a new capability---if the capability is disabled, | |
2476 | * kvm_multiple_exception would write the ancillary information to | |
2477 | * CR2 or DR6, for backwards ABI-compatibility. | |
2478 | */ | |
2479 | if (nested_vmx_is_page_fault_vmexit(vmcs12, | |
2480 | vcpu->arch.exception.error_code)) { | |
bfcf83b1 | 2481 | *exit_qual = vcpu->arch.cr2; |
b96fb439 PB |
2482 | return 1; |
2483 | } | |
2484 | } else { | |
b96fb439 | 2485 | if (vmcs12->exception_bitmap & (1u << nr)) { |
bfcf83b1 WL |
2486 | if (nr == DB_VECTOR) |
2487 | *exit_qual = vcpu->arch.dr6; | |
2488 | else | |
2489 | *exit_qual = 0; | |
b96fb439 PB |
2490 | return 1; |
2491 | } | |
adfe20fb WL |
2492 | } |
2493 | ||
b96fb439 | 2494 | return 0; |
0b6ac343 NHE |
2495 | } |
2496 | ||
cfcd20e5 | 2497 | static void vmx_queue_exception(struct kvm_vcpu *vcpu) |
298101da | 2498 | { |
77ab6db0 | 2499 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
cfcd20e5 WL |
2500 | unsigned nr = vcpu->arch.exception.nr; |
2501 | bool has_error_code = vcpu->arch.exception.has_error_code; | |
cfcd20e5 | 2502 | u32 error_code = vcpu->arch.exception.error_code; |
8ab2d2e2 | 2503 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 2504 | |
8ab2d2e2 | 2505 | if (has_error_code) { |
77ab6db0 | 2506 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
2507 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
2508 | } | |
77ab6db0 | 2509 | |
7ffd92c5 | 2510 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
2511 | int inc_eip = 0; |
2512 | if (kvm_exception_is_soft(nr)) | |
2513 | inc_eip = vcpu->arch.event_exit_inst_len; | |
2514 | if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) | |
a92601bb | 2515 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
77ab6db0 JK |
2516 | return; |
2517 | } | |
2518 | ||
66fd3f7f GN |
2519 | if (kvm_exception_is_soft(nr)) { |
2520 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2521 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
2522 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
2523 | } else | |
2524 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2525 | ||
2526 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
298101da AK |
2527 | } |
2528 | ||
4e47c7a6 SY |
2529 | static bool vmx_rdtscp_supported(void) |
2530 | { | |
2531 | return cpu_has_vmx_rdtscp(); | |
2532 | } | |
2533 | ||
ad756a16 MJ |
2534 | static bool vmx_invpcid_supported(void) |
2535 | { | |
2536 | return cpu_has_vmx_invpcid() && enable_ept; | |
2537 | } | |
2538 | ||
a75beee6 ED |
2539 | /* |
2540 | * Swap MSR entry in host/guest MSR entry array. | |
2541 | */ | |
8b9cf98c | 2542 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 2543 | { |
26bb0981 | 2544 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
2545 | |
2546 | tmp = vmx->guest_msrs[to]; | |
2547 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
2548 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
2549 | } |
2550 | ||
8d14695f YZ |
2551 | static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu) |
2552 | { | |
2553 | unsigned long *msr_bitmap; | |
2554 | ||
670125bd | 2555 | if (is_guest_mode(vcpu)) |
d048c098 | 2556 | msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap; |
3ce424e4 RK |
2557 | else if (cpu_has_secondary_exec_ctrls() && |
2558 | (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) & | |
2559 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { | |
f6e90f9e WL |
2560 | if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) { |
2561 | if (is_long_mode(vcpu)) | |
c63e4563 | 2562 | msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv; |
f6e90f9e | 2563 | else |
c63e4563 | 2564 | msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv; |
f6e90f9e WL |
2565 | } else { |
2566 | if (is_long_mode(vcpu)) | |
c63e4563 | 2567 | msr_bitmap = vmx_msr_bitmap_longmode_x2apic; |
f6e90f9e | 2568 | else |
c63e4563 | 2569 | msr_bitmap = vmx_msr_bitmap_legacy_x2apic; |
f6e90f9e | 2570 | } |
8d14695f YZ |
2571 | } else { |
2572 | if (is_long_mode(vcpu)) | |
2573 | msr_bitmap = vmx_msr_bitmap_longmode; | |
2574 | else | |
2575 | msr_bitmap = vmx_msr_bitmap_legacy; | |
2576 | } | |
2577 | ||
2578 | vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); | |
2579 | } | |
2580 | ||
e38aea3e AK |
2581 | /* |
2582 | * Set up the vmcs to automatically save and restore system | |
2583 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
2584 | * mode, as fiddling with msrs is very expensive. | |
2585 | */ | |
8b9cf98c | 2586 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 2587 | { |
26bb0981 | 2588 | int save_nmsrs, index; |
e38aea3e | 2589 | |
a75beee6 ED |
2590 | save_nmsrs = 0; |
2591 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 2592 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 2593 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 2594 | if (index >= 0) |
8b9cf98c RR |
2595 | move_msr_up(vmx, index, save_nmsrs++); |
2596 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 2597 | if (index >= 0) |
8b9cf98c RR |
2598 | move_msr_up(vmx, index, save_nmsrs++); |
2599 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 2600 | if (index >= 0) |
8b9cf98c | 2601 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 | 2602 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
d6321d49 | 2603 | if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) |
4e47c7a6 | 2604 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 | 2605 | /* |
8c06585d | 2606 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
2607 | * if efer.sce is enabled. |
2608 | */ | |
8c06585d | 2609 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 2610 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 2611 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
2612 | } |
2613 | #endif | |
92c0d900 AK |
2614 | index = __find_msr_index(vmx, MSR_EFER); |
2615 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 2616 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 2617 | |
26bb0981 | 2618 | vmx->save_nmsrs = save_nmsrs; |
5897297b | 2619 | |
8d14695f YZ |
2620 | if (cpu_has_vmx_msr_bitmap()) |
2621 | vmx_set_msr_bitmap(&vmx->vcpu); | |
e38aea3e AK |
2622 | } |
2623 | ||
6aa8b732 AK |
2624 | /* |
2625 | * reads and returns guest's timestamp counter "register" | |
be7b263e HZ |
2626 | * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset |
2627 | * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3 | |
6aa8b732 | 2628 | */ |
be7b263e | 2629 | static u64 guest_read_tsc(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
2630 | { |
2631 | u64 host_tsc, tsc_offset; | |
2632 | ||
4ea1636b | 2633 | host_tsc = rdtsc(); |
6aa8b732 | 2634 | tsc_offset = vmcs_read64(TSC_OFFSET); |
be7b263e | 2635 | return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset; |
6aa8b732 AK |
2636 | } |
2637 | ||
2638 | /* | |
99e3e30a | 2639 | * writes 'offset' into guest's timestamp counter offset register |
6aa8b732 | 2640 | */ |
99e3e30a | 2641 | static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 2642 | { |
27fc51b2 | 2643 | if (is_guest_mode(vcpu)) { |
7991825b | 2644 | /* |
27fc51b2 NHE |
2645 | * We're here if L1 chose not to trap WRMSR to TSC. According |
2646 | * to the spec, this should set L1's TSC; The offset that L1 | |
2647 | * set for L2 remains unchanged, and still needs to be added | |
2648 | * to the newly set TSC to get L2's TSC. | |
7991825b | 2649 | */ |
27fc51b2 | 2650 | struct vmcs12 *vmcs12; |
27fc51b2 NHE |
2651 | /* recalculate vmcs02.TSC_OFFSET: */ |
2652 | vmcs12 = get_vmcs12(vcpu); | |
2653 | vmcs_write64(TSC_OFFSET, offset + | |
2654 | (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ? | |
2655 | vmcs12->tsc_offset : 0)); | |
2656 | } else { | |
489223ed YY |
2657 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2658 | vmcs_read64(TSC_OFFSET), offset); | |
27fc51b2 NHE |
2659 | vmcs_write64(TSC_OFFSET, offset); |
2660 | } | |
6aa8b732 AK |
2661 | } |
2662 | ||
801d3424 NHE |
2663 | /* |
2664 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
2665 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
2666 | * all guests if the "nested" module option is off, and can also be disabled | |
2667 | * for a single guest by disabling its VMX cpuid bit. | |
2668 | */ | |
2669 | static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) | |
2670 | { | |
d6321d49 | 2671 | return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); |
801d3424 NHE |
2672 | } |
2673 | ||
b87a51ae NHE |
2674 | /* |
2675 | * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be | |
2676 | * returned for the various VMX controls MSRs when nested VMX is enabled. | |
2677 | * The same values should also be used to verify that vmcs12 control fields are | |
2678 | * valid during nested entry from L1 to L2. | |
2679 | * Each of these control msrs has a low and high 32-bit half: A low bit is on | |
2680 | * if the corresponding bit in the (32-bit) control field *must* be on, and a | |
2681 | * bit in the high half is on if the corresponding bit in the control field | |
2682 | * may be on. See also vmx_control_verify(). | |
b87a51ae | 2683 | */ |
b9c237bb | 2684 | static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx) |
b87a51ae NHE |
2685 | { |
2686 | /* | |
2687 | * Note that as a general rule, the high half of the MSRs (bits in | |
2688 | * the control fields which may be 1) should be initialized by the | |
2689 | * intersection of the underlying hardware's MSR (i.e., features which | |
2690 | * can be supported) and the list of features we want to expose - | |
2691 | * because they are known to be properly supported in our code. | |
2692 | * Also, usually, the low half of the MSRs (bits which must be 1) can | |
2693 | * be set to 0, meaning that L1 may turn off any of these bits. The | |
2694 | * reason is that if one of these bits is necessary, it will appear | |
2695 | * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control | |
2696 | * fields of vmcs01 and vmcs02, will turn these bits off - and | |
7313c698 | 2697 | * nested_vmx_exit_reflected() will not pass related exits to L1. |
b87a51ae NHE |
2698 | * These rules have exceptions below. |
2699 | */ | |
2700 | ||
2701 | /* pin-based controls */ | |
eabeaacc | 2702 | rdmsr(MSR_IA32_VMX_PINBASED_CTLS, |
b9c237bb WV |
2703 | vmx->nested.nested_vmx_pinbased_ctls_low, |
2704 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
2705 | vmx->nested.nested_vmx_pinbased_ctls_low |= | |
2706 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2707 | vmx->nested.nested_vmx_pinbased_ctls_high &= | |
2708 | PIN_BASED_EXT_INTR_MASK | | |
2709 | PIN_BASED_NMI_EXITING | | |
2710 | PIN_BASED_VIRTUAL_NMIS; | |
2711 | vmx->nested.nested_vmx_pinbased_ctls_high |= | |
2712 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
0238ea91 | 2713 | PIN_BASED_VMX_PREEMPTION_TIMER; |
d62caabb | 2714 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) |
705699a1 WV |
2715 | vmx->nested.nested_vmx_pinbased_ctls_high |= |
2716 | PIN_BASED_POSTED_INTR; | |
b87a51ae | 2717 | |
3dbcd8da | 2718 | /* exit controls */ |
c0dfee58 | 2719 | rdmsr(MSR_IA32_VMX_EXIT_CTLS, |
b9c237bb WV |
2720 | vmx->nested.nested_vmx_exit_ctls_low, |
2721 | vmx->nested.nested_vmx_exit_ctls_high); | |
2722 | vmx->nested.nested_vmx_exit_ctls_low = | |
2723 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
e0ba1a6f | 2724 | |
b9c237bb | 2725 | vmx->nested.nested_vmx_exit_ctls_high &= |
b87a51ae | 2726 | #ifdef CONFIG_X86_64 |
c0dfee58 | 2727 | VM_EXIT_HOST_ADDR_SPACE_SIZE | |
b87a51ae | 2728 | #endif |
f4124500 | 2729 | VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT; |
b9c237bb WV |
2730 | vmx->nested.nested_vmx_exit_ctls_high |= |
2731 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | | |
f4124500 | 2732 | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | |
e0ba1a6f BD |
2733 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; |
2734 | ||
a87036ad | 2735 | if (kvm_mpx_supported()) |
b9c237bb | 2736 | vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; |
b87a51ae | 2737 | |
2996fca0 | 2738 | /* We support free control of debug control saving. */ |
0115f9cb | 2739 | vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS; |
2996fca0 | 2740 | |
b87a51ae NHE |
2741 | /* entry controls */ |
2742 | rdmsr(MSR_IA32_VMX_ENTRY_CTLS, | |
b9c237bb WV |
2743 | vmx->nested.nested_vmx_entry_ctls_low, |
2744 | vmx->nested.nested_vmx_entry_ctls_high); | |
2745 | vmx->nested.nested_vmx_entry_ctls_low = | |
2746 | VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
2747 | vmx->nested.nested_vmx_entry_ctls_high &= | |
57435349 JK |
2748 | #ifdef CONFIG_X86_64 |
2749 | VM_ENTRY_IA32E_MODE | | |
2750 | #endif | |
2751 | VM_ENTRY_LOAD_IA32_PAT; | |
b9c237bb WV |
2752 | vmx->nested.nested_vmx_entry_ctls_high |= |
2753 | (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER); | |
a87036ad | 2754 | if (kvm_mpx_supported()) |
b9c237bb | 2755 | vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; |
57435349 | 2756 | |
2996fca0 | 2757 | /* We support free control of debug control loading. */ |
0115f9cb | 2758 | vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS; |
2996fca0 | 2759 | |
b87a51ae NHE |
2760 | /* cpu-based controls */ |
2761 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, | |
b9c237bb WV |
2762 | vmx->nested.nested_vmx_procbased_ctls_low, |
2763 | vmx->nested.nested_vmx_procbased_ctls_high); | |
2764 | vmx->nested.nested_vmx_procbased_ctls_low = | |
2765 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2766 | vmx->nested.nested_vmx_procbased_ctls_high &= | |
a294c9bb JK |
2767 | CPU_BASED_VIRTUAL_INTR_PENDING | |
2768 | CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING | | |
b87a51ae NHE |
2769 | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | |
2770 | CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | | |
2771 | CPU_BASED_CR3_STORE_EXITING | | |
2772 | #ifdef CONFIG_X86_64 | |
2773 | CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | | |
2774 | #endif | |
2775 | CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | | |
5f3d45e7 MD |
2776 | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG | |
2777 | CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING | | |
2778 | CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING | | |
2779 | CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
b87a51ae NHE |
2780 | /* |
2781 | * We can allow some features even when not supported by the | |
2782 | * hardware. For example, L1 can specify an MSR bitmap - and we | |
2783 | * can use it to avoid exits to L1 - even when L0 runs L2 | |
2784 | * without MSR bitmaps. | |
2785 | */ | |
b9c237bb WV |
2786 | vmx->nested.nested_vmx_procbased_ctls_high |= |
2787 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
560b7ee1 | 2788 | CPU_BASED_USE_MSR_BITMAPS; |
b87a51ae | 2789 | |
3dcdf3ec | 2790 | /* We support free control of CR3 access interception. */ |
0115f9cb | 2791 | vmx->nested.nested_vmx_procbased_ctls_low &= |
3dcdf3ec JK |
2792 | ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); |
2793 | ||
80154d77 PB |
2794 | /* |
2795 | * secondary cpu-based controls. Do not include those that | |
2796 | * depend on CPUID bits, they are added later by vmx_cpuid_update. | |
2797 | */ | |
b87a51ae | 2798 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, |
b9c237bb WV |
2799 | vmx->nested.nested_vmx_secondary_ctls_low, |
2800 | vmx->nested.nested_vmx_secondary_ctls_high); | |
2801 | vmx->nested.nested_vmx_secondary_ctls_low = 0; | |
2802 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
d6851fbe | 2803 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
1b07304c | 2804 | SECONDARY_EXEC_DESC | |
f2b93280 | 2805 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
82f0dd4b | 2806 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
608406e2 | 2807 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
3db13480 | 2808 | SECONDARY_EXEC_WBINVD_EXITING; |
c18911a2 | 2809 | |
afa61f75 NHE |
2810 | if (enable_ept) { |
2811 | /* nested EPT: emulate EPT also to L1 */ | |
b9c237bb | 2812 | vmx->nested.nested_vmx_secondary_ctls_high |= |
0790ec17 | 2813 | SECONDARY_EXEC_ENABLE_EPT; |
b9c237bb | 2814 | vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT | |
7db74265 | 2815 | VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT; |
02120c45 BD |
2816 | if (cpu_has_vmx_ept_execute_only()) |
2817 | vmx->nested.nested_vmx_ept_caps |= | |
2818 | VMX_EPT_EXECUTE_ONLY_BIT; | |
b9c237bb | 2819 | vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept; |
45e11817 | 2820 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT | |
7db74265 PB |
2821 | VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT | |
2822 | VMX_EPT_1GB_PAGE_BIT; | |
03efce6f BD |
2823 | if (enable_ept_ad_bits) { |
2824 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2825 | SECONDARY_EXEC_ENABLE_PML; | |
7461fbc4 | 2826 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT; |
03efce6f | 2827 | } |
1c13bffd | 2828 | } |
afa61f75 | 2829 | |
27c42a1b BD |
2830 | if (cpu_has_vmx_vmfunc()) { |
2831 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2832 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
41ab9372 BD |
2833 | /* |
2834 | * Advertise EPTP switching unconditionally | |
2835 | * since we emulate it | |
2836 | */ | |
2837 | vmx->nested.nested_vmx_vmfunc_controls = | |
2838 | VMX_VMFUNC_EPTP_SWITCHING; | |
27c42a1b BD |
2839 | } |
2840 | ||
ef697a71 PB |
2841 | /* |
2842 | * Old versions of KVM use the single-context version without | |
2843 | * checking for support, so declare that it is supported even | |
2844 | * though it is treated as global context. The alternative is | |
2845 | * not failing the single-context invvpid, and it is worse. | |
2846 | */ | |
63cb6d5f WL |
2847 | if (enable_vpid) { |
2848 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2849 | SECONDARY_EXEC_ENABLE_VPID; | |
089d7b6e | 2850 | vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT | |
bcdde302 | 2851 | VMX_VPID_EXTENT_SUPPORTED_MASK; |
1c13bffd | 2852 | } |
99b83ac8 | 2853 | |
0790ec17 RK |
2854 | if (enable_unrestricted_guest) |
2855 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2856 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
2857 | ||
c18911a2 | 2858 | /* miscellaneous data */ |
b9c237bb WV |
2859 | rdmsr(MSR_IA32_VMX_MISC, |
2860 | vmx->nested.nested_vmx_misc_low, | |
2861 | vmx->nested.nested_vmx_misc_high); | |
2862 | vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA; | |
2863 | vmx->nested.nested_vmx_misc_low |= | |
2864 | VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | | |
f4124500 | 2865 | VMX_MISC_ACTIVITY_HLT; |
b9c237bb | 2866 | vmx->nested.nested_vmx_misc_high = 0; |
62cc6b9d DM |
2867 | |
2868 | /* | |
2869 | * This MSR reports some information about VMX support. We | |
2870 | * should return information about the VMX we emulate for the | |
2871 | * guest, and the VMCS structure we give it - not about the | |
2872 | * VMX support of the underlying hardware. | |
2873 | */ | |
2874 | vmx->nested.nested_vmx_basic = | |
2875 | VMCS12_REVISION | | |
2876 | VMX_BASIC_TRUE_CTLS | | |
2877 | ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | | |
2878 | (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); | |
2879 | ||
2880 | if (cpu_has_vmx_basic_inout()) | |
2881 | vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT; | |
2882 | ||
2883 | /* | |
8322ebbb | 2884 | * These MSRs specify bits which the guest must keep fixed on |
62cc6b9d DM |
2885 | * while L1 is in VMXON mode (in L1's root mode, or running an L2). |
2886 | * We picked the standard core2 setting. | |
2887 | */ | |
2888 | #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) | |
2889 | #define VMXON_CR4_ALWAYSON X86_CR4_VMXE | |
2890 | vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON; | |
62cc6b9d | 2891 | vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON; |
8322ebbb DM |
2892 | |
2893 | /* These MSRs specify bits which the guest must keep fixed off. */ | |
2894 | rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1); | |
2895 | rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1); | |
62cc6b9d DM |
2896 | |
2897 | /* highest index: VMX_PREEMPTION_TIMER_VALUE */ | |
2898 | vmx->nested.nested_vmx_vmcs_enum = 0x2e; | |
b87a51ae NHE |
2899 | } |
2900 | ||
3899152c DM |
2901 | /* |
2902 | * if fixed0[i] == 1: val[i] must be 1 | |
2903 | * if fixed1[i] == 0: val[i] must be 0 | |
2904 | */ | |
2905 | static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1) | |
2906 | { | |
2907 | return ((val & fixed1) | fixed0) == val; | |
b87a51ae NHE |
2908 | } |
2909 | ||
2910 | static inline bool vmx_control_verify(u32 control, u32 low, u32 high) | |
2911 | { | |
3899152c | 2912 | return fixed_bits_valid(control, low, high); |
b87a51ae NHE |
2913 | } |
2914 | ||
2915 | static inline u64 vmx_control_msr(u32 low, u32 high) | |
2916 | { | |
2917 | return low | ((u64)high << 32); | |
2918 | } | |
2919 | ||
62cc6b9d DM |
2920 | static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask) |
2921 | { | |
2922 | superset &= mask; | |
2923 | subset &= mask; | |
2924 | ||
2925 | return (superset | subset) == superset; | |
2926 | } | |
2927 | ||
2928 | static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data) | |
2929 | { | |
2930 | const u64 feature_and_reserved = | |
2931 | /* feature (except bit 48; see below) */ | |
2932 | BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) | | |
2933 | /* reserved */ | |
2934 | BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56); | |
2935 | u64 vmx_basic = vmx->nested.nested_vmx_basic; | |
2936 | ||
2937 | if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved)) | |
2938 | return -EINVAL; | |
2939 | ||
2940 | /* | |
2941 | * KVM does not emulate a version of VMX that constrains physical | |
2942 | * addresses of VMX structures (e.g. VMCS) to 32-bits. | |
2943 | */ | |
2944 | if (data & BIT_ULL(48)) | |
2945 | return -EINVAL; | |
2946 | ||
2947 | if (vmx_basic_vmcs_revision_id(vmx_basic) != | |
2948 | vmx_basic_vmcs_revision_id(data)) | |
2949 | return -EINVAL; | |
2950 | ||
2951 | if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data)) | |
2952 | return -EINVAL; | |
2953 | ||
2954 | vmx->nested.nested_vmx_basic = data; | |
2955 | return 0; | |
2956 | } | |
2957 | ||
2958 | static int | |
2959 | vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
2960 | { | |
2961 | u64 supported; | |
2962 | u32 *lowp, *highp; | |
2963 | ||
2964 | switch (msr_index) { | |
2965 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
2966 | lowp = &vmx->nested.nested_vmx_pinbased_ctls_low; | |
2967 | highp = &vmx->nested.nested_vmx_pinbased_ctls_high; | |
2968 | break; | |
2969 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
2970 | lowp = &vmx->nested.nested_vmx_procbased_ctls_low; | |
2971 | highp = &vmx->nested.nested_vmx_procbased_ctls_high; | |
2972 | break; | |
2973 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
2974 | lowp = &vmx->nested.nested_vmx_exit_ctls_low; | |
2975 | highp = &vmx->nested.nested_vmx_exit_ctls_high; | |
2976 | break; | |
2977 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
2978 | lowp = &vmx->nested.nested_vmx_entry_ctls_low; | |
2979 | highp = &vmx->nested.nested_vmx_entry_ctls_high; | |
2980 | break; | |
2981 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
2982 | lowp = &vmx->nested.nested_vmx_secondary_ctls_low; | |
2983 | highp = &vmx->nested.nested_vmx_secondary_ctls_high; | |
2984 | break; | |
2985 | default: | |
2986 | BUG(); | |
2987 | } | |
2988 | ||
2989 | supported = vmx_control_msr(*lowp, *highp); | |
2990 | ||
2991 | /* Check must-be-1 bits are still 1. */ | |
2992 | if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0))) | |
2993 | return -EINVAL; | |
2994 | ||
2995 | /* Check must-be-0 bits are still 0. */ | |
2996 | if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32))) | |
2997 | return -EINVAL; | |
2998 | ||
2999 | *lowp = data; | |
3000 | *highp = data >> 32; | |
3001 | return 0; | |
3002 | } | |
3003 | ||
3004 | static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data) | |
3005 | { | |
3006 | const u64 feature_and_reserved_bits = | |
3007 | /* feature */ | |
3008 | BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) | | |
3009 | BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) | | |
3010 | /* reserved */ | |
3011 | GENMASK_ULL(13, 9) | BIT_ULL(31); | |
3012 | u64 vmx_misc; | |
3013 | ||
3014 | vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low, | |
3015 | vmx->nested.nested_vmx_misc_high); | |
3016 | ||
3017 | if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits)) | |
3018 | return -EINVAL; | |
3019 | ||
3020 | if ((vmx->nested.nested_vmx_pinbased_ctls_high & | |
3021 | PIN_BASED_VMX_PREEMPTION_TIMER) && | |
3022 | vmx_misc_preemption_timer_rate(data) != | |
3023 | vmx_misc_preemption_timer_rate(vmx_misc)) | |
3024 | return -EINVAL; | |
3025 | ||
3026 | if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc)) | |
3027 | return -EINVAL; | |
3028 | ||
3029 | if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc)) | |
3030 | return -EINVAL; | |
3031 | ||
3032 | if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc)) | |
3033 | return -EINVAL; | |
3034 | ||
3035 | vmx->nested.nested_vmx_misc_low = data; | |
3036 | vmx->nested.nested_vmx_misc_high = data >> 32; | |
3037 | return 0; | |
3038 | } | |
3039 | ||
3040 | static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data) | |
3041 | { | |
3042 | u64 vmx_ept_vpid_cap; | |
3043 | ||
3044 | vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps, | |
3045 | vmx->nested.nested_vmx_vpid_caps); | |
3046 | ||
3047 | /* Every bit is either reserved or a feature bit. */ | |
3048 | if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL)) | |
3049 | return -EINVAL; | |
3050 | ||
3051 | vmx->nested.nested_vmx_ept_caps = data; | |
3052 | vmx->nested.nested_vmx_vpid_caps = data >> 32; | |
3053 | return 0; | |
3054 | } | |
3055 | ||
3056 | static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
3057 | { | |
3058 | u64 *msr; | |
3059 | ||
3060 | switch (msr_index) { | |
3061 | case MSR_IA32_VMX_CR0_FIXED0: | |
3062 | msr = &vmx->nested.nested_vmx_cr0_fixed0; | |
3063 | break; | |
3064 | case MSR_IA32_VMX_CR4_FIXED0: | |
3065 | msr = &vmx->nested.nested_vmx_cr4_fixed0; | |
3066 | break; | |
3067 | default: | |
3068 | BUG(); | |
3069 | } | |
3070 | ||
3071 | /* | |
3072 | * 1 bits (which indicates bits which "must-be-1" during VMX operation) | |
3073 | * must be 1 in the restored value. | |
3074 | */ | |
3075 | if (!is_bitwise_subset(data, *msr, -1ULL)) | |
3076 | return -EINVAL; | |
3077 | ||
3078 | *msr = data; | |
3079 | return 0; | |
3080 | } | |
3081 | ||
3082 | /* | |
3083 | * Called when userspace is restoring VMX MSRs. | |
3084 | * | |
3085 | * Returns 0 on success, non-0 otherwise. | |
3086 | */ | |
3087 | static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
b87a51ae | 3088 | { |
b9c237bb WV |
3089 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3090 | ||
b87a51ae | 3091 | switch (msr_index) { |
b87a51ae | 3092 | case MSR_IA32_VMX_BASIC: |
62cc6b9d DM |
3093 | return vmx_restore_vmx_basic(vmx, data); |
3094 | case MSR_IA32_VMX_PINBASED_CTLS: | |
3095 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
3096 | case MSR_IA32_VMX_EXIT_CTLS: | |
3097 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b87a51ae | 3098 | /* |
62cc6b9d DM |
3099 | * The "non-true" VMX capability MSRs are generated from the |
3100 | * "true" MSRs, so we do not support restoring them directly. | |
3101 | * | |
3102 | * If userspace wants to emulate VMX_BASIC[55]=0, userspace | |
3103 | * should restore the "true" MSRs with the must-be-1 bits | |
3104 | * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND | |
3105 | * DEFAULT SETTINGS". | |
b87a51ae | 3106 | */ |
62cc6b9d DM |
3107 | return -EINVAL; |
3108 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3109 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3110 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3111 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3112 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
3113 | return vmx_restore_control_msr(vmx, msr_index, data); | |
3114 | case MSR_IA32_VMX_MISC: | |
3115 | return vmx_restore_vmx_misc(vmx, data); | |
3116 | case MSR_IA32_VMX_CR0_FIXED0: | |
3117 | case MSR_IA32_VMX_CR4_FIXED0: | |
3118 | return vmx_restore_fixed0_msr(vmx, msr_index, data); | |
3119 | case MSR_IA32_VMX_CR0_FIXED1: | |
3120 | case MSR_IA32_VMX_CR4_FIXED1: | |
3121 | /* | |
3122 | * These MSRs are generated based on the vCPU's CPUID, so we | |
3123 | * do not support restoring them directly. | |
3124 | */ | |
3125 | return -EINVAL; | |
3126 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
3127 | return vmx_restore_vmx_ept_vpid_cap(vmx, data); | |
3128 | case MSR_IA32_VMX_VMCS_ENUM: | |
3129 | vmx->nested.nested_vmx_vmcs_enum = data; | |
3130 | return 0; | |
3131 | default: | |
b87a51ae | 3132 | /* |
62cc6b9d | 3133 | * The rest of the VMX capability MSRs do not support restore. |
b87a51ae | 3134 | */ |
62cc6b9d DM |
3135 | return -EINVAL; |
3136 | } | |
3137 | } | |
3138 | ||
3139 | /* Returns 0 on success, non-0 otherwise. */ | |
3140 | static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
3141 | { | |
3142 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3143 | ||
3144 | switch (msr_index) { | |
3145 | case MSR_IA32_VMX_BASIC: | |
3146 | *pdata = vmx->nested.nested_vmx_basic; | |
b87a51ae NHE |
3147 | break; |
3148 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3149 | case MSR_IA32_VMX_PINBASED_CTLS: | |
b9c237bb WV |
3150 | *pdata = vmx_control_msr( |
3151 | vmx->nested.nested_vmx_pinbased_ctls_low, | |
3152 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
0115f9cb DM |
3153 | if (msr_index == MSR_IA32_VMX_PINBASED_CTLS) |
3154 | *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3155 | break; |
3156 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3157 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
b9c237bb WV |
3158 | *pdata = vmx_control_msr( |
3159 | vmx->nested.nested_vmx_procbased_ctls_low, | |
3160 | vmx->nested.nested_vmx_procbased_ctls_high); | |
0115f9cb DM |
3161 | if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS) |
3162 | *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3163 | break; |
3164 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3165 | case MSR_IA32_VMX_EXIT_CTLS: | |
b9c237bb WV |
3166 | *pdata = vmx_control_msr( |
3167 | vmx->nested.nested_vmx_exit_ctls_low, | |
3168 | vmx->nested.nested_vmx_exit_ctls_high); | |
0115f9cb DM |
3169 | if (msr_index == MSR_IA32_VMX_EXIT_CTLS) |
3170 | *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3171 | break; |
3172 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3173 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b9c237bb WV |
3174 | *pdata = vmx_control_msr( |
3175 | vmx->nested.nested_vmx_entry_ctls_low, | |
3176 | vmx->nested.nested_vmx_entry_ctls_high); | |
0115f9cb DM |
3177 | if (msr_index == MSR_IA32_VMX_ENTRY_CTLS) |
3178 | *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3179 | break; |
3180 | case MSR_IA32_VMX_MISC: | |
b9c237bb WV |
3181 | *pdata = vmx_control_msr( |
3182 | vmx->nested.nested_vmx_misc_low, | |
3183 | vmx->nested.nested_vmx_misc_high); | |
b87a51ae | 3184 | break; |
b87a51ae | 3185 | case MSR_IA32_VMX_CR0_FIXED0: |
62cc6b9d | 3186 | *pdata = vmx->nested.nested_vmx_cr0_fixed0; |
b87a51ae NHE |
3187 | break; |
3188 | case MSR_IA32_VMX_CR0_FIXED1: | |
62cc6b9d | 3189 | *pdata = vmx->nested.nested_vmx_cr0_fixed1; |
b87a51ae NHE |
3190 | break; |
3191 | case MSR_IA32_VMX_CR4_FIXED0: | |
62cc6b9d | 3192 | *pdata = vmx->nested.nested_vmx_cr4_fixed0; |
b87a51ae NHE |
3193 | break; |
3194 | case MSR_IA32_VMX_CR4_FIXED1: | |
62cc6b9d | 3195 | *pdata = vmx->nested.nested_vmx_cr4_fixed1; |
b87a51ae NHE |
3196 | break; |
3197 | case MSR_IA32_VMX_VMCS_ENUM: | |
62cc6b9d | 3198 | *pdata = vmx->nested.nested_vmx_vmcs_enum; |
b87a51ae NHE |
3199 | break; |
3200 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
b9c237bb WV |
3201 | *pdata = vmx_control_msr( |
3202 | vmx->nested.nested_vmx_secondary_ctls_low, | |
3203 | vmx->nested.nested_vmx_secondary_ctls_high); | |
b87a51ae NHE |
3204 | break; |
3205 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
089d7b6e WL |
3206 | *pdata = vmx->nested.nested_vmx_ept_caps | |
3207 | ((u64)vmx->nested.nested_vmx_vpid_caps << 32); | |
b87a51ae | 3208 | break; |
27c42a1b BD |
3209 | case MSR_IA32_VMX_VMFUNC: |
3210 | *pdata = vmx->nested.nested_vmx_vmfunc_controls; | |
3211 | break; | |
b87a51ae | 3212 | default: |
b87a51ae | 3213 | return 1; |
b3897a49 NHE |
3214 | } |
3215 | ||
b87a51ae NHE |
3216 | return 0; |
3217 | } | |
3218 | ||
37e4c997 HZ |
3219 | static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, |
3220 | uint64_t val) | |
3221 | { | |
3222 | uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; | |
3223 | ||
3224 | return !(val & ~valid_bits); | |
3225 | } | |
3226 | ||
6aa8b732 AK |
3227 | /* |
3228 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
3229 | * Returns 0 on success, non-0 otherwise. | |
3230 | * Assumes vcpu_load() was already called. | |
3231 | */ | |
609e36d3 | 3232 | static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3233 | { |
26bb0981 | 3234 | struct shared_msr_entry *msr; |
6aa8b732 | 3235 | |
609e36d3 | 3236 | switch (msr_info->index) { |
05b3e0c2 | 3237 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3238 | case MSR_FS_BASE: |
609e36d3 | 3239 | msr_info->data = vmcs_readl(GUEST_FS_BASE); |
6aa8b732 AK |
3240 | break; |
3241 | case MSR_GS_BASE: | |
609e36d3 | 3242 | msr_info->data = vmcs_readl(GUEST_GS_BASE); |
6aa8b732 | 3243 | break; |
44ea2b17 AK |
3244 | case MSR_KERNEL_GS_BASE: |
3245 | vmx_load_host_state(to_vmx(vcpu)); | |
609e36d3 | 3246 | msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base; |
44ea2b17 | 3247 | break; |
26bb0981 | 3248 | #endif |
6aa8b732 | 3249 | case MSR_EFER: |
609e36d3 | 3250 | return kvm_get_msr_common(vcpu, msr_info); |
af24a4e4 | 3251 | case MSR_IA32_TSC: |
be7b263e | 3252 | msr_info->data = guest_read_tsc(vcpu); |
6aa8b732 AK |
3253 | break; |
3254 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 3255 | msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); |
6aa8b732 AK |
3256 | break; |
3257 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3258 | msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
3259 | break; |
3260 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3261 | msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 3262 | break; |
0dd376e7 | 3263 | case MSR_IA32_BNDCFGS: |
691bd434 | 3264 | if (!kvm_mpx_supported() || |
d6321d49 RK |
3265 | (!msr_info->host_initiated && |
3266 | !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) | |
93c4adc7 | 3267 | return 1; |
609e36d3 | 3268 | msr_info->data = vmcs_read64(GUEST_BNDCFGS); |
0dd376e7 | 3269 | break; |
c45dcc71 AR |
3270 | case MSR_IA32_MCG_EXT_CTL: |
3271 | if (!msr_info->host_initiated && | |
3272 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3273 | FEATURE_CONTROL_LMCE)) | |
cae50139 | 3274 | return 1; |
c45dcc71 AR |
3275 | msr_info->data = vcpu->arch.mcg_ext_ctl; |
3276 | break; | |
cae50139 | 3277 | case MSR_IA32_FEATURE_CONTROL: |
3b84080b | 3278 | msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control; |
cae50139 JK |
3279 | break; |
3280 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
3281 | if (!nested_vmx_allowed(vcpu)) | |
3282 | return 1; | |
609e36d3 | 3283 | return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data); |
20300099 WL |
3284 | case MSR_IA32_XSS: |
3285 | if (!vmx_xsaves_supported()) | |
3286 | return 1; | |
609e36d3 | 3287 | msr_info->data = vcpu->arch.ia32_xss; |
20300099 | 3288 | break; |
4e47c7a6 | 3289 | case MSR_TSC_AUX: |
d6321d49 RK |
3290 | if (!msr_info->host_initiated && |
3291 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) | |
4e47c7a6 SY |
3292 | return 1; |
3293 | /* Otherwise falls through */ | |
6aa8b732 | 3294 | default: |
609e36d3 | 3295 | msr = find_msr_entry(to_vmx(vcpu), msr_info->index); |
3bab1f5d | 3296 | if (msr) { |
609e36d3 | 3297 | msr_info->data = msr->data; |
3bab1f5d | 3298 | break; |
6aa8b732 | 3299 | } |
609e36d3 | 3300 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3301 | } |
3302 | ||
6aa8b732 AK |
3303 | return 0; |
3304 | } | |
3305 | ||
cae50139 JK |
3306 | static void vmx_leave_nested(struct kvm_vcpu *vcpu); |
3307 | ||
6aa8b732 AK |
3308 | /* |
3309 | * Writes msr value into into the appropriate "register". | |
3310 | * Returns 0 on success, non-0 otherwise. | |
3311 | * Assumes vcpu_load() was already called. | |
3312 | */ | |
8fe8ab46 | 3313 | static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3314 | { |
a2fa3e9f | 3315 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 3316 | struct shared_msr_entry *msr; |
2cc51560 | 3317 | int ret = 0; |
8fe8ab46 WA |
3318 | u32 msr_index = msr_info->index; |
3319 | u64 data = msr_info->data; | |
2cc51560 | 3320 | |
6aa8b732 | 3321 | switch (msr_index) { |
3bab1f5d | 3322 | case MSR_EFER: |
8fe8ab46 | 3323 | ret = kvm_set_msr_common(vcpu, msr_info); |
2cc51560 | 3324 | break; |
16175a79 | 3325 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3326 | case MSR_FS_BASE: |
2fb92db1 | 3327 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3328 | vmcs_writel(GUEST_FS_BASE, data); |
3329 | break; | |
3330 | case MSR_GS_BASE: | |
2fb92db1 | 3331 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3332 | vmcs_writel(GUEST_GS_BASE, data); |
3333 | break; | |
44ea2b17 AK |
3334 | case MSR_KERNEL_GS_BASE: |
3335 | vmx_load_host_state(vmx); | |
3336 | vmx->msr_guest_kernel_gs_base = data; | |
3337 | break; | |
6aa8b732 AK |
3338 | #endif |
3339 | case MSR_IA32_SYSENTER_CS: | |
3340 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
3341 | break; | |
3342 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 3343 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
3344 | break; |
3345 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 3346 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 3347 | break; |
0dd376e7 | 3348 | case MSR_IA32_BNDCFGS: |
691bd434 | 3349 | if (!kvm_mpx_supported() || |
d6321d49 RK |
3350 | (!msr_info->host_initiated && |
3351 | !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) | |
93c4adc7 | 3352 | return 1; |
fd8cb433 | 3353 | if (is_noncanonical_address(data & PAGE_MASK, vcpu) || |
4531662d | 3354 | (data & MSR_IA32_BNDCFGS_RSVD)) |
93c4adc7 | 3355 | return 1; |
0dd376e7 LJ |
3356 | vmcs_write64(GUEST_BNDCFGS, data); |
3357 | break; | |
af24a4e4 | 3358 | case MSR_IA32_TSC: |
8fe8ab46 | 3359 | kvm_write_tsc(vcpu, msr_info); |
6aa8b732 | 3360 | break; |
468d472f SY |
3361 | case MSR_IA32_CR_PAT: |
3362 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
4566654b NA |
3363 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) |
3364 | return 1; | |
468d472f SY |
3365 | vmcs_write64(GUEST_IA32_PAT, data); |
3366 | vcpu->arch.pat = data; | |
3367 | break; | |
3368 | } | |
8fe8ab46 | 3369 | ret = kvm_set_msr_common(vcpu, msr_info); |
4e47c7a6 | 3370 | break; |
ba904635 WA |
3371 | case MSR_IA32_TSC_ADJUST: |
3372 | ret = kvm_set_msr_common(vcpu, msr_info); | |
4e47c7a6 | 3373 | break; |
c45dcc71 AR |
3374 | case MSR_IA32_MCG_EXT_CTL: |
3375 | if ((!msr_info->host_initiated && | |
3376 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3377 | FEATURE_CONTROL_LMCE)) || | |
3378 | (data & ~MCG_EXT_CTL_LMCE_EN)) | |
3379 | return 1; | |
3380 | vcpu->arch.mcg_ext_ctl = data; | |
3381 | break; | |
cae50139 | 3382 | case MSR_IA32_FEATURE_CONTROL: |
37e4c997 | 3383 | if (!vmx_feature_control_msr_valid(vcpu, data) || |
3b84080b | 3384 | (to_vmx(vcpu)->msr_ia32_feature_control & |
cae50139 JK |
3385 | FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) |
3386 | return 1; | |
3b84080b | 3387 | vmx->msr_ia32_feature_control = data; |
cae50139 JK |
3388 | if (msr_info->host_initiated && data == 0) |
3389 | vmx_leave_nested(vcpu); | |
3390 | break; | |
3391 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
62cc6b9d DM |
3392 | if (!msr_info->host_initiated) |
3393 | return 1; /* they are read-only */ | |
3394 | if (!nested_vmx_allowed(vcpu)) | |
3395 | return 1; | |
3396 | return vmx_set_vmx_msr(vcpu, msr_index, data); | |
20300099 WL |
3397 | case MSR_IA32_XSS: |
3398 | if (!vmx_xsaves_supported()) | |
3399 | return 1; | |
3400 | /* | |
3401 | * The only supported bit as of Skylake is bit 8, but | |
3402 | * it is not supported on KVM. | |
3403 | */ | |
3404 | if (data != 0) | |
3405 | return 1; | |
3406 | vcpu->arch.ia32_xss = data; | |
3407 | if (vcpu->arch.ia32_xss != host_xss) | |
3408 | add_atomic_switch_msr(vmx, MSR_IA32_XSS, | |
3409 | vcpu->arch.ia32_xss, host_xss); | |
3410 | else | |
3411 | clear_atomic_switch_msr(vmx, MSR_IA32_XSS); | |
3412 | break; | |
4e47c7a6 | 3413 | case MSR_TSC_AUX: |
d6321d49 RK |
3414 | if (!msr_info->host_initiated && |
3415 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) | |
4e47c7a6 SY |
3416 | return 1; |
3417 | /* Check reserved bit, higher 32 bits should be zero */ | |
3418 | if ((data >> 32) != 0) | |
3419 | return 1; | |
3420 | /* Otherwise falls through */ | |
6aa8b732 | 3421 | default: |
8b9cf98c | 3422 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 3423 | if (msr) { |
8b3c3104 | 3424 | u64 old_msr_data = msr->data; |
3bab1f5d | 3425 | msr->data = data; |
2225fd56 AK |
3426 | if (msr - vmx->guest_msrs < vmx->save_nmsrs) { |
3427 | preempt_disable(); | |
8b3c3104 AH |
3428 | ret = kvm_set_shared_msr(msr->index, msr->data, |
3429 | msr->mask); | |
2225fd56 | 3430 | preempt_enable(); |
8b3c3104 AH |
3431 | if (ret) |
3432 | msr->data = old_msr_data; | |
2225fd56 | 3433 | } |
3bab1f5d | 3434 | break; |
6aa8b732 | 3435 | } |
8fe8ab46 | 3436 | ret = kvm_set_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3437 | } |
3438 | ||
2cc51560 | 3439 | return ret; |
6aa8b732 AK |
3440 | } |
3441 | ||
5fdbf976 | 3442 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 3443 | { |
5fdbf976 MT |
3444 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
3445 | switch (reg) { | |
3446 | case VCPU_REGS_RSP: | |
3447 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
3448 | break; | |
3449 | case VCPU_REGS_RIP: | |
3450 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
3451 | break; | |
6de4f3ad AK |
3452 | case VCPU_EXREG_PDPTR: |
3453 | if (enable_ept) | |
3454 | ept_save_pdptrs(vcpu); | |
3455 | break; | |
5fdbf976 MT |
3456 | default: |
3457 | break; | |
3458 | } | |
6aa8b732 AK |
3459 | } |
3460 | ||
6aa8b732 AK |
3461 | static __init int cpu_has_kvm_support(void) |
3462 | { | |
6210e37b | 3463 | return cpu_has_vmx(); |
6aa8b732 AK |
3464 | } |
3465 | ||
3466 | static __init int vmx_disabled_by_bios(void) | |
3467 | { | |
3468 | u64 msr; | |
3469 | ||
3470 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 3471 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 3472 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
3473 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
3474 | && tboot_enabled()) | |
3475 | return 1; | |
23f3e991 | 3476 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 3477 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 3478 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
3479 | && !tboot_enabled()) { |
3480 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 3481 | "activate TXT before enabling KVM\n"); |
cafd6659 | 3482 | return 1; |
f9335afe | 3483 | } |
23f3e991 JC |
3484 | /* launched w/o TXT and VMX disabled */ |
3485 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
3486 | && !tboot_enabled()) | |
3487 | return 1; | |
cafd6659 SW |
3488 | } |
3489 | ||
3490 | return 0; | |
6aa8b732 AK |
3491 | } |
3492 | ||
7725b894 DX |
3493 | static void kvm_cpu_vmxon(u64 addr) |
3494 | { | |
fe0e80be | 3495 | cr4_set_bits(X86_CR4_VMXE); |
1c5ac21a AS |
3496 | intel_pt_handle_vmx(1); |
3497 | ||
7725b894 DX |
3498 | asm volatile (ASM_VMX_VMXON_RAX |
3499 | : : "a"(&addr), "m"(addr) | |
3500 | : "memory", "cc"); | |
3501 | } | |
3502 | ||
13a34e06 | 3503 | static int hardware_enable(void) |
6aa8b732 AK |
3504 | { |
3505 | int cpu = raw_smp_processor_id(); | |
3506 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 3507 | u64 old, test_bits; |
6aa8b732 | 3508 | |
1e02ce4c | 3509 | if (cr4_read_shadow() & X86_CR4_VMXE) |
10474ae8 AG |
3510 | return -EBUSY; |
3511 | ||
d462b819 | 3512 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
bf9f6ac8 FW |
3513 | INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); |
3514 | spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
8f536b76 ZY |
3515 | |
3516 | /* | |
3517 | * Now we can enable the vmclear operation in kdump | |
3518 | * since the loaded_vmcss_on_cpu list on this cpu | |
3519 | * has been initialized. | |
3520 | * | |
3521 | * Though the cpu is not in VMX operation now, there | |
3522 | * is no problem to enable the vmclear operation | |
3523 | * for the loaded_vmcss_on_cpu list is empty! | |
3524 | */ | |
3525 | crash_enable_local_vmclear(cpu); | |
3526 | ||
6aa8b732 | 3527 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
3528 | |
3529 | test_bits = FEATURE_CONTROL_LOCKED; | |
3530 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
3531 | if (tboot_enabled()) | |
3532 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
3533 | ||
3534 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 3535 | /* enable and lock */ |
cafd6659 SW |
3536 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
3537 | } | |
fe0e80be | 3538 | kvm_cpu_vmxon(phys_addr); |
fdf288bf DH |
3539 | if (enable_ept) |
3540 | ept_sync_global(); | |
10474ae8 AG |
3541 | |
3542 | return 0; | |
6aa8b732 AK |
3543 | } |
3544 | ||
d462b819 | 3545 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
3546 | { |
3547 | int cpu = raw_smp_processor_id(); | |
d462b819 | 3548 | struct loaded_vmcs *v, *n; |
543e4243 | 3549 | |
d462b819 NHE |
3550 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
3551 | loaded_vmcss_on_cpu_link) | |
3552 | __loaded_vmcs_clear(v); | |
543e4243 AK |
3553 | } |
3554 | ||
710ff4a8 EH |
3555 | |
3556 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
3557 | * tricks. | |
3558 | */ | |
3559 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 3560 | { |
4ecac3fd | 3561 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
1c5ac21a AS |
3562 | |
3563 | intel_pt_handle_vmx(0); | |
fe0e80be | 3564 | cr4_clear_bits(X86_CR4_VMXE); |
6aa8b732 AK |
3565 | } |
3566 | ||
13a34e06 | 3567 | static void hardware_disable(void) |
710ff4a8 | 3568 | { |
fe0e80be DH |
3569 | vmclear_local_loaded_vmcss(); |
3570 | kvm_cpu_vmxoff(); | |
710ff4a8 EH |
3571 | } |
3572 | ||
1c3d14fe | 3573 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 3574 | u32 msr, u32 *result) |
1c3d14fe YS |
3575 | { |
3576 | u32 vmx_msr_low, vmx_msr_high; | |
3577 | u32 ctl = ctl_min | ctl_opt; | |
3578 | ||
3579 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3580 | ||
3581 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
3582 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
3583 | ||
3584 | /* Ensure minimum (required) set of control bits are supported. */ | |
3585 | if (ctl_min & ~ctl) | |
002c7f7c | 3586 | return -EIO; |
1c3d14fe YS |
3587 | |
3588 | *result = ctl; | |
3589 | return 0; | |
3590 | } | |
3591 | ||
110312c8 AK |
3592 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
3593 | { | |
3594 | u32 vmx_msr_low, vmx_msr_high; | |
3595 | ||
3596 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3597 | return vmx_msr_high & ctl; | |
3598 | } | |
3599 | ||
002c7f7c | 3600 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
3601 | { |
3602 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 3603 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
3604 | u32 _pin_based_exec_control = 0; |
3605 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 3606 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
3607 | u32 _vmexit_control = 0; |
3608 | u32 _vmentry_control = 0; | |
3609 | ||
10166744 | 3610 | min = CPU_BASED_HLT_EXITING | |
1c3d14fe YS |
3611 | #ifdef CONFIG_X86_64 |
3612 | CPU_BASED_CR8_LOAD_EXITING | | |
3613 | CPU_BASED_CR8_STORE_EXITING | | |
3614 | #endif | |
d56f546d SY |
3615 | CPU_BASED_CR3_LOAD_EXITING | |
3616 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
3617 | CPU_BASED_USE_IO_BITMAPS | |
3618 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 3619 | CPU_BASED_USE_TSC_OFFSETING | |
fee84b07 AK |
3620 | CPU_BASED_INVLPG_EXITING | |
3621 | CPU_BASED_RDPMC_EXITING; | |
443381a8 | 3622 | |
668fffa3 MT |
3623 | if (!kvm_mwait_in_guest()) |
3624 | min |= CPU_BASED_MWAIT_EXITING | | |
3625 | CPU_BASED_MONITOR_EXITING; | |
3626 | ||
f78e0e2e | 3627 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 3628 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 3629 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
3630 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
3631 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 3632 | return -EIO; |
6e5d865c YS |
3633 | #ifdef CONFIG_X86_64 |
3634 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3635 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
3636 | ~CPU_BASED_CR8_STORE_EXITING; | |
3637 | #endif | |
f78e0e2e | 3638 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
3639 | min2 = 0; |
3640 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
8d14695f | 3641 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2384d2b3 | 3642 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 3643 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 3644 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 3645 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 | 3646 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
ad756a16 | 3647 | SECONDARY_EXEC_RDTSCP | |
83d4c286 | 3648 | SECONDARY_EXEC_ENABLE_INVPCID | |
c7c9c56c | 3649 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
abc4fc58 | 3650 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
20300099 | 3651 | SECONDARY_EXEC_SHADOW_VMCS | |
843e4330 | 3652 | SECONDARY_EXEC_XSAVES | |
736fdf72 DH |
3653 | SECONDARY_EXEC_RDSEED_EXITING | |
3654 | SECONDARY_EXEC_RDRAND_EXITING | | |
8b3e34e4 | 3655 | SECONDARY_EXEC_ENABLE_PML | |
2a499e49 BD |
3656 | SECONDARY_EXEC_TSC_SCALING | |
3657 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
d56f546d SY |
3658 | if (adjust_vmx_controls(min2, opt2, |
3659 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
3660 | &_cpu_based_2nd_exec_control) < 0) |
3661 | return -EIO; | |
3662 | } | |
3663 | #ifndef CONFIG_X86_64 | |
3664 | if (!(_cpu_based_2nd_exec_control & | |
3665 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
3666 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
3667 | #endif | |
83d4c286 YZ |
3668 | |
3669 | if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3670 | _cpu_based_2nd_exec_control &= ~( | |
8d14695f | 3671 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
c7c9c56c YZ |
3672 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
3673 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
83d4c286 | 3674 | |
d56f546d | 3675 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
3676 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
3677 | enabled */ | |
5fff7d27 GN |
3678 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
3679 | CPU_BASED_CR3_STORE_EXITING | | |
3680 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
3681 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, |
3682 | vmx_capability.ept, vmx_capability.vpid); | |
3683 | } | |
1c3d14fe | 3684 | |
91fa0f8e | 3685 | min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; |
1c3d14fe YS |
3686 | #ifdef CONFIG_X86_64 |
3687 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
3688 | #endif | |
a547c6db | 3689 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT | |
91fa0f8e | 3690 | VM_EXIT_CLEAR_BNDCFGS; |
1c3d14fe YS |
3691 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
3692 | &_vmexit_control) < 0) | |
002c7f7c | 3693 | return -EIO; |
1c3d14fe | 3694 | |
2c82878b PB |
3695 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING | |
3696 | PIN_BASED_VIRTUAL_NMIS; | |
3697 | opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
3698 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
3699 | &_pin_based_exec_control) < 0) | |
3700 | return -EIO; | |
3701 | ||
1c17c3e6 PB |
3702 | if (cpu_has_broken_vmx_preemption_timer()) |
3703 | _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be | 3704 | if (!(_cpu_based_2nd_exec_control & |
91fa0f8e | 3705 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) |
01e439be YZ |
3706 | _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; |
3707 | ||
c845f9c6 | 3708 | min = VM_ENTRY_LOAD_DEBUG_CONTROLS; |
da8999d3 | 3709 | opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS; |
1c3d14fe YS |
3710 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
3711 | &_vmentry_control) < 0) | |
002c7f7c | 3712 | return -EIO; |
6aa8b732 | 3713 | |
c68876fd | 3714 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
3715 | |
3716 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
3717 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 3718 | return -EIO; |
1c3d14fe YS |
3719 | |
3720 | #ifdef CONFIG_X86_64 | |
3721 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
3722 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 3723 | return -EIO; |
1c3d14fe YS |
3724 | #endif |
3725 | ||
3726 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
3727 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 3728 | return -EIO; |
1c3d14fe | 3729 | |
002c7f7c | 3730 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
16cb0255 | 3731 | vmcs_conf->order = get_order(vmcs_conf->size); |
9ac7e3e8 | 3732 | vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; |
002c7f7c | 3733 | vmcs_conf->revision_id = vmx_msr_low; |
1c3d14fe | 3734 | |
002c7f7c YS |
3735 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
3736 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 3737 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
3738 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
3739 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 3740 | |
110312c8 AK |
3741 | cpu_has_load_ia32_efer = |
3742 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3743 | VM_ENTRY_LOAD_IA32_EFER) | |
3744 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3745 | VM_EXIT_LOAD_IA32_EFER); | |
3746 | ||
8bf00a52 GN |
3747 | cpu_has_load_perf_global_ctrl = |
3748 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3749 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
3750 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3751 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
3752 | ||
3753 | /* | |
3754 | * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL | |
bb3541f1 | 3755 | * but due to errata below it can't be used. Workaround is to use |
8bf00a52 GN |
3756 | * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. |
3757 | * | |
3758 | * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] | |
3759 | * | |
3760 | * AAK155 (model 26) | |
3761 | * AAP115 (model 30) | |
3762 | * AAT100 (model 37) | |
3763 | * BC86,AAY89,BD102 (model 44) | |
3764 | * BA97 (model 46) | |
3765 | * | |
3766 | */ | |
3767 | if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) { | |
3768 | switch (boot_cpu_data.x86_model) { | |
3769 | case 26: | |
3770 | case 30: | |
3771 | case 37: | |
3772 | case 44: | |
3773 | case 46: | |
3774 | cpu_has_load_perf_global_ctrl = false; | |
3775 | printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " | |
3776 | "does not work properly. Using workaround\n"); | |
3777 | break; | |
3778 | default: | |
3779 | break; | |
3780 | } | |
3781 | } | |
3782 | ||
782511b0 | 3783 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
20300099 WL |
3784 | rdmsrl(MSR_IA32_XSS, host_xss); |
3785 | ||
1c3d14fe | 3786 | return 0; |
c68876fd | 3787 | } |
6aa8b732 AK |
3788 | |
3789 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
3790 | { | |
3791 | int node = cpu_to_node(cpu); | |
3792 | struct page *pages; | |
3793 | struct vmcs *vmcs; | |
3794 | ||
96db800f | 3795 | pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
3796 | if (!pages) |
3797 | return NULL; | |
3798 | vmcs = page_address(pages); | |
1c3d14fe YS |
3799 | memset(vmcs, 0, vmcs_config.size); |
3800 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
3801 | return vmcs; |
3802 | } | |
3803 | ||
3804 | static struct vmcs *alloc_vmcs(void) | |
3805 | { | |
d3b2c338 | 3806 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
3807 | } |
3808 | ||
3809 | static void free_vmcs(struct vmcs *vmcs) | |
3810 | { | |
1c3d14fe | 3811 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
3812 | } |
3813 | ||
d462b819 NHE |
3814 | /* |
3815 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
3816 | */ | |
3817 | static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
3818 | { | |
3819 | if (!loaded_vmcs->vmcs) | |
3820 | return; | |
3821 | loaded_vmcs_clear(loaded_vmcs); | |
3822 | free_vmcs(loaded_vmcs->vmcs); | |
3823 | loaded_vmcs->vmcs = NULL; | |
355f4fb1 | 3824 | WARN_ON(loaded_vmcs->shadow_vmcs != NULL); |
d462b819 NHE |
3825 | } |
3826 | ||
39959588 | 3827 | static void free_kvm_area(void) |
6aa8b732 AK |
3828 | { |
3829 | int cpu; | |
3830 | ||
3230bb47 | 3831 | for_each_possible_cpu(cpu) { |
6aa8b732 | 3832 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
3833 | per_cpu(vmxarea, cpu) = NULL; |
3834 | } | |
6aa8b732 AK |
3835 | } |
3836 | ||
85fd514e JM |
3837 | enum vmcs_field_type { |
3838 | VMCS_FIELD_TYPE_U16 = 0, | |
3839 | VMCS_FIELD_TYPE_U64 = 1, | |
3840 | VMCS_FIELD_TYPE_U32 = 2, | |
3841 | VMCS_FIELD_TYPE_NATURAL_WIDTH = 3 | |
3842 | }; | |
3843 | ||
3844 | static inline int vmcs_field_type(unsigned long field) | |
3845 | { | |
3846 | if (0x1 & field) /* the *_HIGH fields are all 32 bit */ | |
3847 | return VMCS_FIELD_TYPE_U32; | |
3848 | return (field >> 13) & 0x3 ; | |
3849 | } | |
3850 | ||
3851 | static inline int vmcs_field_readonly(unsigned long field) | |
3852 | { | |
3853 | return (((field >> 10) & 0x3) == 1); | |
3854 | } | |
3855 | ||
fe2b201b BD |
3856 | static void init_vmcs_shadow_fields(void) |
3857 | { | |
3858 | int i, j; | |
3859 | ||
3860 | /* No checks for read only fields yet */ | |
3861 | ||
3862 | for (i = j = 0; i < max_shadow_read_write_fields; i++) { | |
3863 | switch (shadow_read_write_fields[i]) { | |
3864 | case GUEST_BNDCFGS: | |
a87036ad | 3865 | if (!kvm_mpx_supported()) |
fe2b201b BD |
3866 | continue; |
3867 | break; | |
3868 | default: | |
3869 | break; | |
3870 | } | |
3871 | ||
3872 | if (j < i) | |
3873 | shadow_read_write_fields[j] = | |
3874 | shadow_read_write_fields[i]; | |
3875 | j++; | |
3876 | } | |
3877 | max_shadow_read_write_fields = j; | |
3878 | ||
3879 | /* shadowed fields guest access without vmexit */ | |
3880 | for (i = 0; i < max_shadow_read_write_fields; i++) { | |
85fd514e JM |
3881 | unsigned long field = shadow_read_write_fields[i]; |
3882 | ||
3883 | clear_bit(field, vmx_vmwrite_bitmap); | |
3884 | clear_bit(field, vmx_vmread_bitmap); | |
3885 | if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) { | |
3886 | clear_bit(field + 1, vmx_vmwrite_bitmap); | |
3887 | clear_bit(field + 1, vmx_vmread_bitmap); | |
3888 | } | |
3889 | } | |
3890 | for (i = 0; i < max_shadow_read_only_fields; i++) { | |
3891 | unsigned long field = shadow_read_only_fields[i]; | |
3892 | ||
3893 | clear_bit(field, vmx_vmread_bitmap); | |
3894 | if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) | |
3895 | clear_bit(field + 1, vmx_vmread_bitmap); | |
fe2b201b | 3896 | } |
fe2b201b BD |
3897 | } |
3898 | ||
6aa8b732 AK |
3899 | static __init int alloc_kvm_area(void) |
3900 | { | |
3901 | int cpu; | |
3902 | ||
3230bb47 | 3903 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
3904 | struct vmcs *vmcs; |
3905 | ||
3906 | vmcs = alloc_vmcs_cpu(cpu); | |
3907 | if (!vmcs) { | |
3908 | free_kvm_area(); | |
3909 | return -ENOMEM; | |
3910 | } | |
3911 | ||
3912 | per_cpu(vmxarea, cpu) = vmcs; | |
3913 | } | |
3914 | return 0; | |
3915 | } | |
3916 | ||
91b0aa2c | 3917 | static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, |
d99e4152 | 3918 | struct kvm_segment *save) |
6aa8b732 | 3919 | { |
d99e4152 GN |
3920 | if (!emulate_invalid_guest_state) { |
3921 | /* | |
3922 | * CS and SS RPL should be equal during guest entry according | |
3923 | * to VMX spec, but in reality it is not always so. Since vcpu | |
3924 | * is in the middle of the transition from real mode to | |
3925 | * protected mode it is safe to assume that RPL 0 is a good | |
3926 | * default value. | |
3927 | */ | |
3928 | if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) | |
b32a9918 NA |
3929 | save->selector &= ~SEGMENT_RPL_MASK; |
3930 | save->dpl = save->selector & SEGMENT_RPL_MASK; | |
d99e4152 | 3931 | save->s = 1; |
6aa8b732 | 3932 | } |
d99e4152 | 3933 | vmx_set_segment(vcpu, save, seg); |
6aa8b732 AK |
3934 | } |
3935 | ||
3936 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
3937 | { | |
3938 | unsigned long flags; | |
a89a8fb9 | 3939 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3940 | |
d99e4152 GN |
3941 | /* |
3942 | * Update real mode segment cache. It may be not up-to-date if sement | |
3943 | * register was written while vcpu was in a guest mode. | |
3944 | */ | |
3945 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3946 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3947 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3948 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
3949 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); | |
3950 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
3951 | ||
7ffd92c5 | 3952 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 3953 | |
2fb92db1 AK |
3954 | vmx_segment_cache_clear(vmx); |
3955 | ||
f5f7b2fe | 3956 | vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
6aa8b732 AK |
3957 | |
3958 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
3959 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
3960 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
3961 | vmcs_writel(GUEST_RFLAGS, flags); |
3962 | ||
66aee91a RR |
3963 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
3964 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
3965 | |
3966 | update_exception_bitmap(vcpu); | |
3967 | ||
91b0aa2c GN |
3968 | fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); |
3969 | fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); | |
3970 | fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
3971 | fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
3972 | fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
3973 | fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
6aa8b732 AK |
3974 | } |
3975 | ||
f5f7b2fe | 3976 | static void fix_rmode_seg(int seg, struct kvm_segment *save) |
6aa8b732 | 3977 | { |
772e0318 | 3978 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
d99e4152 GN |
3979 | struct kvm_segment var = *save; |
3980 | ||
3981 | var.dpl = 0x3; | |
3982 | if (seg == VCPU_SREG_CS) | |
3983 | var.type = 0x3; | |
3984 | ||
3985 | if (!emulate_invalid_guest_state) { | |
3986 | var.selector = var.base >> 4; | |
3987 | var.base = var.base & 0xffff0; | |
3988 | var.limit = 0xffff; | |
3989 | var.g = 0; | |
3990 | var.db = 0; | |
3991 | var.present = 1; | |
3992 | var.s = 1; | |
3993 | var.l = 0; | |
3994 | var.unusable = 0; | |
3995 | var.type = 0x3; | |
3996 | var.avl = 0; | |
3997 | if (save->base & 0xf) | |
3998 | printk_once(KERN_WARNING "kvm: segment base is not " | |
3999 | "paragraph aligned when entering " | |
4000 | "protected mode (seg=%d)", seg); | |
4001 | } | |
6aa8b732 | 4002 | |
d99e4152 | 4003 | vmcs_write16(sf->selector, var.selector); |
96794e4e | 4004 | vmcs_writel(sf->base, var.base); |
d99e4152 GN |
4005 | vmcs_write32(sf->limit, var.limit); |
4006 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); | |
6aa8b732 AK |
4007 | } |
4008 | ||
4009 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
4010 | { | |
4011 | unsigned long flags; | |
a89a8fb9 | 4012 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 4013 | |
f5f7b2fe AK |
4014 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
4015 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
4016 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
4017 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
4018 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
c6ad1153 GN |
4019 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); |
4020 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
f5f7b2fe | 4021 | |
7ffd92c5 | 4022 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 4023 | |
776e58ea GN |
4024 | /* |
4025 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
4918c6ca | 4026 | * vcpu. Warn the user that an update is overdue. |
776e58ea | 4027 | */ |
4918c6ca | 4028 | if (!vcpu->kvm->arch.tss_addr) |
776e58ea GN |
4029 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " |
4030 | "called before entering vcpu\n"); | |
776e58ea | 4031 | |
2fb92db1 AK |
4032 | vmx_segment_cache_clear(vmx); |
4033 | ||
4918c6ca | 4034 | vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr); |
6aa8b732 | 4035 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
6aa8b732 AK |
4036 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
4037 | ||
4038 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 4039 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 4040 | |
053de044 | 4041 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
4042 | |
4043 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 4044 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
4045 | update_exception_bitmap(vcpu); |
4046 | ||
d99e4152 GN |
4047 | fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); |
4048 | fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); | |
4049 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
4050 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
4051 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
4052 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
b246dd5d | 4053 | |
8668a3c4 | 4054 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
4055 | } |
4056 | ||
401d10de AS |
4057 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
4058 | { | |
4059 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
4060 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
4061 | ||
4062 | if (!msr) | |
4063 | return; | |
401d10de | 4064 | |
44ea2b17 AK |
4065 | /* |
4066 | * Force kernel_gs_base reloading before EFER changes, as control | |
4067 | * of this msr depends on is_long_mode(). | |
4068 | */ | |
4069 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 4070 | vcpu->arch.efer = efer; |
401d10de | 4071 | if (efer & EFER_LMA) { |
2961e876 | 4072 | vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
4073 | msr->data = efer; |
4074 | } else { | |
2961e876 | 4075 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
4076 | |
4077 | msr->data = efer & ~EFER_LME; | |
4078 | } | |
4079 | setup_msrs(vmx); | |
4080 | } | |
4081 | ||
05b3e0c2 | 4082 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
4083 | |
4084 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
4085 | { | |
4086 | u32 guest_tr_ar; | |
4087 | ||
2fb92db1 AK |
4088 | vmx_segment_cache_clear(to_vmx(vcpu)); |
4089 | ||
6aa8b732 | 4090 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
4d283ec9 | 4091 | if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { |
bd80158a JK |
4092 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
4093 | __func__); | |
6aa8b732 | 4094 | vmcs_write32(GUEST_TR_AR_BYTES, |
4d283ec9 AL |
4095 | (guest_tr_ar & ~VMX_AR_TYPE_MASK) |
4096 | | VMX_AR_TYPE_BUSY_64_TSS); | |
6aa8b732 | 4097 | } |
da38f438 | 4098 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
4099 | } |
4100 | ||
4101 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
4102 | { | |
2961e876 | 4103 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
da38f438 | 4104 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
4105 | } |
4106 | ||
4107 | #endif | |
4108 | ||
dd5f5341 | 4109 | static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid) |
2384d2b3 | 4110 | { |
dd180b3e XG |
4111 | if (enable_ept) { |
4112 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
4113 | return; | |
995f00a6 | 4114 | ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa)); |
f0b98c02 JM |
4115 | } else { |
4116 | vpid_sync_context(vpid); | |
dd180b3e | 4117 | } |
2384d2b3 SY |
4118 | } |
4119 | ||
dd5f5341 WL |
4120 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
4121 | { | |
4122 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid); | |
4123 | } | |
4124 | ||
fb6c8198 JM |
4125 | static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu) |
4126 | { | |
4127 | if (enable_ept) | |
4128 | vmx_flush_tlb(vcpu); | |
4129 | } | |
4130 | ||
e8467fda AK |
4131 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
4132 | { | |
4133 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
4134 | ||
4135 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
4136 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
4137 | } | |
4138 | ||
aff48baa AK |
4139 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
4140 | { | |
4141 | if (enable_ept && is_paging(vcpu)) | |
4142 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
4143 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
4144 | } | |
4145 | ||
25c4c276 | 4146 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 4147 | { |
fc78f519 AK |
4148 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
4149 | ||
4150 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
4151 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
4152 | } |
4153 | ||
1439442c SY |
4154 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
4155 | { | |
d0d538b9 GN |
4156 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4157 | ||
6de4f3ad AK |
4158 | if (!test_bit(VCPU_EXREG_PDPTR, |
4159 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
4160 | return; | |
4161 | ||
1439442c | 4162 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
4163 | vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); |
4164 | vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); | |
4165 | vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); | |
4166 | vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); | |
1439442c SY |
4167 | } |
4168 | } | |
4169 | ||
8f5d549f AK |
4170 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
4171 | { | |
d0d538b9 GN |
4172 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4173 | ||
8f5d549f | 4174 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
4175 | mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
4176 | mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
4177 | mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
4178 | mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 4179 | } |
6de4f3ad AK |
4180 | |
4181 | __set_bit(VCPU_EXREG_PDPTR, | |
4182 | (unsigned long *)&vcpu->arch.regs_avail); | |
4183 | __set_bit(VCPU_EXREG_PDPTR, | |
4184 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
4185 | } |
4186 | ||
3899152c DM |
4187 | static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) |
4188 | { | |
4189 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0; | |
4190 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1; | |
4191 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
4192 | ||
4193 | if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high & | |
4194 | SECONDARY_EXEC_UNRESTRICTED_GUEST && | |
4195 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) | |
4196 | fixed0 &= ~(X86_CR0_PE | X86_CR0_PG); | |
4197 | ||
4198 | return fixed_bits_valid(val, fixed0, fixed1); | |
4199 | } | |
4200 | ||
4201 | static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4202 | { | |
4203 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0; | |
4204 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1; | |
4205 | ||
4206 | return fixed_bits_valid(val, fixed0, fixed1); | |
4207 | } | |
4208 | ||
4209 | static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4210 | { | |
4211 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0; | |
4212 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1; | |
4213 | ||
4214 | return fixed_bits_valid(val, fixed0, fixed1); | |
4215 | } | |
4216 | ||
4217 | /* No difference in the restrictions on guest and host CR4 in VMX operation. */ | |
4218 | #define nested_guest_cr4_valid nested_cr4_valid | |
4219 | #define nested_host_cr4_valid nested_cr4_valid | |
4220 | ||
5e1746d6 | 4221 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1439442c SY |
4222 | |
4223 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
4224 | unsigned long cr0, | |
4225 | struct kvm_vcpu *vcpu) | |
4226 | { | |
5233dd51 MT |
4227 | if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
4228 | vmx_decache_cr3(vcpu); | |
1439442c SY |
4229 | if (!(cr0 & X86_CR0_PG)) { |
4230 | /* From paging/starting to nonpaging */ | |
4231 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4232 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
4233 | (CPU_BASED_CR3_LOAD_EXITING | |
4234 | CPU_BASED_CR3_STORE_EXITING)); | |
4235 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4236 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
4237 | } else if (!is_paging(vcpu)) { |
4238 | /* From nonpaging to paging */ | |
4239 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4240 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
4241 | ~(CPU_BASED_CR3_LOAD_EXITING | |
4242 | CPU_BASED_CR3_STORE_EXITING)); | |
4243 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4244 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 4245 | } |
95eb84a7 SY |
4246 | |
4247 | if (!(cr0 & X86_CR0_WP)) | |
4248 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
4249 | } |
4250 | ||
6aa8b732 AK |
4251 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
4252 | { | |
7ffd92c5 | 4253 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
4254 | unsigned long hw_cr0; |
4255 | ||
5037878e | 4256 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK); |
3a624e29 | 4257 | if (enable_unrestricted_guest) |
5037878e | 4258 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; |
218e763f | 4259 | else { |
5037878e | 4260 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; |
1439442c | 4261 | |
218e763f GN |
4262 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
4263 | enter_pmode(vcpu); | |
6aa8b732 | 4264 | |
218e763f GN |
4265 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
4266 | enter_rmode(vcpu); | |
4267 | } | |
6aa8b732 | 4268 | |
05b3e0c2 | 4269 | #ifdef CONFIG_X86_64 |
f6801dff | 4270 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 4271 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 4272 | enter_lmode(vcpu); |
707d92fa | 4273 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
4274 | exit_lmode(vcpu); |
4275 | } | |
4276 | #endif | |
4277 | ||
089d034e | 4278 | if (enable_ept) |
1439442c SY |
4279 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
4280 | ||
6aa8b732 | 4281 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 4282 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 4283 | vcpu->arch.cr0 = cr0; |
14168786 GN |
4284 | |
4285 | /* depends on vcpu->arch.cr0 to be set to a new value */ | |
4286 | vmx->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
4287 | } |
4288 | ||
855feb67 YZ |
4289 | static int get_ept_level(struct kvm_vcpu *vcpu) |
4290 | { | |
4291 | if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) | |
4292 | return 5; | |
4293 | return 4; | |
4294 | } | |
4295 | ||
995f00a6 | 4296 | static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) |
1439442c | 4297 | { |
855feb67 YZ |
4298 | u64 eptp = VMX_EPTP_MT_WB; |
4299 | ||
4300 | eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; | |
1439442c | 4301 | |
995f00a6 PF |
4302 | if (enable_ept_ad_bits && |
4303 | (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) | |
bb97a016 | 4304 | eptp |= VMX_EPTP_AD_ENABLE_BIT; |
1439442c SY |
4305 | eptp |= (root_hpa & PAGE_MASK); |
4306 | ||
4307 | return eptp; | |
4308 | } | |
4309 | ||
6aa8b732 AK |
4310 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
4311 | { | |
1439442c SY |
4312 | unsigned long guest_cr3; |
4313 | u64 eptp; | |
4314 | ||
4315 | guest_cr3 = cr3; | |
089d034e | 4316 | if (enable_ept) { |
995f00a6 | 4317 | eptp = construct_eptp(vcpu, cr3); |
1439442c | 4318 | vmcs_write64(EPT_POINTER, eptp); |
59ab5a8f JK |
4319 | if (is_paging(vcpu) || is_guest_mode(vcpu)) |
4320 | guest_cr3 = kvm_read_cr3(vcpu); | |
4321 | else | |
4322 | guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr; | |
7c93be44 | 4323 | ept_load_pdptrs(vcpu); |
1439442c SY |
4324 | } |
4325 | ||
2384d2b3 | 4326 | vmx_flush_tlb(vcpu); |
1439442c | 4327 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
4328 | } |
4329 | ||
5e1746d6 | 4330 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 4331 | { |
085e68ee BS |
4332 | /* |
4333 | * Pass through host's Machine Check Enable value to hw_cr4, which | |
4334 | * is in force while we are in guest mode. Do not let guests control | |
4335 | * this bit, even if host CR4.MCE == 0. | |
4336 | */ | |
4337 | unsigned long hw_cr4 = | |
4338 | (cr4_read_shadow() & X86_CR4_MCE) | | |
4339 | (cr4 & ~X86_CR4_MCE) | | |
4340 | (to_vmx(vcpu)->rmode.vm86_active ? | |
4341 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1439442c | 4342 | |
5e1746d6 NHE |
4343 | if (cr4 & X86_CR4_VMXE) { |
4344 | /* | |
4345 | * To use VMXON (and later other VMX instructions), a guest | |
4346 | * must first be able to turn on cr4.VMXE (see handle_vmon()). | |
4347 | * So basically the check on whether to allow nested VMX | |
4348 | * is here. | |
4349 | */ | |
4350 | if (!nested_vmx_allowed(vcpu)) | |
4351 | return 1; | |
1a0d74e6 | 4352 | } |
3899152c DM |
4353 | |
4354 | if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) | |
5e1746d6 NHE |
4355 | return 1; |
4356 | ||
ad312c7c | 4357 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
4358 | if (enable_ept) { |
4359 | if (!is_paging(vcpu)) { | |
4360 | hw_cr4 &= ~X86_CR4_PAE; | |
4361 | hw_cr4 |= X86_CR4_PSE; | |
4362 | } else if (!(cr4 & X86_CR4_PAE)) { | |
4363 | hw_cr4 &= ~X86_CR4_PAE; | |
4364 | } | |
4365 | } | |
1439442c | 4366 | |
656ec4a4 RK |
4367 | if (!enable_unrestricted_guest && !is_paging(vcpu)) |
4368 | /* | |
ddba2628 HH |
4369 | * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in |
4370 | * hardware. To emulate this behavior, SMEP/SMAP/PKU needs | |
4371 | * to be manually disabled when guest switches to non-paging | |
4372 | * mode. | |
4373 | * | |
4374 | * If !enable_unrestricted_guest, the CPU is always running | |
4375 | * with CR0.PG=1 and CR4 needs to be modified. | |
4376 | * If enable_unrestricted_guest, the CPU automatically | |
4377 | * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. | |
656ec4a4 | 4378 | */ |
ddba2628 | 4379 | hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); |
656ec4a4 | 4380 | |
1439442c SY |
4381 | vmcs_writel(CR4_READ_SHADOW, cr4); |
4382 | vmcs_writel(GUEST_CR4, hw_cr4); | |
5e1746d6 | 4383 | return 0; |
6aa8b732 AK |
4384 | } |
4385 | ||
6aa8b732 AK |
4386 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
4387 | struct kvm_segment *var, int seg) | |
4388 | { | |
a9179499 | 4389 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
4390 | u32 ar; |
4391 | ||
c6ad1153 | 4392 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
f5f7b2fe | 4393 | *var = vmx->rmode.segs[seg]; |
a9179499 | 4394 | if (seg == VCPU_SREG_TR |
2fb92db1 | 4395 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
f5f7b2fe | 4396 | return; |
1390a28b AK |
4397 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4398 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4399 | return; | |
a9179499 | 4400 | } |
2fb92db1 AK |
4401 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4402 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
4403 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4404 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
03617c18 | 4405 | var->unusable = (ar >> 16) & 1; |
6aa8b732 AK |
4406 | var->type = ar & 15; |
4407 | var->s = (ar >> 4) & 1; | |
4408 | var->dpl = (ar >> 5) & 3; | |
03617c18 GN |
4409 | /* |
4410 | * Some userspaces do not preserve unusable property. Since usable | |
4411 | * segment has to be present according to VMX spec we can use present | |
4412 | * property to amend userspace bug by making unusable segment always | |
4413 | * nonpresent. vmx_segment_access_rights() already marks nonpresent | |
4414 | * segment as unusable. | |
4415 | */ | |
4416 | var->present = !var->unusable; | |
6aa8b732 AK |
4417 | var->avl = (ar >> 12) & 1; |
4418 | var->l = (ar >> 13) & 1; | |
4419 | var->db = (ar >> 14) & 1; | |
4420 | var->g = (ar >> 15) & 1; | |
6aa8b732 AK |
4421 | } |
4422 | ||
a9179499 AK |
4423 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4424 | { | |
a9179499 AK |
4425 | struct kvm_segment s; |
4426 | ||
4427 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
4428 | vmx_get_segment(vcpu, &s, seg); | |
4429 | return s.base; | |
4430 | } | |
2fb92db1 | 4431 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
4432 | } |
4433 | ||
b09408d0 | 4434 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 4435 | { |
b09408d0 MT |
4436 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4437 | ||
ae9fedc7 | 4438 | if (unlikely(vmx->rmode.vm86_active)) |
2e4d2653 | 4439 | return 0; |
ae9fedc7 PB |
4440 | else { |
4441 | int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); | |
4d283ec9 | 4442 | return VMX_AR_DPL(ar); |
69c73028 | 4443 | } |
69c73028 AK |
4444 | } |
4445 | ||
653e3108 | 4446 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 4447 | { |
6aa8b732 AK |
4448 | u32 ar; |
4449 | ||
f0495f9b | 4450 | if (var->unusable || !var->present) |
6aa8b732 AK |
4451 | ar = 1 << 16; |
4452 | else { | |
4453 | ar = var->type & 15; | |
4454 | ar |= (var->s & 1) << 4; | |
4455 | ar |= (var->dpl & 3) << 5; | |
4456 | ar |= (var->present & 1) << 7; | |
4457 | ar |= (var->avl & 1) << 12; | |
4458 | ar |= (var->l & 1) << 13; | |
4459 | ar |= (var->db & 1) << 14; | |
4460 | ar |= (var->g & 1) << 15; | |
4461 | } | |
653e3108 AK |
4462 | |
4463 | return ar; | |
4464 | } | |
4465 | ||
4466 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
4467 | struct kvm_segment *var, int seg) | |
4468 | { | |
7ffd92c5 | 4469 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
772e0318 | 4470 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
653e3108 | 4471 | |
2fb92db1 AK |
4472 | vmx_segment_cache_clear(vmx); |
4473 | ||
1ecd50a9 GN |
4474 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
4475 | vmx->rmode.segs[seg] = *var; | |
4476 | if (seg == VCPU_SREG_TR) | |
4477 | vmcs_write16(sf->selector, var->selector); | |
4478 | else if (var->s) | |
4479 | fix_rmode_seg(seg, &vmx->rmode.segs[seg]); | |
d99e4152 | 4480 | goto out; |
653e3108 | 4481 | } |
1ecd50a9 | 4482 | |
653e3108 AK |
4483 | vmcs_writel(sf->base, var->base); |
4484 | vmcs_write32(sf->limit, var->limit); | |
4485 | vmcs_write16(sf->selector, var->selector); | |
3a624e29 NK |
4486 | |
4487 | /* | |
4488 | * Fix the "Accessed" bit in AR field of segment registers for older | |
4489 | * qemu binaries. | |
4490 | * IA32 arch specifies that at the time of processor reset the | |
4491 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
0fa06071 | 4492 | * is setting it to 0 in the userland code. This causes invalid guest |
3a624e29 NK |
4493 | * state vmexit when "unrestricted guest" mode is turned on. |
4494 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
4495 | * tree. Newer qemu binaries with that qemu fix would not need this | |
4496 | * kvm hack. | |
4497 | */ | |
4498 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
f924d66d | 4499 | var->type |= 0x1; /* Accessed */ |
3a624e29 | 4500 | |
f924d66d | 4501 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); |
d99e4152 GN |
4502 | |
4503 | out: | |
98eb2f8b | 4504 | vmx->emulation_required = emulation_required(vcpu); |
6aa8b732 AK |
4505 | } |
4506 | ||
6aa8b732 AK |
4507 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
4508 | { | |
2fb92db1 | 4509 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
4510 | |
4511 | *db = (ar >> 14) & 1; | |
4512 | *l = (ar >> 13) & 1; | |
4513 | } | |
4514 | ||
89a27f4d | 4515 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4516 | { |
89a27f4d GN |
4517 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
4518 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
4519 | } |
4520 | ||
89a27f4d | 4521 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4522 | { |
89a27f4d GN |
4523 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
4524 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
4525 | } |
4526 | ||
89a27f4d | 4527 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4528 | { |
89a27f4d GN |
4529 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
4530 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
4531 | } |
4532 | ||
89a27f4d | 4533 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4534 | { |
89a27f4d GN |
4535 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
4536 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
4537 | } |
4538 | ||
648dfaa7 MG |
4539 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
4540 | { | |
4541 | struct kvm_segment var; | |
4542 | u32 ar; | |
4543 | ||
4544 | vmx_get_segment(vcpu, &var, seg); | |
07f42f5f | 4545 | var.dpl = 0x3; |
0647f4aa GN |
4546 | if (seg == VCPU_SREG_CS) |
4547 | var.type = 0x3; | |
648dfaa7 MG |
4548 | ar = vmx_segment_access_rights(&var); |
4549 | ||
4550 | if (var.base != (var.selector << 4)) | |
4551 | return false; | |
89efbed0 | 4552 | if (var.limit != 0xffff) |
648dfaa7 | 4553 | return false; |
07f42f5f | 4554 | if (ar != 0xf3) |
648dfaa7 MG |
4555 | return false; |
4556 | ||
4557 | return true; | |
4558 | } | |
4559 | ||
4560 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
4561 | { | |
4562 | struct kvm_segment cs; | |
4563 | unsigned int cs_rpl; | |
4564 | ||
4565 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
b32a9918 | 4566 | cs_rpl = cs.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4567 | |
1872a3f4 AK |
4568 | if (cs.unusable) |
4569 | return false; | |
4d283ec9 | 4570 | if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) |
648dfaa7 MG |
4571 | return false; |
4572 | if (!cs.s) | |
4573 | return false; | |
4d283ec9 | 4574 | if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
4575 | if (cs.dpl > cs_rpl) |
4576 | return false; | |
1872a3f4 | 4577 | } else { |
648dfaa7 MG |
4578 | if (cs.dpl != cs_rpl) |
4579 | return false; | |
4580 | } | |
4581 | if (!cs.present) | |
4582 | return false; | |
4583 | ||
4584 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
4585 | return true; | |
4586 | } | |
4587 | ||
4588 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
4589 | { | |
4590 | struct kvm_segment ss; | |
4591 | unsigned int ss_rpl; | |
4592 | ||
4593 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
b32a9918 | 4594 | ss_rpl = ss.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4595 | |
1872a3f4 AK |
4596 | if (ss.unusable) |
4597 | return true; | |
4598 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
4599 | return false; |
4600 | if (!ss.s) | |
4601 | return false; | |
4602 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
4603 | return false; | |
4604 | if (!ss.present) | |
4605 | return false; | |
4606 | ||
4607 | return true; | |
4608 | } | |
4609 | ||
4610 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
4611 | { | |
4612 | struct kvm_segment var; | |
4613 | unsigned int rpl; | |
4614 | ||
4615 | vmx_get_segment(vcpu, &var, seg); | |
b32a9918 | 4616 | rpl = var.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4617 | |
1872a3f4 AK |
4618 | if (var.unusable) |
4619 | return true; | |
648dfaa7 MG |
4620 | if (!var.s) |
4621 | return false; | |
4622 | if (!var.present) | |
4623 | return false; | |
4d283ec9 | 4624 | if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { |
648dfaa7 MG |
4625 | if (var.dpl < rpl) /* DPL < RPL */ |
4626 | return false; | |
4627 | } | |
4628 | ||
4629 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
4630 | * rights flags | |
4631 | */ | |
4632 | return true; | |
4633 | } | |
4634 | ||
4635 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
4636 | { | |
4637 | struct kvm_segment tr; | |
4638 | ||
4639 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
4640 | ||
1872a3f4 AK |
4641 | if (tr.unusable) |
4642 | return false; | |
b32a9918 | 4643 | if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 | 4644 | return false; |
1872a3f4 | 4645 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
4646 | return false; |
4647 | if (!tr.present) | |
4648 | return false; | |
4649 | ||
4650 | return true; | |
4651 | } | |
4652 | ||
4653 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
4654 | { | |
4655 | struct kvm_segment ldtr; | |
4656 | ||
4657 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
4658 | ||
1872a3f4 AK |
4659 | if (ldtr.unusable) |
4660 | return true; | |
b32a9918 | 4661 | if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 MG |
4662 | return false; |
4663 | if (ldtr.type != 2) | |
4664 | return false; | |
4665 | if (!ldtr.present) | |
4666 | return false; | |
4667 | ||
4668 | return true; | |
4669 | } | |
4670 | ||
4671 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
4672 | { | |
4673 | struct kvm_segment cs, ss; | |
4674 | ||
4675 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
4676 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
4677 | ||
b32a9918 NA |
4678 | return ((cs.selector & SEGMENT_RPL_MASK) == |
4679 | (ss.selector & SEGMENT_RPL_MASK)); | |
648dfaa7 MG |
4680 | } |
4681 | ||
4682 | /* | |
4683 | * Check if guest state is valid. Returns true if valid, false if | |
4684 | * not. | |
4685 | * We assume that registers are always usable | |
4686 | */ | |
4687 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
4688 | { | |
c5e97c80 GN |
4689 | if (enable_unrestricted_guest) |
4690 | return true; | |
4691 | ||
648dfaa7 | 4692 | /* real mode guest state checks */ |
f13882d8 | 4693 | if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { |
648dfaa7 MG |
4694 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
4695 | return false; | |
4696 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
4697 | return false; | |
4698 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
4699 | return false; | |
4700 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
4701 | return false; | |
4702 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
4703 | return false; | |
4704 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
4705 | return false; | |
4706 | } else { | |
4707 | /* protected mode guest state checks */ | |
4708 | if (!cs_ss_rpl_check(vcpu)) | |
4709 | return false; | |
4710 | if (!code_segment_valid(vcpu)) | |
4711 | return false; | |
4712 | if (!stack_segment_valid(vcpu)) | |
4713 | return false; | |
4714 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
4715 | return false; | |
4716 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
4717 | return false; | |
4718 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
4719 | return false; | |
4720 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
4721 | return false; | |
4722 | if (!tr_valid(vcpu)) | |
4723 | return false; | |
4724 | if (!ldtr_valid(vcpu)) | |
4725 | return false; | |
4726 | } | |
4727 | /* TODO: | |
4728 | * - Add checks on RIP | |
4729 | * - Add checks on RFLAGS | |
4730 | */ | |
4731 | ||
4732 | return true; | |
4733 | } | |
4734 | ||
5fa99cbe JM |
4735 | static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa) |
4736 | { | |
4737 | return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu)); | |
4738 | } | |
4739 | ||
d77c26fc | 4740 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 4741 | { |
40dcaa9f | 4742 | gfn_t fn; |
195aefde | 4743 | u16 data = 0; |
1f755a82 | 4744 | int idx, r; |
6aa8b732 | 4745 | |
40dcaa9f | 4746 | idx = srcu_read_lock(&kvm->srcu); |
4918c6ca | 4747 | fn = kvm->arch.tss_addr >> PAGE_SHIFT; |
195aefde IE |
4748 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4749 | if (r < 0) | |
10589a46 | 4750 | goto out; |
195aefde | 4751 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
4752 | r = kvm_write_guest_page(kvm, fn++, &data, |
4753 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 4754 | if (r < 0) |
10589a46 | 4755 | goto out; |
195aefde IE |
4756 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
4757 | if (r < 0) | |
10589a46 | 4758 | goto out; |
195aefde IE |
4759 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4760 | if (r < 0) | |
10589a46 | 4761 | goto out; |
195aefde | 4762 | data = ~0; |
10589a46 MT |
4763 | r = kvm_write_guest_page(kvm, fn, &data, |
4764 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
4765 | sizeof(u8)); | |
10589a46 | 4766 | out: |
40dcaa9f | 4767 | srcu_read_unlock(&kvm->srcu, idx); |
1f755a82 | 4768 | return r; |
6aa8b732 AK |
4769 | } |
4770 | ||
b7ebfb05 SY |
4771 | static int init_rmode_identity_map(struct kvm *kvm) |
4772 | { | |
f51770ed | 4773 | int i, idx, r = 0; |
ba049e93 | 4774 | kvm_pfn_t identity_map_pfn; |
b7ebfb05 SY |
4775 | u32 tmp; |
4776 | ||
a255d479 TC |
4777 | /* Protect kvm->arch.ept_identity_pagetable_done. */ |
4778 | mutex_lock(&kvm->slots_lock); | |
4779 | ||
f51770ed | 4780 | if (likely(kvm->arch.ept_identity_pagetable_done)) |
a255d479 | 4781 | goto out2; |
a255d479 | 4782 | |
d8a6e365 DH |
4783 | if (!kvm->arch.ept_identity_map_addr) |
4784 | kvm->arch.ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
b927a3ce | 4785 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
a255d479 | 4786 | |
d8a6e365 DH |
4787 | r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, |
4788 | kvm->arch.ept_identity_map_addr, PAGE_SIZE); | |
f51770ed | 4789 | if (r < 0) |
a255d479 TC |
4790 | goto out2; |
4791 | ||
40dcaa9f | 4792 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
4793 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
4794 | if (r < 0) | |
4795 | goto out; | |
4796 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
4797 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
4798 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
4799 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
4800 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
4801 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
4802 | if (r < 0) | |
4803 | goto out; | |
4804 | } | |
4805 | kvm->arch.ept_identity_pagetable_done = true; | |
f51770ed | 4806 | |
b7ebfb05 | 4807 | out: |
40dcaa9f | 4808 | srcu_read_unlock(&kvm->srcu, idx); |
a255d479 TC |
4809 | |
4810 | out2: | |
4811 | mutex_unlock(&kvm->slots_lock); | |
f51770ed | 4812 | return r; |
b7ebfb05 SY |
4813 | } |
4814 | ||
6aa8b732 AK |
4815 | static void seg_setup(int seg) |
4816 | { | |
772e0318 | 4817 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
3a624e29 | 4818 | unsigned int ar; |
6aa8b732 AK |
4819 | |
4820 | vmcs_write16(sf->selector, 0); | |
4821 | vmcs_writel(sf->base, 0); | |
4822 | vmcs_write32(sf->limit, 0xffff); | |
d54d07b2 GN |
4823 | ar = 0x93; |
4824 | if (seg == VCPU_SREG_CS) | |
4825 | ar |= 0x08; /* code segment */ | |
3a624e29 NK |
4826 | |
4827 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
4828 | } |
4829 | ||
f78e0e2e SY |
4830 | static int alloc_apic_access_page(struct kvm *kvm) |
4831 | { | |
4484141a | 4832 | struct page *page; |
f78e0e2e SY |
4833 | int r = 0; |
4834 | ||
79fac95e | 4835 | mutex_lock(&kvm->slots_lock); |
c24ae0dc | 4836 | if (kvm->arch.apic_access_page_done) |
f78e0e2e | 4837 | goto out; |
1d8007bd PB |
4838 | r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, |
4839 | APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); | |
f78e0e2e SY |
4840 | if (r) |
4841 | goto out; | |
72dc67a6 | 4842 | |
73a6d941 | 4843 | page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
4484141a XG |
4844 | if (is_error_page(page)) { |
4845 | r = -EFAULT; | |
4846 | goto out; | |
4847 | } | |
4848 | ||
c24ae0dc TC |
4849 | /* |
4850 | * Do not pin the page in memory, so that memory hot-unplug | |
4851 | * is able to migrate it. | |
4852 | */ | |
4853 | put_page(page); | |
4854 | kvm->arch.apic_access_page_done = true; | |
f78e0e2e | 4855 | out: |
79fac95e | 4856 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
4857 | return r; |
4858 | } | |
4859 | ||
991e7a0e | 4860 | static int allocate_vpid(void) |
2384d2b3 SY |
4861 | { |
4862 | int vpid; | |
4863 | ||
919818ab | 4864 | if (!enable_vpid) |
991e7a0e | 4865 | return 0; |
2384d2b3 SY |
4866 | spin_lock(&vmx_vpid_lock); |
4867 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
991e7a0e | 4868 | if (vpid < VMX_NR_VPIDS) |
2384d2b3 | 4869 | __set_bit(vpid, vmx_vpid_bitmap); |
991e7a0e WL |
4870 | else |
4871 | vpid = 0; | |
2384d2b3 | 4872 | spin_unlock(&vmx_vpid_lock); |
991e7a0e | 4873 | return vpid; |
2384d2b3 SY |
4874 | } |
4875 | ||
991e7a0e | 4876 | static void free_vpid(int vpid) |
cdbecfc3 | 4877 | { |
991e7a0e | 4878 | if (!enable_vpid || vpid == 0) |
cdbecfc3 LJ |
4879 | return; |
4880 | spin_lock(&vmx_vpid_lock); | |
991e7a0e | 4881 | __clear_bit(vpid, vmx_vpid_bitmap); |
cdbecfc3 LJ |
4882 | spin_unlock(&vmx_vpid_lock); |
4883 | } | |
4884 | ||
8d14695f YZ |
4885 | #define MSR_TYPE_R 1 |
4886 | #define MSR_TYPE_W 2 | |
4887 | static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, | |
4888 | u32 msr, int type) | |
25c5f225 | 4889 | { |
3e7c73e9 | 4890 | int f = sizeof(unsigned long); |
25c5f225 SY |
4891 | |
4892 | if (!cpu_has_vmx_msr_bitmap()) | |
4893 | return; | |
4894 | ||
4895 | /* | |
4896 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4897 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4898 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4899 | */ | |
25c5f225 | 4900 | if (msr <= 0x1fff) { |
8d14695f YZ |
4901 | if (type & MSR_TYPE_R) |
4902 | /* read-low */ | |
4903 | __clear_bit(msr, msr_bitmap + 0x000 / f); | |
4904 | ||
4905 | if (type & MSR_TYPE_W) | |
4906 | /* write-low */ | |
4907 | __clear_bit(msr, msr_bitmap + 0x800 / f); | |
4908 | ||
25c5f225 SY |
4909 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
4910 | msr &= 0x1fff; | |
8d14695f YZ |
4911 | if (type & MSR_TYPE_R) |
4912 | /* read-high */ | |
4913 | __clear_bit(msr, msr_bitmap + 0x400 / f); | |
4914 | ||
4915 | if (type & MSR_TYPE_W) | |
4916 | /* write-high */ | |
4917 | __clear_bit(msr, msr_bitmap + 0xc00 / f); | |
4918 | ||
4919 | } | |
4920 | } | |
4921 | ||
f2b93280 WV |
4922 | /* |
4923 | * If a msr is allowed by L0, we should check whether it is allowed by L1. | |
4924 | * The corresponding bit will be cleared unless both of L0 and L1 allow it. | |
4925 | */ | |
4926 | static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1, | |
4927 | unsigned long *msr_bitmap_nested, | |
4928 | u32 msr, int type) | |
4929 | { | |
4930 | int f = sizeof(unsigned long); | |
4931 | ||
4932 | if (!cpu_has_vmx_msr_bitmap()) { | |
4933 | WARN_ON(1); | |
4934 | return; | |
4935 | } | |
4936 | ||
4937 | /* | |
4938 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4939 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4940 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4941 | */ | |
4942 | if (msr <= 0x1fff) { | |
4943 | if (type & MSR_TYPE_R && | |
4944 | !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) | |
4945 | /* read-low */ | |
4946 | __clear_bit(msr, msr_bitmap_nested + 0x000 / f); | |
4947 | ||
4948 | if (type & MSR_TYPE_W && | |
4949 | !test_bit(msr, msr_bitmap_l1 + 0x800 / f)) | |
4950 | /* write-low */ | |
4951 | __clear_bit(msr, msr_bitmap_nested + 0x800 / f); | |
4952 | ||
4953 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
4954 | msr &= 0x1fff; | |
4955 | if (type & MSR_TYPE_R && | |
4956 | !test_bit(msr, msr_bitmap_l1 + 0x400 / f)) | |
4957 | /* read-high */ | |
4958 | __clear_bit(msr, msr_bitmap_nested + 0x400 / f); | |
4959 | ||
4960 | if (type & MSR_TYPE_W && | |
4961 | !test_bit(msr, msr_bitmap_l1 + 0xc00 / f)) | |
4962 | /* write-high */ | |
4963 | __clear_bit(msr, msr_bitmap_nested + 0xc00 / f); | |
4964 | ||
4965 | } | |
4966 | } | |
4967 | ||
5897297b AK |
4968 | static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) |
4969 | { | |
4970 | if (!longmode_only) | |
8d14695f YZ |
4971 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, |
4972 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
4973 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, | |
4974 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
4975 | } | |
4976 | ||
2e69f865 | 4977 | static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active) |
8d14695f | 4978 | { |
f6e90f9e | 4979 | if (apicv_active) { |
c63e4563 | 4980 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv, |
2e69f865 | 4981 | msr, type); |
c63e4563 | 4982 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv, |
2e69f865 | 4983 | msr, type); |
f6e90f9e | 4984 | } else { |
f6e90f9e | 4985 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, |
2e69f865 | 4986 | msr, type); |
f6e90f9e | 4987 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, |
2e69f865 | 4988 | msr, type); |
f6e90f9e | 4989 | } |
5897297b AK |
4990 | } |
4991 | ||
b2a05fef | 4992 | static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu) |
d50ab6c1 | 4993 | { |
d62caabb | 4994 | return enable_apicv; |
d50ab6c1 PB |
4995 | } |
4996 | ||
c9f04407 DM |
4997 | static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu) |
4998 | { | |
4999 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
5000 | gfn_t gfn; | |
5001 | ||
5002 | /* | |
5003 | * Don't need to mark the APIC access page dirty; it is never | |
5004 | * written to by the CPU during APIC virtualization. | |
5005 | */ | |
5006 | ||
5007 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
5008 | gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT; | |
5009 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
5010 | } | |
5011 | ||
5012 | if (nested_cpu_has_posted_intr(vmcs12)) { | |
5013 | gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT; | |
5014 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
5015 | } | |
5016 | } | |
5017 | ||
5018 | ||
6342c50a | 5019 | static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu) |
705699a1 WV |
5020 | { |
5021 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5022 | int max_irr; | |
5023 | void *vapic_page; | |
5024 | u16 status; | |
5025 | ||
c9f04407 DM |
5026 | if (!vmx->nested.pi_desc || !vmx->nested.pi_pending) |
5027 | return; | |
705699a1 | 5028 | |
c9f04407 DM |
5029 | vmx->nested.pi_pending = false; |
5030 | if (!pi_test_and_clear_on(vmx->nested.pi_desc)) | |
5031 | return; | |
705699a1 | 5032 | |
c9f04407 DM |
5033 | max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256); |
5034 | if (max_irr != 256) { | |
705699a1 | 5035 | vapic_page = kmap(vmx->nested.virtual_apic_page); |
705699a1 WV |
5036 | __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page); |
5037 | kunmap(vmx->nested.virtual_apic_page); | |
5038 | ||
5039 | status = vmcs_read16(GUEST_INTR_STATUS); | |
5040 | if ((u8)max_irr > ((u8)status & 0xff)) { | |
5041 | status &= ~0xff; | |
5042 | status |= (u8)max_irr; | |
5043 | vmcs_write16(GUEST_INTR_STATUS, status); | |
5044 | } | |
5045 | } | |
c9f04407 DM |
5046 | |
5047 | nested_mark_vmcs12_pages_dirty(vcpu); | |
705699a1 WV |
5048 | } |
5049 | ||
06a5524f WV |
5050 | static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, |
5051 | bool nested) | |
21bc8dc5 RK |
5052 | { |
5053 | #ifdef CONFIG_SMP | |
06a5524f WV |
5054 | int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; |
5055 | ||
21bc8dc5 | 5056 | if (vcpu->mode == IN_GUEST_MODE) { |
28b835d6 | 5057 | /* |
5753743f HZ |
5058 | * The vector of interrupt to be delivered to vcpu had |
5059 | * been set in PIR before this function. | |
5060 | * | |
5061 | * Following cases will be reached in this block, and | |
5062 | * we always send a notification event in all cases as | |
5063 | * explained below. | |
5064 | * | |
5065 | * Case 1: vcpu keeps in non-root mode. Sending a | |
5066 | * notification event posts the interrupt to vcpu. | |
5067 | * | |
5068 | * Case 2: vcpu exits to root mode and is still | |
5069 | * runnable. PIR will be synced to vIRR before the | |
5070 | * next vcpu entry. Sending a notification event in | |
5071 | * this case has no effect, as vcpu is not in root | |
5072 | * mode. | |
28b835d6 | 5073 | * |
5753743f HZ |
5074 | * Case 3: vcpu exits to root mode and is blocked. |
5075 | * vcpu_block() has already synced PIR to vIRR and | |
5076 | * never blocks vcpu if vIRR is not cleared. Therefore, | |
5077 | * a blocked vcpu here does not wait for any requested | |
5078 | * interrupts in PIR, and sending a notification event | |
5079 | * which has no effect is safe here. | |
28b835d6 | 5080 | */ |
28b835d6 | 5081 | |
06a5524f | 5082 | apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); |
21bc8dc5 RK |
5083 | return true; |
5084 | } | |
5085 | #endif | |
5086 | return false; | |
5087 | } | |
5088 | ||
705699a1 WV |
5089 | static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, |
5090 | int vector) | |
5091 | { | |
5092 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5093 | ||
5094 | if (is_guest_mode(vcpu) && | |
5095 | vector == vmx->nested.posted_intr_nv) { | |
5096 | /* the PIR and ON have been set by L1. */ | |
06a5524f | 5097 | kvm_vcpu_trigger_posted_interrupt(vcpu, true); |
705699a1 WV |
5098 | /* |
5099 | * If a posted intr is not recognized by hardware, | |
5100 | * we will accomplish it in the next vmentry. | |
5101 | */ | |
5102 | vmx->nested.pi_pending = true; | |
5103 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5104 | return 0; | |
5105 | } | |
5106 | return -1; | |
5107 | } | |
a20ed54d YZ |
5108 | /* |
5109 | * Send interrupt to vcpu via posted interrupt way. | |
5110 | * 1. If target vcpu is running(non-root mode), send posted interrupt | |
5111 | * notification to vcpu and hardware will sync PIR to vIRR atomically. | |
5112 | * 2. If target vcpu isn't running(root mode), kick it to pick up the | |
5113 | * interrupt from PIR in next vmentry. | |
5114 | */ | |
5115 | static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) | |
5116 | { | |
5117 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5118 | int r; | |
5119 | ||
705699a1 WV |
5120 | r = vmx_deliver_nested_posted_interrupt(vcpu, vector); |
5121 | if (!r) | |
5122 | return; | |
5123 | ||
a20ed54d YZ |
5124 | if (pi_test_and_set_pir(vector, &vmx->pi_desc)) |
5125 | return; | |
5126 | ||
b95234c8 PB |
5127 | /* If a previous notification has sent the IPI, nothing to do. */ |
5128 | if (pi_test_and_set_on(&vmx->pi_desc)) | |
5129 | return; | |
5130 | ||
06a5524f | 5131 | if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) |
a20ed54d YZ |
5132 | kvm_vcpu_kick(vcpu); |
5133 | } | |
5134 | ||
a3a8ff8e NHE |
5135 | /* |
5136 | * Set up the vmcs's constant host-state fields, i.e., host-state fields that | |
5137 | * will not change in the lifetime of the guest. | |
5138 | * Note that host-state that does change is set elsewhere. E.g., host-state | |
5139 | * that is set differently for each CPU is set in vmx_vcpu_load(), not here. | |
5140 | */ | |
a547c6db | 5141 | static void vmx_set_constant_host_state(struct vcpu_vmx *vmx) |
a3a8ff8e NHE |
5142 | { |
5143 | u32 low32, high32; | |
5144 | unsigned long tmpl; | |
5145 | struct desc_ptr dt; | |
d6e41f11 | 5146 | unsigned long cr0, cr3, cr4; |
a3a8ff8e | 5147 | |
04ac88ab AL |
5148 | cr0 = read_cr0(); |
5149 | WARN_ON(cr0 & X86_CR0_TS); | |
5150 | vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ | |
d6e41f11 AL |
5151 | |
5152 | /* | |
5153 | * Save the most likely value for this task's CR3 in the VMCS. | |
5154 | * We can't use __get_current_cr3_fast() because we're not atomic. | |
5155 | */ | |
6c690ee1 | 5156 | cr3 = __read_cr3(); |
d6e41f11 | 5157 | vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ |
44889942 | 5158 | vmx->loaded_vmcs->vmcs_host_cr3 = cr3; |
a3a8ff8e | 5159 | |
d974baa3 | 5160 | /* Save the most likely value for this task's CR4 in the VMCS. */ |
1e02ce4c | 5161 | cr4 = cr4_read_shadow(); |
d974baa3 | 5162 | vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ |
44889942 | 5163 | vmx->loaded_vmcs->vmcs_host_cr4 = cr4; |
d974baa3 | 5164 | |
a3a8ff8e | 5165 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ |
b2da15ac AK |
5166 | #ifdef CONFIG_X86_64 |
5167 | /* | |
5168 | * Load null selectors, so we can avoid reloading them in | |
5169 | * __vmx_load_host_state(), in case userspace uses the null selectors | |
5170 | * too (the expected case). | |
5171 | */ | |
5172 | vmcs_write16(HOST_DS_SELECTOR, 0); | |
5173 | vmcs_write16(HOST_ES_SELECTOR, 0); | |
5174 | #else | |
a3a8ff8e NHE |
5175 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5176 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
b2da15ac | 5177 | #endif |
a3a8ff8e NHE |
5178 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5179 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
5180 | ||
87930019 | 5181 | store_idt(&dt); |
a3a8ff8e | 5182 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ |
a547c6db | 5183 | vmx->host_idt_base = dt.address; |
a3a8ff8e | 5184 | |
83287ea4 | 5185 | vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */ |
a3a8ff8e NHE |
5186 | |
5187 | rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); | |
5188 | vmcs_write32(HOST_IA32_SYSENTER_CS, low32); | |
5189 | rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); | |
5190 | vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ | |
5191 | ||
5192 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { | |
5193 | rdmsr(MSR_IA32_CR_PAT, low32, high32); | |
5194 | vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); | |
5195 | } | |
5196 | } | |
5197 | ||
bf8179a0 NHE |
5198 | static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) |
5199 | { | |
5200 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; | |
5201 | if (enable_ept) | |
5202 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
fe3ef05c NHE |
5203 | if (is_guest_mode(&vmx->vcpu)) |
5204 | vmx->vcpu.arch.cr4_guest_owned_bits &= | |
5205 | ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; | |
bf8179a0 NHE |
5206 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
5207 | } | |
5208 | ||
01e439be YZ |
5209 | static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) |
5210 | { | |
5211 | u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; | |
5212 | ||
d62caabb | 5213 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
01e439be | 5214 | pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; |
64672c95 YJ |
5215 | /* Enable the preemption timer dynamically */ |
5216 | pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
5217 | return pin_based_exec_ctrl; |
5218 | } | |
5219 | ||
d62caabb AS |
5220 | static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
5221 | { | |
5222 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5223 | ||
5224 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); | |
3ce424e4 RK |
5225 | if (cpu_has_secondary_exec_ctrls()) { |
5226 | if (kvm_vcpu_apicv_active(vcpu)) | |
5227 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
5228 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5229 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5230 | else | |
5231 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
5232 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5233 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5234 | } | |
5235 | ||
5236 | if (cpu_has_vmx_msr_bitmap()) | |
5237 | vmx_set_msr_bitmap(vcpu); | |
d62caabb AS |
5238 | } |
5239 | ||
bf8179a0 NHE |
5240 | static u32 vmx_exec_control(struct vcpu_vmx *vmx) |
5241 | { | |
5242 | u32 exec_control = vmcs_config.cpu_based_exec_ctrl; | |
d16c293e PB |
5243 | |
5244 | if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) | |
5245 | exec_control &= ~CPU_BASED_MOV_DR_EXITING; | |
5246 | ||
35754c98 | 5247 | if (!cpu_need_tpr_shadow(&vmx->vcpu)) { |
bf8179a0 NHE |
5248 | exec_control &= ~CPU_BASED_TPR_SHADOW; |
5249 | #ifdef CONFIG_X86_64 | |
5250 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
5251 | CPU_BASED_CR8_LOAD_EXITING; | |
5252 | #endif | |
5253 | } | |
5254 | if (!enable_ept) | |
5255 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
5256 | CPU_BASED_CR3_LOAD_EXITING | | |
5257 | CPU_BASED_INVLPG_EXITING; | |
5258 | return exec_control; | |
5259 | } | |
5260 | ||
45ec368c | 5261 | static bool vmx_rdrand_supported(void) |
bf8179a0 | 5262 | { |
45ec368c | 5263 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
736fdf72 | 5264 | SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5265 | } |
5266 | ||
75f4fc8d JM |
5267 | static bool vmx_rdseed_supported(void) |
5268 | { | |
5269 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
736fdf72 | 5270 | SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5271 | } |
5272 | ||
80154d77 | 5273 | static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) |
bf8179a0 | 5274 | { |
80154d77 PB |
5275 | struct kvm_vcpu *vcpu = &vmx->vcpu; |
5276 | ||
bf8179a0 | 5277 | u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; |
80154d77 | 5278 | if (!cpu_need_virtualize_apic_accesses(vcpu)) |
bf8179a0 NHE |
5279 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
5280 | if (vmx->vpid == 0) | |
5281 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
5282 | if (!enable_ept) { | |
5283 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
5284 | enable_unrestricted_guest = 0; | |
ad756a16 MJ |
5285 | /* Enable INVPCID for non-ept guests may cause performance regression. */ |
5286 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
bf8179a0 NHE |
5287 | } |
5288 | if (!enable_unrestricted_guest) | |
5289 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
5290 | if (!ple_gap) | |
5291 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
80154d77 | 5292 | if (!kvm_vcpu_apicv_active(vcpu)) |
c7c9c56c YZ |
5293 | exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | |
5294 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
8d14695f | 5295 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; |
abc4fc58 AG |
5296 | /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD |
5297 | (handle_vmptrld). | |
5298 | We can NOT enable shadow_vmcs here because we don't have yet | |
5299 | a current VMCS12 | |
5300 | */ | |
5301 | exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
a3eaa864 KH |
5302 | |
5303 | if (!enable_pml) | |
5304 | exec_control &= ~SECONDARY_EXEC_ENABLE_PML; | |
843e4330 | 5305 | |
3db13480 PB |
5306 | if (vmx_xsaves_supported()) { |
5307 | /* Exposing XSAVES only when XSAVE is exposed */ | |
5308 | bool xsaves_enabled = | |
5309 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && | |
5310 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); | |
5311 | ||
5312 | if (!xsaves_enabled) | |
5313 | exec_control &= ~SECONDARY_EXEC_XSAVES; | |
5314 | ||
5315 | if (nested) { | |
5316 | if (xsaves_enabled) | |
5317 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5318 | SECONDARY_EXEC_XSAVES; | |
5319 | else | |
5320 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5321 | ~SECONDARY_EXEC_XSAVES; | |
5322 | } | |
5323 | } | |
5324 | ||
80154d77 PB |
5325 | if (vmx_rdtscp_supported()) { |
5326 | bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); | |
5327 | if (!rdtscp_enabled) | |
5328 | exec_control &= ~SECONDARY_EXEC_RDTSCP; | |
5329 | ||
5330 | if (nested) { | |
5331 | if (rdtscp_enabled) | |
5332 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5333 | SECONDARY_EXEC_RDTSCP; | |
5334 | else | |
5335 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5336 | ~SECONDARY_EXEC_RDTSCP; | |
5337 | } | |
5338 | } | |
5339 | ||
5340 | if (vmx_invpcid_supported()) { | |
5341 | /* Exposing INVPCID only when PCID is exposed */ | |
5342 | bool invpcid_enabled = | |
5343 | guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && | |
5344 | guest_cpuid_has(vcpu, X86_FEATURE_PCID); | |
5345 | ||
5346 | if (!invpcid_enabled) { | |
5347 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
5348 | guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); | |
5349 | } | |
5350 | ||
5351 | if (nested) { | |
5352 | if (invpcid_enabled) | |
5353 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5354 | SECONDARY_EXEC_ENABLE_INVPCID; | |
5355 | else | |
5356 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5357 | ~SECONDARY_EXEC_ENABLE_INVPCID; | |
5358 | } | |
5359 | } | |
5360 | ||
45ec368c JM |
5361 | if (vmx_rdrand_supported()) { |
5362 | bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); | |
5363 | if (rdrand_enabled) | |
736fdf72 | 5364 | exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5365 | |
5366 | if (nested) { | |
5367 | if (rdrand_enabled) | |
5368 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
736fdf72 | 5369 | SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5370 | else |
5371 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
736fdf72 | 5372 | ~SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5373 | } |
5374 | } | |
5375 | ||
75f4fc8d JM |
5376 | if (vmx_rdseed_supported()) { |
5377 | bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); | |
5378 | if (rdseed_enabled) | |
736fdf72 | 5379 | exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5380 | |
5381 | if (nested) { | |
5382 | if (rdseed_enabled) | |
5383 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
736fdf72 | 5384 | SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5385 | else |
5386 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
736fdf72 | 5387 | ~SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5388 | } |
5389 | } | |
5390 | ||
80154d77 | 5391 | vmx->secondary_exec_control = exec_control; |
bf8179a0 NHE |
5392 | } |
5393 | ||
ce88decf XG |
5394 | static void ept_set_mmio_spte_mask(void) |
5395 | { | |
5396 | /* | |
5397 | * EPT Misconfigurations can be generated if the value of bits 2:0 | |
5398 | * of an EPT paging-structure entry is 110b (write/execute). | |
ce88decf | 5399 | */ |
dcdca5fe PF |
5400 | kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, |
5401 | VMX_EPT_MISCONFIG_WX_VALUE); | |
ce88decf XG |
5402 | } |
5403 | ||
f53cd63c | 5404 | #define VMX_XSS_EXIT_BITMAP 0 |
6aa8b732 AK |
5405 | /* |
5406 | * Sets up the vmcs for emulated real mode. | |
5407 | */ | |
12d79917 | 5408 | static void vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 5409 | { |
2e4ce7f5 | 5410 | #ifdef CONFIG_X86_64 |
6aa8b732 | 5411 | unsigned long a; |
2e4ce7f5 | 5412 | #endif |
6aa8b732 | 5413 | int i; |
6aa8b732 | 5414 | |
6aa8b732 | 5415 | /* I/O */ |
3e7c73e9 AK |
5416 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
5417 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 5418 | |
4607c2d7 AG |
5419 | if (enable_shadow_vmcs) { |
5420 | vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); | |
5421 | vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); | |
5422 | } | |
25c5f225 | 5423 | if (cpu_has_vmx_msr_bitmap()) |
5897297b | 5424 | vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy)); |
25c5f225 | 5425 | |
6aa8b732 AK |
5426 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
5427 | ||
6aa8b732 | 5428 | /* Control */ |
01e439be | 5429 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); |
64672c95 | 5430 | vmx->hv_deadline_tsc = -1; |
6e5d865c | 5431 | |
bf8179a0 | 5432 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx)); |
6aa8b732 | 5433 | |
dfa169bb | 5434 | if (cpu_has_secondary_exec_ctrls()) { |
80154d77 | 5435 | vmx_compute_secondary_exec_control(vmx); |
bf8179a0 | 5436 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, |
80154d77 | 5437 | vmx->secondary_exec_control); |
dfa169bb | 5438 | } |
f78e0e2e | 5439 | |
d62caabb | 5440 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) { |
c7c9c56c YZ |
5441 | vmcs_write64(EOI_EXIT_BITMAP0, 0); |
5442 | vmcs_write64(EOI_EXIT_BITMAP1, 0); | |
5443 | vmcs_write64(EOI_EXIT_BITMAP2, 0); | |
5444 | vmcs_write64(EOI_EXIT_BITMAP3, 0); | |
5445 | ||
5446 | vmcs_write16(GUEST_INTR_STATUS, 0); | |
01e439be | 5447 | |
0bcf261c | 5448 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
01e439be | 5449 | vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); |
c7c9c56c YZ |
5450 | } |
5451 | ||
4b8d54f9 ZE |
5452 | if (ple_gap) { |
5453 | vmcs_write32(PLE_GAP, ple_gap); | |
a7653ecd RK |
5454 | vmx->ple_window = ple_window; |
5455 | vmx->ple_window_dirty = true; | |
4b8d54f9 ZE |
5456 | } |
5457 | ||
c3707958 XG |
5458 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
5459 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
6aa8b732 AK |
5460 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
5461 | ||
9581d442 AK |
5462 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
5463 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
a547c6db | 5464 | vmx_set_constant_host_state(vmx); |
05b3e0c2 | 5465 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
5466 | rdmsrl(MSR_FS_BASE, a); |
5467 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
5468 | rdmsrl(MSR_GS_BASE, a); | |
5469 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
5470 | #else | |
5471 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
5472 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
5473 | #endif | |
5474 | ||
2a499e49 BD |
5475 | if (cpu_has_vmx_vmfunc()) |
5476 | vmcs_write64(VM_FUNCTION_CONTROL, 0); | |
5477 | ||
2cc51560 ED |
5478 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
5479 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
61d2ef2c | 5480 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); |
2cc51560 | 5481 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
61d2ef2c | 5482 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); |
6aa8b732 | 5483 | |
74545705 RK |
5484 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) |
5485 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); | |
468d472f | 5486 | |
03916db9 | 5487 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { |
6aa8b732 AK |
5488 | u32 index = vmx_msr_index[i]; |
5489 | u32 data_low, data_high; | |
a2fa3e9f | 5490 | int j = vmx->nmsrs; |
6aa8b732 AK |
5491 | |
5492 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
5493 | continue; | |
432bd6cb AK |
5494 | if (wrmsr_safe(index, data_low, data_high) < 0) |
5495 | continue; | |
26bb0981 AK |
5496 | vmx->guest_msrs[j].index = i; |
5497 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 5498 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 5499 | ++vmx->nmsrs; |
6aa8b732 | 5500 | } |
6aa8b732 | 5501 | |
2961e876 GN |
5502 | |
5503 | vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl); | |
6aa8b732 AK |
5504 | |
5505 | /* 22.2.1, 20.8.1 */ | |
2961e876 | 5506 | vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl); |
1c3d14fe | 5507 | |
bd7e5b08 PB |
5508 | vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; |
5509 | vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); | |
5510 | ||
bf8179a0 | 5511 | set_cr4_guest_host_mask(vmx); |
e00c8cf2 | 5512 | |
f53cd63c WL |
5513 | if (vmx_xsaves_supported()) |
5514 | vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); | |
5515 | ||
4e59516a PF |
5516 | if (enable_pml) { |
5517 | ASSERT(vmx->pml_pg); | |
5518 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
5519 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
5520 | } | |
e00c8cf2 AK |
5521 | } |
5522 | ||
d28bc9dd | 5523 | static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e00c8cf2 AK |
5524 | { |
5525 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
58cb628d | 5526 | struct msr_data apic_base_msr; |
d28bc9dd | 5527 | u64 cr0; |
e00c8cf2 | 5528 | |
7ffd92c5 | 5529 | vmx->rmode.vm86_active = 0; |
e00c8cf2 | 5530 | |
ad312c7c | 5531 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
d28bc9dd NA |
5532 | kvm_set_cr8(vcpu, 0); |
5533 | ||
5534 | if (!init_event) { | |
5535 | apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | | |
5536 | MSR_IA32_APICBASE_ENABLE; | |
5537 | if (kvm_vcpu_is_reset_bsp(vcpu)) | |
5538 | apic_base_msr.data |= MSR_IA32_APICBASE_BSP; | |
5539 | apic_base_msr.host_initiated = true; | |
5540 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
5541 | } | |
e00c8cf2 | 5542 | |
2fb92db1 AK |
5543 | vmx_segment_cache_clear(vmx); |
5544 | ||
5706be0d | 5545 | seg_setup(VCPU_SREG_CS); |
66450a21 | 5546 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
f3531054 | 5547 | vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); |
e00c8cf2 AK |
5548 | |
5549 | seg_setup(VCPU_SREG_DS); | |
5550 | seg_setup(VCPU_SREG_ES); | |
5551 | seg_setup(VCPU_SREG_FS); | |
5552 | seg_setup(VCPU_SREG_GS); | |
5553 | seg_setup(VCPU_SREG_SS); | |
5554 | ||
5555 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
5556 | vmcs_writel(GUEST_TR_BASE, 0); | |
5557 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
5558 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
5559 | ||
5560 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
5561 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
5562 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
5563 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
5564 | ||
d28bc9dd NA |
5565 | if (!init_event) { |
5566 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
5567 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
5568 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
5569 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
5570 | } | |
e00c8cf2 AK |
5571 | |
5572 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
66450a21 | 5573 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 5574 | |
e00c8cf2 AK |
5575 | vmcs_writel(GUEST_GDTR_BASE, 0); |
5576 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
5577 | ||
5578 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
5579 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
5580 | ||
443381a8 | 5581 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 | 5582 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
f3531054 | 5583 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); |
e00c8cf2 | 5584 | |
e00c8cf2 AK |
5585 | setup_msrs(vmx); |
5586 | ||
6aa8b732 AK |
5587 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
5588 | ||
d28bc9dd | 5589 | if (cpu_has_vmx_tpr_shadow() && !init_event) { |
f78e0e2e | 5590 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); |
35754c98 | 5591 | if (cpu_need_tpr_shadow(vcpu)) |
f78e0e2e | 5592 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, |
d28bc9dd | 5593 | __pa(vcpu->arch.apic->regs)); |
f78e0e2e SY |
5594 | vmcs_write32(TPR_THRESHOLD, 0); |
5595 | } | |
5596 | ||
a73896cb | 5597 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
6aa8b732 | 5598 | |
d62caabb | 5599 | if (kvm_vcpu_apicv_active(vcpu)) |
01e439be YZ |
5600 | memset(&vmx->pi_desc, 0, sizeof(struct pi_desc)); |
5601 | ||
2384d2b3 SY |
5602 | if (vmx->vpid != 0) |
5603 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
5604 | ||
d28bc9dd | 5605 | cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
d28bc9dd | 5606 | vmx->vcpu.arch.cr0 = cr0; |
f2463247 | 5607 | vmx_set_cr0(vcpu, cr0); /* enter rmode */ |
d28bc9dd | 5608 | vmx_set_cr4(vcpu, 0); |
5690891b | 5609 | vmx_set_efer(vcpu, 0); |
bd7e5b08 | 5610 | |
d28bc9dd | 5611 | update_exception_bitmap(vcpu); |
6aa8b732 | 5612 | |
dd5f5341 | 5613 | vpid_sync_context(vmx->vpid); |
6aa8b732 AK |
5614 | } |
5615 | ||
b6f1250e NHE |
5616 | /* |
5617 | * In nested virtualization, check if L1 asked to exit on external interrupts. | |
5618 | * For most existing hypervisors, this will always return true. | |
5619 | */ | |
5620 | static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) | |
5621 | { | |
5622 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5623 | PIN_BASED_EXT_INTR_MASK; | |
5624 | } | |
5625 | ||
77b0f5d6 BD |
5626 | /* |
5627 | * In nested virtualization, check if L1 has set | |
5628 | * VM_EXIT_ACK_INTR_ON_EXIT | |
5629 | */ | |
5630 | static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) | |
5631 | { | |
5632 | return get_vmcs12(vcpu)->vm_exit_controls & | |
5633 | VM_EXIT_ACK_INTR_ON_EXIT; | |
5634 | } | |
5635 | ||
ea8ceb83 JK |
5636 | static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) |
5637 | { | |
5638 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5639 | PIN_BASED_NMI_EXITING; | |
5640 | } | |
5641 | ||
c9a7953f | 5642 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 5643 | { |
47c0152e PB |
5644 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
5645 | CPU_BASED_VIRTUAL_INTR_PENDING); | |
3b86cd99 JK |
5646 | } |
5647 | ||
c9a7953f | 5648 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 5649 | { |
2c82878b | 5650 | if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { |
c9a7953f JK |
5651 | enable_irq_window(vcpu); |
5652 | return; | |
5653 | } | |
3b86cd99 | 5654 | |
47c0152e PB |
5655 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
5656 | CPU_BASED_VIRTUAL_NMI_PENDING); | |
3b86cd99 JK |
5657 | } |
5658 | ||
66fd3f7f | 5659 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 5660 | { |
9c8cba37 | 5661 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
5662 | uint32_t intr; |
5663 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 5664 | |
229456fc | 5665 | trace_kvm_inj_virq(irq); |
2714d1d3 | 5666 | |
fa89a817 | 5667 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 5668 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
5669 | int inc_eip = 0; |
5670 | if (vcpu->arch.interrupt.soft) | |
5671 | inc_eip = vcpu->arch.event_exit_inst_len; | |
5672 | if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) | |
a92601bb | 5673 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
85f455f7 ED |
5674 | return; |
5675 | } | |
66fd3f7f GN |
5676 | intr = irq | INTR_INFO_VALID_MASK; |
5677 | if (vcpu->arch.interrupt.soft) { | |
5678 | intr |= INTR_TYPE_SOFT_INTR; | |
5679 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
5680 | vmx->vcpu.arch.event_exit_inst_len); | |
5681 | } else | |
5682 | intr |= INTR_TYPE_EXT_INTR; | |
5683 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
85f455f7 ED |
5684 | } |
5685 | ||
f08864b4 SY |
5686 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
5687 | { | |
66a5a347 JK |
5688 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5689 | ||
4c4a6f79 PB |
5690 | ++vcpu->stat.nmi_injections; |
5691 | vmx->loaded_vmcs->nmi_known_unmasked = false; | |
3b86cd99 | 5692 | |
7ffd92c5 | 5693 | if (vmx->rmode.vm86_active) { |
71f9833b | 5694 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) |
a92601bb | 5695 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
66a5a347 JK |
5696 | return; |
5697 | } | |
c5a6d5f7 | 5698 | |
f08864b4 SY |
5699 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
5700 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
5701 | } |
5702 | ||
3cfc3092 JK |
5703 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
5704 | { | |
4c4a6f79 PB |
5705 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5706 | bool masked; | |
5707 | ||
5708 | if (vmx->loaded_vmcs->nmi_known_unmasked) | |
9d58b931 | 5709 | return false; |
4c4a6f79 PB |
5710 | masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
5711 | vmx->loaded_vmcs->nmi_known_unmasked = !masked; | |
5712 | return masked; | |
3cfc3092 JK |
5713 | } |
5714 | ||
5715 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
5716 | { | |
5717 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5718 | ||
4c4a6f79 | 5719 | vmx->loaded_vmcs->nmi_known_unmasked = !masked; |
2c82878b PB |
5720 | if (masked) |
5721 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5722 | GUEST_INTR_STATE_NMI); | |
5723 | else | |
5724 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5725 | GUEST_INTR_STATE_NMI); | |
3cfc3092 JK |
5726 | } |
5727 | ||
2505dc9f JK |
5728 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
5729 | { | |
b6b8a145 JK |
5730 | if (to_vmx(vcpu)->nested.nested_run_pending) |
5731 | return 0; | |
ea8ceb83 | 5732 | |
2505dc9f JK |
5733 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
5734 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | |
5735 | | GUEST_INTR_STATE_NMI)); | |
5736 | } | |
5737 | ||
78646121 GN |
5738 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
5739 | { | |
b6b8a145 JK |
5740 | return (!to_vmx(vcpu)->nested.nested_run_pending && |
5741 | vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
c4282df9 GN |
5742 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
5743 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
5744 | } |
5745 | ||
cbc94022 IE |
5746 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
5747 | { | |
5748 | int ret; | |
cbc94022 | 5749 | |
1d8007bd PB |
5750 | ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, |
5751 | PAGE_SIZE * 3); | |
cbc94022 IE |
5752 | if (ret) |
5753 | return ret; | |
bfc6d222 | 5754 | kvm->arch.tss_addr = addr; |
1f755a82 | 5755 | return init_rmode_tss(kvm); |
cbc94022 IE |
5756 | } |
5757 | ||
0ca1b4f4 | 5758 | static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) |
6aa8b732 | 5759 | { |
77ab6db0 | 5760 | switch (vec) { |
77ab6db0 | 5761 | case BP_VECTOR: |
c573cd22 JK |
5762 | /* |
5763 | * Update instruction length as we may reinject the exception | |
5764 | * from user space while in guest debugging mode. | |
5765 | */ | |
5766 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
5767 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 | 5768 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
0ca1b4f4 GN |
5769 | return false; |
5770 | /* fall through */ | |
5771 | case DB_VECTOR: | |
5772 | if (vcpu->guest_debug & | |
5773 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
5774 | return false; | |
d0bfb940 JK |
5775 | /* fall through */ |
5776 | case DE_VECTOR: | |
77ab6db0 JK |
5777 | case OF_VECTOR: |
5778 | case BR_VECTOR: | |
5779 | case UD_VECTOR: | |
5780 | case DF_VECTOR: | |
5781 | case SS_VECTOR: | |
5782 | case GP_VECTOR: | |
5783 | case MF_VECTOR: | |
0ca1b4f4 GN |
5784 | return true; |
5785 | break; | |
77ab6db0 | 5786 | } |
0ca1b4f4 GN |
5787 | return false; |
5788 | } | |
5789 | ||
5790 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
5791 | int vec, u32 err_code) | |
5792 | { | |
5793 | /* | |
5794 | * Instruction with address size override prefix opcode 0x67 | |
5795 | * Cause the #SS fault with 0 error code in VM86 mode. | |
5796 | */ | |
5797 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { | |
5798 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) { | |
5799 | if (vcpu->arch.halt_request) { | |
5800 | vcpu->arch.halt_request = 0; | |
5cb56059 | 5801 | return kvm_vcpu_halt(vcpu); |
0ca1b4f4 GN |
5802 | } |
5803 | return 1; | |
5804 | } | |
5805 | return 0; | |
5806 | } | |
5807 | ||
5808 | /* | |
5809 | * Forward all other exceptions that are valid in real mode. | |
5810 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
5811 | * the required debugging infrastructure rework. | |
5812 | */ | |
5813 | kvm_queue_exception(vcpu, vec); | |
5814 | return 1; | |
6aa8b732 AK |
5815 | } |
5816 | ||
a0861c02 AK |
5817 | /* |
5818 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
5819 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
5820 | * We pass a fake environment to the machine check handler because we want | |
5821 | * the guest to be always treated like user space, no matter what context | |
5822 | * it used internally. | |
5823 | */ | |
5824 | static void kvm_machine_check(void) | |
5825 | { | |
5826 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
5827 | struct pt_regs regs = { | |
5828 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
5829 | .flags = X86_EFLAGS_IF, | |
5830 | }; | |
5831 | ||
5832 | do_machine_check(®s, 0); | |
5833 | #endif | |
5834 | } | |
5835 | ||
851ba692 | 5836 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
5837 | { |
5838 | /* already handled by vcpu_run */ | |
5839 | return 1; | |
5840 | } | |
5841 | ||
851ba692 | 5842 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 5843 | { |
1155f76a | 5844 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 5845 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 5846 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 5847 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
5848 | u32 vect_info; |
5849 | enum emulation_result er; | |
5850 | ||
1155f76a | 5851 | vect_info = vmx->idt_vectoring_info; |
88786475 | 5852 | intr_info = vmx->exit_intr_info; |
6aa8b732 | 5853 | |
a0861c02 | 5854 | if (is_machine_check(intr_info)) |
851ba692 | 5855 | return handle_machine_check(vcpu); |
a0861c02 | 5856 | |
ef85b673 | 5857 | if (is_nmi(intr_info)) |
1b6269db | 5858 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc | 5859 | |
7aa81cc0 | 5860 | if (is_invalid_opcode(intr_info)) { |
ae1f5767 JK |
5861 | if (is_guest_mode(vcpu)) { |
5862 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5863 | return 1; | |
5864 | } | |
51d8b661 | 5865 | er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 5866 | if (er != EMULATE_DONE) |
7ee5d940 | 5867 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
5868 | return 1; |
5869 | } | |
5870 | ||
6aa8b732 | 5871 | error_code = 0; |
2e11384c | 5872 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 | 5873 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
bf4ca23e XG |
5874 | |
5875 | /* | |
5876 | * The #PF with PFEC.RSVD = 1 indicates the guest is accessing | |
5877 | * MMIO, it is better to report an internal error. | |
5878 | * See the comments in vmx_handle_exit. | |
5879 | */ | |
5880 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
5881 | !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { | |
5882 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
5883 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
80f0e95d | 5884 | vcpu->run->internal.ndata = 3; |
bf4ca23e XG |
5885 | vcpu->run->internal.data[0] = vect_info; |
5886 | vcpu->run->internal.data[1] = intr_info; | |
80f0e95d | 5887 | vcpu->run->internal.data[2] = error_code; |
bf4ca23e XG |
5888 | return 0; |
5889 | } | |
5890 | ||
6aa8b732 AK |
5891 | if (is_page_fault(intr_info)) { |
5892 | cr2 = vmcs_readl(EXIT_QUALIFICATION); | |
1261bfa3 WL |
5893 | /* EPT won't cause page fault directly */ |
5894 | WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); | |
5895 | return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0, | |
5896 | true); | |
6aa8b732 AK |
5897 | } |
5898 | ||
d0bfb940 | 5899 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
0ca1b4f4 GN |
5900 | |
5901 | if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) | |
5902 | return handle_rmode_exception(vcpu, ex_no, error_code); | |
5903 | ||
42dbaa5a | 5904 | switch (ex_no) { |
54a20552 EN |
5905 | case AC_VECTOR: |
5906 | kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); | |
5907 | return 1; | |
42dbaa5a JK |
5908 | case DB_VECTOR: |
5909 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
5910 | if (!(vcpu->guest_debug & | |
5911 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
8246bf52 | 5912 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 5913 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
fd2a445a HD |
5914 | if (!(dr6 & ~DR6_RESERVED)) /* icebp */ |
5915 | skip_emulated_instruction(vcpu); | |
5916 | ||
42dbaa5a JK |
5917 | kvm_queue_exception(vcpu, DB_VECTOR); |
5918 | return 1; | |
5919 | } | |
5920 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
5921 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
5922 | /* fall through */ | |
5923 | case BP_VECTOR: | |
c573cd22 JK |
5924 | /* |
5925 | * Update instruction length as we may reinject #BP from | |
5926 | * user space while in guest debugging mode. Reading it for | |
5927 | * #DB as well causes no harm, it is not used in that case. | |
5928 | */ | |
5929 | vmx->vcpu.arch.event_exit_inst_len = | |
5930 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 5931 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 5932 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
5933 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
5934 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
5935 | break; |
5936 | default: | |
d0bfb940 JK |
5937 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
5938 | kvm_run->ex.exception = ex_no; | |
5939 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 5940 | break; |
6aa8b732 | 5941 | } |
6aa8b732 AK |
5942 | return 0; |
5943 | } | |
5944 | ||
851ba692 | 5945 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 5946 | { |
1165f5fe | 5947 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
5948 | return 1; |
5949 | } | |
5950 | ||
851ba692 | 5951 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 5952 | { |
851ba692 | 5953 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 5954 | vcpu->mmio_needed = 0; |
988ad74f AK |
5955 | return 0; |
5956 | } | |
6aa8b732 | 5957 | |
851ba692 | 5958 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 5959 | { |
bfdaab09 | 5960 | unsigned long exit_qualification; |
6affcbed | 5961 | int size, in, string, ret; |
039576c0 | 5962 | unsigned port; |
6aa8b732 | 5963 | |
bfdaab09 | 5964 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 5965 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 5966 | in = (exit_qualification & 8) != 0; |
e70669ab | 5967 | |
cf8f70bf | 5968 | ++vcpu->stat.io_exits; |
e70669ab | 5969 | |
cf8f70bf | 5970 | if (string || in) |
51d8b661 | 5971 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 5972 | |
cf8f70bf GN |
5973 | port = exit_qualification >> 16; |
5974 | size = (exit_qualification & 7) + 1; | |
cf8f70bf | 5975 | |
6affcbed KH |
5976 | ret = kvm_skip_emulated_instruction(vcpu); |
5977 | ||
5978 | /* | |
5979 | * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered | |
5980 | * KVM_EXIT_DEBUG here. | |
5981 | */ | |
5982 | return kvm_fast_pio_out(vcpu, size, port) && ret; | |
6aa8b732 AK |
5983 | } |
5984 | ||
102d8325 IM |
5985 | static void |
5986 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
5987 | { | |
5988 | /* | |
5989 | * Patch in the VMCALL instruction: | |
5990 | */ | |
5991 | hypercall[0] = 0x0f; | |
5992 | hypercall[1] = 0x01; | |
5993 | hypercall[2] = 0xc1; | |
102d8325 IM |
5994 | } |
5995 | ||
0fa06071 | 5996 | /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ |
eeadf9e7 NHE |
5997 | static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) |
5998 | { | |
eeadf9e7 | 5999 | if (is_guest_mode(vcpu)) { |
1a0d74e6 JK |
6000 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
6001 | unsigned long orig_val = val; | |
6002 | ||
eeadf9e7 NHE |
6003 | /* |
6004 | * We get here when L2 changed cr0 in a way that did not change | |
6005 | * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), | |
1a0d74e6 JK |
6006 | * but did change L0 shadowed bits. So we first calculate the |
6007 | * effective cr0 value that L1 would like to write into the | |
6008 | * hardware. It consists of the L2-owned bits from the new | |
6009 | * value combined with the L1-owned bits from L1's guest_cr0. | |
eeadf9e7 | 6010 | */ |
1a0d74e6 JK |
6011 | val = (val & ~vmcs12->cr0_guest_host_mask) | |
6012 | (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); | |
6013 | ||
3899152c | 6014 | if (!nested_guest_cr0_valid(vcpu, val)) |
eeadf9e7 | 6015 | return 1; |
1a0d74e6 JK |
6016 | |
6017 | if (kvm_set_cr0(vcpu, val)) | |
6018 | return 1; | |
6019 | vmcs_writel(CR0_READ_SHADOW, orig_val); | |
eeadf9e7 | 6020 | return 0; |
1a0d74e6 JK |
6021 | } else { |
6022 | if (to_vmx(vcpu)->nested.vmxon && | |
3899152c | 6023 | !nested_host_cr0_valid(vcpu, val)) |
1a0d74e6 | 6024 | return 1; |
3899152c | 6025 | |
eeadf9e7 | 6026 | return kvm_set_cr0(vcpu, val); |
1a0d74e6 | 6027 | } |
eeadf9e7 NHE |
6028 | } |
6029 | ||
6030 | static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) | |
6031 | { | |
6032 | if (is_guest_mode(vcpu)) { | |
1a0d74e6 JK |
6033 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
6034 | unsigned long orig_val = val; | |
6035 | ||
6036 | /* analogously to handle_set_cr0 */ | |
6037 | val = (val & ~vmcs12->cr4_guest_host_mask) | | |
6038 | (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); | |
6039 | if (kvm_set_cr4(vcpu, val)) | |
eeadf9e7 | 6040 | return 1; |
1a0d74e6 | 6041 | vmcs_writel(CR4_READ_SHADOW, orig_val); |
eeadf9e7 NHE |
6042 | return 0; |
6043 | } else | |
6044 | return kvm_set_cr4(vcpu, val); | |
6045 | } | |
6046 | ||
851ba692 | 6047 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6048 | { |
229456fc | 6049 | unsigned long exit_qualification, val; |
6aa8b732 AK |
6050 | int cr; |
6051 | int reg; | |
49a9b07e | 6052 | int err; |
6affcbed | 6053 | int ret; |
6aa8b732 | 6054 | |
bfdaab09 | 6055 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
6056 | cr = exit_qualification & 15; |
6057 | reg = (exit_qualification >> 8) & 15; | |
6058 | switch ((exit_qualification >> 4) & 3) { | |
6059 | case 0: /* mov to cr */ | |
1e32c079 | 6060 | val = kvm_register_readl(vcpu, reg); |
229456fc | 6061 | trace_kvm_cr_write(cr, val); |
6aa8b732 AK |
6062 | switch (cr) { |
6063 | case 0: | |
eeadf9e7 | 6064 | err = handle_set_cr0(vcpu, val); |
6affcbed | 6065 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 6066 | case 3: |
2390218b | 6067 | err = kvm_set_cr3(vcpu, val); |
6affcbed | 6068 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 6069 | case 4: |
eeadf9e7 | 6070 | err = handle_set_cr4(vcpu, val); |
6affcbed | 6071 | return kvm_complete_insn_gp(vcpu, err); |
0a5fff19 GN |
6072 | case 8: { |
6073 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
1e32c079 | 6074 | u8 cr8 = (u8)val; |
eea1cff9 | 6075 | err = kvm_set_cr8(vcpu, cr8); |
6affcbed | 6076 | ret = kvm_complete_insn_gp(vcpu, err); |
35754c98 | 6077 | if (lapic_in_kernel(vcpu)) |
6affcbed | 6078 | return ret; |
0a5fff19 | 6079 | if (cr8_prev <= cr8) |
6affcbed KH |
6080 | return ret; |
6081 | /* | |
6082 | * TODO: we might be squashing a | |
6083 | * KVM_GUESTDBG_SINGLESTEP-triggered | |
6084 | * KVM_EXIT_DEBUG here. | |
6085 | */ | |
851ba692 | 6086 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
6087 | return 0; |
6088 | } | |
4b8073e4 | 6089 | } |
6aa8b732 | 6090 | break; |
25c4c276 | 6091 | case 2: /* clts */ |
bd7e5b08 PB |
6092 | WARN_ONCE(1, "Guest should always own CR0.TS"); |
6093 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); | |
4d4ec087 | 6094 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
6affcbed | 6095 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6096 | case 1: /*mov from cr*/ |
6097 | switch (cr) { | |
6098 | case 3: | |
9f8fe504 AK |
6099 | val = kvm_read_cr3(vcpu); |
6100 | kvm_register_write(vcpu, reg, val); | |
6101 | trace_kvm_cr_read(cr, val); | |
6affcbed | 6102 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 | 6103 | case 8: |
229456fc MT |
6104 | val = kvm_get_cr8(vcpu); |
6105 | kvm_register_write(vcpu, reg, val); | |
6106 | trace_kvm_cr_read(cr, val); | |
6affcbed | 6107 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6108 | } |
6109 | break; | |
6110 | case 3: /* lmsw */ | |
a1f83a74 | 6111 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 6112 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 6113 | kvm_lmsw(vcpu, val); |
6aa8b732 | 6114 | |
6affcbed | 6115 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6116 | default: |
6117 | break; | |
6118 | } | |
851ba692 | 6119 | vcpu->run->exit_reason = 0; |
a737f256 | 6120 | vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
6121 | (int)(exit_qualification >> 4) & 3, cr); |
6122 | return 0; | |
6123 | } | |
6124 | ||
851ba692 | 6125 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6126 | { |
bfdaab09 | 6127 | unsigned long exit_qualification; |
16f8a6f9 NA |
6128 | int dr, dr7, reg; |
6129 | ||
6130 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6131 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; | |
6132 | ||
6133 | /* First, if DR does not exist, trigger UD */ | |
6134 | if (!kvm_require_dr(vcpu, dr)) | |
6135 | return 1; | |
6aa8b732 | 6136 | |
f2483415 | 6137 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
6138 | if (!kvm_require_cpl(vcpu, 0)) |
6139 | return 1; | |
16f8a6f9 NA |
6140 | dr7 = vmcs_readl(GUEST_DR7); |
6141 | if (dr7 & DR7_GD) { | |
42dbaa5a JK |
6142 | /* |
6143 | * As the vm-exit takes precedence over the debug trap, we | |
6144 | * need to emulate the latter, either for the host or the | |
6145 | * guest debugging itself. | |
6146 | */ | |
6147 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 | 6148 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
16f8a6f9 | 6149 | vcpu->run->debug.arch.dr7 = dr7; |
82b32774 | 6150 | vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
851ba692 AK |
6151 | vcpu->run->debug.arch.exception = DB_VECTOR; |
6152 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
6153 | return 0; |
6154 | } else { | |
7305eb5d | 6155 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 6156 | vcpu->arch.dr6 |= DR6_BD | DR6_RTM; |
42dbaa5a JK |
6157 | kvm_queue_exception(vcpu, DB_VECTOR); |
6158 | return 1; | |
6159 | } | |
6160 | } | |
6161 | ||
81908bf4 | 6162 | if (vcpu->guest_debug == 0) { |
8f22372f PB |
6163 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6164 | CPU_BASED_MOV_DR_EXITING); | |
81908bf4 PB |
6165 | |
6166 | /* | |
6167 | * No more DR vmexits; force a reload of the debug registers | |
6168 | * and reenter on this instruction. The next vmexit will | |
6169 | * retrieve the full state of the debug registers. | |
6170 | */ | |
6171 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
6172 | return 1; | |
6173 | } | |
6174 | ||
42dbaa5a JK |
6175 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); |
6176 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 | 6177 | unsigned long val; |
4c4d563b JK |
6178 | |
6179 | if (kvm_get_dr(vcpu, dr, &val)) | |
6180 | return 1; | |
6181 | kvm_register_write(vcpu, reg, val); | |
020df079 | 6182 | } else |
5777392e | 6183 | if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) |
4c4d563b JK |
6184 | return 1; |
6185 | ||
6affcbed | 6186 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6187 | } |
6188 | ||
73aaf249 JK |
6189 | static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) |
6190 | { | |
6191 | return vcpu->arch.dr6; | |
6192 | } | |
6193 | ||
6194 | static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) | |
6195 | { | |
6196 | } | |
6197 | ||
81908bf4 PB |
6198 | static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
6199 | { | |
81908bf4 PB |
6200 | get_debugreg(vcpu->arch.db[0], 0); |
6201 | get_debugreg(vcpu->arch.db[1], 1); | |
6202 | get_debugreg(vcpu->arch.db[2], 2); | |
6203 | get_debugreg(vcpu->arch.db[3], 3); | |
6204 | get_debugreg(vcpu->arch.dr6, 6); | |
6205 | vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); | |
6206 | ||
6207 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
8f22372f | 6208 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING); |
81908bf4 PB |
6209 | } |
6210 | ||
020df079 GN |
6211 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
6212 | { | |
6213 | vmcs_writel(GUEST_DR7, val); | |
6214 | } | |
6215 | ||
851ba692 | 6216 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 6217 | { |
6a908b62 | 6218 | return kvm_emulate_cpuid(vcpu); |
6aa8b732 AK |
6219 | } |
6220 | ||
851ba692 | 6221 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6222 | { |
ad312c7c | 6223 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
609e36d3 | 6224 | struct msr_data msr_info; |
6aa8b732 | 6225 | |
609e36d3 PB |
6226 | msr_info.index = ecx; |
6227 | msr_info.host_initiated = false; | |
6228 | if (vmx_get_msr(vcpu, &msr_info)) { | |
59200273 | 6229 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 6230 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6231 | return 1; |
6232 | } | |
6233 | ||
609e36d3 | 6234 | trace_kvm_msr_read(ecx, msr_info.data); |
2714d1d3 | 6235 | |
6aa8b732 | 6236 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
609e36d3 PB |
6237 | vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u; |
6238 | vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u; | |
6affcbed | 6239 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6240 | } |
6241 | ||
851ba692 | 6242 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6243 | { |
8fe8ab46 | 6244 | struct msr_data msr; |
ad312c7c ZX |
6245 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6246 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
6247 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 6248 | |
8fe8ab46 WA |
6249 | msr.data = data; |
6250 | msr.index = ecx; | |
6251 | msr.host_initiated = false; | |
854e8bb1 | 6252 | if (kvm_set_msr(vcpu, &msr) != 0) { |
59200273 | 6253 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 6254 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6255 | return 1; |
6256 | } | |
6257 | ||
59200273 | 6258 | trace_kvm_msr_write(ecx, data); |
6affcbed | 6259 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6260 | } |
6261 | ||
851ba692 | 6262 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 6263 | { |
eb90f341 | 6264 | kvm_apic_update_ppr(vcpu); |
6e5d865c YS |
6265 | return 1; |
6266 | } | |
6267 | ||
851ba692 | 6268 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 6269 | { |
47c0152e PB |
6270 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6271 | CPU_BASED_VIRTUAL_INTR_PENDING); | |
2714d1d3 | 6272 | |
3842d135 AK |
6273 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6274 | ||
a26bf12a | 6275 | ++vcpu->stat.irq_window_exits; |
6aa8b732 AK |
6276 | return 1; |
6277 | } | |
6278 | ||
851ba692 | 6279 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 | 6280 | { |
d3bef15f | 6281 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
6282 | } |
6283 | ||
851ba692 | 6284 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 6285 | { |
0d9c055e | 6286 | return kvm_emulate_hypercall(vcpu); |
c21415e8 IM |
6287 | } |
6288 | ||
ec25d5e6 GN |
6289 | static int handle_invd(struct kvm_vcpu *vcpu) |
6290 | { | |
51d8b661 | 6291 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
6292 | } |
6293 | ||
851ba692 | 6294 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 6295 | { |
f9c617f6 | 6296 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
6297 | |
6298 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
6affcbed | 6299 | return kvm_skip_emulated_instruction(vcpu); |
a7052897 MT |
6300 | } |
6301 | ||
fee84b07 AK |
6302 | static int handle_rdpmc(struct kvm_vcpu *vcpu) |
6303 | { | |
6304 | int err; | |
6305 | ||
6306 | err = kvm_rdpmc(vcpu); | |
6affcbed | 6307 | return kvm_complete_insn_gp(vcpu, err); |
fee84b07 AK |
6308 | } |
6309 | ||
851ba692 | 6310 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 | 6311 | { |
6affcbed | 6312 | return kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
6313 | } |
6314 | ||
2acf923e DC |
6315 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
6316 | { | |
6317 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
6318 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6319 | ||
6320 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
6affcbed | 6321 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e DC |
6322 | return 1; |
6323 | } | |
6324 | ||
f53cd63c WL |
6325 | static int handle_xsaves(struct kvm_vcpu *vcpu) |
6326 | { | |
6affcbed | 6327 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6328 | WARN(1, "this should never happen\n"); |
6329 | return 1; | |
6330 | } | |
6331 | ||
6332 | static int handle_xrstors(struct kvm_vcpu *vcpu) | |
6333 | { | |
6affcbed | 6334 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6335 | WARN(1, "this should never happen\n"); |
6336 | return 1; | |
6337 | } | |
6338 | ||
851ba692 | 6339 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 6340 | { |
58fbbf26 KT |
6341 | if (likely(fasteoi)) { |
6342 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6343 | int access_type, offset; | |
6344 | ||
6345 | access_type = exit_qualification & APIC_ACCESS_TYPE; | |
6346 | offset = exit_qualification & APIC_ACCESS_OFFSET; | |
6347 | /* | |
6348 | * Sane guest uses MOV to write EOI, with written value | |
6349 | * not cared. So make a short-circuit here by avoiding | |
6350 | * heavy instruction emulation. | |
6351 | */ | |
6352 | if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && | |
6353 | (offset == APIC_EOI)) { | |
6354 | kvm_lapic_set_eoi(vcpu); | |
6affcbed | 6355 | return kvm_skip_emulated_instruction(vcpu); |
58fbbf26 KT |
6356 | } |
6357 | } | |
51d8b661 | 6358 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
6359 | } |
6360 | ||
c7c9c56c YZ |
6361 | static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) |
6362 | { | |
6363 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6364 | int vector = exit_qualification & 0xff; | |
6365 | ||
6366 | /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ | |
6367 | kvm_apic_set_eoi_accelerated(vcpu, vector); | |
6368 | return 1; | |
6369 | } | |
6370 | ||
83d4c286 YZ |
6371 | static int handle_apic_write(struct kvm_vcpu *vcpu) |
6372 | { | |
6373 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6374 | u32 offset = exit_qualification & 0xfff; | |
6375 | ||
6376 | /* APIC-write VM exit is trap-like and thus no need to adjust IP */ | |
6377 | kvm_apic_write_nodecode(vcpu, offset); | |
6378 | return 1; | |
6379 | } | |
6380 | ||
851ba692 | 6381 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 6382 | { |
60637aac | 6383 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 6384 | unsigned long exit_qualification; |
e269fb21 JK |
6385 | bool has_error_code = false; |
6386 | u32 error_code = 0; | |
37817f29 | 6387 | u16 tss_selector; |
7f3d35fd | 6388 | int reason, type, idt_v, idt_index; |
64a7ec06 GN |
6389 | |
6390 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
7f3d35fd | 6391 | idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); |
64a7ec06 | 6392 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); |
37817f29 IE |
6393 | |
6394 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6395 | ||
6396 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
6397 | if (reason == TASK_SWITCH_GATE && idt_v) { |
6398 | switch (type) { | |
6399 | case INTR_TYPE_NMI_INTR: | |
6400 | vcpu->arch.nmi_injected = false; | |
654f06fc | 6401 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
6402 | break; |
6403 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 6404 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
6405 | kvm_clear_interrupt_queue(vcpu); |
6406 | break; | |
6407 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
6408 | if (vmx->idt_vectoring_info & |
6409 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
6410 | has_error_code = true; | |
6411 | error_code = | |
6412 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
6413 | } | |
6414 | /* fall through */ | |
64a7ec06 GN |
6415 | case INTR_TYPE_SOFT_EXCEPTION: |
6416 | kvm_clear_exception_queue(vcpu); | |
6417 | break; | |
6418 | default: | |
6419 | break; | |
6420 | } | |
60637aac | 6421 | } |
37817f29 IE |
6422 | tss_selector = exit_qualification; |
6423 | ||
64a7ec06 GN |
6424 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
6425 | type != INTR_TYPE_EXT_INTR && | |
6426 | type != INTR_TYPE_NMI_INTR)) | |
6427 | skip_emulated_instruction(vcpu); | |
6428 | ||
7f3d35fd KW |
6429 | if (kvm_task_switch(vcpu, tss_selector, |
6430 | type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason, | |
6431 | has_error_code, error_code) == EMULATE_FAIL) { | |
acb54517 GN |
6432 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
6433 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6434 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 6435 | return 0; |
acb54517 | 6436 | } |
42dbaa5a | 6437 | |
42dbaa5a JK |
6438 | /* |
6439 | * TODO: What about debug traps on tss switch? | |
6440 | * Are we supposed to inject them and update dr6? | |
6441 | */ | |
6442 | ||
6443 | return 1; | |
37817f29 IE |
6444 | } |
6445 | ||
851ba692 | 6446 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 6447 | { |
f9c617f6 | 6448 | unsigned long exit_qualification; |
1439442c | 6449 | gpa_t gpa; |
eebed243 | 6450 | u64 error_code; |
1439442c | 6451 | |
f9c617f6 | 6452 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c | 6453 | |
0be9c7a8 GN |
6454 | /* |
6455 | * EPT violation happened while executing iret from NMI, | |
6456 | * "blocked by NMI" bit has to be set before next VM entry. | |
6457 | * There are errata that may cause this bit to not be set: | |
6458 | * AAK134, BY25. | |
6459 | */ | |
bcd1c294 | 6460 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && |
bcd1c294 | 6461 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
0be9c7a8 GN |
6462 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); |
6463 | ||
1439442c | 6464 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
229456fc | 6465 | trace_kvm_page_fault(gpa, exit_qualification); |
4f5982a5 | 6466 | |
27959a44 | 6467 | /* Is it a read fault? */ |
ab22a473 | 6468 | error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) |
27959a44 JS |
6469 | ? PFERR_USER_MASK : 0; |
6470 | /* Is it a write fault? */ | |
ab22a473 | 6471 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) |
27959a44 JS |
6472 | ? PFERR_WRITE_MASK : 0; |
6473 | /* Is it a fetch fault? */ | |
ab22a473 | 6474 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) |
27959a44 JS |
6475 | ? PFERR_FETCH_MASK : 0; |
6476 | /* ept page table entry is present? */ | |
6477 | error_code |= (exit_qualification & | |
6478 | (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | | |
6479 | EPT_VIOLATION_EXECUTABLE)) | |
6480 | ? PFERR_PRESENT_MASK : 0; | |
4f5982a5 | 6481 | |
eebed243 PB |
6482 | error_code |= (exit_qualification & 0x100) != 0 ? |
6483 | PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; | |
25d92081 | 6484 | |
25d92081 | 6485 | vcpu->arch.exit_qualification = exit_qualification; |
4f5982a5 | 6486 | return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); |
1439442c SY |
6487 | } |
6488 | ||
851ba692 | 6489 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 | 6490 | { |
f735d4af | 6491 | int ret; |
68f89400 MT |
6492 | gpa_t gpa; |
6493 | ||
9034e6e8 PB |
6494 | /* |
6495 | * A nested guest cannot optimize MMIO vmexits, because we have an | |
6496 | * nGPA here instead of the required GPA. | |
6497 | */ | |
68f89400 | 6498 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
9034e6e8 PB |
6499 | if (!is_guest_mode(vcpu) && |
6500 | !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { | |
931c33b1 | 6501 | trace_kvm_fast_mmio(gpa); |
6affcbed | 6502 | return kvm_skip_emulated_instruction(vcpu); |
68c3b4d1 | 6503 | } |
68f89400 | 6504 | |
e08d26f0 PB |
6505 | ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); |
6506 | if (ret >= 0) | |
6507 | return ret; | |
ce88decf XG |
6508 | |
6509 | /* It is the real ept misconfig */ | |
f735d4af | 6510 | WARN_ON(1); |
68f89400 | 6511 | |
851ba692 AK |
6512 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
6513 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
6514 | |
6515 | return 0; | |
6516 | } | |
6517 | ||
851ba692 | 6518 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 | 6519 | { |
47c0152e PB |
6520 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6521 | CPU_BASED_VIRTUAL_NMI_PENDING); | |
f08864b4 | 6522 | ++vcpu->stat.nmi_window_exits; |
3842d135 | 6523 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
6524 | |
6525 | return 1; | |
6526 | } | |
6527 | ||
80ced186 | 6528 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 6529 | { |
8b3079a5 AK |
6530 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6531 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 6532 | int ret = 1; |
49e9d557 AK |
6533 | u32 cpu_exec_ctrl; |
6534 | bool intr_window_requested; | |
b8405c18 | 6535 | unsigned count = 130; |
49e9d557 AK |
6536 | |
6537 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
6538 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 | 6539 | |
98eb2f8b | 6540 | while (vmx->emulation_required && count-- != 0) { |
bdea48e3 | 6541 | if (intr_window_requested && vmx_interrupt_allowed(vcpu)) |
49e9d557 AK |
6542 | return handle_interrupt_window(&vmx->vcpu); |
6543 | ||
72875d8a | 6544 | if (kvm_test_request(KVM_REQ_EVENT, vcpu)) |
de87dcdd AK |
6545 | return 1; |
6546 | ||
991eebf9 | 6547 | err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE); |
ea953ef0 | 6548 | |
ac0a48c3 | 6549 | if (err == EMULATE_USER_EXIT) { |
94452b9e | 6550 | ++vcpu->stat.mmio_exits; |
80ced186 MG |
6551 | ret = 0; |
6552 | goto out; | |
6553 | } | |
1d5a4d9b | 6554 | |
de5f70e0 AK |
6555 | if (err != EMULATE_DONE) { |
6556 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6557 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6558 | vcpu->run->internal.ndata = 0; | |
6d77dbfc | 6559 | return 0; |
de5f70e0 | 6560 | } |
ea953ef0 | 6561 | |
8d76c49e GN |
6562 | if (vcpu->arch.halt_request) { |
6563 | vcpu->arch.halt_request = 0; | |
5cb56059 | 6564 | ret = kvm_vcpu_halt(vcpu); |
8d76c49e GN |
6565 | goto out; |
6566 | } | |
6567 | ||
ea953ef0 | 6568 | if (signal_pending(current)) |
80ced186 | 6569 | goto out; |
ea953ef0 MG |
6570 | if (need_resched()) |
6571 | schedule(); | |
6572 | } | |
6573 | ||
80ced186 MG |
6574 | out: |
6575 | return ret; | |
ea953ef0 MG |
6576 | } |
6577 | ||
b4a2d31d RK |
6578 | static int __grow_ple_window(int val) |
6579 | { | |
6580 | if (ple_window_grow < 1) | |
6581 | return ple_window; | |
6582 | ||
6583 | val = min(val, ple_window_actual_max); | |
6584 | ||
6585 | if (ple_window_grow < ple_window) | |
6586 | val *= ple_window_grow; | |
6587 | else | |
6588 | val += ple_window_grow; | |
6589 | ||
6590 | return val; | |
6591 | } | |
6592 | ||
6593 | static int __shrink_ple_window(int val, int modifier, int minimum) | |
6594 | { | |
6595 | if (modifier < 1) | |
6596 | return ple_window; | |
6597 | ||
6598 | if (modifier < ple_window) | |
6599 | val /= modifier; | |
6600 | else | |
6601 | val -= modifier; | |
6602 | ||
6603 | return max(val, minimum); | |
6604 | } | |
6605 | ||
6606 | static void grow_ple_window(struct kvm_vcpu *vcpu) | |
6607 | { | |
6608 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6609 | int old = vmx->ple_window; | |
6610 | ||
6611 | vmx->ple_window = __grow_ple_window(old); | |
6612 | ||
6613 | if (vmx->ple_window != old) | |
6614 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6615 | |
6616 | trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6617 | } |
6618 | ||
6619 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
6620 | { | |
6621 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6622 | int old = vmx->ple_window; | |
6623 | ||
6624 | vmx->ple_window = __shrink_ple_window(old, | |
6625 | ple_window_shrink, ple_window); | |
6626 | ||
6627 | if (vmx->ple_window != old) | |
6628 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6629 | |
6630 | trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6631 | } |
6632 | ||
6633 | /* | |
6634 | * ple_window_actual_max is computed to be one grow_ple_window() below | |
6635 | * ple_window_max. (See __grow_ple_window for the reason.) | |
6636 | * This prevents overflows, because ple_window_max is int. | |
6637 | * ple_window_max effectively rounded down to a multiple of ple_window_grow in | |
6638 | * this process. | |
6639 | * ple_window_max is also prevented from setting vmx->ple_window < ple_window. | |
6640 | */ | |
6641 | static void update_ple_window_actual_max(void) | |
6642 | { | |
6643 | ple_window_actual_max = | |
6644 | __shrink_ple_window(max(ple_window_max, ple_window), | |
6645 | ple_window_grow, INT_MIN); | |
6646 | } | |
6647 | ||
bf9f6ac8 FW |
6648 | /* |
6649 | * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. | |
6650 | */ | |
6651 | static void wakeup_handler(void) | |
6652 | { | |
6653 | struct kvm_vcpu *vcpu; | |
6654 | int cpu = smp_processor_id(); | |
6655 | ||
6656 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6657 | list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), | |
6658 | blocked_vcpu_list) { | |
6659 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
6660 | ||
6661 | if (pi_test_on(pi_desc) == 1) | |
6662 | kvm_vcpu_kick(vcpu); | |
6663 | } | |
6664 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6665 | } | |
6666 | ||
f160c7b7 JS |
6667 | void vmx_enable_tdp(void) |
6668 | { | |
6669 | kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, | |
6670 | enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, | |
6671 | enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, | |
6672 | 0ull, VMX_EPT_EXECUTABLE_MASK, | |
6673 | cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, | |
d0ec49d4 | 6674 | VMX_EPT_RWX_MASK, 0ull); |
f160c7b7 JS |
6675 | |
6676 | ept_set_mmio_spte_mask(); | |
6677 | kvm_enable_tdp(); | |
6678 | } | |
6679 | ||
f2c7648d TC |
6680 | static __init int hardware_setup(void) |
6681 | { | |
34a1cd60 TC |
6682 | int r = -ENOMEM, i, msr; |
6683 | ||
6684 | rdmsrl_safe(MSR_EFER, &host_efer); | |
6685 | ||
6686 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) | |
6687 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
6688 | ||
23611332 RK |
6689 | for (i = 0; i < VMX_BITMAP_NR; i++) { |
6690 | vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6691 | if (!vmx_bitmap[i]) | |
6692 | goto out; | |
6693 | } | |
34a1cd60 TC |
6694 | |
6695 | vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL); | |
34a1cd60 TC |
6696 | memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); |
6697 | memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); | |
6698 | ||
6699 | /* | |
6700 | * Allow direct access to the PC debug port (it is often used for I/O | |
6701 | * delays, but the vmexits simply slow things down). | |
6702 | */ | |
6703 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); | |
6704 | clear_bit(0x80, vmx_io_bitmap_a); | |
6705 | ||
6706 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); | |
6707 | ||
6708 | memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE); | |
6709 | memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE); | |
6710 | ||
34a1cd60 TC |
6711 | if (setup_vmcs_config(&vmcs_config) < 0) { |
6712 | r = -EIO; | |
23611332 | 6713 | goto out; |
baa03522 | 6714 | } |
f2c7648d TC |
6715 | |
6716 | if (boot_cpu_has(X86_FEATURE_NX)) | |
6717 | kvm_enable_efer_bits(EFER_NX); | |
6718 | ||
08d839c4 WL |
6719 | if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || |
6720 | !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) | |
f2c7648d | 6721 | enable_vpid = 0; |
08d839c4 | 6722 | |
f2c7648d TC |
6723 | if (!cpu_has_vmx_shadow_vmcs()) |
6724 | enable_shadow_vmcs = 0; | |
6725 | if (enable_shadow_vmcs) | |
6726 | init_vmcs_shadow_fields(); | |
6727 | ||
6728 | if (!cpu_has_vmx_ept() || | |
42aa53b4 | 6729 | !cpu_has_vmx_ept_4levels() || |
f5f51586 DH |
6730 | !cpu_has_vmx_ept_mt_wb() || |
6731 | !cpu_has_vmx_invept_global()) { | |
f2c7648d TC |
6732 | enable_ept = 0; |
6733 | enable_unrestricted_guest = 0; | |
6734 | enable_ept_ad_bits = 0; | |
6735 | } | |
6736 | ||
fce6ac4c | 6737 | if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) |
f2c7648d TC |
6738 | enable_ept_ad_bits = 0; |
6739 | ||
6740 | if (!cpu_has_vmx_unrestricted_guest()) | |
6741 | enable_unrestricted_guest = 0; | |
6742 | ||
ad15a296 | 6743 | if (!cpu_has_vmx_flexpriority()) |
f2c7648d TC |
6744 | flexpriority_enabled = 0; |
6745 | ||
ad15a296 PB |
6746 | /* |
6747 | * set_apic_access_page_addr() is used to reload apic access | |
6748 | * page upon invalidation. No need to do anything if not | |
6749 | * using the APIC_ACCESS_ADDR VMCS field. | |
6750 | */ | |
6751 | if (!flexpriority_enabled) | |
f2c7648d | 6752 | kvm_x86_ops->set_apic_access_page_addr = NULL; |
f2c7648d TC |
6753 | |
6754 | if (!cpu_has_vmx_tpr_shadow()) | |
6755 | kvm_x86_ops->update_cr8_intercept = NULL; | |
6756 | ||
6757 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) | |
6758 | kvm_disable_largepages(); | |
6759 | ||
0f107682 | 6760 | if (!cpu_has_vmx_ple()) { |
f2c7648d | 6761 | ple_gap = 0; |
0f107682 WL |
6762 | ple_window = 0; |
6763 | ple_window_grow = 0; | |
6764 | ple_window_max = 0; | |
6765 | ple_window_shrink = 0; | |
6766 | } | |
f2c7648d | 6767 | |
76dfafd5 | 6768 | if (!cpu_has_vmx_apicv()) { |
f2c7648d | 6769 | enable_apicv = 0; |
76dfafd5 PB |
6770 | kvm_x86_ops->sync_pir_to_irr = NULL; |
6771 | } | |
f2c7648d | 6772 | |
64903d61 HZ |
6773 | if (cpu_has_vmx_tsc_scaling()) { |
6774 | kvm_has_tsc_control = true; | |
6775 | kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; | |
6776 | kvm_tsc_scaling_ratio_frac_bits = 48; | |
6777 | } | |
6778 | ||
baa03522 TC |
6779 | vmx_disable_intercept_for_msr(MSR_FS_BASE, false); |
6780 | vmx_disable_intercept_for_msr(MSR_GS_BASE, false); | |
6781 | vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); | |
6782 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); | |
6783 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); | |
6784 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); | |
baa03522 | 6785 | |
c63e4563 | 6786 | memcpy(vmx_msr_bitmap_legacy_x2apic_apicv, |
baa03522 | 6787 | vmx_msr_bitmap_legacy, PAGE_SIZE); |
c63e4563 | 6788 | memcpy(vmx_msr_bitmap_longmode_x2apic_apicv, |
baa03522 | 6789 | vmx_msr_bitmap_longmode, PAGE_SIZE); |
c63e4563 | 6790 | memcpy(vmx_msr_bitmap_legacy_x2apic, |
f6e90f9e | 6791 | vmx_msr_bitmap_legacy, PAGE_SIZE); |
c63e4563 | 6792 | memcpy(vmx_msr_bitmap_longmode_x2apic, |
f6e90f9e | 6793 | vmx_msr_bitmap_longmode, PAGE_SIZE); |
baa03522 | 6794 | |
04bb92e4 WL |
6795 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
6796 | ||
40d8338d RK |
6797 | for (msr = 0x800; msr <= 0x8ff; msr++) { |
6798 | if (msr == 0x839 /* TMCCT */) | |
6799 | continue; | |
2e69f865 | 6800 | vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true); |
40d8338d | 6801 | } |
3ce424e4 | 6802 | |
f6e90f9e | 6803 | /* |
2e69f865 RK |
6804 | * TPR reads and writes can be virtualized even if virtual interrupt |
6805 | * delivery is not in use. | |
f6e90f9e | 6806 | */ |
2e69f865 RK |
6807 | vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true); |
6808 | vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false); | |
3ce424e4 | 6809 | |
3ce424e4 | 6810 | /* EOI */ |
2e69f865 | 6811 | vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true); |
3ce424e4 | 6812 | /* SELF-IPI */ |
2e69f865 | 6813 | vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true); |
baa03522 | 6814 | |
f160c7b7 JS |
6815 | if (enable_ept) |
6816 | vmx_enable_tdp(); | |
6817 | else | |
baa03522 TC |
6818 | kvm_disable_tdp(); |
6819 | ||
6820 | update_ple_window_actual_max(); | |
6821 | ||
843e4330 KH |
6822 | /* |
6823 | * Only enable PML when hardware supports PML feature, and both EPT | |
6824 | * and EPT A/D bit features are enabled -- PML depends on them to work. | |
6825 | */ | |
6826 | if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) | |
6827 | enable_pml = 0; | |
6828 | ||
6829 | if (!enable_pml) { | |
6830 | kvm_x86_ops->slot_enable_log_dirty = NULL; | |
6831 | kvm_x86_ops->slot_disable_log_dirty = NULL; | |
6832 | kvm_x86_ops->flush_log_dirty = NULL; | |
6833 | kvm_x86_ops->enable_log_dirty_pt_masked = NULL; | |
6834 | } | |
6835 | ||
64672c95 YJ |
6836 | if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) { |
6837 | u64 vmx_msr; | |
6838 | ||
6839 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
6840 | cpu_preemption_timer_multi = | |
6841 | vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; | |
6842 | } else { | |
6843 | kvm_x86_ops->set_hv_timer = NULL; | |
6844 | kvm_x86_ops->cancel_hv_timer = NULL; | |
6845 | } | |
6846 | ||
bf9f6ac8 FW |
6847 | kvm_set_posted_intr_wakeup_handler(wakeup_handler); |
6848 | ||
c45dcc71 AR |
6849 | kvm_mce_cap_supported |= MCG_LMCE_P; |
6850 | ||
f2c7648d | 6851 | return alloc_kvm_area(); |
34a1cd60 | 6852 | |
34a1cd60 | 6853 | out: |
23611332 RK |
6854 | for (i = 0; i < VMX_BITMAP_NR; i++) |
6855 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 TC |
6856 | |
6857 | return r; | |
f2c7648d TC |
6858 | } |
6859 | ||
6860 | static __exit void hardware_unsetup(void) | |
6861 | { | |
23611332 RK |
6862 | int i; |
6863 | ||
6864 | for (i = 0; i < VMX_BITMAP_NR; i++) | |
6865 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 | 6866 | |
f2c7648d TC |
6867 | free_kvm_area(); |
6868 | } | |
6869 | ||
4b8d54f9 ZE |
6870 | /* |
6871 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
6872 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
6873 | */ | |
9fb41ba8 | 6874 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 | 6875 | { |
b4a2d31d RK |
6876 | if (ple_gap) |
6877 | grow_ple_window(vcpu); | |
6878 | ||
de63ad4c LM |
6879 | /* |
6880 | * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" | |
6881 | * VM-execution control is ignored if CPL > 0. OTOH, KVM | |
6882 | * never set PAUSE_EXITING and just set PLE if supported, | |
6883 | * so the vcpu must be CPL=0 if it gets a PAUSE exit. | |
6884 | */ | |
6885 | kvm_vcpu_on_spin(vcpu, true); | |
6affcbed | 6886 | return kvm_skip_emulated_instruction(vcpu); |
4b8d54f9 ZE |
6887 | } |
6888 | ||
87c00572 | 6889 | static int handle_nop(struct kvm_vcpu *vcpu) |
59708670 | 6890 | { |
6affcbed | 6891 | return kvm_skip_emulated_instruction(vcpu); |
59708670 SY |
6892 | } |
6893 | ||
87c00572 GS |
6894 | static int handle_mwait(struct kvm_vcpu *vcpu) |
6895 | { | |
6896 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
6897 | return handle_nop(vcpu); | |
6898 | } | |
6899 | ||
45ec368c JM |
6900 | static int handle_invalid_op(struct kvm_vcpu *vcpu) |
6901 | { | |
6902 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6903 | return 1; | |
6904 | } | |
6905 | ||
5f3d45e7 MD |
6906 | static int handle_monitor_trap(struct kvm_vcpu *vcpu) |
6907 | { | |
6908 | return 1; | |
6909 | } | |
6910 | ||
87c00572 GS |
6911 | static int handle_monitor(struct kvm_vcpu *vcpu) |
6912 | { | |
6913 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
6914 | return handle_nop(vcpu); | |
6915 | } | |
6916 | ||
ff2f6fe9 NHE |
6917 | /* |
6918 | * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12. | |
6919 | * We could reuse a single VMCS for all the L2 guests, but we also want the | |
6920 | * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this | |
6921 | * allows keeping them loaded on the processor, and in the future will allow | |
6922 | * optimizations where prepare_vmcs02 doesn't need to set all the fields on | |
6923 | * every entry if they never change. | |
6924 | * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE | |
6925 | * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first. | |
6926 | * | |
6927 | * The following functions allocate and free a vmcs02 in this pool. | |
6928 | */ | |
6929 | ||
6930 | /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */ | |
6931 | static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx) | |
6932 | { | |
6933 | struct vmcs02_list *item; | |
6934 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6935 | if (item->vmptr == vmx->nested.current_vmptr) { | |
6936 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6937 | return &item->vmcs02; | |
6938 | } | |
6939 | ||
6940 | if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) { | |
6941 | /* Recycle the least recently used VMCS. */ | |
d74c0e6b GT |
6942 | item = list_last_entry(&vmx->nested.vmcs02_pool, |
6943 | struct vmcs02_list, list); | |
ff2f6fe9 NHE |
6944 | item->vmptr = vmx->nested.current_vmptr; |
6945 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6946 | return &item->vmcs02; | |
6947 | } | |
6948 | ||
6949 | /* Create a new VMCS */ | |
0fa24ce3 | 6950 | item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL); |
ff2f6fe9 NHE |
6951 | if (!item) |
6952 | return NULL; | |
6953 | item->vmcs02.vmcs = alloc_vmcs(); | |
355f4fb1 | 6954 | item->vmcs02.shadow_vmcs = NULL; |
ff2f6fe9 NHE |
6955 | if (!item->vmcs02.vmcs) { |
6956 | kfree(item); | |
6957 | return NULL; | |
6958 | } | |
6959 | loaded_vmcs_init(&item->vmcs02); | |
6960 | item->vmptr = vmx->nested.current_vmptr; | |
6961 | list_add(&(item->list), &(vmx->nested.vmcs02_pool)); | |
6962 | vmx->nested.vmcs02_num++; | |
6963 | return &item->vmcs02; | |
6964 | } | |
6965 | ||
6966 | /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */ | |
6967 | static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr) | |
6968 | { | |
6969 | struct vmcs02_list *item; | |
6970 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6971 | if (item->vmptr == vmptr) { | |
6972 | free_loaded_vmcs(&item->vmcs02); | |
6973 | list_del(&item->list); | |
6974 | kfree(item); | |
6975 | vmx->nested.vmcs02_num--; | |
6976 | return; | |
6977 | } | |
6978 | } | |
6979 | ||
6980 | /* | |
6981 | * Free all VMCSs saved for this vcpu, except the one pointed by | |
4fa7734c PB |
6982 | * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs |
6983 | * must be &vmx->vmcs01. | |
ff2f6fe9 NHE |
6984 | */ |
6985 | static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx) | |
6986 | { | |
6987 | struct vmcs02_list *item, *n; | |
4fa7734c PB |
6988 | |
6989 | WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01); | |
ff2f6fe9 | 6990 | list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) { |
4fa7734c PB |
6991 | /* |
6992 | * Something will leak if the above WARN triggers. Better than | |
6993 | * a use-after-free. | |
6994 | */ | |
6995 | if (vmx->loaded_vmcs == &item->vmcs02) | |
6996 | continue; | |
6997 | ||
6998 | free_loaded_vmcs(&item->vmcs02); | |
ff2f6fe9 NHE |
6999 | list_del(&item->list); |
7000 | kfree(item); | |
4fa7734c | 7001 | vmx->nested.vmcs02_num--; |
ff2f6fe9 | 7002 | } |
ff2f6fe9 NHE |
7003 | } |
7004 | ||
0658fbaa ACL |
7005 | /* |
7006 | * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), | |
7007 | * set the success or error code of an emulated VMX instruction, as specified | |
7008 | * by Vol 2B, VMX Instruction Reference, "Conventions". | |
7009 | */ | |
7010 | static void nested_vmx_succeed(struct kvm_vcpu *vcpu) | |
7011 | { | |
7012 | vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) | |
7013 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
7014 | X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); | |
7015 | } | |
7016 | ||
7017 | static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu) | |
7018 | { | |
7019 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
7020 | & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | | |
7021 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
7022 | | X86_EFLAGS_CF); | |
7023 | } | |
7024 | ||
145c28dd | 7025 | static void nested_vmx_failValid(struct kvm_vcpu *vcpu, |
0658fbaa ACL |
7026 | u32 vm_instruction_error) |
7027 | { | |
7028 | if (to_vmx(vcpu)->nested.current_vmptr == -1ull) { | |
7029 | /* | |
7030 | * failValid writes the error number to the current VMCS, which | |
7031 | * can't be done there isn't a current VMCS. | |
7032 | */ | |
7033 | nested_vmx_failInvalid(vcpu); | |
7034 | return; | |
7035 | } | |
7036 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
7037 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
7038 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
7039 | | X86_EFLAGS_ZF); | |
7040 | get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; | |
7041 | /* | |
7042 | * We don't need to force a shadow sync because | |
7043 | * VM_INSTRUCTION_ERROR is not shadowed | |
7044 | */ | |
7045 | } | |
145c28dd | 7046 | |
ff651cb6 WV |
7047 | static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator) |
7048 | { | |
7049 | /* TODO: not to reset guest simply here. */ | |
7050 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
bbe41b95 | 7051 | pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator); |
ff651cb6 WV |
7052 | } |
7053 | ||
f4124500 JK |
7054 | static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) |
7055 | { | |
7056 | struct vcpu_vmx *vmx = | |
7057 | container_of(timer, struct vcpu_vmx, nested.preemption_timer); | |
7058 | ||
7059 | vmx->nested.preemption_timer_expired = true; | |
7060 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); | |
7061 | kvm_vcpu_kick(&vmx->vcpu); | |
7062 | ||
7063 | return HRTIMER_NORESTART; | |
7064 | } | |
7065 | ||
19677e32 BD |
7066 | /* |
7067 | * Decode the memory-address operand of a vmx instruction, as recorded on an | |
7068 | * exit caused by such an instruction (run by a guest hypervisor). | |
7069 | * On success, returns 0. When the operand is invalid, returns 1 and throws | |
7070 | * #UD or #GP. | |
7071 | */ | |
7072 | static int get_vmx_mem_address(struct kvm_vcpu *vcpu, | |
7073 | unsigned long exit_qualification, | |
f9eb4af6 | 7074 | u32 vmx_instruction_info, bool wr, gva_t *ret) |
19677e32 | 7075 | { |
f9eb4af6 EK |
7076 | gva_t off; |
7077 | bool exn; | |
7078 | struct kvm_segment s; | |
7079 | ||
19677e32 BD |
7080 | /* |
7081 | * According to Vol. 3B, "Information for VM Exits Due to Instruction | |
7082 | * Execution", on an exit, vmx_instruction_info holds most of the | |
7083 | * addressing components of the operand. Only the displacement part | |
7084 | * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). | |
7085 | * For how an actual address is calculated from all these components, | |
7086 | * refer to Vol. 1, "Operand Addressing". | |
7087 | */ | |
7088 | int scaling = vmx_instruction_info & 3; | |
7089 | int addr_size = (vmx_instruction_info >> 7) & 7; | |
7090 | bool is_reg = vmx_instruction_info & (1u << 10); | |
7091 | int seg_reg = (vmx_instruction_info >> 15) & 7; | |
7092 | int index_reg = (vmx_instruction_info >> 18) & 0xf; | |
7093 | bool index_is_valid = !(vmx_instruction_info & (1u << 22)); | |
7094 | int base_reg = (vmx_instruction_info >> 23) & 0xf; | |
7095 | bool base_is_valid = !(vmx_instruction_info & (1u << 27)); | |
7096 | ||
7097 | if (is_reg) { | |
7098 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7099 | return 1; | |
7100 | } | |
7101 | ||
7102 | /* Addr = segment_base + offset */ | |
7103 | /* offset = base + [index * scale] + displacement */ | |
f9eb4af6 | 7104 | off = exit_qualification; /* holds the displacement */ |
19677e32 | 7105 | if (base_is_valid) |
f9eb4af6 | 7106 | off += kvm_register_read(vcpu, base_reg); |
19677e32 | 7107 | if (index_is_valid) |
f9eb4af6 EK |
7108 | off += kvm_register_read(vcpu, index_reg)<<scaling; |
7109 | vmx_get_segment(vcpu, &s, seg_reg); | |
7110 | *ret = s.base + off; | |
19677e32 BD |
7111 | |
7112 | if (addr_size == 1) /* 32 bit */ | |
7113 | *ret &= 0xffffffff; | |
7114 | ||
f9eb4af6 EK |
7115 | /* Checks for #GP/#SS exceptions. */ |
7116 | exn = false; | |
ff30ef40 QC |
7117 | if (is_long_mode(vcpu)) { |
7118 | /* Long mode: #GP(0)/#SS(0) if the memory address is in a | |
7119 | * non-canonical form. This is the only check on the memory | |
7120 | * destination for long mode! | |
7121 | */ | |
fd8cb433 | 7122 | exn = is_noncanonical_address(*ret, vcpu); |
ff30ef40 | 7123 | } else if (is_protmode(vcpu)) { |
f9eb4af6 EK |
7124 | /* Protected mode: apply checks for segment validity in the |
7125 | * following order: | |
7126 | * - segment type check (#GP(0) may be thrown) | |
7127 | * - usability check (#GP(0)/#SS(0)) | |
7128 | * - limit check (#GP(0)/#SS(0)) | |
7129 | */ | |
7130 | if (wr) | |
7131 | /* #GP(0) if the destination operand is located in a | |
7132 | * read-only data segment or any code segment. | |
7133 | */ | |
7134 | exn = ((s.type & 0xa) == 0 || (s.type & 8)); | |
7135 | else | |
7136 | /* #GP(0) if the source operand is located in an | |
7137 | * execute-only code segment | |
7138 | */ | |
7139 | exn = ((s.type & 0xa) == 8); | |
ff30ef40 QC |
7140 | if (exn) { |
7141 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
7142 | return 1; | |
7143 | } | |
f9eb4af6 EK |
7144 | /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. |
7145 | */ | |
7146 | exn = (s.unusable != 0); | |
7147 | /* Protected mode: #GP(0)/#SS(0) if the memory | |
7148 | * operand is outside the segment limit. | |
7149 | */ | |
7150 | exn = exn || (off + sizeof(u64) > s.limit); | |
7151 | } | |
7152 | if (exn) { | |
7153 | kvm_queue_exception_e(vcpu, | |
7154 | seg_reg == VCPU_SREG_SS ? | |
7155 | SS_VECTOR : GP_VECTOR, | |
7156 | 0); | |
7157 | return 1; | |
7158 | } | |
7159 | ||
19677e32 BD |
7160 | return 0; |
7161 | } | |
7162 | ||
cbf71279 | 7163 | static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer) |
3573e22c BD |
7164 | { |
7165 | gva_t gva; | |
3573e22c | 7166 | struct x86_exception e; |
3573e22c BD |
7167 | |
7168 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7169 | vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva)) |
3573e22c BD |
7170 | return 1; |
7171 | ||
cbf71279 RK |
7172 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer, |
7173 | sizeof(*vmpointer), &e)) { | |
3573e22c BD |
7174 | kvm_inject_page_fault(vcpu, &e); |
7175 | return 1; | |
7176 | } | |
7177 | ||
3573e22c BD |
7178 | return 0; |
7179 | } | |
7180 | ||
e29acc55 JM |
7181 | static int enter_vmx_operation(struct kvm_vcpu *vcpu) |
7182 | { | |
7183 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7184 | struct vmcs *shadow_vmcs; | |
7185 | ||
7186 | if (cpu_has_vmx_msr_bitmap()) { | |
7187 | vmx->nested.msr_bitmap = | |
7188 | (unsigned long *)__get_free_page(GFP_KERNEL); | |
7189 | if (!vmx->nested.msr_bitmap) | |
7190 | goto out_msr_bitmap; | |
7191 | } | |
7192 | ||
7193 | vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL); | |
7194 | if (!vmx->nested.cached_vmcs12) | |
7195 | goto out_cached_vmcs12; | |
7196 | ||
7197 | if (enable_shadow_vmcs) { | |
7198 | shadow_vmcs = alloc_vmcs(); | |
7199 | if (!shadow_vmcs) | |
7200 | goto out_shadow_vmcs; | |
7201 | /* mark vmcs as shadow */ | |
7202 | shadow_vmcs->revision_id |= (1u << 31); | |
7203 | /* init shadow vmcs */ | |
7204 | vmcs_clear(shadow_vmcs); | |
7205 | vmx->vmcs01.shadow_vmcs = shadow_vmcs; | |
7206 | } | |
7207 | ||
7208 | INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool)); | |
7209 | vmx->nested.vmcs02_num = 0; | |
7210 | ||
7211 | hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, | |
7212 | HRTIMER_MODE_REL_PINNED); | |
7213 | vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; | |
7214 | ||
7215 | vmx->nested.vmxon = true; | |
7216 | return 0; | |
7217 | ||
7218 | out_shadow_vmcs: | |
7219 | kfree(vmx->nested.cached_vmcs12); | |
7220 | ||
7221 | out_cached_vmcs12: | |
7222 | free_page((unsigned long)vmx->nested.msr_bitmap); | |
7223 | ||
7224 | out_msr_bitmap: | |
7225 | return -ENOMEM; | |
7226 | } | |
7227 | ||
ec378aee NHE |
7228 | /* |
7229 | * Emulate the VMXON instruction. | |
7230 | * Currently, we just remember that VMX is active, and do not save or even | |
7231 | * inspect the argument to VMXON (the so-called "VMXON pointer") because we | |
7232 | * do not currently need to store anything in that guest-allocated memory | |
7233 | * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their | |
7234 | * argument is different from the VMXON pointer (which the spec says they do). | |
7235 | */ | |
7236 | static int handle_vmon(struct kvm_vcpu *vcpu) | |
7237 | { | |
e29acc55 | 7238 | int ret; |
cbf71279 RK |
7239 | gpa_t vmptr; |
7240 | struct page *page; | |
ec378aee | 7241 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b3897a49 NHE |
7242 | const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED |
7243 | | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
ec378aee | 7244 | |
70f3aac9 JM |
7245 | /* |
7246 | * The Intel VMX Instruction Reference lists a bunch of bits that are | |
7247 | * prerequisite to running VMXON, most notably cr4.VMXE must be set to | |
7248 | * 1 (see vmx_set_cr4() for when we allow the guest to set this). | |
7249 | * Otherwise, we should fail with #UD. But most faulting conditions | |
7250 | * have already been checked by hardware, prior to the VM-exit for | |
7251 | * VMXON. We do test guest cr4.VMXE because processor CR4 always has | |
7252 | * that bit set to 1 in non-root mode. | |
ec378aee | 7253 | */ |
70f3aac9 | 7254 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) { |
ec378aee NHE |
7255 | kvm_queue_exception(vcpu, UD_VECTOR); |
7256 | return 1; | |
7257 | } | |
7258 | ||
145c28dd AG |
7259 | if (vmx->nested.vmxon) { |
7260 | nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); | |
6affcbed | 7261 | return kvm_skip_emulated_instruction(vcpu); |
145c28dd | 7262 | } |
b3897a49 | 7263 | |
3b84080b | 7264 | if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES) |
b3897a49 NHE |
7265 | != VMXON_NEEDED_FEATURES) { |
7266 | kvm_inject_gp(vcpu, 0); | |
7267 | return 1; | |
7268 | } | |
7269 | ||
cbf71279 | 7270 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
21e7fbe7 | 7271 | return 1; |
cbf71279 RK |
7272 | |
7273 | /* | |
7274 | * SDM 3: 24.11.5 | |
7275 | * The first 4 bytes of VMXON region contain the supported | |
7276 | * VMCS revision identifier | |
7277 | * | |
7278 | * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case; | |
7279 | * which replaces physical address width with 32 | |
7280 | */ | |
7281 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { | |
7282 | nested_vmx_failInvalid(vcpu); | |
7283 | return kvm_skip_emulated_instruction(vcpu); | |
7284 | } | |
7285 | ||
5e2f30b7 DH |
7286 | page = kvm_vcpu_gpa_to_page(vcpu, vmptr); |
7287 | if (is_error_page(page)) { | |
cbf71279 RK |
7288 | nested_vmx_failInvalid(vcpu); |
7289 | return kvm_skip_emulated_instruction(vcpu); | |
7290 | } | |
7291 | if (*(u32 *)kmap(page) != VMCS12_REVISION) { | |
7292 | kunmap(page); | |
53a70daf | 7293 | kvm_release_page_clean(page); |
cbf71279 RK |
7294 | nested_vmx_failInvalid(vcpu); |
7295 | return kvm_skip_emulated_instruction(vcpu); | |
7296 | } | |
7297 | kunmap(page); | |
53a70daf | 7298 | kvm_release_page_clean(page); |
cbf71279 RK |
7299 | |
7300 | vmx->nested.vmxon_ptr = vmptr; | |
e29acc55 JM |
7301 | ret = enter_vmx_operation(vcpu); |
7302 | if (ret) | |
7303 | return ret; | |
ec378aee | 7304 | |
a25eb114 | 7305 | nested_vmx_succeed(vcpu); |
6affcbed | 7306 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7307 | } |
7308 | ||
7309 | /* | |
7310 | * Intel's VMX Instruction Reference specifies a common set of prerequisites | |
7311 | * for running VMX instructions (except VMXON, whose prerequisites are | |
7312 | * slightly different). It also specifies what exception to inject otherwise. | |
70f3aac9 JM |
7313 | * Note that many of these exceptions have priority over VM exits, so they |
7314 | * don't have to be checked again here. | |
ec378aee NHE |
7315 | */ |
7316 | static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) | |
7317 | { | |
70f3aac9 | 7318 | if (!to_vmx(vcpu)->nested.vmxon) { |
ec378aee NHE |
7319 | kvm_queue_exception(vcpu, UD_VECTOR); |
7320 | return 0; | |
7321 | } | |
ec378aee NHE |
7322 | return 1; |
7323 | } | |
7324 | ||
8ca44e88 DM |
7325 | static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx) |
7326 | { | |
7327 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS); | |
7328 | vmcs_write64(VMCS_LINK_POINTER, -1ull); | |
7329 | } | |
7330 | ||
e7953d7f AG |
7331 | static inline void nested_release_vmcs12(struct vcpu_vmx *vmx) |
7332 | { | |
9a2a05b9 PB |
7333 | if (vmx->nested.current_vmptr == -1ull) |
7334 | return; | |
7335 | ||
012f83cb | 7336 | if (enable_shadow_vmcs) { |
9a2a05b9 PB |
7337 | /* copy to memory all shadowed fields in case |
7338 | they were modified */ | |
7339 | copy_shadow_to_vmcs12(vmx); | |
7340 | vmx->nested.sync_shadow_vmcs = false; | |
8ca44e88 | 7341 | vmx_disable_shadow_vmcs(vmx); |
012f83cb | 7342 | } |
705699a1 | 7343 | vmx->nested.posted_intr_nv = -1; |
4f2777bc DM |
7344 | |
7345 | /* Flush VMCS12 to guest memory */ | |
9f744c59 PB |
7346 | kvm_vcpu_write_guest_page(&vmx->vcpu, |
7347 | vmx->nested.current_vmptr >> PAGE_SHIFT, | |
7348 | vmx->nested.cached_vmcs12, 0, VMCS12_SIZE); | |
4f2777bc | 7349 | |
9a2a05b9 | 7350 | vmx->nested.current_vmptr = -1ull; |
e7953d7f AG |
7351 | } |
7352 | ||
ec378aee NHE |
7353 | /* |
7354 | * Free whatever needs to be freed from vmx->nested when L1 goes down, or | |
7355 | * just stops using VMX. | |
7356 | */ | |
7357 | static void free_nested(struct vcpu_vmx *vmx) | |
7358 | { | |
7359 | if (!vmx->nested.vmxon) | |
7360 | return; | |
9a2a05b9 | 7361 | |
ec378aee | 7362 | vmx->nested.vmxon = false; |
5c614b35 | 7363 | free_vpid(vmx->nested.vpid02); |
8ca44e88 DM |
7364 | vmx->nested.posted_intr_nv = -1; |
7365 | vmx->nested.current_vmptr = -1ull; | |
d048c098 RK |
7366 | if (vmx->nested.msr_bitmap) { |
7367 | free_page((unsigned long)vmx->nested.msr_bitmap); | |
7368 | vmx->nested.msr_bitmap = NULL; | |
7369 | } | |
355f4fb1 | 7370 | if (enable_shadow_vmcs) { |
8ca44e88 | 7371 | vmx_disable_shadow_vmcs(vmx); |
355f4fb1 JM |
7372 | vmcs_clear(vmx->vmcs01.shadow_vmcs); |
7373 | free_vmcs(vmx->vmcs01.shadow_vmcs); | |
7374 | vmx->vmcs01.shadow_vmcs = NULL; | |
7375 | } | |
4f2777bc | 7376 | kfree(vmx->nested.cached_vmcs12); |
fe3ef05c NHE |
7377 | /* Unpin physical memory we referred to in current vmcs02 */ |
7378 | if (vmx->nested.apic_access_page) { | |
53a70daf | 7379 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
48d89b92 | 7380 | vmx->nested.apic_access_page = NULL; |
fe3ef05c | 7381 | } |
a7c0b07d | 7382 | if (vmx->nested.virtual_apic_page) { |
53a70daf | 7383 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
48d89b92 | 7384 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 7385 | } |
705699a1 WV |
7386 | if (vmx->nested.pi_desc_page) { |
7387 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 7388 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
705699a1 WV |
7389 | vmx->nested.pi_desc_page = NULL; |
7390 | vmx->nested.pi_desc = NULL; | |
7391 | } | |
ff2f6fe9 NHE |
7392 | |
7393 | nested_free_all_saved_vmcss(vmx); | |
ec378aee NHE |
7394 | } |
7395 | ||
7396 | /* Emulate the VMXOFF instruction */ | |
7397 | static int handle_vmoff(struct kvm_vcpu *vcpu) | |
7398 | { | |
7399 | if (!nested_vmx_check_permission(vcpu)) | |
7400 | return 1; | |
7401 | free_nested(to_vmx(vcpu)); | |
a25eb114 | 7402 | nested_vmx_succeed(vcpu); |
6affcbed | 7403 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7404 | } |
7405 | ||
27d6c865 NHE |
7406 | /* Emulate the VMCLEAR instruction */ |
7407 | static int handle_vmclear(struct kvm_vcpu *vcpu) | |
7408 | { | |
7409 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
587d7e72 | 7410 | u32 zero = 0; |
27d6c865 | 7411 | gpa_t vmptr; |
27d6c865 NHE |
7412 | |
7413 | if (!nested_vmx_check_permission(vcpu)) | |
7414 | return 1; | |
7415 | ||
cbf71279 | 7416 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
27d6c865 | 7417 | return 1; |
27d6c865 | 7418 | |
cbf71279 RK |
7419 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { |
7420 | nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS); | |
7421 | return kvm_skip_emulated_instruction(vcpu); | |
7422 | } | |
7423 | ||
7424 | if (vmptr == vmx->nested.vmxon_ptr) { | |
7425 | nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER); | |
7426 | return kvm_skip_emulated_instruction(vcpu); | |
7427 | } | |
7428 | ||
9a2a05b9 | 7429 | if (vmptr == vmx->nested.current_vmptr) |
e7953d7f | 7430 | nested_release_vmcs12(vmx); |
27d6c865 | 7431 | |
587d7e72 JM |
7432 | kvm_vcpu_write_guest(vcpu, |
7433 | vmptr + offsetof(struct vmcs12, launch_state), | |
7434 | &zero, sizeof(zero)); | |
27d6c865 NHE |
7435 | |
7436 | nested_free_vmcs02(vmx, vmptr); | |
7437 | ||
27d6c865 | 7438 | nested_vmx_succeed(vcpu); |
6affcbed | 7439 | return kvm_skip_emulated_instruction(vcpu); |
27d6c865 NHE |
7440 | } |
7441 | ||
cd232ad0 NHE |
7442 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch); |
7443 | ||
7444 | /* Emulate the VMLAUNCH instruction */ | |
7445 | static int handle_vmlaunch(struct kvm_vcpu *vcpu) | |
7446 | { | |
7447 | return nested_vmx_run(vcpu, true); | |
7448 | } | |
7449 | ||
7450 | /* Emulate the VMRESUME instruction */ | |
7451 | static int handle_vmresume(struct kvm_vcpu *vcpu) | |
7452 | { | |
7453 | ||
7454 | return nested_vmx_run(vcpu, false); | |
7455 | } | |
7456 | ||
49f705c5 NHE |
7457 | /* |
7458 | * Read a vmcs12 field. Since these can have varying lengths and we return | |
7459 | * one type, we chose the biggest type (u64) and zero-extend the return value | |
7460 | * to that size. Note that the caller, handle_vmread, might need to use only | |
7461 | * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of | |
7462 | * 64-bit fields are to be returned). | |
7463 | */ | |
a2ae9df7 PB |
7464 | static inline int vmcs12_read_any(struct kvm_vcpu *vcpu, |
7465 | unsigned long field, u64 *ret) | |
49f705c5 NHE |
7466 | { |
7467 | short offset = vmcs_field_to_offset(field); | |
7468 | char *p; | |
7469 | ||
7470 | if (offset < 0) | |
a2ae9df7 | 7471 | return offset; |
49f705c5 NHE |
7472 | |
7473 | p = ((char *)(get_vmcs12(vcpu))) + offset; | |
7474 | ||
7475 | switch (vmcs_field_type(field)) { | |
7476 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7477 | *ret = *((natural_width *)p); | |
a2ae9df7 | 7478 | return 0; |
49f705c5 NHE |
7479 | case VMCS_FIELD_TYPE_U16: |
7480 | *ret = *((u16 *)p); | |
a2ae9df7 | 7481 | return 0; |
49f705c5 NHE |
7482 | case VMCS_FIELD_TYPE_U32: |
7483 | *ret = *((u32 *)p); | |
a2ae9df7 | 7484 | return 0; |
49f705c5 NHE |
7485 | case VMCS_FIELD_TYPE_U64: |
7486 | *ret = *((u64 *)p); | |
a2ae9df7 | 7487 | return 0; |
49f705c5 | 7488 | default: |
a2ae9df7 PB |
7489 | WARN_ON(1); |
7490 | return -ENOENT; | |
49f705c5 NHE |
7491 | } |
7492 | } | |
7493 | ||
20b97fea | 7494 | |
a2ae9df7 PB |
7495 | static inline int vmcs12_write_any(struct kvm_vcpu *vcpu, |
7496 | unsigned long field, u64 field_value){ | |
20b97fea AG |
7497 | short offset = vmcs_field_to_offset(field); |
7498 | char *p = ((char *) get_vmcs12(vcpu)) + offset; | |
7499 | if (offset < 0) | |
a2ae9df7 | 7500 | return offset; |
20b97fea AG |
7501 | |
7502 | switch (vmcs_field_type(field)) { | |
7503 | case VMCS_FIELD_TYPE_U16: | |
7504 | *(u16 *)p = field_value; | |
a2ae9df7 | 7505 | return 0; |
20b97fea AG |
7506 | case VMCS_FIELD_TYPE_U32: |
7507 | *(u32 *)p = field_value; | |
a2ae9df7 | 7508 | return 0; |
20b97fea AG |
7509 | case VMCS_FIELD_TYPE_U64: |
7510 | *(u64 *)p = field_value; | |
a2ae9df7 | 7511 | return 0; |
20b97fea AG |
7512 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: |
7513 | *(natural_width *)p = field_value; | |
a2ae9df7 | 7514 | return 0; |
20b97fea | 7515 | default: |
a2ae9df7 PB |
7516 | WARN_ON(1); |
7517 | return -ENOENT; | |
20b97fea AG |
7518 | } |
7519 | ||
7520 | } | |
7521 | ||
16f5b903 AG |
7522 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) |
7523 | { | |
7524 | int i; | |
7525 | unsigned long field; | |
7526 | u64 field_value; | |
355f4fb1 | 7527 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c2bae893 MK |
7528 | const unsigned long *fields = shadow_read_write_fields; |
7529 | const int num_fields = max_shadow_read_write_fields; | |
16f5b903 | 7530 | |
282da870 JK |
7531 | preempt_disable(); |
7532 | ||
16f5b903 AG |
7533 | vmcs_load(shadow_vmcs); |
7534 | ||
7535 | for (i = 0; i < num_fields; i++) { | |
7536 | field = fields[i]; | |
7537 | switch (vmcs_field_type(field)) { | |
7538 | case VMCS_FIELD_TYPE_U16: | |
7539 | field_value = vmcs_read16(field); | |
7540 | break; | |
7541 | case VMCS_FIELD_TYPE_U32: | |
7542 | field_value = vmcs_read32(field); | |
7543 | break; | |
7544 | case VMCS_FIELD_TYPE_U64: | |
7545 | field_value = vmcs_read64(field); | |
7546 | break; | |
7547 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7548 | field_value = vmcs_readl(field); | |
7549 | break; | |
a2ae9df7 PB |
7550 | default: |
7551 | WARN_ON(1); | |
7552 | continue; | |
16f5b903 AG |
7553 | } |
7554 | vmcs12_write_any(&vmx->vcpu, field, field_value); | |
7555 | } | |
7556 | ||
7557 | vmcs_clear(shadow_vmcs); | |
7558 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
282da870 JK |
7559 | |
7560 | preempt_enable(); | |
16f5b903 AG |
7561 | } |
7562 | ||
c3114420 AG |
7563 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) |
7564 | { | |
c2bae893 MK |
7565 | const unsigned long *fields[] = { |
7566 | shadow_read_write_fields, | |
7567 | shadow_read_only_fields | |
c3114420 | 7568 | }; |
c2bae893 | 7569 | const int max_fields[] = { |
c3114420 AG |
7570 | max_shadow_read_write_fields, |
7571 | max_shadow_read_only_fields | |
7572 | }; | |
7573 | int i, q; | |
7574 | unsigned long field; | |
7575 | u64 field_value = 0; | |
355f4fb1 | 7576 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c3114420 AG |
7577 | |
7578 | vmcs_load(shadow_vmcs); | |
7579 | ||
c2bae893 | 7580 | for (q = 0; q < ARRAY_SIZE(fields); q++) { |
c3114420 AG |
7581 | for (i = 0; i < max_fields[q]; i++) { |
7582 | field = fields[q][i]; | |
7583 | vmcs12_read_any(&vmx->vcpu, field, &field_value); | |
7584 | ||
7585 | switch (vmcs_field_type(field)) { | |
7586 | case VMCS_FIELD_TYPE_U16: | |
7587 | vmcs_write16(field, (u16)field_value); | |
7588 | break; | |
7589 | case VMCS_FIELD_TYPE_U32: | |
7590 | vmcs_write32(field, (u32)field_value); | |
7591 | break; | |
7592 | case VMCS_FIELD_TYPE_U64: | |
7593 | vmcs_write64(field, (u64)field_value); | |
7594 | break; | |
7595 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7596 | vmcs_writel(field, (long)field_value); | |
7597 | break; | |
a2ae9df7 PB |
7598 | default: |
7599 | WARN_ON(1); | |
7600 | break; | |
c3114420 AG |
7601 | } |
7602 | } | |
7603 | } | |
7604 | ||
7605 | vmcs_clear(shadow_vmcs); | |
7606 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
7607 | } | |
7608 | ||
49f705c5 NHE |
7609 | /* |
7610 | * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was | |
7611 | * used before) all generate the same failure when it is missing. | |
7612 | */ | |
7613 | static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu) | |
7614 | { | |
7615 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7616 | if (vmx->nested.current_vmptr == -1ull) { | |
7617 | nested_vmx_failInvalid(vcpu); | |
49f705c5 NHE |
7618 | return 0; |
7619 | } | |
7620 | return 1; | |
7621 | } | |
7622 | ||
7623 | static int handle_vmread(struct kvm_vcpu *vcpu) | |
7624 | { | |
7625 | unsigned long field; | |
7626 | u64 field_value; | |
7627 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7628 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7629 | gva_t gva = 0; | |
7630 | ||
eb277562 | 7631 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
7632 | return 1; |
7633 | ||
6affcbed KH |
7634 | if (!nested_vmx_check_vmcs12(vcpu)) |
7635 | return kvm_skip_emulated_instruction(vcpu); | |
49f705c5 NHE |
7636 | |
7637 | /* Decode instruction info and find the field to read */ | |
27e6fb5d | 7638 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 | 7639 | /* Read the field, zero-extended to a u64 field_value */ |
a2ae9df7 | 7640 | if (vmcs12_read_any(vcpu, field, &field_value) < 0) { |
49f705c5 | 7641 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 7642 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7643 | } |
7644 | /* | |
7645 | * Now copy part of this value to register or memory, as requested. | |
7646 | * Note that the number of bits actually copied is 32 or 64 depending | |
7647 | * on the guest's mode (32 or 64 bit), not on the given field's length. | |
7648 | */ | |
7649 | if (vmx_instruction_info & (1u << 10)) { | |
27e6fb5d | 7650 | kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf), |
49f705c5 NHE |
7651 | field_value); |
7652 | } else { | |
7653 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7654 | vmx_instruction_info, true, &gva)) |
49f705c5 | 7655 | return 1; |
70f3aac9 | 7656 | /* _system ok, as hardware has verified cpl=0 */ |
49f705c5 NHE |
7657 | kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva, |
7658 | &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL); | |
7659 | } | |
7660 | ||
7661 | nested_vmx_succeed(vcpu); | |
6affcbed | 7662 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7663 | } |
7664 | ||
7665 | ||
7666 | static int handle_vmwrite(struct kvm_vcpu *vcpu) | |
7667 | { | |
7668 | unsigned long field; | |
7669 | gva_t gva; | |
7670 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7671 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
49f705c5 NHE |
7672 | /* The value to write might be 32 or 64 bits, depending on L1's long |
7673 | * mode, and eventually we need to write that into a field of several | |
7674 | * possible lengths. The code below first zero-extends the value to 64 | |
6a6256f9 | 7675 | * bit (field_value), and then copies only the appropriate number of |
49f705c5 NHE |
7676 | * bits into the vmcs12 field. |
7677 | */ | |
7678 | u64 field_value = 0; | |
7679 | struct x86_exception e; | |
7680 | ||
eb277562 | 7681 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
7682 | return 1; |
7683 | ||
6affcbed KH |
7684 | if (!nested_vmx_check_vmcs12(vcpu)) |
7685 | return kvm_skip_emulated_instruction(vcpu); | |
eb277562 | 7686 | |
49f705c5 | 7687 | if (vmx_instruction_info & (1u << 10)) |
27e6fb5d | 7688 | field_value = kvm_register_readl(vcpu, |
49f705c5 NHE |
7689 | (((vmx_instruction_info) >> 3) & 0xf)); |
7690 | else { | |
7691 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7692 | vmx_instruction_info, false, &gva)) |
49f705c5 NHE |
7693 | return 1; |
7694 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, | |
27e6fb5d | 7695 | &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) { |
49f705c5 NHE |
7696 | kvm_inject_page_fault(vcpu, &e); |
7697 | return 1; | |
7698 | } | |
7699 | } | |
7700 | ||
7701 | ||
27e6fb5d | 7702 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 NHE |
7703 | if (vmcs_field_readonly(field)) { |
7704 | nested_vmx_failValid(vcpu, | |
7705 | VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); | |
6affcbed | 7706 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7707 | } |
7708 | ||
a2ae9df7 | 7709 | if (vmcs12_write_any(vcpu, field, field_value) < 0) { |
49f705c5 | 7710 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 7711 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7712 | } |
7713 | ||
7714 | nested_vmx_succeed(vcpu); | |
6affcbed | 7715 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7716 | } |
7717 | ||
a8bc284e JM |
7718 | static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr) |
7719 | { | |
7720 | vmx->nested.current_vmptr = vmptr; | |
7721 | if (enable_shadow_vmcs) { | |
7722 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
7723 | SECONDARY_EXEC_SHADOW_VMCS); | |
7724 | vmcs_write64(VMCS_LINK_POINTER, | |
7725 | __pa(vmx->vmcs01.shadow_vmcs)); | |
7726 | vmx->nested.sync_shadow_vmcs = true; | |
7727 | } | |
7728 | } | |
7729 | ||
63846663 NHE |
7730 | /* Emulate the VMPTRLD instruction */ |
7731 | static int handle_vmptrld(struct kvm_vcpu *vcpu) | |
7732 | { | |
7733 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
63846663 | 7734 | gpa_t vmptr; |
63846663 NHE |
7735 | |
7736 | if (!nested_vmx_check_permission(vcpu)) | |
7737 | return 1; | |
7738 | ||
cbf71279 | 7739 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
63846663 | 7740 | return 1; |
63846663 | 7741 | |
cbf71279 RK |
7742 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { |
7743 | nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS); | |
7744 | return kvm_skip_emulated_instruction(vcpu); | |
7745 | } | |
7746 | ||
7747 | if (vmptr == vmx->nested.vmxon_ptr) { | |
7748 | nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER); | |
7749 | return kvm_skip_emulated_instruction(vcpu); | |
7750 | } | |
7751 | ||
63846663 NHE |
7752 | if (vmx->nested.current_vmptr != vmptr) { |
7753 | struct vmcs12 *new_vmcs12; | |
7754 | struct page *page; | |
5e2f30b7 DH |
7755 | page = kvm_vcpu_gpa_to_page(vcpu, vmptr); |
7756 | if (is_error_page(page)) { | |
63846663 | 7757 | nested_vmx_failInvalid(vcpu); |
6affcbed | 7758 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
7759 | } |
7760 | new_vmcs12 = kmap(page); | |
7761 | if (new_vmcs12->revision_id != VMCS12_REVISION) { | |
7762 | kunmap(page); | |
53a70daf | 7763 | kvm_release_page_clean(page); |
63846663 NHE |
7764 | nested_vmx_failValid(vcpu, |
7765 | VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); | |
6affcbed | 7766 | return kvm_skip_emulated_instruction(vcpu); |
63846663 | 7767 | } |
63846663 | 7768 | |
9a2a05b9 | 7769 | nested_release_vmcs12(vmx); |
4f2777bc DM |
7770 | /* |
7771 | * Load VMCS12 from guest memory since it is not already | |
7772 | * cached. | |
7773 | */ | |
9f744c59 PB |
7774 | memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE); |
7775 | kunmap(page); | |
53a70daf | 7776 | kvm_release_page_clean(page); |
9f744c59 | 7777 | |
a8bc284e | 7778 | set_current_vmptr(vmx, vmptr); |
63846663 NHE |
7779 | } |
7780 | ||
7781 | nested_vmx_succeed(vcpu); | |
6affcbed | 7782 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
7783 | } |
7784 | ||
6a4d7550 NHE |
7785 | /* Emulate the VMPTRST instruction */ |
7786 | static int handle_vmptrst(struct kvm_vcpu *vcpu) | |
7787 | { | |
7788 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7789 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7790 | gva_t vmcs_gva; | |
7791 | struct x86_exception e; | |
7792 | ||
7793 | if (!nested_vmx_check_permission(vcpu)) | |
7794 | return 1; | |
7795 | ||
7796 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7797 | vmx_instruction_info, true, &vmcs_gva)) |
6a4d7550 | 7798 | return 1; |
70f3aac9 | 7799 | /* ok to use *_system, as hardware has verified cpl=0 */ |
6a4d7550 NHE |
7800 | if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva, |
7801 | (void *)&to_vmx(vcpu)->nested.current_vmptr, | |
7802 | sizeof(u64), &e)) { | |
7803 | kvm_inject_page_fault(vcpu, &e); | |
7804 | return 1; | |
7805 | } | |
7806 | nested_vmx_succeed(vcpu); | |
6affcbed | 7807 | return kvm_skip_emulated_instruction(vcpu); |
6a4d7550 NHE |
7808 | } |
7809 | ||
bfd0a56b NHE |
7810 | /* Emulate the INVEPT instruction */ |
7811 | static int handle_invept(struct kvm_vcpu *vcpu) | |
7812 | { | |
b9c237bb | 7813 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
bfd0a56b NHE |
7814 | u32 vmx_instruction_info, types; |
7815 | unsigned long type; | |
7816 | gva_t gva; | |
7817 | struct x86_exception e; | |
7818 | struct { | |
7819 | u64 eptp, gpa; | |
7820 | } operand; | |
bfd0a56b | 7821 | |
b9c237bb WV |
7822 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & |
7823 | SECONDARY_EXEC_ENABLE_EPT) || | |
7824 | !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) { | |
bfd0a56b NHE |
7825 | kvm_queue_exception(vcpu, UD_VECTOR); |
7826 | return 1; | |
7827 | } | |
7828 | ||
7829 | if (!nested_vmx_check_permission(vcpu)) | |
7830 | return 1; | |
7831 | ||
bfd0a56b | 7832 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); |
27e6fb5d | 7833 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); |
bfd0a56b | 7834 | |
b9c237bb | 7835 | types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; |
bfd0a56b | 7836 | |
85c856b3 | 7837 | if (type >= 32 || !(types & (1 << type))) { |
bfd0a56b NHE |
7838 | nested_vmx_failValid(vcpu, |
7839 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7840 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
7841 | } |
7842 | ||
7843 | /* According to the Intel VMX instruction reference, the memory | |
7844 | * operand is read even if it isn't needed (e.g., for type==global) | |
7845 | */ | |
7846 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7847 | vmx_instruction_info, false, &gva)) |
bfd0a56b NHE |
7848 | return 1; |
7849 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand, | |
7850 | sizeof(operand), &e)) { | |
7851 | kvm_inject_page_fault(vcpu, &e); | |
7852 | return 1; | |
7853 | } | |
7854 | ||
7855 | switch (type) { | |
bfd0a56b | 7856 | case VMX_EPT_EXTENT_GLOBAL: |
45e11817 BD |
7857 | /* |
7858 | * TODO: track mappings and invalidate | |
7859 | * single context requests appropriately | |
7860 | */ | |
7861 | case VMX_EPT_EXTENT_CONTEXT: | |
bfd0a56b | 7862 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 7863 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
bfd0a56b NHE |
7864 | nested_vmx_succeed(vcpu); |
7865 | break; | |
7866 | default: | |
7867 | BUG_ON(1); | |
7868 | break; | |
7869 | } | |
7870 | ||
6affcbed | 7871 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
7872 | } |
7873 | ||
a642fc30 PM |
7874 | static int handle_invvpid(struct kvm_vcpu *vcpu) |
7875 | { | |
99b83ac8 WL |
7876 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7877 | u32 vmx_instruction_info; | |
7878 | unsigned long type, types; | |
7879 | gva_t gva; | |
7880 | struct x86_exception e; | |
40352605 JM |
7881 | struct { |
7882 | u64 vpid; | |
7883 | u64 gla; | |
7884 | } operand; | |
99b83ac8 WL |
7885 | |
7886 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & | |
7887 | SECONDARY_EXEC_ENABLE_VPID) || | |
7888 | !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) { | |
7889 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7890 | return 1; | |
7891 | } | |
7892 | ||
7893 | if (!nested_vmx_check_permission(vcpu)) | |
7894 | return 1; | |
7895 | ||
7896 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7897 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); | |
7898 | ||
bcdde302 JD |
7899 | types = (vmx->nested.nested_vmx_vpid_caps & |
7900 | VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8; | |
99b83ac8 | 7901 | |
85c856b3 | 7902 | if (type >= 32 || !(types & (1 << type))) { |
99b83ac8 WL |
7903 | nested_vmx_failValid(vcpu, |
7904 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7905 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
7906 | } |
7907 | ||
7908 | /* according to the intel vmx instruction reference, the memory | |
7909 | * operand is read even if it isn't needed (e.g., for type==global) | |
7910 | */ | |
7911 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
7912 | vmx_instruction_info, false, &gva)) | |
7913 | return 1; | |
40352605 JM |
7914 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand, |
7915 | sizeof(operand), &e)) { | |
99b83ac8 WL |
7916 | kvm_inject_page_fault(vcpu, &e); |
7917 | return 1; | |
7918 | } | |
40352605 JM |
7919 | if (operand.vpid >> 16) { |
7920 | nested_vmx_failValid(vcpu, | |
7921 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
7922 | return kvm_skip_emulated_instruction(vcpu); | |
7923 | } | |
99b83ac8 WL |
7924 | |
7925 | switch (type) { | |
bcdde302 | 7926 | case VMX_VPID_EXTENT_INDIVIDUAL_ADDR: |
fd8cb433 | 7927 | if (is_noncanonical_address(operand.gla, vcpu)) { |
40352605 JM |
7928 | nested_vmx_failValid(vcpu, |
7929 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
7930 | return kvm_skip_emulated_instruction(vcpu); | |
7931 | } | |
7932 | /* fall through */ | |
ef697a71 | 7933 | case VMX_VPID_EXTENT_SINGLE_CONTEXT: |
bcdde302 | 7934 | case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL: |
40352605 | 7935 | if (!operand.vpid) { |
bcdde302 JD |
7936 | nested_vmx_failValid(vcpu, |
7937 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7938 | return kvm_skip_emulated_instruction(vcpu); |
bcdde302 JD |
7939 | } |
7940 | break; | |
99b83ac8 | 7941 | case VMX_VPID_EXTENT_ALL_CONTEXT: |
99b83ac8 WL |
7942 | break; |
7943 | default: | |
bcdde302 | 7944 | WARN_ON_ONCE(1); |
6affcbed | 7945 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
7946 | } |
7947 | ||
bcdde302 JD |
7948 | __vmx_flush_tlb(vcpu, vmx->nested.vpid02); |
7949 | nested_vmx_succeed(vcpu); | |
7950 | ||
6affcbed | 7951 | return kvm_skip_emulated_instruction(vcpu); |
a642fc30 PM |
7952 | } |
7953 | ||
843e4330 KH |
7954 | static int handle_pml_full(struct kvm_vcpu *vcpu) |
7955 | { | |
7956 | unsigned long exit_qualification; | |
7957 | ||
7958 | trace_kvm_pml_full(vcpu->vcpu_id); | |
7959 | ||
7960 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7961 | ||
7962 | /* | |
7963 | * PML buffer FULL happened while executing iret from NMI, | |
7964 | * "blocked by NMI" bit has to be set before next VM entry. | |
7965 | */ | |
7966 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && | |
843e4330 KH |
7967 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
7968 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
7969 | GUEST_INTR_STATE_NMI); | |
7970 | ||
7971 | /* | |
7972 | * PML buffer already flushed at beginning of VMEXIT. Nothing to do | |
7973 | * here.., and there's no userspace involvement needed for PML. | |
7974 | */ | |
7975 | return 1; | |
7976 | } | |
7977 | ||
64672c95 YJ |
7978 | static int handle_preemption_timer(struct kvm_vcpu *vcpu) |
7979 | { | |
7980 | kvm_lapic_expired_hv_timer(vcpu); | |
7981 | return 1; | |
7982 | } | |
7983 | ||
41ab9372 BD |
7984 | static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address) |
7985 | { | |
7986 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
41ab9372 BD |
7987 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
7988 | ||
7989 | /* Check for memory type validity */ | |
bb97a016 DH |
7990 | switch (address & VMX_EPTP_MT_MASK) { |
7991 | case VMX_EPTP_MT_UC: | |
41ab9372 BD |
7992 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT)) |
7993 | return false; | |
7994 | break; | |
bb97a016 | 7995 | case VMX_EPTP_MT_WB: |
41ab9372 BD |
7996 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT)) |
7997 | return false; | |
7998 | break; | |
7999 | default: | |
8000 | return false; | |
8001 | } | |
8002 | ||
bb97a016 DH |
8003 | /* only 4 levels page-walk length are valid */ |
8004 | if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4) | |
41ab9372 BD |
8005 | return false; |
8006 | ||
8007 | /* Reserved bits should not be set */ | |
8008 | if (address >> maxphyaddr || ((address >> 7) & 0x1f)) | |
8009 | return false; | |
8010 | ||
8011 | /* AD, if set, should be supported */ | |
bb97a016 | 8012 | if (address & VMX_EPTP_AD_ENABLE_BIT) { |
41ab9372 BD |
8013 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT)) |
8014 | return false; | |
8015 | } | |
8016 | ||
8017 | return true; | |
8018 | } | |
8019 | ||
8020 | static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu, | |
8021 | struct vmcs12 *vmcs12) | |
8022 | { | |
8023 | u32 index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
8024 | u64 address; | |
8025 | bool accessed_dirty; | |
8026 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; | |
8027 | ||
8028 | if (!nested_cpu_has_eptp_switching(vmcs12) || | |
8029 | !nested_cpu_has_ept(vmcs12)) | |
8030 | return 1; | |
8031 | ||
8032 | if (index >= VMFUNC_EPTP_ENTRIES) | |
8033 | return 1; | |
8034 | ||
8035 | ||
8036 | if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT, | |
8037 | &address, index * 8, 8)) | |
8038 | return 1; | |
8039 | ||
bb97a016 | 8040 | accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT); |
41ab9372 BD |
8041 | |
8042 | /* | |
8043 | * If the (L2) guest does a vmfunc to the currently | |
8044 | * active ept pointer, we don't have to do anything else | |
8045 | */ | |
8046 | if (vmcs12->ept_pointer != address) { | |
8047 | if (!valid_ept_address(vcpu, address)) | |
8048 | return 1; | |
8049 | ||
8050 | kvm_mmu_unload(vcpu); | |
8051 | mmu->ept_ad = accessed_dirty; | |
8052 | mmu->base_role.ad_disabled = !accessed_dirty; | |
8053 | vmcs12->ept_pointer = address; | |
8054 | /* | |
8055 | * TODO: Check what's the correct approach in case | |
8056 | * mmu reload fails. Currently, we just let the next | |
8057 | * reload potentially fail | |
8058 | */ | |
8059 | kvm_mmu_reload(vcpu); | |
8060 | } | |
8061 | ||
8062 | return 0; | |
8063 | } | |
8064 | ||
2a499e49 BD |
8065 | static int handle_vmfunc(struct kvm_vcpu *vcpu) |
8066 | { | |
27c42a1b BD |
8067 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8068 | struct vmcs12 *vmcs12; | |
8069 | u32 function = vcpu->arch.regs[VCPU_REGS_RAX]; | |
8070 | ||
8071 | /* | |
8072 | * VMFUNC is only supported for nested guests, but we always enable the | |
8073 | * secondary control for simplicity; for non-nested mode, fake that we | |
8074 | * didn't by injecting #UD. | |
8075 | */ | |
8076 | if (!is_guest_mode(vcpu)) { | |
8077 | kvm_queue_exception(vcpu, UD_VECTOR); | |
8078 | return 1; | |
8079 | } | |
8080 | ||
8081 | vmcs12 = get_vmcs12(vcpu); | |
8082 | if ((vmcs12->vm_function_control & (1 << function)) == 0) | |
8083 | goto fail; | |
41ab9372 BD |
8084 | |
8085 | switch (function) { | |
8086 | case 0: | |
8087 | if (nested_vmx_eptp_switching(vcpu, vmcs12)) | |
8088 | goto fail; | |
8089 | break; | |
8090 | default: | |
8091 | goto fail; | |
8092 | } | |
8093 | return kvm_skip_emulated_instruction(vcpu); | |
27c42a1b BD |
8094 | |
8095 | fail: | |
8096 | nested_vmx_vmexit(vcpu, vmx->exit_reason, | |
8097 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8098 | vmcs_readl(EXIT_QUALIFICATION)); | |
2a499e49 BD |
8099 | return 1; |
8100 | } | |
8101 | ||
6aa8b732 AK |
8102 | /* |
8103 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
8104 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
8105 | * to be done to userspace and return 0. | |
8106 | */ | |
772e0318 | 8107 | static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
8108 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
8109 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 8110 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 8111 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 8112 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
8113 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
8114 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
8115 | [EXIT_REASON_CPUID] = handle_cpuid, | |
8116 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
8117 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
8118 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
8119 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 8120 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 8121 | [EXIT_REASON_INVLPG] = handle_invlpg, |
fee84b07 | 8122 | [EXIT_REASON_RDPMC] = handle_rdpmc, |
c21415e8 | 8123 | [EXIT_REASON_VMCALL] = handle_vmcall, |
27d6c865 | 8124 | [EXIT_REASON_VMCLEAR] = handle_vmclear, |
cd232ad0 | 8125 | [EXIT_REASON_VMLAUNCH] = handle_vmlaunch, |
63846663 | 8126 | [EXIT_REASON_VMPTRLD] = handle_vmptrld, |
6a4d7550 | 8127 | [EXIT_REASON_VMPTRST] = handle_vmptrst, |
49f705c5 | 8128 | [EXIT_REASON_VMREAD] = handle_vmread, |
cd232ad0 | 8129 | [EXIT_REASON_VMRESUME] = handle_vmresume, |
49f705c5 | 8130 | [EXIT_REASON_VMWRITE] = handle_vmwrite, |
ec378aee NHE |
8131 | [EXIT_REASON_VMOFF] = handle_vmoff, |
8132 | [EXIT_REASON_VMON] = handle_vmon, | |
f78e0e2e SY |
8133 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
8134 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
83d4c286 | 8135 | [EXIT_REASON_APIC_WRITE] = handle_apic_write, |
c7c9c56c | 8136 | [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, |
e5edaa01 | 8137 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 8138 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 8139 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 8140 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
8141 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
8142 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 8143 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
87c00572 | 8144 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, |
5f3d45e7 | 8145 | [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, |
87c00572 | 8146 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, |
bfd0a56b | 8147 | [EXIT_REASON_INVEPT] = handle_invept, |
a642fc30 | 8148 | [EXIT_REASON_INVVPID] = handle_invvpid, |
45ec368c | 8149 | [EXIT_REASON_RDRAND] = handle_invalid_op, |
75f4fc8d | 8150 | [EXIT_REASON_RDSEED] = handle_invalid_op, |
f53cd63c WL |
8151 | [EXIT_REASON_XSAVES] = handle_xsaves, |
8152 | [EXIT_REASON_XRSTORS] = handle_xrstors, | |
843e4330 | 8153 | [EXIT_REASON_PML_FULL] = handle_pml_full, |
2a499e49 | 8154 | [EXIT_REASON_VMFUNC] = handle_vmfunc, |
64672c95 | 8155 | [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, |
6aa8b732 AK |
8156 | }; |
8157 | ||
8158 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 8159 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 8160 | |
908a7bdd JK |
8161 | static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, |
8162 | struct vmcs12 *vmcs12) | |
8163 | { | |
8164 | unsigned long exit_qualification; | |
8165 | gpa_t bitmap, last_bitmap; | |
8166 | unsigned int port; | |
8167 | int size; | |
8168 | u8 b; | |
8169 | ||
908a7bdd | 8170 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) |
2f0a6397 | 8171 | return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); |
908a7bdd JK |
8172 | |
8173 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8174 | ||
8175 | port = exit_qualification >> 16; | |
8176 | size = (exit_qualification & 7) + 1; | |
8177 | ||
8178 | last_bitmap = (gpa_t)-1; | |
8179 | b = -1; | |
8180 | ||
8181 | while (size > 0) { | |
8182 | if (port < 0x8000) | |
8183 | bitmap = vmcs12->io_bitmap_a; | |
8184 | else if (port < 0x10000) | |
8185 | bitmap = vmcs12->io_bitmap_b; | |
8186 | else | |
1d804d07 | 8187 | return true; |
908a7bdd JK |
8188 | bitmap += (port & 0x7fff) / 8; |
8189 | ||
8190 | if (last_bitmap != bitmap) | |
54bf36aa | 8191 | if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1)) |
1d804d07 | 8192 | return true; |
908a7bdd | 8193 | if (b & (1 << (port & 7))) |
1d804d07 | 8194 | return true; |
908a7bdd JK |
8195 | |
8196 | port++; | |
8197 | size--; | |
8198 | last_bitmap = bitmap; | |
8199 | } | |
8200 | ||
1d804d07 | 8201 | return false; |
908a7bdd JK |
8202 | } |
8203 | ||
644d711a NHE |
8204 | /* |
8205 | * Return 1 if we should exit from L2 to L1 to handle an MSR access access, | |
8206 | * rather than handle it ourselves in L0. I.e., check whether L1 expressed | |
8207 | * disinterest in the current event (read or write a specific MSR) by using an | |
8208 | * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. | |
8209 | */ | |
8210 | static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, | |
8211 | struct vmcs12 *vmcs12, u32 exit_reason) | |
8212 | { | |
8213 | u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
8214 | gpa_t bitmap; | |
8215 | ||
cbd29cb6 | 8216 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
1d804d07 | 8217 | return true; |
644d711a NHE |
8218 | |
8219 | /* | |
8220 | * The MSR_BITMAP page is divided into four 1024-byte bitmaps, | |
8221 | * for the four combinations of read/write and low/high MSR numbers. | |
8222 | * First we need to figure out which of the four to use: | |
8223 | */ | |
8224 | bitmap = vmcs12->msr_bitmap; | |
8225 | if (exit_reason == EXIT_REASON_MSR_WRITE) | |
8226 | bitmap += 2048; | |
8227 | if (msr_index >= 0xc0000000) { | |
8228 | msr_index -= 0xc0000000; | |
8229 | bitmap += 1024; | |
8230 | } | |
8231 | ||
8232 | /* Then read the msr_index'th bit from this bitmap: */ | |
8233 | if (msr_index < 1024*8) { | |
8234 | unsigned char b; | |
54bf36aa | 8235 | if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1)) |
1d804d07 | 8236 | return true; |
644d711a NHE |
8237 | return 1 & (b >> (msr_index & 7)); |
8238 | } else | |
1d804d07 | 8239 | return true; /* let L1 handle the wrong parameter */ |
644d711a NHE |
8240 | } |
8241 | ||
8242 | /* | |
8243 | * Return 1 if we should exit from L2 to L1 to handle a CR access exit, | |
8244 | * rather than handle it ourselves in L0. I.e., check if L1 wanted to | |
8245 | * intercept (via guest_host_mask etc.) the current event. | |
8246 | */ | |
8247 | static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, | |
8248 | struct vmcs12 *vmcs12) | |
8249 | { | |
8250 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8251 | int cr = exit_qualification & 15; | |
e1d39b17 JS |
8252 | int reg; |
8253 | unsigned long val; | |
644d711a NHE |
8254 | |
8255 | switch ((exit_qualification >> 4) & 3) { | |
8256 | case 0: /* mov to cr */ | |
e1d39b17 JS |
8257 | reg = (exit_qualification >> 8) & 15; |
8258 | val = kvm_register_readl(vcpu, reg); | |
644d711a NHE |
8259 | switch (cr) { |
8260 | case 0: | |
8261 | if (vmcs12->cr0_guest_host_mask & | |
8262 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 8263 | return true; |
644d711a NHE |
8264 | break; |
8265 | case 3: | |
8266 | if ((vmcs12->cr3_target_count >= 1 && | |
8267 | vmcs12->cr3_target_value0 == val) || | |
8268 | (vmcs12->cr3_target_count >= 2 && | |
8269 | vmcs12->cr3_target_value1 == val) || | |
8270 | (vmcs12->cr3_target_count >= 3 && | |
8271 | vmcs12->cr3_target_value2 == val) || | |
8272 | (vmcs12->cr3_target_count >= 4 && | |
8273 | vmcs12->cr3_target_value3 == val)) | |
1d804d07 | 8274 | return false; |
644d711a | 8275 | if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) |
1d804d07 | 8276 | return true; |
644d711a NHE |
8277 | break; |
8278 | case 4: | |
8279 | if (vmcs12->cr4_guest_host_mask & | |
8280 | (vmcs12->cr4_read_shadow ^ val)) | |
1d804d07 | 8281 | return true; |
644d711a NHE |
8282 | break; |
8283 | case 8: | |
8284 | if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) | |
1d804d07 | 8285 | return true; |
644d711a NHE |
8286 | break; |
8287 | } | |
8288 | break; | |
8289 | case 2: /* clts */ | |
8290 | if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && | |
8291 | (vmcs12->cr0_read_shadow & X86_CR0_TS)) | |
1d804d07 | 8292 | return true; |
644d711a NHE |
8293 | break; |
8294 | case 1: /* mov from cr */ | |
8295 | switch (cr) { | |
8296 | case 3: | |
8297 | if (vmcs12->cpu_based_vm_exec_control & | |
8298 | CPU_BASED_CR3_STORE_EXITING) | |
1d804d07 | 8299 | return true; |
644d711a NHE |
8300 | break; |
8301 | case 8: | |
8302 | if (vmcs12->cpu_based_vm_exec_control & | |
8303 | CPU_BASED_CR8_STORE_EXITING) | |
1d804d07 | 8304 | return true; |
644d711a NHE |
8305 | break; |
8306 | } | |
8307 | break; | |
8308 | case 3: /* lmsw */ | |
8309 | /* | |
8310 | * lmsw can change bits 1..3 of cr0, and only set bit 0 of | |
8311 | * cr0. Other attempted changes are ignored, with no exit. | |
8312 | */ | |
e1d39b17 | 8313 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
644d711a NHE |
8314 | if (vmcs12->cr0_guest_host_mask & 0xe & |
8315 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 8316 | return true; |
644d711a NHE |
8317 | if ((vmcs12->cr0_guest_host_mask & 0x1) && |
8318 | !(vmcs12->cr0_read_shadow & 0x1) && | |
8319 | (val & 0x1)) | |
1d804d07 | 8320 | return true; |
644d711a NHE |
8321 | break; |
8322 | } | |
1d804d07 | 8323 | return false; |
644d711a NHE |
8324 | } |
8325 | ||
8326 | /* | |
8327 | * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we | |
8328 | * should handle it ourselves in L0 (and then continue L2). Only call this | |
8329 | * when in is_guest_mode (L2). | |
8330 | */ | |
7313c698 | 8331 | static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason) |
644d711a | 8332 | { |
644d711a NHE |
8333 | u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
8334 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8335 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
8336 | ||
4f350c6d JM |
8337 | if (vmx->nested.nested_run_pending) |
8338 | return false; | |
8339 | ||
8340 | if (unlikely(vmx->fail)) { | |
8341 | pr_info_ratelimited("%s failed vm entry %x\n", __func__, | |
8342 | vmcs_read32(VM_INSTRUCTION_ERROR)); | |
8343 | return true; | |
8344 | } | |
542060ea | 8345 | |
c9f04407 DM |
8346 | /* |
8347 | * The host physical addresses of some pages of guest memory | |
8348 | * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU | |
8349 | * may write to these pages via their host physical address while | |
8350 | * L2 is running, bypassing any address-translation-based dirty | |
8351 | * tracking (e.g. EPT write protection). | |
8352 | * | |
8353 | * Mark them dirty on every exit from L2 to prevent them from | |
8354 | * getting out of sync with dirty tracking. | |
8355 | */ | |
8356 | nested_mark_vmcs12_pages_dirty(vcpu); | |
8357 | ||
4f350c6d JM |
8358 | trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason, |
8359 | vmcs_readl(EXIT_QUALIFICATION), | |
8360 | vmx->idt_vectoring_info, | |
8361 | intr_info, | |
8362 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8363 | KVM_ISA_VMX); | |
644d711a NHE |
8364 | |
8365 | switch (exit_reason) { | |
8366 | case EXIT_REASON_EXCEPTION_NMI: | |
ef85b673 | 8367 | if (is_nmi(intr_info)) |
1d804d07 | 8368 | return false; |
644d711a | 8369 | else if (is_page_fault(intr_info)) |
52a5c155 | 8370 | return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept; |
e504c909 | 8371 | else if (is_no_device(intr_info) && |
ccf9844e | 8372 | !(vmcs12->guest_cr0 & X86_CR0_TS)) |
1d804d07 | 8373 | return false; |
6f05485d JK |
8374 | else if (is_debug(intr_info) && |
8375 | vcpu->guest_debug & | |
8376 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
8377 | return false; | |
8378 | else if (is_breakpoint(intr_info) && | |
8379 | vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
8380 | return false; | |
644d711a NHE |
8381 | return vmcs12->exception_bitmap & |
8382 | (1u << (intr_info & INTR_INFO_VECTOR_MASK)); | |
8383 | case EXIT_REASON_EXTERNAL_INTERRUPT: | |
1d804d07 | 8384 | return false; |
644d711a | 8385 | case EXIT_REASON_TRIPLE_FAULT: |
1d804d07 | 8386 | return true; |
644d711a | 8387 | case EXIT_REASON_PENDING_INTERRUPT: |
3b656cf7 | 8388 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING); |
644d711a | 8389 | case EXIT_REASON_NMI_WINDOW: |
3b656cf7 | 8390 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING); |
644d711a | 8391 | case EXIT_REASON_TASK_SWITCH: |
1d804d07 | 8392 | return true; |
644d711a | 8393 | case EXIT_REASON_CPUID: |
1d804d07 | 8394 | return true; |
644d711a NHE |
8395 | case EXIT_REASON_HLT: |
8396 | return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); | |
8397 | case EXIT_REASON_INVD: | |
1d804d07 | 8398 | return true; |
644d711a NHE |
8399 | case EXIT_REASON_INVLPG: |
8400 | return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
8401 | case EXIT_REASON_RDPMC: | |
8402 | return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); | |
a5f46457 | 8403 | case EXIT_REASON_RDRAND: |
736fdf72 | 8404 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING); |
a5f46457 | 8405 | case EXIT_REASON_RDSEED: |
736fdf72 | 8406 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING); |
b3a2a907 | 8407 | case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP: |
644d711a NHE |
8408 | return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); |
8409 | case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: | |
8410 | case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: | |
8411 | case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD: | |
8412 | case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE: | |
8413 | case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: | |
a642fc30 | 8414 | case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: |
644d711a NHE |
8415 | /* |
8416 | * VMX instructions trap unconditionally. This allows L1 to | |
8417 | * emulate them for its L2 guest, i.e., allows 3-level nesting! | |
8418 | */ | |
1d804d07 | 8419 | return true; |
644d711a NHE |
8420 | case EXIT_REASON_CR_ACCESS: |
8421 | return nested_vmx_exit_handled_cr(vcpu, vmcs12); | |
8422 | case EXIT_REASON_DR_ACCESS: | |
8423 | return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); | |
8424 | case EXIT_REASON_IO_INSTRUCTION: | |
908a7bdd | 8425 | return nested_vmx_exit_handled_io(vcpu, vmcs12); |
1b07304c PB |
8426 | case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR: |
8427 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC); | |
644d711a NHE |
8428 | case EXIT_REASON_MSR_READ: |
8429 | case EXIT_REASON_MSR_WRITE: | |
8430 | return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); | |
8431 | case EXIT_REASON_INVALID_STATE: | |
1d804d07 | 8432 | return true; |
644d711a NHE |
8433 | case EXIT_REASON_MWAIT_INSTRUCTION: |
8434 | return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); | |
5f3d45e7 MD |
8435 | case EXIT_REASON_MONITOR_TRAP_FLAG: |
8436 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); | |
644d711a NHE |
8437 | case EXIT_REASON_MONITOR_INSTRUCTION: |
8438 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); | |
8439 | case EXIT_REASON_PAUSE_INSTRUCTION: | |
8440 | return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || | |
8441 | nested_cpu_has2(vmcs12, | |
8442 | SECONDARY_EXEC_PAUSE_LOOP_EXITING); | |
8443 | case EXIT_REASON_MCE_DURING_VMENTRY: | |
1d804d07 | 8444 | return false; |
644d711a | 8445 | case EXIT_REASON_TPR_BELOW_THRESHOLD: |
a7c0b07d | 8446 | return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); |
644d711a NHE |
8447 | case EXIT_REASON_APIC_ACCESS: |
8448 | return nested_cpu_has2(vmcs12, | |
8449 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
82f0dd4b | 8450 | case EXIT_REASON_APIC_WRITE: |
608406e2 WV |
8451 | case EXIT_REASON_EOI_INDUCED: |
8452 | /* apic_write and eoi_induced should exit unconditionally. */ | |
1d804d07 | 8453 | return true; |
644d711a | 8454 | case EXIT_REASON_EPT_VIOLATION: |
2b1be677 NHE |
8455 | /* |
8456 | * L0 always deals with the EPT violation. If nested EPT is | |
8457 | * used, and the nested mmu code discovers that the address is | |
8458 | * missing in the guest EPT table (EPT12), the EPT violation | |
8459 | * will be injected with nested_ept_inject_page_fault() | |
8460 | */ | |
1d804d07 | 8461 | return false; |
644d711a | 8462 | case EXIT_REASON_EPT_MISCONFIG: |
2b1be677 NHE |
8463 | /* |
8464 | * L2 never uses directly L1's EPT, but rather L0's own EPT | |
8465 | * table (shadow on EPT) or a merged EPT table that L0 built | |
8466 | * (EPT on EPT). So any problems with the structure of the | |
8467 | * table is L0's fault. | |
8468 | */ | |
1d804d07 | 8469 | return false; |
90a2db6d PB |
8470 | case EXIT_REASON_INVPCID: |
8471 | return | |
8472 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) && | |
8473 | nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
644d711a NHE |
8474 | case EXIT_REASON_WBINVD: |
8475 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); | |
8476 | case EXIT_REASON_XSETBV: | |
1d804d07 | 8477 | return true; |
81dc01f7 WL |
8478 | case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: |
8479 | /* | |
8480 | * This should never happen, since it is not possible to | |
8481 | * set XSS to a non-zero value---neither in L1 nor in L2. | |
8482 | * If if it were, XSS would have to be checked against | |
8483 | * the XSS exit bitmap in vmcs12. | |
8484 | */ | |
8485 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); | |
55123e3c WL |
8486 | case EXIT_REASON_PREEMPTION_TIMER: |
8487 | return false; | |
ab007cc9 | 8488 | case EXIT_REASON_PML_FULL: |
03efce6f | 8489 | /* We emulate PML support to L1. */ |
ab007cc9 | 8490 | return false; |
2a499e49 BD |
8491 | case EXIT_REASON_VMFUNC: |
8492 | /* VM functions are emulated through L2->L0 vmexits. */ | |
8493 | return false; | |
644d711a | 8494 | default: |
1d804d07 | 8495 | return true; |
644d711a NHE |
8496 | } |
8497 | } | |
8498 | ||
7313c698 PB |
8499 | static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason) |
8500 | { | |
8501 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
8502 | ||
8503 | /* | |
8504 | * At this point, the exit interruption info in exit_intr_info | |
8505 | * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT | |
8506 | * we need to query the in-kernel LAPIC. | |
8507 | */ | |
8508 | WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT); | |
8509 | if ((exit_intr_info & | |
8510 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) == | |
8511 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) { | |
8512 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
8513 | vmcs12->vm_exit_intr_error_code = | |
8514 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
8515 | } | |
8516 | ||
8517 | nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info, | |
8518 | vmcs_readl(EXIT_QUALIFICATION)); | |
8519 | return 1; | |
8520 | } | |
8521 | ||
586f9607 AK |
8522 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
8523 | { | |
8524 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
8525 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
8526 | } | |
8527 | ||
a3eaa864 | 8528 | static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) |
843e4330 | 8529 | { |
a3eaa864 KH |
8530 | if (vmx->pml_pg) { |
8531 | __free_page(vmx->pml_pg); | |
8532 | vmx->pml_pg = NULL; | |
8533 | } | |
843e4330 KH |
8534 | } |
8535 | ||
54bf36aa | 8536 | static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) |
843e4330 | 8537 | { |
54bf36aa | 8538 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
843e4330 KH |
8539 | u64 *pml_buf; |
8540 | u16 pml_idx; | |
8541 | ||
8542 | pml_idx = vmcs_read16(GUEST_PML_INDEX); | |
8543 | ||
8544 | /* Do nothing if PML buffer is empty */ | |
8545 | if (pml_idx == (PML_ENTITY_NUM - 1)) | |
8546 | return; | |
8547 | ||
8548 | /* PML index always points to next available PML buffer entity */ | |
8549 | if (pml_idx >= PML_ENTITY_NUM) | |
8550 | pml_idx = 0; | |
8551 | else | |
8552 | pml_idx++; | |
8553 | ||
8554 | pml_buf = page_address(vmx->pml_pg); | |
8555 | for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { | |
8556 | u64 gpa; | |
8557 | ||
8558 | gpa = pml_buf[pml_idx]; | |
8559 | WARN_ON(gpa & (PAGE_SIZE - 1)); | |
54bf36aa | 8560 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
843e4330 KH |
8561 | } |
8562 | ||
8563 | /* reset PML index */ | |
8564 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
8565 | } | |
8566 | ||
8567 | /* | |
8568 | * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. | |
8569 | * Called before reporting dirty_bitmap to userspace. | |
8570 | */ | |
8571 | static void kvm_flush_pml_buffers(struct kvm *kvm) | |
8572 | { | |
8573 | int i; | |
8574 | struct kvm_vcpu *vcpu; | |
8575 | /* | |
8576 | * We only need to kick vcpu out of guest mode here, as PML buffer | |
8577 | * is flushed at beginning of all VMEXITs, and it's obvious that only | |
8578 | * vcpus running in guest are possible to have unflushed GPAs in PML | |
8579 | * buffer. | |
8580 | */ | |
8581 | kvm_for_each_vcpu(i, vcpu, kvm) | |
8582 | kvm_vcpu_kick(vcpu); | |
8583 | } | |
8584 | ||
4eb64dce PB |
8585 | static void vmx_dump_sel(char *name, uint32_t sel) |
8586 | { | |
8587 | pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", | |
96794e4e | 8588 | name, vmcs_read16(sel), |
4eb64dce PB |
8589 | vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), |
8590 | vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), | |
8591 | vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); | |
8592 | } | |
8593 | ||
8594 | static void vmx_dump_dtsel(char *name, uint32_t limit) | |
8595 | { | |
8596 | pr_err("%s limit=0x%08x, base=0x%016lx\n", | |
8597 | name, vmcs_read32(limit), | |
8598 | vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); | |
8599 | } | |
8600 | ||
8601 | static void dump_vmcs(void) | |
8602 | { | |
8603 | u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); | |
8604 | u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); | |
8605 | u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
8606 | u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); | |
8607 | u32 secondary_exec_control = 0; | |
8608 | unsigned long cr4 = vmcs_readl(GUEST_CR4); | |
f3531054 | 8609 | u64 efer = vmcs_read64(GUEST_IA32_EFER); |
4eb64dce PB |
8610 | int i, n; |
8611 | ||
8612 | if (cpu_has_secondary_exec_ctrls()) | |
8613 | secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8614 | ||
8615 | pr_err("*** Guest State ***\n"); | |
8616 | pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8617 | vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), | |
8618 | vmcs_readl(CR0_GUEST_HOST_MASK)); | |
8619 | pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8620 | cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); | |
8621 | pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); | |
8622 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && | |
8623 | (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) | |
8624 | { | |
845c5b40 PB |
8625 | pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", |
8626 | vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); | |
8627 | pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", | |
8628 | vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); | |
4eb64dce PB |
8629 | } |
8630 | pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", | |
8631 | vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); | |
8632 | pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", | |
8633 | vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); | |
8634 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8635 | vmcs_readl(GUEST_SYSENTER_ESP), | |
8636 | vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); | |
8637 | vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); | |
8638 | vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); | |
8639 | vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); | |
8640 | vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); | |
8641 | vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); | |
8642 | vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); | |
8643 | vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); | |
8644 | vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); | |
8645 | vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); | |
8646 | vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); | |
8647 | if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || | |
8648 | (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) | |
845c5b40 PB |
8649 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8650 | efer, vmcs_read64(GUEST_IA32_PAT)); | |
8651 | pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", | |
8652 | vmcs_read64(GUEST_IA32_DEBUGCTL), | |
4eb64dce PB |
8653 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); |
8654 | if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
845c5b40 PB |
8655 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8656 | vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce | 8657 | if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) |
845c5b40 | 8658 | pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); |
4eb64dce PB |
8659 | pr_err("Interruptibility = %08x ActivityState = %08x\n", |
8660 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), | |
8661 | vmcs_read32(GUEST_ACTIVITY_STATE)); | |
8662 | if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) | |
8663 | pr_err("InterruptStatus = %04x\n", | |
8664 | vmcs_read16(GUEST_INTR_STATUS)); | |
8665 | ||
8666 | pr_err("*** Host State ***\n"); | |
8667 | pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", | |
8668 | vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); | |
8669 | pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", | |
8670 | vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), | |
8671 | vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), | |
8672 | vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), | |
8673 | vmcs_read16(HOST_TR_SELECTOR)); | |
8674 | pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", | |
8675 | vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), | |
8676 | vmcs_readl(HOST_TR_BASE)); | |
8677 | pr_err("GDTBase=%016lx IDTBase=%016lx\n", | |
8678 | vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); | |
8679 | pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", | |
8680 | vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), | |
8681 | vmcs_readl(HOST_CR4)); | |
8682 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8683 | vmcs_readl(HOST_IA32_SYSENTER_ESP), | |
8684 | vmcs_read32(HOST_IA32_SYSENTER_CS), | |
8685 | vmcs_readl(HOST_IA32_SYSENTER_EIP)); | |
8686 | if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) | |
845c5b40 PB |
8687 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8688 | vmcs_read64(HOST_IA32_EFER), | |
8689 | vmcs_read64(HOST_IA32_PAT)); | |
4eb64dce | 8690 | if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
845c5b40 PB |
8691 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8692 | vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce PB |
8693 | |
8694 | pr_err("*** Control State ***\n"); | |
8695 | pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", | |
8696 | pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); | |
8697 | pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); | |
8698 | pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", | |
8699 | vmcs_read32(EXCEPTION_BITMAP), | |
8700 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), | |
8701 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); | |
8702 | pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8703 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
8704 | vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), | |
8705 | vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); | |
8706 | pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8707 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8708 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8709 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
8710 | pr_err(" reason=%08x qualification=%016lx\n", | |
8711 | vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); | |
8712 | pr_err("IDTVectoring: info=%08x errcode=%08x\n", | |
8713 | vmcs_read32(IDT_VECTORING_INFO_FIELD), | |
8714 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
845c5b40 | 8715 | pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); |
8cfe9866 | 8716 | if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) |
845c5b40 PB |
8717 | pr_err("TSC Multiplier = 0x%016llx\n", |
8718 | vmcs_read64(TSC_MULTIPLIER)); | |
4eb64dce PB |
8719 | if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) |
8720 | pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); | |
8721 | if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) | |
8722 | pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); | |
8723 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) | |
845c5b40 | 8724 | pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); |
4eb64dce PB |
8725 | n = vmcs_read32(CR3_TARGET_COUNT); |
8726 | for (i = 0; i + 1 < n; i += 4) | |
8727 | pr_err("CR3 target%u=%016lx target%u=%016lx\n", | |
8728 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), | |
8729 | i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); | |
8730 | if (i < n) | |
8731 | pr_err("CR3 target%u=%016lx\n", | |
8732 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); | |
8733 | if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) | |
8734 | pr_err("PLE Gap=%08x Window=%08x\n", | |
8735 | vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); | |
8736 | if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) | |
8737 | pr_err("Virtual processor ID = 0x%04x\n", | |
8738 | vmcs_read16(VIRTUAL_PROCESSOR_ID)); | |
8739 | } | |
8740 | ||
6aa8b732 AK |
8741 | /* |
8742 | * The guest has exited. See if we can fix it or if we need userspace | |
8743 | * assistance. | |
8744 | */ | |
851ba692 | 8745 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 8746 | { |
29bd8a78 | 8747 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 8748 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 8749 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 8750 | |
8b89fe1f PB |
8751 | trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); |
8752 | ||
843e4330 KH |
8753 | /* |
8754 | * Flush logged GPAs PML buffer, this will make dirty_bitmap more | |
8755 | * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before | |
8756 | * querying dirty_bitmap, we only need to kick all vcpus out of guest | |
8757 | * mode as if vcpus is in root mode, the PML buffer must has been | |
8758 | * flushed already. | |
8759 | */ | |
8760 | if (enable_pml) | |
54bf36aa | 8761 | vmx_flush_pml_buffer(vcpu); |
843e4330 | 8762 | |
80ced186 | 8763 | /* If guest state is invalid, start emulating */ |
14168786 | 8764 | if (vmx->emulation_required) |
80ced186 | 8765 | return handle_invalid_guest_state(vcpu); |
1d5a4d9b | 8766 | |
7313c698 PB |
8767 | if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) |
8768 | return nested_vmx_reflect_vmexit(vcpu, exit_reason); | |
644d711a | 8769 | |
5120702e | 8770 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
4eb64dce | 8771 | dump_vmcs(); |
5120702e MG |
8772 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8773 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
8774 | = exit_reason; | |
8775 | return 0; | |
8776 | } | |
8777 | ||
29bd8a78 | 8778 | if (unlikely(vmx->fail)) { |
851ba692 AK |
8779 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8780 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
8781 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
8782 | return 0; | |
8783 | } | |
6aa8b732 | 8784 | |
b9bf6882 XG |
8785 | /* |
8786 | * Note: | |
8787 | * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by | |
8788 | * delivery event since it indicates guest is accessing MMIO. | |
8789 | * The vm-exit can be triggered again after return to guest that | |
8790 | * will cause infinite loop. | |
8791 | */ | |
d77c26fc | 8792 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 8793 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac | 8794 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
b244c9fc | 8795 | exit_reason != EXIT_REASON_PML_FULL && |
b9bf6882 XG |
8796 | exit_reason != EXIT_REASON_TASK_SWITCH)) { |
8797 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
8798 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; | |
70bcd708 | 8799 | vcpu->run->internal.ndata = 3; |
b9bf6882 XG |
8800 | vcpu->run->internal.data[0] = vectoring_info; |
8801 | vcpu->run->internal.data[1] = exit_reason; | |
70bcd708 PB |
8802 | vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; |
8803 | if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { | |
8804 | vcpu->run->internal.ndata++; | |
8805 | vcpu->run->internal.data[3] = | |
8806 | vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
8807 | } | |
b9bf6882 XG |
8808 | return 0; |
8809 | } | |
3b86cd99 | 8810 | |
6aa8b732 AK |
8811 | if (exit_reason < kvm_vmx_max_exit_handlers |
8812 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 8813 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 8814 | else { |
6c6c5e03 RK |
8815 | vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", |
8816 | exit_reason); | |
2bc19dc3 MT |
8817 | kvm_queue_exception(vcpu, UD_VECTOR); |
8818 | return 1; | |
6aa8b732 | 8819 | } |
6aa8b732 AK |
8820 | } |
8821 | ||
95ba8273 | 8822 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 8823 | { |
a7c0b07d WL |
8824 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
8825 | ||
8826 | if (is_guest_mode(vcpu) && | |
8827 | nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
8828 | return; | |
8829 | ||
95ba8273 | 8830 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
8831 | vmcs_write32(TPR_THRESHOLD, 0); |
8832 | return; | |
8833 | } | |
8834 | ||
95ba8273 | 8835 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
8836 | } |
8837 | ||
8d14695f YZ |
8838 | static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
8839 | { | |
8840 | u32 sec_exec_control; | |
8841 | ||
dccbfcf5 RK |
8842 | /* Postpone execution until vmcs01 is the current VMCS. */ |
8843 | if (is_guest_mode(vcpu)) { | |
8844 | to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true; | |
8845 | return; | |
8846 | } | |
8847 | ||
f6e90f9e | 8848 | if (!cpu_has_vmx_virtualize_x2apic_mode()) |
8d14695f YZ |
8849 | return; |
8850 | ||
35754c98 | 8851 | if (!cpu_need_tpr_shadow(vcpu)) |
8d14695f YZ |
8852 | return; |
8853 | ||
8854 | sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8855 | ||
8856 | if (set) { | |
8857 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
8858 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8859 | } else { | |
8860 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8861 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
fb6c8198 | 8862 | vmx_flush_tlb_ept_only(vcpu); |
8d14695f YZ |
8863 | } |
8864 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control); | |
8865 | ||
8866 | vmx_set_msr_bitmap(vcpu); | |
8867 | } | |
8868 | ||
38b99173 TC |
8869 | static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) |
8870 | { | |
8871 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8872 | ||
8873 | /* | |
8874 | * Currently we do not handle the nested case where L2 has an | |
8875 | * APIC access page of its own; that page is still pinned. | |
8876 | * Hence, we skip the case where the VCPU is in guest mode _and_ | |
8877 | * L1 prepared an APIC access page for L2. | |
8878 | * | |
8879 | * For the case where L1 and L2 share the same APIC access page | |
8880 | * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear | |
8881 | * in the vmcs12), this function will only update either the vmcs01 | |
8882 | * or the vmcs02. If the former, the vmcs02 will be updated by | |
8883 | * prepare_vmcs02. If the latter, the vmcs01 will be updated in | |
8884 | * the next L2->L1 exit. | |
8885 | */ | |
8886 | if (!is_guest_mode(vcpu) || | |
4f2777bc | 8887 | !nested_cpu_has2(get_vmcs12(&vmx->vcpu), |
fb6c8198 | 8888 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { |
38b99173 | 8889 | vmcs_write64(APIC_ACCESS_ADDR, hpa); |
fb6c8198 JM |
8890 | vmx_flush_tlb_ept_only(vcpu); |
8891 | } | |
38b99173 TC |
8892 | } |
8893 | ||
67c9dddc | 8894 | static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
c7c9c56c YZ |
8895 | { |
8896 | u16 status; | |
8897 | u8 old; | |
8898 | ||
67c9dddc PB |
8899 | if (max_isr == -1) |
8900 | max_isr = 0; | |
c7c9c56c YZ |
8901 | |
8902 | status = vmcs_read16(GUEST_INTR_STATUS); | |
8903 | old = status >> 8; | |
67c9dddc | 8904 | if (max_isr != old) { |
c7c9c56c | 8905 | status &= 0xff; |
67c9dddc | 8906 | status |= max_isr << 8; |
c7c9c56c YZ |
8907 | vmcs_write16(GUEST_INTR_STATUS, status); |
8908 | } | |
8909 | } | |
8910 | ||
8911 | static void vmx_set_rvi(int vector) | |
8912 | { | |
8913 | u16 status; | |
8914 | u8 old; | |
8915 | ||
4114c27d WW |
8916 | if (vector == -1) |
8917 | vector = 0; | |
8918 | ||
c7c9c56c YZ |
8919 | status = vmcs_read16(GUEST_INTR_STATUS); |
8920 | old = (u8)status & 0xff; | |
8921 | if ((u8)vector != old) { | |
8922 | status &= ~0xff; | |
8923 | status |= (u8)vector; | |
8924 | vmcs_write16(GUEST_INTR_STATUS, status); | |
8925 | } | |
8926 | } | |
8927 | ||
8928 | static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
8929 | { | |
4114c27d WW |
8930 | if (!is_guest_mode(vcpu)) { |
8931 | vmx_set_rvi(max_irr); | |
8932 | return; | |
8933 | } | |
8934 | ||
c7c9c56c YZ |
8935 | if (max_irr == -1) |
8936 | return; | |
8937 | ||
963fee16 | 8938 | /* |
4114c27d WW |
8939 | * In guest mode. If a vmexit is needed, vmx_check_nested_events |
8940 | * handles it. | |
963fee16 | 8941 | */ |
4114c27d | 8942 | if (nested_exit_on_intr(vcpu)) |
963fee16 WL |
8943 | return; |
8944 | ||
963fee16 | 8945 | /* |
4114c27d | 8946 | * Else, fall back to pre-APICv interrupt injection since L2 |
963fee16 WL |
8947 | * is run without virtual interrupt delivery. |
8948 | */ | |
8949 | if (!kvm_event_needs_reinjection(vcpu) && | |
8950 | vmx_interrupt_allowed(vcpu)) { | |
8951 | kvm_queue_interrupt(vcpu, max_irr, false); | |
8952 | vmx_inject_irq(vcpu); | |
8953 | } | |
c7c9c56c YZ |
8954 | } |
8955 | ||
76dfafd5 | 8956 | static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) |
810e6def PB |
8957 | { |
8958 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
76dfafd5 | 8959 | int max_irr; |
810e6def | 8960 | |
76dfafd5 PB |
8961 | WARN_ON(!vcpu->arch.apicv_active); |
8962 | if (pi_test_on(&vmx->pi_desc)) { | |
8963 | pi_clear_on(&vmx->pi_desc); | |
8964 | /* | |
8965 | * IOMMU can write to PIR.ON, so the barrier matters even on UP. | |
8966 | * But on x86 this is just a compiler barrier anyway. | |
8967 | */ | |
8968 | smp_mb__after_atomic(); | |
8969 | max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir); | |
8970 | } else { | |
8971 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
8972 | } | |
8973 | vmx_hwapic_irr_update(vcpu, max_irr); | |
8974 | return max_irr; | |
810e6def PB |
8975 | } |
8976 | ||
6308630b | 8977 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c | 8978 | { |
d62caabb | 8979 | if (!kvm_vcpu_apicv_active(vcpu)) |
3d81bc7e YZ |
8980 | return; |
8981 | ||
c7c9c56c YZ |
8982 | vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); |
8983 | vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); | |
8984 | vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); | |
8985 | vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); | |
8986 | } | |
8987 | ||
967235d3 PB |
8988 | static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) |
8989 | { | |
8990 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8991 | ||
8992 | pi_clear_on(&vmx->pi_desc); | |
8993 | memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); | |
8994 | } | |
8995 | ||
51aa01d1 | 8996 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 8997 | { |
48ae0fb4 JM |
8998 | u32 exit_intr_info = 0; |
8999 | u16 basic_exit_reason = (u16)vmx->exit_reason; | |
00eba012 | 9000 | |
48ae0fb4 JM |
9001 | if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY |
9002 | || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI)) | |
00eba012 AK |
9003 | return; |
9004 | ||
48ae0fb4 JM |
9005 | if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) |
9006 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9007 | vmx->exit_intr_info = exit_intr_info; | |
a0861c02 | 9008 | |
1261bfa3 WL |
9009 | /* if exit due to PF check for async PF */ |
9010 | if (is_page_fault(exit_intr_info)) | |
9011 | vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); | |
9012 | ||
a0861c02 | 9013 | /* Handle machine checks before interrupts are enabled */ |
48ae0fb4 JM |
9014 | if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY || |
9015 | is_machine_check(exit_intr_info)) | |
a0861c02 AK |
9016 | kvm_machine_check(); |
9017 | ||
20f65983 | 9018 | /* We need to handle NMIs before interrupts are enabled */ |
ef85b673 | 9019 | if (is_nmi(exit_intr_info)) { |
ff9d07a0 | 9020 | kvm_before_handle_nmi(&vmx->vcpu); |
20f65983 | 9021 | asm("int $2"); |
ff9d07a0 ZY |
9022 | kvm_after_handle_nmi(&vmx->vcpu); |
9023 | } | |
51aa01d1 | 9024 | } |
20f65983 | 9025 | |
a547c6db YZ |
9026 | static void vmx_handle_external_intr(struct kvm_vcpu *vcpu) |
9027 | { | |
9028 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9029 | ||
a547c6db YZ |
9030 | if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK)) |
9031 | == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) { | |
9032 | unsigned int vector; | |
9033 | unsigned long entry; | |
9034 | gate_desc *desc; | |
9035 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9036 | #ifdef CONFIG_X86_64 | |
9037 | unsigned long tmp; | |
9038 | #endif | |
9039 | ||
9040 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
9041 | desc = (gate_desc *)vmx->host_idt_base + vector; | |
64b163fa | 9042 | entry = gate_offset(desc); |
a547c6db YZ |
9043 | asm volatile( |
9044 | #ifdef CONFIG_X86_64 | |
9045 | "mov %%" _ASM_SP ", %[sp]\n\t" | |
9046 | "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" | |
9047 | "push $%c[ss]\n\t" | |
9048 | "push %[sp]\n\t" | |
9049 | #endif | |
9050 | "pushf\n\t" | |
a547c6db YZ |
9051 | __ASM_SIZE(push) " $%c[cs]\n\t" |
9052 | "call *%[entry]\n\t" | |
9053 | : | |
9054 | #ifdef CONFIG_X86_64 | |
3f62de5f | 9055 | [sp]"=&r"(tmp), |
a547c6db | 9056 | #endif |
f5caf621 | 9057 | ASM_CALL_CONSTRAINT |
a547c6db YZ |
9058 | : |
9059 | [entry]"r"(entry), | |
9060 | [ss]"i"(__KERNEL_DS), | |
9061 | [cs]"i"(__KERNEL_CS) | |
9062 | ); | |
f2485b3e | 9063 | } |
a547c6db | 9064 | } |
c207aee4 | 9065 | STACK_FRAME_NON_STANDARD(vmx_handle_external_intr); |
a547c6db | 9066 | |
6d396b55 PB |
9067 | static bool vmx_has_high_real_mode_segbase(void) |
9068 | { | |
9069 | return enable_unrestricted_guest || emulate_invalid_guest_state; | |
9070 | } | |
9071 | ||
da8999d3 LJ |
9072 | static bool vmx_mpx_supported(void) |
9073 | { | |
9074 | return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && | |
9075 | (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); | |
9076 | } | |
9077 | ||
55412b2e WL |
9078 | static bool vmx_xsaves_supported(void) |
9079 | { | |
9080 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
9081 | SECONDARY_EXEC_XSAVES; | |
9082 | } | |
9083 | ||
51aa01d1 AK |
9084 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
9085 | { | |
c5ca8e57 | 9086 | u32 exit_intr_info; |
51aa01d1 AK |
9087 | bool unblock_nmi; |
9088 | u8 vector; | |
9089 | bool idtv_info_valid; | |
9090 | ||
9091 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 9092 | |
4c4a6f79 | 9093 | if (vmx->loaded_vmcs->nmi_known_unmasked) |
2c82878b PB |
9094 | return; |
9095 | /* | |
9096 | * Can't use vmx->exit_intr_info since we're not sure what | |
9097 | * the exit reason is. | |
9098 | */ | |
9099 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9100 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | |
9101 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
9102 | /* | |
9103 | * SDM 3: 27.7.1.2 (September 2008) | |
9104 | * Re-set bit "block by NMI" before VM entry if vmexit caused by | |
9105 | * a guest IRET fault. | |
9106 | * SDM 3: 23.2.2 (September 2008) | |
9107 | * Bit 12 is undefined in any of the following cases: | |
9108 | * If the VM exit sets the valid bit in the IDT-vectoring | |
9109 | * information field. | |
9110 | * If the VM exit is due to a double fault. | |
9111 | */ | |
9112 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && | |
9113 | vector != DF_VECTOR && !idtv_info_valid) | |
9114 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
9115 | GUEST_INTR_STATE_NMI); | |
9116 | else | |
4c4a6f79 | 9117 | vmx->loaded_vmcs->nmi_known_unmasked = |
2c82878b PB |
9118 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) |
9119 | & GUEST_INTR_STATE_NMI); | |
51aa01d1 AK |
9120 | } |
9121 | ||
3ab66e8a | 9122 | static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, |
83422e17 AK |
9123 | u32 idt_vectoring_info, |
9124 | int instr_len_field, | |
9125 | int error_code_field) | |
51aa01d1 | 9126 | { |
51aa01d1 AK |
9127 | u8 vector; |
9128 | int type; | |
9129 | bool idtv_info_valid; | |
9130 | ||
9131 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 9132 | |
3ab66e8a JK |
9133 | vcpu->arch.nmi_injected = false; |
9134 | kvm_clear_exception_queue(vcpu); | |
9135 | kvm_clear_interrupt_queue(vcpu); | |
37b96e98 GN |
9136 | |
9137 | if (!idtv_info_valid) | |
9138 | return; | |
9139 | ||
3ab66e8a | 9140 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3842d135 | 9141 | |
668f612f AK |
9142 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
9143 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 9144 | |
64a7ec06 | 9145 | switch (type) { |
37b96e98 | 9146 | case INTR_TYPE_NMI_INTR: |
3ab66e8a | 9147 | vcpu->arch.nmi_injected = true; |
668f612f | 9148 | /* |
7b4a25cb | 9149 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
9150 | * Clear bit "block by NMI" before VM entry if a NMI |
9151 | * delivery faulted. | |
668f612f | 9152 | */ |
3ab66e8a | 9153 | vmx_set_nmi_mask(vcpu, false); |
37b96e98 | 9154 | break; |
37b96e98 | 9155 | case INTR_TYPE_SOFT_EXCEPTION: |
3ab66e8a | 9156 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f GN |
9157 | /* fall through */ |
9158 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 9159 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 9160 | u32 err = vmcs_read32(error_code_field); |
851eb667 | 9161 | kvm_requeue_exception_e(vcpu, vector, err); |
35920a35 | 9162 | } else |
851eb667 | 9163 | kvm_requeue_exception(vcpu, vector); |
37b96e98 | 9164 | break; |
66fd3f7f | 9165 | case INTR_TYPE_SOFT_INTR: |
3ab66e8a | 9166 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f | 9167 | /* fall through */ |
37b96e98 | 9168 | case INTR_TYPE_EXT_INTR: |
3ab66e8a | 9169 | kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); |
37b96e98 GN |
9170 | break; |
9171 | default: | |
9172 | break; | |
f7d9238f | 9173 | } |
cf393f75 AK |
9174 | } |
9175 | ||
83422e17 AK |
9176 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
9177 | { | |
3ab66e8a | 9178 | __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, |
83422e17 AK |
9179 | VM_EXIT_INSTRUCTION_LEN, |
9180 | IDT_VECTORING_ERROR_CODE); | |
9181 | } | |
9182 | ||
b463a6f7 AK |
9183 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
9184 | { | |
3ab66e8a | 9185 | __vmx_complete_interrupts(vcpu, |
b463a6f7 AK |
9186 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), |
9187 | VM_ENTRY_INSTRUCTION_LEN, | |
9188 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
9189 | ||
9190 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
9191 | } | |
9192 | ||
d7cd9796 GN |
9193 | static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) |
9194 | { | |
9195 | int i, nr_msrs; | |
9196 | struct perf_guest_switch_msr *msrs; | |
9197 | ||
9198 | msrs = perf_guest_get_msrs(&nr_msrs); | |
9199 | ||
9200 | if (!msrs) | |
9201 | return; | |
9202 | ||
9203 | for (i = 0; i < nr_msrs; i++) | |
9204 | if (msrs[i].host == msrs[i].guest) | |
9205 | clear_atomic_switch_msr(vmx, msrs[i].msr); | |
9206 | else | |
9207 | add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, | |
9208 | msrs[i].host); | |
9209 | } | |
9210 | ||
33365e7a | 9211 | static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu) |
64672c95 YJ |
9212 | { |
9213 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9214 | u64 tscl; | |
9215 | u32 delta_tsc; | |
9216 | ||
9217 | if (vmx->hv_deadline_tsc == -1) | |
9218 | return; | |
9219 | ||
9220 | tscl = rdtsc(); | |
9221 | if (vmx->hv_deadline_tsc > tscl) | |
9222 | /* sure to be 32 bit only because checked on set_hv_timer */ | |
9223 | delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> | |
9224 | cpu_preemption_timer_multi); | |
9225 | else | |
9226 | delta_tsc = 0; | |
9227 | ||
9228 | vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); | |
9229 | } | |
9230 | ||
a3b5ba49 | 9231 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 9232 | { |
a2fa3e9f | 9233 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
d6e41f11 | 9234 | unsigned long debugctlmsr, cr3, cr4; |
104f226b | 9235 | |
104f226b AK |
9236 | /* Don't enter VMX if guest state is invalid, let the exit handler |
9237 | start emulation until we arrive back to a valid state */ | |
14168786 | 9238 | if (vmx->emulation_required) |
104f226b AK |
9239 | return; |
9240 | ||
a7653ecd RK |
9241 | if (vmx->ple_window_dirty) { |
9242 | vmx->ple_window_dirty = false; | |
9243 | vmcs_write32(PLE_WINDOW, vmx->ple_window); | |
9244 | } | |
9245 | ||
012f83cb AG |
9246 | if (vmx->nested.sync_shadow_vmcs) { |
9247 | copy_vmcs12_to_shadow(vmx); | |
9248 | vmx->nested.sync_shadow_vmcs = false; | |
9249 | } | |
9250 | ||
104f226b AK |
9251 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
9252 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
9253 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
9254 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
9255 | ||
d6e41f11 | 9256 | cr3 = __get_current_cr3_fast(); |
44889942 | 9257 | if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) { |
d6e41f11 | 9258 | vmcs_writel(HOST_CR3, cr3); |
44889942 | 9259 | vmx->loaded_vmcs->vmcs_host_cr3 = cr3; |
d6e41f11 AL |
9260 | } |
9261 | ||
1e02ce4c | 9262 | cr4 = cr4_read_shadow(); |
44889942 | 9263 | if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) { |
d974baa3 | 9264 | vmcs_writel(HOST_CR4, cr4); |
44889942 | 9265 | vmx->loaded_vmcs->vmcs_host_cr4 = cr4; |
d974baa3 AL |
9266 | } |
9267 | ||
104f226b AK |
9268 | /* When single-stepping over STI and MOV SS, we must clear the |
9269 | * corresponding interruptibility bits in the guest state. Otherwise | |
9270 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
9271 | * exceptions being set, but that's not correct for the guest debugging | |
9272 | * case. */ | |
9273 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
9274 | vmx_set_interrupt_shadow(vcpu, 0); | |
9275 | ||
b9dd21e1 PB |
9276 | if (static_cpu_has(X86_FEATURE_PKU) && |
9277 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && | |
9278 | vcpu->arch.pkru != vmx->host_pkru) | |
9279 | __write_pkru(vcpu->arch.pkru); | |
1be0e61c | 9280 | |
d7cd9796 | 9281 | atomic_switch_perf_msrs(vmx); |
2a7921b7 | 9282 | debugctlmsr = get_debugctlmsr(); |
d7cd9796 | 9283 | |
64672c95 YJ |
9284 | vmx_arm_hv_timer(vcpu); |
9285 | ||
d462b819 | 9286 | vmx->__launched = vmx->loaded_vmcs->launched; |
104f226b | 9287 | asm( |
6aa8b732 | 9288 | /* Store host registers */ |
b188c81f AK |
9289 | "push %%" _ASM_DX "; push %%" _ASM_BP ";" |
9290 | "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */ | |
9291 | "push %%" _ASM_CX " \n\t" | |
9292 | "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t" | |
313dbd49 | 9293 | "je 1f \n\t" |
b188c81f | 9294 | "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t" |
4ecac3fd | 9295 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 9296 | "1: \n\t" |
d3edefc0 | 9297 | /* Reload cr2 if changed */ |
b188c81f AK |
9298 | "mov %c[cr2](%0), %%" _ASM_AX " \n\t" |
9299 | "mov %%cr2, %%" _ASM_DX " \n\t" | |
9300 | "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t" | |
d3edefc0 | 9301 | "je 2f \n\t" |
b188c81f | 9302 | "mov %%" _ASM_AX", %%cr2 \n\t" |
d3edefc0 | 9303 | "2: \n\t" |
6aa8b732 | 9304 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 9305 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 9306 | /* Load guest registers. Don't clobber flags. */ |
b188c81f AK |
9307 | "mov %c[rax](%0), %%" _ASM_AX " \n\t" |
9308 | "mov %c[rbx](%0), %%" _ASM_BX " \n\t" | |
9309 | "mov %c[rdx](%0), %%" _ASM_DX " \n\t" | |
9310 | "mov %c[rsi](%0), %%" _ASM_SI " \n\t" | |
9311 | "mov %c[rdi](%0), %%" _ASM_DI " \n\t" | |
9312 | "mov %c[rbp](%0), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 9313 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
9314 | "mov %c[r8](%0), %%r8 \n\t" |
9315 | "mov %c[r9](%0), %%r9 \n\t" | |
9316 | "mov %c[r10](%0), %%r10 \n\t" | |
9317 | "mov %c[r11](%0), %%r11 \n\t" | |
9318 | "mov %c[r12](%0), %%r12 \n\t" | |
9319 | "mov %c[r13](%0), %%r13 \n\t" | |
9320 | "mov %c[r14](%0), %%r14 \n\t" | |
9321 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 9322 | #endif |
b188c81f | 9323 | "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */ |
c801949d | 9324 | |
6aa8b732 | 9325 | /* Enter guest mode */ |
83287ea4 | 9326 | "jne 1f \n\t" |
4ecac3fd | 9327 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
83287ea4 AK |
9328 | "jmp 2f \n\t" |
9329 | "1: " __ex(ASM_VMX_VMRESUME) "\n\t" | |
9330 | "2: " | |
6aa8b732 | 9331 | /* Save guest registers, load host registers, keep flags */ |
b188c81f | 9332 | "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t" |
40712fae | 9333 | "pop %0 \n\t" |
b188c81f AK |
9334 | "mov %%" _ASM_AX ", %c[rax](%0) \n\t" |
9335 | "mov %%" _ASM_BX ", %c[rbx](%0) \n\t" | |
9336 | __ASM_SIZE(pop) " %c[rcx](%0) \n\t" | |
9337 | "mov %%" _ASM_DX ", %c[rdx](%0) \n\t" | |
9338 | "mov %%" _ASM_SI ", %c[rsi](%0) \n\t" | |
9339 | "mov %%" _ASM_DI ", %c[rdi](%0) \n\t" | |
9340 | "mov %%" _ASM_BP ", %c[rbp](%0) \n\t" | |
05b3e0c2 | 9341 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
9342 | "mov %%r8, %c[r8](%0) \n\t" |
9343 | "mov %%r9, %c[r9](%0) \n\t" | |
9344 | "mov %%r10, %c[r10](%0) \n\t" | |
9345 | "mov %%r11, %c[r11](%0) \n\t" | |
9346 | "mov %%r12, %c[r12](%0) \n\t" | |
9347 | "mov %%r13, %c[r13](%0) \n\t" | |
9348 | "mov %%r14, %c[r14](%0) \n\t" | |
9349 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 9350 | #endif |
b188c81f AK |
9351 | "mov %%cr2, %%" _ASM_AX " \n\t" |
9352 | "mov %%" _ASM_AX ", %c[cr2](%0) \n\t" | |
c801949d | 9353 | |
b188c81f | 9354 | "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t" |
e08aa78a | 9355 | "setbe %c[fail](%0) \n\t" |
83287ea4 AK |
9356 | ".pushsection .rodata \n\t" |
9357 | ".global vmx_return \n\t" | |
9358 | "vmx_return: " _ASM_PTR " 2b \n\t" | |
9359 | ".popsection" | |
e08aa78a | 9360 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), |
d462b819 | 9361 | [launched]"i"(offsetof(struct vcpu_vmx, __launched)), |
e08aa78a | 9362 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), |
313dbd49 | 9363 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
9364 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
9365 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
9366 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
9367 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
9368 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
9369 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
9370 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 9371 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
9372 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
9373 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
9374 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
9375 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
9376 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
9377 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
9378 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
9379 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 9380 | #endif |
40712fae AK |
9381 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
9382 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 LV |
9383 | : "cc", "memory" |
9384 | #ifdef CONFIG_X86_64 | |
b188c81f | 9385 | , "rax", "rbx", "rdi", "rsi" |
c2036300 | 9386 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
b188c81f AK |
9387 | #else |
9388 | , "eax", "ebx", "edi", "esi" | |
c2036300 LV |
9389 | #endif |
9390 | ); | |
6aa8b732 | 9391 | |
2a7921b7 GN |
9392 | /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ |
9393 | if (debugctlmsr) | |
9394 | update_debugctlmsr(debugctlmsr); | |
9395 | ||
aa67f609 AK |
9396 | #ifndef CONFIG_X86_64 |
9397 | /* | |
9398 | * The sysexit path does not restore ds/es, so we must set them to | |
9399 | * a reasonable value ourselves. | |
9400 | * | |
9401 | * We can't defer this to vmx_load_host_state() since that function | |
9402 | * may be executed in interrupt context, which saves and restore segments | |
9403 | * around it, nullifying its effect. | |
9404 | */ | |
9405 | loadsegment(ds, __USER_DS); | |
9406 | loadsegment(es, __USER_DS); | |
9407 | #endif | |
9408 | ||
6de4f3ad | 9409 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
6de12732 | 9410 | | (1 << VCPU_EXREG_RFLAGS) |
aff48baa | 9411 | | (1 << VCPU_EXREG_PDPTR) |
2fb92db1 | 9412 | | (1 << VCPU_EXREG_SEGMENTS) |
aff48baa | 9413 | | (1 << VCPU_EXREG_CR3)); |
5fdbf976 MT |
9414 | vcpu->arch.regs_dirty = 0; |
9415 | ||
1be0e61c XG |
9416 | /* |
9417 | * eager fpu is enabled if PKEY is supported and CR4 is switched | |
9418 | * back on host, so it is safe to read guest PKRU from current | |
9419 | * XSAVE. | |
9420 | */ | |
b9dd21e1 PB |
9421 | if (static_cpu_has(X86_FEATURE_PKU) && |
9422 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { | |
9423 | vcpu->arch.pkru = __read_pkru(); | |
9424 | if (vcpu->arch.pkru != vmx->host_pkru) | |
1be0e61c | 9425 | __write_pkru(vmx->host_pkru); |
1be0e61c XG |
9426 | } |
9427 | ||
e0b890d3 GN |
9428 | /* |
9429 | * the KVM_REQ_EVENT optimization bit is only on for one entry, and if | |
9430 | * we did not inject a still-pending event to L1 now because of | |
9431 | * nested_run_pending, we need to re-enable this bit. | |
9432 | */ | |
9433 | if (vmx->nested.nested_run_pending) | |
9434 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9435 | ||
9436 | vmx->nested.nested_run_pending = 0; | |
b060ca3b JM |
9437 | vmx->idt_vectoring_info = 0; |
9438 | ||
9439 | vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); | |
9440 | if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) | |
9441 | return; | |
9442 | ||
9443 | vmx->loaded_vmcs->launched = 1; | |
9444 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
e0b890d3 | 9445 | |
51aa01d1 AK |
9446 | vmx_complete_atomic_exit(vmx); |
9447 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 9448 | vmx_complete_interrupts(vmx); |
6aa8b732 | 9449 | } |
c207aee4 | 9450 | STACK_FRAME_NON_STANDARD(vmx_vcpu_run); |
6aa8b732 | 9451 | |
1279a6b1 | 9452 | static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs) |
4fa7734c PB |
9453 | { |
9454 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9455 | int cpu; | |
9456 | ||
1279a6b1 | 9457 | if (vmx->loaded_vmcs == vmcs) |
4fa7734c PB |
9458 | return; |
9459 | ||
9460 | cpu = get_cpu(); | |
1279a6b1 | 9461 | vmx->loaded_vmcs = vmcs; |
4fa7734c PB |
9462 | vmx_vcpu_put(vcpu); |
9463 | vmx_vcpu_load(vcpu, cpu); | |
4fa7734c PB |
9464 | put_cpu(); |
9465 | } | |
9466 | ||
2f1fe811 JM |
9467 | /* |
9468 | * Ensure that the current vmcs of the logical processor is the | |
9469 | * vmcs01 of the vcpu before calling free_nested(). | |
9470 | */ | |
9471 | static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu) | |
9472 | { | |
9473 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9474 | int r; | |
9475 | ||
9476 | r = vcpu_load(vcpu); | |
9477 | BUG_ON(r); | |
1279a6b1 | 9478 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
2f1fe811 JM |
9479 | free_nested(vmx); |
9480 | vcpu_put(vcpu); | |
9481 | } | |
9482 | ||
6aa8b732 AK |
9483 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
9484 | { | |
fb3f0f51 RR |
9485 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
9486 | ||
843e4330 | 9487 | if (enable_pml) |
a3eaa864 | 9488 | vmx_destroy_pml_buffer(vmx); |
991e7a0e | 9489 | free_vpid(vmx->vpid); |
4fa7734c | 9490 | leave_guest_mode(vcpu); |
2f1fe811 | 9491 | vmx_free_vcpu_nested(vcpu); |
4fa7734c | 9492 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 RR |
9493 | kfree(vmx->guest_msrs); |
9494 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 9495 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
9496 | } |
9497 | ||
fb3f0f51 | 9498 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 9499 | { |
fb3f0f51 | 9500 | int err; |
c16f862d | 9501 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 9502 | int cpu; |
6aa8b732 | 9503 | |
a2fa3e9f | 9504 | if (!vmx) |
fb3f0f51 RR |
9505 | return ERR_PTR(-ENOMEM); |
9506 | ||
991e7a0e | 9507 | vmx->vpid = allocate_vpid(); |
2384d2b3 | 9508 | |
fb3f0f51 RR |
9509 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
9510 | if (err) | |
9511 | goto free_vcpu; | |
965b58a5 | 9512 | |
4e59516a PF |
9513 | err = -ENOMEM; |
9514 | ||
9515 | /* | |
9516 | * If PML is turned on, failure on enabling PML just results in failure | |
9517 | * of creating the vcpu, therefore we can simplify PML logic (by | |
9518 | * avoiding dealing with cases, such as enabling PML partially on vcpus | |
9519 | * for the guest, etc. | |
9520 | */ | |
9521 | if (enable_pml) { | |
9522 | vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
9523 | if (!vmx->pml_pg) | |
9524 | goto uninit_vcpu; | |
9525 | } | |
9526 | ||
a2fa3e9f | 9527 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
03916db9 PB |
9528 | BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0]) |
9529 | > PAGE_SIZE); | |
0123be42 | 9530 | |
4e59516a PF |
9531 | if (!vmx->guest_msrs) |
9532 | goto free_pml; | |
965b58a5 | 9533 | |
d462b819 NHE |
9534 | vmx->loaded_vmcs = &vmx->vmcs01; |
9535 | vmx->loaded_vmcs->vmcs = alloc_vmcs(); | |
355f4fb1 | 9536 | vmx->loaded_vmcs->shadow_vmcs = NULL; |
d462b819 | 9537 | if (!vmx->loaded_vmcs->vmcs) |
fb3f0f51 | 9538 | goto free_msrs; |
d462b819 | 9539 | loaded_vmcs_init(vmx->loaded_vmcs); |
a2fa3e9f | 9540 | |
15ad7146 AK |
9541 | cpu = get_cpu(); |
9542 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 9543 | vmx->vcpu.cpu = cpu; |
12d79917 | 9544 | vmx_vcpu_setup(vmx); |
fb3f0f51 | 9545 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 9546 | put_cpu(); |
35754c98 | 9547 | if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
be6d05cf JK |
9548 | err = alloc_apic_access_page(kvm); |
9549 | if (err) | |
5e4a0b3c | 9550 | goto free_vmcs; |
a63cb560 | 9551 | } |
fb3f0f51 | 9552 | |
b927a3ce | 9553 | if (enable_ept) { |
f51770ed TC |
9554 | err = init_rmode_identity_map(kvm); |
9555 | if (err) | |
93ea5388 | 9556 | goto free_vmcs; |
b927a3ce | 9557 | } |
b7ebfb05 | 9558 | |
5c614b35 | 9559 | if (nested) { |
b9c237bb | 9560 | nested_vmx_setup_ctls_msrs(vmx); |
5c614b35 WL |
9561 | vmx->nested.vpid02 = allocate_vpid(); |
9562 | } | |
b9c237bb | 9563 | |
705699a1 | 9564 | vmx->nested.posted_intr_nv = -1; |
a9d30f33 | 9565 | vmx->nested.current_vmptr = -1ull; |
a9d30f33 | 9566 | |
37e4c997 HZ |
9567 | vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED; |
9568 | ||
31afb2ea PB |
9569 | /* |
9570 | * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR | |
9571 | * or POSTED_INTR_WAKEUP_VECTOR. | |
9572 | */ | |
9573 | vmx->pi_desc.nv = POSTED_INTR_VECTOR; | |
9574 | vmx->pi_desc.sn = 1; | |
9575 | ||
fb3f0f51 RR |
9576 | return &vmx->vcpu; |
9577 | ||
9578 | free_vmcs: | |
5c614b35 | 9579 | free_vpid(vmx->nested.vpid02); |
5f3fbc34 | 9580 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 | 9581 | free_msrs: |
fb3f0f51 | 9582 | kfree(vmx->guest_msrs); |
4e59516a PF |
9583 | free_pml: |
9584 | vmx_destroy_pml_buffer(vmx); | |
fb3f0f51 RR |
9585 | uninit_vcpu: |
9586 | kvm_vcpu_uninit(&vmx->vcpu); | |
9587 | free_vcpu: | |
991e7a0e | 9588 | free_vpid(vmx->vpid); |
a4770347 | 9589 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 9590 | return ERR_PTR(err); |
6aa8b732 AK |
9591 | } |
9592 | ||
002c7f7c YS |
9593 | static void __init vmx_check_processor_compat(void *rtn) |
9594 | { | |
9595 | struct vmcs_config vmcs_conf; | |
9596 | ||
9597 | *(int *)rtn = 0; | |
9598 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
9599 | *(int *)rtn = -EIO; | |
9600 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
9601 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
9602 | smp_processor_id()); | |
9603 | *(int *)rtn = -EIO; | |
9604 | } | |
9605 | } | |
9606 | ||
4b12f0de | 9607 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 9608 | { |
b18d5431 XG |
9609 | u8 cache; |
9610 | u64 ipat = 0; | |
4b12f0de | 9611 | |
522c68c4 | 9612 | /* For VT-d and EPT combination |
606decd6 | 9613 | * 1. MMIO: always map as UC |
522c68c4 SY |
9614 | * 2. EPT with VT-d: |
9615 | * a. VT-d without snooping control feature: can't guarantee the | |
606decd6 | 9616 | * result, try to trust guest. |
522c68c4 SY |
9617 | * b. VT-d with snooping control feature: snooping control feature of |
9618 | * VT-d engine can guarantee the cache correctness. Just set it | |
9619 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 9620 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
9621 | * consistent with host MTRR |
9622 | */ | |
606decd6 PB |
9623 | if (is_mmio) { |
9624 | cache = MTRR_TYPE_UNCACHABLE; | |
9625 | goto exit; | |
9626 | } | |
9627 | ||
9628 | if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { | |
b18d5431 XG |
9629 | ipat = VMX_EPT_IPAT_BIT; |
9630 | cache = MTRR_TYPE_WRBACK; | |
9631 | goto exit; | |
9632 | } | |
9633 | ||
9634 | if (kvm_read_cr0(vcpu) & X86_CR0_CD) { | |
9635 | ipat = VMX_EPT_IPAT_BIT; | |
0da029ed | 9636 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) |
fb279950 XG |
9637 | cache = MTRR_TYPE_WRBACK; |
9638 | else | |
9639 | cache = MTRR_TYPE_UNCACHABLE; | |
b18d5431 XG |
9640 | goto exit; |
9641 | } | |
9642 | ||
ff53604b | 9643 | cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); |
b18d5431 XG |
9644 | |
9645 | exit: | |
9646 | return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; | |
64d4d521 SY |
9647 | } |
9648 | ||
17cc3935 | 9649 | static int vmx_get_lpage_level(void) |
344f414f | 9650 | { |
878403b7 SY |
9651 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
9652 | return PT_DIRECTORY_LEVEL; | |
9653 | else | |
9654 | /* For shadow and EPT supported 1GB page */ | |
9655 | return PT_PDPE_LEVEL; | |
344f414f JR |
9656 | } |
9657 | ||
feda805f XG |
9658 | static void vmcs_set_secondary_exec_control(u32 new_ctl) |
9659 | { | |
9660 | /* | |
9661 | * These bits in the secondary execution controls field | |
9662 | * are dynamic, the others are mostly based on the hypervisor | |
9663 | * architecture and the guest's CPUID. Do not touch the | |
9664 | * dynamic bits. | |
9665 | */ | |
9666 | u32 mask = | |
9667 | SECONDARY_EXEC_SHADOW_VMCS | | |
9668 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | | |
9669 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
9670 | ||
9671 | u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
9672 | ||
9673 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
9674 | (new_ctl & ~mask) | (cur_ctl & mask)); | |
9675 | } | |
9676 | ||
8322ebbb DM |
9677 | /* |
9678 | * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits | |
9679 | * (indicating "allowed-1") if they are supported in the guest's CPUID. | |
9680 | */ | |
9681 | static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) | |
9682 | { | |
9683 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9684 | struct kvm_cpuid_entry2 *entry; | |
9685 | ||
9686 | vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff; | |
9687 | vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE; | |
9688 | ||
9689 | #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ | |
9690 | if (entry && (entry->_reg & (_cpuid_mask))) \ | |
9691 | vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \ | |
9692 | } while (0) | |
9693 | ||
9694 | entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); | |
9695 | cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME)); | |
9696 | cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME)); | |
9697 | cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC)); | |
9698 | cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE)); | |
9699 | cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE)); | |
9700 | cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE)); | |
9701 | cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE)); | |
9702 | cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE)); | |
9703 | cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR)); | |
9704 | cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM)); | |
9705 | cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX)); | |
9706 | cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX)); | |
9707 | cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID)); | |
9708 | cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE)); | |
9709 | ||
9710 | entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); | |
9711 | cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE)); | |
9712 | cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP)); | |
9713 | cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP)); | |
9714 | cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU)); | |
9715 | /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */ | |
9716 | cr4_fixed1_update(bit(11), ecx, bit(2)); | |
9717 | ||
9718 | #undef cr4_fixed1_update | |
9719 | } | |
9720 | ||
0e851880 SY |
9721 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
9722 | { | |
4e47c7a6 | 9723 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4e47c7a6 | 9724 | |
80154d77 PB |
9725 | if (cpu_has_secondary_exec_ctrls()) { |
9726 | vmx_compute_secondary_exec_control(vmx); | |
9727 | vmcs_set_secondary_exec_control(vmx->secondary_exec_control); | |
ad756a16 | 9728 | } |
8b3e34e4 | 9729 | |
37e4c997 HZ |
9730 | if (nested_vmx_allowed(vcpu)) |
9731 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
9732 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
9733 | else | |
9734 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
9735 | ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
8322ebbb DM |
9736 | |
9737 | if (nested_vmx_allowed(vcpu)) | |
9738 | nested_vmx_cr_fixed1_bits_update(vcpu); | |
0e851880 SY |
9739 | } |
9740 | ||
d4330ef2 JR |
9741 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
9742 | { | |
7b8050f5 NHE |
9743 | if (func == 1 && nested) |
9744 | entry->ecx |= bit(X86_FEATURE_VMX); | |
d4330ef2 JR |
9745 | } |
9746 | ||
25d92081 YZ |
9747 | static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, |
9748 | struct x86_exception *fault) | |
9749 | { | |
533558bc | 9750 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
c5f983f6 | 9751 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
533558bc | 9752 | u32 exit_reason; |
c5f983f6 | 9753 | unsigned long exit_qualification = vcpu->arch.exit_qualification; |
25d92081 | 9754 | |
c5f983f6 BD |
9755 | if (vmx->nested.pml_full) { |
9756 | exit_reason = EXIT_REASON_PML_FULL; | |
9757 | vmx->nested.pml_full = false; | |
9758 | exit_qualification &= INTR_INFO_UNBLOCK_NMI; | |
9759 | } else if (fault->error_code & PFERR_RSVD_MASK) | |
533558bc | 9760 | exit_reason = EXIT_REASON_EPT_MISCONFIG; |
25d92081 | 9761 | else |
533558bc | 9762 | exit_reason = EXIT_REASON_EPT_VIOLATION; |
c5f983f6 BD |
9763 | |
9764 | nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification); | |
25d92081 YZ |
9765 | vmcs12->guest_physical_address = fault->address; |
9766 | } | |
9767 | ||
995f00a6 PF |
9768 | static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu) |
9769 | { | |
bb97a016 | 9770 | return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT; |
995f00a6 PF |
9771 | } |
9772 | ||
155a97a3 NHE |
9773 | /* Callbacks for nested_ept_init_mmu_context: */ |
9774 | ||
9775 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu) | |
9776 | { | |
9777 | /* return the page table to be shadowed - in our case, EPT12 */ | |
9778 | return get_vmcs12(vcpu)->ept_pointer; | |
9779 | } | |
9780 | ||
ae1e2d10 | 9781 | static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) |
155a97a3 | 9782 | { |
ad896af0 | 9783 | WARN_ON(mmu_is_nested(vcpu)); |
a057e0e2 | 9784 | if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu))) |
ae1e2d10 PB |
9785 | return 1; |
9786 | ||
9787 | kvm_mmu_unload(vcpu); | |
ad896af0 | 9788 | kvm_init_shadow_ept_mmu(vcpu, |
b9c237bb | 9789 | to_vmx(vcpu)->nested.nested_vmx_ept_caps & |
ae1e2d10 | 9790 | VMX_EPT_EXECUTE_ONLY_BIT, |
a057e0e2 | 9791 | nested_ept_ad_enabled(vcpu)); |
155a97a3 NHE |
9792 | vcpu->arch.mmu.set_cr3 = vmx_set_cr3; |
9793 | vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3; | |
9794 | vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault; | |
9795 | ||
9796 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
ae1e2d10 | 9797 | return 0; |
155a97a3 NHE |
9798 | } |
9799 | ||
9800 | static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
9801 | { | |
9802 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
9803 | } | |
9804 | ||
19d5f10b EK |
9805 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, |
9806 | u16 error_code) | |
9807 | { | |
9808 | bool inequality, bit; | |
9809 | ||
9810 | bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0; | |
9811 | inequality = | |
9812 | (error_code & vmcs12->page_fault_error_code_mask) != | |
9813 | vmcs12->page_fault_error_code_match; | |
9814 | return inequality ^ bit; | |
9815 | } | |
9816 | ||
feaf0c7d GN |
9817 | static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, |
9818 | struct x86_exception *fault) | |
9819 | { | |
9820 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
9821 | ||
9822 | WARN_ON(!is_guest_mode(vcpu)); | |
9823 | ||
305d0ab4 WL |
9824 | if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) && |
9825 | !to_vmx(vcpu)->nested.nested_run_pending) { | |
b96fb439 PB |
9826 | vmcs12->vm_exit_intr_error_code = fault->error_code; |
9827 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
9828 | PF_VECTOR | INTR_TYPE_HARD_EXCEPTION | | |
9829 | INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK, | |
9830 | fault->address); | |
7313c698 | 9831 | } else { |
feaf0c7d | 9832 | kvm_inject_page_fault(vcpu, fault); |
7313c698 | 9833 | } |
feaf0c7d GN |
9834 | } |
9835 | ||
6beb7bd5 JM |
9836 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, |
9837 | struct vmcs12 *vmcs12); | |
9838 | ||
9839 | static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu, | |
a2bcba50 WL |
9840 | struct vmcs12 *vmcs12) |
9841 | { | |
9842 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5e2f30b7 | 9843 | struct page *page; |
6beb7bd5 | 9844 | u64 hpa; |
a2bcba50 WL |
9845 | |
9846 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
a2bcba50 WL |
9847 | /* |
9848 | * Translate L1 physical address to host physical | |
9849 | * address for vmcs02. Keep the page pinned, so this | |
9850 | * physical address remains valid. We keep a reference | |
9851 | * to it so we can release it later. | |
9852 | */ | |
5e2f30b7 | 9853 | if (vmx->nested.apic_access_page) { /* shouldn't happen */ |
53a70daf | 9854 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
5e2f30b7 DH |
9855 | vmx->nested.apic_access_page = NULL; |
9856 | } | |
9857 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr); | |
6beb7bd5 JM |
9858 | /* |
9859 | * If translation failed, no matter: This feature asks | |
9860 | * to exit when accessing the given address, and if it | |
9861 | * can never be accessed, this feature won't do | |
9862 | * anything anyway. | |
9863 | */ | |
5e2f30b7 DH |
9864 | if (!is_error_page(page)) { |
9865 | vmx->nested.apic_access_page = page; | |
6beb7bd5 JM |
9866 | hpa = page_to_phys(vmx->nested.apic_access_page); |
9867 | vmcs_write64(APIC_ACCESS_ADDR, hpa); | |
9868 | } else { | |
9869 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
9870 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
9871 | } | |
9872 | } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) && | |
9873 | cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { | |
9874 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
9875 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
9876 | kvm_vcpu_reload_apic_access_page(vcpu); | |
a2bcba50 | 9877 | } |
a7c0b07d WL |
9878 | |
9879 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
5e2f30b7 | 9880 | if (vmx->nested.virtual_apic_page) { /* shouldn't happen */ |
53a70daf | 9881 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
5e2f30b7 DH |
9882 | vmx->nested.virtual_apic_page = NULL; |
9883 | } | |
9884 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr); | |
a7c0b07d WL |
9885 | |
9886 | /* | |
6beb7bd5 JM |
9887 | * If translation failed, VM entry will fail because |
9888 | * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull. | |
9889 | * Failing the vm entry is _not_ what the processor | |
9890 | * does but it's basically the only possibility we | |
9891 | * have. We could still enter the guest if CR8 load | |
9892 | * exits are enabled, CR8 store exits are enabled, and | |
9893 | * virtualize APIC access is disabled; in this case | |
9894 | * the processor would never use the TPR shadow and we | |
9895 | * could simply clear the bit from the execution | |
9896 | * control. But such a configuration is useless, so | |
9897 | * let's keep the code simple. | |
a7c0b07d | 9898 | */ |
5e2f30b7 DH |
9899 | if (!is_error_page(page)) { |
9900 | vmx->nested.virtual_apic_page = page; | |
6beb7bd5 JM |
9901 | hpa = page_to_phys(vmx->nested.virtual_apic_page); |
9902 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa); | |
9903 | } | |
a7c0b07d WL |
9904 | } |
9905 | ||
705699a1 | 9906 | if (nested_cpu_has_posted_intr(vmcs12)) { |
705699a1 WV |
9907 | if (vmx->nested.pi_desc_page) { /* shouldn't happen */ |
9908 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 9909 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
5e2f30b7 | 9910 | vmx->nested.pi_desc_page = NULL; |
705699a1 | 9911 | } |
5e2f30b7 DH |
9912 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr); |
9913 | if (is_error_page(page)) | |
6beb7bd5 | 9914 | return; |
5e2f30b7 DH |
9915 | vmx->nested.pi_desc_page = page; |
9916 | vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page); | |
705699a1 WV |
9917 | vmx->nested.pi_desc = |
9918 | (struct pi_desc *)((void *)vmx->nested.pi_desc + | |
9919 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
9920 | (PAGE_SIZE - 1))); | |
6beb7bd5 JM |
9921 | vmcs_write64(POSTED_INTR_DESC_ADDR, |
9922 | page_to_phys(vmx->nested.pi_desc_page) + | |
9923 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
9924 | (PAGE_SIZE - 1))); | |
705699a1 | 9925 | } |
6beb7bd5 JM |
9926 | if (cpu_has_vmx_msr_bitmap() && |
9927 | nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) && | |
9928 | nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) | |
9929 | ; | |
9930 | else | |
9931 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, | |
9932 | CPU_BASED_USE_MSR_BITMAPS); | |
a2bcba50 WL |
9933 | } |
9934 | ||
f4124500 JK |
9935 | static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu) |
9936 | { | |
9937 | u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value; | |
9938 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9939 | ||
9940 | if (vcpu->arch.virtual_tsc_khz == 0) | |
9941 | return; | |
9942 | ||
9943 | /* Make sure short timeouts reliably trigger an immediate vmexit. | |
9944 | * hrtimer_start does not guarantee this. */ | |
9945 | if (preemption_timeout <= 1) { | |
9946 | vmx_preemption_timer_fn(&vmx->nested.preemption_timer); | |
9947 | return; | |
9948 | } | |
9949 | ||
9950 | preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
9951 | preemption_timeout *= 1000000; | |
9952 | do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); | |
9953 | hrtimer_start(&vmx->nested.preemption_timer, | |
9954 | ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL); | |
9955 | } | |
9956 | ||
56a20510 JM |
9957 | static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu, |
9958 | struct vmcs12 *vmcs12) | |
9959 | { | |
9960 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) | |
9961 | return 0; | |
9962 | ||
9963 | if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) || | |
9964 | !page_address_valid(vcpu, vmcs12->io_bitmap_b)) | |
9965 | return -EINVAL; | |
9966 | ||
9967 | return 0; | |
9968 | } | |
9969 | ||
3af18d9c WV |
9970 | static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, |
9971 | struct vmcs12 *vmcs12) | |
9972 | { | |
3af18d9c WV |
9973 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
9974 | return 0; | |
9975 | ||
5fa99cbe | 9976 | if (!page_address_valid(vcpu, vmcs12->msr_bitmap)) |
3af18d9c WV |
9977 | return -EINVAL; |
9978 | ||
9979 | return 0; | |
9980 | } | |
9981 | ||
712b12d7 JM |
9982 | static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu, |
9983 | struct vmcs12 *vmcs12) | |
9984 | { | |
9985 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
9986 | return 0; | |
9987 | ||
9988 | if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr)) | |
9989 | return -EINVAL; | |
9990 | ||
9991 | return 0; | |
9992 | } | |
9993 | ||
3af18d9c WV |
9994 | /* |
9995 | * Merge L0's and L1's MSR bitmap, return false to indicate that | |
9996 | * we do not use the hardware. | |
9997 | */ | |
9998 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, | |
9999 | struct vmcs12 *vmcs12) | |
10000 | { | |
82f0dd4b | 10001 | int msr; |
f2b93280 | 10002 | struct page *page; |
d048c098 RK |
10003 | unsigned long *msr_bitmap_l1; |
10004 | unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap; | |
f2b93280 | 10005 | |
d048c098 | 10006 | /* This shortcut is ok because we support only x2APIC MSRs so far. */ |
f2b93280 WV |
10007 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12)) |
10008 | return false; | |
10009 | ||
5e2f30b7 DH |
10010 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap); |
10011 | if (is_error_page(page)) | |
f2b93280 | 10012 | return false; |
d048c098 | 10013 | msr_bitmap_l1 = (unsigned long *)kmap(page); |
f2b93280 | 10014 | |
d048c098 RK |
10015 | memset(msr_bitmap_l0, 0xff, PAGE_SIZE); |
10016 | ||
f2b93280 | 10017 | if (nested_cpu_has_virt_x2apic_mode(vmcs12)) { |
82f0dd4b WV |
10018 | if (nested_cpu_has_apic_reg_virt(vmcs12)) |
10019 | for (msr = 0x800; msr <= 0x8ff; msr++) | |
10020 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 10021 | msr_bitmap_l1, msr_bitmap_l0, |
82f0dd4b | 10022 | msr, MSR_TYPE_R); |
d048c098 RK |
10023 | |
10024 | nested_vmx_disable_intercept_for_msr( | |
10025 | msr_bitmap_l1, msr_bitmap_l0, | |
f2b93280 WV |
10026 | APIC_BASE_MSR + (APIC_TASKPRI >> 4), |
10027 | MSR_TYPE_R | MSR_TYPE_W); | |
d048c098 | 10028 | |
608406e2 | 10029 | if (nested_cpu_has_vid(vmcs12)) { |
608406e2 | 10030 | nested_vmx_disable_intercept_for_msr( |
d048c098 | 10031 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
10032 | APIC_BASE_MSR + (APIC_EOI >> 4), |
10033 | MSR_TYPE_W); | |
10034 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 10035 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
10036 | APIC_BASE_MSR + (APIC_SELF_IPI >> 4), |
10037 | MSR_TYPE_W); | |
10038 | } | |
82f0dd4b | 10039 | } |
f2b93280 | 10040 | kunmap(page); |
53a70daf | 10041 | kvm_release_page_clean(page); |
f2b93280 WV |
10042 | |
10043 | return true; | |
10044 | } | |
10045 | ||
10046 | static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu, | |
10047 | struct vmcs12 *vmcs12) | |
10048 | { | |
82f0dd4b | 10049 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && |
608406e2 | 10050 | !nested_cpu_has_apic_reg_virt(vmcs12) && |
705699a1 WV |
10051 | !nested_cpu_has_vid(vmcs12) && |
10052 | !nested_cpu_has_posted_intr(vmcs12)) | |
f2b93280 WV |
10053 | return 0; |
10054 | ||
10055 | /* | |
10056 | * If virtualize x2apic mode is enabled, | |
10057 | * virtualize apic access must be disabled. | |
10058 | */ | |
82f0dd4b WV |
10059 | if (nested_cpu_has_virt_x2apic_mode(vmcs12) && |
10060 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
f2b93280 WV |
10061 | return -EINVAL; |
10062 | ||
608406e2 WV |
10063 | /* |
10064 | * If virtual interrupt delivery is enabled, | |
10065 | * we must exit on external interrupts. | |
10066 | */ | |
10067 | if (nested_cpu_has_vid(vmcs12) && | |
10068 | !nested_exit_on_intr(vcpu)) | |
10069 | return -EINVAL; | |
10070 | ||
705699a1 WV |
10071 | /* |
10072 | * bits 15:8 should be zero in posted_intr_nv, | |
10073 | * the descriptor address has been already checked | |
10074 | * in nested_get_vmcs12_pages. | |
10075 | */ | |
10076 | if (nested_cpu_has_posted_intr(vmcs12) && | |
10077 | (!nested_cpu_has_vid(vmcs12) || | |
10078 | !nested_exit_intr_ack_set(vcpu) || | |
10079 | vmcs12->posted_intr_nv & 0xff00)) | |
10080 | return -EINVAL; | |
10081 | ||
f2b93280 WV |
10082 | /* tpr shadow is needed by all apicv features. */ |
10083 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
10084 | return -EINVAL; | |
10085 | ||
10086 | return 0; | |
3af18d9c WV |
10087 | } |
10088 | ||
e9ac033e EK |
10089 | static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu, |
10090 | unsigned long count_field, | |
92d71bc6 | 10091 | unsigned long addr_field) |
ff651cb6 | 10092 | { |
92d71bc6 | 10093 | int maxphyaddr; |
e9ac033e EK |
10094 | u64 count, addr; |
10095 | ||
10096 | if (vmcs12_read_any(vcpu, count_field, &count) || | |
10097 | vmcs12_read_any(vcpu, addr_field, &addr)) { | |
10098 | WARN_ON(1); | |
10099 | return -EINVAL; | |
10100 | } | |
10101 | if (count == 0) | |
10102 | return 0; | |
92d71bc6 | 10103 | maxphyaddr = cpuid_maxphyaddr(vcpu); |
e9ac033e EK |
10104 | if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr || |
10105 | (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) { | |
bbe41b95 | 10106 | pr_debug_ratelimited( |
e9ac033e EK |
10107 | "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)", |
10108 | addr_field, maxphyaddr, count, addr); | |
10109 | return -EINVAL; | |
10110 | } | |
10111 | return 0; | |
10112 | } | |
10113 | ||
10114 | static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu, | |
10115 | struct vmcs12 *vmcs12) | |
10116 | { | |
e9ac033e EK |
10117 | if (vmcs12->vm_exit_msr_load_count == 0 && |
10118 | vmcs12->vm_exit_msr_store_count == 0 && | |
10119 | vmcs12->vm_entry_msr_load_count == 0) | |
10120 | return 0; /* Fast path */ | |
e9ac033e | 10121 | if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT, |
92d71bc6 | 10122 | VM_EXIT_MSR_LOAD_ADDR) || |
e9ac033e | 10123 | nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT, |
92d71bc6 | 10124 | VM_EXIT_MSR_STORE_ADDR) || |
e9ac033e | 10125 | nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT, |
92d71bc6 | 10126 | VM_ENTRY_MSR_LOAD_ADDR)) |
e9ac033e EK |
10127 | return -EINVAL; |
10128 | return 0; | |
10129 | } | |
10130 | ||
c5f983f6 BD |
10131 | static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu, |
10132 | struct vmcs12 *vmcs12) | |
10133 | { | |
10134 | u64 address = vmcs12->pml_address; | |
10135 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
10136 | ||
10137 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) { | |
10138 | if (!nested_cpu_has_ept(vmcs12) || | |
10139 | !IS_ALIGNED(address, 4096) || | |
10140 | address >> maxphyaddr) | |
10141 | return -EINVAL; | |
10142 | } | |
10143 | ||
10144 | return 0; | |
10145 | } | |
10146 | ||
e9ac033e EK |
10147 | static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu, |
10148 | struct vmx_msr_entry *e) | |
10149 | { | |
10150 | /* x2APIC MSR accesses are not allowed */ | |
8a9781f7 | 10151 | if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8) |
e9ac033e EK |
10152 | return -EINVAL; |
10153 | if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */ | |
10154 | e->index == MSR_IA32_UCODE_REV) | |
10155 | return -EINVAL; | |
10156 | if (e->reserved != 0) | |
ff651cb6 WV |
10157 | return -EINVAL; |
10158 | return 0; | |
10159 | } | |
10160 | ||
e9ac033e EK |
10161 | static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu, |
10162 | struct vmx_msr_entry *e) | |
ff651cb6 WV |
10163 | { |
10164 | if (e->index == MSR_FS_BASE || | |
10165 | e->index == MSR_GS_BASE || | |
e9ac033e EK |
10166 | e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */ |
10167 | nested_vmx_msr_check_common(vcpu, e)) | |
10168 | return -EINVAL; | |
10169 | return 0; | |
10170 | } | |
10171 | ||
10172 | static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu, | |
10173 | struct vmx_msr_entry *e) | |
10174 | { | |
10175 | if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */ | |
10176 | nested_vmx_msr_check_common(vcpu, e)) | |
ff651cb6 WV |
10177 | return -EINVAL; |
10178 | return 0; | |
10179 | } | |
10180 | ||
10181 | /* | |
10182 | * Load guest's/host's msr at nested entry/exit. | |
10183 | * return 0 for success, entry index for failure. | |
10184 | */ | |
10185 | static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
10186 | { | |
10187 | u32 i; | |
10188 | struct vmx_msr_entry e; | |
10189 | struct msr_data msr; | |
10190 | ||
10191 | msr.host_initiated = false; | |
10192 | for (i = 0; i < count; i++) { | |
54bf36aa PB |
10193 | if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e), |
10194 | &e, sizeof(e))) { | |
bbe41b95 | 10195 | pr_debug_ratelimited( |
e9ac033e EK |
10196 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
10197 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 10198 | goto fail; |
e9ac033e EK |
10199 | } |
10200 | if (nested_vmx_load_msr_check(vcpu, &e)) { | |
bbe41b95 | 10201 | pr_debug_ratelimited( |
e9ac033e EK |
10202 | "%s check failed (%u, 0x%x, 0x%x)\n", |
10203 | __func__, i, e.index, e.reserved); | |
10204 | goto fail; | |
10205 | } | |
ff651cb6 WV |
10206 | msr.index = e.index; |
10207 | msr.data = e.value; | |
e9ac033e | 10208 | if (kvm_set_msr(vcpu, &msr)) { |
bbe41b95 | 10209 | pr_debug_ratelimited( |
e9ac033e EK |
10210 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
10211 | __func__, i, e.index, e.value); | |
ff651cb6 | 10212 | goto fail; |
e9ac033e | 10213 | } |
ff651cb6 WV |
10214 | } |
10215 | return 0; | |
10216 | fail: | |
10217 | return i + 1; | |
10218 | } | |
10219 | ||
10220 | static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
10221 | { | |
10222 | u32 i; | |
10223 | struct vmx_msr_entry e; | |
10224 | ||
10225 | for (i = 0; i < count; i++) { | |
609e36d3 | 10226 | struct msr_data msr_info; |
54bf36aa PB |
10227 | if (kvm_vcpu_read_guest(vcpu, |
10228 | gpa + i * sizeof(e), | |
10229 | &e, 2 * sizeof(u32))) { | |
bbe41b95 | 10230 | pr_debug_ratelimited( |
e9ac033e EK |
10231 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
10232 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 10233 | return -EINVAL; |
e9ac033e EK |
10234 | } |
10235 | if (nested_vmx_store_msr_check(vcpu, &e)) { | |
bbe41b95 | 10236 | pr_debug_ratelimited( |
e9ac033e EK |
10237 | "%s check failed (%u, 0x%x, 0x%x)\n", |
10238 | __func__, i, e.index, e.reserved); | |
ff651cb6 | 10239 | return -EINVAL; |
e9ac033e | 10240 | } |
609e36d3 PB |
10241 | msr_info.host_initiated = false; |
10242 | msr_info.index = e.index; | |
10243 | if (kvm_get_msr(vcpu, &msr_info)) { | |
bbe41b95 | 10244 | pr_debug_ratelimited( |
e9ac033e EK |
10245 | "%s cannot read MSR (%u, 0x%x)\n", |
10246 | __func__, i, e.index); | |
10247 | return -EINVAL; | |
10248 | } | |
54bf36aa PB |
10249 | if (kvm_vcpu_write_guest(vcpu, |
10250 | gpa + i * sizeof(e) + | |
10251 | offsetof(struct vmx_msr_entry, value), | |
10252 | &msr_info.data, sizeof(msr_info.data))) { | |
bbe41b95 | 10253 | pr_debug_ratelimited( |
e9ac033e | 10254 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
609e36d3 | 10255 | __func__, i, e.index, msr_info.data); |
e9ac033e EK |
10256 | return -EINVAL; |
10257 | } | |
ff651cb6 WV |
10258 | } |
10259 | return 0; | |
10260 | } | |
10261 | ||
1dc35dac LP |
10262 | static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val) |
10263 | { | |
10264 | unsigned long invalid_mask; | |
10265 | ||
10266 | invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu); | |
10267 | return (val & invalid_mask) == 0; | |
10268 | } | |
10269 | ||
9ed38ffa LP |
10270 | /* |
10271 | * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are | |
10272 | * emulating VM entry into a guest with EPT enabled. | |
10273 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code | |
10274 | * is assigned to entry_failure_code on failure. | |
10275 | */ | |
10276 | static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept, | |
ca0bde28 | 10277 | u32 *entry_failure_code) |
9ed38ffa | 10278 | { |
9ed38ffa | 10279 | if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) { |
1dc35dac | 10280 | if (!nested_cr3_valid(vcpu, cr3)) { |
9ed38ffa LP |
10281 | *entry_failure_code = ENTRY_FAIL_DEFAULT; |
10282 | return 1; | |
10283 | } | |
10284 | ||
10285 | /* | |
10286 | * If PAE paging and EPT are both on, CR3 is not used by the CPU and | |
10287 | * must not be dereferenced. | |
10288 | */ | |
10289 | if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) && | |
10290 | !nested_ept) { | |
10291 | if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) { | |
10292 | *entry_failure_code = ENTRY_FAIL_PDPTE; | |
10293 | return 1; | |
10294 | } | |
10295 | } | |
10296 | ||
10297 | vcpu->arch.cr3 = cr3; | |
10298 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
10299 | } | |
10300 | ||
10301 | kvm_mmu_reset_context(vcpu); | |
10302 | return 0; | |
10303 | } | |
10304 | ||
fe3ef05c NHE |
10305 | /* |
10306 | * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested | |
10307 | * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it | |
b4619660 | 10308 | * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 |
fe3ef05c NHE |
10309 | * guest in a way that will both be appropriate to L1's requests, and our |
10310 | * needs. In addition to modifying the active vmcs (which is vmcs02), this | |
10311 | * function also has additional necessary side-effects, like setting various | |
10312 | * vcpu->arch fields. | |
ee146c1c LP |
10313 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code |
10314 | * is assigned to entry_failure_code on failure. | |
fe3ef05c | 10315 | */ |
ee146c1c | 10316 | static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, |
ca0bde28 | 10317 | bool from_vmentry, u32 *entry_failure_code) |
fe3ef05c NHE |
10318 | { |
10319 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
03efce6f | 10320 | u32 exec_control, vmcs12_exec_ctrl; |
fe3ef05c NHE |
10321 | |
10322 | vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); | |
10323 | vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); | |
10324 | vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); | |
10325 | vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); | |
10326 | vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); | |
10327 | vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); | |
10328 | vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); | |
10329 | vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); | |
10330 | vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); | |
10331 | vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); | |
10332 | vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); | |
10333 | vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); | |
10334 | vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); | |
10335 | vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); | |
10336 | vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); | |
10337 | vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); | |
10338 | vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); | |
10339 | vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); | |
10340 | vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); | |
10341 | vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); | |
10342 | vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); | |
10343 | vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); | |
10344 | vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); | |
10345 | vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); | |
10346 | vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); | |
10347 | vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); | |
10348 | vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); | |
10349 | vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); | |
10350 | vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); | |
10351 | vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); | |
10352 | vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); | |
10353 | vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); | |
10354 | vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); | |
10355 | vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); | |
10356 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); | |
10357 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); | |
10358 | ||
cf8b84f4 JM |
10359 | if (from_vmentry && |
10360 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) { | |
2996fca0 JK |
10361 | kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); |
10362 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); | |
10363 | } else { | |
10364 | kvm_set_dr(vcpu, 7, vcpu->arch.dr7); | |
10365 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl); | |
10366 | } | |
cf8b84f4 JM |
10367 | if (from_vmentry) { |
10368 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
10369 | vmcs12->vm_entry_intr_info_field); | |
10370 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
10371 | vmcs12->vm_entry_exception_error_code); | |
10372 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
10373 | vmcs12->vm_entry_instruction_len); | |
10374 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
10375 | vmcs12->guest_interruptibility_info); | |
2d6144e3 WL |
10376 | vmx->loaded_vmcs->nmi_known_unmasked = |
10377 | !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI); | |
cf8b84f4 JM |
10378 | } else { |
10379 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
10380 | } | |
fe3ef05c | 10381 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); |
63fbf59f | 10382 | vmx_set_rflags(vcpu, vmcs12->guest_rflags); |
fe3ef05c NHE |
10383 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, |
10384 | vmcs12->guest_pending_dbg_exceptions); | |
10385 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); | |
10386 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); | |
10387 | ||
81dc01f7 WL |
10388 | if (nested_cpu_has_xsaves(vmcs12)) |
10389 | vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); | |
fe3ef05c NHE |
10390 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
10391 | ||
f4124500 | 10392 | exec_control = vmcs12->pin_based_vm_exec_control; |
9314006d PB |
10393 | |
10394 | /* Preemption timer setting is only taken from vmcs01. */ | |
705699a1 | 10395 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; |
9314006d PB |
10396 | exec_control |= vmcs_config.pin_based_exec_ctrl; |
10397 | if (vmx->hv_deadline_tsc == -1) | |
10398 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
705699a1 | 10399 | |
9314006d | 10400 | /* Posted interrupts setting is only taken from vmcs12. */ |
705699a1 | 10401 | if (nested_cpu_has_posted_intr(vmcs12)) { |
705699a1 WV |
10402 | vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv; |
10403 | vmx->nested.pi_pending = false; | |
06a5524f | 10404 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR); |
6beb7bd5 | 10405 | } else { |
705699a1 | 10406 | exec_control &= ~PIN_BASED_POSTED_INTR; |
6beb7bd5 | 10407 | } |
705699a1 | 10408 | |
f4124500 | 10409 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control); |
fe3ef05c | 10410 | |
f4124500 JK |
10411 | vmx->nested.preemption_timer_expired = false; |
10412 | if (nested_cpu_has_preemption_timer(vmcs12)) | |
10413 | vmx_start_preemption_timer(vcpu); | |
0238ea91 | 10414 | |
fe3ef05c NHE |
10415 | /* |
10416 | * Whether page-faults are trapped is determined by a combination of | |
10417 | * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. | |
10418 | * If enable_ept, L0 doesn't care about page faults and we should | |
10419 | * set all of these to L1's desires. However, if !enable_ept, L0 does | |
10420 | * care about (at least some) page faults, and because it is not easy | |
10421 | * (if at all possible?) to merge L0 and L1's desires, we simply ask | |
10422 | * to exit on each and every L2 page fault. This is done by setting | |
10423 | * MASK=MATCH=0 and (see below) EB.PF=1. | |
10424 | * Note that below we don't need special code to set EB.PF beyond the | |
10425 | * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, | |
10426 | * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when | |
10427 | * !enable_ept, EB.PF is 1, so the "or" will always be 1. | |
fe3ef05c NHE |
10428 | */ |
10429 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, | |
10430 | enable_ept ? vmcs12->page_fault_error_code_mask : 0); | |
10431 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, | |
10432 | enable_ept ? vmcs12->page_fault_error_code_match : 0); | |
10433 | ||
10434 | if (cpu_has_secondary_exec_ctrls()) { | |
80154d77 | 10435 | exec_control = vmx->secondary_exec_control; |
e2821620 | 10436 | |
fe3ef05c | 10437 | /* Take the following fields only from vmcs12 */ |
696dfd95 | 10438 | exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
90a2db6d | 10439 | SECONDARY_EXEC_ENABLE_INVPCID | |
b3a2a907 | 10440 | SECONDARY_EXEC_RDTSCP | |
3db13480 | 10441 | SECONDARY_EXEC_XSAVES | |
696dfd95 | 10442 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
27c42a1b BD |
10443 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
10444 | SECONDARY_EXEC_ENABLE_VMFUNC); | |
fe3ef05c | 10445 | if (nested_cpu_has(vmcs12, |
03efce6f BD |
10446 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) { |
10447 | vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control & | |
10448 | ~SECONDARY_EXEC_ENABLE_PML; | |
10449 | exec_control |= vmcs12_exec_ctrl; | |
10450 | } | |
fe3ef05c | 10451 | |
27c42a1b BD |
10452 | /* All VMFUNCs are currently emulated through L0 vmexits. */ |
10453 | if (exec_control & SECONDARY_EXEC_ENABLE_VMFUNC) | |
10454 | vmcs_write64(VM_FUNCTION_CONTROL, 0); | |
10455 | ||
608406e2 WV |
10456 | if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { |
10457 | vmcs_write64(EOI_EXIT_BITMAP0, | |
10458 | vmcs12->eoi_exit_bitmap0); | |
10459 | vmcs_write64(EOI_EXIT_BITMAP1, | |
10460 | vmcs12->eoi_exit_bitmap1); | |
10461 | vmcs_write64(EOI_EXIT_BITMAP2, | |
10462 | vmcs12->eoi_exit_bitmap2); | |
10463 | vmcs_write64(EOI_EXIT_BITMAP3, | |
10464 | vmcs12->eoi_exit_bitmap3); | |
10465 | vmcs_write16(GUEST_INTR_STATUS, | |
10466 | vmcs12->guest_intr_status); | |
10467 | } | |
10468 | ||
6beb7bd5 JM |
10469 | /* |
10470 | * Write an illegal value to APIC_ACCESS_ADDR. Later, | |
10471 | * nested_get_vmcs12_pages will either fix it up or | |
10472 | * remove the VM execution control. | |
10473 | */ | |
10474 | if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) | |
10475 | vmcs_write64(APIC_ACCESS_ADDR, -1ull); | |
10476 | ||
fe3ef05c NHE |
10477 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
10478 | } | |
10479 | ||
10480 | ||
10481 | /* | |
10482 | * Set host-state according to L0's settings (vmcs12 is irrelevant here) | |
10483 | * Some constant fields are set here by vmx_set_constant_host_state(). | |
10484 | * Other fields are different per CPU, and will be set later when | |
10485 | * vmx_vcpu_load() is called, and when vmx_save_host_state() is called. | |
10486 | */ | |
a547c6db | 10487 | vmx_set_constant_host_state(vmx); |
fe3ef05c | 10488 | |
83bafef1 JM |
10489 | /* |
10490 | * Set the MSR load/store lists to match L0's settings. | |
10491 | */ | |
10492 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); | |
10493 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
10494 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); | |
10495 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
10496 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); | |
10497 | ||
fe3ef05c NHE |
10498 | /* |
10499 | * HOST_RSP is normally set correctly in vmx_vcpu_run() just before | |
10500 | * entry, but only if the current (host) sp changed from the value | |
10501 | * we wrote last (vmx->host_rsp). This cache is no longer relevant | |
10502 | * if we switch vmcs, and rather than hold a separate cache per vmcs, | |
10503 | * here we just force the write to happen on entry. | |
10504 | */ | |
10505 | vmx->host_rsp = 0; | |
10506 | ||
10507 | exec_control = vmx_exec_control(vmx); /* L0's desires */ | |
10508 | exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
10509 | exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
10510 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
10511 | exec_control |= vmcs12->cpu_based_vm_exec_control; | |
a7c0b07d | 10512 | |
6beb7bd5 JM |
10513 | /* |
10514 | * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if | |
10515 | * nested_get_vmcs12_pages can't fix it up, the illegal value | |
10516 | * will result in a VM entry failure. | |
10517 | */ | |
a7c0b07d | 10518 | if (exec_control & CPU_BASED_TPR_SHADOW) { |
6beb7bd5 | 10519 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull); |
a7c0b07d | 10520 | vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); |
51aa68e7 JM |
10521 | } else { |
10522 | #ifdef CONFIG_X86_64 | |
10523 | exec_control |= CPU_BASED_CR8_LOAD_EXITING | | |
10524 | CPU_BASED_CR8_STORE_EXITING; | |
10525 | #endif | |
a7c0b07d WL |
10526 | } |
10527 | ||
fe3ef05c | 10528 | /* |
3af18d9c | 10529 | * Merging of IO bitmap not currently supported. |
fe3ef05c NHE |
10530 | * Rather, exit every time. |
10531 | */ | |
fe3ef05c NHE |
10532 | exec_control &= ~CPU_BASED_USE_IO_BITMAPS; |
10533 | exec_control |= CPU_BASED_UNCOND_IO_EXITING; | |
10534 | ||
10535 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
10536 | ||
10537 | /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the | |
10538 | * bitwise-or of what L1 wants to trap for L2, and what we want to | |
10539 | * trap. Note that CR0.TS also needs updating - we do this later. | |
10540 | */ | |
10541 | update_exception_bitmap(vcpu); | |
10542 | vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; | |
10543 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
10544 | ||
8049d651 NHE |
10545 | /* L2->L1 exit controls are emulated - the hardware exit is to L0 so |
10546 | * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER | |
10547 | * bits are further modified by vmx_set_efer() below. | |
10548 | */ | |
f4124500 | 10549 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
8049d651 NHE |
10550 | |
10551 | /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are | |
10552 | * emulated by vmx_set_efer(), below. | |
10553 | */ | |
2961e876 | 10554 | vm_entry_controls_init(vmx, |
8049d651 NHE |
10555 | (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER & |
10556 | ~VM_ENTRY_IA32E_MODE) | | |
fe3ef05c NHE |
10557 | (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE)); |
10558 | ||
cf8b84f4 JM |
10559 | if (from_vmentry && |
10560 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) { | |
fe3ef05c | 10561 | vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); |
44811c02 | 10562 | vcpu->arch.pat = vmcs12->guest_ia32_pat; |
cf8b84f4 | 10563 | } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { |
fe3ef05c | 10564 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); |
cf8b84f4 | 10565 | } |
fe3ef05c NHE |
10566 | |
10567 | set_cr4_guest_host_mask(vmx); | |
10568 | ||
cf8b84f4 JM |
10569 | if (from_vmentry && |
10570 | vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) | |
36be0b9d PB |
10571 | vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); |
10572 | ||
27fc51b2 NHE |
10573 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
10574 | vmcs_write64(TSC_OFFSET, | |
ea26e4ec | 10575 | vcpu->arch.tsc_offset + vmcs12->tsc_offset); |
27fc51b2 | 10576 | else |
ea26e4ec | 10577 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
c95ba92a PF |
10578 | if (kvm_has_tsc_control) |
10579 | decache_tsc_multiplier(vmx); | |
fe3ef05c NHE |
10580 | |
10581 | if (enable_vpid) { | |
10582 | /* | |
5c614b35 WL |
10583 | * There is no direct mapping between vpid02 and vpid12, the |
10584 | * vpid02 is per-vCPU for L0 and reused while the value of | |
10585 | * vpid12 is changed w/ one invvpid during nested vmentry. | |
10586 | * The vpid12 is allocated by L1 for L2, so it will not | |
10587 | * influence global bitmap(for vpid01 and vpid02 allocation) | |
10588 | * even if spawn a lot of nested vCPUs. | |
fe3ef05c | 10589 | */ |
5c614b35 WL |
10590 | if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) { |
10591 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02); | |
10592 | if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) { | |
10593 | vmx->nested.last_vpid = vmcs12->virtual_processor_id; | |
10594 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02); | |
10595 | } | |
10596 | } else { | |
10597 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
10598 | vmx_flush_tlb(vcpu); | |
10599 | } | |
10600 | ||
fe3ef05c NHE |
10601 | } |
10602 | ||
1fb883bb LP |
10603 | if (enable_pml) { |
10604 | /* | |
10605 | * Conceptually we want to copy the PML address and index from | |
10606 | * vmcs01 here, and then back to vmcs01 on nested vmexit. But, | |
10607 | * since we always flush the log on each vmexit, this happens | |
10608 | * to be equivalent to simply resetting the fields in vmcs02. | |
10609 | */ | |
10610 | ASSERT(vmx->pml_pg); | |
10611 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
10612 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
10613 | } | |
10614 | ||
155a97a3 | 10615 | if (nested_cpu_has_ept(vmcs12)) { |
ae1e2d10 PB |
10616 | if (nested_ept_init_mmu_context(vcpu)) { |
10617 | *entry_failure_code = ENTRY_FAIL_DEFAULT; | |
10618 | return 1; | |
10619 | } | |
fb6c8198 JM |
10620 | } else if (nested_cpu_has2(vmcs12, |
10621 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
10622 | vmx_flush_tlb_ept_only(vcpu); | |
155a97a3 NHE |
10623 | } |
10624 | ||
fe3ef05c | 10625 | /* |
bd7e5b08 PB |
10626 | * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those |
10627 | * bits which we consider mandatory enabled. | |
fe3ef05c NHE |
10628 | * The CR0_READ_SHADOW is what L2 should have expected to read given |
10629 | * the specifications by L1; It's not enough to take | |
10630 | * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we | |
10631 | * have more bits than L1 expected. | |
10632 | */ | |
10633 | vmx_set_cr0(vcpu, vmcs12->guest_cr0); | |
10634 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
10635 | ||
10636 | vmx_set_cr4(vcpu, vmcs12->guest_cr4); | |
10637 | vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); | |
10638 | ||
cf8b84f4 JM |
10639 | if (from_vmentry && |
10640 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) | |
5a6a9748 DM |
10641 | vcpu->arch.efer = vmcs12->guest_ia32_efer; |
10642 | else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) | |
10643 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); | |
10644 | else | |
10645 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
10646 | /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ | |
10647 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
10648 | ||
9ed38ffa | 10649 | /* Shadow page tables on either EPT or shadow page tables. */ |
7ad658b6 | 10650 | if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12), |
9ed38ffa LP |
10651 | entry_failure_code)) |
10652 | return 1; | |
7ca29de2 | 10653 | |
feaf0c7d GN |
10654 | if (!enable_ept) |
10655 | vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; | |
10656 | ||
3633cfc3 NHE |
10657 | /* |
10658 | * L1 may access the L2's PDPTR, so save them to construct vmcs12 | |
10659 | */ | |
10660 | if (enable_ept) { | |
10661 | vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); | |
10662 | vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); | |
10663 | vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); | |
10664 | vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); | |
10665 | } | |
10666 | ||
fe3ef05c NHE |
10667 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp); |
10668 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip); | |
ee146c1c | 10669 | return 0; |
fe3ef05c NHE |
10670 | } |
10671 | ||
ca0bde28 | 10672 | static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) |
cd232ad0 | 10673 | { |
cd232ad0 | 10674 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7c177938 | 10675 | |
6dfacadd | 10676 | if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && |
ca0bde28 JM |
10677 | vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) |
10678 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
26539bd0 | 10679 | |
56a20510 JM |
10680 | if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12)) |
10681 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10682 | ||
ca0bde28 JM |
10683 | if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) |
10684 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
7c177938 | 10685 | |
712b12d7 JM |
10686 | if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12)) |
10687 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10688 | ||
ca0bde28 JM |
10689 | if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) |
10690 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
f2b93280 | 10691 | |
ca0bde28 JM |
10692 | if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) |
10693 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
e9ac033e | 10694 | |
c5f983f6 BD |
10695 | if (nested_vmx_check_pml_controls(vcpu, vmcs12)) |
10696 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10697 | ||
7c177938 | 10698 | if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, |
0115f9cb | 10699 | vmx->nested.nested_vmx_procbased_ctls_low, |
b9c237bb | 10700 | vmx->nested.nested_vmx_procbased_ctls_high) || |
2e5b0bd9 JM |
10701 | (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && |
10702 | !vmx_control_verify(vmcs12->secondary_vm_exec_control, | |
10703 | vmx->nested.nested_vmx_secondary_ctls_low, | |
10704 | vmx->nested.nested_vmx_secondary_ctls_high)) || | |
7c177938 | 10705 | !vmx_control_verify(vmcs12->pin_based_vm_exec_control, |
b9c237bb WV |
10706 | vmx->nested.nested_vmx_pinbased_ctls_low, |
10707 | vmx->nested.nested_vmx_pinbased_ctls_high) || | |
7c177938 | 10708 | !vmx_control_verify(vmcs12->vm_exit_controls, |
0115f9cb | 10709 | vmx->nested.nested_vmx_exit_ctls_low, |
b9c237bb | 10710 | vmx->nested.nested_vmx_exit_ctls_high) || |
7c177938 | 10711 | !vmx_control_verify(vmcs12->vm_entry_controls, |
0115f9cb | 10712 | vmx->nested.nested_vmx_entry_ctls_low, |
b9c237bb | 10713 | vmx->nested.nested_vmx_entry_ctls_high)) |
ca0bde28 | 10714 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; |
7c177938 | 10715 | |
41ab9372 BD |
10716 | if (nested_cpu_has_vmfunc(vmcs12)) { |
10717 | if (vmcs12->vm_function_control & | |
10718 | ~vmx->nested.nested_vmx_vmfunc_controls) | |
10719 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10720 | ||
10721 | if (nested_cpu_has_eptp_switching(vmcs12)) { | |
10722 | if (!nested_cpu_has_ept(vmcs12) || | |
10723 | !page_address_valid(vcpu, vmcs12->eptp_list_address)) | |
10724 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10725 | } | |
10726 | } | |
27c42a1b | 10727 | |
c7c2c709 JM |
10728 | if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) |
10729 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10730 | ||
3899152c | 10731 | if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) || |
1dc35dac | 10732 | !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) || |
ca0bde28 JM |
10733 | !nested_cr3_valid(vcpu, vmcs12->host_cr3)) |
10734 | return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; | |
10735 | ||
10736 | return 0; | |
10737 | } | |
10738 | ||
10739 | static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
10740 | u32 *exit_qual) | |
10741 | { | |
10742 | bool ia32e; | |
10743 | ||
10744 | *exit_qual = ENTRY_FAIL_DEFAULT; | |
7c177938 | 10745 | |
3899152c | 10746 | if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) || |
ca0bde28 | 10747 | !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)) |
b428018a | 10748 | return 1; |
ca0bde28 JM |
10749 | |
10750 | if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) && | |
10751 | vmcs12->vmcs_link_pointer != -1ull) { | |
10752 | *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR; | |
b428018a | 10753 | return 1; |
7c177938 NHE |
10754 | } |
10755 | ||
384bb783 | 10756 | /* |
cb0c8cda | 10757 | * If the load IA32_EFER VM-entry control is 1, the following checks |
384bb783 JK |
10758 | * are performed on the field for the IA32_EFER MSR: |
10759 | * - Bits reserved in the IA32_EFER MSR must be 0. | |
10760 | * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of | |
10761 | * the IA-32e mode guest VM-exit control. It must also be identical | |
10762 | * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to | |
10763 | * CR0.PG) is 1. | |
10764 | */ | |
ca0bde28 JM |
10765 | if (to_vmx(vcpu)->nested.nested_run_pending && |
10766 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) { | |
384bb783 JK |
10767 | ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; |
10768 | if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) || | |
10769 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) || | |
10770 | ((vmcs12->guest_cr0 & X86_CR0_PG) && | |
ca0bde28 | 10771 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) |
b428018a | 10772 | return 1; |
384bb783 JK |
10773 | } |
10774 | ||
10775 | /* | |
10776 | * If the load IA32_EFER VM-exit control is 1, bits reserved in the | |
10777 | * IA32_EFER MSR must be 0 in the field for that register. In addition, | |
10778 | * the values of the LMA and LME bits in the field must each be that of | |
10779 | * the host address-space size VM-exit control. | |
10780 | */ | |
10781 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { | |
10782 | ia32e = (vmcs12->vm_exit_controls & | |
10783 | VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0; | |
10784 | if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) || | |
10785 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) || | |
ca0bde28 | 10786 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) |
b428018a | 10787 | return 1; |
ca0bde28 JM |
10788 | } |
10789 | ||
10790 | return 0; | |
10791 | } | |
10792 | ||
858e25c0 JM |
10793 | static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry) |
10794 | { | |
10795 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10796 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
10797 | struct loaded_vmcs *vmcs02; | |
858e25c0 JM |
10798 | u32 msr_entry_idx; |
10799 | u32 exit_qual; | |
10800 | ||
10801 | vmcs02 = nested_get_current_vmcs02(vmx); | |
10802 | if (!vmcs02) | |
10803 | return -ENOMEM; | |
10804 | ||
10805 | enter_guest_mode(vcpu); | |
10806 | ||
10807 | if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) | |
10808 | vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
10809 | ||
1279a6b1 | 10810 | vmx_switch_vmcs(vcpu, vmcs02); |
858e25c0 JM |
10811 | vmx_segment_cache_clear(vmx); |
10812 | ||
10813 | if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) { | |
10814 | leave_guest_mode(vcpu); | |
1279a6b1 | 10815 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
858e25c0 JM |
10816 | nested_vmx_entry_failure(vcpu, vmcs12, |
10817 | EXIT_REASON_INVALID_STATE, exit_qual); | |
10818 | return 1; | |
10819 | } | |
10820 | ||
10821 | nested_get_vmcs12_pages(vcpu, vmcs12); | |
10822 | ||
10823 | msr_entry_idx = nested_vmx_load_msr(vcpu, | |
10824 | vmcs12->vm_entry_msr_load_addr, | |
10825 | vmcs12->vm_entry_msr_load_count); | |
10826 | if (msr_entry_idx) { | |
10827 | leave_guest_mode(vcpu); | |
1279a6b1 | 10828 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
858e25c0 JM |
10829 | nested_vmx_entry_failure(vcpu, vmcs12, |
10830 | EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx); | |
10831 | return 1; | |
10832 | } | |
10833 | ||
858e25c0 JM |
10834 | /* |
10835 | * Note no nested_vmx_succeed or nested_vmx_fail here. At this point | |
10836 | * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet | |
10837 | * returned as far as L1 is concerned. It will only return (and set | |
10838 | * the success flag) when L2 exits (see nested_vmx_vmexit()). | |
10839 | */ | |
10840 | return 0; | |
10841 | } | |
10842 | ||
ca0bde28 JM |
10843 | /* |
10844 | * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 | |
10845 | * for running an L2 nested guest. | |
10846 | */ | |
10847 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) | |
10848 | { | |
10849 | struct vmcs12 *vmcs12; | |
10850 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
b3f1dfb6 | 10851 | u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu); |
ca0bde28 JM |
10852 | u32 exit_qual; |
10853 | int ret; | |
10854 | ||
10855 | if (!nested_vmx_check_permission(vcpu)) | |
10856 | return 1; | |
10857 | ||
10858 | if (!nested_vmx_check_vmcs12(vcpu)) | |
10859 | goto out; | |
10860 | ||
10861 | vmcs12 = get_vmcs12(vcpu); | |
10862 | ||
10863 | if (enable_shadow_vmcs) | |
10864 | copy_shadow_to_vmcs12(vmx); | |
10865 | ||
10866 | /* | |
10867 | * The nested entry process starts with enforcing various prerequisites | |
10868 | * on vmcs12 as required by the Intel SDM, and act appropriately when | |
10869 | * they fail: As the SDM explains, some conditions should cause the | |
10870 | * instruction to fail, while others will cause the instruction to seem | |
10871 | * to succeed, but return an EXIT_REASON_INVALID_STATE. | |
10872 | * To speed up the normal (success) code path, we should avoid checking | |
10873 | * for misconfigurations which will anyway be caught by the processor | |
10874 | * when using the merged vmcs02. | |
10875 | */ | |
b3f1dfb6 JM |
10876 | if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) { |
10877 | nested_vmx_failValid(vcpu, | |
10878 | VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS); | |
10879 | goto out; | |
10880 | } | |
10881 | ||
ca0bde28 JM |
10882 | if (vmcs12->launch_state == launch) { |
10883 | nested_vmx_failValid(vcpu, | |
10884 | launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS | |
10885 | : VMXERR_VMRESUME_NONLAUNCHED_VMCS); | |
10886 | goto out; | |
10887 | } | |
10888 | ||
10889 | ret = check_vmentry_prereqs(vcpu, vmcs12); | |
10890 | if (ret) { | |
10891 | nested_vmx_failValid(vcpu, ret); | |
10892 | goto out; | |
10893 | } | |
10894 | ||
10895 | /* | |
10896 | * After this point, the trap flag no longer triggers a singlestep trap | |
10897 | * on the vm entry instructions; don't call kvm_skip_emulated_instruction. | |
10898 | * This is not 100% correct; for performance reasons, we delegate most | |
10899 | * of the checks on host state to the processor. If those fail, | |
10900 | * the singlestep trap is missed. | |
10901 | */ | |
10902 | skip_emulated_instruction(vcpu); | |
10903 | ||
10904 | ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual); | |
10905 | if (ret) { | |
10906 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10907 | EXIT_REASON_INVALID_STATE, exit_qual); | |
10908 | return 1; | |
384bb783 JK |
10909 | } |
10910 | ||
7c177938 NHE |
10911 | /* |
10912 | * We're finally done with prerequisite checking, and can start with | |
10913 | * the nested entry. | |
10914 | */ | |
10915 | ||
858e25c0 JM |
10916 | ret = enter_vmx_non_root_mode(vcpu, true); |
10917 | if (ret) | |
10918 | return ret; | |
ff651cb6 | 10919 | |
6dfacadd | 10920 | if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) |
5cb56059 | 10921 | return kvm_vcpu_halt(vcpu); |
6dfacadd | 10922 | |
7af40ad3 JK |
10923 | vmx->nested.nested_run_pending = 1; |
10924 | ||
cd232ad0 | 10925 | return 1; |
eb277562 KH |
10926 | |
10927 | out: | |
6affcbed | 10928 | return kvm_skip_emulated_instruction(vcpu); |
cd232ad0 NHE |
10929 | } |
10930 | ||
4704d0be NHE |
10931 | /* |
10932 | * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date | |
10933 | * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK). | |
10934 | * This function returns the new value we should put in vmcs12.guest_cr0. | |
10935 | * It's not enough to just return the vmcs02 GUEST_CR0. Rather, | |
10936 | * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now | |
10937 | * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 | |
10938 | * didn't trap the bit, because if L1 did, so would L0). | |
10939 | * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have | |
10940 | * been modified by L2, and L1 knows it. So just leave the old value of | |
10941 | * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 | |
10942 | * isn't relevant, because if L0 traps this bit it can set it to anything. | |
10943 | * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have | |
10944 | * changed these bits, and therefore they need to be updated, but L0 | |
10945 | * didn't necessarily allow them to be changed in GUEST_CR0 - and rather | |
10946 | * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. | |
10947 | */ | |
10948 | static inline unsigned long | |
10949 | vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
10950 | { | |
10951 | return | |
10952 | /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | | |
10953 | /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | | |
10954 | /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | | |
10955 | vcpu->arch.cr0_guest_owned_bits)); | |
10956 | } | |
10957 | ||
10958 | static inline unsigned long | |
10959 | vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
10960 | { | |
10961 | return | |
10962 | /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | | |
10963 | /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | | |
10964 | /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | | |
10965 | vcpu->arch.cr4_guest_owned_bits)); | |
10966 | } | |
10967 | ||
5f3d5799 JK |
10968 | static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, |
10969 | struct vmcs12 *vmcs12) | |
10970 | { | |
10971 | u32 idt_vectoring; | |
10972 | unsigned int nr; | |
10973 | ||
664f8e26 | 10974 | if (vcpu->arch.exception.injected) { |
5f3d5799 JK |
10975 | nr = vcpu->arch.exception.nr; |
10976 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
10977 | ||
10978 | if (kvm_exception_is_soft(nr)) { | |
10979 | vmcs12->vm_exit_instruction_len = | |
10980 | vcpu->arch.event_exit_inst_len; | |
10981 | idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; | |
10982 | } else | |
10983 | idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; | |
10984 | ||
10985 | if (vcpu->arch.exception.has_error_code) { | |
10986 | idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; | |
10987 | vmcs12->idt_vectoring_error_code = | |
10988 | vcpu->arch.exception.error_code; | |
10989 | } | |
10990 | ||
10991 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
cd2633c5 | 10992 | } else if (vcpu->arch.nmi_injected) { |
5f3d5799 JK |
10993 | vmcs12->idt_vectoring_info_field = |
10994 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; | |
10995 | } else if (vcpu->arch.interrupt.pending) { | |
10996 | nr = vcpu->arch.interrupt.nr; | |
10997 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
10998 | ||
10999 | if (vcpu->arch.interrupt.soft) { | |
11000 | idt_vectoring |= INTR_TYPE_SOFT_INTR; | |
11001 | vmcs12->vm_entry_instruction_len = | |
11002 | vcpu->arch.event_exit_inst_len; | |
11003 | } else | |
11004 | idt_vectoring |= INTR_TYPE_EXT_INTR; | |
11005 | ||
11006 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
11007 | } | |
11008 | } | |
11009 | ||
b6b8a145 JK |
11010 | static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) |
11011 | { | |
11012 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
bfcf83b1 | 11013 | unsigned long exit_qual; |
b6b8a145 | 11014 | |
274bba52 | 11015 | if (kvm_event_needs_reinjection(vcpu)) |
acc9ab60 WL |
11016 | return -EBUSY; |
11017 | ||
bfcf83b1 WL |
11018 | if (vcpu->arch.exception.pending && |
11019 | nested_vmx_check_exception(vcpu, &exit_qual)) { | |
11020 | if (vmx->nested.nested_run_pending) | |
11021 | return -EBUSY; | |
11022 | nested_vmx_inject_exception_vmexit(vcpu, exit_qual); | |
11023 | vcpu->arch.exception.pending = false; | |
11024 | return 0; | |
11025 | } | |
11026 | ||
f4124500 JK |
11027 | if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && |
11028 | vmx->nested.preemption_timer_expired) { | |
11029 | if (vmx->nested.nested_run_pending) | |
11030 | return -EBUSY; | |
11031 | nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); | |
11032 | return 0; | |
11033 | } | |
11034 | ||
b6b8a145 | 11035 | if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) { |
acc9ab60 | 11036 | if (vmx->nested.nested_run_pending) |
b6b8a145 JK |
11037 | return -EBUSY; |
11038 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
11039 | NMI_VECTOR | INTR_TYPE_NMI_INTR | | |
11040 | INTR_INFO_VALID_MASK, 0); | |
11041 | /* | |
11042 | * The NMI-triggered VM exit counts as injection: | |
11043 | * clear this one and block further NMIs. | |
11044 | */ | |
11045 | vcpu->arch.nmi_pending = 0; | |
11046 | vmx_set_nmi_mask(vcpu, true); | |
11047 | return 0; | |
11048 | } | |
11049 | ||
11050 | if ((kvm_cpu_has_interrupt(vcpu) || external_intr) && | |
11051 | nested_exit_on_intr(vcpu)) { | |
11052 | if (vmx->nested.nested_run_pending) | |
11053 | return -EBUSY; | |
11054 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); | |
705699a1 | 11055 | return 0; |
b6b8a145 JK |
11056 | } |
11057 | ||
6342c50a DH |
11058 | vmx_complete_nested_posted_interrupt(vcpu); |
11059 | return 0; | |
b6b8a145 JK |
11060 | } |
11061 | ||
f4124500 JK |
11062 | static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) |
11063 | { | |
11064 | ktime_t remaining = | |
11065 | hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); | |
11066 | u64 value; | |
11067 | ||
11068 | if (ktime_to_ns(remaining) <= 0) | |
11069 | return 0; | |
11070 | ||
11071 | value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; | |
11072 | do_div(value, 1000000); | |
11073 | return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
11074 | } | |
11075 | ||
4704d0be | 11076 | /* |
cf8b84f4 JM |
11077 | * Update the guest state fields of vmcs12 to reflect changes that |
11078 | * occurred while L2 was running. (The "IA-32e mode guest" bit of the | |
11079 | * VM-entry controls is also updated, since this is really a guest | |
11080 | * state bit.) | |
4704d0be | 11081 | */ |
cf8b84f4 | 11082 | static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) |
4704d0be | 11083 | { |
4704d0be NHE |
11084 | vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); |
11085 | vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); | |
11086 | ||
4704d0be NHE |
11087 | vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); |
11088 | vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP); | |
11089 | vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); | |
11090 | ||
11091 | vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); | |
11092 | vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); | |
11093 | vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); | |
11094 | vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); | |
11095 | vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); | |
11096 | vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); | |
11097 | vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); | |
11098 | vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); | |
11099 | vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); | |
11100 | vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); | |
11101 | vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
11102 | vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); | |
11103 | vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); | |
11104 | vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); | |
11105 | vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); | |
11106 | vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); | |
11107 | vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
11108 | vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
11109 | vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); | |
11110 | vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); | |
11111 | vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); | |
11112 | vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); | |
11113 | vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); | |
11114 | vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); | |
11115 | vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); | |
11116 | vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); | |
11117 | vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); | |
11118 | vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); | |
11119 | vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); | |
11120 | vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); | |
11121 | vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); | |
11122 | vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); | |
11123 | vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); | |
11124 | vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); | |
11125 | vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); | |
11126 | vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); | |
11127 | ||
4704d0be NHE |
11128 | vmcs12->guest_interruptibility_info = |
11129 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
11130 | vmcs12->guest_pending_dbg_exceptions = | |
11131 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); | |
3edf1e69 JK |
11132 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
11133 | vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; | |
11134 | else | |
11135 | vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; | |
4704d0be | 11136 | |
f4124500 JK |
11137 | if (nested_cpu_has_preemption_timer(vmcs12)) { |
11138 | if (vmcs12->vm_exit_controls & | |
11139 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER) | |
11140 | vmcs12->vmx_preemption_timer_value = | |
11141 | vmx_get_preemption_timer_value(vcpu); | |
11142 | hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); | |
11143 | } | |
7854cbca | 11144 | |
3633cfc3 NHE |
11145 | /* |
11146 | * In some cases (usually, nested EPT), L2 is allowed to change its | |
11147 | * own CR3 without exiting. If it has changed it, we must keep it. | |
11148 | * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined | |
11149 | * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. | |
11150 | * | |
11151 | * Additionally, restore L2's PDPTR to vmcs12. | |
11152 | */ | |
11153 | if (enable_ept) { | |
f3531054 | 11154 | vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3); |
3633cfc3 NHE |
11155 | vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); |
11156 | vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); | |
11157 | vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); | |
11158 | vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); | |
11159 | } | |
11160 | ||
d281e13b | 11161 | vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS); |
119a9c01 | 11162 | |
608406e2 WV |
11163 | if (nested_cpu_has_vid(vmcs12)) |
11164 | vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS); | |
11165 | ||
c18911a2 JK |
11166 | vmcs12->vm_entry_controls = |
11167 | (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | | |
2961e876 | 11168 | (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); |
c18911a2 | 11169 | |
2996fca0 JK |
11170 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) { |
11171 | kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); | |
11172 | vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
11173 | } | |
11174 | ||
4704d0be NHE |
11175 | /* TODO: These cannot have changed unless we have MSR bitmaps and |
11176 | * the relevant bit asks not to trap the change */ | |
b8c07d55 | 11177 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) |
4704d0be | 11178 | vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT); |
10ba54a5 JK |
11179 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) |
11180 | vmcs12->guest_ia32_efer = vcpu->arch.efer; | |
4704d0be NHE |
11181 | vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS); |
11182 | vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP); | |
11183 | vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP); | |
a87036ad | 11184 | if (kvm_mpx_supported()) |
36be0b9d | 11185 | vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); |
cf8b84f4 JM |
11186 | } |
11187 | ||
11188 | /* | |
11189 | * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits | |
11190 | * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), | |
11191 | * and this function updates it to reflect the changes to the guest state while | |
11192 | * L2 was running (and perhaps made some exits which were handled directly by L0 | |
11193 | * without going back to L1), and to reflect the exit reason. | |
11194 | * Note that we do not have to copy here all VMCS fields, just those that | |
11195 | * could have changed by the L2 guest or the exit - i.e., the guest-state and | |
11196 | * exit-information fields only. Other fields are modified by L1 with VMWRITE, | |
11197 | * which already writes to vmcs12 directly. | |
11198 | */ | |
11199 | static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
11200 | u32 exit_reason, u32 exit_intr_info, | |
11201 | unsigned long exit_qualification) | |
11202 | { | |
11203 | /* update guest state fields: */ | |
11204 | sync_vmcs12(vcpu, vmcs12); | |
4704d0be NHE |
11205 | |
11206 | /* update exit information fields: */ | |
11207 | ||
533558bc JK |
11208 | vmcs12->vm_exit_reason = exit_reason; |
11209 | vmcs12->exit_qualification = exit_qualification; | |
533558bc | 11210 | vmcs12->vm_exit_intr_info = exit_intr_info; |
7313c698 | 11211 | |
5f3d5799 | 11212 | vmcs12->idt_vectoring_info_field = 0; |
4704d0be NHE |
11213 | vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
11214 | vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
11215 | ||
5f3d5799 | 11216 | if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { |
7cdc2d62 JM |
11217 | vmcs12->launch_state = 1; |
11218 | ||
5f3d5799 JK |
11219 | /* vm_entry_intr_info_field is cleared on exit. Emulate this |
11220 | * instead of reading the real value. */ | |
4704d0be | 11221 | vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; |
5f3d5799 JK |
11222 | |
11223 | /* | |
11224 | * Transfer the event that L0 or L1 may wanted to inject into | |
11225 | * L2 to IDT_VECTORING_INFO_FIELD. | |
11226 | */ | |
11227 | vmcs12_save_pending_event(vcpu, vmcs12); | |
11228 | } | |
11229 | ||
11230 | /* | |
11231 | * Drop what we picked up for L2 via vmx_complete_interrupts. It is | |
11232 | * preserved above and would only end up incorrectly in L1. | |
11233 | */ | |
11234 | vcpu->arch.nmi_injected = false; | |
11235 | kvm_clear_exception_queue(vcpu); | |
11236 | kvm_clear_interrupt_queue(vcpu); | |
4704d0be NHE |
11237 | } |
11238 | ||
11239 | /* | |
11240 | * A part of what we need to when the nested L2 guest exits and we want to | |
11241 | * run its L1 parent, is to reset L1's guest state to the host state specified | |
11242 | * in vmcs12. | |
11243 | * This function is to be called not only on normal nested exit, but also on | |
11244 | * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry | |
11245 | * Failures During or After Loading Guest State"). | |
11246 | * This function should be called when the active VMCS is L1's (vmcs01). | |
11247 | */ | |
733568f9 JK |
11248 | static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, |
11249 | struct vmcs12 *vmcs12) | |
4704d0be | 11250 | { |
21feb4eb | 11251 | struct kvm_segment seg; |
ca0bde28 | 11252 | u32 entry_failure_code; |
21feb4eb | 11253 | |
4704d0be NHE |
11254 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) |
11255 | vcpu->arch.efer = vmcs12->host_ia32_efer; | |
d1fa0352 | 11256 | else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) |
4704d0be NHE |
11257 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
11258 | else | |
11259 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
11260 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
11261 | ||
11262 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp); | |
11263 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip); | |
1adfa76a | 11264 | vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); |
4704d0be NHE |
11265 | /* |
11266 | * Note that calling vmx_set_cr0 is important, even if cr0 hasn't | |
bd7e5b08 PB |
11267 | * actually changed, because vmx_set_cr0 refers to efer set above. |
11268 | * | |
11269 | * CR0_GUEST_HOST_MASK is already set in the original vmcs01 | |
11270 | * (KVM doesn't change it); | |
4704d0be | 11271 | */ |
bd7e5b08 | 11272 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
9e3e4dbf | 11273 | vmx_set_cr0(vcpu, vmcs12->host_cr0); |
4704d0be | 11274 | |
bd7e5b08 | 11275 | /* Same as above - no reason to call set_cr4_guest_host_mask(). */ |
4704d0be | 11276 | vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); |
8eb3f87d | 11277 | vmx_set_cr4(vcpu, vmcs12->host_cr4); |
4704d0be | 11278 | |
29bf08f1 | 11279 | nested_ept_uninit_mmu_context(vcpu); |
155a97a3 | 11280 | |
1dc35dac LP |
11281 | /* |
11282 | * Only PDPTE load can fail as the value of cr3 was checked on entry and | |
11283 | * couldn't have changed. | |
11284 | */ | |
11285 | if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code)) | |
11286 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL); | |
4704d0be | 11287 | |
feaf0c7d GN |
11288 | if (!enable_ept) |
11289 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
11290 | ||
4704d0be NHE |
11291 | if (enable_vpid) { |
11292 | /* | |
11293 | * Trivially support vpid by letting L2s share their parent | |
11294 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
11295 | * each L2 its own vpid and exposing the vpid feature to L1. | |
11296 | */ | |
11297 | vmx_flush_tlb(vcpu); | |
11298 | } | |
06a5524f WV |
11299 | /* Restore posted intr vector. */ |
11300 | if (nested_cpu_has_posted_intr(vmcs12)) | |
11301 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); | |
4704d0be NHE |
11302 | |
11303 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); | |
11304 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); | |
11305 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); | |
11306 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); | |
11307 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); | |
4704d0be | 11308 | |
36be0b9d PB |
11309 | /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ |
11310 | if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) | |
11311 | vmcs_write64(GUEST_BNDCFGS, 0); | |
11312 | ||
44811c02 | 11313 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { |
4704d0be | 11314 | vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); |
44811c02 JK |
11315 | vcpu->arch.pat = vmcs12->host_ia32_pat; |
11316 | } | |
4704d0be NHE |
11317 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
11318 | vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, | |
11319 | vmcs12->host_ia32_perf_global_ctrl); | |
503cd0c5 | 11320 | |
21feb4eb ACL |
11321 | /* Set L1 segment info according to Intel SDM |
11322 | 27.5.2 Loading Host Segment and Descriptor-Table Registers */ | |
11323 | seg = (struct kvm_segment) { | |
11324 | .base = 0, | |
11325 | .limit = 0xFFFFFFFF, | |
11326 | .selector = vmcs12->host_cs_selector, | |
11327 | .type = 11, | |
11328 | .present = 1, | |
11329 | .s = 1, | |
11330 | .g = 1 | |
11331 | }; | |
11332 | if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) | |
11333 | seg.l = 1; | |
11334 | else | |
11335 | seg.db = 1; | |
11336 | vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); | |
11337 | seg = (struct kvm_segment) { | |
11338 | .base = 0, | |
11339 | .limit = 0xFFFFFFFF, | |
11340 | .type = 3, | |
11341 | .present = 1, | |
11342 | .s = 1, | |
11343 | .db = 1, | |
11344 | .g = 1 | |
11345 | }; | |
11346 | seg.selector = vmcs12->host_ds_selector; | |
11347 | vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); | |
11348 | seg.selector = vmcs12->host_es_selector; | |
11349 | vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); | |
11350 | seg.selector = vmcs12->host_ss_selector; | |
11351 | vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); | |
11352 | seg.selector = vmcs12->host_fs_selector; | |
11353 | seg.base = vmcs12->host_fs_base; | |
11354 | vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); | |
11355 | seg.selector = vmcs12->host_gs_selector; | |
11356 | seg.base = vmcs12->host_gs_base; | |
11357 | vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); | |
11358 | seg = (struct kvm_segment) { | |
205befd9 | 11359 | .base = vmcs12->host_tr_base, |
21feb4eb ACL |
11360 | .limit = 0x67, |
11361 | .selector = vmcs12->host_tr_selector, | |
11362 | .type = 11, | |
11363 | .present = 1 | |
11364 | }; | |
11365 | vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); | |
11366 | ||
503cd0c5 JK |
11367 | kvm_set_dr(vcpu, 7, 0x400); |
11368 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
ff651cb6 | 11369 | |
3af18d9c WV |
11370 | if (cpu_has_vmx_msr_bitmap()) |
11371 | vmx_set_msr_bitmap(vcpu); | |
11372 | ||
ff651cb6 WV |
11373 | if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr, |
11374 | vmcs12->vm_exit_msr_load_count)) | |
11375 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); | |
4704d0be NHE |
11376 | } |
11377 | ||
11378 | /* | |
11379 | * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 | |
11380 | * and modify vmcs12 to make it see what it would expect to see there if | |
11381 | * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) | |
11382 | */ | |
533558bc JK |
11383 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
11384 | u32 exit_intr_info, | |
11385 | unsigned long exit_qualification) | |
4704d0be NHE |
11386 | { |
11387 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4704d0be NHE |
11388 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
11389 | ||
5f3d5799 JK |
11390 | /* trying to cancel vmlaunch/vmresume is a bug */ |
11391 | WARN_ON_ONCE(vmx->nested.nested_run_pending); | |
11392 | ||
4f350c6d JM |
11393 | /* |
11394 | * The only expected VM-instruction error is "VM entry with | |
11395 | * invalid control field(s)." Anything else indicates a | |
11396 | * problem with L0. | |
11397 | */ | |
11398 | WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) != | |
11399 | VMXERR_ENTRY_INVALID_CONTROL_FIELD)); | |
11400 | ||
4704d0be | 11401 | leave_guest_mode(vcpu); |
4704d0be | 11402 | |
4f350c6d JM |
11403 | if (likely(!vmx->fail)) { |
11404 | prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info, | |
11405 | exit_qualification); | |
ff651cb6 | 11406 | |
4f350c6d JM |
11407 | if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr, |
11408 | vmcs12->vm_exit_msr_store_count)) | |
11409 | nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL); | |
11410 | } | |
cf3215d9 | 11411 | |
1279a6b1 | 11412 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
8391ce44 PB |
11413 | vm_entry_controls_reset_shadow(vmx); |
11414 | vm_exit_controls_reset_shadow(vmx); | |
36c3cc42 JK |
11415 | vmx_segment_cache_clear(vmx); |
11416 | ||
4704d0be NHE |
11417 | /* if no vmcs02 cache requested, remove the one we used */ |
11418 | if (VMCS02_POOL_SIZE == 0) | |
11419 | nested_free_vmcs02(vmx, vmx->nested.current_vmptr); | |
11420 | ||
9314006d | 11421 | /* Update any VMCS fields that might have changed while L2 ran */ |
83bafef1 JM |
11422 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr); |
11423 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
ea26e4ec | 11424 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
9314006d PB |
11425 | if (vmx->hv_deadline_tsc == -1) |
11426 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11427 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
11428 | else | |
11429 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11430 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c95ba92a PF |
11431 | if (kvm_has_tsc_control) |
11432 | decache_tsc_multiplier(vmx); | |
4704d0be | 11433 | |
dccbfcf5 RK |
11434 | if (vmx->nested.change_vmcs01_virtual_x2apic_mode) { |
11435 | vmx->nested.change_vmcs01_virtual_x2apic_mode = false; | |
11436 | vmx_set_virtual_x2apic_mode(vcpu, | |
11437 | vcpu->arch.apic_base & X2APIC_ENABLE); | |
fb6c8198 JM |
11438 | } else if (!nested_cpu_has_ept(vmcs12) && |
11439 | nested_cpu_has2(vmcs12, | |
11440 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
11441 | vmx_flush_tlb_ept_only(vcpu); | |
dccbfcf5 | 11442 | } |
4704d0be NHE |
11443 | |
11444 | /* This is needed for same reason as it was needed in prepare_vmcs02 */ | |
11445 | vmx->host_rsp = 0; | |
11446 | ||
11447 | /* Unpin physical memory we referred to in vmcs02 */ | |
11448 | if (vmx->nested.apic_access_page) { | |
53a70daf | 11449 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
48d89b92 | 11450 | vmx->nested.apic_access_page = NULL; |
4704d0be | 11451 | } |
a7c0b07d | 11452 | if (vmx->nested.virtual_apic_page) { |
53a70daf | 11453 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
48d89b92 | 11454 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 11455 | } |
705699a1 WV |
11456 | if (vmx->nested.pi_desc_page) { |
11457 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 11458 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
705699a1 WV |
11459 | vmx->nested.pi_desc_page = NULL; |
11460 | vmx->nested.pi_desc = NULL; | |
11461 | } | |
4704d0be | 11462 | |
38b99173 TC |
11463 | /* |
11464 | * We are now running in L2, mmu_notifier will force to reload the | |
11465 | * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1. | |
11466 | */ | |
c83b6d15 | 11467 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
38b99173 | 11468 | |
012f83cb AG |
11469 | if (enable_shadow_vmcs) |
11470 | vmx->nested.sync_shadow_vmcs = true; | |
b6b8a145 JK |
11471 | |
11472 | /* in case we halted in L2 */ | |
11473 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4f350c6d JM |
11474 | |
11475 | if (likely(!vmx->fail)) { | |
11476 | /* | |
11477 | * TODO: SDM says that with acknowledge interrupt on | |
11478 | * exit, bit 31 of the VM-exit interrupt information | |
11479 | * (valid interrupt) is always set to 1 on | |
11480 | * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't | |
11481 | * need kvm_cpu_has_interrupt(). See the commit | |
11482 | * message for details. | |
11483 | */ | |
11484 | if (nested_exit_intr_ack_set(vcpu) && | |
11485 | exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT && | |
11486 | kvm_cpu_has_interrupt(vcpu)) { | |
11487 | int irq = kvm_cpu_get_interrupt(vcpu); | |
11488 | WARN_ON(irq < 0); | |
11489 | vmcs12->vm_exit_intr_info = irq | | |
11490 | INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; | |
11491 | } | |
11492 | ||
11493 | trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, | |
11494 | vmcs12->exit_qualification, | |
11495 | vmcs12->idt_vectoring_info_field, | |
11496 | vmcs12->vm_exit_intr_info, | |
11497 | vmcs12->vm_exit_intr_error_code, | |
11498 | KVM_ISA_VMX); | |
11499 | ||
11500 | load_vmcs12_host_state(vcpu, vmcs12); | |
11501 | ||
11502 | return; | |
11503 | } | |
11504 | ||
11505 | /* | |
11506 | * After an early L2 VM-entry failure, we're now back | |
11507 | * in L1 which thinks it just finished a VMLAUNCH or | |
11508 | * VMRESUME instruction, so we need to set the failure | |
11509 | * flag and the VM-instruction error field of the VMCS | |
11510 | * accordingly. | |
11511 | */ | |
11512 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
11513 | /* | |
11514 | * The emulated instruction was already skipped in | |
11515 | * nested_vmx_run, but the updated RIP was never | |
11516 | * written back to the vmcs01. | |
11517 | */ | |
11518 | skip_emulated_instruction(vcpu); | |
11519 | vmx->fail = 0; | |
4704d0be NHE |
11520 | } |
11521 | ||
42124925 JK |
11522 | /* |
11523 | * Forcibly leave nested mode in order to be able to reset the VCPU later on. | |
11524 | */ | |
11525 | static void vmx_leave_nested(struct kvm_vcpu *vcpu) | |
11526 | { | |
2f707d97 WL |
11527 | if (is_guest_mode(vcpu)) { |
11528 | to_vmx(vcpu)->nested.nested_run_pending = 0; | |
533558bc | 11529 | nested_vmx_vmexit(vcpu, -1, 0, 0); |
2f707d97 | 11530 | } |
42124925 JK |
11531 | free_nested(to_vmx(vcpu)); |
11532 | } | |
11533 | ||
7c177938 NHE |
11534 | /* |
11535 | * L1's failure to enter L2 is a subset of a normal exit, as explained in | |
11536 | * 23.7 "VM-entry failures during or after loading guest state" (this also | |
11537 | * lists the acceptable exit-reason and exit-qualification parameters). | |
11538 | * It should only be called before L2 actually succeeded to run, and when | |
11539 | * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss). | |
11540 | */ | |
11541 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, | |
11542 | struct vmcs12 *vmcs12, | |
11543 | u32 reason, unsigned long qualification) | |
11544 | { | |
11545 | load_vmcs12_host_state(vcpu, vmcs12); | |
11546 | vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY; | |
11547 | vmcs12->exit_qualification = qualification; | |
11548 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
11549 | if (enable_shadow_vmcs) |
11550 | to_vmx(vcpu)->nested.sync_shadow_vmcs = true; | |
7c177938 NHE |
11551 | } |
11552 | ||
8a76d7f2 JR |
11553 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
11554 | struct x86_instruction_info *info, | |
11555 | enum x86_intercept_stage stage) | |
11556 | { | |
11557 | return X86EMUL_CONTINUE; | |
11558 | } | |
11559 | ||
64672c95 YJ |
11560 | #ifdef CONFIG_X86_64 |
11561 | /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ | |
11562 | static inline int u64_shl_div_u64(u64 a, unsigned int shift, | |
11563 | u64 divisor, u64 *result) | |
11564 | { | |
11565 | u64 low = a << shift, high = a >> (64 - shift); | |
11566 | ||
11567 | /* To avoid the overflow on divq */ | |
11568 | if (high >= divisor) | |
11569 | return 1; | |
11570 | ||
11571 | /* Low hold the result, high hold rem which is discarded */ | |
11572 | asm("divq %2\n\t" : "=a" (low), "=d" (high) : | |
11573 | "rm" (divisor), "0" (low), "1" (high)); | |
11574 | *result = low; | |
11575 | ||
11576 | return 0; | |
11577 | } | |
11578 | ||
11579 | static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc) | |
11580 | { | |
11581 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9175d2e9 PB |
11582 | u64 tscl = rdtsc(); |
11583 | u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); | |
11584 | u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; | |
64672c95 YJ |
11585 | |
11586 | /* Convert to host delta tsc if tsc scaling is enabled */ | |
11587 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && | |
11588 | u64_shl_div_u64(delta_tsc, | |
11589 | kvm_tsc_scaling_ratio_frac_bits, | |
11590 | vcpu->arch.tsc_scaling_ratio, | |
11591 | &delta_tsc)) | |
11592 | return -ERANGE; | |
11593 | ||
11594 | /* | |
11595 | * If the delta tsc can't fit in the 32 bit after the multi shift, | |
11596 | * we can't use the preemption timer. | |
11597 | * It's possible that it fits on later vmentries, but checking | |
11598 | * on every vmentry is costly so we just use an hrtimer. | |
11599 | */ | |
11600 | if (delta_tsc >> (cpu_preemption_timer_multi + 32)) | |
11601 | return -ERANGE; | |
11602 | ||
11603 | vmx->hv_deadline_tsc = tscl + delta_tsc; | |
11604 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11605 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c8533544 WL |
11606 | |
11607 | return delta_tsc == 0; | |
64672c95 YJ |
11608 | } |
11609 | ||
11610 | static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) | |
11611 | { | |
11612 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
11613 | vmx->hv_deadline_tsc = -1; | |
11614 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11615 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
11616 | } | |
11617 | #endif | |
11618 | ||
48d89b92 | 11619 | static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) |
ae97a3b8 | 11620 | { |
b4a2d31d RK |
11621 | if (ple_gap) |
11622 | shrink_ple_window(vcpu); | |
ae97a3b8 RK |
11623 | } |
11624 | ||
843e4330 KH |
11625 | static void vmx_slot_enable_log_dirty(struct kvm *kvm, |
11626 | struct kvm_memory_slot *slot) | |
11627 | { | |
11628 | kvm_mmu_slot_leaf_clear_dirty(kvm, slot); | |
11629 | kvm_mmu_slot_largepage_remove_write_access(kvm, slot); | |
11630 | } | |
11631 | ||
11632 | static void vmx_slot_disable_log_dirty(struct kvm *kvm, | |
11633 | struct kvm_memory_slot *slot) | |
11634 | { | |
11635 | kvm_mmu_slot_set_dirty(kvm, slot); | |
11636 | } | |
11637 | ||
11638 | static void vmx_flush_log_dirty(struct kvm *kvm) | |
11639 | { | |
11640 | kvm_flush_pml_buffers(kvm); | |
11641 | } | |
11642 | ||
c5f983f6 BD |
11643 | static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) |
11644 | { | |
11645 | struct vmcs12 *vmcs12; | |
11646 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
11647 | gpa_t gpa; | |
11648 | struct page *page = NULL; | |
11649 | u64 *pml_address; | |
11650 | ||
11651 | if (is_guest_mode(vcpu)) { | |
11652 | WARN_ON_ONCE(vmx->nested.pml_full); | |
11653 | ||
11654 | /* | |
11655 | * Check if PML is enabled for the nested guest. | |
11656 | * Whether eptp bit 6 is set is already checked | |
11657 | * as part of A/D emulation. | |
11658 | */ | |
11659 | vmcs12 = get_vmcs12(vcpu); | |
11660 | if (!nested_cpu_has_pml(vmcs12)) | |
11661 | return 0; | |
11662 | ||
4769886b | 11663 | if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { |
c5f983f6 BD |
11664 | vmx->nested.pml_full = true; |
11665 | return 1; | |
11666 | } | |
11667 | ||
11668 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; | |
11669 | ||
5e2f30b7 DH |
11670 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address); |
11671 | if (is_error_page(page)) | |
c5f983f6 BD |
11672 | return 0; |
11673 | ||
11674 | pml_address = kmap(page); | |
11675 | pml_address[vmcs12->guest_pml_index--] = gpa; | |
11676 | kunmap(page); | |
53a70daf | 11677 | kvm_release_page_clean(page); |
c5f983f6 BD |
11678 | } |
11679 | ||
11680 | return 0; | |
11681 | } | |
11682 | ||
843e4330 KH |
11683 | static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, |
11684 | struct kvm_memory_slot *memslot, | |
11685 | gfn_t offset, unsigned long mask) | |
11686 | { | |
11687 | kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); | |
11688 | } | |
11689 | ||
cd39e117 PB |
11690 | static void __pi_post_block(struct kvm_vcpu *vcpu) |
11691 | { | |
11692 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
11693 | struct pi_desc old, new; | |
11694 | unsigned int dest; | |
cd39e117 PB |
11695 | |
11696 | do { | |
11697 | old.control = new.control = pi_desc->control; | |
8b306e2f PB |
11698 | WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, |
11699 | "Wakeup handler not enabled while the VCPU is blocked\n"); | |
cd39e117 PB |
11700 | |
11701 | dest = cpu_physical_id(vcpu->cpu); | |
11702 | ||
11703 | if (x2apic_enabled()) | |
11704 | new.ndst = dest; | |
11705 | else | |
11706 | new.ndst = (dest << 8) & 0xFF00; | |
11707 | ||
cd39e117 PB |
11708 | /* set 'NV' to 'notification vector' */ |
11709 | new.nv = POSTED_INTR_VECTOR; | |
c0a1666b PB |
11710 | } while (cmpxchg64(&pi_desc->control, old.control, |
11711 | new.control) != old.control); | |
cd39e117 | 11712 | |
8b306e2f PB |
11713 | if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { |
11714 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
cd39e117 | 11715 | list_del(&vcpu->blocked_vcpu_list); |
8b306e2f | 11716 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); |
cd39e117 PB |
11717 | vcpu->pre_pcpu = -1; |
11718 | } | |
11719 | } | |
11720 | ||
bf9f6ac8 FW |
11721 | /* |
11722 | * This routine does the following things for vCPU which is going | |
11723 | * to be blocked if VT-d PI is enabled. | |
11724 | * - Store the vCPU to the wakeup list, so when interrupts happen | |
11725 | * we can find the right vCPU to wake up. | |
11726 | * - Change the Posted-interrupt descriptor as below: | |
11727 | * 'NDST' <-- vcpu->pre_pcpu | |
11728 | * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR | |
11729 | * - If 'ON' is set during this process, which means at least one | |
11730 | * interrupt is posted for this vCPU, we cannot block it, in | |
11731 | * this case, return 1, otherwise, return 0. | |
11732 | * | |
11733 | */ | |
bc22512b | 11734 | static int pi_pre_block(struct kvm_vcpu *vcpu) |
bf9f6ac8 | 11735 | { |
bf9f6ac8 FW |
11736 | unsigned int dest; |
11737 | struct pi_desc old, new; | |
11738 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
11739 | ||
11740 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
11741 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
11742 | !kvm_vcpu_apicv_active(vcpu)) | |
bf9f6ac8 FW |
11743 | return 0; |
11744 | ||
8b306e2f PB |
11745 | WARN_ON(irqs_disabled()); |
11746 | local_irq_disable(); | |
11747 | if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { | |
11748 | vcpu->pre_pcpu = vcpu->cpu; | |
11749 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
11750 | list_add_tail(&vcpu->blocked_vcpu_list, | |
11751 | &per_cpu(blocked_vcpu_on_cpu, | |
11752 | vcpu->pre_pcpu)); | |
11753 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
11754 | } | |
bf9f6ac8 FW |
11755 | |
11756 | do { | |
11757 | old.control = new.control = pi_desc->control; | |
11758 | ||
bf9f6ac8 FW |
11759 | WARN((pi_desc->sn == 1), |
11760 | "Warning: SN field of posted-interrupts " | |
11761 | "is set before blocking\n"); | |
11762 | ||
11763 | /* | |
11764 | * Since vCPU can be preempted during this process, | |
11765 | * vcpu->cpu could be different with pre_pcpu, we | |
11766 | * need to set pre_pcpu as the destination of wakeup | |
11767 | * notification event, then we can find the right vCPU | |
11768 | * to wakeup in wakeup handler if interrupts happen | |
11769 | * when the vCPU is in blocked state. | |
11770 | */ | |
11771 | dest = cpu_physical_id(vcpu->pre_pcpu); | |
11772 | ||
11773 | if (x2apic_enabled()) | |
11774 | new.ndst = dest; | |
11775 | else | |
11776 | new.ndst = (dest << 8) & 0xFF00; | |
11777 | ||
11778 | /* set 'NV' to 'wakeup vector' */ | |
11779 | new.nv = POSTED_INTR_WAKEUP_VECTOR; | |
c0a1666b PB |
11780 | } while (cmpxchg64(&pi_desc->control, old.control, |
11781 | new.control) != old.control); | |
bf9f6ac8 | 11782 | |
8b306e2f PB |
11783 | /* We should not block the vCPU if an interrupt is posted for it. */ |
11784 | if (pi_test_on(pi_desc) == 1) | |
11785 | __pi_post_block(vcpu); | |
11786 | ||
11787 | local_irq_enable(); | |
11788 | return (vcpu->pre_pcpu == -1); | |
bf9f6ac8 FW |
11789 | } |
11790 | ||
bc22512b YJ |
11791 | static int vmx_pre_block(struct kvm_vcpu *vcpu) |
11792 | { | |
11793 | if (pi_pre_block(vcpu)) | |
11794 | return 1; | |
11795 | ||
64672c95 YJ |
11796 | if (kvm_lapic_hv_timer_in_use(vcpu)) |
11797 | kvm_lapic_switch_to_sw_timer(vcpu); | |
11798 | ||
bc22512b YJ |
11799 | return 0; |
11800 | } | |
11801 | ||
11802 | static void pi_post_block(struct kvm_vcpu *vcpu) | |
bf9f6ac8 | 11803 | { |
8b306e2f | 11804 | if (vcpu->pre_pcpu == -1) |
bf9f6ac8 FW |
11805 | return; |
11806 | ||
8b306e2f PB |
11807 | WARN_ON(irqs_disabled()); |
11808 | local_irq_disable(); | |
cd39e117 | 11809 | __pi_post_block(vcpu); |
8b306e2f | 11810 | local_irq_enable(); |
bf9f6ac8 FW |
11811 | } |
11812 | ||
bc22512b YJ |
11813 | static void vmx_post_block(struct kvm_vcpu *vcpu) |
11814 | { | |
64672c95 YJ |
11815 | if (kvm_x86_ops->set_hv_timer) |
11816 | kvm_lapic_switch_to_hv_timer(vcpu); | |
11817 | ||
bc22512b YJ |
11818 | pi_post_block(vcpu); |
11819 | } | |
11820 | ||
efc64404 FW |
11821 | /* |
11822 | * vmx_update_pi_irte - set IRTE for Posted-Interrupts | |
11823 | * | |
11824 | * @kvm: kvm | |
11825 | * @host_irq: host irq of the interrupt | |
11826 | * @guest_irq: gsi of the interrupt | |
11827 | * @set: set or unset PI | |
11828 | * returns 0 on success, < 0 on failure | |
11829 | */ | |
11830 | static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
11831 | uint32_t guest_irq, bool set) | |
11832 | { | |
11833 | struct kvm_kernel_irq_routing_entry *e; | |
11834 | struct kvm_irq_routing_table *irq_rt; | |
11835 | struct kvm_lapic_irq irq; | |
11836 | struct kvm_vcpu *vcpu; | |
11837 | struct vcpu_data vcpu_info; | |
3a8b0677 | 11838 | int idx, ret = 0; |
efc64404 FW |
11839 | |
11840 | if (!kvm_arch_has_assigned_device(kvm) || | |
a0052191 YZ |
11841 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
11842 | !kvm_vcpu_apicv_active(kvm->vcpus[0])) | |
efc64404 FW |
11843 | return 0; |
11844 | ||
11845 | idx = srcu_read_lock(&kvm->irq_srcu); | |
11846 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
3a8b0677 JS |
11847 | if (guest_irq >= irq_rt->nr_rt_entries || |
11848 | hlist_empty(&irq_rt->map[guest_irq])) { | |
11849 | pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", | |
11850 | guest_irq, irq_rt->nr_rt_entries); | |
11851 | goto out; | |
11852 | } | |
efc64404 FW |
11853 | |
11854 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
11855 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
11856 | continue; | |
11857 | /* | |
11858 | * VT-d PI cannot support posting multicast/broadcast | |
11859 | * interrupts to a vCPU, we still use interrupt remapping | |
11860 | * for these kind of interrupts. | |
11861 | * | |
11862 | * For lowest-priority interrupts, we only support | |
11863 | * those with single CPU as the destination, e.g. user | |
11864 | * configures the interrupts via /proc/irq or uses | |
11865 | * irqbalance to make the interrupts single-CPU. | |
11866 | * | |
11867 | * We will support full lowest-priority interrupt later. | |
11868 | */ | |
11869 | ||
37131313 | 11870 | kvm_set_msi_irq(kvm, e, &irq); |
23a1c257 FW |
11871 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { |
11872 | /* | |
11873 | * Make sure the IRTE is in remapped mode if | |
11874 | * we don't handle it in posted mode. | |
11875 | */ | |
11876 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
11877 | if (ret < 0) { | |
11878 | printk(KERN_INFO | |
11879 | "failed to back to remapped mode, irq: %u\n", | |
11880 | host_irq); | |
11881 | goto out; | |
11882 | } | |
11883 | ||
efc64404 | 11884 | continue; |
23a1c257 | 11885 | } |
efc64404 FW |
11886 | |
11887 | vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); | |
11888 | vcpu_info.vector = irq.vector; | |
11889 | ||
b6ce9780 | 11890 | trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi, |
efc64404 FW |
11891 | vcpu_info.vector, vcpu_info.pi_desc_addr, set); |
11892 | ||
11893 | if (set) | |
11894 | ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); | |
dc91f2eb | 11895 | else |
efc64404 | 11896 | ret = irq_set_vcpu_affinity(host_irq, NULL); |
efc64404 FW |
11897 | |
11898 | if (ret < 0) { | |
11899 | printk(KERN_INFO "%s: failed to update PI IRTE\n", | |
11900 | __func__); | |
11901 | goto out; | |
11902 | } | |
11903 | } | |
11904 | ||
11905 | ret = 0; | |
11906 | out: | |
11907 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
11908 | return ret; | |
11909 | } | |
11910 | ||
c45dcc71 AR |
11911 | static void vmx_setup_mce(struct kvm_vcpu *vcpu) |
11912 | { | |
11913 | if (vcpu->arch.mcg_cap & MCG_LMCE_P) | |
11914 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
11915 | FEATURE_CONTROL_LMCE; | |
11916 | else | |
11917 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
11918 | ~FEATURE_CONTROL_LMCE; | |
11919 | } | |
11920 | ||
404f6aac | 11921 | static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { |
6aa8b732 AK |
11922 | .cpu_has_kvm_support = cpu_has_kvm_support, |
11923 | .disabled_by_bios = vmx_disabled_by_bios, | |
11924 | .hardware_setup = hardware_setup, | |
11925 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 11926 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
11927 | .hardware_enable = hardware_enable, |
11928 | .hardware_disable = hardware_disable, | |
04547156 | 11929 | .cpu_has_accelerated_tpr = report_flexpriority, |
6d396b55 | 11930 | .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase, |
6aa8b732 AK |
11931 | |
11932 | .vcpu_create = vmx_create_vcpu, | |
11933 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 11934 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 11935 | |
04d2cc77 | 11936 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
11937 | .vcpu_load = vmx_vcpu_load, |
11938 | .vcpu_put = vmx_vcpu_put, | |
11939 | ||
a96036b8 | 11940 | .update_bp_intercept = update_exception_bitmap, |
6aa8b732 AK |
11941 | .get_msr = vmx_get_msr, |
11942 | .set_msr = vmx_set_msr, | |
11943 | .get_segment_base = vmx_get_segment_base, | |
11944 | .get_segment = vmx_get_segment, | |
11945 | .set_segment = vmx_set_segment, | |
2e4d2653 | 11946 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 11947 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 11948 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 11949 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 11950 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 11951 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
11952 | .set_cr3 = vmx_set_cr3, |
11953 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 11954 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
11955 | .get_idt = vmx_get_idt, |
11956 | .set_idt = vmx_set_idt, | |
11957 | .get_gdt = vmx_get_gdt, | |
11958 | .set_gdt = vmx_set_gdt, | |
73aaf249 JK |
11959 | .get_dr6 = vmx_get_dr6, |
11960 | .set_dr6 = vmx_set_dr6, | |
020df079 | 11961 | .set_dr7 = vmx_set_dr7, |
81908bf4 | 11962 | .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, |
5fdbf976 | 11963 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
11964 | .get_rflags = vmx_get_rflags, |
11965 | .set_rflags = vmx_set_rflags, | |
be94f6b7 | 11966 | |
6aa8b732 | 11967 | .tlb_flush = vmx_flush_tlb, |
6aa8b732 | 11968 | |
6aa8b732 | 11969 | .run = vmx_vcpu_run, |
6062d012 | 11970 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 11971 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
11972 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
11973 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 11974 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 11975 | .set_irq = vmx_inject_irq, |
95ba8273 | 11976 | .set_nmi = vmx_inject_nmi, |
298101da | 11977 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 11978 | .cancel_injection = vmx_cancel_injection, |
78646121 | 11979 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 11980 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
11981 | .get_nmi_mask = vmx_get_nmi_mask, |
11982 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
11983 | .enable_nmi_window = enable_nmi_window, |
11984 | .enable_irq_window = enable_irq_window, | |
11985 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 11986 | .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode, |
38b99173 | 11987 | .set_apic_access_page_addr = vmx_set_apic_access_page_addr, |
d62caabb AS |
11988 | .get_enable_apicv = vmx_get_enable_apicv, |
11989 | .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, | |
c7c9c56c | 11990 | .load_eoi_exitmap = vmx_load_eoi_exitmap, |
967235d3 | 11991 | .apicv_post_state_restore = vmx_apicv_post_state_restore, |
c7c9c56c YZ |
11992 | .hwapic_irr_update = vmx_hwapic_irr_update, |
11993 | .hwapic_isr_update = vmx_hwapic_isr_update, | |
a20ed54d YZ |
11994 | .sync_pir_to_irr = vmx_sync_pir_to_irr, |
11995 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, | |
95ba8273 | 11996 | |
cbc94022 | 11997 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 11998 | .get_tdp_level = get_ept_level, |
4b12f0de | 11999 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 12000 | |
586f9607 | 12001 | .get_exit_info = vmx_get_exit_info, |
586f9607 | 12002 | |
17cc3935 | 12003 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
12004 | |
12005 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
12006 | |
12007 | .rdtscp_supported = vmx_rdtscp_supported, | |
ad756a16 | 12008 | .invpcid_supported = vmx_invpcid_supported, |
d4330ef2 JR |
12009 | |
12010 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
12011 | |
12012 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a ZA |
12013 | |
12014 | .write_tsc_offset = vmx_write_tsc_offset, | |
1c97f0a0 JR |
12015 | |
12016 | .set_tdp_cr3 = vmx_set_cr3, | |
8a76d7f2 JR |
12017 | |
12018 | .check_intercept = vmx_check_intercept, | |
a547c6db | 12019 | .handle_external_intr = vmx_handle_external_intr, |
da8999d3 | 12020 | .mpx_supported = vmx_mpx_supported, |
55412b2e | 12021 | .xsaves_supported = vmx_xsaves_supported, |
b6b8a145 JK |
12022 | |
12023 | .check_nested_events = vmx_check_nested_events, | |
ae97a3b8 RK |
12024 | |
12025 | .sched_in = vmx_sched_in, | |
843e4330 KH |
12026 | |
12027 | .slot_enable_log_dirty = vmx_slot_enable_log_dirty, | |
12028 | .slot_disable_log_dirty = vmx_slot_disable_log_dirty, | |
12029 | .flush_log_dirty = vmx_flush_log_dirty, | |
12030 | .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, | |
c5f983f6 | 12031 | .write_log_dirty = vmx_write_pml_buffer, |
25462f7f | 12032 | |
bf9f6ac8 FW |
12033 | .pre_block = vmx_pre_block, |
12034 | .post_block = vmx_post_block, | |
12035 | ||
25462f7f | 12036 | .pmu_ops = &intel_pmu_ops, |
efc64404 FW |
12037 | |
12038 | .update_pi_irte = vmx_update_pi_irte, | |
64672c95 YJ |
12039 | |
12040 | #ifdef CONFIG_X86_64 | |
12041 | .set_hv_timer = vmx_set_hv_timer, | |
12042 | .cancel_hv_timer = vmx_cancel_hv_timer, | |
12043 | #endif | |
c45dcc71 AR |
12044 | |
12045 | .setup_mce = vmx_setup_mce, | |
6aa8b732 AK |
12046 | }; |
12047 | ||
12048 | static int __init vmx_init(void) | |
12049 | { | |
34a1cd60 TC |
12050 | int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
12051 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
fdef3ad1 | 12052 | if (r) |
34a1cd60 | 12053 | return r; |
25c5f225 | 12054 | |
2965faa5 | 12055 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
12056 | rcu_assign_pointer(crash_vmclear_loaded_vmcss, |
12057 | crash_vmclear_local_loaded_vmcss); | |
12058 | #endif | |
12059 | ||
fdef3ad1 | 12060 | return 0; |
6aa8b732 AK |
12061 | } |
12062 | ||
12063 | static void __exit vmx_exit(void) | |
12064 | { | |
2965faa5 | 12065 | #ifdef CONFIG_KEXEC_CORE |
3b63a43f | 12066 | RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); |
8f536b76 ZY |
12067 | synchronize_rcu(); |
12068 | #endif | |
12069 | ||
cb498ea2 | 12070 | kvm_exit(); |
6aa8b732 AK |
12071 | } |
12072 | ||
12073 | module_init(vmx_init) | |
12074 | module_exit(vmx_exit) |