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KVM: VMX: Allow single-stepping when uninterruptible
[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
5fdbf976 28#include "kvm_cache_regs.h"
35920a35 29#include "x86.h"
e495606d 30
6aa8b732 31#include <asm/io.h>
3b3be0d1 32#include <asm/desc.h>
13673a90 33#include <asm/vmx.h>
6210e37b 34#include <asm/virtext.h>
6aa8b732 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
c7addb90
AK		 41static int bypass_guest_pf = 1;
42module_param(bypass_guest_pf, bool, 0);
43
2384d2b3
SY		 44static int enable_vpid = 1;
45module_param(enable_vpid, bool, 0);
46
4c9fc8ef
AK		 47static int flexpriority_enabled = 1;
48module_param(flexpriority_enabled, bool, 0);
49
1439442c 50static int enable_ept = 1;
d56f546d
SY		 51module_param(enable_ept, bool, 0);
52
04fa4d32
MG		 53static int emulate_invalid_guest_state = 0;
54module_param(emulate_invalid_guest_state, bool, 0);
55
a2fa3e9f
GH		 56struct vmcs {
57 u32 revision_id;
58 u32 abort;
59 char data[0];
60};
61
62struct vcpu_vmx {
fb3f0f51 63 struct kvm_vcpu vcpu;
543e4243 64 struct list_head local_vcpus_link;
313dbd49 65 unsigned long host_rsp;
a2fa3e9f 66 int launched;
29bd8a78 67 u8 fail;
1155f76a 68 u32 idt_vectoring_info;
a2fa3e9f
GH		 69 struct kvm_msr_entry *guest_msrs;
70 struct kvm_msr_entry *host_msrs;
71 int nmsrs;
72 int save_nmsrs;
73 int msr_offset_efer;
74#ifdef CONFIG_X86_64
75 int msr_offset_kernel_gs_base;
76#endif
77 struct vmcs *vmcs;
78 struct {
79 int loaded;
80 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 81 int gs_ldt_reload_needed;
82 int fs_reload_needed;
51c6cf66 83 int guest_efer_loaded;
d77c26fc 84 } host_state;
9c8cba37
AK		 85 struct {
86 struct {
87 bool pending;
88 u8 vector;
89 unsigned rip;
90 } irq;
91 } rmode;
2384d2b3 92 int vpid;
04fa4d32 93 bool emulation_required;
3b86cd99
JK		 94
95 /* Support for vnmi-less CPUs */
96 int soft_vnmi_blocked;
97 ktime_t entry_time;
98 s64 vnmi_blocked_time;
a2fa3e9f
GH		 99};
100
101static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
102{
fb3f0f51 103 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 104}
105
b7ebfb05 106static int init_rmode(struct kvm *kvm);
4e1096d2 107static u64 construct_eptp(unsigned long root_hpa);
75880a01 108
6aa8b732
AK		 109static DEFINE_PER_CPU(struct vmcs *, vmxarea);
110static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 111static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 112
fdef3ad1
HQ		 113static struct page *vmx_io_bitmap_a;
114static struct page *vmx_io_bitmap_b;
25c5f225 115static struct page *vmx_msr_bitmap;
fdef3ad1 116
2384d2b3
SY		 117static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
118static DEFINE_SPINLOCK(vmx_vpid_lock);
119
1c3d14fe 120static struct vmcs_config {
6aa8b732
AK		 121 int size;
122 int order;
123 u32 revision_id;
1c3d14fe
YS		 124 u32 pin_based_exec_ctrl;
125 u32 cpu_based_exec_ctrl;
f78e0e2e 126 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 127 u32 vmexit_ctrl;
128 u32 vmentry_ctrl;
129} vmcs_config;
6aa8b732 130
efff9e53 131static struct vmx_capability {
d56f546d
SY		 132 u32 ept;
133 u32 vpid;
134} vmx_capability;
135
6aa8b732
AK		 136#define VMX_SEGMENT_FIELD(seg) \
137 [VCPU_SREG_##seg] = { \
138 .selector = GUEST_##seg##_SELECTOR, \
139 .base = GUEST_##seg##_BASE, \
140 .limit = GUEST_##seg##_LIMIT, \
141 .ar_bytes = GUEST_##seg##_AR_BYTES, \
142 }
143
144static struct kvm_vmx_segment_field {
145 unsigned selector;
146 unsigned base;
147 unsigned limit;
148 unsigned ar_bytes;
149} kvm_vmx_segment_fields[] = {
150 VMX_SEGMENT_FIELD(CS),
151 VMX_SEGMENT_FIELD(DS),
152 VMX_SEGMENT_FIELD(ES),
153 VMX_SEGMENT_FIELD(FS),
154 VMX_SEGMENT_FIELD(GS),
155 VMX_SEGMENT_FIELD(SS),
156 VMX_SEGMENT_FIELD(TR),
157 VMX_SEGMENT_FIELD(LDTR),
158};
159
4d56c8a7
AK		 160/*
161 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
162 * away by decrementing the array size.
163 */
6aa8b732 164static const u32 vmx_msr_index[] = {
05b3e0c2 165#ifdef CONFIG_X86_64
6aa8b732
AK		 166 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
167#endif
168 MSR_EFER, MSR_K6_STAR,
169};
9d8f549d 170#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 171
a2fa3e9f
GH		 172static void load_msrs(struct kvm_msr_entry *e, int n)
173{
174 int i;
175
176 for (i = 0; i < n; ++i)
177 wrmsrl(e[i].index, e[i].data);
178}
179
180static void save_msrs(struct kvm_msr_entry *e, int n)
181{
182 int i;
183
184 for (i = 0; i < n; ++i)
185 rdmsrl(e[i].index, e[i].data);
186}
187
6aa8b732
AK		 188static inline int is_page_fault(u32 intr_info)
189{
190 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
191 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 192 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 193}
194
2ab455cc
AL		 195static inline int is_no_device(u32 intr_info)
196{
197 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
198 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 199 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 200}
201
7aa81cc0
AL		 202static inline int is_invalid_opcode(u32 intr_info)
203{
204 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
205 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 206 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 207}
208
6aa8b732
AK		 209static inline int is_external_interrupt(u32 intr_info)
210{
211 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
212 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
213}
214
25c5f225
SY		 215static inline int cpu_has_vmx_msr_bitmap(void)
216{
217 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
218}
219
6e5d865c
YS		 220static inline int cpu_has_vmx_tpr_shadow(void)
221{
222 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
223}
224
225static inline int vm_need_tpr_shadow(struct kvm *kvm)
226{
227 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
228}
229
f78e0e2e
SY		 230static inline int cpu_has_secondary_exec_ctrls(void)
231{
232 return (vmcs_config.cpu_based_exec_ctrl &
233 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
234}
235
774ead3a 236static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 237{
4c9fc8ef
AK		 238 return flexpriority_enabled
239 && (vmcs_config.cpu_based_2nd_exec_ctrl &
240 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
f78e0e2e
SY		 241}
242
d56f546d
SY		 243static inline int cpu_has_vmx_invept_individual_addr(void)
244{
245 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
246}
247
248static inline int cpu_has_vmx_invept_context(void)
249{
250 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
251}
252
253static inline int cpu_has_vmx_invept_global(void)
254{
255 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
256}
257
258static inline int cpu_has_vmx_ept(void)
259{
260 return (vmcs_config.cpu_based_2nd_exec_ctrl &
261 SECONDARY_EXEC_ENABLE_EPT);
262}
263
264static inline int vm_need_ept(void)
265{
266 return (cpu_has_vmx_ept() && enable_ept);
267}
268
f78e0e2e
SY		 269static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
270{
271 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
272 (irqchip_in_kernel(kvm)));
273}
274
2384d2b3
SY		 275static inline int cpu_has_vmx_vpid(void)
276{
277 return (vmcs_config.cpu_based_2nd_exec_ctrl &
278 SECONDARY_EXEC_ENABLE_VPID);
279}
280
f08864b4
SY		 281static inline int cpu_has_virtual_nmis(void)
282{
283 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
284}
285
8b9cf98c 286static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 287{
288 int i;
289
a2fa3e9f
GH		 290 for (i = 0; i < vmx->nmsrs; ++i)
291 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 292 return i;
293 return -1;
294}
295
2384d2b3
SY		 296static inline void __invvpid(int ext, u16 vpid, gva_t gva)
297{
298 struct {
299 u64 vpid : 16;
300 u64 rsvd : 48;
301 u64 gva;
302 } operand = { vpid, 0, gva };
303
4ecac3fd 304 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 305 /* CF==1 or ZF==1 --> rc = -1 */
306 "; ja 1f ; ud2 ; 1:"
307 : : "a"(&operand), "c"(ext) : "cc", "memory");
308}
309
1439442c
SY		 310static inline void __invept(int ext, u64 eptp, gpa_t gpa)
311{
312 struct {
313 u64 eptp, gpa;
314 } operand = {eptp, gpa};
315
4ecac3fd 316 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 317 /* CF==1 or ZF==1 --> rc = -1 */
318 "; ja 1f ; ud2 ; 1:\n"
319 : : "a" (&operand), "c" (ext) : "cc", "memory");
320}
321
8b9cf98c 322static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 323{
324 int i;
325
8b9cf98c 326 i = __find_msr_index(vmx, msr);
a75beee6 327 if (i >= 0)
a2fa3e9f 328 return &vmx->guest_msrs[i];
8b6d44c7 329 return NULL;
7725f0ba
AK		 330}
331
6aa8b732
AK		 332static void vmcs_clear(struct vmcs *vmcs)
333{
334 u64 phys_addr = __pa(vmcs);
335 u8 error;
336
4ecac3fd 337 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 338 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
339 : "cc", "memory");
340 if (error)
341 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
342 vmcs, phys_addr);
343}
344
345static void __vcpu_clear(void *arg)
346{
8b9cf98c 347 struct vcpu_vmx *vmx = arg;
d3b2c338 348 int cpu = raw_smp_processor_id();
6aa8b732 349
8b9cf98c 350 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 351 vmcs_clear(vmx->vmcs);
352 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 353 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 354 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 355 list_del(&vmx->local_vcpus_link);
356 vmx->vcpu.cpu = -1;
357 vmx->launched = 0;
6aa8b732
AK		 358}
359
8b9cf98c 360static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 361{
eae5ecb5
AK		 362 if (vmx->vcpu.cpu == -1)
363 return;
8691e5a8 364 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 365}
366
2384d2b3
SY		 367static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
368{
369 if (vmx->vpid == 0)
370 return;
371
372 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
373}
374
1439442c
SY		 375static inline void ept_sync_global(void)
376{
377 if (cpu_has_vmx_invept_global())
378 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
379}
380
381static inline void ept_sync_context(u64 eptp)
382{
383 if (vm_need_ept()) {
384 if (cpu_has_vmx_invept_context())
385 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
386 else
387 ept_sync_global();
388 }
389}
390
391static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
392{
393 if (vm_need_ept()) {
394 if (cpu_has_vmx_invept_individual_addr())
395 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
396 eptp, gpa);
397 else
398 ept_sync_context(eptp);
399 }
400}
401
6aa8b732
AK		 402static unsigned long vmcs_readl(unsigned long field)
403{
404 unsigned long value;
405
4ecac3fd 406 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 407 : "=a"(value) : "d"(field) : "cc");
408 return value;
409}
410
411static u16 vmcs_read16(unsigned long field)
412{
413 return vmcs_readl(field);
414}
415
416static u32 vmcs_read32(unsigned long field)
417{
418 return vmcs_readl(field);
419}
420
421static u64 vmcs_read64(unsigned long field)
422{
05b3e0c2 423#ifdef CONFIG_X86_64
6aa8b732
AK		 424 return vmcs_readl(field);
425#else
426 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
427#endif
428}
429
e52de1b8
AK		 430static noinline void vmwrite_error(unsigned long field, unsigned long value)
431{
432 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
433 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
434 dump_stack();
435}
436
6aa8b732
AK		 437static void vmcs_writel(unsigned long field, unsigned long value)
438{
439 u8 error;
440
4ecac3fd 441 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 442 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 443 if (unlikely(error))
444 vmwrite_error(field, value);
6aa8b732
AK		 445}
446
447static void vmcs_write16(unsigned long field, u16 value)
448{
449 vmcs_writel(field, value);
450}
451
452static void vmcs_write32(unsigned long field, u32 value)
453{
454 vmcs_writel(field, value);
455}
456
457static void vmcs_write64(unsigned long field, u64 value)
458{
6aa8b732 459 vmcs_writel(field, value);
7682f2d0 460#ifndef CONFIG_X86_64
6aa8b732
AK		 461 asm volatile ("");
462 vmcs_writel(field+1, value >> 32);
463#endif
464}
465
2ab455cc
AL		 466static void vmcs_clear_bits(unsigned long field, u32 mask)
467{
468 vmcs_writel(field, vmcs_readl(field) & ~mask);
469}
470
471static void vmcs_set_bits(unsigned long field, u32 mask)
472{
473 vmcs_writel(field, vmcs_readl(field) | mask);
474}
475
abd3f2d6
AK		 476static void update_exception_bitmap(struct kvm_vcpu *vcpu)
477{
478 u32 eb;
479
7aa81cc0 480 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 481 if (!vcpu->fpu_active)
482 eb |= 1u << NM_VECTOR;
d0bfb940
JK		 483 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
484 if (vcpu->guest_debug &
485 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
486 eb |= 1u << DB_VECTOR;
487 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
488 eb |= 1u << BP_VECTOR;
489 }
ad312c7c 490 if (vcpu->arch.rmode.active)
abd3f2d6 491 eb = ~0;
1439442c
SY		 492 if (vm_need_ept())
493 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 494 vmcs_write32(EXCEPTION_BITMAP, eb);
495}
496
33ed6329
AK		 497static void reload_tss(void)
498{
33ed6329
AK		 499 /*
500 * VT restores TR but not its size. Useless.
501 */
502 struct descriptor_table gdt;
a5f61300 503 struct desc_struct *descs;
33ed6329 504
d6e88aec 505 kvm_get_gdt(&gdt);
33ed6329
AK		 506 descs = (void *)gdt.base;
507 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
508 load_TR_desc();
33ed6329
AK		 509}
510
8b9cf98c 511static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 512{
a2fa3e9f 513 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 514 u64 host_efer = vmx->host_msrs[efer_offset].data;
515 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
516 u64 ignore_bits;
517
518 if (efer_offset < 0)
519 return;
520 /*
521 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
522 * outside long mode
523 */
524 ignore_bits = EFER_NX | EFER_SCE;
525#ifdef CONFIG_X86_64
526 ignore_bits |= EFER_LMA | EFER_LME;
527 /* SCE is meaningful only in long mode on Intel */
528 if (guest_efer & EFER_LMA)
529 ignore_bits &= ~(u64)EFER_SCE;
530#endif
531 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
532 return;
2cc51560 533
51c6cf66
AK		 534 vmx->host_state.guest_efer_loaded = 1;
535 guest_efer &= ~ignore_bits;
536 guest_efer |= host_efer & ignore_bits;
537 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 538 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 539}
540
51c6cf66
AK		 541static void reload_host_efer(struct vcpu_vmx *vmx)
542{
543 if (vmx->host_state.guest_efer_loaded) {
544 vmx->host_state.guest_efer_loaded = 0;
545 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
546 }
547}
548
04d2cc77 549static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 550{
04d2cc77
AK		 551 struct vcpu_vmx *vmx = to_vmx(vcpu);
552
a2fa3e9f 553 if (vmx->host_state.loaded)
33ed6329
AK		 554 return;
555
a2fa3e9f 556 vmx->host_state.loaded = 1;
33ed6329
AK		 557 /*
558 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
559 * allow segment selectors with cpl > 0 or ti == 1.
560 */
d6e88aec 561 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 562 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 563 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 564 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 565 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 566 vmx->host_state.fs_reload_needed = 0;
567 } else {
33ed6329 568 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 569 vmx->host_state.fs_reload_needed = 1;
33ed6329 570 }
d6e88aec 571 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 572 if (!(vmx->host_state.gs_sel & 7))
573 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 574 else {
575 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 576 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 577 }
578
579#ifdef CONFIG_X86_64
580 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
581 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
582#else
a2fa3e9f
GH		 583 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
584 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 585#endif
707c0874
AK		 586
587#ifdef CONFIG_X86_64
d77c26fc 588 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 589 save_msrs(vmx->host_msrs +
590 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 591
707c0874 592#endif
a2fa3e9f 593 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 594 load_transition_efer(vmx);
33ed6329
AK		 595}
596
a9b21b62 597static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 598{
15ad7146 599 unsigned long flags;
33ed6329 600
a2fa3e9f 601 if (!vmx->host_state.loaded)
33ed6329
AK		 602 return;
603
e1beb1d3 604 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 605 vmx->host_state.loaded = 0;
152d3f2f 606 if (vmx->host_state.fs_reload_needed)
d6e88aec 607 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 608 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 609 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 610 /*
611 * If we have to reload gs, we must take care to
612 * preserve our gs base.
613 */
15ad7146 614 local_irq_save(flags);
d6e88aec 615 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 616#ifdef CONFIG_X86_64
617 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
618#endif
15ad7146 619 local_irq_restore(flags);
33ed6329 620 }
152d3f2f 621 reload_tss();
a2fa3e9f
GH		 622 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
623 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 624 reload_host_efer(vmx);
33ed6329
AK		 625}
626
a9b21b62
AK		 627static void vmx_load_host_state(struct vcpu_vmx *vmx)
628{
629 preempt_disable();
630 __vmx_load_host_state(vmx);
631 preempt_enable();
632}
633
6aa8b732
AK		 634/*
635 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
636 * vcpu mutex is already taken.
637 */
15ad7146 638static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 639{
a2fa3e9f
GH		 640 struct vcpu_vmx *vmx = to_vmx(vcpu);
641 u64 phys_addr = __pa(vmx->vmcs);
019960ae 642 u64 tsc_this, delta, new_offset;
6aa8b732 643
a3d7f85f 644 if (vcpu->cpu != cpu) {
8b9cf98c 645 vcpu_clear(vmx);
2f599714 646 kvm_migrate_timers(vcpu);
2384d2b3 647 vpid_sync_vcpu_all(vmx);
543e4243
AK		 648 local_irq_disable();
649 list_add(&vmx->local_vcpus_link,
650 &per_cpu(vcpus_on_cpu, cpu));
651 local_irq_enable();
a3d7f85f 652 }
6aa8b732 653
a2fa3e9f 654 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 655 u8 error;
656
a2fa3e9f 657 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 658 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 659 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
660 : "cc");
661 if (error)
662 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 663 vmx->vmcs, phys_addr);
6aa8b732
AK		 664 }
665
666 if (vcpu->cpu != cpu) {
667 struct descriptor_table dt;
668 unsigned long sysenter_esp;
669
670 vcpu->cpu = cpu;
671 /*
672 * Linux uses per-cpu TSS and GDT, so set these when switching
673 * processors.
674 */
d6e88aec
AK		 675 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
676 kvm_get_gdt(&dt);
6aa8b732
AK		 677 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
678
679 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
680 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 681
682 /*
683 * Make sure the time stamp counter is monotonous.
684 */
685 rdtscll(tsc_this);
019960ae
AK		 686 if (tsc_this < vcpu->arch.host_tsc) {
687 delta = vcpu->arch.host_tsc - tsc_this;
688 new_offset = vmcs_read64(TSC_OFFSET) + delta;
689 vmcs_write64(TSC_OFFSET, new_offset);
690 }
6aa8b732 691 }
6aa8b732
AK		 692}
693
694static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
695{
a9b21b62 696 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 697}
698
5fd86fcf
AK		 699static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
700{
701 if (vcpu->fpu_active)
702 return;
703 vcpu->fpu_active = 1;
707d92fa 704 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 705 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 706 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 707 update_exception_bitmap(vcpu);
708}
709
710static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
711{
712 if (!vcpu->fpu_active)
713 return;
714 vcpu->fpu_active = 0;
707d92fa 715 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 716 update_exception_bitmap(vcpu);
717}
718
6aa8b732
AK		 719static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
720{
721 return vmcs_readl(GUEST_RFLAGS);
722}
723
724static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
725{
ad312c7c 726 if (vcpu->arch.rmode.active)
053de044 727 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 728 vmcs_writel(GUEST_RFLAGS, rflags);
729}
730
731static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
732{
733 unsigned long rip;
734 u32 interruptibility;
735
5fdbf976 736 rip = kvm_rip_read(vcpu);
6aa8b732 737 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 738 kvm_rip_write(vcpu, rip);
6aa8b732
AK		 739
740 /*
741 * We emulated an instruction, so temporary interrupt blocking
742 * should be removed, if set.
743 */
744 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
745 if (interruptibility & 3)
746 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
747 interruptibility & ~3);
ad312c7c 748 vcpu->arch.interrupt_window_open = 1;
6aa8b732
AK		 749}
750
298101da
AK		 751static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
752 bool has_error_code, u32 error_code)
753{
77ab6db0 754 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 755 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 756
8ab2d2e2 757 if (has_error_code) {
77ab6db0 758 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 759 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
760 }
77ab6db0
JK		 761
762 if (vcpu->arch.rmode.active) {
763 vmx->rmode.irq.pending = true;
764 vmx->rmode.irq.vector = nr;
765 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
8ab2d2e2 766 if (nr == BP_VECTOR || nr == OF_VECTOR)
77ab6db0 767 vmx->rmode.irq.rip++;
8ab2d2e2
JK		 768 intr_info |= INTR_TYPE_SOFT_INTR;
769 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 770 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
771 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
772 return;
773 }
774
8ab2d2e2
JK		 775 if (nr == BP_VECTOR || nr == OF_VECTOR) {
776 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
777 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
778 } else
779 intr_info |= INTR_TYPE_HARD_EXCEPTION;
780
781 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 782}
783
784static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
785{
35920a35 786 return false;
298101da
AK		 787}
788
a75beee6
ED		 789/*
790 * Swap MSR entry in host/guest MSR entry array.
791 */
54e11fa1 792#ifdef CONFIG_X86_64
8b9cf98c 793static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 794{
a2fa3e9f
GH		 795 struct kvm_msr_entry tmp;
796
797 tmp = vmx->guest_msrs[to];
798 vmx->guest_msrs[to] = vmx->guest_msrs[from];
799 vmx->guest_msrs[from] = tmp;
800 tmp = vmx->host_msrs[to];
801 vmx->host_msrs[to] = vmx->host_msrs[from];
802 vmx->host_msrs[from] = tmp;
a75beee6 803}
54e11fa1 804#endif
a75beee6 805
e38aea3e
AK		 806/*
807 * Set up the vmcs to automatically save and restore system
808 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
809 * mode, as fiddling with msrs is very expensive.
810 */
8b9cf98c 811static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 812{
2cc51560 813 int save_nmsrs;
e38aea3e 814
33f9c505 815 vmx_load_host_state(vmx);
a75beee6
ED		 816 save_nmsrs = 0;
817#ifdef CONFIG_X86_64
8b9cf98c 818 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 819 int index;
820
8b9cf98c 821 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 822 if (index >= 0)
8b9cf98c
RR		 823 move_msr_up(vmx, index, save_nmsrs++);
824 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 825 if (index >= 0)
8b9cf98c
RR		 826 move_msr_up(vmx, index, save_nmsrs++);
827 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 828 if (index >= 0)
8b9cf98c
RR		 829 move_msr_up(vmx, index, save_nmsrs++);
830 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 831 if (index >= 0)
8b9cf98c 832 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 833 /*
834 * MSR_K6_STAR is only needed on long mode guests, and only
835 * if efer.sce is enabled.
836 */
8b9cf98c 837 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 838 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 839 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 840 }
841#endif
a2fa3e9f 842 vmx->save_nmsrs = save_nmsrs;
e38aea3e 843
4d56c8a7 844#ifdef CONFIG_X86_64
a2fa3e9f 845 vmx->msr_offset_kernel_gs_base =
8b9cf98c 846 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 847#endif
8b9cf98c 848 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 849}
850
6aa8b732
AK		 851/*
852 * reads and returns guest's timestamp counter "register"
853 * guest_tsc = host_tsc + tsc_offset -- 21.3
854 */
855static u64 guest_read_tsc(void)
856{
857 u64 host_tsc, tsc_offset;
858
859 rdtscll(host_tsc);
860 tsc_offset = vmcs_read64(TSC_OFFSET);
861 return host_tsc + tsc_offset;
862}
863
864/*
865 * writes 'guest_tsc' into guest's timestamp counter "register"
866 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
867 */
868static void guest_write_tsc(u64 guest_tsc)
869{
870 u64 host_tsc;
871
872 rdtscll(host_tsc);
873 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
874}
875
6aa8b732
AK		 876/*
877 * Reads an msr value (of 'msr_index') into 'pdata'.
878 * Returns 0 on success, non-0 otherwise.
879 * Assumes vcpu_load() was already called.
880 */
881static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
882{
883 u64 data;
a2fa3e9f 884 struct kvm_msr_entry *msr;
6aa8b732
AK		 885
886 if (!pdata) {
887 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
888 return -EINVAL;
889 }
890
891 switch (msr_index) {
05b3e0c2 892#ifdef CONFIG_X86_64
6aa8b732
AK		 893 case MSR_FS_BASE:
894 data = vmcs_readl(GUEST_FS_BASE);
895 break;
896 case MSR_GS_BASE:
897 data = vmcs_readl(GUEST_GS_BASE);
898 break;
899 case MSR_EFER:
3bab1f5d 900 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 901#endif
902 case MSR_IA32_TIME_STAMP_COUNTER:
903 data = guest_read_tsc();
904 break;
905 case MSR_IA32_SYSENTER_CS:
906 data = vmcs_read32(GUEST_SYSENTER_CS);
907 break;
908 case MSR_IA32_SYSENTER_EIP:
f5b42c33 909 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 910 break;
911 case MSR_IA32_SYSENTER_ESP:
f5b42c33 912 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 913 break;
6aa8b732 914 default:
516a1a7e 915 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 916 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 917 if (msr) {
918 data = msr->data;
919 break;
6aa8b732 920 }
3bab1f5d 921 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 922 }
923
924 *pdata = data;
925 return 0;
926}
927
928/*
929 * Writes msr value into into the appropriate "register".
930 * Returns 0 on success, non-0 otherwise.
931 * Assumes vcpu_load() was already called.
932 */
933static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
934{
a2fa3e9f
GH		 935 struct vcpu_vmx *vmx = to_vmx(vcpu);
936 struct kvm_msr_entry *msr;
2cc51560
ED		 937 int ret = 0;
938
6aa8b732 939 switch (msr_index) {
05b3e0c2 940#ifdef CONFIG_X86_64
3bab1f5d 941 case MSR_EFER:
a9b21b62 942 vmx_load_host_state(vmx);
2cc51560 943 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 944 break;
6aa8b732
AK		 945 case MSR_FS_BASE:
946 vmcs_writel(GUEST_FS_BASE, data);
947 break;
948 case MSR_GS_BASE:
949 vmcs_writel(GUEST_GS_BASE, data);
950 break;
951#endif
952 case MSR_IA32_SYSENTER_CS:
953 vmcs_write32(GUEST_SYSENTER_CS, data);
954 break;
955 case MSR_IA32_SYSENTER_EIP:
f5b42c33 956 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 957 break;
958 case MSR_IA32_SYSENTER_ESP:
f5b42c33 959 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 960 break;
d27d4aca 961 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732 962 guest_write_tsc(data);
efa67e0d
CL		 963 break;
964 case MSR_P6_PERFCTR0:
965 case MSR_P6_PERFCTR1:
966 case MSR_P6_EVNTSEL0:
967 case MSR_P6_EVNTSEL1:
968 /*
969 * Just discard all writes to the performance counters; this
970 * should keep both older linux and windows 64-bit guests
971 * happy
972 */
973 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
974
6aa8b732 975 break;
468d472f
SY		 976 case MSR_IA32_CR_PAT:
977 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
978 vmcs_write64(GUEST_IA32_PAT, data);
979 vcpu->arch.pat = data;
980 break;
981 }
982 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 983 default:
a9b21b62 984 vmx_load_host_state(vmx);
8b9cf98c 985 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 986 if (msr) {
987 msr->data = data;
988 break;
6aa8b732 989 }
2cc51560 990 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 991 }
992
2cc51560 993 return ret;
6aa8b732
AK		 994}
995
5fdbf976 996static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 997{
5fdbf976
MT		 998 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
999 switch (reg) {
1000 case VCPU_REGS_RSP:
1001 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1002 break;
1003 case VCPU_REGS_RIP:
1004 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1005 break;
1006 default:
1007 break;
1008 }
6aa8b732
AK		 1009}
1010
d0bfb940 1011static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1012{
d0bfb940
JK		 1013 int old_debug = vcpu->guest_debug;
1014 unsigned long flags;
6aa8b732 1015
d0bfb940
JK		 1016 vcpu->guest_debug = dbg->control;
1017 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1018 vcpu->guest_debug = 0;
6aa8b732 1019
d0bfb940
JK		 1020 flags = vmcs_readl(GUEST_RFLAGS);
1021 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1022 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1023 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
6aa8b732 1024 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
d0bfb940 1025 vmcs_writel(GUEST_RFLAGS, flags);
6aa8b732 1026
abd3f2d6 1027 update_exception_bitmap(vcpu);
6aa8b732
AK		 1028
1029 return 0;
1030}
1031
2a8067f1
ED		 1032static int vmx_get_irq(struct kvm_vcpu *vcpu)
1033{
f7d9238f
AK		 1034 if (!vcpu->arch.interrupt.pending)
1035 return -1;
1036 return vcpu->arch.interrupt.nr;
2a8067f1
ED		 1037}
1038
6aa8b732
AK		 1039static __init int cpu_has_kvm_support(void)
1040{
6210e37b 1041 return cpu_has_vmx();
6aa8b732
AK		 1042}
1043
1044static __init int vmx_disabled_by_bios(void)
1045{
1046 u64 msr;
1047
1048 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1049 return (msr & (FEATURE_CONTROL_LOCKED |
1050 FEATURE_CONTROL_VMXON_ENABLED))
1051 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1052 /* locked but not enabled */
6aa8b732
AK		 1053}
1054
774c47f1 1055static void hardware_enable(void *garbage)
6aa8b732
AK		 1056{
1057 int cpu = raw_smp_processor_id();
1058 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1059 u64 old;
1060
543e4243 1061 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1062 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1063 if ((old & (FEATURE_CONTROL_LOCKED |
1064 FEATURE_CONTROL_VMXON_ENABLED))
1065 != (FEATURE_CONTROL_LOCKED |
1066 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1067 /* enable and lock */
62b3ffb8 1068 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1069 FEATURE_CONTROL_LOCKED |
1070 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1071 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1072 asm volatile (ASM_VMX_VMXON_RAX
1073 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1074 : "memory", "cc");
1075}
1076
543e4243
AK		 1077static void vmclear_local_vcpus(void)
1078{
1079 int cpu = raw_smp_processor_id();
1080 struct vcpu_vmx *vmx, *n;
1081
1082 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1083 local_vcpus_link)
1084 __vcpu_clear(vmx);
1085}
1086
710ff4a8
EH		 1087
1088/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1089 * tricks.
1090 */
1091static void kvm_cpu_vmxoff(void)
6aa8b732 1092{
4ecac3fd 1093 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1094 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1095}
1096
710ff4a8
EH		 1097static void hardware_disable(void *garbage)
1098{
1099 vmclear_local_vcpus();
1100 kvm_cpu_vmxoff();
1101}
1102
1c3d14fe 1103static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1104 u32 msr, u32 *result)
1c3d14fe
YS		 1105{
1106 u32 vmx_msr_low, vmx_msr_high;
1107 u32 ctl = ctl_min | ctl_opt;
1108
1109 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1110
1111 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1112 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1113
1114 /* Ensure minimum (required) set of control bits are supported. */
1115 if (ctl_min & ~ctl)
002c7f7c 1116 return -EIO;
1c3d14fe
YS		 1117
1118 *result = ctl;
1119 return 0;
1120}
1121
002c7f7c 1122static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1123{
1124 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1125 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1126 u32 _pin_based_exec_control = 0;
1127 u32 _cpu_based_exec_control = 0;
f78e0e2e 1128 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1129 u32 _vmexit_control = 0;
1130 u32 _vmentry_control = 0;
1131
1132 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1133 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1134 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1135 &_pin_based_exec_control) < 0)
002c7f7c 1136 return -EIO;
1c3d14fe
YS		 1137
1138 min = CPU_BASED_HLT_EXITING |
1139#ifdef CONFIG_X86_64
1140 CPU_BASED_CR8_LOAD_EXITING |
1141 CPU_BASED_CR8_STORE_EXITING |
1142#endif
d56f546d
SY		 1143 CPU_BASED_CR3_LOAD_EXITING |
1144 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1145 CPU_BASED_USE_IO_BITMAPS |
1146 CPU_BASED_MOV_DR_EXITING |
a7052897
MT		 1147 CPU_BASED_USE_TSC_OFFSETING |
1148 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1149 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1150 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1151 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1152 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1153 &_cpu_based_exec_control) < 0)
002c7f7c 1154 return -EIO;
6e5d865c
YS		 1155#ifdef CONFIG_X86_64
1156 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1157 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1158 ~CPU_BASED_CR8_STORE_EXITING;
1159#endif
f78e0e2e 1160 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1161 min2 = 0;
1162 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1163 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d
SY		 1164 SECONDARY_EXEC_ENABLE_VPID |
1165 SECONDARY_EXEC_ENABLE_EPT;
1166 if (adjust_vmx_controls(min2, opt2,
1167 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1168 &_cpu_based_2nd_exec_control) < 0)
1169 return -EIO;
1170 }
1171#ifndef CONFIG_X86_64
1172 if (!(_cpu_based_2nd_exec_control &
1173 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1174 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1175#endif
d56f546d 1176 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1177 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1178 enabled */
d56f546d 1179 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
a7052897
MT		 1180 CPU_BASED_CR3_STORE_EXITING |
1181 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1182 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1183 &_cpu_based_exec_control) < 0)
1184 return -EIO;
1185 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1186 vmx_capability.ept, vmx_capability.vpid);
1187 }
1c3d14fe
YS		 1188
1189 min = 0;
1190#ifdef CONFIG_X86_64
1191 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1192#endif
468d472f 1193 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1194 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1195 &_vmexit_control) < 0)
002c7f7c 1196 return -EIO;
1c3d14fe 1197
468d472f
SY		 1198 min = 0;
1199 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1200 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1201 &_vmentry_control) < 0)
002c7f7c 1202 return -EIO;
6aa8b732 1203
c68876fd 1204 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1205
1206 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1207 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1208 return -EIO;
1c3d14fe
YS		 1209
1210#ifdef CONFIG_X86_64
1211 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1212 if (vmx_msr_high & (1u<<16))
002c7f7c 1213 return -EIO;
1c3d14fe
YS		 1214#endif
1215
1216 /* Require Write-Back (WB) memory type for VMCS accesses. */
1217 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1218 return -EIO;
1c3d14fe 1219
002c7f7c
YS		 1220 vmcs_conf->size = vmx_msr_high & 0x1fff;
1221 vmcs_conf->order = get_order(vmcs_config.size);
1222 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1223
002c7f7c
YS		 1224 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1225 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1226 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1227 vmcs_conf->vmexit_ctrl = _vmexit_control;
1228 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1229
1230 return 0;
c68876fd 1231}
6aa8b732
AK		 1232
1233static struct vmcs *alloc_vmcs_cpu(int cpu)
1234{
1235 int node = cpu_to_node(cpu);
1236 struct page *pages;
1237 struct vmcs *vmcs;
1238
1c3d14fe 1239 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1240 if (!pages)
1241 return NULL;
1242 vmcs = page_address(pages);
1c3d14fe
YS		 1243 memset(vmcs, 0, vmcs_config.size);
1244 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1245 return vmcs;
1246}
1247
1248static struct vmcs *alloc_vmcs(void)
1249{
d3b2c338 1250 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1251}
1252
1253static void free_vmcs(struct vmcs *vmcs)
1254{
1c3d14fe 1255 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1256}
1257
39959588 1258static void free_kvm_area(void)
6aa8b732
AK		 1259{
1260 int cpu;
1261
1262 for_each_online_cpu(cpu)
1263 free_vmcs(per_cpu(vmxarea, cpu));
1264}
1265
6aa8b732
AK		 1266static __init int alloc_kvm_area(void)
1267{
1268 int cpu;
1269
1270 for_each_online_cpu(cpu) {
1271 struct vmcs *vmcs;
1272
1273 vmcs = alloc_vmcs_cpu(cpu);
1274 if (!vmcs) {
1275 free_kvm_area();
1276 return -ENOMEM;
1277 }
1278
1279 per_cpu(vmxarea, cpu) = vmcs;
1280 }
1281 return 0;
1282}
1283
1284static __init int hardware_setup(void)
1285{
002c7f7c
YS		 1286 if (setup_vmcs_config(&vmcs_config) < 0)
1287 return -EIO;
50a37eb4
JR		 1288
1289 if (boot_cpu_has(X86_FEATURE_NX))
1290 kvm_enable_efer_bits(EFER_NX);
1291
6aa8b732
AK		 1292 return alloc_kvm_area();
1293}
1294
1295static __exit void hardware_unsetup(void)
1296{
1297 free_kvm_area();
1298}
1299
6aa8b732
AK		 1300static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1301{
1302 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1303
6af11b9e 1304 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1305 vmcs_write16(sf->selector, save->selector);
1306 vmcs_writel(sf->base, save->base);
1307 vmcs_write32(sf->limit, save->limit);
1308 vmcs_write32(sf->ar_bytes, save->ar);
1309 } else {
1310 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1311 << AR_DPL_SHIFT;
1312 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1313 }
1314}
1315
1316static void enter_pmode(struct kvm_vcpu *vcpu)
1317{
1318 unsigned long flags;
a89a8fb9 1319 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1320
a89a8fb9 1321 vmx->emulation_required = 1;
ad312c7c 1322 vcpu->arch.rmode.active = 0;
6aa8b732 1323
ad312c7c
ZX		 1324 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1325 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1326 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
6aa8b732
AK		 1327
1328 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1329 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
ad312c7c 1330 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1331 vmcs_writel(GUEST_RFLAGS, flags);
1332
66aee91a
RR		 1333 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1334 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1335
1336 update_exception_bitmap(vcpu);
1337
a89a8fb9
MG		 1338 if (emulate_invalid_guest_state)
1339 return;
1340
ad312c7c
ZX		 1341 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1342 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1343 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1344 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
6aa8b732
AK		 1345
1346 vmcs_write16(GUEST_SS_SELECTOR, 0);
1347 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1348
1349 vmcs_write16(GUEST_CS_SELECTOR,
1350 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1351 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1352}
1353
d77c26fc 1354static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1355{
bfc6d222 1356 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1357 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1358 kvm->memslots[0].npages - 3;
1359 return base_gfn << PAGE_SHIFT;
1360 }
bfc6d222 1361 return kvm->arch.tss_addr;
6aa8b732
AK		 1362}
1363
1364static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1365{
1366 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1367
1368 save->selector = vmcs_read16(sf->selector);
1369 save->base = vmcs_readl(sf->base);
1370 save->limit = vmcs_read32(sf->limit);
1371 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1372 vmcs_write16(sf->selector, save->base >> 4);
1373 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1374 vmcs_write32(sf->limit, 0xffff);
1375 vmcs_write32(sf->ar_bytes, 0xf3);
1376}
1377
1378static void enter_rmode(struct kvm_vcpu *vcpu)
1379{
1380 unsigned long flags;
a89a8fb9 1381 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1382
a89a8fb9 1383 vmx->emulation_required = 1;
ad312c7c 1384 vcpu->arch.rmode.active = 1;
6aa8b732 1385
ad312c7c 1386 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1387 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1388
ad312c7c 1389 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1390 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1391
ad312c7c 1392 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1393 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1394
1395 flags = vmcs_readl(GUEST_RFLAGS);
ad312c7c
ZX		 1396 vcpu->arch.rmode.save_iopl
1397 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1398
053de044 1399 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1400
1401 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1402 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1403 update_exception_bitmap(vcpu);
1404
a89a8fb9
MG		 1405 if (emulate_invalid_guest_state)
1406 goto continue_rmode;
1407
6aa8b732
AK		 1408 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1409 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1410 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1411
1412 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1413 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1414 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1415 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1416 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1417
ad312c7c
ZX		 1418 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1419 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1420 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1421 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
75880a01 1422
a89a8fb9 1423continue_rmode:
8668a3c4 1424 kvm_mmu_reset_context(vcpu);
b7ebfb05 1425 init_rmode(vcpu->kvm);
6aa8b732
AK		 1426}
1427
05b3e0c2 1428#ifdef CONFIG_X86_64
6aa8b732
AK		 1429
1430static void enter_lmode(struct kvm_vcpu *vcpu)
1431{
1432 u32 guest_tr_ar;
1433
1434 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1435 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1436 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1437 __func__);
6aa8b732
AK		 1438 vmcs_write32(GUEST_TR_AR_BYTES,
1439 (guest_tr_ar & ~AR_TYPE_MASK)
1440 | AR_TYPE_BUSY_64_TSS);
1441 }
1442
ad312c7c 1443 vcpu->arch.shadow_efer |= EFER_LMA;
6aa8b732 1444
8b9cf98c 1445 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1446 vmcs_write32(VM_ENTRY_CONTROLS,
1447 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1448 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1449}
1450
1451static void exit_lmode(struct kvm_vcpu *vcpu)
1452{
ad312c7c 1453 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1454
1455 vmcs_write32(VM_ENTRY_CONTROLS,
1456 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1457 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1458}
1459
1460#endif
1461
2384d2b3
SY		 1462static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1463{
1464 vpid_sync_vcpu_all(to_vmx(vcpu));
4e1096d2
SY		 1465 if (vm_need_ept())
1466 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1467}
1468
25c4c276 1469static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1470{
ad312c7c
ZX		 1471 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1472 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1473}
1474
1439442c
SY		 1475static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1476{
1477 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1478 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1479 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1480 return;
1481 }
1482 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1483 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1484 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1485 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1486 }
1487}
1488
1489static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1490
1491static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1492 unsigned long cr0,
1493 struct kvm_vcpu *vcpu)
1494{
1495 if (!(cr0 & X86_CR0_PG)) {
1496 /* From paging/starting to nonpaging */
1497 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1498 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1499 (CPU_BASED_CR3_LOAD_EXITING |
1500 CPU_BASED_CR3_STORE_EXITING));
1501 vcpu->arch.cr0 = cr0;
1502 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1503 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1504 *hw_cr0 &= ~X86_CR0_WP;
1505 } else if (!is_paging(vcpu)) {
1506 /* From nonpaging to paging */
1507 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1508 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1509 ~(CPU_BASED_CR3_LOAD_EXITING |
1510 CPU_BASED_CR3_STORE_EXITING));
1511 vcpu->arch.cr0 = cr0;
1512 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1513 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1514 *hw_cr0 &= ~X86_CR0_WP;
1515 }
1516}
1517
1518static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1519 struct kvm_vcpu *vcpu)
1520{
1521 if (!is_paging(vcpu)) {
1522 *hw_cr4 &= ~X86_CR4_PAE;
1523 *hw_cr4 |= X86_CR4_PSE;
1524 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1525 *hw_cr4 &= ~X86_CR4_PAE;
1526}
1527
6aa8b732
AK		 1528static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1529{
1439442c
SY		 1530 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1531 KVM_VM_CR0_ALWAYS_ON;
1532
5fd86fcf
AK		 1533 vmx_fpu_deactivate(vcpu);
1534
ad312c7c 1535 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1536 enter_pmode(vcpu);
1537
ad312c7c 1538 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1539 enter_rmode(vcpu);
1540
05b3e0c2 1541#ifdef CONFIG_X86_64
ad312c7c 1542 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1543 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1544 enter_lmode(vcpu);
707d92fa 1545 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1546 exit_lmode(vcpu);
1547 }
1548#endif
1549
1439442c
SY		 1550 if (vm_need_ept())
1551 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1552
6aa8b732 1553 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1554 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1555 vcpu->arch.cr0 = cr0;
5fd86fcf 1556
707d92fa 1557 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1558 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1559}
1560
1439442c
SY		 1561static u64 construct_eptp(unsigned long root_hpa)
1562{
1563 u64 eptp;
1564
1565 /* TODO write the value reading from MSR */
1566 eptp = VMX_EPT_DEFAULT_MT |
1567 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1568 eptp |= (root_hpa & PAGE_MASK);
1569
1570 return eptp;
1571}
1572
6aa8b732
AK		 1573static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1574{
1439442c
SY		 1575 unsigned long guest_cr3;
1576 u64 eptp;
1577
1578 guest_cr3 = cr3;
1579 if (vm_need_ept()) {
1580 eptp = construct_eptp(cr3);
1581 vmcs_write64(EPT_POINTER, eptp);
1582 ept_sync_context(eptp);
1583 ept_load_pdptrs(vcpu);
1584 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1585 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1586 }
1587
2384d2b3 1588 vmx_flush_tlb(vcpu);
1439442c 1589 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1590 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1591 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1592}
1593
1594static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1595{
1439442c
SY		 1596 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1597 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1598
ad312c7c 1599 vcpu->arch.cr4 = cr4;
1439442c
SY		 1600 if (vm_need_ept())
1601 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1602
1603 vmcs_writel(CR4_READ_SHADOW, cr4);
1604 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1605}
1606
6aa8b732
AK		 1607static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1608{
8b9cf98c
RR		 1609 struct vcpu_vmx *vmx = to_vmx(vcpu);
1610 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732 1611
ad312c7c 1612 vcpu->arch.shadow_efer = efer;
9f62e19a
JR		 1613 if (!msr)
1614 return;
6aa8b732
AK		 1615 if (efer & EFER_LMA) {
1616 vmcs_write32(VM_ENTRY_CONTROLS,
1617 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1618 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1619 msr->data = efer;
1620
1621 } else {
1622 vmcs_write32(VM_ENTRY_CONTROLS,
1623 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1624 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1625
1626 msr->data = efer & ~EFER_LME;
1627 }
8b9cf98c 1628 setup_msrs(vmx);
6aa8b732
AK		 1629}
1630
6aa8b732
AK		 1631static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1632{
1633 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1634
1635 return vmcs_readl(sf->base);
1636}
1637
1638static void vmx_get_segment(struct kvm_vcpu *vcpu,
1639 struct kvm_segment *var, int seg)
1640{
1641 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1642 u32 ar;
1643
1644 var->base = vmcs_readl(sf->base);
1645 var->limit = vmcs_read32(sf->limit);
1646 var->selector = vmcs_read16(sf->selector);
1647 ar = vmcs_read32(sf->ar_bytes);
1648 if (ar & AR_UNUSABLE_MASK)
1649 ar = 0;
1650 var->type = ar & 15;
1651 var->s = (ar >> 4) & 1;
1652 var->dpl = (ar >> 5) & 3;
1653 var->present = (ar >> 7) & 1;
1654 var->avl = (ar >> 12) & 1;
1655 var->l = (ar >> 13) & 1;
1656 var->db = (ar >> 14) & 1;
1657 var->g = (ar >> 15) & 1;
1658 var->unusable = (ar >> 16) & 1;
1659}
1660
2e4d2653
IE		 1661static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1662{
1663 struct kvm_segment kvm_seg;
1664
1665 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1666 return 0;
1667
1668 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1669 return 3;
1670
1671 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1672 return kvm_seg.selector & 3;
1673}
1674
653e3108 1675static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1676{
6aa8b732
AK		 1677 u32 ar;
1678
653e3108 1679 if (var->unusable)
6aa8b732
AK		 1680 ar = 1 << 16;
1681 else {
1682 ar = var->type & 15;
1683 ar |= (var->s & 1) << 4;
1684 ar |= (var->dpl & 3) << 5;
1685 ar |= (var->present & 1) << 7;
1686 ar |= (var->avl & 1) << 12;
1687 ar |= (var->l & 1) << 13;
1688 ar |= (var->db & 1) << 14;
1689 ar |= (var->g & 1) << 15;
1690 }
f7fbf1fd
UL		 1691 if (ar == 0) /* a 0 value means unusable */
1692 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1693
1694 return ar;
1695}
1696
1697static void vmx_set_segment(struct kvm_vcpu *vcpu,
1698 struct kvm_segment *var, int seg)
1699{
1700 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1701 u32 ar;
1702
ad312c7c
ZX		 1703 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1704 vcpu->arch.rmode.tr.selector = var->selector;
1705 vcpu->arch.rmode.tr.base = var->base;
1706 vcpu->arch.rmode.tr.limit = var->limit;
1707 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1708 return;
1709 }
1710 vmcs_writel(sf->base, var->base);
1711 vmcs_write32(sf->limit, var->limit);
1712 vmcs_write16(sf->selector, var->selector);
ad312c7c 1713 if (vcpu->arch.rmode.active && var->s) {
653e3108
AK		 1714 /*
1715 * Hack real-mode segments into vm86 compatibility.
1716 */
1717 if (var->base == 0xffff0000 && var->selector == 0xf000)
1718 vmcs_writel(sf->base, 0xf0000);
1719 ar = 0xf3;
1720 } else
1721 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1722 vmcs_write32(sf->ar_bytes, ar);
1723}
1724
6aa8b732
AK		 1725static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1726{
1727 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1728
1729 *db = (ar >> 14) & 1;
1730 *l = (ar >> 13) & 1;
1731}
1732
1733static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1734{
1735 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1736 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1737}
1738
1739static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1740{
1741 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1742 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1743}
1744
1745static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1746{
1747 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1748 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1749}
1750
1751static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1752{
1753 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1754 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1755}
1756
648dfaa7
MG		 1757static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1758{
1759 struct kvm_segment var;
1760 u32 ar;
1761
1762 vmx_get_segment(vcpu, &var, seg);
1763 ar = vmx_segment_access_rights(&var);
1764
1765 if (var.base != (var.selector << 4))
1766 return false;
1767 if (var.limit != 0xffff)
1768 return false;
1769 if (ar != 0xf3)
1770 return false;
1771
1772 return true;
1773}
1774
1775static bool code_segment_valid(struct kvm_vcpu *vcpu)
1776{
1777 struct kvm_segment cs;
1778 unsigned int cs_rpl;
1779
1780 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1781 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1782
1783 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1784 return false;
1785 if (!cs.s)
1786 return false;
1787 if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) {
1788 if (cs.dpl > cs_rpl)
1789 return false;
1790 } else if (cs.type & AR_TYPE_CODE_MASK) {
1791 if (cs.dpl != cs_rpl)
1792 return false;
1793 }
1794 if (!cs.present)
1795 return false;
1796
1797 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1798 return true;
1799}
1800
1801static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1802{
1803 struct kvm_segment ss;
1804 unsigned int ss_rpl;
1805
1806 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1807 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1808
1809 if ((ss.type != 3) || (ss.type != 7))
1810 return false;
1811 if (!ss.s)
1812 return false;
1813 if (ss.dpl != ss_rpl) /* DPL != RPL */
1814 return false;
1815 if (!ss.present)
1816 return false;
1817
1818 return true;
1819}
1820
1821static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1822{
1823 struct kvm_segment var;
1824 unsigned int rpl;
1825
1826 vmx_get_segment(vcpu, &var, seg);
1827 rpl = var.selector & SELECTOR_RPL_MASK;
1828
1829 if (!var.s)
1830 return false;
1831 if (!var.present)
1832 return false;
1833 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1834 if (var.dpl < rpl) /* DPL < RPL */
1835 return false;
1836 }
1837
1838 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1839 * rights flags
1840 */
1841 return true;
1842}
1843
1844static bool tr_valid(struct kvm_vcpu *vcpu)
1845{
1846 struct kvm_segment tr;
1847
1848 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1849
1850 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1851 return false;
1852 if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */
1853 return false;
1854 if (!tr.present)
1855 return false;
1856
1857 return true;
1858}
1859
1860static bool ldtr_valid(struct kvm_vcpu *vcpu)
1861{
1862 struct kvm_segment ldtr;
1863
1864 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1865
1866 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1867 return false;
1868 if (ldtr.type != 2)
1869 return false;
1870 if (!ldtr.present)
1871 return false;
1872
1873 return true;
1874}
1875
1876static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1877{
1878 struct kvm_segment cs, ss;
1879
1880 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1881 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1882
1883 return ((cs.selector & SELECTOR_RPL_MASK) ==
1884 (ss.selector & SELECTOR_RPL_MASK));
1885}
1886
1887/*
1888 * Check if guest state is valid. Returns true if valid, false if
1889 * not.
1890 * We assume that registers are always usable
1891 */
1892static bool guest_state_valid(struct kvm_vcpu *vcpu)
1893{
1894 /* real mode guest state checks */
1895 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1896 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1897 return false;
1898 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1899 return false;
1900 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1901 return false;
1902 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1903 return false;
1904 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1905 return false;
1906 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1907 return false;
1908 } else {
1909 /* protected mode guest state checks */
1910 if (!cs_ss_rpl_check(vcpu))
1911 return false;
1912 if (!code_segment_valid(vcpu))
1913 return false;
1914 if (!stack_segment_valid(vcpu))
1915 return false;
1916 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1917 return false;
1918 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1919 return false;
1920 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1921 return false;
1922 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1923 return false;
1924 if (!tr_valid(vcpu))
1925 return false;
1926 if (!ldtr_valid(vcpu))
1927 return false;
1928 }
1929 /* TODO:
1930 * - Add checks on RIP
1931 * - Add checks on RFLAGS
1932 */
1933
1934 return true;
1935}
1936
d77c26fc 1937static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1938{
6aa8b732 1939 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 1940 u16 data = 0;
10589a46 1941 int ret = 0;
195aefde 1942 int r;
6aa8b732 1943
195aefde
IE		 1944 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1945 if (r < 0)
10589a46 1946 goto out;
195aefde 1947 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 1948 r = kvm_write_guest_page(kvm, fn++, &data,
1949 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 1950 if (r < 0)
10589a46 1951 goto out;
195aefde
IE		 1952 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1953 if (r < 0)
10589a46 1954 goto out;
195aefde
IE		 1955 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1956 if (r < 0)
10589a46 1957 goto out;
195aefde 1958 data = ~0;
10589a46
MT		 1959 r = kvm_write_guest_page(kvm, fn, &data,
1960 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1961 sizeof(u8));
195aefde 1962 if (r < 0)
10589a46
MT		 1963 goto out;
1964
1965 ret = 1;
1966out:
10589a46 1967 return ret;
6aa8b732
AK		 1968}
1969
b7ebfb05
SY		 1970static int init_rmode_identity_map(struct kvm *kvm)
1971{
1972 int i, r, ret;
1973 pfn_t identity_map_pfn;
1974 u32 tmp;
1975
1976 if (!vm_need_ept())
1977 return 1;
1978 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1979 printk(KERN_ERR "EPT: identity-mapping pagetable "
1980 "haven't been allocated!\n");
1981 return 0;
1982 }
1983 if (likely(kvm->arch.ept_identity_pagetable_done))
1984 return 1;
1985 ret = 0;
1986 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1987 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1988 if (r < 0)
1989 goto out;
1990 /* Set up identity-mapping pagetable for EPT in real mode */
1991 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1992 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1993 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1994 r = kvm_write_guest_page(kvm, identity_map_pfn,
1995 &tmp, i * sizeof(tmp), sizeof(tmp));
1996 if (r < 0)
1997 goto out;
1998 }
1999 kvm->arch.ept_identity_pagetable_done = true;
2000 ret = 1;
2001out:
2002 return ret;
2003}
2004
6aa8b732
AK		 2005static void seg_setup(int seg)
2006{
2007 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2008
2009 vmcs_write16(sf->selector, 0);
2010 vmcs_writel(sf->base, 0);
2011 vmcs_write32(sf->limit, 0xffff);
a16b20da 2012 vmcs_write32(sf->ar_bytes, 0xf3);
6aa8b732
AK		 2013}
2014
f78e0e2e
SY		 2015static int alloc_apic_access_page(struct kvm *kvm)
2016{
2017 struct kvm_userspace_memory_region kvm_userspace_mem;
2018 int r = 0;
2019
72dc67a6 2020 down_write(&kvm->slots_lock);
bfc6d222 2021 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2022 goto out;
2023 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2024 kvm_userspace_mem.flags = 0;
2025 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2026 kvm_userspace_mem.memory_size = PAGE_SIZE;
2027 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2028 if (r)
2029 goto out;
72dc67a6 2030
bfc6d222 2031 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2032out:
72dc67a6 2033 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2034 return r;
2035}
2036
b7ebfb05
SY		 2037static int alloc_identity_pagetable(struct kvm *kvm)
2038{
2039 struct kvm_userspace_memory_region kvm_userspace_mem;
2040 int r = 0;
2041
2042 down_write(&kvm->slots_lock);
2043 if (kvm->arch.ept_identity_pagetable)
2044 goto out;
2045 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2046 kvm_userspace_mem.flags = 0;
2047 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2048 kvm_userspace_mem.memory_size = PAGE_SIZE;
2049 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2050 if (r)
2051 goto out;
2052
b7ebfb05
SY		 2053 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2054 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
b7ebfb05
SY		 2055out:
2056 up_write(&kvm->slots_lock);
2057 return r;
2058}
2059
2384d2b3
SY		 2060static void allocate_vpid(struct vcpu_vmx *vmx)
2061{
2062 int vpid;
2063
2064 vmx->vpid = 0;
2065 if (!enable_vpid || !cpu_has_vmx_vpid())
2066 return;
2067 spin_lock(&vmx_vpid_lock);
2068 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2069 if (vpid < VMX_NR_VPIDS) {
2070 vmx->vpid = vpid;
2071 __set_bit(vpid, vmx_vpid_bitmap);
2072 }
2073 spin_unlock(&vmx_vpid_lock);
2074}
2075
8b2cf73c 2076static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
25c5f225
SY		 2077{
2078 void *va;
2079
2080 if (!cpu_has_vmx_msr_bitmap())
2081 return;
2082
2083 /*
2084 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2085 * have the write-low and read-high bitmap offsets the wrong way round.
2086 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2087 */
2088 va = kmap(msr_bitmap);
2089 if (msr <= 0x1fff) {
2090 __clear_bit(msr, va + 0x000); /* read-low */
2091 __clear_bit(msr, va + 0x800); /* write-low */
2092 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2093 msr &= 0x1fff;
2094 __clear_bit(msr, va + 0x400); /* read-high */
2095 __clear_bit(msr, va + 0xc00); /* write-high */
2096 }
2097 kunmap(msr_bitmap);
2098}
2099
6aa8b732
AK		 2100/*
2101 * Sets up the vmcs for emulated real mode.
2102 */
8b9cf98c 2103static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2104{
468d472f 2105 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2106 u32 junk;
468d472f 2107 u64 host_pat;
6aa8b732
AK		 2108 unsigned long a;
2109 struct descriptor_table dt;
2110 int i;
cd2276a7 2111 unsigned long kvm_vmx_return;
6e5d865c 2112 u32 exec_control;
6aa8b732 2113
6aa8b732 2114 /* I/O */
fdef3ad1
HQ		 2115 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2116 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732 2117
25c5f225
SY		 2118 if (cpu_has_vmx_msr_bitmap())
2119 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2120
6aa8b732
AK		 2121 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2122
6aa8b732 2123 /* Control */
1c3d14fe
YS		 2124 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2125 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2126
2127 exec_control = vmcs_config.cpu_based_exec_ctrl;
2128 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2129 exec_control &= ~CPU_BASED_TPR_SHADOW;
2130#ifdef CONFIG_X86_64
2131 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2132 CPU_BASED_CR8_LOAD_EXITING;
2133#endif
2134 }
d56f546d
SY		 2135 if (!vm_need_ept())
2136 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2137 CPU_BASED_CR3_LOAD_EXITING |
2138 CPU_BASED_INVLPG_EXITING;
6e5d865c 2139 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2140
83ff3b9d
SY		 2141 if (cpu_has_secondary_exec_ctrls()) {
2142 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2143 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2144 exec_control &=
2145 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2146 if (vmx->vpid == 0)
2147 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
d56f546d
SY		 2148 if (!vm_need_ept())
2149 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
83ff3b9d
SY		 2150 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2151 }
f78e0e2e 2152
c7addb90
AK		 2153 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2154 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2155 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2156
2157 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2158 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2159 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2160
2161 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2162 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2163 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2164 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2165 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2166 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2167#ifdef CONFIG_X86_64
6aa8b732
AK		 2168 rdmsrl(MSR_FS_BASE, a);
2169 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2170 rdmsrl(MSR_GS_BASE, a);
2171 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2172#else
2173 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2174 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2175#endif
2176
2177 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2178
d6e88aec 2179 kvm_get_idt(&dt);
6aa8b732
AK		 2180 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2181
d77c26fc 2182 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2183 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2184 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2185 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2186 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2187
2188 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2189 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2190 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2191 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2192 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2193 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2194
468d472f
SY		 2195 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2196 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2197 host_pat = msr_low | ((u64) msr_high << 32);
2198 vmcs_write64(HOST_IA32_PAT, host_pat);
2199 }
2200 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2201 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2202 host_pat = msr_low | ((u64) msr_high << 32);
2203 /* Write the default value follow host pat */
2204 vmcs_write64(GUEST_IA32_PAT, host_pat);
2205 /* Keep arch.pat sync with GUEST_IA32_PAT */
2206 vmx->vcpu.arch.pat = host_pat;
2207 }
2208
6aa8b732
AK		 2209 for (i = 0; i < NR_VMX_MSR; ++i) {
2210 u32 index = vmx_msr_index[i];
2211 u32 data_low, data_high;
2212 u64 data;
a2fa3e9f 2213 int j = vmx->nmsrs;
6aa8b732
AK		 2214
2215 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2216 continue;
432bd6cb
AK		 2217 if (wrmsr_safe(index, data_low, data_high) < 0)
2218 continue;
6aa8b732 2219 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 2220 vmx->host_msrs[j].index = index;
2221 vmx->host_msrs[j].reserved = 0;
2222 vmx->host_msrs[j].data = data;
2223 vmx->guest_msrs[j] = vmx->host_msrs[j];
2224 ++vmx->nmsrs;
6aa8b732 2225 }
6aa8b732 2226
1c3d14fe 2227 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2228
2229 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2230 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2231
e00c8cf2
AK		 2232 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2233 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2234
f78e0e2e 2235
e00c8cf2
AK		 2236 return 0;
2237}
2238
b7ebfb05
SY		 2239static int init_rmode(struct kvm *kvm)
2240{
2241 if (!init_rmode_tss(kvm))
2242 return 0;
2243 if (!init_rmode_identity_map(kvm))
2244 return 0;
2245 return 1;
2246}
2247
e00c8cf2
AK		 2248static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2249{
2250 struct vcpu_vmx *vmx = to_vmx(vcpu);
2251 u64 msr;
2252 int ret;
2253
5fdbf976 2254 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2255 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2256 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2257 ret = -ENOMEM;
2258 goto out;
2259 }
2260
ad312c7c 2261 vmx->vcpu.arch.rmode.active = 0;
e00c8cf2 2262
3b86cd99
JK		 2263 vmx->soft_vnmi_blocked = 0;
2264
ad312c7c 2265 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2266 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2
AK		 2267 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2268 if (vmx->vcpu.vcpu_id == 0)
2269 msr |= MSR_IA32_APICBASE_BSP;
2270 kvm_set_apic_base(&vmx->vcpu, msr);
2271
2272 fx_init(&vmx->vcpu);
2273
5706be0d 2274 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2275 /*
2276 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2277 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2278 */
2279 if (vmx->vcpu.vcpu_id == 0) {
2280 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2281 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2282 } else {
ad312c7c
ZX		 2283 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2284 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2285 }
e00c8cf2
AK		 2286
2287 seg_setup(VCPU_SREG_DS);
2288 seg_setup(VCPU_SREG_ES);
2289 seg_setup(VCPU_SREG_FS);
2290 seg_setup(VCPU_SREG_GS);
2291 seg_setup(VCPU_SREG_SS);
2292
2293 vmcs_write16(GUEST_TR_SELECTOR, 0);
2294 vmcs_writel(GUEST_TR_BASE, 0);
2295 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2296 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2297
2298 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2299 vmcs_writel(GUEST_LDTR_BASE, 0);
2300 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2301 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2302
2303 vmcs_write32(GUEST_SYSENTER_CS, 0);
2304 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2305 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2306
2307 vmcs_writel(GUEST_RFLAGS, 0x02);
2308 if (vmx->vcpu.vcpu_id == 0)
5fdbf976 2309 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2310 else
5fdbf976
MT		 2311 kvm_rip_write(vcpu, 0);
2312 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2
AK		 2313
2314 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2315 vmcs_writel(GUEST_DR7, 0x400);
2316
2317 vmcs_writel(GUEST_GDTR_BASE, 0);
2318 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2319
2320 vmcs_writel(GUEST_IDTR_BASE, 0);
2321 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2322
2323 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2324 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2325 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2326
2327 guest_write_tsc(0);
2328
2329 /* Special registers */
2330 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2331
2332 setup_msrs(vmx);
2333
6aa8b732
AK		 2334 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2335
f78e0e2e
SY		 2336 if (cpu_has_vmx_tpr_shadow()) {
2337 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2338 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2339 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2340 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2341 vmcs_write32(TPR_THRESHOLD, 0);
2342 }
2343
2344 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2345 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2346 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2347
2384d2b3
SY		 2348 if (vmx->vpid != 0)
2349 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2350
ad312c7c
ZX		 2351 vmx->vcpu.arch.cr0 = 0x60000010;
2352 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2353 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2354 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2355 vmx_fpu_activate(&vmx->vcpu);
2356 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2357
2384d2b3
SY		 2358 vpid_sync_vcpu_all(vmx);
2359
3200f405 2360 ret = 0;
6aa8b732 2361
a89a8fb9
MG		 2362 /* HACK: Don't enable emulation on guest boot/reset */
2363 vmx->emulation_required = 0;
2364
6aa8b732 2365out:
3200f405 2366 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2367 return ret;
2368}
2369
3b86cd99
JK		 2370static void enable_irq_window(struct kvm_vcpu *vcpu)
2371{
2372 u32 cpu_based_vm_exec_control;
2373
2374 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2375 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2376 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2377}
2378
2379static void enable_nmi_window(struct kvm_vcpu *vcpu)
2380{
2381 u32 cpu_based_vm_exec_control;
2382
2383 if (!cpu_has_virtual_nmis()) {
2384 enable_irq_window(vcpu);
2385 return;
2386 }
2387
2388 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2389 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2390 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2391}
2392
85f455f7
ED		 2393static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2394{
9c8cba37
AK		 2395 struct vcpu_vmx *vmx = to_vmx(vcpu);
2396
2714d1d3
FEL		 2397 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2398
fa89a817 2399 ++vcpu->stat.irq_injections;
ad312c7c 2400 if (vcpu->arch.rmode.active) {
9c8cba37
AK		 2401 vmx->rmode.irq.pending = true;
2402 vmx->rmode.irq.vector = irq;
5fdbf976 2403 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
9c5623e3
AK		 2404 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2405 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2406 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2407 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2408 return;
2409 }
2410 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2411 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2412}
2413
f08864b4
SY		 2414static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2415{
66a5a347
JK		 2416 struct vcpu_vmx *vmx = to_vmx(vcpu);
2417
3b86cd99
JK		 2418 if (!cpu_has_virtual_nmis()) {
2419 /*
2420 * Tracking the NMI-blocked state in software is built upon
2421 * finding the next open IRQ window. This, in turn, depends on
2422 * well-behaving guests: They have to keep IRQs disabled at
2423 * least as long as the NMI handler runs. Otherwise we may
2424 * cause NMI nesting, maybe breaking the guest. But as this is
2425 * highly unlikely, we can live with the residual risk.
2426 */
2427 vmx->soft_vnmi_blocked = 1;
2428 vmx->vnmi_blocked_time = 0;
2429 }
2430
487b391d 2431 ++vcpu->stat.nmi_injections;
66a5a347
JK		 2432 if (vcpu->arch.rmode.active) {
2433 vmx->rmode.irq.pending = true;
2434 vmx->rmode.irq.vector = NMI_VECTOR;
2435 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2436 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2437 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2438 INTR_INFO_VALID_MASK);
2439 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2440 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2441 return;
2442 }
f08864b4
SY		 2443 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2444 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2445}
2446
33f089ca
JK		 2447static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2448{
2449 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2450
2451 vcpu->arch.nmi_window_open =
2452 !(guest_intr & (GUEST_INTR_STATE_STI |
2453 GUEST_INTR_STATE_MOV_SS |
2454 GUEST_INTR_STATE_NMI));
3b86cd99
JK		 2455 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2456 vcpu->arch.nmi_window_open = 0;
33f089ca
JK		 2457
2458 vcpu->arch.interrupt_window_open =
2459 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2460 !(guest_intr & (GUEST_INTR_STATE_STI |
2461 GUEST_INTR_STATE_MOV_SS)));
2462}
2463
6aa8b732
AK		 2464static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2465{
ad312c7c
ZX		 2466 int word_index = __ffs(vcpu->arch.irq_summary);
2467 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
6aa8b732
AK		 2468 int irq = word_index * BITS_PER_LONG + bit_index;
2469
ad312c7c
ZX		 2470 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2471 if (!vcpu->arch.irq_pending[word_index])
2472 clear_bit(word_index, &vcpu->arch.irq_summary);
ecfc79c7 2473 kvm_queue_interrupt(vcpu, irq);
6aa8b732
AK		 2474}
2475
f460ee43
JK		 2476static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2477 struct kvm_run *kvm_run)
2478{
2479 vmx_update_window_states(vcpu);
2480
55934c0b
JK		 2481 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2482 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2483 GUEST_INTR_STATE_STI |
2484 GUEST_INTR_STATE_MOV_SS);
2485
3b86cd99 2486 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
264ff01d
JK		 2487 if (vcpu->arch.interrupt.pending) {
2488 enable_nmi_window(vcpu);
2489 } else if (vcpu->arch.nmi_window_open) {
3b86cd99
JK		 2490 vcpu->arch.nmi_pending = false;
2491 vcpu->arch.nmi_injected = true;
2492 } else {
2493 enable_nmi_window(vcpu);
487b391d
JK		 2494 return;
2495 }
3b86cd99
JK		 2496 }
2497 if (vcpu->arch.nmi_injected) {
2498 vmx_inject_nmi(vcpu);
4531220b 2499 if (vcpu->arch.nmi_pending)
487b391d 2500 enable_nmi_window(vcpu);
3b86cd99
JK		 2501 else if (vcpu->arch.irq_summary
2502 || kvm_run->request_interrupt_window)
2503 enable_irq_window(vcpu);
2504 return;
487b391d
JK		 2505 }
2506
f460ee43
JK		 2507 if (vcpu->arch.interrupt_window_open) {
2508 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2509 kvm_do_inject_irq(vcpu);
2510
2511 if (vcpu->arch.interrupt.pending)
2512 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2513 }
ad312c7c
ZX		 2514 if (!vcpu->arch.interrupt_window_open &&
2515 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
f460ee43 2516 enable_irq_window(vcpu);
6aa8b732
AK		 2517}
2518
cbc94022
IE		 2519static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2520{
2521 int ret;
2522 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2523 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2524 .guest_phys_addr = addr,
2525 .memory_size = PAGE_SIZE * 3,
2526 .flags = 0,
2527 };
2528
2529 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2530 if (ret)
2531 return ret;
bfc6d222 2532 kvm->arch.tss_addr = addr;
cbc94022
IE		 2533 return 0;
2534}
2535
6aa8b732
AK		 2536static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2537 int vec, u32 err_code)
2538{
b3f37707
NK		 2539 /*
2540 * Instruction with address size override prefix opcode 0x67
2541 * Cause the #SS fault with 0 error code in VM86 mode.
2542 */
2543 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2544 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2545 return 1;
77ab6db0
JK		 2546 /*
2547 * Forward all other exceptions that are valid in real mode.
2548 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2549 * the required debugging infrastructure rework.
2550 */
2551 switch (vec) {
77ab6db0 2552 case DB_VECTOR:
d0bfb940
JK		 2553 if (vcpu->guest_debug &
2554 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2555 return 0;
2556 kvm_queue_exception(vcpu, vec);
2557 return 1;
77ab6db0 2558 case BP_VECTOR:
d0bfb940
JK		 2559 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2560 return 0;
2561 /* fall through */
2562 case DE_VECTOR:
77ab6db0
JK		 2563 case OF_VECTOR:
2564 case BR_VECTOR:
2565 case UD_VECTOR:
2566 case DF_VECTOR:
2567 case SS_VECTOR:
2568 case GP_VECTOR:
2569 case MF_VECTOR:
2570 kvm_queue_exception(vcpu, vec);
2571 return 1;
2572 }
6aa8b732
AK		 2573 return 0;
2574}
2575
2576static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2577{
1155f76a 2578 struct vcpu_vmx *vmx = to_vmx(vcpu);
d0bfb940 2579 u32 intr_info, ex_no, error_code;
6aa8b732
AK		 2580 unsigned long cr2, rip;
2581 u32 vect_info;
2582 enum emulation_result er;
2583
1155f76a 2584 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2585 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2586
2587 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2588 !is_page_fault(intr_info))
6aa8b732 2589 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2590 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2591
85f455f7 2592 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732 2593 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
ad312c7c
ZX		 2594 set_bit(irq, vcpu->arch.irq_pending);
2595 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
6aa8b732
AK		 2596 }
2597
e4a41889 2598 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2599 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2600
2601 if (is_no_device(intr_info)) {
5fd86fcf 2602 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2603 return 1;
2604 }
2605
7aa81cc0 2606 if (is_invalid_opcode(intr_info)) {
571008da 2607 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2608 if (er != EMULATE_DONE)
7ee5d940 2609 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2610 return 1;
2611 }
2612
6aa8b732 2613 error_code = 0;
5fdbf976 2614 rip = kvm_rip_read(vcpu);
2e11384c 2615 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2616 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2617 if (is_page_fault(intr_info)) {
1439442c
SY		 2618 /* EPT won't cause page fault directly */
2619 if (vm_need_ept())
2620 BUG();
6aa8b732 2621 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2714d1d3
FEL		 2622 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2623 (u32)((u64)cr2 >> 32), handler);
f7d9238f 2624 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
577bdc49 2625 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2626 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2627 }
2628
ad312c7c 2629 if (vcpu->arch.rmode.active &&
6aa8b732 2630 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2631 error_code)) {
ad312c7c
ZX		 2632 if (vcpu->arch.halt_request) {
2633 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2634 return kvm_emulate_halt(vcpu);
2635 }
6aa8b732 2636 return 1;
72d6e5a0 2637 }
6aa8b732 2638
d0bfb940
JK		 2639 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2640 if (ex_no == DB_VECTOR || ex_no == BP_VECTOR) {
6aa8b732 2641 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2642 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2643 kvm_run->debug.arch.exception = ex_no;
2644 } else {
2645 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2646 kvm_run->ex.exception = ex_no;
2647 kvm_run->ex.error_code = error_code;
6aa8b732 2648 }
6aa8b732
AK		 2649 return 0;
2650}
2651
2652static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2653 struct kvm_run *kvm_run)
2654{
1165f5fe 2655 ++vcpu->stat.irq_exits;
2714d1d3 2656 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
6aa8b732
AK		 2657 return 1;
2658}
2659
988ad74f
AK		 2660static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2661{
2662 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2663 return 0;
2664}
6aa8b732 2665
6aa8b732
AK		 2666static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2667{
bfdaab09 2668 unsigned long exit_qualification;
039576c0
AK		 2669 int size, down, in, string, rep;
2670 unsigned port;
6aa8b732 2671
1165f5fe 2672 ++vcpu->stat.io_exits;
bfdaab09 2673 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2674 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2675
2676 if (string) {
3427318f
LV		 2677 if (emulate_instruction(vcpu,
2678 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2679 return 0;
2680 return 1;
2681 }
2682
2683 size = (exit_qualification & 7) + 1;
2684 in = (exit_qualification & 8) != 0;
039576c0 2685 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 2686 rep = (exit_qualification & 32) != 0;
2687 port = exit_qualification >> 16;
e70669ab 2688
e93f36bc 2689 skip_emulated_instruction(vcpu);
3090dd73 2690 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2691}
2692
102d8325
IM		 2693static void
2694vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2695{
2696 /*
2697 * Patch in the VMCALL instruction:
2698 */
2699 hypercall[0] = 0x0f;
2700 hypercall[1] = 0x01;
2701 hypercall[2] = 0xc1;
102d8325
IM		 2702}
2703
6aa8b732
AK		 2704static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2705{
bfdaab09 2706 unsigned long exit_qualification;
6aa8b732
AK		 2707 int cr;
2708 int reg;
2709
bfdaab09 2710 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2711 cr = exit_qualification & 15;
2712 reg = (exit_qualification >> 8) & 15;
2713 switch ((exit_qualification >> 4) & 3) {
2714 case 0: /* mov to cr */
5fdbf976
MT		 2715 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2716 (u32)kvm_register_read(vcpu, reg),
2717 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2718 handler);
6aa8b732
AK		 2719 switch (cr) {
2720 case 0:
5fdbf976 2721 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2722 skip_emulated_instruction(vcpu);
2723 return 1;
2724 case 3:
5fdbf976 2725 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2726 skip_emulated_instruction(vcpu);
2727 return 1;
2728 case 4:
5fdbf976 2729 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2730 skip_emulated_instruction(vcpu);
2731 return 1;
2732 case 8:
5fdbf976 2733 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
6aa8b732 2734 skip_emulated_instruction(vcpu);
e5314067
AK		 2735 if (irqchip_in_kernel(vcpu->kvm))
2736 return 1;
253abdee
YS		 2737 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2738 return 0;
6aa8b732
AK		 2739 };
2740 break;
25c4c276 2741 case 2: /* clts */
5fd86fcf 2742 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2743 vcpu->arch.cr0 &= ~X86_CR0_TS;
2744 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2745 vmx_fpu_activate(vcpu);
2714d1d3 2746 KVMTRACE_0D(CLTS, vcpu, handler);
25c4c276
AL		 2747 skip_emulated_instruction(vcpu);
2748 return 1;
6aa8b732
AK		 2749 case 1: /*mov from cr*/
2750 switch (cr) {
2751 case 3:
5fdbf976 2752 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2714d1d3 2753 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
5fdbf976
MT		 2754 (u32)kvm_register_read(vcpu, reg),
2755 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2714d1d3 2756 handler);
6aa8b732
AK		 2757 skip_emulated_instruction(vcpu);
2758 return 1;
2759 case 8:
5fdbf976 2760 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2714d1d3 2761 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
5fdbf976 2762 (u32)kvm_register_read(vcpu, reg), handler);
6aa8b732
AK		 2763 skip_emulated_instruction(vcpu);
2764 return 1;
2765 }
2766 break;
2767 case 3: /* lmsw */
2d3ad1f4 2768 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2769
2770 skip_emulated_instruction(vcpu);
2771 return 1;
2772 default:
2773 break;
2774 }
2775 kvm_run->exit_reason = 0;
f0242478 2776 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2777 (int)(exit_qualification >> 4) & 3, cr);
2778 return 0;
2779}
2780
2781static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2782{
bfdaab09 2783 unsigned long exit_qualification;
6aa8b732
AK		 2784 unsigned long val;
2785 int dr, reg;
2786
2787 /*
2788 * FIXME: this code assumes the host is debugging the guest.
2789 * need to deal with guest debugging itself too.
2790 */
bfdaab09 2791 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2792 dr = exit_qualification & 7;
2793 reg = (exit_qualification >> 8) & 15;
6aa8b732
AK		 2794 if (exit_qualification & 16) {
2795 /* mov from dr */
2796 switch (dr) {
2797 case 6:
2798 val = 0xffff0ff0;
2799 break;
2800 case 7:
2801 val = 0x400;
2802 break;
2803 default:
2804 val = 0;
2805 }
5fdbf976 2806 kvm_register_write(vcpu, reg, val);
2714d1d3 2807 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
6aa8b732
AK		 2808 } else {
2809 /* mov to dr */
2810 }
6aa8b732
AK		 2811 skip_emulated_instruction(vcpu);
2812 return 1;
2813}
2814
2815static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2816{
06465c5a
AK		 2817 kvm_emulate_cpuid(vcpu);
2818 return 1;
6aa8b732
AK		 2819}
2820
2821static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2822{
ad312c7c 2823 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2824 u64 data;
2825
2826 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 2827 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2828 return 1;
2829 }
2830
2714d1d3
FEL		 2831 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2832 handler);
2833
6aa8b732 2834 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 2835 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2836 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 2837 skip_emulated_instruction(vcpu);
2838 return 1;
2839}
2840
2841static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2842{
ad312c7c
ZX		 2843 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2844 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2845 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 2846
2714d1d3
FEL		 2847 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2848 handler);
2849
6aa8b732 2850 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 2851 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2852 return 1;
2853 }
2854
2855 skip_emulated_instruction(vcpu);
2856 return 1;
2857}
2858
6e5d865c
YS		 2859static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2860 struct kvm_run *kvm_run)
2861{
2862 return 1;
2863}
2864
6aa8b732
AK		 2865static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2866 struct kvm_run *kvm_run)
2867{
85f455f7
ED		 2868 u32 cpu_based_vm_exec_control;
2869
2870 /* clear pending irq */
2871 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2872 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2873 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3
FEL		 2874
2875 KVMTRACE_0D(PEND_INTR, vcpu, handler);
a26bf12a 2876 ++vcpu->stat.irq_window_exits;
2714d1d3 2877
c1150d8c
DL		 2878 /*
2879 * If the user space waits to inject interrupts, exit as soon as
2880 * possible
2881 */
2882 if (kvm_run->request_interrupt_window &&
ad312c7c 2883 !vcpu->arch.irq_summary) {
c1150d8c 2884 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 2885 return 0;
2886 }
6aa8b732
AK		 2887 return 1;
2888}
2889
2890static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2891{
2892 skip_emulated_instruction(vcpu);
d3bef15f 2893 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2894}
2895
c21415e8
IM		 2896static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2897{
510043da 2898 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2899 kvm_emulate_hypercall(vcpu);
2900 return 1;
c21415e8
IM		 2901}
2902
a7052897
MT		 2903static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2904{
2905 u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2906
2907 kvm_mmu_invlpg(vcpu, exit_qualification);
2908 skip_emulated_instruction(vcpu);
2909 return 1;
2910}
2911
e5edaa01
ED		 2912static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2913{
2914 skip_emulated_instruction(vcpu);
2915 /* TODO: Add support for VT-d/pass-through device */
2916 return 1;
2917}
2918
f78e0e2e
SY		 2919static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2920{
2921 u64 exit_qualification;
2922 enum emulation_result er;
2923 unsigned long offset;
2924
2925 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2926 offset = exit_qualification & 0xffful;
2927
2928 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2929
2930 if (er != EMULATE_DONE) {
2931 printk(KERN_ERR
2932 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2933 offset);
2934 return -ENOTSUPP;
2935 }
2936 return 1;
2937}
2938
37817f29
IE		 2939static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2940{
60637aac 2941 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 2942 unsigned long exit_qualification;
2943 u16 tss_selector;
2944 int reason;
2945
2946 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2947
2948 reason = (u32)exit_qualification >> 30;
60637aac
JK		 2949 if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
2950 (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
2951 (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
2952 == INTR_TYPE_NMI_INTR) {
2953 vcpu->arch.nmi_injected = false;
2954 if (cpu_has_virtual_nmis())
2955 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2956 GUEST_INTR_STATE_NMI);
2957 }
37817f29
IE		 2958 tss_selector = exit_qualification;
2959
2960 return kvm_task_switch(vcpu, tss_selector, reason);
2961}
2962
1439442c
SY		 2963static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2964{
2965 u64 exit_qualification;
2966 enum emulation_result er;
2967 gpa_t gpa;
2968 unsigned long hva;
2969 int gla_validity;
2970 int r;
2971
2972 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2973
2974 if (exit_qualification & (1 << 6)) {
2975 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2976 return -ENOTSUPP;
2977 }
2978
2979 gla_validity = (exit_qualification >> 7) & 0x3;
2980 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2981 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2982 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2983 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2984 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2985 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2986 (long unsigned int)exit_qualification);
2987 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2988 kvm_run->hw.hardware_exit_reason = 0;
2989 return -ENOTSUPP;
2990 }
2991
2992 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2993 hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2994 if (!kvm_is_error_hva(hva)) {
2995 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2996 if (r < 0) {
2997 printk(KERN_ERR "EPT: Not enough memory!\n");
2998 return -ENOMEM;
2999 }
3000 return 1;
3001 } else {
3002 /* must be MMIO */
3003 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3004
3005 if (er == EMULATE_FAIL) {
3006 printk(KERN_ERR
3007 "EPT: Fail to handle EPT violation vmexit!er is %d\n",
3008 er);
3009 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3010 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3011 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3012 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3013 (long unsigned int)exit_qualification);
3014 return -ENOTSUPP;
3015 } else if (er == EMULATE_DO_MMIO)
3016 return 0;
3017 }
3018 return 1;
3019}
3020
f08864b4
SY		 3021static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3022{
3023 u32 cpu_based_vm_exec_control;
3024
3025 /* clear pending NMI */
3026 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3027 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3028 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3029 ++vcpu->stat.nmi_window_exits;
3030
3031 return 1;
3032}
3033
ea953ef0
MG		 3034static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3035 struct kvm_run *kvm_run)
3036{
3037 struct vcpu_vmx *vmx = to_vmx(vcpu);
3038 int err;
3039
3040 preempt_enable();
3041 local_irq_enable();
3042
3043 while (!guest_state_valid(vcpu)) {
3044 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3045
1d5a4d9b
GT		 3046 if (err == EMULATE_DO_MMIO)
3047 break;
3048
3049 if (err != EMULATE_DONE) {
3050 kvm_report_emulation_failure(vcpu, "emulation failure");
3051 return;
ea953ef0
MG		 3052 }
3053
3054 if (signal_pending(current))
3055 break;
3056 if (need_resched())
3057 schedule();
3058 }
3059
3060 local_irq_disable();
3061 preempt_disable();
3062
1d5a4d9b
GT		 3063 /* Guest state should be valid now except if we need to
3064 * emulate an MMIO */
3065 if (guest_state_valid(vcpu))
3066 vmx->emulation_required = 0;
ea953ef0
MG		 3067}
3068
6aa8b732
AK		 3069/*
3070 * The exit handlers return 1 if the exit was handled fully and guest execution
3071 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3072 * to be done to userspace and return 0.
3073 */
3074static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3075 struct kvm_run *kvm_run) = {
3076 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3077 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3078 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3079 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3080 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3081 [EXIT_REASON_CR_ACCESS] = handle_cr,
3082 [EXIT_REASON_DR_ACCESS] = handle_dr,
3083 [EXIT_REASON_CPUID] = handle_cpuid,
3084 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3085 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3086 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3087 [EXIT_REASON_HLT] = handle_halt,
a7052897 3088 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3089 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 3090 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3091 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3092 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3093 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
1439442c 3094 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6aa8b732
AK		 3095};
3096
3097static const int kvm_vmx_max_exit_handlers =
50a3485c 3098 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3099
3100/*
3101 * The guest has exited. See if we can fix it or if we need userspace
3102 * assistance.
3103 */
3104static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3105{
6aa8b732 3106 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 3107 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 3108 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3109
5fdbf976
MT		 3110 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3111 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
2714d1d3 3112
1d5a4d9b
GT		 3113 /* If we need to emulate an MMIO from handle_invalid_guest_state
3114 * we just return 0 */
3115 if (vmx->emulation_required && emulate_invalid_guest_state)
3116 return 0;
3117
1439442c
SY		 3118 /* Access CR3 don't cause VMExit in paging mode, so we need
3119 * to sync with guest real CR3. */
3120 if (vm_need_ept() && is_paging(vcpu)) {
3121 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3122 ept_load_pdptrs(vcpu);
3123 }
3124
29bd8a78
AK		 3125 if (unlikely(vmx->fail)) {
3126 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3127 kvm_run->fail_entry.hardware_entry_failure_reason
3128 = vmcs_read32(VM_INSTRUCTION_ERROR);
3129 return 0;
3130 }
6aa8b732 3131
d77c26fc 3132 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3133 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3134 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3135 exit_reason != EXIT_REASON_TASK_SWITCH))
3136 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3137 "(0x%x) and exit reason is 0x%x\n",
3138 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3139
3140 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3141 if (vcpu->arch.interrupt_window_open) {
3142 vmx->soft_vnmi_blocked = 0;
3143 vcpu->arch.nmi_window_open = 1;
3144 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3145 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3146 /*
3147 * This CPU don't support us in finding the end of an
3148 * NMI-blocked window if the guest runs with IRQs
3149 * disabled. So we pull the trigger after 1 s of
3150 * futile waiting, but inform the user about this.
3151 */
3152 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3153 "state on VCPU %d after 1 s timeout\n",
3154 __func__, vcpu->vcpu_id);
3155 vmx->soft_vnmi_blocked = 0;
3156 vmx->vcpu.arch.nmi_window_open = 1;
3157 }
3b86cd99
JK		 3158 }
3159
6aa8b732
AK		 3160 if (exit_reason < kvm_vmx_max_exit_handlers
3161 && kvm_vmx_exit_handlers[exit_reason])
3162 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3163 else {
3164 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3165 kvm_run->hw.hardware_exit_reason = exit_reason;
3166 }
3167 return 0;
3168}
3169
6e5d865c
YS		 3170static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3171{
3172 int max_irr, tpr;
3173
3174 if (!vm_need_tpr_shadow(vcpu->kvm))
3175 return;
3176
3177 if (!kvm_lapic_enabled(vcpu) ||
3178 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3179 vmcs_write32(TPR_THRESHOLD, 0);
3180 return;
3181 }
3182
3183 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3184 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3185}
3186
cf393f75
AK		 3187static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3188{
3189 u32 exit_intr_info;
668f612f 3190 u32 idt_vectoring_info;
cf393f75
AK		 3191 bool unblock_nmi;
3192 u8 vector;
668f612f
AK		 3193 int type;
3194 bool idtv_info_valid;
35920a35 3195 u32 error;
cf393f75
AK		 3196
3197 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3198 if (cpu_has_virtual_nmis()) {
3199 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3200 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3201 /*
3202 * SDM 3: 25.7.1.2
3203 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3204 * a guest IRET fault.
3205 */
3206 if (unblock_nmi && vector != DF_VECTOR)
3207 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3208 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3209 } else if (unlikely(vmx->soft_vnmi_blocked))
3210 vmx->vnmi_blocked_time +=
3211 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f
AK		 3212
3213 idt_vectoring_info = vmx->idt_vectoring_info;
3214 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3215 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3216 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3217 if (vmx->vcpu.arch.nmi_injected) {
3218 /*
3219 * SDM 3: 25.7.1.2
3220 * Clear bit "block by NMI" before VM entry if a NMI delivery
3221 * faulted.
3222 */
3223 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3224 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3225 GUEST_INTR_STATE_NMI);
3226 else
3227 vmx->vcpu.arch.nmi_injected = false;
3228 }
35920a35 3229 kvm_clear_exception_queue(&vmx->vcpu);
8ab2d2e2
JK		 3230 if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION ||
3231 type == INTR_TYPE_SOFT_EXCEPTION)) {
35920a35
AK		 3232 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3233 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3234 kvm_queue_exception_e(&vmx->vcpu, vector, error);
3235 } else
3236 kvm_queue_exception(&vmx->vcpu, vector);
3237 vmx->idt_vectoring_info = 0;
3238 }
f7d9238f
AK		 3239 kvm_clear_interrupt_queue(&vmx->vcpu);
3240 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3241 kvm_queue_interrupt(&vmx->vcpu, vector);
3242 vmx->idt_vectoring_info = 0;
3243 }
cf393f75
AK		 3244}
3245
85f455f7
ED		 3246static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3247{
6e5d865c
YS		 3248 update_tpr_threshold(vcpu);
3249
33f089ca
JK		 3250 vmx_update_window_states(vcpu);
3251
55934c0b
JK		 3252 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3253 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3254 GUEST_INTR_STATE_STI |
3255 GUEST_INTR_STATE_MOV_SS);
3256
3b86cd99
JK		 3257 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3258 if (vcpu->arch.interrupt.pending) {
3259 enable_nmi_window(vcpu);
3260 } else if (vcpu->arch.nmi_window_open) {
3261 vcpu->arch.nmi_pending = false;
3262 vcpu->arch.nmi_injected = true;
3263 } else {
3264 enable_nmi_window(vcpu);
f08864b4
SY		 3265 return;
3266 }
f08864b4 3267 }
3b86cd99
JK		 3268 if (vcpu->arch.nmi_injected) {
3269 vmx_inject_nmi(vcpu);
3270 if (vcpu->arch.nmi_pending)
3271 enable_nmi_window(vcpu);
3272 else if (kvm_cpu_has_interrupt(vcpu))
3273 enable_irq_window(vcpu);
3274 return;
3275 }
f7d9238f 3276 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
33f089ca 3277 if (vcpu->arch.interrupt_window_open)
f7d9238f
AK		 3278 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3279 else
3280 enable_irq_window(vcpu);
3281 }
3282 if (vcpu->arch.interrupt.pending) {
3283 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
df203ec9
AK		 3284 if (kvm_cpu_has_interrupt(vcpu))
3285 enable_irq_window(vcpu);
f7d9238f 3286 }
85f455f7
ED		 3287}
3288
9c8cba37
AK		 3289/*
3290 * Failure to inject an interrupt should give us the information
3291 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3292 * when fetching the interrupt redirection bitmap in the real-mode
3293 * tss, this doesn't happen. So we do it ourselves.
3294 */
3295static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3296{
3297 vmx->rmode.irq.pending = 0;
5fdbf976 3298 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3299 return;
5fdbf976 3300 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3301 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3302 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3303 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3304 return;
3305 }
3306 vmx->idt_vectoring_info =
3307 VECTORING_INFO_VALID_MASK
3308 | INTR_TYPE_EXT_INTR
3309 | vmx->rmode.irq.vector;
3310}
3311
c801949d
AK		 3312#ifdef CONFIG_X86_64
3313#define R "r"
3314#define Q "q"
3315#else
3316#define R "e"
3317#define Q "l"
3318#endif
3319
04d2cc77 3320static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 3321{
a2fa3e9f 3322 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 3323 u32 intr_info;
e6adf283 3324
3b86cd99
JK		 3325 /* Record the guest's net vcpu time for enforced NMI injections. */
3326 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3327 vmx->entry_time = ktime_get();
3328
a89a8fb9
MG		 3329 /* Handle invalid guest state instead of entering VMX */
3330 if (vmx->emulation_required && emulate_invalid_guest_state) {
3331 handle_invalid_guest_state(vcpu, kvm_run);
3332 return;
3333 }
3334
5fdbf976
MT		 3335 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3336 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3337 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3338 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3339
e6adf283
AK		 3340 /*
3341 * Loading guest fpu may have cleared host cr0.ts
3342 */
3343 vmcs_writel(HOST_CR0, read_cr0());
3344
d77c26fc 3345 asm(
6aa8b732 3346 /* Store host registers */
c801949d
AK		 3347 "push %%"R"dx; push %%"R"bp;"
3348 "push %%"R"cx \n\t"
313dbd49
AK		 3349 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3350 "je 1f \n\t"
3351 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3352 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3353 "1: \n\t"
6aa8b732 3354 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3355 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3356 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3357 "mov %c[cr2](%0), %%"R"ax \n\t"
3358 "mov %%"R"ax, %%cr2 \n\t"
3359 "mov %c[rax](%0), %%"R"ax \n\t"
3360 "mov %c[rbx](%0), %%"R"bx \n\t"
3361 "mov %c[rdx](%0), %%"R"dx \n\t"
3362 "mov %c[rsi](%0), %%"R"si \n\t"
3363 "mov %c[rdi](%0), %%"R"di \n\t"
3364 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3365#ifdef CONFIG_X86_64
e08aa78a
AK		 3366 "mov %c[r8](%0), %%r8 \n\t"
3367 "mov %c[r9](%0), %%r9 \n\t"
3368 "mov %c[r10](%0), %%r10 \n\t"
3369 "mov %c[r11](%0), %%r11 \n\t"
3370 "mov %c[r12](%0), %%r12 \n\t"
3371 "mov %c[r13](%0), %%r13 \n\t"
3372 "mov %c[r14](%0), %%r14 \n\t"
3373 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3374#endif
c801949d
AK		 3375 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3376
6aa8b732 3377 /* Enter guest mode */
cd2276a7 3378 "jne .Llaunched \n\t"
4ecac3fd 3379 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3380 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3381 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3382 ".Lkvm_vmx_return: "
6aa8b732 3383 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3384 "xchg %0, (%%"R"sp) \n\t"
3385 "mov %%"R"ax, %c[rax](%0) \n\t"
3386 "mov %%"R"bx, %c[rbx](%0) \n\t"
3387 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3388 "mov %%"R"dx, %c[rdx](%0) \n\t"
3389 "mov %%"R"si, %c[rsi](%0) \n\t"
3390 "mov %%"R"di, %c[rdi](%0) \n\t"
3391 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3392#ifdef CONFIG_X86_64
e08aa78a
AK		 3393 "mov %%r8, %c[r8](%0) \n\t"
3394 "mov %%r9, %c[r9](%0) \n\t"
3395 "mov %%r10, %c[r10](%0) \n\t"
3396 "mov %%r11, %c[r11](%0) \n\t"
3397 "mov %%r12, %c[r12](%0) \n\t"
3398 "mov %%r13, %c[r13](%0) \n\t"
3399 "mov %%r14, %c[r14](%0) \n\t"
3400 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3401#endif
c801949d
AK		 3402 "mov %%cr2, %%"R"ax \n\t"
3403 "mov %%"R"ax, %c[cr2](%0) \n\t"
3404
3405 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3406 "setbe %c[fail](%0) \n\t"
3407 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3408 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3409 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3410 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3411 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3412 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3413 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3414 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3415 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3416 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3417 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3418#ifdef CONFIG_X86_64
ad312c7c
ZX		 3419 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3420 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3421 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3422 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3423 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3424 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3425 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3426 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3427#endif
ad312c7c 3428 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3429 : "cc", "memory"
c801949d 3430 , R"bx", R"di", R"si"
c2036300 3431#ifdef CONFIG_X86_64
c2036300
LV		 3432 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3433#endif
3434 );
6aa8b732 3435
5fdbf976
MT		 3436 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3437 vcpu->arch.regs_dirty = 0;
3438
1155f76a 3439 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3440 if (vmx->rmode.irq.pending)
3441 fixup_rmode_irq(vmx);
1155f76a 3442
33f089ca 3443 vmx_update_window_states(vcpu);
6aa8b732 3444
d77c26fc 3445 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3446 vmx->launched = 1;
1b6269db
AK		 3447
3448 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3449
3450 /* We need to handle NMIs before interrupts are enabled */
e4a41889 3451 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
f08864b4 3452 (intr_info & INTR_INFO_VALID_MASK)) {
2714d1d3 3453 KVMTRACE_0D(NMI, vcpu, handler);
1b6269db 3454 asm("int $2");
2714d1d3 3455 }
cf393f75
AK		 3456
3457 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3458}
3459
c801949d
AK		 3460#undef R
3461#undef Q
3462
6aa8b732
AK		 3463static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3464{
a2fa3e9f
GH		 3465 struct vcpu_vmx *vmx = to_vmx(vcpu);
3466
3467 if (vmx->vmcs) {
543e4243 3468 vcpu_clear(vmx);
a2fa3e9f
GH		 3469 free_vmcs(vmx->vmcs);
3470 vmx->vmcs = NULL;
6aa8b732
AK		 3471 }
3472}
3473
3474static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3475{
fb3f0f51
RR		 3476 struct vcpu_vmx *vmx = to_vmx(vcpu);
3477
2384d2b3
SY		 3478 spin_lock(&vmx_vpid_lock);
3479 if (vmx->vpid != 0)
3480 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3481 spin_unlock(&vmx_vpid_lock);
6aa8b732 3482 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3483 kfree(vmx->host_msrs);
3484 kfree(vmx->guest_msrs);
3485 kvm_vcpu_uninit(vcpu);
a4770347 3486 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3487}
3488
fb3f0f51 3489static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3490{
fb3f0f51 3491 int err;
c16f862d 3492 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3493 int cpu;
6aa8b732 3494
a2fa3e9f 3495 if (!vmx)
fb3f0f51
RR		 3496 return ERR_PTR(-ENOMEM);
3497
2384d2b3
SY		 3498 allocate_vpid(vmx);
3499
fb3f0f51
RR		 3500 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3501 if (err)
3502 goto free_vcpu;
965b58a5 3503
a2fa3e9f 3504 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3505 if (!vmx->guest_msrs) {
3506 err = -ENOMEM;
3507 goto uninit_vcpu;
3508 }
965b58a5 3509
a2fa3e9f
GH		 3510 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3511 if (!vmx->host_msrs)
fb3f0f51 3512 goto free_guest_msrs;
965b58a5 3513
a2fa3e9f
GH		 3514 vmx->vmcs = alloc_vmcs();
3515 if (!vmx->vmcs)
fb3f0f51 3516 goto free_msrs;
a2fa3e9f
GH		 3517
3518 vmcs_clear(vmx->vmcs);
3519
15ad7146
AK		 3520 cpu = get_cpu();
3521 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3522 err = vmx_vcpu_setup(vmx);
fb3f0f51 3523 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3524 put_cpu();
fb3f0f51
RR		 3525 if (err)
3526 goto free_vmcs;
5e4a0b3c
MT		 3527 if (vm_need_virtualize_apic_accesses(kvm))
3528 if (alloc_apic_access_page(kvm) != 0)
3529 goto free_vmcs;
fb3f0f51 3530
b7ebfb05
SY		 3531 if (vm_need_ept())
3532 if (alloc_identity_pagetable(kvm) != 0)
3533 goto free_vmcs;
3534
fb3f0f51
RR		 3535 return &vmx->vcpu;
3536
3537free_vmcs:
3538 free_vmcs(vmx->vmcs);
3539free_msrs:
3540 kfree(vmx->host_msrs);
3541free_guest_msrs:
3542 kfree(vmx->guest_msrs);
3543uninit_vcpu:
3544 kvm_vcpu_uninit(&vmx->vcpu);
3545free_vcpu:
a4770347 3546 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3547 return ERR_PTR(err);
6aa8b732
AK		 3548}
3549
002c7f7c
YS		 3550static void __init vmx_check_processor_compat(void *rtn)
3551{
3552 struct vmcs_config vmcs_conf;
3553
3554 *(int *)rtn = 0;
3555 if (setup_vmcs_config(&vmcs_conf) < 0)
3556 *(int *)rtn = -EIO;
3557 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3558 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3559 smp_processor_id());
3560 *(int *)rtn = -EIO;
3561 }
3562}
3563
67253af5
SY		 3564static int get_ept_level(void)
3565{
3566 return VMX_EPT_DEFAULT_GAW + 1;
3567}
3568
64d4d521
SY		 3569static int vmx_get_mt_mask_shift(void)
3570{
3571 return VMX_EPT_MT_EPTE_SHIFT;
3572}
3573
cbdd1bea 3574static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3575 .cpu_has_kvm_support = cpu_has_kvm_support,
3576 .disabled_by_bios = vmx_disabled_by_bios,
3577 .hardware_setup = hardware_setup,
3578 .hardware_unsetup = hardware_unsetup,
002c7f7c 3579 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3580 .hardware_enable = hardware_enable,
3581 .hardware_disable = hardware_disable,
774ead3a 3582 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
6aa8b732
AK		 3583
3584 .vcpu_create = vmx_create_vcpu,
3585 .vcpu_free = vmx_free_vcpu,
04d2cc77 3586 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3587
04d2cc77 3588 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3589 .vcpu_load = vmx_vcpu_load,
3590 .vcpu_put = vmx_vcpu_put,
3591
3592 .set_guest_debug = set_guest_debug,
3593 .get_msr = vmx_get_msr,
3594 .set_msr = vmx_set_msr,
3595 .get_segment_base = vmx_get_segment_base,
3596 .get_segment = vmx_get_segment,
3597 .set_segment = vmx_set_segment,
2e4d2653 3598 .get_cpl = vmx_get_cpl,
6aa8b732 3599 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3600 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3601 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3602 .set_cr3 = vmx_set_cr3,
3603 .set_cr4 = vmx_set_cr4,
6aa8b732 3604 .set_efer = vmx_set_efer,
6aa8b732
AK		 3605 .get_idt = vmx_get_idt,
3606 .set_idt = vmx_set_idt,
3607 .get_gdt = vmx_get_gdt,
3608 .set_gdt = vmx_set_gdt,
5fdbf976 3609 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 3610 .get_rflags = vmx_get_rflags,
3611 .set_rflags = vmx_set_rflags,
3612
3613 .tlb_flush = vmx_flush_tlb,
6aa8b732 3614
6aa8b732 3615 .run = vmx_vcpu_run,
04d2cc77 3616 .handle_exit = kvm_handle_exit,
6aa8b732 3617 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 3618 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 3619 .get_irq = vmx_get_irq,
3620 .set_irq = vmx_inject_irq,
298101da
AK		 3621 .queue_exception = vmx_queue_exception,
3622 .exception_injected = vmx_exception_injected,
04d2cc77
AK		 3623 .inject_pending_irq = vmx_intr_assist,
3624 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 3625
3626 .set_tss_addr = vmx_set_tss_addr,
67253af5 3627 .get_tdp_level = get_ept_level,
64d4d521 3628 .get_mt_mask_shift = vmx_get_mt_mask_shift,
6aa8b732
AK		 3629};
3630
3631static int __init vmx_init(void)
3632{
25c5f225 3633 void *va;
fdef3ad1
HQ		 3634 int r;
3635
3636 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3637 if (!vmx_io_bitmap_a)
3638 return -ENOMEM;
3639
3640 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3641 if (!vmx_io_bitmap_b) {
3642 r = -ENOMEM;
3643 goto out;
3644 }
3645
25c5f225
SY		 3646 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3647 if (!vmx_msr_bitmap) {
3648 r = -ENOMEM;
3649 goto out1;
3650 }
3651
fdef3ad1
HQ		 3652 /*
3653 * Allow direct access to the PC debug port (it is often used for I/O
3654 * delays, but the vmexits simply slow things down).
3655 */
25c5f225
SY		 3656 va = kmap(vmx_io_bitmap_a);
3657 memset(va, 0xff, PAGE_SIZE);
3658 clear_bit(0x80, va);
cd0536d7 3659 kunmap(vmx_io_bitmap_a);
fdef3ad1 3660
25c5f225
SY		 3661 va = kmap(vmx_io_bitmap_b);
3662 memset(va, 0xff, PAGE_SIZE);
cd0536d7 3663 kunmap(vmx_io_bitmap_b);
fdef3ad1 3664
25c5f225
SY		 3665 va = kmap(vmx_msr_bitmap);
3666 memset(va, 0xff, PAGE_SIZE);
3667 kunmap(vmx_msr_bitmap);
3668
2384d2b3
SY		 3669 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3670
cb498ea2 3671 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 3672 if (r)
25c5f225
SY		 3673 goto out2;
3674
3675 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3676 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3677 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3678 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3679 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
fdef3ad1 3680
5fdbcb9d 3681 if (vm_need_ept()) {
1439442c 3682 bypass_guest_pf = 0;
5fdbcb9d 3683 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 3684 VMX_EPT_WRITABLE_MASK);
534e38b4 3685 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
64d4d521
SY		 3686 VMX_EPT_EXECUTABLE_MASK,
3687 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
5fdbcb9d
SY		 3688 kvm_enable_tdp();
3689 } else
3690 kvm_disable_tdp();
1439442c 3691
c7addb90
AK		 3692 if (bypass_guest_pf)
3693 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3694
1439442c
SY		 3695 ept_sync_global();
3696
fdef3ad1
HQ		 3697 return 0;
3698
25c5f225
SY		 3699out2:
3700 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3701out1:
3702 __free_page(vmx_io_bitmap_b);
3703out:
3704 __free_page(vmx_io_bitmap_a);
3705 return r;
6aa8b732
AK		 3706}
3707
3708static void __exit vmx_exit(void)
3709{
25c5f225 3710 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3711 __free_page(vmx_io_bitmap_b);
3712 __free_page(vmx_io_bitmap_a);
3713
cb498ea2 3714 kvm_exit();
6aa8b732
AK		 3715}
3716
3717module_init(vmx_init)
3718module_exit(vmx_exit)
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