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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
8 | * | |
9 | * Authors: | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
17 | ||
85f455f7 | 18 | #include "irq.h" |
6aa8b732 | 19 | #include "vmx.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
edf88417 | 22 | #include <linux/kvm_host.h> |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/mm.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
c7addb90 | 28 | #include <linux/moduleparam.h> |
e495606d | 29 | |
6aa8b732 | 30 | #include <asm/io.h> |
3b3be0d1 | 31 | #include <asm/desc.h> |
6aa8b732 | 32 | |
4ecac3fd AK |
33 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
34 | ||
6aa8b732 AK |
35 | MODULE_AUTHOR("Qumranet"); |
36 | MODULE_LICENSE("GPL"); | |
37 | ||
c7addb90 AK |
38 | static int bypass_guest_pf = 1; |
39 | module_param(bypass_guest_pf, bool, 0); | |
40 | ||
2384d2b3 SY |
41 | static int enable_vpid = 1; |
42 | module_param(enable_vpid, bool, 0); | |
43 | ||
4c9fc8ef AK |
44 | static int flexpriority_enabled = 1; |
45 | module_param(flexpriority_enabled, bool, 0); | |
46 | ||
1439442c | 47 | static int enable_ept = 1; |
d56f546d SY |
48 | module_param(enable_ept, bool, 0); |
49 | ||
a2fa3e9f GH |
50 | struct vmcs { |
51 | u32 revision_id; | |
52 | u32 abort; | |
53 | char data[0]; | |
54 | }; | |
55 | ||
56 | struct vcpu_vmx { | |
fb3f0f51 | 57 | struct kvm_vcpu vcpu; |
543e4243 | 58 | struct list_head local_vcpus_link; |
a2fa3e9f | 59 | int launched; |
29bd8a78 | 60 | u8 fail; |
1155f76a | 61 | u32 idt_vectoring_info; |
a2fa3e9f GH |
62 | struct kvm_msr_entry *guest_msrs; |
63 | struct kvm_msr_entry *host_msrs; | |
64 | int nmsrs; | |
65 | int save_nmsrs; | |
66 | int msr_offset_efer; | |
67 | #ifdef CONFIG_X86_64 | |
68 | int msr_offset_kernel_gs_base; | |
69 | #endif | |
70 | struct vmcs *vmcs; | |
71 | struct { | |
72 | int loaded; | |
73 | u16 fs_sel, gs_sel, ldt_sel; | |
152d3f2f LV |
74 | int gs_ldt_reload_needed; |
75 | int fs_reload_needed; | |
51c6cf66 | 76 | int guest_efer_loaded; |
d77c26fc | 77 | } host_state; |
9c8cba37 AK |
78 | struct { |
79 | struct { | |
80 | bool pending; | |
81 | u8 vector; | |
82 | unsigned rip; | |
83 | } irq; | |
84 | } rmode; | |
2384d2b3 | 85 | int vpid; |
a2fa3e9f GH |
86 | }; |
87 | ||
88 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) | |
89 | { | |
fb3f0f51 | 90 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
91 | } |
92 | ||
b7ebfb05 | 93 | static int init_rmode(struct kvm *kvm); |
4e1096d2 | 94 | static u64 construct_eptp(unsigned long root_hpa); |
75880a01 | 95 | |
6aa8b732 AK |
96 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
97 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
543e4243 | 98 | static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu); |
6aa8b732 | 99 | |
fdef3ad1 HQ |
100 | static struct page *vmx_io_bitmap_a; |
101 | static struct page *vmx_io_bitmap_b; | |
25c5f225 | 102 | static struct page *vmx_msr_bitmap; |
fdef3ad1 | 103 | |
2384d2b3 SY |
104 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
105 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
106 | ||
1c3d14fe | 107 | static struct vmcs_config { |
6aa8b732 AK |
108 | int size; |
109 | int order; | |
110 | u32 revision_id; | |
1c3d14fe YS |
111 | u32 pin_based_exec_ctrl; |
112 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 113 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
114 | u32 vmexit_ctrl; |
115 | u32 vmentry_ctrl; | |
116 | } vmcs_config; | |
6aa8b732 | 117 | |
d56f546d SY |
118 | struct vmx_capability { |
119 | u32 ept; | |
120 | u32 vpid; | |
121 | } vmx_capability; | |
122 | ||
6aa8b732 AK |
123 | #define VMX_SEGMENT_FIELD(seg) \ |
124 | [VCPU_SREG_##seg] = { \ | |
125 | .selector = GUEST_##seg##_SELECTOR, \ | |
126 | .base = GUEST_##seg##_BASE, \ | |
127 | .limit = GUEST_##seg##_LIMIT, \ | |
128 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
129 | } | |
130 | ||
131 | static struct kvm_vmx_segment_field { | |
132 | unsigned selector; | |
133 | unsigned base; | |
134 | unsigned limit; | |
135 | unsigned ar_bytes; | |
136 | } kvm_vmx_segment_fields[] = { | |
137 | VMX_SEGMENT_FIELD(CS), | |
138 | VMX_SEGMENT_FIELD(DS), | |
139 | VMX_SEGMENT_FIELD(ES), | |
140 | VMX_SEGMENT_FIELD(FS), | |
141 | VMX_SEGMENT_FIELD(GS), | |
142 | VMX_SEGMENT_FIELD(SS), | |
143 | VMX_SEGMENT_FIELD(TR), | |
144 | VMX_SEGMENT_FIELD(LDTR), | |
145 | }; | |
146 | ||
4d56c8a7 AK |
147 | /* |
148 | * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it | |
149 | * away by decrementing the array size. | |
150 | */ | |
6aa8b732 | 151 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 152 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
153 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE, |
154 | #endif | |
155 | MSR_EFER, MSR_K6_STAR, | |
156 | }; | |
9d8f549d | 157 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 158 | |
a2fa3e9f GH |
159 | static void load_msrs(struct kvm_msr_entry *e, int n) |
160 | { | |
161 | int i; | |
162 | ||
163 | for (i = 0; i < n; ++i) | |
164 | wrmsrl(e[i].index, e[i].data); | |
165 | } | |
166 | ||
167 | static void save_msrs(struct kvm_msr_entry *e, int n) | |
168 | { | |
169 | int i; | |
170 | ||
171 | for (i = 0; i < n; ++i) | |
172 | rdmsrl(e[i].index, e[i].data); | |
173 | } | |
174 | ||
6aa8b732 AK |
175 | static inline int is_page_fault(u32 intr_info) |
176 | { | |
177 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
178 | INTR_INFO_VALID_MASK)) == | |
179 | (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); | |
180 | } | |
181 | ||
2ab455cc AL |
182 | static inline int is_no_device(u32 intr_info) |
183 | { | |
184 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
185 | INTR_INFO_VALID_MASK)) == | |
186 | (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); | |
187 | } | |
188 | ||
7aa81cc0 AL |
189 | static inline int is_invalid_opcode(u32 intr_info) |
190 | { | |
191 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
192 | INTR_INFO_VALID_MASK)) == | |
193 | (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); | |
194 | } | |
195 | ||
6aa8b732 AK |
196 | static inline int is_external_interrupt(u32 intr_info) |
197 | { | |
198 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
199 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
200 | } | |
201 | ||
25c5f225 SY |
202 | static inline int cpu_has_vmx_msr_bitmap(void) |
203 | { | |
204 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS); | |
205 | } | |
206 | ||
6e5d865c YS |
207 | static inline int cpu_has_vmx_tpr_shadow(void) |
208 | { | |
209 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW); | |
210 | } | |
211 | ||
212 | static inline int vm_need_tpr_shadow(struct kvm *kvm) | |
213 | { | |
214 | return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm))); | |
215 | } | |
216 | ||
f78e0e2e SY |
217 | static inline int cpu_has_secondary_exec_ctrls(void) |
218 | { | |
219 | return (vmcs_config.cpu_based_exec_ctrl & | |
220 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); | |
221 | } | |
222 | ||
774ead3a | 223 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 224 | { |
4c9fc8ef AK |
225 | return flexpriority_enabled |
226 | && (vmcs_config.cpu_based_2nd_exec_ctrl & | |
227 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
f78e0e2e SY |
228 | } |
229 | ||
d56f546d SY |
230 | static inline int cpu_has_vmx_invept_individual_addr(void) |
231 | { | |
232 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT)); | |
233 | } | |
234 | ||
235 | static inline int cpu_has_vmx_invept_context(void) | |
236 | { | |
237 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT)); | |
238 | } | |
239 | ||
240 | static inline int cpu_has_vmx_invept_global(void) | |
241 | { | |
242 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT)); | |
243 | } | |
244 | ||
245 | static inline int cpu_has_vmx_ept(void) | |
246 | { | |
247 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
248 | SECONDARY_EXEC_ENABLE_EPT); | |
249 | } | |
250 | ||
251 | static inline int vm_need_ept(void) | |
252 | { | |
253 | return (cpu_has_vmx_ept() && enable_ept); | |
254 | } | |
255 | ||
f78e0e2e SY |
256 | static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm) |
257 | { | |
258 | return ((cpu_has_vmx_virtualize_apic_accesses()) && | |
259 | (irqchip_in_kernel(kvm))); | |
260 | } | |
261 | ||
2384d2b3 SY |
262 | static inline int cpu_has_vmx_vpid(void) |
263 | { | |
264 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
265 | SECONDARY_EXEC_ENABLE_VPID); | |
266 | } | |
267 | ||
f08864b4 SY |
268 | static inline int cpu_has_virtual_nmis(void) |
269 | { | |
270 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
271 | } | |
272 | ||
8b9cf98c | 273 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
274 | { |
275 | int i; | |
276 | ||
a2fa3e9f GH |
277 | for (i = 0; i < vmx->nmsrs; ++i) |
278 | if (vmx->guest_msrs[i].index == msr) | |
a75beee6 ED |
279 | return i; |
280 | return -1; | |
281 | } | |
282 | ||
2384d2b3 SY |
283 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
284 | { | |
285 | struct { | |
286 | u64 vpid : 16; | |
287 | u64 rsvd : 48; | |
288 | u64 gva; | |
289 | } operand = { vpid, 0, gva }; | |
290 | ||
4ecac3fd | 291 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
292 | /* CF==1 or ZF==1 --> rc = -1 */ |
293 | "; ja 1f ; ud2 ; 1:" | |
294 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
295 | } | |
296 | ||
1439442c SY |
297 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
298 | { | |
299 | struct { | |
300 | u64 eptp, gpa; | |
301 | } operand = {eptp, gpa}; | |
302 | ||
4ecac3fd | 303 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
304 | /* CF==1 or ZF==1 --> rc = -1 */ |
305 | "; ja 1f ; ud2 ; 1:\n" | |
306 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
307 | } | |
308 | ||
8b9cf98c | 309 | static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
310 | { |
311 | int i; | |
312 | ||
8b9cf98c | 313 | i = __find_msr_index(vmx, msr); |
a75beee6 | 314 | if (i >= 0) |
a2fa3e9f | 315 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 316 | return NULL; |
7725f0ba AK |
317 | } |
318 | ||
6aa8b732 AK |
319 | static void vmcs_clear(struct vmcs *vmcs) |
320 | { | |
321 | u64 phys_addr = __pa(vmcs); | |
322 | u8 error; | |
323 | ||
4ecac3fd | 324 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
6aa8b732 AK |
325 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) |
326 | : "cc", "memory"); | |
327 | if (error) | |
328 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
329 | vmcs, phys_addr); | |
330 | } | |
331 | ||
332 | static void __vcpu_clear(void *arg) | |
333 | { | |
8b9cf98c | 334 | struct vcpu_vmx *vmx = arg; |
d3b2c338 | 335 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 336 | |
8b9cf98c | 337 | if (vmx->vcpu.cpu == cpu) |
a2fa3e9f GH |
338 | vmcs_clear(vmx->vmcs); |
339 | if (per_cpu(current_vmcs, cpu) == vmx->vmcs) | |
6aa8b732 | 340 | per_cpu(current_vmcs, cpu) = NULL; |
ad312c7c | 341 | rdtscll(vmx->vcpu.arch.host_tsc); |
543e4243 AK |
342 | list_del(&vmx->local_vcpus_link); |
343 | vmx->vcpu.cpu = -1; | |
344 | vmx->launched = 0; | |
6aa8b732 AK |
345 | } |
346 | ||
8b9cf98c | 347 | static void vcpu_clear(struct vcpu_vmx *vmx) |
8d0be2b3 | 348 | { |
eae5ecb5 AK |
349 | if (vmx->vcpu.cpu == -1) |
350 | return; | |
8691e5a8 | 351 | smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1); |
8d0be2b3 AK |
352 | } |
353 | ||
2384d2b3 SY |
354 | static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx) |
355 | { | |
356 | if (vmx->vpid == 0) | |
357 | return; | |
358 | ||
359 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); | |
360 | } | |
361 | ||
1439442c SY |
362 | static inline void ept_sync_global(void) |
363 | { | |
364 | if (cpu_has_vmx_invept_global()) | |
365 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
366 | } | |
367 | ||
368 | static inline void ept_sync_context(u64 eptp) | |
369 | { | |
370 | if (vm_need_ept()) { | |
371 | if (cpu_has_vmx_invept_context()) | |
372 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
373 | else | |
374 | ept_sync_global(); | |
375 | } | |
376 | } | |
377 | ||
378 | static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa) | |
379 | { | |
380 | if (vm_need_ept()) { | |
381 | if (cpu_has_vmx_invept_individual_addr()) | |
382 | __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR, | |
383 | eptp, gpa); | |
384 | else | |
385 | ept_sync_context(eptp); | |
386 | } | |
387 | } | |
388 | ||
6aa8b732 AK |
389 | static unsigned long vmcs_readl(unsigned long field) |
390 | { | |
391 | unsigned long value; | |
392 | ||
4ecac3fd | 393 | asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX) |
6aa8b732 AK |
394 | : "=a"(value) : "d"(field) : "cc"); |
395 | return value; | |
396 | } | |
397 | ||
398 | static u16 vmcs_read16(unsigned long field) | |
399 | { | |
400 | return vmcs_readl(field); | |
401 | } | |
402 | ||
403 | static u32 vmcs_read32(unsigned long field) | |
404 | { | |
405 | return vmcs_readl(field); | |
406 | } | |
407 | ||
408 | static u64 vmcs_read64(unsigned long field) | |
409 | { | |
05b3e0c2 | 410 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
411 | return vmcs_readl(field); |
412 | #else | |
413 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
414 | #endif | |
415 | } | |
416 | ||
e52de1b8 AK |
417 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
418 | { | |
419 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
420 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
421 | dump_stack(); | |
422 | } | |
423 | ||
6aa8b732 AK |
424 | static void vmcs_writel(unsigned long field, unsigned long value) |
425 | { | |
426 | u8 error; | |
427 | ||
4ecac3fd | 428 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 429 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
430 | if (unlikely(error)) |
431 | vmwrite_error(field, value); | |
6aa8b732 AK |
432 | } |
433 | ||
434 | static void vmcs_write16(unsigned long field, u16 value) | |
435 | { | |
436 | vmcs_writel(field, value); | |
437 | } | |
438 | ||
439 | static void vmcs_write32(unsigned long field, u32 value) | |
440 | { | |
441 | vmcs_writel(field, value); | |
442 | } | |
443 | ||
444 | static void vmcs_write64(unsigned long field, u64 value) | |
445 | { | |
6aa8b732 | 446 | vmcs_writel(field, value); |
7682f2d0 | 447 | #ifndef CONFIG_X86_64 |
6aa8b732 AK |
448 | asm volatile (""); |
449 | vmcs_writel(field+1, value >> 32); | |
450 | #endif | |
451 | } | |
452 | ||
2ab455cc AL |
453 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
454 | { | |
455 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
456 | } | |
457 | ||
458 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
459 | { | |
460 | vmcs_writel(field, vmcs_readl(field) | mask); | |
461 | } | |
462 | ||
abd3f2d6 AK |
463 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
464 | { | |
465 | u32 eb; | |
466 | ||
7aa81cc0 | 467 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR); |
abd3f2d6 AK |
468 | if (!vcpu->fpu_active) |
469 | eb |= 1u << NM_VECTOR; | |
470 | if (vcpu->guest_debug.enabled) | |
471 | eb |= 1u << 1; | |
ad312c7c | 472 | if (vcpu->arch.rmode.active) |
abd3f2d6 | 473 | eb = ~0; |
1439442c SY |
474 | if (vm_need_ept()) |
475 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ | |
abd3f2d6 AK |
476 | vmcs_write32(EXCEPTION_BITMAP, eb); |
477 | } | |
478 | ||
33ed6329 AK |
479 | static void reload_tss(void) |
480 | { | |
33ed6329 AK |
481 | /* |
482 | * VT restores TR but not its size. Useless. | |
483 | */ | |
484 | struct descriptor_table gdt; | |
a5f61300 | 485 | struct desc_struct *descs; |
33ed6329 | 486 | |
d6e88aec | 487 | kvm_get_gdt(&gdt); |
33ed6329 AK |
488 | descs = (void *)gdt.base; |
489 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ | |
490 | load_TR_desc(); | |
33ed6329 AK |
491 | } |
492 | ||
8b9cf98c | 493 | static void load_transition_efer(struct vcpu_vmx *vmx) |
2cc51560 | 494 | { |
a2fa3e9f | 495 | int efer_offset = vmx->msr_offset_efer; |
51c6cf66 AK |
496 | u64 host_efer = vmx->host_msrs[efer_offset].data; |
497 | u64 guest_efer = vmx->guest_msrs[efer_offset].data; | |
498 | u64 ignore_bits; | |
499 | ||
500 | if (efer_offset < 0) | |
501 | return; | |
502 | /* | |
503 | * NX is emulated; LMA and LME handled by hardware; SCE meaninless | |
504 | * outside long mode | |
505 | */ | |
506 | ignore_bits = EFER_NX | EFER_SCE; | |
507 | #ifdef CONFIG_X86_64 | |
508 | ignore_bits |= EFER_LMA | EFER_LME; | |
509 | /* SCE is meaningful only in long mode on Intel */ | |
510 | if (guest_efer & EFER_LMA) | |
511 | ignore_bits &= ~(u64)EFER_SCE; | |
512 | #endif | |
513 | if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits)) | |
514 | return; | |
2cc51560 | 515 | |
51c6cf66 AK |
516 | vmx->host_state.guest_efer_loaded = 1; |
517 | guest_efer &= ~ignore_bits; | |
518 | guest_efer |= host_efer & ignore_bits; | |
519 | wrmsrl(MSR_EFER, guest_efer); | |
8b9cf98c | 520 | vmx->vcpu.stat.efer_reload++; |
2cc51560 ED |
521 | } |
522 | ||
51c6cf66 AK |
523 | static void reload_host_efer(struct vcpu_vmx *vmx) |
524 | { | |
525 | if (vmx->host_state.guest_efer_loaded) { | |
526 | vmx->host_state.guest_efer_loaded = 0; | |
527 | load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1); | |
528 | } | |
529 | } | |
530 | ||
04d2cc77 | 531 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 532 | { |
04d2cc77 AK |
533 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
534 | ||
a2fa3e9f | 535 | if (vmx->host_state.loaded) |
33ed6329 AK |
536 | return; |
537 | ||
a2fa3e9f | 538 | vmx->host_state.loaded = 1; |
33ed6329 AK |
539 | /* |
540 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
541 | * allow segment selectors with cpl > 0 or ti == 1. | |
542 | */ | |
d6e88aec | 543 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 544 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
d6e88aec | 545 | vmx->host_state.fs_sel = kvm_read_fs(); |
152d3f2f | 546 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 547 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
548 | vmx->host_state.fs_reload_needed = 0; |
549 | } else { | |
33ed6329 | 550 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 551 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 552 | } |
d6e88aec | 553 | vmx->host_state.gs_sel = kvm_read_gs(); |
a2fa3e9f GH |
554 | if (!(vmx->host_state.gs_sel & 7)) |
555 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
556 | else { |
557 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 558 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
559 | } |
560 | ||
561 | #ifdef CONFIG_X86_64 | |
562 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
563 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
564 | #else | |
a2fa3e9f GH |
565 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
566 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 567 | #endif |
707c0874 AK |
568 | |
569 | #ifdef CONFIG_X86_64 | |
d77c26fc | 570 | if (is_long_mode(&vmx->vcpu)) |
a2fa3e9f GH |
571 | save_msrs(vmx->host_msrs + |
572 | vmx->msr_offset_kernel_gs_base, 1); | |
d77c26fc | 573 | |
707c0874 | 574 | #endif |
a2fa3e9f | 575 | load_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
51c6cf66 | 576 | load_transition_efer(vmx); |
33ed6329 AK |
577 | } |
578 | ||
a9b21b62 | 579 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 580 | { |
15ad7146 | 581 | unsigned long flags; |
33ed6329 | 582 | |
a2fa3e9f | 583 | if (!vmx->host_state.loaded) |
33ed6329 AK |
584 | return; |
585 | ||
e1beb1d3 | 586 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 587 | vmx->host_state.loaded = 0; |
152d3f2f | 588 | if (vmx->host_state.fs_reload_needed) |
d6e88aec | 589 | kvm_load_fs(vmx->host_state.fs_sel); |
152d3f2f | 590 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 591 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 AK |
592 | /* |
593 | * If we have to reload gs, we must take care to | |
594 | * preserve our gs base. | |
595 | */ | |
15ad7146 | 596 | local_irq_save(flags); |
d6e88aec | 597 | kvm_load_gs(vmx->host_state.gs_sel); |
33ed6329 AK |
598 | #ifdef CONFIG_X86_64 |
599 | wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE)); | |
600 | #endif | |
15ad7146 | 601 | local_irq_restore(flags); |
33ed6329 | 602 | } |
152d3f2f | 603 | reload_tss(); |
a2fa3e9f GH |
604 | save_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
605 | load_msrs(vmx->host_msrs, vmx->save_nmsrs); | |
51c6cf66 | 606 | reload_host_efer(vmx); |
33ed6329 AK |
607 | } |
608 | ||
a9b21b62 AK |
609 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
610 | { | |
611 | preempt_disable(); | |
612 | __vmx_load_host_state(vmx); | |
613 | preempt_enable(); | |
614 | } | |
615 | ||
6aa8b732 AK |
616 | /* |
617 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
618 | * vcpu mutex is already taken. | |
619 | */ | |
15ad7146 | 620 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 621 | { |
a2fa3e9f GH |
622 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
623 | u64 phys_addr = __pa(vmx->vmcs); | |
019960ae | 624 | u64 tsc_this, delta, new_offset; |
6aa8b732 | 625 | |
a3d7f85f | 626 | if (vcpu->cpu != cpu) { |
8b9cf98c | 627 | vcpu_clear(vmx); |
2f599714 | 628 | kvm_migrate_timers(vcpu); |
2384d2b3 | 629 | vpid_sync_vcpu_all(vmx); |
543e4243 AK |
630 | local_irq_disable(); |
631 | list_add(&vmx->local_vcpus_link, | |
632 | &per_cpu(vcpus_on_cpu, cpu)); | |
633 | local_irq_enable(); | |
a3d7f85f | 634 | } |
6aa8b732 | 635 | |
a2fa3e9f | 636 | if (per_cpu(current_vmcs, cpu) != vmx->vmcs) { |
6aa8b732 AK |
637 | u8 error; |
638 | ||
a2fa3e9f | 639 | per_cpu(current_vmcs, cpu) = vmx->vmcs; |
4ecac3fd | 640 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" |
6aa8b732 AK |
641 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) |
642 | : "cc"); | |
643 | if (error) | |
644 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
a2fa3e9f | 645 | vmx->vmcs, phys_addr); |
6aa8b732 AK |
646 | } |
647 | ||
648 | if (vcpu->cpu != cpu) { | |
649 | struct descriptor_table dt; | |
650 | unsigned long sysenter_esp; | |
651 | ||
652 | vcpu->cpu = cpu; | |
653 | /* | |
654 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
655 | * processors. | |
656 | */ | |
d6e88aec AK |
657 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
658 | kvm_get_gdt(&dt); | |
6aa8b732 AK |
659 | vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */ |
660 | ||
661 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
662 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
7700270e AK |
663 | |
664 | /* | |
665 | * Make sure the time stamp counter is monotonous. | |
666 | */ | |
667 | rdtscll(tsc_this); | |
019960ae AK |
668 | if (tsc_this < vcpu->arch.host_tsc) { |
669 | delta = vcpu->arch.host_tsc - tsc_this; | |
670 | new_offset = vmcs_read64(TSC_OFFSET) + delta; | |
671 | vmcs_write64(TSC_OFFSET, new_offset); | |
672 | } | |
6aa8b732 | 673 | } |
6aa8b732 AK |
674 | } |
675 | ||
676 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
677 | { | |
a9b21b62 | 678 | __vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
679 | } |
680 | ||
5fd86fcf AK |
681 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
682 | { | |
683 | if (vcpu->fpu_active) | |
684 | return; | |
685 | vcpu->fpu_active = 1; | |
707d92fa | 686 | vmcs_clear_bits(GUEST_CR0, X86_CR0_TS); |
ad312c7c | 687 | if (vcpu->arch.cr0 & X86_CR0_TS) |
707d92fa | 688 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
689 | update_exception_bitmap(vcpu); |
690 | } | |
691 | ||
692 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) | |
693 | { | |
694 | if (!vcpu->fpu_active) | |
695 | return; | |
696 | vcpu->fpu_active = 0; | |
707d92fa | 697 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
698 | update_exception_bitmap(vcpu); |
699 | } | |
700 | ||
6aa8b732 AK |
701 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
702 | { | |
703 | return vmcs_readl(GUEST_RFLAGS); | |
704 | } | |
705 | ||
706 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
707 | { | |
ad312c7c | 708 | if (vcpu->arch.rmode.active) |
053de044 | 709 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
710 | vmcs_writel(GUEST_RFLAGS, rflags); |
711 | } | |
712 | ||
713 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
714 | { | |
715 | unsigned long rip; | |
716 | u32 interruptibility; | |
717 | ||
718 | rip = vmcs_readl(GUEST_RIP); | |
719 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
720 | vmcs_writel(GUEST_RIP, rip); | |
721 | ||
722 | /* | |
723 | * We emulated an instruction, so temporary interrupt blocking | |
724 | * should be removed, if set. | |
725 | */ | |
726 | interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
727 | if (interruptibility & 3) | |
728 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
729 | interruptibility & ~3); | |
ad312c7c | 730 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
731 | } |
732 | ||
298101da AK |
733 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
734 | bool has_error_code, u32 error_code) | |
735 | { | |
736 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
737 | nr | INTR_TYPE_EXCEPTION | |
2e11384c | 738 | | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0) |
298101da AK |
739 | | INTR_INFO_VALID_MASK); |
740 | if (has_error_code) | |
741 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); | |
742 | } | |
743 | ||
744 | static bool vmx_exception_injected(struct kvm_vcpu *vcpu) | |
745 | { | |
746 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
747 | ||
748 | return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
749 | } | |
750 | ||
a75beee6 ED |
751 | /* |
752 | * Swap MSR entry in host/guest MSR entry array. | |
753 | */ | |
54e11fa1 | 754 | #ifdef CONFIG_X86_64 |
8b9cf98c | 755 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 756 | { |
a2fa3e9f GH |
757 | struct kvm_msr_entry tmp; |
758 | ||
759 | tmp = vmx->guest_msrs[to]; | |
760 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
761 | vmx->guest_msrs[from] = tmp; | |
762 | tmp = vmx->host_msrs[to]; | |
763 | vmx->host_msrs[to] = vmx->host_msrs[from]; | |
764 | vmx->host_msrs[from] = tmp; | |
a75beee6 | 765 | } |
54e11fa1 | 766 | #endif |
a75beee6 | 767 | |
e38aea3e AK |
768 | /* |
769 | * Set up the vmcs to automatically save and restore system | |
770 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
771 | * mode, as fiddling with msrs is very expensive. | |
772 | */ | |
8b9cf98c | 773 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 774 | { |
2cc51560 | 775 | int save_nmsrs; |
e38aea3e | 776 | |
33f9c505 | 777 | vmx_load_host_state(vmx); |
a75beee6 ED |
778 | save_nmsrs = 0; |
779 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 780 | if (is_long_mode(&vmx->vcpu)) { |
2cc51560 ED |
781 | int index; |
782 | ||
8b9cf98c | 783 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 784 | if (index >= 0) |
8b9cf98c RR |
785 | move_msr_up(vmx, index, save_nmsrs++); |
786 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 787 | if (index >= 0) |
8b9cf98c RR |
788 | move_msr_up(vmx, index, save_nmsrs++); |
789 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 790 | if (index >= 0) |
8b9cf98c RR |
791 | move_msr_up(vmx, index, save_nmsrs++); |
792 | index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE); | |
a75beee6 | 793 | if (index >= 0) |
8b9cf98c | 794 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
795 | /* |
796 | * MSR_K6_STAR is only needed on long mode guests, and only | |
797 | * if efer.sce is enabled. | |
798 | */ | |
8b9cf98c | 799 | index = __find_msr_index(vmx, MSR_K6_STAR); |
ad312c7c | 800 | if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE)) |
8b9cf98c | 801 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
802 | } |
803 | #endif | |
a2fa3e9f | 804 | vmx->save_nmsrs = save_nmsrs; |
e38aea3e | 805 | |
4d56c8a7 | 806 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 807 | vmx->msr_offset_kernel_gs_base = |
8b9cf98c | 808 | __find_msr_index(vmx, MSR_KERNEL_GS_BASE); |
4d56c8a7 | 809 | #endif |
8b9cf98c | 810 | vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER); |
e38aea3e AK |
811 | } |
812 | ||
6aa8b732 AK |
813 | /* |
814 | * reads and returns guest's timestamp counter "register" | |
815 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
816 | */ | |
817 | static u64 guest_read_tsc(void) | |
818 | { | |
819 | u64 host_tsc, tsc_offset; | |
820 | ||
821 | rdtscll(host_tsc); | |
822 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
823 | return host_tsc + tsc_offset; | |
824 | } | |
825 | ||
826 | /* | |
827 | * writes 'guest_tsc' into guest's timestamp counter "register" | |
828 | * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc | |
829 | */ | |
830 | static void guest_write_tsc(u64 guest_tsc) | |
831 | { | |
832 | u64 host_tsc; | |
833 | ||
834 | rdtscll(host_tsc); | |
835 | vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc); | |
836 | } | |
837 | ||
6aa8b732 AK |
838 | /* |
839 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
840 | * Returns 0 on success, non-0 otherwise. | |
841 | * Assumes vcpu_load() was already called. | |
842 | */ | |
843 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
844 | { | |
845 | u64 data; | |
a2fa3e9f | 846 | struct kvm_msr_entry *msr; |
6aa8b732 AK |
847 | |
848 | if (!pdata) { | |
849 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
850 | return -EINVAL; | |
851 | } | |
852 | ||
853 | switch (msr_index) { | |
05b3e0c2 | 854 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
855 | case MSR_FS_BASE: |
856 | data = vmcs_readl(GUEST_FS_BASE); | |
857 | break; | |
858 | case MSR_GS_BASE: | |
859 | data = vmcs_readl(GUEST_GS_BASE); | |
860 | break; | |
861 | case MSR_EFER: | |
3bab1f5d | 862 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
863 | #endif |
864 | case MSR_IA32_TIME_STAMP_COUNTER: | |
865 | data = guest_read_tsc(); | |
866 | break; | |
867 | case MSR_IA32_SYSENTER_CS: | |
868 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
869 | break; | |
870 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 871 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
872 | break; |
873 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 874 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 875 | break; |
6aa8b732 | 876 | default: |
8b9cf98c | 877 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d AK |
878 | if (msr) { |
879 | data = msr->data; | |
880 | break; | |
6aa8b732 | 881 | } |
3bab1f5d | 882 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
883 | } |
884 | ||
885 | *pdata = data; | |
886 | return 0; | |
887 | } | |
888 | ||
889 | /* | |
890 | * Writes msr value into into the appropriate "register". | |
891 | * Returns 0 on success, non-0 otherwise. | |
892 | * Assumes vcpu_load() was already called. | |
893 | */ | |
894 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
895 | { | |
a2fa3e9f GH |
896 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
897 | struct kvm_msr_entry *msr; | |
2cc51560 ED |
898 | int ret = 0; |
899 | ||
6aa8b732 | 900 | switch (msr_index) { |
05b3e0c2 | 901 | #ifdef CONFIG_X86_64 |
3bab1f5d | 902 | case MSR_EFER: |
a9b21b62 | 903 | vmx_load_host_state(vmx); |
2cc51560 | 904 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
2cc51560 | 905 | break; |
6aa8b732 AK |
906 | case MSR_FS_BASE: |
907 | vmcs_writel(GUEST_FS_BASE, data); | |
908 | break; | |
909 | case MSR_GS_BASE: | |
910 | vmcs_writel(GUEST_GS_BASE, data); | |
911 | break; | |
912 | #endif | |
913 | case MSR_IA32_SYSENTER_CS: | |
914 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
915 | break; | |
916 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 917 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
918 | break; |
919 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 920 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 921 | break; |
d27d4aca | 922 | case MSR_IA32_TIME_STAMP_COUNTER: |
6aa8b732 | 923 | guest_write_tsc(data); |
efa67e0d CL |
924 | break; |
925 | case MSR_P6_PERFCTR0: | |
926 | case MSR_P6_PERFCTR1: | |
927 | case MSR_P6_EVNTSEL0: | |
928 | case MSR_P6_EVNTSEL1: | |
929 | /* | |
930 | * Just discard all writes to the performance counters; this | |
931 | * should keep both older linux and windows 64-bit guests | |
932 | * happy | |
933 | */ | |
934 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data); | |
935 | ||
6aa8b732 | 936 | break; |
6aa8b732 | 937 | default: |
a9b21b62 | 938 | vmx_load_host_state(vmx); |
8b9cf98c | 939 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d AK |
940 | if (msr) { |
941 | msr->data = data; | |
942 | break; | |
6aa8b732 | 943 | } |
2cc51560 | 944 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
945 | } |
946 | ||
2cc51560 | 947 | return ret; |
6aa8b732 AK |
948 | } |
949 | ||
950 | /* | |
951 | * Sync the rsp and rip registers into the vcpu structure. This allows | |
ad312c7c | 952 | * registers to be accessed by indexing vcpu->arch.regs. |
6aa8b732 AK |
953 | */ |
954 | static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu) | |
955 | { | |
ad312c7c ZX |
956 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); |
957 | vcpu->arch.rip = vmcs_readl(GUEST_RIP); | |
6aa8b732 AK |
958 | } |
959 | ||
960 | /* | |
961 | * Syncs rsp and rip back into the vmcs. Should be called after possible | |
962 | * modification. | |
963 | */ | |
964 | static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu) | |
965 | { | |
ad312c7c ZX |
966 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); |
967 | vmcs_writel(GUEST_RIP, vcpu->arch.rip); | |
6aa8b732 AK |
968 | } |
969 | ||
970 | static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
971 | { | |
972 | unsigned long dr7 = 0x400; | |
6aa8b732 AK |
973 | int old_singlestep; |
974 | ||
6aa8b732 AK |
975 | old_singlestep = vcpu->guest_debug.singlestep; |
976 | ||
977 | vcpu->guest_debug.enabled = dbg->enabled; | |
978 | if (vcpu->guest_debug.enabled) { | |
979 | int i; | |
980 | ||
981 | dr7 |= 0x200; /* exact */ | |
982 | for (i = 0; i < 4; ++i) { | |
983 | if (!dbg->breakpoints[i].enabled) | |
984 | continue; | |
985 | vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address; | |
986 | dr7 |= 2 << (i*2); /* global enable */ | |
987 | dr7 |= 0 << (i*4+16); /* execution breakpoint */ | |
988 | } | |
989 | ||
6aa8b732 | 990 | vcpu->guest_debug.singlestep = dbg->singlestep; |
abd3f2d6 | 991 | } else |
6aa8b732 | 992 | vcpu->guest_debug.singlestep = 0; |
6aa8b732 AK |
993 | |
994 | if (old_singlestep && !vcpu->guest_debug.singlestep) { | |
995 | unsigned long flags; | |
996 | ||
997 | flags = vmcs_readl(GUEST_RFLAGS); | |
998 | flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
999 | vmcs_writel(GUEST_RFLAGS, flags); | |
1000 | } | |
1001 | ||
abd3f2d6 | 1002 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
1003 | vmcs_writel(GUEST_DR7, dr7); |
1004 | ||
1005 | return 0; | |
1006 | } | |
1007 | ||
2a8067f1 ED |
1008 | static int vmx_get_irq(struct kvm_vcpu *vcpu) |
1009 | { | |
1155f76a | 1010 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2a8067f1 ED |
1011 | u32 idtv_info_field; |
1012 | ||
1155f76a | 1013 | idtv_info_field = vmx->idt_vectoring_info; |
2a8067f1 ED |
1014 | if (idtv_info_field & INTR_INFO_VALID_MASK) { |
1015 | if (is_external_interrupt(idtv_info_field)) | |
1016 | return idtv_info_field & VECTORING_INFO_VECTOR_MASK; | |
1017 | else | |
d77c26fc | 1018 | printk(KERN_DEBUG "pending exception: not handled yet\n"); |
2a8067f1 ED |
1019 | } |
1020 | return -1; | |
1021 | } | |
1022 | ||
6aa8b732 AK |
1023 | static __init int cpu_has_kvm_support(void) |
1024 | { | |
1025 | unsigned long ecx = cpuid_ecx(1); | |
1026 | return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */ | |
1027 | } | |
1028 | ||
1029 | static __init int vmx_disabled_by_bios(void) | |
1030 | { | |
1031 | u64 msr; | |
1032 | ||
1033 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
62b3ffb8 YS |
1034 | return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED | |
1035 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
1036 | == MSR_IA32_FEATURE_CONTROL_LOCKED; | |
1037 | /* locked but not enabled */ | |
6aa8b732 AK |
1038 | } |
1039 | ||
774c47f1 | 1040 | static void hardware_enable(void *garbage) |
6aa8b732 AK |
1041 | { |
1042 | int cpu = raw_smp_processor_id(); | |
1043 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
1044 | u64 old; | |
1045 | ||
543e4243 | 1046 | INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu)); |
6aa8b732 | 1047 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
62b3ffb8 YS |
1048 | if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED | |
1049 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
1050 | != (MSR_IA32_FEATURE_CONTROL_LOCKED | | |
1051 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
6aa8b732 | 1052 | /* enable and lock */ |
62b3ffb8 YS |
1053 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | |
1054 | MSR_IA32_FEATURE_CONTROL_LOCKED | | |
1055 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED); | |
66aee91a | 1056 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
4ecac3fd AK |
1057 | asm volatile (ASM_VMX_VMXON_RAX |
1058 | : : "a"(&phys_addr), "m"(phys_addr) | |
6aa8b732 AK |
1059 | : "memory", "cc"); |
1060 | } | |
1061 | ||
543e4243 AK |
1062 | static void vmclear_local_vcpus(void) |
1063 | { | |
1064 | int cpu = raw_smp_processor_id(); | |
1065 | struct vcpu_vmx *vmx, *n; | |
1066 | ||
1067 | list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu), | |
1068 | local_vcpus_link) | |
1069 | __vcpu_clear(vmx); | |
1070 | } | |
1071 | ||
6aa8b732 AK |
1072 | static void hardware_disable(void *garbage) |
1073 | { | |
543e4243 | 1074 | vmclear_local_vcpus(); |
4ecac3fd | 1075 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
e693d71b | 1076 | write_cr4(read_cr4() & ~X86_CR4_VMXE); |
6aa8b732 AK |
1077 | } |
1078 | ||
1c3d14fe | 1079 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 1080 | u32 msr, u32 *result) |
1c3d14fe YS |
1081 | { |
1082 | u32 vmx_msr_low, vmx_msr_high; | |
1083 | u32 ctl = ctl_min | ctl_opt; | |
1084 | ||
1085 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
1086 | ||
1087 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
1088 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
1089 | ||
1090 | /* Ensure minimum (required) set of control bits are supported. */ | |
1091 | if (ctl_min & ~ctl) | |
002c7f7c | 1092 | return -EIO; |
1c3d14fe YS |
1093 | |
1094 | *result = ctl; | |
1095 | return 0; | |
1096 | } | |
1097 | ||
002c7f7c | 1098 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
1099 | { |
1100 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 1101 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
1102 | u32 _pin_based_exec_control = 0; |
1103 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 1104 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
1105 | u32 _vmexit_control = 0; |
1106 | u32 _vmentry_control = 0; | |
1107 | ||
1108 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
f08864b4 | 1109 | opt = PIN_BASED_VIRTUAL_NMIS; |
1c3d14fe YS |
1110 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
1111 | &_pin_based_exec_control) < 0) | |
002c7f7c | 1112 | return -EIO; |
1c3d14fe YS |
1113 | |
1114 | min = CPU_BASED_HLT_EXITING | | |
1115 | #ifdef CONFIG_X86_64 | |
1116 | CPU_BASED_CR8_LOAD_EXITING | | |
1117 | CPU_BASED_CR8_STORE_EXITING | | |
1118 | #endif | |
d56f546d SY |
1119 | CPU_BASED_CR3_LOAD_EXITING | |
1120 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
1121 | CPU_BASED_USE_IO_BITMAPS | |
1122 | CPU_BASED_MOV_DR_EXITING | | |
1123 | CPU_BASED_USE_TSC_OFFSETING; | |
f78e0e2e | 1124 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 1125 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 1126 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
1127 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
1128 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 1129 | return -EIO; |
6e5d865c YS |
1130 | #ifdef CONFIG_X86_64 |
1131 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
1132 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
1133 | ~CPU_BASED_CR8_STORE_EXITING; | |
1134 | #endif | |
f78e0e2e | 1135 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
1136 | min2 = 0; |
1137 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
2384d2b3 | 1138 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d SY |
1139 | SECONDARY_EXEC_ENABLE_VPID | |
1140 | SECONDARY_EXEC_ENABLE_EPT; | |
1141 | if (adjust_vmx_controls(min2, opt2, | |
1142 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
1143 | &_cpu_based_2nd_exec_control) < 0) |
1144 | return -EIO; | |
1145 | } | |
1146 | #ifndef CONFIG_X86_64 | |
1147 | if (!(_cpu_based_2nd_exec_control & | |
1148 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
1149 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1150 | #endif | |
d56f546d SY |
1151 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
1152 | /* CR3 accesses don't need to cause VM Exits when EPT enabled */ | |
1153 | min &= ~(CPU_BASED_CR3_LOAD_EXITING | | |
1154 | CPU_BASED_CR3_STORE_EXITING); | |
1155 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, | |
1156 | &_cpu_based_exec_control) < 0) | |
1157 | return -EIO; | |
1158 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, | |
1159 | vmx_capability.ept, vmx_capability.vpid); | |
1160 | } | |
1c3d14fe YS |
1161 | |
1162 | min = 0; | |
1163 | #ifdef CONFIG_X86_64 | |
1164 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
1165 | #endif | |
1166 | opt = 0; | |
1167 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, | |
1168 | &_vmexit_control) < 0) | |
002c7f7c | 1169 | return -EIO; |
1c3d14fe YS |
1170 | |
1171 | min = opt = 0; | |
1172 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, | |
1173 | &_vmentry_control) < 0) | |
002c7f7c | 1174 | return -EIO; |
6aa8b732 | 1175 | |
c68876fd | 1176 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
1177 | |
1178 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
1179 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 1180 | return -EIO; |
1c3d14fe YS |
1181 | |
1182 | #ifdef CONFIG_X86_64 | |
1183 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
1184 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 1185 | return -EIO; |
1c3d14fe YS |
1186 | #endif |
1187 | ||
1188 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
1189 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 1190 | return -EIO; |
1c3d14fe | 1191 | |
002c7f7c YS |
1192 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
1193 | vmcs_conf->order = get_order(vmcs_config.size); | |
1194 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 1195 | |
002c7f7c YS |
1196 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
1197 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 1198 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
1199 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
1200 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe YS |
1201 | |
1202 | return 0; | |
c68876fd | 1203 | } |
6aa8b732 AK |
1204 | |
1205 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
1206 | { | |
1207 | int node = cpu_to_node(cpu); | |
1208 | struct page *pages; | |
1209 | struct vmcs *vmcs; | |
1210 | ||
1c3d14fe | 1211 | pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
1212 | if (!pages) |
1213 | return NULL; | |
1214 | vmcs = page_address(pages); | |
1c3d14fe YS |
1215 | memset(vmcs, 0, vmcs_config.size); |
1216 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
1217 | return vmcs; |
1218 | } | |
1219 | ||
1220 | static struct vmcs *alloc_vmcs(void) | |
1221 | { | |
d3b2c338 | 1222 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
1223 | } |
1224 | ||
1225 | static void free_vmcs(struct vmcs *vmcs) | |
1226 | { | |
1c3d14fe | 1227 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
1228 | } |
1229 | ||
39959588 | 1230 | static void free_kvm_area(void) |
6aa8b732 AK |
1231 | { |
1232 | int cpu; | |
1233 | ||
1234 | for_each_online_cpu(cpu) | |
1235 | free_vmcs(per_cpu(vmxarea, cpu)); | |
1236 | } | |
1237 | ||
6aa8b732 AK |
1238 | static __init int alloc_kvm_area(void) |
1239 | { | |
1240 | int cpu; | |
1241 | ||
1242 | for_each_online_cpu(cpu) { | |
1243 | struct vmcs *vmcs; | |
1244 | ||
1245 | vmcs = alloc_vmcs_cpu(cpu); | |
1246 | if (!vmcs) { | |
1247 | free_kvm_area(); | |
1248 | return -ENOMEM; | |
1249 | } | |
1250 | ||
1251 | per_cpu(vmxarea, cpu) = vmcs; | |
1252 | } | |
1253 | return 0; | |
1254 | } | |
1255 | ||
1256 | static __init int hardware_setup(void) | |
1257 | { | |
002c7f7c YS |
1258 | if (setup_vmcs_config(&vmcs_config) < 0) |
1259 | return -EIO; | |
50a37eb4 JR |
1260 | |
1261 | if (boot_cpu_has(X86_FEATURE_NX)) | |
1262 | kvm_enable_efer_bits(EFER_NX); | |
1263 | ||
6aa8b732 AK |
1264 | return alloc_kvm_area(); |
1265 | } | |
1266 | ||
1267 | static __exit void hardware_unsetup(void) | |
1268 | { | |
1269 | free_kvm_area(); | |
1270 | } | |
1271 | ||
6aa8b732 AK |
1272 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
1273 | { | |
1274 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1275 | ||
6af11b9e | 1276 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
1277 | vmcs_write16(sf->selector, save->selector); |
1278 | vmcs_writel(sf->base, save->base); | |
1279 | vmcs_write32(sf->limit, save->limit); | |
1280 | vmcs_write32(sf->ar_bytes, save->ar); | |
1281 | } else { | |
1282 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
1283 | << AR_DPL_SHIFT; | |
1284 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
1285 | } | |
1286 | } | |
1287 | ||
1288 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
1289 | { | |
1290 | unsigned long flags; | |
1291 | ||
ad312c7c | 1292 | vcpu->arch.rmode.active = 0; |
6aa8b732 | 1293 | |
ad312c7c ZX |
1294 | vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base); |
1295 | vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit); | |
1296 | vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar); | |
6aa8b732 AK |
1297 | |
1298 | flags = vmcs_readl(GUEST_RFLAGS); | |
053de044 | 1299 | flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM); |
ad312c7c | 1300 | flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT); |
6aa8b732 AK |
1301 | vmcs_writel(GUEST_RFLAGS, flags); |
1302 | ||
66aee91a RR |
1303 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
1304 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
1305 | |
1306 | update_exception_bitmap(vcpu); | |
1307 | ||
ad312c7c ZX |
1308 | fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es); |
1309 | fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1310 | fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1311 | fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
6aa8b732 AK |
1312 | |
1313 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
1314 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
1315 | ||
1316 | vmcs_write16(GUEST_CS_SELECTOR, | |
1317 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
1318 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1319 | } | |
1320 | ||
d77c26fc | 1321 | static gva_t rmode_tss_base(struct kvm *kvm) |
6aa8b732 | 1322 | { |
bfc6d222 | 1323 | if (!kvm->arch.tss_addr) { |
cbc94022 IE |
1324 | gfn_t base_gfn = kvm->memslots[0].base_gfn + |
1325 | kvm->memslots[0].npages - 3; | |
1326 | return base_gfn << PAGE_SHIFT; | |
1327 | } | |
bfc6d222 | 1328 | return kvm->arch.tss_addr; |
6aa8b732 AK |
1329 | } |
1330 | ||
1331 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
1332 | { | |
1333 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1334 | ||
1335 | save->selector = vmcs_read16(sf->selector); | |
1336 | save->base = vmcs_readl(sf->base); | |
1337 | save->limit = vmcs_read32(sf->limit); | |
1338 | save->ar = vmcs_read32(sf->ar_bytes); | |
15b00f32 JK |
1339 | vmcs_write16(sf->selector, save->base >> 4); |
1340 | vmcs_write32(sf->base, save->base & 0xfffff); | |
6aa8b732 AK |
1341 | vmcs_write32(sf->limit, 0xffff); |
1342 | vmcs_write32(sf->ar_bytes, 0xf3); | |
1343 | } | |
1344 | ||
1345 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
1346 | { | |
1347 | unsigned long flags; | |
1348 | ||
ad312c7c | 1349 | vcpu->arch.rmode.active = 1; |
6aa8b732 | 1350 | |
ad312c7c | 1351 | vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE); |
6aa8b732 AK |
1352 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); |
1353 | ||
ad312c7c | 1354 | vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); |
6aa8b732 AK |
1355 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
1356 | ||
ad312c7c | 1357 | vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); |
6aa8b732 AK |
1358 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
1359 | ||
1360 | flags = vmcs_readl(GUEST_RFLAGS); | |
ad312c7c ZX |
1361 | vcpu->arch.rmode.save_iopl |
1362 | = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
6aa8b732 | 1363 | |
053de044 | 1364 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
1365 | |
1366 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 1367 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
1368 | update_exception_bitmap(vcpu); |
1369 | ||
1370 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); | |
1371 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
1372 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
1373 | ||
1374 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 1375 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
1376 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
1377 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
1378 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
1379 | ||
ad312c7c ZX |
1380 | fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es); |
1381 | fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1382 | fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1383 | fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
75880a01 | 1384 | |
8668a3c4 | 1385 | kvm_mmu_reset_context(vcpu); |
b7ebfb05 | 1386 | init_rmode(vcpu->kvm); |
6aa8b732 AK |
1387 | } |
1388 | ||
05b3e0c2 | 1389 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1390 | |
1391 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
1392 | { | |
1393 | u32 guest_tr_ar; | |
1394 | ||
1395 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1396 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
1397 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
b8688d51 | 1398 | __func__); |
6aa8b732 AK |
1399 | vmcs_write32(GUEST_TR_AR_BYTES, |
1400 | (guest_tr_ar & ~AR_TYPE_MASK) | |
1401 | | AR_TYPE_BUSY_64_TSS); | |
1402 | } | |
1403 | ||
ad312c7c | 1404 | vcpu->arch.shadow_efer |= EFER_LMA; |
6aa8b732 | 1405 | |
8b9cf98c | 1406 | find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1407 | vmcs_write32(VM_ENTRY_CONTROLS, |
1408 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1409 | | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1410 | } |
1411 | ||
1412 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
1413 | { | |
ad312c7c | 1414 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
6aa8b732 AK |
1415 | |
1416 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1417 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1418 | & ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1419 | } |
1420 | ||
1421 | #endif | |
1422 | ||
2384d2b3 SY |
1423 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
1424 | { | |
1425 | vpid_sync_vcpu_all(to_vmx(vcpu)); | |
4e1096d2 SY |
1426 | if (vm_need_ept()) |
1427 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); | |
2384d2b3 SY |
1428 | } |
1429 | ||
25c4c276 | 1430 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 1431 | { |
ad312c7c ZX |
1432 | vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK; |
1433 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK; | |
399badf3 AK |
1434 | } |
1435 | ||
1439442c SY |
1436 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
1437 | { | |
1438 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1439 | if (!load_pdptrs(vcpu, vcpu->arch.cr3)) { | |
1440 | printk(KERN_ERR "EPT: Fail to load pdptrs!\n"); | |
1441 | return; | |
1442 | } | |
1443 | vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]); | |
1444 | vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]); | |
1445 | vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]); | |
1446 | vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]); | |
1447 | } | |
1448 | } | |
1449 | ||
1450 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); | |
1451 | ||
1452 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
1453 | unsigned long cr0, | |
1454 | struct kvm_vcpu *vcpu) | |
1455 | { | |
1456 | if (!(cr0 & X86_CR0_PG)) { | |
1457 | /* From paging/starting to nonpaging */ | |
1458 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1459 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
1460 | (CPU_BASED_CR3_LOAD_EXITING | |
1461 | CPU_BASED_CR3_STORE_EXITING)); | |
1462 | vcpu->arch.cr0 = cr0; | |
1463 | vmx_set_cr4(vcpu, vcpu->arch.cr4); | |
1464 | *hw_cr0 |= X86_CR0_PE | X86_CR0_PG; | |
1465 | *hw_cr0 &= ~X86_CR0_WP; | |
1466 | } else if (!is_paging(vcpu)) { | |
1467 | /* From nonpaging to paging */ | |
1468 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1469 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
1470 | ~(CPU_BASED_CR3_LOAD_EXITING | |
1471 | CPU_BASED_CR3_STORE_EXITING)); | |
1472 | vcpu->arch.cr0 = cr0; | |
1473 | vmx_set_cr4(vcpu, vcpu->arch.cr4); | |
1474 | if (!(vcpu->arch.cr0 & X86_CR0_WP)) | |
1475 | *hw_cr0 &= ~X86_CR0_WP; | |
1476 | } | |
1477 | } | |
1478 | ||
1479 | static void ept_update_paging_mode_cr4(unsigned long *hw_cr4, | |
1480 | struct kvm_vcpu *vcpu) | |
1481 | { | |
1482 | if (!is_paging(vcpu)) { | |
1483 | *hw_cr4 &= ~X86_CR4_PAE; | |
1484 | *hw_cr4 |= X86_CR4_PSE; | |
1485 | } else if (!(vcpu->arch.cr4 & X86_CR4_PAE)) | |
1486 | *hw_cr4 &= ~X86_CR4_PAE; | |
1487 | } | |
1488 | ||
6aa8b732 AK |
1489 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1490 | { | |
1439442c SY |
1491 | unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | |
1492 | KVM_VM_CR0_ALWAYS_ON; | |
1493 | ||
5fd86fcf AK |
1494 | vmx_fpu_deactivate(vcpu); |
1495 | ||
ad312c7c | 1496 | if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1497 | enter_pmode(vcpu); |
1498 | ||
ad312c7c | 1499 | if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1500 | enter_rmode(vcpu); |
1501 | ||
05b3e0c2 | 1502 | #ifdef CONFIG_X86_64 |
ad312c7c | 1503 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 1504 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 1505 | enter_lmode(vcpu); |
707d92fa | 1506 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
1507 | exit_lmode(vcpu); |
1508 | } | |
1509 | #endif | |
1510 | ||
1439442c SY |
1511 | if (vm_need_ept()) |
1512 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); | |
1513 | ||
6aa8b732 | 1514 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 1515 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 1516 | vcpu->arch.cr0 = cr0; |
5fd86fcf | 1517 | |
707d92fa | 1518 | if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE)) |
5fd86fcf | 1519 | vmx_fpu_activate(vcpu); |
6aa8b732 AK |
1520 | } |
1521 | ||
1439442c SY |
1522 | static u64 construct_eptp(unsigned long root_hpa) |
1523 | { | |
1524 | u64 eptp; | |
1525 | ||
1526 | /* TODO write the value reading from MSR */ | |
1527 | eptp = VMX_EPT_DEFAULT_MT | | |
1528 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
1529 | eptp |= (root_hpa & PAGE_MASK); | |
1530 | ||
1531 | return eptp; | |
1532 | } | |
1533 | ||
6aa8b732 AK |
1534 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
1535 | { | |
1439442c SY |
1536 | unsigned long guest_cr3; |
1537 | u64 eptp; | |
1538 | ||
1539 | guest_cr3 = cr3; | |
1540 | if (vm_need_ept()) { | |
1541 | eptp = construct_eptp(cr3); | |
1542 | vmcs_write64(EPT_POINTER, eptp); | |
1543 | ept_sync_context(eptp); | |
1544 | ept_load_pdptrs(vcpu); | |
1545 | guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 : | |
1546 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
1547 | } | |
1548 | ||
2384d2b3 | 1549 | vmx_flush_tlb(vcpu); |
1439442c | 1550 | vmcs_writel(GUEST_CR3, guest_cr3); |
ad312c7c | 1551 | if (vcpu->arch.cr0 & X86_CR0_PE) |
5fd86fcf | 1552 | vmx_fpu_deactivate(vcpu); |
6aa8b732 AK |
1553 | } |
1554 | ||
1555 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1556 | { | |
1439442c SY |
1557 | unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ? |
1558 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1559 | ||
ad312c7c | 1560 | vcpu->arch.cr4 = cr4; |
1439442c SY |
1561 | if (vm_need_ept()) |
1562 | ept_update_paging_mode_cr4(&hw_cr4, vcpu); | |
1563 | ||
1564 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
1565 | vmcs_writel(GUEST_CR4, hw_cr4); | |
6aa8b732 AK |
1566 | } |
1567 | ||
6aa8b732 AK |
1568 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
1569 | { | |
8b9cf98c RR |
1570 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1571 | struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); | |
6aa8b732 | 1572 | |
ad312c7c | 1573 | vcpu->arch.shadow_efer = efer; |
9f62e19a JR |
1574 | if (!msr) |
1575 | return; | |
6aa8b732 AK |
1576 | if (efer & EFER_LMA) { |
1577 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1578 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
1e4e6e00 | 1579 | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1580 | msr->data = efer; |
1581 | ||
1582 | } else { | |
1583 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1584 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
1e4e6e00 | 1585 | ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1586 | |
1587 | msr->data = efer & ~EFER_LME; | |
1588 | } | |
8b9cf98c | 1589 | setup_msrs(vmx); |
6aa8b732 AK |
1590 | } |
1591 | ||
6aa8b732 AK |
1592 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
1593 | { | |
1594 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1595 | ||
1596 | return vmcs_readl(sf->base); | |
1597 | } | |
1598 | ||
1599 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
1600 | struct kvm_segment *var, int seg) | |
1601 | { | |
1602 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1603 | u32 ar; | |
1604 | ||
1605 | var->base = vmcs_readl(sf->base); | |
1606 | var->limit = vmcs_read32(sf->limit); | |
1607 | var->selector = vmcs_read16(sf->selector); | |
1608 | ar = vmcs_read32(sf->ar_bytes); | |
1609 | if (ar & AR_UNUSABLE_MASK) | |
1610 | ar = 0; | |
1611 | var->type = ar & 15; | |
1612 | var->s = (ar >> 4) & 1; | |
1613 | var->dpl = (ar >> 5) & 3; | |
1614 | var->present = (ar >> 7) & 1; | |
1615 | var->avl = (ar >> 12) & 1; | |
1616 | var->l = (ar >> 13) & 1; | |
1617 | var->db = (ar >> 14) & 1; | |
1618 | var->g = (ar >> 15) & 1; | |
1619 | var->unusable = (ar >> 16) & 1; | |
1620 | } | |
1621 | ||
2e4d2653 IE |
1622 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
1623 | { | |
1624 | struct kvm_segment kvm_seg; | |
1625 | ||
1626 | if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */ | |
1627 | return 0; | |
1628 | ||
1629 | if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */ | |
1630 | return 3; | |
1631 | ||
1632 | vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS); | |
1633 | return kvm_seg.selector & 3; | |
1634 | } | |
1635 | ||
653e3108 | 1636 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 1637 | { |
6aa8b732 AK |
1638 | u32 ar; |
1639 | ||
653e3108 | 1640 | if (var->unusable) |
6aa8b732 AK |
1641 | ar = 1 << 16; |
1642 | else { | |
1643 | ar = var->type & 15; | |
1644 | ar |= (var->s & 1) << 4; | |
1645 | ar |= (var->dpl & 3) << 5; | |
1646 | ar |= (var->present & 1) << 7; | |
1647 | ar |= (var->avl & 1) << 12; | |
1648 | ar |= (var->l & 1) << 13; | |
1649 | ar |= (var->db & 1) << 14; | |
1650 | ar |= (var->g & 1) << 15; | |
1651 | } | |
f7fbf1fd UL |
1652 | if (ar == 0) /* a 0 value means unusable */ |
1653 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
1654 | |
1655 | return ar; | |
1656 | } | |
1657 | ||
1658 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
1659 | struct kvm_segment *var, int seg) | |
1660 | { | |
1661 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1662 | u32 ar; | |
1663 | ||
ad312c7c ZX |
1664 | if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) { |
1665 | vcpu->arch.rmode.tr.selector = var->selector; | |
1666 | vcpu->arch.rmode.tr.base = var->base; | |
1667 | vcpu->arch.rmode.tr.limit = var->limit; | |
1668 | vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var); | |
653e3108 AK |
1669 | return; |
1670 | } | |
1671 | vmcs_writel(sf->base, var->base); | |
1672 | vmcs_write32(sf->limit, var->limit); | |
1673 | vmcs_write16(sf->selector, var->selector); | |
ad312c7c | 1674 | if (vcpu->arch.rmode.active && var->s) { |
653e3108 AK |
1675 | /* |
1676 | * Hack real-mode segments into vm86 compatibility. | |
1677 | */ | |
1678 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
1679 | vmcs_writel(sf->base, 0xf0000); | |
1680 | ar = 0xf3; | |
1681 | } else | |
1682 | ar = vmx_segment_access_rights(var); | |
6aa8b732 AK |
1683 | vmcs_write32(sf->ar_bytes, ar); |
1684 | } | |
1685 | ||
6aa8b732 AK |
1686 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
1687 | { | |
1688 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
1689 | ||
1690 | *db = (ar >> 14) & 1; | |
1691 | *l = (ar >> 13) & 1; | |
1692 | } | |
1693 | ||
1694 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1695 | { | |
1696 | dt->limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
1697 | dt->base = vmcs_readl(GUEST_IDTR_BASE); | |
1698 | } | |
1699 | ||
1700 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1701 | { | |
1702 | vmcs_write32(GUEST_IDTR_LIMIT, dt->limit); | |
1703 | vmcs_writel(GUEST_IDTR_BASE, dt->base); | |
1704 | } | |
1705 | ||
1706 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1707 | { | |
1708 | dt->limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
1709 | dt->base = vmcs_readl(GUEST_GDTR_BASE); | |
1710 | } | |
1711 | ||
1712 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1713 | { | |
1714 | vmcs_write32(GUEST_GDTR_LIMIT, dt->limit); | |
1715 | vmcs_writel(GUEST_GDTR_BASE, dt->base); | |
1716 | } | |
1717 | ||
d77c26fc | 1718 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 1719 | { |
6aa8b732 | 1720 | gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT; |
195aefde | 1721 | u16 data = 0; |
10589a46 | 1722 | int ret = 0; |
195aefde | 1723 | int r; |
6aa8b732 | 1724 | |
195aefde IE |
1725 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1726 | if (r < 0) | |
10589a46 | 1727 | goto out; |
195aefde IE |
1728 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
1729 | r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16)); | |
1730 | if (r < 0) | |
10589a46 | 1731 | goto out; |
195aefde IE |
1732 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
1733 | if (r < 0) | |
10589a46 | 1734 | goto out; |
195aefde IE |
1735 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1736 | if (r < 0) | |
10589a46 | 1737 | goto out; |
195aefde | 1738 | data = ~0; |
10589a46 MT |
1739 | r = kvm_write_guest_page(kvm, fn, &data, |
1740 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
1741 | sizeof(u8)); | |
195aefde | 1742 | if (r < 0) |
10589a46 MT |
1743 | goto out; |
1744 | ||
1745 | ret = 1; | |
1746 | out: | |
10589a46 | 1747 | return ret; |
6aa8b732 AK |
1748 | } |
1749 | ||
b7ebfb05 SY |
1750 | static int init_rmode_identity_map(struct kvm *kvm) |
1751 | { | |
1752 | int i, r, ret; | |
1753 | pfn_t identity_map_pfn; | |
1754 | u32 tmp; | |
1755 | ||
1756 | if (!vm_need_ept()) | |
1757 | return 1; | |
1758 | if (unlikely(!kvm->arch.ept_identity_pagetable)) { | |
1759 | printk(KERN_ERR "EPT: identity-mapping pagetable " | |
1760 | "haven't been allocated!\n"); | |
1761 | return 0; | |
1762 | } | |
1763 | if (likely(kvm->arch.ept_identity_pagetable_done)) | |
1764 | return 1; | |
1765 | ret = 0; | |
1766 | identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT; | |
1767 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); | |
1768 | if (r < 0) | |
1769 | goto out; | |
1770 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
1771 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
1772 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
1773 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
1774 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
1775 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
1776 | if (r < 0) | |
1777 | goto out; | |
1778 | } | |
1779 | kvm->arch.ept_identity_pagetable_done = true; | |
1780 | ret = 1; | |
1781 | out: | |
1782 | return ret; | |
1783 | } | |
1784 | ||
6aa8b732 AK |
1785 | static void seg_setup(int seg) |
1786 | { | |
1787 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1788 | ||
1789 | vmcs_write16(sf->selector, 0); | |
1790 | vmcs_writel(sf->base, 0); | |
1791 | vmcs_write32(sf->limit, 0xffff); | |
1792 | vmcs_write32(sf->ar_bytes, 0x93); | |
1793 | } | |
1794 | ||
f78e0e2e SY |
1795 | static int alloc_apic_access_page(struct kvm *kvm) |
1796 | { | |
1797 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
1798 | int r = 0; | |
1799 | ||
72dc67a6 | 1800 | down_write(&kvm->slots_lock); |
bfc6d222 | 1801 | if (kvm->arch.apic_access_page) |
f78e0e2e SY |
1802 | goto out; |
1803 | kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
1804 | kvm_userspace_mem.flags = 0; | |
1805 | kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL; | |
1806 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
1807 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
1808 | if (r) | |
1809 | goto out; | |
72dc67a6 IE |
1810 | |
1811 | down_read(¤t->mm->mmap_sem); | |
bfc6d222 | 1812 | kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00); |
72dc67a6 | 1813 | up_read(¤t->mm->mmap_sem); |
f78e0e2e | 1814 | out: |
72dc67a6 | 1815 | up_write(&kvm->slots_lock); |
f78e0e2e SY |
1816 | return r; |
1817 | } | |
1818 | ||
b7ebfb05 SY |
1819 | static int alloc_identity_pagetable(struct kvm *kvm) |
1820 | { | |
1821 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
1822 | int r = 0; | |
1823 | ||
1824 | down_write(&kvm->slots_lock); | |
1825 | if (kvm->arch.ept_identity_pagetable) | |
1826 | goto out; | |
1827 | kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
1828 | kvm_userspace_mem.flags = 0; | |
1829 | kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
1830 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
1831 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
1832 | if (r) | |
1833 | goto out; | |
1834 | ||
1835 | down_read(¤t->mm->mmap_sem); | |
1836 | kvm->arch.ept_identity_pagetable = gfn_to_page(kvm, | |
1837 | VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT); | |
1838 | up_read(¤t->mm->mmap_sem); | |
1839 | out: | |
1840 | up_write(&kvm->slots_lock); | |
1841 | return r; | |
1842 | } | |
1843 | ||
2384d2b3 SY |
1844 | static void allocate_vpid(struct vcpu_vmx *vmx) |
1845 | { | |
1846 | int vpid; | |
1847 | ||
1848 | vmx->vpid = 0; | |
1849 | if (!enable_vpid || !cpu_has_vmx_vpid()) | |
1850 | return; | |
1851 | spin_lock(&vmx_vpid_lock); | |
1852 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
1853 | if (vpid < VMX_NR_VPIDS) { | |
1854 | vmx->vpid = vpid; | |
1855 | __set_bit(vpid, vmx_vpid_bitmap); | |
1856 | } | |
1857 | spin_unlock(&vmx_vpid_lock); | |
1858 | } | |
1859 | ||
8b2cf73c | 1860 | static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr) |
25c5f225 SY |
1861 | { |
1862 | void *va; | |
1863 | ||
1864 | if (!cpu_has_vmx_msr_bitmap()) | |
1865 | return; | |
1866 | ||
1867 | /* | |
1868 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
1869 | * have the write-low and read-high bitmap offsets the wrong way round. | |
1870 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
1871 | */ | |
1872 | va = kmap(msr_bitmap); | |
1873 | if (msr <= 0x1fff) { | |
1874 | __clear_bit(msr, va + 0x000); /* read-low */ | |
1875 | __clear_bit(msr, va + 0x800); /* write-low */ | |
1876 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
1877 | msr &= 0x1fff; | |
1878 | __clear_bit(msr, va + 0x400); /* read-high */ | |
1879 | __clear_bit(msr, va + 0xc00); /* write-high */ | |
1880 | } | |
1881 | kunmap(msr_bitmap); | |
1882 | } | |
1883 | ||
6aa8b732 AK |
1884 | /* |
1885 | * Sets up the vmcs for emulated real mode. | |
1886 | */ | |
8b9cf98c | 1887 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 AK |
1888 | { |
1889 | u32 host_sysenter_cs; | |
1890 | u32 junk; | |
1891 | unsigned long a; | |
1892 | struct descriptor_table dt; | |
1893 | int i; | |
cd2276a7 | 1894 | unsigned long kvm_vmx_return; |
6e5d865c | 1895 | u32 exec_control; |
6aa8b732 | 1896 | |
6aa8b732 | 1897 | /* I/O */ |
fdef3ad1 HQ |
1898 | vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a)); |
1899 | vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b)); | |
6aa8b732 | 1900 | |
25c5f225 SY |
1901 | if (cpu_has_vmx_msr_bitmap()) |
1902 | vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap)); | |
1903 | ||
6aa8b732 AK |
1904 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
1905 | ||
6aa8b732 | 1906 | /* Control */ |
1c3d14fe YS |
1907 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, |
1908 | vmcs_config.pin_based_exec_ctrl); | |
6e5d865c YS |
1909 | |
1910 | exec_control = vmcs_config.cpu_based_exec_ctrl; | |
1911 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { | |
1912 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1913 | #ifdef CONFIG_X86_64 | |
1914 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
1915 | CPU_BASED_CR8_LOAD_EXITING; | |
1916 | #endif | |
1917 | } | |
d56f546d SY |
1918 | if (!vm_need_ept()) |
1919 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
1920 | CPU_BASED_CR3_LOAD_EXITING; | |
6e5d865c | 1921 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); |
6aa8b732 | 1922 | |
83ff3b9d SY |
1923 | if (cpu_has_secondary_exec_ctrls()) { |
1924 | exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
1925 | if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
1926 | exec_control &= | |
1927 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
2384d2b3 SY |
1928 | if (vmx->vpid == 0) |
1929 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
d56f546d SY |
1930 | if (!vm_need_ept()) |
1931 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
83ff3b9d SY |
1932 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
1933 | } | |
f78e0e2e | 1934 | |
c7addb90 AK |
1935 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf); |
1936 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf); | |
6aa8b732 AK |
1937 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
1938 | ||
1939 | vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */ | |
1940 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ | |
1941 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
1942 | ||
1943 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
1944 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1945 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
d6e88aec AK |
1946 | vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */ |
1947 | vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */ | |
6aa8b732 | 1948 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
05b3e0c2 | 1949 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1950 | rdmsrl(MSR_FS_BASE, a); |
1951 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
1952 | rdmsrl(MSR_GS_BASE, a); | |
1953 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
1954 | #else | |
1955 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
1956 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
1957 | #endif | |
1958 | ||
1959 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
1960 | ||
d6e88aec | 1961 | kvm_get_idt(&dt); |
6aa8b732 AK |
1962 | vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */ |
1963 | ||
d77c26fc | 1964 | asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); |
cd2276a7 | 1965 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ |
2cc51560 ED |
1966 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
1967 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
1968 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); | |
6aa8b732 AK |
1969 | |
1970 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
1971 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
1972 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
1973 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
1974 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
1975 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
1976 | ||
6aa8b732 AK |
1977 | for (i = 0; i < NR_VMX_MSR; ++i) { |
1978 | u32 index = vmx_msr_index[i]; | |
1979 | u32 data_low, data_high; | |
1980 | u64 data; | |
a2fa3e9f | 1981 | int j = vmx->nmsrs; |
6aa8b732 AK |
1982 | |
1983 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
1984 | continue; | |
432bd6cb AK |
1985 | if (wrmsr_safe(index, data_low, data_high) < 0) |
1986 | continue; | |
6aa8b732 | 1987 | data = data_low | ((u64)data_high << 32); |
a2fa3e9f GH |
1988 | vmx->host_msrs[j].index = index; |
1989 | vmx->host_msrs[j].reserved = 0; | |
1990 | vmx->host_msrs[j].data = data; | |
1991 | vmx->guest_msrs[j] = vmx->host_msrs[j]; | |
1992 | ++vmx->nmsrs; | |
6aa8b732 | 1993 | } |
6aa8b732 | 1994 | |
1c3d14fe | 1995 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
1996 | |
1997 | /* 22.2.1, 20.8.1 */ | |
1c3d14fe YS |
1998 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); |
1999 | ||
e00c8cf2 AK |
2000 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
2001 | vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK); | |
2002 | ||
f78e0e2e | 2003 | |
e00c8cf2 AK |
2004 | return 0; |
2005 | } | |
2006 | ||
b7ebfb05 SY |
2007 | static int init_rmode(struct kvm *kvm) |
2008 | { | |
2009 | if (!init_rmode_tss(kvm)) | |
2010 | return 0; | |
2011 | if (!init_rmode_identity_map(kvm)) | |
2012 | return 0; | |
2013 | return 1; | |
2014 | } | |
2015 | ||
e00c8cf2 AK |
2016 | static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) |
2017 | { | |
2018 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2019 | u64 msr; | |
2020 | int ret; | |
2021 | ||
3200f405 | 2022 | down_read(&vcpu->kvm->slots_lock); |
b7ebfb05 | 2023 | if (!init_rmode(vmx->vcpu.kvm)) { |
e00c8cf2 AK |
2024 | ret = -ENOMEM; |
2025 | goto out; | |
2026 | } | |
2027 | ||
ad312c7c | 2028 | vmx->vcpu.arch.rmode.active = 0; |
e00c8cf2 | 2029 | |
ad312c7c | 2030 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
2d3ad1f4 | 2031 | kvm_set_cr8(&vmx->vcpu, 0); |
e00c8cf2 AK |
2032 | msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
2033 | if (vmx->vcpu.vcpu_id == 0) | |
2034 | msr |= MSR_IA32_APICBASE_BSP; | |
2035 | kvm_set_apic_base(&vmx->vcpu, msr); | |
2036 | ||
2037 | fx_init(&vmx->vcpu); | |
2038 | ||
2039 | /* | |
2040 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
2041 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
2042 | */ | |
2043 | if (vmx->vcpu.vcpu_id == 0) { | |
2044 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); | |
2045 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
2046 | } else { | |
ad312c7c ZX |
2047 | vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8); |
2048 | vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12); | |
e00c8cf2 AK |
2049 | } |
2050 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); | |
2051 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
2052 | ||
2053 | seg_setup(VCPU_SREG_DS); | |
2054 | seg_setup(VCPU_SREG_ES); | |
2055 | seg_setup(VCPU_SREG_FS); | |
2056 | seg_setup(VCPU_SREG_GS); | |
2057 | seg_setup(VCPU_SREG_SS); | |
2058 | ||
2059 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
2060 | vmcs_writel(GUEST_TR_BASE, 0); | |
2061 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
2062 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
2063 | ||
2064 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
2065 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
2066 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
2067 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
2068 | ||
2069 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
2070 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
2071 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
2072 | ||
2073 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
2074 | if (vmx->vcpu.vcpu_id == 0) | |
2075 | vmcs_writel(GUEST_RIP, 0xfff0); | |
2076 | else | |
2077 | vmcs_writel(GUEST_RIP, 0); | |
2078 | vmcs_writel(GUEST_RSP, 0); | |
2079 | ||
2080 | /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */ | |
2081 | vmcs_writel(GUEST_DR7, 0x400); | |
2082 | ||
2083 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
2084 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
2085 | ||
2086 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
2087 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
2088 | ||
2089 | vmcs_write32(GUEST_ACTIVITY_STATE, 0); | |
2090 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); | |
2091 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
2092 | ||
2093 | guest_write_tsc(0); | |
2094 | ||
2095 | /* Special registers */ | |
2096 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
2097 | ||
2098 | setup_msrs(vmx); | |
2099 | ||
6aa8b732 AK |
2100 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
2101 | ||
f78e0e2e SY |
2102 | if (cpu_has_vmx_tpr_shadow()) { |
2103 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); | |
2104 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
2105 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
ad312c7c | 2106 | page_to_phys(vmx->vcpu.arch.apic->regs_page)); |
f78e0e2e SY |
2107 | vmcs_write32(TPR_THRESHOLD, 0); |
2108 | } | |
2109 | ||
2110 | if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2111 | vmcs_write64(APIC_ACCESS_ADDR, | |
bfc6d222 | 2112 | page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); |
6aa8b732 | 2113 | |
2384d2b3 SY |
2114 | if (vmx->vpid != 0) |
2115 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
2116 | ||
ad312c7c ZX |
2117 | vmx->vcpu.arch.cr0 = 0x60000010; |
2118 | vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */ | |
8b9cf98c | 2119 | vmx_set_cr4(&vmx->vcpu, 0); |
8b9cf98c | 2120 | vmx_set_efer(&vmx->vcpu, 0); |
8b9cf98c RR |
2121 | vmx_fpu_activate(&vmx->vcpu); |
2122 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 | 2123 | |
2384d2b3 SY |
2124 | vpid_sync_vcpu_all(vmx); |
2125 | ||
3200f405 | 2126 | ret = 0; |
6aa8b732 | 2127 | |
6aa8b732 | 2128 | out: |
3200f405 | 2129 | up_read(&vcpu->kvm->slots_lock); |
6aa8b732 AK |
2130 | return ret; |
2131 | } | |
2132 | ||
85f455f7 ED |
2133 | static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq) |
2134 | { | |
9c8cba37 AK |
2135 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2136 | ||
2714d1d3 FEL |
2137 | KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler); |
2138 | ||
ad312c7c | 2139 | if (vcpu->arch.rmode.active) { |
9c8cba37 AK |
2140 | vmx->rmode.irq.pending = true; |
2141 | vmx->rmode.irq.vector = irq; | |
2142 | vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP); | |
9c5623e3 AK |
2143 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
2144 | irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK); | |
2145 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
9c8cba37 | 2146 | vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1); |
85f455f7 ED |
2147 | return; |
2148 | } | |
2149 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2150 | irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
2151 | } | |
2152 | ||
f08864b4 SY |
2153 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
2154 | { | |
2155 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2156 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
2157 | vcpu->arch.nmi_pending = 0; | |
2158 | } | |
2159 | ||
6aa8b732 AK |
2160 | static void kvm_do_inject_irq(struct kvm_vcpu *vcpu) |
2161 | { | |
ad312c7c ZX |
2162 | int word_index = __ffs(vcpu->arch.irq_summary); |
2163 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
2164 | int irq = word_index * BITS_PER_LONG + bit_index; |
2165 | ||
ad312c7c ZX |
2166 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
2167 | if (!vcpu->arch.irq_pending[word_index]) | |
2168 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
85f455f7 | 2169 | vmx_inject_irq(vcpu, irq); |
6aa8b732 AK |
2170 | } |
2171 | ||
c1150d8c DL |
2172 | |
2173 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, | |
2174 | struct kvm_run *kvm_run) | |
6aa8b732 | 2175 | { |
c1150d8c DL |
2176 | u32 cpu_based_vm_exec_control; |
2177 | ||
ad312c7c | 2178 | vcpu->arch.interrupt_window_open = |
c1150d8c DL |
2179 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && |
2180 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
2181 | ||
ad312c7c ZX |
2182 | if (vcpu->arch.interrupt_window_open && |
2183 | vcpu->arch.irq_summary && | |
c1150d8c | 2184 | !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK)) |
6aa8b732 | 2185 | /* |
c1150d8c | 2186 | * If interrupts enabled, and not blocked by sti or mov ss. Good. |
6aa8b732 AK |
2187 | */ |
2188 | kvm_do_inject_irq(vcpu); | |
c1150d8c DL |
2189 | |
2190 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
ad312c7c ZX |
2191 | if (!vcpu->arch.interrupt_window_open && |
2192 | (vcpu->arch.irq_summary || kvm_run->request_interrupt_window)) | |
6aa8b732 AK |
2193 | /* |
2194 | * Interrupts blocked. Wait for unblock. | |
2195 | */ | |
c1150d8c DL |
2196 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; |
2197 | else | |
2198 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
2199 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
6aa8b732 AK |
2200 | } |
2201 | ||
cbc94022 IE |
2202 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
2203 | { | |
2204 | int ret; | |
2205 | struct kvm_userspace_memory_region tss_mem = { | |
2206 | .slot = 8, | |
2207 | .guest_phys_addr = addr, | |
2208 | .memory_size = PAGE_SIZE * 3, | |
2209 | .flags = 0, | |
2210 | }; | |
2211 | ||
2212 | ret = kvm_set_memory_region(kvm, &tss_mem, 0); | |
2213 | if (ret) | |
2214 | return ret; | |
bfc6d222 | 2215 | kvm->arch.tss_addr = addr; |
cbc94022 IE |
2216 | return 0; |
2217 | } | |
2218 | ||
6aa8b732 AK |
2219 | static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu) |
2220 | { | |
2221 | struct kvm_guest_debug *dbg = &vcpu->guest_debug; | |
2222 | ||
2223 | set_debugreg(dbg->bp[0], 0); | |
2224 | set_debugreg(dbg->bp[1], 1); | |
2225 | set_debugreg(dbg->bp[2], 2); | |
2226 | set_debugreg(dbg->bp[3], 3); | |
2227 | ||
2228 | if (dbg->singlestep) { | |
2229 | unsigned long flags; | |
2230 | ||
2231 | flags = vmcs_readl(GUEST_RFLAGS); | |
2232 | flags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
2233 | vmcs_writel(GUEST_RFLAGS, flags); | |
2234 | } | |
2235 | } | |
2236 | ||
2237 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
2238 | int vec, u32 err_code) | |
2239 | { | |
ad312c7c | 2240 | if (!vcpu->arch.rmode.active) |
6aa8b732 AK |
2241 | return 0; |
2242 | ||
b3f37707 NK |
2243 | /* |
2244 | * Instruction with address size override prefix opcode 0x67 | |
2245 | * Cause the #SS fault with 0 error code in VM86 mode. | |
2246 | */ | |
2247 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
3427318f | 2248 | if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE) |
6aa8b732 AK |
2249 | return 1; |
2250 | return 0; | |
2251 | } | |
2252 | ||
2253 | static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2254 | { | |
1155f76a | 2255 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
2256 | u32 intr_info, error_code; |
2257 | unsigned long cr2, rip; | |
2258 | u32 vect_info; | |
2259 | enum emulation_result er; | |
2260 | ||
1155f76a | 2261 | vect_info = vmx->idt_vectoring_info; |
6aa8b732 AK |
2262 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
2263 | ||
2264 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
d77c26fc | 2265 | !is_page_fault(intr_info)) |
6aa8b732 | 2266 | printk(KERN_ERR "%s: unexpected, vectoring info 0x%x " |
b8688d51 | 2267 | "intr info 0x%x\n", __func__, vect_info, intr_info); |
6aa8b732 | 2268 | |
85f455f7 | 2269 | if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) { |
6aa8b732 | 2270 | int irq = vect_info & VECTORING_INFO_VECTOR_MASK; |
ad312c7c ZX |
2271 | set_bit(irq, vcpu->arch.irq_pending); |
2272 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
2273 | } |
2274 | ||
1b6269db AK |
2275 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */ |
2276 | return 1; /* already handled by vmx_vcpu_run() */ | |
2ab455cc AL |
2277 | |
2278 | if (is_no_device(intr_info)) { | |
5fd86fcf | 2279 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
2280 | return 1; |
2281 | } | |
2282 | ||
7aa81cc0 | 2283 | if (is_invalid_opcode(intr_info)) { |
571008da | 2284 | er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 2285 | if (er != EMULATE_DONE) |
7ee5d940 | 2286 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
2287 | return 1; |
2288 | } | |
2289 | ||
6aa8b732 AK |
2290 | error_code = 0; |
2291 | rip = vmcs_readl(GUEST_RIP); | |
2e11384c | 2292 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 AK |
2293 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
2294 | if (is_page_fault(intr_info)) { | |
1439442c SY |
2295 | /* EPT won't cause page fault directly */ |
2296 | if (vm_need_ept()) | |
2297 | BUG(); | |
6aa8b732 | 2298 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
2714d1d3 FEL |
2299 | KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2, |
2300 | (u32)((u64)cr2 >> 32), handler); | |
577bdc49 AK |
2301 | if (vect_info & VECTORING_INFO_VALID_MASK) |
2302 | kvm_mmu_unprotect_page_virt(vcpu, cr2); | |
3067714c | 2303 | return kvm_mmu_page_fault(vcpu, cr2, error_code); |
6aa8b732 AK |
2304 | } |
2305 | ||
ad312c7c | 2306 | if (vcpu->arch.rmode.active && |
6aa8b732 | 2307 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, |
72d6e5a0 | 2308 | error_code)) { |
ad312c7c ZX |
2309 | if (vcpu->arch.halt_request) { |
2310 | vcpu->arch.halt_request = 0; | |
72d6e5a0 AK |
2311 | return kvm_emulate_halt(vcpu); |
2312 | } | |
6aa8b732 | 2313 | return 1; |
72d6e5a0 | 2314 | } |
6aa8b732 | 2315 | |
d77c26fc MD |
2316 | if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == |
2317 | (INTR_TYPE_EXCEPTION | 1)) { | |
6aa8b732 AK |
2318 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2319 | return 0; | |
2320 | } | |
2321 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; | |
2322 | kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK; | |
2323 | kvm_run->ex.error_code = error_code; | |
2324 | return 0; | |
2325 | } | |
2326 | ||
2327 | static int handle_external_interrupt(struct kvm_vcpu *vcpu, | |
2328 | struct kvm_run *kvm_run) | |
2329 | { | |
1165f5fe | 2330 | ++vcpu->stat.irq_exits; |
2714d1d3 | 2331 | KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler); |
6aa8b732 AK |
2332 | return 1; |
2333 | } | |
2334 | ||
988ad74f AK |
2335 | static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2336 | { | |
2337 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2338 | return 0; | |
2339 | } | |
6aa8b732 | 2340 | |
6aa8b732 AK |
2341 | static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2342 | { | |
bfdaab09 | 2343 | unsigned long exit_qualification; |
039576c0 AK |
2344 | int size, down, in, string, rep; |
2345 | unsigned port; | |
6aa8b732 | 2346 | |
1165f5fe | 2347 | ++vcpu->stat.io_exits; |
bfdaab09 | 2348 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 2349 | string = (exit_qualification & 16) != 0; |
e70669ab LV |
2350 | |
2351 | if (string) { | |
3427318f LV |
2352 | if (emulate_instruction(vcpu, |
2353 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
2354 | return 0; |
2355 | return 1; | |
2356 | } | |
2357 | ||
2358 | size = (exit_qualification & 7) + 1; | |
2359 | in = (exit_qualification & 8) != 0; | |
039576c0 | 2360 | down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0; |
039576c0 AK |
2361 | rep = (exit_qualification & 32) != 0; |
2362 | port = exit_qualification >> 16; | |
e70669ab | 2363 | |
3090dd73 | 2364 | return kvm_emulate_pio(vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
2365 | } |
2366 | ||
102d8325 IM |
2367 | static void |
2368 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
2369 | { | |
2370 | /* | |
2371 | * Patch in the VMCALL instruction: | |
2372 | */ | |
2373 | hypercall[0] = 0x0f; | |
2374 | hypercall[1] = 0x01; | |
2375 | hypercall[2] = 0xc1; | |
102d8325 IM |
2376 | } |
2377 | ||
6aa8b732 AK |
2378 | static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2379 | { | |
bfdaab09 | 2380 | unsigned long exit_qualification; |
6aa8b732 AK |
2381 | int cr; |
2382 | int reg; | |
2383 | ||
bfdaab09 | 2384 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2385 | cr = exit_qualification & 15; |
2386 | reg = (exit_qualification >> 8) & 15; | |
2387 | switch ((exit_qualification >> 4) & 3) { | |
2388 | case 0: /* mov to cr */ | |
2714d1d3 FEL |
2389 | KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)vcpu->arch.regs[reg], |
2390 | (u32)((u64)vcpu->arch.regs[reg] >> 32), handler); | |
6aa8b732 AK |
2391 | switch (cr) { |
2392 | case 0: | |
2393 | vcpu_load_rsp_rip(vcpu); | |
2d3ad1f4 | 2394 | kvm_set_cr0(vcpu, vcpu->arch.regs[reg]); |
6aa8b732 AK |
2395 | skip_emulated_instruction(vcpu); |
2396 | return 1; | |
2397 | case 3: | |
2398 | vcpu_load_rsp_rip(vcpu); | |
2d3ad1f4 | 2399 | kvm_set_cr3(vcpu, vcpu->arch.regs[reg]); |
6aa8b732 AK |
2400 | skip_emulated_instruction(vcpu); |
2401 | return 1; | |
2402 | case 4: | |
2403 | vcpu_load_rsp_rip(vcpu); | |
2d3ad1f4 | 2404 | kvm_set_cr4(vcpu, vcpu->arch.regs[reg]); |
6aa8b732 AK |
2405 | skip_emulated_instruction(vcpu); |
2406 | return 1; | |
2407 | case 8: | |
2408 | vcpu_load_rsp_rip(vcpu); | |
2d3ad1f4 | 2409 | kvm_set_cr8(vcpu, vcpu->arch.regs[reg]); |
6aa8b732 | 2410 | skip_emulated_instruction(vcpu); |
e5314067 AK |
2411 | if (irqchip_in_kernel(vcpu->kvm)) |
2412 | return 1; | |
253abdee YS |
2413 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2414 | return 0; | |
6aa8b732 AK |
2415 | }; |
2416 | break; | |
25c4c276 AL |
2417 | case 2: /* clts */ |
2418 | vcpu_load_rsp_rip(vcpu); | |
5fd86fcf | 2419 | vmx_fpu_deactivate(vcpu); |
ad312c7c ZX |
2420 | vcpu->arch.cr0 &= ~X86_CR0_TS; |
2421 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf | 2422 | vmx_fpu_activate(vcpu); |
2714d1d3 | 2423 | KVMTRACE_0D(CLTS, vcpu, handler); |
25c4c276 AL |
2424 | skip_emulated_instruction(vcpu); |
2425 | return 1; | |
6aa8b732 AK |
2426 | case 1: /*mov from cr*/ |
2427 | switch (cr) { | |
2428 | case 3: | |
2429 | vcpu_load_rsp_rip(vcpu); | |
ad312c7c | 2430 | vcpu->arch.regs[reg] = vcpu->arch.cr3; |
6aa8b732 | 2431 | vcpu_put_rsp_rip(vcpu); |
2714d1d3 FEL |
2432 | KVMTRACE_3D(CR_READ, vcpu, (u32)cr, |
2433 | (u32)vcpu->arch.regs[reg], | |
2434 | (u32)((u64)vcpu->arch.regs[reg] >> 32), | |
2435 | handler); | |
6aa8b732 AK |
2436 | skip_emulated_instruction(vcpu); |
2437 | return 1; | |
2438 | case 8: | |
6aa8b732 | 2439 | vcpu_load_rsp_rip(vcpu); |
2d3ad1f4 | 2440 | vcpu->arch.regs[reg] = kvm_get_cr8(vcpu); |
6aa8b732 | 2441 | vcpu_put_rsp_rip(vcpu); |
2714d1d3 FEL |
2442 | KVMTRACE_2D(CR_READ, vcpu, (u32)cr, |
2443 | (u32)vcpu->arch.regs[reg], handler); | |
6aa8b732 AK |
2444 | skip_emulated_instruction(vcpu); |
2445 | return 1; | |
2446 | } | |
2447 | break; | |
2448 | case 3: /* lmsw */ | |
2d3ad1f4 | 2449 | kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f); |
6aa8b732 AK |
2450 | |
2451 | skip_emulated_instruction(vcpu); | |
2452 | return 1; | |
2453 | default: | |
2454 | break; | |
2455 | } | |
2456 | kvm_run->exit_reason = 0; | |
f0242478 | 2457 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
2458 | (int)(exit_qualification >> 4) & 3, cr); |
2459 | return 0; | |
2460 | } | |
2461 | ||
2462 | static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2463 | { | |
bfdaab09 | 2464 | unsigned long exit_qualification; |
6aa8b732 AK |
2465 | unsigned long val; |
2466 | int dr, reg; | |
2467 | ||
2468 | /* | |
2469 | * FIXME: this code assumes the host is debugging the guest. | |
2470 | * need to deal with guest debugging itself too. | |
2471 | */ | |
bfdaab09 | 2472 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2473 | dr = exit_qualification & 7; |
2474 | reg = (exit_qualification >> 8) & 15; | |
2475 | vcpu_load_rsp_rip(vcpu); | |
2476 | if (exit_qualification & 16) { | |
2477 | /* mov from dr */ | |
2478 | switch (dr) { | |
2479 | case 6: | |
2480 | val = 0xffff0ff0; | |
2481 | break; | |
2482 | case 7: | |
2483 | val = 0x400; | |
2484 | break; | |
2485 | default: | |
2486 | val = 0; | |
2487 | } | |
ad312c7c | 2488 | vcpu->arch.regs[reg] = val; |
2714d1d3 | 2489 | KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler); |
6aa8b732 AK |
2490 | } else { |
2491 | /* mov to dr */ | |
2492 | } | |
2493 | vcpu_put_rsp_rip(vcpu); | |
2494 | skip_emulated_instruction(vcpu); | |
2495 | return 1; | |
2496 | } | |
2497 | ||
2498 | static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2499 | { | |
06465c5a AK |
2500 | kvm_emulate_cpuid(vcpu); |
2501 | return 1; | |
6aa8b732 AK |
2502 | } |
2503 | ||
2504 | static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2505 | { | |
ad312c7c | 2506 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2507 | u64 data; |
2508 | ||
2509 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
c1a5d4f9 | 2510 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
2511 | return 1; |
2512 | } | |
2513 | ||
2714d1d3 FEL |
2514 | KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32), |
2515 | handler); | |
2516 | ||
6aa8b732 | 2517 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
ad312c7c ZX |
2518 | vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u; |
2519 | vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
6aa8b732 AK |
2520 | skip_emulated_instruction(vcpu); |
2521 | return 1; | |
2522 | } | |
2523 | ||
2524 | static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2525 | { | |
ad312c7c ZX |
2526 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
2527 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
2528 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 2529 | |
2714d1d3 FEL |
2530 | KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32), |
2531 | handler); | |
2532 | ||
6aa8b732 | 2533 | if (vmx_set_msr(vcpu, ecx, data) != 0) { |
c1a5d4f9 | 2534 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
2535 | return 1; |
2536 | } | |
2537 | ||
2538 | skip_emulated_instruction(vcpu); | |
2539 | return 1; | |
2540 | } | |
2541 | ||
6e5d865c YS |
2542 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu, |
2543 | struct kvm_run *kvm_run) | |
2544 | { | |
2545 | return 1; | |
2546 | } | |
2547 | ||
6aa8b732 AK |
2548 | static int handle_interrupt_window(struct kvm_vcpu *vcpu, |
2549 | struct kvm_run *kvm_run) | |
2550 | { | |
85f455f7 ED |
2551 | u32 cpu_based_vm_exec_control; |
2552 | ||
2553 | /* clear pending irq */ | |
2554 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2555 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
2556 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 FEL |
2557 | |
2558 | KVMTRACE_0D(PEND_INTR, vcpu, handler); | |
2559 | ||
c1150d8c DL |
2560 | /* |
2561 | * If the user space waits to inject interrupts, exit as soon as | |
2562 | * possible | |
2563 | */ | |
2564 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 2565 | !vcpu->arch.irq_summary) { |
c1150d8c | 2566 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1165f5fe | 2567 | ++vcpu->stat.irq_window_exits; |
c1150d8c DL |
2568 | return 0; |
2569 | } | |
6aa8b732 AK |
2570 | return 1; |
2571 | } | |
2572 | ||
2573 | static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2574 | { | |
2575 | skip_emulated_instruction(vcpu); | |
d3bef15f | 2576 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
2577 | } |
2578 | ||
c21415e8 IM |
2579 | static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2580 | { | |
510043da | 2581 | skip_emulated_instruction(vcpu); |
7aa81cc0 AL |
2582 | kvm_emulate_hypercall(vcpu); |
2583 | return 1; | |
c21415e8 IM |
2584 | } |
2585 | ||
e5edaa01 ED |
2586 | static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2587 | { | |
2588 | skip_emulated_instruction(vcpu); | |
2589 | /* TODO: Add support for VT-d/pass-through device */ | |
2590 | return 1; | |
2591 | } | |
2592 | ||
f78e0e2e SY |
2593 | static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2594 | { | |
2595 | u64 exit_qualification; | |
2596 | enum emulation_result er; | |
2597 | unsigned long offset; | |
2598 | ||
2599 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2600 | offset = exit_qualification & 0xffful; | |
2601 | ||
2602 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
2603 | ||
2604 | if (er != EMULATE_DONE) { | |
2605 | printk(KERN_ERR | |
2606 | "Fail to handle apic access vmexit! Offset is 0x%lx\n", | |
2607 | offset); | |
2608 | return -ENOTSUPP; | |
2609 | } | |
2610 | return 1; | |
2611 | } | |
2612 | ||
37817f29 IE |
2613 | static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2614 | { | |
2615 | unsigned long exit_qualification; | |
2616 | u16 tss_selector; | |
2617 | int reason; | |
2618 | ||
2619 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
2620 | ||
2621 | reason = (u32)exit_qualification >> 30; | |
2622 | tss_selector = exit_qualification; | |
2623 | ||
2624 | return kvm_task_switch(vcpu, tss_selector, reason); | |
2625 | } | |
2626 | ||
1439442c SY |
2627 | static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2628 | { | |
2629 | u64 exit_qualification; | |
2630 | enum emulation_result er; | |
2631 | gpa_t gpa; | |
2632 | unsigned long hva; | |
2633 | int gla_validity; | |
2634 | int r; | |
2635 | ||
2636 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2637 | ||
2638 | if (exit_qualification & (1 << 6)) { | |
2639 | printk(KERN_ERR "EPT: GPA exceeds GAW!\n"); | |
2640 | return -ENOTSUPP; | |
2641 | } | |
2642 | ||
2643 | gla_validity = (exit_qualification >> 7) & 0x3; | |
2644 | if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) { | |
2645 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | |
2646 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
2647 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
2648 | (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS)); | |
2649 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", | |
2650 | (long unsigned int)exit_qualification); | |
2651 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
2652 | kvm_run->hw.hardware_exit_reason = 0; | |
2653 | return -ENOTSUPP; | |
2654 | } | |
2655 | ||
2656 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
2657 | hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT); | |
2658 | if (!kvm_is_error_hva(hva)) { | |
2659 | r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0); | |
2660 | if (r < 0) { | |
2661 | printk(KERN_ERR "EPT: Not enough memory!\n"); | |
2662 | return -ENOMEM; | |
2663 | } | |
2664 | return 1; | |
2665 | } else { | |
2666 | /* must be MMIO */ | |
2667 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
2668 | ||
2669 | if (er == EMULATE_FAIL) { | |
2670 | printk(KERN_ERR | |
2671 | "EPT: Fail to handle EPT violation vmexit!er is %d\n", | |
2672 | er); | |
2673 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
2674 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
2675 | (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS)); | |
2676 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", | |
2677 | (long unsigned int)exit_qualification); | |
2678 | return -ENOTSUPP; | |
2679 | } else if (er == EMULATE_DO_MMIO) | |
2680 | return 0; | |
2681 | } | |
2682 | return 1; | |
2683 | } | |
2684 | ||
f08864b4 SY |
2685 | static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2686 | { | |
2687 | u32 cpu_based_vm_exec_control; | |
2688 | ||
2689 | /* clear pending NMI */ | |
2690 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2691 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
2692 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2693 | ++vcpu->stat.nmi_window_exits; | |
2694 | ||
2695 | return 1; | |
2696 | } | |
2697 | ||
6aa8b732 AK |
2698 | /* |
2699 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
2700 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
2701 | * to be done to userspace and return 0. | |
2702 | */ | |
2703 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, | |
2704 | struct kvm_run *kvm_run) = { | |
2705 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, | |
2706 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 2707 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 2708 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 2709 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
2710 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
2711 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
2712 | [EXIT_REASON_CPUID] = handle_cpuid, | |
2713 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
2714 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
2715 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
2716 | [EXIT_REASON_HLT] = handle_halt, | |
c21415e8 | 2717 | [EXIT_REASON_VMCALL] = handle_vmcall, |
f78e0e2e SY |
2718 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
2719 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
e5edaa01 | 2720 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
37817f29 | 2721 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
1439442c | 2722 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
6aa8b732 AK |
2723 | }; |
2724 | ||
2725 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 2726 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 AK |
2727 | |
2728 | /* | |
2729 | * The guest has exited. See if we can fix it or if we need userspace | |
2730 | * assistance. | |
2731 | */ | |
2732 | static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |
2733 | { | |
6aa8b732 | 2734 | u32 exit_reason = vmcs_read32(VM_EXIT_REASON); |
29bd8a78 | 2735 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1155f76a | 2736 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 2737 | |
2714d1d3 FEL |
2738 | KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)vmcs_readl(GUEST_RIP), |
2739 | (u32)((u64)vmcs_readl(GUEST_RIP) >> 32), entryexit); | |
2740 | ||
1439442c SY |
2741 | /* Access CR3 don't cause VMExit in paging mode, so we need |
2742 | * to sync with guest real CR3. */ | |
2743 | if (vm_need_ept() && is_paging(vcpu)) { | |
2744 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
2745 | ept_load_pdptrs(vcpu); | |
2746 | } | |
2747 | ||
29bd8a78 AK |
2748 | if (unlikely(vmx->fail)) { |
2749 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
2750 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2751 | = vmcs_read32(VM_INSTRUCTION_ERROR); | |
2752 | return 0; | |
2753 | } | |
6aa8b732 | 2754 | |
d77c26fc | 2755 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c SY |
2756 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
2757 | exit_reason != EXIT_REASON_EPT_VIOLATION)) | |
6aa8b732 | 2758 | printk(KERN_WARNING "%s: unexpected, valid vectoring info and " |
b8688d51 | 2759 | "exit reason is 0x%x\n", __func__, exit_reason); |
6aa8b732 AK |
2760 | if (exit_reason < kvm_vmx_max_exit_handlers |
2761 | && kvm_vmx_exit_handlers[exit_reason]) | |
2762 | return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run); | |
2763 | else { | |
2764 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
2765 | kvm_run->hw.hardware_exit_reason = exit_reason; | |
2766 | } | |
2767 | return 0; | |
2768 | } | |
2769 | ||
6e5d865c YS |
2770 | static void update_tpr_threshold(struct kvm_vcpu *vcpu) |
2771 | { | |
2772 | int max_irr, tpr; | |
2773 | ||
2774 | if (!vm_need_tpr_shadow(vcpu->kvm)) | |
2775 | return; | |
2776 | ||
2777 | if (!kvm_lapic_enabled(vcpu) || | |
2778 | ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) { | |
2779 | vmcs_write32(TPR_THRESHOLD, 0); | |
2780 | return; | |
2781 | } | |
2782 | ||
2783 | tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4; | |
2784 | vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4); | |
2785 | } | |
2786 | ||
85f455f7 ED |
2787 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
2788 | { | |
2789 | u32 cpu_based_vm_exec_control; | |
2790 | ||
2791 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2792 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
2793 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2794 | } | |
2795 | ||
f08864b4 SY |
2796 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
2797 | { | |
2798 | u32 cpu_based_vm_exec_control; | |
2799 | ||
2800 | if (!cpu_has_virtual_nmis()) | |
2801 | return; | |
2802 | ||
2803 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2804 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
2805 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2806 | } | |
2807 | ||
2808 | static int vmx_nmi_enabled(struct kvm_vcpu *vcpu) | |
2809 | { | |
2810 | u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2811 | return !(guest_intr & (GUEST_INTR_STATE_NMI | | |
2812 | GUEST_INTR_STATE_MOV_SS | | |
2813 | GUEST_INTR_STATE_STI)); | |
2814 | } | |
2815 | ||
2816 | static int vmx_irq_enabled(struct kvm_vcpu *vcpu) | |
2817 | { | |
2818 | u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2819 | return (!(guest_intr & (GUEST_INTR_STATE_MOV_SS | | |
2820 | GUEST_INTR_STATE_STI)) && | |
2821 | (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF)); | |
2822 | } | |
2823 | ||
2824 | static void enable_intr_window(struct kvm_vcpu *vcpu) | |
2825 | { | |
2826 | if (vcpu->arch.nmi_pending) | |
2827 | enable_nmi_window(vcpu); | |
2828 | else if (kvm_cpu_has_interrupt(vcpu)) | |
2829 | enable_irq_window(vcpu); | |
2830 | } | |
2831 | ||
85f455f7 ED |
2832 | static void vmx_intr_assist(struct kvm_vcpu *vcpu) |
2833 | { | |
1155f76a | 2834 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
f08864b4 | 2835 | u32 idtv_info_field, intr_info_field, exit_intr_info_field; |
1b9778da | 2836 | int vector; |
85f455f7 | 2837 | |
6e5d865c YS |
2838 | update_tpr_threshold(vcpu); |
2839 | ||
85f455f7 | 2840 | intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD); |
f08864b4 | 2841 | exit_intr_info_field = vmcs_read32(VM_EXIT_INTR_INFO); |
1155f76a | 2842 | idtv_info_field = vmx->idt_vectoring_info; |
85f455f7 ED |
2843 | if (intr_info_field & INTR_INFO_VALID_MASK) { |
2844 | if (idtv_info_field & INTR_INFO_VALID_MASK) { | |
2845 | /* TODO: fault when IDT_Vectoring */ | |
9584bf2c RH |
2846 | if (printk_ratelimit()) |
2847 | printk(KERN_ERR "Fault when IDT_Vectoring\n"); | |
85f455f7 | 2848 | } |
f08864b4 | 2849 | enable_intr_window(vcpu); |
85f455f7 ED |
2850 | return; |
2851 | } | |
2852 | if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) { | |
9c8cba37 AK |
2853 | if ((idtv_info_field & VECTORING_INFO_TYPE_MASK) |
2854 | == INTR_TYPE_EXT_INTR | |
ad312c7c | 2855 | && vcpu->arch.rmode.active) { |
9c8cba37 AK |
2856 | u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK; |
2857 | ||
2858 | vmx_inject_irq(vcpu, vect); | |
f08864b4 | 2859 | enable_intr_window(vcpu); |
9c8cba37 AK |
2860 | return; |
2861 | } | |
2862 | ||
2714d1d3 FEL |
2863 | KVMTRACE_1D(REDELIVER_EVT, vcpu, idtv_info_field, handler); |
2864 | ||
f08864b4 SY |
2865 | /* |
2866 | * SDM 3: 25.7.1.2 | |
2867 | * Clear bit "block by NMI" before VM entry if a NMI delivery | |
2868 | * faulted. | |
2869 | */ | |
2870 | if ((idtv_info_field & VECTORING_INFO_TYPE_MASK) | |
2871 | == INTR_TYPE_NMI_INTR && cpu_has_virtual_nmis()) | |
2872 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
2873 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & | |
2874 | ~GUEST_INTR_STATE_NMI); | |
2875 | ||
2876 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field | |
2877 | & ~INTR_INFO_RESVD_BITS_MASK); | |
85f455f7 ED |
2878 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, |
2879 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
2880 | ||
2e11384c | 2881 | if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK)) |
85f455f7 ED |
2882 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, |
2883 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
f08864b4 | 2884 | enable_intr_window(vcpu); |
85f455f7 ED |
2885 | return; |
2886 | } | |
f08864b4 SY |
2887 | if (cpu_has_virtual_nmis()) { |
2888 | /* | |
2889 | * SDM 3: 25.7.1.2 | |
2890 | * Re-set bit "block by NMI" before VM entry if vmexit caused by | |
2891 | * a guest IRET fault. | |
2892 | */ | |
2893 | if ((exit_intr_info_field & INTR_INFO_UNBLOCK_NMI) && | |
2894 | (exit_intr_info_field & INTR_INFO_VECTOR_MASK) != 8) | |
2895 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
2896 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | | |
2897 | GUEST_INTR_STATE_NMI); | |
2898 | else if (vcpu->arch.nmi_pending) { | |
2899 | if (vmx_nmi_enabled(vcpu)) | |
2900 | vmx_inject_nmi(vcpu); | |
2901 | enable_intr_window(vcpu); | |
2902 | return; | |
2903 | } | |
2904 | ||
2905 | } | |
2906 | if (!kvm_cpu_has_interrupt(vcpu)) | |
85f455f7 | 2907 | return; |
f08864b4 | 2908 | if (vmx_irq_enabled(vcpu)) { |
1b9778da ED |
2909 | vector = kvm_cpu_get_interrupt(vcpu); |
2910 | vmx_inject_irq(vcpu, vector); | |
2911 | kvm_timer_intr_post(vcpu, vector); | |
2912 | } else | |
85f455f7 ED |
2913 | enable_irq_window(vcpu); |
2914 | } | |
2915 | ||
9c8cba37 AK |
2916 | /* |
2917 | * Failure to inject an interrupt should give us the information | |
2918 | * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs | |
2919 | * when fetching the interrupt redirection bitmap in the real-mode | |
2920 | * tss, this doesn't happen. So we do it ourselves. | |
2921 | */ | |
2922 | static void fixup_rmode_irq(struct vcpu_vmx *vmx) | |
2923 | { | |
2924 | vmx->rmode.irq.pending = 0; | |
2925 | if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip) | |
2926 | return; | |
2927 | vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip); | |
2928 | if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) { | |
2929 | vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK; | |
2930 | vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR; | |
2931 | return; | |
2932 | } | |
2933 | vmx->idt_vectoring_info = | |
2934 | VECTORING_INFO_VALID_MASK | |
2935 | | INTR_TYPE_EXT_INTR | |
2936 | | vmx->rmode.irq.vector; | |
2937 | } | |
2938 | ||
04d2cc77 | 2939 | static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6aa8b732 | 2940 | { |
a2fa3e9f | 2941 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1b6269db | 2942 | u32 intr_info; |
e6adf283 AK |
2943 | |
2944 | /* | |
2945 | * Loading guest fpu may have cleared host cr0.ts | |
2946 | */ | |
2947 | vmcs_writel(HOST_CR0, read_cr0()); | |
2948 | ||
d77c26fc | 2949 | asm( |
6aa8b732 | 2950 | /* Store host registers */ |
05b3e0c2 | 2951 | #ifdef CONFIG_X86_64 |
c2036300 | 2952 | "push %%rdx; push %%rbp;" |
6aa8b732 | 2953 | "push %%rcx \n\t" |
6aa8b732 | 2954 | #else |
ff593e5a LV |
2955 | "push %%edx; push %%ebp;" |
2956 | "push %%ecx \n\t" | |
6aa8b732 | 2957 | #endif |
4ecac3fd | 2958 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
6aa8b732 | 2959 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 2960 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 2961 | /* Load guest registers. Don't clobber flags. */ |
05b3e0c2 | 2962 | #ifdef CONFIG_X86_64 |
e08aa78a | 2963 | "mov %c[cr2](%0), %%rax \n\t" |
6aa8b732 | 2964 | "mov %%rax, %%cr2 \n\t" |
e08aa78a AK |
2965 | "mov %c[rax](%0), %%rax \n\t" |
2966 | "mov %c[rbx](%0), %%rbx \n\t" | |
2967 | "mov %c[rdx](%0), %%rdx \n\t" | |
2968 | "mov %c[rsi](%0), %%rsi \n\t" | |
2969 | "mov %c[rdi](%0), %%rdi \n\t" | |
2970 | "mov %c[rbp](%0), %%rbp \n\t" | |
2971 | "mov %c[r8](%0), %%r8 \n\t" | |
2972 | "mov %c[r9](%0), %%r9 \n\t" | |
2973 | "mov %c[r10](%0), %%r10 \n\t" | |
2974 | "mov %c[r11](%0), %%r11 \n\t" | |
2975 | "mov %c[r12](%0), %%r12 \n\t" | |
2976 | "mov %c[r13](%0), %%r13 \n\t" | |
2977 | "mov %c[r14](%0), %%r14 \n\t" | |
2978 | "mov %c[r15](%0), %%r15 \n\t" | |
2979 | "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */ | |
6aa8b732 | 2980 | #else |
e08aa78a | 2981 | "mov %c[cr2](%0), %%eax \n\t" |
6aa8b732 | 2982 | "mov %%eax, %%cr2 \n\t" |
e08aa78a AK |
2983 | "mov %c[rax](%0), %%eax \n\t" |
2984 | "mov %c[rbx](%0), %%ebx \n\t" | |
2985 | "mov %c[rdx](%0), %%edx \n\t" | |
2986 | "mov %c[rsi](%0), %%esi \n\t" | |
2987 | "mov %c[rdi](%0), %%edi \n\t" | |
2988 | "mov %c[rbp](%0), %%ebp \n\t" | |
2989 | "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */ | |
6aa8b732 AK |
2990 | #endif |
2991 | /* Enter guest mode */ | |
cd2276a7 | 2992 | "jne .Llaunched \n\t" |
4ecac3fd | 2993 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
cd2276a7 | 2994 | "jmp .Lkvm_vmx_return \n\t" |
4ecac3fd | 2995 | ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t" |
cd2276a7 | 2996 | ".Lkvm_vmx_return: " |
6aa8b732 | 2997 | /* Save guest registers, load host registers, keep flags */ |
05b3e0c2 | 2998 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
2999 | "xchg %0, (%%rsp) \n\t" |
3000 | "mov %%rax, %c[rax](%0) \n\t" | |
3001 | "mov %%rbx, %c[rbx](%0) \n\t" | |
3002 | "pushq (%%rsp); popq %c[rcx](%0) \n\t" | |
3003 | "mov %%rdx, %c[rdx](%0) \n\t" | |
3004 | "mov %%rsi, %c[rsi](%0) \n\t" | |
3005 | "mov %%rdi, %c[rdi](%0) \n\t" | |
3006 | "mov %%rbp, %c[rbp](%0) \n\t" | |
3007 | "mov %%r8, %c[r8](%0) \n\t" | |
3008 | "mov %%r9, %c[r9](%0) \n\t" | |
3009 | "mov %%r10, %c[r10](%0) \n\t" | |
3010 | "mov %%r11, %c[r11](%0) \n\t" | |
3011 | "mov %%r12, %c[r12](%0) \n\t" | |
3012 | "mov %%r13, %c[r13](%0) \n\t" | |
3013 | "mov %%r14, %c[r14](%0) \n\t" | |
3014 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 3015 | "mov %%cr2, %%rax \n\t" |
e08aa78a | 3016 | "mov %%rax, %c[cr2](%0) \n\t" |
6aa8b732 | 3017 | |
e08aa78a | 3018 | "pop %%rbp; pop %%rbp; pop %%rdx \n\t" |
6aa8b732 | 3019 | #else |
e08aa78a AK |
3020 | "xchg %0, (%%esp) \n\t" |
3021 | "mov %%eax, %c[rax](%0) \n\t" | |
3022 | "mov %%ebx, %c[rbx](%0) \n\t" | |
3023 | "pushl (%%esp); popl %c[rcx](%0) \n\t" | |
3024 | "mov %%edx, %c[rdx](%0) \n\t" | |
3025 | "mov %%esi, %c[rsi](%0) \n\t" | |
3026 | "mov %%edi, %c[rdi](%0) \n\t" | |
3027 | "mov %%ebp, %c[rbp](%0) \n\t" | |
6aa8b732 | 3028 | "mov %%cr2, %%eax \n\t" |
e08aa78a | 3029 | "mov %%eax, %c[cr2](%0) \n\t" |
6aa8b732 | 3030 | |
e08aa78a | 3031 | "pop %%ebp; pop %%ebp; pop %%edx \n\t" |
6aa8b732 | 3032 | #endif |
e08aa78a AK |
3033 | "setbe %c[fail](%0) \n\t" |
3034 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), | |
3035 | [launched]"i"(offsetof(struct vcpu_vmx, launched)), | |
3036 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), | |
ad312c7c ZX |
3037 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
3038 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
3039 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3040 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3041 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3042 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3043 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 3044 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3045 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
3046 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
3047 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
3048 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
3049 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
3050 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
3051 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
3052 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 3053 | #endif |
ad312c7c | 3054 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)) |
c2036300 LV |
3055 | : "cc", "memory" |
3056 | #ifdef CONFIG_X86_64 | |
3057 | , "rbx", "rdi", "rsi" | |
3058 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
ff593e5a LV |
3059 | #else |
3060 | , "ebx", "edi", "rsi" | |
c2036300 LV |
3061 | #endif |
3062 | ); | |
6aa8b732 | 3063 | |
1155f76a | 3064 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
9c8cba37 AK |
3065 | if (vmx->rmode.irq.pending) |
3066 | fixup_rmode_irq(vmx); | |
1155f76a | 3067 | |
ad312c7c | 3068 | vcpu->arch.interrupt_window_open = |
f08864b4 SY |
3069 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
3070 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)) == 0; | |
6aa8b732 | 3071 | |
d77c26fc | 3072 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
15ad7146 | 3073 | vmx->launched = 1; |
1b6269db AK |
3074 | |
3075 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
3076 | ||
3077 | /* We need to handle NMIs before interrupts are enabled */ | |
f08864b4 SY |
3078 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200 && |
3079 | (intr_info & INTR_INFO_VALID_MASK)) { | |
2714d1d3 | 3080 | KVMTRACE_0D(NMI, vcpu, handler); |
1b6269db | 3081 | asm("int $2"); |
2714d1d3 | 3082 | } |
6aa8b732 AK |
3083 | } |
3084 | ||
6aa8b732 AK |
3085 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) |
3086 | { | |
a2fa3e9f GH |
3087 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3088 | ||
3089 | if (vmx->vmcs) { | |
543e4243 | 3090 | vcpu_clear(vmx); |
a2fa3e9f GH |
3091 | free_vmcs(vmx->vmcs); |
3092 | vmx->vmcs = NULL; | |
6aa8b732 AK |
3093 | } |
3094 | } | |
3095 | ||
3096 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
3097 | { | |
fb3f0f51 RR |
3098 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3099 | ||
2384d2b3 SY |
3100 | spin_lock(&vmx_vpid_lock); |
3101 | if (vmx->vpid != 0) | |
3102 | __clear_bit(vmx->vpid, vmx_vpid_bitmap); | |
3103 | spin_unlock(&vmx_vpid_lock); | |
6aa8b732 | 3104 | vmx_free_vmcs(vcpu); |
fb3f0f51 RR |
3105 | kfree(vmx->host_msrs); |
3106 | kfree(vmx->guest_msrs); | |
3107 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 3108 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
3109 | } |
3110 | ||
fb3f0f51 | 3111 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 3112 | { |
fb3f0f51 | 3113 | int err; |
c16f862d | 3114 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 3115 | int cpu; |
6aa8b732 | 3116 | |
a2fa3e9f | 3117 | if (!vmx) |
fb3f0f51 RR |
3118 | return ERR_PTR(-ENOMEM); |
3119 | ||
2384d2b3 | 3120 | allocate_vpid(vmx); |
1439442c SY |
3121 | if (id == 0 && vm_need_ept()) { |
3122 | kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK | | |
3123 | VMX_EPT_WRITABLE_MASK | | |
3124 | VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT); | |
3125 | kvm_mmu_set_mask_ptes(0ull, VMX_EPT_FAKE_ACCESSED_MASK, | |
3126 | VMX_EPT_FAKE_DIRTY_MASK, 0ull, | |
3127 | VMX_EPT_EXECUTABLE_MASK); | |
3128 | kvm_enable_tdp(); | |
3129 | } | |
2384d2b3 | 3130 | |
fb3f0f51 RR |
3131 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
3132 | if (err) | |
3133 | goto free_vcpu; | |
965b58a5 | 3134 | |
a2fa3e9f | 3135 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
fb3f0f51 RR |
3136 | if (!vmx->guest_msrs) { |
3137 | err = -ENOMEM; | |
3138 | goto uninit_vcpu; | |
3139 | } | |
965b58a5 | 3140 | |
a2fa3e9f GH |
3141 | vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
3142 | if (!vmx->host_msrs) | |
fb3f0f51 | 3143 | goto free_guest_msrs; |
965b58a5 | 3144 | |
a2fa3e9f GH |
3145 | vmx->vmcs = alloc_vmcs(); |
3146 | if (!vmx->vmcs) | |
fb3f0f51 | 3147 | goto free_msrs; |
a2fa3e9f GH |
3148 | |
3149 | vmcs_clear(vmx->vmcs); | |
3150 | ||
15ad7146 AK |
3151 | cpu = get_cpu(); |
3152 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
8b9cf98c | 3153 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 3154 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 3155 | put_cpu(); |
fb3f0f51 RR |
3156 | if (err) |
3157 | goto free_vmcs; | |
5e4a0b3c MT |
3158 | if (vm_need_virtualize_apic_accesses(kvm)) |
3159 | if (alloc_apic_access_page(kvm) != 0) | |
3160 | goto free_vmcs; | |
fb3f0f51 | 3161 | |
b7ebfb05 SY |
3162 | if (vm_need_ept()) |
3163 | if (alloc_identity_pagetable(kvm) != 0) | |
3164 | goto free_vmcs; | |
3165 | ||
fb3f0f51 RR |
3166 | return &vmx->vcpu; |
3167 | ||
3168 | free_vmcs: | |
3169 | free_vmcs(vmx->vmcs); | |
3170 | free_msrs: | |
3171 | kfree(vmx->host_msrs); | |
3172 | free_guest_msrs: | |
3173 | kfree(vmx->guest_msrs); | |
3174 | uninit_vcpu: | |
3175 | kvm_vcpu_uninit(&vmx->vcpu); | |
3176 | free_vcpu: | |
a4770347 | 3177 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 3178 | return ERR_PTR(err); |
6aa8b732 AK |
3179 | } |
3180 | ||
002c7f7c YS |
3181 | static void __init vmx_check_processor_compat(void *rtn) |
3182 | { | |
3183 | struct vmcs_config vmcs_conf; | |
3184 | ||
3185 | *(int *)rtn = 0; | |
3186 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
3187 | *(int *)rtn = -EIO; | |
3188 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
3189 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
3190 | smp_processor_id()); | |
3191 | *(int *)rtn = -EIO; | |
3192 | } | |
3193 | } | |
3194 | ||
67253af5 SY |
3195 | static int get_ept_level(void) |
3196 | { | |
3197 | return VMX_EPT_DEFAULT_GAW + 1; | |
3198 | } | |
3199 | ||
cbdd1bea | 3200 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
3201 | .cpu_has_kvm_support = cpu_has_kvm_support, |
3202 | .disabled_by_bios = vmx_disabled_by_bios, | |
3203 | .hardware_setup = hardware_setup, | |
3204 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 3205 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
3206 | .hardware_enable = hardware_enable, |
3207 | .hardware_disable = hardware_disable, | |
774ead3a | 3208 | .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses, |
6aa8b732 AK |
3209 | |
3210 | .vcpu_create = vmx_create_vcpu, | |
3211 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 3212 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 3213 | |
04d2cc77 | 3214 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
3215 | .vcpu_load = vmx_vcpu_load, |
3216 | .vcpu_put = vmx_vcpu_put, | |
3217 | ||
3218 | .set_guest_debug = set_guest_debug, | |
04d2cc77 | 3219 | .guest_debug_pre = kvm_guest_debug_pre, |
6aa8b732 AK |
3220 | .get_msr = vmx_get_msr, |
3221 | .set_msr = vmx_set_msr, | |
3222 | .get_segment_base = vmx_get_segment_base, | |
3223 | .get_segment = vmx_get_segment, | |
3224 | .set_segment = vmx_set_segment, | |
2e4d2653 | 3225 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 3226 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
25c4c276 | 3227 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 3228 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
3229 | .set_cr3 = vmx_set_cr3, |
3230 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 3231 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
3232 | .get_idt = vmx_get_idt, |
3233 | .set_idt = vmx_set_idt, | |
3234 | .get_gdt = vmx_get_gdt, | |
3235 | .set_gdt = vmx_set_gdt, | |
3236 | .cache_regs = vcpu_load_rsp_rip, | |
3237 | .decache_regs = vcpu_put_rsp_rip, | |
3238 | .get_rflags = vmx_get_rflags, | |
3239 | .set_rflags = vmx_set_rflags, | |
3240 | ||
3241 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 3242 | |
6aa8b732 | 3243 | .run = vmx_vcpu_run, |
04d2cc77 | 3244 | .handle_exit = kvm_handle_exit, |
6aa8b732 | 3245 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 3246 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 ED |
3247 | .get_irq = vmx_get_irq, |
3248 | .set_irq = vmx_inject_irq, | |
298101da AK |
3249 | .queue_exception = vmx_queue_exception, |
3250 | .exception_injected = vmx_exception_injected, | |
04d2cc77 AK |
3251 | .inject_pending_irq = vmx_intr_assist, |
3252 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
3253 | |
3254 | .set_tss_addr = vmx_set_tss_addr, | |
67253af5 | 3255 | .get_tdp_level = get_ept_level, |
6aa8b732 AK |
3256 | }; |
3257 | ||
3258 | static int __init vmx_init(void) | |
3259 | { | |
25c5f225 | 3260 | void *va; |
fdef3ad1 HQ |
3261 | int r; |
3262 | ||
3263 | vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
3264 | if (!vmx_io_bitmap_a) | |
3265 | return -ENOMEM; | |
3266 | ||
3267 | vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
3268 | if (!vmx_io_bitmap_b) { | |
3269 | r = -ENOMEM; | |
3270 | goto out; | |
3271 | } | |
3272 | ||
25c5f225 SY |
3273 | vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); |
3274 | if (!vmx_msr_bitmap) { | |
3275 | r = -ENOMEM; | |
3276 | goto out1; | |
3277 | } | |
3278 | ||
fdef3ad1 HQ |
3279 | /* |
3280 | * Allow direct access to the PC debug port (it is often used for I/O | |
3281 | * delays, but the vmexits simply slow things down). | |
3282 | */ | |
25c5f225 SY |
3283 | va = kmap(vmx_io_bitmap_a); |
3284 | memset(va, 0xff, PAGE_SIZE); | |
3285 | clear_bit(0x80, va); | |
cd0536d7 | 3286 | kunmap(vmx_io_bitmap_a); |
fdef3ad1 | 3287 | |
25c5f225 SY |
3288 | va = kmap(vmx_io_bitmap_b); |
3289 | memset(va, 0xff, PAGE_SIZE); | |
cd0536d7 | 3290 | kunmap(vmx_io_bitmap_b); |
fdef3ad1 | 3291 | |
25c5f225 SY |
3292 | va = kmap(vmx_msr_bitmap); |
3293 | memset(va, 0xff, PAGE_SIZE); | |
3294 | kunmap(vmx_msr_bitmap); | |
3295 | ||
2384d2b3 SY |
3296 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
3297 | ||
cb498ea2 | 3298 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE); |
fdef3ad1 | 3299 | if (r) |
25c5f225 SY |
3300 | goto out2; |
3301 | ||
3302 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE); | |
3303 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE); | |
3304 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS); | |
3305 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP); | |
3306 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP); | |
fdef3ad1 | 3307 | |
5ec5726a | 3308 | if (vm_need_ept()) |
1439442c SY |
3309 | bypass_guest_pf = 0; |
3310 | ||
c7addb90 AK |
3311 | if (bypass_guest_pf) |
3312 | kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull); | |
3313 | ||
1439442c SY |
3314 | ept_sync_global(); |
3315 | ||
fdef3ad1 HQ |
3316 | return 0; |
3317 | ||
25c5f225 SY |
3318 | out2: |
3319 | __free_page(vmx_msr_bitmap); | |
fdef3ad1 HQ |
3320 | out1: |
3321 | __free_page(vmx_io_bitmap_b); | |
3322 | out: | |
3323 | __free_page(vmx_io_bitmap_a); | |
3324 | return r; | |
6aa8b732 AK |
3325 | } |
3326 | ||
3327 | static void __exit vmx_exit(void) | |
3328 | { | |
25c5f225 | 3329 | __free_page(vmx_msr_bitmap); |
fdef3ad1 HQ |
3330 | __free_page(vmx_io_bitmap_b); |
3331 | __free_page(vmx_io_bitmap_a); | |
3332 | ||
cb498ea2 | 3333 | kvm_exit(); |
6aa8b732 AK |
3334 | } |
3335 | ||
3336 | module_init(vmx_init) | |
3337 | module_exit(vmx_exit) |