]>
Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
8 | * | |
9 | * Authors: | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
17 | ||
85f455f7 | 18 | #include "irq.h" |
6aa8b732 | 19 | #include "vmx.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
edf88417 | 22 | #include <linux/kvm_host.h> |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/mm.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
c7addb90 | 28 | #include <linux/moduleparam.h> |
e495606d | 29 | |
6aa8b732 | 30 | #include <asm/io.h> |
3b3be0d1 | 31 | #include <asm/desc.h> |
6aa8b732 | 32 | |
6aa8b732 AK |
33 | MODULE_AUTHOR("Qumranet"); |
34 | MODULE_LICENSE("GPL"); | |
35 | ||
c7addb90 AK |
36 | static int bypass_guest_pf = 1; |
37 | module_param(bypass_guest_pf, bool, 0); | |
38 | ||
2384d2b3 SY |
39 | static int enable_vpid = 1; |
40 | module_param(enable_vpid, bool, 0); | |
41 | ||
4c9fc8ef AK |
42 | static int flexpriority_enabled = 1; |
43 | module_param(flexpriority_enabled, bool, 0); | |
44 | ||
d56f546d SY |
45 | static int enable_ept; |
46 | module_param(enable_ept, bool, 0); | |
47 | ||
a2fa3e9f GH |
48 | struct vmcs { |
49 | u32 revision_id; | |
50 | u32 abort; | |
51 | char data[0]; | |
52 | }; | |
53 | ||
54 | struct vcpu_vmx { | |
fb3f0f51 | 55 | struct kvm_vcpu vcpu; |
a2fa3e9f | 56 | int launched; |
29bd8a78 | 57 | u8 fail; |
1155f76a | 58 | u32 idt_vectoring_info; |
a2fa3e9f GH |
59 | struct kvm_msr_entry *guest_msrs; |
60 | struct kvm_msr_entry *host_msrs; | |
61 | int nmsrs; | |
62 | int save_nmsrs; | |
63 | int msr_offset_efer; | |
64 | #ifdef CONFIG_X86_64 | |
65 | int msr_offset_kernel_gs_base; | |
66 | #endif | |
67 | struct vmcs *vmcs; | |
68 | struct { | |
69 | int loaded; | |
70 | u16 fs_sel, gs_sel, ldt_sel; | |
152d3f2f LV |
71 | int gs_ldt_reload_needed; |
72 | int fs_reload_needed; | |
51c6cf66 | 73 | int guest_efer_loaded; |
d77c26fc | 74 | } host_state; |
9c8cba37 AK |
75 | struct { |
76 | struct { | |
77 | bool pending; | |
78 | u8 vector; | |
79 | unsigned rip; | |
80 | } irq; | |
81 | } rmode; | |
2384d2b3 | 82 | int vpid; |
a2fa3e9f GH |
83 | }; |
84 | ||
85 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) | |
86 | { | |
fb3f0f51 | 87 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
88 | } |
89 | ||
75880a01 AK |
90 | static int init_rmode_tss(struct kvm *kvm); |
91 | ||
6aa8b732 AK |
92 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
93 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
94 | ||
fdef3ad1 HQ |
95 | static struct page *vmx_io_bitmap_a; |
96 | static struct page *vmx_io_bitmap_b; | |
25c5f225 | 97 | static struct page *vmx_msr_bitmap; |
fdef3ad1 | 98 | |
2384d2b3 SY |
99 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
100 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
101 | ||
1c3d14fe | 102 | static struct vmcs_config { |
6aa8b732 AK |
103 | int size; |
104 | int order; | |
105 | u32 revision_id; | |
1c3d14fe YS |
106 | u32 pin_based_exec_ctrl; |
107 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 108 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
109 | u32 vmexit_ctrl; |
110 | u32 vmentry_ctrl; | |
111 | } vmcs_config; | |
6aa8b732 | 112 | |
d56f546d SY |
113 | struct vmx_capability { |
114 | u32 ept; | |
115 | u32 vpid; | |
116 | } vmx_capability; | |
117 | ||
6aa8b732 AK |
118 | #define VMX_SEGMENT_FIELD(seg) \ |
119 | [VCPU_SREG_##seg] = { \ | |
120 | .selector = GUEST_##seg##_SELECTOR, \ | |
121 | .base = GUEST_##seg##_BASE, \ | |
122 | .limit = GUEST_##seg##_LIMIT, \ | |
123 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
124 | } | |
125 | ||
126 | static struct kvm_vmx_segment_field { | |
127 | unsigned selector; | |
128 | unsigned base; | |
129 | unsigned limit; | |
130 | unsigned ar_bytes; | |
131 | } kvm_vmx_segment_fields[] = { | |
132 | VMX_SEGMENT_FIELD(CS), | |
133 | VMX_SEGMENT_FIELD(DS), | |
134 | VMX_SEGMENT_FIELD(ES), | |
135 | VMX_SEGMENT_FIELD(FS), | |
136 | VMX_SEGMENT_FIELD(GS), | |
137 | VMX_SEGMENT_FIELD(SS), | |
138 | VMX_SEGMENT_FIELD(TR), | |
139 | VMX_SEGMENT_FIELD(LDTR), | |
140 | }; | |
141 | ||
4d56c8a7 AK |
142 | /* |
143 | * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it | |
144 | * away by decrementing the array size. | |
145 | */ | |
6aa8b732 | 146 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 147 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
148 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE, |
149 | #endif | |
150 | MSR_EFER, MSR_K6_STAR, | |
151 | }; | |
9d8f549d | 152 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 153 | |
a2fa3e9f GH |
154 | static void load_msrs(struct kvm_msr_entry *e, int n) |
155 | { | |
156 | int i; | |
157 | ||
158 | for (i = 0; i < n; ++i) | |
159 | wrmsrl(e[i].index, e[i].data); | |
160 | } | |
161 | ||
162 | static void save_msrs(struct kvm_msr_entry *e, int n) | |
163 | { | |
164 | int i; | |
165 | ||
166 | for (i = 0; i < n; ++i) | |
167 | rdmsrl(e[i].index, e[i].data); | |
168 | } | |
169 | ||
6aa8b732 AK |
170 | static inline int is_page_fault(u32 intr_info) |
171 | { | |
172 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
173 | INTR_INFO_VALID_MASK)) == | |
174 | (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); | |
175 | } | |
176 | ||
2ab455cc AL |
177 | static inline int is_no_device(u32 intr_info) |
178 | { | |
179 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
180 | INTR_INFO_VALID_MASK)) == | |
181 | (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); | |
182 | } | |
183 | ||
7aa81cc0 AL |
184 | static inline int is_invalid_opcode(u32 intr_info) |
185 | { | |
186 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
187 | INTR_INFO_VALID_MASK)) == | |
188 | (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); | |
189 | } | |
190 | ||
6aa8b732 AK |
191 | static inline int is_external_interrupt(u32 intr_info) |
192 | { | |
193 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
194 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
195 | } | |
196 | ||
25c5f225 SY |
197 | static inline int cpu_has_vmx_msr_bitmap(void) |
198 | { | |
199 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS); | |
200 | } | |
201 | ||
6e5d865c YS |
202 | static inline int cpu_has_vmx_tpr_shadow(void) |
203 | { | |
204 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW); | |
205 | } | |
206 | ||
207 | static inline int vm_need_tpr_shadow(struct kvm *kvm) | |
208 | { | |
209 | return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm))); | |
210 | } | |
211 | ||
f78e0e2e SY |
212 | static inline int cpu_has_secondary_exec_ctrls(void) |
213 | { | |
214 | return (vmcs_config.cpu_based_exec_ctrl & | |
215 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); | |
216 | } | |
217 | ||
774ead3a | 218 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 219 | { |
4c9fc8ef AK |
220 | return flexpriority_enabled |
221 | && (vmcs_config.cpu_based_2nd_exec_ctrl & | |
222 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
f78e0e2e SY |
223 | } |
224 | ||
d56f546d SY |
225 | static inline int cpu_has_vmx_invept_individual_addr(void) |
226 | { | |
227 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT)); | |
228 | } | |
229 | ||
230 | static inline int cpu_has_vmx_invept_context(void) | |
231 | { | |
232 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT)); | |
233 | } | |
234 | ||
235 | static inline int cpu_has_vmx_invept_global(void) | |
236 | { | |
237 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT)); | |
238 | } | |
239 | ||
240 | static inline int cpu_has_vmx_ept(void) | |
241 | { | |
242 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
243 | SECONDARY_EXEC_ENABLE_EPT); | |
244 | } | |
245 | ||
246 | static inline int vm_need_ept(void) | |
247 | { | |
248 | return (cpu_has_vmx_ept() && enable_ept); | |
249 | } | |
250 | ||
f78e0e2e SY |
251 | static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm) |
252 | { | |
253 | return ((cpu_has_vmx_virtualize_apic_accesses()) && | |
254 | (irqchip_in_kernel(kvm))); | |
255 | } | |
256 | ||
2384d2b3 SY |
257 | static inline int cpu_has_vmx_vpid(void) |
258 | { | |
259 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
260 | SECONDARY_EXEC_ENABLE_VPID); | |
261 | } | |
262 | ||
8b9cf98c | 263 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
264 | { |
265 | int i; | |
266 | ||
a2fa3e9f GH |
267 | for (i = 0; i < vmx->nmsrs; ++i) |
268 | if (vmx->guest_msrs[i].index == msr) | |
a75beee6 ED |
269 | return i; |
270 | return -1; | |
271 | } | |
272 | ||
2384d2b3 SY |
273 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
274 | { | |
275 | struct { | |
276 | u64 vpid : 16; | |
277 | u64 rsvd : 48; | |
278 | u64 gva; | |
279 | } operand = { vpid, 0, gva }; | |
280 | ||
281 | asm volatile (ASM_VMX_INVVPID | |
282 | /* CF==1 or ZF==1 --> rc = -1 */ | |
283 | "; ja 1f ; ud2 ; 1:" | |
284 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
285 | } | |
286 | ||
8b9cf98c | 287 | static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
288 | { |
289 | int i; | |
290 | ||
8b9cf98c | 291 | i = __find_msr_index(vmx, msr); |
a75beee6 | 292 | if (i >= 0) |
a2fa3e9f | 293 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 294 | return NULL; |
7725f0ba AK |
295 | } |
296 | ||
6aa8b732 AK |
297 | static void vmcs_clear(struct vmcs *vmcs) |
298 | { | |
299 | u64 phys_addr = __pa(vmcs); | |
300 | u8 error; | |
301 | ||
302 | asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0" | |
303 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
304 | : "cc", "memory"); | |
305 | if (error) | |
306 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
307 | vmcs, phys_addr); | |
308 | } | |
309 | ||
310 | static void __vcpu_clear(void *arg) | |
311 | { | |
8b9cf98c | 312 | struct vcpu_vmx *vmx = arg; |
d3b2c338 | 313 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 314 | |
8b9cf98c | 315 | if (vmx->vcpu.cpu == cpu) |
a2fa3e9f GH |
316 | vmcs_clear(vmx->vmcs); |
317 | if (per_cpu(current_vmcs, cpu) == vmx->vmcs) | |
6aa8b732 | 318 | per_cpu(current_vmcs, cpu) = NULL; |
ad312c7c | 319 | rdtscll(vmx->vcpu.arch.host_tsc); |
6aa8b732 AK |
320 | } |
321 | ||
8b9cf98c | 322 | static void vcpu_clear(struct vcpu_vmx *vmx) |
8d0be2b3 | 323 | { |
eae5ecb5 AK |
324 | if (vmx->vcpu.cpu == -1) |
325 | return; | |
f566e09f | 326 | smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1); |
8b9cf98c | 327 | vmx->launched = 0; |
8d0be2b3 AK |
328 | } |
329 | ||
2384d2b3 SY |
330 | static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx) |
331 | { | |
332 | if (vmx->vpid == 0) | |
333 | return; | |
334 | ||
335 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); | |
336 | } | |
337 | ||
6aa8b732 AK |
338 | static unsigned long vmcs_readl(unsigned long field) |
339 | { | |
340 | unsigned long value; | |
341 | ||
342 | asm volatile (ASM_VMX_VMREAD_RDX_RAX | |
343 | : "=a"(value) : "d"(field) : "cc"); | |
344 | return value; | |
345 | } | |
346 | ||
347 | static u16 vmcs_read16(unsigned long field) | |
348 | { | |
349 | return vmcs_readl(field); | |
350 | } | |
351 | ||
352 | static u32 vmcs_read32(unsigned long field) | |
353 | { | |
354 | return vmcs_readl(field); | |
355 | } | |
356 | ||
357 | static u64 vmcs_read64(unsigned long field) | |
358 | { | |
05b3e0c2 | 359 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
360 | return vmcs_readl(field); |
361 | #else | |
362 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
363 | #endif | |
364 | } | |
365 | ||
e52de1b8 AK |
366 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
367 | { | |
368 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
369 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
370 | dump_stack(); | |
371 | } | |
372 | ||
6aa8b732 AK |
373 | static void vmcs_writel(unsigned long field, unsigned long value) |
374 | { | |
375 | u8 error; | |
376 | ||
377 | asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0" | |
d77c26fc | 378 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
379 | if (unlikely(error)) |
380 | vmwrite_error(field, value); | |
6aa8b732 AK |
381 | } |
382 | ||
383 | static void vmcs_write16(unsigned long field, u16 value) | |
384 | { | |
385 | vmcs_writel(field, value); | |
386 | } | |
387 | ||
388 | static void vmcs_write32(unsigned long field, u32 value) | |
389 | { | |
390 | vmcs_writel(field, value); | |
391 | } | |
392 | ||
393 | static void vmcs_write64(unsigned long field, u64 value) | |
394 | { | |
05b3e0c2 | 395 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
396 | vmcs_writel(field, value); |
397 | #else | |
398 | vmcs_writel(field, value); | |
399 | asm volatile (""); | |
400 | vmcs_writel(field+1, value >> 32); | |
401 | #endif | |
402 | } | |
403 | ||
2ab455cc AL |
404 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
405 | { | |
406 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
407 | } | |
408 | ||
409 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
410 | { | |
411 | vmcs_writel(field, vmcs_readl(field) | mask); | |
412 | } | |
413 | ||
abd3f2d6 AK |
414 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
415 | { | |
416 | u32 eb; | |
417 | ||
7aa81cc0 | 418 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR); |
abd3f2d6 AK |
419 | if (!vcpu->fpu_active) |
420 | eb |= 1u << NM_VECTOR; | |
421 | if (vcpu->guest_debug.enabled) | |
422 | eb |= 1u << 1; | |
ad312c7c | 423 | if (vcpu->arch.rmode.active) |
abd3f2d6 AK |
424 | eb = ~0; |
425 | vmcs_write32(EXCEPTION_BITMAP, eb); | |
426 | } | |
427 | ||
33ed6329 AK |
428 | static void reload_tss(void) |
429 | { | |
33ed6329 AK |
430 | /* |
431 | * VT restores TR but not its size. Useless. | |
432 | */ | |
433 | struct descriptor_table gdt; | |
a5f61300 | 434 | struct desc_struct *descs; |
33ed6329 AK |
435 | |
436 | get_gdt(&gdt); | |
437 | descs = (void *)gdt.base; | |
438 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ | |
439 | load_TR_desc(); | |
33ed6329 AK |
440 | } |
441 | ||
8b9cf98c | 442 | static void load_transition_efer(struct vcpu_vmx *vmx) |
2cc51560 | 443 | { |
a2fa3e9f | 444 | int efer_offset = vmx->msr_offset_efer; |
51c6cf66 AK |
445 | u64 host_efer = vmx->host_msrs[efer_offset].data; |
446 | u64 guest_efer = vmx->guest_msrs[efer_offset].data; | |
447 | u64 ignore_bits; | |
448 | ||
449 | if (efer_offset < 0) | |
450 | return; | |
451 | /* | |
452 | * NX is emulated; LMA and LME handled by hardware; SCE meaninless | |
453 | * outside long mode | |
454 | */ | |
455 | ignore_bits = EFER_NX | EFER_SCE; | |
456 | #ifdef CONFIG_X86_64 | |
457 | ignore_bits |= EFER_LMA | EFER_LME; | |
458 | /* SCE is meaningful only in long mode on Intel */ | |
459 | if (guest_efer & EFER_LMA) | |
460 | ignore_bits &= ~(u64)EFER_SCE; | |
461 | #endif | |
462 | if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits)) | |
463 | return; | |
2cc51560 | 464 | |
51c6cf66 AK |
465 | vmx->host_state.guest_efer_loaded = 1; |
466 | guest_efer &= ~ignore_bits; | |
467 | guest_efer |= host_efer & ignore_bits; | |
468 | wrmsrl(MSR_EFER, guest_efer); | |
8b9cf98c | 469 | vmx->vcpu.stat.efer_reload++; |
2cc51560 ED |
470 | } |
471 | ||
51c6cf66 AK |
472 | static void reload_host_efer(struct vcpu_vmx *vmx) |
473 | { | |
474 | if (vmx->host_state.guest_efer_loaded) { | |
475 | vmx->host_state.guest_efer_loaded = 0; | |
476 | load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1); | |
477 | } | |
478 | } | |
479 | ||
04d2cc77 | 480 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 481 | { |
04d2cc77 AK |
482 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
483 | ||
a2fa3e9f | 484 | if (vmx->host_state.loaded) |
33ed6329 AK |
485 | return; |
486 | ||
a2fa3e9f | 487 | vmx->host_state.loaded = 1; |
33ed6329 AK |
488 | /* |
489 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
490 | * allow segment selectors with cpl > 0 or ti == 1. | |
491 | */ | |
a2fa3e9f | 492 | vmx->host_state.ldt_sel = read_ldt(); |
152d3f2f | 493 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
a2fa3e9f | 494 | vmx->host_state.fs_sel = read_fs(); |
152d3f2f | 495 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 496 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
497 | vmx->host_state.fs_reload_needed = 0; |
498 | } else { | |
33ed6329 | 499 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 500 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 501 | } |
a2fa3e9f GH |
502 | vmx->host_state.gs_sel = read_gs(); |
503 | if (!(vmx->host_state.gs_sel & 7)) | |
504 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
505 | else { |
506 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 507 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
508 | } |
509 | ||
510 | #ifdef CONFIG_X86_64 | |
511 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
512 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
513 | #else | |
a2fa3e9f GH |
514 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
515 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 516 | #endif |
707c0874 AK |
517 | |
518 | #ifdef CONFIG_X86_64 | |
d77c26fc | 519 | if (is_long_mode(&vmx->vcpu)) |
a2fa3e9f GH |
520 | save_msrs(vmx->host_msrs + |
521 | vmx->msr_offset_kernel_gs_base, 1); | |
d77c26fc | 522 | |
707c0874 | 523 | #endif |
a2fa3e9f | 524 | load_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
51c6cf66 | 525 | load_transition_efer(vmx); |
33ed6329 AK |
526 | } |
527 | ||
8b9cf98c | 528 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 529 | { |
15ad7146 | 530 | unsigned long flags; |
33ed6329 | 531 | |
a2fa3e9f | 532 | if (!vmx->host_state.loaded) |
33ed6329 AK |
533 | return; |
534 | ||
e1beb1d3 | 535 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 536 | vmx->host_state.loaded = 0; |
152d3f2f | 537 | if (vmx->host_state.fs_reload_needed) |
a2fa3e9f | 538 | load_fs(vmx->host_state.fs_sel); |
152d3f2f LV |
539 | if (vmx->host_state.gs_ldt_reload_needed) { |
540 | load_ldt(vmx->host_state.ldt_sel); | |
33ed6329 AK |
541 | /* |
542 | * If we have to reload gs, we must take care to | |
543 | * preserve our gs base. | |
544 | */ | |
15ad7146 | 545 | local_irq_save(flags); |
a2fa3e9f | 546 | load_gs(vmx->host_state.gs_sel); |
33ed6329 AK |
547 | #ifdef CONFIG_X86_64 |
548 | wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE)); | |
549 | #endif | |
15ad7146 | 550 | local_irq_restore(flags); |
33ed6329 | 551 | } |
152d3f2f | 552 | reload_tss(); |
a2fa3e9f GH |
553 | save_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
554 | load_msrs(vmx->host_msrs, vmx->save_nmsrs); | |
51c6cf66 | 555 | reload_host_efer(vmx); |
33ed6329 AK |
556 | } |
557 | ||
6aa8b732 AK |
558 | /* |
559 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
560 | * vcpu mutex is already taken. | |
561 | */ | |
15ad7146 | 562 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 563 | { |
a2fa3e9f GH |
564 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
565 | u64 phys_addr = __pa(vmx->vmcs); | |
019960ae | 566 | u64 tsc_this, delta, new_offset; |
6aa8b732 | 567 | |
a3d7f85f | 568 | if (vcpu->cpu != cpu) { |
8b9cf98c | 569 | vcpu_clear(vmx); |
a3d7f85f | 570 | kvm_migrate_apic_timer(vcpu); |
2384d2b3 | 571 | vpid_sync_vcpu_all(vmx); |
a3d7f85f | 572 | } |
6aa8b732 | 573 | |
a2fa3e9f | 574 | if (per_cpu(current_vmcs, cpu) != vmx->vmcs) { |
6aa8b732 AK |
575 | u8 error; |
576 | ||
a2fa3e9f | 577 | per_cpu(current_vmcs, cpu) = vmx->vmcs; |
6aa8b732 AK |
578 | asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0" |
579 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
580 | : "cc"); | |
581 | if (error) | |
582 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
a2fa3e9f | 583 | vmx->vmcs, phys_addr); |
6aa8b732 AK |
584 | } |
585 | ||
586 | if (vcpu->cpu != cpu) { | |
587 | struct descriptor_table dt; | |
588 | unsigned long sysenter_esp; | |
589 | ||
590 | vcpu->cpu = cpu; | |
591 | /* | |
592 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
593 | * processors. | |
594 | */ | |
595 | vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */ | |
596 | get_gdt(&dt); | |
597 | vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */ | |
598 | ||
599 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
600 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
7700270e AK |
601 | |
602 | /* | |
603 | * Make sure the time stamp counter is monotonous. | |
604 | */ | |
605 | rdtscll(tsc_this); | |
019960ae AK |
606 | if (tsc_this < vcpu->arch.host_tsc) { |
607 | delta = vcpu->arch.host_tsc - tsc_this; | |
608 | new_offset = vmcs_read64(TSC_OFFSET) + delta; | |
609 | vmcs_write64(TSC_OFFSET, new_offset); | |
610 | } | |
6aa8b732 | 611 | } |
6aa8b732 AK |
612 | } |
613 | ||
614 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
615 | { | |
8b9cf98c | 616 | vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
617 | } |
618 | ||
5fd86fcf AK |
619 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
620 | { | |
621 | if (vcpu->fpu_active) | |
622 | return; | |
623 | vcpu->fpu_active = 1; | |
707d92fa | 624 | vmcs_clear_bits(GUEST_CR0, X86_CR0_TS); |
ad312c7c | 625 | if (vcpu->arch.cr0 & X86_CR0_TS) |
707d92fa | 626 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
627 | update_exception_bitmap(vcpu); |
628 | } | |
629 | ||
630 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) | |
631 | { | |
632 | if (!vcpu->fpu_active) | |
633 | return; | |
634 | vcpu->fpu_active = 0; | |
707d92fa | 635 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
636 | update_exception_bitmap(vcpu); |
637 | } | |
638 | ||
774c47f1 AK |
639 | static void vmx_vcpu_decache(struct kvm_vcpu *vcpu) |
640 | { | |
8b9cf98c | 641 | vcpu_clear(to_vmx(vcpu)); |
774c47f1 AK |
642 | } |
643 | ||
6aa8b732 AK |
644 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
645 | { | |
646 | return vmcs_readl(GUEST_RFLAGS); | |
647 | } | |
648 | ||
649 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
650 | { | |
ad312c7c | 651 | if (vcpu->arch.rmode.active) |
053de044 | 652 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
653 | vmcs_writel(GUEST_RFLAGS, rflags); |
654 | } | |
655 | ||
656 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
657 | { | |
658 | unsigned long rip; | |
659 | u32 interruptibility; | |
660 | ||
661 | rip = vmcs_readl(GUEST_RIP); | |
662 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
663 | vmcs_writel(GUEST_RIP, rip); | |
664 | ||
665 | /* | |
666 | * We emulated an instruction, so temporary interrupt blocking | |
667 | * should be removed, if set. | |
668 | */ | |
669 | interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
670 | if (interruptibility & 3) | |
671 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
672 | interruptibility & ~3); | |
ad312c7c | 673 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
674 | } |
675 | ||
298101da AK |
676 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
677 | bool has_error_code, u32 error_code) | |
678 | { | |
679 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
680 | nr | INTR_TYPE_EXCEPTION | |
2e11384c | 681 | | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0) |
298101da AK |
682 | | INTR_INFO_VALID_MASK); |
683 | if (has_error_code) | |
684 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); | |
685 | } | |
686 | ||
687 | static bool vmx_exception_injected(struct kvm_vcpu *vcpu) | |
688 | { | |
689 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
690 | ||
691 | return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
692 | } | |
693 | ||
a75beee6 ED |
694 | /* |
695 | * Swap MSR entry in host/guest MSR entry array. | |
696 | */ | |
54e11fa1 | 697 | #ifdef CONFIG_X86_64 |
8b9cf98c | 698 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 699 | { |
a2fa3e9f GH |
700 | struct kvm_msr_entry tmp; |
701 | ||
702 | tmp = vmx->guest_msrs[to]; | |
703 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
704 | vmx->guest_msrs[from] = tmp; | |
705 | tmp = vmx->host_msrs[to]; | |
706 | vmx->host_msrs[to] = vmx->host_msrs[from]; | |
707 | vmx->host_msrs[from] = tmp; | |
a75beee6 | 708 | } |
54e11fa1 | 709 | #endif |
a75beee6 | 710 | |
e38aea3e AK |
711 | /* |
712 | * Set up the vmcs to automatically save and restore system | |
713 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
714 | * mode, as fiddling with msrs is very expensive. | |
715 | */ | |
8b9cf98c | 716 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 717 | { |
2cc51560 | 718 | int save_nmsrs; |
e38aea3e | 719 | |
33f9c505 | 720 | vmx_load_host_state(vmx); |
a75beee6 ED |
721 | save_nmsrs = 0; |
722 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 723 | if (is_long_mode(&vmx->vcpu)) { |
2cc51560 ED |
724 | int index; |
725 | ||
8b9cf98c | 726 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 727 | if (index >= 0) |
8b9cf98c RR |
728 | move_msr_up(vmx, index, save_nmsrs++); |
729 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 730 | if (index >= 0) |
8b9cf98c RR |
731 | move_msr_up(vmx, index, save_nmsrs++); |
732 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 733 | if (index >= 0) |
8b9cf98c RR |
734 | move_msr_up(vmx, index, save_nmsrs++); |
735 | index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE); | |
a75beee6 | 736 | if (index >= 0) |
8b9cf98c | 737 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
738 | /* |
739 | * MSR_K6_STAR is only needed on long mode guests, and only | |
740 | * if efer.sce is enabled. | |
741 | */ | |
8b9cf98c | 742 | index = __find_msr_index(vmx, MSR_K6_STAR); |
ad312c7c | 743 | if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE)) |
8b9cf98c | 744 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
745 | } |
746 | #endif | |
a2fa3e9f | 747 | vmx->save_nmsrs = save_nmsrs; |
e38aea3e | 748 | |
4d56c8a7 | 749 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 750 | vmx->msr_offset_kernel_gs_base = |
8b9cf98c | 751 | __find_msr_index(vmx, MSR_KERNEL_GS_BASE); |
4d56c8a7 | 752 | #endif |
8b9cf98c | 753 | vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER); |
e38aea3e AK |
754 | } |
755 | ||
6aa8b732 AK |
756 | /* |
757 | * reads and returns guest's timestamp counter "register" | |
758 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
759 | */ | |
760 | static u64 guest_read_tsc(void) | |
761 | { | |
762 | u64 host_tsc, tsc_offset; | |
763 | ||
764 | rdtscll(host_tsc); | |
765 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
766 | return host_tsc + tsc_offset; | |
767 | } | |
768 | ||
769 | /* | |
770 | * writes 'guest_tsc' into guest's timestamp counter "register" | |
771 | * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc | |
772 | */ | |
773 | static void guest_write_tsc(u64 guest_tsc) | |
774 | { | |
775 | u64 host_tsc; | |
776 | ||
777 | rdtscll(host_tsc); | |
778 | vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc); | |
779 | } | |
780 | ||
6aa8b732 AK |
781 | /* |
782 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
783 | * Returns 0 on success, non-0 otherwise. | |
784 | * Assumes vcpu_load() was already called. | |
785 | */ | |
786 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
787 | { | |
788 | u64 data; | |
a2fa3e9f | 789 | struct kvm_msr_entry *msr; |
6aa8b732 AK |
790 | |
791 | if (!pdata) { | |
792 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
793 | return -EINVAL; | |
794 | } | |
795 | ||
796 | switch (msr_index) { | |
05b3e0c2 | 797 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
798 | case MSR_FS_BASE: |
799 | data = vmcs_readl(GUEST_FS_BASE); | |
800 | break; | |
801 | case MSR_GS_BASE: | |
802 | data = vmcs_readl(GUEST_GS_BASE); | |
803 | break; | |
804 | case MSR_EFER: | |
3bab1f5d | 805 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
806 | #endif |
807 | case MSR_IA32_TIME_STAMP_COUNTER: | |
808 | data = guest_read_tsc(); | |
809 | break; | |
810 | case MSR_IA32_SYSENTER_CS: | |
811 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
812 | break; | |
813 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 814 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
815 | break; |
816 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 817 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 818 | break; |
6aa8b732 | 819 | default: |
8b9cf98c | 820 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d AK |
821 | if (msr) { |
822 | data = msr->data; | |
823 | break; | |
6aa8b732 | 824 | } |
3bab1f5d | 825 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
826 | } |
827 | ||
828 | *pdata = data; | |
829 | return 0; | |
830 | } | |
831 | ||
832 | /* | |
833 | * Writes msr value into into the appropriate "register". | |
834 | * Returns 0 on success, non-0 otherwise. | |
835 | * Assumes vcpu_load() was already called. | |
836 | */ | |
837 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
838 | { | |
a2fa3e9f GH |
839 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
840 | struct kvm_msr_entry *msr; | |
2cc51560 ED |
841 | int ret = 0; |
842 | ||
6aa8b732 | 843 | switch (msr_index) { |
05b3e0c2 | 844 | #ifdef CONFIG_X86_64 |
3bab1f5d | 845 | case MSR_EFER: |
2cc51560 | 846 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
51c6cf66 AK |
847 | if (vmx->host_state.loaded) { |
848 | reload_host_efer(vmx); | |
8b9cf98c | 849 | load_transition_efer(vmx); |
51c6cf66 | 850 | } |
2cc51560 | 851 | break; |
6aa8b732 AK |
852 | case MSR_FS_BASE: |
853 | vmcs_writel(GUEST_FS_BASE, data); | |
854 | break; | |
855 | case MSR_GS_BASE: | |
856 | vmcs_writel(GUEST_GS_BASE, data); | |
857 | break; | |
858 | #endif | |
859 | case MSR_IA32_SYSENTER_CS: | |
860 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
861 | break; | |
862 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 863 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
864 | break; |
865 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 866 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 867 | break; |
d27d4aca | 868 | case MSR_IA32_TIME_STAMP_COUNTER: |
6aa8b732 AK |
869 | guest_write_tsc(data); |
870 | break; | |
6aa8b732 | 871 | default: |
8b9cf98c | 872 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d AK |
873 | if (msr) { |
874 | msr->data = data; | |
a2fa3e9f GH |
875 | if (vmx->host_state.loaded) |
876 | load_msrs(vmx->guest_msrs, vmx->save_nmsrs); | |
3bab1f5d | 877 | break; |
6aa8b732 | 878 | } |
2cc51560 | 879 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
880 | } |
881 | ||
2cc51560 | 882 | return ret; |
6aa8b732 AK |
883 | } |
884 | ||
885 | /* | |
886 | * Sync the rsp and rip registers into the vcpu structure. This allows | |
ad312c7c | 887 | * registers to be accessed by indexing vcpu->arch.regs. |
6aa8b732 AK |
888 | */ |
889 | static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu) | |
890 | { | |
ad312c7c ZX |
891 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); |
892 | vcpu->arch.rip = vmcs_readl(GUEST_RIP); | |
6aa8b732 AK |
893 | } |
894 | ||
895 | /* | |
896 | * Syncs rsp and rip back into the vmcs. Should be called after possible | |
897 | * modification. | |
898 | */ | |
899 | static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu) | |
900 | { | |
ad312c7c ZX |
901 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); |
902 | vmcs_writel(GUEST_RIP, vcpu->arch.rip); | |
6aa8b732 AK |
903 | } |
904 | ||
905 | static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
906 | { | |
907 | unsigned long dr7 = 0x400; | |
6aa8b732 AK |
908 | int old_singlestep; |
909 | ||
6aa8b732 AK |
910 | old_singlestep = vcpu->guest_debug.singlestep; |
911 | ||
912 | vcpu->guest_debug.enabled = dbg->enabled; | |
913 | if (vcpu->guest_debug.enabled) { | |
914 | int i; | |
915 | ||
916 | dr7 |= 0x200; /* exact */ | |
917 | for (i = 0; i < 4; ++i) { | |
918 | if (!dbg->breakpoints[i].enabled) | |
919 | continue; | |
920 | vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address; | |
921 | dr7 |= 2 << (i*2); /* global enable */ | |
922 | dr7 |= 0 << (i*4+16); /* execution breakpoint */ | |
923 | } | |
924 | ||
6aa8b732 | 925 | vcpu->guest_debug.singlestep = dbg->singlestep; |
abd3f2d6 | 926 | } else |
6aa8b732 | 927 | vcpu->guest_debug.singlestep = 0; |
6aa8b732 AK |
928 | |
929 | if (old_singlestep && !vcpu->guest_debug.singlestep) { | |
930 | unsigned long flags; | |
931 | ||
932 | flags = vmcs_readl(GUEST_RFLAGS); | |
933 | flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
934 | vmcs_writel(GUEST_RFLAGS, flags); | |
935 | } | |
936 | ||
abd3f2d6 | 937 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
938 | vmcs_writel(GUEST_DR7, dr7); |
939 | ||
940 | return 0; | |
941 | } | |
942 | ||
2a8067f1 ED |
943 | static int vmx_get_irq(struct kvm_vcpu *vcpu) |
944 | { | |
1155f76a | 945 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2a8067f1 ED |
946 | u32 idtv_info_field; |
947 | ||
1155f76a | 948 | idtv_info_field = vmx->idt_vectoring_info; |
2a8067f1 ED |
949 | if (idtv_info_field & INTR_INFO_VALID_MASK) { |
950 | if (is_external_interrupt(idtv_info_field)) | |
951 | return idtv_info_field & VECTORING_INFO_VECTOR_MASK; | |
952 | else | |
d77c26fc | 953 | printk(KERN_DEBUG "pending exception: not handled yet\n"); |
2a8067f1 ED |
954 | } |
955 | return -1; | |
956 | } | |
957 | ||
6aa8b732 AK |
958 | static __init int cpu_has_kvm_support(void) |
959 | { | |
960 | unsigned long ecx = cpuid_ecx(1); | |
961 | return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */ | |
962 | } | |
963 | ||
964 | static __init int vmx_disabled_by_bios(void) | |
965 | { | |
966 | u64 msr; | |
967 | ||
968 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
62b3ffb8 YS |
969 | return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED | |
970 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
971 | == MSR_IA32_FEATURE_CONTROL_LOCKED; | |
972 | /* locked but not enabled */ | |
6aa8b732 AK |
973 | } |
974 | ||
774c47f1 | 975 | static void hardware_enable(void *garbage) |
6aa8b732 AK |
976 | { |
977 | int cpu = raw_smp_processor_id(); | |
978 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
979 | u64 old; | |
980 | ||
981 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); | |
62b3ffb8 YS |
982 | if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED | |
983 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
984 | != (MSR_IA32_FEATURE_CONTROL_LOCKED | | |
985 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
6aa8b732 | 986 | /* enable and lock */ |
62b3ffb8 YS |
987 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | |
988 | MSR_IA32_FEATURE_CONTROL_LOCKED | | |
989 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED); | |
66aee91a | 990 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
6aa8b732 AK |
991 | asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr) |
992 | : "memory", "cc"); | |
993 | } | |
994 | ||
995 | static void hardware_disable(void *garbage) | |
996 | { | |
997 | asm volatile (ASM_VMX_VMXOFF : : : "cc"); | |
998 | } | |
999 | ||
1c3d14fe | 1000 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 1001 | u32 msr, u32 *result) |
1c3d14fe YS |
1002 | { |
1003 | u32 vmx_msr_low, vmx_msr_high; | |
1004 | u32 ctl = ctl_min | ctl_opt; | |
1005 | ||
1006 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
1007 | ||
1008 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
1009 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
1010 | ||
1011 | /* Ensure minimum (required) set of control bits are supported. */ | |
1012 | if (ctl_min & ~ctl) | |
002c7f7c | 1013 | return -EIO; |
1c3d14fe YS |
1014 | |
1015 | *result = ctl; | |
1016 | return 0; | |
1017 | } | |
1018 | ||
002c7f7c | 1019 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
1020 | { |
1021 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 1022 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
1023 | u32 _pin_based_exec_control = 0; |
1024 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 1025 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
1026 | u32 _vmexit_control = 0; |
1027 | u32 _vmentry_control = 0; | |
1028 | ||
1029 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
1030 | opt = 0; | |
1031 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, | |
1032 | &_pin_based_exec_control) < 0) | |
002c7f7c | 1033 | return -EIO; |
1c3d14fe YS |
1034 | |
1035 | min = CPU_BASED_HLT_EXITING | | |
1036 | #ifdef CONFIG_X86_64 | |
1037 | CPU_BASED_CR8_LOAD_EXITING | | |
1038 | CPU_BASED_CR8_STORE_EXITING | | |
1039 | #endif | |
d56f546d SY |
1040 | CPU_BASED_CR3_LOAD_EXITING | |
1041 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
1042 | CPU_BASED_USE_IO_BITMAPS | |
1043 | CPU_BASED_MOV_DR_EXITING | | |
1044 | CPU_BASED_USE_TSC_OFFSETING; | |
f78e0e2e | 1045 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 1046 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 1047 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
1048 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
1049 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 1050 | return -EIO; |
6e5d865c YS |
1051 | #ifdef CONFIG_X86_64 |
1052 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
1053 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
1054 | ~CPU_BASED_CR8_STORE_EXITING; | |
1055 | #endif | |
f78e0e2e | 1056 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
1057 | min2 = 0; |
1058 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
2384d2b3 | 1059 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d SY |
1060 | SECONDARY_EXEC_ENABLE_VPID | |
1061 | SECONDARY_EXEC_ENABLE_EPT; | |
1062 | if (adjust_vmx_controls(min2, opt2, | |
1063 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
1064 | &_cpu_based_2nd_exec_control) < 0) |
1065 | return -EIO; | |
1066 | } | |
1067 | #ifndef CONFIG_X86_64 | |
1068 | if (!(_cpu_based_2nd_exec_control & | |
1069 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
1070 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1071 | #endif | |
d56f546d SY |
1072 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
1073 | /* CR3 accesses don't need to cause VM Exits when EPT enabled */ | |
1074 | min &= ~(CPU_BASED_CR3_LOAD_EXITING | | |
1075 | CPU_BASED_CR3_STORE_EXITING); | |
1076 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, | |
1077 | &_cpu_based_exec_control) < 0) | |
1078 | return -EIO; | |
1079 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, | |
1080 | vmx_capability.ept, vmx_capability.vpid); | |
1081 | } | |
1c3d14fe YS |
1082 | |
1083 | min = 0; | |
1084 | #ifdef CONFIG_X86_64 | |
1085 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
1086 | #endif | |
1087 | opt = 0; | |
1088 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, | |
1089 | &_vmexit_control) < 0) | |
002c7f7c | 1090 | return -EIO; |
1c3d14fe YS |
1091 | |
1092 | min = opt = 0; | |
1093 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, | |
1094 | &_vmentry_control) < 0) | |
002c7f7c | 1095 | return -EIO; |
6aa8b732 | 1096 | |
c68876fd | 1097 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
1098 | |
1099 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
1100 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 1101 | return -EIO; |
1c3d14fe YS |
1102 | |
1103 | #ifdef CONFIG_X86_64 | |
1104 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
1105 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 1106 | return -EIO; |
1c3d14fe YS |
1107 | #endif |
1108 | ||
1109 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
1110 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 1111 | return -EIO; |
1c3d14fe | 1112 | |
002c7f7c YS |
1113 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
1114 | vmcs_conf->order = get_order(vmcs_config.size); | |
1115 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 1116 | |
002c7f7c YS |
1117 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
1118 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 1119 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
1120 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
1121 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe YS |
1122 | |
1123 | return 0; | |
c68876fd | 1124 | } |
6aa8b732 AK |
1125 | |
1126 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
1127 | { | |
1128 | int node = cpu_to_node(cpu); | |
1129 | struct page *pages; | |
1130 | struct vmcs *vmcs; | |
1131 | ||
1c3d14fe | 1132 | pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
1133 | if (!pages) |
1134 | return NULL; | |
1135 | vmcs = page_address(pages); | |
1c3d14fe YS |
1136 | memset(vmcs, 0, vmcs_config.size); |
1137 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
1138 | return vmcs; |
1139 | } | |
1140 | ||
1141 | static struct vmcs *alloc_vmcs(void) | |
1142 | { | |
d3b2c338 | 1143 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
1144 | } |
1145 | ||
1146 | static void free_vmcs(struct vmcs *vmcs) | |
1147 | { | |
1c3d14fe | 1148 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
1149 | } |
1150 | ||
39959588 | 1151 | static void free_kvm_area(void) |
6aa8b732 AK |
1152 | { |
1153 | int cpu; | |
1154 | ||
1155 | for_each_online_cpu(cpu) | |
1156 | free_vmcs(per_cpu(vmxarea, cpu)); | |
1157 | } | |
1158 | ||
6aa8b732 AK |
1159 | static __init int alloc_kvm_area(void) |
1160 | { | |
1161 | int cpu; | |
1162 | ||
1163 | for_each_online_cpu(cpu) { | |
1164 | struct vmcs *vmcs; | |
1165 | ||
1166 | vmcs = alloc_vmcs_cpu(cpu); | |
1167 | if (!vmcs) { | |
1168 | free_kvm_area(); | |
1169 | return -ENOMEM; | |
1170 | } | |
1171 | ||
1172 | per_cpu(vmxarea, cpu) = vmcs; | |
1173 | } | |
1174 | return 0; | |
1175 | } | |
1176 | ||
1177 | static __init int hardware_setup(void) | |
1178 | { | |
002c7f7c YS |
1179 | if (setup_vmcs_config(&vmcs_config) < 0) |
1180 | return -EIO; | |
50a37eb4 JR |
1181 | |
1182 | if (boot_cpu_has(X86_FEATURE_NX)) | |
1183 | kvm_enable_efer_bits(EFER_NX); | |
1184 | ||
6aa8b732 AK |
1185 | return alloc_kvm_area(); |
1186 | } | |
1187 | ||
1188 | static __exit void hardware_unsetup(void) | |
1189 | { | |
1190 | free_kvm_area(); | |
1191 | } | |
1192 | ||
6aa8b732 AK |
1193 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
1194 | { | |
1195 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1196 | ||
6af11b9e | 1197 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
1198 | vmcs_write16(sf->selector, save->selector); |
1199 | vmcs_writel(sf->base, save->base); | |
1200 | vmcs_write32(sf->limit, save->limit); | |
1201 | vmcs_write32(sf->ar_bytes, save->ar); | |
1202 | } else { | |
1203 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
1204 | << AR_DPL_SHIFT; | |
1205 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
1206 | } | |
1207 | } | |
1208 | ||
1209 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
1210 | { | |
1211 | unsigned long flags; | |
1212 | ||
ad312c7c | 1213 | vcpu->arch.rmode.active = 0; |
6aa8b732 | 1214 | |
ad312c7c ZX |
1215 | vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base); |
1216 | vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit); | |
1217 | vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar); | |
6aa8b732 AK |
1218 | |
1219 | flags = vmcs_readl(GUEST_RFLAGS); | |
053de044 | 1220 | flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM); |
ad312c7c | 1221 | flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT); |
6aa8b732 AK |
1222 | vmcs_writel(GUEST_RFLAGS, flags); |
1223 | ||
66aee91a RR |
1224 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
1225 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
1226 | |
1227 | update_exception_bitmap(vcpu); | |
1228 | ||
ad312c7c ZX |
1229 | fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es); |
1230 | fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1231 | fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1232 | fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
6aa8b732 AK |
1233 | |
1234 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
1235 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
1236 | ||
1237 | vmcs_write16(GUEST_CS_SELECTOR, | |
1238 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
1239 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1240 | } | |
1241 | ||
d77c26fc | 1242 | static gva_t rmode_tss_base(struct kvm *kvm) |
6aa8b732 | 1243 | { |
bfc6d222 | 1244 | if (!kvm->arch.tss_addr) { |
cbc94022 IE |
1245 | gfn_t base_gfn = kvm->memslots[0].base_gfn + |
1246 | kvm->memslots[0].npages - 3; | |
1247 | return base_gfn << PAGE_SHIFT; | |
1248 | } | |
bfc6d222 | 1249 | return kvm->arch.tss_addr; |
6aa8b732 AK |
1250 | } |
1251 | ||
1252 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
1253 | { | |
1254 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1255 | ||
1256 | save->selector = vmcs_read16(sf->selector); | |
1257 | save->base = vmcs_readl(sf->base); | |
1258 | save->limit = vmcs_read32(sf->limit); | |
1259 | save->ar = vmcs_read32(sf->ar_bytes); | |
15b00f32 JK |
1260 | vmcs_write16(sf->selector, save->base >> 4); |
1261 | vmcs_write32(sf->base, save->base & 0xfffff); | |
6aa8b732 AK |
1262 | vmcs_write32(sf->limit, 0xffff); |
1263 | vmcs_write32(sf->ar_bytes, 0xf3); | |
1264 | } | |
1265 | ||
1266 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
1267 | { | |
1268 | unsigned long flags; | |
1269 | ||
ad312c7c | 1270 | vcpu->arch.rmode.active = 1; |
6aa8b732 | 1271 | |
ad312c7c | 1272 | vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE); |
6aa8b732 AK |
1273 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); |
1274 | ||
ad312c7c | 1275 | vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); |
6aa8b732 AK |
1276 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
1277 | ||
ad312c7c | 1278 | vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); |
6aa8b732 AK |
1279 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
1280 | ||
1281 | flags = vmcs_readl(GUEST_RFLAGS); | |
ad312c7c ZX |
1282 | vcpu->arch.rmode.save_iopl |
1283 | = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
6aa8b732 | 1284 | |
053de044 | 1285 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
1286 | |
1287 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 1288 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
1289 | update_exception_bitmap(vcpu); |
1290 | ||
1291 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); | |
1292 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
1293 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
1294 | ||
1295 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 1296 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
1297 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
1298 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
1299 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
1300 | ||
ad312c7c ZX |
1301 | fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es); |
1302 | fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1303 | fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1304 | fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
75880a01 | 1305 | |
8668a3c4 | 1306 | kvm_mmu_reset_context(vcpu); |
75880a01 | 1307 | init_rmode_tss(vcpu->kvm); |
6aa8b732 AK |
1308 | } |
1309 | ||
05b3e0c2 | 1310 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1311 | |
1312 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
1313 | { | |
1314 | u32 guest_tr_ar; | |
1315 | ||
1316 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1317 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
1318 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
b8688d51 | 1319 | __func__); |
6aa8b732 AK |
1320 | vmcs_write32(GUEST_TR_AR_BYTES, |
1321 | (guest_tr_ar & ~AR_TYPE_MASK) | |
1322 | | AR_TYPE_BUSY_64_TSS); | |
1323 | } | |
1324 | ||
ad312c7c | 1325 | vcpu->arch.shadow_efer |= EFER_LMA; |
6aa8b732 | 1326 | |
8b9cf98c | 1327 | find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1328 | vmcs_write32(VM_ENTRY_CONTROLS, |
1329 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1330 | | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1331 | } |
1332 | ||
1333 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
1334 | { | |
ad312c7c | 1335 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
6aa8b732 AK |
1336 | |
1337 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1338 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1339 | & ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1340 | } |
1341 | ||
1342 | #endif | |
1343 | ||
2384d2b3 SY |
1344 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
1345 | { | |
1346 | vpid_sync_vcpu_all(to_vmx(vcpu)); | |
1347 | } | |
1348 | ||
25c4c276 | 1349 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 1350 | { |
ad312c7c ZX |
1351 | vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK; |
1352 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK; | |
399badf3 AK |
1353 | } |
1354 | ||
6aa8b732 AK |
1355 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1356 | { | |
5fd86fcf AK |
1357 | vmx_fpu_deactivate(vcpu); |
1358 | ||
ad312c7c | 1359 | if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1360 | enter_pmode(vcpu); |
1361 | ||
ad312c7c | 1362 | if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1363 | enter_rmode(vcpu); |
1364 | ||
05b3e0c2 | 1365 | #ifdef CONFIG_X86_64 |
ad312c7c | 1366 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 1367 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 1368 | enter_lmode(vcpu); |
707d92fa | 1369 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
1370 | exit_lmode(vcpu); |
1371 | } | |
1372 | #endif | |
1373 | ||
1374 | vmcs_writel(CR0_READ_SHADOW, cr0); | |
1375 | vmcs_writel(GUEST_CR0, | |
1376 | (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON); | |
ad312c7c | 1377 | vcpu->arch.cr0 = cr0; |
5fd86fcf | 1378 | |
707d92fa | 1379 | if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE)) |
5fd86fcf | 1380 | vmx_fpu_activate(vcpu); |
6aa8b732 AK |
1381 | } |
1382 | ||
6aa8b732 AK |
1383 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
1384 | { | |
2384d2b3 | 1385 | vmx_flush_tlb(vcpu); |
6aa8b732 | 1386 | vmcs_writel(GUEST_CR3, cr3); |
ad312c7c | 1387 | if (vcpu->arch.cr0 & X86_CR0_PE) |
5fd86fcf | 1388 | vmx_fpu_deactivate(vcpu); |
6aa8b732 AK |
1389 | } |
1390 | ||
1391 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1392 | { | |
1393 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
ad312c7c | 1394 | vmcs_writel(GUEST_CR4, cr4 | (vcpu->arch.rmode.active ? |
6aa8b732 | 1395 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON)); |
ad312c7c | 1396 | vcpu->arch.cr4 = cr4; |
6aa8b732 AK |
1397 | } |
1398 | ||
6aa8b732 AK |
1399 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
1400 | { | |
8b9cf98c RR |
1401 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1402 | struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); | |
6aa8b732 | 1403 | |
ad312c7c | 1404 | vcpu->arch.shadow_efer = efer; |
9f62e19a JR |
1405 | if (!msr) |
1406 | return; | |
6aa8b732 AK |
1407 | if (efer & EFER_LMA) { |
1408 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1409 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
1e4e6e00 | 1410 | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1411 | msr->data = efer; |
1412 | ||
1413 | } else { | |
1414 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1415 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
1e4e6e00 | 1416 | ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1417 | |
1418 | msr->data = efer & ~EFER_LME; | |
1419 | } | |
8b9cf98c | 1420 | setup_msrs(vmx); |
6aa8b732 AK |
1421 | } |
1422 | ||
6aa8b732 AK |
1423 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
1424 | { | |
1425 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1426 | ||
1427 | return vmcs_readl(sf->base); | |
1428 | } | |
1429 | ||
1430 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
1431 | struct kvm_segment *var, int seg) | |
1432 | { | |
1433 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1434 | u32 ar; | |
1435 | ||
1436 | var->base = vmcs_readl(sf->base); | |
1437 | var->limit = vmcs_read32(sf->limit); | |
1438 | var->selector = vmcs_read16(sf->selector); | |
1439 | ar = vmcs_read32(sf->ar_bytes); | |
1440 | if (ar & AR_UNUSABLE_MASK) | |
1441 | ar = 0; | |
1442 | var->type = ar & 15; | |
1443 | var->s = (ar >> 4) & 1; | |
1444 | var->dpl = (ar >> 5) & 3; | |
1445 | var->present = (ar >> 7) & 1; | |
1446 | var->avl = (ar >> 12) & 1; | |
1447 | var->l = (ar >> 13) & 1; | |
1448 | var->db = (ar >> 14) & 1; | |
1449 | var->g = (ar >> 15) & 1; | |
1450 | var->unusable = (ar >> 16) & 1; | |
1451 | } | |
1452 | ||
2e4d2653 IE |
1453 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
1454 | { | |
1455 | struct kvm_segment kvm_seg; | |
1456 | ||
1457 | if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */ | |
1458 | return 0; | |
1459 | ||
1460 | if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */ | |
1461 | return 3; | |
1462 | ||
1463 | vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS); | |
1464 | return kvm_seg.selector & 3; | |
1465 | } | |
1466 | ||
653e3108 | 1467 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 1468 | { |
6aa8b732 AK |
1469 | u32 ar; |
1470 | ||
653e3108 | 1471 | if (var->unusable) |
6aa8b732 AK |
1472 | ar = 1 << 16; |
1473 | else { | |
1474 | ar = var->type & 15; | |
1475 | ar |= (var->s & 1) << 4; | |
1476 | ar |= (var->dpl & 3) << 5; | |
1477 | ar |= (var->present & 1) << 7; | |
1478 | ar |= (var->avl & 1) << 12; | |
1479 | ar |= (var->l & 1) << 13; | |
1480 | ar |= (var->db & 1) << 14; | |
1481 | ar |= (var->g & 1) << 15; | |
1482 | } | |
f7fbf1fd UL |
1483 | if (ar == 0) /* a 0 value means unusable */ |
1484 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
1485 | |
1486 | return ar; | |
1487 | } | |
1488 | ||
1489 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
1490 | struct kvm_segment *var, int seg) | |
1491 | { | |
1492 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1493 | u32 ar; | |
1494 | ||
ad312c7c ZX |
1495 | if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) { |
1496 | vcpu->arch.rmode.tr.selector = var->selector; | |
1497 | vcpu->arch.rmode.tr.base = var->base; | |
1498 | vcpu->arch.rmode.tr.limit = var->limit; | |
1499 | vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var); | |
653e3108 AK |
1500 | return; |
1501 | } | |
1502 | vmcs_writel(sf->base, var->base); | |
1503 | vmcs_write32(sf->limit, var->limit); | |
1504 | vmcs_write16(sf->selector, var->selector); | |
ad312c7c | 1505 | if (vcpu->arch.rmode.active && var->s) { |
653e3108 AK |
1506 | /* |
1507 | * Hack real-mode segments into vm86 compatibility. | |
1508 | */ | |
1509 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
1510 | vmcs_writel(sf->base, 0xf0000); | |
1511 | ar = 0xf3; | |
1512 | } else | |
1513 | ar = vmx_segment_access_rights(var); | |
6aa8b732 AK |
1514 | vmcs_write32(sf->ar_bytes, ar); |
1515 | } | |
1516 | ||
6aa8b732 AK |
1517 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
1518 | { | |
1519 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
1520 | ||
1521 | *db = (ar >> 14) & 1; | |
1522 | *l = (ar >> 13) & 1; | |
1523 | } | |
1524 | ||
1525 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1526 | { | |
1527 | dt->limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
1528 | dt->base = vmcs_readl(GUEST_IDTR_BASE); | |
1529 | } | |
1530 | ||
1531 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1532 | { | |
1533 | vmcs_write32(GUEST_IDTR_LIMIT, dt->limit); | |
1534 | vmcs_writel(GUEST_IDTR_BASE, dt->base); | |
1535 | } | |
1536 | ||
1537 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1538 | { | |
1539 | dt->limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
1540 | dt->base = vmcs_readl(GUEST_GDTR_BASE); | |
1541 | } | |
1542 | ||
1543 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1544 | { | |
1545 | vmcs_write32(GUEST_GDTR_LIMIT, dt->limit); | |
1546 | vmcs_writel(GUEST_GDTR_BASE, dt->base); | |
1547 | } | |
1548 | ||
d77c26fc | 1549 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 1550 | { |
6aa8b732 | 1551 | gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT; |
195aefde | 1552 | u16 data = 0; |
10589a46 | 1553 | int ret = 0; |
195aefde | 1554 | int r; |
6aa8b732 | 1555 | |
195aefde IE |
1556 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1557 | if (r < 0) | |
10589a46 | 1558 | goto out; |
195aefde IE |
1559 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
1560 | r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16)); | |
1561 | if (r < 0) | |
10589a46 | 1562 | goto out; |
195aefde IE |
1563 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
1564 | if (r < 0) | |
10589a46 | 1565 | goto out; |
195aefde IE |
1566 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1567 | if (r < 0) | |
10589a46 | 1568 | goto out; |
195aefde | 1569 | data = ~0; |
10589a46 MT |
1570 | r = kvm_write_guest_page(kvm, fn, &data, |
1571 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
1572 | sizeof(u8)); | |
195aefde | 1573 | if (r < 0) |
10589a46 MT |
1574 | goto out; |
1575 | ||
1576 | ret = 1; | |
1577 | out: | |
10589a46 | 1578 | return ret; |
6aa8b732 AK |
1579 | } |
1580 | ||
6aa8b732 AK |
1581 | static void seg_setup(int seg) |
1582 | { | |
1583 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1584 | ||
1585 | vmcs_write16(sf->selector, 0); | |
1586 | vmcs_writel(sf->base, 0); | |
1587 | vmcs_write32(sf->limit, 0xffff); | |
1588 | vmcs_write32(sf->ar_bytes, 0x93); | |
1589 | } | |
1590 | ||
f78e0e2e SY |
1591 | static int alloc_apic_access_page(struct kvm *kvm) |
1592 | { | |
1593 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
1594 | int r = 0; | |
1595 | ||
72dc67a6 | 1596 | down_write(&kvm->slots_lock); |
bfc6d222 | 1597 | if (kvm->arch.apic_access_page) |
f78e0e2e SY |
1598 | goto out; |
1599 | kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
1600 | kvm_userspace_mem.flags = 0; | |
1601 | kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL; | |
1602 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
1603 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
1604 | if (r) | |
1605 | goto out; | |
72dc67a6 IE |
1606 | |
1607 | down_read(¤t->mm->mmap_sem); | |
bfc6d222 | 1608 | kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00); |
72dc67a6 | 1609 | up_read(¤t->mm->mmap_sem); |
f78e0e2e | 1610 | out: |
72dc67a6 | 1611 | up_write(&kvm->slots_lock); |
f78e0e2e SY |
1612 | return r; |
1613 | } | |
1614 | ||
2384d2b3 SY |
1615 | static void allocate_vpid(struct vcpu_vmx *vmx) |
1616 | { | |
1617 | int vpid; | |
1618 | ||
1619 | vmx->vpid = 0; | |
1620 | if (!enable_vpid || !cpu_has_vmx_vpid()) | |
1621 | return; | |
1622 | spin_lock(&vmx_vpid_lock); | |
1623 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
1624 | if (vpid < VMX_NR_VPIDS) { | |
1625 | vmx->vpid = vpid; | |
1626 | __set_bit(vpid, vmx_vpid_bitmap); | |
1627 | } | |
1628 | spin_unlock(&vmx_vpid_lock); | |
1629 | } | |
1630 | ||
25c5f225 SY |
1631 | void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr) |
1632 | { | |
1633 | void *va; | |
1634 | ||
1635 | if (!cpu_has_vmx_msr_bitmap()) | |
1636 | return; | |
1637 | ||
1638 | /* | |
1639 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
1640 | * have the write-low and read-high bitmap offsets the wrong way round. | |
1641 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
1642 | */ | |
1643 | va = kmap(msr_bitmap); | |
1644 | if (msr <= 0x1fff) { | |
1645 | __clear_bit(msr, va + 0x000); /* read-low */ | |
1646 | __clear_bit(msr, va + 0x800); /* write-low */ | |
1647 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
1648 | msr &= 0x1fff; | |
1649 | __clear_bit(msr, va + 0x400); /* read-high */ | |
1650 | __clear_bit(msr, va + 0xc00); /* write-high */ | |
1651 | } | |
1652 | kunmap(msr_bitmap); | |
1653 | } | |
1654 | ||
6aa8b732 AK |
1655 | /* |
1656 | * Sets up the vmcs for emulated real mode. | |
1657 | */ | |
8b9cf98c | 1658 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 AK |
1659 | { |
1660 | u32 host_sysenter_cs; | |
1661 | u32 junk; | |
1662 | unsigned long a; | |
1663 | struct descriptor_table dt; | |
1664 | int i; | |
cd2276a7 | 1665 | unsigned long kvm_vmx_return; |
6e5d865c | 1666 | u32 exec_control; |
6aa8b732 | 1667 | |
6aa8b732 | 1668 | /* I/O */ |
fdef3ad1 HQ |
1669 | vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a)); |
1670 | vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b)); | |
6aa8b732 | 1671 | |
25c5f225 SY |
1672 | if (cpu_has_vmx_msr_bitmap()) |
1673 | vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap)); | |
1674 | ||
6aa8b732 AK |
1675 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
1676 | ||
6aa8b732 | 1677 | /* Control */ |
1c3d14fe YS |
1678 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, |
1679 | vmcs_config.pin_based_exec_ctrl); | |
6e5d865c YS |
1680 | |
1681 | exec_control = vmcs_config.cpu_based_exec_ctrl; | |
1682 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { | |
1683 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1684 | #ifdef CONFIG_X86_64 | |
1685 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
1686 | CPU_BASED_CR8_LOAD_EXITING; | |
1687 | #endif | |
1688 | } | |
d56f546d SY |
1689 | if (!vm_need_ept()) |
1690 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
1691 | CPU_BASED_CR3_LOAD_EXITING; | |
6e5d865c | 1692 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); |
6aa8b732 | 1693 | |
83ff3b9d SY |
1694 | if (cpu_has_secondary_exec_ctrls()) { |
1695 | exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
1696 | if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
1697 | exec_control &= | |
1698 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
2384d2b3 SY |
1699 | if (vmx->vpid == 0) |
1700 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
d56f546d SY |
1701 | if (!vm_need_ept()) |
1702 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
83ff3b9d SY |
1703 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
1704 | } | |
f78e0e2e | 1705 | |
c7addb90 AK |
1706 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf); |
1707 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf); | |
6aa8b732 AK |
1708 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
1709 | ||
1710 | vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */ | |
1711 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ | |
1712 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
1713 | ||
1714 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
1715 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1716 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1717 | vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */ | |
1718 | vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */ | |
1719 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
05b3e0c2 | 1720 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1721 | rdmsrl(MSR_FS_BASE, a); |
1722 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
1723 | rdmsrl(MSR_GS_BASE, a); | |
1724 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
1725 | #else | |
1726 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
1727 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
1728 | #endif | |
1729 | ||
1730 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
1731 | ||
1732 | get_idt(&dt); | |
1733 | vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */ | |
1734 | ||
d77c26fc | 1735 | asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); |
cd2276a7 | 1736 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ |
2cc51560 ED |
1737 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
1738 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
1739 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); | |
6aa8b732 AK |
1740 | |
1741 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
1742 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
1743 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
1744 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
1745 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
1746 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
1747 | ||
6aa8b732 AK |
1748 | for (i = 0; i < NR_VMX_MSR; ++i) { |
1749 | u32 index = vmx_msr_index[i]; | |
1750 | u32 data_low, data_high; | |
1751 | u64 data; | |
a2fa3e9f | 1752 | int j = vmx->nmsrs; |
6aa8b732 AK |
1753 | |
1754 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
1755 | continue; | |
432bd6cb AK |
1756 | if (wrmsr_safe(index, data_low, data_high) < 0) |
1757 | continue; | |
6aa8b732 | 1758 | data = data_low | ((u64)data_high << 32); |
a2fa3e9f GH |
1759 | vmx->host_msrs[j].index = index; |
1760 | vmx->host_msrs[j].reserved = 0; | |
1761 | vmx->host_msrs[j].data = data; | |
1762 | vmx->guest_msrs[j] = vmx->host_msrs[j]; | |
1763 | ++vmx->nmsrs; | |
6aa8b732 | 1764 | } |
6aa8b732 | 1765 | |
1c3d14fe | 1766 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
1767 | |
1768 | /* 22.2.1, 20.8.1 */ | |
1c3d14fe YS |
1769 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); |
1770 | ||
e00c8cf2 AK |
1771 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
1772 | vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK); | |
1773 | ||
f78e0e2e | 1774 | |
e00c8cf2 AK |
1775 | return 0; |
1776 | } | |
1777 | ||
1778 | static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) | |
1779 | { | |
1780 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
1781 | u64 msr; | |
1782 | int ret; | |
1783 | ||
3200f405 | 1784 | down_read(&vcpu->kvm->slots_lock); |
e00c8cf2 AK |
1785 | if (!init_rmode_tss(vmx->vcpu.kvm)) { |
1786 | ret = -ENOMEM; | |
1787 | goto out; | |
1788 | } | |
1789 | ||
ad312c7c | 1790 | vmx->vcpu.arch.rmode.active = 0; |
e00c8cf2 | 1791 | |
ad312c7c | 1792 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
2d3ad1f4 | 1793 | kvm_set_cr8(&vmx->vcpu, 0); |
e00c8cf2 AK |
1794 | msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
1795 | if (vmx->vcpu.vcpu_id == 0) | |
1796 | msr |= MSR_IA32_APICBASE_BSP; | |
1797 | kvm_set_apic_base(&vmx->vcpu, msr); | |
1798 | ||
1799 | fx_init(&vmx->vcpu); | |
1800 | ||
1801 | /* | |
1802 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
1803 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
1804 | */ | |
1805 | if (vmx->vcpu.vcpu_id == 0) { | |
1806 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); | |
1807 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
1808 | } else { | |
ad312c7c ZX |
1809 | vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8); |
1810 | vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12); | |
e00c8cf2 AK |
1811 | } |
1812 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); | |
1813 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1814 | ||
1815 | seg_setup(VCPU_SREG_DS); | |
1816 | seg_setup(VCPU_SREG_ES); | |
1817 | seg_setup(VCPU_SREG_FS); | |
1818 | seg_setup(VCPU_SREG_GS); | |
1819 | seg_setup(VCPU_SREG_SS); | |
1820 | ||
1821 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
1822 | vmcs_writel(GUEST_TR_BASE, 0); | |
1823 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
1824 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
1825 | ||
1826 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
1827 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
1828 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
1829 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
1830 | ||
1831 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
1832 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
1833 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
1834 | ||
1835 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
1836 | if (vmx->vcpu.vcpu_id == 0) | |
1837 | vmcs_writel(GUEST_RIP, 0xfff0); | |
1838 | else | |
1839 | vmcs_writel(GUEST_RIP, 0); | |
1840 | vmcs_writel(GUEST_RSP, 0); | |
1841 | ||
1842 | /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */ | |
1843 | vmcs_writel(GUEST_DR7, 0x400); | |
1844 | ||
1845 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
1846 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
1847 | ||
1848 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
1849 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
1850 | ||
1851 | vmcs_write32(GUEST_ACTIVITY_STATE, 0); | |
1852 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); | |
1853 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
1854 | ||
1855 | guest_write_tsc(0); | |
1856 | ||
1857 | /* Special registers */ | |
1858 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
1859 | ||
1860 | setup_msrs(vmx); | |
1861 | ||
6aa8b732 AK |
1862 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
1863 | ||
f78e0e2e SY |
1864 | if (cpu_has_vmx_tpr_shadow()) { |
1865 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); | |
1866 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
1867 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
ad312c7c | 1868 | page_to_phys(vmx->vcpu.arch.apic->regs_page)); |
f78e0e2e SY |
1869 | vmcs_write32(TPR_THRESHOLD, 0); |
1870 | } | |
1871 | ||
1872 | if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
1873 | vmcs_write64(APIC_ACCESS_ADDR, | |
bfc6d222 | 1874 | page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); |
6aa8b732 | 1875 | |
2384d2b3 SY |
1876 | if (vmx->vpid != 0) |
1877 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
1878 | ||
ad312c7c ZX |
1879 | vmx->vcpu.arch.cr0 = 0x60000010; |
1880 | vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */ | |
8b9cf98c | 1881 | vmx_set_cr4(&vmx->vcpu, 0); |
8b9cf98c | 1882 | vmx_set_efer(&vmx->vcpu, 0); |
8b9cf98c RR |
1883 | vmx_fpu_activate(&vmx->vcpu); |
1884 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 | 1885 | |
2384d2b3 SY |
1886 | vpid_sync_vcpu_all(vmx); |
1887 | ||
3200f405 | 1888 | ret = 0; |
6aa8b732 | 1889 | |
6aa8b732 | 1890 | out: |
3200f405 | 1891 | up_read(&vcpu->kvm->slots_lock); |
6aa8b732 AK |
1892 | return ret; |
1893 | } | |
1894 | ||
85f455f7 ED |
1895 | static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq) |
1896 | { | |
9c8cba37 AK |
1897 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1898 | ||
2714d1d3 FEL |
1899 | KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler); |
1900 | ||
ad312c7c | 1901 | if (vcpu->arch.rmode.active) { |
9c8cba37 AK |
1902 | vmx->rmode.irq.pending = true; |
1903 | vmx->rmode.irq.vector = irq; | |
1904 | vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP); | |
9c5623e3 AK |
1905 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
1906 | irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK); | |
1907 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
9c8cba37 | 1908 | vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1); |
85f455f7 ED |
1909 | return; |
1910 | } | |
1911 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
1912 | irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1913 | } | |
1914 | ||
6aa8b732 AK |
1915 | static void kvm_do_inject_irq(struct kvm_vcpu *vcpu) |
1916 | { | |
ad312c7c ZX |
1917 | int word_index = __ffs(vcpu->arch.irq_summary); |
1918 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
1919 | int irq = word_index * BITS_PER_LONG + bit_index; |
1920 | ||
ad312c7c ZX |
1921 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
1922 | if (!vcpu->arch.irq_pending[word_index]) | |
1923 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
85f455f7 | 1924 | vmx_inject_irq(vcpu, irq); |
6aa8b732 AK |
1925 | } |
1926 | ||
c1150d8c DL |
1927 | |
1928 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, | |
1929 | struct kvm_run *kvm_run) | |
6aa8b732 | 1930 | { |
c1150d8c DL |
1931 | u32 cpu_based_vm_exec_control; |
1932 | ||
ad312c7c | 1933 | vcpu->arch.interrupt_window_open = |
c1150d8c DL |
1934 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && |
1935 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
1936 | ||
ad312c7c ZX |
1937 | if (vcpu->arch.interrupt_window_open && |
1938 | vcpu->arch.irq_summary && | |
c1150d8c | 1939 | !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK)) |
6aa8b732 | 1940 | /* |
c1150d8c | 1941 | * If interrupts enabled, and not blocked by sti or mov ss. Good. |
6aa8b732 AK |
1942 | */ |
1943 | kvm_do_inject_irq(vcpu); | |
c1150d8c DL |
1944 | |
1945 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
ad312c7c ZX |
1946 | if (!vcpu->arch.interrupt_window_open && |
1947 | (vcpu->arch.irq_summary || kvm_run->request_interrupt_window)) | |
6aa8b732 AK |
1948 | /* |
1949 | * Interrupts blocked. Wait for unblock. | |
1950 | */ | |
c1150d8c DL |
1951 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; |
1952 | else | |
1953 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
1954 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
6aa8b732 AK |
1955 | } |
1956 | ||
cbc94022 IE |
1957 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
1958 | { | |
1959 | int ret; | |
1960 | struct kvm_userspace_memory_region tss_mem = { | |
1961 | .slot = 8, | |
1962 | .guest_phys_addr = addr, | |
1963 | .memory_size = PAGE_SIZE * 3, | |
1964 | .flags = 0, | |
1965 | }; | |
1966 | ||
1967 | ret = kvm_set_memory_region(kvm, &tss_mem, 0); | |
1968 | if (ret) | |
1969 | return ret; | |
bfc6d222 | 1970 | kvm->arch.tss_addr = addr; |
cbc94022 IE |
1971 | return 0; |
1972 | } | |
1973 | ||
6aa8b732 AK |
1974 | static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu) |
1975 | { | |
1976 | struct kvm_guest_debug *dbg = &vcpu->guest_debug; | |
1977 | ||
1978 | set_debugreg(dbg->bp[0], 0); | |
1979 | set_debugreg(dbg->bp[1], 1); | |
1980 | set_debugreg(dbg->bp[2], 2); | |
1981 | set_debugreg(dbg->bp[3], 3); | |
1982 | ||
1983 | if (dbg->singlestep) { | |
1984 | unsigned long flags; | |
1985 | ||
1986 | flags = vmcs_readl(GUEST_RFLAGS); | |
1987 | flags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
1988 | vmcs_writel(GUEST_RFLAGS, flags); | |
1989 | } | |
1990 | } | |
1991 | ||
1992 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
1993 | int vec, u32 err_code) | |
1994 | { | |
ad312c7c | 1995 | if (!vcpu->arch.rmode.active) |
6aa8b732 AK |
1996 | return 0; |
1997 | ||
b3f37707 NK |
1998 | /* |
1999 | * Instruction with address size override prefix opcode 0x67 | |
2000 | * Cause the #SS fault with 0 error code in VM86 mode. | |
2001 | */ | |
2002 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
3427318f | 2003 | if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE) |
6aa8b732 AK |
2004 | return 1; |
2005 | return 0; | |
2006 | } | |
2007 | ||
2008 | static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2009 | { | |
1155f76a | 2010 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
2011 | u32 intr_info, error_code; |
2012 | unsigned long cr2, rip; | |
2013 | u32 vect_info; | |
2014 | enum emulation_result er; | |
2015 | ||
1155f76a | 2016 | vect_info = vmx->idt_vectoring_info; |
6aa8b732 AK |
2017 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
2018 | ||
2019 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
d77c26fc | 2020 | !is_page_fault(intr_info)) |
6aa8b732 | 2021 | printk(KERN_ERR "%s: unexpected, vectoring info 0x%x " |
b8688d51 | 2022 | "intr info 0x%x\n", __func__, vect_info, intr_info); |
6aa8b732 | 2023 | |
85f455f7 | 2024 | if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) { |
6aa8b732 | 2025 | int irq = vect_info & VECTORING_INFO_VECTOR_MASK; |
ad312c7c ZX |
2026 | set_bit(irq, vcpu->arch.irq_pending); |
2027 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
2028 | } |
2029 | ||
1b6269db AK |
2030 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */ |
2031 | return 1; /* already handled by vmx_vcpu_run() */ | |
2ab455cc AL |
2032 | |
2033 | if (is_no_device(intr_info)) { | |
5fd86fcf | 2034 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
2035 | return 1; |
2036 | } | |
2037 | ||
7aa81cc0 | 2038 | if (is_invalid_opcode(intr_info)) { |
571008da | 2039 | er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 2040 | if (er != EMULATE_DONE) |
7ee5d940 | 2041 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
2042 | return 1; |
2043 | } | |
2044 | ||
6aa8b732 AK |
2045 | error_code = 0; |
2046 | rip = vmcs_readl(GUEST_RIP); | |
2e11384c | 2047 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 AK |
2048 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
2049 | if (is_page_fault(intr_info)) { | |
2050 | cr2 = vmcs_readl(EXIT_QUALIFICATION); | |
2714d1d3 FEL |
2051 | KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2, |
2052 | (u32)((u64)cr2 >> 32), handler); | |
3067714c | 2053 | return kvm_mmu_page_fault(vcpu, cr2, error_code); |
6aa8b732 AK |
2054 | } |
2055 | ||
ad312c7c | 2056 | if (vcpu->arch.rmode.active && |
6aa8b732 | 2057 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, |
72d6e5a0 | 2058 | error_code)) { |
ad312c7c ZX |
2059 | if (vcpu->arch.halt_request) { |
2060 | vcpu->arch.halt_request = 0; | |
72d6e5a0 AK |
2061 | return kvm_emulate_halt(vcpu); |
2062 | } | |
6aa8b732 | 2063 | return 1; |
72d6e5a0 | 2064 | } |
6aa8b732 | 2065 | |
d77c26fc MD |
2066 | if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == |
2067 | (INTR_TYPE_EXCEPTION | 1)) { | |
6aa8b732 AK |
2068 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2069 | return 0; | |
2070 | } | |
2071 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; | |
2072 | kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK; | |
2073 | kvm_run->ex.error_code = error_code; | |
2074 | return 0; | |
2075 | } | |
2076 | ||
2077 | static int handle_external_interrupt(struct kvm_vcpu *vcpu, | |
2078 | struct kvm_run *kvm_run) | |
2079 | { | |
1165f5fe | 2080 | ++vcpu->stat.irq_exits; |
2714d1d3 | 2081 | KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler); |
6aa8b732 AK |
2082 | return 1; |
2083 | } | |
2084 | ||
988ad74f AK |
2085 | static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2086 | { | |
2087 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2088 | return 0; | |
2089 | } | |
6aa8b732 | 2090 | |
6aa8b732 AK |
2091 | static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2092 | { | |
bfdaab09 | 2093 | unsigned long exit_qualification; |
039576c0 AK |
2094 | int size, down, in, string, rep; |
2095 | unsigned port; | |
6aa8b732 | 2096 | |
1165f5fe | 2097 | ++vcpu->stat.io_exits; |
bfdaab09 | 2098 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 2099 | string = (exit_qualification & 16) != 0; |
e70669ab LV |
2100 | |
2101 | if (string) { | |
3427318f LV |
2102 | if (emulate_instruction(vcpu, |
2103 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
2104 | return 0; |
2105 | return 1; | |
2106 | } | |
2107 | ||
2108 | size = (exit_qualification & 7) + 1; | |
2109 | in = (exit_qualification & 8) != 0; | |
039576c0 | 2110 | down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0; |
039576c0 AK |
2111 | rep = (exit_qualification & 32) != 0; |
2112 | port = exit_qualification >> 16; | |
e70669ab | 2113 | |
3090dd73 | 2114 | return kvm_emulate_pio(vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
2115 | } |
2116 | ||
102d8325 IM |
2117 | static void |
2118 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
2119 | { | |
2120 | /* | |
2121 | * Patch in the VMCALL instruction: | |
2122 | */ | |
2123 | hypercall[0] = 0x0f; | |
2124 | hypercall[1] = 0x01; | |
2125 | hypercall[2] = 0xc1; | |
102d8325 IM |
2126 | } |
2127 | ||
6aa8b732 AK |
2128 | static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2129 | { | |
bfdaab09 | 2130 | unsigned long exit_qualification; |
6aa8b732 AK |
2131 | int cr; |
2132 | int reg; | |
2133 | ||
bfdaab09 | 2134 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2135 | cr = exit_qualification & 15; |
2136 | reg = (exit_qualification >> 8) & 15; | |
2137 | switch ((exit_qualification >> 4) & 3) { | |
2138 | case 0: /* mov to cr */ | |
2714d1d3 FEL |
2139 | KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)vcpu->arch.regs[reg], |
2140 | (u32)((u64)vcpu->arch.regs[reg] >> 32), handler); | |
6aa8b732 AK |
2141 | switch (cr) { |
2142 | case 0: | |
2143 | vcpu_load_rsp_rip(vcpu); | |
2d3ad1f4 | 2144 | kvm_set_cr0(vcpu, vcpu->arch.regs[reg]); |
6aa8b732 AK |
2145 | skip_emulated_instruction(vcpu); |
2146 | return 1; | |
2147 | case 3: | |
2148 | vcpu_load_rsp_rip(vcpu); | |
2d3ad1f4 | 2149 | kvm_set_cr3(vcpu, vcpu->arch.regs[reg]); |
6aa8b732 AK |
2150 | skip_emulated_instruction(vcpu); |
2151 | return 1; | |
2152 | case 4: | |
2153 | vcpu_load_rsp_rip(vcpu); | |
2d3ad1f4 | 2154 | kvm_set_cr4(vcpu, vcpu->arch.regs[reg]); |
6aa8b732 AK |
2155 | skip_emulated_instruction(vcpu); |
2156 | return 1; | |
2157 | case 8: | |
2158 | vcpu_load_rsp_rip(vcpu); | |
2d3ad1f4 | 2159 | kvm_set_cr8(vcpu, vcpu->arch.regs[reg]); |
6aa8b732 | 2160 | skip_emulated_instruction(vcpu); |
e5314067 AK |
2161 | if (irqchip_in_kernel(vcpu->kvm)) |
2162 | return 1; | |
253abdee YS |
2163 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2164 | return 0; | |
6aa8b732 AK |
2165 | }; |
2166 | break; | |
25c4c276 AL |
2167 | case 2: /* clts */ |
2168 | vcpu_load_rsp_rip(vcpu); | |
5fd86fcf | 2169 | vmx_fpu_deactivate(vcpu); |
ad312c7c ZX |
2170 | vcpu->arch.cr0 &= ~X86_CR0_TS; |
2171 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf | 2172 | vmx_fpu_activate(vcpu); |
2714d1d3 | 2173 | KVMTRACE_0D(CLTS, vcpu, handler); |
25c4c276 AL |
2174 | skip_emulated_instruction(vcpu); |
2175 | return 1; | |
6aa8b732 AK |
2176 | case 1: /*mov from cr*/ |
2177 | switch (cr) { | |
2178 | case 3: | |
2179 | vcpu_load_rsp_rip(vcpu); | |
ad312c7c | 2180 | vcpu->arch.regs[reg] = vcpu->arch.cr3; |
6aa8b732 | 2181 | vcpu_put_rsp_rip(vcpu); |
2714d1d3 FEL |
2182 | KVMTRACE_3D(CR_READ, vcpu, (u32)cr, |
2183 | (u32)vcpu->arch.regs[reg], | |
2184 | (u32)((u64)vcpu->arch.regs[reg] >> 32), | |
2185 | handler); | |
6aa8b732 AK |
2186 | skip_emulated_instruction(vcpu); |
2187 | return 1; | |
2188 | case 8: | |
6aa8b732 | 2189 | vcpu_load_rsp_rip(vcpu); |
2d3ad1f4 | 2190 | vcpu->arch.regs[reg] = kvm_get_cr8(vcpu); |
6aa8b732 | 2191 | vcpu_put_rsp_rip(vcpu); |
2714d1d3 FEL |
2192 | KVMTRACE_2D(CR_READ, vcpu, (u32)cr, |
2193 | (u32)vcpu->arch.regs[reg], handler); | |
6aa8b732 AK |
2194 | skip_emulated_instruction(vcpu); |
2195 | return 1; | |
2196 | } | |
2197 | break; | |
2198 | case 3: /* lmsw */ | |
2d3ad1f4 | 2199 | kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f); |
6aa8b732 AK |
2200 | |
2201 | skip_emulated_instruction(vcpu); | |
2202 | return 1; | |
2203 | default: | |
2204 | break; | |
2205 | } | |
2206 | kvm_run->exit_reason = 0; | |
f0242478 | 2207 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
2208 | (int)(exit_qualification >> 4) & 3, cr); |
2209 | return 0; | |
2210 | } | |
2211 | ||
2212 | static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2213 | { | |
bfdaab09 | 2214 | unsigned long exit_qualification; |
6aa8b732 AK |
2215 | unsigned long val; |
2216 | int dr, reg; | |
2217 | ||
2218 | /* | |
2219 | * FIXME: this code assumes the host is debugging the guest. | |
2220 | * need to deal with guest debugging itself too. | |
2221 | */ | |
bfdaab09 | 2222 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2223 | dr = exit_qualification & 7; |
2224 | reg = (exit_qualification >> 8) & 15; | |
2225 | vcpu_load_rsp_rip(vcpu); | |
2226 | if (exit_qualification & 16) { | |
2227 | /* mov from dr */ | |
2228 | switch (dr) { | |
2229 | case 6: | |
2230 | val = 0xffff0ff0; | |
2231 | break; | |
2232 | case 7: | |
2233 | val = 0x400; | |
2234 | break; | |
2235 | default: | |
2236 | val = 0; | |
2237 | } | |
ad312c7c | 2238 | vcpu->arch.regs[reg] = val; |
2714d1d3 | 2239 | KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler); |
6aa8b732 AK |
2240 | } else { |
2241 | /* mov to dr */ | |
2242 | } | |
2243 | vcpu_put_rsp_rip(vcpu); | |
2244 | skip_emulated_instruction(vcpu); | |
2245 | return 1; | |
2246 | } | |
2247 | ||
2248 | static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2249 | { | |
06465c5a AK |
2250 | kvm_emulate_cpuid(vcpu); |
2251 | return 1; | |
6aa8b732 AK |
2252 | } |
2253 | ||
2254 | static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2255 | { | |
ad312c7c | 2256 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2257 | u64 data; |
2258 | ||
2259 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
c1a5d4f9 | 2260 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
2261 | return 1; |
2262 | } | |
2263 | ||
2714d1d3 FEL |
2264 | KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32), |
2265 | handler); | |
2266 | ||
6aa8b732 | 2267 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
ad312c7c ZX |
2268 | vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u; |
2269 | vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
6aa8b732 AK |
2270 | skip_emulated_instruction(vcpu); |
2271 | return 1; | |
2272 | } | |
2273 | ||
2274 | static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2275 | { | |
ad312c7c ZX |
2276 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
2277 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
2278 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 2279 | |
2714d1d3 FEL |
2280 | KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32), |
2281 | handler); | |
2282 | ||
6aa8b732 | 2283 | if (vmx_set_msr(vcpu, ecx, data) != 0) { |
c1a5d4f9 | 2284 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
2285 | return 1; |
2286 | } | |
2287 | ||
2288 | skip_emulated_instruction(vcpu); | |
2289 | return 1; | |
2290 | } | |
2291 | ||
6e5d865c YS |
2292 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu, |
2293 | struct kvm_run *kvm_run) | |
2294 | { | |
2295 | return 1; | |
2296 | } | |
2297 | ||
6aa8b732 AK |
2298 | static int handle_interrupt_window(struct kvm_vcpu *vcpu, |
2299 | struct kvm_run *kvm_run) | |
2300 | { | |
85f455f7 ED |
2301 | u32 cpu_based_vm_exec_control; |
2302 | ||
2303 | /* clear pending irq */ | |
2304 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2305 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
2306 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 FEL |
2307 | |
2308 | KVMTRACE_0D(PEND_INTR, vcpu, handler); | |
2309 | ||
c1150d8c DL |
2310 | /* |
2311 | * If the user space waits to inject interrupts, exit as soon as | |
2312 | * possible | |
2313 | */ | |
2314 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 2315 | !vcpu->arch.irq_summary) { |
c1150d8c | 2316 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1165f5fe | 2317 | ++vcpu->stat.irq_window_exits; |
c1150d8c DL |
2318 | return 0; |
2319 | } | |
6aa8b732 AK |
2320 | return 1; |
2321 | } | |
2322 | ||
2323 | static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2324 | { | |
2325 | skip_emulated_instruction(vcpu); | |
d3bef15f | 2326 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
2327 | } |
2328 | ||
c21415e8 IM |
2329 | static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2330 | { | |
510043da | 2331 | skip_emulated_instruction(vcpu); |
7aa81cc0 AL |
2332 | kvm_emulate_hypercall(vcpu); |
2333 | return 1; | |
c21415e8 IM |
2334 | } |
2335 | ||
e5edaa01 ED |
2336 | static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2337 | { | |
2338 | skip_emulated_instruction(vcpu); | |
2339 | /* TODO: Add support for VT-d/pass-through device */ | |
2340 | return 1; | |
2341 | } | |
2342 | ||
f78e0e2e SY |
2343 | static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2344 | { | |
2345 | u64 exit_qualification; | |
2346 | enum emulation_result er; | |
2347 | unsigned long offset; | |
2348 | ||
2349 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2350 | offset = exit_qualification & 0xffful; | |
2351 | ||
2714d1d3 FEL |
2352 | KVMTRACE_1D(APIC_ACCESS, vcpu, (u32)offset, handler); |
2353 | ||
f78e0e2e SY |
2354 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); |
2355 | ||
2356 | if (er != EMULATE_DONE) { | |
2357 | printk(KERN_ERR | |
2358 | "Fail to handle apic access vmexit! Offset is 0x%lx\n", | |
2359 | offset); | |
2360 | return -ENOTSUPP; | |
2361 | } | |
2362 | return 1; | |
2363 | } | |
2364 | ||
37817f29 IE |
2365 | static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2366 | { | |
2367 | unsigned long exit_qualification; | |
2368 | u16 tss_selector; | |
2369 | int reason; | |
2370 | ||
2371 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
2372 | ||
2373 | reason = (u32)exit_qualification >> 30; | |
2374 | tss_selector = exit_qualification; | |
2375 | ||
2376 | return kvm_task_switch(vcpu, tss_selector, reason); | |
2377 | } | |
2378 | ||
6aa8b732 AK |
2379 | /* |
2380 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
2381 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
2382 | * to be done to userspace and return 0. | |
2383 | */ | |
2384 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, | |
2385 | struct kvm_run *kvm_run) = { | |
2386 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, | |
2387 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 2388 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
6aa8b732 | 2389 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
2390 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
2391 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
2392 | [EXIT_REASON_CPUID] = handle_cpuid, | |
2393 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
2394 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
2395 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
2396 | [EXIT_REASON_HLT] = handle_halt, | |
c21415e8 | 2397 | [EXIT_REASON_VMCALL] = handle_vmcall, |
f78e0e2e SY |
2398 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
2399 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
e5edaa01 | 2400 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
37817f29 | 2401 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
6aa8b732 AK |
2402 | }; |
2403 | ||
2404 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 2405 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 AK |
2406 | |
2407 | /* | |
2408 | * The guest has exited. See if we can fix it or if we need userspace | |
2409 | * assistance. | |
2410 | */ | |
2411 | static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |
2412 | { | |
6aa8b732 | 2413 | u32 exit_reason = vmcs_read32(VM_EXIT_REASON); |
29bd8a78 | 2414 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1155f76a | 2415 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 2416 | |
2714d1d3 FEL |
2417 | KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)vmcs_readl(GUEST_RIP), |
2418 | (u32)((u64)vmcs_readl(GUEST_RIP) >> 32), entryexit); | |
2419 | ||
29bd8a78 AK |
2420 | if (unlikely(vmx->fail)) { |
2421 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
2422 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2423 | = vmcs_read32(VM_INSTRUCTION_ERROR); | |
2424 | return 0; | |
2425 | } | |
6aa8b732 | 2426 | |
d77c26fc MD |
2427 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
2428 | exit_reason != EXIT_REASON_EXCEPTION_NMI) | |
6aa8b732 | 2429 | printk(KERN_WARNING "%s: unexpected, valid vectoring info and " |
b8688d51 | 2430 | "exit reason is 0x%x\n", __func__, exit_reason); |
6aa8b732 AK |
2431 | if (exit_reason < kvm_vmx_max_exit_handlers |
2432 | && kvm_vmx_exit_handlers[exit_reason]) | |
2433 | return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run); | |
2434 | else { | |
2435 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
2436 | kvm_run->hw.hardware_exit_reason = exit_reason; | |
2437 | } | |
2438 | return 0; | |
2439 | } | |
2440 | ||
6e5d865c YS |
2441 | static void update_tpr_threshold(struct kvm_vcpu *vcpu) |
2442 | { | |
2443 | int max_irr, tpr; | |
2444 | ||
2445 | if (!vm_need_tpr_shadow(vcpu->kvm)) | |
2446 | return; | |
2447 | ||
2448 | if (!kvm_lapic_enabled(vcpu) || | |
2449 | ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) { | |
2450 | vmcs_write32(TPR_THRESHOLD, 0); | |
2451 | return; | |
2452 | } | |
2453 | ||
2454 | tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4; | |
2455 | vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4); | |
2456 | } | |
2457 | ||
85f455f7 ED |
2458 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
2459 | { | |
2460 | u32 cpu_based_vm_exec_control; | |
2461 | ||
2462 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2463 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
2464 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2465 | } | |
2466 | ||
2467 | static void vmx_intr_assist(struct kvm_vcpu *vcpu) | |
2468 | { | |
1155f76a | 2469 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
85f455f7 ED |
2470 | u32 idtv_info_field, intr_info_field; |
2471 | int has_ext_irq, interrupt_window_open; | |
1b9778da | 2472 | int vector; |
85f455f7 | 2473 | |
6e5d865c YS |
2474 | update_tpr_threshold(vcpu); |
2475 | ||
85f455f7 ED |
2476 | has_ext_irq = kvm_cpu_has_interrupt(vcpu); |
2477 | intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD); | |
1155f76a | 2478 | idtv_info_field = vmx->idt_vectoring_info; |
85f455f7 ED |
2479 | if (intr_info_field & INTR_INFO_VALID_MASK) { |
2480 | if (idtv_info_field & INTR_INFO_VALID_MASK) { | |
2481 | /* TODO: fault when IDT_Vectoring */ | |
9584bf2c RH |
2482 | if (printk_ratelimit()) |
2483 | printk(KERN_ERR "Fault when IDT_Vectoring\n"); | |
85f455f7 ED |
2484 | } |
2485 | if (has_ext_irq) | |
2486 | enable_irq_window(vcpu); | |
2487 | return; | |
2488 | } | |
2489 | if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) { | |
9c8cba37 AK |
2490 | if ((idtv_info_field & VECTORING_INFO_TYPE_MASK) |
2491 | == INTR_TYPE_EXT_INTR | |
ad312c7c | 2492 | && vcpu->arch.rmode.active) { |
9c8cba37 AK |
2493 | u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK; |
2494 | ||
2495 | vmx_inject_irq(vcpu, vect); | |
2496 | if (unlikely(has_ext_irq)) | |
2497 | enable_irq_window(vcpu); | |
2498 | return; | |
2499 | } | |
2500 | ||
2714d1d3 FEL |
2501 | KVMTRACE_1D(REDELIVER_EVT, vcpu, idtv_info_field, handler); |
2502 | ||
85f455f7 ED |
2503 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field); |
2504 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2505 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
2506 | ||
2e11384c | 2507 | if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK)) |
85f455f7 ED |
2508 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, |
2509 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
2510 | if (unlikely(has_ext_irq)) | |
2511 | enable_irq_window(vcpu); | |
2512 | return; | |
2513 | } | |
2514 | if (!has_ext_irq) | |
2515 | return; | |
2516 | interrupt_window_open = | |
2517 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
2518 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
1b9778da ED |
2519 | if (interrupt_window_open) { |
2520 | vector = kvm_cpu_get_interrupt(vcpu); | |
2521 | vmx_inject_irq(vcpu, vector); | |
2522 | kvm_timer_intr_post(vcpu, vector); | |
2523 | } else | |
85f455f7 ED |
2524 | enable_irq_window(vcpu); |
2525 | } | |
2526 | ||
9c8cba37 AK |
2527 | /* |
2528 | * Failure to inject an interrupt should give us the information | |
2529 | * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs | |
2530 | * when fetching the interrupt redirection bitmap in the real-mode | |
2531 | * tss, this doesn't happen. So we do it ourselves. | |
2532 | */ | |
2533 | static void fixup_rmode_irq(struct vcpu_vmx *vmx) | |
2534 | { | |
2535 | vmx->rmode.irq.pending = 0; | |
2536 | if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip) | |
2537 | return; | |
2538 | vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip); | |
2539 | if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) { | |
2540 | vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK; | |
2541 | vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR; | |
2542 | return; | |
2543 | } | |
2544 | vmx->idt_vectoring_info = | |
2545 | VECTORING_INFO_VALID_MASK | |
2546 | | INTR_TYPE_EXT_INTR | |
2547 | | vmx->rmode.irq.vector; | |
2548 | } | |
2549 | ||
04d2cc77 | 2550 | static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6aa8b732 | 2551 | { |
a2fa3e9f | 2552 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1b6269db | 2553 | u32 intr_info; |
e6adf283 AK |
2554 | |
2555 | /* | |
2556 | * Loading guest fpu may have cleared host cr0.ts | |
2557 | */ | |
2558 | vmcs_writel(HOST_CR0, read_cr0()); | |
2559 | ||
d77c26fc | 2560 | asm( |
6aa8b732 | 2561 | /* Store host registers */ |
05b3e0c2 | 2562 | #ifdef CONFIG_X86_64 |
c2036300 | 2563 | "push %%rdx; push %%rbp;" |
6aa8b732 | 2564 | "push %%rcx \n\t" |
6aa8b732 | 2565 | #else |
ff593e5a LV |
2566 | "push %%edx; push %%ebp;" |
2567 | "push %%ecx \n\t" | |
6aa8b732 | 2568 | #endif |
c2036300 | 2569 | ASM_VMX_VMWRITE_RSP_RDX "\n\t" |
6aa8b732 | 2570 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 2571 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 2572 | /* Load guest registers. Don't clobber flags. */ |
05b3e0c2 | 2573 | #ifdef CONFIG_X86_64 |
e08aa78a | 2574 | "mov %c[cr2](%0), %%rax \n\t" |
6aa8b732 | 2575 | "mov %%rax, %%cr2 \n\t" |
e08aa78a AK |
2576 | "mov %c[rax](%0), %%rax \n\t" |
2577 | "mov %c[rbx](%0), %%rbx \n\t" | |
2578 | "mov %c[rdx](%0), %%rdx \n\t" | |
2579 | "mov %c[rsi](%0), %%rsi \n\t" | |
2580 | "mov %c[rdi](%0), %%rdi \n\t" | |
2581 | "mov %c[rbp](%0), %%rbp \n\t" | |
2582 | "mov %c[r8](%0), %%r8 \n\t" | |
2583 | "mov %c[r9](%0), %%r9 \n\t" | |
2584 | "mov %c[r10](%0), %%r10 \n\t" | |
2585 | "mov %c[r11](%0), %%r11 \n\t" | |
2586 | "mov %c[r12](%0), %%r12 \n\t" | |
2587 | "mov %c[r13](%0), %%r13 \n\t" | |
2588 | "mov %c[r14](%0), %%r14 \n\t" | |
2589 | "mov %c[r15](%0), %%r15 \n\t" | |
2590 | "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */ | |
6aa8b732 | 2591 | #else |
e08aa78a | 2592 | "mov %c[cr2](%0), %%eax \n\t" |
6aa8b732 | 2593 | "mov %%eax, %%cr2 \n\t" |
e08aa78a AK |
2594 | "mov %c[rax](%0), %%eax \n\t" |
2595 | "mov %c[rbx](%0), %%ebx \n\t" | |
2596 | "mov %c[rdx](%0), %%edx \n\t" | |
2597 | "mov %c[rsi](%0), %%esi \n\t" | |
2598 | "mov %c[rdi](%0), %%edi \n\t" | |
2599 | "mov %c[rbp](%0), %%ebp \n\t" | |
2600 | "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */ | |
6aa8b732 AK |
2601 | #endif |
2602 | /* Enter guest mode */ | |
cd2276a7 | 2603 | "jne .Llaunched \n\t" |
6aa8b732 | 2604 | ASM_VMX_VMLAUNCH "\n\t" |
cd2276a7 AK |
2605 | "jmp .Lkvm_vmx_return \n\t" |
2606 | ".Llaunched: " ASM_VMX_VMRESUME "\n\t" | |
2607 | ".Lkvm_vmx_return: " | |
6aa8b732 | 2608 | /* Save guest registers, load host registers, keep flags */ |
05b3e0c2 | 2609 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
2610 | "xchg %0, (%%rsp) \n\t" |
2611 | "mov %%rax, %c[rax](%0) \n\t" | |
2612 | "mov %%rbx, %c[rbx](%0) \n\t" | |
2613 | "pushq (%%rsp); popq %c[rcx](%0) \n\t" | |
2614 | "mov %%rdx, %c[rdx](%0) \n\t" | |
2615 | "mov %%rsi, %c[rsi](%0) \n\t" | |
2616 | "mov %%rdi, %c[rdi](%0) \n\t" | |
2617 | "mov %%rbp, %c[rbp](%0) \n\t" | |
2618 | "mov %%r8, %c[r8](%0) \n\t" | |
2619 | "mov %%r9, %c[r9](%0) \n\t" | |
2620 | "mov %%r10, %c[r10](%0) \n\t" | |
2621 | "mov %%r11, %c[r11](%0) \n\t" | |
2622 | "mov %%r12, %c[r12](%0) \n\t" | |
2623 | "mov %%r13, %c[r13](%0) \n\t" | |
2624 | "mov %%r14, %c[r14](%0) \n\t" | |
2625 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 2626 | "mov %%cr2, %%rax \n\t" |
e08aa78a | 2627 | "mov %%rax, %c[cr2](%0) \n\t" |
6aa8b732 | 2628 | |
e08aa78a | 2629 | "pop %%rbp; pop %%rbp; pop %%rdx \n\t" |
6aa8b732 | 2630 | #else |
e08aa78a AK |
2631 | "xchg %0, (%%esp) \n\t" |
2632 | "mov %%eax, %c[rax](%0) \n\t" | |
2633 | "mov %%ebx, %c[rbx](%0) \n\t" | |
2634 | "pushl (%%esp); popl %c[rcx](%0) \n\t" | |
2635 | "mov %%edx, %c[rdx](%0) \n\t" | |
2636 | "mov %%esi, %c[rsi](%0) \n\t" | |
2637 | "mov %%edi, %c[rdi](%0) \n\t" | |
2638 | "mov %%ebp, %c[rbp](%0) \n\t" | |
6aa8b732 | 2639 | "mov %%cr2, %%eax \n\t" |
e08aa78a | 2640 | "mov %%eax, %c[cr2](%0) \n\t" |
6aa8b732 | 2641 | |
e08aa78a | 2642 | "pop %%ebp; pop %%ebp; pop %%edx \n\t" |
6aa8b732 | 2643 | #endif |
e08aa78a AK |
2644 | "setbe %c[fail](%0) \n\t" |
2645 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), | |
2646 | [launched]"i"(offsetof(struct vcpu_vmx, launched)), | |
2647 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), | |
ad312c7c ZX |
2648 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
2649 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
2650 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
2651 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
2652 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
2653 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
2654 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 2655 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
2656 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
2657 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
2658 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
2659 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
2660 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
2661 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
2662 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
2663 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 2664 | #endif |
ad312c7c | 2665 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)) |
c2036300 LV |
2666 | : "cc", "memory" |
2667 | #ifdef CONFIG_X86_64 | |
2668 | , "rbx", "rdi", "rsi" | |
2669 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
ff593e5a LV |
2670 | #else |
2671 | , "ebx", "edi", "rsi" | |
c2036300 LV |
2672 | #endif |
2673 | ); | |
6aa8b732 | 2674 | |
1155f76a | 2675 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
9c8cba37 AK |
2676 | if (vmx->rmode.irq.pending) |
2677 | fixup_rmode_irq(vmx); | |
1155f76a | 2678 | |
ad312c7c | 2679 | vcpu->arch.interrupt_window_open = |
d77c26fc | 2680 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0; |
6aa8b732 | 2681 | |
d77c26fc | 2682 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
15ad7146 | 2683 | vmx->launched = 1; |
1b6269db AK |
2684 | |
2685 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
2686 | ||
2687 | /* We need to handle NMIs before interrupts are enabled */ | |
2714d1d3 FEL |
2688 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */ |
2689 | KVMTRACE_0D(NMI, vcpu, handler); | |
1b6269db | 2690 | asm("int $2"); |
2714d1d3 | 2691 | } |
6aa8b732 AK |
2692 | } |
2693 | ||
6aa8b732 AK |
2694 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) |
2695 | { | |
a2fa3e9f GH |
2696 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2697 | ||
2698 | if (vmx->vmcs) { | |
8b9cf98c | 2699 | on_each_cpu(__vcpu_clear, vmx, 0, 1); |
a2fa3e9f GH |
2700 | free_vmcs(vmx->vmcs); |
2701 | vmx->vmcs = NULL; | |
6aa8b732 AK |
2702 | } |
2703 | } | |
2704 | ||
2705 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
2706 | { | |
fb3f0f51 RR |
2707 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2708 | ||
2384d2b3 SY |
2709 | spin_lock(&vmx_vpid_lock); |
2710 | if (vmx->vpid != 0) | |
2711 | __clear_bit(vmx->vpid, vmx_vpid_bitmap); | |
2712 | spin_unlock(&vmx_vpid_lock); | |
6aa8b732 | 2713 | vmx_free_vmcs(vcpu); |
fb3f0f51 RR |
2714 | kfree(vmx->host_msrs); |
2715 | kfree(vmx->guest_msrs); | |
2716 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 2717 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
2718 | } |
2719 | ||
fb3f0f51 | 2720 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 2721 | { |
fb3f0f51 | 2722 | int err; |
c16f862d | 2723 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 2724 | int cpu; |
6aa8b732 | 2725 | |
a2fa3e9f | 2726 | if (!vmx) |
fb3f0f51 RR |
2727 | return ERR_PTR(-ENOMEM); |
2728 | ||
2384d2b3 SY |
2729 | allocate_vpid(vmx); |
2730 | ||
fb3f0f51 RR |
2731 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
2732 | if (err) | |
2733 | goto free_vcpu; | |
965b58a5 | 2734 | |
a2fa3e9f | 2735 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
fb3f0f51 RR |
2736 | if (!vmx->guest_msrs) { |
2737 | err = -ENOMEM; | |
2738 | goto uninit_vcpu; | |
2739 | } | |
965b58a5 | 2740 | |
a2fa3e9f GH |
2741 | vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
2742 | if (!vmx->host_msrs) | |
fb3f0f51 | 2743 | goto free_guest_msrs; |
965b58a5 | 2744 | |
a2fa3e9f GH |
2745 | vmx->vmcs = alloc_vmcs(); |
2746 | if (!vmx->vmcs) | |
fb3f0f51 | 2747 | goto free_msrs; |
a2fa3e9f GH |
2748 | |
2749 | vmcs_clear(vmx->vmcs); | |
2750 | ||
15ad7146 AK |
2751 | cpu = get_cpu(); |
2752 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
8b9cf98c | 2753 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 2754 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 2755 | put_cpu(); |
fb3f0f51 RR |
2756 | if (err) |
2757 | goto free_vmcs; | |
5e4a0b3c MT |
2758 | if (vm_need_virtualize_apic_accesses(kvm)) |
2759 | if (alloc_apic_access_page(kvm) != 0) | |
2760 | goto free_vmcs; | |
fb3f0f51 RR |
2761 | |
2762 | return &vmx->vcpu; | |
2763 | ||
2764 | free_vmcs: | |
2765 | free_vmcs(vmx->vmcs); | |
2766 | free_msrs: | |
2767 | kfree(vmx->host_msrs); | |
2768 | free_guest_msrs: | |
2769 | kfree(vmx->guest_msrs); | |
2770 | uninit_vcpu: | |
2771 | kvm_vcpu_uninit(&vmx->vcpu); | |
2772 | free_vcpu: | |
a4770347 | 2773 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 2774 | return ERR_PTR(err); |
6aa8b732 AK |
2775 | } |
2776 | ||
002c7f7c YS |
2777 | static void __init vmx_check_processor_compat(void *rtn) |
2778 | { | |
2779 | struct vmcs_config vmcs_conf; | |
2780 | ||
2781 | *(int *)rtn = 0; | |
2782 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
2783 | *(int *)rtn = -EIO; | |
2784 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
2785 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
2786 | smp_processor_id()); | |
2787 | *(int *)rtn = -EIO; | |
2788 | } | |
2789 | } | |
2790 | ||
cbdd1bea | 2791 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
2792 | .cpu_has_kvm_support = cpu_has_kvm_support, |
2793 | .disabled_by_bios = vmx_disabled_by_bios, | |
2794 | .hardware_setup = hardware_setup, | |
2795 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 2796 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
2797 | .hardware_enable = hardware_enable, |
2798 | .hardware_disable = hardware_disable, | |
774ead3a | 2799 | .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses, |
6aa8b732 AK |
2800 | |
2801 | .vcpu_create = vmx_create_vcpu, | |
2802 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 2803 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 2804 | |
04d2cc77 | 2805 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
2806 | .vcpu_load = vmx_vcpu_load, |
2807 | .vcpu_put = vmx_vcpu_put, | |
774c47f1 | 2808 | .vcpu_decache = vmx_vcpu_decache, |
6aa8b732 AK |
2809 | |
2810 | .set_guest_debug = set_guest_debug, | |
04d2cc77 | 2811 | .guest_debug_pre = kvm_guest_debug_pre, |
6aa8b732 AK |
2812 | .get_msr = vmx_get_msr, |
2813 | .set_msr = vmx_set_msr, | |
2814 | .get_segment_base = vmx_get_segment_base, | |
2815 | .get_segment = vmx_get_segment, | |
2816 | .set_segment = vmx_set_segment, | |
2e4d2653 | 2817 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 2818 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
25c4c276 | 2819 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 2820 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
2821 | .set_cr3 = vmx_set_cr3, |
2822 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 2823 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
2824 | .get_idt = vmx_get_idt, |
2825 | .set_idt = vmx_set_idt, | |
2826 | .get_gdt = vmx_get_gdt, | |
2827 | .set_gdt = vmx_set_gdt, | |
2828 | .cache_regs = vcpu_load_rsp_rip, | |
2829 | .decache_regs = vcpu_put_rsp_rip, | |
2830 | .get_rflags = vmx_get_rflags, | |
2831 | .set_rflags = vmx_set_rflags, | |
2832 | ||
2833 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 2834 | |
6aa8b732 | 2835 | .run = vmx_vcpu_run, |
04d2cc77 | 2836 | .handle_exit = kvm_handle_exit, |
6aa8b732 | 2837 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 2838 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 ED |
2839 | .get_irq = vmx_get_irq, |
2840 | .set_irq = vmx_inject_irq, | |
298101da AK |
2841 | .queue_exception = vmx_queue_exception, |
2842 | .exception_injected = vmx_exception_injected, | |
04d2cc77 AK |
2843 | .inject_pending_irq = vmx_intr_assist, |
2844 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
2845 | |
2846 | .set_tss_addr = vmx_set_tss_addr, | |
6aa8b732 AK |
2847 | }; |
2848 | ||
2849 | static int __init vmx_init(void) | |
2850 | { | |
25c5f225 | 2851 | void *va; |
fdef3ad1 HQ |
2852 | int r; |
2853 | ||
2854 | vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
2855 | if (!vmx_io_bitmap_a) | |
2856 | return -ENOMEM; | |
2857 | ||
2858 | vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
2859 | if (!vmx_io_bitmap_b) { | |
2860 | r = -ENOMEM; | |
2861 | goto out; | |
2862 | } | |
2863 | ||
25c5f225 SY |
2864 | vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); |
2865 | if (!vmx_msr_bitmap) { | |
2866 | r = -ENOMEM; | |
2867 | goto out1; | |
2868 | } | |
2869 | ||
fdef3ad1 HQ |
2870 | /* |
2871 | * Allow direct access to the PC debug port (it is often used for I/O | |
2872 | * delays, but the vmexits simply slow things down). | |
2873 | */ | |
25c5f225 SY |
2874 | va = kmap(vmx_io_bitmap_a); |
2875 | memset(va, 0xff, PAGE_SIZE); | |
2876 | clear_bit(0x80, va); | |
cd0536d7 | 2877 | kunmap(vmx_io_bitmap_a); |
fdef3ad1 | 2878 | |
25c5f225 SY |
2879 | va = kmap(vmx_io_bitmap_b); |
2880 | memset(va, 0xff, PAGE_SIZE); | |
cd0536d7 | 2881 | kunmap(vmx_io_bitmap_b); |
fdef3ad1 | 2882 | |
25c5f225 SY |
2883 | va = kmap(vmx_msr_bitmap); |
2884 | memset(va, 0xff, PAGE_SIZE); | |
2885 | kunmap(vmx_msr_bitmap); | |
2886 | ||
2384d2b3 SY |
2887 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
2888 | ||
cb498ea2 | 2889 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE); |
fdef3ad1 | 2890 | if (r) |
25c5f225 SY |
2891 | goto out2; |
2892 | ||
2893 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE); | |
2894 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE); | |
2895 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS); | |
2896 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP); | |
2897 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP); | |
fdef3ad1 | 2898 | |
c7addb90 AK |
2899 | if (bypass_guest_pf) |
2900 | kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull); | |
2901 | ||
fdef3ad1 HQ |
2902 | return 0; |
2903 | ||
25c5f225 SY |
2904 | out2: |
2905 | __free_page(vmx_msr_bitmap); | |
fdef3ad1 HQ |
2906 | out1: |
2907 | __free_page(vmx_io_bitmap_b); | |
2908 | out: | |
2909 | __free_page(vmx_io_bitmap_a); | |
2910 | return r; | |
6aa8b732 AK |
2911 | } |
2912 | ||
2913 | static void __exit vmx_exit(void) | |
2914 | { | |
25c5f225 | 2915 | __free_page(vmx_msr_bitmap); |
fdef3ad1 HQ |
2916 | __free_page(vmx_io_bitmap_b); |
2917 | __free_page(vmx_io_bitmap_a); | |
2918 | ||
cb498ea2 | 2919 | kvm_exit(); |
6aa8b732 AK |
2920 | } |
2921 | ||
2922 | module_init(vmx_init) | |
2923 | module_exit(vmx_exit) |