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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
00b27a3e | 21 | #include "cpuid.h" |
d62caabb | 22 | #include "lapic.h" |
e495606d | 23 | |
edf88417 | 24 | #include <linux/kvm_host.h> |
6aa8b732 | 25 | #include <linux/module.h> |
9d8f549d | 26 | #include <linux/kernel.h> |
6aa8b732 AK |
27 | #include <linux/mm.h> |
28 | #include <linux/highmem.h> | |
e8edc6e0 | 29 | #include <linux/sched.h> |
c7addb90 | 30 | #include <linux/moduleparam.h> |
e9bda3b3 | 31 | #include <linux/mod_devicetable.h> |
af658dca | 32 | #include <linux/trace_events.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
cafd6659 | 34 | #include <linux/tboot.h> |
f4124500 | 35 | #include <linux/hrtimer.h> |
c207aee4 | 36 | #include <linux/frame.h> |
085331df | 37 | #include <linux/nospec.h> |
5fdbf976 | 38 | #include "kvm_cache_regs.h" |
35920a35 | 39 | #include "x86.h" |
e495606d | 40 | |
28b835d6 | 41 | #include <asm/cpu.h> |
6aa8b732 | 42 | #include <asm/io.h> |
3b3be0d1 | 43 | #include <asm/desc.h> |
13673a90 | 44 | #include <asm/vmx.h> |
6210e37b | 45 | #include <asm/virtext.h> |
a0861c02 | 46 | #include <asm/mce.h> |
952f07ec | 47 | #include <asm/fpu/internal.h> |
d7cd9796 | 48 | #include <asm/perf_event.h> |
81908bf4 | 49 | #include <asm/debugreg.h> |
8f536b76 | 50 | #include <asm/kexec.h> |
dab2087d | 51 | #include <asm/apic.h> |
efc64404 | 52 | #include <asm/irq_remapping.h> |
d6e41f11 | 53 | #include <asm/mmu_context.h> |
28a27752 | 54 | #include <asm/spec-ctrl.h> |
773e8a04 | 55 | #include <asm/mshyperv.h> |
6aa8b732 | 56 | |
229456fc | 57 | #include "trace.h" |
25462f7f | 58 | #include "pmu.h" |
773e8a04 | 59 | #include "vmx_evmcs.h" |
229456fc | 60 | |
4ecac3fd | 61 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
5e520e62 AK |
62 | #define __ex_clear(x, reg) \ |
63 | ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) | |
4ecac3fd | 64 | |
6aa8b732 AK |
65 | MODULE_AUTHOR("Qumranet"); |
66 | MODULE_LICENSE("GPL"); | |
67 | ||
e9bda3b3 JT |
68 | static const struct x86_cpu_id vmx_cpu_id[] = { |
69 | X86_FEATURE_MATCH(X86_FEATURE_VMX), | |
70 | {} | |
71 | }; | |
72 | MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); | |
73 | ||
476bc001 | 74 | static bool __read_mostly enable_vpid = 1; |
736caefe | 75 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 76 | |
d02fcf50 PB |
77 | static bool __read_mostly enable_vnmi = 1; |
78 | module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); | |
79 | ||
476bc001 | 80 | static bool __read_mostly flexpriority_enabled = 1; |
736caefe | 81 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 82 | |
476bc001 | 83 | static bool __read_mostly enable_ept = 1; |
736caefe | 84 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 85 | |
476bc001 | 86 | static bool __read_mostly enable_unrestricted_guest = 1; |
3a624e29 NK |
87 | module_param_named(unrestricted_guest, |
88 | enable_unrestricted_guest, bool, S_IRUGO); | |
89 | ||
83c3a331 XH |
90 | static bool __read_mostly enable_ept_ad_bits = 1; |
91 | module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); | |
92 | ||
a27685c3 | 93 | static bool __read_mostly emulate_invalid_guest_state = true; |
c1f8bc04 | 94 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 95 | |
476bc001 | 96 | static bool __read_mostly fasteoi = 1; |
58fbbf26 KT |
97 | module_param(fasteoi, bool, S_IRUGO); |
98 | ||
5a71785d | 99 | static bool __read_mostly enable_apicv = 1; |
01e439be | 100 | module_param(enable_apicv, bool, S_IRUGO); |
83d4c286 | 101 | |
abc4fc58 AG |
102 | static bool __read_mostly enable_shadow_vmcs = 1; |
103 | module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); | |
801d3424 NHE |
104 | /* |
105 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
106 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
107 | * use VMX instructions. | |
108 | */ | |
476bc001 | 109 | static bool __read_mostly nested = 0; |
801d3424 NHE |
110 | module_param(nested, bool, S_IRUGO); |
111 | ||
20300099 WL |
112 | static u64 __read_mostly host_xss; |
113 | ||
843e4330 KH |
114 | static bool __read_mostly enable_pml = 1; |
115 | module_param_named(pml, enable_pml, bool, S_IRUGO); | |
116 | ||
904e14fb PB |
117 | #define MSR_TYPE_R 1 |
118 | #define MSR_TYPE_W 2 | |
119 | #define MSR_TYPE_RW 3 | |
120 | ||
121 | #define MSR_BITMAP_MODE_X2APIC 1 | |
122 | #define MSR_BITMAP_MODE_X2APIC_APICV 2 | |
123 | #define MSR_BITMAP_MODE_LM 4 | |
124 | ||
64903d61 HZ |
125 | #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL |
126 | ||
64672c95 YJ |
127 | /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ |
128 | static int __read_mostly cpu_preemption_timer_multi; | |
129 | static bool __read_mostly enable_preemption_timer = 1; | |
130 | #ifdef CONFIG_X86_64 | |
131 | module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); | |
132 | #endif | |
133 | ||
5037878e | 134 | #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD) |
1706bd0c SC |
135 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE |
136 | #define KVM_VM_CR0_ALWAYS_ON \ | |
137 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ | |
138 | X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
139 | #define KVM_CR4_GUEST_OWNED_BITS \ |
140 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
fd8cb433 | 141 | | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) |
4c38609a | 142 | |
5dc1f044 | 143 | #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE |
cdc0e244 AK |
144 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
145 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
146 | ||
78ac8b47 AK |
147 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
148 | ||
f4124500 JK |
149 | #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 |
150 | ||
16c2aec6 JD |
151 | /* |
152 | * Hyper-V requires all of these, so mark them as supported even though | |
153 | * they are just treated the same as all-context. | |
154 | */ | |
155 | #define VMX_VPID_EXTENT_SUPPORTED_MASK \ | |
156 | (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \ | |
157 | VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \ | |
158 | VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \ | |
159 | VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT) | |
160 | ||
4b8d54f9 ZE |
161 | /* |
162 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
163 | * ple_gap: upper bound on the amount of time between two successive | |
164 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 165 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
166 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
167 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
168 | * less than 2^12 cycles | |
169 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
170 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
171 | */ | |
c8e88717 | 172 | static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; |
b4a2d31d | 173 | |
7fbc85a5 BM |
174 | static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; |
175 | module_param(ple_window, uint, 0444); | |
4b8d54f9 | 176 | |
b4a2d31d | 177 | /* Default doubles per-vcpu window every exit. */ |
c8e88717 | 178 | static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; |
7fbc85a5 | 179 | module_param(ple_window_grow, uint, 0444); |
b4a2d31d RK |
180 | |
181 | /* Default resets per-vcpu window every exit to ple_window. */ | |
c8e88717 | 182 | static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; |
7fbc85a5 | 183 | module_param(ple_window_shrink, uint, 0444); |
b4a2d31d RK |
184 | |
185 | /* Default is to compute the maximum so we can never overflow. */ | |
7fbc85a5 BM |
186 | static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; |
187 | module_param(ple_window_max, uint, 0444); | |
b4a2d31d | 188 | |
83287ea4 AK |
189 | extern const ulong vmx_return; |
190 | ||
40bbb9d0 SC |
191 | struct kvm_vmx { |
192 | struct kvm kvm; | |
193 | ||
194 | unsigned int tss_addr; | |
195 | bool ept_identity_pagetable_done; | |
196 | gpa_t ept_identity_map_addr; | |
197 | }; | |
198 | ||
8bf00a52 | 199 | #define NR_AUTOLOAD_MSRS 8 |
61d2ef2c | 200 | |
a2fa3e9f GH |
201 | struct vmcs { |
202 | u32 revision_id; | |
203 | u32 abort; | |
204 | char data[0]; | |
205 | }; | |
206 | ||
d462b819 NHE |
207 | /* |
208 | * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also | |
209 | * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs | |
210 | * loaded on this CPU (so we can clear them if the CPU goes down). | |
211 | */ | |
212 | struct loaded_vmcs { | |
213 | struct vmcs *vmcs; | |
355f4fb1 | 214 | struct vmcs *shadow_vmcs; |
d462b819 | 215 | int cpu; |
4c4a6f79 PB |
216 | bool launched; |
217 | bool nmi_known_unmasked; | |
44889942 LP |
218 | unsigned long vmcs_host_cr3; /* May not match real cr3 */ |
219 | unsigned long vmcs_host_cr4; /* May not match real cr4 */ | |
8a1b4392 PB |
220 | /* Support for vnmi-less CPUs */ |
221 | int soft_vnmi_blocked; | |
222 | ktime_t entry_time; | |
223 | s64 vnmi_blocked_time; | |
904e14fb | 224 | unsigned long *msr_bitmap; |
d462b819 NHE |
225 | struct list_head loaded_vmcss_on_cpu_link; |
226 | }; | |
227 | ||
26bb0981 AK |
228 | struct shared_msr_entry { |
229 | unsigned index; | |
230 | u64 data; | |
d5696725 | 231 | u64 mask; |
26bb0981 AK |
232 | }; |
233 | ||
a9d30f33 NHE |
234 | /* |
235 | * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a | |
236 | * single nested guest (L2), hence the name vmcs12. Any VMX implementation has | |
237 | * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is | |
238 | * stored in guest memory specified by VMPTRLD, but is opaque to the guest, | |
239 | * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. | |
240 | * More than one of these structures may exist, if L1 runs multiple L2 guests. | |
de3a0021 | 241 | * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the |
a9d30f33 NHE |
242 | * underlying hardware which will be used to run L2. |
243 | * This structure is packed to ensure that its layout is identical across | |
244 | * machines (necessary for live migration). | |
245 | * If there are changes in this struct, VMCS12_REVISION must be changed. | |
246 | */ | |
22bd0358 | 247 | typedef u64 natural_width; |
a9d30f33 NHE |
248 | struct __packed vmcs12 { |
249 | /* According to the Intel spec, a VMCS region must start with the | |
250 | * following two fields. Then follow implementation-specific data. | |
251 | */ | |
252 | u32 revision_id; | |
253 | u32 abort; | |
22bd0358 | 254 | |
27d6c865 NHE |
255 | u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ |
256 | u32 padding[7]; /* room for future expansion */ | |
257 | ||
22bd0358 NHE |
258 | u64 io_bitmap_a; |
259 | u64 io_bitmap_b; | |
260 | u64 msr_bitmap; | |
261 | u64 vm_exit_msr_store_addr; | |
262 | u64 vm_exit_msr_load_addr; | |
263 | u64 vm_entry_msr_load_addr; | |
264 | u64 tsc_offset; | |
265 | u64 virtual_apic_page_addr; | |
266 | u64 apic_access_addr; | |
705699a1 | 267 | u64 posted_intr_desc_addr; |
27c42a1b | 268 | u64 vm_function_control; |
22bd0358 | 269 | u64 ept_pointer; |
608406e2 WV |
270 | u64 eoi_exit_bitmap0; |
271 | u64 eoi_exit_bitmap1; | |
272 | u64 eoi_exit_bitmap2; | |
273 | u64 eoi_exit_bitmap3; | |
41ab9372 | 274 | u64 eptp_list_address; |
81dc01f7 | 275 | u64 xss_exit_bitmap; |
22bd0358 NHE |
276 | u64 guest_physical_address; |
277 | u64 vmcs_link_pointer; | |
c5f983f6 | 278 | u64 pml_address; |
22bd0358 NHE |
279 | u64 guest_ia32_debugctl; |
280 | u64 guest_ia32_pat; | |
281 | u64 guest_ia32_efer; | |
282 | u64 guest_ia32_perf_global_ctrl; | |
283 | u64 guest_pdptr0; | |
284 | u64 guest_pdptr1; | |
285 | u64 guest_pdptr2; | |
286 | u64 guest_pdptr3; | |
36be0b9d | 287 | u64 guest_bndcfgs; |
22bd0358 NHE |
288 | u64 host_ia32_pat; |
289 | u64 host_ia32_efer; | |
290 | u64 host_ia32_perf_global_ctrl; | |
291 | u64 padding64[8]; /* room for future expansion */ | |
292 | /* | |
293 | * To allow migration of L1 (complete with its L2 guests) between | |
294 | * machines of different natural widths (32 or 64 bit), we cannot have | |
295 | * unsigned long fields with no explict size. We use u64 (aliased | |
296 | * natural_width) instead. Luckily, x86 is little-endian. | |
297 | */ | |
298 | natural_width cr0_guest_host_mask; | |
299 | natural_width cr4_guest_host_mask; | |
300 | natural_width cr0_read_shadow; | |
301 | natural_width cr4_read_shadow; | |
302 | natural_width cr3_target_value0; | |
303 | natural_width cr3_target_value1; | |
304 | natural_width cr3_target_value2; | |
305 | natural_width cr3_target_value3; | |
306 | natural_width exit_qualification; | |
307 | natural_width guest_linear_address; | |
308 | natural_width guest_cr0; | |
309 | natural_width guest_cr3; | |
310 | natural_width guest_cr4; | |
311 | natural_width guest_es_base; | |
312 | natural_width guest_cs_base; | |
313 | natural_width guest_ss_base; | |
314 | natural_width guest_ds_base; | |
315 | natural_width guest_fs_base; | |
316 | natural_width guest_gs_base; | |
317 | natural_width guest_ldtr_base; | |
318 | natural_width guest_tr_base; | |
319 | natural_width guest_gdtr_base; | |
320 | natural_width guest_idtr_base; | |
321 | natural_width guest_dr7; | |
322 | natural_width guest_rsp; | |
323 | natural_width guest_rip; | |
324 | natural_width guest_rflags; | |
325 | natural_width guest_pending_dbg_exceptions; | |
326 | natural_width guest_sysenter_esp; | |
327 | natural_width guest_sysenter_eip; | |
328 | natural_width host_cr0; | |
329 | natural_width host_cr3; | |
330 | natural_width host_cr4; | |
331 | natural_width host_fs_base; | |
332 | natural_width host_gs_base; | |
333 | natural_width host_tr_base; | |
334 | natural_width host_gdtr_base; | |
335 | natural_width host_idtr_base; | |
336 | natural_width host_ia32_sysenter_esp; | |
337 | natural_width host_ia32_sysenter_eip; | |
338 | natural_width host_rsp; | |
339 | natural_width host_rip; | |
340 | natural_width paddingl[8]; /* room for future expansion */ | |
341 | u32 pin_based_vm_exec_control; | |
342 | u32 cpu_based_vm_exec_control; | |
343 | u32 exception_bitmap; | |
344 | u32 page_fault_error_code_mask; | |
345 | u32 page_fault_error_code_match; | |
346 | u32 cr3_target_count; | |
347 | u32 vm_exit_controls; | |
348 | u32 vm_exit_msr_store_count; | |
349 | u32 vm_exit_msr_load_count; | |
350 | u32 vm_entry_controls; | |
351 | u32 vm_entry_msr_load_count; | |
352 | u32 vm_entry_intr_info_field; | |
353 | u32 vm_entry_exception_error_code; | |
354 | u32 vm_entry_instruction_len; | |
355 | u32 tpr_threshold; | |
356 | u32 secondary_vm_exec_control; | |
357 | u32 vm_instruction_error; | |
358 | u32 vm_exit_reason; | |
359 | u32 vm_exit_intr_info; | |
360 | u32 vm_exit_intr_error_code; | |
361 | u32 idt_vectoring_info_field; | |
362 | u32 idt_vectoring_error_code; | |
363 | u32 vm_exit_instruction_len; | |
364 | u32 vmx_instruction_info; | |
365 | u32 guest_es_limit; | |
366 | u32 guest_cs_limit; | |
367 | u32 guest_ss_limit; | |
368 | u32 guest_ds_limit; | |
369 | u32 guest_fs_limit; | |
370 | u32 guest_gs_limit; | |
371 | u32 guest_ldtr_limit; | |
372 | u32 guest_tr_limit; | |
373 | u32 guest_gdtr_limit; | |
374 | u32 guest_idtr_limit; | |
375 | u32 guest_es_ar_bytes; | |
376 | u32 guest_cs_ar_bytes; | |
377 | u32 guest_ss_ar_bytes; | |
378 | u32 guest_ds_ar_bytes; | |
379 | u32 guest_fs_ar_bytes; | |
380 | u32 guest_gs_ar_bytes; | |
381 | u32 guest_ldtr_ar_bytes; | |
382 | u32 guest_tr_ar_bytes; | |
383 | u32 guest_interruptibility_info; | |
384 | u32 guest_activity_state; | |
385 | u32 guest_sysenter_cs; | |
386 | u32 host_ia32_sysenter_cs; | |
0238ea91 JK |
387 | u32 vmx_preemption_timer_value; |
388 | u32 padding32[7]; /* room for future expansion */ | |
22bd0358 | 389 | u16 virtual_processor_id; |
705699a1 | 390 | u16 posted_intr_nv; |
22bd0358 NHE |
391 | u16 guest_es_selector; |
392 | u16 guest_cs_selector; | |
393 | u16 guest_ss_selector; | |
394 | u16 guest_ds_selector; | |
395 | u16 guest_fs_selector; | |
396 | u16 guest_gs_selector; | |
397 | u16 guest_ldtr_selector; | |
398 | u16 guest_tr_selector; | |
608406e2 | 399 | u16 guest_intr_status; |
c5f983f6 | 400 | u16 guest_pml_index; |
22bd0358 NHE |
401 | u16 host_es_selector; |
402 | u16 host_cs_selector; | |
403 | u16 host_ss_selector; | |
404 | u16 host_ds_selector; | |
405 | u16 host_fs_selector; | |
406 | u16 host_gs_selector; | |
407 | u16 host_tr_selector; | |
a9d30f33 NHE |
408 | }; |
409 | ||
410 | /* | |
411 | * VMCS12_REVISION is an arbitrary id that should be changed if the content or | |
412 | * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and | |
413 | * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. | |
414 | */ | |
415 | #define VMCS12_REVISION 0x11e57ed0 | |
416 | ||
417 | /* | |
418 | * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region | |
419 | * and any VMCS region. Although only sizeof(struct vmcs12) are used by the | |
420 | * current implementation, 4K are reserved to avoid future complications. | |
421 | */ | |
422 | #define VMCS12_SIZE 0x1000 | |
423 | ||
5b15706d JM |
424 | /* |
425 | * VMCS12_MAX_FIELD_INDEX is the highest index value used in any | |
426 | * supported VMCS12 field encoding. | |
427 | */ | |
428 | #define VMCS12_MAX_FIELD_INDEX 0x17 | |
429 | ||
6677f3da PB |
430 | struct nested_vmx_msrs { |
431 | /* | |
432 | * We only store the "true" versions of the VMX capability MSRs. We | |
433 | * generate the "non-true" versions by setting the must-be-1 bits | |
434 | * according to the SDM. | |
435 | */ | |
436 | u32 procbased_ctls_low; | |
437 | u32 procbased_ctls_high; | |
438 | u32 secondary_ctls_low; | |
439 | u32 secondary_ctls_high; | |
440 | u32 pinbased_ctls_low; | |
441 | u32 pinbased_ctls_high; | |
442 | u32 exit_ctls_low; | |
443 | u32 exit_ctls_high; | |
444 | u32 entry_ctls_low; | |
445 | u32 entry_ctls_high; | |
446 | u32 misc_low; | |
447 | u32 misc_high; | |
448 | u32 ept_caps; | |
449 | u32 vpid_caps; | |
450 | u64 basic; | |
451 | u64 cr0_fixed0; | |
452 | u64 cr0_fixed1; | |
453 | u64 cr4_fixed0; | |
454 | u64 cr4_fixed1; | |
455 | u64 vmcs_enum; | |
456 | u64 vmfunc_controls; | |
457 | }; | |
458 | ||
ec378aee NHE |
459 | /* |
460 | * The nested_vmx structure is part of vcpu_vmx, and holds information we need | |
461 | * for correct emulation of VMX (i.e., nested VMX) on this vcpu. | |
462 | */ | |
463 | struct nested_vmx { | |
464 | /* Has the level1 guest done vmxon? */ | |
465 | bool vmxon; | |
3573e22c | 466 | gpa_t vmxon_ptr; |
c5f983f6 | 467 | bool pml_full; |
a9d30f33 NHE |
468 | |
469 | /* The guest-physical address of the current VMCS L1 keeps for L2 */ | |
470 | gpa_t current_vmptr; | |
4f2777bc DM |
471 | /* |
472 | * Cache of the guest's VMCS, existing outside of guest memory. | |
473 | * Loaded from guest memory during VMPTRLD. Flushed to guest | |
8ca44e88 | 474 | * memory during VMCLEAR and VMPTRLD. |
4f2777bc DM |
475 | */ |
476 | struct vmcs12 *cached_vmcs12; | |
012f83cb AG |
477 | /* |
478 | * Indicates if the shadow vmcs must be updated with the | |
479 | * data hold by vmcs12 | |
480 | */ | |
481 | bool sync_shadow_vmcs; | |
74a497fa | 482 | bool dirty_vmcs12; |
ff2f6fe9 | 483 | |
dccbfcf5 | 484 | bool change_vmcs01_virtual_x2apic_mode; |
644d711a NHE |
485 | /* L2 must run next, and mustn't decide to exit to L1. */ |
486 | bool nested_run_pending; | |
de3a0021 JM |
487 | |
488 | struct loaded_vmcs vmcs02; | |
489 | ||
fe3ef05c | 490 | /* |
de3a0021 JM |
491 | * Guest pages referred to in the vmcs02 with host-physical |
492 | * pointers, so we must keep them pinned while L2 runs. | |
fe3ef05c NHE |
493 | */ |
494 | struct page *apic_access_page; | |
a7c0b07d | 495 | struct page *virtual_apic_page; |
705699a1 WV |
496 | struct page *pi_desc_page; |
497 | struct pi_desc *pi_desc; | |
498 | bool pi_pending; | |
499 | u16 posted_intr_nv; | |
f4124500 JK |
500 | |
501 | struct hrtimer preemption_timer; | |
502 | bool preemption_timer_expired; | |
2996fca0 JK |
503 | |
504 | /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ | |
505 | u64 vmcs01_debugctl; | |
b9c237bb | 506 | |
5c614b35 WL |
507 | u16 vpid02; |
508 | u16 last_vpid; | |
509 | ||
6677f3da | 510 | struct nested_vmx_msrs msrs; |
72e9cbdb LP |
511 | |
512 | /* SMM related state */ | |
513 | struct { | |
514 | /* in VMX operation on SMM entry? */ | |
515 | bool vmxon; | |
516 | /* in guest mode on SMM entry? */ | |
517 | bool guest_mode; | |
518 | } smm; | |
ec378aee NHE |
519 | }; |
520 | ||
01e439be | 521 | #define POSTED_INTR_ON 0 |
ebbfc765 FW |
522 | #define POSTED_INTR_SN 1 |
523 | ||
01e439be YZ |
524 | /* Posted-Interrupt Descriptor */ |
525 | struct pi_desc { | |
526 | u32 pir[8]; /* Posted interrupt requested */ | |
6ef1522f FW |
527 | union { |
528 | struct { | |
529 | /* bit 256 - Outstanding Notification */ | |
530 | u16 on : 1, | |
531 | /* bit 257 - Suppress Notification */ | |
532 | sn : 1, | |
533 | /* bit 271:258 - Reserved */ | |
534 | rsvd_1 : 14; | |
535 | /* bit 279:272 - Notification Vector */ | |
536 | u8 nv; | |
537 | /* bit 287:280 - Reserved */ | |
538 | u8 rsvd_2; | |
539 | /* bit 319:288 - Notification Destination */ | |
540 | u32 ndst; | |
541 | }; | |
542 | u64 control; | |
543 | }; | |
544 | u32 rsvd[6]; | |
01e439be YZ |
545 | } __aligned(64); |
546 | ||
a20ed54d YZ |
547 | static bool pi_test_and_set_on(struct pi_desc *pi_desc) |
548 | { | |
549 | return test_and_set_bit(POSTED_INTR_ON, | |
550 | (unsigned long *)&pi_desc->control); | |
551 | } | |
552 | ||
553 | static bool pi_test_and_clear_on(struct pi_desc *pi_desc) | |
554 | { | |
555 | return test_and_clear_bit(POSTED_INTR_ON, | |
556 | (unsigned long *)&pi_desc->control); | |
557 | } | |
558 | ||
559 | static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) | |
560 | { | |
561 | return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); | |
562 | } | |
563 | ||
ebbfc765 FW |
564 | static inline void pi_clear_sn(struct pi_desc *pi_desc) |
565 | { | |
566 | return clear_bit(POSTED_INTR_SN, | |
567 | (unsigned long *)&pi_desc->control); | |
568 | } | |
569 | ||
570 | static inline void pi_set_sn(struct pi_desc *pi_desc) | |
571 | { | |
572 | return set_bit(POSTED_INTR_SN, | |
573 | (unsigned long *)&pi_desc->control); | |
574 | } | |
575 | ||
ad361091 PB |
576 | static inline void pi_clear_on(struct pi_desc *pi_desc) |
577 | { | |
578 | clear_bit(POSTED_INTR_ON, | |
579 | (unsigned long *)&pi_desc->control); | |
580 | } | |
581 | ||
ebbfc765 FW |
582 | static inline int pi_test_on(struct pi_desc *pi_desc) |
583 | { | |
584 | return test_bit(POSTED_INTR_ON, | |
585 | (unsigned long *)&pi_desc->control); | |
586 | } | |
587 | ||
588 | static inline int pi_test_sn(struct pi_desc *pi_desc) | |
589 | { | |
590 | return test_bit(POSTED_INTR_SN, | |
591 | (unsigned long *)&pi_desc->control); | |
592 | } | |
593 | ||
a2fa3e9f | 594 | struct vcpu_vmx { |
fb3f0f51 | 595 | struct kvm_vcpu vcpu; |
313dbd49 | 596 | unsigned long host_rsp; |
29bd8a78 | 597 | u8 fail; |
904e14fb | 598 | u8 msr_bitmap_mode; |
51aa01d1 | 599 | u32 exit_intr_info; |
1155f76a | 600 | u32 idt_vectoring_info; |
6de12732 | 601 | ulong rflags; |
26bb0981 | 602 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
603 | int nmsrs; |
604 | int save_nmsrs; | |
a547c6db | 605 | unsigned long host_idt_base; |
a2fa3e9f | 606 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
607 | u64 msr_host_kernel_gs_base; |
608 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f | 609 | #endif |
15d45071 | 610 | |
28c1c9fa | 611 | u64 arch_capabilities; |
d28b387f | 612 | u64 spec_ctrl; |
28c1c9fa | 613 | |
2961e876 GN |
614 | u32 vm_entry_controls_shadow; |
615 | u32 vm_exit_controls_shadow; | |
80154d77 PB |
616 | u32 secondary_exec_control; |
617 | ||
d462b819 NHE |
618 | /* |
619 | * loaded_vmcs points to the VMCS currently used in this vcpu. For a | |
620 | * non-nested (L1) guest, it always points to vmcs01. For a nested | |
621 | * guest (L2), it points to a different VMCS. | |
622 | */ | |
623 | struct loaded_vmcs vmcs01; | |
624 | struct loaded_vmcs *loaded_vmcs; | |
625 | bool __launched; /* temporary, used in vmx_vcpu_run */ | |
61d2ef2c AK |
626 | struct msr_autoload { |
627 | unsigned nr; | |
628 | struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; | |
629 | struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; | |
630 | } msr_autoload; | |
a2fa3e9f GH |
631 | struct { |
632 | int loaded; | |
633 | u16 fs_sel, gs_sel, ldt_sel; | |
b2da15ac AK |
634 | #ifdef CONFIG_X86_64 |
635 | u16 ds_sel, es_sel; | |
636 | #endif | |
152d3f2f LV |
637 | int gs_ldt_reload_needed; |
638 | int fs_reload_needed; | |
da8999d3 | 639 | u64 msr_host_bndcfgs; |
d77c26fc | 640 | } host_state; |
9c8cba37 | 641 | struct { |
7ffd92c5 | 642 | int vm86_active; |
78ac8b47 | 643 | ulong save_rflags; |
f5f7b2fe AK |
644 | struct kvm_segment segs[8]; |
645 | } rmode; | |
646 | struct { | |
647 | u32 bitmask; /* 4 bits per segment (1 bit per field) */ | |
7ffd92c5 AK |
648 | struct kvm_save_segment { |
649 | u16 selector; | |
650 | unsigned long base; | |
651 | u32 limit; | |
652 | u32 ar; | |
f5f7b2fe | 653 | } seg[8]; |
2fb92db1 | 654 | } segment_cache; |
2384d2b3 | 655 | int vpid; |
04fa4d32 | 656 | bool emulation_required; |
3b86cd99 | 657 | |
a0861c02 | 658 | u32 exit_reason; |
4e47c7a6 | 659 | |
01e439be YZ |
660 | /* Posted interrupt descriptor */ |
661 | struct pi_desc pi_desc; | |
662 | ||
ec378aee NHE |
663 | /* Support for a guest hypervisor (nested VMX) */ |
664 | struct nested_vmx nested; | |
a7653ecd RK |
665 | |
666 | /* Dynamic PLE window. */ | |
667 | int ple_window; | |
668 | bool ple_window_dirty; | |
843e4330 KH |
669 | |
670 | /* Support for PML */ | |
671 | #define PML_ENTITY_NUM 512 | |
672 | struct page *pml_pg; | |
2680d6da | 673 | |
64672c95 YJ |
674 | /* apic deadline value in host tsc */ |
675 | u64 hv_deadline_tsc; | |
676 | ||
2680d6da | 677 | u64 current_tsc_ratio; |
1be0e61c | 678 | |
1be0e61c | 679 | u32 host_pkru; |
3b84080b | 680 | |
74c55931 WL |
681 | unsigned long host_debugctlmsr; |
682 | ||
37e4c997 HZ |
683 | /* |
684 | * Only bits masked by msr_ia32_feature_control_valid_bits can be set in | |
685 | * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included | |
686 | * in msr_ia32_feature_control_valid_bits. | |
687 | */ | |
3b84080b | 688 | u64 msr_ia32_feature_control; |
37e4c997 | 689 | u64 msr_ia32_feature_control_valid_bits; |
a2fa3e9f GH |
690 | }; |
691 | ||
2fb92db1 AK |
692 | enum segment_cache_field { |
693 | SEG_FIELD_SEL = 0, | |
694 | SEG_FIELD_BASE = 1, | |
695 | SEG_FIELD_LIMIT = 2, | |
696 | SEG_FIELD_AR = 3, | |
697 | ||
698 | SEG_FIELD_NR = 4 | |
699 | }; | |
700 | ||
40bbb9d0 SC |
701 | static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm) |
702 | { | |
703 | return container_of(kvm, struct kvm_vmx, kvm); | |
704 | } | |
705 | ||
a2fa3e9f GH |
706 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
707 | { | |
fb3f0f51 | 708 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
709 | } |
710 | ||
efc64404 FW |
711 | static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu) |
712 | { | |
713 | return &(to_vmx(vcpu)->pi_desc); | |
714 | } | |
715 | ||
58e9ffae | 716 | #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n))))) |
22bd0358 | 717 | #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x) |
58e9ffae JM |
718 | #define FIELD(number, name) [ROL16(number, 6)] = VMCS12_OFFSET(name) |
719 | #define FIELD64(number, name) \ | |
720 | FIELD(number, name), \ | |
721 | [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32) | |
22bd0358 | 722 | |
4607c2d7 | 723 | |
44900ba6 | 724 | static u16 shadow_read_only_fields[] = { |
c9e9deae PB |
725 | #define SHADOW_FIELD_RO(x) x, |
726 | #include "vmx_shadow_fields.h" | |
4607c2d7 | 727 | }; |
fe2b201b | 728 | static int max_shadow_read_only_fields = |
4607c2d7 AG |
729 | ARRAY_SIZE(shadow_read_only_fields); |
730 | ||
44900ba6 | 731 | static u16 shadow_read_write_fields[] = { |
c9e9deae PB |
732 | #define SHADOW_FIELD_RW(x) x, |
733 | #include "vmx_shadow_fields.h" | |
4607c2d7 | 734 | }; |
fe2b201b | 735 | static int max_shadow_read_write_fields = |
4607c2d7 AG |
736 | ARRAY_SIZE(shadow_read_write_fields); |
737 | ||
772e0318 | 738 | static const unsigned short vmcs_field_to_offset_table[] = { |
22bd0358 | 739 | FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id), |
705699a1 | 740 | FIELD(POSTED_INTR_NV, posted_intr_nv), |
22bd0358 NHE |
741 | FIELD(GUEST_ES_SELECTOR, guest_es_selector), |
742 | FIELD(GUEST_CS_SELECTOR, guest_cs_selector), | |
743 | FIELD(GUEST_SS_SELECTOR, guest_ss_selector), | |
744 | FIELD(GUEST_DS_SELECTOR, guest_ds_selector), | |
745 | FIELD(GUEST_FS_SELECTOR, guest_fs_selector), | |
746 | FIELD(GUEST_GS_SELECTOR, guest_gs_selector), | |
747 | FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector), | |
748 | FIELD(GUEST_TR_SELECTOR, guest_tr_selector), | |
608406e2 | 749 | FIELD(GUEST_INTR_STATUS, guest_intr_status), |
c5f983f6 | 750 | FIELD(GUEST_PML_INDEX, guest_pml_index), |
22bd0358 NHE |
751 | FIELD(HOST_ES_SELECTOR, host_es_selector), |
752 | FIELD(HOST_CS_SELECTOR, host_cs_selector), | |
753 | FIELD(HOST_SS_SELECTOR, host_ss_selector), | |
754 | FIELD(HOST_DS_SELECTOR, host_ds_selector), | |
755 | FIELD(HOST_FS_SELECTOR, host_fs_selector), | |
756 | FIELD(HOST_GS_SELECTOR, host_gs_selector), | |
757 | FIELD(HOST_TR_SELECTOR, host_tr_selector), | |
758 | FIELD64(IO_BITMAP_A, io_bitmap_a), | |
759 | FIELD64(IO_BITMAP_B, io_bitmap_b), | |
760 | FIELD64(MSR_BITMAP, msr_bitmap), | |
761 | FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr), | |
762 | FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr), | |
763 | FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr), | |
764 | FIELD64(TSC_OFFSET, tsc_offset), | |
765 | FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), | |
766 | FIELD64(APIC_ACCESS_ADDR, apic_access_addr), | |
705699a1 | 767 | FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr), |
27c42a1b | 768 | FIELD64(VM_FUNCTION_CONTROL, vm_function_control), |
22bd0358 | 769 | FIELD64(EPT_POINTER, ept_pointer), |
608406e2 WV |
770 | FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0), |
771 | FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1), | |
772 | FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2), | |
773 | FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3), | |
41ab9372 | 774 | FIELD64(EPTP_LIST_ADDRESS, eptp_list_address), |
81dc01f7 | 775 | FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap), |
22bd0358 NHE |
776 | FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), |
777 | FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), | |
c5f983f6 | 778 | FIELD64(PML_ADDRESS, pml_address), |
22bd0358 NHE |
779 | FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), |
780 | FIELD64(GUEST_IA32_PAT, guest_ia32_pat), | |
781 | FIELD64(GUEST_IA32_EFER, guest_ia32_efer), | |
782 | FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl), | |
783 | FIELD64(GUEST_PDPTR0, guest_pdptr0), | |
784 | FIELD64(GUEST_PDPTR1, guest_pdptr1), | |
785 | FIELD64(GUEST_PDPTR2, guest_pdptr2), | |
786 | FIELD64(GUEST_PDPTR3, guest_pdptr3), | |
36be0b9d | 787 | FIELD64(GUEST_BNDCFGS, guest_bndcfgs), |
22bd0358 NHE |
788 | FIELD64(HOST_IA32_PAT, host_ia32_pat), |
789 | FIELD64(HOST_IA32_EFER, host_ia32_efer), | |
790 | FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), | |
791 | FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), | |
792 | FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), | |
793 | FIELD(EXCEPTION_BITMAP, exception_bitmap), | |
794 | FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask), | |
795 | FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match), | |
796 | FIELD(CR3_TARGET_COUNT, cr3_target_count), | |
797 | FIELD(VM_EXIT_CONTROLS, vm_exit_controls), | |
798 | FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count), | |
799 | FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count), | |
800 | FIELD(VM_ENTRY_CONTROLS, vm_entry_controls), | |
801 | FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count), | |
802 | FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field), | |
803 | FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code), | |
804 | FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len), | |
805 | FIELD(TPR_THRESHOLD, tpr_threshold), | |
806 | FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control), | |
807 | FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error), | |
808 | FIELD(VM_EXIT_REASON, vm_exit_reason), | |
809 | FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info), | |
810 | FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code), | |
811 | FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field), | |
812 | FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code), | |
813 | FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len), | |
814 | FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info), | |
815 | FIELD(GUEST_ES_LIMIT, guest_es_limit), | |
816 | FIELD(GUEST_CS_LIMIT, guest_cs_limit), | |
817 | FIELD(GUEST_SS_LIMIT, guest_ss_limit), | |
818 | FIELD(GUEST_DS_LIMIT, guest_ds_limit), | |
819 | FIELD(GUEST_FS_LIMIT, guest_fs_limit), | |
820 | FIELD(GUEST_GS_LIMIT, guest_gs_limit), | |
821 | FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit), | |
822 | FIELD(GUEST_TR_LIMIT, guest_tr_limit), | |
823 | FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit), | |
824 | FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit), | |
825 | FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes), | |
826 | FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes), | |
827 | FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes), | |
828 | FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes), | |
829 | FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes), | |
830 | FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes), | |
831 | FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes), | |
832 | FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes), | |
833 | FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info), | |
834 | FIELD(GUEST_ACTIVITY_STATE, guest_activity_state), | |
835 | FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs), | |
836 | FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs), | |
0238ea91 | 837 | FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value), |
22bd0358 NHE |
838 | FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask), |
839 | FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask), | |
840 | FIELD(CR0_READ_SHADOW, cr0_read_shadow), | |
841 | FIELD(CR4_READ_SHADOW, cr4_read_shadow), | |
842 | FIELD(CR3_TARGET_VALUE0, cr3_target_value0), | |
843 | FIELD(CR3_TARGET_VALUE1, cr3_target_value1), | |
844 | FIELD(CR3_TARGET_VALUE2, cr3_target_value2), | |
845 | FIELD(CR3_TARGET_VALUE3, cr3_target_value3), | |
846 | FIELD(EXIT_QUALIFICATION, exit_qualification), | |
847 | FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address), | |
848 | FIELD(GUEST_CR0, guest_cr0), | |
849 | FIELD(GUEST_CR3, guest_cr3), | |
850 | FIELD(GUEST_CR4, guest_cr4), | |
851 | FIELD(GUEST_ES_BASE, guest_es_base), | |
852 | FIELD(GUEST_CS_BASE, guest_cs_base), | |
853 | FIELD(GUEST_SS_BASE, guest_ss_base), | |
854 | FIELD(GUEST_DS_BASE, guest_ds_base), | |
855 | FIELD(GUEST_FS_BASE, guest_fs_base), | |
856 | FIELD(GUEST_GS_BASE, guest_gs_base), | |
857 | FIELD(GUEST_LDTR_BASE, guest_ldtr_base), | |
858 | FIELD(GUEST_TR_BASE, guest_tr_base), | |
859 | FIELD(GUEST_GDTR_BASE, guest_gdtr_base), | |
860 | FIELD(GUEST_IDTR_BASE, guest_idtr_base), | |
861 | FIELD(GUEST_DR7, guest_dr7), | |
862 | FIELD(GUEST_RSP, guest_rsp), | |
863 | FIELD(GUEST_RIP, guest_rip), | |
864 | FIELD(GUEST_RFLAGS, guest_rflags), | |
865 | FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions), | |
866 | FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp), | |
867 | FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip), | |
868 | FIELD(HOST_CR0, host_cr0), | |
869 | FIELD(HOST_CR3, host_cr3), | |
870 | FIELD(HOST_CR4, host_cr4), | |
871 | FIELD(HOST_FS_BASE, host_fs_base), | |
872 | FIELD(HOST_GS_BASE, host_gs_base), | |
873 | FIELD(HOST_TR_BASE, host_tr_base), | |
874 | FIELD(HOST_GDTR_BASE, host_gdtr_base), | |
875 | FIELD(HOST_IDTR_BASE, host_idtr_base), | |
876 | FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp), | |
877 | FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip), | |
878 | FIELD(HOST_RSP, host_rsp), | |
879 | FIELD(HOST_RIP, host_rip), | |
880 | }; | |
22bd0358 NHE |
881 | |
882 | static inline short vmcs_field_to_offset(unsigned long field) | |
883 | { | |
085331df DW |
884 | const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table); |
885 | unsigned short offset; | |
58e9ffae JM |
886 | unsigned index; |
887 | ||
888 | if (field >> 15) | |
889 | return -ENOENT; | |
a2ae9df7 | 890 | |
58e9ffae | 891 | index = ROL16(field, 6); |
15303ba5 | 892 | if (index >= size) |
75f139aa AH |
893 | return -ENOENT; |
894 | ||
15303ba5 LT |
895 | index = array_index_nospec(index, size); |
896 | offset = vmcs_field_to_offset_table[index]; | |
085331df | 897 | if (offset == 0) |
a2ae9df7 | 898 | return -ENOENT; |
085331df | 899 | return offset; |
22bd0358 NHE |
900 | } |
901 | ||
a9d30f33 NHE |
902 | static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
903 | { | |
4f2777bc | 904 | return to_vmx(vcpu)->nested.cached_vmcs12; |
a9d30f33 NHE |
905 | } |
906 | ||
995f00a6 | 907 | static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu); |
bfd0a56b | 908 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu); |
995f00a6 | 909 | static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa); |
f53cd63c | 910 | static bool vmx_xsaves_supported(void); |
b246dd5d OW |
911 | static void vmx_set_segment(struct kvm_vcpu *vcpu, |
912 | struct kvm_segment *var, int seg); | |
913 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
914 | struct kvm_segment *var, int seg); | |
d99e4152 GN |
915 | static bool guest_state_valid(struct kvm_vcpu *vcpu); |
916 | static u32 vmx_segment_access_rights(struct kvm_segment *var); | |
16f5b903 | 917 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx); |
b96fb439 PB |
918 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); |
919 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); | |
920 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, | |
921 | u16 error_code); | |
904e14fb | 922 | static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu); |
15d45071 AR |
923 | static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, |
924 | u32 msr, int type); | |
75880a01 | 925 | |
6aa8b732 AK |
926 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
927 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
d462b819 NHE |
928 | /* |
929 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
930 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
931 | */ | |
932 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
6aa8b732 | 933 | |
bf9f6ac8 FW |
934 | /* |
935 | * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we | |
936 | * can find which vCPU should be waken up. | |
937 | */ | |
938 | static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); | |
939 | static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); | |
940 | ||
23611332 | 941 | enum { |
23611332 RK |
942 | VMX_VMREAD_BITMAP, |
943 | VMX_VMWRITE_BITMAP, | |
944 | VMX_BITMAP_NR | |
945 | }; | |
946 | ||
947 | static unsigned long *vmx_bitmap[VMX_BITMAP_NR]; | |
948 | ||
23611332 RK |
949 | #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP]) |
950 | #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP]) | |
fdef3ad1 | 951 | |
110312c8 | 952 | static bool cpu_has_load_ia32_efer; |
8bf00a52 | 953 | static bool cpu_has_load_perf_global_ctrl; |
110312c8 | 954 | |
2384d2b3 SY |
955 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
956 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
957 | ||
1c3d14fe | 958 | static struct vmcs_config { |
6aa8b732 AK |
959 | int size; |
960 | int order; | |
9ac7e3e8 | 961 | u32 basic_cap; |
6aa8b732 | 962 | u32 revision_id; |
1c3d14fe YS |
963 | u32 pin_based_exec_ctrl; |
964 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 965 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
966 | u32 vmexit_ctrl; |
967 | u32 vmentry_ctrl; | |
1389309c | 968 | struct nested_vmx_msrs nested; |
1c3d14fe | 969 | } vmcs_config; |
6aa8b732 | 970 | |
efff9e53 | 971 | static struct vmx_capability { |
d56f546d SY |
972 | u32 ept; |
973 | u32 vpid; | |
974 | } vmx_capability; | |
975 | ||
6aa8b732 AK |
976 | #define VMX_SEGMENT_FIELD(seg) \ |
977 | [VCPU_SREG_##seg] = { \ | |
978 | .selector = GUEST_##seg##_SELECTOR, \ | |
979 | .base = GUEST_##seg##_BASE, \ | |
980 | .limit = GUEST_##seg##_LIMIT, \ | |
981 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
982 | } | |
983 | ||
772e0318 | 984 | static const struct kvm_vmx_segment_field { |
6aa8b732 AK |
985 | unsigned selector; |
986 | unsigned base; | |
987 | unsigned limit; | |
988 | unsigned ar_bytes; | |
989 | } kvm_vmx_segment_fields[] = { | |
990 | VMX_SEGMENT_FIELD(CS), | |
991 | VMX_SEGMENT_FIELD(DS), | |
992 | VMX_SEGMENT_FIELD(ES), | |
993 | VMX_SEGMENT_FIELD(FS), | |
994 | VMX_SEGMENT_FIELD(GS), | |
995 | VMX_SEGMENT_FIELD(SS), | |
996 | VMX_SEGMENT_FIELD(TR), | |
997 | VMX_SEGMENT_FIELD(LDTR), | |
998 | }; | |
999 | ||
26bb0981 AK |
1000 | static u64 host_efer; |
1001 | ||
6de4f3ad AK |
1002 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
1003 | ||
4d56c8a7 | 1004 | /* |
8c06585d | 1005 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
1006 | * away by decrementing the array size. |
1007 | */ | |
6aa8b732 | 1008 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 1009 | #ifdef CONFIG_X86_64 |
44ea2b17 | 1010 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 1011 | #endif |
8c06585d | 1012 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 1013 | }; |
6aa8b732 | 1014 | |
773e8a04 VK |
1015 | DEFINE_STATIC_KEY_FALSE(enable_evmcs); |
1016 | ||
1017 | #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs)) | |
1018 | ||
1019 | #define KVM_EVMCS_VERSION 1 | |
1020 | ||
1021 | #if IS_ENABLED(CONFIG_HYPERV) | |
1022 | static bool __read_mostly enlightened_vmcs = true; | |
1023 | module_param(enlightened_vmcs, bool, 0444); | |
1024 | ||
1025 | static inline void evmcs_write64(unsigned long field, u64 value) | |
1026 | { | |
1027 | u16 clean_field; | |
1028 | int offset = get_evmcs_offset(field, &clean_field); | |
1029 | ||
1030 | if (offset < 0) | |
1031 | return; | |
1032 | ||
1033 | *(u64 *)((char *)current_evmcs + offset) = value; | |
1034 | ||
1035 | current_evmcs->hv_clean_fields &= ~clean_field; | |
1036 | } | |
1037 | ||
1038 | static inline void evmcs_write32(unsigned long field, u32 value) | |
1039 | { | |
1040 | u16 clean_field; | |
1041 | int offset = get_evmcs_offset(field, &clean_field); | |
1042 | ||
1043 | if (offset < 0) | |
1044 | return; | |
1045 | ||
1046 | *(u32 *)((char *)current_evmcs + offset) = value; | |
1047 | current_evmcs->hv_clean_fields &= ~clean_field; | |
1048 | } | |
1049 | ||
1050 | static inline void evmcs_write16(unsigned long field, u16 value) | |
1051 | { | |
1052 | u16 clean_field; | |
1053 | int offset = get_evmcs_offset(field, &clean_field); | |
1054 | ||
1055 | if (offset < 0) | |
1056 | return; | |
1057 | ||
1058 | *(u16 *)((char *)current_evmcs + offset) = value; | |
1059 | current_evmcs->hv_clean_fields &= ~clean_field; | |
1060 | } | |
1061 | ||
1062 | static inline u64 evmcs_read64(unsigned long field) | |
1063 | { | |
1064 | int offset = get_evmcs_offset(field, NULL); | |
1065 | ||
1066 | if (offset < 0) | |
1067 | return 0; | |
1068 | ||
1069 | return *(u64 *)((char *)current_evmcs + offset); | |
1070 | } | |
1071 | ||
1072 | static inline u32 evmcs_read32(unsigned long field) | |
1073 | { | |
1074 | int offset = get_evmcs_offset(field, NULL); | |
1075 | ||
1076 | if (offset < 0) | |
1077 | return 0; | |
1078 | ||
1079 | return *(u32 *)((char *)current_evmcs + offset); | |
1080 | } | |
1081 | ||
1082 | static inline u16 evmcs_read16(unsigned long field) | |
1083 | { | |
1084 | int offset = get_evmcs_offset(field, NULL); | |
1085 | ||
1086 | if (offset < 0) | |
1087 | return 0; | |
1088 | ||
1089 | return *(u16 *)((char *)current_evmcs + offset); | |
1090 | } | |
1091 | ||
1092 | static void evmcs_load(u64 phys_addr) | |
1093 | { | |
1094 | struct hv_vp_assist_page *vp_ap = | |
1095 | hv_get_vp_assist_page(smp_processor_id()); | |
1096 | ||
1097 | vp_ap->current_nested_vmcs = phys_addr; | |
1098 | vp_ap->enlighten_vmentry = 1; | |
1099 | } | |
1100 | ||
1101 | static void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) | |
1102 | { | |
1103 | /* | |
1104 | * Enlightened VMCSv1 doesn't support these: | |
1105 | * | |
1106 | * POSTED_INTR_NV = 0x00000002, | |
1107 | * GUEST_INTR_STATUS = 0x00000810, | |
1108 | * APIC_ACCESS_ADDR = 0x00002014, | |
1109 | * POSTED_INTR_DESC_ADDR = 0x00002016, | |
1110 | * EOI_EXIT_BITMAP0 = 0x0000201c, | |
1111 | * EOI_EXIT_BITMAP1 = 0x0000201e, | |
1112 | * EOI_EXIT_BITMAP2 = 0x00002020, | |
1113 | * EOI_EXIT_BITMAP3 = 0x00002022, | |
1114 | */ | |
1115 | vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; | |
1116 | vmcs_conf->cpu_based_2nd_exec_ctrl &= | |
1117 | ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; | |
1118 | vmcs_conf->cpu_based_2nd_exec_ctrl &= | |
1119 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1120 | vmcs_conf->cpu_based_2nd_exec_ctrl &= | |
1121 | ~SECONDARY_EXEC_APIC_REGISTER_VIRT; | |
1122 | ||
1123 | /* | |
1124 | * GUEST_PML_INDEX = 0x00000812, | |
1125 | * PML_ADDRESS = 0x0000200e, | |
1126 | */ | |
1127 | vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_PML; | |
1128 | ||
1129 | /* VM_FUNCTION_CONTROL = 0x00002018, */ | |
1130 | vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_VMFUNC; | |
1131 | ||
1132 | /* | |
1133 | * EPTP_LIST_ADDRESS = 0x00002024, | |
1134 | * VMREAD_BITMAP = 0x00002026, | |
1135 | * VMWRITE_BITMAP = 0x00002028, | |
1136 | */ | |
1137 | vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
1138 | ||
1139 | /* | |
1140 | * TSC_MULTIPLIER = 0x00002032, | |
1141 | */ | |
1142 | vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_TSC_SCALING; | |
1143 | ||
1144 | /* | |
1145 | * PLE_GAP = 0x00004020, | |
1146 | * PLE_WINDOW = 0x00004022, | |
1147 | */ | |
1148 | vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
1149 | ||
1150 | /* | |
1151 | * VMX_PREEMPTION_TIMER_VALUE = 0x0000482E, | |
1152 | */ | |
1153 | vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
1154 | ||
1155 | /* | |
1156 | * GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808, | |
1157 | * HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04, | |
1158 | */ | |
1159 | vmcs_conf->vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; | |
1160 | vmcs_conf->vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; | |
1161 | ||
1162 | /* | |
1163 | * Currently unsupported in KVM: | |
1164 | * GUEST_IA32_RTIT_CTL = 0x00002814, | |
1165 | */ | |
1166 | } | |
1167 | #else /* !IS_ENABLED(CONFIG_HYPERV) */ | |
1168 | static inline void evmcs_write64(unsigned long field, u64 value) {} | |
1169 | static inline void evmcs_write32(unsigned long field, u32 value) {} | |
1170 | static inline void evmcs_write16(unsigned long field, u16 value) {} | |
1171 | static inline u64 evmcs_read64(unsigned long field) { return 0; } | |
1172 | static inline u32 evmcs_read32(unsigned long field) { return 0; } | |
1173 | static inline u16 evmcs_read16(unsigned long field) { return 0; } | |
1174 | static inline void evmcs_load(u64 phys_addr) {} | |
1175 | static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {} | |
1176 | #endif /* IS_ENABLED(CONFIG_HYPERV) */ | |
1177 | ||
5bb16016 | 1178 | static inline bool is_exception_n(u32 intr_info, u8 vector) |
6aa8b732 AK |
1179 | { |
1180 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1181 | INTR_INFO_VALID_MASK)) == | |
5bb16016 JK |
1182 | (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK); |
1183 | } | |
1184 | ||
6f05485d JK |
1185 | static inline bool is_debug(u32 intr_info) |
1186 | { | |
1187 | return is_exception_n(intr_info, DB_VECTOR); | |
1188 | } | |
1189 | ||
1190 | static inline bool is_breakpoint(u32 intr_info) | |
1191 | { | |
1192 | return is_exception_n(intr_info, BP_VECTOR); | |
1193 | } | |
1194 | ||
5bb16016 JK |
1195 | static inline bool is_page_fault(u32 intr_info) |
1196 | { | |
1197 | return is_exception_n(intr_info, PF_VECTOR); | |
6aa8b732 AK |
1198 | } |
1199 | ||
31299944 | 1200 | static inline bool is_no_device(u32 intr_info) |
2ab455cc | 1201 | { |
5bb16016 | 1202 | return is_exception_n(intr_info, NM_VECTOR); |
2ab455cc AL |
1203 | } |
1204 | ||
31299944 | 1205 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 | 1206 | { |
5bb16016 | 1207 | return is_exception_n(intr_info, UD_VECTOR); |
7aa81cc0 AL |
1208 | } |
1209 | ||
9e869480 LA |
1210 | static inline bool is_gp_fault(u32 intr_info) |
1211 | { | |
1212 | return is_exception_n(intr_info, GP_VECTOR); | |
1213 | } | |
1214 | ||
31299944 | 1215 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
1216 | { |
1217 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1218 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1219 | } | |
1220 | ||
31299944 | 1221 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
1222 | { |
1223 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1224 | INTR_INFO_VALID_MASK)) == | |
1225 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
1226 | } | |
1227 | ||
32d43cd3 LT |
1228 | /* Undocumented: icebp/int1 */ |
1229 | static inline bool is_icebp(u32 intr_info) | |
1230 | { | |
1231 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1232 | == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK); | |
1233 | } | |
1234 | ||
31299944 | 1235 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 1236 | { |
04547156 | 1237 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
1238 | } |
1239 | ||
31299944 | 1240 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 1241 | { |
04547156 | 1242 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
1243 | } |
1244 | ||
35754c98 | 1245 | static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) |
6e5d865c | 1246 | { |
35754c98 | 1247 | return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); |
6e5d865c YS |
1248 | } |
1249 | ||
31299944 | 1250 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 1251 | { |
04547156 SY |
1252 | return vmcs_config.cpu_based_exec_ctrl & |
1253 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
1254 | } |
1255 | ||
774ead3a | 1256 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 1257 | { |
04547156 SY |
1258 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1259 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1260 | } | |
1261 | ||
8d14695f YZ |
1262 | static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) |
1263 | { | |
1264 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1265 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
1266 | } | |
1267 | ||
83d4c286 YZ |
1268 | static inline bool cpu_has_vmx_apic_register_virt(void) |
1269 | { | |
1270 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1271 | SECONDARY_EXEC_APIC_REGISTER_VIRT; | |
1272 | } | |
1273 | ||
c7c9c56c YZ |
1274 | static inline bool cpu_has_vmx_virtual_intr_delivery(void) |
1275 | { | |
1276 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1277 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; | |
1278 | } | |
1279 | ||
64672c95 YJ |
1280 | /* |
1281 | * Comment's format: document - errata name - stepping - processor name. | |
1282 | * Refer from | |
1283 | * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp | |
1284 | */ | |
1285 | static u32 vmx_preemption_cpu_tfms[] = { | |
1286 | /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ | |
1287 | 0x000206E6, | |
1288 | /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ | |
1289 | /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ | |
1290 | /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1291 | 0x00020652, | |
1292 | /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1293 | 0x00020655, | |
1294 | /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ | |
1295 | /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ | |
1296 | /* | |
1297 | * 320767.pdf - AAP86 - B1 - | |
1298 | * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile | |
1299 | */ | |
1300 | 0x000106E5, | |
1301 | /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ | |
1302 | 0x000106A0, | |
1303 | /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ | |
1304 | 0x000106A1, | |
1305 | /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ | |
1306 | 0x000106A4, | |
1307 | /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ | |
1308 | /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ | |
1309 | /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ | |
1310 | 0x000106A5, | |
1311 | }; | |
1312 | ||
1313 | static inline bool cpu_has_broken_vmx_preemption_timer(void) | |
1314 | { | |
1315 | u32 eax = cpuid_eax(0x00000001), i; | |
1316 | ||
1317 | /* Clear the reserved bits */ | |
1318 | eax &= ~(0x3U << 14 | 0xfU << 28); | |
03f6a22a | 1319 | for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) |
64672c95 YJ |
1320 | if (eax == vmx_preemption_cpu_tfms[i]) |
1321 | return true; | |
1322 | ||
1323 | return false; | |
1324 | } | |
1325 | ||
1326 | static inline bool cpu_has_vmx_preemption_timer(void) | |
1327 | { | |
64672c95 YJ |
1328 | return vmcs_config.pin_based_exec_ctrl & |
1329 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1330 | } | |
1331 | ||
01e439be YZ |
1332 | static inline bool cpu_has_vmx_posted_intr(void) |
1333 | { | |
d6a858d1 PB |
1334 | return IS_ENABLED(CONFIG_X86_LOCAL_APIC) && |
1335 | vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; | |
01e439be YZ |
1336 | } |
1337 | ||
1338 | static inline bool cpu_has_vmx_apicv(void) | |
1339 | { | |
1340 | return cpu_has_vmx_apic_register_virt() && | |
1341 | cpu_has_vmx_virtual_intr_delivery() && | |
1342 | cpu_has_vmx_posted_intr(); | |
1343 | } | |
1344 | ||
04547156 SY |
1345 | static inline bool cpu_has_vmx_flexpriority(void) |
1346 | { | |
1347 | return cpu_has_vmx_tpr_shadow() && | |
1348 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
1349 | } |
1350 | ||
e799794e MT |
1351 | static inline bool cpu_has_vmx_ept_execute_only(void) |
1352 | { | |
31299944 | 1353 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
1354 | } |
1355 | ||
e799794e MT |
1356 | static inline bool cpu_has_vmx_ept_2m_page(void) |
1357 | { | |
31299944 | 1358 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
1359 | } |
1360 | ||
878403b7 SY |
1361 | static inline bool cpu_has_vmx_ept_1g_page(void) |
1362 | { | |
31299944 | 1363 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
1364 | } |
1365 | ||
4bc9b982 SY |
1366 | static inline bool cpu_has_vmx_ept_4levels(void) |
1367 | { | |
1368 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
1369 | } | |
1370 | ||
42aa53b4 DH |
1371 | static inline bool cpu_has_vmx_ept_mt_wb(void) |
1372 | { | |
1373 | return vmx_capability.ept & VMX_EPTP_WB_BIT; | |
1374 | } | |
1375 | ||
855feb67 YZ |
1376 | static inline bool cpu_has_vmx_ept_5levels(void) |
1377 | { | |
1378 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT; | |
1379 | } | |
1380 | ||
83c3a331 XH |
1381 | static inline bool cpu_has_vmx_ept_ad_bits(void) |
1382 | { | |
1383 | return vmx_capability.ept & VMX_EPT_AD_BIT; | |
1384 | } | |
1385 | ||
31299944 | 1386 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 1387 | { |
31299944 | 1388 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
1389 | } |
1390 | ||
31299944 | 1391 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 1392 | { |
31299944 | 1393 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
1394 | } |
1395 | ||
518c8aee GJ |
1396 | static inline bool cpu_has_vmx_invvpid_single(void) |
1397 | { | |
1398 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
1399 | } | |
1400 | ||
b9d762fa GJ |
1401 | static inline bool cpu_has_vmx_invvpid_global(void) |
1402 | { | |
1403 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
1404 | } | |
1405 | ||
08d839c4 WL |
1406 | static inline bool cpu_has_vmx_invvpid(void) |
1407 | { | |
1408 | return vmx_capability.vpid & VMX_VPID_INVVPID_BIT; | |
1409 | } | |
1410 | ||
31299944 | 1411 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 1412 | { |
04547156 SY |
1413 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1414 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
1415 | } |
1416 | ||
31299944 | 1417 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
1418 | { |
1419 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1420 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
1421 | } | |
1422 | ||
31299944 | 1423 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
1424 | { |
1425 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1426 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
1427 | } | |
1428 | ||
9ac7e3e8 JD |
1429 | static inline bool cpu_has_vmx_basic_inout(void) |
1430 | { | |
1431 | return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT); | |
1432 | } | |
1433 | ||
35754c98 | 1434 | static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) |
f78e0e2e | 1435 | { |
35754c98 | 1436 | return flexpriority_enabled && lapic_in_kernel(vcpu); |
f78e0e2e SY |
1437 | } |
1438 | ||
31299944 | 1439 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 1440 | { |
04547156 SY |
1441 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1442 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
1443 | } |
1444 | ||
31299944 | 1445 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
1446 | { |
1447 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1448 | SECONDARY_EXEC_RDTSCP; | |
1449 | } | |
1450 | ||
ad756a16 MJ |
1451 | static inline bool cpu_has_vmx_invpcid(void) |
1452 | { | |
1453 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1454 | SECONDARY_EXEC_ENABLE_INVPCID; | |
1455 | } | |
1456 | ||
8a1b4392 PB |
1457 | static inline bool cpu_has_virtual_nmis(void) |
1458 | { | |
1459 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
1460 | } | |
1461 | ||
f5f48ee1 SY |
1462 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
1463 | { | |
1464 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1465 | SECONDARY_EXEC_WBINVD_EXITING; | |
1466 | } | |
1467 | ||
abc4fc58 AG |
1468 | static inline bool cpu_has_vmx_shadow_vmcs(void) |
1469 | { | |
1470 | u64 vmx_msr; | |
1471 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
1472 | /* check if the cpu supports writing r/o exit information fields */ | |
1473 | if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) | |
1474 | return false; | |
1475 | ||
1476 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1477 | SECONDARY_EXEC_SHADOW_VMCS; | |
1478 | } | |
1479 | ||
843e4330 KH |
1480 | static inline bool cpu_has_vmx_pml(void) |
1481 | { | |
1482 | return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; | |
1483 | } | |
1484 | ||
64903d61 HZ |
1485 | static inline bool cpu_has_vmx_tsc_scaling(void) |
1486 | { | |
1487 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1488 | SECONDARY_EXEC_TSC_SCALING; | |
1489 | } | |
1490 | ||
2a499e49 BD |
1491 | static inline bool cpu_has_vmx_vmfunc(void) |
1492 | { | |
1493 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1494 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
1495 | } | |
1496 | ||
64f7a115 SC |
1497 | static bool vmx_umip_emulated(void) |
1498 | { | |
1499 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1500 | SECONDARY_EXEC_DESC; | |
1501 | } | |
1502 | ||
04547156 SY |
1503 | static inline bool report_flexpriority(void) |
1504 | { | |
1505 | return flexpriority_enabled; | |
1506 | } | |
1507 | ||
c7c2c709 JM |
1508 | static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu) |
1509 | { | |
6677f3da | 1510 | return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low); |
c7c2c709 JM |
1511 | } |
1512 | ||
fe3ef05c NHE |
1513 | static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) |
1514 | { | |
1515 | return vmcs12->cpu_based_vm_exec_control & bit; | |
1516 | } | |
1517 | ||
1518 | static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) | |
1519 | { | |
1520 | return (vmcs12->cpu_based_vm_exec_control & | |
1521 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && | |
1522 | (vmcs12->secondary_vm_exec_control & bit); | |
1523 | } | |
1524 | ||
f4124500 JK |
1525 | static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) |
1526 | { | |
1527 | return vmcs12->pin_based_vm_exec_control & | |
1528 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1529 | } | |
1530 | ||
0c7f650e KS |
1531 | static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12) |
1532 | { | |
1533 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING; | |
1534 | } | |
1535 | ||
1536 | static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12) | |
1537 | { | |
1538 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS; | |
1539 | } | |
1540 | ||
155a97a3 NHE |
1541 | static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) |
1542 | { | |
1543 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); | |
1544 | } | |
1545 | ||
81dc01f7 WL |
1546 | static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) |
1547 | { | |
3db13480 | 1548 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); |
81dc01f7 WL |
1549 | } |
1550 | ||
c5f983f6 BD |
1551 | static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12) |
1552 | { | |
1553 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML); | |
1554 | } | |
1555 | ||
f2b93280 WV |
1556 | static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) |
1557 | { | |
1558 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); | |
1559 | } | |
1560 | ||
5c614b35 WL |
1561 | static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) |
1562 | { | |
1563 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); | |
1564 | } | |
1565 | ||
82f0dd4b WV |
1566 | static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) |
1567 | { | |
1568 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); | |
1569 | } | |
1570 | ||
608406e2 WV |
1571 | static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) |
1572 | { | |
1573 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
1574 | } | |
1575 | ||
705699a1 WV |
1576 | static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) |
1577 | { | |
1578 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; | |
1579 | } | |
1580 | ||
27c42a1b BD |
1581 | static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12) |
1582 | { | |
1583 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC); | |
1584 | } | |
1585 | ||
41ab9372 BD |
1586 | static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12) |
1587 | { | |
1588 | return nested_cpu_has_vmfunc(vmcs12) && | |
1589 | (vmcs12->vm_function_control & | |
1590 | VMX_VMFUNC_EPTP_SWITCHING); | |
1591 | } | |
1592 | ||
ef85b673 | 1593 | static inline bool is_nmi(u32 intr_info) |
644d711a NHE |
1594 | { |
1595 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
ef85b673 | 1596 | == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK); |
644d711a NHE |
1597 | } |
1598 | ||
533558bc JK |
1599 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
1600 | u32 exit_intr_info, | |
1601 | unsigned long exit_qualification); | |
7c177938 NHE |
1602 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, |
1603 | struct vmcs12 *vmcs12, | |
1604 | u32 reason, unsigned long qualification); | |
1605 | ||
8b9cf98c | 1606 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
1607 | { |
1608 | int i; | |
1609 | ||
a2fa3e9f | 1610 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 1611 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
1612 | return i; |
1613 | return -1; | |
1614 | } | |
1615 | ||
2384d2b3 SY |
1616 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
1617 | { | |
1618 | struct { | |
1619 | u64 vpid : 16; | |
1620 | u64 rsvd : 48; | |
1621 | u64 gva; | |
1622 | } operand = { vpid, 0, gva }; | |
1623 | ||
4ecac3fd | 1624 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
1625 | /* CF==1 or ZF==1 --> rc = -1 */ |
1626 | "; ja 1f ; ud2 ; 1:" | |
1627 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
1628 | } | |
1629 | ||
1439442c SY |
1630 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
1631 | { | |
1632 | struct { | |
1633 | u64 eptp, gpa; | |
1634 | } operand = {eptp, gpa}; | |
1635 | ||
4ecac3fd | 1636 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
1637 | /* CF==1 or ZF==1 --> rc = -1 */ |
1638 | "; ja 1f ; ud2 ; 1:\n" | |
1639 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
1640 | } | |
1641 | ||
26bb0981 | 1642 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
1643 | { |
1644 | int i; | |
1645 | ||
8b9cf98c | 1646 | i = __find_msr_index(vmx, msr); |
a75beee6 | 1647 | if (i >= 0) |
a2fa3e9f | 1648 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 1649 | return NULL; |
7725f0ba AK |
1650 | } |
1651 | ||
6aa8b732 AK |
1652 | static void vmcs_clear(struct vmcs *vmcs) |
1653 | { | |
1654 | u64 phys_addr = __pa(vmcs); | |
1655 | u8 error; | |
1656 | ||
4ecac3fd | 1657 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 1658 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
1659 | : "cc", "memory"); |
1660 | if (error) | |
1661 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
1662 | vmcs, phys_addr); | |
1663 | } | |
1664 | ||
d462b819 NHE |
1665 | static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
1666 | { | |
1667 | vmcs_clear(loaded_vmcs->vmcs); | |
355f4fb1 JM |
1668 | if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) |
1669 | vmcs_clear(loaded_vmcs->shadow_vmcs); | |
d462b819 NHE |
1670 | loaded_vmcs->cpu = -1; |
1671 | loaded_vmcs->launched = 0; | |
1672 | } | |
1673 | ||
7725b894 DX |
1674 | static void vmcs_load(struct vmcs *vmcs) |
1675 | { | |
1676 | u64 phys_addr = __pa(vmcs); | |
1677 | u8 error; | |
1678 | ||
773e8a04 VK |
1679 | if (static_branch_unlikely(&enable_evmcs)) |
1680 | return evmcs_load(phys_addr); | |
1681 | ||
7725b894 | 1682 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" |
16d8f72f | 1683 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
1684 | : "cc", "memory"); |
1685 | if (error) | |
2844d849 | 1686 | printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n", |
7725b894 DX |
1687 | vmcs, phys_addr); |
1688 | } | |
1689 | ||
2965faa5 | 1690 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
1691 | /* |
1692 | * This bitmap is used to indicate whether the vmclear | |
1693 | * operation is enabled on all cpus. All disabled by | |
1694 | * default. | |
1695 | */ | |
1696 | static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; | |
1697 | ||
1698 | static inline void crash_enable_local_vmclear(int cpu) | |
1699 | { | |
1700 | cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1701 | } | |
1702 | ||
1703 | static inline void crash_disable_local_vmclear(int cpu) | |
1704 | { | |
1705 | cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1706 | } | |
1707 | ||
1708 | static inline int crash_local_vmclear_enabled(int cpu) | |
1709 | { | |
1710 | return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1711 | } | |
1712 | ||
1713 | static void crash_vmclear_local_loaded_vmcss(void) | |
1714 | { | |
1715 | int cpu = raw_smp_processor_id(); | |
1716 | struct loaded_vmcs *v; | |
1717 | ||
1718 | if (!crash_local_vmclear_enabled(cpu)) | |
1719 | return; | |
1720 | ||
1721 | list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), | |
1722 | loaded_vmcss_on_cpu_link) | |
1723 | vmcs_clear(v->vmcs); | |
1724 | } | |
1725 | #else | |
1726 | static inline void crash_enable_local_vmclear(int cpu) { } | |
1727 | static inline void crash_disable_local_vmclear(int cpu) { } | |
2965faa5 | 1728 | #endif /* CONFIG_KEXEC_CORE */ |
8f536b76 | 1729 | |
d462b819 | 1730 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 1731 | { |
d462b819 | 1732 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 1733 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 1734 | |
d462b819 NHE |
1735 | if (loaded_vmcs->cpu != cpu) |
1736 | return; /* vcpu migration can race with cpu offline */ | |
1737 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 1738 | per_cpu(current_vmcs, cpu) = NULL; |
8f536b76 | 1739 | crash_disable_local_vmclear(cpu); |
d462b819 | 1740 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
5a560f8b XG |
1741 | |
1742 | /* | |
1743 | * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link | |
1744 | * is before setting loaded_vmcs->vcpu to -1 which is done in | |
1745 | * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist | |
1746 | * then adds the vmcs into percpu list before it is deleted. | |
1747 | */ | |
1748 | smp_wmb(); | |
1749 | ||
d462b819 | 1750 | loaded_vmcs_init(loaded_vmcs); |
8f536b76 | 1751 | crash_enable_local_vmclear(cpu); |
6aa8b732 AK |
1752 | } |
1753 | ||
d462b819 | 1754 | static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 1755 | { |
e6c7d321 XG |
1756 | int cpu = loaded_vmcs->cpu; |
1757 | ||
1758 | if (cpu != -1) | |
1759 | smp_call_function_single(cpu, | |
1760 | __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
1761 | } |
1762 | ||
dd5f5341 | 1763 | static inline void vpid_sync_vcpu_single(int vpid) |
2384d2b3 | 1764 | { |
dd5f5341 | 1765 | if (vpid == 0) |
2384d2b3 SY |
1766 | return; |
1767 | ||
518c8aee | 1768 | if (cpu_has_vmx_invvpid_single()) |
dd5f5341 | 1769 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0); |
2384d2b3 SY |
1770 | } |
1771 | ||
b9d762fa GJ |
1772 | static inline void vpid_sync_vcpu_global(void) |
1773 | { | |
1774 | if (cpu_has_vmx_invvpid_global()) | |
1775 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
1776 | } | |
1777 | ||
dd5f5341 | 1778 | static inline void vpid_sync_context(int vpid) |
b9d762fa GJ |
1779 | { |
1780 | if (cpu_has_vmx_invvpid_single()) | |
dd5f5341 | 1781 | vpid_sync_vcpu_single(vpid); |
b9d762fa GJ |
1782 | else |
1783 | vpid_sync_vcpu_global(); | |
1784 | } | |
1785 | ||
1439442c SY |
1786 | static inline void ept_sync_global(void) |
1787 | { | |
f5f51586 | 1788 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); |
1439442c SY |
1789 | } |
1790 | ||
1791 | static inline void ept_sync_context(u64 eptp) | |
1792 | { | |
0e1252dc DH |
1793 | if (cpu_has_vmx_invept_context()) |
1794 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
1795 | else | |
1796 | ept_sync_global(); | |
1439442c SY |
1797 | } |
1798 | ||
8a86aea9 PB |
1799 | static __always_inline void vmcs_check16(unsigned long field) |
1800 | { | |
1801 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1802 | "16-bit accessor invalid for 64-bit field"); | |
1803 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1804 | "16-bit accessor invalid for 64-bit high field"); | |
1805 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1806 | "16-bit accessor invalid for 32-bit high field"); | |
1807 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1808 | "16-bit accessor invalid for natural width field"); | |
1809 | } | |
1810 | ||
1811 | static __always_inline void vmcs_check32(unsigned long field) | |
1812 | { | |
1813 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1814 | "32-bit accessor invalid for 16-bit field"); | |
1815 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1816 | "32-bit accessor invalid for natural width field"); | |
1817 | } | |
1818 | ||
1819 | static __always_inline void vmcs_check64(unsigned long field) | |
1820 | { | |
1821 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1822 | "64-bit accessor invalid for 16-bit field"); | |
1823 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1824 | "64-bit accessor invalid for 64-bit high field"); | |
1825 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1826 | "64-bit accessor invalid for 32-bit field"); | |
1827 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1828 | "64-bit accessor invalid for natural width field"); | |
1829 | } | |
1830 | ||
1831 | static __always_inline void vmcs_checkl(unsigned long field) | |
1832 | { | |
1833 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1834 | "Natural width accessor invalid for 16-bit field"); | |
1835 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1836 | "Natural width accessor invalid for 64-bit field"); | |
1837 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1838 | "Natural width accessor invalid for 64-bit high field"); | |
1839 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1840 | "Natural width accessor invalid for 32-bit field"); | |
1841 | } | |
1842 | ||
1843 | static __always_inline unsigned long __vmcs_readl(unsigned long field) | |
6aa8b732 | 1844 | { |
5e520e62 | 1845 | unsigned long value; |
6aa8b732 | 1846 | |
5e520e62 AK |
1847 | asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
1848 | : "=a"(value) : "d"(field) : "cc"); | |
6aa8b732 AK |
1849 | return value; |
1850 | } | |
1851 | ||
96304217 | 1852 | static __always_inline u16 vmcs_read16(unsigned long field) |
6aa8b732 | 1853 | { |
8a86aea9 | 1854 | vmcs_check16(field); |
773e8a04 VK |
1855 | if (static_branch_unlikely(&enable_evmcs)) |
1856 | return evmcs_read16(field); | |
8a86aea9 | 1857 | return __vmcs_readl(field); |
6aa8b732 AK |
1858 | } |
1859 | ||
96304217 | 1860 | static __always_inline u32 vmcs_read32(unsigned long field) |
6aa8b732 | 1861 | { |
8a86aea9 | 1862 | vmcs_check32(field); |
773e8a04 VK |
1863 | if (static_branch_unlikely(&enable_evmcs)) |
1864 | return evmcs_read32(field); | |
8a86aea9 | 1865 | return __vmcs_readl(field); |
6aa8b732 AK |
1866 | } |
1867 | ||
96304217 | 1868 | static __always_inline u64 vmcs_read64(unsigned long field) |
6aa8b732 | 1869 | { |
8a86aea9 | 1870 | vmcs_check64(field); |
773e8a04 VK |
1871 | if (static_branch_unlikely(&enable_evmcs)) |
1872 | return evmcs_read64(field); | |
05b3e0c2 | 1873 | #ifdef CONFIG_X86_64 |
8a86aea9 | 1874 | return __vmcs_readl(field); |
6aa8b732 | 1875 | #else |
8a86aea9 | 1876 | return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32); |
6aa8b732 AK |
1877 | #endif |
1878 | } | |
1879 | ||
8a86aea9 PB |
1880 | static __always_inline unsigned long vmcs_readl(unsigned long field) |
1881 | { | |
1882 | vmcs_checkl(field); | |
773e8a04 VK |
1883 | if (static_branch_unlikely(&enable_evmcs)) |
1884 | return evmcs_read64(field); | |
8a86aea9 PB |
1885 | return __vmcs_readl(field); |
1886 | } | |
1887 | ||
e52de1b8 AK |
1888 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
1889 | { | |
1890 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
1891 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1892 | dump_stack(); | |
1893 | } | |
1894 | ||
8a86aea9 | 1895 | static __always_inline void __vmcs_writel(unsigned long field, unsigned long value) |
6aa8b732 AK |
1896 | { |
1897 | u8 error; | |
1898 | ||
4ecac3fd | 1899 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 1900 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
1901 | if (unlikely(error)) |
1902 | vmwrite_error(field, value); | |
6aa8b732 AK |
1903 | } |
1904 | ||
8a86aea9 | 1905 | static __always_inline void vmcs_write16(unsigned long field, u16 value) |
6aa8b732 | 1906 | { |
8a86aea9 | 1907 | vmcs_check16(field); |
773e8a04 VK |
1908 | if (static_branch_unlikely(&enable_evmcs)) |
1909 | return evmcs_write16(field, value); | |
1910 | ||
8a86aea9 | 1911 | __vmcs_writel(field, value); |
6aa8b732 AK |
1912 | } |
1913 | ||
8a86aea9 | 1914 | static __always_inline void vmcs_write32(unsigned long field, u32 value) |
6aa8b732 | 1915 | { |
8a86aea9 | 1916 | vmcs_check32(field); |
773e8a04 VK |
1917 | if (static_branch_unlikely(&enable_evmcs)) |
1918 | return evmcs_write32(field, value); | |
1919 | ||
8a86aea9 | 1920 | __vmcs_writel(field, value); |
6aa8b732 AK |
1921 | } |
1922 | ||
8a86aea9 | 1923 | static __always_inline void vmcs_write64(unsigned long field, u64 value) |
6aa8b732 | 1924 | { |
8a86aea9 | 1925 | vmcs_check64(field); |
773e8a04 VK |
1926 | if (static_branch_unlikely(&enable_evmcs)) |
1927 | return evmcs_write64(field, value); | |
1928 | ||
8a86aea9 | 1929 | __vmcs_writel(field, value); |
7682f2d0 | 1930 | #ifndef CONFIG_X86_64 |
6aa8b732 | 1931 | asm volatile (""); |
8a86aea9 | 1932 | __vmcs_writel(field+1, value >> 32); |
6aa8b732 AK |
1933 | #endif |
1934 | } | |
1935 | ||
8a86aea9 | 1936 | static __always_inline void vmcs_writel(unsigned long field, unsigned long value) |
2ab455cc | 1937 | { |
8a86aea9 | 1938 | vmcs_checkl(field); |
773e8a04 VK |
1939 | if (static_branch_unlikely(&enable_evmcs)) |
1940 | return evmcs_write64(field, value); | |
1941 | ||
8a86aea9 | 1942 | __vmcs_writel(field, value); |
2ab455cc AL |
1943 | } |
1944 | ||
8a86aea9 | 1945 | static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask) |
2ab455cc | 1946 | { |
8a86aea9 PB |
1947 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1948 | "vmcs_clear_bits does not support 64-bit fields"); | |
773e8a04 VK |
1949 | if (static_branch_unlikely(&enable_evmcs)) |
1950 | return evmcs_write32(field, evmcs_read32(field) & ~mask); | |
1951 | ||
8a86aea9 | 1952 | __vmcs_writel(field, __vmcs_readl(field) & ~mask); |
2ab455cc AL |
1953 | } |
1954 | ||
8a86aea9 | 1955 | static __always_inline void vmcs_set_bits(unsigned long field, u32 mask) |
2ab455cc | 1956 | { |
8a86aea9 PB |
1957 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1958 | "vmcs_set_bits does not support 64-bit fields"); | |
773e8a04 VK |
1959 | if (static_branch_unlikely(&enable_evmcs)) |
1960 | return evmcs_write32(field, evmcs_read32(field) | mask); | |
1961 | ||
8a86aea9 | 1962 | __vmcs_writel(field, __vmcs_readl(field) | mask); |
2ab455cc AL |
1963 | } |
1964 | ||
8391ce44 PB |
1965 | static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx) |
1966 | { | |
1967 | vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS); | |
1968 | } | |
1969 | ||
2961e876 GN |
1970 | static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val) |
1971 | { | |
1972 | vmcs_write32(VM_ENTRY_CONTROLS, val); | |
1973 | vmx->vm_entry_controls_shadow = val; | |
1974 | } | |
1975 | ||
1976 | static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1977 | { | |
1978 | if (vmx->vm_entry_controls_shadow != val) | |
1979 | vm_entry_controls_init(vmx, val); | |
1980 | } | |
1981 | ||
1982 | static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx) | |
1983 | { | |
1984 | return vmx->vm_entry_controls_shadow; | |
1985 | } | |
1986 | ||
1987 | ||
1988 | static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1989 | { | |
1990 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val); | |
1991 | } | |
1992 | ||
1993 | static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1994 | { | |
1995 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val); | |
1996 | } | |
1997 | ||
8391ce44 PB |
1998 | static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx) |
1999 | { | |
2000 | vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS); | |
2001 | } | |
2002 | ||
2961e876 GN |
2003 | static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val) |
2004 | { | |
2005 | vmcs_write32(VM_EXIT_CONTROLS, val); | |
2006 | vmx->vm_exit_controls_shadow = val; | |
2007 | } | |
2008 | ||
2009 | static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val) | |
2010 | { | |
2011 | if (vmx->vm_exit_controls_shadow != val) | |
2012 | vm_exit_controls_init(vmx, val); | |
2013 | } | |
2014 | ||
2015 | static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx) | |
2016 | { | |
2017 | return vmx->vm_exit_controls_shadow; | |
2018 | } | |
2019 | ||
2020 | ||
2021 | static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
2022 | { | |
2023 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val); | |
2024 | } | |
2025 | ||
2026 | static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
2027 | { | |
2028 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val); | |
2029 | } | |
2030 | ||
2fb92db1 AK |
2031 | static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
2032 | { | |
2033 | vmx->segment_cache.bitmask = 0; | |
2034 | } | |
2035 | ||
2036 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, | |
2037 | unsigned field) | |
2038 | { | |
2039 | bool ret; | |
2040 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
2041 | ||
2042 | if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { | |
2043 | vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); | |
2044 | vmx->segment_cache.bitmask = 0; | |
2045 | } | |
2046 | ret = vmx->segment_cache.bitmask & mask; | |
2047 | vmx->segment_cache.bitmask |= mask; | |
2048 | return ret; | |
2049 | } | |
2050 | ||
2051 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
2052 | { | |
2053 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
2054 | ||
2055 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
2056 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
2057 | return *p; | |
2058 | } | |
2059 | ||
2060 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
2061 | { | |
2062 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
2063 | ||
2064 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
2065 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
2066 | return *p; | |
2067 | } | |
2068 | ||
2069 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
2070 | { | |
2071 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
2072 | ||
2073 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
2074 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
2075 | return *p; | |
2076 | } | |
2077 | ||
2078 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
2079 | { | |
2080 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
2081 | ||
2082 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
2083 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
2084 | return *p; | |
2085 | } | |
2086 | ||
abd3f2d6 AK |
2087 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
2088 | { | |
2089 | u32 eb; | |
2090 | ||
fd7373cc | 2091 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
bd7e5b08 | 2092 | (1u << DB_VECTOR) | (1u << AC_VECTOR); |
9e869480 LA |
2093 | /* |
2094 | * Guest access to VMware backdoor ports could legitimately | |
2095 | * trigger #GP because of TSS I/O permission bitmap. | |
2096 | * We intercept those #GP and allow access to them anyway | |
2097 | * as VMware does. | |
2098 | */ | |
2099 | if (enable_vmware_backdoor) | |
2100 | eb |= (1u << GP_VECTOR); | |
fd7373cc JK |
2101 | if ((vcpu->guest_debug & |
2102 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
2103 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
2104 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 2105 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 2106 | eb = ~0; |
089d034e | 2107 | if (enable_ept) |
1439442c | 2108 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
36cf24e0 NHE |
2109 | |
2110 | /* When we are running a nested L2 guest and L1 specified for it a | |
2111 | * certain exception bitmap, we must trap the same exceptions and pass | |
2112 | * them to L1. When running L2, we will only handle the exceptions | |
2113 | * specified above if L1 did not want them. | |
2114 | */ | |
2115 | if (is_guest_mode(vcpu)) | |
2116 | eb |= get_vmcs12(vcpu)->exception_bitmap; | |
2117 | ||
abd3f2d6 AK |
2118 | vmcs_write32(EXCEPTION_BITMAP, eb); |
2119 | } | |
2120 | ||
d28b387f KA |
2121 | /* |
2122 | * Check if MSR is intercepted for currently loaded MSR bitmap. | |
2123 | */ | |
2124 | static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) | |
2125 | { | |
2126 | unsigned long *msr_bitmap; | |
2127 | int f = sizeof(unsigned long); | |
2128 | ||
2129 | if (!cpu_has_vmx_msr_bitmap()) | |
2130 | return true; | |
2131 | ||
2132 | msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; | |
2133 | ||
2134 | if (msr <= 0x1fff) { | |
2135 | return !!test_bit(msr, msr_bitmap + 0x800 / f); | |
2136 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
2137 | msr &= 0x1fff; | |
2138 | return !!test_bit(msr, msr_bitmap + 0xc00 / f); | |
2139 | } | |
2140 | ||
2141 | return true; | |
2142 | } | |
2143 | ||
15d45071 AR |
2144 | /* |
2145 | * Check if MSR is intercepted for L01 MSR bitmap. | |
2146 | */ | |
2147 | static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr) | |
2148 | { | |
2149 | unsigned long *msr_bitmap; | |
2150 | int f = sizeof(unsigned long); | |
2151 | ||
2152 | if (!cpu_has_vmx_msr_bitmap()) | |
2153 | return true; | |
2154 | ||
2155 | msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap; | |
2156 | ||
2157 | if (msr <= 0x1fff) { | |
2158 | return !!test_bit(msr, msr_bitmap + 0x800 / f); | |
2159 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
2160 | msr &= 0x1fff; | |
2161 | return !!test_bit(msr, msr_bitmap + 0xc00 / f); | |
2162 | } | |
2163 | ||
2164 | return true; | |
2165 | } | |
2166 | ||
2961e876 GN |
2167 | static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
2168 | unsigned long entry, unsigned long exit) | |
8bf00a52 | 2169 | { |
2961e876 GN |
2170 | vm_entry_controls_clearbit(vmx, entry); |
2171 | vm_exit_controls_clearbit(vmx, exit); | |
8bf00a52 GN |
2172 | } |
2173 | ||
61d2ef2c AK |
2174 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
2175 | { | |
2176 | unsigned i; | |
2177 | struct msr_autoload *m = &vmx->msr_autoload; | |
2178 | ||
8bf00a52 GN |
2179 | switch (msr) { |
2180 | case MSR_EFER: | |
2181 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
2182 | clear_atomic_switch_msr_special(vmx, |
2183 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
2184 | VM_EXIT_LOAD_IA32_EFER); |
2185 | return; | |
2186 | } | |
2187 | break; | |
2188 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
2189 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 2190 | clear_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
2191 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
2192 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
2193 | return; | |
2194 | } | |
2195 | break; | |
110312c8 AK |
2196 | } |
2197 | ||
61d2ef2c AK |
2198 | for (i = 0; i < m->nr; ++i) |
2199 | if (m->guest[i].index == msr) | |
2200 | break; | |
2201 | ||
2202 | if (i == m->nr) | |
2203 | return; | |
2204 | --m->nr; | |
2205 | m->guest[i] = m->guest[m->nr]; | |
2206 | m->host[i] = m->host[m->nr]; | |
2207 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
2208 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
2209 | } | |
2210 | ||
2961e876 GN |
2211 | static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
2212 | unsigned long entry, unsigned long exit, | |
2213 | unsigned long guest_val_vmcs, unsigned long host_val_vmcs, | |
2214 | u64 guest_val, u64 host_val) | |
8bf00a52 GN |
2215 | { |
2216 | vmcs_write64(guest_val_vmcs, guest_val); | |
2217 | vmcs_write64(host_val_vmcs, host_val); | |
2961e876 GN |
2218 | vm_entry_controls_setbit(vmx, entry); |
2219 | vm_exit_controls_setbit(vmx, exit); | |
8bf00a52 GN |
2220 | } |
2221 | ||
61d2ef2c AK |
2222 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
2223 | u64 guest_val, u64 host_val) | |
2224 | { | |
2225 | unsigned i; | |
2226 | struct msr_autoload *m = &vmx->msr_autoload; | |
2227 | ||
8bf00a52 GN |
2228 | switch (msr) { |
2229 | case MSR_EFER: | |
2230 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
2231 | add_atomic_switch_msr_special(vmx, |
2232 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
2233 | VM_EXIT_LOAD_IA32_EFER, |
2234 | GUEST_IA32_EFER, | |
2235 | HOST_IA32_EFER, | |
2236 | guest_val, host_val); | |
2237 | return; | |
2238 | } | |
2239 | break; | |
2240 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
2241 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 2242 | add_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
2243 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
2244 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, | |
2245 | GUEST_IA32_PERF_GLOBAL_CTRL, | |
2246 | HOST_IA32_PERF_GLOBAL_CTRL, | |
2247 | guest_val, host_val); | |
2248 | return; | |
2249 | } | |
2250 | break; | |
7099e2e1 RK |
2251 | case MSR_IA32_PEBS_ENABLE: |
2252 | /* PEBS needs a quiescent period after being disabled (to write | |
2253 | * a record). Disabling PEBS through VMX MSR swapping doesn't | |
2254 | * provide that period, so a CPU could write host's record into | |
2255 | * guest's memory. | |
2256 | */ | |
2257 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
110312c8 AK |
2258 | } |
2259 | ||
61d2ef2c AK |
2260 | for (i = 0; i < m->nr; ++i) |
2261 | if (m->guest[i].index == msr) | |
2262 | break; | |
2263 | ||
e7fc6f93 | 2264 | if (i == NR_AUTOLOAD_MSRS) { |
60266204 | 2265 | printk_once(KERN_WARNING "Not enough msr switch entries. " |
e7fc6f93 GN |
2266 | "Can't add msr %x\n", msr); |
2267 | return; | |
2268 | } else if (i == m->nr) { | |
61d2ef2c AK |
2269 | ++m->nr; |
2270 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
2271 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
2272 | } | |
2273 | ||
2274 | m->guest[i].index = msr; | |
2275 | m->guest[i].value = guest_val; | |
2276 | m->host[i].index = msr; | |
2277 | m->host[i].value = host_val; | |
2278 | } | |
2279 | ||
92c0d900 | 2280 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 2281 | { |
844a5fe2 PB |
2282 | u64 guest_efer = vmx->vcpu.arch.efer; |
2283 | u64 ignore_bits = 0; | |
2284 | ||
2285 | if (!enable_ept) { | |
2286 | /* | |
2287 | * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing | |
2288 | * host CPUID is more efficient than testing guest CPUID | |
2289 | * or CR4. Host SMEP is anyway a requirement for guest SMEP. | |
2290 | */ | |
2291 | if (boot_cpu_has(X86_FEATURE_SMEP)) | |
2292 | guest_efer |= EFER_NX; | |
2293 | else if (!(guest_efer & EFER_NX)) | |
2294 | ignore_bits |= EFER_NX; | |
2295 | } | |
3a34a881 | 2296 | |
51c6cf66 | 2297 | /* |
844a5fe2 | 2298 | * LMA and LME handled by hardware; SCE meaningless outside long mode. |
51c6cf66 | 2299 | */ |
844a5fe2 | 2300 | ignore_bits |= EFER_SCE; |
51c6cf66 AK |
2301 | #ifdef CONFIG_X86_64 |
2302 | ignore_bits |= EFER_LMA | EFER_LME; | |
2303 | /* SCE is meaningful only in long mode on Intel */ | |
2304 | if (guest_efer & EFER_LMA) | |
2305 | ignore_bits &= ~(u64)EFER_SCE; | |
2306 | #endif | |
84ad33ef AK |
2307 | |
2308 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
f6577a5f AL |
2309 | |
2310 | /* | |
2311 | * On EPT, we can't emulate NX, so we must switch EFER atomically. | |
2312 | * On CPUs that support "load IA32_EFER", always switch EFER | |
2313 | * atomically, since it's faster than switching it manually. | |
2314 | */ | |
2315 | if (cpu_has_load_ia32_efer || | |
2316 | (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { | |
84ad33ef AK |
2317 | if (!(guest_efer & EFER_LMA)) |
2318 | guest_efer &= ~EFER_LME; | |
54b98bff AL |
2319 | if (guest_efer != host_efer) |
2320 | add_atomic_switch_msr(vmx, MSR_EFER, | |
2321 | guest_efer, host_efer); | |
84ad33ef | 2322 | return false; |
844a5fe2 PB |
2323 | } else { |
2324 | guest_efer &= ~ignore_bits; | |
2325 | guest_efer |= host_efer & ignore_bits; | |
2326 | ||
2327 | vmx->guest_msrs[efer_offset].data = guest_efer; | |
2328 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; | |
84ad33ef | 2329 | |
844a5fe2 PB |
2330 | return true; |
2331 | } | |
51c6cf66 AK |
2332 | } |
2333 | ||
e28baead AL |
2334 | #ifdef CONFIG_X86_32 |
2335 | /* | |
2336 | * On 32-bit kernels, VM exits still load the FS and GS bases from the | |
2337 | * VMCS rather than the segment table. KVM uses this helper to figure | |
2338 | * out the current bases to poke them into the VMCS before entry. | |
2339 | */ | |
2d49ec72 GN |
2340 | static unsigned long segment_base(u16 selector) |
2341 | { | |
8c2e41f7 | 2342 | struct desc_struct *table; |
2d49ec72 GN |
2343 | unsigned long v; |
2344 | ||
8c2e41f7 | 2345 | if (!(selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
2346 | return 0; |
2347 | ||
45fc8757 | 2348 | table = get_current_gdt_ro(); |
2d49ec72 | 2349 | |
8c2e41f7 | 2350 | if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { |
2d49ec72 GN |
2351 | u16 ldt_selector = kvm_read_ldt(); |
2352 | ||
8c2e41f7 | 2353 | if (!(ldt_selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
2354 | return 0; |
2355 | ||
8c2e41f7 | 2356 | table = (struct desc_struct *)segment_base(ldt_selector); |
2d49ec72 | 2357 | } |
8c2e41f7 | 2358 | v = get_desc_base(&table[selector >> 3]); |
2d49ec72 GN |
2359 | return v; |
2360 | } | |
e28baead | 2361 | #endif |
2d49ec72 | 2362 | |
04d2cc77 | 2363 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 2364 | { |
04d2cc77 | 2365 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
51e8a8cc | 2366 | #ifdef CONFIG_X86_64 |
35060ed6 | 2367 | int cpu = raw_smp_processor_id(); |
b062b794 | 2368 | unsigned long fs_base, kernel_gs_base; |
51e8a8cc | 2369 | #endif |
26bb0981 | 2370 | int i; |
04d2cc77 | 2371 | |
a2fa3e9f | 2372 | if (vmx->host_state.loaded) |
33ed6329 AK |
2373 | return; |
2374 | ||
a2fa3e9f | 2375 | vmx->host_state.loaded = 1; |
33ed6329 AK |
2376 | /* |
2377 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
2378 | * allow segment selectors with cpl > 0 or ti == 1. | |
2379 | */ | |
d6e88aec | 2380 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 2381 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
42b933b5 VK |
2382 | |
2383 | #ifdef CONFIG_X86_64 | |
b062b794 VK |
2384 | if (likely(is_64bit_mm(current->mm))) { |
2385 | save_fsgs_for_kvm(); | |
2386 | vmx->host_state.fs_sel = current->thread.fsindex; | |
2387 | vmx->host_state.gs_sel = current->thread.gsindex; | |
2388 | fs_base = current->thread.fsbase; | |
2389 | kernel_gs_base = current->thread.gsbase; | |
2390 | } else { | |
2391 | #endif | |
2392 | savesegment(fs, vmx->host_state.fs_sel); | |
2393 | savesegment(gs, vmx->host_state.gs_sel); | |
2394 | #ifdef CONFIG_X86_64 | |
2395 | fs_base = read_msr(MSR_FS_BASE); | |
2396 | kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); | |
2397 | } | |
42b933b5 | 2398 | #endif |
152d3f2f | 2399 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 2400 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
2401 | vmx->host_state.fs_reload_needed = 0; |
2402 | } else { | |
33ed6329 | 2403 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 2404 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 2405 | } |
a2fa3e9f GH |
2406 | if (!(vmx->host_state.gs_sel & 7)) |
2407 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
2408 | else { |
2409 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 2410 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
2411 | } |
2412 | ||
b2da15ac AK |
2413 | #ifdef CONFIG_X86_64 |
2414 | savesegment(ds, vmx->host_state.ds_sel); | |
2415 | savesegment(es, vmx->host_state.es_sel); | |
b2da15ac | 2416 | |
b062b794 | 2417 | vmcs_writel(HOST_FS_BASE, fs_base); |
35060ed6 | 2418 | vmcs_writel(HOST_GS_BASE, cpu_kernelmode_gs_base(cpu)); |
707c0874 | 2419 | |
b062b794 | 2420 | vmx->msr_host_kernel_gs_base = kernel_gs_base; |
c8770e7b | 2421 | if (is_long_mode(&vmx->vcpu)) |
44ea2b17 | 2422 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
4fde8d57 PB |
2423 | #else |
2424 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); | |
2425 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
707c0874 | 2426 | #endif |
da8999d3 LJ |
2427 | if (boot_cpu_has(X86_FEATURE_MPX)) |
2428 | rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
26bb0981 AK |
2429 | for (i = 0; i < vmx->save_nmsrs; ++i) |
2430 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
2431 | vmx->guest_msrs[i].data, |
2432 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
2433 | } |
2434 | ||
a9b21b62 | 2435 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 2436 | { |
a2fa3e9f | 2437 | if (!vmx->host_state.loaded) |
33ed6329 AK |
2438 | return; |
2439 | ||
e1beb1d3 | 2440 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 2441 | vmx->host_state.loaded = 0; |
c8770e7b AK |
2442 | #ifdef CONFIG_X86_64 |
2443 | if (is_long_mode(&vmx->vcpu)) | |
2444 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
2445 | #endif | |
152d3f2f | 2446 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 2447 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 2448 | #ifdef CONFIG_X86_64 |
9581d442 | 2449 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
2450 | #else |
2451 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 2452 | #endif |
33ed6329 | 2453 | } |
0a77fe4c AK |
2454 | if (vmx->host_state.fs_reload_needed) |
2455 | loadsegment(fs, vmx->host_state.fs_sel); | |
b2da15ac AK |
2456 | #ifdef CONFIG_X86_64 |
2457 | if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) { | |
2458 | loadsegment(ds, vmx->host_state.ds_sel); | |
2459 | loadsegment(es, vmx->host_state.es_sel); | |
2460 | } | |
b2da15ac | 2461 | #endif |
b7ffc44d | 2462 | invalidate_tss_limit(); |
44ea2b17 | 2463 | #ifdef CONFIG_X86_64 |
c8770e7b | 2464 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 2465 | #endif |
da8999d3 LJ |
2466 | if (vmx->host_state.msr_host_bndcfgs) |
2467 | wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
45fc8757 | 2468 | load_fixmap_gdt(raw_smp_processor_id()); |
33ed6329 AK |
2469 | } |
2470 | ||
a9b21b62 AK |
2471 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
2472 | { | |
2473 | preempt_disable(); | |
2474 | __vmx_load_host_state(vmx); | |
2475 | preempt_enable(); | |
2476 | } | |
2477 | ||
28b835d6 FW |
2478 | static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) |
2479 | { | |
2480 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2481 | struct pi_desc old, new; | |
2482 | unsigned int dest; | |
2483 | ||
31afb2ea PB |
2484 | /* |
2485 | * In case of hot-plug or hot-unplug, we may have to undo | |
2486 | * vmx_vcpu_pi_put even if there is no assigned device. And we | |
2487 | * always keep PI.NDST up to date for simplicity: it makes the | |
2488 | * code easier, and CPU migration is not a fast path. | |
2489 | */ | |
2490 | if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) | |
28b835d6 FW |
2491 | return; |
2492 | ||
31afb2ea PB |
2493 | /* |
2494 | * First handle the simple case where no cmpxchg is necessary; just | |
2495 | * allow posting non-urgent interrupts. | |
2496 | * | |
2497 | * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change | |
2498 | * PI.NDST: pi_post_block will do it for us and the wakeup_handler | |
2499 | * expects the VCPU to be on the blocked_vcpu_list that matches | |
2500 | * PI.NDST. | |
2501 | */ | |
2502 | if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || | |
2503 | vcpu->cpu == cpu) { | |
2504 | pi_clear_sn(pi_desc); | |
28b835d6 | 2505 | return; |
31afb2ea | 2506 | } |
28b835d6 | 2507 | |
31afb2ea | 2508 | /* The full case. */ |
28b835d6 FW |
2509 | do { |
2510 | old.control = new.control = pi_desc->control; | |
2511 | ||
31afb2ea | 2512 | dest = cpu_physical_id(cpu); |
28b835d6 | 2513 | |
31afb2ea PB |
2514 | if (x2apic_enabled()) |
2515 | new.ndst = dest; | |
2516 | else | |
2517 | new.ndst = (dest << 8) & 0xFF00; | |
28b835d6 | 2518 | |
28b835d6 | 2519 | new.sn = 0; |
c0a1666b PB |
2520 | } while (cmpxchg64(&pi_desc->control, old.control, |
2521 | new.control) != old.control); | |
28b835d6 | 2522 | } |
1be0e61c | 2523 | |
c95ba92a PF |
2524 | static void decache_tsc_multiplier(struct vcpu_vmx *vmx) |
2525 | { | |
2526 | vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio; | |
2527 | vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); | |
2528 | } | |
2529 | ||
6aa8b732 AK |
2530 | /* |
2531 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
2532 | * vcpu mutex is already taken. | |
2533 | */ | |
15ad7146 | 2534 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 2535 | { |
a2fa3e9f | 2536 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b80c76ec | 2537 | bool already_loaded = vmx->loaded_vmcs->cpu == cpu; |
6aa8b732 | 2538 | |
b80c76ec | 2539 | if (!already_loaded) { |
fe0e80be | 2540 | loaded_vmcs_clear(vmx->loaded_vmcs); |
92fe13be | 2541 | local_irq_disable(); |
8f536b76 | 2542 | crash_disable_local_vmclear(cpu); |
5a560f8b XG |
2543 | |
2544 | /* | |
2545 | * Read loaded_vmcs->cpu should be before fetching | |
2546 | * loaded_vmcs->loaded_vmcss_on_cpu_link. | |
2547 | * See the comments in __loaded_vmcs_clear(). | |
2548 | */ | |
2549 | smp_rmb(); | |
2550 | ||
d462b819 NHE |
2551 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
2552 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
8f536b76 | 2553 | crash_enable_local_vmclear(cpu); |
92fe13be | 2554 | local_irq_enable(); |
b80c76ec JM |
2555 | } |
2556 | ||
2557 | if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { | |
2558 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; | |
2559 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
15d45071 | 2560 | indirect_branch_prediction_barrier(); |
b80c76ec JM |
2561 | } |
2562 | ||
2563 | if (!already_loaded) { | |
59c58ceb | 2564 | void *gdt = get_current_gdt_ro(); |
b80c76ec JM |
2565 | unsigned long sysenter_esp; |
2566 | ||
2567 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
92fe13be | 2568 | |
6aa8b732 AK |
2569 | /* |
2570 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
e0c23063 | 2571 | * processors. See 22.2.4. |
6aa8b732 | 2572 | */ |
e0c23063 | 2573 | vmcs_writel(HOST_TR_BASE, |
72f5e08d | 2574 | (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); |
59c58ceb | 2575 | vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ |
6aa8b732 | 2576 | |
b7ffc44d AL |
2577 | /* |
2578 | * VM exits change the host TR limit to 0x67 after a VM | |
2579 | * exit. This is okay, since 0x67 covers everything except | |
2580 | * the IO bitmap and have have code to handle the IO bitmap | |
2581 | * being lost after a VM exit. | |
2582 | */ | |
2583 | BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67); | |
2584 | ||
6aa8b732 AK |
2585 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); |
2586 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
ff2c3a18 | 2587 | |
d462b819 | 2588 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 2589 | } |
28b835d6 | 2590 | |
2680d6da OH |
2591 | /* Setup TSC multiplier */ |
2592 | if (kvm_has_tsc_control && | |
c95ba92a PF |
2593 | vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) |
2594 | decache_tsc_multiplier(vmx); | |
2680d6da | 2595 | |
28b835d6 | 2596 | vmx_vcpu_pi_load(vcpu, cpu); |
1be0e61c | 2597 | vmx->host_pkru = read_pkru(); |
74c55931 | 2598 | vmx->host_debugctlmsr = get_debugctlmsr(); |
28b835d6 FW |
2599 | } |
2600 | ||
2601 | static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) | |
2602 | { | |
2603 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2604 | ||
2605 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
2606 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
2607 | !kvm_vcpu_apicv_active(vcpu)) | |
28b835d6 FW |
2608 | return; |
2609 | ||
2610 | /* Set SN when the vCPU is preempted */ | |
2611 | if (vcpu->preempted) | |
2612 | pi_set_sn(pi_desc); | |
6aa8b732 AK |
2613 | } |
2614 | ||
2615 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
2616 | { | |
28b835d6 FW |
2617 | vmx_vcpu_pi_put(vcpu); |
2618 | ||
a9b21b62 | 2619 | __vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
2620 | } |
2621 | ||
f244deed WL |
2622 | static bool emulation_required(struct kvm_vcpu *vcpu) |
2623 | { | |
2624 | return emulate_invalid_guest_state && !guest_state_valid(vcpu); | |
2625 | } | |
2626 | ||
edcafe3c AK |
2627 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
2628 | ||
fe3ef05c NHE |
2629 | /* |
2630 | * Return the cr0 value that a nested guest would read. This is a combination | |
2631 | * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by | |
2632 | * its hypervisor (cr0_read_shadow). | |
2633 | */ | |
2634 | static inline unsigned long nested_read_cr0(struct vmcs12 *fields) | |
2635 | { | |
2636 | return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | | |
2637 | (fields->cr0_read_shadow & fields->cr0_guest_host_mask); | |
2638 | } | |
2639 | static inline unsigned long nested_read_cr4(struct vmcs12 *fields) | |
2640 | { | |
2641 | return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | | |
2642 | (fields->cr4_read_shadow & fields->cr4_guest_host_mask); | |
2643 | } | |
2644 | ||
6aa8b732 AK |
2645 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
2646 | { | |
78ac8b47 | 2647 | unsigned long rflags, save_rflags; |
345dcaa8 | 2648 | |
6de12732 AK |
2649 | if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
2650 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); | |
2651 | rflags = vmcs_readl(GUEST_RFLAGS); | |
2652 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
2653 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2654 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
2655 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2656 | } | |
2657 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 | 2658 | } |
6de12732 | 2659 | return to_vmx(vcpu)->rflags; |
6aa8b732 AK |
2660 | } |
2661 | ||
2662 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
2663 | { | |
f244deed WL |
2664 | unsigned long old_rflags = vmx_get_rflags(vcpu); |
2665 | ||
6de12732 AK |
2666 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
2667 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 AK |
2668 | if (to_vmx(vcpu)->rmode.vm86_active) { |
2669 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 2670 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 2671 | } |
6aa8b732 | 2672 | vmcs_writel(GUEST_RFLAGS, rflags); |
f244deed WL |
2673 | |
2674 | if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM) | |
2675 | to_vmx(vcpu)->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
2676 | } |
2677 | ||
37ccdcbe | 2678 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
2679 | { |
2680 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2681 | int ret = 0; | |
2682 | ||
2683 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 2684 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 2685 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 2686 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 | 2687 | |
37ccdcbe | 2688 | return ret; |
2809f5d2 GC |
2689 | } |
2690 | ||
2691 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
2692 | { | |
2693 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2694 | u32 interruptibility = interruptibility_old; | |
2695 | ||
2696 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
2697 | ||
48005f64 | 2698 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 2699 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 2700 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
2701 | interruptibility |= GUEST_INTR_STATE_STI; |
2702 | ||
2703 | if ((interruptibility != interruptibility_old)) | |
2704 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
2705 | } | |
2706 | ||
6aa8b732 AK |
2707 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
2708 | { | |
2709 | unsigned long rip; | |
6aa8b732 | 2710 | |
5fdbf976 | 2711 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 2712 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 2713 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 2714 | |
2809f5d2 GC |
2715 | /* skipping an emulated instruction also counts */ |
2716 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
2717 | } |
2718 | ||
b96fb439 PB |
2719 | static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu, |
2720 | unsigned long exit_qual) | |
2721 | { | |
2722 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2723 | unsigned int nr = vcpu->arch.exception.nr; | |
2724 | u32 intr_info = nr | INTR_INFO_VALID_MASK; | |
2725 | ||
2726 | if (vcpu->arch.exception.has_error_code) { | |
2727 | vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code; | |
2728 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; | |
2729 | } | |
2730 | ||
2731 | if (kvm_exception_is_soft(nr)) | |
2732 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; | |
2733 | else | |
2734 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2735 | ||
2736 | if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) && | |
2737 | vmx_get_nmi_mask(vcpu)) | |
2738 | intr_info |= INTR_INFO_UNBLOCK_NMI; | |
2739 | ||
2740 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual); | |
2741 | } | |
2742 | ||
0b6ac343 NHE |
2743 | /* |
2744 | * KVM wants to inject page-faults which it got to the guest. This function | |
2745 | * checks whether in a nested guest, we need to inject them to L1 or L2. | |
0b6ac343 | 2746 | */ |
bfcf83b1 | 2747 | static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual) |
0b6ac343 NHE |
2748 | { |
2749 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
adfe20fb | 2750 | unsigned int nr = vcpu->arch.exception.nr; |
0b6ac343 | 2751 | |
b96fb439 PB |
2752 | if (nr == PF_VECTOR) { |
2753 | if (vcpu->arch.exception.nested_apf) { | |
bfcf83b1 | 2754 | *exit_qual = vcpu->arch.apf.nested_apf_token; |
b96fb439 PB |
2755 | return 1; |
2756 | } | |
2757 | /* | |
2758 | * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception. | |
2759 | * The fix is to add the ancillary datum (CR2 or DR6) to structs | |
2760 | * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 | |
2761 | * can be written only when inject_pending_event runs. This should be | |
2762 | * conditional on a new capability---if the capability is disabled, | |
2763 | * kvm_multiple_exception would write the ancillary information to | |
2764 | * CR2 or DR6, for backwards ABI-compatibility. | |
2765 | */ | |
2766 | if (nested_vmx_is_page_fault_vmexit(vmcs12, | |
2767 | vcpu->arch.exception.error_code)) { | |
bfcf83b1 | 2768 | *exit_qual = vcpu->arch.cr2; |
b96fb439 PB |
2769 | return 1; |
2770 | } | |
2771 | } else { | |
b96fb439 | 2772 | if (vmcs12->exception_bitmap & (1u << nr)) { |
bfcf83b1 WL |
2773 | if (nr == DB_VECTOR) |
2774 | *exit_qual = vcpu->arch.dr6; | |
2775 | else | |
2776 | *exit_qual = 0; | |
b96fb439 PB |
2777 | return 1; |
2778 | } | |
adfe20fb WL |
2779 | } |
2780 | ||
b96fb439 | 2781 | return 0; |
0b6ac343 NHE |
2782 | } |
2783 | ||
caa057a2 WL |
2784 | static void vmx_clear_hlt(struct kvm_vcpu *vcpu) |
2785 | { | |
2786 | /* | |
2787 | * Ensure that we clear the HLT state in the VMCS. We don't need to | |
2788 | * explicitly skip the instruction because if the HLT state is set, | |
2789 | * then the instruction is already executing and RIP has already been | |
2790 | * advanced. | |
2791 | */ | |
2792 | if (kvm_hlt_in_guest(vcpu->kvm) && | |
2793 | vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) | |
2794 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); | |
2795 | } | |
2796 | ||
cfcd20e5 | 2797 | static void vmx_queue_exception(struct kvm_vcpu *vcpu) |
298101da | 2798 | { |
77ab6db0 | 2799 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
cfcd20e5 WL |
2800 | unsigned nr = vcpu->arch.exception.nr; |
2801 | bool has_error_code = vcpu->arch.exception.has_error_code; | |
cfcd20e5 | 2802 | u32 error_code = vcpu->arch.exception.error_code; |
8ab2d2e2 | 2803 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 2804 | |
8ab2d2e2 | 2805 | if (has_error_code) { |
77ab6db0 | 2806 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
2807 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
2808 | } | |
77ab6db0 | 2809 | |
7ffd92c5 | 2810 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
2811 | int inc_eip = 0; |
2812 | if (kvm_exception_is_soft(nr)) | |
2813 | inc_eip = vcpu->arch.event_exit_inst_len; | |
2814 | if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) | |
a92601bb | 2815 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
77ab6db0 JK |
2816 | return; |
2817 | } | |
2818 | ||
add5ff7a SC |
2819 | WARN_ON_ONCE(vmx->emulation_required); |
2820 | ||
66fd3f7f GN |
2821 | if (kvm_exception_is_soft(nr)) { |
2822 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2823 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
2824 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
2825 | } else | |
2826 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2827 | ||
2828 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
caa057a2 WL |
2829 | |
2830 | vmx_clear_hlt(vcpu); | |
298101da AK |
2831 | } |
2832 | ||
4e47c7a6 SY |
2833 | static bool vmx_rdtscp_supported(void) |
2834 | { | |
2835 | return cpu_has_vmx_rdtscp(); | |
2836 | } | |
2837 | ||
ad756a16 MJ |
2838 | static bool vmx_invpcid_supported(void) |
2839 | { | |
2840 | return cpu_has_vmx_invpcid() && enable_ept; | |
2841 | } | |
2842 | ||
a75beee6 ED |
2843 | /* |
2844 | * Swap MSR entry in host/guest MSR entry array. | |
2845 | */ | |
8b9cf98c | 2846 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 2847 | { |
26bb0981 | 2848 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
2849 | |
2850 | tmp = vmx->guest_msrs[to]; | |
2851 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
2852 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
2853 | } |
2854 | ||
e38aea3e AK |
2855 | /* |
2856 | * Set up the vmcs to automatically save and restore system | |
2857 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
2858 | * mode, as fiddling with msrs is very expensive. | |
2859 | */ | |
8b9cf98c | 2860 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 2861 | { |
26bb0981 | 2862 | int save_nmsrs, index; |
e38aea3e | 2863 | |
a75beee6 ED |
2864 | save_nmsrs = 0; |
2865 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 2866 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 2867 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 2868 | if (index >= 0) |
8b9cf98c RR |
2869 | move_msr_up(vmx, index, save_nmsrs++); |
2870 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 2871 | if (index >= 0) |
8b9cf98c RR |
2872 | move_msr_up(vmx, index, save_nmsrs++); |
2873 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 2874 | if (index >= 0) |
8b9cf98c | 2875 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 | 2876 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
d6321d49 | 2877 | if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) |
4e47c7a6 | 2878 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 | 2879 | /* |
8c06585d | 2880 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
2881 | * if efer.sce is enabled. |
2882 | */ | |
8c06585d | 2883 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 2884 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 2885 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
2886 | } |
2887 | #endif | |
92c0d900 AK |
2888 | index = __find_msr_index(vmx, MSR_EFER); |
2889 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 2890 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 2891 | |
26bb0981 | 2892 | vmx->save_nmsrs = save_nmsrs; |
5897297b | 2893 | |
8d14695f | 2894 | if (cpu_has_vmx_msr_bitmap()) |
904e14fb | 2895 | vmx_update_msr_bitmap(&vmx->vcpu); |
e38aea3e AK |
2896 | } |
2897 | ||
e79f245d | 2898 | static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) |
6aa8b732 | 2899 | { |
e79f245d | 2900 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
6aa8b732 | 2901 | |
e79f245d KA |
2902 | if (is_guest_mode(vcpu) && |
2903 | (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)) | |
2904 | return vcpu->arch.tsc_offset - vmcs12->tsc_offset; | |
2905 | ||
2906 | return vcpu->arch.tsc_offset; | |
6aa8b732 AK |
2907 | } |
2908 | ||
2909 | /* | |
99e3e30a | 2910 | * writes 'offset' into guest's timestamp counter offset register |
6aa8b732 | 2911 | */ |
99e3e30a | 2912 | static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 2913 | { |
27fc51b2 | 2914 | if (is_guest_mode(vcpu)) { |
7991825b | 2915 | /* |
27fc51b2 NHE |
2916 | * We're here if L1 chose not to trap WRMSR to TSC. According |
2917 | * to the spec, this should set L1's TSC; The offset that L1 | |
2918 | * set for L2 remains unchanged, and still needs to be added | |
2919 | * to the newly set TSC to get L2's TSC. | |
7991825b | 2920 | */ |
27fc51b2 | 2921 | struct vmcs12 *vmcs12; |
27fc51b2 NHE |
2922 | /* recalculate vmcs02.TSC_OFFSET: */ |
2923 | vmcs12 = get_vmcs12(vcpu); | |
2924 | vmcs_write64(TSC_OFFSET, offset + | |
2925 | (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ? | |
2926 | vmcs12->tsc_offset : 0)); | |
2927 | } else { | |
489223ed YY |
2928 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2929 | vmcs_read64(TSC_OFFSET), offset); | |
27fc51b2 NHE |
2930 | vmcs_write64(TSC_OFFSET, offset); |
2931 | } | |
6aa8b732 AK |
2932 | } |
2933 | ||
801d3424 NHE |
2934 | /* |
2935 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
2936 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
2937 | * all guests if the "nested" module option is off, and can also be disabled | |
2938 | * for a single guest by disabling its VMX cpuid bit. | |
2939 | */ | |
2940 | static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) | |
2941 | { | |
d6321d49 | 2942 | return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); |
801d3424 NHE |
2943 | } |
2944 | ||
b87a51ae NHE |
2945 | /* |
2946 | * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be | |
2947 | * returned for the various VMX controls MSRs when nested VMX is enabled. | |
2948 | * The same values should also be used to verify that vmcs12 control fields are | |
2949 | * valid during nested entry from L1 to L2. | |
2950 | * Each of these control msrs has a low and high 32-bit half: A low bit is on | |
2951 | * if the corresponding bit in the (32-bit) control field *must* be on, and a | |
2952 | * bit in the high half is on if the corresponding bit in the control field | |
2953 | * may be on. See also vmx_control_verify(). | |
b87a51ae | 2954 | */ |
6677f3da | 2955 | static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv) |
b87a51ae | 2956 | { |
1389309c PB |
2957 | if (!nested) { |
2958 | memset(msrs, 0, sizeof(*msrs)); | |
2959 | return; | |
2960 | } | |
2961 | ||
b87a51ae NHE |
2962 | /* |
2963 | * Note that as a general rule, the high half of the MSRs (bits in | |
2964 | * the control fields which may be 1) should be initialized by the | |
2965 | * intersection of the underlying hardware's MSR (i.e., features which | |
2966 | * can be supported) and the list of features we want to expose - | |
2967 | * because they are known to be properly supported in our code. | |
2968 | * Also, usually, the low half of the MSRs (bits which must be 1) can | |
2969 | * be set to 0, meaning that L1 may turn off any of these bits. The | |
2970 | * reason is that if one of these bits is necessary, it will appear | |
2971 | * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control | |
2972 | * fields of vmcs01 and vmcs02, will turn these bits off - and | |
7313c698 | 2973 | * nested_vmx_exit_reflected() will not pass related exits to L1. |
b87a51ae NHE |
2974 | * These rules have exceptions below. |
2975 | */ | |
2976 | ||
2977 | /* pin-based controls */ | |
eabeaacc | 2978 | rdmsr(MSR_IA32_VMX_PINBASED_CTLS, |
6677f3da PB |
2979 | msrs->pinbased_ctls_low, |
2980 | msrs->pinbased_ctls_high); | |
2981 | msrs->pinbased_ctls_low |= | |
b9c237bb | 2982 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; |
6677f3da | 2983 | msrs->pinbased_ctls_high &= |
b9c237bb WV |
2984 | PIN_BASED_EXT_INTR_MASK | |
2985 | PIN_BASED_NMI_EXITING | | |
1389309c PB |
2986 | PIN_BASED_VIRTUAL_NMIS | |
2987 | (apicv ? PIN_BASED_POSTED_INTR : 0); | |
6677f3da | 2988 | msrs->pinbased_ctls_high |= |
b9c237bb | 2989 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | |
0238ea91 | 2990 | PIN_BASED_VMX_PREEMPTION_TIMER; |
b87a51ae | 2991 | |
3dbcd8da | 2992 | /* exit controls */ |
c0dfee58 | 2993 | rdmsr(MSR_IA32_VMX_EXIT_CTLS, |
6677f3da PB |
2994 | msrs->exit_ctls_low, |
2995 | msrs->exit_ctls_high); | |
2996 | msrs->exit_ctls_low = | |
b9c237bb | 2997 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; |
e0ba1a6f | 2998 | |
6677f3da | 2999 | msrs->exit_ctls_high &= |
b87a51ae | 3000 | #ifdef CONFIG_X86_64 |
c0dfee58 | 3001 | VM_EXIT_HOST_ADDR_SPACE_SIZE | |
b87a51ae | 3002 | #endif |
f4124500 | 3003 | VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT; |
6677f3da | 3004 | msrs->exit_ctls_high |= |
b9c237bb | 3005 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | |
f4124500 | 3006 | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | |
e0ba1a6f BD |
3007 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; |
3008 | ||
a87036ad | 3009 | if (kvm_mpx_supported()) |
6677f3da | 3010 | msrs->exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; |
b87a51ae | 3011 | |
2996fca0 | 3012 | /* We support free control of debug control saving. */ |
6677f3da | 3013 | msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS; |
2996fca0 | 3014 | |
b87a51ae NHE |
3015 | /* entry controls */ |
3016 | rdmsr(MSR_IA32_VMX_ENTRY_CTLS, | |
6677f3da PB |
3017 | msrs->entry_ctls_low, |
3018 | msrs->entry_ctls_high); | |
3019 | msrs->entry_ctls_low = | |
b9c237bb | 3020 | VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; |
6677f3da | 3021 | msrs->entry_ctls_high &= |
57435349 JK |
3022 | #ifdef CONFIG_X86_64 |
3023 | VM_ENTRY_IA32E_MODE | | |
3024 | #endif | |
3025 | VM_ENTRY_LOAD_IA32_PAT; | |
6677f3da | 3026 | msrs->entry_ctls_high |= |
b9c237bb | 3027 | (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER); |
a87036ad | 3028 | if (kvm_mpx_supported()) |
6677f3da | 3029 | msrs->entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; |
57435349 | 3030 | |
2996fca0 | 3031 | /* We support free control of debug control loading. */ |
6677f3da | 3032 | msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS; |
2996fca0 | 3033 | |
b87a51ae NHE |
3034 | /* cpu-based controls */ |
3035 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, | |
6677f3da PB |
3036 | msrs->procbased_ctls_low, |
3037 | msrs->procbased_ctls_high); | |
3038 | msrs->procbased_ctls_low = | |
b9c237bb | 3039 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; |
6677f3da | 3040 | msrs->procbased_ctls_high &= |
a294c9bb JK |
3041 | CPU_BASED_VIRTUAL_INTR_PENDING | |
3042 | CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING | | |
b87a51ae NHE |
3043 | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | |
3044 | CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | | |
3045 | CPU_BASED_CR3_STORE_EXITING | | |
3046 | #ifdef CONFIG_X86_64 | |
3047 | CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | | |
3048 | #endif | |
3049 | CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | | |
5f3d45e7 MD |
3050 | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG | |
3051 | CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING | | |
3052 | CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING | | |
3053 | CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
b87a51ae NHE |
3054 | /* |
3055 | * We can allow some features even when not supported by the | |
3056 | * hardware. For example, L1 can specify an MSR bitmap - and we | |
3057 | * can use it to avoid exits to L1 - even when L0 runs L2 | |
3058 | * without MSR bitmaps. | |
3059 | */ | |
6677f3da | 3060 | msrs->procbased_ctls_high |= |
b9c237bb | 3061 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | |
560b7ee1 | 3062 | CPU_BASED_USE_MSR_BITMAPS; |
b87a51ae | 3063 | |
3dcdf3ec | 3064 | /* We support free control of CR3 access interception. */ |
6677f3da | 3065 | msrs->procbased_ctls_low &= |
3dcdf3ec JK |
3066 | ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); |
3067 | ||
80154d77 PB |
3068 | /* |
3069 | * secondary cpu-based controls. Do not include those that | |
3070 | * depend on CPUID bits, they are added later by vmx_cpuid_update. | |
3071 | */ | |
b87a51ae | 3072 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, |
6677f3da PB |
3073 | msrs->secondary_ctls_low, |
3074 | msrs->secondary_ctls_high); | |
3075 | msrs->secondary_ctls_low = 0; | |
3076 | msrs->secondary_ctls_high &= | |
d6851fbe | 3077 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
1b07304c | 3078 | SECONDARY_EXEC_DESC | |
f2b93280 | 3079 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
82f0dd4b | 3080 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
608406e2 | 3081 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
3db13480 | 3082 | SECONDARY_EXEC_WBINVD_EXITING; |
c18911a2 | 3083 | |
afa61f75 NHE |
3084 | if (enable_ept) { |
3085 | /* nested EPT: emulate EPT also to L1 */ | |
6677f3da | 3086 | msrs->secondary_ctls_high |= |
0790ec17 | 3087 | SECONDARY_EXEC_ENABLE_EPT; |
6677f3da | 3088 | msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT | |
7db74265 | 3089 | VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT; |
02120c45 | 3090 | if (cpu_has_vmx_ept_execute_only()) |
6677f3da | 3091 | msrs->ept_caps |= |
02120c45 | 3092 | VMX_EPT_EXECUTE_ONLY_BIT; |
6677f3da PB |
3093 | msrs->ept_caps &= vmx_capability.ept; |
3094 | msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT | | |
7db74265 PB |
3095 | VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT | |
3096 | VMX_EPT_1GB_PAGE_BIT; | |
03efce6f | 3097 | if (enable_ept_ad_bits) { |
6677f3da | 3098 | msrs->secondary_ctls_high |= |
03efce6f | 3099 | SECONDARY_EXEC_ENABLE_PML; |
6677f3da | 3100 | msrs->ept_caps |= VMX_EPT_AD_BIT; |
03efce6f | 3101 | } |
1c13bffd | 3102 | } |
afa61f75 | 3103 | |
27c42a1b | 3104 | if (cpu_has_vmx_vmfunc()) { |
6677f3da | 3105 | msrs->secondary_ctls_high |= |
27c42a1b | 3106 | SECONDARY_EXEC_ENABLE_VMFUNC; |
41ab9372 BD |
3107 | /* |
3108 | * Advertise EPTP switching unconditionally | |
3109 | * since we emulate it | |
3110 | */ | |
575b3a2c | 3111 | if (enable_ept) |
6677f3da | 3112 | msrs->vmfunc_controls = |
575b3a2c | 3113 | VMX_VMFUNC_EPTP_SWITCHING; |
27c42a1b BD |
3114 | } |
3115 | ||
ef697a71 PB |
3116 | /* |
3117 | * Old versions of KVM use the single-context version without | |
3118 | * checking for support, so declare that it is supported even | |
3119 | * though it is treated as global context. The alternative is | |
3120 | * not failing the single-context invvpid, and it is worse. | |
3121 | */ | |
63cb6d5f | 3122 | if (enable_vpid) { |
6677f3da | 3123 | msrs->secondary_ctls_high |= |
63cb6d5f | 3124 | SECONDARY_EXEC_ENABLE_VPID; |
6677f3da | 3125 | msrs->vpid_caps = VMX_VPID_INVVPID_BIT | |
bcdde302 | 3126 | VMX_VPID_EXTENT_SUPPORTED_MASK; |
1c13bffd | 3127 | } |
99b83ac8 | 3128 | |
0790ec17 | 3129 | if (enable_unrestricted_guest) |
6677f3da | 3130 | msrs->secondary_ctls_high |= |
0790ec17 RK |
3131 | SECONDARY_EXEC_UNRESTRICTED_GUEST; |
3132 | ||
c18911a2 | 3133 | /* miscellaneous data */ |
b9c237bb | 3134 | rdmsr(MSR_IA32_VMX_MISC, |
6677f3da PB |
3135 | msrs->misc_low, |
3136 | msrs->misc_high); | |
3137 | msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA; | |
3138 | msrs->misc_low |= | |
b9c237bb | 3139 | VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | |
f4124500 | 3140 | VMX_MISC_ACTIVITY_HLT; |
6677f3da | 3141 | msrs->misc_high = 0; |
62cc6b9d DM |
3142 | |
3143 | /* | |
3144 | * This MSR reports some information about VMX support. We | |
3145 | * should return information about the VMX we emulate for the | |
3146 | * guest, and the VMCS structure we give it - not about the | |
3147 | * VMX support of the underlying hardware. | |
3148 | */ | |
6677f3da | 3149 | msrs->basic = |
62cc6b9d DM |
3150 | VMCS12_REVISION | |
3151 | VMX_BASIC_TRUE_CTLS | | |
3152 | ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | | |
3153 | (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); | |
3154 | ||
3155 | if (cpu_has_vmx_basic_inout()) | |
6677f3da | 3156 | msrs->basic |= VMX_BASIC_INOUT; |
62cc6b9d DM |
3157 | |
3158 | /* | |
8322ebbb | 3159 | * These MSRs specify bits which the guest must keep fixed on |
62cc6b9d DM |
3160 | * while L1 is in VMXON mode (in L1's root mode, or running an L2). |
3161 | * We picked the standard core2 setting. | |
3162 | */ | |
3163 | #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) | |
3164 | #define VMXON_CR4_ALWAYSON X86_CR4_VMXE | |
6677f3da PB |
3165 | msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON; |
3166 | msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON; | |
8322ebbb DM |
3167 | |
3168 | /* These MSRs specify bits which the guest must keep fixed off. */ | |
6677f3da PB |
3169 | rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1); |
3170 | rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1); | |
62cc6b9d DM |
3171 | |
3172 | /* highest index: VMX_PREEMPTION_TIMER_VALUE */ | |
6677f3da | 3173 | msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1; |
b87a51ae NHE |
3174 | } |
3175 | ||
3899152c DM |
3176 | /* |
3177 | * if fixed0[i] == 1: val[i] must be 1 | |
3178 | * if fixed1[i] == 0: val[i] must be 0 | |
3179 | */ | |
3180 | static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1) | |
3181 | { | |
3182 | return ((val & fixed1) | fixed0) == val; | |
b87a51ae NHE |
3183 | } |
3184 | ||
3185 | static inline bool vmx_control_verify(u32 control, u32 low, u32 high) | |
3186 | { | |
3899152c | 3187 | return fixed_bits_valid(control, low, high); |
b87a51ae NHE |
3188 | } |
3189 | ||
3190 | static inline u64 vmx_control_msr(u32 low, u32 high) | |
3191 | { | |
3192 | return low | ((u64)high << 32); | |
3193 | } | |
3194 | ||
62cc6b9d DM |
3195 | static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask) |
3196 | { | |
3197 | superset &= mask; | |
3198 | subset &= mask; | |
3199 | ||
3200 | return (superset | subset) == superset; | |
3201 | } | |
3202 | ||
3203 | static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data) | |
3204 | { | |
3205 | const u64 feature_and_reserved = | |
3206 | /* feature (except bit 48; see below) */ | |
3207 | BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) | | |
3208 | /* reserved */ | |
3209 | BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56); | |
6677f3da | 3210 | u64 vmx_basic = vmx->nested.msrs.basic; |
62cc6b9d DM |
3211 | |
3212 | if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved)) | |
3213 | return -EINVAL; | |
3214 | ||
3215 | /* | |
3216 | * KVM does not emulate a version of VMX that constrains physical | |
3217 | * addresses of VMX structures (e.g. VMCS) to 32-bits. | |
3218 | */ | |
3219 | if (data & BIT_ULL(48)) | |
3220 | return -EINVAL; | |
3221 | ||
3222 | if (vmx_basic_vmcs_revision_id(vmx_basic) != | |
3223 | vmx_basic_vmcs_revision_id(data)) | |
3224 | return -EINVAL; | |
3225 | ||
3226 | if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data)) | |
3227 | return -EINVAL; | |
3228 | ||
6677f3da | 3229 | vmx->nested.msrs.basic = data; |
62cc6b9d DM |
3230 | return 0; |
3231 | } | |
3232 | ||
3233 | static int | |
3234 | vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
3235 | { | |
3236 | u64 supported; | |
3237 | u32 *lowp, *highp; | |
3238 | ||
3239 | switch (msr_index) { | |
3240 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
6677f3da PB |
3241 | lowp = &vmx->nested.msrs.pinbased_ctls_low; |
3242 | highp = &vmx->nested.msrs.pinbased_ctls_high; | |
62cc6b9d DM |
3243 | break; |
3244 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
6677f3da PB |
3245 | lowp = &vmx->nested.msrs.procbased_ctls_low; |
3246 | highp = &vmx->nested.msrs.procbased_ctls_high; | |
62cc6b9d DM |
3247 | break; |
3248 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
6677f3da PB |
3249 | lowp = &vmx->nested.msrs.exit_ctls_low; |
3250 | highp = &vmx->nested.msrs.exit_ctls_high; | |
62cc6b9d DM |
3251 | break; |
3252 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
6677f3da PB |
3253 | lowp = &vmx->nested.msrs.entry_ctls_low; |
3254 | highp = &vmx->nested.msrs.entry_ctls_high; | |
62cc6b9d DM |
3255 | break; |
3256 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
6677f3da PB |
3257 | lowp = &vmx->nested.msrs.secondary_ctls_low; |
3258 | highp = &vmx->nested.msrs.secondary_ctls_high; | |
62cc6b9d DM |
3259 | break; |
3260 | default: | |
3261 | BUG(); | |
3262 | } | |
3263 | ||
3264 | supported = vmx_control_msr(*lowp, *highp); | |
3265 | ||
3266 | /* Check must-be-1 bits are still 1. */ | |
3267 | if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0))) | |
3268 | return -EINVAL; | |
3269 | ||
3270 | /* Check must-be-0 bits are still 0. */ | |
3271 | if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32))) | |
3272 | return -EINVAL; | |
3273 | ||
3274 | *lowp = data; | |
3275 | *highp = data >> 32; | |
3276 | return 0; | |
3277 | } | |
3278 | ||
3279 | static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data) | |
3280 | { | |
3281 | const u64 feature_and_reserved_bits = | |
3282 | /* feature */ | |
3283 | BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) | | |
3284 | BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) | | |
3285 | /* reserved */ | |
3286 | GENMASK_ULL(13, 9) | BIT_ULL(31); | |
3287 | u64 vmx_misc; | |
3288 | ||
6677f3da PB |
3289 | vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low, |
3290 | vmx->nested.msrs.misc_high); | |
62cc6b9d DM |
3291 | |
3292 | if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits)) | |
3293 | return -EINVAL; | |
3294 | ||
6677f3da | 3295 | if ((vmx->nested.msrs.pinbased_ctls_high & |
62cc6b9d DM |
3296 | PIN_BASED_VMX_PREEMPTION_TIMER) && |
3297 | vmx_misc_preemption_timer_rate(data) != | |
3298 | vmx_misc_preemption_timer_rate(vmx_misc)) | |
3299 | return -EINVAL; | |
3300 | ||
3301 | if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc)) | |
3302 | return -EINVAL; | |
3303 | ||
3304 | if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc)) | |
3305 | return -EINVAL; | |
3306 | ||
3307 | if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc)) | |
3308 | return -EINVAL; | |
3309 | ||
6677f3da PB |
3310 | vmx->nested.msrs.misc_low = data; |
3311 | vmx->nested.msrs.misc_high = data >> 32; | |
62cc6b9d DM |
3312 | return 0; |
3313 | } | |
3314 | ||
3315 | static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data) | |
3316 | { | |
3317 | u64 vmx_ept_vpid_cap; | |
3318 | ||
6677f3da PB |
3319 | vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps, |
3320 | vmx->nested.msrs.vpid_caps); | |
62cc6b9d DM |
3321 | |
3322 | /* Every bit is either reserved or a feature bit. */ | |
3323 | if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL)) | |
3324 | return -EINVAL; | |
3325 | ||
6677f3da PB |
3326 | vmx->nested.msrs.ept_caps = data; |
3327 | vmx->nested.msrs.vpid_caps = data >> 32; | |
62cc6b9d DM |
3328 | return 0; |
3329 | } | |
3330 | ||
3331 | static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
3332 | { | |
3333 | u64 *msr; | |
3334 | ||
3335 | switch (msr_index) { | |
3336 | case MSR_IA32_VMX_CR0_FIXED0: | |
6677f3da | 3337 | msr = &vmx->nested.msrs.cr0_fixed0; |
62cc6b9d DM |
3338 | break; |
3339 | case MSR_IA32_VMX_CR4_FIXED0: | |
6677f3da | 3340 | msr = &vmx->nested.msrs.cr4_fixed0; |
62cc6b9d DM |
3341 | break; |
3342 | default: | |
3343 | BUG(); | |
3344 | } | |
3345 | ||
3346 | /* | |
3347 | * 1 bits (which indicates bits which "must-be-1" during VMX operation) | |
3348 | * must be 1 in the restored value. | |
3349 | */ | |
3350 | if (!is_bitwise_subset(data, *msr, -1ULL)) | |
3351 | return -EINVAL; | |
3352 | ||
3353 | *msr = data; | |
3354 | return 0; | |
3355 | } | |
3356 | ||
3357 | /* | |
3358 | * Called when userspace is restoring VMX MSRs. | |
3359 | * | |
3360 | * Returns 0 on success, non-0 otherwise. | |
3361 | */ | |
3362 | static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
b87a51ae | 3363 | { |
b9c237bb WV |
3364 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3365 | ||
b87a51ae | 3366 | switch (msr_index) { |
b87a51ae | 3367 | case MSR_IA32_VMX_BASIC: |
62cc6b9d DM |
3368 | return vmx_restore_vmx_basic(vmx, data); |
3369 | case MSR_IA32_VMX_PINBASED_CTLS: | |
3370 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
3371 | case MSR_IA32_VMX_EXIT_CTLS: | |
3372 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b87a51ae | 3373 | /* |
62cc6b9d DM |
3374 | * The "non-true" VMX capability MSRs are generated from the |
3375 | * "true" MSRs, so we do not support restoring them directly. | |
3376 | * | |
3377 | * If userspace wants to emulate VMX_BASIC[55]=0, userspace | |
3378 | * should restore the "true" MSRs with the must-be-1 bits | |
3379 | * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND | |
3380 | * DEFAULT SETTINGS". | |
b87a51ae | 3381 | */ |
62cc6b9d DM |
3382 | return -EINVAL; |
3383 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3384 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3385 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3386 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3387 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
3388 | return vmx_restore_control_msr(vmx, msr_index, data); | |
3389 | case MSR_IA32_VMX_MISC: | |
3390 | return vmx_restore_vmx_misc(vmx, data); | |
3391 | case MSR_IA32_VMX_CR0_FIXED0: | |
3392 | case MSR_IA32_VMX_CR4_FIXED0: | |
3393 | return vmx_restore_fixed0_msr(vmx, msr_index, data); | |
3394 | case MSR_IA32_VMX_CR0_FIXED1: | |
3395 | case MSR_IA32_VMX_CR4_FIXED1: | |
3396 | /* | |
3397 | * These MSRs are generated based on the vCPU's CPUID, so we | |
3398 | * do not support restoring them directly. | |
3399 | */ | |
3400 | return -EINVAL; | |
3401 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
3402 | return vmx_restore_vmx_ept_vpid_cap(vmx, data); | |
3403 | case MSR_IA32_VMX_VMCS_ENUM: | |
6677f3da | 3404 | vmx->nested.msrs.vmcs_enum = data; |
62cc6b9d DM |
3405 | return 0; |
3406 | default: | |
b87a51ae | 3407 | /* |
62cc6b9d | 3408 | * The rest of the VMX capability MSRs do not support restore. |
b87a51ae | 3409 | */ |
62cc6b9d DM |
3410 | return -EINVAL; |
3411 | } | |
3412 | } | |
3413 | ||
3414 | /* Returns 0 on success, non-0 otherwise. */ | |
6677f3da | 3415 | static int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata) |
62cc6b9d | 3416 | { |
62cc6b9d DM |
3417 | switch (msr_index) { |
3418 | case MSR_IA32_VMX_BASIC: | |
6677f3da | 3419 | *pdata = msrs->basic; |
b87a51ae NHE |
3420 | break; |
3421 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3422 | case MSR_IA32_VMX_PINBASED_CTLS: | |
b9c237bb | 3423 | *pdata = vmx_control_msr( |
6677f3da PB |
3424 | msrs->pinbased_ctls_low, |
3425 | msrs->pinbased_ctls_high); | |
0115f9cb DM |
3426 | if (msr_index == MSR_IA32_VMX_PINBASED_CTLS) |
3427 | *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3428 | break; |
3429 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3430 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
b9c237bb | 3431 | *pdata = vmx_control_msr( |
6677f3da PB |
3432 | msrs->procbased_ctls_low, |
3433 | msrs->procbased_ctls_high); | |
0115f9cb DM |
3434 | if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS) |
3435 | *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3436 | break; |
3437 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3438 | case MSR_IA32_VMX_EXIT_CTLS: | |
b9c237bb | 3439 | *pdata = vmx_control_msr( |
6677f3da PB |
3440 | msrs->exit_ctls_low, |
3441 | msrs->exit_ctls_high); | |
0115f9cb DM |
3442 | if (msr_index == MSR_IA32_VMX_EXIT_CTLS) |
3443 | *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3444 | break; |
3445 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3446 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b9c237bb | 3447 | *pdata = vmx_control_msr( |
6677f3da PB |
3448 | msrs->entry_ctls_low, |
3449 | msrs->entry_ctls_high); | |
0115f9cb DM |
3450 | if (msr_index == MSR_IA32_VMX_ENTRY_CTLS) |
3451 | *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3452 | break; |
3453 | case MSR_IA32_VMX_MISC: | |
b9c237bb | 3454 | *pdata = vmx_control_msr( |
6677f3da PB |
3455 | msrs->misc_low, |
3456 | msrs->misc_high); | |
b87a51ae | 3457 | break; |
b87a51ae | 3458 | case MSR_IA32_VMX_CR0_FIXED0: |
6677f3da | 3459 | *pdata = msrs->cr0_fixed0; |
b87a51ae NHE |
3460 | break; |
3461 | case MSR_IA32_VMX_CR0_FIXED1: | |
6677f3da | 3462 | *pdata = msrs->cr0_fixed1; |
b87a51ae NHE |
3463 | break; |
3464 | case MSR_IA32_VMX_CR4_FIXED0: | |
6677f3da | 3465 | *pdata = msrs->cr4_fixed0; |
b87a51ae NHE |
3466 | break; |
3467 | case MSR_IA32_VMX_CR4_FIXED1: | |
6677f3da | 3468 | *pdata = msrs->cr4_fixed1; |
b87a51ae NHE |
3469 | break; |
3470 | case MSR_IA32_VMX_VMCS_ENUM: | |
6677f3da | 3471 | *pdata = msrs->vmcs_enum; |
b87a51ae NHE |
3472 | break; |
3473 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
b9c237bb | 3474 | *pdata = vmx_control_msr( |
6677f3da PB |
3475 | msrs->secondary_ctls_low, |
3476 | msrs->secondary_ctls_high); | |
b87a51ae NHE |
3477 | break; |
3478 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
6677f3da PB |
3479 | *pdata = msrs->ept_caps | |
3480 | ((u64)msrs->vpid_caps << 32); | |
b87a51ae | 3481 | break; |
27c42a1b | 3482 | case MSR_IA32_VMX_VMFUNC: |
6677f3da | 3483 | *pdata = msrs->vmfunc_controls; |
27c42a1b | 3484 | break; |
b87a51ae | 3485 | default: |
b87a51ae | 3486 | return 1; |
b3897a49 NHE |
3487 | } |
3488 | ||
b87a51ae NHE |
3489 | return 0; |
3490 | } | |
3491 | ||
37e4c997 HZ |
3492 | static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, |
3493 | uint64_t val) | |
3494 | { | |
3495 | uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; | |
3496 | ||
3497 | return !(val & ~valid_bits); | |
3498 | } | |
3499 | ||
801e459a TL |
3500 | static int vmx_get_msr_feature(struct kvm_msr_entry *msr) |
3501 | { | |
1389309c PB |
3502 | switch (msr->index) { |
3503 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
3504 | if (!nested) | |
3505 | return 1; | |
3506 | return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); | |
3507 | default: | |
3508 | return 1; | |
3509 | } | |
3510 | ||
3511 | return 0; | |
801e459a TL |
3512 | } |
3513 | ||
6aa8b732 AK |
3514 | /* |
3515 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
3516 | * Returns 0 on success, non-0 otherwise. | |
3517 | * Assumes vcpu_load() was already called. | |
3518 | */ | |
609e36d3 | 3519 | static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3520 | { |
a6cb099a | 3521 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 3522 | struct shared_msr_entry *msr; |
6aa8b732 | 3523 | |
609e36d3 | 3524 | switch (msr_info->index) { |
05b3e0c2 | 3525 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3526 | case MSR_FS_BASE: |
609e36d3 | 3527 | msr_info->data = vmcs_readl(GUEST_FS_BASE); |
6aa8b732 AK |
3528 | break; |
3529 | case MSR_GS_BASE: | |
609e36d3 | 3530 | msr_info->data = vmcs_readl(GUEST_GS_BASE); |
6aa8b732 | 3531 | break; |
44ea2b17 | 3532 | case MSR_KERNEL_GS_BASE: |
a6cb099a BP |
3533 | vmx_load_host_state(vmx); |
3534 | msr_info->data = vmx->msr_guest_kernel_gs_base; | |
44ea2b17 | 3535 | break; |
26bb0981 | 3536 | #endif |
6aa8b732 | 3537 | case MSR_EFER: |
609e36d3 | 3538 | return kvm_get_msr_common(vcpu, msr_info); |
d28b387f KA |
3539 | case MSR_IA32_SPEC_CTRL: |
3540 | if (!msr_info->host_initiated && | |
d28b387f KA |
3541 | !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) |
3542 | return 1; | |
3543 | ||
3544 | msr_info->data = to_vmx(vcpu)->spec_ctrl; | |
3545 | break; | |
28c1c9fa KA |
3546 | case MSR_IA32_ARCH_CAPABILITIES: |
3547 | if (!msr_info->host_initiated && | |
3548 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3549 | return 1; | |
3550 | msr_info->data = to_vmx(vcpu)->arch_capabilities; | |
3551 | break; | |
6aa8b732 | 3552 | case MSR_IA32_SYSENTER_CS: |
609e36d3 | 3553 | msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); |
6aa8b732 AK |
3554 | break; |
3555 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3556 | msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
3557 | break; |
3558 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3559 | msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 3560 | break; |
0dd376e7 | 3561 | case MSR_IA32_BNDCFGS: |
691bd434 | 3562 | if (!kvm_mpx_supported() || |
d6321d49 RK |
3563 | (!msr_info->host_initiated && |
3564 | !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) | |
93c4adc7 | 3565 | return 1; |
609e36d3 | 3566 | msr_info->data = vmcs_read64(GUEST_BNDCFGS); |
0dd376e7 | 3567 | break; |
c45dcc71 AR |
3568 | case MSR_IA32_MCG_EXT_CTL: |
3569 | if (!msr_info->host_initiated && | |
a6cb099a | 3570 | !(vmx->msr_ia32_feature_control & |
c45dcc71 | 3571 | FEATURE_CONTROL_LMCE)) |
cae50139 | 3572 | return 1; |
c45dcc71 AR |
3573 | msr_info->data = vcpu->arch.mcg_ext_ctl; |
3574 | break; | |
cae50139 | 3575 | case MSR_IA32_FEATURE_CONTROL: |
a6cb099a | 3576 | msr_info->data = vmx->msr_ia32_feature_control; |
cae50139 JK |
3577 | break; |
3578 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
3579 | if (!nested_vmx_allowed(vcpu)) | |
3580 | return 1; | |
6677f3da PB |
3581 | return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, |
3582 | &msr_info->data); | |
20300099 WL |
3583 | case MSR_IA32_XSS: |
3584 | if (!vmx_xsaves_supported()) | |
3585 | return 1; | |
609e36d3 | 3586 | msr_info->data = vcpu->arch.ia32_xss; |
20300099 | 3587 | break; |
4e47c7a6 | 3588 | case MSR_TSC_AUX: |
d6321d49 RK |
3589 | if (!msr_info->host_initiated && |
3590 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) | |
4e47c7a6 SY |
3591 | return 1; |
3592 | /* Otherwise falls through */ | |
6aa8b732 | 3593 | default: |
a6cb099a | 3594 | msr = find_msr_entry(vmx, msr_info->index); |
3bab1f5d | 3595 | if (msr) { |
609e36d3 | 3596 | msr_info->data = msr->data; |
3bab1f5d | 3597 | break; |
6aa8b732 | 3598 | } |
609e36d3 | 3599 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3600 | } |
3601 | ||
6aa8b732 AK |
3602 | return 0; |
3603 | } | |
3604 | ||
cae50139 JK |
3605 | static void vmx_leave_nested(struct kvm_vcpu *vcpu); |
3606 | ||
6aa8b732 AK |
3607 | /* |
3608 | * Writes msr value into into the appropriate "register". | |
3609 | * Returns 0 on success, non-0 otherwise. | |
3610 | * Assumes vcpu_load() was already called. | |
3611 | */ | |
8fe8ab46 | 3612 | static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3613 | { |
a2fa3e9f | 3614 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 3615 | struct shared_msr_entry *msr; |
2cc51560 | 3616 | int ret = 0; |
8fe8ab46 WA |
3617 | u32 msr_index = msr_info->index; |
3618 | u64 data = msr_info->data; | |
2cc51560 | 3619 | |
6aa8b732 | 3620 | switch (msr_index) { |
3bab1f5d | 3621 | case MSR_EFER: |
8fe8ab46 | 3622 | ret = kvm_set_msr_common(vcpu, msr_info); |
2cc51560 | 3623 | break; |
16175a79 | 3624 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3625 | case MSR_FS_BASE: |
2fb92db1 | 3626 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3627 | vmcs_writel(GUEST_FS_BASE, data); |
3628 | break; | |
3629 | case MSR_GS_BASE: | |
2fb92db1 | 3630 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3631 | vmcs_writel(GUEST_GS_BASE, data); |
3632 | break; | |
44ea2b17 AK |
3633 | case MSR_KERNEL_GS_BASE: |
3634 | vmx_load_host_state(vmx); | |
3635 | vmx->msr_guest_kernel_gs_base = data; | |
3636 | break; | |
6aa8b732 AK |
3637 | #endif |
3638 | case MSR_IA32_SYSENTER_CS: | |
3639 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
3640 | break; | |
3641 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 3642 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
3643 | break; |
3644 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 3645 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 3646 | break; |
0dd376e7 | 3647 | case MSR_IA32_BNDCFGS: |
691bd434 | 3648 | if (!kvm_mpx_supported() || |
d6321d49 RK |
3649 | (!msr_info->host_initiated && |
3650 | !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) | |
93c4adc7 | 3651 | return 1; |
fd8cb433 | 3652 | if (is_noncanonical_address(data & PAGE_MASK, vcpu) || |
4531662d | 3653 | (data & MSR_IA32_BNDCFGS_RSVD)) |
93c4adc7 | 3654 | return 1; |
0dd376e7 LJ |
3655 | vmcs_write64(GUEST_BNDCFGS, data); |
3656 | break; | |
d28b387f KA |
3657 | case MSR_IA32_SPEC_CTRL: |
3658 | if (!msr_info->host_initiated && | |
d28b387f KA |
3659 | !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) |
3660 | return 1; | |
3661 | ||
3662 | /* The STIBP bit doesn't fault even if it's not advertised */ | |
9f65fb29 | 3663 | if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD)) |
d28b387f KA |
3664 | return 1; |
3665 | ||
3666 | vmx->spec_ctrl = data; | |
3667 | ||
3668 | if (!data) | |
3669 | break; | |
3670 | ||
3671 | /* | |
3672 | * For non-nested: | |
3673 | * When it's written (to non-zero) for the first time, pass | |
3674 | * it through. | |
3675 | * | |
3676 | * For nested: | |
3677 | * The handling of the MSR bitmap for L2 guests is done in | |
3678 | * nested_vmx_merge_msr_bitmap. We should not touch the | |
3679 | * vmcs02.msr_bitmap here since it gets completely overwritten | |
3680 | * in the merging. We update the vmcs01 here for L1 as well | |
3681 | * since it will end up touching the MSR anyway now. | |
3682 | */ | |
3683 | vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, | |
3684 | MSR_IA32_SPEC_CTRL, | |
3685 | MSR_TYPE_RW); | |
3686 | break; | |
15d45071 AR |
3687 | case MSR_IA32_PRED_CMD: |
3688 | if (!msr_info->host_initiated && | |
15d45071 AR |
3689 | !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) |
3690 | return 1; | |
3691 | ||
3692 | if (data & ~PRED_CMD_IBPB) | |
3693 | return 1; | |
3694 | ||
3695 | if (!data) | |
3696 | break; | |
3697 | ||
3698 | wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); | |
3699 | ||
3700 | /* | |
3701 | * For non-nested: | |
3702 | * When it's written (to non-zero) for the first time, pass | |
3703 | * it through. | |
3704 | * | |
3705 | * For nested: | |
3706 | * The handling of the MSR bitmap for L2 guests is done in | |
3707 | * nested_vmx_merge_msr_bitmap. We should not touch the | |
3708 | * vmcs02.msr_bitmap here since it gets completely overwritten | |
3709 | * in the merging. | |
3710 | */ | |
3711 | vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, | |
3712 | MSR_TYPE_W); | |
3713 | break; | |
28c1c9fa KA |
3714 | case MSR_IA32_ARCH_CAPABILITIES: |
3715 | if (!msr_info->host_initiated) | |
3716 | return 1; | |
3717 | vmx->arch_capabilities = data; | |
3718 | break; | |
468d472f SY |
3719 | case MSR_IA32_CR_PAT: |
3720 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
4566654b NA |
3721 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) |
3722 | return 1; | |
468d472f SY |
3723 | vmcs_write64(GUEST_IA32_PAT, data); |
3724 | vcpu->arch.pat = data; | |
3725 | break; | |
3726 | } | |
8fe8ab46 | 3727 | ret = kvm_set_msr_common(vcpu, msr_info); |
4e47c7a6 | 3728 | break; |
ba904635 WA |
3729 | case MSR_IA32_TSC_ADJUST: |
3730 | ret = kvm_set_msr_common(vcpu, msr_info); | |
4e47c7a6 | 3731 | break; |
c45dcc71 AR |
3732 | case MSR_IA32_MCG_EXT_CTL: |
3733 | if ((!msr_info->host_initiated && | |
3734 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3735 | FEATURE_CONTROL_LMCE)) || | |
3736 | (data & ~MCG_EXT_CTL_LMCE_EN)) | |
3737 | return 1; | |
3738 | vcpu->arch.mcg_ext_ctl = data; | |
3739 | break; | |
cae50139 | 3740 | case MSR_IA32_FEATURE_CONTROL: |
37e4c997 | 3741 | if (!vmx_feature_control_msr_valid(vcpu, data) || |
3b84080b | 3742 | (to_vmx(vcpu)->msr_ia32_feature_control & |
cae50139 JK |
3743 | FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) |
3744 | return 1; | |
3b84080b | 3745 | vmx->msr_ia32_feature_control = data; |
cae50139 JK |
3746 | if (msr_info->host_initiated && data == 0) |
3747 | vmx_leave_nested(vcpu); | |
3748 | break; | |
3749 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
62cc6b9d DM |
3750 | if (!msr_info->host_initiated) |
3751 | return 1; /* they are read-only */ | |
3752 | if (!nested_vmx_allowed(vcpu)) | |
3753 | return 1; | |
3754 | return vmx_set_vmx_msr(vcpu, msr_index, data); | |
20300099 WL |
3755 | case MSR_IA32_XSS: |
3756 | if (!vmx_xsaves_supported()) | |
3757 | return 1; | |
3758 | /* | |
3759 | * The only supported bit as of Skylake is bit 8, but | |
3760 | * it is not supported on KVM. | |
3761 | */ | |
3762 | if (data != 0) | |
3763 | return 1; | |
3764 | vcpu->arch.ia32_xss = data; | |
3765 | if (vcpu->arch.ia32_xss != host_xss) | |
3766 | add_atomic_switch_msr(vmx, MSR_IA32_XSS, | |
3767 | vcpu->arch.ia32_xss, host_xss); | |
3768 | else | |
3769 | clear_atomic_switch_msr(vmx, MSR_IA32_XSS); | |
3770 | break; | |
4e47c7a6 | 3771 | case MSR_TSC_AUX: |
d6321d49 RK |
3772 | if (!msr_info->host_initiated && |
3773 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) | |
4e47c7a6 SY |
3774 | return 1; |
3775 | /* Check reserved bit, higher 32 bits should be zero */ | |
3776 | if ((data >> 32) != 0) | |
3777 | return 1; | |
3778 | /* Otherwise falls through */ | |
6aa8b732 | 3779 | default: |
8b9cf98c | 3780 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 3781 | if (msr) { |
8b3c3104 | 3782 | u64 old_msr_data = msr->data; |
3bab1f5d | 3783 | msr->data = data; |
2225fd56 AK |
3784 | if (msr - vmx->guest_msrs < vmx->save_nmsrs) { |
3785 | preempt_disable(); | |
8b3c3104 AH |
3786 | ret = kvm_set_shared_msr(msr->index, msr->data, |
3787 | msr->mask); | |
2225fd56 | 3788 | preempt_enable(); |
8b3c3104 AH |
3789 | if (ret) |
3790 | msr->data = old_msr_data; | |
2225fd56 | 3791 | } |
3bab1f5d | 3792 | break; |
6aa8b732 | 3793 | } |
8fe8ab46 | 3794 | ret = kvm_set_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3795 | } |
3796 | ||
2cc51560 | 3797 | return ret; |
6aa8b732 AK |
3798 | } |
3799 | ||
5fdbf976 | 3800 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 3801 | { |
5fdbf976 MT |
3802 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
3803 | switch (reg) { | |
3804 | case VCPU_REGS_RSP: | |
3805 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
3806 | break; | |
3807 | case VCPU_REGS_RIP: | |
3808 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
3809 | break; | |
6de4f3ad AK |
3810 | case VCPU_EXREG_PDPTR: |
3811 | if (enable_ept) | |
3812 | ept_save_pdptrs(vcpu); | |
3813 | break; | |
5fdbf976 MT |
3814 | default: |
3815 | break; | |
3816 | } | |
6aa8b732 AK |
3817 | } |
3818 | ||
6aa8b732 AK |
3819 | static __init int cpu_has_kvm_support(void) |
3820 | { | |
6210e37b | 3821 | return cpu_has_vmx(); |
6aa8b732 AK |
3822 | } |
3823 | ||
3824 | static __init int vmx_disabled_by_bios(void) | |
3825 | { | |
3826 | u64 msr; | |
3827 | ||
3828 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 3829 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 3830 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
3831 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
3832 | && tboot_enabled()) | |
3833 | return 1; | |
23f3e991 | 3834 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 3835 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 3836 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
3837 | && !tboot_enabled()) { |
3838 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 3839 | "activate TXT before enabling KVM\n"); |
cafd6659 | 3840 | return 1; |
f9335afe | 3841 | } |
23f3e991 JC |
3842 | /* launched w/o TXT and VMX disabled */ |
3843 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
3844 | && !tboot_enabled()) | |
3845 | return 1; | |
cafd6659 SW |
3846 | } |
3847 | ||
3848 | return 0; | |
6aa8b732 AK |
3849 | } |
3850 | ||
7725b894 DX |
3851 | static void kvm_cpu_vmxon(u64 addr) |
3852 | { | |
fe0e80be | 3853 | cr4_set_bits(X86_CR4_VMXE); |
1c5ac21a AS |
3854 | intel_pt_handle_vmx(1); |
3855 | ||
7725b894 DX |
3856 | asm volatile (ASM_VMX_VMXON_RAX |
3857 | : : "a"(&addr), "m"(addr) | |
3858 | : "memory", "cc"); | |
3859 | } | |
3860 | ||
13a34e06 | 3861 | static int hardware_enable(void) |
6aa8b732 AK |
3862 | { |
3863 | int cpu = raw_smp_processor_id(); | |
3864 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 3865 | u64 old, test_bits; |
6aa8b732 | 3866 | |
1e02ce4c | 3867 | if (cr4_read_shadow() & X86_CR4_VMXE) |
10474ae8 AG |
3868 | return -EBUSY; |
3869 | ||
773e8a04 VK |
3870 | /* |
3871 | * This can happen if we hot-added a CPU but failed to allocate | |
3872 | * VP assist page for it. | |
3873 | */ | |
3874 | if (static_branch_unlikely(&enable_evmcs) && | |
3875 | !hv_get_vp_assist_page(cpu)) | |
3876 | return -EFAULT; | |
3877 | ||
d462b819 | 3878 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
bf9f6ac8 FW |
3879 | INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); |
3880 | spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
8f536b76 ZY |
3881 | |
3882 | /* | |
3883 | * Now we can enable the vmclear operation in kdump | |
3884 | * since the loaded_vmcss_on_cpu list on this cpu | |
3885 | * has been initialized. | |
3886 | * | |
3887 | * Though the cpu is not in VMX operation now, there | |
3888 | * is no problem to enable the vmclear operation | |
3889 | * for the loaded_vmcss_on_cpu list is empty! | |
3890 | */ | |
3891 | crash_enable_local_vmclear(cpu); | |
3892 | ||
6aa8b732 | 3893 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
3894 | |
3895 | test_bits = FEATURE_CONTROL_LOCKED; | |
3896 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
3897 | if (tboot_enabled()) | |
3898 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
3899 | ||
3900 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 3901 | /* enable and lock */ |
cafd6659 SW |
3902 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
3903 | } | |
fe0e80be | 3904 | kvm_cpu_vmxon(phys_addr); |
fdf288bf DH |
3905 | if (enable_ept) |
3906 | ept_sync_global(); | |
10474ae8 AG |
3907 | |
3908 | return 0; | |
6aa8b732 AK |
3909 | } |
3910 | ||
d462b819 | 3911 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
3912 | { |
3913 | int cpu = raw_smp_processor_id(); | |
d462b819 | 3914 | struct loaded_vmcs *v, *n; |
543e4243 | 3915 | |
d462b819 NHE |
3916 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
3917 | loaded_vmcss_on_cpu_link) | |
3918 | __loaded_vmcs_clear(v); | |
543e4243 AK |
3919 | } |
3920 | ||
710ff4a8 EH |
3921 | |
3922 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
3923 | * tricks. | |
3924 | */ | |
3925 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 3926 | { |
4ecac3fd | 3927 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
1c5ac21a AS |
3928 | |
3929 | intel_pt_handle_vmx(0); | |
fe0e80be | 3930 | cr4_clear_bits(X86_CR4_VMXE); |
6aa8b732 AK |
3931 | } |
3932 | ||
13a34e06 | 3933 | static void hardware_disable(void) |
710ff4a8 | 3934 | { |
fe0e80be DH |
3935 | vmclear_local_loaded_vmcss(); |
3936 | kvm_cpu_vmxoff(); | |
710ff4a8 EH |
3937 | } |
3938 | ||
1c3d14fe | 3939 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 3940 | u32 msr, u32 *result) |
1c3d14fe YS |
3941 | { |
3942 | u32 vmx_msr_low, vmx_msr_high; | |
3943 | u32 ctl = ctl_min | ctl_opt; | |
3944 | ||
3945 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3946 | ||
3947 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
3948 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
3949 | ||
3950 | /* Ensure minimum (required) set of control bits are supported. */ | |
3951 | if (ctl_min & ~ctl) | |
002c7f7c | 3952 | return -EIO; |
1c3d14fe YS |
3953 | |
3954 | *result = ctl; | |
3955 | return 0; | |
3956 | } | |
3957 | ||
110312c8 AK |
3958 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
3959 | { | |
3960 | u32 vmx_msr_low, vmx_msr_high; | |
3961 | ||
3962 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3963 | return vmx_msr_high & ctl; | |
3964 | } | |
3965 | ||
002c7f7c | 3966 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
3967 | { |
3968 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 3969 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
3970 | u32 _pin_based_exec_control = 0; |
3971 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 3972 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
3973 | u32 _vmexit_control = 0; |
3974 | u32 _vmentry_control = 0; | |
3975 | ||
1389309c | 3976 | memset(vmcs_conf, 0, sizeof(*vmcs_conf)); |
10166744 | 3977 | min = CPU_BASED_HLT_EXITING | |
1c3d14fe YS |
3978 | #ifdef CONFIG_X86_64 |
3979 | CPU_BASED_CR8_LOAD_EXITING | | |
3980 | CPU_BASED_CR8_STORE_EXITING | | |
3981 | #endif | |
d56f546d SY |
3982 | CPU_BASED_CR3_LOAD_EXITING | |
3983 | CPU_BASED_CR3_STORE_EXITING | | |
8eb73e2d | 3984 | CPU_BASED_UNCOND_IO_EXITING | |
1c3d14fe | 3985 | CPU_BASED_MOV_DR_EXITING | |
a7052897 | 3986 | CPU_BASED_USE_TSC_OFFSETING | |
4d5422ce WL |
3987 | CPU_BASED_MWAIT_EXITING | |
3988 | CPU_BASED_MONITOR_EXITING | | |
fee84b07 AK |
3989 | CPU_BASED_INVLPG_EXITING | |
3990 | CPU_BASED_RDPMC_EXITING; | |
443381a8 | 3991 | |
f78e0e2e | 3992 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 3993 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 3994 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
3995 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
3996 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 3997 | return -EIO; |
6e5d865c YS |
3998 | #ifdef CONFIG_X86_64 |
3999 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
4000 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
4001 | ~CPU_BASED_CR8_STORE_EXITING; | |
4002 | #endif | |
f78e0e2e | 4003 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
4004 | min2 = 0; |
4005 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
8d14695f | 4006 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2384d2b3 | 4007 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 4008 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 4009 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 4010 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 | 4011 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
0367f205 | 4012 | SECONDARY_EXEC_DESC | |
ad756a16 | 4013 | SECONDARY_EXEC_RDTSCP | |
83d4c286 | 4014 | SECONDARY_EXEC_ENABLE_INVPCID | |
c7c9c56c | 4015 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
abc4fc58 | 4016 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
20300099 | 4017 | SECONDARY_EXEC_SHADOW_VMCS | |
843e4330 | 4018 | SECONDARY_EXEC_XSAVES | |
736fdf72 DH |
4019 | SECONDARY_EXEC_RDSEED_EXITING | |
4020 | SECONDARY_EXEC_RDRAND_EXITING | | |
8b3e34e4 | 4021 | SECONDARY_EXEC_ENABLE_PML | |
2a499e49 BD |
4022 | SECONDARY_EXEC_TSC_SCALING | |
4023 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
d56f546d SY |
4024 | if (adjust_vmx_controls(min2, opt2, |
4025 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
4026 | &_cpu_based_2nd_exec_control) < 0) |
4027 | return -EIO; | |
4028 | } | |
4029 | #ifndef CONFIG_X86_64 | |
4030 | if (!(_cpu_based_2nd_exec_control & | |
4031 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
4032 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
4033 | #endif | |
83d4c286 YZ |
4034 | |
4035 | if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
4036 | _cpu_based_2nd_exec_control &= ~( | |
8d14695f | 4037 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
c7c9c56c YZ |
4038 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
4039 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
83d4c286 | 4040 | |
61f1dd90 WL |
4041 | rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, |
4042 | &vmx_capability.ept, &vmx_capability.vpid); | |
4043 | ||
d56f546d | 4044 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
4045 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
4046 | enabled */ | |
5fff7d27 GN |
4047 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
4048 | CPU_BASED_CR3_STORE_EXITING | | |
4049 | CPU_BASED_INVLPG_EXITING); | |
61f1dd90 WL |
4050 | } else if (vmx_capability.ept) { |
4051 | vmx_capability.ept = 0; | |
4052 | pr_warn_once("EPT CAP should not exist if not support " | |
4053 | "1-setting enable EPT VM-execution control\n"); | |
4054 | } | |
4055 | if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && | |
4056 | vmx_capability.vpid) { | |
4057 | vmx_capability.vpid = 0; | |
4058 | pr_warn_once("VPID CAP should not exist if not support " | |
4059 | "1-setting enable VPID VM-execution control\n"); | |
d56f546d | 4060 | } |
1c3d14fe | 4061 | |
91fa0f8e | 4062 | min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; |
1c3d14fe YS |
4063 | #ifdef CONFIG_X86_64 |
4064 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
4065 | #endif | |
a547c6db | 4066 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT | |
91fa0f8e | 4067 | VM_EXIT_CLEAR_BNDCFGS; |
1c3d14fe YS |
4068 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
4069 | &_vmexit_control) < 0) | |
002c7f7c | 4070 | return -EIO; |
1c3d14fe | 4071 | |
8a1b4392 PB |
4072 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; |
4073 | opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | | |
4074 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
4075 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
4076 | &_pin_based_exec_control) < 0) | |
4077 | return -EIO; | |
4078 | ||
1c17c3e6 PB |
4079 | if (cpu_has_broken_vmx_preemption_timer()) |
4080 | _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be | 4081 | if (!(_cpu_based_2nd_exec_control & |
91fa0f8e | 4082 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) |
01e439be YZ |
4083 | _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; |
4084 | ||
c845f9c6 | 4085 | min = VM_ENTRY_LOAD_DEBUG_CONTROLS; |
da8999d3 | 4086 | opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS; |
1c3d14fe YS |
4087 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
4088 | &_vmentry_control) < 0) | |
002c7f7c | 4089 | return -EIO; |
6aa8b732 | 4090 | |
c68876fd | 4091 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
4092 | |
4093 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
4094 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 4095 | return -EIO; |
1c3d14fe YS |
4096 | |
4097 | #ifdef CONFIG_X86_64 | |
4098 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
4099 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 4100 | return -EIO; |
1c3d14fe YS |
4101 | #endif |
4102 | ||
4103 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
4104 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 4105 | return -EIO; |
1c3d14fe | 4106 | |
002c7f7c | 4107 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
16cb0255 | 4108 | vmcs_conf->order = get_order(vmcs_conf->size); |
9ac7e3e8 | 4109 | vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; |
773e8a04 VK |
4110 | |
4111 | /* KVM supports Enlightened VMCS v1 only */ | |
4112 | if (static_branch_unlikely(&enable_evmcs)) | |
4113 | vmcs_conf->revision_id = KVM_EVMCS_VERSION; | |
4114 | else | |
4115 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 4116 | |
002c7f7c YS |
4117 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
4118 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 4119 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
4120 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
4121 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 4122 | |
773e8a04 VK |
4123 | if (static_branch_unlikely(&enable_evmcs)) |
4124 | evmcs_sanitize_exec_ctrls(vmcs_conf); | |
4125 | ||
110312c8 AK |
4126 | cpu_has_load_ia32_efer = |
4127 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
4128 | VM_ENTRY_LOAD_IA32_EFER) | |
4129 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
4130 | VM_EXIT_LOAD_IA32_EFER); | |
4131 | ||
8bf00a52 GN |
4132 | cpu_has_load_perf_global_ctrl = |
4133 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
4134 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
4135 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
4136 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
4137 | ||
4138 | /* | |
4139 | * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL | |
bb3541f1 | 4140 | * but due to errata below it can't be used. Workaround is to use |
8bf00a52 GN |
4141 | * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. |
4142 | * | |
4143 | * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] | |
4144 | * | |
4145 | * AAK155 (model 26) | |
4146 | * AAP115 (model 30) | |
4147 | * AAT100 (model 37) | |
4148 | * BC86,AAY89,BD102 (model 44) | |
4149 | * BA97 (model 46) | |
4150 | * | |
4151 | */ | |
4152 | if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) { | |
4153 | switch (boot_cpu_data.x86_model) { | |
4154 | case 26: | |
4155 | case 30: | |
4156 | case 37: | |
4157 | case 44: | |
4158 | case 46: | |
4159 | cpu_has_load_perf_global_ctrl = false; | |
4160 | printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " | |
4161 | "does not work properly. Using workaround\n"); | |
4162 | break; | |
4163 | default: | |
4164 | break; | |
4165 | } | |
4166 | } | |
4167 | ||
782511b0 | 4168 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
20300099 WL |
4169 | rdmsrl(MSR_IA32_XSS, host_xss); |
4170 | ||
1c3d14fe | 4171 | return 0; |
c68876fd | 4172 | } |
6aa8b732 AK |
4173 | |
4174 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
4175 | { | |
4176 | int node = cpu_to_node(cpu); | |
4177 | struct page *pages; | |
4178 | struct vmcs *vmcs; | |
4179 | ||
96db800f | 4180 | pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
4181 | if (!pages) |
4182 | return NULL; | |
4183 | vmcs = page_address(pages); | |
1c3d14fe YS |
4184 | memset(vmcs, 0, vmcs_config.size); |
4185 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
4186 | return vmcs; |
4187 | } | |
4188 | ||
6aa8b732 AK |
4189 | static void free_vmcs(struct vmcs *vmcs) |
4190 | { | |
1c3d14fe | 4191 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
4192 | } |
4193 | ||
d462b819 NHE |
4194 | /* |
4195 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
4196 | */ | |
4197 | static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
4198 | { | |
4199 | if (!loaded_vmcs->vmcs) | |
4200 | return; | |
4201 | loaded_vmcs_clear(loaded_vmcs); | |
4202 | free_vmcs(loaded_vmcs->vmcs); | |
4203 | loaded_vmcs->vmcs = NULL; | |
904e14fb PB |
4204 | if (loaded_vmcs->msr_bitmap) |
4205 | free_page((unsigned long)loaded_vmcs->msr_bitmap); | |
355f4fb1 | 4206 | WARN_ON(loaded_vmcs->shadow_vmcs != NULL); |
d462b819 NHE |
4207 | } |
4208 | ||
f21f165e PB |
4209 | static struct vmcs *alloc_vmcs(void) |
4210 | { | |
4211 | return alloc_vmcs_cpu(raw_smp_processor_id()); | |
4212 | } | |
4213 | ||
4214 | static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
4215 | { | |
4216 | loaded_vmcs->vmcs = alloc_vmcs(); | |
4217 | if (!loaded_vmcs->vmcs) | |
4218 | return -ENOMEM; | |
4219 | ||
4220 | loaded_vmcs->shadow_vmcs = NULL; | |
4221 | loaded_vmcs_init(loaded_vmcs); | |
904e14fb PB |
4222 | |
4223 | if (cpu_has_vmx_msr_bitmap()) { | |
4224 | loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL); | |
4225 | if (!loaded_vmcs->msr_bitmap) | |
4226 | goto out_vmcs; | |
4227 | memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); | |
4228 | } | |
f21f165e | 4229 | return 0; |
904e14fb PB |
4230 | |
4231 | out_vmcs: | |
4232 | free_loaded_vmcs(loaded_vmcs); | |
4233 | return -ENOMEM; | |
f21f165e PB |
4234 | } |
4235 | ||
39959588 | 4236 | static void free_kvm_area(void) |
6aa8b732 AK |
4237 | { |
4238 | int cpu; | |
4239 | ||
3230bb47 | 4240 | for_each_possible_cpu(cpu) { |
6aa8b732 | 4241 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
4242 | per_cpu(vmxarea, cpu) = NULL; |
4243 | } | |
6aa8b732 AK |
4244 | } |
4245 | ||
d37f4267 JM |
4246 | enum vmcs_field_width { |
4247 | VMCS_FIELD_WIDTH_U16 = 0, | |
4248 | VMCS_FIELD_WIDTH_U64 = 1, | |
4249 | VMCS_FIELD_WIDTH_U32 = 2, | |
4250 | VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3 | |
85fd514e JM |
4251 | }; |
4252 | ||
d37f4267 | 4253 | static inline int vmcs_field_width(unsigned long field) |
85fd514e JM |
4254 | { |
4255 | if (0x1 & field) /* the *_HIGH fields are all 32 bit */ | |
d37f4267 | 4256 | return VMCS_FIELD_WIDTH_U32; |
85fd514e JM |
4257 | return (field >> 13) & 0x3 ; |
4258 | } | |
4259 | ||
4260 | static inline int vmcs_field_readonly(unsigned long field) | |
4261 | { | |
4262 | return (((field >> 10) & 0x3) == 1); | |
4263 | } | |
4264 | ||
fe2b201b BD |
4265 | static void init_vmcs_shadow_fields(void) |
4266 | { | |
4267 | int i, j; | |
4268 | ||
44900ba6 PB |
4269 | for (i = j = 0; i < max_shadow_read_only_fields; i++) { |
4270 | u16 field = shadow_read_only_fields[i]; | |
d37f4267 | 4271 | if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 && |
44900ba6 PB |
4272 | (i + 1 == max_shadow_read_only_fields || |
4273 | shadow_read_only_fields[i + 1] != field + 1)) | |
4274 | pr_err("Missing field from shadow_read_only_field %x\n", | |
4275 | field + 1); | |
4276 | ||
4277 | clear_bit(field, vmx_vmread_bitmap); | |
4278 | #ifdef CONFIG_X86_64 | |
4279 | if (field & 1) | |
4280 | continue; | |
4281 | #endif | |
4282 | if (j < i) | |
4283 | shadow_read_only_fields[j] = field; | |
4284 | j++; | |
4285 | } | |
4286 | max_shadow_read_only_fields = j; | |
fe2b201b BD |
4287 | |
4288 | for (i = j = 0; i < max_shadow_read_write_fields; i++) { | |
44900ba6 | 4289 | u16 field = shadow_read_write_fields[i]; |
d37f4267 | 4290 | if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 && |
44900ba6 PB |
4291 | (i + 1 == max_shadow_read_write_fields || |
4292 | shadow_read_write_fields[i + 1] != field + 1)) | |
4293 | pr_err("Missing field from shadow_read_write_field %x\n", | |
4294 | field + 1); | |
4295 | ||
c5d167b2 PB |
4296 | /* |
4297 | * PML and the preemption timer can be emulated, but the | |
4298 | * processor cannot vmwrite to fields that don't exist | |
4299 | * on bare metal. | |
4300 | */ | |
44900ba6 | 4301 | switch (field) { |
c5d167b2 PB |
4302 | case GUEST_PML_INDEX: |
4303 | if (!cpu_has_vmx_pml()) | |
4304 | continue; | |
4305 | break; | |
4306 | case VMX_PREEMPTION_TIMER_VALUE: | |
4307 | if (!cpu_has_vmx_preemption_timer()) | |
4308 | continue; | |
4309 | break; | |
4310 | case GUEST_INTR_STATUS: | |
4311 | if (!cpu_has_vmx_apicv()) | |
fe2b201b BD |
4312 | continue; |
4313 | break; | |
4314 | default: | |
4315 | break; | |
4316 | } | |
4317 | ||
44900ba6 PB |
4318 | clear_bit(field, vmx_vmwrite_bitmap); |
4319 | clear_bit(field, vmx_vmread_bitmap); | |
4320 | #ifdef CONFIG_X86_64 | |
4321 | if (field & 1) | |
4322 | continue; | |
4323 | #endif | |
fe2b201b | 4324 | if (j < i) |
44900ba6 | 4325 | shadow_read_write_fields[j] = field; |
fe2b201b BD |
4326 | j++; |
4327 | } | |
4328 | max_shadow_read_write_fields = j; | |
fe2b201b BD |
4329 | } |
4330 | ||
6aa8b732 AK |
4331 | static __init int alloc_kvm_area(void) |
4332 | { | |
4333 | int cpu; | |
4334 | ||
3230bb47 | 4335 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
4336 | struct vmcs *vmcs; |
4337 | ||
4338 | vmcs = alloc_vmcs_cpu(cpu); | |
4339 | if (!vmcs) { | |
4340 | free_kvm_area(); | |
4341 | return -ENOMEM; | |
4342 | } | |
4343 | ||
4344 | per_cpu(vmxarea, cpu) = vmcs; | |
4345 | } | |
4346 | return 0; | |
4347 | } | |
4348 | ||
91b0aa2c | 4349 | static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, |
d99e4152 | 4350 | struct kvm_segment *save) |
6aa8b732 | 4351 | { |
d99e4152 GN |
4352 | if (!emulate_invalid_guest_state) { |
4353 | /* | |
4354 | * CS and SS RPL should be equal during guest entry according | |
4355 | * to VMX spec, but in reality it is not always so. Since vcpu | |
4356 | * is in the middle of the transition from real mode to | |
4357 | * protected mode it is safe to assume that RPL 0 is a good | |
4358 | * default value. | |
4359 | */ | |
4360 | if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) | |
b32a9918 NA |
4361 | save->selector &= ~SEGMENT_RPL_MASK; |
4362 | save->dpl = save->selector & SEGMENT_RPL_MASK; | |
d99e4152 | 4363 | save->s = 1; |
6aa8b732 | 4364 | } |
d99e4152 | 4365 | vmx_set_segment(vcpu, save, seg); |
6aa8b732 AK |
4366 | } |
4367 | ||
4368 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
4369 | { | |
4370 | unsigned long flags; | |
a89a8fb9 | 4371 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 4372 | |
d99e4152 GN |
4373 | /* |
4374 | * Update real mode segment cache. It may be not up-to-date if sement | |
4375 | * register was written while vcpu was in a guest mode. | |
4376 | */ | |
4377 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
4378 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
4379 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
4380 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
4381 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); | |
4382 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
4383 | ||
7ffd92c5 | 4384 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 4385 | |
2fb92db1 AK |
4386 | vmx_segment_cache_clear(vmx); |
4387 | ||
f5f7b2fe | 4388 | vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
6aa8b732 AK |
4389 | |
4390 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
4391 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
4392 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
4393 | vmcs_writel(GUEST_RFLAGS, flags); |
4394 | ||
66aee91a RR |
4395 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
4396 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
4397 | |
4398 | update_exception_bitmap(vcpu); | |
4399 | ||
91b0aa2c GN |
4400 | fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); |
4401 | fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); | |
4402 | fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
4403 | fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
4404 | fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
4405 | fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
6aa8b732 AK |
4406 | } |
4407 | ||
f5f7b2fe | 4408 | static void fix_rmode_seg(int seg, struct kvm_segment *save) |
6aa8b732 | 4409 | { |
772e0318 | 4410 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
d99e4152 GN |
4411 | struct kvm_segment var = *save; |
4412 | ||
4413 | var.dpl = 0x3; | |
4414 | if (seg == VCPU_SREG_CS) | |
4415 | var.type = 0x3; | |
4416 | ||
4417 | if (!emulate_invalid_guest_state) { | |
4418 | var.selector = var.base >> 4; | |
4419 | var.base = var.base & 0xffff0; | |
4420 | var.limit = 0xffff; | |
4421 | var.g = 0; | |
4422 | var.db = 0; | |
4423 | var.present = 1; | |
4424 | var.s = 1; | |
4425 | var.l = 0; | |
4426 | var.unusable = 0; | |
4427 | var.type = 0x3; | |
4428 | var.avl = 0; | |
4429 | if (save->base & 0xf) | |
4430 | printk_once(KERN_WARNING "kvm: segment base is not " | |
4431 | "paragraph aligned when entering " | |
4432 | "protected mode (seg=%d)", seg); | |
4433 | } | |
6aa8b732 | 4434 | |
d99e4152 | 4435 | vmcs_write16(sf->selector, var.selector); |
96794e4e | 4436 | vmcs_writel(sf->base, var.base); |
d99e4152 GN |
4437 | vmcs_write32(sf->limit, var.limit); |
4438 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); | |
6aa8b732 AK |
4439 | } |
4440 | ||
4441 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
4442 | { | |
4443 | unsigned long flags; | |
a89a8fb9 | 4444 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
40bbb9d0 | 4445 | struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); |
6aa8b732 | 4446 | |
f5f7b2fe AK |
4447 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
4448 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
4449 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
4450 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
4451 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
c6ad1153 GN |
4452 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); |
4453 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
f5f7b2fe | 4454 | |
7ffd92c5 | 4455 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 4456 | |
776e58ea GN |
4457 | /* |
4458 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
4918c6ca | 4459 | * vcpu. Warn the user that an update is overdue. |
776e58ea | 4460 | */ |
40bbb9d0 | 4461 | if (!kvm_vmx->tss_addr) |
776e58ea GN |
4462 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " |
4463 | "called before entering vcpu\n"); | |
776e58ea | 4464 | |
2fb92db1 AK |
4465 | vmx_segment_cache_clear(vmx); |
4466 | ||
40bbb9d0 | 4467 | vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); |
6aa8b732 | 4468 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
6aa8b732 AK |
4469 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
4470 | ||
4471 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 4472 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 4473 | |
053de044 | 4474 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
4475 | |
4476 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 4477 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
4478 | update_exception_bitmap(vcpu); |
4479 | ||
d99e4152 GN |
4480 | fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); |
4481 | fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); | |
4482 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
4483 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
4484 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
4485 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
b246dd5d | 4486 | |
8668a3c4 | 4487 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
4488 | } |
4489 | ||
401d10de AS |
4490 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
4491 | { | |
4492 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
4493 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
4494 | ||
4495 | if (!msr) | |
4496 | return; | |
401d10de | 4497 | |
44ea2b17 AK |
4498 | /* |
4499 | * Force kernel_gs_base reloading before EFER changes, as control | |
4500 | * of this msr depends on is_long_mode(). | |
4501 | */ | |
4502 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 4503 | vcpu->arch.efer = efer; |
401d10de | 4504 | if (efer & EFER_LMA) { |
2961e876 | 4505 | vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
4506 | msr->data = efer; |
4507 | } else { | |
2961e876 | 4508 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
4509 | |
4510 | msr->data = efer & ~EFER_LME; | |
4511 | } | |
4512 | setup_msrs(vmx); | |
4513 | } | |
4514 | ||
05b3e0c2 | 4515 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
4516 | |
4517 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
4518 | { | |
4519 | u32 guest_tr_ar; | |
4520 | ||
2fb92db1 AK |
4521 | vmx_segment_cache_clear(to_vmx(vcpu)); |
4522 | ||
6aa8b732 | 4523 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
4d283ec9 | 4524 | if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { |
bd80158a JK |
4525 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
4526 | __func__); | |
6aa8b732 | 4527 | vmcs_write32(GUEST_TR_AR_BYTES, |
4d283ec9 AL |
4528 | (guest_tr_ar & ~VMX_AR_TYPE_MASK) |
4529 | | VMX_AR_TYPE_BUSY_64_TSS); | |
6aa8b732 | 4530 | } |
da38f438 | 4531 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
4532 | } |
4533 | ||
4534 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
4535 | { | |
2961e876 | 4536 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
da38f438 | 4537 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
4538 | } |
4539 | ||
4540 | #endif | |
4541 | ||
c2ba05cc WL |
4542 | static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid, |
4543 | bool invalidate_gpa) | |
2384d2b3 | 4544 | { |
c2ba05cc | 4545 | if (enable_ept && (invalidate_gpa || !enable_vpid)) { |
dd180b3e XG |
4546 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
4547 | return; | |
995f00a6 | 4548 | ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa)); |
f0b98c02 JM |
4549 | } else { |
4550 | vpid_sync_context(vpid); | |
dd180b3e | 4551 | } |
2384d2b3 SY |
4552 | } |
4553 | ||
c2ba05cc | 4554 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) |
dd5f5341 | 4555 | { |
c2ba05cc | 4556 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa); |
dd5f5341 WL |
4557 | } |
4558 | ||
e8467fda AK |
4559 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
4560 | { | |
4561 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
4562 | ||
4563 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
4564 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
4565 | } | |
4566 | ||
aff48baa AK |
4567 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
4568 | { | |
b4d18517 | 4569 | if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu))) |
aff48baa AK |
4570 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); |
4571 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
4572 | } | |
4573 | ||
25c4c276 | 4574 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 4575 | { |
fc78f519 AK |
4576 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
4577 | ||
4578 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
4579 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
4580 | } |
4581 | ||
1439442c SY |
4582 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
4583 | { | |
d0d538b9 GN |
4584 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4585 | ||
6de4f3ad AK |
4586 | if (!test_bit(VCPU_EXREG_PDPTR, |
4587 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
4588 | return; | |
4589 | ||
1439442c | 4590 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
4591 | vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); |
4592 | vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); | |
4593 | vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); | |
4594 | vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); | |
1439442c SY |
4595 | } |
4596 | } | |
4597 | ||
8f5d549f AK |
4598 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
4599 | { | |
d0d538b9 GN |
4600 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4601 | ||
8f5d549f | 4602 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
4603 | mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
4604 | mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
4605 | mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
4606 | mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 4607 | } |
6de4f3ad AK |
4608 | |
4609 | __set_bit(VCPU_EXREG_PDPTR, | |
4610 | (unsigned long *)&vcpu->arch.regs_avail); | |
4611 | __set_bit(VCPU_EXREG_PDPTR, | |
4612 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
4613 | } |
4614 | ||
3899152c DM |
4615 | static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) |
4616 | { | |
6677f3da PB |
4617 | u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0; |
4618 | u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1; | |
3899152c DM |
4619 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
4620 | ||
6677f3da | 4621 | if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high & |
3899152c DM |
4622 | SECONDARY_EXEC_UNRESTRICTED_GUEST && |
4623 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) | |
4624 | fixed0 &= ~(X86_CR0_PE | X86_CR0_PG); | |
4625 | ||
4626 | return fixed_bits_valid(val, fixed0, fixed1); | |
4627 | } | |
4628 | ||
4629 | static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4630 | { | |
6677f3da PB |
4631 | u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0; |
4632 | u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1; | |
3899152c DM |
4633 | |
4634 | return fixed_bits_valid(val, fixed0, fixed1); | |
4635 | } | |
4636 | ||
4637 | static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4638 | { | |
6677f3da PB |
4639 | u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0; |
4640 | u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1; | |
3899152c DM |
4641 | |
4642 | return fixed_bits_valid(val, fixed0, fixed1); | |
4643 | } | |
4644 | ||
4645 | /* No difference in the restrictions on guest and host CR4 in VMX operation. */ | |
4646 | #define nested_guest_cr4_valid nested_cr4_valid | |
4647 | #define nested_host_cr4_valid nested_cr4_valid | |
4648 | ||
5e1746d6 | 4649 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1439442c SY |
4650 | |
4651 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
4652 | unsigned long cr0, | |
4653 | struct kvm_vcpu *vcpu) | |
4654 | { | |
5233dd51 MT |
4655 | if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
4656 | vmx_decache_cr3(vcpu); | |
1439442c SY |
4657 | if (!(cr0 & X86_CR0_PG)) { |
4658 | /* From paging/starting to nonpaging */ | |
4659 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4660 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
4661 | (CPU_BASED_CR3_LOAD_EXITING | |
4662 | CPU_BASED_CR3_STORE_EXITING)); | |
4663 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4664 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
4665 | } else if (!is_paging(vcpu)) { |
4666 | /* From nonpaging to paging */ | |
4667 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4668 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
4669 | ~(CPU_BASED_CR3_LOAD_EXITING | |
4670 | CPU_BASED_CR3_STORE_EXITING)); | |
4671 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4672 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 4673 | } |
95eb84a7 SY |
4674 | |
4675 | if (!(cr0 & X86_CR0_WP)) | |
4676 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
4677 | } |
4678 | ||
6aa8b732 AK |
4679 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
4680 | { | |
7ffd92c5 | 4681 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
4682 | unsigned long hw_cr0; |
4683 | ||
5037878e | 4684 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK); |
3a624e29 | 4685 | if (enable_unrestricted_guest) |
5037878e | 4686 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; |
218e763f | 4687 | else { |
5037878e | 4688 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; |
1439442c | 4689 | |
218e763f GN |
4690 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
4691 | enter_pmode(vcpu); | |
6aa8b732 | 4692 | |
218e763f GN |
4693 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
4694 | enter_rmode(vcpu); | |
4695 | } | |
6aa8b732 | 4696 | |
05b3e0c2 | 4697 | #ifdef CONFIG_X86_64 |
f6801dff | 4698 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 4699 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 4700 | enter_lmode(vcpu); |
707d92fa | 4701 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
4702 | exit_lmode(vcpu); |
4703 | } | |
4704 | #endif | |
4705 | ||
b4d18517 | 4706 | if (enable_ept && !enable_unrestricted_guest) |
1439442c SY |
4707 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
4708 | ||
6aa8b732 | 4709 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 4710 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 4711 | vcpu->arch.cr0 = cr0; |
14168786 GN |
4712 | |
4713 | /* depends on vcpu->arch.cr0 to be set to a new value */ | |
4714 | vmx->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
4715 | } |
4716 | ||
855feb67 YZ |
4717 | static int get_ept_level(struct kvm_vcpu *vcpu) |
4718 | { | |
4719 | if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) | |
4720 | return 5; | |
4721 | return 4; | |
4722 | } | |
4723 | ||
995f00a6 | 4724 | static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) |
1439442c | 4725 | { |
855feb67 YZ |
4726 | u64 eptp = VMX_EPTP_MT_WB; |
4727 | ||
4728 | eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; | |
1439442c | 4729 | |
995f00a6 PF |
4730 | if (enable_ept_ad_bits && |
4731 | (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) | |
bb97a016 | 4732 | eptp |= VMX_EPTP_AD_ENABLE_BIT; |
1439442c SY |
4733 | eptp |= (root_hpa & PAGE_MASK); |
4734 | ||
4735 | return eptp; | |
4736 | } | |
4737 | ||
6aa8b732 AK |
4738 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
4739 | { | |
1439442c SY |
4740 | unsigned long guest_cr3; |
4741 | u64 eptp; | |
4742 | ||
4743 | guest_cr3 = cr3; | |
089d034e | 4744 | if (enable_ept) { |
995f00a6 | 4745 | eptp = construct_eptp(vcpu, cr3); |
1439442c | 4746 | vmcs_write64(EPT_POINTER, eptp); |
e90008df SC |
4747 | if (enable_unrestricted_guest || is_paging(vcpu) || |
4748 | is_guest_mode(vcpu)) | |
59ab5a8f JK |
4749 | guest_cr3 = kvm_read_cr3(vcpu); |
4750 | else | |
40bbb9d0 | 4751 | guest_cr3 = to_kvm_vmx(vcpu->kvm)->ept_identity_map_addr; |
7c93be44 | 4752 | ept_load_pdptrs(vcpu); |
1439442c SY |
4753 | } |
4754 | ||
c2ba05cc | 4755 | vmx_flush_tlb(vcpu, true); |
1439442c | 4756 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
4757 | } |
4758 | ||
5e1746d6 | 4759 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 4760 | { |
085e68ee BS |
4761 | /* |
4762 | * Pass through host's Machine Check Enable value to hw_cr4, which | |
4763 | * is in force while we are in guest mode. Do not let guests control | |
4764 | * this bit, even if host CR4.MCE == 0. | |
4765 | */ | |
5dc1f044 SC |
4766 | unsigned long hw_cr4; |
4767 | ||
4768 | hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); | |
4769 | if (enable_unrestricted_guest) | |
4770 | hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; | |
4771 | else if (to_vmx(vcpu)->rmode.vm86_active) | |
4772 | hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; | |
4773 | else | |
4774 | hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; | |
1439442c | 4775 | |
64f7a115 SC |
4776 | if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { |
4777 | if (cr4 & X86_CR4_UMIP) { | |
4778 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
0367f205 | 4779 | SECONDARY_EXEC_DESC); |
64f7a115 SC |
4780 | hw_cr4 &= ~X86_CR4_UMIP; |
4781 | } else if (!is_guest_mode(vcpu) || | |
4782 | !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) | |
4783 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
4784 | SECONDARY_EXEC_DESC); | |
4785 | } | |
0367f205 | 4786 | |
5e1746d6 NHE |
4787 | if (cr4 & X86_CR4_VMXE) { |
4788 | /* | |
4789 | * To use VMXON (and later other VMX instructions), a guest | |
4790 | * must first be able to turn on cr4.VMXE (see handle_vmon()). | |
4791 | * So basically the check on whether to allow nested VMX | |
4792 | * is here. | |
4793 | */ | |
4794 | if (!nested_vmx_allowed(vcpu)) | |
4795 | return 1; | |
1a0d74e6 | 4796 | } |
3899152c DM |
4797 | |
4798 | if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) | |
5e1746d6 NHE |
4799 | return 1; |
4800 | ||
ad312c7c | 4801 | vcpu->arch.cr4 = cr4; |
5dc1f044 SC |
4802 | |
4803 | if (!enable_unrestricted_guest) { | |
4804 | if (enable_ept) { | |
4805 | if (!is_paging(vcpu)) { | |
4806 | hw_cr4 &= ~X86_CR4_PAE; | |
4807 | hw_cr4 |= X86_CR4_PSE; | |
4808 | } else if (!(cr4 & X86_CR4_PAE)) { | |
4809 | hw_cr4 &= ~X86_CR4_PAE; | |
4810 | } | |
bc23008b | 4811 | } |
1439442c | 4812 | |
656ec4a4 | 4813 | /* |
ddba2628 HH |
4814 | * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in |
4815 | * hardware. To emulate this behavior, SMEP/SMAP/PKU needs | |
4816 | * to be manually disabled when guest switches to non-paging | |
4817 | * mode. | |
4818 | * | |
4819 | * If !enable_unrestricted_guest, the CPU is always running | |
4820 | * with CR0.PG=1 and CR4 needs to be modified. | |
4821 | * If enable_unrestricted_guest, the CPU automatically | |
4822 | * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. | |
656ec4a4 | 4823 | */ |
5dc1f044 SC |
4824 | if (!is_paging(vcpu)) |
4825 | hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); | |
4826 | } | |
656ec4a4 | 4827 | |
1439442c SY |
4828 | vmcs_writel(CR4_READ_SHADOW, cr4); |
4829 | vmcs_writel(GUEST_CR4, hw_cr4); | |
5e1746d6 | 4830 | return 0; |
6aa8b732 AK |
4831 | } |
4832 | ||
6aa8b732 AK |
4833 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
4834 | struct kvm_segment *var, int seg) | |
4835 | { | |
a9179499 | 4836 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
4837 | u32 ar; |
4838 | ||
c6ad1153 | 4839 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
f5f7b2fe | 4840 | *var = vmx->rmode.segs[seg]; |
a9179499 | 4841 | if (seg == VCPU_SREG_TR |
2fb92db1 | 4842 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
f5f7b2fe | 4843 | return; |
1390a28b AK |
4844 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4845 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4846 | return; | |
a9179499 | 4847 | } |
2fb92db1 AK |
4848 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4849 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
4850 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4851 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
03617c18 | 4852 | var->unusable = (ar >> 16) & 1; |
6aa8b732 AK |
4853 | var->type = ar & 15; |
4854 | var->s = (ar >> 4) & 1; | |
4855 | var->dpl = (ar >> 5) & 3; | |
03617c18 GN |
4856 | /* |
4857 | * Some userspaces do not preserve unusable property. Since usable | |
4858 | * segment has to be present according to VMX spec we can use present | |
4859 | * property to amend userspace bug by making unusable segment always | |
4860 | * nonpresent. vmx_segment_access_rights() already marks nonpresent | |
4861 | * segment as unusable. | |
4862 | */ | |
4863 | var->present = !var->unusable; | |
6aa8b732 AK |
4864 | var->avl = (ar >> 12) & 1; |
4865 | var->l = (ar >> 13) & 1; | |
4866 | var->db = (ar >> 14) & 1; | |
4867 | var->g = (ar >> 15) & 1; | |
6aa8b732 AK |
4868 | } |
4869 | ||
a9179499 AK |
4870 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4871 | { | |
a9179499 AK |
4872 | struct kvm_segment s; |
4873 | ||
4874 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
4875 | vmx_get_segment(vcpu, &s, seg); | |
4876 | return s.base; | |
4877 | } | |
2fb92db1 | 4878 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
4879 | } |
4880 | ||
b09408d0 | 4881 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 4882 | { |
b09408d0 MT |
4883 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4884 | ||
ae9fedc7 | 4885 | if (unlikely(vmx->rmode.vm86_active)) |
2e4d2653 | 4886 | return 0; |
ae9fedc7 PB |
4887 | else { |
4888 | int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); | |
4d283ec9 | 4889 | return VMX_AR_DPL(ar); |
69c73028 | 4890 | } |
69c73028 AK |
4891 | } |
4892 | ||
653e3108 | 4893 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 4894 | { |
6aa8b732 AK |
4895 | u32 ar; |
4896 | ||
f0495f9b | 4897 | if (var->unusable || !var->present) |
6aa8b732 AK |
4898 | ar = 1 << 16; |
4899 | else { | |
4900 | ar = var->type & 15; | |
4901 | ar |= (var->s & 1) << 4; | |
4902 | ar |= (var->dpl & 3) << 5; | |
4903 | ar |= (var->present & 1) << 7; | |
4904 | ar |= (var->avl & 1) << 12; | |
4905 | ar |= (var->l & 1) << 13; | |
4906 | ar |= (var->db & 1) << 14; | |
4907 | ar |= (var->g & 1) << 15; | |
4908 | } | |
653e3108 AK |
4909 | |
4910 | return ar; | |
4911 | } | |
4912 | ||
4913 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
4914 | struct kvm_segment *var, int seg) | |
4915 | { | |
7ffd92c5 | 4916 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
772e0318 | 4917 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
653e3108 | 4918 | |
2fb92db1 AK |
4919 | vmx_segment_cache_clear(vmx); |
4920 | ||
1ecd50a9 GN |
4921 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
4922 | vmx->rmode.segs[seg] = *var; | |
4923 | if (seg == VCPU_SREG_TR) | |
4924 | vmcs_write16(sf->selector, var->selector); | |
4925 | else if (var->s) | |
4926 | fix_rmode_seg(seg, &vmx->rmode.segs[seg]); | |
d99e4152 | 4927 | goto out; |
653e3108 | 4928 | } |
1ecd50a9 | 4929 | |
653e3108 AK |
4930 | vmcs_writel(sf->base, var->base); |
4931 | vmcs_write32(sf->limit, var->limit); | |
4932 | vmcs_write16(sf->selector, var->selector); | |
3a624e29 NK |
4933 | |
4934 | /* | |
4935 | * Fix the "Accessed" bit in AR field of segment registers for older | |
4936 | * qemu binaries. | |
4937 | * IA32 arch specifies that at the time of processor reset the | |
4938 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
0fa06071 | 4939 | * is setting it to 0 in the userland code. This causes invalid guest |
3a624e29 NK |
4940 | * state vmexit when "unrestricted guest" mode is turned on. |
4941 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
4942 | * tree. Newer qemu binaries with that qemu fix would not need this | |
4943 | * kvm hack. | |
4944 | */ | |
4945 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
f924d66d | 4946 | var->type |= 0x1; /* Accessed */ |
3a624e29 | 4947 | |
f924d66d | 4948 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); |
d99e4152 GN |
4949 | |
4950 | out: | |
98eb2f8b | 4951 | vmx->emulation_required = emulation_required(vcpu); |
6aa8b732 AK |
4952 | } |
4953 | ||
6aa8b732 AK |
4954 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
4955 | { | |
2fb92db1 | 4956 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
4957 | |
4958 | *db = (ar >> 14) & 1; | |
4959 | *l = (ar >> 13) & 1; | |
4960 | } | |
4961 | ||
89a27f4d | 4962 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4963 | { |
89a27f4d GN |
4964 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
4965 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
4966 | } |
4967 | ||
89a27f4d | 4968 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4969 | { |
89a27f4d GN |
4970 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
4971 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
4972 | } |
4973 | ||
89a27f4d | 4974 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4975 | { |
89a27f4d GN |
4976 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
4977 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
4978 | } |
4979 | ||
89a27f4d | 4980 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4981 | { |
89a27f4d GN |
4982 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
4983 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
4984 | } |
4985 | ||
648dfaa7 MG |
4986 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
4987 | { | |
4988 | struct kvm_segment var; | |
4989 | u32 ar; | |
4990 | ||
4991 | vmx_get_segment(vcpu, &var, seg); | |
07f42f5f | 4992 | var.dpl = 0x3; |
0647f4aa GN |
4993 | if (seg == VCPU_SREG_CS) |
4994 | var.type = 0x3; | |
648dfaa7 MG |
4995 | ar = vmx_segment_access_rights(&var); |
4996 | ||
4997 | if (var.base != (var.selector << 4)) | |
4998 | return false; | |
89efbed0 | 4999 | if (var.limit != 0xffff) |
648dfaa7 | 5000 | return false; |
07f42f5f | 5001 | if (ar != 0xf3) |
648dfaa7 MG |
5002 | return false; |
5003 | ||
5004 | return true; | |
5005 | } | |
5006 | ||
5007 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
5008 | { | |
5009 | struct kvm_segment cs; | |
5010 | unsigned int cs_rpl; | |
5011 | ||
5012 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
b32a9918 | 5013 | cs_rpl = cs.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 5014 | |
1872a3f4 AK |
5015 | if (cs.unusable) |
5016 | return false; | |
4d283ec9 | 5017 | if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) |
648dfaa7 MG |
5018 | return false; |
5019 | if (!cs.s) | |
5020 | return false; | |
4d283ec9 | 5021 | if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
5022 | if (cs.dpl > cs_rpl) |
5023 | return false; | |
1872a3f4 | 5024 | } else { |
648dfaa7 MG |
5025 | if (cs.dpl != cs_rpl) |
5026 | return false; | |
5027 | } | |
5028 | if (!cs.present) | |
5029 | return false; | |
5030 | ||
5031 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
5032 | return true; | |
5033 | } | |
5034 | ||
5035 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
5036 | { | |
5037 | struct kvm_segment ss; | |
5038 | unsigned int ss_rpl; | |
5039 | ||
5040 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
b32a9918 | 5041 | ss_rpl = ss.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 5042 | |
1872a3f4 AK |
5043 | if (ss.unusable) |
5044 | return true; | |
5045 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
5046 | return false; |
5047 | if (!ss.s) | |
5048 | return false; | |
5049 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
5050 | return false; | |
5051 | if (!ss.present) | |
5052 | return false; | |
5053 | ||
5054 | return true; | |
5055 | } | |
5056 | ||
5057 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
5058 | { | |
5059 | struct kvm_segment var; | |
5060 | unsigned int rpl; | |
5061 | ||
5062 | vmx_get_segment(vcpu, &var, seg); | |
b32a9918 | 5063 | rpl = var.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 5064 | |
1872a3f4 AK |
5065 | if (var.unusable) |
5066 | return true; | |
648dfaa7 MG |
5067 | if (!var.s) |
5068 | return false; | |
5069 | if (!var.present) | |
5070 | return false; | |
4d283ec9 | 5071 | if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { |
648dfaa7 MG |
5072 | if (var.dpl < rpl) /* DPL < RPL */ |
5073 | return false; | |
5074 | } | |
5075 | ||
5076 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
5077 | * rights flags | |
5078 | */ | |
5079 | return true; | |
5080 | } | |
5081 | ||
5082 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
5083 | { | |
5084 | struct kvm_segment tr; | |
5085 | ||
5086 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
5087 | ||
1872a3f4 AK |
5088 | if (tr.unusable) |
5089 | return false; | |
b32a9918 | 5090 | if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 | 5091 | return false; |
1872a3f4 | 5092 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
5093 | return false; |
5094 | if (!tr.present) | |
5095 | return false; | |
5096 | ||
5097 | return true; | |
5098 | } | |
5099 | ||
5100 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
5101 | { | |
5102 | struct kvm_segment ldtr; | |
5103 | ||
5104 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
5105 | ||
1872a3f4 AK |
5106 | if (ldtr.unusable) |
5107 | return true; | |
b32a9918 | 5108 | if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 MG |
5109 | return false; |
5110 | if (ldtr.type != 2) | |
5111 | return false; | |
5112 | if (!ldtr.present) | |
5113 | return false; | |
5114 | ||
5115 | return true; | |
5116 | } | |
5117 | ||
5118 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
5119 | { | |
5120 | struct kvm_segment cs, ss; | |
5121 | ||
5122 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
5123 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
5124 | ||
b32a9918 NA |
5125 | return ((cs.selector & SEGMENT_RPL_MASK) == |
5126 | (ss.selector & SEGMENT_RPL_MASK)); | |
648dfaa7 MG |
5127 | } |
5128 | ||
5129 | /* | |
5130 | * Check if guest state is valid. Returns true if valid, false if | |
5131 | * not. | |
5132 | * We assume that registers are always usable | |
5133 | */ | |
5134 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
5135 | { | |
c5e97c80 GN |
5136 | if (enable_unrestricted_guest) |
5137 | return true; | |
5138 | ||
648dfaa7 | 5139 | /* real mode guest state checks */ |
f13882d8 | 5140 | if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { |
648dfaa7 MG |
5141 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
5142 | return false; | |
5143 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
5144 | return false; | |
5145 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
5146 | return false; | |
5147 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
5148 | return false; | |
5149 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
5150 | return false; | |
5151 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
5152 | return false; | |
5153 | } else { | |
5154 | /* protected mode guest state checks */ | |
5155 | if (!cs_ss_rpl_check(vcpu)) | |
5156 | return false; | |
5157 | if (!code_segment_valid(vcpu)) | |
5158 | return false; | |
5159 | if (!stack_segment_valid(vcpu)) | |
5160 | return false; | |
5161 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
5162 | return false; | |
5163 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
5164 | return false; | |
5165 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
5166 | return false; | |
5167 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
5168 | return false; | |
5169 | if (!tr_valid(vcpu)) | |
5170 | return false; | |
5171 | if (!ldtr_valid(vcpu)) | |
5172 | return false; | |
5173 | } | |
5174 | /* TODO: | |
5175 | * - Add checks on RIP | |
5176 | * - Add checks on RFLAGS | |
5177 | */ | |
5178 | ||
5179 | return true; | |
5180 | } | |
5181 | ||
5fa99cbe JM |
5182 | static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa) |
5183 | { | |
5184 | return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu)); | |
5185 | } | |
5186 | ||
d77c26fc | 5187 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 5188 | { |
40dcaa9f | 5189 | gfn_t fn; |
195aefde | 5190 | u16 data = 0; |
1f755a82 | 5191 | int idx, r; |
6aa8b732 | 5192 | |
40dcaa9f | 5193 | idx = srcu_read_lock(&kvm->srcu); |
40bbb9d0 | 5194 | fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; |
195aefde IE |
5195 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
5196 | if (r < 0) | |
10589a46 | 5197 | goto out; |
195aefde | 5198 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
5199 | r = kvm_write_guest_page(kvm, fn++, &data, |
5200 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 5201 | if (r < 0) |
10589a46 | 5202 | goto out; |
195aefde IE |
5203 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
5204 | if (r < 0) | |
10589a46 | 5205 | goto out; |
195aefde IE |
5206 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
5207 | if (r < 0) | |
10589a46 | 5208 | goto out; |
195aefde | 5209 | data = ~0; |
10589a46 MT |
5210 | r = kvm_write_guest_page(kvm, fn, &data, |
5211 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
5212 | sizeof(u8)); | |
10589a46 | 5213 | out: |
40dcaa9f | 5214 | srcu_read_unlock(&kvm->srcu, idx); |
1f755a82 | 5215 | return r; |
6aa8b732 AK |
5216 | } |
5217 | ||
b7ebfb05 SY |
5218 | static int init_rmode_identity_map(struct kvm *kvm) |
5219 | { | |
40bbb9d0 | 5220 | struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); |
f51770ed | 5221 | int i, idx, r = 0; |
ba049e93 | 5222 | kvm_pfn_t identity_map_pfn; |
b7ebfb05 SY |
5223 | u32 tmp; |
5224 | ||
40bbb9d0 | 5225 | /* Protect kvm_vmx->ept_identity_pagetable_done. */ |
a255d479 TC |
5226 | mutex_lock(&kvm->slots_lock); |
5227 | ||
40bbb9d0 | 5228 | if (likely(kvm_vmx->ept_identity_pagetable_done)) |
a255d479 | 5229 | goto out2; |
a255d479 | 5230 | |
40bbb9d0 SC |
5231 | if (!kvm_vmx->ept_identity_map_addr) |
5232 | kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
5233 | identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; | |
a255d479 | 5234 | |
d8a6e365 | 5235 | r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, |
40bbb9d0 | 5236 | kvm_vmx->ept_identity_map_addr, PAGE_SIZE); |
f51770ed | 5237 | if (r < 0) |
a255d479 TC |
5238 | goto out2; |
5239 | ||
40dcaa9f | 5240 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
5241 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
5242 | if (r < 0) | |
5243 | goto out; | |
5244 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
5245 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
5246 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
5247 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
5248 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
5249 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
5250 | if (r < 0) | |
5251 | goto out; | |
5252 | } | |
40bbb9d0 | 5253 | kvm_vmx->ept_identity_pagetable_done = true; |
f51770ed | 5254 | |
b7ebfb05 | 5255 | out: |
40dcaa9f | 5256 | srcu_read_unlock(&kvm->srcu, idx); |
a255d479 TC |
5257 | |
5258 | out2: | |
5259 | mutex_unlock(&kvm->slots_lock); | |
f51770ed | 5260 | return r; |
b7ebfb05 SY |
5261 | } |
5262 | ||
6aa8b732 AK |
5263 | static void seg_setup(int seg) |
5264 | { | |
772e0318 | 5265 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
3a624e29 | 5266 | unsigned int ar; |
6aa8b732 AK |
5267 | |
5268 | vmcs_write16(sf->selector, 0); | |
5269 | vmcs_writel(sf->base, 0); | |
5270 | vmcs_write32(sf->limit, 0xffff); | |
d54d07b2 GN |
5271 | ar = 0x93; |
5272 | if (seg == VCPU_SREG_CS) | |
5273 | ar |= 0x08; /* code segment */ | |
3a624e29 NK |
5274 | |
5275 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
5276 | } |
5277 | ||
f78e0e2e SY |
5278 | static int alloc_apic_access_page(struct kvm *kvm) |
5279 | { | |
4484141a | 5280 | struct page *page; |
f78e0e2e SY |
5281 | int r = 0; |
5282 | ||
79fac95e | 5283 | mutex_lock(&kvm->slots_lock); |
c24ae0dc | 5284 | if (kvm->arch.apic_access_page_done) |
f78e0e2e | 5285 | goto out; |
1d8007bd PB |
5286 | r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, |
5287 | APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); | |
f78e0e2e SY |
5288 | if (r) |
5289 | goto out; | |
72dc67a6 | 5290 | |
73a6d941 | 5291 | page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
4484141a XG |
5292 | if (is_error_page(page)) { |
5293 | r = -EFAULT; | |
5294 | goto out; | |
5295 | } | |
5296 | ||
c24ae0dc TC |
5297 | /* |
5298 | * Do not pin the page in memory, so that memory hot-unplug | |
5299 | * is able to migrate it. | |
5300 | */ | |
5301 | put_page(page); | |
5302 | kvm->arch.apic_access_page_done = true; | |
f78e0e2e | 5303 | out: |
79fac95e | 5304 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
5305 | return r; |
5306 | } | |
5307 | ||
991e7a0e | 5308 | static int allocate_vpid(void) |
2384d2b3 SY |
5309 | { |
5310 | int vpid; | |
5311 | ||
919818ab | 5312 | if (!enable_vpid) |
991e7a0e | 5313 | return 0; |
2384d2b3 SY |
5314 | spin_lock(&vmx_vpid_lock); |
5315 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
991e7a0e | 5316 | if (vpid < VMX_NR_VPIDS) |
2384d2b3 | 5317 | __set_bit(vpid, vmx_vpid_bitmap); |
991e7a0e WL |
5318 | else |
5319 | vpid = 0; | |
2384d2b3 | 5320 | spin_unlock(&vmx_vpid_lock); |
991e7a0e | 5321 | return vpid; |
2384d2b3 SY |
5322 | } |
5323 | ||
991e7a0e | 5324 | static void free_vpid(int vpid) |
cdbecfc3 | 5325 | { |
991e7a0e | 5326 | if (!enable_vpid || vpid == 0) |
cdbecfc3 LJ |
5327 | return; |
5328 | spin_lock(&vmx_vpid_lock); | |
991e7a0e | 5329 | __clear_bit(vpid, vmx_vpid_bitmap); |
cdbecfc3 LJ |
5330 | spin_unlock(&vmx_vpid_lock); |
5331 | } | |
5332 | ||
904e14fb PB |
5333 | static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, |
5334 | u32 msr, int type) | |
25c5f225 | 5335 | { |
3e7c73e9 | 5336 | int f = sizeof(unsigned long); |
25c5f225 SY |
5337 | |
5338 | if (!cpu_has_vmx_msr_bitmap()) | |
5339 | return; | |
5340 | ||
5341 | /* | |
5342 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
5343 | * have the write-low and read-high bitmap offsets the wrong way round. | |
5344 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
5345 | */ | |
25c5f225 | 5346 | if (msr <= 0x1fff) { |
8d14695f YZ |
5347 | if (type & MSR_TYPE_R) |
5348 | /* read-low */ | |
5349 | __clear_bit(msr, msr_bitmap + 0x000 / f); | |
5350 | ||
5351 | if (type & MSR_TYPE_W) | |
5352 | /* write-low */ | |
5353 | __clear_bit(msr, msr_bitmap + 0x800 / f); | |
5354 | ||
25c5f225 SY |
5355 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
5356 | msr &= 0x1fff; | |
8d14695f YZ |
5357 | if (type & MSR_TYPE_R) |
5358 | /* read-high */ | |
5359 | __clear_bit(msr, msr_bitmap + 0x400 / f); | |
5360 | ||
5361 | if (type & MSR_TYPE_W) | |
5362 | /* write-high */ | |
5363 | __clear_bit(msr, msr_bitmap + 0xc00 / f); | |
5364 | ||
5365 | } | |
5366 | } | |
5367 | ||
904e14fb PB |
5368 | static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, |
5369 | u32 msr, int type) | |
5370 | { | |
5371 | int f = sizeof(unsigned long); | |
5372 | ||
5373 | if (!cpu_has_vmx_msr_bitmap()) | |
5374 | return; | |
5375 | ||
5376 | /* | |
5377 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
5378 | * have the write-low and read-high bitmap offsets the wrong way round. | |
5379 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
5380 | */ | |
5381 | if (msr <= 0x1fff) { | |
5382 | if (type & MSR_TYPE_R) | |
5383 | /* read-low */ | |
5384 | __set_bit(msr, msr_bitmap + 0x000 / f); | |
5385 | ||
5386 | if (type & MSR_TYPE_W) | |
5387 | /* write-low */ | |
5388 | __set_bit(msr, msr_bitmap + 0x800 / f); | |
5389 | ||
5390 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
5391 | msr &= 0x1fff; | |
5392 | if (type & MSR_TYPE_R) | |
5393 | /* read-high */ | |
5394 | __set_bit(msr, msr_bitmap + 0x400 / f); | |
5395 | ||
5396 | if (type & MSR_TYPE_W) | |
5397 | /* write-high */ | |
5398 | __set_bit(msr, msr_bitmap + 0xc00 / f); | |
5399 | ||
5400 | } | |
5401 | } | |
5402 | ||
5403 | static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap, | |
5404 | u32 msr, int type, bool value) | |
5405 | { | |
5406 | if (value) | |
5407 | vmx_enable_intercept_for_msr(msr_bitmap, msr, type); | |
5408 | else | |
5409 | vmx_disable_intercept_for_msr(msr_bitmap, msr, type); | |
5410 | } | |
5411 | ||
f2b93280 WV |
5412 | /* |
5413 | * If a msr is allowed by L0, we should check whether it is allowed by L1. | |
5414 | * The corresponding bit will be cleared unless both of L0 and L1 allow it. | |
5415 | */ | |
5416 | static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1, | |
5417 | unsigned long *msr_bitmap_nested, | |
5418 | u32 msr, int type) | |
5419 | { | |
5420 | int f = sizeof(unsigned long); | |
5421 | ||
f2b93280 WV |
5422 | /* |
5423 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
5424 | * have the write-low and read-high bitmap offsets the wrong way round. | |
5425 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
5426 | */ | |
5427 | if (msr <= 0x1fff) { | |
5428 | if (type & MSR_TYPE_R && | |
5429 | !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) | |
5430 | /* read-low */ | |
5431 | __clear_bit(msr, msr_bitmap_nested + 0x000 / f); | |
5432 | ||
5433 | if (type & MSR_TYPE_W && | |
5434 | !test_bit(msr, msr_bitmap_l1 + 0x800 / f)) | |
5435 | /* write-low */ | |
5436 | __clear_bit(msr, msr_bitmap_nested + 0x800 / f); | |
5437 | ||
5438 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
5439 | msr &= 0x1fff; | |
5440 | if (type & MSR_TYPE_R && | |
5441 | !test_bit(msr, msr_bitmap_l1 + 0x400 / f)) | |
5442 | /* read-high */ | |
5443 | __clear_bit(msr, msr_bitmap_nested + 0x400 / f); | |
5444 | ||
5445 | if (type & MSR_TYPE_W && | |
5446 | !test_bit(msr, msr_bitmap_l1 + 0xc00 / f)) | |
5447 | /* write-high */ | |
5448 | __clear_bit(msr, msr_bitmap_nested + 0xc00 / f); | |
5449 | ||
5450 | } | |
5451 | } | |
5452 | ||
904e14fb | 5453 | static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) |
5897297b | 5454 | { |
904e14fb PB |
5455 | u8 mode = 0; |
5456 | ||
5457 | if (cpu_has_secondary_exec_ctrls() && | |
5458 | (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) & | |
5459 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { | |
5460 | mode |= MSR_BITMAP_MODE_X2APIC; | |
5461 | if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) | |
5462 | mode |= MSR_BITMAP_MODE_X2APIC_APICV; | |
5463 | } | |
5464 | ||
5465 | if (is_long_mode(vcpu)) | |
5466 | mode |= MSR_BITMAP_MODE_LM; | |
5467 | ||
5468 | return mode; | |
8d14695f YZ |
5469 | } |
5470 | ||
904e14fb PB |
5471 | #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4)) |
5472 | ||
5473 | static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, | |
5474 | u8 mode) | |
8d14695f | 5475 | { |
904e14fb PB |
5476 | int msr; |
5477 | ||
5478 | for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { | |
5479 | unsigned word = msr / BITS_PER_LONG; | |
5480 | msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; | |
5481 | msr_bitmap[word + (0x800 / sizeof(long))] = ~0; | |
5482 | } | |
5483 | ||
5484 | if (mode & MSR_BITMAP_MODE_X2APIC) { | |
5485 | /* | |
5486 | * TPR reads and writes can be virtualized even if virtual interrupt | |
5487 | * delivery is not in use. | |
5488 | */ | |
5489 | vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); | |
5490 | if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { | |
5491 | vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); | |
5492 | vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); | |
5493 | vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); | |
5494 | } | |
f6e90f9e | 5495 | } |
5897297b AK |
5496 | } |
5497 | ||
904e14fb PB |
5498 | static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) |
5499 | { | |
5500 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5501 | unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; | |
5502 | u8 mode = vmx_msr_bitmap_mode(vcpu); | |
5503 | u8 changed = mode ^ vmx->msr_bitmap_mode; | |
5504 | ||
5505 | if (!changed) | |
5506 | return; | |
5507 | ||
5508 | vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW, | |
5509 | !(mode & MSR_BITMAP_MODE_LM)); | |
5510 | ||
5511 | if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) | |
5512 | vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); | |
5513 | ||
5514 | vmx->msr_bitmap_mode = mode; | |
5515 | } | |
5516 | ||
b2a05fef | 5517 | static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu) |
d50ab6c1 | 5518 | { |
d62caabb | 5519 | return enable_apicv; |
d50ab6c1 PB |
5520 | } |
5521 | ||
c9f04407 DM |
5522 | static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu) |
5523 | { | |
5524 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
5525 | gfn_t gfn; | |
5526 | ||
5527 | /* | |
5528 | * Don't need to mark the APIC access page dirty; it is never | |
5529 | * written to by the CPU during APIC virtualization. | |
5530 | */ | |
5531 | ||
5532 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
5533 | gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT; | |
5534 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
5535 | } | |
5536 | ||
5537 | if (nested_cpu_has_posted_intr(vmcs12)) { | |
5538 | gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT; | |
5539 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
5540 | } | |
5541 | } | |
5542 | ||
5543 | ||
6342c50a | 5544 | static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu) |
705699a1 WV |
5545 | { |
5546 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5547 | int max_irr; | |
5548 | void *vapic_page; | |
5549 | u16 status; | |
5550 | ||
c9f04407 DM |
5551 | if (!vmx->nested.pi_desc || !vmx->nested.pi_pending) |
5552 | return; | |
705699a1 | 5553 | |
c9f04407 DM |
5554 | vmx->nested.pi_pending = false; |
5555 | if (!pi_test_and_clear_on(vmx->nested.pi_desc)) | |
5556 | return; | |
705699a1 | 5557 | |
c9f04407 DM |
5558 | max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256); |
5559 | if (max_irr != 256) { | |
705699a1 | 5560 | vapic_page = kmap(vmx->nested.virtual_apic_page); |
e7387b0e LA |
5561 | __kvm_apic_update_irr(vmx->nested.pi_desc->pir, |
5562 | vapic_page, &max_irr); | |
705699a1 WV |
5563 | kunmap(vmx->nested.virtual_apic_page); |
5564 | ||
5565 | status = vmcs_read16(GUEST_INTR_STATUS); | |
5566 | if ((u8)max_irr > ((u8)status & 0xff)) { | |
5567 | status &= ~0xff; | |
5568 | status |= (u8)max_irr; | |
5569 | vmcs_write16(GUEST_INTR_STATUS, status); | |
5570 | } | |
5571 | } | |
c9f04407 DM |
5572 | |
5573 | nested_mark_vmcs12_pages_dirty(vcpu); | |
705699a1 WV |
5574 | } |
5575 | ||
06a5524f WV |
5576 | static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, |
5577 | bool nested) | |
21bc8dc5 RK |
5578 | { |
5579 | #ifdef CONFIG_SMP | |
06a5524f WV |
5580 | int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; |
5581 | ||
21bc8dc5 | 5582 | if (vcpu->mode == IN_GUEST_MODE) { |
28b835d6 | 5583 | /* |
5753743f HZ |
5584 | * The vector of interrupt to be delivered to vcpu had |
5585 | * been set in PIR before this function. | |
5586 | * | |
5587 | * Following cases will be reached in this block, and | |
5588 | * we always send a notification event in all cases as | |
5589 | * explained below. | |
5590 | * | |
5591 | * Case 1: vcpu keeps in non-root mode. Sending a | |
5592 | * notification event posts the interrupt to vcpu. | |
5593 | * | |
5594 | * Case 2: vcpu exits to root mode and is still | |
5595 | * runnable. PIR will be synced to vIRR before the | |
5596 | * next vcpu entry. Sending a notification event in | |
5597 | * this case has no effect, as vcpu is not in root | |
5598 | * mode. | |
28b835d6 | 5599 | * |
5753743f HZ |
5600 | * Case 3: vcpu exits to root mode and is blocked. |
5601 | * vcpu_block() has already synced PIR to vIRR and | |
5602 | * never blocks vcpu if vIRR is not cleared. Therefore, | |
5603 | * a blocked vcpu here does not wait for any requested | |
5604 | * interrupts in PIR, and sending a notification event | |
5605 | * which has no effect is safe here. | |
28b835d6 | 5606 | */ |
28b835d6 | 5607 | |
06a5524f | 5608 | apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); |
21bc8dc5 RK |
5609 | return true; |
5610 | } | |
5611 | #endif | |
5612 | return false; | |
5613 | } | |
5614 | ||
705699a1 WV |
5615 | static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, |
5616 | int vector) | |
5617 | { | |
5618 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5619 | ||
5620 | if (is_guest_mode(vcpu) && | |
5621 | vector == vmx->nested.posted_intr_nv) { | |
705699a1 WV |
5622 | /* |
5623 | * If a posted intr is not recognized by hardware, | |
5624 | * we will accomplish it in the next vmentry. | |
5625 | */ | |
5626 | vmx->nested.pi_pending = true; | |
5627 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6b697711 LA |
5628 | /* the PIR and ON have been set by L1. */ |
5629 | if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) | |
5630 | kvm_vcpu_kick(vcpu); | |
705699a1 WV |
5631 | return 0; |
5632 | } | |
5633 | return -1; | |
5634 | } | |
a20ed54d YZ |
5635 | /* |
5636 | * Send interrupt to vcpu via posted interrupt way. | |
5637 | * 1. If target vcpu is running(non-root mode), send posted interrupt | |
5638 | * notification to vcpu and hardware will sync PIR to vIRR atomically. | |
5639 | * 2. If target vcpu isn't running(root mode), kick it to pick up the | |
5640 | * interrupt from PIR in next vmentry. | |
5641 | */ | |
5642 | static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) | |
5643 | { | |
5644 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5645 | int r; | |
5646 | ||
705699a1 WV |
5647 | r = vmx_deliver_nested_posted_interrupt(vcpu, vector); |
5648 | if (!r) | |
5649 | return; | |
5650 | ||
a20ed54d YZ |
5651 | if (pi_test_and_set_pir(vector, &vmx->pi_desc)) |
5652 | return; | |
5653 | ||
b95234c8 PB |
5654 | /* If a previous notification has sent the IPI, nothing to do. */ |
5655 | if (pi_test_and_set_on(&vmx->pi_desc)) | |
5656 | return; | |
5657 | ||
06a5524f | 5658 | if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) |
a20ed54d YZ |
5659 | kvm_vcpu_kick(vcpu); |
5660 | } | |
5661 | ||
a3a8ff8e NHE |
5662 | /* |
5663 | * Set up the vmcs's constant host-state fields, i.e., host-state fields that | |
5664 | * will not change in the lifetime of the guest. | |
5665 | * Note that host-state that does change is set elsewhere. E.g., host-state | |
5666 | * that is set differently for each CPU is set in vmx_vcpu_load(), not here. | |
5667 | */ | |
a547c6db | 5668 | static void vmx_set_constant_host_state(struct vcpu_vmx *vmx) |
a3a8ff8e NHE |
5669 | { |
5670 | u32 low32, high32; | |
5671 | unsigned long tmpl; | |
5672 | struct desc_ptr dt; | |
d6e41f11 | 5673 | unsigned long cr0, cr3, cr4; |
a3a8ff8e | 5674 | |
04ac88ab AL |
5675 | cr0 = read_cr0(); |
5676 | WARN_ON(cr0 & X86_CR0_TS); | |
5677 | vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ | |
d6e41f11 AL |
5678 | |
5679 | /* | |
5680 | * Save the most likely value for this task's CR3 in the VMCS. | |
5681 | * We can't use __get_current_cr3_fast() because we're not atomic. | |
5682 | */ | |
6c690ee1 | 5683 | cr3 = __read_cr3(); |
d6e41f11 | 5684 | vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ |
44889942 | 5685 | vmx->loaded_vmcs->vmcs_host_cr3 = cr3; |
a3a8ff8e | 5686 | |
d974baa3 | 5687 | /* Save the most likely value for this task's CR4 in the VMCS. */ |
1e02ce4c | 5688 | cr4 = cr4_read_shadow(); |
d974baa3 | 5689 | vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ |
44889942 | 5690 | vmx->loaded_vmcs->vmcs_host_cr4 = cr4; |
d974baa3 | 5691 | |
a3a8ff8e | 5692 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ |
b2da15ac AK |
5693 | #ifdef CONFIG_X86_64 |
5694 | /* | |
5695 | * Load null selectors, so we can avoid reloading them in | |
5696 | * __vmx_load_host_state(), in case userspace uses the null selectors | |
5697 | * too (the expected case). | |
5698 | */ | |
5699 | vmcs_write16(HOST_DS_SELECTOR, 0); | |
5700 | vmcs_write16(HOST_ES_SELECTOR, 0); | |
5701 | #else | |
a3a8ff8e NHE |
5702 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5703 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
b2da15ac | 5704 | #endif |
a3a8ff8e NHE |
5705 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5706 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
5707 | ||
87930019 | 5708 | store_idt(&dt); |
a3a8ff8e | 5709 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ |
a547c6db | 5710 | vmx->host_idt_base = dt.address; |
a3a8ff8e | 5711 | |
83287ea4 | 5712 | vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */ |
a3a8ff8e NHE |
5713 | |
5714 | rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); | |
5715 | vmcs_write32(HOST_IA32_SYSENTER_CS, low32); | |
5716 | rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); | |
5717 | vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ | |
5718 | ||
5719 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { | |
5720 | rdmsr(MSR_IA32_CR_PAT, low32, high32); | |
5721 | vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); | |
5722 | } | |
5723 | } | |
5724 | ||
bf8179a0 NHE |
5725 | static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) |
5726 | { | |
5727 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; | |
5728 | if (enable_ept) | |
5729 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
fe3ef05c NHE |
5730 | if (is_guest_mode(&vmx->vcpu)) |
5731 | vmx->vcpu.arch.cr4_guest_owned_bits &= | |
5732 | ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; | |
bf8179a0 NHE |
5733 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
5734 | } | |
5735 | ||
01e439be YZ |
5736 | static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) |
5737 | { | |
5738 | u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; | |
5739 | ||
d62caabb | 5740 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
01e439be | 5741 | pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; |
d02fcf50 PB |
5742 | |
5743 | if (!enable_vnmi) | |
5744 | pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; | |
5745 | ||
64672c95 YJ |
5746 | /* Enable the preemption timer dynamically */ |
5747 | pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
5748 | return pin_based_exec_ctrl; |
5749 | } | |
5750 | ||
d62caabb AS |
5751 | static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
5752 | { | |
5753 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5754 | ||
5755 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); | |
3ce424e4 RK |
5756 | if (cpu_has_secondary_exec_ctrls()) { |
5757 | if (kvm_vcpu_apicv_active(vcpu)) | |
5758 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
5759 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5760 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5761 | else | |
5762 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
5763 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5764 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5765 | } | |
5766 | ||
5767 | if (cpu_has_vmx_msr_bitmap()) | |
904e14fb | 5768 | vmx_update_msr_bitmap(vcpu); |
d62caabb AS |
5769 | } |
5770 | ||
bf8179a0 NHE |
5771 | static u32 vmx_exec_control(struct vcpu_vmx *vmx) |
5772 | { | |
5773 | u32 exec_control = vmcs_config.cpu_based_exec_ctrl; | |
d16c293e PB |
5774 | |
5775 | if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) | |
5776 | exec_control &= ~CPU_BASED_MOV_DR_EXITING; | |
5777 | ||
35754c98 | 5778 | if (!cpu_need_tpr_shadow(&vmx->vcpu)) { |
bf8179a0 NHE |
5779 | exec_control &= ~CPU_BASED_TPR_SHADOW; |
5780 | #ifdef CONFIG_X86_64 | |
5781 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
5782 | CPU_BASED_CR8_LOAD_EXITING; | |
5783 | #endif | |
5784 | } | |
5785 | if (!enable_ept) | |
5786 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
5787 | CPU_BASED_CR3_LOAD_EXITING | | |
5788 | CPU_BASED_INVLPG_EXITING; | |
4d5422ce WL |
5789 | if (kvm_mwait_in_guest(vmx->vcpu.kvm)) |
5790 | exec_control &= ~(CPU_BASED_MWAIT_EXITING | | |
5791 | CPU_BASED_MONITOR_EXITING); | |
caa057a2 WL |
5792 | if (kvm_hlt_in_guest(vmx->vcpu.kvm)) |
5793 | exec_control &= ~CPU_BASED_HLT_EXITING; | |
bf8179a0 NHE |
5794 | return exec_control; |
5795 | } | |
5796 | ||
45ec368c | 5797 | static bool vmx_rdrand_supported(void) |
bf8179a0 | 5798 | { |
45ec368c | 5799 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
736fdf72 | 5800 | SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5801 | } |
5802 | ||
75f4fc8d JM |
5803 | static bool vmx_rdseed_supported(void) |
5804 | { | |
5805 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
736fdf72 | 5806 | SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5807 | } |
5808 | ||
80154d77 | 5809 | static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) |
bf8179a0 | 5810 | { |
80154d77 PB |
5811 | struct kvm_vcpu *vcpu = &vmx->vcpu; |
5812 | ||
bf8179a0 | 5813 | u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; |
0367f205 | 5814 | |
80154d77 | 5815 | if (!cpu_need_virtualize_apic_accesses(vcpu)) |
bf8179a0 NHE |
5816 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
5817 | if (vmx->vpid == 0) | |
5818 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
5819 | if (!enable_ept) { | |
5820 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
5821 | enable_unrestricted_guest = 0; | |
ad756a16 MJ |
5822 | /* Enable INVPCID for non-ept guests may cause performance regression. */ |
5823 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
bf8179a0 NHE |
5824 | } |
5825 | if (!enable_unrestricted_guest) | |
5826 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
b31c114b | 5827 | if (kvm_pause_in_guest(vmx->vcpu.kvm)) |
bf8179a0 | 5828 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; |
80154d77 | 5829 | if (!kvm_vcpu_apicv_active(vcpu)) |
c7c9c56c YZ |
5830 | exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | |
5831 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
8d14695f | 5832 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; |
0367f205 PB |
5833 | |
5834 | /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, | |
5835 | * in vmx_set_cr4. */ | |
5836 | exec_control &= ~SECONDARY_EXEC_DESC; | |
5837 | ||
abc4fc58 AG |
5838 | /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD |
5839 | (handle_vmptrld). | |
5840 | We can NOT enable shadow_vmcs here because we don't have yet | |
5841 | a current VMCS12 | |
5842 | */ | |
5843 | exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
a3eaa864 KH |
5844 | |
5845 | if (!enable_pml) | |
5846 | exec_control &= ~SECONDARY_EXEC_ENABLE_PML; | |
843e4330 | 5847 | |
3db13480 PB |
5848 | if (vmx_xsaves_supported()) { |
5849 | /* Exposing XSAVES only when XSAVE is exposed */ | |
5850 | bool xsaves_enabled = | |
5851 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && | |
5852 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); | |
5853 | ||
5854 | if (!xsaves_enabled) | |
5855 | exec_control &= ~SECONDARY_EXEC_XSAVES; | |
5856 | ||
5857 | if (nested) { | |
5858 | if (xsaves_enabled) | |
6677f3da | 5859 | vmx->nested.msrs.secondary_ctls_high |= |
3db13480 PB |
5860 | SECONDARY_EXEC_XSAVES; |
5861 | else | |
6677f3da | 5862 | vmx->nested.msrs.secondary_ctls_high &= |
3db13480 PB |
5863 | ~SECONDARY_EXEC_XSAVES; |
5864 | } | |
5865 | } | |
5866 | ||
80154d77 PB |
5867 | if (vmx_rdtscp_supported()) { |
5868 | bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); | |
5869 | if (!rdtscp_enabled) | |
5870 | exec_control &= ~SECONDARY_EXEC_RDTSCP; | |
5871 | ||
5872 | if (nested) { | |
5873 | if (rdtscp_enabled) | |
6677f3da | 5874 | vmx->nested.msrs.secondary_ctls_high |= |
80154d77 PB |
5875 | SECONDARY_EXEC_RDTSCP; |
5876 | else | |
6677f3da | 5877 | vmx->nested.msrs.secondary_ctls_high &= |
80154d77 PB |
5878 | ~SECONDARY_EXEC_RDTSCP; |
5879 | } | |
5880 | } | |
5881 | ||
5882 | if (vmx_invpcid_supported()) { | |
5883 | /* Exposing INVPCID only when PCID is exposed */ | |
5884 | bool invpcid_enabled = | |
5885 | guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && | |
5886 | guest_cpuid_has(vcpu, X86_FEATURE_PCID); | |
5887 | ||
5888 | if (!invpcid_enabled) { | |
5889 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
5890 | guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); | |
5891 | } | |
5892 | ||
5893 | if (nested) { | |
5894 | if (invpcid_enabled) | |
6677f3da | 5895 | vmx->nested.msrs.secondary_ctls_high |= |
80154d77 PB |
5896 | SECONDARY_EXEC_ENABLE_INVPCID; |
5897 | else | |
6677f3da | 5898 | vmx->nested.msrs.secondary_ctls_high &= |
80154d77 PB |
5899 | ~SECONDARY_EXEC_ENABLE_INVPCID; |
5900 | } | |
5901 | } | |
5902 | ||
45ec368c JM |
5903 | if (vmx_rdrand_supported()) { |
5904 | bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); | |
5905 | if (rdrand_enabled) | |
736fdf72 | 5906 | exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5907 | |
5908 | if (nested) { | |
5909 | if (rdrand_enabled) | |
6677f3da | 5910 | vmx->nested.msrs.secondary_ctls_high |= |
736fdf72 | 5911 | SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c | 5912 | else |
6677f3da | 5913 | vmx->nested.msrs.secondary_ctls_high &= |
736fdf72 | 5914 | ~SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5915 | } |
5916 | } | |
5917 | ||
75f4fc8d JM |
5918 | if (vmx_rdseed_supported()) { |
5919 | bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); | |
5920 | if (rdseed_enabled) | |
736fdf72 | 5921 | exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5922 | |
5923 | if (nested) { | |
5924 | if (rdseed_enabled) | |
6677f3da | 5925 | vmx->nested.msrs.secondary_ctls_high |= |
736fdf72 | 5926 | SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d | 5927 | else |
6677f3da | 5928 | vmx->nested.msrs.secondary_ctls_high &= |
736fdf72 | 5929 | ~SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5930 | } |
5931 | } | |
5932 | ||
80154d77 | 5933 | vmx->secondary_exec_control = exec_control; |
bf8179a0 NHE |
5934 | } |
5935 | ||
ce88decf XG |
5936 | static void ept_set_mmio_spte_mask(void) |
5937 | { | |
5938 | /* | |
5939 | * EPT Misconfigurations can be generated if the value of bits 2:0 | |
5940 | * of an EPT paging-structure entry is 110b (write/execute). | |
ce88decf | 5941 | */ |
dcdca5fe PF |
5942 | kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, |
5943 | VMX_EPT_MISCONFIG_WX_VALUE); | |
ce88decf XG |
5944 | } |
5945 | ||
f53cd63c | 5946 | #define VMX_XSS_EXIT_BITMAP 0 |
6aa8b732 AK |
5947 | /* |
5948 | * Sets up the vmcs for emulated real mode. | |
5949 | */ | |
12d79917 | 5950 | static void vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 5951 | { |
2e4ce7f5 | 5952 | #ifdef CONFIG_X86_64 |
6aa8b732 | 5953 | unsigned long a; |
2e4ce7f5 | 5954 | #endif |
6aa8b732 | 5955 | int i; |
6aa8b732 | 5956 | |
4607c2d7 AG |
5957 | if (enable_shadow_vmcs) { |
5958 | vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); | |
5959 | vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); | |
5960 | } | |
25c5f225 | 5961 | if (cpu_has_vmx_msr_bitmap()) |
904e14fb | 5962 | vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); |
25c5f225 | 5963 | |
6aa8b732 AK |
5964 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
5965 | ||
6aa8b732 | 5966 | /* Control */ |
01e439be | 5967 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); |
64672c95 | 5968 | vmx->hv_deadline_tsc = -1; |
6e5d865c | 5969 | |
bf8179a0 | 5970 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx)); |
6aa8b732 | 5971 | |
dfa169bb | 5972 | if (cpu_has_secondary_exec_ctrls()) { |
80154d77 | 5973 | vmx_compute_secondary_exec_control(vmx); |
bf8179a0 | 5974 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, |
80154d77 | 5975 | vmx->secondary_exec_control); |
dfa169bb | 5976 | } |
f78e0e2e | 5977 | |
d62caabb | 5978 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) { |
c7c9c56c YZ |
5979 | vmcs_write64(EOI_EXIT_BITMAP0, 0); |
5980 | vmcs_write64(EOI_EXIT_BITMAP1, 0); | |
5981 | vmcs_write64(EOI_EXIT_BITMAP2, 0); | |
5982 | vmcs_write64(EOI_EXIT_BITMAP3, 0); | |
5983 | ||
5984 | vmcs_write16(GUEST_INTR_STATUS, 0); | |
01e439be | 5985 | |
0bcf261c | 5986 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
01e439be | 5987 | vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); |
c7c9c56c YZ |
5988 | } |
5989 | ||
b31c114b | 5990 | if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { |
4b8d54f9 | 5991 | vmcs_write32(PLE_GAP, ple_gap); |
a7653ecd RK |
5992 | vmx->ple_window = ple_window; |
5993 | vmx->ple_window_dirty = true; | |
4b8d54f9 ZE |
5994 | } |
5995 | ||
c3707958 XG |
5996 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
5997 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
6aa8b732 AK |
5998 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
5999 | ||
9581d442 AK |
6000 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
6001 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
a547c6db | 6002 | vmx_set_constant_host_state(vmx); |
05b3e0c2 | 6003 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
6004 | rdmsrl(MSR_FS_BASE, a); |
6005 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
6006 | rdmsrl(MSR_GS_BASE, a); | |
6007 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
6008 | #else | |
6009 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
6010 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
6011 | #endif | |
6012 | ||
2a499e49 BD |
6013 | if (cpu_has_vmx_vmfunc()) |
6014 | vmcs_write64(VM_FUNCTION_CONTROL, 0); | |
6015 | ||
2cc51560 ED |
6016 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
6017 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
61d2ef2c | 6018 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); |
2cc51560 | 6019 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
61d2ef2c | 6020 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); |
6aa8b732 | 6021 | |
74545705 RK |
6022 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) |
6023 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); | |
468d472f | 6024 | |
03916db9 | 6025 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { |
6aa8b732 AK |
6026 | u32 index = vmx_msr_index[i]; |
6027 | u32 data_low, data_high; | |
a2fa3e9f | 6028 | int j = vmx->nmsrs; |
6aa8b732 AK |
6029 | |
6030 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
6031 | continue; | |
432bd6cb AK |
6032 | if (wrmsr_safe(index, data_low, data_high) < 0) |
6033 | continue; | |
26bb0981 AK |
6034 | vmx->guest_msrs[j].index = i; |
6035 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 6036 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 6037 | ++vmx->nmsrs; |
6aa8b732 | 6038 | } |
6aa8b732 | 6039 | |
28c1c9fa KA |
6040 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
6041 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities); | |
2961e876 GN |
6042 | |
6043 | vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl); | |
6aa8b732 AK |
6044 | |
6045 | /* 22.2.1, 20.8.1 */ | |
2961e876 | 6046 | vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl); |
1c3d14fe | 6047 | |
bd7e5b08 PB |
6048 | vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; |
6049 | vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); | |
6050 | ||
bf8179a0 | 6051 | set_cr4_guest_host_mask(vmx); |
e00c8cf2 | 6052 | |
f53cd63c WL |
6053 | if (vmx_xsaves_supported()) |
6054 | vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); | |
6055 | ||
4e59516a PF |
6056 | if (enable_pml) { |
6057 | ASSERT(vmx->pml_pg); | |
6058 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
6059 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
6060 | } | |
e00c8cf2 AK |
6061 | } |
6062 | ||
d28bc9dd | 6063 | static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e00c8cf2 AK |
6064 | { |
6065 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
58cb628d | 6066 | struct msr_data apic_base_msr; |
d28bc9dd | 6067 | u64 cr0; |
e00c8cf2 | 6068 | |
7ffd92c5 | 6069 | vmx->rmode.vm86_active = 0; |
d28b387f | 6070 | vmx->spec_ctrl = 0; |
e00c8cf2 | 6071 | |
518e7b94 | 6072 | vcpu->arch.microcode_version = 0x100000000ULL; |
ad312c7c | 6073 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
d28bc9dd NA |
6074 | kvm_set_cr8(vcpu, 0); |
6075 | ||
6076 | if (!init_event) { | |
6077 | apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | | |
6078 | MSR_IA32_APICBASE_ENABLE; | |
6079 | if (kvm_vcpu_is_reset_bsp(vcpu)) | |
6080 | apic_base_msr.data |= MSR_IA32_APICBASE_BSP; | |
6081 | apic_base_msr.host_initiated = true; | |
6082 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
6083 | } | |
e00c8cf2 | 6084 | |
2fb92db1 AK |
6085 | vmx_segment_cache_clear(vmx); |
6086 | ||
5706be0d | 6087 | seg_setup(VCPU_SREG_CS); |
66450a21 | 6088 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
f3531054 | 6089 | vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); |
e00c8cf2 AK |
6090 | |
6091 | seg_setup(VCPU_SREG_DS); | |
6092 | seg_setup(VCPU_SREG_ES); | |
6093 | seg_setup(VCPU_SREG_FS); | |
6094 | seg_setup(VCPU_SREG_GS); | |
6095 | seg_setup(VCPU_SREG_SS); | |
6096 | ||
6097 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
6098 | vmcs_writel(GUEST_TR_BASE, 0); | |
6099 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
6100 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
6101 | ||
6102 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
6103 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
6104 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
6105 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
6106 | ||
d28bc9dd NA |
6107 | if (!init_event) { |
6108 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
6109 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
6110 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
6111 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
6112 | } | |
e00c8cf2 | 6113 | |
c37c2873 | 6114 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); |
66450a21 | 6115 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 6116 | |
e00c8cf2 AK |
6117 | vmcs_writel(GUEST_GDTR_BASE, 0); |
6118 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
6119 | ||
6120 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
6121 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
6122 | ||
443381a8 | 6123 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 | 6124 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
f3531054 | 6125 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); |
a554d207 WL |
6126 | if (kvm_mpx_supported()) |
6127 | vmcs_write64(GUEST_BNDCFGS, 0); | |
e00c8cf2 | 6128 | |
e00c8cf2 AK |
6129 | setup_msrs(vmx); |
6130 | ||
6aa8b732 AK |
6131 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
6132 | ||
d28bc9dd | 6133 | if (cpu_has_vmx_tpr_shadow() && !init_event) { |
f78e0e2e | 6134 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); |
35754c98 | 6135 | if (cpu_need_tpr_shadow(vcpu)) |
f78e0e2e | 6136 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, |
d28bc9dd | 6137 | __pa(vcpu->arch.apic->regs)); |
f78e0e2e SY |
6138 | vmcs_write32(TPR_THRESHOLD, 0); |
6139 | } | |
6140 | ||
a73896cb | 6141 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
6aa8b732 | 6142 | |
2384d2b3 SY |
6143 | if (vmx->vpid != 0) |
6144 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
6145 | ||
d28bc9dd | 6146 | cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
d28bc9dd | 6147 | vmx->vcpu.arch.cr0 = cr0; |
f2463247 | 6148 | vmx_set_cr0(vcpu, cr0); /* enter rmode */ |
d28bc9dd | 6149 | vmx_set_cr4(vcpu, 0); |
5690891b | 6150 | vmx_set_efer(vcpu, 0); |
bd7e5b08 | 6151 | |
d28bc9dd | 6152 | update_exception_bitmap(vcpu); |
6aa8b732 | 6153 | |
dd5f5341 | 6154 | vpid_sync_context(vmx->vpid); |
caa057a2 WL |
6155 | if (init_event) |
6156 | vmx_clear_hlt(vcpu); | |
6aa8b732 AK |
6157 | } |
6158 | ||
b6f1250e NHE |
6159 | /* |
6160 | * In nested virtualization, check if L1 asked to exit on external interrupts. | |
6161 | * For most existing hypervisors, this will always return true. | |
6162 | */ | |
6163 | static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) | |
6164 | { | |
6165 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
6166 | PIN_BASED_EXT_INTR_MASK; | |
6167 | } | |
6168 | ||
77b0f5d6 BD |
6169 | /* |
6170 | * In nested virtualization, check if L1 has set | |
6171 | * VM_EXIT_ACK_INTR_ON_EXIT | |
6172 | */ | |
6173 | static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) | |
6174 | { | |
6175 | return get_vmcs12(vcpu)->vm_exit_controls & | |
6176 | VM_EXIT_ACK_INTR_ON_EXIT; | |
6177 | } | |
6178 | ||
ea8ceb83 JK |
6179 | static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) |
6180 | { | |
0c7f650e | 6181 | return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu)); |
ea8ceb83 JK |
6182 | } |
6183 | ||
c9a7953f | 6184 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 6185 | { |
47c0152e PB |
6186 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
6187 | CPU_BASED_VIRTUAL_INTR_PENDING); | |
3b86cd99 JK |
6188 | } |
6189 | ||
c9a7953f | 6190 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 6191 | { |
d02fcf50 | 6192 | if (!enable_vnmi || |
8a1b4392 | 6193 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { |
c9a7953f JK |
6194 | enable_irq_window(vcpu); |
6195 | return; | |
6196 | } | |
3b86cd99 | 6197 | |
47c0152e PB |
6198 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
6199 | CPU_BASED_VIRTUAL_NMI_PENDING); | |
3b86cd99 JK |
6200 | } |
6201 | ||
66fd3f7f | 6202 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 6203 | { |
9c8cba37 | 6204 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
6205 | uint32_t intr; |
6206 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 6207 | |
229456fc | 6208 | trace_kvm_inj_virq(irq); |
2714d1d3 | 6209 | |
fa89a817 | 6210 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 6211 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
6212 | int inc_eip = 0; |
6213 | if (vcpu->arch.interrupt.soft) | |
6214 | inc_eip = vcpu->arch.event_exit_inst_len; | |
6215 | if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) | |
a92601bb | 6216 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
85f455f7 ED |
6217 | return; |
6218 | } | |
66fd3f7f GN |
6219 | intr = irq | INTR_INFO_VALID_MASK; |
6220 | if (vcpu->arch.interrupt.soft) { | |
6221 | intr |= INTR_TYPE_SOFT_INTR; | |
6222 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
6223 | vmx->vcpu.arch.event_exit_inst_len); | |
6224 | } else | |
6225 | intr |= INTR_TYPE_EXT_INTR; | |
6226 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
caa057a2 WL |
6227 | |
6228 | vmx_clear_hlt(vcpu); | |
85f455f7 ED |
6229 | } |
6230 | ||
f08864b4 SY |
6231 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
6232 | { | |
66a5a347 JK |
6233 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6234 | ||
d02fcf50 | 6235 | if (!enable_vnmi) { |
8a1b4392 PB |
6236 | /* |
6237 | * Tracking the NMI-blocked state in software is built upon | |
6238 | * finding the next open IRQ window. This, in turn, depends on | |
6239 | * well-behaving guests: They have to keep IRQs disabled at | |
6240 | * least as long as the NMI handler runs. Otherwise we may | |
6241 | * cause NMI nesting, maybe breaking the guest. But as this is | |
6242 | * highly unlikely, we can live with the residual risk. | |
6243 | */ | |
6244 | vmx->loaded_vmcs->soft_vnmi_blocked = 1; | |
6245 | vmx->loaded_vmcs->vnmi_blocked_time = 0; | |
6246 | } | |
6247 | ||
4c4a6f79 PB |
6248 | ++vcpu->stat.nmi_injections; |
6249 | vmx->loaded_vmcs->nmi_known_unmasked = false; | |
3b86cd99 | 6250 | |
7ffd92c5 | 6251 | if (vmx->rmode.vm86_active) { |
71f9833b | 6252 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) |
a92601bb | 6253 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
66a5a347 JK |
6254 | return; |
6255 | } | |
c5a6d5f7 | 6256 | |
f08864b4 SY |
6257 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
6258 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
caa057a2 WL |
6259 | |
6260 | vmx_clear_hlt(vcpu); | |
f08864b4 SY |
6261 | } |
6262 | ||
3cfc3092 JK |
6263 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
6264 | { | |
4c4a6f79 PB |
6265 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6266 | bool masked; | |
6267 | ||
d02fcf50 | 6268 | if (!enable_vnmi) |
8a1b4392 | 6269 | return vmx->loaded_vmcs->soft_vnmi_blocked; |
4c4a6f79 | 6270 | if (vmx->loaded_vmcs->nmi_known_unmasked) |
9d58b931 | 6271 | return false; |
4c4a6f79 PB |
6272 | masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
6273 | vmx->loaded_vmcs->nmi_known_unmasked = !masked; | |
6274 | return masked; | |
3cfc3092 JK |
6275 | } |
6276 | ||
6277 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
6278 | { | |
6279 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6280 | ||
d02fcf50 | 6281 | if (!enable_vnmi) { |
8a1b4392 PB |
6282 | if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { |
6283 | vmx->loaded_vmcs->soft_vnmi_blocked = masked; | |
6284 | vmx->loaded_vmcs->vnmi_blocked_time = 0; | |
6285 | } | |
6286 | } else { | |
6287 | vmx->loaded_vmcs->nmi_known_unmasked = !masked; | |
6288 | if (masked) | |
6289 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
6290 | GUEST_INTR_STATE_NMI); | |
6291 | else | |
6292 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
6293 | GUEST_INTR_STATE_NMI); | |
6294 | } | |
3cfc3092 JK |
6295 | } |
6296 | ||
2505dc9f JK |
6297 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
6298 | { | |
b6b8a145 JK |
6299 | if (to_vmx(vcpu)->nested.nested_run_pending) |
6300 | return 0; | |
ea8ceb83 | 6301 | |
d02fcf50 | 6302 | if (!enable_vnmi && |
8a1b4392 PB |
6303 | to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) |
6304 | return 0; | |
6305 | ||
2505dc9f JK |
6306 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
6307 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | |
6308 | | GUEST_INTR_STATE_NMI)); | |
6309 | } | |
6310 | ||
78646121 GN |
6311 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
6312 | { | |
b6b8a145 JK |
6313 | return (!to_vmx(vcpu)->nested.nested_run_pending && |
6314 | vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
c4282df9 GN |
6315 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
6316 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
6317 | } |
6318 | ||
cbc94022 IE |
6319 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
6320 | { | |
6321 | int ret; | |
cbc94022 | 6322 | |
f7eaeb0a SC |
6323 | if (enable_unrestricted_guest) |
6324 | return 0; | |
6325 | ||
1d8007bd PB |
6326 | ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, |
6327 | PAGE_SIZE * 3); | |
cbc94022 IE |
6328 | if (ret) |
6329 | return ret; | |
40bbb9d0 | 6330 | to_kvm_vmx(kvm)->tss_addr = addr; |
1f755a82 | 6331 | return init_rmode_tss(kvm); |
cbc94022 IE |
6332 | } |
6333 | ||
2ac52ab8 SC |
6334 | static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) |
6335 | { | |
40bbb9d0 | 6336 | to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; |
2ac52ab8 SC |
6337 | return 0; |
6338 | } | |
6339 | ||
0ca1b4f4 | 6340 | static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) |
6aa8b732 | 6341 | { |
77ab6db0 | 6342 | switch (vec) { |
77ab6db0 | 6343 | case BP_VECTOR: |
c573cd22 JK |
6344 | /* |
6345 | * Update instruction length as we may reinject the exception | |
6346 | * from user space while in guest debugging mode. | |
6347 | */ | |
6348 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
6349 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 | 6350 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
0ca1b4f4 GN |
6351 | return false; |
6352 | /* fall through */ | |
6353 | case DB_VECTOR: | |
6354 | if (vcpu->guest_debug & | |
6355 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
6356 | return false; | |
d0bfb940 JK |
6357 | /* fall through */ |
6358 | case DE_VECTOR: | |
77ab6db0 JK |
6359 | case OF_VECTOR: |
6360 | case BR_VECTOR: | |
6361 | case UD_VECTOR: | |
6362 | case DF_VECTOR: | |
6363 | case SS_VECTOR: | |
6364 | case GP_VECTOR: | |
6365 | case MF_VECTOR: | |
0ca1b4f4 GN |
6366 | return true; |
6367 | break; | |
77ab6db0 | 6368 | } |
0ca1b4f4 GN |
6369 | return false; |
6370 | } | |
6371 | ||
6372 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
6373 | int vec, u32 err_code) | |
6374 | { | |
6375 | /* | |
6376 | * Instruction with address size override prefix opcode 0x67 | |
6377 | * Cause the #SS fault with 0 error code in VM86 mode. | |
6378 | */ | |
6379 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { | |
6380 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) { | |
6381 | if (vcpu->arch.halt_request) { | |
6382 | vcpu->arch.halt_request = 0; | |
5cb56059 | 6383 | return kvm_vcpu_halt(vcpu); |
0ca1b4f4 GN |
6384 | } |
6385 | return 1; | |
6386 | } | |
6387 | return 0; | |
6388 | } | |
6389 | ||
6390 | /* | |
6391 | * Forward all other exceptions that are valid in real mode. | |
6392 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
6393 | * the required debugging infrastructure rework. | |
6394 | */ | |
6395 | kvm_queue_exception(vcpu, vec); | |
6396 | return 1; | |
6aa8b732 AK |
6397 | } |
6398 | ||
a0861c02 AK |
6399 | /* |
6400 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
6401 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
6402 | * We pass a fake environment to the machine check handler because we want | |
6403 | * the guest to be always treated like user space, no matter what context | |
6404 | * it used internally. | |
6405 | */ | |
6406 | static void kvm_machine_check(void) | |
6407 | { | |
6408 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
6409 | struct pt_regs regs = { | |
6410 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
6411 | .flags = X86_EFLAGS_IF, | |
6412 | }; | |
6413 | ||
6414 | do_machine_check(®s, 0); | |
6415 | #endif | |
6416 | } | |
6417 | ||
851ba692 | 6418 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
6419 | { |
6420 | /* already handled by vcpu_run */ | |
6421 | return 1; | |
6422 | } | |
6423 | ||
851ba692 | 6424 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 6425 | { |
1155f76a | 6426 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 6427 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 6428 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 6429 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
6430 | u32 vect_info; |
6431 | enum emulation_result er; | |
6432 | ||
1155f76a | 6433 | vect_info = vmx->idt_vectoring_info; |
88786475 | 6434 | intr_info = vmx->exit_intr_info; |
6aa8b732 | 6435 | |
a0861c02 | 6436 | if (is_machine_check(intr_info)) |
851ba692 | 6437 | return handle_machine_check(vcpu); |
a0861c02 | 6438 | |
ef85b673 | 6439 | if (is_nmi(intr_info)) |
1b6269db | 6440 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc | 6441 | |
082d06ed WL |
6442 | if (is_invalid_opcode(intr_info)) |
6443 | return handle_ud(vcpu); | |
7aa81cc0 | 6444 | |
6aa8b732 | 6445 | error_code = 0; |
2e11384c | 6446 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 | 6447 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
bf4ca23e | 6448 | |
9e869480 LA |
6449 | if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { |
6450 | WARN_ON_ONCE(!enable_vmware_backdoor); | |
6451 | er = emulate_instruction(vcpu, | |
6452 | EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL); | |
6453 | if (er == EMULATE_USER_EXIT) | |
6454 | return 0; | |
6455 | else if (er != EMULATE_DONE) | |
6456 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
6457 | return 1; | |
6458 | } | |
6459 | ||
bf4ca23e XG |
6460 | /* |
6461 | * The #PF with PFEC.RSVD = 1 indicates the guest is accessing | |
6462 | * MMIO, it is better to report an internal error. | |
6463 | * See the comments in vmx_handle_exit. | |
6464 | */ | |
6465 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
6466 | !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { | |
6467 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6468 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
80f0e95d | 6469 | vcpu->run->internal.ndata = 3; |
bf4ca23e XG |
6470 | vcpu->run->internal.data[0] = vect_info; |
6471 | vcpu->run->internal.data[1] = intr_info; | |
80f0e95d | 6472 | vcpu->run->internal.data[2] = error_code; |
bf4ca23e XG |
6473 | return 0; |
6474 | } | |
6475 | ||
6aa8b732 AK |
6476 | if (is_page_fault(intr_info)) { |
6477 | cr2 = vmcs_readl(EXIT_QUALIFICATION); | |
1261bfa3 WL |
6478 | /* EPT won't cause page fault directly */ |
6479 | WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); | |
d0006530 | 6480 | return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); |
6aa8b732 AK |
6481 | } |
6482 | ||
d0bfb940 | 6483 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
0ca1b4f4 GN |
6484 | |
6485 | if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) | |
6486 | return handle_rmode_exception(vcpu, ex_no, error_code); | |
6487 | ||
42dbaa5a | 6488 | switch (ex_no) { |
54a20552 EN |
6489 | case AC_VECTOR: |
6490 | kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); | |
6491 | return 1; | |
42dbaa5a JK |
6492 | case DB_VECTOR: |
6493 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
6494 | if (!(vcpu->guest_debug & | |
6495 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
8246bf52 | 6496 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 6497 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
32d43cd3 | 6498 | if (is_icebp(intr_info)) |
fd2a445a HD |
6499 | skip_emulated_instruction(vcpu); |
6500 | ||
42dbaa5a JK |
6501 | kvm_queue_exception(vcpu, DB_VECTOR); |
6502 | return 1; | |
6503 | } | |
6504 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
6505 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
6506 | /* fall through */ | |
6507 | case BP_VECTOR: | |
c573cd22 JK |
6508 | /* |
6509 | * Update instruction length as we may reinject #BP from | |
6510 | * user space while in guest debugging mode. Reading it for | |
6511 | * #DB as well causes no harm, it is not used in that case. | |
6512 | */ | |
6513 | vmx->vcpu.arch.event_exit_inst_len = | |
6514 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 6515 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 6516 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
6517 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
6518 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
6519 | break; |
6520 | default: | |
d0bfb940 JK |
6521 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
6522 | kvm_run->ex.exception = ex_no; | |
6523 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 6524 | break; |
6aa8b732 | 6525 | } |
6aa8b732 AK |
6526 | return 0; |
6527 | } | |
6528 | ||
851ba692 | 6529 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 6530 | { |
1165f5fe | 6531 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
6532 | return 1; |
6533 | } | |
6534 | ||
851ba692 | 6535 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 6536 | { |
851ba692 | 6537 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 6538 | vcpu->mmio_needed = 0; |
988ad74f AK |
6539 | return 0; |
6540 | } | |
6aa8b732 | 6541 | |
851ba692 | 6542 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 6543 | { |
bfdaab09 | 6544 | unsigned long exit_qualification; |
dca7f128 | 6545 | int size, in, string; |
039576c0 | 6546 | unsigned port; |
6aa8b732 | 6547 | |
bfdaab09 | 6548 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 6549 | string = (exit_qualification & 16) != 0; |
e70669ab | 6550 | |
cf8f70bf | 6551 | ++vcpu->stat.io_exits; |
e70669ab | 6552 | |
432baf60 | 6553 | if (string) |
51d8b661 | 6554 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 6555 | |
cf8f70bf GN |
6556 | port = exit_qualification >> 16; |
6557 | size = (exit_qualification & 7) + 1; | |
432baf60 | 6558 | in = (exit_qualification & 8) != 0; |
cf8f70bf | 6559 | |
dca7f128 | 6560 | return kvm_fast_pio(vcpu, size, port, in); |
6aa8b732 AK |
6561 | } |
6562 | ||
102d8325 IM |
6563 | static void |
6564 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
6565 | { | |
6566 | /* | |
6567 | * Patch in the VMCALL instruction: | |
6568 | */ | |
6569 | hypercall[0] = 0x0f; | |
6570 | hypercall[1] = 0x01; | |
6571 | hypercall[2] = 0xc1; | |
102d8325 IM |
6572 | } |
6573 | ||
0fa06071 | 6574 | /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ |
eeadf9e7 NHE |
6575 | static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) |
6576 | { | |
eeadf9e7 | 6577 | if (is_guest_mode(vcpu)) { |
1a0d74e6 JK |
6578 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
6579 | unsigned long orig_val = val; | |
6580 | ||
eeadf9e7 NHE |
6581 | /* |
6582 | * We get here when L2 changed cr0 in a way that did not change | |
6583 | * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), | |
1a0d74e6 JK |
6584 | * but did change L0 shadowed bits. So we first calculate the |
6585 | * effective cr0 value that L1 would like to write into the | |
6586 | * hardware. It consists of the L2-owned bits from the new | |
6587 | * value combined with the L1-owned bits from L1's guest_cr0. | |
eeadf9e7 | 6588 | */ |
1a0d74e6 JK |
6589 | val = (val & ~vmcs12->cr0_guest_host_mask) | |
6590 | (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); | |
6591 | ||
3899152c | 6592 | if (!nested_guest_cr0_valid(vcpu, val)) |
eeadf9e7 | 6593 | return 1; |
1a0d74e6 JK |
6594 | |
6595 | if (kvm_set_cr0(vcpu, val)) | |
6596 | return 1; | |
6597 | vmcs_writel(CR0_READ_SHADOW, orig_val); | |
eeadf9e7 | 6598 | return 0; |
1a0d74e6 JK |
6599 | } else { |
6600 | if (to_vmx(vcpu)->nested.vmxon && | |
3899152c | 6601 | !nested_host_cr0_valid(vcpu, val)) |
1a0d74e6 | 6602 | return 1; |
3899152c | 6603 | |
eeadf9e7 | 6604 | return kvm_set_cr0(vcpu, val); |
1a0d74e6 | 6605 | } |
eeadf9e7 NHE |
6606 | } |
6607 | ||
6608 | static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) | |
6609 | { | |
6610 | if (is_guest_mode(vcpu)) { | |
1a0d74e6 JK |
6611 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
6612 | unsigned long orig_val = val; | |
6613 | ||
6614 | /* analogously to handle_set_cr0 */ | |
6615 | val = (val & ~vmcs12->cr4_guest_host_mask) | | |
6616 | (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); | |
6617 | if (kvm_set_cr4(vcpu, val)) | |
eeadf9e7 | 6618 | return 1; |
1a0d74e6 | 6619 | vmcs_writel(CR4_READ_SHADOW, orig_val); |
eeadf9e7 NHE |
6620 | return 0; |
6621 | } else | |
6622 | return kvm_set_cr4(vcpu, val); | |
6623 | } | |
6624 | ||
0367f205 PB |
6625 | static int handle_desc(struct kvm_vcpu *vcpu) |
6626 | { | |
6627 | WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); | |
6628 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; | |
6629 | } | |
6630 | ||
851ba692 | 6631 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6632 | { |
229456fc | 6633 | unsigned long exit_qualification, val; |
6aa8b732 AK |
6634 | int cr; |
6635 | int reg; | |
49a9b07e | 6636 | int err; |
6affcbed | 6637 | int ret; |
6aa8b732 | 6638 | |
bfdaab09 | 6639 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
6640 | cr = exit_qualification & 15; |
6641 | reg = (exit_qualification >> 8) & 15; | |
6642 | switch ((exit_qualification >> 4) & 3) { | |
6643 | case 0: /* mov to cr */ | |
1e32c079 | 6644 | val = kvm_register_readl(vcpu, reg); |
229456fc | 6645 | trace_kvm_cr_write(cr, val); |
6aa8b732 AK |
6646 | switch (cr) { |
6647 | case 0: | |
eeadf9e7 | 6648 | err = handle_set_cr0(vcpu, val); |
6affcbed | 6649 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 6650 | case 3: |
e1de91cc | 6651 | WARN_ON_ONCE(enable_unrestricted_guest); |
2390218b | 6652 | err = kvm_set_cr3(vcpu, val); |
6affcbed | 6653 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 6654 | case 4: |
eeadf9e7 | 6655 | err = handle_set_cr4(vcpu, val); |
6affcbed | 6656 | return kvm_complete_insn_gp(vcpu, err); |
0a5fff19 GN |
6657 | case 8: { |
6658 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
1e32c079 | 6659 | u8 cr8 = (u8)val; |
eea1cff9 | 6660 | err = kvm_set_cr8(vcpu, cr8); |
6affcbed | 6661 | ret = kvm_complete_insn_gp(vcpu, err); |
35754c98 | 6662 | if (lapic_in_kernel(vcpu)) |
6affcbed | 6663 | return ret; |
0a5fff19 | 6664 | if (cr8_prev <= cr8) |
6affcbed KH |
6665 | return ret; |
6666 | /* | |
6667 | * TODO: we might be squashing a | |
6668 | * KVM_GUESTDBG_SINGLESTEP-triggered | |
6669 | * KVM_EXIT_DEBUG here. | |
6670 | */ | |
851ba692 | 6671 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
6672 | return 0; |
6673 | } | |
4b8073e4 | 6674 | } |
6aa8b732 | 6675 | break; |
25c4c276 | 6676 | case 2: /* clts */ |
bd7e5b08 PB |
6677 | WARN_ONCE(1, "Guest should always own CR0.TS"); |
6678 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); | |
4d4ec087 | 6679 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
6affcbed | 6680 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6681 | case 1: /*mov from cr*/ |
6682 | switch (cr) { | |
6683 | case 3: | |
e1de91cc | 6684 | WARN_ON_ONCE(enable_unrestricted_guest); |
9f8fe504 AK |
6685 | val = kvm_read_cr3(vcpu); |
6686 | kvm_register_write(vcpu, reg, val); | |
6687 | trace_kvm_cr_read(cr, val); | |
6affcbed | 6688 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 | 6689 | case 8: |
229456fc MT |
6690 | val = kvm_get_cr8(vcpu); |
6691 | kvm_register_write(vcpu, reg, val); | |
6692 | trace_kvm_cr_read(cr, val); | |
6affcbed | 6693 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6694 | } |
6695 | break; | |
6696 | case 3: /* lmsw */ | |
a1f83a74 | 6697 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 6698 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 6699 | kvm_lmsw(vcpu, val); |
6aa8b732 | 6700 | |
6affcbed | 6701 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6702 | default: |
6703 | break; | |
6704 | } | |
851ba692 | 6705 | vcpu->run->exit_reason = 0; |
a737f256 | 6706 | vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
6707 | (int)(exit_qualification >> 4) & 3, cr); |
6708 | return 0; | |
6709 | } | |
6710 | ||
851ba692 | 6711 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6712 | { |
bfdaab09 | 6713 | unsigned long exit_qualification; |
16f8a6f9 NA |
6714 | int dr, dr7, reg; |
6715 | ||
6716 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6717 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; | |
6718 | ||
6719 | /* First, if DR does not exist, trigger UD */ | |
6720 | if (!kvm_require_dr(vcpu, dr)) | |
6721 | return 1; | |
6aa8b732 | 6722 | |
f2483415 | 6723 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
6724 | if (!kvm_require_cpl(vcpu, 0)) |
6725 | return 1; | |
16f8a6f9 NA |
6726 | dr7 = vmcs_readl(GUEST_DR7); |
6727 | if (dr7 & DR7_GD) { | |
42dbaa5a JK |
6728 | /* |
6729 | * As the vm-exit takes precedence over the debug trap, we | |
6730 | * need to emulate the latter, either for the host or the | |
6731 | * guest debugging itself. | |
6732 | */ | |
6733 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 | 6734 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
16f8a6f9 | 6735 | vcpu->run->debug.arch.dr7 = dr7; |
82b32774 | 6736 | vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
851ba692 AK |
6737 | vcpu->run->debug.arch.exception = DB_VECTOR; |
6738 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
6739 | return 0; |
6740 | } else { | |
7305eb5d | 6741 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 6742 | vcpu->arch.dr6 |= DR6_BD | DR6_RTM; |
42dbaa5a JK |
6743 | kvm_queue_exception(vcpu, DB_VECTOR); |
6744 | return 1; | |
6745 | } | |
6746 | } | |
6747 | ||
81908bf4 | 6748 | if (vcpu->guest_debug == 0) { |
8f22372f PB |
6749 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6750 | CPU_BASED_MOV_DR_EXITING); | |
81908bf4 PB |
6751 | |
6752 | /* | |
6753 | * No more DR vmexits; force a reload of the debug registers | |
6754 | * and reenter on this instruction. The next vmexit will | |
6755 | * retrieve the full state of the debug registers. | |
6756 | */ | |
6757 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
6758 | return 1; | |
6759 | } | |
6760 | ||
42dbaa5a JK |
6761 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); |
6762 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 | 6763 | unsigned long val; |
4c4d563b JK |
6764 | |
6765 | if (kvm_get_dr(vcpu, dr, &val)) | |
6766 | return 1; | |
6767 | kvm_register_write(vcpu, reg, val); | |
020df079 | 6768 | } else |
5777392e | 6769 | if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) |
4c4d563b JK |
6770 | return 1; |
6771 | ||
6affcbed | 6772 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6773 | } |
6774 | ||
73aaf249 JK |
6775 | static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) |
6776 | { | |
6777 | return vcpu->arch.dr6; | |
6778 | } | |
6779 | ||
6780 | static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) | |
6781 | { | |
6782 | } | |
6783 | ||
81908bf4 PB |
6784 | static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
6785 | { | |
81908bf4 PB |
6786 | get_debugreg(vcpu->arch.db[0], 0); |
6787 | get_debugreg(vcpu->arch.db[1], 1); | |
6788 | get_debugreg(vcpu->arch.db[2], 2); | |
6789 | get_debugreg(vcpu->arch.db[3], 3); | |
6790 | get_debugreg(vcpu->arch.dr6, 6); | |
6791 | vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); | |
6792 | ||
6793 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
8f22372f | 6794 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING); |
81908bf4 PB |
6795 | } |
6796 | ||
020df079 GN |
6797 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
6798 | { | |
6799 | vmcs_writel(GUEST_DR7, val); | |
6800 | } | |
6801 | ||
851ba692 | 6802 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 6803 | { |
6a908b62 | 6804 | return kvm_emulate_cpuid(vcpu); |
6aa8b732 AK |
6805 | } |
6806 | ||
851ba692 | 6807 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6808 | { |
ad312c7c | 6809 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
609e36d3 | 6810 | struct msr_data msr_info; |
6aa8b732 | 6811 | |
609e36d3 PB |
6812 | msr_info.index = ecx; |
6813 | msr_info.host_initiated = false; | |
6814 | if (vmx_get_msr(vcpu, &msr_info)) { | |
59200273 | 6815 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 6816 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6817 | return 1; |
6818 | } | |
6819 | ||
609e36d3 | 6820 | trace_kvm_msr_read(ecx, msr_info.data); |
2714d1d3 | 6821 | |
6aa8b732 | 6822 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
609e36d3 PB |
6823 | vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u; |
6824 | vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u; | |
6affcbed | 6825 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6826 | } |
6827 | ||
851ba692 | 6828 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6829 | { |
8fe8ab46 | 6830 | struct msr_data msr; |
ad312c7c ZX |
6831 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6832 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
6833 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 6834 | |
8fe8ab46 WA |
6835 | msr.data = data; |
6836 | msr.index = ecx; | |
6837 | msr.host_initiated = false; | |
854e8bb1 | 6838 | if (kvm_set_msr(vcpu, &msr) != 0) { |
59200273 | 6839 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 6840 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6841 | return 1; |
6842 | } | |
6843 | ||
59200273 | 6844 | trace_kvm_msr_write(ecx, data); |
6affcbed | 6845 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6846 | } |
6847 | ||
851ba692 | 6848 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 6849 | { |
eb90f341 | 6850 | kvm_apic_update_ppr(vcpu); |
6e5d865c YS |
6851 | return 1; |
6852 | } | |
6853 | ||
851ba692 | 6854 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 6855 | { |
47c0152e PB |
6856 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6857 | CPU_BASED_VIRTUAL_INTR_PENDING); | |
2714d1d3 | 6858 | |
3842d135 AK |
6859 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6860 | ||
a26bf12a | 6861 | ++vcpu->stat.irq_window_exits; |
6aa8b732 AK |
6862 | return 1; |
6863 | } | |
6864 | ||
851ba692 | 6865 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 | 6866 | { |
d3bef15f | 6867 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
6868 | } |
6869 | ||
851ba692 | 6870 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 6871 | { |
0d9c055e | 6872 | return kvm_emulate_hypercall(vcpu); |
c21415e8 IM |
6873 | } |
6874 | ||
ec25d5e6 GN |
6875 | static int handle_invd(struct kvm_vcpu *vcpu) |
6876 | { | |
51d8b661 | 6877 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
6878 | } |
6879 | ||
851ba692 | 6880 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 6881 | { |
f9c617f6 | 6882 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
6883 | |
6884 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
6affcbed | 6885 | return kvm_skip_emulated_instruction(vcpu); |
a7052897 MT |
6886 | } |
6887 | ||
fee84b07 AK |
6888 | static int handle_rdpmc(struct kvm_vcpu *vcpu) |
6889 | { | |
6890 | int err; | |
6891 | ||
6892 | err = kvm_rdpmc(vcpu); | |
6affcbed | 6893 | return kvm_complete_insn_gp(vcpu, err); |
fee84b07 AK |
6894 | } |
6895 | ||
851ba692 | 6896 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 | 6897 | { |
6affcbed | 6898 | return kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
6899 | } |
6900 | ||
2acf923e DC |
6901 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
6902 | { | |
6903 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
6904 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6905 | ||
6906 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
6affcbed | 6907 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e DC |
6908 | return 1; |
6909 | } | |
6910 | ||
f53cd63c WL |
6911 | static int handle_xsaves(struct kvm_vcpu *vcpu) |
6912 | { | |
6affcbed | 6913 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6914 | WARN(1, "this should never happen\n"); |
6915 | return 1; | |
6916 | } | |
6917 | ||
6918 | static int handle_xrstors(struct kvm_vcpu *vcpu) | |
6919 | { | |
6affcbed | 6920 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6921 | WARN(1, "this should never happen\n"); |
6922 | return 1; | |
6923 | } | |
6924 | ||
851ba692 | 6925 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 6926 | { |
58fbbf26 KT |
6927 | if (likely(fasteoi)) { |
6928 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6929 | int access_type, offset; | |
6930 | ||
6931 | access_type = exit_qualification & APIC_ACCESS_TYPE; | |
6932 | offset = exit_qualification & APIC_ACCESS_OFFSET; | |
6933 | /* | |
6934 | * Sane guest uses MOV to write EOI, with written value | |
6935 | * not cared. So make a short-circuit here by avoiding | |
6936 | * heavy instruction emulation. | |
6937 | */ | |
6938 | if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && | |
6939 | (offset == APIC_EOI)) { | |
6940 | kvm_lapic_set_eoi(vcpu); | |
6affcbed | 6941 | return kvm_skip_emulated_instruction(vcpu); |
58fbbf26 KT |
6942 | } |
6943 | } | |
51d8b661 | 6944 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
6945 | } |
6946 | ||
c7c9c56c YZ |
6947 | static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) |
6948 | { | |
6949 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6950 | int vector = exit_qualification & 0xff; | |
6951 | ||
6952 | /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ | |
6953 | kvm_apic_set_eoi_accelerated(vcpu, vector); | |
6954 | return 1; | |
6955 | } | |
6956 | ||
83d4c286 YZ |
6957 | static int handle_apic_write(struct kvm_vcpu *vcpu) |
6958 | { | |
6959 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6960 | u32 offset = exit_qualification & 0xfff; | |
6961 | ||
6962 | /* APIC-write VM exit is trap-like and thus no need to adjust IP */ | |
6963 | kvm_apic_write_nodecode(vcpu, offset); | |
6964 | return 1; | |
6965 | } | |
6966 | ||
851ba692 | 6967 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 6968 | { |
60637aac | 6969 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 6970 | unsigned long exit_qualification; |
e269fb21 JK |
6971 | bool has_error_code = false; |
6972 | u32 error_code = 0; | |
37817f29 | 6973 | u16 tss_selector; |
7f3d35fd | 6974 | int reason, type, idt_v, idt_index; |
64a7ec06 GN |
6975 | |
6976 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
7f3d35fd | 6977 | idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); |
64a7ec06 | 6978 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); |
37817f29 IE |
6979 | |
6980 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6981 | ||
6982 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
6983 | if (reason == TASK_SWITCH_GATE && idt_v) { |
6984 | switch (type) { | |
6985 | case INTR_TYPE_NMI_INTR: | |
6986 | vcpu->arch.nmi_injected = false; | |
654f06fc | 6987 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
6988 | break; |
6989 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 6990 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
6991 | kvm_clear_interrupt_queue(vcpu); |
6992 | break; | |
6993 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
6994 | if (vmx->idt_vectoring_info & |
6995 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
6996 | has_error_code = true; | |
6997 | error_code = | |
6998 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
6999 | } | |
7000 | /* fall through */ | |
64a7ec06 GN |
7001 | case INTR_TYPE_SOFT_EXCEPTION: |
7002 | kvm_clear_exception_queue(vcpu); | |
7003 | break; | |
7004 | default: | |
7005 | break; | |
7006 | } | |
60637aac | 7007 | } |
37817f29 IE |
7008 | tss_selector = exit_qualification; |
7009 | ||
64a7ec06 GN |
7010 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
7011 | type != INTR_TYPE_EXT_INTR && | |
7012 | type != INTR_TYPE_NMI_INTR)) | |
7013 | skip_emulated_instruction(vcpu); | |
7014 | ||
7f3d35fd KW |
7015 | if (kvm_task_switch(vcpu, tss_selector, |
7016 | type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason, | |
7017 | has_error_code, error_code) == EMULATE_FAIL) { | |
acb54517 GN |
7018 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
7019 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7020 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 7021 | return 0; |
acb54517 | 7022 | } |
42dbaa5a | 7023 | |
42dbaa5a JK |
7024 | /* |
7025 | * TODO: What about debug traps on tss switch? | |
7026 | * Are we supposed to inject them and update dr6? | |
7027 | */ | |
7028 | ||
7029 | return 1; | |
37817f29 IE |
7030 | } |
7031 | ||
851ba692 | 7032 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 7033 | { |
f9c617f6 | 7034 | unsigned long exit_qualification; |
1439442c | 7035 | gpa_t gpa; |
eebed243 | 7036 | u64 error_code; |
1439442c | 7037 | |
f9c617f6 | 7038 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c | 7039 | |
0be9c7a8 GN |
7040 | /* |
7041 | * EPT violation happened while executing iret from NMI, | |
7042 | * "blocked by NMI" bit has to be set before next VM entry. | |
7043 | * There are errata that may cause this bit to not be set: | |
7044 | * AAK134, BY25. | |
7045 | */ | |
bcd1c294 | 7046 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && |
d02fcf50 | 7047 | enable_vnmi && |
bcd1c294 | 7048 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
0be9c7a8 GN |
7049 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); |
7050 | ||
1439442c | 7051 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
229456fc | 7052 | trace_kvm_page_fault(gpa, exit_qualification); |
4f5982a5 | 7053 | |
27959a44 | 7054 | /* Is it a read fault? */ |
ab22a473 | 7055 | error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) |
27959a44 JS |
7056 | ? PFERR_USER_MASK : 0; |
7057 | /* Is it a write fault? */ | |
ab22a473 | 7058 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) |
27959a44 JS |
7059 | ? PFERR_WRITE_MASK : 0; |
7060 | /* Is it a fetch fault? */ | |
ab22a473 | 7061 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) |
27959a44 JS |
7062 | ? PFERR_FETCH_MASK : 0; |
7063 | /* ept page table entry is present? */ | |
7064 | error_code |= (exit_qualification & | |
7065 | (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | | |
7066 | EPT_VIOLATION_EXECUTABLE)) | |
7067 | ? PFERR_PRESENT_MASK : 0; | |
4f5982a5 | 7068 | |
eebed243 PB |
7069 | error_code |= (exit_qualification & 0x100) != 0 ? |
7070 | PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; | |
25d92081 | 7071 | |
25d92081 | 7072 | vcpu->arch.exit_qualification = exit_qualification; |
4f5982a5 | 7073 | return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); |
1439442c SY |
7074 | } |
7075 | ||
851ba692 | 7076 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 | 7077 | { |
68f89400 MT |
7078 | gpa_t gpa; |
7079 | ||
9034e6e8 PB |
7080 | /* |
7081 | * A nested guest cannot optimize MMIO vmexits, because we have an | |
7082 | * nGPA here instead of the required GPA. | |
7083 | */ | |
68f89400 | 7084 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
9034e6e8 PB |
7085 | if (!is_guest_mode(vcpu) && |
7086 | !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { | |
931c33b1 | 7087 | trace_kvm_fast_mmio(gpa); |
d391f120 VK |
7088 | /* |
7089 | * Doing kvm_skip_emulated_instruction() depends on undefined | |
7090 | * behavior: Intel's manual doesn't mandate | |
7091 | * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG | |
7092 | * occurs and while on real hardware it was observed to be set, | |
7093 | * other hypervisors (namely Hyper-V) don't set it, we end up | |
7094 | * advancing IP with some random value. Disable fast mmio when | |
7095 | * running nested and keep it for real hardware in hope that | |
7096 | * VM_EXIT_INSTRUCTION_LEN will always be set correctly. | |
7097 | */ | |
7098 | if (!static_cpu_has(X86_FEATURE_HYPERVISOR)) | |
7099 | return kvm_skip_emulated_instruction(vcpu); | |
7100 | else | |
7101 | return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP, | |
7102 | NULL, 0) == EMULATE_DONE; | |
68c3b4d1 | 7103 | } |
68f89400 | 7104 | |
c75d0edc | 7105 | return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); |
68f89400 MT |
7106 | } |
7107 | ||
851ba692 | 7108 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 | 7109 | { |
d02fcf50 | 7110 | WARN_ON_ONCE(!enable_vnmi); |
47c0152e PB |
7111 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
7112 | CPU_BASED_VIRTUAL_NMI_PENDING); | |
f08864b4 | 7113 | ++vcpu->stat.nmi_window_exits; |
3842d135 | 7114 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
7115 | |
7116 | return 1; | |
7117 | } | |
7118 | ||
80ced186 | 7119 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 7120 | { |
8b3079a5 AK |
7121 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7122 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 7123 | int ret = 1; |
49e9d557 AK |
7124 | u32 cpu_exec_ctrl; |
7125 | bool intr_window_requested; | |
b8405c18 | 7126 | unsigned count = 130; |
49e9d557 | 7127 | |
2bb8cafe SC |
7128 | /* |
7129 | * We should never reach the point where we are emulating L2 | |
7130 | * due to invalid guest state as that means we incorrectly | |
7131 | * allowed a nested VMEntry with an invalid vmcs12. | |
7132 | */ | |
7133 | WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending); | |
7134 | ||
49e9d557 AK |
7135 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); |
7136 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 | 7137 | |
98eb2f8b | 7138 | while (vmx->emulation_required && count-- != 0) { |
bdea48e3 | 7139 | if (intr_window_requested && vmx_interrupt_allowed(vcpu)) |
49e9d557 AK |
7140 | return handle_interrupt_window(&vmx->vcpu); |
7141 | ||
72875d8a | 7142 | if (kvm_test_request(KVM_REQ_EVENT, vcpu)) |
de87dcdd AK |
7143 | return 1; |
7144 | ||
9b8ae637 | 7145 | err = emulate_instruction(vcpu, 0); |
ea953ef0 | 7146 | |
ac0a48c3 | 7147 | if (err == EMULATE_USER_EXIT) { |
94452b9e | 7148 | ++vcpu->stat.mmio_exits; |
80ced186 MG |
7149 | ret = 0; |
7150 | goto out; | |
7151 | } | |
1d5a4d9b | 7152 | |
add5ff7a SC |
7153 | if (err != EMULATE_DONE) |
7154 | goto emulation_error; | |
7155 | ||
7156 | if (vmx->emulation_required && !vmx->rmode.vm86_active && | |
7157 | vcpu->arch.exception.pending) | |
7158 | goto emulation_error; | |
ea953ef0 | 7159 | |
8d76c49e GN |
7160 | if (vcpu->arch.halt_request) { |
7161 | vcpu->arch.halt_request = 0; | |
5cb56059 | 7162 | ret = kvm_vcpu_halt(vcpu); |
8d76c49e GN |
7163 | goto out; |
7164 | } | |
7165 | ||
ea953ef0 | 7166 | if (signal_pending(current)) |
80ced186 | 7167 | goto out; |
ea953ef0 MG |
7168 | if (need_resched()) |
7169 | schedule(); | |
7170 | } | |
7171 | ||
80ced186 MG |
7172 | out: |
7173 | return ret; | |
b4a2d31d | 7174 | |
add5ff7a SC |
7175 | emulation_error: |
7176 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7177 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7178 | vcpu->run->internal.ndata = 0; | |
7179 | return 0; | |
b4a2d31d RK |
7180 | } |
7181 | ||
7182 | static void grow_ple_window(struct kvm_vcpu *vcpu) | |
7183 | { | |
7184 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7185 | int old = vmx->ple_window; | |
7186 | ||
c8e88717 BM |
7187 | vmx->ple_window = __grow_ple_window(old, ple_window, |
7188 | ple_window_grow, | |
7189 | ple_window_max); | |
b4a2d31d RK |
7190 | |
7191 | if (vmx->ple_window != old) | |
7192 | vmx->ple_window_dirty = true; | |
7b46268d RK |
7193 | |
7194 | trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
7195 | } |
7196 | ||
7197 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
7198 | { | |
7199 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7200 | int old = vmx->ple_window; | |
7201 | ||
c8e88717 BM |
7202 | vmx->ple_window = __shrink_ple_window(old, ple_window, |
7203 | ple_window_shrink, | |
7204 | ple_window); | |
b4a2d31d RK |
7205 | |
7206 | if (vmx->ple_window != old) | |
7207 | vmx->ple_window_dirty = true; | |
7b46268d RK |
7208 | |
7209 | trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
7210 | } |
7211 | ||
bf9f6ac8 FW |
7212 | /* |
7213 | * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. | |
7214 | */ | |
7215 | static void wakeup_handler(void) | |
7216 | { | |
7217 | struct kvm_vcpu *vcpu; | |
7218 | int cpu = smp_processor_id(); | |
7219 | ||
7220 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
7221 | list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), | |
7222 | blocked_vcpu_list) { | |
7223 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
7224 | ||
7225 | if (pi_test_on(pi_desc) == 1) | |
7226 | kvm_vcpu_kick(vcpu); | |
7227 | } | |
7228 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
7229 | } | |
7230 | ||
e01bca2f | 7231 | static void vmx_enable_tdp(void) |
f160c7b7 JS |
7232 | { |
7233 | kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, | |
7234 | enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, | |
7235 | enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, | |
7236 | 0ull, VMX_EPT_EXECUTABLE_MASK, | |
7237 | cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, | |
d0ec49d4 | 7238 | VMX_EPT_RWX_MASK, 0ull); |
f160c7b7 JS |
7239 | |
7240 | ept_set_mmio_spte_mask(); | |
7241 | kvm_enable_tdp(); | |
7242 | } | |
7243 | ||
f2c7648d TC |
7244 | static __init int hardware_setup(void) |
7245 | { | |
904e14fb | 7246 | int r = -ENOMEM, i; |
34a1cd60 TC |
7247 | |
7248 | rdmsrl_safe(MSR_EFER, &host_efer); | |
7249 | ||
7250 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) | |
7251 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
7252 | ||
23611332 RK |
7253 | for (i = 0; i < VMX_BITMAP_NR; i++) { |
7254 | vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL); | |
7255 | if (!vmx_bitmap[i]) | |
7256 | goto out; | |
7257 | } | |
34a1cd60 | 7258 | |
34a1cd60 TC |
7259 | memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); |
7260 | memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); | |
7261 | ||
34a1cd60 TC |
7262 | if (setup_vmcs_config(&vmcs_config) < 0) { |
7263 | r = -EIO; | |
23611332 | 7264 | goto out; |
baa03522 | 7265 | } |
f2c7648d TC |
7266 | |
7267 | if (boot_cpu_has(X86_FEATURE_NX)) | |
7268 | kvm_enable_efer_bits(EFER_NX); | |
7269 | ||
08d839c4 WL |
7270 | if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || |
7271 | !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) | |
f2c7648d | 7272 | enable_vpid = 0; |
08d839c4 | 7273 | |
f2c7648d | 7274 | if (!cpu_has_vmx_ept() || |
42aa53b4 | 7275 | !cpu_has_vmx_ept_4levels() || |
f5f51586 | 7276 | !cpu_has_vmx_ept_mt_wb() || |
8ad8182e | 7277 | !cpu_has_vmx_invept_global()) |
f2c7648d | 7278 | enable_ept = 0; |
f2c7648d | 7279 | |
fce6ac4c | 7280 | if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) |
f2c7648d TC |
7281 | enable_ept_ad_bits = 0; |
7282 | ||
8ad8182e | 7283 | if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) |
f2c7648d TC |
7284 | enable_unrestricted_guest = 0; |
7285 | ||
ad15a296 | 7286 | if (!cpu_has_vmx_flexpriority()) |
f2c7648d TC |
7287 | flexpriority_enabled = 0; |
7288 | ||
d02fcf50 PB |
7289 | if (!cpu_has_virtual_nmis()) |
7290 | enable_vnmi = 0; | |
7291 | ||
ad15a296 PB |
7292 | /* |
7293 | * set_apic_access_page_addr() is used to reload apic access | |
7294 | * page upon invalidation. No need to do anything if not | |
7295 | * using the APIC_ACCESS_ADDR VMCS field. | |
7296 | */ | |
7297 | if (!flexpriority_enabled) | |
f2c7648d | 7298 | kvm_x86_ops->set_apic_access_page_addr = NULL; |
f2c7648d TC |
7299 | |
7300 | if (!cpu_has_vmx_tpr_shadow()) | |
7301 | kvm_x86_ops->update_cr8_intercept = NULL; | |
7302 | ||
7303 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) | |
7304 | kvm_disable_largepages(); | |
7305 | ||
0f107682 | 7306 | if (!cpu_has_vmx_ple()) { |
f2c7648d | 7307 | ple_gap = 0; |
0f107682 WL |
7308 | ple_window = 0; |
7309 | ple_window_grow = 0; | |
7310 | ple_window_max = 0; | |
7311 | ple_window_shrink = 0; | |
7312 | } | |
f2c7648d | 7313 | |
76dfafd5 | 7314 | if (!cpu_has_vmx_apicv()) { |
f2c7648d | 7315 | enable_apicv = 0; |
76dfafd5 PB |
7316 | kvm_x86_ops->sync_pir_to_irr = NULL; |
7317 | } | |
f2c7648d | 7318 | |
64903d61 HZ |
7319 | if (cpu_has_vmx_tsc_scaling()) { |
7320 | kvm_has_tsc_control = true; | |
7321 | kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; | |
7322 | kvm_tsc_scaling_ratio_frac_bits = 48; | |
7323 | } | |
7324 | ||
04bb92e4 WL |
7325 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
7326 | ||
f160c7b7 JS |
7327 | if (enable_ept) |
7328 | vmx_enable_tdp(); | |
7329 | else | |
baa03522 TC |
7330 | kvm_disable_tdp(); |
7331 | ||
843e4330 KH |
7332 | /* |
7333 | * Only enable PML when hardware supports PML feature, and both EPT | |
7334 | * and EPT A/D bit features are enabled -- PML depends on them to work. | |
7335 | */ | |
7336 | if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) | |
7337 | enable_pml = 0; | |
7338 | ||
7339 | if (!enable_pml) { | |
7340 | kvm_x86_ops->slot_enable_log_dirty = NULL; | |
7341 | kvm_x86_ops->slot_disable_log_dirty = NULL; | |
7342 | kvm_x86_ops->flush_log_dirty = NULL; | |
7343 | kvm_x86_ops->enable_log_dirty_pt_masked = NULL; | |
7344 | } | |
7345 | ||
64672c95 YJ |
7346 | if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) { |
7347 | u64 vmx_msr; | |
7348 | ||
7349 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
7350 | cpu_preemption_timer_multi = | |
7351 | vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; | |
7352 | } else { | |
7353 | kvm_x86_ops->set_hv_timer = NULL; | |
7354 | kvm_x86_ops->cancel_hv_timer = NULL; | |
7355 | } | |
7356 | ||
c5d167b2 PB |
7357 | if (!cpu_has_vmx_shadow_vmcs()) |
7358 | enable_shadow_vmcs = 0; | |
7359 | if (enable_shadow_vmcs) | |
7360 | init_vmcs_shadow_fields(); | |
7361 | ||
bf9f6ac8 | 7362 | kvm_set_posted_intr_wakeup_handler(wakeup_handler); |
1389309c | 7363 | nested_vmx_setup_ctls_msrs(&vmcs_config.nested, enable_apicv); |
bf9f6ac8 | 7364 | |
c45dcc71 AR |
7365 | kvm_mce_cap_supported |= MCG_LMCE_P; |
7366 | ||
f2c7648d | 7367 | return alloc_kvm_area(); |
34a1cd60 | 7368 | |
34a1cd60 | 7369 | out: |
23611332 RK |
7370 | for (i = 0; i < VMX_BITMAP_NR; i++) |
7371 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 TC |
7372 | |
7373 | return r; | |
f2c7648d TC |
7374 | } |
7375 | ||
7376 | static __exit void hardware_unsetup(void) | |
7377 | { | |
23611332 RK |
7378 | int i; |
7379 | ||
7380 | for (i = 0; i < VMX_BITMAP_NR; i++) | |
7381 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 | 7382 | |
f2c7648d TC |
7383 | free_kvm_area(); |
7384 | } | |
7385 | ||
4b8d54f9 ZE |
7386 | /* |
7387 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
7388 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
7389 | */ | |
9fb41ba8 | 7390 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 | 7391 | { |
b31c114b | 7392 | if (!kvm_pause_in_guest(vcpu->kvm)) |
b4a2d31d RK |
7393 | grow_ple_window(vcpu); |
7394 | ||
de63ad4c LM |
7395 | /* |
7396 | * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" | |
7397 | * VM-execution control is ignored if CPL > 0. OTOH, KVM | |
7398 | * never set PAUSE_EXITING and just set PLE if supported, | |
7399 | * so the vcpu must be CPL=0 if it gets a PAUSE exit. | |
7400 | */ | |
7401 | kvm_vcpu_on_spin(vcpu, true); | |
6affcbed | 7402 | return kvm_skip_emulated_instruction(vcpu); |
4b8d54f9 ZE |
7403 | } |
7404 | ||
87c00572 | 7405 | static int handle_nop(struct kvm_vcpu *vcpu) |
59708670 | 7406 | { |
6affcbed | 7407 | return kvm_skip_emulated_instruction(vcpu); |
59708670 SY |
7408 | } |
7409 | ||
87c00572 GS |
7410 | static int handle_mwait(struct kvm_vcpu *vcpu) |
7411 | { | |
7412 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
7413 | return handle_nop(vcpu); | |
7414 | } | |
7415 | ||
45ec368c JM |
7416 | static int handle_invalid_op(struct kvm_vcpu *vcpu) |
7417 | { | |
7418 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7419 | return 1; | |
7420 | } | |
7421 | ||
5f3d45e7 MD |
7422 | static int handle_monitor_trap(struct kvm_vcpu *vcpu) |
7423 | { | |
7424 | return 1; | |
7425 | } | |
7426 | ||
87c00572 GS |
7427 | static int handle_monitor(struct kvm_vcpu *vcpu) |
7428 | { | |
7429 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
7430 | return handle_nop(vcpu); | |
7431 | } | |
7432 | ||
0658fbaa ACL |
7433 | /* |
7434 | * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), | |
7435 | * set the success or error code of an emulated VMX instruction, as specified | |
7436 | * by Vol 2B, VMX Instruction Reference, "Conventions". | |
7437 | */ | |
7438 | static void nested_vmx_succeed(struct kvm_vcpu *vcpu) | |
7439 | { | |
7440 | vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) | |
7441 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
7442 | X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); | |
7443 | } | |
7444 | ||
7445 | static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu) | |
7446 | { | |
7447 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
7448 | & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | | |
7449 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
7450 | | X86_EFLAGS_CF); | |
7451 | } | |
7452 | ||
145c28dd | 7453 | static void nested_vmx_failValid(struct kvm_vcpu *vcpu, |
0658fbaa ACL |
7454 | u32 vm_instruction_error) |
7455 | { | |
7456 | if (to_vmx(vcpu)->nested.current_vmptr == -1ull) { | |
7457 | /* | |
7458 | * failValid writes the error number to the current VMCS, which | |
7459 | * can't be done there isn't a current VMCS. | |
7460 | */ | |
7461 | nested_vmx_failInvalid(vcpu); | |
7462 | return; | |
7463 | } | |
7464 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
7465 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
7466 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
7467 | | X86_EFLAGS_ZF); | |
7468 | get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; | |
7469 | /* | |
7470 | * We don't need to force a shadow sync because | |
7471 | * VM_INSTRUCTION_ERROR is not shadowed | |
7472 | */ | |
7473 | } | |
145c28dd | 7474 | |
ff651cb6 WV |
7475 | static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator) |
7476 | { | |
7477 | /* TODO: not to reset guest simply here. */ | |
7478 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
bbe41b95 | 7479 | pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator); |
ff651cb6 WV |
7480 | } |
7481 | ||
f4124500 JK |
7482 | static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) |
7483 | { | |
7484 | struct vcpu_vmx *vmx = | |
7485 | container_of(timer, struct vcpu_vmx, nested.preemption_timer); | |
7486 | ||
7487 | vmx->nested.preemption_timer_expired = true; | |
7488 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); | |
7489 | kvm_vcpu_kick(&vmx->vcpu); | |
7490 | ||
7491 | return HRTIMER_NORESTART; | |
7492 | } | |
7493 | ||
19677e32 BD |
7494 | /* |
7495 | * Decode the memory-address operand of a vmx instruction, as recorded on an | |
7496 | * exit caused by such an instruction (run by a guest hypervisor). | |
7497 | * On success, returns 0. When the operand is invalid, returns 1 and throws | |
7498 | * #UD or #GP. | |
7499 | */ | |
7500 | static int get_vmx_mem_address(struct kvm_vcpu *vcpu, | |
7501 | unsigned long exit_qualification, | |
f9eb4af6 | 7502 | u32 vmx_instruction_info, bool wr, gva_t *ret) |
19677e32 | 7503 | { |
f9eb4af6 EK |
7504 | gva_t off; |
7505 | bool exn; | |
7506 | struct kvm_segment s; | |
7507 | ||
19677e32 BD |
7508 | /* |
7509 | * According to Vol. 3B, "Information for VM Exits Due to Instruction | |
7510 | * Execution", on an exit, vmx_instruction_info holds most of the | |
7511 | * addressing components of the operand. Only the displacement part | |
7512 | * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). | |
7513 | * For how an actual address is calculated from all these components, | |
7514 | * refer to Vol. 1, "Operand Addressing". | |
7515 | */ | |
7516 | int scaling = vmx_instruction_info & 3; | |
7517 | int addr_size = (vmx_instruction_info >> 7) & 7; | |
7518 | bool is_reg = vmx_instruction_info & (1u << 10); | |
7519 | int seg_reg = (vmx_instruction_info >> 15) & 7; | |
7520 | int index_reg = (vmx_instruction_info >> 18) & 0xf; | |
7521 | bool index_is_valid = !(vmx_instruction_info & (1u << 22)); | |
7522 | int base_reg = (vmx_instruction_info >> 23) & 0xf; | |
7523 | bool base_is_valid = !(vmx_instruction_info & (1u << 27)); | |
7524 | ||
7525 | if (is_reg) { | |
7526 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7527 | return 1; | |
7528 | } | |
7529 | ||
7530 | /* Addr = segment_base + offset */ | |
7531 | /* offset = base + [index * scale] + displacement */ | |
f9eb4af6 | 7532 | off = exit_qualification; /* holds the displacement */ |
19677e32 | 7533 | if (base_is_valid) |
f9eb4af6 | 7534 | off += kvm_register_read(vcpu, base_reg); |
19677e32 | 7535 | if (index_is_valid) |
f9eb4af6 EK |
7536 | off += kvm_register_read(vcpu, index_reg)<<scaling; |
7537 | vmx_get_segment(vcpu, &s, seg_reg); | |
7538 | *ret = s.base + off; | |
19677e32 BD |
7539 | |
7540 | if (addr_size == 1) /* 32 bit */ | |
7541 | *ret &= 0xffffffff; | |
7542 | ||
f9eb4af6 EK |
7543 | /* Checks for #GP/#SS exceptions. */ |
7544 | exn = false; | |
ff30ef40 QC |
7545 | if (is_long_mode(vcpu)) { |
7546 | /* Long mode: #GP(0)/#SS(0) if the memory address is in a | |
7547 | * non-canonical form. This is the only check on the memory | |
7548 | * destination for long mode! | |
7549 | */ | |
fd8cb433 | 7550 | exn = is_noncanonical_address(*ret, vcpu); |
ff30ef40 | 7551 | } else if (is_protmode(vcpu)) { |
f9eb4af6 EK |
7552 | /* Protected mode: apply checks for segment validity in the |
7553 | * following order: | |
7554 | * - segment type check (#GP(0) may be thrown) | |
7555 | * - usability check (#GP(0)/#SS(0)) | |
7556 | * - limit check (#GP(0)/#SS(0)) | |
7557 | */ | |
7558 | if (wr) | |
7559 | /* #GP(0) if the destination operand is located in a | |
7560 | * read-only data segment or any code segment. | |
7561 | */ | |
7562 | exn = ((s.type & 0xa) == 0 || (s.type & 8)); | |
7563 | else | |
7564 | /* #GP(0) if the source operand is located in an | |
7565 | * execute-only code segment | |
7566 | */ | |
7567 | exn = ((s.type & 0xa) == 8); | |
ff30ef40 QC |
7568 | if (exn) { |
7569 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
7570 | return 1; | |
7571 | } | |
f9eb4af6 EK |
7572 | /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. |
7573 | */ | |
7574 | exn = (s.unusable != 0); | |
7575 | /* Protected mode: #GP(0)/#SS(0) if the memory | |
7576 | * operand is outside the segment limit. | |
7577 | */ | |
7578 | exn = exn || (off + sizeof(u64) > s.limit); | |
7579 | } | |
7580 | if (exn) { | |
7581 | kvm_queue_exception_e(vcpu, | |
7582 | seg_reg == VCPU_SREG_SS ? | |
7583 | SS_VECTOR : GP_VECTOR, | |
7584 | 0); | |
7585 | return 1; | |
7586 | } | |
7587 | ||
19677e32 BD |
7588 | return 0; |
7589 | } | |
7590 | ||
cbf71279 | 7591 | static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer) |
3573e22c BD |
7592 | { |
7593 | gva_t gva; | |
3573e22c | 7594 | struct x86_exception e; |
3573e22c BD |
7595 | |
7596 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7597 | vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva)) |
3573e22c BD |
7598 | return 1; |
7599 | ||
cbf71279 RK |
7600 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer, |
7601 | sizeof(*vmpointer), &e)) { | |
3573e22c BD |
7602 | kvm_inject_page_fault(vcpu, &e); |
7603 | return 1; | |
7604 | } | |
7605 | ||
3573e22c BD |
7606 | return 0; |
7607 | } | |
7608 | ||
e29acc55 JM |
7609 | static int enter_vmx_operation(struct kvm_vcpu *vcpu) |
7610 | { | |
7611 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7612 | struct vmcs *shadow_vmcs; | |
f21f165e | 7613 | int r; |
e29acc55 | 7614 | |
f21f165e PB |
7615 | r = alloc_loaded_vmcs(&vmx->nested.vmcs02); |
7616 | if (r < 0) | |
de3a0021 | 7617 | goto out_vmcs02; |
e29acc55 JM |
7618 | |
7619 | vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL); | |
7620 | if (!vmx->nested.cached_vmcs12) | |
7621 | goto out_cached_vmcs12; | |
7622 | ||
7623 | if (enable_shadow_vmcs) { | |
7624 | shadow_vmcs = alloc_vmcs(); | |
7625 | if (!shadow_vmcs) | |
7626 | goto out_shadow_vmcs; | |
7627 | /* mark vmcs as shadow */ | |
7628 | shadow_vmcs->revision_id |= (1u << 31); | |
7629 | /* init shadow vmcs */ | |
7630 | vmcs_clear(shadow_vmcs); | |
7631 | vmx->vmcs01.shadow_vmcs = shadow_vmcs; | |
7632 | } | |
7633 | ||
e29acc55 JM |
7634 | hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, |
7635 | HRTIMER_MODE_REL_PINNED); | |
7636 | vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; | |
7637 | ||
7638 | vmx->nested.vmxon = true; | |
7639 | return 0; | |
7640 | ||
7641 | out_shadow_vmcs: | |
7642 | kfree(vmx->nested.cached_vmcs12); | |
7643 | ||
7644 | out_cached_vmcs12: | |
de3a0021 | 7645 | free_loaded_vmcs(&vmx->nested.vmcs02); |
e29acc55 | 7646 | |
de3a0021 | 7647 | out_vmcs02: |
e29acc55 JM |
7648 | return -ENOMEM; |
7649 | } | |
7650 | ||
ec378aee NHE |
7651 | /* |
7652 | * Emulate the VMXON instruction. | |
7653 | * Currently, we just remember that VMX is active, and do not save or even | |
7654 | * inspect the argument to VMXON (the so-called "VMXON pointer") because we | |
7655 | * do not currently need to store anything in that guest-allocated memory | |
7656 | * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their | |
7657 | * argument is different from the VMXON pointer (which the spec says they do). | |
7658 | */ | |
7659 | static int handle_vmon(struct kvm_vcpu *vcpu) | |
7660 | { | |
e29acc55 | 7661 | int ret; |
cbf71279 RK |
7662 | gpa_t vmptr; |
7663 | struct page *page; | |
ec378aee | 7664 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b3897a49 NHE |
7665 | const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED |
7666 | | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
ec378aee | 7667 | |
70f3aac9 JM |
7668 | /* |
7669 | * The Intel VMX Instruction Reference lists a bunch of bits that are | |
7670 | * prerequisite to running VMXON, most notably cr4.VMXE must be set to | |
7671 | * 1 (see vmx_set_cr4() for when we allow the guest to set this). | |
7672 | * Otherwise, we should fail with #UD. But most faulting conditions | |
7673 | * have already been checked by hardware, prior to the VM-exit for | |
7674 | * VMXON. We do test guest cr4.VMXE because processor CR4 always has | |
7675 | * that bit set to 1 in non-root mode. | |
ec378aee | 7676 | */ |
70f3aac9 | 7677 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) { |
ec378aee NHE |
7678 | kvm_queue_exception(vcpu, UD_VECTOR); |
7679 | return 1; | |
7680 | } | |
7681 | ||
145c28dd AG |
7682 | if (vmx->nested.vmxon) { |
7683 | nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); | |
6affcbed | 7684 | return kvm_skip_emulated_instruction(vcpu); |
145c28dd | 7685 | } |
b3897a49 | 7686 | |
3b84080b | 7687 | if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES) |
b3897a49 NHE |
7688 | != VMXON_NEEDED_FEATURES) { |
7689 | kvm_inject_gp(vcpu, 0); | |
7690 | return 1; | |
7691 | } | |
7692 | ||
cbf71279 | 7693 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
21e7fbe7 | 7694 | return 1; |
cbf71279 RK |
7695 | |
7696 | /* | |
7697 | * SDM 3: 24.11.5 | |
7698 | * The first 4 bytes of VMXON region contain the supported | |
7699 | * VMCS revision identifier | |
7700 | * | |
7701 | * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case; | |
7702 | * which replaces physical address width with 32 | |
7703 | */ | |
7704 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { | |
7705 | nested_vmx_failInvalid(vcpu); | |
7706 | return kvm_skip_emulated_instruction(vcpu); | |
7707 | } | |
7708 | ||
5e2f30b7 DH |
7709 | page = kvm_vcpu_gpa_to_page(vcpu, vmptr); |
7710 | if (is_error_page(page)) { | |
cbf71279 RK |
7711 | nested_vmx_failInvalid(vcpu); |
7712 | return kvm_skip_emulated_instruction(vcpu); | |
7713 | } | |
7714 | if (*(u32 *)kmap(page) != VMCS12_REVISION) { | |
7715 | kunmap(page); | |
53a70daf | 7716 | kvm_release_page_clean(page); |
cbf71279 RK |
7717 | nested_vmx_failInvalid(vcpu); |
7718 | return kvm_skip_emulated_instruction(vcpu); | |
7719 | } | |
7720 | kunmap(page); | |
53a70daf | 7721 | kvm_release_page_clean(page); |
cbf71279 RK |
7722 | |
7723 | vmx->nested.vmxon_ptr = vmptr; | |
e29acc55 JM |
7724 | ret = enter_vmx_operation(vcpu); |
7725 | if (ret) | |
7726 | return ret; | |
ec378aee | 7727 | |
a25eb114 | 7728 | nested_vmx_succeed(vcpu); |
6affcbed | 7729 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7730 | } |
7731 | ||
7732 | /* | |
7733 | * Intel's VMX Instruction Reference specifies a common set of prerequisites | |
7734 | * for running VMX instructions (except VMXON, whose prerequisites are | |
7735 | * slightly different). It also specifies what exception to inject otherwise. | |
70f3aac9 JM |
7736 | * Note that many of these exceptions have priority over VM exits, so they |
7737 | * don't have to be checked again here. | |
ec378aee NHE |
7738 | */ |
7739 | static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) | |
7740 | { | |
70f3aac9 | 7741 | if (!to_vmx(vcpu)->nested.vmxon) { |
ec378aee NHE |
7742 | kvm_queue_exception(vcpu, UD_VECTOR); |
7743 | return 0; | |
7744 | } | |
ec378aee NHE |
7745 | return 1; |
7746 | } | |
7747 | ||
8ca44e88 DM |
7748 | static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx) |
7749 | { | |
7750 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS); | |
7751 | vmcs_write64(VMCS_LINK_POINTER, -1ull); | |
7752 | } | |
7753 | ||
e7953d7f AG |
7754 | static inline void nested_release_vmcs12(struct vcpu_vmx *vmx) |
7755 | { | |
9a2a05b9 PB |
7756 | if (vmx->nested.current_vmptr == -1ull) |
7757 | return; | |
7758 | ||
012f83cb | 7759 | if (enable_shadow_vmcs) { |
9a2a05b9 PB |
7760 | /* copy to memory all shadowed fields in case |
7761 | they were modified */ | |
7762 | copy_shadow_to_vmcs12(vmx); | |
7763 | vmx->nested.sync_shadow_vmcs = false; | |
8ca44e88 | 7764 | vmx_disable_shadow_vmcs(vmx); |
012f83cb | 7765 | } |
705699a1 | 7766 | vmx->nested.posted_intr_nv = -1; |
4f2777bc DM |
7767 | |
7768 | /* Flush VMCS12 to guest memory */ | |
9f744c59 PB |
7769 | kvm_vcpu_write_guest_page(&vmx->vcpu, |
7770 | vmx->nested.current_vmptr >> PAGE_SHIFT, | |
7771 | vmx->nested.cached_vmcs12, 0, VMCS12_SIZE); | |
4f2777bc | 7772 | |
9a2a05b9 | 7773 | vmx->nested.current_vmptr = -1ull; |
e7953d7f AG |
7774 | } |
7775 | ||
ec378aee NHE |
7776 | /* |
7777 | * Free whatever needs to be freed from vmx->nested when L1 goes down, or | |
7778 | * just stops using VMX. | |
7779 | */ | |
7780 | static void free_nested(struct vcpu_vmx *vmx) | |
7781 | { | |
b7455825 | 7782 | if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon) |
ec378aee | 7783 | return; |
9a2a05b9 | 7784 | |
ec378aee | 7785 | vmx->nested.vmxon = false; |
b7455825 | 7786 | vmx->nested.smm.vmxon = false; |
5c614b35 | 7787 | free_vpid(vmx->nested.vpid02); |
8ca44e88 DM |
7788 | vmx->nested.posted_intr_nv = -1; |
7789 | vmx->nested.current_vmptr = -1ull; | |
355f4fb1 | 7790 | if (enable_shadow_vmcs) { |
8ca44e88 | 7791 | vmx_disable_shadow_vmcs(vmx); |
355f4fb1 JM |
7792 | vmcs_clear(vmx->vmcs01.shadow_vmcs); |
7793 | free_vmcs(vmx->vmcs01.shadow_vmcs); | |
7794 | vmx->vmcs01.shadow_vmcs = NULL; | |
7795 | } | |
4f2777bc | 7796 | kfree(vmx->nested.cached_vmcs12); |
de3a0021 | 7797 | /* Unpin physical memory we referred to in the vmcs02 */ |
fe3ef05c | 7798 | if (vmx->nested.apic_access_page) { |
53a70daf | 7799 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
48d89b92 | 7800 | vmx->nested.apic_access_page = NULL; |
fe3ef05c | 7801 | } |
a7c0b07d | 7802 | if (vmx->nested.virtual_apic_page) { |
53a70daf | 7803 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
48d89b92 | 7804 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 7805 | } |
705699a1 WV |
7806 | if (vmx->nested.pi_desc_page) { |
7807 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 7808 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
705699a1 WV |
7809 | vmx->nested.pi_desc_page = NULL; |
7810 | vmx->nested.pi_desc = NULL; | |
7811 | } | |
ff2f6fe9 | 7812 | |
de3a0021 | 7813 | free_loaded_vmcs(&vmx->nested.vmcs02); |
ec378aee NHE |
7814 | } |
7815 | ||
7816 | /* Emulate the VMXOFF instruction */ | |
7817 | static int handle_vmoff(struct kvm_vcpu *vcpu) | |
7818 | { | |
7819 | if (!nested_vmx_check_permission(vcpu)) | |
7820 | return 1; | |
7821 | free_nested(to_vmx(vcpu)); | |
a25eb114 | 7822 | nested_vmx_succeed(vcpu); |
6affcbed | 7823 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7824 | } |
7825 | ||
27d6c865 NHE |
7826 | /* Emulate the VMCLEAR instruction */ |
7827 | static int handle_vmclear(struct kvm_vcpu *vcpu) | |
7828 | { | |
7829 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
587d7e72 | 7830 | u32 zero = 0; |
27d6c865 | 7831 | gpa_t vmptr; |
27d6c865 NHE |
7832 | |
7833 | if (!nested_vmx_check_permission(vcpu)) | |
7834 | return 1; | |
7835 | ||
cbf71279 | 7836 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
27d6c865 | 7837 | return 1; |
27d6c865 | 7838 | |
cbf71279 RK |
7839 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { |
7840 | nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS); | |
7841 | return kvm_skip_emulated_instruction(vcpu); | |
7842 | } | |
7843 | ||
7844 | if (vmptr == vmx->nested.vmxon_ptr) { | |
7845 | nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER); | |
7846 | return kvm_skip_emulated_instruction(vcpu); | |
7847 | } | |
7848 | ||
9a2a05b9 | 7849 | if (vmptr == vmx->nested.current_vmptr) |
e7953d7f | 7850 | nested_release_vmcs12(vmx); |
27d6c865 | 7851 | |
587d7e72 JM |
7852 | kvm_vcpu_write_guest(vcpu, |
7853 | vmptr + offsetof(struct vmcs12, launch_state), | |
7854 | &zero, sizeof(zero)); | |
27d6c865 | 7855 | |
27d6c865 | 7856 | nested_vmx_succeed(vcpu); |
6affcbed | 7857 | return kvm_skip_emulated_instruction(vcpu); |
27d6c865 NHE |
7858 | } |
7859 | ||
cd232ad0 NHE |
7860 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch); |
7861 | ||
7862 | /* Emulate the VMLAUNCH instruction */ | |
7863 | static int handle_vmlaunch(struct kvm_vcpu *vcpu) | |
7864 | { | |
7865 | return nested_vmx_run(vcpu, true); | |
7866 | } | |
7867 | ||
7868 | /* Emulate the VMRESUME instruction */ | |
7869 | static int handle_vmresume(struct kvm_vcpu *vcpu) | |
7870 | { | |
7871 | ||
7872 | return nested_vmx_run(vcpu, false); | |
7873 | } | |
7874 | ||
49f705c5 NHE |
7875 | /* |
7876 | * Read a vmcs12 field. Since these can have varying lengths and we return | |
7877 | * one type, we chose the biggest type (u64) and zero-extend the return value | |
7878 | * to that size. Note that the caller, handle_vmread, might need to use only | |
7879 | * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of | |
7880 | * 64-bit fields are to be returned). | |
7881 | */ | |
a2ae9df7 PB |
7882 | static inline int vmcs12_read_any(struct kvm_vcpu *vcpu, |
7883 | unsigned long field, u64 *ret) | |
49f705c5 NHE |
7884 | { |
7885 | short offset = vmcs_field_to_offset(field); | |
7886 | char *p; | |
7887 | ||
7888 | if (offset < 0) | |
a2ae9df7 | 7889 | return offset; |
49f705c5 NHE |
7890 | |
7891 | p = ((char *)(get_vmcs12(vcpu))) + offset; | |
7892 | ||
d37f4267 JM |
7893 | switch (vmcs_field_width(field)) { |
7894 | case VMCS_FIELD_WIDTH_NATURAL_WIDTH: | |
49f705c5 | 7895 | *ret = *((natural_width *)p); |
a2ae9df7 | 7896 | return 0; |
d37f4267 | 7897 | case VMCS_FIELD_WIDTH_U16: |
49f705c5 | 7898 | *ret = *((u16 *)p); |
a2ae9df7 | 7899 | return 0; |
d37f4267 | 7900 | case VMCS_FIELD_WIDTH_U32: |
49f705c5 | 7901 | *ret = *((u32 *)p); |
a2ae9df7 | 7902 | return 0; |
d37f4267 | 7903 | case VMCS_FIELD_WIDTH_U64: |
49f705c5 | 7904 | *ret = *((u64 *)p); |
a2ae9df7 | 7905 | return 0; |
49f705c5 | 7906 | default: |
a2ae9df7 PB |
7907 | WARN_ON(1); |
7908 | return -ENOENT; | |
49f705c5 NHE |
7909 | } |
7910 | } | |
7911 | ||
20b97fea | 7912 | |
a2ae9df7 PB |
7913 | static inline int vmcs12_write_any(struct kvm_vcpu *vcpu, |
7914 | unsigned long field, u64 field_value){ | |
20b97fea AG |
7915 | short offset = vmcs_field_to_offset(field); |
7916 | char *p = ((char *) get_vmcs12(vcpu)) + offset; | |
7917 | if (offset < 0) | |
a2ae9df7 | 7918 | return offset; |
20b97fea | 7919 | |
d37f4267 JM |
7920 | switch (vmcs_field_width(field)) { |
7921 | case VMCS_FIELD_WIDTH_U16: | |
20b97fea | 7922 | *(u16 *)p = field_value; |
a2ae9df7 | 7923 | return 0; |
d37f4267 | 7924 | case VMCS_FIELD_WIDTH_U32: |
20b97fea | 7925 | *(u32 *)p = field_value; |
a2ae9df7 | 7926 | return 0; |
d37f4267 | 7927 | case VMCS_FIELD_WIDTH_U64: |
20b97fea | 7928 | *(u64 *)p = field_value; |
a2ae9df7 | 7929 | return 0; |
d37f4267 | 7930 | case VMCS_FIELD_WIDTH_NATURAL_WIDTH: |
20b97fea | 7931 | *(natural_width *)p = field_value; |
a2ae9df7 | 7932 | return 0; |
20b97fea | 7933 | default: |
a2ae9df7 PB |
7934 | WARN_ON(1); |
7935 | return -ENOENT; | |
20b97fea AG |
7936 | } |
7937 | ||
7938 | } | |
7939 | ||
16f5b903 AG |
7940 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) |
7941 | { | |
7942 | int i; | |
7943 | unsigned long field; | |
7944 | u64 field_value; | |
355f4fb1 | 7945 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
44900ba6 | 7946 | const u16 *fields = shadow_read_write_fields; |
c2bae893 | 7947 | const int num_fields = max_shadow_read_write_fields; |
16f5b903 | 7948 | |
282da870 JK |
7949 | preempt_disable(); |
7950 | ||
16f5b903 AG |
7951 | vmcs_load(shadow_vmcs); |
7952 | ||
7953 | for (i = 0; i < num_fields; i++) { | |
7954 | field = fields[i]; | |
44900ba6 | 7955 | field_value = __vmcs_readl(field); |
16f5b903 AG |
7956 | vmcs12_write_any(&vmx->vcpu, field, field_value); |
7957 | } | |
7958 | ||
7959 | vmcs_clear(shadow_vmcs); | |
7960 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
282da870 JK |
7961 | |
7962 | preempt_enable(); | |
16f5b903 AG |
7963 | } |
7964 | ||
c3114420 AG |
7965 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) |
7966 | { | |
44900ba6 | 7967 | const u16 *fields[] = { |
c2bae893 MK |
7968 | shadow_read_write_fields, |
7969 | shadow_read_only_fields | |
c3114420 | 7970 | }; |
c2bae893 | 7971 | const int max_fields[] = { |
c3114420 AG |
7972 | max_shadow_read_write_fields, |
7973 | max_shadow_read_only_fields | |
7974 | }; | |
7975 | int i, q; | |
7976 | unsigned long field; | |
7977 | u64 field_value = 0; | |
355f4fb1 | 7978 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c3114420 AG |
7979 | |
7980 | vmcs_load(shadow_vmcs); | |
7981 | ||
c2bae893 | 7982 | for (q = 0; q < ARRAY_SIZE(fields); q++) { |
c3114420 AG |
7983 | for (i = 0; i < max_fields[q]; i++) { |
7984 | field = fields[q][i]; | |
7985 | vmcs12_read_any(&vmx->vcpu, field, &field_value); | |
44900ba6 | 7986 | __vmcs_writel(field, field_value); |
c3114420 AG |
7987 | } |
7988 | } | |
7989 | ||
7990 | vmcs_clear(shadow_vmcs); | |
7991 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
7992 | } | |
7993 | ||
49f705c5 NHE |
7994 | /* |
7995 | * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was | |
7996 | * used before) all generate the same failure when it is missing. | |
7997 | */ | |
7998 | static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu) | |
7999 | { | |
8000 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8001 | if (vmx->nested.current_vmptr == -1ull) { | |
8002 | nested_vmx_failInvalid(vcpu); | |
49f705c5 NHE |
8003 | return 0; |
8004 | } | |
8005 | return 1; | |
8006 | } | |
8007 | ||
8008 | static int handle_vmread(struct kvm_vcpu *vcpu) | |
8009 | { | |
8010 | unsigned long field; | |
8011 | u64 field_value; | |
8012 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8013 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
8014 | gva_t gva = 0; | |
8015 | ||
eb277562 | 8016 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
8017 | return 1; |
8018 | ||
6affcbed KH |
8019 | if (!nested_vmx_check_vmcs12(vcpu)) |
8020 | return kvm_skip_emulated_instruction(vcpu); | |
49f705c5 NHE |
8021 | |
8022 | /* Decode instruction info and find the field to read */ | |
27e6fb5d | 8023 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 | 8024 | /* Read the field, zero-extended to a u64 field_value */ |
a2ae9df7 | 8025 | if (vmcs12_read_any(vcpu, field, &field_value) < 0) { |
49f705c5 | 8026 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 8027 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
8028 | } |
8029 | /* | |
8030 | * Now copy part of this value to register or memory, as requested. | |
8031 | * Note that the number of bits actually copied is 32 or 64 depending | |
8032 | * on the guest's mode (32 or 64 bit), not on the given field's length. | |
8033 | */ | |
8034 | if (vmx_instruction_info & (1u << 10)) { | |
27e6fb5d | 8035 | kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf), |
49f705c5 NHE |
8036 | field_value); |
8037 | } else { | |
8038 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 8039 | vmx_instruction_info, true, &gva)) |
49f705c5 | 8040 | return 1; |
70f3aac9 | 8041 | /* _system ok, as hardware has verified cpl=0 */ |
49f705c5 NHE |
8042 | kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva, |
8043 | &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL); | |
8044 | } | |
8045 | ||
8046 | nested_vmx_succeed(vcpu); | |
6affcbed | 8047 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
8048 | } |
8049 | ||
8050 | ||
8051 | static int handle_vmwrite(struct kvm_vcpu *vcpu) | |
8052 | { | |
8053 | unsigned long field; | |
8054 | gva_t gva; | |
74a497fa | 8055 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
49f705c5 NHE |
8056 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
8057 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
74a497fa | 8058 | |
49f705c5 NHE |
8059 | /* The value to write might be 32 or 64 bits, depending on L1's long |
8060 | * mode, and eventually we need to write that into a field of several | |
8061 | * possible lengths. The code below first zero-extends the value to 64 | |
6a6256f9 | 8062 | * bit (field_value), and then copies only the appropriate number of |
49f705c5 NHE |
8063 | * bits into the vmcs12 field. |
8064 | */ | |
8065 | u64 field_value = 0; | |
8066 | struct x86_exception e; | |
8067 | ||
eb277562 | 8068 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
8069 | return 1; |
8070 | ||
6affcbed KH |
8071 | if (!nested_vmx_check_vmcs12(vcpu)) |
8072 | return kvm_skip_emulated_instruction(vcpu); | |
eb277562 | 8073 | |
49f705c5 | 8074 | if (vmx_instruction_info & (1u << 10)) |
27e6fb5d | 8075 | field_value = kvm_register_readl(vcpu, |
49f705c5 NHE |
8076 | (((vmx_instruction_info) >> 3) & 0xf)); |
8077 | else { | |
8078 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 8079 | vmx_instruction_info, false, &gva)) |
49f705c5 NHE |
8080 | return 1; |
8081 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, | |
27e6fb5d | 8082 | &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) { |
49f705c5 NHE |
8083 | kvm_inject_page_fault(vcpu, &e); |
8084 | return 1; | |
8085 | } | |
8086 | } | |
8087 | ||
8088 | ||
27e6fb5d | 8089 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 NHE |
8090 | if (vmcs_field_readonly(field)) { |
8091 | nested_vmx_failValid(vcpu, | |
8092 | VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); | |
6affcbed | 8093 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
8094 | } |
8095 | ||
a2ae9df7 | 8096 | if (vmcs12_write_any(vcpu, field, field_value) < 0) { |
49f705c5 | 8097 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 8098 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
8099 | } |
8100 | ||
74a497fa PB |
8101 | switch (field) { |
8102 | #define SHADOW_FIELD_RW(x) case x: | |
8103 | #include "vmx_shadow_fields.h" | |
8104 | /* | |
8105 | * The fields that can be updated by L1 without a vmexit are | |
8106 | * always updated in the vmcs02, the others go down the slow | |
8107 | * path of prepare_vmcs02. | |
8108 | */ | |
8109 | break; | |
8110 | default: | |
8111 | vmx->nested.dirty_vmcs12 = true; | |
8112 | break; | |
8113 | } | |
8114 | ||
49f705c5 | 8115 | nested_vmx_succeed(vcpu); |
6affcbed | 8116 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
8117 | } |
8118 | ||
a8bc284e JM |
8119 | static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr) |
8120 | { | |
8121 | vmx->nested.current_vmptr = vmptr; | |
8122 | if (enable_shadow_vmcs) { | |
8123 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
8124 | SECONDARY_EXEC_SHADOW_VMCS); | |
8125 | vmcs_write64(VMCS_LINK_POINTER, | |
8126 | __pa(vmx->vmcs01.shadow_vmcs)); | |
8127 | vmx->nested.sync_shadow_vmcs = true; | |
8128 | } | |
74a497fa | 8129 | vmx->nested.dirty_vmcs12 = true; |
a8bc284e JM |
8130 | } |
8131 | ||
63846663 NHE |
8132 | /* Emulate the VMPTRLD instruction */ |
8133 | static int handle_vmptrld(struct kvm_vcpu *vcpu) | |
8134 | { | |
8135 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
63846663 | 8136 | gpa_t vmptr; |
63846663 NHE |
8137 | |
8138 | if (!nested_vmx_check_permission(vcpu)) | |
8139 | return 1; | |
8140 | ||
cbf71279 | 8141 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
63846663 | 8142 | return 1; |
63846663 | 8143 | |
cbf71279 RK |
8144 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { |
8145 | nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS); | |
8146 | return kvm_skip_emulated_instruction(vcpu); | |
8147 | } | |
8148 | ||
8149 | if (vmptr == vmx->nested.vmxon_ptr) { | |
8150 | nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER); | |
8151 | return kvm_skip_emulated_instruction(vcpu); | |
8152 | } | |
8153 | ||
63846663 NHE |
8154 | if (vmx->nested.current_vmptr != vmptr) { |
8155 | struct vmcs12 *new_vmcs12; | |
8156 | struct page *page; | |
5e2f30b7 DH |
8157 | page = kvm_vcpu_gpa_to_page(vcpu, vmptr); |
8158 | if (is_error_page(page)) { | |
63846663 | 8159 | nested_vmx_failInvalid(vcpu); |
6affcbed | 8160 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
8161 | } |
8162 | new_vmcs12 = kmap(page); | |
8163 | if (new_vmcs12->revision_id != VMCS12_REVISION) { | |
8164 | kunmap(page); | |
53a70daf | 8165 | kvm_release_page_clean(page); |
63846663 NHE |
8166 | nested_vmx_failValid(vcpu, |
8167 | VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); | |
6affcbed | 8168 | return kvm_skip_emulated_instruction(vcpu); |
63846663 | 8169 | } |
63846663 | 8170 | |
9a2a05b9 | 8171 | nested_release_vmcs12(vmx); |
4f2777bc DM |
8172 | /* |
8173 | * Load VMCS12 from guest memory since it is not already | |
8174 | * cached. | |
8175 | */ | |
9f744c59 PB |
8176 | memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE); |
8177 | kunmap(page); | |
53a70daf | 8178 | kvm_release_page_clean(page); |
9f744c59 | 8179 | |
a8bc284e | 8180 | set_current_vmptr(vmx, vmptr); |
63846663 NHE |
8181 | } |
8182 | ||
8183 | nested_vmx_succeed(vcpu); | |
6affcbed | 8184 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
8185 | } |
8186 | ||
6a4d7550 NHE |
8187 | /* Emulate the VMPTRST instruction */ |
8188 | static int handle_vmptrst(struct kvm_vcpu *vcpu) | |
8189 | { | |
8190 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8191 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
8192 | gva_t vmcs_gva; | |
8193 | struct x86_exception e; | |
8194 | ||
8195 | if (!nested_vmx_check_permission(vcpu)) | |
8196 | return 1; | |
8197 | ||
8198 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 8199 | vmx_instruction_info, true, &vmcs_gva)) |
6a4d7550 | 8200 | return 1; |
70f3aac9 | 8201 | /* ok to use *_system, as hardware has verified cpl=0 */ |
6a4d7550 NHE |
8202 | if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva, |
8203 | (void *)&to_vmx(vcpu)->nested.current_vmptr, | |
8204 | sizeof(u64), &e)) { | |
8205 | kvm_inject_page_fault(vcpu, &e); | |
8206 | return 1; | |
8207 | } | |
8208 | nested_vmx_succeed(vcpu); | |
6affcbed | 8209 | return kvm_skip_emulated_instruction(vcpu); |
6a4d7550 NHE |
8210 | } |
8211 | ||
bfd0a56b NHE |
8212 | /* Emulate the INVEPT instruction */ |
8213 | static int handle_invept(struct kvm_vcpu *vcpu) | |
8214 | { | |
b9c237bb | 8215 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
bfd0a56b NHE |
8216 | u32 vmx_instruction_info, types; |
8217 | unsigned long type; | |
8218 | gva_t gva; | |
8219 | struct x86_exception e; | |
8220 | struct { | |
8221 | u64 eptp, gpa; | |
8222 | } operand; | |
bfd0a56b | 8223 | |
6677f3da | 8224 | if (!(vmx->nested.msrs.secondary_ctls_high & |
b9c237bb | 8225 | SECONDARY_EXEC_ENABLE_EPT) || |
6677f3da | 8226 | !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) { |
bfd0a56b NHE |
8227 | kvm_queue_exception(vcpu, UD_VECTOR); |
8228 | return 1; | |
8229 | } | |
8230 | ||
8231 | if (!nested_vmx_check_permission(vcpu)) | |
8232 | return 1; | |
8233 | ||
bfd0a56b | 8234 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); |
27e6fb5d | 8235 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); |
bfd0a56b | 8236 | |
6677f3da | 8237 | types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; |
bfd0a56b | 8238 | |
85c856b3 | 8239 | if (type >= 32 || !(types & (1 << type))) { |
bfd0a56b NHE |
8240 | nested_vmx_failValid(vcpu, |
8241 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 8242 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
8243 | } |
8244 | ||
8245 | /* According to the Intel VMX instruction reference, the memory | |
8246 | * operand is read even if it isn't needed (e.g., for type==global) | |
8247 | */ | |
8248 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 8249 | vmx_instruction_info, false, &gva)) |
bfd0a56b NHE |
8250 | return 1; |
8251 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand, | |
8252 | sizeof(operand), &e)) { | |
8253 | kvm_inject_page_fault(vcpu, &e); | |
8254 | return 1; | |
8255 | } | |
8256 | ||
8257 | switch (type) { | |
bfd0a56b | 8258 | case VMX_EPT_EXTENT_GLOBAL: |
45e11817 BD |
8259 | /* |
8260 | * TODO: track mappings and invalidate | |
8261 | * single context requests appropriately | |
8262 | */ | |
8263 | case VMX_EPT_EXTENT_CONTEXT: | |
bfd0a56b | 8264 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 8265 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
bfd0a56b NHE |
8266 | nested_vmx_succeed(vcpu); |
8267 | break; | |
8268 | default: | |
8269 | BUG_ON(1); | |
8270 | break; | |
8271 | } | |
8272 | ||
6affcbed | 8273 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
8274 | } |
8275 | ||
a642fc30 PM |
8276 | static int handle_invvpid(struct kvm_vcpu *vcpu) |
8277 | { | |
99b83ac8 WL |
8278 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8279 | u32 vmx_instruction_info; | |
8280 | unsigned long type, types; | |
8281 | gva_t gva; | |
8282 | struct x86_exception e; | |
40352605 JM |
8283 | struct { |
8284 | u64 vpid; | |
8285 | u64 gla; | |
8286 | } operand; | |
99b83ac8 | 8287 | |
6677f3da | 8288 | if (!(vmx->nested.msrs.secondary_ctls_high & |
99b83ac8 | 8289 | SECONDARY_EXEC_ENABLE_VPID) || |
6677f3da | 8290 | !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) { |
99b83ac8 WL |
8291 | kvm_queue_exception(vcpu, UD_VECTOR); |
8292 | return 1; | |
8293 | } | |
8294 | ||
8295 | if (!nested_vmx_check_permission(vcpu)) | |
8296 | return 1; | |
8297 | ||
8298 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
8299 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); | |
8300 | ||
6677f3da | 8301 | types = (vmx->nested.msrs.vpid_caps & |
bcdde302 | 8302 | VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8; |
99b83ac8 | 8303 | |
85c856b3 | 8304 | if (type >= 32 || !(types & (1 << type))) { |
99b83ac8 WL |
8305 | nested_vmx_failValid(vcpu, |
8306 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 8307 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
8308 | } |
8309 | ||
8310 | /* according to the intel vmx instruction reference, the memory | |
8311 | * operand is read even if it isn't needed (e.g., for type==global) | |
8312 | */ | |
8313 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
8314 | vmx_instruction_info, false, &gva)) | |
8315 | return 1; | |
40352605 JM |
8316 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand, |
8317 | sizeof(operand), &e)) { | |
99b83ac8 WL |
8318 | kvm_inject_page_fault(vcpu, &e); |
8319 | return 1; | |
8320 | } | |
40352605 JM |
8321 | if (operand.vpid >> 16) { |
8322 | nested_vmx_failValid(vcpu, | |
8323 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
8324 | return kvm_skip_emulated_instruction(vcpu); | |
8325 | } | |
99b83ac8 WL |
8326 | |
8327 | switch (type) { | |
bcdde302 | 8328 | case VMX_VPID_EXTENT_INDIVIDUAL_ADDR: |
fd8cb433 | 8329 | if (is_noncanonical_address(operand.gla, vcpu)) { |
40352605 JM |
8330 | nested_vmx_failValid(vcpu, |
8331 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
8332 | return kvm_skip_emulated_instruction(vcpu); | |
8333 | } | |
8334 | /* fall through */ | |
ef697a71 | 8335 | case VMX_VPID_EXTENT_SINGLE_CONTEXT: |
bcdde302 | 8336 | case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL: |
40352605 | 8337 | if (!operand.vpid) { |
bcdde302 JD |
8338 | nested_vmx_failValid(vcpu, |
8339 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 8340 | return kvm_skip_emulated_instruction(vcpu); |
bcdde302 JD |
8341 | } |
8342 | break; | |
99b83ac8 | 8343 | case VMX_VPID_EXTENT_ALL_CONTEXT: |
99b83ac8 WL |
8344 | break; |
8345 | default: | |
bcdde302 | 8346 | WARN_ON_ONCE(1); |
6affcbed | 8347 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
8348 | } |
8349 | ||
c2ba05cc | 8350 | __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true); |
bcdde302 JD |
8351 | nested_vmx_succeed(vcpu); |
8352 | ||
6affcbed | 8353 | return kvm_skip_emulated_instruction(vcpu); |
a642fc30 PM |
8354 | } |
8355 | ||
843e4330 KH |
8356 | static int handle_pml_full(struct kvm_vcpu *vcpu) |
8357 | { | |
8358 | unsigned long exit_qualification; | |
8359 | ||
8360 | trace_kvm_pml_full(vcpu->vcpu_id); | |
8361 | ||
8362 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8363 | ||
8364 | /* | |
8365 | * PML buffer FULL happened while executing iret from NMI, | |
8366 | * "blocked by NMI" bit has to be set before next VM entry. | |
8367 | */ | |
8368 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && | |
d02fcf50 | 8369 | enable_vnmi && |
843e4330 KH |
8370 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
8371 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
8372 | GUEST_INTR_STATE_NMI); | |
8373 | ||
8374 | /* | |
8375 | * PML buffer already flushed at beginning of VMEXIT. Nothing to do | |
8376 | * here.., and there's no userspace involvement needed for PML. | |
8377 | */ | |
8378 | return 1; | |
8379 | } | |
8380 | ||
64672c95 YJ |
8381 | static int handle_preemption_timer(struct kvm_vcpu *vcpu) |
8382 | { | |
8383 | kvm_lapic_expired_hv_timer(vcpu); | |
8384 | return 1; | |
8385 | } | |
8386 | ||
41ab9372 BD |
8387 | static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address) |
8388 | { | |
8389 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
41ab9372 BD |
8390 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
8391 | ||
8392 | /* Check for memory type validity */ | |
bb97a016 DH |
8393 | switch (address & VMX_EPTP_MT_MASK) { |
8394 | case VMX_EPTP_MT_UC: | |
6677f3da | 8395 | if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT)) |
41ab9372 BD |
8396 | return false; |
8397 | break; | |
bb97a016 | 8398 | case VMX_EPTP_MT_WB: |
6677f3da | 8399 | if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT)) |
41ab9372 BD |
8400 | return false; |
8401 | break; | |
8402 | default: | |
8403 | return false; | |
8404 | } | |
8405 | ||
bb97a016 DH |
8406 | /* only 4 levels page-walk length are valid */ |
8407 | if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4) | |
41ab9372 BD |
8408 | return false; |
8409 | ||
8410 | /* Reserved bits should not be set */ | |
8411 | if (address >> maxphyaddr || ((address >> 7) & 0x1f)) | |
8412 | return false; | |
8413 | ||
8414 | /* AD, if set, should be supported */ | |
bb97a016 | 8415 | if (address & VMX_EPTP_AD_ENABLE_BIT) { |
6677f3da | 8416 | if (!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT)) |
41ab9372 BD |
8417 | return false; |
8418 | } | |
8419 | ||
8420 | return true; | |
8421 | } | |
8422 | ||
8423 | static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu, | |
8424 | struct vmcs12 *vmcs12) | |
8425 | { | |
8426 | u32 index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
8427 | u64 address; | |
8428 | bool accessed_dirty; | |
8429 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; | |
8430 | ||
8431 | if (!nested_cpu_has_eptp_switching(vmcs12) || | |
8432 | !nested_cpu_has_ept(vmcs12)) | |
8433 | return 1; | |
8434 | ||
8435 | if (index >= VMFUNC_EPTP_ENTRIES) | |
8436 | return 1; | |
8437 | ||
8438 | ||
8439 | if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT, | |
8440 | &address, index * 8, 8)) | |
8441 | return 1; | |
8442 | ||
bb97a016 | 8443 | accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT); |
41ab9372 BD |
8444 | |
8445 | /* | |
8446 | * If the (L2) guest does a vmfunc to the currently | |
8447 | * active ept pointer, we don't have to do anything else | |
8448 | */ | |
8449 | if (vmcs12->ept_pointer != address) { | |
8450 | if (!valid_ept_address(vcpu, address)) | |
8451 | return 1; | |
8452 | ||
8453 | kvm_mmu_unload(vcpu); | |
8454 | mmu->ept_ad = accessed_dirty; | |
8455 | mmu->base_role.ad_disabled = !accessed_dirty; | |
8456 | vmcs12->ept_pointer = address; | |
8457 | /* | |
8458 | * TODO: Check what's the correct approach in case | |
8459 | * mmu reload fails. Currently, we just let the next | |
8460 | * reload potentially fail | |
8461 | */ | |
8462 | kvm_mmu_reload(vcpu); | |
8463 | } | |
8464 | ||
8465 | return 0; | |
8466 | } | |
8467 | ||
2a499e49 BD |
8468 | static int handle_vmfunc(struct kvm_vcpu *vcpu) |
8469 | { | |
27c42a1b BD |
8470 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8471 | struct vmcs12 *vmcs12; | |
8472 | u32 function = vcpu->arch.regs[VCPU_REGS_RAX]; | |
8473 | ||
8474 | /* | |
8475 | * VMFUNC is only supported for nested guests, but we always enable the | |
8476 | * secondary control for simplicity; for non-nested mode, fake that we | |
8477 | * didn't by injecting #UD. | |
8478 | */ | |
8479 | if (!is_guest_mode(vcpu)) { | |
8480 | kvm_queue_exception(vcpu, UD_VECTOR); | |
8481 | return 1; | |
8482 | } | |
8483 | ||
8484 | vmcs12 = get_vmcs12(vcpu); | |
8485 | if ((vmcs12->vm_function_control & (1 << function)) == 0) | |
8486 | goto fail; | |
41ab9372 BD |
8487 | |
8488 | switch (function) { | |
8489 | case 0: | |
8490 | if (nested_vmx_eptp_switching(vcpu, vmcs12)) | |
8491 | goto fail; | |
8492 | break; | |
8493 | default: | |
8494 | goto fail; | |
8495 | } | |
8496 | return kvm_skip_emulated_instruction(vcpu); | |
27c42a1b BD |
8497 | |
8498 | fail: | |
8499 | nested_vmx_vmexit(vcpu, vmx->exit_reason, | |
8500 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8501 | vmcs_readl(EXIT_QUALIFICATION)); | |
2a499e49 BD |
8502 | return 1; |
8503 | } | |
8504 | ||
6aa8b732 AK |
8505 | /* |
8506 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
8507 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
8508 | * to be done to userspace and return 0. | |
8509 | */ | |
772e0318 | 8510 | static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
8511 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
8512 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 8513 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 8514 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 8515 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
8516 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
8517 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
8518 | [EXIT_REASON_CPUID] = handle_cpuid, | |
8519 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
8520 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
8521 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
8522 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 8523 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 8524 | [EXIT_REASON_INVLPG] = handle_invlpg, |
fee84b07 | 8525 | [EXIT_REASON_RDPMC] = handle_rdpmc, |
c21415e8 | 8526 | [EXIT_REASON_VMCALL] = handle_vmcall, |
27d6c865 | 8527 | [EXIT_REASON_VMCLEAR] = handle_vmclear, |
cd232ad0 | 8528 | [EXIT_REASON_VMLAUNCH] = handle_vmlaunch, |
63846663 | 8529 | [EXIT_REASON_VMPTRLD] = handle_vmptrld, |
6a4d7550 | 8530 | [EXIT_REASON_VMPTRST] = handle_vmptrst, |
49f705c5 | 8531 | [EXIT_REASON_VMREAD] = handle_vmread, |
cd232ad0 | 8532 | [EXIT_REASON_VMRESUME] = handle_vmresume, |
49f705c5 | 8533 | [EXIT_REASON_VMWRITE] = handle_vmwrite, |
ec378aee NHE |
8534 | [EXIT_REASON_VMOFF] = handle_vmoff, |
8535 | [EXIT_REASON_VMON] = handle_vmon, | |
f78e0e2e SY |
8536 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
8537 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
83d4c286 | 8538 | [EXIT_REASON_APIC_WRITE] = handle_apic_write, |
c7c9c56c | 8539 | [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, |
e5edaa01 | 8540 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 8541 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 8542 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 8543 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
0367f205 PB |
8544 | [EXIT_REASON_GDTR_IDTR] = handle_desc, |
8545 | [EXIT_REASON_LDTR_TR] = handle_desc, | |
68f89400 MT |
8546 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
8547 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 8548 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
87c00572 | 8549 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, |
5f3d45e7 | 8550 | [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, |
87c00572 | 8551 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, |
bfd0a56b | 8552 | [EXIT_REASON_INVEPT] = handle_invept, |
a642fc30 | 8553 | [EXIT_REASON_INVVPID] = handle_invvpid, |
45ec368c | 8554 | [EXIT_REASON_RDRAND] = handle_invalid_op, |
75f4fc8d | 8555 | [EXIT_REASON_RDSEED] = handle_invalid_op, |
f53cd63c WL |
8556 | [EXIT_REASON_XSAVES] = handle_xsaves, |
8557 | [EXIT_REASON_XRSTORS] = handle_xrstors, | |
843e4330 | 8558 | [EXIT_REASON_PML_FULL] = handle_pml_full, |
2a499e49 | 8559 | [EXIT_REASON_VMFUNC] = handle_vmfunc, |
64672c95 | 8560 | [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, |
6aa8b732 AK |
8561 | }; |
8562 | ||
8563 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 8564 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 8565 | |
908a7bdd JK |
8566 | static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, |
8567 | struct vmcs12 *vmcs12) | |
8568 | { | |
8569 | unsigned long exit_qualification; | |
8570 | gpa_t bitmap, last_bitmap; | |
8571 | unsigned int port; | |
8572 | int size; | |
8573 | u8 b; | |
8574 | ||
908a7bdd | 8575 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) |
2f0a6397 | 8576 | return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); |
908a7bdd JK |
8577 | |
8578 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8579 | ||
8580 | port = exit_qualification >> 16; | |
8581 | size = (exit_qualification & 7) + 1; | |
8582 | ||
8583 | last_bitmap = (gpa_t)-1; | |
8584 | b = -1; | |
8585 | ||
8586 | while (size > 0) { | |
8587 | if (port < 0x8000) | |
8588 | bitmap = vmcs12->io_bitmap_a; | |
8589 | else if (port < 0x10000) | |
8590 | bitmap = vmcs12->io_bitmap_b; | |
8591 | else | |
1d804d07 | 8592 | return true; |
908a7bdd JK |
8593 | bitmap += (port & 0x7fff) / 8; |
8594 | ||
8595 | if (last_bitmap != bitmap) | |
54bf36aa | 8596 | if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1)) |
1d804d07 | 8597 | return true; |
908a7bdd | 8598 | if (b & (1 << (port & 7))) |
1d804d07 | 8599 | return true; |
908a7bdd JK |
8600 | |
8601 | port++; | |
8602 | size--; | |
8603 | last_bitmap = bitmap; | |
8604 | } | |
8605 | ||
1d804d07 | 8606 | return false; |
908a7bdd JK |
8607 | } |
8608 | ||
644d711a NHE |
8609 | /* |
8610 | * Return 1 if we should exit from L2 to L1 to handle an MSR access access, | |
8611 | * rather than handle it ourselves in L0. I.e., check whether L1 expressed | |
8612 | * disinterest in the current event (read or write a specific MSR) by using an | |
8613 | * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. | |
8614 | */ | |
8615 | static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, | |
8616 | struct vmcs12 *vmcs12, u32 exit_reason) | |
8617 | { | |
8618 | u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
8619 | gpa_t bitmap; | |
8620 | ||
cbd29cb6 | 8621 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
1d804d07 | 8622 | return true; |
644d711a NHE |
8623 | |
8624 | /* | |
8625 | * The MSR_BITMAP page is divided into four 1024-byte bitmaps, | |
8626 | * for the four combinations of read/write and low/high MSR numbers. | |
8627 | * First we need to figure out which of the four to use: | |
8628 | */ | |
8629 | bitmap = vmcs12->msr_bitmap; | |
8630 | if (exit_reason == EXIT_REASON_MSR_WRITE) | |
8631 | bitmap += 2048; | |
8632 | if (msr_index >= 0xc0000000) { | |
8633 | msr_index -= 0xc0000000; | |
8634 | bitmap += 1024; | |
8635 | } | |
8636 | ||
8637 | /* Then read the msr_index'th bit from this bitmap: */ | |
8638 | if (msr_index < 1024*8) { | |
8639 | unsigned char b; | |
54bf36aa | 8640 | if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1)) |
1d804d07 | 8641 | return true; |
644d711a NHE |
8642 | return 1 & (b >> (msr_index & 7)); |
8643 | } else | |
1d804d07 | 8644 | return true; /* let L1 handle the wrong parameter */ |
644d711a NHE |
8645 | } |
8646 | ||
8647 | /* | |
8648 | * Return 1 if we should exit from L2 to L1 to handle a CR access exit, | |
8649 | * rather than handle it ourselves in L0. I.e., check if L1 wanted to | |
8650 | * intercept (via guest_host_mask etc.) the current event. | |
8651 | */ | |
8652 | static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, | |
8653 | struct vmcs12 *vmcs12) | |
8654 | { | |
8655 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8656 | int cr = exit_qualification & 15; | |
e1d39b17 JS |
8657 | int reg; |
8658 | unsigned long val; | |
644d711a NHE |
8659 | |
8660 | switch ((exit_qualification >> 4) & 3) { | |
8661 | case 0: /* mov to cr */ | |
e1d39b17 JS |
8662 | reg = (exit_qualification >> 8) & 15; |
8663 | val = kvm_register_readl(vcpu, reg); | |
644d711a NHE |
8664 | switch (cr) { |
8665 | case 0: | |
8666 | if (vmcs12->cr0_guest_host_mask & | |
8667 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 8668 | return true; |
644d711a NHE |
8669 | break; |
8670 | case 3: | |
8671 | if ((vmcs12->cr3_target_count >= 1 && | |
8672 | vmcs12->cr3_target_value0 == val) || | |
8673 | (vmcs12->cr3_target_count >= 2 && | |
8674 | vmcs12->cr3_target_value1 == val) || | |
8675 | (vmcs12->cr3_target_count >= 3 && | |
8676 | vmcs12->cr3_target_value2 == val) || | |
8677 | (vmcs12->cr3_target_count >= 4 && | |
8678 | vmcs12->cr3_target_value3 == val)) | |
1d804d07 | 8679 | return false; |
644d711a | 8680 | if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) |
1d804d07 | 8681 | return true; |
644d711a NHE |
8682 | break; |
8683 | case 4: | |
8684 | if (vmcs12->cr4_guest_host_mask & | |
8685 | (vmcs12->cr4_read_shadow ^ val)) | |
1d804d07 | 8686 | return true; |
644d711a NHE |
8687 | break; |
8688 | case 8: | |
8689 | if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) | |
1d804d07 | 8690 | return true; |
644d711a NHE |
8691 | break; |
8692 | } | |
8693 | break; | |
8694 | case 2: /* clts */ | |
8695 | if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && | |
8696 | (vmcs12->cr0_read_shadow & X86_CR0_TS)) | |
1d804d07 | 8697 | return true; |
644d711a NHE |
8698 | break; |
8699 | case 1: /* mov from cr */ | |
8700 | switch (cr) { | |
8701 | case 3: | |
8702 | if (vmcs12->cpu_based_vm_exec_control & | |
8703 | CPU_BASED_CR3_STORE_EXITING) | |
1d804d07 | 8704 | return true; |
644d711a NHE |
8705 | break; |
8706 | case 8: | |
8707 | if (vmcs12->cpu_based_vm_exec_control & | |
8708 | CPU_BASED_CR8_STORE_EXITING) | |
1d804d07 | 8709 | return true; |
644d711a NHE |
8710 | break; |
8711 | } | |
8712 | break; | |
8713 | case 3: /* lmsw */ | |
8714 | /* | |
8715 | * lmsw can change bits 1..3 of cr0, and only set bit 0 of | |
8716 | * cr0. Other attempted changes are ignored, with no exit. | |
8717 | */ | |
e1d39b17 | 8718 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
644d711a NHE |
8719 | if (vmcs12->cr0_guest_host_mask & 0xe & |
8720 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 8721 | return true; |
644d711a NHE |
8722 | if ((vmcs12->cr0_guest_host_mask & 0x1) && |
8723 | !(vmcs12->cr0_read_shadow & 0x1) && | |
8724 | (val & 0x1)) | |
1d804d07 | 8725 | return true; |
644d711a NHE |
8726 | break; |
8727 | } | |
1d804d07 | 8728 | return false; |
644d711a NHE |
8729 | } |
8730 | ||
8731 | /* | |
8732 | * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we | |
8733 | * should handle it ourselves in L0 (and then continue L2). Only call this | |
8734 | * when in is_guest_mode (L2). | |
8735 | */ | |
7313c698 | 8736 | static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason) |
644d711a | 8737 | { |
644d711a NHE |
8738 | u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
8739 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8740 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
8741 | ||
4f350c6d JM |
8742 | if (vmx->nested.nested_run_pending) |
8743 | return false; | |
8744 | ||
8745 | if (unlikely(vmx->fail)) { | |
8746 | pr_info_ratelimited("%s failed vm entry %x\n", __func__, | |
8747 | vmcs_read32(VM_INSTRUCTION_ERROR)); | |
8748 | return true; | |
8749 | } | |
542060ea | 8750 | |
c9f04407 DM |
8751 | /* |
8752 | * The host physical addresses of some pages of guest memory | |
de3a0021 JM |
8753 | * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC |
8754 | * Page). The CPU may write to these pages via their host | |
8755 | * physical address while L2 is running, bypassing any | |
8756 | * address-translation-based dirty tracking (e.g. EPT write | |
8757 | * protection). | |
c9f04407 DM |
8758 | * |
8759 | * Mark them dirty on every exit from L2 to prevent them from | |
8760 | * getting out of sync with dirty tracking. | |
8761 | */ | |
8762 | nested_mark_vmcs12_pages_dirty(vcpu); | |
8763 | ||
4f350c6d JM |
8764 | trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason, |
8765 | vmcs_readl(EXIT_QUALIFICATION), | |
8766 | vmx->idt_vectoring_info, | |
8767 | intr_info, | |
8768 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8769 | KVM_ISA_VMX); | |
644d711a NHE |
8770 | |
8771 | switch (exit_reason) { | |
8772 | case EXIT_REASON_EXCEPTION_NMI: | |
ef85b673 | 8773 | if (is_nmi(intr_info)) |
1d804d07 | 8774 | return false; |
644d711a | 8775 | else if (is_page_fault(intr_info)) |
52a5c155 | 8776 | return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept; |
e504c909 | 8777 | else if (is_no_device(intr_info) && |
ccf9844e | 8778 | !(vmcs12->guest_cr0 & X86_CR0_TS)) |
1d804d07 | 8779 | return false; |
6f05485d JK |
8780 | else if (is_debug(intr_info) && |
8781 | vcpu->guest_debug & | |
8782 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
8783 | return false; | |
8784 | else if (is_breakpoint(intr_info) && | |
8785 | vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
8786 | return false; | |
644d711a NHE |
8787 | return vmcs12->exception_bitmap & |
8788 | (1u << (intr_info & INTR_INFO_VECTOR_MASK)); | |
8789 | case EXIT_REASON_EXTERNAL_INTERRUPT: | |
1d804d07 | 8790 | return false; |
644d711a | 8791 | case EXIT_REASON_TRIPLE_FAULT: |
1d804d07 | 8792 | return true; |
644d711a | 8793 | case EXIT_REASON_PENDING_INTERRUPT: |
3b656cf7 | 8794 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING); |
644d711a | 8795 | case EXIT_REASON_NMI_WINDOW: |
3b656cf7 | 8796 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING); |
644d711a | 8797 | case EXIT_REASON_TASK_SWITCH: |
1d804d07 | 8798 | return true; |
644d711a | 8799 | case EXIT_REASON_CPUID: |
1d804d07 | 8800 | return true; |
644d711a NHE |
8801 | case EXIT_REASON_HLT: |
8802 | return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); | |
8803 | case EXIT_REASON_INVD: | |
1d804d07 | 8804 | return true; |
644d711a NHE |
8805 | case EXIT_REASON_INVLPG: |
8806 | return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
8807 | case EXIT_REASON_RDPMC: | |
8808 | return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); | |
a5f46457 | 8809 | case EXIT_REASON_RDRAND: |
736fdf72 | 8810 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING); |
a5f46457 | 8811 | case EXIT_REASON_RDSEED: |
736fdf72 | 8812 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING); |
b3a2a907 | 8813 | case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP: |
644d711a NHE |
8814 | return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); |
8815 | case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: | |
8816 | case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: | |
8817 | case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD: | |
8818 | case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE: | |
8819 | case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: | |
a642fc30 | 8820 | case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: |
644d711a NHE |
8821 | /* |
8822 | * VMX instructions trap unconditionally. This allows L1 to | |
8823 | * emulate them for its L2 guest, i.e., allows 3-level nesting! | |
8824 | */ | |
1d804d07 | 8825 | return true; |
644d711a NHE |
8826 | case EXIT_REASON_CR_ACCESS: |
8827 | return nested_vmx_exit_handled_cr(vcpu, vmcs12); | |
8828 | case EXIT_REASON_DR_ACCESS: | |
8829 | return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); | |
8830 | case EXIT_REASON_IO_INSTRUCTION: | |
908a7bdd | 8831 | return nested_vmx_exit_handled_io(vcpu, vmcs12); |
1b07304c PB |
8832 | case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR: |
8833 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC); | |
644d711a NHE |
8834 | case EXIT_REASON_MSR_READ: |
8835 | case EXIT_REASON_MSR_WRITE: | |
8836 | return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); | |
8837 | case EXIT_REASON_INVALID_STATE: | |
1d804d07 | 8838 | return true; |
644d711a NHE |
8839 | case EXIT_REASON_MWAIT_INSTRUCTION: |
8840 | return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); | |
5f3d45e7 MD |
8841 | case EXIT_REASON_MONITOR_TRAP_FLAG: |
8842 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); | |
644d711a NHE |
8843 | case EXIT_REASON_MONITOR_INSTRUCTION: |
8844 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); | |
8845 | case EXIT_REASON_PAUSE_INSTRUCTION: | |
8846 | return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || | |
8847 | nested_cpu_has2(vmcs12, | |
8848 | SECONDARY_EXEC_PAUSE_LOOP_EXITING); | |
8849 | case EXIT_REASON_MCE_DURING_VMENTRY: | |
1d804d07 | 8850 | return false; |
644d711a | 8851 | case EXIT_REASON_TPR_BELOW_THRESHOLD: |
a7c0b07d | 8852 | return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); |
644d711a NHE |
8853 | case EXIT_REASON_APIC_ACCESS: |
8854 | return nested_cpu_has2(vmcs12, | |
8855 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
82f0dd4b | 8856 | case EXIT_REASON_APIC_WRITE: |
608406e2 WV |
8857 | case EXIT_REASON_EOI_INDUCED: |
8858 | /* apic_write and eoi_induced should exit unconditionally. */ | |
1d804d07 | 8859 | return true; |
644d711a | 8860 | case EXIT_REASON_EPT_VIOLATION: |
2b1be677 NHE |
8861 | /* |
8862 | * L0 always deals with the EPT violation. If nested EPT is | |
8863 | * used, and the nested mmu code discovers that the address is | |
8864 | * missing in the guest EPT table (EPT12), the EPT violation | |
8865 | * will be injected with nested_ept_inject_page_fault() | |
8866 | */ | |
1d804d07 | 8867 | return false; |
644d711a | 8868 | case EXIT_REASON_EPT_MISCONFIG: |
2b1be677 NHE |
8869 | /* |
8870 | * L2 never uses directly L1's EPT, but rather L0's own EPT | |
8871 | * table (shadow on EPT) or a merged EPT table that L0 built | |
8872 | * (EPT on EPT). So any problems with the structure of the | |
8873 | * table is L0's fault. | |
8874 | */ | |
1d804d07 | 8875 | return false; |
90a2db6d PB |
8876 | case EXIT_REASON_INVPCID: |
8877 | return | |
8878 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) && | |
8879 | nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
644d711a NHE |
8880 | case EXIT_REASON_WBINVD: |
8881 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); | |
8882 | case EXIT_REASON_XSETBV: | |
1d804d07 | 8883 | return true; |
81dc01f7 WL |
8884 | case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: |
8885 | /* | |
8886 | * This should never happen, since it is not possible to | |
8887 | * set XSS to a non-zero value---neither in L1 nor in L2. | |
8888 | * If if it were, XSS would have to be checked against | |
8889 | * the XSS exit bitmap in vmcs12. | |
8890 | */ | |
8891 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); | |
55123e3c WL |
8892 | case EXIT_REASON_PREEMPTION_TIMER: |
8893 | return false; | |
ab007cc9 | 8894 | case EXIT_REASON_PML_FULL: |
03efce6f | 8895 | /* We emulate PML support to L1. */ |
ab007cc9 | 8896 | return false; |
2a499e49 BD |
8897 | case EXIT_REASON_VMFUNC: |
8898 | /* VM functions are emulated through L2->L0 vmexits. */ | |
8899 | return false; | |
644d711a | 8900 | default: |
1d804d07 | 8901 | return true; |
644d711a NHE |
8902 | } |
8903 | } | |
8904 | ||
7313c698 PB |
8905 | static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason) |
8906 | { | |
8907 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
8908 | ||
8909 | /* | |
8910 | * At this point, the exit interruption info in exit_intr_info | |
8911 | * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT | |
8912 | * we need to query the in-kernel LAPIC. | |
8913 | */ | |
8914 | WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT); | |
8915 | if ((exit_intr_info & | |
8916 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) == | |
8917 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) { | |
8918 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
8919 | vmcs12->vm_exit_intr_error_code = | |
8920 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
8921 | } | |
8922 | ||
8923 | nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info, | |
8924 | vmcs_readl(EXIT_QUALIFICATION)); | |
8925 | return 1; | |
8926 | } | |
8927 | ||
586f9607 AK |
8928 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
8929 | { | |
8930 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
8931 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
8932 | } | |
8933 | ||
a3eaa864 | 8934 | static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) |
843e4330 | 8935 | { |
a3eaa864 KH |
8936 | if (vmx->pml_pg) { |
8937 | __free_page(vmx->pml_pg); | |
8938 | vmx->pml_pg = NULL; | |
8939 | } | |
843e4330 KH |
8940 | } |
8941 | ||
54bf36aa | 8942 | static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) |
843e4330 | 8943 | { |
54bf36aa | 8944 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
843e4330 KH |
8945 | u64 *pml_buf; |
8946 | u16 pml_idx; | |
8947 | ||
8948 | pml_idx = vmcs_read16(GUEST_PML_INDEX); | |
8949 | ||
8950 | /* Do nothing if PML buffer is empty */ | |
8951 | if (pml_idx == (PML_ENTITY_NUM - 1)) | |
8952 | return; | |
8953 | ||
8954 | /* PML index always points to next available PML buffer entity */ | |
8955 | if (pml_idx >= PML_ENTITY_NUM) | |
8956 | pml_idx = 0; | |
8957 | else | |
8958 | pml_idx++; | |
8959 | ||
8960 | pml_buf = page_address(vmx->pml_pg); | |
8961 | for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { | |
8962 | u64 gpa; | |
8963 | ||
8964 | gpa = pml_buf[pml_idx]; | |
8965 | WARN_ON(gpa & (PAGE_SIZE - 1)); | |
54bf36aa | 8966 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
843e4330 KH |
8967 | } |
8968 | ||
8969 | /* reset PML index */ | |
8970 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
8971 | } | |
8972 | ||
8973 | /* | |
8974 | * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. | |
8975 | * Called before reporting dirty_bitmap to userspace. | |
8976 | */ | |
8977 | static void kvm_flush_pml_buffers(struct kvm *kvm) | |
8978 | { | |
8979 | int i; | |
8980 | struct kvm_vcpu *vcpu; | |
8981 | /* | |
8982 | * We only need to kick vcpu out of guest mode here, as PML buffer | |
8983 | * is flushed at beginning of all VMEXITs, and it's obvious that only | |
8984 | * vcpus running in guest are possible to have unflushed GPAs in PML | |
8985 | * buffer. | |
8986 | */ | |
8987 | kvm_for_each_vcpu(i, vcpu, kvm) | |
8988 | kvm_vcpu_kick(vcpu); | |
8989 | } | |
8990 | ||
4eb64dce PB |
8991 | static void vmx_dump_sel(char *name, uint32_t sel) |
8992 | { | |
8993 | pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", | |
96794e4e | 8994 | name, vmcs_read16(sel), |
4eb64dce PB |
8995 | vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), |
8996 | vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), | |
8997 | vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); | |
8998 | } | |
8999 | ||
9000 | static void vmx_dump_dtsel(char *name, uint32_t limit) | |
9001 | { | |
9002 | pr_err("%s limit=0x%08x, base=0x%016lx\n", | |
9003 | name, vmcs_read32(limit), | |
9004 | vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); | |
9005 | } | |
9006 | ||
9007 | static void dump_vmcs(void) | |
9008 | { | |
9009 | u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); | |
9010 | u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); | |
9011 | u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
9012 | u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); | |
9013 | u32 secondary_exec_control = 0; | |
9014 | unsigned long cr4 = vmcs_readl(GUEST_CR4); | |
f3531054 | 9015 | u64 efer = vmcs_read64(GUEST_IA32_EFER); |
4eb64dce PB |
9016 | int i, n; |
9017 | ||
9018 | if (cpu_has_secondary_exec_ctrls()) | |
9019 | secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
9020 | ||
9021 | pr_err("*** Guest State ***\n"); | |
9022 | pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
9023 | vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), | |
9024 | vmcs_readl(CR0_GUEST_HOST_MASK)); | |
9025 | pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
9026 | cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); | |
9027 | pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); | |
9028 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && | |
9029 | (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) | |
9030 | { | |
845c5b40 PB |
9031 | pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", |
9032 | vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); | |
9033 | pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", | |
9034 | vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); | |
4eb64dce PB |
9035 | } |
9036 | pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", | |
9037 | vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); | |
9038 | pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", | |
9039 | vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); | |
9040 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
9041 | vmcs_readl(GUEST_SYSENTER_ESP), | |
9042 | vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); | |
9043 | vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); | |
9044 | vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); | |
9045 | vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); | |
9046 | vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); | |
9047 | vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); | |
9048 | vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); | |
9049 | vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); | |
9050 | vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); | |
9051 | vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); | |
9052 | vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); | |
9053 | if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || | |
9054 | (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) | |
845c5b40 PB |
9055 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
9056 | efer, vmcs_read64(GUEST_IA32_PAT)); | |
9057 | pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", | |
9058 | vmcs_read64(GUEST_IA32_DEBUGCTL), | |
4eb64dce | 9059 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); |
773e8a04 VK |
9060 | if (cpu_has_load_perf_global_ctrl && |
9061 | vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
845c5b40 PB |
9062 | pr_err("PerfGlobCtl = 0x%016llx\n", |
9063 | vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce | 9064 | if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) |
845c5b40 | 9065 | pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); |
4eb64dce PB |
9066 | pr_err("Interruptibility = %08x ActivityState = %08x\n", |
9067 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), | |
9068 | vmcs_read32(GUEST_ACTIVITY_STATE)); | |
9069 | if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) | |
9070 | pr_err("InterruptStatus = %04x\n", | |
9071 | vmcs_read16(GUEST_INTR_STATUS)); | |
9072 | ||
9073 | pr_err("*** Host State ***\n"); | |
9074 | pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", | |
9075 | vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); | |
9076 | pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", | |
9077 | vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), | |
9078 | vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), | |
9079 | vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), | |
9080 | vmcs_read16(HOST_TR_SELECTOR)); | |
9081 | pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", | |
9082 | vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), | |
9083 | vmcs_readl(HOST_TR_BASE)); | |
9084 | pr_err("GDTBase=%016lx IDTBase=%016lx\n", | |
9085 | vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); | |
9086 | pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", | |
9087 | vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), | |
9088 | vmcs_readl(HOST_CR4)); | |
9089 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
9090 | vmcs_readl(HOST_IA32_SYSENTER_ESP), | |
9091 | vmcs_read32(HOST_IA32_SYSENTER_CS), | |
9092 | vmcs_readl(HOST_IA32_SYSENTER_EIP)); | |
9093 | if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) | |
845c5b40 PB |
9094 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
9095 | vmcs_read64(HOST_IA32_EFER), | |
9096 | vmcs_read64(HOST_IA32_PAT)); | |
773e8a04 VK |
9097 | if (cpu_has_load_perf_global_ctrl && |
9098 | vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) | |
845c5b40 PB |
9099 | pr_err("PerfGlobCtl = 0x%016llx\n", |
9100 | vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce PB |
9101 | |
9102 | pr_err("*** Control State ***\n"); | |
9103 | pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", | |
9104 | pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); | |
9105 | pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); | |
9106 | pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", | |
9107 | vmcs_read32(EXCEPTION_BITMAP), | |
9108 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), | |
9109 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); | |
9110 | pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", | |
9111 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
9112 | vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), | |
9113 | vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); | |
9114 | pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", | |
9115 | vmcs_read32(VM_EXIT_INTR_INFO), | |
9116 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
9117 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
9118 | pr_err(" reason=%08x qualification=%016lx\n", | |
9119 | vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); | |
9120 | pr_err("IDTVectoring: info=%08x errcode=%08x\n", | |
9121 | vmcs_read32(IDT_VECTORING_INFO_FIELD), | |
9122 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
845c5b40 | 9123 | pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); |
8cfe9866 | 9124 | if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) |
845c5b40 PB |
9125 | pr_err("TSC Multiplier = 0x%016llx\n", |
9126 | vmcs_read64(TSC_MULTIPLIER)); | |
4eb64dce PB |
9127 | if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) |
9128 | pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); | |
9129 | if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) | |
9130 | pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); | |
9131 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) | |
845c5b40 | 9132 | pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); |
4eb64dce PB |
9133 | n = vmcs_read32(CR3_TARGET_COUNT); |
9134 | for (i = 0; i + 1 < n; i += 4) | |
9135 | pr_err("CR3 target%u=%016lx target%u=%016lx\n", | |
9136 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), | |
9137 | i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); | |
9138 | if (i < n) | |
9139 | pr_err("CR3 target%u=%016lx\n", | |
9140 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); | |
9141 | if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) | |
9142 | pr_err("PLE Gap=%08x Window=%08x\n", | |
9143 | vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); | |
9144 | if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) | |
9145 | pr_err("Virtual processor ID = 0x%04x\n", | |
9146 | vmcs_read16(VIRTUAL_PROCESSOR_ID)); | |
9147 | } | |
9148 | ||
6aa8b732 AK |
9149 | /* |
9150 | * The guest has exited. See if we can fix it or if we need userspace | |
9151 | * assistance. | |
9152 | */ | |
851ba692 | 9153 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 9154 | { |
29bd8a78 | 9155 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 9156 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 9157 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 9158 | |
8b89fe1f PB |
9159 | trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); |
9160 | ||
843e4330 KH |
9161 | /* |
9162 | * Flush logged GPAs PML buffer, this will make dirty_bitmap more | |
9163 | * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before | |
9164 | * querying dirty_bitmap, we only need to kick all vcpus out of guest | |
9165 | * mode as if vcpus is in root mode, the PML buffer must has been | |
9166 | * flushed already. | |
9167 | */ | |
9168 | if (enable_pml) | |
54bf36aa | 9169 | vmx_flush_pml_buffer(vcpu); |
843e4330 | 9170 | |
80ced186 | 9171 | /* If guest state is invalid, start emulating */ |
14168786 | 9172 | if (vmx->emulation_required) |
80ced186 | 9173 | return handle_invalid_guest_state(vcpu); |
1d5a4d9b | 9174 | |
7313c698 PB |
9175 | if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) |
9176 | return nested_vmx_reflect_vmexit(vcpu, exit_reason); | |
644d711a | 9177 | |
5120702e | 9178 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
4eb64dce | 9179 | dump_vmcs(); |
5120702e MG |
9180 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
9181 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
9182 | = exit_reason; | |
9183 | return 0; | |
9184 | } | |
9185 | ||
29bd8a78 | 9186 | if (unlikely(vmx->fail)) { |
851ba692 AK |
9187 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
9188 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
9189 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
9190 | return 0; | |
9191 | } | |
6aa8b732 | 9192 | |
b9bf6882 XG |
9193 | /* |
9194 | * Note: | |
9195 | * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by | |
9196 | * delivery event since it indicates guest is accessing MMIO. | |
9197 | * The vm-exit can be triggered again after return to guest that | |
9198 | * will cause infinite loop. | |
9199 | */ | |
d77c26fc | 9200 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 9201 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac | 9202 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
b244c9fc | 9203 | exit_reason != EXIT_REASON_PML_FULL && |
b9bf6882 XG |
9204 | exit_reason != EXIT_REASON_TASK_SWITCH)) { |
9205 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
9206 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; | |
70bcd708 | 9207 | vcpu->run->internal.ndata = 3; |
b9bf6882 XG |
9208 | vcpu->run->internal.data[0] = vectoring_info; |
9209 | vcpu->run->internal.data[1] = exit_reason; | |
70bcd708 PB |
9210 | vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; |
9211 | if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { | |
9212 | vcpu->run->internal.ndata++; | |
9213 | vcpu->run->internal.data[3] = | |
9214 | vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
9215 | } | |
b9bf6882 XG |
9216 | return 0; |
9217 | } | |
3b86cd99 | 9218 | |
d02fcf50 | 9219 | if (unlikely(!enable_vnmi && |
8a1b4392 PB |
9220 | vmx->loaded_vmcs->soft_vnmi_blocked)) { |
9221 | if (vmx_interrupt_allowed(vcpu)) { | |
9222 | vmx->loaded_vmcs->soft_vnmi_blocked = 0; | |
9223 | } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && | |
9224 | vcpu->arch.nmi_pending) { | |
9225 | /* | |
9226 | * This CPU don't support us in finding the end of an | |
9227 | * NMI-blocked window if the guest runs with IRQs | |
9228 | * disabled. So we pull the trigger after 1 s of | |
9229 | * futile waiting, but inform the user about this. | |
9230 | */ | |
9231 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
9232 | "state on VCPU %d after 1 s timeout\n", | |
9233 | __func__, vcpu->vcpu_id); | |
9234 | vmx->loaded_vmcs->soft_vnmi_blocked = 0; | |
9235 | } | |
9236 | } | |
9237 | ||
6aa8b732 AK |
9238 | if (exit_reason < kvm_vmx_max_exit_handlers |
9239 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 9240 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 9241 | else { |
6c6c5e03 RK |
9242 | vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", |
9243 | exit_reason); | |
2bc19dc3 MT |
9244 | kvm_queue_exception(vcpu, UD_VECTOR); |
9245 | return 1; | |
6aa8b732 | 9246 | } |
6aa8b732 AK |
9247 | } |
9248 | ||
95ba8273 | 9249 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 9250 | { |
a7c0b07d WL |
9251 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
9252 | ||
9253 | if (is_guest_mode(vcpu) && | |
9254 | nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
9255 | return; | |
9256 | ||
95ba8273 | 9257 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
9258 | vmcs_write32(TPR_THRESHOLD, 0); |
9259 | return; | |
9260 | } | |
9261 | ||
95ba8273 | 9262 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
9263 | } |
9264 | ||
8d14695f YZ |
9265 | static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
9266 | { | |
9267 | u32 sec_exec_control; | |
9268 | ||
dccbfcf5 RK |
9269 | /* Postpone execution until vmcs01 is the current VMCS. */ |
9270 | if (is_guest_mode(vcpu)) { | |
9271 | to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true; | |
9272 | return; | |
9273 | } | |
9274 | ||
f6e90f9e | 9275 | if (!cpu_has_vmx_virtualize_x2apic_mode()) |
8d14695f YZ |
9276 | return; |
9277 | ||
35754c98 | 9278 | if (!cpu_need_tpr_shadow(vcpu)) |
8d14695f YZ |
9279 | return; |
9280 | ||
9281 | sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
9282 | ||
9283 | if (set) { | |
9284 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
9285 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
9286 | } else { | |
9287 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
9288 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
a468f2db | 9289 | vmx_flush_tlb(vcpu, true); |
8d14695f YZ |
9290 | } |
9291 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control); | |
9292 | ||
904e14fb | 9293 | vmx_update_msr_bitmap(vcpu); |
8d14695f YZ |
9294 | } |
9295 | ||
38b99173 TC |
9296 | static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) |
9297 | { | |
9298 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9299 | ||
9300 | /* | |
9301 | * Currently we do not handle the nested case where L2 has an | |
9302 | * APIC access page of its own; that page is still pinned. | |
9303 | * Hence, we skip the case where the VCPU is in guest mode _and_ | |
9304 | * L1 prepared an APIC access page for L2. | |
9305 | * | |
9306 | * For the case where L1 and L2 share the same APIC access page | |
9307 | * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear | |
9308 | * in the vmcs12), this function will only update either the vmcs01 | |
9309 | * or the vmcs02. If the former, the vmcs02 will be updated by | |
9310 | * prepare_vmcs02. If the latter, the vmcs01 will be updated in | |
9311 | * the next L2->L1 exit. | |
9312 | */ | |
9313 | if (!is_guest_mode(vcpu) || | |
4f2777bc | 9314 | !nested_cpu_has2(get_vmcs12(&vmx->vcpu), |
fb6c8198 | 9315 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { |
38b99173 | 9316 | vmcs_write64(APIC_ACCESS_ADDR, hpa); |
a468f2db | 9317 | vmx_flush_tlb(vcpu, true); |
fb6c8198 | 9318 | } |
38b99173 TC |
9319 | } |
9320 | ||
67c9dddc | 9321 | static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
c7c9c56c YZ |
9322 | { |
9323 | u16 status; | |
9324 | u8 old; | |
9325 | ||
67c9dddc PB |
9326 | if (max_isr == -1) |
9327 | max_isr = 0; | |
c7c9c56c YZ |
9328 | |
9329 | status = vmcs_read16(GUEST_INTR_STATUS); | |
9330 | old = status >> 8; | |
67c9dddc | 9331 | if (max_isr != old) { |
c7c9c56c | 9332 | status &= 0xff; |
67c9dddc | 9333 | status |= max_isr << 8; |
c7c9c56c YZ |
9334 | vmcs_write16(GUEST_INTR_STATUS, status); |
9335 | } | |
9336 | } | |
9337 | ||
9338 | static void vmx_set_rvi(int vector) | |
9339 | { | |
9340 | u16 status; | |
9341 | u8 old; | |
9342 | ||
4114c27d WW |
9343 | if (vector == -1) |
9344 | vector = 0; | |
9345 | ||
c7c9c56c YZ |
9346 | status = vmcs_read16(GUEST_INTR_STATUS); |
9347 | old = (u8)status & 0xff; | |
9348 | if ((u8)vector != old) { | |
9349 | status &= ~0xff; | |
9350 | status |= (u8)vector; | |
9351 | vmcs_write16(GUEST_INTR_STATUS, status); | |
9352 | } | |
9353 | } | |
9354 | ||
9355 | static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
9356 | { | |
963fee16 | 9357 | /* |
851c1a18 LA |
9358 | * When running L2, updating RVI is only relevant when |
9359 | * vmcs12 virtual-interrupt-delivery enabled. | |
9360 | * However, it can be enabled only when L1 also | |
9361 | * intercepts external-interrupts and in that case | |
9362 | * we should not update vmcs02 RVI but instead intercept | |
9363 | * interrupt. Therefore, do nothing when running L2. | |
963fee16 | 9364 | */ |
851c1a18 LA |
9365 | if (!is_guest_mode(vcpu)) |
9366 | vmx_set_rvi(max_irr); | |
c7c9c56c YZ |
9367 | } |
9368 | ||
76dfafd5 | 9369 | static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) |
810e6def PB |
9370 | { |
9371 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
76dfafd5 | 9372 | int max_irr; |
f27a85c4 | 9373 | bool max_irr_updated; |
810e6def | 9374 | |
76dfafd5 PB |
9375 | WARN_ON(!vcpu->arch.apicv_active); |
9376 | if (pi_test_on(&vmx->pi_desc)) { | |
9377 | pi_clear_on(&vmx->pi_desc); | |
9378 | /* | |
9379 | * IOMMU can write to PIR.ON, so the barrier matters even on UP. | |
9380 | * But on x86 this is just a compiler barrier anyway. | |
9381 | */ | |
9382 | smp_mb__after_atomic(); | |
f27a85c4 LA |
9383 | max_irr_updated = |
9384 | kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); | |
9385 | ||
9386 | /* | |
9387 | * If we are running L2 and L1 has a new pending interrupt | |
9388 | * which can be injected, we should re-evaluate | |
9389 | * what should be done with this new L1 interrupt. | |
851c1a18 LA |
9390 | * If L1 intercepts external-interrupts, we should |
9391 | * exit from L2 to L1. Otherwise, interrupt should be | |
9392 | * delivered directly to L2. | |
f27a85c4 | 9393 | */ |
851c1a18 LA |
9394 | if (is_guest_mode(vcpu) && max_irr_updated) { |
9395 | if (nested_exit_on_intr(vcpu)) | |
9396 | kvm_vcpu_exiting_guest_mode(vcpu); | |
9397 | else | |
9398 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9399 | } | |
76dfafd5 PB |
9400 | } else { |
9401 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
9402 | } | |
9403 | vmx_hwapic_irr_update(vcpu, max_irr); | |
9404 | return max_irr; | |
810e6def PB |
9405 | } |
9406 | ||
6308630b | 9407 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c | 9408 | { |
d62caabb | 9409 | if (!kvm_vcpu_apicv_active(vcpu)) |
3d81bc7e YZ |
9410 | return; |
9411 | ||
c7c9c56c YZ |
9412 | vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); |
9413 | vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); | |
9414 | vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); | |
9415 | vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); | |
9416 | } | |
9417 | ||
967235d3 PB |
9418 | static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) |
9419 | { | |
9420 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9421 | ||
9422 | pi_clear_on(&vmx->pi_desc); | |
9423 | memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); | |
9424 | } | |
9425 | ||
51aa01d1 | 9426 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 9427 | { |
48ae0fb4 JM |
9428 | u32 exit_intr_info = 0; |
9429 | u16 basic_exit_reason = (u16)vmx->exit_reason; | |
00eba012 | 9430 | |
48ae0fb4 JM |
9431 | if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY |
9432 | || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI)) | |
00eba012 AK |
9433 | return; |
9434 | ||
48ae0fb4 JM |
9435 | if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) |
9436 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9437 | vmx->exit_intr_info = exit_intr_info; | |
a0861c02 | 9438 | |
1261bfa3 WL |
9439 | /* if exit due to PF check for async PF */ |
9440 | if (is_page_fault(exit_intr_info)) | |
9441 | vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); | |
9442 | ||
a0861c02 | 9443 | /* Handle machine checks before interrupts are enabled */ |
48ae0fb4 JM |
9444 | if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY || |
9445 | is_machine_check(exit_intr_info)) | |
a0861c02 AK |
9446 | kvm_machine_check(); |
9447 | ||
20f65983 | 9448 | /* We need to handle NMIs before interrupts are enabled */ |
ef85b673 | 9449 | if (is_nmi(exit_intr_info)) { |
dd60d217 | 9450 | kvm_before_interrupt(&vmx->vcpu); |
20f65983 | 9451 | asm("int $2"); |
dd60d217 | 9452 | kvm_after_interrupt(&vmx->vcpu); |
ff9d07a0 | 9453 | } |
51aa01d1 | 9454 | } |
20f65983 | 9455 | |
a547c6db YZ |
9456 | static void vmx_handle_external_intr(struct kvm_vcpu *vcpu) |
9457 | { | |
9458 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9459 | ||
a547c6db YZ |
9460 | if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK)) |
9461 | == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) { | |
9462 | unsigned int vector; | |
9463 | unsigned long entry; | |
9464 | gate_desc *desc; | |
9465 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9466 | #ifdef CONFIG_X86_64 | |
9467 | unsigned long tmp; | |
9468 | #endif | |
9469 | ||
9470 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
9471 | desc = (gate_desc *)vmx->host_idt_base + vector; | |
64b163fa | 9472 | entry = gate_offset(desc); |
a547c6db YZ |
9473 | asm volatile( |
9474 | #ifdef CONFIG_X86_64 | |
9475 | "mov %%" _ASM_SP ", %[sp]\n\t" | |
9476 | "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" | |
9477 | "push $%c[ss]\n\t" | |
9478 | "push %[sp]\n\t" | |
9479 | #endif | |
9480 | "pushf\n\t" | |
a547c6db | 9481 | __ASM_SIZE(push) " $%c[cs]\n\t" |
c940a3fb | 9482 | CALL_NOSPEC |
a547c6db YZ |
9483 | : |
9484 | #ifdef CONFIG_X86_64 | |
3f62de5f | 9485 | [sp]"=&r"(tmp), |
a547c6db | 9486 | #endif |
f5caf621 | 9487 | ASM_CALL_CONSTRAINT |
a547c6db | 9488 | : |
c940a3fb | 9489 | THUNK_TARGET(entry), |
a547c6db YZ |
9490 | [ss]"i"(__KERNEL_DS), |
9491 | [cs]"i"(__KERNEL_CS) | |
9492 | ); | |
f2485b3e | 9493 | } |
a547c6db | 9494 | } |
c207aee4 | 9495 | STACK_FRAME_NON_STANDARD(vmx_handle_external_intr); |
a547c6db | 9496 | |
bc226f07 | 9497 | static bool vmx_has_emulated_msr(int index) |
6d396b55 | 9498 | { |
bc226f07 TL |
9499 | switch (index) { |
9500 | case MSR_IA32_SMBASE: | |
9501 | /* | |
9502 | * We cannot do SMM unless we can run the guest in big | |
9503 | * real mode. | |
9504 | */ | |
9505 | return enable_unrestricted_guest || emulate_invalid_guest_state; | |
9506 | case MSR_AMD64_VIRT_SPEC_CTRL: | |
9507 | /* This is AMD only. */ | |
9508 | return false; | |
9509 | default: | |
9510 | return true; | |
9511 | } | |
6d396b55 PB |
9512 | } |
9513 | ||
da8999d3 LJ |
9514 | static bool vmx_mpx_supported(void) |
9515 | { | |
9516 | return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && | |
9517 | (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); | |
9518 | } | |
9519 | ||
55412b2e WL |
9520 | static bool vmx_xsaves_supported(void) |
9521 | { | |
9522 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
9523 | SECONDARY_EXEC_XSAVES; | |
9524 | } | |
9525 | ||
51aa01d1 AK |
9526 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
9527 | { | |
c5ca8e57 | 9528 | u32 exit_intr_info; |
51aa01d1 AK |
9529 | bool unblock_nmi; |
9530 | u8 vector; | |
9531 | bool idtv_info_valid; | |
9532 | ||
9533 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 9534 | |
d02fcf50 | 9535 | if (enable_vnmi) { |
8a1b4392 PB |
9536 | if (vmx->loaded_vmcs->nmi_known_unmasked) |
9537 | return; | |
9538 | /* | |
9539 | * Can't use vmx->exit_intr_info since we're not sure what | |
9540 | * the exit reason is. | |
9541 | */ | |
9542 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9543 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | |
9544 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
9545 | /* | |
9546 | * SDM 3: 27.7.1.2 (September 2008) | |
9547 | * Re-set bit "block by NMI" before VM entry if vmexit caused by | |
9548 | * a guest IRET fault. | |
9549 | * SDM 3: 23.2.2 (September 2008) | |
9550 | * Bit 12 is undefined in any of the following cases: | |
9551 | * If the VM exit sets the valid bit in the IDT-vectoring | |
9552 | * information field. | |
9553 | * If the VM exit is due to a double fault. | |
9554 | */ | |
9555 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && | |
9556 | vector != DF_VECTOR && !idtv_info_valid) | |
9557 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
9558 | GUEST_INTR_STATE_NMI); | |
9559 | else | |
9560 | vmx->loaded_vmcs->nmi_known_unmasked = | |
9561 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | |
9562 | & GUEST_INTR_STATE_NMI); | |
9563 | } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) | |
9564 | vmx->loaded_vmcs->vnmi_blocked_time += | |
9565 | ktime_to_ns(ktime_sub(ktime_get(), | |
9566 | vmx->loaded_vmcs->entry_time)); | |
51aa01d1 AK |
9567 | } |
9568 | ||
3ab66e8a | 9569 | static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, |
83422e17 AK |
9570 | u32 idt_vectoring_info, |
9571 | int instr_len_field, | |
9572 | int error_code_field) | |
51aa01d1 | 9573 | { |
51aa01d1 AK |
9574 | u8 vector; |
9575 | int type; | |
9576 | bool idtv_info_valid; | |
9577 | ||
9578 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 9579 | |
3ab66e8a JK |
9580 | vcpu->arch.nmi_injected = false; |
9581 | kvm_clear_exception_queue(vcpu); | |
9582 | kvm_clear_interrupt_queue(vcpu); | |
37b96e98 GN |
9583 | |
9584 | if (!idtv_info_valid) | |
9585 | return; | |
9586 | ||
3ab66e8a | 9587 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3842d135 | 9588 | |
668f612f AK |
9589 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
9590 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 9591 | |
64a7ec06 | 9592 | switch (type) { |
37b96e98 | 9593 | case INTR_TYPE_NMI_INTR: |
3ab66e8a | 9594 | vcpu->arch.nmi_injected = true; |
668f612f | 9595 | /* |
7b4a25cb | 9596 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
9597 | * Clear bit "block by NMI" before VM entry if a NMI |
9598 | * delivery faulted. | |
668f612f | 9599 | */ |
3ab66e8a | 9600 | vmx_set_nmi_mask(vcpu, false); |
37b96e98 | 9601 | break; |
37b96e98 | 9602 | case INTR_TYPE_SOFT_EXCEPTION: |
3ab66e8a | 9603 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f GN |
9604 | /* fall through */ |
9605 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 9606 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 9607 | u32 err = vmcs_read32(error_code_field); |
851eb667 | 9608 | kvm_requeue_exception_e(vcpu, vector, err); |
35920a35 | 9609 | } else |
851eb667 | 9610 | kvm_requeue_exception(vcpu, vector); |
37b96e98 | 9611 | break; |
66fd3f7f | 9612 | case INTR_TYPE_SOFT_INTR: |
3ab66e8a | 9613 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f | 9614 | /* fall through */ |
37b96e98 | 9615 | case INTR_TYPE_EXT_INTR: |
3ab66e8a | 9616 | kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); |
37b96e98 GN |
9617 | break; |
9618 | default: | |
9619 | break; | |
f7d9238f | 9620 | } |
cf393f75 AK |
9621 | } |
9622 | ||
83422e17 AK |
9623 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
9624 | { | |
3ab66e8a | 9625 | __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, |
83422e17 AK |
9626 | VM_EXIT_INSTRUCTION_LEN, |
9627 | IDT_VECTORING_ERROR_CODE); | |
9628 | } | |
9629 | ||
b463a6f7 AK |
9630 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
9631 | { | |
3ab66e8a | 9632 | __vmx_complete_interrupts(vcpu, |
b463a6f7 AK |
9633 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), |
9634 | VM_ENTRY_INSTRUCTION_LEN, | |
9635 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
9636 | ||
9637 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
9638 | } | |
9639 | ||
d7cd9796 GN |
9640 | static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) |
9641 | { | |
9642 | int i, nr_msrs; | |
9643 | struct perf_guest_switch_msr *msrs; | |
9644 | ||
9645 | msrs = perf_guest_get_msrs(&nr_msrs); | |
9646 | ||
9647 | if (!msrs) | |
9648 | return; | |
9649 | ||
9650 | for (i = 0; i < nr_msrs; i++) | |
9651 | if (msrs[i].host == msrs[i].guest) | |
9652 | clear_atomic_switch_msr(vmx, msrs[i].msr); | |
9653 | else | |
9654 | add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, | |
9655 | msrs[i].host); | |
9656 | } | |
9657 | ||
33365e7a | 9658 | static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu) |
64672c95 YJ |
9659 | { |
9660 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9661 | u64 tscl; | |
9662 | u32 delta_tsc; | |
9663 | ||
9664 | if (vmx->hv_deadline_tsc == -1) | |
9665 | return; | |
9666 | ||
9667 | tscl = rdtsc(); | |
9668 | if (vmx->hv_deadline_tsc > tscl) | |
9669 | /* sure to be 32 bit only because checked on set_hv_timer */ | |
9670 | delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> | |
9671 | cpu_preemption_timer_multi); | |
9672 | else | |
9673 | delta_tsc = 0; | |
9674 | ||
9675 | vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); | |
9676 | } | |
9677 | ||
a3b5ba49 | 9678 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 9679 | { |
a2fa3e9f | 9680 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
773e8a04 | 9681 | unsigned long cr3, cr4, evmcs_rsp; |
104f226b | 9682 | |
8a1b4392 | 9683 | /* Record the guest's net vcpu time for enforced NMI injections. */ |
d02fcf50 | 9684 | if (unlikely(!enable_vnmi && |
8a1b4392 PB |
9685 | vmx->loaded_vmcs->soft_vnmi_blocked)) |
9686 | vmx->loaded_vmcs->entry_time = ktime_get(); | |
9687 | ||
104f226b AK |
9688 | /* Don't enter VMX if guest state is invalid, let the exit handler |
9689 | start emulation until we arrive back to a valid state */ | |
14168786 | 9690 | if (vmx->emulation_required) |
104f226b AK |
9691 | return; |
9692 | ||
a7653ecd RK |
9693 | if (vmx->ple_window_dirty) { |
9694 | vmx->ple_window_dirty = false; | |
9695 | vmcs_write32(PLE_WINDOW, vmx->ple_window); | |
9696 | } | |
9697 | ||
012f83cb AG |
9698 | if (vmx->nested.sync_shadow_vmcs) { |
9699 | copy_vmcs12_to_shadow(vmx); | |
9700 | vmx->nested.sync_shadow_vmcs = false; | |
9701 | } | |
9702 | ||
104f226b AK |
9703 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
9704 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
9705 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
9706 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
9707 | ||
d6e41f11 | 9708 | cr3 = __get_current_cr3_fast(); |
44889942 | 9709 | if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) { |
d6e41f11 | 9710 | vmcs_writel(HOST_CR3, cr3); |
44889942 | 9711 | vmx->loaded_vmcs->vmcs_host_cr3 = cr3; |
d6e41f11 AL |
9712 | } |
9713 | ||
1e02ce4c | 9714 | cr4 = cr4_read_shadow(); |
44889942 | 9715 | if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) { |
d974baa3 | 9716 | vmcs_writel(HOST_CR4, cr4); |
44889942 | 9717 | vmx->loaded_vmcs->vmcs_host_cr4 = cr4; |
d974baa3 AL |
9718 | } |
9719 | ||
104f226b AK |
9720 | /* When single-stepping over STI and MOV SS, we must clear the |
9721 | * corresponding interruptibility bits in the guest state. Otherwise | |
9722 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
9723 | * exceptions being set, but that's not correct for the guest debugging | |
9724 | * case. */ | |
9725 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
9726 | vmx_set_interrupt_shadow(vcpu, 0); | |
9727 | ||
b9dd21e1 PB |
9728 | if (static_cpu_has(X86_FEATURE_PKU) && |
9729 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && | |
9730 | vcpu->arch.pkru != vmx->host_pkru) | |
9731 | __write_pkru(vcpu->arch.pkru); | |
1be0e61c | 9732 | |
d7cd9796 GN |
9733 | atomic_switch_perf_msrs(vmx); |
9734 | ||
64672c95 YJ |
9735 | vmx_arm_hv_timer(vcpu); |
9736 | ||
d28b387f KA |
9737 | /* |
9738 | * If this vCPU has touched SPEC_CTRL, restore the guest's value if | |
9739 | * it's non-zero. Since vmentry is serialising on affected CPUs, there | |
9740 | * is no need to worry about the conditional branch over the wrmsr | |
9741 | * being speculatively taken. | |
9742 | */ | |
ccbcd267 | 9743 | x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); |
d28b387f | 9744 | |
d462b819 | 9745 | vmx->__launched = vmx->loaded_vmcs->launched; |
773e8a04 VK |
9746 | |
9747 | evmcs_rsp = static_branch_unlikely(&enable_evmcs) ? | |
9748 | (unsigned long)¤t_evmcs->host_rsp : 0; | |
9749 | ||
104f226b | 9750 | asm( |
6aa8b732 | 9751 | /* Store host registers */ |
b188c81f AK |
9752 | "push %%" _ASM_DX "; push %%" _ASM_BP ";" |
9753 | "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */ | |
9754 | "push %%" _ASM_CX " \n\t" | |
9755 | "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t" | |
313dbd49 | 9756 | "je 1f \n\t" |
b188c81f | 9757 | "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t" |
773e8a04 VK |
9758 | /* Avoid VMWRITE when Enlightened VMCS is in use */ |
9759 | "test %%" _ASM_SI ", %%" _ASM_SI " \n\t" | |
9760 | "jz 2f \n\t" | |
9761 | "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t" | |
9762 | "jmp 1f \n\t" | |
9763 | "2: \n\t" | |
4ecac3fd | 9764 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 9765 | "1: \n\t" |
d3edefc0 | 9766 | /* Reload cr2 if changed */ |
b188c81f AK |
9767 | "mov %c[cr2](%0), %%" _ASM_AX " \n\t" |
9768 | "mov %%cr2, %%" _ASM_DX " \n\t" | |
9769 | "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t" | |
773e8a04 | 9770 | "je 3f \n\t" |
b188c81f | 9771 | "mov %%" _ASM_AX", %%cr2 \n\t" |
773e8a04 | 9772 | "3: \n\t" |
6aa8b732 | 9773 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 9774 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 9775 | /* Load guest registers. Don't clobber flags. */ |
b188c81f AK |
9776 | "mov %c[rax](%0), %%" _ASM_AX " \n\t" |
9777 | "mov %c[rbx](%0), %%" _ASM_BX " \n\t" | |
9778 | "mov %c[rdx](%0), %%" _ASM_DX " \n\t" | |
9779 | "mov %c[rsi](%0), %%" _ASM_SI " \n\t" | |
9780 | "mov %c[rdi](%0), %%" _ASM_DI " \n\t" | |
9781 | "mov %c[rbp](%0), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 9782 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
9783 | "mov %c[r8](%0), %%r8 \n\t" |
9784 | "mov %c[r9](%0), %%r9 \n\t" | |
9785 | "mov %c[r10](%0), %%r10 \n\t" | |
9786 | "mov %c[r11](%0), %%r11 \n\t" | |
9787 | "mov %c[r12](%0), %%r12 \n\t" | |
9788 | "mov %c[r13](%0), %%r13 \n\t" | |
9789 | "mov %c[r14](%0), %%r14 \n\t" | |
9790 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 9791 | #endif |
b188c81f | 9792 | "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */ |
c801949d | 9793 | |
6aa8b732 | 9794 | /* Enter guest mode */ |
83287ea4 | 9795 | "jne 1f \n\t" |
4ecac3fd | 9796 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
83287ea4 AK |
9797 | "jmp 2f \n\t" |
9798 | "1: " __ex(ASM_VMX_VMRESUME) "\n\t" | |
9799 | "2: " | |
6aa8b732 | 9800 | /* Save guest registers, load host registers, keep flags */ |
b188c81f | 9801 | "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t" |
40712fae | 9802 | "pop %0 \n\t" |
0cb5b306 | 9803 | "setbe %c[fail](%0)\n\t" |
b188c81f AK |
9804 | "mov %%" _ASM_AX ", %c[rax](%0) \n\t" |
9805 | "mov %%" _ASM_BX ", %c[rbx](%0) \n\t" | |
9806 | __ASM_SIZE(pop) " %c[rcx](%0) \n\t" | |
9807 | "mov %%" _ASM_DX ", %c[rdx](%0) \n\t" | |
9808 | "mov %%" _ASM_SI ", %c[rsi](%0) \n\t" | |
9809 | "mov %%" _ASM_DI ", %c[rdi](%0) \n\t" | |
9810 | "mov %%" _ASM_BP ", %c[rbp](%0) \n\t" | |
05b3e0c2 | 9811 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
9812 | "mov %%r8, %c[r8](%0) \n\t" |
9813 | "mov %%r9, %c[r9](%0) \n\t" | |
9814 | "mov %%r10, %c[r10](%0) \n\t" | |
9815 | "mov %%r11, %c[r11](%0) \n\t" | |
9816 | "mov %%r12, %c[r12](%0) \n\t" | |
9817 | "mov %%r13, %c[r13](%0) \n\t" | |
9818 | "mov %%r14, %c[r14](%0) \n\t" | |
9819 | "mov %%r15, %c[r15](%0) \n\t" | |
0cb5b306 JM |
9820 | "xor %%r8d, %%r8d \n\t" |
9821 | "xor %%r9d, %%r9d \n\t" | |
9822 | "xor %%r10d, %%r10d \n\t" | |
9823 | "xor %%r11d, %%r11d \n\t" | |
9824 | "xor %%r12d, %%r12d \n\t" | |
9825 | "xor %%r13d, %%r13d \n\t" | |
9826 | "xor %%r14d, %%r14d \n\t" | |
9827 | "xor %%r15d, %%r15d \n\t" | |
6aa8b732 | 9828 | #endif |
b188c81f AK |
9829 | "mov %%cr2, %%" _ASM_AX " \n\t" |
9830 | "mov %%" _ASM_AX ", %c[cr2](%0) \n\t" | |
c801949d | 9831 | |
0cb5b306 JM |
9832 | "xor %%eax, %%eax \n\t" |
9833 | "xor %%ebx, %%ebx \n\t" | |
9834 | "xor %%esi, %%esi \n\t" | |
9835 | "xor %%edi, %%edi \n\t" | |
b188c81f | 9836 | "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t" |
83287ea4 AK |
9837 | ".pushsection .rodata \n\t" |
9838 | ".global vmx_return \n\t" | |
9839 | "vmx_return: " _ASM_PTR " 2b \n\t" | |
9840 | ".popsection" | |
773e8a04 | 9841 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp), |
d462b819 | 9842 | [launched]"i"(offsetof(struct vcpu_vmx, __launched)), |
e08aa78a | 9843 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), |
313dbd49 | 9844 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
9845 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
9846 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
9847 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
9848 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
9849 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
9850 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
9851 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 9852 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
9853 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
9854 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
9855 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
9856 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
9857 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
9858 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
9859 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
9860 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 9861 | #endif |
40712fae AK |
9862 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
9863 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 LV |
9864 | : "cc", "memory" |
9865 | #ifdef CONFIG_X86_64 | |
773e8a04 | 9866 | , "rax", "rbx", "rdi" |
c2036300 | 9867 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
b188c81f | 9868 | #else |
773e8a04 | 9869 | , "eax", "ebx", "edi" |
c2036300 LV |
9870 | #endif |
9871 | ); | |
6aa8b732 | 9872 | |
d28b387f KA |
9873 | /* |
9874 | * We do not use IBRS in the kernel. If this vCPU has used the | |
9875 | * SPEC_CTRL MSR it may have left it on; save the value and | |
9876 | * turn it off. This is much more efficient than blindly adding | |
9877 | * it to the atomic save/restore list. Especially as the former | |
9878 | * (Saving guest MSRs on vmexit) doesn't even exist in KVM. | |
9879 | * | |
9880 | * For non-nested case: | |
9881 | * If the L01 MSR bitmap does not intercept the MSR, then we need to | |
9882 | * save it. | |
9883 | * | |
9884 | * For nested case: | |
9885 | * If the L02 MSR bitmap does not intercept the MSR, then we need to | |
9886 | * save it. | |
9887 | */ | |
946fbbc1 | 9888 | if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) |
ecb586bd | 9889 | vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); |
d28b387f | 9890 | |
ccbcd267 | 9891 | x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); |
d28b387f | 9892 | |
117cc7a9 DW |
9893 | /* Eliminate branch target predictions from guest mode */ |
9894 | vmexit_fill_RSB(); | |
9895 | ||
773e8a04 VK |
9896 | /* All fields are clean at this point */ |
9897 | if (static_branch_unlikely(&enable_evmcs)) | |
9898 | current_evmcs->hv_clean_fields |= | |
9899 | HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; | |
9900 | ||
2a7921b7 | 9901 | /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ |
74c55931 WL |
9902 | if (vmx->host_debugctlmsr) |
9903 | update_debugctlmsr(vmx->host_debugctlmsr); | |
2a7921b7 | 9904 | |
aa67f609 AK |
9905 | #ifndef CONFIG_X86_64 |
9906 | /* | |
9907 | * The sysexit path does not restore ds/es, so we must set them to | |
9908 | * a reasonable value ourselves. | |
9909 | * | |
9910 | * We can't defer this to vmx_load_host_state() since that function | |
9911 | * may be executed in interrupt context, which saves and restore segments | |
9912 | * around it, nullifying its effect. | |
9913 | */ | |
9914 | loadsegment(ds, __USER_DS); | |
9915 | loadsegment(es, __USER_DS); | |
9916 | #endif | |
9917 | ||
6de4f3ad | 9918 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
6de12732 | 9919 | | (1 << VCPU_EXREG_RFLAGS) |
aff48baa | 9920 | | (1 << VCPU_EXREG_PDPTR) |
2fb92db1 | 9921 | | (1 << VCPU_EXREG_SEGMENTS) |
aff48baa | 9922 | | (1 << VCPU_EXREG_CR3)); |
5fdbf976 MT |
9923 | vcpu->arch.regs_dirty = 0; |
9924 | ||
1be0e61c XG |
9925 | /* |
9926 | * eager fpu is enabled if PKEY is supported and CR4 is switched | |
9927 | * back on host, so it is safe to read guest PKRU from current | |
9928 | * XSAVE. | |
9929 | */ | |
b9dd21e1 PB |
9930 | if (static_cpu_has(X86_FEATURE_PKU) && |
9931 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { | |
9932 | vcpu->arch.pkru = __read_pkru(); | |
9933 | if (vcpu->arch.pkru != vmx->host_pkru) | |
1be0e61c | 9934 | __write_pkru(vmx->host_pkru); |
1be0e61c XG |
9935 | } |
9936 | ||
e0b890d3 | 9937 | vmx->nested.nested_run_pending = 0; |
b060ca3b JM |
9938 | vmx->idt_vectoring_info = 0; |
9939 | ||
9940 | vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); | |
9941 | if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) | |
9942 | return; | |
9943 | ||
9944 | vmx->loaded_vmcs->launched = 1; | |
9945 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
e0b890d3 | 9946 | |
51aa01d1 AK |
9947 | vmx_complete_atomic_exit(vmx); |
9948 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 9949 | vmx_complete_interrupts(vmx); |
6aa8b732 | 9950 | } |
c207aee4 | 9951 | STACK_FRAME_NON_STANDARD(vmx_vcpu_run); |
6aa8b732 | 9952 | |
434a1e94 SC |
9953 | static struct kvm *vmx_vm_alloc(void) |
9954 | { | |
40bbb9d0 SC |
9955 | struct kvm_vmx *kvm_vmx = kzalloc(sizeof(struct kvm_vmx), GFP_KERNEL); |
9956 | return &kvm_vmx->kvm; | |
434a1e94 SC |
9957 | } |
9958 | ||
9959 | static void vmx_vm_free(struct kvm *kvm) | |
9960 | { | |
40bbb9d0 | 9961 | kfree(to_kvm_vmx(kvm)); |
434a1e94 SC |
9962 | } |
9963 | ||
1279a6b1 | 9964 | static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs) |
4fa7734c PB |
9965 | { |
9966 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9967 | int cpu; | |
9968 | ||
1279a6b1 | 9969 | if (vmx->loaded_vmcs == vmcs) |
4fa7734c PB |
9970 | return; |
9971 | ||
9972 | cpu = get_cpu(); | |
1279a6b1 | 9973 | vmx->loaded_vmcs = vmcs; |
4fa7734c PB |
9974 | vmx_vcpu_put(vcpu); |
9975 | vmx_vcpu_load(vcpu, cpu); | |
4fa7734c PB |
9976 | put_cpu(); |
9977 | } | |
9978 | ||
2f1fe811 JM |
9979 | /* |
9980 | * Ensure that the current vmcs of the logical processor is the | |
9981 | * vmcs01 of the vcpu before calling free_nested(). | |
9982 | */ | |
9983 | static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu) | |
9984 | { | |
9985 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2f1fe811 | 9986 | |
ec7660cc | 9987 | vcpu_load(vcpu); |
1279a6b1 | 9988 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
2f1fe811 JM |
9989 | free_nested(vmx); |
9990 | vcpu_put(vcpu); | |
9991 | } | |
9992 | ||
6aa8b732 AK |
9993 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
9994 | { | |
fb3f0f51 RR |
9995 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
9996 | ||
843e4330 | 9997 | if (enable_pml) |
a3eaa864 | 9998 | vmx_destroy_pml_buffer(vmx); |
991e7a0e | 9999 | free_vpid(vmx->vpid); |
4fa7734c | 10000 | leave_guest_mode(vcpu); |
2f1fe811 | 10001 | vmx_free_vcpu_nested(vcpu); |
4fa7734c | 10002 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 RR |
10003 | kfree(vmx->guest_msrs); |
10004 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 10005 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
10006 | } |
10007 | ||
fb3f0f51 | 10008 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 10009 | { |
fb3f0f51 | 10010 | int err; |
c16f862d | 10011 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
904e14fb | 10012 | unsigned long *msr_bitmap; |
15ad7146 | 10013 | int cpu; |
6aa8b732 | 10014 | |
a2fa3e9f | 10015 | if (!vmx) |
fb3f0f51 RR |
10016 | return ERR_PTR(-ENOMEM); |
10017 | ||
991e7a0e | 10018 | vmx->vpid = allocate_vpid(); |
2384d2b3 | 10019 | |
fb3f0f51 RR |
10020 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
10021 | if (err) | |
10022 | goto free_vcpu; | |
965b58a5 | 10023 | |
4e59516a PF |
10024 | err = -ENOMEM; |
10025 | ||
10026 | /* | |
10027 | * If PML is turned on, failure on enabling PML just results in failure | |
10028 | * of creating the vcpu, therefore we can simplify PML logic (by | |
10029 | * avoiding dealing with cases, such as enabling PML partially on vcpus | |
10030 | * for the guest, etc. | |
10031 | */ | |
10032 | if (enable_pml) { | |
10033 | vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
10034 | if (!vmx->pml_pg) | |
10035 | goto uninit_vcpu; | |
10036 | } | |
10037 | ||
a2fa3e9f | 10038 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
03916db9 PB |
10039 | BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0]) |
10040 | > PAGE_SIZE); | |
0123be42 | 10041 | |
4e59516a PF |
10042 | if (!vmx->guest_msrs) |
10043 | goto free_pml; | |
965b58a5 | 10044 | |
f21f165e PB |
10045 | err = alloc_loaded_vmcs(&vmx->vmcs01); |
10046 | if (err < 0) | |
fb3f0f51 | 10047 | goto free_msrs; |
a2fa3e9f | 10048 | |
904e14fb PB |
10049 | msr_bitmap = vmx->vmcs01.msr_bitmap; |
10050 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); | |
10051 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); | |
10052 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); | |
10053 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); | |
10054 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); | |
10055 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); | |
10056 | vmx->msr_bitmap_mode = 0; | |
10057 | ||
f21f165e | 10058 | vmx->loaded_vmcs = &vmx->vmcs01; |
15ad7146 AK |
10059 | cpu = get_cpu(); |
10060 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 10061 | vmx->vcpu.cpu = cpu; |
12d79917 | 10062 | vmx_vcpu_setup(vmx); |
fb3f0f51 | 10063 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 10064 | put_cpu(); |
35754c98 | 10065 | if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
be6d05cf JK |
10066 | err = alloc_apic_access_page(kvm); |
10067 | if (err) | |
5e4a0b3c | 10068 | goto free_vmcs; |
a63cb560 | 10069 | } |
fb3f0f51 | 10070 | |
e90008df | 10071 | if (enable_ept && !enable_unrestricted_guest) { |
f51770ed TC |
10072 | err = init_rmode_identity_map(kvm); |
10073 | if (err) | |
93ea5388 | 10074 | goto free_vmcs; |
b927a3ce | 10075 | } |
b7ebfb05 | 10076 | |
5c614b35 | 10077 | if (nested) { |
6677f3da PB |
10078 | nested_vmx_setup_ctls_msrs(&vmx->nested.msrs, |
10079 | kvm_vcpu_apicv_active(&vmx->vcpu)); | |
5c614b35 WL |
10080 | vmx->nested.vpid02 = allocate_vpid(); |
10081 | } | |
b9c237bb | 10082 | |
705699a1 | 10083 | vmx->nested.posted_intr_nv = -1; |
a9d30f33 | 10084 | vmx->nested.current_vmptr = -1ull; |
a9d30f33 | 10085 | |
37e4c997 HZ |
10086 | vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED; |
10087 | ||
31afb2ea PB |
10088 | /* |
10089 | * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR | |
10090 | * or POSTED_INTR_WAKEUP_VECTOR. | |
10091 | */ | |
10092 | vmx->pi_desc.nv = POSTED_INTR_VECTOR; | |
10093 | vmx->pi_desc.sn = 1; | |
10094 | ||
fb3f0f51 RR |
10095 | return &vmx->vcpu; |
10096 | ||
10097 | free_vmcs: | |
5c614b35 | 10098 | free_vpid(vmx->nested.vpid02); |
5f3fbc34 | 10099 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 | 10100 | free_msrs: |
fb3f0f51 | 10101 | kfree(vmx->guest_msrs); |
4e59516a PF |
10102 | free_pml: |
10103 | vmx_destroy_pml_buffer(vmx); | |
fb3f0f51 RR |
10104 | uninit_vcpu: |
10105 | kvm_vcpu_uninit(&vmx->vcpu); | |
10106 | free_vcpu: | |
991e7a0e | 10107 | free_vpid(vmx->vpid); |
a4770347 | 10108 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 10109 | return ERR_PTR(err); |
6aa8b732 AK |
10110 | } |
10111 | ||
b31c114b WL |
10112 | static int vmx_vm_init(struct kvm *kvm) |
10113 | { | |
10114 | if (!ple_gap) | |
10115 | kvm->arch.pause_in_guest = true; | |
10116 | return 0; | |
10117 | } | |
10118 | ||
002c7f7c YS |
10119 | static void __init vmx_check_processor_compat(void *rtn) |
10120 | { | |
10121 | struct vmcs_config vmcs_conf; | |
10122 | ||
10123 | *(int *)rtn = 0; | |
10124 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
10125 | *(int *)rtn = -EIO; | |
1389309c | 10126 | nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, enable_apicv); |
002c7f7c YS |
10127 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { |
10128 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
10129 | smp_processor_id()); | |
10130 | *(int *)rtn = -EIO; | |
10131 | } | |
10132 | } | |
10133 | ||
4b12f0de | 10134 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 10135 | { |
b18d5431 XG |
10136 | u8 cache; |
10137 | u64 ipat = 0; | |
4b12f0de | 10138 | |
522c68c4 | 10139 | /* For VT-d and EPT combination |
606decd6 | 10140 | * 1. MMIO: always map as UC |
522c68c4 SY |
10141 | * 2. EPT with VT-d: |
10142 | * a. VT-d without snooping control feature: can't guarantee the | |
606decd6 | 10143 | * result, try to trust guest. |
522c68c4 SY |
10144 | * b. VT-d with snooping control feature: snooping control feature of |
10145 | * VT-d engine can guarantee the cache correctness. Just set it | |
10146 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 10147 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
10148 | * consistent with host MTRR |
10149 | */ | |
606decd6 PB |
10150 | if (is_mmio) { |
10151 | cache = MTRR_TYPE_UNCACHABLE; | |
10152 | goto exit; | |
10153 | } | |
10154 | ||
10155 | if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { | |
b18d5431 XG |
10156 | ipat = VMX_EPT_IPAT_BIT; |
10157 | cache = MTRR_TYPE_WRBACK; | |
10158 | goto exit; | |
10159 | } | |
10160 | ||
10161 | if (kvm_read_cr0(vcpu) & X86_CR0_CD) { | |
10162 | ipat = VMX_EPT_IPAT_BIT; | |
0da029ed | 10163 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) |
fb279950 XG |
10164 | cache = MTRR_TYPE_WRBACK; |
10165 | else | |
10166 | cache = MTRR_TYPE_UNCACHABLE; | |
b18d5431 XG |
10167 | goto exit; |
10168 | } | |
10169 | ||
ff53604b | 10170 | cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); |
b18d5431 XG |
10171 | |
10172 | exit: | |
10173 | return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; | |
64d4d521 SY |
10174 | } |
10175 | ||
17cc3935 | 10176 | static int vmx_get_lpage_level(void) |
344f414f | 10177 | { |
878403b7 SY |
10178 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
10179 | return PT_DIRECTORY_LEVEL; | |
10180 | else | |
10181 | /* For shadow and EPT supported 1GB page */ | |
10182 | return PT_PDPE_LEVEL; | |
344f414f JR |
10183 | } |
10184 | ||
feda805f XG |
10185 | static void vmcs_set_secondary_exec_control(u32 new_ctl) |
10186 | { | |
10187 | /* | |
10188 | * These bits in the secondary execution controls field | |
10189 | * are dynamic, the others are mostly based on the hypervisor | |
10190 | * architecture and the guest's CPUID. Do not touch the | |
10191 | * dynamic bits. | |
10192 | */ | |
10193 | u32 mask = | |
10194 | SECONDARY_EXEC_SHADOW_VMCS | | |
10195 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | | |
0367f205 PB |
10196 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
10197 | SECONDARY_EXEC_DESC; | |
feda805f XG |
10198 | |
10199 | u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
10200 | ||
10201 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
10202 | (new_ctl & ~mask) | (cur_ctl & mask)); | |
10203 | } | |
10204 | ||
8322ebbb DM |
10205 | /* |
10206 | * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits | |
10207 | * (indicating "allowed-1") if they are supported in the guest's CPUID. | |
10208 | */ | |
10209 | static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) | |
10210 | { | |
10211 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10212 | struct kvm_cpuid_entry2 *entry; | |
10213 | ||
6677f3da PB |
10214 | vmx->nested.msrs.cr0_fixed1 = 0xffffffff; |
10215 | vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; | |
8322ebbb DM |
10216 | |
10217 | #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ | |
10218 | if (entry && (entry->_reg & (_cpuid_mask))) \ | |
6677f3da | 10219 | vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ |
8322ebbb DM |
10220 | } while (0) |
10221 | ||
10222 | entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); | |
10223 | cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME)); | |
10224 | cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME)); | |
10225 | cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC)); | |
10226 | cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE)); | |
10227 | cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE)); | |
10228 | cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE)); | |
10229 | cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE)); | |
10230 | cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE)); | |
10231 | cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR)); | |
10232 | cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM)); | |
10233 | cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX)); | |
10234 | cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX)); | |
10235 | cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID)); | |
10236 | cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE)); | |
10237 | ||
10238 | entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); | |
10239 | cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE)); | |
10240 | cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP)); | |
10241 | cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP)); | |
10242 | cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU)); | |
c4ad77e0 | 10243 | cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP)); |
8322ebbb DM |
10244 | |
10245 | #undef cr4_fixed1_update | |
10246 | } | |
10247 | ||
0e851880 SY |
10248 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
10249 | { | |
4e47c7a6 | 10250 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4e47c7a6 | 10251 | |
80154d77 PB |
10252 | if (cpu_has_secondary_exec_ctrls()) { |
10253 | vmx_compute_secondary_exec_control(vmx); | |
10254 | vmcs_set_secondary_exec_control(vmx->secondary_exec_control); | |
ad756a16 | 10255 | } |
8b3e34e4 | 10256 | |
37e4c997 HZ |
10257 | if (nested_vmx_allowed(vcpu)) |
10258 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
10259 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
10260 | else | |
10261 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
10262 | ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
8322ebbb DM |
10263 | |
10264 | if (nested_vmx_allowed(vcpu)) | |
10265 | nested_vmx_cr_fixed1_bits_update(vcpu); | |
0e851880 SY |
10266 | } |
10267 | ||
d4330ef2 JR |
10268 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
10269 | { | |
7b8050f5 NHE |
10270 | if (func == 1 && nested) |
10271 | entry->ecx |= bit(X86_FEATURE_VMX); | |
d4330ef2 JR |
10272 | } |
10273 | ||
25d92081 YZ |
10274 | static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, |
10275 | struct x86_exception *fault) | |
10276 | { | |
533558bc | 10277 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
c5f983f6 | 10278 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
533558bc | 10279 | u32 exit_reason; |
c5f983f6 | 10280 | unsigned long exit_qualification = vcpu->arch.exit_qualification; |
25d92081 | 10281 | |
c5f983f6 BD |
10282 | if (vmx->nested.pml_full) { |
10283 | exit_reason = EXIT_REASON_PML_FULL; | |
10284 | vmx->nested.pml_full = false; | |
10285 | exit_qualification &= INTR_INFO_UNBLOCK_NMI; | |
10286 | } else if (fault->error_code & PFERR_RSVD_MASK) | |
533558bc | 10287 | exit_reason = EXIT_REASON_EPT_MISCONFIG; |
25d92081 | 10288 | else |
533558bc | 10289 | exit_reason = EXIT_REASON_EPT_VIOLATION; |
c5f983f6 BD |
10290 | |
10291 | nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification); | |
25d92081 YZ |
10292 | vmcs12->guest_physical_address = fault->address; |
10293 | } | |
10294 | ||
995f00a6 PF |
10295 | static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu) |
10296 | { | |
bb97a016 | 10297 | return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT; |
995f00a6 PF |
10298 | } |
10299 | ||
155a97a3 NHE |
10300 | /* Callbacks for nested_ept_init_mmu_context: */ |
10301 | ||
10302 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu) | |
10303 | { | |
10304 | /* return the page table to be shadowed - in our case, EPT12 */ | |
10305 | return get_vmcs12(vcpu)->ept_pointer; | |
10306 | } | |
10307 | ||
ae1e2d10 | 10308 | static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) |
155a97a3 | 10309 | { |
ad896af0 | 10310 | WARN_ON(mmu_is_nested(vcpu)); |
a057e0e2 | 10311 | if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu))) |
ae1e2d10 PB |
10312 | return 1; |
10313 | ||
10314 | kvm_mmu_unload(vcpu); | |
ad896af0 | 10315 | kvm_init_shadow_ept_mmu(vcpu, |
6677f3da | 10316 | to_vmx(vcpu)->nested.msrs.ept_caps & |
ae1e2d10 | 10317 | VMX_EPT_EXECUTE_ONLY_BIT, |
a057e0e2 | 10318 | nested_ept_ad_enabled(vcpu)); |
155a97a3 NHE |
10319 | vcpu->arch.mmu.set_cr3 = vmx_set_cr3; |
10320 | vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3; | |
10321 | vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault; | |
10322 | ||
10323 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
ae1e2d10 | 10324 | return 0; |
155a97a3 NHE |
10325 | } |
10326 | ||
10327 | static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
10328 | { | |
10329 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
10330 | } | |
10331 | ||
19d5f10b EK |
10332 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, |
10333 | u16 error_code) | |
10334 | { | |
10335 | bool inequality, bit; | |
10336 | ||
10337 | bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0; | |
10338 | inequality = | |
10339 | (error_code & vmcs12->page_fault_error_code_mask) != | |
10340 | vmcs12->page_fault_error_code_match; | |
10341 | return inequality ^ bit; | |
10342 | } | |
10343 | ||
feaf0c7d GN |
10344 | static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, |
10345 | struct x86_exception *fault) | |
10346 | { | |
10347 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
10348 | ||
10349 | WARN_ON(!is_guest_mode(vcpu)); | |
10350 | ||
305d0ab4 WL |
10351 | if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) && |
10352 | !to_vmx(vcpu)->nested.nested_run_pending) { | |
b96fb439 PB |
10353 | vmcs12->vm_exit_intr_error_code = fault->error_code; |
10354 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
10355 | PF_VECTOR | INTR_TYPE_HARD_EXCEPTION | | |
10356 | INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK, | |
10357 | fault->address); | |
7313c698 | 10358 | } else { |
feaf0c7d | 10359 | kvm_inject_page_fault(vcpu, fault); |
7313c698 | 10360 | } |
feaf0c7d GN |
10361 | } |
10362 | ||
c992384b PB |
10363 | static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu, |
10364 | struct vmcs12 *vmcs12); | |
6beb7bd5 JM |
10365 | |
10366 | static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu, | |
a2bcba50 WL |
10367 | struct vmcs12 *vmcs12) |
10368 | { | |
10369 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5e2f30b7 | 10370 | struct page *page; |
6beb7bd5 | 10371 | u64 hpa; |
a2bcba50 WL |
10372 | |
10373 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
a2bcba50 WL |
10374 | /* |
10375 | * Translate L1 physical address to host physical | |
10376 | * address for vmcs02. Keep the page pinned, so this | |
10377 | * physical address remains valid. We keep a reference | |
10378 | * to it so we can release it later. | |
10379 | */ | |
5e2f30b7 | 10380 | if (vmx->nested.apic_access_page) { /* shouldn't happen */ |
53a70daf | 10381 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
5e2f30b7 DH |
10382 | vmx->nested.apic_access_page = NULL; |
10383 | } | |
10384 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr); | |
6beb7bd5 JM |
10385 | /* |
10386 | * If translation failed, no matter: This feature asks | |
10387 | * to exit when accessing the given address, and if it | |
10388 | * can never be accessed, this feature won't do | |
10389 | * anything anyway. | |
10390 | */ | |
5e2f30b7 DH |
10391 | if (!is_error_page(page)) { |
10392 | vmx->nested.apic_access_page = page; | |
6beb7bd5 JM |
10393 | hpa = page_to_phys(vmx->nested.apic_access_page); |
10394 | vmcs_write64(APIC_ACCESS_ADDR, hpa); | |
10395 | } else { | |
10396 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
10397 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
10398 | } | |
10399 | } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) && | |
10400 | cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { | |
10401 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
10402 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
10403 | kvm_vcpu_reload_apic_access_page(vcpu); | |
a2bcba50 | 10404 | } |
a7c0b07d WL |
10405 | |
10406 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
5e2f30b7 | 10407 | if (vmx->nested.virtual_apic_page) { /* shouldn't happen */ |
53a70daf | 10408 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
5e2f30b7 DH |
10409 | vmx->nested.virtual_apic_page = NULL; |
10410 | } | |
10411 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr); | |
a7c0b07d WL |
10412 | |
10413 | /* | |
6beb7bd5 JM |
10414 | * If translation failed, VM entry will fail because |
10415 | * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull. | |
10416 | * Failing the vm entry is _not_ what the processor | |
10417 | * does but it's basically the only possibility we | |
10418 | * have. We could still enter the guest if CR8 load | |
10419 | * exits are enabled, CR8 store exits are enabled, and | |
10420 | * virtualize APIC access is disabled; in this case | |
10421 | * the processor would never use the TPR shadow and we | |
10422 | * could simply clear the bit from the execution | |
10423 | * control. But such a configuration is useless, so | |
10424 | * let's keep the code simple. | |
a7c0b07d | 10425 | */ |
5e2f30b7 DH |
10426 | if (!is_error_page(page)) { |
10427 | vmx->nested.virtual_apic_page = page; | |
6beb7bd5 JM |
10428 | hpa = page_to_phys(vmx->nested.virtual_apic_page); |
10429 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa); | |
10430 | } | |
a7c0b07d WL |
10431 | } |
10432 | ||
705699a1 | 10433 | if (nested_cpu_has_posted_intr(vmcs12)) { |
705699a1 WV |
10434 | if (vmx->nested.pi_desc_page) { /* shouldn't happen */ |
10435 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 10436 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
5e2f30b7 | 10437 | vmx->nested.pi_desc_page = NULL; |
705699a1 | 10438 | } |
5e2f30b7 DH |
10439 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr); |
10440 | if (is_error_page(page)) | |
6beb7bd5 | 10441 | return; |
5e2f30b7 DH |
10442 | vmx->nested.pi_desc_page = page; |
10443 | vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page); | |
705699a1 WV |
10444 | vmx->nested.pi_desc = |
10445 | (struct pi_desc *)((void *)vmx->nested.pi_desc + | |
10446 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
10447 | (PAGE_SIZE - 1))); | |
6beb7bd5 JM |
10448 | vmcs_write64(POSTED_INTR_DESC_ADDR, |
10449 | page_to_phys(vmx->nested.pi_desc_page) + | |
10450 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
10451 | (PAGE_SIZE - 1))); | |
705699a1 | 10452 | } |
d4667ca1 | 10453 | if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12)) |
3712caeb KA |
10454 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
10455 | CPU_BASED_USE_MSR_BITMAPS); | |
6beb7bd5 JM |
10456 | else |
10457 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, | |
10458 | CPU_BASED_USE_MSR_BITMAPS); | |
a2bcba50 WL |
10459 | } |
10460 | ||
f4124500 JK |
10461 | static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu) |
10462 | { | |
10463 | u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value; | |
10464 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10465 | ||
10466 | if (vcpu->arch.virtual_tsc_khz == 0) | |
10467 | return; | |
10468 | ||
10469 | /* Make sure short timeouts reliably trigger an immediate vmexit. | |
10470 | * hrtimer_start does not guarantee this. */ | |
10471 | if (preemption_timeout <= 1) { | |
10472 | vmx_preemption_timer_fn(&vmx->nested.preemption_timer); | |
10473 | return; | |
10474 | } | |
10475 | ||
10476 | preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
10477 | preemption_timeout *= 1000000; | |
10478 | do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); | |
10479 | hrtimer_start(&vmx->nested.preemption_timer, | |
10480 | ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL); | |
10481 | } | |
10482 | ||
56a20510 JM |
10483 | static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu, |
10484 | struct vmcs12 *vmcs12) | |
10485 | { | |
10486 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) | |
10487 | return 0; | |
10488 | ||
10489 | if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) || | |
10490 | !page_address_valid(vcpu, vmcs12->io_bitmap_b)) | |
10491 | return -EINVAL; | |
10492 | ||
10493 | return 0; | |
10494 | } | |
10495 | ||
3af18d9c WV |
10496 | static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, |
10497 | struct vmcs12 *vmcs12) | |
10498 | { | |
3af18d9c WV |
10499 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
10500 | return 0; | |
10501 | ||
5fa99cbe | 10502 | if (!page_address_valid(vcpu, vmcs12->msr_bitmap)) |
3af18d9c WV |
10503 | return -EINVAL; |
10504 | ||
10505 | return 0; | |
10506 | } | |
10507 | ||
712b12d7 JM |
10508 | static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu, |
10509 | struct vmcs12 *vmcs12) | |
10510 | { | |
10511 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
10512 | return 0; | |
10513 | ||
10514 | if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr)) | |
10515 | return -EINVAL; | |
10516 | ||
10517 | return 0; | |
10518 | } | |
10519 | ||
3af18d9c WV |
10520 | /* |
10521 | * Merge L0's and L1's MSR bitmap, return false to indicate that | |
10522 | * we do not use the hardware. | |
10523 | */ | |
c992384b PB |
10524 | static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu, |
10525 | struct vmcs12 *vmcs12) | |
3af18d9c | 10526 | { |
82f0dd4b | 10527 | int msr; |
f2b93280 | 10528 | struct page *page; |
d048c098 | 10529 | unsigned long *msr_bitmap_l1; |
904e14fb | 10530 | unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap; |
15d45071 | 10531 | /* |
d28b387f | 10532 | * pred_cmd & spec_ctrl are trying to verify two things: |
15d45071 AR |
10533 | * |
10534 | * 1. L0 gave a permission to L1 to actually passthrough the MSR. This | |
10535 | * ensures that we do not accidentally generate an L02 MSR bitmap | |
10536 | * from the L12 MSR bitmap that is too permissive. | |
10537 | * 2. That L1 or L2s have actually used the MSR. This avoids | |
10538 | * unnecessarily merging of the bitmap if the MSR is unused. This | |
10539 | * works properly because we only update the L01 MSR bitmap lazily. | |
10540 | * So even if L0 should pass L1 these MSRs, the L01 bitmap is only | |
10541 | * updated to reflect this when L1 (or its L2s) actually write to | |
10542 | * the MSR. | |
10543 | */ | |
206587a9 KA |
10544 | bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD); |
10545 | bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL); | |
f2b93280 | 10546 | |
c992384b PB |
10547 | /* Nothing to do if the MSR bitmap is not in use. */ |
10548 | if (!cpu_has_vmx_msr_bitmap() || | |
10549 | !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) | |
10550 | return false; | |
10551 | ||
15d45071 | 10552 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && |
d28b387f | 10553 | !pred_cmd && !spec_ctrl) |
f2b93280 WV |
10554 | return false; |
10555 | ||
5e2f30b7 DH |
10556 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap); |
10557 | if (is_error_page(page)) | |
f2b93280 | 10558 | return false; |
f2b93280 | 10559 | |
c992384b PB |
10560 | msr_bitmap_l1 = (unsigned long *)kmap(page); |
10561 | if (nested_cpu_has_apic_reg_virt(vmcs12)) { | |
10562 | /* | |
10563 | * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it | |
10564 | * just lets the processor take the value from the virtual-APIC page; | |
10565 | * take those 256 bits directly from the L1 bitmap. | |
10566 | */ | |
10567 | for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { | |
10568 | unsigned word = msr / BITS_PER_LONG; | |
10569 | msr_bitmap_l0[word] = msr_bitmap_l1[word]; | |
10570 | msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0; | |
10571 | } | |
10572 | } else { | |
10573 | for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { | |
10574 | unsigned word = msr / BITS_PER_LONG; | |
10575 | msr_bitmap_l0[word] = ~0; | |
10576 | msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0; | |
10577 | } | |
10578 | } | |
d048c098 | 10579 | |
c992384b PB |
10580 | nested_vmx_disable_intercept_for_msr( |
10581 | msr_bitmap_l1, msr_bitmap_l0, | |
d7231e75 | 10582 | X2APIC_MSR(APIC_TASKPRI), |
c992384b | 10583 | MSR_TYPE_W); |
d048c098 | 10584 | |
c992384b | 10585 | if (nested_cpu_has_vid(vmcs12)) { |
d048c098 | 10586 | nested_vmx_disable_intercept_for_msr( |
c992384b | 10587 | msr_bitmap_l1, msr_bitmap_l0, |
d7231e75 | 10588 | X2APIC_MSR(APIC_EOI), |
c992384b PB |
10589 | MSR_TYPE_W); |
10590 | nested_vmx_disable_intercept_for_msr( | |
10591 | msr_bitmap_l1, msr_bitmap_l0, | |
d7231e75 | 10592 | X2APIC_MSR(APIC_SELF_IPI), |
c992384b | 10593 | MSR_TYPE_W); |
82f0dd4b | 10594 | } |
15d45071 | 10595 | |
d28b387f KA |
10596 | if (spec_ctrl) |
10597 | nested_vmx_disable_intercept_for_msr( | |
10598 | msr_bitmap_l1, msr_bitmap_l0, | |
10599 | MSR_IA32_SPEC_CTRL, | |
10600 | MSR_TYPE_R | MSR_TYPE_W); | |
10601 | ||
15d45071 AR |
10602 | if (pred_cmd) |
10603 | nested_vmx_disable_intercept_for_msr( | |
10604 | msr_bitmap_l1, msr_bitmap_l0, | |
10605 | MSR_IA32_PRED_CMD, | |
10606 | MSR_TYPE_W); | |
10607 | ||
f2b93280 | 10608 | kunmap(page); |
53a70daf | 10609 | kvm_release_page_clean(page); |
f2b93280 WV |
10610 | |
10611 | return true; | |
10612 | } | |
10613 | ||
f0f4cf5b KS |
10614 | static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu, |
10615 | struct vmcs12 *vmcs12) | |
10616 | { | |
10617 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) && | |
10618 | !page_address_valid(vcpu, vmcs12->apic_access_addr)) | |
10619 | return -EINVAL; | |
10620 | else | |
10621 | return 0; | |
10622 | } | |
10623 | ||
f2b93280 WV |
10624 | static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu, |
10625 | struct vmcs12 *vmcs12) | |
10626 | { | |
82f0dd4b | 10627 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && |
608406e2 | 10628 | !nested_cpu_has_apic_reg_virt(vmcs12) && |
705699a1 WV |
10629 | !nested_cpu_has_vid(vmcs12) && |
10630 | !nested_cpu_has_posted_intr(vmcs12)) | |
f2b93280 WV |
10631 | return 0; |
10632 | ||
10633 | /* | |
10634 | * If virtualize x2apic mode is enabled, | |
10635 | * virtualize apic access must be disabled. | |
10636 | */ | |
82f0dd4b WV |
10637 | if (nested_cpu_has_virt_x2apic_mode(vmcs12) && |
10638 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
f2b93280 WV |
10639 | return -EINVAL; |
10640 | ||
608406e2 WV |
10641 | /* |
10642 | * If virtual interrupt delivery is enabled, | |
10643 | * we must exit on external interrupts. | |
10644 | */ | |
10645 | if (nested_cpu_has_vid(vmcs12) && | |
10646 | !nested_exit_on_intr(vcpu)) | |
10647 | return -EINVAL; | |
10648 | ||
705699a1 WV |
10649 | /* |
10650 | * bits 15:8 should be zero in posted_intr_nv, | |
10651 | * the descriptor address has been already checked | |
10652 | * in nested_get_vmcs12_pages. | |
10653 | */ | |
10654 | if (nested_cpu_has_posted_intr(vmcs12) && | |
10655 | (!nested_cpu_has_vid(vmcs12) || | |
10656 | !nested_exit_intr_ack_set(vcpu) || | |
10657 | vmcs12->posted_intr_nv & 0xff00)) | |
10658 | return -EINVAL; | |
10659 | ||
f2b93280 WV |
10660 | /* tpr shadow is needed by all apicv features. */ |
10661 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
10662 | return -EINVAL; | |
10663 | ||
10664 | return 0; | |
3af18d9c WV |
10665 | } |
10666 | ||
e9ac033e EK |
10667 | static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu, |
10668 | unsigned long count_field, | |
92d71bc6 | 10669 | unsigned long addr_field) |
ff651cb6 | 10670 | { |
92d71bc6 | 10671 | int maxphyaddr; |
e9ac033e EK |
10672 | u64 count, addr; |
10673 | ||
10674 | if (vmcs12_read_any(vcpu, count_field, &count) || | |
10675 | vmcs12_read_any(vcpu, addr_field, &addr)) { | |
10676 | WARN_ON(1); | |
10677 | return -EINVAL; | |
10678 | } | |
10679 | if (count == 0) | |
10680 | return 0; | |
92d71bc6 | 10681 | maxphyaddr = cpuid_maxphyaddr(vcpu); |
e9ac033e EK |
10682 | if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr || |
10683 | (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) { | |
bbe41b95 | 10684 | pr_debug_ratelimited( |
e9ac033e EK |
10685 | "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)", |
10686 | addr_field, maxphyaddr, count, addr); | |
10687 | return -EINVAL; | |
10688 | } | |
10689 | return 0; | |
10690 | } | |
10691 | ||
10692 | static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu, | |
10693 | struct vmcs12 *vmcs12) | |
10694 | { | |
e9ac033e EK |
10695 | if (vmcs12->vm_exit_msr_load_count == 0 && |
10696 | vmcs12->vm_exit_msr_store_count == 0 && | |
10697 | vmcs12->vm_entry_msr_load_count == 0) | |
10698 | return 0; /* Fast path */ | |
e9ac033e | 10699 | if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT, |
92d71bc6 | 10700 | VM_EXIT_MSR_LOAD_ADDR) || |
e9ac033e | 10701 | nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT, |
92d71bc6 | 10702 | VM_EXIT_MSR_STORE_ADDR) || |
e9ac033e | 10703 | nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT, |
92d71bc6 | 10704 | VM_ENTRY_MSR_LOAD_ADDR)) |
e9ac033e EK |
10705 | return -EINVAL; |
10706 | return 0; | |
10707 | } | |
10708 | ||
c5f983f6 BD |
10709 | static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu, |
10710 | struct vmcs12 *vmcs12) | |
10711 | { | |
10712 | u64 address = vmcs12->pml_address; | |
10713 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
10714 | ||
10715 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) { | |
10716 | if (!nested_cpu_has_ept(vmcs12) || | |
10717 | !IS_ALIGNED(address, 4096) || | |
10718 | address >> maxphyaddr) | |
10719 | return -EINVAL; | |
10720 | } | |
10721 | ||
10722 | return 0; | |
10723 | } | |
10724 | ||
e9ac033e EK |
10725 | static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu, |
10726 | struct vmx_msr_entry *e) | |
10727 | { | |
10728 | /* x2APIC MSR accesses are not allowed */ | |
8a9781f7 | 10729 | if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8) |
e9ac033e EK |
10730 | return -EINVAL; |
10731 | if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */ | |
10732 | e->index == MSR_IA32_UCODE_REV) | |
10733 | return -EINVAL; | |
10734 | if (e->reserved != 0) | |
ff651cb6 WV |
10735 | return -EINVAL; |
10736 | return 0; | |
10737 | } | |
10738 | ||
e9ac033e EK |
10739 | static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu, |
10740 | struct vmx_msr_entry *e) | |
ff651cb6 WV |
10741 | { |
10742 | if (e->index == MSR_FS_BASE || | |
10743 | e->index == MSR_GS_BASE || | |
e9ac033e EK |
10744 | e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */ |
10745 | nested_vmx_msr_check_common(vcpu, e)) | |
10746 | return -EINVAL; | |
10747 | return 0; | |
10748 | } | |
10749 | ||
10750 | static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu, | |
10751 | struct vmx_msr_entry *e) | |
10752 | { | |
10753 | if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */ | |
10754 | nested_vmx_msr_check_common(vcpu, e)) | |
ff651cb6 WV |
10755 | return -EINVAL; |
10756 | return 0; | |
10757 | } | |
10758 | ||
10759 | /* | |
10760 | * Load guest's/host's msr at nested entry/exit. | |
10761 | * return 0 for success, entry index for failure. | |
10762 | */ | |
10763 | static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
10764 | { | |
10765 | u32 i; | |
10766 | struct vmx_msr_entry e; | |
10767 | struct msr_data msr; | |
10768 | ||
10769 | msr.host_initiated = false; | |
10770 | for (i = 0; i < count; i++) { | |
54bf36aa PB |
10771 | if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e), |
10772 | &e, sizeof(e))) { | |
bbe41b95 | 10773 | pr_debug_ratelimited( |
e9ac033e EK |
10774 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
10775 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 10776 | goto fail; |
e9ac033e EK |
10777 | } |
10778 | if (nested_vmx_load_msr_check(vcpu, &e)) { | |
bbe41b95 | 10779 | pr_debug_ratelimited( |
e9ac033e EK |
10780 | "%s check failed (%u, 0x%x, 0x%x)\n", |
10781 | __func__, i, e.index, e.reserved); | |
10782 | goto fail; | |
10783 | } | |
ff651cb6 WV |
10784 | msr.index = e.index; |
10785 | msr.data = e.value; | |
e9ac033e | 10786 | if (kvm_set_msr(vcpu, &msr)) { |
bbe41b95 | 10787 | pr_debug_ratelimited( |
e9ac033e EK |
10788 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
10789 | __func__, i, e.index, e.value); | |
ff651cb6 | 10790 | goto fail; |
e9ac033e | 10791 | } |
ff651cb6 WV |
10792 | } |
10793 | return 0; | |
10794 | fail: | |
10795 | return i + 1; | |
10796 | } | |
10797 | ||
10798 | static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
10799 | { | |
10800 | u32 i; | |
10801 | struct vmx_msr_entry e; | |
10802 | ||
10803 | for (i = 0; i < count; i++) { | |
609e36d3 | 10804 | struct msr_data msr_info; |
54bf36aa PB |
10805 | if (kvm_vcpu_read_guest(vcpu, |
10806 | gpa + i * sizeof(e), | |
10807 | &e, 2 * sizeof(u32))) { | |
bbe41b95 | 10808 | pr_debug_ratelimited( |
e9ac033e EK |
10809 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
10810 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 10811 | return -EINVAL; |
e9ac033e EK |
10812 | } |
10813 | if (nested_vmx_store_msr_check(vcpu, &e)) { | |
bbe41b95 | 10814 | pr_debug_ratelimited( |
e9ac033e EK |
10815 | "%s check failed (%u, 0x%x, 0x%x)\n", |
10816 | __func__, i, e.index, e.reserved); | |
ff651cb6 | 10817 | return -EINVAL; |
e9ac033e | 10818 | } |
609e36d3 PB |
10819 | msr_info.host_initiated = false; |
10820 | msr_info.index = e.index; | |
10821 | if (kvm_get_msr(vcpu, &msr_info)) { | |
bbe41b95 | 10822 | pr_debug_ratelimited( |
e9ac033e EK |
10823 | "%s cannot read MSR (%u, 0x%x)\n", |
10824 | __func__, i, e.index); | |
10825 | return -EINVAL; | |
10826 | } | |
54bf36aa PB |
10827 | if (kvm_vcpu_write_guest(vcpu, |
10828 | gpa + i * sizeof(e) + | |
10829 | offsetof(struct vmx_msr_entry, value), | |
10830 | &msr_info.data, sizeof(msr_info.data))) { | |
bbe41b95 | 10831 | pr_debug_ratelimited( |
e9ac033e | 10832 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
609e36d3 | 10833 | __func__, i, e.index, msr_info.data); |
e9ac033e EK |
10834 | return -EINVAL; |
10835 | } | |
ff651cb6 WV |
10836 | } |
10837 | return 0; | |
10838 | } | |
10839 | ||
1dc35dac LP |
10840 | static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val) |
10841 | { | |
10842 | unsigned long invalid_mask; | |
10843 | ||
10844 | invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu); | |
10845 | return (val & invalid_mask) == 0; | |
10846 | } | |
10847 | ||
9ed38ffa LP |
10848 | /* |
10849 | * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are | |
10850 | * emulating VM entry into a guest with EPT enabled. | |
10851 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code | |
10852 | * is assigned to entry_failure_code on failure. | |
10853 | */ | |
10854 | static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept, | |
ca0bde28 | 10855 | u32 *entry_failure_code) |
9ed38ffa | 10856 | { |
9ed38ffa | 10857 | if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) { |
1dc35dac | 10858 | if (!nested_cr3_valid(vcpu, cr3)) { |
9ed38ffa LP |
10859 | *entry_failure_code = ENTRY_FAIL_DEFAULT; |
10860 | return 1; | |
10861 | } | |
10862 | ||
10863 | /* | |
10864 | * If PAE paging and EPT are both on, CR3 is not used by the CPU and | |
10865 | * must not be dereferenced. | |
10866 | */ | |
10867 | if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) && | |
10868 | !nested_ept) { | |
10869 | if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) { | |
10870 | *entry_failure_code = ENTRY_FAIL_PDPTE; | |
10871 | return 1; | |
10872 | } | |
10873 | } | |
10874 | ||
10875 | vcpu->arch.cr3 = cr3; | |
10876 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
10877 | } | |
10878 | ||
10879 | kvm_mmu_reset_context(vcpu); | |
10880 | return 0; | |
10881 | } | |
10882 | ||
74a497fa PB |
10883 | static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, |
10884 | bool from_vmentry) | |
fe3ef05c NHE |
10885 | { |
10886 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
fe3ef05c NHE |
10887 | |
10888 | vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); | |
fe3ef05c NHE |
10889 | vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); |
10890 | vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); | |
10891 | vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); | |
10892 | vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); | |
10893 | vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); | |
10894 | vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); | |
10895 | vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); | |
fe3ef05c NHE |
10896 | vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); |
10897 | vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); | |
10898 | vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); | |
10899 | vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); | |
10900 | vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); | |
10901 | vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); | |
10902 | vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); | |
10903 | vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); | |
10904 | vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); | |
fe3ef05c NHE |
10905 | vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); |
10906 | vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); | |
10907 | vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); | |
10908 | vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); | |
10909 | vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); | |
10910 | vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); | |
fe3ef05c NHE |
10911 | vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); |
10912 | vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); | |
10913 | vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); | |
10914 | vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); | |
10915 | vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); | |
10916 | vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); | |
10917 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); | |
10918 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); | |
10919 | ||
25a2e4fe PB |
10920 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); |
10921 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, | |
10922 | vmcs12->guest_pending_dbg_exceptions); | |
10923 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); | |
10924 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); | |
10925 | ||
10926 | if (nested_cpu_has_xsaves(vmcs12)) | |
10927 | vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); | |
10928 | vmcs_write64(VMCS_LINK_POINTER, -1ull); | |
10929 | ||
10930 | if (cpu_has_vmx_posted_intr()) | |
10931 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR); | |
10932 | ||
10933 | /* | |
10934 | * Whether page-faults are trapped is determined by a combination of | |
10935 | * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. | |
10936 | * If enable_ept, L0 doesn't care about page faults and we should | |
10937 | * set all of these to L1's desires. However, if !enable_ept, L0 does | |
10938 | * care about (at least some) page faults, and because it is not easy | |
10939 | * (if at all possible?) to merge L0 and L1's desires, we simply ask | |
10940 | * to exit on each and every L2 page fault. This is done by setting | |
10941 | * MASK=MATCH=0 and (see below) EB.PF=1. | |
10942 | * Note that below we don't need special code to set EB.PF beyond the | |
10943 | * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, | |
10944 | * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when | |
10945 | * !enable_ept, EB.PF is 1, so the "or" will always be 1. | |
10946 | */ | |
10947 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, | |
10948 | enable_ept ? vmcs12->page_fault_error_code_mask : 0); | |
10949 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, | |
10950 | enable_ept ? vmcs12->page_fault_error_code_match : 0); | |
10951 | ||
10952 | /* All VMFUNCs are currently emulated through L0 vmexits. */ | |
10953 | if (cpu_has_vmx_vmfunc()) | |
10954 | vmcs_write64(VM_FUNCTION_CONTROL, 0); | |
10955 | ||
10956 | if (cpu_has_vmx_apicv()) { | |
10957 | vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0); | |
10958 | vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1); | |
10959 | vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2); | |
10960 | vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3); | |
10961 | } | |
10962 | ||
10963 | /* | |
10964 | * Set host-state according to L0's settings (vmcs12 is irrelevant here) | |
10965 | * Some constant fields are set here by vmx_set_constant_host_state(). | |
10966 | * Other fields are different per CPU, and will be set later when | |
10967 | * vmx_vcpu_load() is called, and when vmx_save_host_state() is called. | |
10968 | */ | |
10969 | vmx_set_constant_host_state(vmx); | |
10970 | ||
10971 | /* | |
10972 | * Set the MSR load/store lists to match L0's settings. | |
10973 | */ | |
10974 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); | |
10975 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
10976 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); | |
10977 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
10978 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); | |
10979 | ||
10980 | set_cr4_guest_host_mask(vmx); | |
10981 | ||
10982 | if (vmx_mpx_supported()) | |
10983 | vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); | |
10984 | ||
10985 | if (enable_vpid) { | |
10986 | if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) | |
10987 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02); | |
10988 | else | |
10989 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
10990 | } | |
10991 | ||
10992 | /* | |
10993 | * L1 may access the L2's PDPTR, so save them to construct vmcs12 | |
10994 | */ | |
10995 | if (enable_ept) { | |
10996 | vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); | |
10997 | vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); | |
10998 | vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); | |
10999 | vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); | |
11000 | } | |
80132f4c RK |
11001 | |
11002 | if (cpu_has_vmx_msr_bitmap()) | |
11003 | vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap)); | |
8665c3f9 PB |
11004 | } |
11005 | ||
11006 | /* | |
11007 | * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested | |
11008 | * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it | |
11009 | * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 | |
11010 | * guest in a way that will both be appropriate to L1's requests, and our | |
11011 | * needs. In addition to modifying the active vmcs (which is vmcs02), this | |
11012 | * function also has additional necessary side-effects, like setting various | |
11013 | * vcpu->arch fields. | |
11014 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code | |
11015 | * is assigned to entry_failure_code on failure. | |
11016 | */ | |
11017 | static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
11018 | bool from_vmentry, u32 *entry_failure_code) | |
11019 | { | |
11020 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
11021 | u32 exec_control, vmcs12_exec_ctrl; | |
11022 | ||
9d1887ef SC |
11023 | if (vmx->nested.dirty_vmcs12) { |
11024 | prepare_vmcs02_full(vcpu, vmcs12, from_vmentry); | |
11025 | vmx->nested.dirty_vmcs12 = false; | |
11026 | } | |
11027 | ||
8665c3f9 PB |
11028 | /* |
11029 | * First, the fields that are shadowed. This must be kept in sync | |
11030 | * with vmx_shadow_fields.h. | |
11031 | */ | |
11032 | ||
11033 | vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); | |
11034 | vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); | |
11035 | vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); | |
11036 | vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); | |
11037 | vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); | |
11038 | ||
11039 | /* | |
11040 | * Not in vmcs02: GUEST_PML_INDEX, HOST_FS_SELECTOR, HOST_GS_SELECTOR, | |
11041 | * HOST_FS_BASE, HOST_GS_BASE. | |
11042 | */ | |
fe3ef05c | 11043 | |
cf8b84f4 JM |
11044 | if (from_vmentry && |
11045 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) { | |
2996fca0 JK |
11046 | kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); |
11047 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); | |
11048 | } else { | |
11049 | kvm_set_dr(vcpu, 7, vcpu->arch.dr7); | |
11050 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl); | |
11051 | } | |
cf8b84f4 JM |
11052 | if (from_vmentry) { |
11053 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
11054 | vmcs12->vm_entry_intr_info_field); | |
11055 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
11056 | vmcs12->vm_entry_exception_error_code); | |
11057 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
11058 | vmcs12->vm_entry_instruction_len); | |
11059 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
11060 | vmcs12->guest_interruptibility_info); | |
2d6144e3 WL |
11061 | vmx->loaded_vmcs->nmi_known_unmasked = |
11062 | !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI); | |
cf8b84f4 JM |
11063 | } else { |
11064 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
11065 | } | |
63fbf59f | 11066 | vmx_set_rflags(vcpu, vmcs12->guest_rflags); |
fe3ef05c | 11067 | |
f4124500 | 11068 | exec_control = vmcs12->pin_based_vm_exec_control; |
9314006d PB |
11069 | |
11070 | /* Preemption timer setting is only taken from vmcs01. */ | |
705699a1 | 11071 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; |
9314006d PB |
11072 | exec_control |= vmcs_config.pin_based_exec_ctrl; |
11073 | if (vmx->hv_deadline_tsc == -1) | |
11074 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
705699a1 | 11075 | |
9314006d | 11076 | /* Posted interrupts setting is only taken from vmcs12. */ |
705699a1 | 11077 | if (nested_cpu_has_posted_intr(vmcs12)) { |
705699a1 WV |
11078 | vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv; |
11079 | vmx->nested.pi_pending = false; | |
6beb7bd5 | 11080 | } else { |
705699a1 | 11081 | exec_control &= ~PIN_BASED_POSTED_INTR; |
6beb7bd5 | 11082 | } |
705699a1 | 11083 | |
f4124500 | 11084 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control); |
fe3ef05c | 11085 | |
f4124500 JK |
11086 | vmx->nested.preemption_timer_expired = false; |
11087 | if (nested_cpu_has_preemption_timer(vmcs12)) | |
11088 | vmx_start_preemption_timer(vcpu); | |
0238ea91 | 11089 | |
fe3ef05c | 11090 | if (cpu_has_secondary_exec_ctrls()) { |
80154d77 | 11091 | exec_control = vmx->secondary_exec_control; |
e2821620 | 11092 | |
fe3ef05c | 11093 | /* Take the following fields only from vmcs12 */ |
696dfd95 | 11094 | exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
90a2db6d | 11095 | SECONDARY_EXEC_ENABLE_INVPCID | |
b3a2a907 | 11096 | SECONDARY_EXEC_RDTSCP | |
3db13480 | 11097 | SECONDARY_EXEC_XSAVES | |
696dfd95 | 11098 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
27c42a1b BD |
11099 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
11100 | SECONDARY_EXEC_ENABLE_VMFUNC); | |
fe3ef05c | 11101 | if (nested_cpu_has(vmcs12, |
03efce6f BD |
11102 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) { |
11103 | vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control & | |
11104 | ~SECONDARY_EXEC_ENABLE_PML; | |
11105 | exec_control |= vmcs12_exec_ctrl; | |
11106 | } | |
fe3ef05c | 11107 | |
25a2e4fe | 11108 | if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) |
608406e2 WV |
11109 | vmcs_write16(GUEST_INTR_STATUS, |
11110 | vmcs12->guest_intr_status); | |
608406e2 | 11111 | |
6beb7bd5 JM |
11112 | /* |
11113 | * Write an illegal value to APIC_ACCESS_ADDR. Later, | |
11114 | * nested_get_vmcs12_pages will either fix it up or | |
11115 | * remove the VM execution control. | |
11116 | */ | |
11117 | if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) | |
11118 | vmcs_write64(APIC_ACCESS_ADDR, -1ull); | |
11119 | ||
fe3ef05c NHE |
11120 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
11121 | } | |
11122 | ||
fe3ef05c NHE |
11123 | /* |
11124 | * HOST_RSP is normally set correctly in vmx_vcpu_run() just before | |
11125 | * entry, but only if the current (host) sp changed from the value | |
11126 | * we wrote last (vmx->host_rsp). This cache is no longer relevant | |
11127 | * if we switch vmcs, and rather than hold a separate cache per vmcs, | |
11128 | * here we just force the write to happen on entry. | |
11129 | */ | |
11130 | vmx->host_rsp = 0; | |
11131 | ||
11132 | exec_control = vmx_exec_control(vmx); /* L0's desires */ | |
11133 | exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
11134 | exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
11135 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
11136 | exec_control |= vmcs12->cpu_based_vm_exec_control; | |
a7c0b07d | 11137 | |
6beb7bd5 JM |
11138 | /* |
11139 | * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if | |
11140 | * nested_get_vmcs12_pages can't fix it up, the illegal value | |
11141 | * will result in a VM entry failure. | |
11142 | */ | |
a7c0b07d | 11143 | if (exec_control & CPU_BASED_TPR_SHADOW) { |
6beb7bd5 | 11144 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull); |
a7c0b07d | 11145 | vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); |
51aa68e7 JM |
11146 | } else { |
11147 | #ifdef CONFIG_X86_64 | |
11148 | exec_control |= CPU_BASED_CR8_LOAD_EXITING | | |
11149 | CPU_BASED_CR8_STORE_EXITING; | |
11150 | #endif | |
a7c0b07d WL |
11151 | } |
11152 | ||
fe3ef05c | 11153 | /* |
8eb73e2d QX |
11154 | * A vmexit (to either L1 hypervisor or L0 userspace) is always needed |
11155 | * for I/O port accesses. | |
fe3ef05c | 11156 | */ |
fe3ef05c NHE |
11157 | exec_control &= ~CPU_BASED_USE_IO_BITMAPS; |
11158 | exec_control |= CPU_BASED_UNCOND_IO_EXITING; | |
11159 | ||
11160 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
11161 | ||
11162 | /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the | |
11163 | * bitwise-or of what L1 wants to trap for L2, and what we want to | |
11164 | * trap. Note that CR0.TS also needs updating - we do this later. | |
11165 | */ | |
11166 | update_exception_bitmap(vcpu); | |
11167 | vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; | |
11168 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
11169 | ||
8049d651 NHE |
11170 | /* L2->L1 exit controls are emulated - the hardware exit is to L0 so |
11171 | * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER | |
11172 | * bits are further modified by vmx_set_efer() below. | |
11173 | */ | |
f4124500 | 11174 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
8049d651 NHE |
11175 | |
11176 | /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are | |
11177 | * emulated by vmx_set_efer(), below. | |
11178 | */ | |
2961e876 | 11179 | vm_entry_controls_init(vmx, |
8049d651 NHE |
11180 | (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER & |
11181 | ~VM_ENTRY_IA32E_MODE) | | |
fe3ef05c NHE |
11182 | (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE)); |
11183 | ||
cf8b84f4 JM |
11184 | if (from_vmentry && |
11185 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) { | |
fe3ef05c | 11186 | vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); |
44811c02 | 11187 | vcpu->arch.pat = vmcs12->guest_ia32_pat; |
cf8b84f4 | 11188 | } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { |
fe3ef05c | 11189 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); |
cf8b84f4 | 11190 | } |
fe3ef05c | 11191 | |
e79f245d KA |
11192 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
11193 | ||
c95ba92a PF |
11194 | if (kvm_has_tsc_control) |
11195 | decache_tsc_multiplier(vmx); | |
fe3ef05c NHE |
11196 | |
11197 | if (enable_vpid) { | |
11198 | /* | |
5c614b35 WL |
11199 | * There is no direct mapping between vpid02 and vpid12, the |
11200 | * vpid02 is per-vCPU for L0 and reused while the value of | |
11201 | * vpid12 is changed w/ one invvpid during nested vmentry. | |
11202 | * The vpid12 is allocated by L1 for L2, so it will not | |
11203 | * influence global bitmap(for vpid01 and vpid02 allocation) | |
11204 | * even if spawn a lot of nested vCPUs. | |
fe3ef05c | 11205 | */ |
5c614b35 | 11206 | if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) { |
5c614b35 WL |
11207 | if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) { |
11208 | vmx->nested.last_vpid = vmcs12->virtual_processor_id; | |
c2ba05cc | 11209 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02, true); |
5c614b35 WL |
11210 | } |
11211 | } else { | |
c2ba05cc | 11212 | vmx_flush_tlb(vcpu, true); |
5c614b35 | 11213 | } |
fe3ef05c NHE |
11214 | } |
11215 | ||
1fb883bb LP |
11216 | if (enable_pml) { |
11217 | /* | |
11218 | * Conceptually we want to copy the PML address and index from | |
11219 | * vmcs01 here, and then back to vmcs01 on nested vmexit. But, | |
11220 | * since we always flush the log on each vmexit, this happens | |
11221 | * to be equivalent to simply resetting the fields in vmcs02. | |
11222 | */ | |
11223 | ASSERT(vmx->pml_pg); | |
11224 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
11225 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
11226 | } | |
11227 | ||
155a97a3 | 11228 | if (nested_cpu_has_ept(vmcs12)) { |
ae1e2d10 PB |
11229 | if (nested_ept_init_mmu_context(vcpu)) { |
11230 | *entry_failure_code = ENTRY_FAIL_DEFAULT; | |
11231 | return 1; | |
11232 | } | |
fb6c8198 JM |
11233 | } else if (nested_cpu_has2(vmcs12, |
11234 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
a468f2db | 11235 | vmx_flush_tlb(vcpu, true); |
155a97a3 NHE |
11236 | } |
11237 | ||
fe3ef05c | 11238 | /* |
bd7e5b08 PB |
11239 | * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those |
11240 | * bits which we consider mandatory enabled. | |
fe3ef05c NHE |
11241 | * The CR0_READ_SHADOW is what L2 should have expected to read given |
11242 | * the specifications by L1; It's not enough to take | |
11243 | * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we | |
11244 | * have more bits than L1 expected. | |
11245 | */ | |
11246 | vmx_set_cr0(vcpu, vmcs12->guest_cr0); | |
11247 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
11248 | ||
11249 | vmx_set_cr4(vcpu, vmcs12->guest_cr4); | |
11250 | vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); | |
11251 | ||
cf8b84f4 JM |
11252 | if (from_vmentry && |
11253 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) | |
5a6a9748 DM |
11254 | vcpu->arch.efer = vmcs12->guest_ia32_efer; |
11255 | else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) | |
11256 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); | |
11257 | else | |
11258 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
11259 | /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ | |
11260 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
11261 | ||
2bb8cafe SC |
11262 | /* |
11263 | * Guest state is invalid and unrestricted guest is disabled, | |
11264 | * which means L1 attempted VMEntry to L2 with invalid state. | |
11265 | * Fail the VMEntry. | |
11266 | */ | |
3184a995 PB |
11267 | if (vmx->emulation_required) { |
11268 | *entry_failure_code = ENTRY_FAIL_DEFAULT; | |
2bb8cafe | 11269 | return 1; |
3184a995 | 11270 | } |
2bb8cafe | 11271 | |
9ed38ffa | 11272 | /* Shadow page tables on either EPT or shadow page tables. */ |
7ad658b6 | 11273 | if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12), |
9ed38ffa LP |
11274 | entry_failure_code)) |
11275 | return 1; | |
7ca29de2 | 11276 | |
feaf0c7d GN |
11277 | if (!enable_ept) |
11278 | vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; | |
11279 | ||
fe3ef05c NHE |
11280 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp); |
11281 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip); | |
ee146c1c | 11282 | return 0; |
fe3ef05c NHE |
11283 | } |
11284 | ||
0c7f650e KS |
11285 | static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12) |
11286 | { | |
11287 | if (!nested_cpu_has_nmi_exiting(vmcs12) && | |
11288 | nested_cpu_has_virtual_nmis(vmcs12)) | |
11289 | return -EINVAL; | |
11290 | ||
11291 | if (!nested_cpu_has_virtual_nmis(vmcs12) && | |
11292 | nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING)) | |
11293 | return -EINVAL; | |
11294 | ||
11295 | return 0; | |
11296 | } | |
11297 | ||
ca0bde28 | 11298 | static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) |
cd232ad0 | 11299 | { |
cd232ad0 | 11300 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7c177938 | 11301 | |
6dfacadd | 11302 | if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && |
ca0bde28 JM |
11303 | vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) |
11304 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
26539bd0 | 11305 | |
56a20510 JM |
11306 | if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12)) |
11307 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11308 | ||
ca0bde28 JM |
11309 | if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) |
11310 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
7c177938 | 11311 | |
f0f4cf5b KS |
11312 | if (nested_vmx_check_apic_access_controls(vcpu, vmcs12)) |
11313 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11314 | ||
712b12d7 JM |
11315 | if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12)) |
11316 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11317 | ||
ca0bde28 JM |
11318 | if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) |
11319 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
f2b93280 | 11320 | |
ca0bde28 JM |
11321 | if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) |
11322 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
e9ac033e | 11323 | |
c5f983f6 BD |
11324 | if (nested_vmx_check_pml_controls(vcpu, vmcs12)) |
11325 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11326 | ||
7c177938 | 11327 | if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, |
6677f3da PB |
11328 | vmx->nested.msrs.procbased_ctls_low, |
11329 | vmx->nested.msrs.procbased_ctls_high) || | |
2e5b0bd9 JM |
11330 | (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && |
11331 | !vmx_control_verify(vmcs12->secondary_vm_exec_control, | |
6677f3da PB |
11332 | vmx->nested.msrs.secondary_ctls_low, |
11333 | vmx->nested.msrs.secondary_ctls_high)) || | |
7c177938 | 11334 | !vmx_control_verify(vmcs12->pin_based_vm_exec_control, |
6677f3da PB |
11335 | vmx->nested.msrs.pinbased_ctls_low, |
11336 | vmx->nested.msrs.pinbased_ctls_high) || | |
7c177938 | 11337 | !vmx_control_verify(vmcs12->vm_exit_controls, |
6677f3da PB |
11338 | vmx->nested.msrs.exit_ctls_low, |
11339 | vmx->nested.msrs.exit_ctls_high) || | |
7c177938 | 11340 | !vmx_control_verify(vmcs12->vm_entry_controls, |
6677f3da PB |
11341 | vmx->nested.msrs.entry_ctls_low, |
11342 | vmx->nested.msrs.entry_ctls_high)) | |
ca0bde28 | 11343 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; |
7c177938 | 11344 | |
0c7f650e | 11345 | if (nested_vmx_check_nmi_controls(vmcs12)) |
ca0bde28 | 11346 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; |
7c177938 | 11347 | |
41ab9372 BD |
11348 | if (nested_cpu_has_vmfunc(vmcs12)) { |
11349 | if (vmcs12->vm_function_control & | |
6677f3da | 11350 | ~vmx->nested.msrs.vmfunc_controls) |
41ab9372 BD |
11351 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; |
11352 | ||
11353 | if (nested_cpu_has_eptp_switching(vmcs12)) { | |
11354 | if (!nested_cpu_has_ept(vmcs12) || | |
11355 | !page_address_valid(vcpu, vmcs12->eptp_list_address)) | |
11356 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11357 | } | |
11358 | } | |
27c42a1b | 11359 | |
c7c2c709 JM |
11360 | if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) |
11361 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11362 | ||
3899152c | 11363 | if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) || |
1dc35dac | 11364 | !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) || |
ca0bde28 JM |
11365 | !nested_cr3_valid(vcpu, vmcs12->host_cr3)) |
11366 | return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; | |
11367 | ||
11368 | return 0; | |
11369 | } | |
11370 | ||
11371 | static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
11372 | u32 *exit_qual) | |
11373 | { | |
11374 | bool ia32e; | |
11375 | ||
11376 | *exit_qual = ENTRY_FAIL_DEFAULT; | |
7c177938 | 11377 | |
3899152c | 11378 | if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) || |
ca0bde28 | 11379 | !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)) |
b428018a | 11380 | return 1; |
ca0bde28 JM |
11381 | |
11382 | if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) && | |
11383 | vmcs12->vmcs_link_pointer != -1ull) { | |
11384 | *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR; | |
b428018a | 11385 | return 1; |
7c177938 NHE |
11386 | } |
11387 | ||
384bb783 | 11388 | /* |
cb0c8cda | 11389 | * If the load IA32_EFER VM-entry control is 1, the following checks |
384bb783 JK |
11390 | * are performed on the field for the IA32_EFER MSR: |
11391 | * - Bits reserved in the IA32_EFER MSR must be 0. | |
11392 | * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of | |
11393 | * the IA-32e mode guest VM-exit control. It must also be identical | |
11394 | * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to | |
11395 | * CR0.PG) is 1. | |
11396 | */ | |
ca0bde28 JM |
11397 | if (to_vmx(vcpu)->nested.nested_run_pending && |
11398 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) { | |
384bb783 JK |
11399 | ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; |
11400 | if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) || | |
11401 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) || | |
11402 | ((vmcs12->guest_cr0 & X86_CR0_PG) && | |
ca0bde28 | 11403 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) |
b428018a | 11404 | return 1; |
384bb783 JK |
11405 | } |
11406 | ||
11407 | /* | |
11408 | * If the load IA32_EFER VM-exit control is 1, bits reserved in the | |
11409 | * IA32_EFER MSR must be 0 in the field for that register. In addition, | |
11410 | * the values of the LMA and LME bits in the field must each be that of | |
11411 | * the host address-space size VM-exit control. | |
11412 | */ | |
11413 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { | |
11414 | ia32e = (vmcs12->vm_exit_controls & | |
11415 | VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0; | |
11416 | if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) || | |
11417 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) || | |
ca0bde28 | 11418 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) |
b428018a | 11419 | return 1; |
ca0bde28 JM |
11420 | } |
11421 | ||
f1b026a3 WL |
11422 | if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) && |
11423 | (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) || | |
11424 | (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD))) | |
11425 | return 1; | |
11426 | ||
ca0bde28 JM |
11427 | return 0; |
11428 | } | |
11429 | ||
858e25c0 JM |
11430 | static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry) |
11431 | { | |
11432 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
11433 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
858e25c0 | 11434 | u32 exit_qual; |
e79f245d | 11435 | int r; |
858e25c0 | 11436 | |
858e25c0 JM |
11437 | enter_guest_mode(vcpu); |
11438 | ||
11439 | if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) | |
11440 | vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
11441 | ||
de3a0021 | 11442 | vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02); |
858e25c0 JM |
11443 | vmx_segment_cache_clear(vmx); |
11444 | ||
e79f245d KA |
11445 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
11446 | vcpu->arch.tsc_offset += vmcs12->tsc_offset; | |
11447 | ||
11448 | r = EXIT_REASON_INVALID_STATE; | |
11449 | if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) | |
11450 | goto fail; | |
858e25c0 JM |
11451 | |
11452 | nested_get_vmcs12_pages(vcpu, vmcs12); | |
11453 | ||
e79f245d | 11454 | r = EXIT_REASON_MSR_LOAD_FAIL; |
0b88abdc JM |
11455 | exit_qual = nested_vmx_load_msr(vcpu, |
11456 | vmcs12->vm_entry_msr_load_addr, | |
11457 | vmcs12->vm_entry_msr_load_count); | |
11458 | if (exit_qual) | |
e79f245d | 11459 | goto fail; |
858e25c0 | 11460 | |
858e25c0 JM |
11461 | /* |
11462 | * Note no nested_vmx_succeed or nested_vmx_fail here. At this point | |
11463 | * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet | |
11464 | * returned as far as L1 is concerned. It will only return (and set | |
11465 | * the success flag) when L2 exits (see nested_vmx_vmexit()). | |
11466 | */ | |
11467 | return 0; | |
e79f245d KA |
11468 | |
11469 | fail: | |
11470 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) | |
11471 | vcpu->arch.tsc_offset -= vmcs12->tsc_offset; | |
11472 | leave_guest_mode(vcpu); | |
11473 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); | |
11474 | nested_vmx_entry_failure(vcpu, vmcs12, r, exit_qual); | |
11475 | return 1; | |
858e25c0 JM |
11476 | } |
11477 | ||
ca0bde28 JM |
11478 | /* |
11479 | * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 | |
11480 | * for running an L2 nested guest. | |
11481 | */ | |
11482 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) | |
11483 | { | |
11484 | struct vmcs12 *vmcs12; | |
11485 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
b3f1dfb6 | 11486 | u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu); |
ca0bde28 JM |
11487 | u32 exit_qual; |
11488 | int ret; | |
11489 | ||
11490 | if (!nested_vmx_check_permission(vcpu)) | |
11491 | return 1; | |
11492 | ||
11493 | if (!nested_vmx_check_vmcs12(vcpu)) | |
11494 | goto out; | |
11495 | ||
11496 | vmcs12 = get_vmcs12(vcpu); | |
11497 | ||
11498 | if (enable_shadow_vmcs) | |
11499 | copy_shadow_to_vmcs12(vmx); | |
11500 | ||
11501 | /* | |
11502 | * The nested entry process starts with enforcing various prerequisites | |
11503 | * on vmcs12 as required by the Intel SDM, and act appropriately when | |
11504 | * they fail: As the SDM explains, some conditions should cause the | |
11505 | * instruction to fail, while others will cause the instruction to seem | |
11506 | * to succeed, but return an EXIT_REASON_INVALID_STATE. | |
11507 | * To speed up the normal (success) code path, we should avoid checking | |
11508 | * for misconfigurations which will anyway be caught by the processor | |
11509 | * when using the merged vmcs02. | |
11510 | */ | |
b3f1dfb6 JM |
11511 | if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) { |
11512 | nested_vmx_failValid(vcpu, | |
11513 | VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS); | |
11514 | goto out; | |
11515 | } | |
11516 | ||
ca0bde28 JM |
11517 | if (vmcs12->launch_state == launch) { |
11518 | nested_vmx_failValid(vcpu, | |
11519 | launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS | |
11520 | : VMXERR_VMRESUME_NONLAUNCHED_VMCS); | |
11521 | goto out; | |
11522 | } | |
11523 | ||
11524 | ret = check_vmentry_prereqs(vcpu, vmcs12); | |
11525 | if (ret) { | |
11526 | nested_vmx_failValid(vcpu, ret); | |
11527 | goto out; | |
11528 | } | |
11529 | ||
11530 | /* | |
11531 | * After this point, the trap flag no longer triggers a singlestep trap | |
11532 | * on the vm entry instructions; don't call kvm_skip_emulated_instruction. | |
11533 | * This is not 100% correct; for performance reasons, we delegate most | |
11534 | * of the checks on host state to the processor. If those fail, | |
11535 | * the singlestep trap is missed. | |
11536 | */ | |
11537 | skip_emulated_instruction(vcpu); | |
11538 | ||
11539 | ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual); | |
11540 | if (ret) { | |
11541 | nested_vmx_entry_failure(vcpu, vmcs12, | |
11542 | EXIT_REASON_INVALID_STATE, exit_qual); | |
11543 | return 1; | |
384bb783 JK |
11544 | } |
11545 | ||
7c177938 NHE |
11546 | /* |
11547 | * We're finally done with prerequisite checking, and can start with | |
11548 | * the nested entry. | |
11549 | */ | |
11550 | ||
858e25c0 JM |
11551 | ret = enter_vmx_non_root_mode(vcpu, true); |
11552 | if (ret) | |
11553 | return ret; | |
ff651cb6 | 11554 | |
135a06c3 CG |
11555 | /* |
11556 | * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken | |
11557 | * by event injection, halt vcpu. | |
11558 | */ | |
11559 | if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) && | |
11560 | !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK)) | |
5cb56059 | 11561 | return kvm_vcpu_halt(vcpu); |
6dfacadd | 11562 | |
7af40ad3 JK |
11563 | vmx->nested.nested_run_pending = 1; |
11564 | ||
cd232ad0 | 11565 | return 1; |
eb277562 KH |
11566 | |
11567 | out: | |
6affcbed | 11568 | return kvm_skip_emulated_instruction(vcpu); |
cd232ad0 NHE |
11569 | } |
11570 | ||
4704d0be NHE |
11571 | /* |
11572 | * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date | |
11573 | * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK). | |
11574 | * This function returns the new value we should put in vmcs12.guest_cr0. | |
11575 | * It's not enough to just return the vmcs02 GUEST_CR0. Rather, | |
11576 | * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now | |
11577 | * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 | |
11578 | * didn't trap the bit, because if L1 did, so would L0). | |
11579 | * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have | |
11580 | * been modified by L2, and L1 knows it. So just leave the old value of | |
11581 | * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 | |
11582 | * isn't relevant, because if L0 traps this bit it can set it to anything. | |
11583 | * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have | |
11584 | * changed these bits, and therefore they need to be updated, but L0 | |
11585 | * didn't necessarily allow them to be changed in GUEST_CR0 - and rather | |
11586 | * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. | |
11587 | */ | |
11588 | static inline unsigned long | |
11589 | vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
11590 | { | |
11591 | return | |
11592 | /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | | |
11593 | /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | | |
11594 | /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | | |
11595 | vcpu->arch.cr0_guest_owned_bits)); | |
11596 | } | |
11597 | ||
11598 | static inline unsigned long | |
11599 | vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
11600 | { | |
11601 | return | |
11602 | /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | | |
11603 | /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | | |
11604 | /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | | |
11605 | vcpu->arch.cr4_guest_owned_bits)); | |
11606 | } | |
11607 | ||
5f3d5799 JK |
11608 | static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, |
11609 | struct vmcs12 *vmcs12) | |
11610 | { | |
11611 | u32 idt_vectoring; | |
11612 | unsigned int nr; | |
11613 | ||
664f8e26 | 11614 | if (vcpu->arch.exception.injected) { |
5f3d5799 JK |
11615 | nr = vcpu->arch.exception.nr; |
11616 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
11617 | ||
11618 | if (kvm_exception_is_soft(nr)) { | |
11619 | vmcs12->vm_exit_instruction_len = | |
11620 | vcpu->arch.event_exit_inst_len; | |
11621 | idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; | |
11622 | } else | |
11623 | idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; | |
11624 | ||
11625 | if (vcpu->arch.exception.has_error_code) { | |
11626 | idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; | |
11627 | vmcs12->idt_vectoring_error_code = | |
11628 | vcpu->arch.exception.error_code; | |
11629 | } | |
11630 | ||
11631 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
cd2633c5 | 11632 | } else if (vcpu->arch.nmi_injected) { |
5f3d5799 JK |
11633 | vmcs12->idt_vectoring_info_field = |
11634 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; | |
04140b41 | 11635 | } else if (vcpu->arch.interrupt.injected) { |
5f3d5799 JK |
11636 | nr = vcpu->arch.interrupt.nr; |
11637 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
11638 | ||
11639 | if (vcpu->arch.interrupt.soft) { | |
11640 | idt_vectoring |= INTR_TYPE_SOFT_INTR; | |
11641 | vmcs12->vm_entry_instruction_len = | |
11642 | vcpu->arch.event_exit_inst_len; | |
11643 | } else | |
11644 | idt_vectoring |= INTR_TYPE_EXT_INTR; | |
11645 | ||
11646 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
11647 | } | |
11648 | } | |
11649 | ||
b6b8a145 JK |
11650 | static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) |
11651 | { | |
11652 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
bfcf83b1 | 11653 | unsigned long exit_qual; |
917dc606 LA |
11654 | bool block_nested_events = |
11655 | vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu); | |
acc9ab60 | 11656 | |
bfcf83b1 WL |
11657 | if (vcpu->arch.exception.pending && |
11658 | nested_vmx_check_exception(vcpu, &exit_qual)) { | |
917dc606 | 11659 | if (block_nested_events) |
bfcf83b1 WL |
11660 | return -EBUSY; |
11661 | nested_vmx_inject_exception_vmexit(vcpu, exit_qual); | |
bfcf83b1 WL |
11662 | return 0; |
11663 | } | |
11664 | ||
f4124500 JK |
11665 | if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && |
11666 | vmx->nested.preemption_timer_expired) { | |
917dc606 | 11667 | if (block_nested_events) |
f4124500 JK |
11668 | return -EBUSY; |
11669 | nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); | |
11670 | return 0; | |
11671 | } | |
11672 | ||
b6b8a145 | 11673 | if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) { |
917dc606 | 11674 | if (block_nested_events) |
b6b8a145 JK |
11675 | return -EBUSY; |
11676 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
11677 | NMI_VECTOR | INTR_TYPE_NMI_INTR | | |
11678 | INTR_INFO_VALID_MASK, 0); | |
11679 | /* | |
11680 | * The NMI-triggered VM exit counts as injection: | |
11681 | * clear this one and block further NMIs. | |
11682 | */ | |
11683 | vcpu->arch.nmi_pending = 0; | |
11684 | vmx_set_nmi_mask(vcpu, true); | |
11685 | return 0; | |
11686 | } | |
11687 | ||
11688 | if ((kvm_cpu_has_interrupt(vcpu) || external_intr) && | |
11689 | nested_exit_on_intr(vcpu)) { | |
917dc606 | 11690 | if (block_nested_events) |
b6b8a145 JK |
11691 | return -EBUSY; |
11692 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); | |
705699a1 | 11693 | return 0; |
b6b8a145 JK |
11694 | } |
11695 | ||
6342c50a DH |
11696 | vmx_complete_nested_posted_interrupt(vcpu); |
11697 | return 0; | |
b6b8a145 JK |
11698 | } |
11699 | ||
f4124500 JK |
11700 | static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) |
11701 | { | |
11702 | ktime_t remaining = | |
11703 | hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); | |
11704 | u64 value; | |
11705 | ||
11706 | if (ktime_to_ns(remaining) <= 0) | |
11707 | return 0; | |
11708 | ||
11709 | value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; | |
11710 | do_div(value, 1000000); | |
11711 | return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
11712 | } | |
11713 | ||
4704d0be | 11714 | /* |
cf8b84f4 JM |
11715 | * Update the guest state fields of vmcs12 to reflect changes that |
11716 | * occurred while L2 was running. (The "IA-32e mode guest" bit of the | |
11717 | * VM-entry controls is also updated, since this is really a guest | |
11718 | * state bit.) | |
4704d0be | 11719 | */ |
cf8b84f4 | 11720 | static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) |
4704d0be | 11721 | { |
4704d0be NHE |
11722 | vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); |
11723 | vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); | |
11724 | ||
4704d0be NHE |
11725 | vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); |
11726 | vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP); | |
11727 | vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); | |
11728 | ||
11729 | vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); | |
11730 | vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); | |
11731 | vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); | |
11732 | vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); | |
11733 | vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); | |
11734 | vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); | |
11735 | vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); | |
11736 | vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); | |
11737 | vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); | |
11738 | vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); | |
11739 | vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
11740 | vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); | |
11741 | vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); | |
11742 | vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); | |
11743 | vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); | |
11744 | vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); | |
11745 | vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
11746 | vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
11747 | vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); | |
11748 | vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); | |
11749 | vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); | |
11750 | vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); | |
11751 | vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); | |
11752 | vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); | |
11753 | vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); | |
11754 | vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); | |
11755 | vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); | |
11756 | vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); | |
11757 | vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); | |
11758 | vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); | |
11759 | vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); | |
11760 | vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); | |
11761 | vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); | |
11762 | vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); | |
11763 | vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); | |
11764 | vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); | |
11765 | ||
4704d0be NHE |
11766 | vmcs12->guest_interruptibility_info = |
11767 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
11768 | vmcs12->guest_pending_dbg_exceptions = | |
11769 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); | |
3edf1e69 JK |
11770 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
11771 | vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; | |
11772 | else | |
11773 | vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; | |
4704d0be | 11774 | |
f4124500 JK |
11775 | if (nested_cpu_has_preemption_timer(vmcs12)) { |
11776 | if (vmcs12->vm_exit_controls & | |
11777 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER) | |
11778 | vmcs12->vmx_preemption_timer_value = | |
11779 | vmx_get_preemption_timer_value(vcpu); | |
11780 | hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); | |
11781 | } | |
7854cbca | 11782 | |
3633cfc3 NHE |
11783 | /* |
11784 | * In some cases (usually, nested EPT), L2 is allowed to change its | |
11785 | * own CR3 without exiting. If it has changed it, we must keep it. | |
11786 | * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined | |
11787 | * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. | |
11788 | * | |
11789 | * Additionally, restore L2's PDPTR to vmcs12. | |
11790 | */ | |
11791 | if (enable_ept) { | |
f3531054 | 11792 | vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3); |
3633cfc3 NHE |
11793 | vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); |
11794 | vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); | |
11795 | vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); | |
11796 | vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); | |
11797 | } | |
11798 | ||
d281e13b | 11799 | vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS); |
119a9c01 | 11800 | |
608406e2 WV |
11801 | if (nested_cpu_has_vid(vmcs12)) |
11802 | vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS); | |
11803 | ||
c18911a2 JK |
11804 | vmcs12->vm_entry_controls = |
11805 | (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | | |
2961e876 | 11806 | (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); |
c18911a2 | 11807 | |
2996fca0 JK |
11808 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) { |
11809 | kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); | |
11810 | vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
11811 | } | |
11812 | ||
4704d0be NHE |
11813 | /* TODO: These cannot have changed unless we have MSR bitmaps and |
11814 | * the relevant bit asks not to trap the change */ | |
b8c07d55 | 11815 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) |
4704d0be | 11816 | vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT); |
10ba54a5 JK |
11817 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) |
11818 | vmcs12->guest_ia32_efer = vcpu->arch.efer; | |
4704d0be NHE |
11819 | vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS); |
11820 | vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP); | |
11821 | vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP); | |
a87036ad | 11822 | if (kvm_mpx_supported()) |
36be0b9d | 11823 | vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); |
cf8b84f4 JM |
11824 | } |
11825 | ||
11826 | /* | |
11827 | * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits | |
11828 | * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), | |
11829 | * and this function updates it to reflect the changes to the guest state while | |
11830 | * L2 was running (and perhaps made some exits which were handled directly by L0 | |
11831 | * without going back to L1), and to reflect the exit reason. | |
11832 | * Note that we do not have to copy here all VMCS fields, just those that | |
11833 | * could have changed by the L2 guest or the exit - i.e., the guest-state and | |
11834 | * exit-information fields only. Other fields are modified by L1 with VMWRITE, | |
11835 | * which already writes to vmcs12 directly. | |
11836 | */ | |
11837 | static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
11838 | u32 exit_reason, u32 exit_intr_info, | |
11839 | unsigned long exit_qualification) | |
11840 | { | |
11841 | /* update guest state fields: */ | |
11842 | sync_vmcs12(vcpu, vmcs12); | |
4704d0be NHE |
11843 | |
11844 | /* update exit information fields: */ | |
11845 | ||
533558bc JK |
11846 | vmcs12->vm_exit_reason = exit_reason; |
11847 | vmcs12->exit_qualification = exit_qualification; | |
533558bc | 11848 | vmcs12->vm_exit_intr_info = exit_intr_info; |
7313c698 | 11849 | |
5f3d5799 | 11850 | vmcs12->idt_vectoring_info_field = 0; |
4704d0be NHE |
11851 | vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
11852 | vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
11853 | ||
5f3d5799 | 11854 | if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { |
7cdc2d62 JM |
11855 | vmcs12->launch_state = 1; |
11856 | ||
5f3d5799 JK |
11857 | /* vm_entry_intr_info_field is cleared on exit. Emulate this |
11858 | * instead of reading the real value. */ | |
4704d0be | 11859 | vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; |
5f3d5799 JK |
11860 | |
11861 | /* | |
11862 | * Transfer the event that L0 or L1 may wanted to inject into | |
11863 | * L2 to IDT_VECTORING_INFO_FIELD. | |
11864 | */ | |
11865 | vmcs12_save_pending_event(vcpu, vmcs12); | |
11866 | } | |
11867 | ||
11868 | /* | |
11869 | * Drop what we picked up for L2 via vmx_complete_interrupts. It is | |
11870 | * preserved above and would only end up incorrectly in L1. | |
11871 | */ | |
11872 | vcpu->arch.nmi_injected = false; | |
11873 | kvm_clear_exception_queue(vcpu); | |
11874 | kvm_clear_interrupt_queue(vcpu); | |
4704d0be NHE |
11875 | } |
11876 | ||
5af41573 WL |
11877 | static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu, |
11878 | struct vmcs12 *vmcs12) | |
11879 | { | |
11880 | u32 entry_failure_code; | |
11881 | ||
11882 | nested_ept_uninit_mmu_context(vcpu); | |
11883 | ||
11884 | /* | |
11885 | * Only PDPTE load can fail as the value of cr3 was checked on entry and | |
11886 | * couldn't have changed. | |
11887 | */ | |
11888 | if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code)) | |
11889 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL); | |
11890 | ||
11891 | if (!enable_ept) | |
11892 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
11893 | } | |
11894 | ||
4704d0be NHE |
11895 | /* |
11896 | * A part of what we need to when the nested L2 guest exits and we want to | |
11897 | * run its L1 parent, is to reset L1's guest state to the host state specified | |
11898 | * in vmcs12. | |
11899 | * This function is to be called not only on normal nested exit, but also on | |
11900 | * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry | |
11901 | * Failures During or After Loading Guest State"). | |
11902 | * This function should be called when the active VMCS is L1's (vmcs01). | |
11903 | */ | |
733568f9 JK |
11904 | static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, |
11905 | struct vmcs12 *vmcs12) | |
4704d0be | 11906 | { |
21feb4eb ACL |
11907 | struct kvm_segment seg; |
11908 | ||
4704d0be NHE |
11909 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) |
11910 | vcpu->arch.efer = vmcs12->host_ia32_efer; | |
d1fa0352 | 11911 | else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) |
4704d0be NHE |
11912 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
11913 | else | |
11914 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
11915 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
11916 | ||
11917 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp); | |
11918 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip); | |
1adfa76a | 11919 | vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); |
4704d0be NHE |
11920 | /* |
11921 | * Note that calling vmx_set_cr0 is important, even if cr0 hasn't | |
bd7e5b08 PB |
11922 | * actually changed, because vmx_set_cr0 refers to efer set above. |
11923 | * | |
11924 | * CR0_GUEST_HOST_MASK is already set in the original vmcs01 | |
11925 | * (KVM doesn't change it); | |
4704d0be | 11926 | */ |
bd7e5b08 | 11927 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
9e3e4dbf | 11928 | vmx_set_cr0(vcpu, vmcs12->host_cr0); |
4704d0be | 11929 | |
bd7e5b08 | 11930 | /* Same as above - no reason to call set_cr4_guest_host_mask(). */ |
4704d0be | 11931 | vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); |
8eb3f87d | 11932 | vmx_set_cr4(vcpu, vmcs12->host_cr4); |
4704d0be | 11933 | |
5af41573 | 11934 | load_vmcs12_mmu_host_state(vcpu, vmcs12); |
feaf0c7d | 11935 | |
4704d0be NHE |
11936 | if (enable_vpid) { |
11937 | /* | |
11938 | * Trivially support vpid by letting L2s share their parent | |
11939 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
11940 | * each L2 its own vpid and exposing the vpid feature to L1. | |
11941 | */ | |
c2ba05cc | 11942 | vmx_flush_tlb(vcpu, true); |
4704d0be | 11943 | } |
4704d0be NHE |
11944 | |
11945 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); | |
11946 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); | |
11947 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); | |
11948 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); | |
11949 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); | |
21f2d551 LP |
11950 | vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF); |
11951 | vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF); | |
4704d0be | 11952 | |
36be0b9d PB |
11953 | /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ |
11954 | if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) | |
11955 | vmcs_write64(GUEST_BNDCFGS, 0); | |
11956 | ||
44811c02 | 11957 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { |
4704d0be | 11958 | vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); |
44811c02 JK |
11959 | vcpu->arch.pat = vmcs12->host_ia32_pat; |
11960 | } | |
4704d0be NHE |
11961 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
11962 | vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, | |
11963 | vmcs12->host_ia32_perf_global_ctrl); | |
503cd0c5 | 11964 | |
21feb4eb ACL |
11965 | /* Set L1 segment info according to Intel SDM |
11966 | 27.5.2 Loading Host Segment and Descriptor-Table Registers */ | |
11967 | seg = (struct kvm_segment) { | |
11968 | .base = 0, | |
11969 | .limit = 0xFFFFFFFF, | |
11970 | .selector = vmcs12->host_cs_selector, | |
11971 | .type = 11, | |
11972 | .present = 1, | |
11973 | .s = 1, | |
11974 | .g = 1 | |
11975 | }; | |
11976 | if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) | |
11977 | seg.l = 1; | |
11978 | else | |
11979 | seg.db = 1; | |
11980 | vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); | |
11981 | seg = (struct kvm_segment) { | |
11982 | .base = 0, | |
11983 | .limit = 0xFFFFFFFF, | |
11984 | .type = 3, | |
11985 | .present = 1, | |
11986 | .s = 1, | |
11987 | .db = 1, | |
11988 | .g = 1 | |
11989 | }; | |
11990 | seg.selector = vmcs12->host_ds_selector; | |
11991 | vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); | |
11992 | seg.selector = vmcs12->host_es_selector; | |
11993 | vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); | |
11994 | seg.selector = vmcs12->host_ss_selector; | |
11995 | vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); | |
11996 | seg.selector = vmcs12->host_fs_selector; | |
11997 | seg.base = vmcs12->host_fs_base; | |
11998 | vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); | |
11999 | seg.selector = vmcs12->host_gs_selector; | |
12000 | seg.base = vmcs12->host_gs_base; | |
12001 | vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); | |
12002 | seg = (struct kvm_segment) { | |
205befd9 | 12003 | .base = vmcs12->host_tr_base, |
21feb4eb ACL |
12004 | .limit = 0x67, |
12005 | .selector = vmcs12->host_tr_selector, | |
12006 | .type = 11, | |
12007 | .present = 1 | |
12008 | }; | |
12009 | vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); | |
12010 | ||
503cd0c5 JK |
12011 | kvm_set_dr(vcpu, 7, 0x400); |
12012 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
ff651cb6 | 12013 | |
3af18d9c | 12014 | if (cpu_has_vmx_msr_bitmap()) |
904e14fb | 12015 | vmx_update_msr_bitmap(vcpu); |
3af18d9c | 12016 | |
ff651cb6 WV |
12017 | if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr, |
12018 | vmcs12->vm_exit_msr_load_count)) | |
12019 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); | |
4704d0be NHE |
12020 | } |
12021 | ||
12022 | /* | |
12023 | * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 | |
12024 | * and modify vmcs12 to make it see what it would expect to see there if | |
12025 | * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) | |
12026 | */ | |
533558bc JK |
12027 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
12028 | u32 exit_intr_info, | |
12029 | unsigned long exit_qualification) | |
4704d0be NHE |
12030 | { |
12031 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4704d0be NHE |
12032 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
12033 | ||
5f3d5799 JK |
12034 | /* trying to cancel vmlaunch/vmresume is a bug */ |
12035 | WARN_ON_ONCE(vmx->nested.nested_run_pending); | |
12036 | ||
4f350c6d JM |
12037 | /* |
12038 | * The only expected VM-instruction error is "VM entry with | |
12039 | * invalid control field(s)." Anything else indicates a | |
12040 | * problem with L0. | |
12041 | */ | |
12042 | WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) != | |
12043 | VMXERR_ENTRY_INVALID_CONTROL_FIELD)); | |
12044 | ||
4704d0be | 12045 | leave_guest_mode(vcpu); |
4704d0be | 12046 | |
e79f245d KA |
12047 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
12048 | vcpu->arch.tsc_offset -= vmcs12->tsc_offset; | |
12049 | ||
4f350c6d | 12050 | if (likely(!vmx->fail)) { |
72e9cbdb LP |
12051 | if (exit_reason == -1) |
12052 | sync_vmcs12(vcpu, vmcs12); | |
12053 | else | |
12054 | prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info, | |
12055 | exit_qualification); | |
ff651cb6 | 12056 | |
4f350c6d JM |
12057 | if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr, |
12058 | vmcs12->vm_exit_msr_store_count)) | |
12059 | nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL); | |
12060 | } | |
cf3215d9 | 12061 | |
1279a6b1 | 12062 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
8391ce44 PB |
12063 | vm_entry_controls_reset_shadow(vmx); |
12064 | vm_exit_controls_reset_shadow(vmx); | |
36c3cc42 JK |
12065 | vmx_segment_cache_clear(vmx); |
12066 | ||
9314006d | 12067 | /* Update any VMCS fields that might have changed while L2 ran */ |
83bafef1 JM |
12068 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr); |
12069 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
ea26e4ec | 12070 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
9314006d PB |
12071 | if (vmx->hv_deadline_tsc == -1) |
12072 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
12073 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
12074 | else | |
12075 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
12076 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c95ba92a PF |
12077 | if (kvm_has_tsc_control) |
12078 | decache_tsc_multiplier(vmx); | |
4704d0be | 12079 | |
dccbfcf5 RK |
12080 | if (vmx->nested.change_vmcs01_virtual_x2apic_mode) { |
12081 | vmx->nested.change_vmcs01_virtual_x2apic_mode = false; | |
12082 | vmx_set_virtual_x2apic_mode(vcpu, | |
12083 | vcpu->arch.apic_base & X2APIC_ENABLE); | |
fb6c8198 JM |
12084 | } else if (!nested_cpu_has_ept(vmcs12) && |
12085 | nested_cpu_has2(vmcs12, | |
12086 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
a468f2db | 12087 | vmx_flush_tlb(vcpu, true); |
dccbfcf5 | 12088 | } |
4704d0be NHE |
12089 | |
12090 | /* This is needed for same reason as it was needed in prepare_vmcs02 */ | |
12091 | vmx->host_rsp = 0; | |
12092 | ||
12093 | /* Unpin physical memory we referred to in vmcs02 */ | |
12094 | if (vmx->nested.apic_access_page) { | |
53a70daf | 12095 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
48d89b92 | 12096 | vmx->nested.apic_access_page = NULL; |
4704d0be | 12097 | } |
a7c0b07d | 12098 | if (vmx->nested.virtual_apic_page) { |
53a70daf | 12099 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
48d89b92 | 12100 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 12101 | } |
705699a1 WV |
12102 | if (vmx->nested.pi_desc_page) { |
12103 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 12104 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
705699a1 WV |
12105 | vmx->nested.pi_desc_page = NULL; |
12106 | vmx->nested.pi_desc = NULL; | |
12107 | } | |
4704d0be | 12108 | |
38b99173 TC |
12109 | /* |
12110 | * We are now running in L2, mmu_notifier will force to reload the | |
12111 | * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1. | |
12112 | */ | |
c83b6d15 | 12113 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
38b99173 | 12114 | |
72e9cbdb | 12115 | if (enable_shadow_vmcs && exit_reason != -1) |
012f83cb | 12116 | vmx->nested.sync_shadow_vmcs = true; |
b6b8a145 JK |
12117 | |
12118 | /* in case we halted in L2 */ | |
12119 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4f350c6d JM |
12120 | |
12121 | if (likely(!vmx->fail)) { | |
12122 | /* | |
12123 | * TODO: SDM says that with acknowledge interrupt on | |
12124 | * exit, bit 31 of the VM-exit interrupt information | |
12125 | * (valid interrupt) is always set to 1 on | |
12126 | * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't | |
12127 | * need kvm_cpu_has_interrupt(). See the commit | |
12128 | * message for details. | |
12129 | */ | |
12130 | if (nested_exit_intr_ack_set(vcpu) && | |
12131 | exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT && | |
12132 | kvm_cpu_has_interrupt(vcpu)) { | |
12133 | int irq = kvm_cpu_get_interrupt(vcpu); | |
12134 | WARN_ON(irq < 0); | |
12135 | vmcs12->vm_exit_intr_info = irq | | |
12136 | INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; | |
12137 | } | |
12138 | ||
72e9cbdb LP |
12139 | if (exit_reason != -1) |
12140 | trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, | |
12141 | vmcs12->exit_qualification, | |
12142 | vmcs12->idt_vectoring_info_field, | |
12143 | vmcs12->vm_exit_intr_info, | |
12144 | vmcs12->vm_exit_intr_error_code, | |
12145 | KVM_ISA_VMX); | |
4f350c6d JM |
12146 | |
12147 | load_vmcs12_host_state(vcpu, vmcs12); | |
12148 | ||
12149 | return; | |
12150 | } | |
12151 | ||
12152 | /* | |
12153 | * After an early L2 VM-entry failure, we're now back | |
12154 | * in L1 which thinks it just finished a VMLAUNCH or | |
12155 | * VMRESUME instruction, so we need to set the failure | |
12156 | * flag and the VM-instruction error field of the VMCS | |
12157 | * accordingly. | |
12158 | */ | |
12159 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
5af41573 WL |
12160 | |
12161 | load_vmcs12_mmu_host_state(vcpu, vmcs12); | |
12162 | ||
4f350c6d JM |
12163 | /* |
12164 | * The emulated instruction was already skipped in | |
12165 | * nested_vmx_run, but the updated RIP was never | |
12166 | * written back to the vmcs01. | |
12167 | */ | |
12168 | skip_emulated_instruction(vcpu); | |
12169 | vmx->fail = 0; | |
4704d0be NHE |
12170 | } |
12171 | ||
42124925 JK |
12172 | /* |
12173 | * Forcibly leave nested mode in order to be able to reset the VCPU later on. | |
12174 | */ | |
12175 | static void vmx_leave_nested(struct kvm_vcpu *vcpu) | |
12176 | { | |
2f707d97 WL |
12177 | if (is_guest_mode(vcpu)) { |
12178 | to_vmx(vcpu)->nested.nested_run_pending = 0; | |
533558bc | 12179 | nested_vmx_vmexit(vcpu, -1, 0, 0); |
2f707d97 | 12180 | } |
42124925 JK |
12181 | free_nested(to_vmx(vcpu)); |
12182 | } | |
12183 | ||
7c177938 NHE |
12184 | /* |
12185 | * L1's failure to enter L2 is a subset of a normal exit, as explained in | |
12186 | * 23.7 "VM-entry failures during or after loading guest state" (this also | |
12187 | * lists the acceptable exit-reason and exit-qualification parameters). | |
12188 | * It should only be called before L2 actually succeeded to run, and when | |
12189 | * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss). | |
12190 | */ | |
12191 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, | |
12192 | struct vmcs12 *vmcs12, | |
12193 | u32 reason, unsigned long qualification) | |
12194 | { | |
12195 | load_vmcs12_host_state(vcpu, vmcs12); | |
12196 | vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY; | |
12197 | vmcs12->exit_qualification = qualification; | |
12198 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
12199 | if (enable_shadow_vmcs) |
12200 | to_vmx(vcpu)->nested.sync_shadow_vmcs = true; | |
7c177938 NHE |
12201 | } |
12202 | ||
8a76d7f2 JR |
12203 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
12204 | struct x86_instruction_info *info, | |
12205 | enum x86_intercept_stage stage) | |
12206 | { | |
fb6d4d34 PB |
12207 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
12208 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
12209 | ||
12210 | /* | |
12211 | * RDPID causes #UD if disabled through secondary execution controls. | |
12212 | * Because it is marked as EmulateOnUD, we need to intercept it here. | |
12213 | */ | |
12214 | if (info->intercept == x86_intercept_rdtscp && | |
12215 | !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { | |
12216 | ctxt->exception.vector = UD_VECTOR; | |
12217 | ctxt->exception.error_code_valid = false; | |
12218 | return X86EMUL_PROPAGATE_FAULT; | |
12219 | } | |
12220 | ||
12221 | /* TODO: check more intercepts... */ | |
8a76d7f2 JR |
12222 | return X86EMUL_CONTINUE; |
12223 | } | |
12224 | ||
64672c95 YJ |
12225 | #ifdef CONFIG_X86_64 |
12226 | /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ | |
12227 | static inline int u64_shl_div_u64(u64 a, unsigned int shift, | |
12228 | u64 divisor, u64 *result) | |
12229 | { | |
12230 | u64 low = a << shift, high = a >> (64 - shift); | |
12231 | ||
12232 | /* To avoid the overflow on divq */ | |
12233 | if (high >= divisor) | |
12234 | return 1; | |
12235 | ||
12236 | /* Low hold the result, high hold rem which is discarded */ | |
12237 | asm("divq %2\n\t" : "=a" (low), "=d" (high) : | |
12238 | "rm" (divisor), "0" (low), "1" (high)); | |
12239 | *result = low; | |
12240 | ||
12241 | return 0; | |
12242 | } | |
12243 | ||
12244 | static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc) | |
12245 | { | |
386c6ddb KA |
12246 | struct vcpu_vmx *vmx; |
12247 | u64 tscl, guest_tscl, delta_tsc; | |
12248 | ||
12249 | if (kvm_mwait_in_guest(vcpu->kvm)) | |
12250 | return -EOPNOTSUPP; | |
12251 | ||
12252 | vmx = to_vmx(vcpu); | |
12253 | tscl = rdtsc(); | |
12254 | guest_tscl = kvm_read_l1_tsc(vcpu, tscl); | |
12255 | delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; | |
64672c95 YJ |
12256 | |
12257 | /* Convert to host delta tsc if tsc scaling is enabled */ | |
12258 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && | |
12259 | u64_shl_div_u64(delta_tsc, | |
12260 | kvm_tsc_scaling_ratio_frac_bits, | |
12261 | vcpu->arch.tsc_scaling_ratio, | |
12262 | &delta_tsc)) | |
12263 | return -ERANGE; | |
12264 | ||
12265 | /* | |
12266 | * If the delta tsc can't fit in the 32 bit after the multi shift, | |
12267 | * we can't use the preemption timer. | |
12268 | * It's possible that it fits on later vmentries, but checking | |
12269 | * on every vmentry is costly so we just use an hrtimer. | |
12270 | */ | |
12271 | if (delta_tsc >> (cpu_preemption_timer_multi + 32)) | |
12272 | return -ERANGE; | |
12273 | ||
12274 | vmx->hv_deadline_tsc = tscl + delta_tsc; | |
12275 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
12276 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c8533544 WL |
12277 | |
12278 | return delta_tsc == 0; | |
64672c95 YJ |
12279 | } |
12280 | ||
12281 | static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) | |
12282 | { | |
12283 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
12284 | vmx->hv_deadline_tsc = -1; | |
12285 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
12286 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
12287 | } | |
12288 | #endif | |
12289 | ||
48d89b92 | 12290 | static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) |
ae97a3b8 | 12291 | { |
b31c114b | 12292 | if (!kvm_pause_in_guest(vcpu->kvm)) |
b4a2d31d | 12293 | shrink_ple_window(vcpu); |
ae97a3b8 RK |
12294 | } |
12295 | ||
843e4330 KH |
12296 | static void vmx_slot_enable_log_dirty(struct kvm *kvm, |
12297 | struct kvm_memory_slot *slot) | |
12298 | { | |
12299 | kvm_mmu_slot_leaf_clear_dirty(kvm, slot); | |
12300 | kvm_mmu_slot_largepage_remove_write_access(kvm, slot); | |
12301 | } | |
12302 | ||
12303 | static void vmx_slot_disable_log_dirty(struct kvm *kvm, | |
12304 | struct kvm_memory_slot *slot) | |
12305 | { | |
12306 | kvm_mmu_slot_set_dirty(kvm, slot); | |
12307 | } | |
12308 | ||
12309 | static void vmx_flush_log_dirty(struct kvm *kvm) | |
12310 | { | |
12311 | kvm_flush_pml_buffers(kvm); | |
12312 | } | |
12313 | ||
c5f983f6 BD |
12314 | static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) |
12315 | { | |
12316 | struct vmcs12 *vmcs12; | |
12317 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
12318 | gpa_t gpa; | |
12319 | struct page *page = NULL; | |
12320 | u64 *pml_address; | |
12321 | ||
12322 | if (is_guest_mode(vcpu)) { | |
12323 | WARN_ON_ONCE(vmx->nested.pml_full); | |
12324 | ||
12325 | /* | |
12326 | * Check if PML is enabled for the nested guest. | |
12327 | * Whether eptp bit 6 is set is already checked | |
12328 | * as part of A/D emulation. | |
12329 | */ | |
12330 | vmcs12 = get_vmcs12(vcpu); | |
12331 | if (!nested_cpu_has_pml(vmcs12)) | |
12332 | return 0; | |
12333 | ||
4769886b | 12334 | if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { |
c5f983f6 BD |
12335 | vmx->nested.pml_full = true; |
12336 | return 1; | |
12337 | } | |
12338 | ||
12339 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; | |
12340 | ||
5e2f30b7 DH |
12341 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address); |
12342 | if (is_error_page(page)) | |
c5f983f6 BD |
12343 | return 0; |
12344 | ||
12345 | pml_address = kmap(page); | |
12346 | pml_address[vmcs12->guest_pml_index--] = gpa; | |
12347 | kunmap(page); | |
53a70daf | 12348 | kvm_release_page_clean(page); |
c5f983f6 BD |
12349 | } |
12350 | ||
12351 | return 0; | |
12352 | } | |
12353 | ||
843e4330 KH |
12354 | static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, |
12355 | struct kvm_memory_slot *memslot, | |
12356 | gfn_t offset, unsigned long mask) | |
12357 | { | |
12358 | kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); | |
12359 | } | |
12360 | ||
cd39e117 PB |
12361 | static void __pi_post_block(struct kvm_vcpu *vcpu) |
12362 | { | |
12363 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
12364 | struct pi_desc old, new; | |
12365 | unsigned int dest; | |
cd39e117 PB |
12366 | |
12367 | do { | |
12368 | old.control = new.control = pi_desc->control; | |
8b306e2f PB |
12369 | WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, |
12370 | "Wakeup handler not enabled while the VCPU is blocked\n"); | |
cd39e117 PB |
12371 | |
12372 | dest = cpu_physical_id(vcpu->cpu); | |
12373 | ||
12374 | if (x2apic_enabled()) | |
12375 | new.ndst = dest; | |
12376 | else | |
12377 | new.ndst = (dest << 8) & 0xFF00; | |
12378 | ||
cd39e117 PB |
12379 | /* set 'NV' to 'notification vector' */ |
12380 | new.nv = POSTED_INTR_VECTOR; | |
c0a1666b PB |
12381 | } while (cmpxchg64(&pi_desc->control, old.control, |
12382 | new.control) != old.control); | |
cd39e117 | 12383 | |
8b306e2f PB |
12384 | if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { |
12385 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
cd39e117 | 12386 | list_del(&vcpu->blocked_vcpu_list); |
8b306e2f | 12387 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); |
cd39e117 PB |
12388 | vcpu->pre_pcpu = -1; |
12389 | } | |
12390 | } | |
12391 | ||
bf9f6ac8 FW |
12392 | /* |
12393 | * This routine does the following things for vCPU which is going | |
12394 | * to be blocked if VT-d PI is enabled. | |
12395 | * - Store the vCPU to the wakeup list, so when interrupts happen | |
12396 | * we can find the right vCPU to wake up. | |
12397 | * - Change the Posted-interrupt descriptor as below: | |
12398 | * 'NDST' <-- vcpu->pre_pcpu | |
12399 | * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR | |
12400 | * - If 'ON' is set during this process, which means at least one | |
12401 | * interrupt is posted for this vCPU, we cannot block it, in | |
12402 | * this case, return 1, otherwise, return 0. | |
12403 | * | |
12404 | */ | |
bc22512b | 12405 | static int pi_pre_block(struct kvm_vcpu *vcpu) |
bf9f6ac8 | 12406 | { |
bf9f6ac8 FW |
12407 | unsigned int dest; |
12408 | struct pi_desc old, new; | |
12409 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
12410 | ||
12411 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
12412 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
12413 | !kvm_vcpu_apicv_active(vcpu)) | |
bf9f6ac8 FW |
12414 | return 0; |
12415 | ||
8b306e2f PB |
12416 | WARN_ON(irqs_disabled()); |
12417 | local_irq_disable(); | |
12418 | if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { | |
12419 | vcpu->pre_pcpu = vcpu->cpu; | |
12420 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
12421 | list_add_tail(&vcpu->blocked_vcpu_list, | |
12422 | &per_cpu(blocked_vcpu_on_cpu, | |
12423 | vcpu->pre_pcpu)); | |
12424 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
12425 | } | |
bf9f6ac8 FW |
12426 | |
12427 | do { | |
12428 | old.control = new.control = pi_desc->control; | |
12429 | ||
bf9f6ac8 FW |
12430 | WARN((pi_desc->sn == 1), |
12431 | "Warning: SN field of posted-interrupts " | |
12432 | "is set before blocking\n"); | |
12433 | ||
12434 | /* | |
12435 | * Since vCPU can be preempted during this process, | |
12436 | * vcpu->cpu could be different with pre_pcpu, we | |
12437 | * need to set pre_pcpu as the destination of wakeup | |
12438 | * notification event, then we can find the right vCPU | |
12439 | * to wakeup in wakeup handler if interrupts happen | |
12440 | * when the vCPU is in blocked state. | |
12441 | */ | |
12442 | dest = cpu_physical_id(vcpu->pre_pcpu); | |
12443 | ||
12444 | if (x2apic_enabled()) | |
12445 | new.ndst = dest; | |
12446 | else | |
12447 | new.ndst = (dest << 8) & 0xFF00; | |
12448 | ||
12449 | /* set 'NV' to 'wakeup vector' */ | |
12450 | new.nv = POSTED_INTR_WAKEUP_VECTOR; | |
c0a1666b PB |
12451 | } while (cmpxchg64(&pi_desc->control, old.control, |
12452 | new.control) != old.control); | |
bf9f6ac8 | 12453 | |
8b306e2f PB |
12454 | /* We should not block the vCPU if an interrupt is posted for it. */ |
12455 | if (pi_test_on(pi_desc) == 1) | |
12456 | __pi_post_block(vcpu); | |
12457 | ||
12458 | local_irq_enable(); | |
12459 | return (vcpu->pre_pcpu == -1); | |
bf9f6ac8 FW |
12460 | } |
12461 | ||
bc22512b YJ |
12462 | static int vmx_pre_block(struct kvm_vcpu *vcpu) |
12463 | { | |
12464 | if (pi_pre_block(vcpu)) | |
12465 | return 1; | |
12466 | ||
64672c95 YJ |
12467 | if (kvm_lapic_hv_timer_in_use(vcpu)) |
12468 | kvm_lapic_switch_to_sw_timer(vcpu); | |
12469 | ||
bc22512b YJ |
12470 | return 0; |
12471 | } | |
12472 | ||
12473 | static void pi_post_block(struct kvm_vcpu *vcpu) | |
bf9f6ac8 | 12474 | { |
8b306e2f | 12475 | if (vcpu->pre_pcpu == -1) |
bf9f6ac8 FW |
12476 | return; |
12477 | ||
8b306e2f PB |
12478 | WARN_ON(irqs_disabled()); |
12479 | local_irq_disable(); | |
cd39e117 | 12480 | __pi_post_block(vcpu); |
8b306e2f | 12481 | local_irq_enable(); |
bf9f6ac8 FW |
12482 | } |
12483 | ||
bc22512b YJ |
12484 | static void vmx_post_block(struct kvm_vcpu *vcpu) |
12485 | { | |
64672c95 YJ |
12486 | if (kvm_x86_ops->set_hv_timer) |
12487 | kvm_lapic_switch_to_hv_timer(vcpu); | |
12488 | ||
bc22512b YJ |
12489 | pi_post_block(vcpu); |
12490 | } | |
12491 | ||
efc64404 FW |
12492 | /* |
12493 | * vmx_update_pi_irte - set IRTE for Posted-Interrupts | |
12494 | * | |
12495 | * @kvm: kvm | |
12496 | * @host_irq: host irq of the interrupt | |
12497 | * @guest_irq: gsi of the interrupt | |
12498 | * @set: set or unset PI | |
12499 | * returns 0 on success, < 0 on failure | |
12500 | */ | |
12501 | static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
12502 | uint32_t guest_irq, bool set) | |
12503 | { | |
12504 | struct kvm_kernel_irq_routing_entry *e; | |
12505 | struct kvm_irq_routing_table *irq_rt; | |
12506 | struct kvm_lapic_irq irq; | |
12507 | struct kvm_vcpu *vcpu; | |
12508 | struct vcpu_data vcpu_info; | |
3a8b0677 | 12509 | int idx, ret = 0; |
efc64404 FW |
12510 | |
12511 | if (!kvm_arch_has_assigned_device(kvm) || | |
a0052191 YZ |
12512 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
12513 | !kvm_vcpu_apicv_active(kvm->vcpus[0])) | |
efc64404 FW |
12514 | return 0; |
12515 | ||
12516 | idx = srcu_read_lock(&kvm->irq_srcu); | |
12517 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
3a8b0677 JS |
12518 | if (guest_irq >= irq_rt->nr_rt_entries || |
12519 | hlist_empty(&irq_rt->map[guest_irq])) { | |
12520 | pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", | |
12521 | guest_irq, irq_rt->nr_rt_entries); | |
12522 | goto out; | |
12523 | } | |
efc64404 FW |
12524 | |
12525 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
12526 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
12527 | continue; | |
12528 | /* | |
12529 | * VT-d PI cannot support posting multicast/broadcast | |
12530 | * interrupts to a vCPU, we still use interrupt remapping | |
12531 | * for these kind of interrupts. | |
12532 | * | |
12533 | * For lowest-priority interrupts, we only support | |
12534 | * those with single CPU as the destination, e.g. user | |
12535 | * configures the interrupts via /proc/irq or uses | |
12536 | * irqbalance to make the interrupts single-CPU. | |
12537 | * | |
12538 | * We will support full lowest-priority interrupt later. | |
12539 | */ | |
12540 | ||
37131313 | 12541 | kvm_set_msi_irq(kvm, e, &irq); |
23a1c257 FW |
12542 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { |
12543 | /* | |
12544 | * Make sure the IRTE is in remapped mode if | |
12545 | * we don't handle it in posted mode. | |
12546 | */ | |
12547 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
12548 | if (ret < 0) { | |
12549 | printk(KERN_INFO | |
12550 | "failed to back to remapped mode, irq: %u\n", | |
12551 | host_irq); | |
12552 | goto out; | |
12553 | } | |
12554 | ||
efc64404 | 12555 | continue; |
23a1c257 | 12556 | } |
efc64404 FW |
12557 | |
12558 | vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); | |
12559 | vcpu_info.vector = irq.vector; | |
12560 | ||
2698d82e | 12561 | trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, |
efc64404 FW |
12562 | vcpu_info.vector, vcpu_info.pi_desc_addr, set); |
12563 | ||
12564 | if (set) | |
12565 | ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); | |
dc91f2eb | 12566 | else |
efc64404 | 12567 | ret = irq_set_vcpu_affinity(host_irq, NULL); |
efc64404 FW |
12568 | |
12569 | if (ret < 0) { | |
12570 | printk(KERN_INFO "%s: failed to update PI IRTE\n", | |
12571 | __func__); | |
12572 | goto out; | |
12573 | } | |
12574 | } | |
12575 | ||
12576 | ret = 0; | |
12577 | out: | |
12578 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
12579 | return ret; | |
12580 | } | |
12581 | ||
c45dcc71 AR |
12582 | static void vmx_setup_mce(struct kvm_vcpu *vcpu) |
12583 | { | |
12584 | if (vcpu->arch.mcg_cap & MCG_LMCE_P) | |
12585 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
12586 | FEATURE_CONTROL_LMCE; | |
12587 | else | |
12588 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
12589 | ~FEATURE_CONTROL_LMCE; | |
12590 | } | |
12591 | ||
72d7b374 LP |
12592 | static int vmx_smi_allowed(struct kvm_vcpu *vcpu) |
12593 | { | |
72e9cbdb LP |
12594 | /* we need a nested vmexit to enter SMM, postpone if run is pending */ |
12595 | if (to_vmx(vcpu)->nested.nested_run_pending) | |
12596 | return 0; | |
72d7b374 LP |
12597 | return 1; |
12598 | } | |
12599 | ||
0234bf88 LP |
12600 | static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) |
12601 | { | |
72e9cbdb LP |
12602 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
12603 | ||
12604 | vmx->nested.smm.guest_mode = is_guest_mode(vcpu); | |
12605 | if (vmx->nested.smm.guest_mode) | |
12606 | nested_vmx_vmexit(vcpu, -1, 0, 0); | |
12607 | ||
12608 | vmx->nested.smm.vmxon = vmx->nested.vmxon; | |
12609 | vmx->nested.vmxon = false; | |
caa057a2 | 12610 | vmx_clear_hlt(vcpu); |
0234bf88 LP |
12611 | return 0; |
12612 | } | |
12613 | ||
12614 | static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase) | |
12615 | { | |
72e9cbdb LP |
12616 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
12617 | int ret; | |
12618 | ||
12619 | if (vmx->nested.smm.vmxon) { | |
12620 | vmx->nested.vmxon = true; | |
12621 | vmx->nested.smm.vmxon = false; | |
12622 | } | |
12623 | ||
12624 | if (vmx->nested.smm.guest_mode) { | |
12625 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
12626 | ret = enter_vmx_non_root_mode(vcpu, false); | |
12627 | vcpu->arch.hflags |= HF_SMM_MASK; | |
12628 | if (ret) | |
12629 | return ret; | |
12630 | ||
12631 | vmx->nested.smm.guest_mode = false; | |
12632 | } | |
0234bf88 LP |
12633 | return 0; |
12634 | } | |
12635 | ||
cc3d967f LP |
12636 | static int enable_smi_window(struct kvm_vcpu *vcpu) |
12637 | { | |
12638 | return 0; | |
12639 | } | |
12640 | ||
404f6aac | 12641 | static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { |
6aa8b732 AK |
12642 | .cpu_has_kvm_support = cpu_has_kvm_support, |
12643 | .disabled_by_bios = vmx_disabled_by_bios, | |
12644 | .hardware_setup = hardware_setup, | |
12645 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 12646 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
12647 | .hardware_enable = hardware_enable, |
12648 | .hardware_disable = hardware_disable, | |
04547156 | 12649 | .cpu_has_accelerated_tpr = report_flexpriority, |
bc226f07 | 12650 | .has_emulated_msr = vmx_has_emulated_msr, |
6aa8b732 | 12651 | |
b31c114b | 12652 | .vm_init = vmx_vm_init, |
434a1e94 SC |
12653 | .vm_alloc = vmx_vm_alloc, |
12654 | .vm_free = vmx_vm_free, | |
b31c114b | 12655 | |
6aa8b732 AK |
12656 | .vcpu_create = vmx_create_vcpu, |
12657 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 12658 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 12659 | |
04d2cc77 | 12660 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
12661 | .vcpu_load = vmx_vcpu_load, |
12662 | .vcpu_put = vmx_vcpu_put, | |
12663 | ||
a96036b8 | 12664 | .update_bp_intercept = update_exception_bitmap, |
801e459a | 12665 | .get_msr_feature = vmx_get_msr_feature, |
6aa8b732 AK |
12666 | .get_msr = vmx_get_msr, |
12667 | .set_msr = vmx_set_msr, | |
12668 | .get_segment_base = vmx_get_segment_base, | |
12669 | .get_segment = vmx_get_segment, | |
12670 | .set_segment = vmx_set_segment, | |
2e4d2653 | 12671 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 12672 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 12673 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 12674 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 12675 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 12676 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
12677 | .set_cr3 = vmx_set_cr3, |
12678 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 12679 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
12680 | .get_idt = vmx_get_idt, |
12681 | .set_idt = vmx_set_idt, | |
12682 | .get_gdt = vmx_get_gdt, | |
12683 | .set_gdt = vmx_set_gdt, | |
73aaf249 JK |
12684 | .get_dr6 = vmx_get_dr6, |
12685 | .set_dr6 = vmx_set_dr6, | |
020df079 | 12686 | .set_dr7 = vmx_set_dr7, |
81908bf4 | 12687 | .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, |
5fdbf976 | 12688 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
12689 | .get_rflags = vmx_get_rflags, |
12690 | .set_rflags = vmx_set_rflags, | |
be94f6b7 | 12691 | |
6aa8b732 | 12692 | .tlb_flush = vmx_flush_tlb, |
6aa8b732 | 12693 | |
6aa8b732 | 12694 | .run = vmx_vcpu_run, |
6062d012 | 12695 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 12696 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
12697 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
12698 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 12699 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 12700 | .set_irq = vmx_inject_irq, |
95ba8273 | 12701 | .set_nmi = vmx_inject_nmi, |
298101da | 12702 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 12703 | .cancel_injection = vmx_cancel_injection, |
78646121 | 12704 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 12705 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
12706 | .get_nmi_mask = vmx_get_nmi_mask, |
12707 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
12708 | .enable_nmi_window = enable_nmi_window, |
12709 | .enable_irq_window = enable_irq_window, | |
12710 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 12711 | .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode, |
38b99173 | 12712 | .set_apic_access_page_addr = vmx_set_apic_access_page_addr, |
d62caabb AS |
12713 | .get_enable_apicv = vmx_get_enable_apicv, |
12714 | .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, | |
c7c9c56c | 12715 | .load_eoi_exitmap = vmx_load_eoi_exitmap, |
967235d3 | 12716 | .apicv_post_state_restore = vmx_apicv_post_state_restore, |
c7c9c56c YZ |
12717 | .hwapic_irr_update = vmx_hwapic_irr_update, |
12718 | .hwapic_isr_update = vmx_hwapic_isr_update, | |
a20ed54d YZ |
12719 | .sync_pir_to_irr = vmx_sync_pir_to_irr, |
12720 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, | |
95ba8273 | 12721 | |
cbc94022 | 12722 | .set_tss_addr = vmx_set_tss_addr, |
2ac52ab8 | 12723 | .set_identity_map_addr = vmx_set_identity_map_addr, |
67253af5 | 12724 | .get_tdp_level = get_ept_level, |
4b12f0de | 12725 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 12726 | |
586f9607 | 12727 | .get_exit_info = vmx_get_exit_info, |
586f9607 | 12728 | |
17cc3935 | 12729 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
12730 | |
12731 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
12732 | |
12733 | .rdtscp_supported = vmx_rdtscp_supported, | |
ad756a16 | 12734 | .invpcid_supported = vmx_invpcid_supported, |
d4330ef2 JR |
12735 | |
12736 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
12737 | |
12738 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a | 12739 | |
e79f245d | 12740 | .read_l1_tsc_offset = vmx_read_l1_tsc_offset, |
99e3e30a | 12741 | .write_tsc_offset = vmx_write_tsc_offset, |
1c97f0a0 JR |
12742 | |
12743 | .set_tdp_cr3 = vmx_set_cr3, | |
8a76d7f2 JR |
12744 | |
12745 | .check_intercept = vmx_check_intercept, | |
a547c6db | 12746 | .handle_external_intr = vmx_handle_external_intr, |
da8999d3 | 12747 | .mpx_supported = vmx_mpx_supported, |
55412b2e | 12748 | .xsaves_supported = vmx_xsaves_supported, |
66336cab | 12749 | .umip_emulated = vmx_umip_emulated, |
b6b8a145 JK |
12750 | |
12751 | .check_nested_events = vmx_check_nested_events, | |
ae97a3b8 RK |
12752 | |
12753 | .sched_in = vmx_sched_in, | |
843e4330 KH |
12754 | |
12755 | .slot_enable_log_dirty = vmx_slot_enable_log_dirty, | |
12756 | .slot_disable_log_dirty = vmx_slot_disable_log_dirty, | |
12757 | .flush_log_dirty = vmx_flush_log_dirty, | |
12758 | .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, | |
c5f983f6 | 12759 | .write_log_dirty = vmx_write_pml_buffer, |
25462f7f | 12760 | |
bf9f6ac8 FW |
12761 | .pre_block = vmx_pre_block, |
12762 | .post_block = vmx_post_block, | |
12763 | ||
25462f7f | 12764 | .pmu_ops = &intel_pmu_ops, |
efc64404 FW |
12765 | |
12766 | .update_pi_irte = vmx_update_pi_irte, | |
64672c95 YJ |
12767 | |
12768 | #ifdef CONFIG_X86_64 | |
12769 | .set_hv_timer = vmx_set_hv_timer, | |
12770 | .cancel_hv_timer = vmx_cancel_hv_timer, | |
12771 | #endif | |
c45dcc71 AR |
12772 | |
12773 | .setup_mce = vmx_setup_mce, | |
0234bf88 | 12774 | |
72d7b374 | 12775 | .smi_allowed = vmx_smi_allowed, |
0234bf88 LP |
12776 | .pre_enter_smm = vmx_pre_enter_smm, |
12777 | .pre_leave_smm = vmx_pre_leave_smm, | |
cc3d967f | 12778 | .enable_smi_window = enable_smi_window, |
6aa8b732 AK |
12779 | }; |
12780 | ||
12781 | static int __init vmx_init(void) | |
12782 | { | |
773e8a04 VK |
12783 | int r; |
12784 | ||
12785 | #if IS_ENABLED(CONFIG_HYPERV) | |
12786 | /* | |
12787 | * Enlightened VMCS usage should be recommended and the host needs | |
12788 | * to support eVMCS v1 or above. We can also disable eVMCS support | |
12789 | * with module parameter. | |
12790 | */ | |
12791 | if (enlightened_vmcs && | |
12792 | ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && | |
12793 | (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= | |
12794 | KVM_EVMCS_VERSION) { | |
12795 | int cpu; | |
12796 | ||
12797 | /* Check that we have assist pages on all online CPUs */ | |
12798 | for_each_online_cpu(cpu) { | |
12799 | if (!hv_get_vp_assist_page(cpu)) { | |
12800 | enlightened_vmcs = false; | |
12801 | break; | |
12802 | } | |
12803 | } | |
12804 | ||
12805 | if (enlightened_vmcs) { | |
12806 | pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); | |
12807 | static_branch_enable(&enable_evmcs); | |
12808 | } | |
12809 | } else { | |
12810 | enlightened_vmcs = false; | |
12811 | } | |
12812 | #endif | |
12813 | ||
12814 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), | |
34a1cd60 | 12815 | __alignof__(struct vcpu_vmx), THIS_MODULE); |
fdef3ad1 | 12816 | if (r) |
34a1cd60 | 12817 | return r; |
25c5f225 | 12818 | |
2965faa5 | 12819 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
12820 | rcu_assign_pointer(crash_vmclear_loaded_vmcss, |
12821 | crash_vmclear_local_loaded_vmcss); | |
12822 | #endif | |
12823 | ||
fdef3ad1 | 12824 | return 0; |
6aa8b732 AK |
12825 | } |
12826 | ||
12827 | static void __exit vmx_exit(void) | |
12828 | { | |
2965faa5 | 12829 | #ifdef CONFIG_KEXEC_CORE |
3b63a43f | 12830 | RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); |
8f536b76 ZY |
12831 | synchronize_rcu(); |
12832 | #endif | |
12833 | ||
cb498ea2 | 12834 | kvm_exit(); |
773e8a04 VK |
12835 | |
12836 | #if IS_ENABLED(CONFIG_HYPERV) | |
12837 | if (static_branch_unlikely(&enable_evmcs)) { | |
12838 | int cpu; | |
12839 | struct hv_vp_assist_page *vp_ap; | |
12840 | /* | |
12841 | * Reset everything to support using non-enlightened VMCS | |
12842 | * access later (e.g. when we reload the module with | |
12843 | * enlightened_vmcs=0) | |
12844 | */ | |
12845 | for_each_online_cpu(cpu) { | |
12846 | vp_ap = hv_get_vp_assist_page(cpu); | |
12847 | ||
12848 | if (!vp_ap) | |
12849 | continue; | |
12850 | ||
12851 | vp_ap->current_nested_vmcs = 0; | |
12852 | vp_ap->enlighten_vmentry = 0; | |
12853 | } | |
12854 | ||
12855 | static_branch_disable(&enable_evmcs); | |
12856 | } | |
12857 | #endif | |
6aa8b732 AK |
12858 | } |
12859 | ||
12860 | module_init(vmx_init) | |
12861 | module_exit(vmx_exit) |