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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
00b27a3e | 21 | #include "cpuid.h" |
d62caabb | 22 | #include "lapic.h" |
e495606d | 23 | |
edf88417 | 24 | #include <linux/kvm_host.h> |
6aa8b732 | 25 | #include <linux/module.h> |
9d8f549d | 26 | #include <linux/kernel.h> |
6aa8b732 AK |
27 | #include <linux/mm.h> |
28 | #include <linux/highmem.h> | |
e8edc6e0 | 29 | #include <linux/sched.h> |
c7addb90 | 30 | #include <linux/moduleparam.h> |
e9bda3b3 | 31 | #include <linux/mod_devicetable.h> |
af658dca | 32 | #include <linux/trace_events.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
cafd6659 | 34 | #include <linux/tboot.h> |
f4124500 | 35 | #include <linux/hrtimer.h> |
c207aee4 | 36 | #include <linux/frame.h> |
085331df | 37 | #include <linux/nospec.h> |
5fdbf976 | 38 | #include "kvm_cache_regs.h" |
35920a35 | 39 | #include "x86.h" |
e495606d | 40 | |
28b835d6 | 41 | #include <asm/cpu.h> |
6aa8b732 | 42 | #include <asm/io.h> |
3b3be0d1 | 43 | #include <asm/desc.h> |
13673a90 | 44 | #include <asm/vmx.h> |
6210e37b | 45 | #include <asm/virtext.h> |
a0861c02 | 46 | #include <asm/mce.h> |
952f07ec | 47 | #include <asm/fpu/internal.h> |
d7cd9796 | 48 | #include <asm/perf_event.h> |
81908bf4 | 49 | #include <asm/debugreg.h> |
8f536b76 | 50 | #include <asm/kexec.h> |
dab2087d | 51 | #include <asm/apic.h> |
efc64404 | 52 | #include <asm/irq_remapping.h> |
d6e41f11 | 53 | #include <asm/mmu_context.h> |
117cc7a9 | 54 | #include <asm/nospec-branch.h> |
6aa8b732 | 55 | |
229456fc | 56 | #include "trace.h" |
25462f7f | 57 | #include "pmu.h" |
229456fc | 58 | |
4ecac3fd | 59 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
5e520e62 AK |
60 | #define __ex_clear(x, reg) \ |
61 | ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) | |
4ecac3fd | 62 | |
6aa8b732 AK |
63 | MODULE_AUTHOR("Qumranet"); |
64 | MODULE_LICENSE("GPL"); | |
65 | ||
e9bda3b3 JT |
66 | static const struct x86_cpu_id vmx_cpu_id[] = { |
67 | X86_FEATURE_MATCH(X86_FEATURE_VMX), | |
68 | {} | |
69 | }; | |
70 | MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); | |
71 | ||
476bc001 | 72 | static bool __read_mostly enable_vpid = 1; |
736caefe | 73 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 74 | |
d02fcf50 PB |
75 | static bool __read_mostly enable_vnmi = 1; |
76 | module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); | |
77 | ||
476bc001 | 78 | static bool __read_mostly flexpriority_enabled = 1; |
736caefe | 79 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 80 | |
476bc001 | 81 | static bool __read_mostly enable_ept = 1; |
736caefe | 82 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 83 | |
476bc001 | 84 | static bool __read_mostly enable_unrestricted_guest = 1; |
3a624e29 NK |
85 | module_param_named(unrestricted_guest, |
86 | enable_unrestricted_guest, bool, S_IRUGO); | |
87 | ||
83c3a331 XH |
88 | static bool __read_mostly enable_ept_ad_bits = 1; |
89 | module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); | |
90 | ||
a27685c3 | 91 | static bool __read_mostly emulate_invalid_guest_state = true; |
c1f8bc04 | 92 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 93 | |
476bc001 | 94 | static bool __read_mostly fasteoi = 1; |
58fbbf26 KT |
95 | module_param(fasteoi, bool, S_IRUGO); |
96 | ||
5a71785d | 97 | static bool __read_mostly enable_apicv = 1; |
01e439be | 98 | module_param(enable_apicv, bool, S_IRUGO); |
83d4c286 | 99 | |
abc4fc58 AG |
100 | static bool __read_mostly enable_shadow_vmcs = 1; |
101 | module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); | |
801d3424 NHE |
102 | /* |
103 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
104 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
105 | * use VMX instructions. | |
106 | */ | |
476bc001 | 107 | static bool __read_mostly nested = 0; |
801d3424 NHE |
108 | module_param(nested, bool, S_IRUGO); |
109 | ||
20300099 WL |
110 | static u64 __read_mostly host_xss; |
111 | ||
843e4330 KH |
112 | static bool __read_mostly enable_pml = 1; |
113 | module_param_named(pml, enable_pml, bool, S_IRUGO); | |
114 | ||
904e14fb PB |
115 | #define MSR_TYPE_R 1 |
116 | #define MSR_TYPE_W 2 | |
117 | #define MSR_TYPE_RW 3 | |
118 | ||
119 | #define MSR_BITMAP_MODE_X2APIC 1 | |
120 | #define MSR_BITMAP_MODE_X2APIC_APICV 2 | |
121 | #define MSR_BITMAP_MODE_LM 4 | |
122 | ||
64903d61 HZ |
123 | #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL |
124 | ||
64672c95 YJ |
125 | /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ |
126 | static int __read_mostly cpu_preemption_timer_multi; | |
127 | static bool __read_mostly enable_preemption_timer = 1; | |
128 | #ifdef CONFIG_X86_64 | |
129 | module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); | |
130 | #endif | |
131 | ||
5037878e GN |
132 | #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD) |
133 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE) | |
cdc0e244 AK |
134 | #define KVM_VM_CR0_ALWAYS_ON \ |
135 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
136 | #define KVM_CR4_GUEST_OWNED_BITS \ |
137 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
fd8cb433 | 138 | | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) |
4c38609a | 139 | |
cdc0e244 AK |
140 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
141 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
142 | ||
78ac8b47 AK |
143 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
144 | ||
f4124500 JK |
145 | #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 |
146 | ||
16c2aec6 JD |
147 | /* |
148 | * Hyper-V requires all of these, so mark them as supported even though | |
149 | * they are just treated the same as all-context. | |
150 | */ | |
151 | #define VMX_VPID_EXTENT_SUPPORTED_MASK \ | |
152 | (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \ | |
153 | VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \ | |
154 | VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \ | |
155 | VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT) | |
156 | ||
4b8d54f9 ZE |
157 | /* |
158 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
159 | * ple_gap: upper bound on the amount of time between two successive | |
160 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 161 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
162 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
163 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
164 | * less than 2^12 cycles | |
165 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
166 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
167 | */ | |
b4a2d31d RK |
168 | #define KVM_VMX_DEFAULT_PLE_GAP 128 |
169 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 | |
170 | #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2 | |
171 | #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0 | |
172 | #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \ | |
173 | INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW | |
174 | ||
4b8d54f9 ZE |
175 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; |
176 | module_param(ple_gap, int, S_IRUGO); | |
177 | ||
178 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
179 | module_param(ple_window, int, S_IRUGO); | |
180 | ||
b4a2d31d RK |
181 | /* Default doubles per-vcpu window every exit. */ |
182 | static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW; | |
183 | module_param(ple_window_grow, int, S_IRUGO); | |
184 | ||
185 | /* Default resets per-vcpu window every exit to ple_window. */ | |
186 | static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK; | |
187 | module_param(ple_window_shrink, int, S_IRUGO); | |
188 | ||
189 | /* Default is to compute the maximum so we can never overflow. */ | |
190 | static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
191 | static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
192 | module_param(ple_window_max, int, S_IRUGO); | |
193 | ||
83287ea4 AK |
194 | extern const ulong vmx_return; |
195 | ||
8bf00a52 | 196 | #define NR_AUTOLOAD_MSRS 8 |
61d2ef2c | 197 | |
a2fa3e9f GH |
198 | struct vmcs { |
199 | u32 revision_id; | |
200 | u32 abort; | |
201 | char data[0]; | |
202 | }; | |
203 | ||
d462b819 NHE |
204 | /* |
205 | * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also | |
206 | * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs | |
207 | * loaded on this CPU (so we can clear them if the CPU goes down). | |
208 | */ | |
209 | struct loaded_vmcs { | |
210 | struct vmcs *vmcs; | |
355f4fb1 | 211 | struct vmcs *shadow_vmcs; |
d462b819 | 212 | int cpu; |
4c4a6f79 PB |
213 | bool launched; |
214 | bool nmi_known_unmasked; | |
44889942 LP |
215 | unsigned long vmcs_host_cr3; /* May not match real cr3 */ |
216 | unsigned long vmcs_host_cr4; /* May not match real cr4 */ | |
8a1b4392 PB |
217 | /* Support for vnmi-less CPUs */ |
218 | int soft_vnmi_blocked; | |
219 | ktime_t entry_time; | |
220 | s64 vnmi_blocked_time; | |
904e14fb | 221 | unsigned long *msr_bitmap; |
d462b819 NHE |
222 | struct list_head loaded_vmcss_on_cpu_link; |
223 | }; | |
224 | ||
26bb0981 AK |
225 | struct shared_msr_entry { |
226 | unsigned index; | |
227 | u64 data; | |
d5696725 | 228 | u64 mask; |
26bb0981 AK |
229 | }; |
230 | ||
a9d30f33 NHE |
231 | /* |
232 | * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a | |
233 | * single nested guest (L2), hence the name vmcs12. Any VMX implementation has | |
234 | * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is | |
235 | * stored in guest memory specified by VMPTRLD, but is opaque to the guest, | |
236 | * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. | |
237 | * More than one of these structures may exist, if L1 runs multiple L2 guests. | |
de3a0021 | 238 | * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the |
a9d30f33 NHE |
239 | * underlying hardware which will be used to run L2. |
240 | * This structure is packed to ensure that its layout is identical across | |
241 | * machines (necessary for live migration). | |
242 | * If there are changes in this struct, VMCS12_REVISION must be changed. | |
243 | */ | |
22bd0358 | 244 | typedef u64 natural_width; |
a9d30f33 NHE |
245 | struct __packed vmcs12 { |
246 | /* According to the Intel spec, a VMCS region must start with the | |
247 | * following two fields. Then follow implementation-specific data. | |
248 | */ | |
249 | u32 revision_id; | |
250 | u32 abort; | |
22bd0358 | 251 | |
27d6c865 NHE |
252 | u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ |
253 | u32 padding[7]; /* room for future expansion */ | |
254 | ||
22bd0358 NHE |
255 | u64 io_bitmap_a; |
256 | u64 io_bitmap_b; | |
257 | u64 msr_bitmap; | |
258 | u64 vm_exit_msr_store_addr; | |
259 | u64 vm_exit_msr_load_addr; | |
260 | u64 vm_entry_msr_load_addr; | |
261 | u64 tsc_offset; | |
262 | u64 virtual_apic_page_addr; | |
263 | u64 apic_access_addr; | |
705699a1 | 264 | u64 posted_intr_desc_addr; |
27c42a1b | 265 | u64 vm_function_control; |
22bd0358 | 266 | u64 ept_pointer; |
608406e2 WV |
267 | u64 eoi_exit_bitmap0; |
268 | u64 eoi_exit_bitmap1; | |
269 | u64 eoi_exit_bitmap2; | |
270 | u64 eoi_exit_bitmap3; | |
41ab9372 | 271 | u64 eptp_list_address; |
81dc01f7 | 272 | u64 xss_exit_bitmap; |
22bd0358 NHE |
273 | u64 guest_physical_address; |
274 | u64 vmcs_link_pointer; | |
c5f983f6 | 275 | u64 pml_address; |
22bd0358 NHE |
276 | u64 guest_ia32_debugctl; |
277 | u64 guest_ia32_pat; | |
278 | u64 guest_ia32_efer; | |
279 | u64 guest_ia32_perf_global_ctrl; | |
280 | u64 guest_pdptr0; | |
281 | u64 guest_pdptr1; | |
282 | u64 guest_pdptr2; | |
283 | u64 guest_pdptr3; | |
36be0b9d | 284 | u64 guest_bndcfgs; |
22bd0358 NHE |
285 | u64 host_ia32_pat; |
286 | u64 host_ia32_efer; | |
287 | u64 host_ia32_perf_global_ctrl; | |
288 | u64 padding64[8]; /* room for future expansion */ | |
289 | /* | |
290 | * To allow migration of L1 (complete with its L2 guests) between | |
291 | * machines of different natural widths (32 or 64 bit), we cannot have | |
292 | * unsigned long fields with no explict size. We use u64 (aliased | |
293 | * natural_width) instead. Luckily, x86 is little-endian. | |
294 | */ | |
295 | natural_width cr0_guest_host_mask; | |
296 | natural_width cr4_guest_host_mask; | |
297 | natural_width cr0_read_shadow; | |
298 | natural_width cr4_read_shadow; | |
299 | natural_width cr3_target_value0; | |
300 | natural_width cr3_target_value1; | |
301 | natural_width cr3_target_value2; | |
302 | natural_width cr3_target_value3; | |
303 | natural_width exit_qualification; | |
304 | natural_width guest_linear_address; | |
305 | natural_width guest_cr0; | |
306 | natural_width guest_cr3; | |
307 | natural_width guest_cr4; | |
308 | natural_width guest_es_base; | |
309 | natural_width guest_cs_base; | |
310 | natural_width guest_ss_base; | |
311 | natural_width guest_ds_base; | |
312 | natural_width guest_fs_base; | |
313 | natural_width guest_gs_base; | |
314 | natural_width guest_ldtr_base; | |
315 | natural_width guest_tr_base; | |
316 | natural_width guest_gdtr_base; | |
317 | natural_width guest_idtr_base; | |
318 | natural_width guest_dr7; | |
319 | natural_width guest_rsp; | |
320 | natural_width guest_rip; | |
321 | natural_width guest_rflags; | |
322 | natural_width guest_pending_dbg_exceptions; | |
323 | natural_width guest_sysenter_esp; | |
324 | natural_width guest_sysenter_eip; | |
325 | natural_width host_cr0; | |
326 | natural_width host_cr3; | |
327 | natural_width host_cr4; | |
328 | natural_width host_fs_base; | |
329 | natural_width host_gs_base; | |
330 | natural_width host_tr_base; | |
331 | natural_width host_gdtr_base; | |
332 | natural_width host_idtr_base; | |
333 | natural_width host_ia32_sysenter_esp; | |
334 | natural_width host_ia32_sysenter_eip; | |
335 | natural_width host_rsp; | |
336 | natural_width host_rip; | |
337 | natural_width paddingl[8]; /* room for future expansion */ | |
338 | u32 pin_based_vm_exec_control; | |
339 | u32 cpu_based_vm_exec_control; | |
340 | u32 exception_bitmap; | |
341 | u32 page_fault_error_code_mask; | |
342 | u32 page_fault_error_code_match; | |
343 | u32 cr3_target_count; | |
344 | u32 vm_exit_controls; | |
345 | u32 vm_exit_msr_store_count; | |
346 | u32 vm_exit_msr_load_count; | |
347 | u32 vm_entry_controls; | |
348 | u32 vm_entry_msr_load_count; | |
349 | u32 vm_entry_intr_info_field; | |
350 | u32 vm_entry_exception_error_code; | |
351 | u32 vm_entry_instruction_len; | |
352 | u32 tpr_threshold; | |
353 | u32 secondary_vm_exec_control; | |
354 | u32 vm_instruction_error; | |
355 | u32 vm_exit_reason; | |
356 | u32 vm_exit_intr_info; | |
357 | u32 vm_exit_intr_error_code; | |
358 | u32 idt_vectoring_info_field; | |
359 | u32 idt_vectoring_error_code; | |
360 | u32 vm_exit_instruction_len; | |
361 | u32 vmx_instruction_info; | |
362 | u32 guest_es_limit; | |
363 | u32 guest_cs_limit; | |
364 | u32 guest_ss_limit; | |
365 | u32 guest_ds_limit; | |
366 | u32 guest_fs_limit; | |
367 | u32 guest_gs_limit; | |
368 | u32 guest_ldtr_limit; | |
369 | u32 guest_tr_limit; | |
370 | u32 guest_gdtr_limit; | |
371 | u32 guest_idtr_limit; | |
372 | u32 guest_es_ar_bytes; | |
373 | u32 guest_cs_ar_bytes; | |
374 | u32 guest_ss_ar_bytes; | |
375 | u32 guest_ds_ar_bytes; | |
376 | u32 guest_fs_ar_bytes; | |
377 | u32 guest_gs_ar_bytes; | |
378 | u32 guest_ldtr_ar_bytes; | |
379 | u32 guest_tr_ar_bytes; | |
380 | u32 guest_interruptibility_info; | |
381 | u32 guest_activity_state; | |
382 | u32 guest_sysenter_cs; | |
383 | u32 host_ia32_sysenter_cs; | |
0238ea91 JK |
384 | u32 vmx_preemption_timer_value; |
385 | u32 padding32[7]; /* room for future expansion */ | |
22bd0358 | 386 | u16 virtual_processor_id; |
705699a1 | 387 | u16 posted_intr_nv; |
22bd0358 NHE |
388 | u16 guest_es_selector; |
389 | u16 guest_cs_selector; | |
390 | u16 guest_ss_selector; | |
391 | u16 guest_ds_selector; | |
392 | u16 guest_fs_selector; | |
393 | u16 guest_gs_selector; | |
394 | u16 guest_ldtr_selector; | |
395 | u16 guest_tr_selector; | |
608406e2 | 396 | u16 guest_intr_status; |
c5f983f6 | 397 | u16 guest_pml_index; |
22bd0358 NHE |
398 | u16 host_es_selector; |
399 | u16 host_cs_selector; | |
400 | u16 host_ss_selector; | |
401 | u16 host_ds_selector; | |
402 | u16 host_fs_selector; | |
403 | u16 host_gs_selector; | |
404 | u16 host_tr_selector; | |
a9d30f33 NHE |
405 | }; |
406 | ||
407 | /* | |
408 | * VMCS12_REVISION is an arbitrary id that should be changed if the content or | |
409 | * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and | |
410 | * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. | |
411 | */ | |
412 | #define VMCS12_REVISION 0x11e57ed0 | |
413 | ||
414 | /* | |
415 | * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region | |
416 | * and any VMCS region. Although only sizeof(struct vmcs12) are used by the | |
417 | * current implementation, 4K are reserved to avoid future complications. | |
418 | */ | |
419 | #define VMCS12_SIZE 0x1000 | |
420 | ||
ec378aee NHE |
421 | /* |
422 | * The nested_vmx structure is part of vcpu_vmx, and holds information we need | |
423 | * for correct emulation of VMX (i.e., nested VMX) on this vcpu. | |
424 | */ | |
425 | struct nested_vmx { | |
426 | /* Has the level1 guest done vmxon? */ | |
427 | bool vmxon; | |
3573e22c | 428 | gpa_t vmxon_ptr; |
c5f983f6 | 429 | bool pml_full; |
a9d30f33 NHE |
430 | |
431 | /* The guest-physical address of the current VMCS L1 keeps for L2 */ | |
432 | gpa_t current_vmptr; | |
4f2777bc DM |
433 | /* |
434 | * Cache of the guest's VMCS, existing outside of guest memory. | |
435 | * Loaded from guest memory during VMPTRLD. Flushed to guest | |
8ca44e88 | 436 | * memory during VMCLEAR and VMPTRLD. |
4f2777bc DM |
437 | */ |
438 | struct vmcs12 *cached_vmcs12; | |
012f83cb AG |
439 | /* |
440 | * Indicates if the shadow vmcs must be updated with the | |
441 | * data hold by vmcs12 | |
442 | */ | |
443 | bool sync_shadow_vmcs; | |
ff2f6fe9 | 444 | |
dccbfcf5 | 445 | bool change_vmcs01_virtual_x2apic_mode; |
644d711a NHE |
446 | /* L2 must run next, and mustn't decide to exit to L1. */ |
447 | bool nested_run_pending; | |
de3a0021 JM |
448 | |
449 | struct loaded_vmcs vmcs02; | |
450 | ||
fe3ef05c | 451 | /* |
de3a0021 JM |
452 | * Guest pages referred to in the vmcs02 with host-physical |
453 | * pointers, so we must keep them pinned while L2 runs. | |
fe3ef05c NHE |
454 | */ |
455 | struct page *apic_access_page; | |
a7c0b07d | 456 | struct page *virtual_apic_page; |
705699a1 WV |
457 | struct page *pi_desc_page; |
458 | struct pi_desc *pi_desc; | |
459 | bool pi_pending; | |
460 | u16 posted_intr_nv; | |
f4124500 JK |
461 | |
462 | struct hrtimer preemption_timer; | |
463 | bool preemption_timer_expired; | |
2996fca0 JK |
464 | |
465 | /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ | |
466 | u64 vmcs01_debugctl; | |
b9c237bb | 467 | |
5c614b35 WL |
468 | u16 vpid02; |
469 | u16 last_vpid; | |
470 | ||
0115f9cb DM |
471 | /* |
472 | * We only store the "true" versions of the VMX capability MSRs. We | |
473 | * generate the "non-true" versions by setting the must-be-1 bits | |
474 | * according to the SDM. | |
475 | */ | |
b9c237bb WV |
476 | u32 nested_vmx_procbased_ctls_low; |
477 | u32 nested_vmx_procbased_ctls_high; | |
b9c237bb WV |
478 | u32 nested_vmx_secondary_ctls_low; |
479 | u32 nested_vmx_secondary_ctls_high; | |
480 | u32 nested_vmx_pinbased_ctls_low; | |
481 | u32 nested_vmx_pinbased_ctls_high; | |
482 | u32 nested_vmx_exit_ctls_low; | |
483 | u32 nested_vmx_exit_ctls_high; | |
b9c237bb WV |
484 | u32 nested_vmx_entry_ctls_low; |
485 | u32 nested_vmx_entry_ctls_high; | |
b9c237bb WV |
486 | u32 nested_vmx_misc_low; |
487 | u32 nested_vmx_misc_high; | |
488 | u32 nested_vmx_ept_caps; | |
99b83ac8 | 489 | u32 nested_vmx_vpid_caps; |
62cc6b9d DM |
490 | u64 nested_vmx_basic; |
491 | u64 nested_vmx_cr0_fixed0; | |
492 | u64 nested_vmx_cr0_fixed1; | |
493 | u64 nested_vmx_cr4_fixed0; | |
494 | u64 nested_vmx_cr4_fixed1; | |
495 | u64 nested_vmx_vmcs_enum; | |
27c42a1b | 496 | u64 nested_vmx_vmfunc_controls; |
72e9cbdb LP |
497 | |
498 | /* SMM related state */ | |
499 | struct { | |
500 | /* in VMX operation on SMM entry? */ | |
501 | bool vmxon; | |
502 | /* in guest mode on SMM entry? */ | |
503 | bool guest_mode; | |
504 | } smm; | |
ec378aee NHE |
505 | }; |
506 | ||
01e439be | 507 | #define POSTED_INTR_ON 0 |
ebbfc765 FW |
508 | #define POSTED_INTR_SN 1 |
509 | ||
01e439be YZ |
510 | /* Posted-Interrupt Descriptor */ |
511 | struct pi_desc { | |
512 | u32 pir[8]; /* Posted interrupt requested */ | |
6ef1522f FW |
513 | union { |
514 | struct { | |
515 | /* bit 256 - Outstanding Notification */ | |
516 | u16 on : 1, | |
517 | /* bit 257 - Suppress Notification */ | |
518 | sn : 1, | |
519 | /* bit 271:258 - Reserved */ | |
520 | rsvd_1 : 14; | |
521 | /* bit 279:272 - Notification Vector */ | |
522 | u8 nv; | |
523 | /* bit 287:280 - Reserved */ | |
524 | u8 rsvd_2; | |
525 | /* bit 319:288 - Notification Destination */ | |
526 | u32 ndst; | |
527 | }; | |
528 | u64 control; | |
529 | }; | |
530 | u32 rsvd[6]; | |
01e439be YZ |
531 | } __aligned(64); |
532 | ||
a20ed54d YZ |
533 | static bool pi_test_and_set_on(struct pi_desc *pi_desc) |
534 | { | |
535 | return test_and_set_bit(POSTED_INTR_ON, | |
536 | (unsigned long *)&pi_desc->control); | |
537 | } | |
538 | ||
539 | static bool pi_test_and_clear_on(struct pi_desc *pi_desc) | |
540 | { | |
541 | return test_and_clear_bit(POSTED_INTR_ON, | |
542 | (unsigned long *)&pi_desc->control); | |
543 | } | |
544 | ||
545 | static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) | |
546 | { | |
547 | return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); | |
548 | } | |
549 | ||
ebbfc765 FW |
550 | static inline void pi_clear_sn(struct pi_desc *pi_desc) |
551 | { | |
552 | return clear_bit(POSTED_INTR_SN, | |
553 | (unsigned long *)&pi_desc->control); | |
554 | } | |
555 | ||
556 | static inline void pi_set_sn(struct pi_desc *pi_desc) | |
557 | { | |
558 | return set_bit(POSTED_INTR_SN, | |
559 | (unsigned long *)&pi_desc->control); | |
560 | } | |
561 | ||
ad361091 PB |
562 | static inline void pi_clear_on(struct pi_desc *pi_desc) |
563 | { | |
564 | clear_bit(POSTED_INTR_ON, | |
565 | (unsigned long *)&pi_desc->control); | |
566 | } | |
567 | ||
ebbfc765 FW |
568 | static inline int pi_test_on(struct pi_desc *pi_desc) |
569 | { | |
570 | return test_bit(POSTED_INTR_ON, | |
571 | (unsigned long *)&pi_desc->control); | |
572 | } | |
573 | ||
574 | static inline int pi_test_sn(struct pi_desc *pi_desc) | |
575 | { | |
576 | return test_bit(POSTED_INTR_SN, | |
577 | (unsigned long *)&pi_desc->control); | |
578 | } | |
579 | ||
a2fa3e9f | 580 | struct vcpu_vmx { |
fb3f0f51 | 581 | struct kvm_vcpu vcpu; |
313dbd49 | 582 | unsigned long host_rsp; |
29bd8a78 | 583 | u8 fail; |
904e14fb | 584 | u8 msr_bitmap_mode; |
51aa01d1 | 585 | u32 exit_intr_info; |
1155f76a | 586 | u32 idt_vectoring_info; |
6de12732 | 587 | ulong rflags; |
26bb0981 | 588 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
589 | int nmsrs; |
590 | int save_nmsrs; | |
a547c6db | 591 | unsigned long host_idt_base; |
a2fa3e9f | 592 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
593 | u64 msr_host_kernel_gs_base; |
594 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f | 595 | #endif |
2961e876 GN |
596 | u32 vm_entry_controls_shadow; |
597 | u32 vm_exit_controls_shadow; | |
80154d77 PB |
598 | u32 secondary_exec_control; |
599 | ||
d462b819 NHE |
600 | /* |
601 | * loaded_vmcs points to the VMCS currently used in this vcpu. For a | |
602 | * non-nested (L1) guest, it always points to vmcs01. For a nested | |
603 | * guest (L2), it points to a different VMCS. | |
604 | */ | |
605 | struct loaded_vmcs vmcs01; | |
606 | struct loaded_vmcs *loaded_vmcs; | |
607 | bool __launched; /* temporary, used in vmx_vcpu_run */ | |
61d2ef2c AK |
608 | struct msr_autoload { |
609 | unsigned nr; | |
610 | struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; | |
611 | struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; | |
612 | } msr_autoload; | |
a2fa3e9f GH |
613 | struct { |
614 | int loaded; | |
615 | u16 fs_sel, gs_sel, ldt_sel; | |
b2da15ac AK |
616 | #ifdef CONFIG_X86_64 |
617 | u16 ds_sel, es_sel; | |
618 | #endif | |
152d3f2f LV |
619 | int gs_ldt_reload_needed; |
620 | int fs_reload_needed; | |
da8999d3 | 621 | u64 msr_host_bndcfgs; |
d77c26fc | 622 | } host_state; |
9c8cba37 | 623 | struct { |
7ffd92c5 | 624 | int vm86_active; |
78ac8b47 | 625 | ulong save_rflags; |
f5f7b2fe AK |
626 | struct kvm_segment segs[8]; |
627 | } rmode; | |
628 | struct { | |
629 | u32 bitmask; /* 4 bits per segment (1 bit per field) */ | |
7ffd92c5 AK |
630 | struct kvm_save_segment { |
631 | u16 selector; | |
632 | unsigned long base; | |
633 | u32 limit; | |
634 | u32 ar; | |
f5f7b2fe | 635 | } seg[8]; |
2fb92db1 | 636 | } segment_cache; |
2384d2b3 | 637 | int vpid; |
04fa4d32 | 638 | bool emulation_required; |
3b86cd99 | 639 | |
a0861c02 | 640 | u32 exit_reason; |
4e47c7a6 | 641 | |
01e439be YZ |
642 | /* Posted interrupt descriptor */ |
643 | struct pi_desc pi_desc; | |
644 | ||
ec378aee NHE |
645 | /* Support for a guest hypervisor (nested VMX) */ |
646 | struct nested_vmx nested; | |
a7653ecd RK |
647 | |
648 | /* Dynamic PLE window. */ | |
649 | int ple_window; | |
650 | bool ple_window_dirty; | |
843e4330 KH |
651 | |
652 | /* Support for PML */ | |
653 | #define PML_ENTITY_NUM 512 | |
654 | struct page *pml_pg; | |
2680d6da | 655 | |
64672c95 YJ |
656 | /* apic deadline value in host tsc */ |
657 | u64 hv_deadline_tsc; | |
658 | ||
2680d6da | 659 | u64 current_tsc_ratio; |
1be0e61c | 660 | |
1be0e61c | 661 | u32 host_pkru; |
3b84080b | 662 | |
37e4c997 HZ |
663 | /* |
664 | * Only bits masked by msr_ia32_feature_control_valid_bits can be set in | |
665 | * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included | |
666 | * in msr_ia32_feature_control_valid_bits. | |
667 | */ | |
3b84080b | 668 | u64 msr_ia32_feature_control; |
37e4c997 | 669 | u64 msr_ia32_feature_control_valid_bits; |
a2fa3e9f GH |
670 | }; |
671 | ||
2fb92db1 AK |
672 | enum segment_cache_field { |
673 | SEG_FIELD_SEL = 0, | |
674 | SEG_FIELD_BASE = 1, | |
675 | SEG_FIELD_LIMIT = 2, | |
676 | SEG_FIELD_AR = 3, | |
677 | ||
678 | SEG_FIELD_NR = 4 | |
679 | }; | |
680 | ||
a2fa3e9f GH |
681 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
682 | { | |
fb3f0f51 | 683 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
684 | } |
685 | ||
efc64404 FW |
686 | static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu) |
687 | { | |
688 | return &(to_vmx(vcpu)->pi_desc); | |
689 | } | |
690 | ||
22bd0358 NHE |
691 | #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x) |
692 | #define FIELD(number, name) [number] = VMCS12_OFFSET(name) | |
693 | #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \ | |
694 | [number##_HIGH] = VMCS12_OFFSET(name)+4 | |
695 | ||
4607c2d7 | 696 | |
fe2b201b | 697 | static unsigned long shadow_read_only_fields[] = { |
4607c2d7 AG |
698 | /* |
699 | * We do NOT shadow fields that are modified when L0 | |
700 | * traps and emulates any vmx instruction (e.g. VMPTRLD, | |
701 | * VMXON...) executed by L1. | |
702 | * For example, VM_INSTRUCTION_ERROR is read | |
703 | * by L1 if a vmx instruction fails (part of the error path). | |
704 | * Note the code assumes this logic. If for some reason | |
705 | * we start shadowing these fields then we need to | |
706 | * force a shadow sync when L0 emulates vmx instructions | |
707 | * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified | |
708 | * by nested_vmx_failValid) | |
709 | */ | |
710 | VM_EXIT_REASON, | |
711 | VM_EXIT_INTR_INFO, | |
712 | VM_EXIT_INSTRUCTION_LEN, | |
713 | IDT_VECTORING_INFO_FIELD, | |
714 | IDT_VECTORING_ERROR_CODE, | |
715 | VM_EXIT_INTR_ERROR_CODE, | |
716 | EXIT_QUALIFICATION, | |
717 | GUEST_LINEAR_ADDRESS, | |
718 | GUEST_PHYSICAL_ADDRESS | |
719 | }; | |
fe2b201b | 720 | static int max_shadow_read_only_fields = |
4607c2d7 AG |
721 | ARRAY_SIZE(shadow_read_only_fields); |
722 | ||
fe2b201b | 723 | static unsigned long shadow_read_write_fields[] = { |
a7c0b07d | 724 | TPR_THRESHOLD, |
4607c2d7 AG |
725 | GUEST_RIP, |
726 | GUEST_RSP, | |
727 | GUEST_CR0, | |
728 | GUEST_CR3, | |
729 | GUEST_CR4, | |
730 | GUEST_INTERRUPTIBILITY_INFO, | |
731 | GUEST_RFLAGS, | |
732 | GUEST_CS_SELECTOR, | |
733 | GUEST_CS_AR_BYTES, | |
734 | GUEST_CS_LIMIT, | |
735 | GUEST_CS_BASE, | |
736 | GUEST_ES_BASE, | |
36be0b9d | 737 | GUEST_BNDCFGS, |
4607c2d7 AG |
738 | CR0_GUEST_HOST_MASK, |
739 | CR0_READ_SHADOW, | |
740 | CR4_READ_SHADOW, | |
741 | TSC_OFFSET, | |
742 | EXCEPTION_BITMAP, | |
743 | CPU_BASED_VM_EXEC_CONTROL, | |
744 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
745 | VM_ENTRY_INTR_INFO_FIELD, | |
746 | VM_ENTRY_INSTRUCTION_LEN, | |
747 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
748 | HOST_FS_BASE, | |
749 | HOST_GS_BASE, | |
750 | HOST_FS_SELECTOR, | |
751 | HOST_GS_SELECTOR | |
752 | }; | |
fe2b201b | 753 | static int max_shadow_read_write_fields = |
4607c2d7 AG |
754 | ARRAY_SIZE(shadow_read_write_fields); |
755 | ||
772e0318 | 756 | static const unsigned short vmcs_field_to_offset_table[] = { |
22bd0358 | 757 | FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id), |
705699a1 | 758 | FIELD(POSTED_INTR_NV, posted_intr_nv), |
22bd0358 NHE |
759 | FIELD(GUEST_ES_SELECTOR, guest_es_selector), |
760 | FIELD(GUEST_CS_SELECTOR, guest_cs_selector), | |
761 | FIELD(GUEST_SS_SELECTOR, guest_ss_selector), | |
762 | FIELD(GUEST_DS_SELECTOR, guest_ds_selector), | |
763 | FIELD(GUEST_FS_SELECTOR, guest_fs_selector), | |
764 | FIELD(GUEST_GS_SELECTOR, guest_gs_selector), | |
765 | FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector), | |
766 | FIELD(GUEST_TR_SELECTOR, guest_tr_selector), | |
608406e2 | 767 | FIELD(GUEST_INTR_STATUS, guest_intr_status), |
c5f983f6 | 768 | FIELD(GUEST_PML_INDEX, guest_pml_index), |
22bd0358 NHE |
769 | FIELD(HOST_ES_SELECTOR, host_es_selector), |
770 | FIELD(HOST_CS_SELECTOR, host_cs_selector), | |
771 | FIELD(HOST_SS_SELECTOR, host_ss_selector), | |
772 | FIELD(HOST_DS_SELECTOR, host_ds_selector), | |
773 | FIELD(HOST_FS_SELECTOR, host_fs_selector), | |
774 | FIELD(HOST_GS_SELECTOR, host_gs_selector), | |
775 | FIELD(HOST_TR_SELECTOR, host_tr_selector), | |
776 | FIELD64(IO_BITMAP_A, io_bitmap_a), | |
777 | FIELD64(IO_BITMAP_B, io_bitmap_b), | |
778 | FIELD64(MSR_BITMAP, msr_bitmap), | |
779 | FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr), | |
780 | FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr), | |
781 | FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr), | |
782 | FIELD64(TSC_OFFSET, tsc_offset), | |
783 | FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), | |
784 | FIELD64(APIC_ACCESS_ADDR, apic_access_addr), | |
705699a1 | 785 | FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr), |
27c42a1b | 786 | FIELD64(VM_FUNCTION_CONTROL, vm_function_control), |
22bd0358 | 787 | FIELD64(EPT_POINTER, ept_pointer), |
608406e2 WV |
788 | FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0), |
789 | FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1), | |
790 | FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2), | |
791 | FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3), | |
41ab9372 | 792 | FIELD64(EPTP_LIST_ADDRESS, eptp_list_address), |
81dc01f7 | 793 | FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap), |
22bd0358 NHE |
794 | FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), |
795 | FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), | |
c5f983f6 | 796 | FIELD64(PML_ADDRESS, pml_address), |
22bd0358 NHE |
797 | FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), |
798 | FIELD64(GUEST_IA32_PAT, guest_ia32_pat), | |
799 | FIELD64(GUEST_IA32_EFER, guest_ia32_efer), | |
800 | FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl), | |
801 | FIELD64(GUEST_PDPTR0, guest_pdptr0), | |
802 | FIELD64(GUEST_PDPTR1, guest_pdptr1), | |
803 | FIELD64(GUEST_PDPTR2, guest_pdptr2), | |
804 | FIELD64(GUEST_PDPTR3, guest_pdptr3), | |
36be0b9d | 805 | FIELD64(GUEST_BNDCFGS, guest_bndcfgs), |
22bd0358 NHE |
806 | FIELD64(HOST_IA32_PAT, host_ia32_pat), |
807 | FIELD64(HOST_IA32_EFER, host_ia32_efer), | |
808 | FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), | |
809 | FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), | |
810 | FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), | |
811 | FIELD(EXCEPTION_BITMAP, exception_bitmap), | |
812 | FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask), | |
813 | FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match), | |
814 | FIELD(CR3_TARGET_COUNT, cr3_target_count), | |
815 | FIELD(VM_EXIT_CONTROLS, vm_exit_controls), | |
816 | FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count), | |
817 | FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count), | |
818 | FIELD(VM_ENTRY_CONTROLS, vm_entry_controls), | |
819 | FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count), | |
820 | FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field), | |
821 | FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code), | |
822 | FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len), | |
823 | FIELD(TPR_THRESHOLD, tpr_threshold), | |
824 | FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control), | |
825 | FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error), | |
826 | FIELD(VM_EXIT_REASON, vm_exit_reason), | |
827 | FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info), | |
828 | FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code), | |
829 | FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field), | |
830 | FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code), | |
831 | FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len), | |
832 | FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info), | |
833 | FIELD(GUEST_ES_LIMIT, guest_es_limit), | |
834 | FIELD(GUEST_CS_LIMIT, guest_cs_limit), | |
835 | FIELD(GUEST_SS_LIMIT, guest_ss_limit), | |
836 | FIELD(GUEST_DS_LIMIT, guest_ds_limit), | |
837 | FIELD(GUEST_FS_LIMIT, guest_fs_limit), | |
838 | FIELD(GUEST_GS_LIMIT, guest_gs_limit), | |
839 | FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit), | |
840 | FIELD(GUEST_TR_LIMIT, guest_tr_limit), | |
841 | FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit), | |
842 | FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit), | |
843 | FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes), | |
844 | FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes), | |
845 | FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes), | |
846 | FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes), | |
847 | FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes), | |
848 | FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes), | |
849 | FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes), | |
850 | FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes), | |
851 | FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info), | |
852 | FIELD(GUEST_ACTIVITY_STATE, guest_activity_state), | |
853 | FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs), | |
854 | FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs), | |
0238ea91 | 855 | FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value), |
22bd0358 NHE |
856 | FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask), |
857 | FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask), | |
858 | FIELD(CR0_READ_SHADOW, cr0_read_shadow), | |
859 | FIELD(CR4_READ_SHADOW, cr4_read_shadow), | |
860 | FIELD(CR3_TARGET_VALUE0, cr3_target_value0), | |
861 | FIELD(CR3_TARGET_VALUE1, cr3_target_value1), | |
862 | FIELD(CR3_TARGET_VALUE2, cr3_target_value2), | |
863 | FIELD(CR3_TARGET_VALUE3, cr3_target_value3), | |
864 | FIELD(EXIT_QUALIFICATION, exit_qualification), | |
865 | FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address), | |
866 | FIELD(GUEST_CR0, guest_cr0), | |
867 | FIELD(GUEST_CR3, guest_cr3), | |
868 | FIELD(GUEST_CR4, guest_cr4), | |
869 | FIELD(GUEST_ES_BASE, guest_es_base), | |
870 | FIELD(GUEST_CS_BASE, guest_cs_base), | |
871 | FIELD(GUEST_SS_BASE, guest_ss_base), | |
872 | FIELD(GUEST_DS_BASE, guest_ds_base), | |
873 | FIELD(GUEST_FS_BASE, guest_fs_base), | |
874 | FIELD(GUEST_GS_BASE, guest_gs_base), | |
875 | FIELD(GUEST_LDTR_BASE, guest_ldtr_base), | |
876 | FIELD(GUEST_TR_BASE, guest_tr_base), | |
877 | FIELD(GUEST_GDTR_BASE, guest_gdtr_base), | |
878 | FIELD(GUEST_IDTR_BASE, guest_idtr_base), | |
879 | FIELD(GUEST_DR7, guest_dr7), | |
880 | FIELD(GUEST_RSP, guest_rsp), | |
881 | FIELD(GUEST_RIP, guest_rip), | |
882 | FIELD(GUEST_RFLAGS, guest_rflags), | |
883 | FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions), | |
884 | FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp), | |
885 | FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip), | |
886 | FIELD(HOST_CR0, host_cr0), | |
887 | FIELD(HOST_CR3, host_cr3), | |
888 | FIELD(HOST_CR4, host_cr4), | |
889 | FIELD(HOST_FS_BASE, host_fs_base), | |
890 | FIELD(HOST_GS_BASE, host_gs_base), | |
891 | FIELD(HOST_TR_BASE, host_tr_base), | |
892 | FIELD(HOST_GDTR_BASE, host_gdtr_base), | |
893 | FIELD(HOST_IDTR_BASE, host_idtr_base), | |
894 | FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp), | |
895 | FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip), | |
896 | FIELD(HOST_RSP, host_rsp), | |
897 | FIELD(HOST_RIP, host_rip), | |
898 | }; | |
22bd0358 NHE |
899 | |
900 | static inline short vmcs_field_to_offset(unsigned long field) | |
901 | { | |
085331df DW |
902 | const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table); |
903 | unsigned short offset; | |
a2ae9df7 | 904 | |
085331df DW |
905 | BUILD_BUG_ON(size > SHRT_MAX); |
906 | if (field >= size) | |
75f139aa AH |
907 | return -ENOENT; |
908 | ||
085331df DW |
909 | field = array_index_nospec(field, size); |
910 | offset = vmcs_field_to_offset_table[field]; | |
911 | if (offset == 0) | |
a2ae9df7 | 912 | return -ENOENT; |
085331df | 913 | return offset; |
22bd0358 NHE |
914 | } |
915 | ||
a9d30f33 NHE |
916 | static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
917 | { | |
4f2777bc | 918 | return to_vmx(vcpu)->nested.cached_vmcs12; |
a9d30f33 NHE |
919 | } |
920 | ||
995f00a6 | 921 | static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu); |
bfd0a56b | 922 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu); |
995f00a6 | 923 | static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa); |
f53cd63c | 924 | static bool vmx_xsaves_supported(void); |
b246dd5d OW |
925 | static void vmx_set_segment(struct kvm_vcpu *vcpu, |
926 | struct kvm_segment *var, int seg); | |
927 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
928 | struct kvm_segment *var, int seg); | |
d99e4152 GN |
929 | static bool guest_state_valid(struct kvm_vcpu *vcpu); |
930 | static u32 vmx_segment_access_rights(struct kvm_segment *var); | |
16f5b903 | 931 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx); |
b96fb439 PB |
932 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); |
933 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); | |
934 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, | |
935 | u16 error_code); | |
904e14fb | 936 | static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu); |
75880a01 | 937 | |
6aa8b732 AK |
938 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
939 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
d462b819 NHE |
940 | /* |
941 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
942 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
943 | */ | |
944 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
6aa8b732 | 945 | |
bf9f6ac8 FW |
946 | /* |
947 | * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we | |
948 | * can find which vCPU should be waken up. | |
949 | */ | |
950 | static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); | |
951 | static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); | |
952 | ||
23611332 RK |
953 | enum { |
954 | VMX_IO_BITMAP_A, | |
955 | VMX_IO_BITMAP_B, | |
23611332 RK |
956 | VMX_VMREAD_BITMAP, |
957 | VMX_VMWRITE_BITMAP, | |
958 | VMX_BITMAP_NR | |
959 | }; | |
960 | ||
961 | static unsigned long *vmx_bitmap[VMX_BITMAP_NR]; | |
962 | ||
963 | #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A]) | |
964 | #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B]) | |
23611332 RK |
965 | #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP]) |
966 | #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP]) | |
fdef3ad1 | 967 | |
110312c8 | 968 | static bool cpu_has_load_ia32_efer; |
8bf00a52 | 969 | static bool cpu_has_load_perf_global_ctrl; |
110312c8 | 970 | |
2384d2b3 SY |
971 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
972 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
973 | ||
1c3d14fe | 974 | static struct vmcs_config { |
6aa8b732 AK |
975 | int size; |
976 | int order; | |
9ac7e3e8 | 977 | u32 basic_cap; |
6aa8b732 | 978 | u32 revision_id; |
1c3d14fe YS |
979 | u32 pin_based_exec_ctrl; |
980 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 981 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
982 | u32 vmexit_ctrl; |
983 | u32 vmentry_ctrl; | |
984 | } vmcs_config; | |
6aa8b732 | 985 | |
efff9e53 | 986 | static struct vmx_capability { |
d56f546d SY |
987 | u32 ept; |
988 | u32 vpid; | |
989 | } vmx_capability; | |
990 | ||
6aa8b732 AK |
991 | #define VMX_SEGMENT_FIELD(seg) \ |
992 | [VCPU_SREG_##seg] = { \ | |
993 | .selector = GUEST_##seg##_SELECTOR, \ | |
994 | .base = GUEST_##seg##_BASE, \ | |
995 | .limit = GUEST_##seg##_LIMIT, \ | |
996 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
997 | } | |
998 | ||
772e0318 | 999 | static const struct kvm_vmx_segment_field { |
6aa8b732 AK |
1000 | unsigned selector; |
1001 | unsigned base; | |
1002 | unsigned limit; | |
1003 | unsigned ar_bytes; | |
1004 | } kvm_vmx_segment_fields[] = { | |
1005 | VMX_SEGMENT_FIELD(CS), | |
1006 | VMX_SEGMENT_FIELD(DS), | |
1007 | VMX_SEGMENT_FIELD(ES), | |
1008 | VMX_SEGMENT_FIELD(FS), | |
1009 | VMX_SEGMENT_FIELD(GS), | |
1010 | VMX_SEGMENT_FIELD(SS), | |
1011 | VMX_SEGMENT_FIELD(TR), | |
1012 | VMX_SEGMENT_FIELD(LDTR), | |
1013 | }; | |
1014 | ||
26bb0981 AK |
1015 | static u64 host_efer; |
1016 | ||
6de4f3ad AK |
1017 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
1018 | ||
4d56c8a7 | 1019 | /* |
8c06585d | 1020 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
1021 | * away by decrementing the array size. |
1022 | */ | |
6aa8b732 | 1023 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 1024 | #ifdef CONFIG_X86_64 |
44ea2b17 | 1025 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 1026 | #endif |
8c06585d | 1027 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 1028 | }; |
6aa8b732 | 1029 | |
5bb16016 | 1030 | static inline bool is_exception_n(u32 intr_info, u8 vector) |
6aa8b732 AK |
1031 | { |
1032 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1033 | INTR_INFO_VALID_MASK)) == | |
5bb16016 JK |
1034 | (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK); |
1035 | } | |
1036 | ||
6f05485d JK |
1037 | static inline bool is_debug(u32 intr_info) |
1038 | { | |
1039 | return is_exception_n(intr_info, DB_VECTOR); | |
1040 | } | |
1041 | ||
1042 | static inline bool is_breakpoint(u32 intr_info) | |
1043 | { | |
1044 | return is_exception_n(intr_info, BP_VECTOR); | |
1045 | } | |
1046 | ||
5bb16016 JK |
1047 | static inline bool is_page_fault(u32 intr_info) |
1048 | { | |
1049 | return is_exception_n(intr_info, PF_VECTOR); | |
6aa8b732 AK |
1050 | } |
1051 | ||
31299944 | 1052 | static inline bool is_no_device(u32 intr_info) |
2ab455cc | 1053 | { |
5bb16016 | 1054 | return is_exception_n(intr_info, NM_VECTOR); |
2ab455cc AL |
1055 | } |
1056 | ||
31299944 | 1057 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 | 1058 | { |
5bb16016 | 1059 | return is_exception_n(intr_info, UD_VECTOR); |
7aa81cc0 AL |
1060 | } |
1061 | ||
31299944 | 1062 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
1063 | { |
1064 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1065 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1066 | } | |
1067 | ||
31299944 | 1068 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
1069 | { |
1070 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1071 | INTR_INFO_VALID_MASK)) == | |
1072 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
1073 | } | |
1074 | ||
31299944 | 1075 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 1076 | { |
04547156 | 1077 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
1078 | } |
1079 | ||
31299944 | 1080 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 1081 | { |
04547156 | 1082 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
1083 | } |
1084 | ||
35754c98 | 1085 | static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) |
6e5d865c | 1086 | { |
35754c98 | 1087 | return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); |
6e5d865c YS |
1088 | } |
1089 | ||
31299944 | 1090 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 1091 | { |
04547156 SY |
1092 | return vmcs_config.cpu_based_exec_ctrl & |
1093 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
1094 | } |
1095 | ||
774ead3a | 1096 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 1097 | { |
04547156 SY |
1098 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1099 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1100 | } | |
1101 | ||
8d14695f YZ |
1102 | static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) |
1103 | { | |
1104 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1105 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
1106 | } | |
1107 | ||
83d4c286 YZ |
1108 | static inline bool cpu_has_vmx_apic_register_virt(void) |
1109 | { | |
1110 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1111 | SECONDARY_EXEC_APIC_REGISTER_VIRT; | |
1112 | } | |
1113 | ||
c7c9c56c YZ |
1114 | static inline bool cpu_has_vmx_virtual_intr_delivery(void) |
1115 | { | |
1116 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1117 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; | |
1118 | } | |
1119 | ||
64672c95 YJ |
1120 | /* |
1121 | * Comment's format: document - errata name - stepping - processor name. | |
1122 | * Refer from | |
1123 | * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp | |
1124 | */ | |
1125 | static u32 vmx_preemption_cpu_tfms[] = { | |
1126 | /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ | |
1127 | 0x000206E6, | |
1128 | /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ | |
1129 | /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ | |
1130 | /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1131 | 0x00020652, | |
1132 | /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1133 | 0x00020655, | |
1134 | /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ | |
1135 | /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ | |
1136 | /* | |
1137 | * 320767.pdf - AAP86 - B1 - | |
1138 | * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile | |
1139 | */ | |
1140 | 0x000106E5, | |
1141 | /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ | |
1142 | 0x000106A0, | |
1143 | /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ | |
1144 | 0x000106A1, | |
1145 | /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ | |
1146 | 0x000106A4, | |
1147 | /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ | |
1148 | /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ | |
1149 | /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ | |
1150 | 0x000106A5, | |
1151 | }; | |
1152 | ||
1153 | static inline bool cpu_has_broken_vmx_preemption_timer(void) | |
1154 | { | |
1155 | u32 eax = cpuid_eax(0x00000001), i; | |
1156 | ||
1157 | /* Clear the reserved bits */ | |
1158 | eax &= ~(0x3U << 14 | 0xfU << 28); | |
03f6a22a | 1159 | for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) |
64672c95 YJ |
1160 | if (eax == vmx_preemption_cpu_tfms[i]) |
1161 | return true; | |
1162 | ||
1163 | return false; | |
1164 | } | |
1165 | ||
1166 | static inline bool cpu_has_vmx_preemption_timer(void) | |
1167 | { | |
64672c95 YJ |
1168 | return vmcs_config.pin_based_exec_ctrl & |
1169 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1170 | } | |
1171 | ||
01e439be YZ |
1172 | static inline bool cpu_has_vmx_posted_intr(void) |
1173 | { | |
d6a858d1 PB |
1174 | return IS_ENABLED(CONFIG_X86_LOCAL_APIC) && |
1175 | vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; | |
01e439be YZ |
1176 | } |
1177 | ||
1178 | static inline bool cpu_has_vmx_apicv(void) | |
1179 | { | |
1180 | return cpu_has_vmx_apic_register_virt() && | |
1181 | cpu_has_vmx_virtual_intr_delivery() && | |
1182 | cpu_has_vmx_posted_intr(); | |
1183 | } | |
1184 | ||
04547156 SY |
1185 | static inline bool cpu_has_vmx_flexpriority(void) |
1186 | { | |
1187 | return cpu_has_vmx_tpr_shadow() && | |
1188 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
1189 | } |
1190 | ||
e799794e MT |
1191 | static inline bool cpu_has_vmx_ept_execute_only(void) |
1192 | { | |
31299944 | 1193 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
1194 | } |
1195 | ||
e799794e MT |
1196 | static inline bool cpu_has_vmx_ept_2m_page(void) |
1197 | { | |
31299944 | 1198 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
1199 | } |
1200 | ||
878403b7 SY |
1201 | static inline bool cpu_has_vmx_ept_1g_page(void) |
1202 | { | |
31299944 | 1203 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
1204 | } |
1205 | ||
4bc9b982 SY |
1206 | static inline bool cpu_has_vmx_ept_4levels(void) |
1207 | { | |
1208 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
1209 | } | |
1210 | ||
42aa53b4 DH |
1211 | static inline bool cpu_has_vmx_ept_mt_wb(void) |
1212 | { | |
1213 | return vmx_capability.ept & VMX_EPTP_WB_BIT; | |
1214 | } | |
1215 | ||
855feb67 YZ |
1216 | static inline bool cpu_has_vmx_ept_5levels(void) |
1217 | { | |
1218 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT; | |
1219 | } | |
1220 | ||
83c3a331 XH |
1221 | static inline bool cpu_has_vmx_ept_ad_bits(void) |
1222 | { | |
1223 | return vmx_capability.ept & VMX_EPT_AD_BIT; | |
1224 | } | |
1225 | ||
31299944 | 1226 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 1227 | { |
31299944 | 1228 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
1229 | } |
1230 | ||
31299944 | 1231 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 1232 | { |
31299944 | 1233 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
1234 | } |
1235 | ||
518c8aee GJ |
1236 | static inline bool cpu_has_vmx_invvpid_single(void) |
1237 | { | |
1238 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
1239 | } | |
1240 | ||
b9d762fa GJ |
1241 | static inline bool cpu_has_vmx_invvpid_global(void) |
1242 | { | |
1243 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
1244 | } | |
1245 | ||
08d839c4 WL |
1246 | static inline bool cpu_has_vmx_invvpid(void) |
1247 | { | |
1248 | return vmx_capability.vpid & VMX_VPID_INVVPID_BIT; | |
1249 | } | |
1250 | ||
31299944 | 1251 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 1252 | { |
04547156 SY |
1253 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1254 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
1255 | } |
1256 | ||
31299944 | 1257 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
1258 | { |
1259 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1260 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
1261 | } | |
1262 | ||
31299944 | 1263 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
1264 | { |
1265 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1266 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
1267 | } | |
1268 | ||
9ac7e3e8 JD |
1269 | static inline bool cpu_has_vmx_basic_inout(void) |
1270 | { | |
1271 | return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT); | |
1272 | } | |
1273 | ||
35754c98 | 1274 | static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) |
f78e0e2e | 1275 | { |
35754c98 | 1276 | return flexpriority_enabled && lapic_in_kernel(vcpu); |
f78e0e2e SY |
1277 | } |
1278 | ||
31299944 | 1279 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 1280 | { |
04547156 SY |
1281 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1282 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
1283 | } |
1284 | ||
31299944 | 1285 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
1286 | { |
1287 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1288 | SECONDARY_EXEC_RDTSCP; | |
1289 | } | |
1290 | ||
ad756a16 MJ |
1291 | static inline bool cpu_has_vmx_invpcid(void) |
1292 | { | |
1293 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1294 | SECONDARY_EXEC_ENABLE_INVPCID; | |
1295 | } | |
1296 | ||
8a1b4392 PB |
1297 | static inline bool cpu_has_virtual_nmis(void) |
1298 | { | |
1299 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
1300 | } | |
1301 | ||
f5f48ee1 SY |
1302 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
1303 | { | |
1304 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1305 | SECONDARY_EXEC_WBINVD_EXITING; | |
1306 | } | |
1307 | ||
abc4fc58 AG |
1308 | static inline bool cpu_has_vmx_shadow_vmcs(void) |
1309 | { | |
1310 | u64 vmx_msr; | |
1311 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
1312 | /* check if the cpu supports writing r/o exit information fields */ | |
1313 | if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) | |
1314 | return false; | |
1315 | ||
1316 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1317 | SECONDARY_EXEC_SHADOW_VMCS; | |
1318 | } | |
1319 | ||
843e4330 KH |
1320 | static inline bool cpu_has_vmx_pml(void) |
1321 | { | |
1322 | return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; | |
1323 | } | |
1324 | ||
64903d61 HZ |
1325 | static inline bool cpu_has_vmx_tsc_scaling(void) |
1326 | { | |
1327 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1328 | SECONDARY_EXEC_TSC_SCALING; | |
1329 | } | |
1330 | ||
2a499e49 BD |
1331 | static inline bool cpu_has_vmx_vmfunc(void) |
1332 | { | |
1333 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1334 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
1335 | } | |
1336 | ||
04547156 SY |
1337 | static inline bool report_flexpriority(void) |
1338 | { | |
1339 | return flexpriority_enabled; | |
1340 | } | |
1341 | ||
c7c2c709 JM |
1342 | static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu) |
1343 | { | |
1344 | return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low); | |
1345 | } | |
1346 | ||
fe3ef05c NHE |
1347 | static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) |
1348 | { | |
1349 | return vmcs12->cpu_based_vm_exec_control & bit; | |
1350 | } | |
1351 | ||
1352 | static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) | |
1353 | { | |
1354 | return (vmcs12->cpu_based_vm_exec_control & | |
1355 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && | |
1356 | (vmcs12->secondary_vm_exec_control & bit); | |
1357 | } | |
1358 | ||
f4124500 JK |
1359 | static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) |
1360 | { | |
1361 | return vmcs12->pin_based_vm_exec_control & | |
1362 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1363 | } | |
1364 | ||
155a97a3 NHE |
1365 | static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) |
1366 | { | |
1367 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); | |
1368 | } | |
1369 | ||
81dc01f7 WL |
1370 | static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) |
1371 | { | |
3db13480 | 1372 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); |
81dc01f7 WL |
1373 | } |
1374 | ||
c5f983f6 BD |
1375 | static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12) |
1376 | { | |
1377 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML); | |
1378 | } | |
1379 | ||
f2b93280 WV |
1380 | static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) |
1381 | { | |
1382 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); | |
1383 | } | |
1384 | ||
5c614b35 WL |
1385 | static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) |
1386 | { | |
1387 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); | |
1388 | } | |
1389 | ||
82f0dd4b WV |
1390 | static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) |
1391 | { | |
1392 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); | |
1393 | } | |
1394 | ||
608406e2 WV |
1395 | static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) |
1396 | { | |
1397 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
1398 | } | |
1399 | ||
705699a1 WV |
1400 | static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) |
1401 | { | |
1402 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; | |
1403 | } | |
1404 | ||
27c42a1b BD |
1405 | static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12) |
1406 | { | |
1407 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC); | |
1408 | } | |
1409 | ||
41ab9372 BD |
1410 | static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12) |
1411 | { | |
1412 | return nested_cpu_has_vmfunc(vmcs12) && | |
1413 | (vmcs12->vm_function_control & | |
1414 | VMX_VMFUNC_EPTP_SWITCHING); | |
1415 | } | |
1416 | ||
ef85b673 | 1417 | static inline bool is_nmi(u32 intr_info) |
644d711a NHE |
1418 | { |
1419 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
ef85b673 | 1420 | == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK); |
644d711a NHE |
1421 | } |
1422 | ||
533558bc JK |
1423 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
1424 | u32 exit_intr_info, | |
1425 | unsigned long exit_qualification); | |
7c177938 NHE |
1426 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, |
1427 | struct vmcs12 *vmcs12, | |
1428 | u32 reason, unsigned long qualification); | |
1429 | ||
8b9cf98c | 1430 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
1431 | { |
1432 | int i; | |
1433 | ||
a2fa3e9f | 1434 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 1435 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
1436 | return i; |
1437 | return -1; | |
1438 | } | |
1439 | ||
2384d2b3 SY |
1440 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
1441 | { | |
1442 | struct { | |
1443 | u64 vpid : 16; | |
1444 | u64 rsvd : 48; | |
1445 | u64 gva; | |
1446 | } operand = { vpid, 0, gva }; | |
1447 | ||
4ecac3fd | 1448 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
1449 | /* CF==1 or ZF==1 --> rc = -1 */ |
1450 | "; ja 1f ; ud2 ; 1:" | |
1451 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
1452 | } | |
1453 | ||
1439442c SY |
1454 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
1455 | { | |
1456 | struct { | |
1457 | u64 eptp, gpa; | |
1458 | } operand = {eptp, gpa}; | |
1459 | ||
4ecac3fd | 1460 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
1461 | /* CF==1 or ZF==1 --> rc = -1 */ |
1462 | "; ja 1f ; ud2 ; 1:\n" | |
1463 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
1464 | } | |
1465 | ||
26bb0981 | 1466 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
1467 | { |
1468 | int i; | |
1469 | ||
8b9cf98c | 1470 | i = __find_msr_index(vmx, msr); |
a75beee6 | 1471 | if (i >= 0) |
a2fa3e9f | 1472 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 1473 | return NULL; |
7725f0ba AK |
1474 | } |
1475 | ||
6aa8b732 AK |
1476 | static void vmcs_clear(struct vmcs *vmcs) |
1477 | { | |
1478 | u64 phys_addr = __pa(vmcs); | |
1479 | u8 error; | |
1480 | ||
4ecac3fd | 1481 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 1482 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
1483 | : "cc", "memory"); |
1484 | if (error) | |
1485 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
1486 | vmcs, phys_addr); | |
1487 | } | |
1488 | ||
d462b819 NHE |
1489 | static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
1490 | { | |
1491 | vmcs_clear(loaded_vmcs->vmcs); | |
355f4fb1 JM |
1492 | if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) |
1493 | vmcs_clear(loaded_vmcs->shadow_vmcs); | |
d462b819 NHE |
1494 | loaded_vmcs->cpu = -1; |
1495 | loaded_vmcs->launched = 0; | |
1496 | } | |
1497 | ||
7725b894 DX |
1498 | static void vmcs_load(struct vmcs *vmcs) |
1499 | { | |
1500 | u64 phys_addr = __pa(vmcs); | |
1501 | u8 error; | |
1502 | ||
1503 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
16d8f72f | 1504 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
1505 | : "cc", "memory"); |
1506 | if (error) | |
2844d849 | 1507 | printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n", |
7725b894 DX |
1508 | vmcs, phys_addr); |
1509 | } | |
1510 | ||
2965faa5 | 1511 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
1512 | /* |
1513 | * This bitmap is used to indicate whether the vmclear | |
1514 | * operation is enabled on all cpus. All disabled by | |
1515 | * default. | |
1516 | */ | |
1517 | static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; | |
1518 | ||
1519 | static inline void crash_enable_local_vmclear(int cpu) | |
1520 | { | |
1521 | cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1522 | } | |
1523 | ||
1524 | static inline void crash_disable_local_vmclear(int cpu) | |
1525 | { | |
1526 | cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1527 | } | |
1528 | ||
1529 | static inline int crash_local_vmclear_enabled(int cpu) | |
1530 | { | |
1531 | return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1532 | } | |
1533 | ||
1534 | static void crash_vmclear_local_loaded_vmcss(void) | |
1535 | { | |
1536 | int cpu = raw_smp_processor_id(); | |
1537 | struct loaded_vmcs *v; | |
1538 | ||
1539 | if (!crash_local_vmclear_enabled(cpu)) | |
1540 | return; | |
1541 | ||
1542 | list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), | |
1543 | loaded_vmcss_on_cpu_link) | |
1544 | vmcs_clear(v->vmcs); | |
1545 | } | |
1546 | #else | |
1547 | static inline void crash_enable_local_vmclear(int cpu) { } | |
1548 | static inline void crash_disable_local_vmclear(int cpu) { } | |
2965faa5 | 1549 | #endif /* CONFIG_KEXEC_CORE */ |
8f536b76 | 1550 | |
d462b819 | 1551 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 1552 | { |
d462b819 | 1553 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 1554 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 1555 | |
d462b819 NHE |
1556 | if (loaded_vmcs->cpu != cpu) |
1557 | return; /* vcpu migration can race with cpu offline */ | |
1558 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 1559 | per_cpu(current_vmcs, cpu) = NULL; |
8f536b76 | 1560 | crash_disable_local_vmclear(cpu); |
d462b819 | 1561 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
5a560f8b XG |
1562 | |
1563 | /* | |
1564 | * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link | |
1565 | * is before setting loaded_vmcs->vcpu to -1 which is done in | |
1566 | * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist | |
1567 | * then adds the vmcs into percpu list before it is deleted. | |
1568 | */ | |
1569 | smp_wmb(); | |
1570 | ||
d462b819 | 1571 | loaded_vmcs_init(loaded_vmcs); |
8f536b76 | 1572 | crash_enable_local_vmclear(cpu); |
6aa8b732 AK |
1573 | } |
1574 | ||
d462b819 | 1575 | static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 1576 | { |
e6c7d321 XG |
1577 | int cpu = loaded_vmcs->cpu; |
1578 | ||
1579 | if (cpu != -1) | |
1580 | smp_call_function_single(cpu, | |
1581 | __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
1582 | } |
1583 | ||
dd5f5341 | 1584 | static inline void vpid_sync_vcpu_single(int vpid) |
2384d2b3 | 1585 | { |
dd5f5341 | 1586 | if (vpid == 0) |
2384d2b3 SY |
1587 | return; |
1588 | ||
518c8aee | 1589 | if (cpu_has_vmx_invvpid_single()) |
dd5f5341 | 1590 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0); |
2384d2b3 SY |
1591 | } |
1592 | ||
b9d762fa GJ |
1593 | static inline void vpid_sync_vcpu_global(void) |
1594 | { | |
1595 | if (cpu_has_vmx_invvpid_global()) | |
1596 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
1597 | } | |
1598 | ||
dd5f5341 | 1599 | static inline void vpid_sync_context(int vpid) |
b9d762fa GJ |
1600 | { |
1601 | if (cpu_has_vmx_invvpid_single()) | |
dd5f5341 | 1602 | vpid_sync_vcpu_single(vpid); |
b9d762fa GJ |
1603 | else |
1604 | vpid_sync_vcpu_global(); | |
1605 | } | |
1606 | ||
1439442c SY |
1607 | static inline void ept_sync_global(void) |
1608 | { | |
f5f51586 | 1609 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); |
1439442c SY |
1610 | } |
1611 | ||
1612 | static inline void ept_sync_context(u64 eptp) | |
1613 | { | |
0e1252dc DH |
1614 | if (cpu_has_vmx_invept_context()) |
1615 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
1616 | else | |
1617 | ept_sync_global(); | |
1439442c SY |
1618 | } |
1619 | ||
8a86aea9 PB |
1620 | static __always_inline void vmcs_check16(unsigned long field) |
1621 | { | |
1622 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1623 | "16-bit accessor invalid for 64-bit field"); | |
1624 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1625 | "16-bit accessor invalid for 64-bit high field"); | |
1626 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1627 | "16-bit accessor invalid for 32-bit high field"); | |
1628 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1629 | "16-bit accessor invalid for natural width field"); | |
1630 | } | |
1631 | ||
1632 | static __always_inline void vmcs_check32(unsigned long field) | |
1633 | { | |
1634 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1635 | "32-bit accessor invalid for 16-bit field"); | |
1636 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1637 | "32-bit accessor invalid for natural width field"); | |
1638 | } | |
1639 | ||
1640 | static __always_inline void vmcs_check64(unsigned long field) | |
1641 | { | |
1642 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1643 | "64-bit accessor invalid for 16-bit field"); | |
1644 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1645 | "64-bit accessor invalid for 64-bit high field"); | |
1646 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1647 | "64-bit accessor invalid for 32-bit field"); | |
1648 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1649 | "64-bit accessor invalid for natural width field"); | |
1650 | } | |
1651 | ||
1652 | static __always_inline void vmcs_checkl(unsigned long field) | |
1653 | { | |
1654 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1655 | "Natural width accessor invalid for 16-bit field"); | |
1656 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1657 | "Natural width accessor invalid for 64-bit field"); | |
1658 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1659 | "Natural width accessor invalid for 64-bit high field"); | |
1660 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1661 | "Natural width accessor invalid for 32-bit field"); | |
1662 | } | |
1663 | ||
1664 | static __always_inline unsigned long __vmcs_readl(unsigned long field) | |
6aa8b732 | 1665 | { |
5e520e62 | 1666 | unsigned long value; |
6aa8b732 | 1667 | |
5e520e62 AK |
1668 | asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
1669 | : "=a"(value) : "d"(field) : "cc"); | |
6aa8b732 AK |
1670 | return value; |
1671 | } | |
1672 | ||
96304217 | 1673 | static __always_inline u16 vmcs_read16(unsigned long field) |
6aa8b732 | 1674 | { |
8a86aea9 PB |
1675 | vmcs_check16(field); |
1676 | return __vmcs_readl(field); | |
6aa8b732 AK |
1677 | } |
1678 | ||
96304217 | 1679 | static __always_inline u32 vmcs_read32(unsigned long field) |
6aa8b732 | 1680 | { |
8a86aea9 PB |
1681 | vmcs_check32(field); |
1682 | return __vmcs_readl(field); | |
6aa8b732 AK |
1683 | } |
1684 | ||
96304217 | 1685 | static __always_inline u64 vmcs_read64(unsigned long field) |
6aa8b732 | 1686 | { |
8a86aea9 | 1687 | vmcs_check64(field); |
05b3e0c2 | 1688 | #ifdef CONFIG_X86_64 |
8a86aea9 | 1689 | return __vmcs_readl(field); |
6aa8b732 | 1690 | #else |
8a86aea9 | 1691 | return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32); |
6aa8b732 AK |
1692 | #endif |
1693 | } | |
1694 | ||
8a86aea9 PB |
1695 | static __always_inline unsigned long vmcs_readl(unsigned long field) |
1696 | { | |
1697 | vmcs_checkl(field); | |
1698 | return __vmcs_readl(field); | |
1699 | } | |
1700 | ||
e52de1b8 AK |
1701 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
1702 | { | |
1703 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
1704 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1705 | dump_stack(); | |
1706 | } | |
1707 | ||
8a86aea9 | 1708 | static __always_inline void __vmcs_writel(unsigned long field, unsigned long value) |
6aa8b732 AK |
1709 | { |
1710 | u8 error; | |
1711 | ||
4ecac3fd | 1712 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 1713 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
1714 | if (unlikely(error)) |
1715 | vmwrite_error(field, value); | |
6aa8b732 AK |
1716 | } |
1717 | ||
8a86aea9 | 1718 | static __always_inline void vmcs_write16(unsigned long field, u16 value) |
6aa8b732 | 1719 | { |
8a86aea9 PB |
1720 | vmcs_check16(field); |
1721 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1722 | } |
1723 | ||
8a86aea9 | 1724 | static __always_inline void vmcs_write32(unsigned long field, u32 value) |
6aa8b732 | 1725 | { |
8a86aea9 PB |
1726 | vmcs_check32(field); |
1727 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1728 | } |
1729 | ||
8a86aea9 | 1730 | static __always_inline void vmcs_write64(unsigned long field, u64 value) |
6aa8b732 | 1731 | { |
8a86aea9 PB |
1732 | vmcs_check64(field); |
1733 | __vmcs_writel(field, value); | |
7682f2d0 | 1734 | #ifndef CONFIG_X86_64 |
6aa8b732 | 1735 | asm volatile (""); |
8a86aea9 | 1736 | __vmcs_writel(field+1, value >> 32); |
6aa8b732 AK |
1737 | #endif |
1738 | } | |
1739 | ||
8a86aea9 | 1740 | static __always_inline void vmcs_writel(unsigned long field, unsigned long value) |
2ab455cc | 1741 | { |
8a86aea9 PB |
1742 | vmcs_checkl(field); |
1743 | __vmcs_writel(field, value); | |
2ab455cc AL |
1744 | } |
1745 | ||
8a86aea9 | 1746 | static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask) |
2ab455cc | 1747 | { |
8a86aea9 PB |
1748 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1749 | "vmcs_clear_bits does not support 64-bit fields"); | |
1750 | __vmcs_writel(field, __vmcs_readl(field) & ~mask); | |
2ab455cc AL |
1751 | } |
1752 | ||
8a86aea9 | 1753 | static __always_inline void vmcs_set_bits(unsigned long field, u32 mask) |
2ab455cc | 1754 | { |
8a86aea9 PB |
1755 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1756 | "vmcs_set_bits does not support 64-bit fields"); | |
1757 | __vmcs_writel(field, __vmcs_readl(field) | mask); | |
2ab455cc AL |
1758 | } |
1759 | ||
8391ce44 PB |
1760 | static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx) |
1761 | { | |
1762 | vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS); | |
1763 | } | |
1764 | ||
2961e876 GN |
1765 | static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val) |
1766 | { | |
1767 | vmcs_write32(VM_ENTRY_CONTROLS, val); | |
1768 | vmx->vm_entry_controls_shadow = val; | |
1769 | } | |
1770 | ||
1771 | static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1772 | { | |
1773 | if (vmx->vm_entry_controls_shadow != val) | |
1774 | vm_entry_controls_init(vmx, val); | |
1775 | } | |
1776 | ||
1777 | static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx) | |
1778 | { | |
1779 | return vmx->vm_entry_controls_shadow; | |
1780 | } | |
1781 | ||
1782 | ||
1783 | static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1784 | { | |
1785 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val); | |
1786 | } | |
1787 | ||
1788 | static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1789 | { | |
1790 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val); | |
1791 | } | |
1792 | ||
8391ce44 PB |
1793 | static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx) |
1794 | { | |
1795 | vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS); | |
1796 | } | |
1797 | ||
2961e876 GN |
1798 | static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val) |
1799 | { | |
1800 | vmcs_write32(VM_EXIT_CONTROLS, val); | |
1801 | vmx->vm_exit_controls_shadow = val; | |
1802 | } | |
1803 | ||
1804 | static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1805 | { | |
1806 | if (vmx->vm_exit_controls_shadow != val) | |
1807 | vm_exit_controls_init(vmx, val); | |
1808 | } | |
1809 | ||
1810 | static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx) | |
1811 | { | |
1812 | return vmx->vm_exit_controls_shadow; | |
1813 | } | |
1814 | ||
1815 | ||
1816 | static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1817 | { | |
1818 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val); | |
1819 | } | |
1820 | ||
1821 | static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1822 | { | |
1823 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val); | |
1824 | } | |
1825 | ||
2fb92db1 AK |
1826 | static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
1827 | { | |
1828 | vmx->segment_cache.bitmask = 0; | |
1829 | } | |
1830 | ||
1831 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, | |
1832 | unsigned field) | |
1833 | { | |
1834 | bool ret; | |
1835 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
1836 | ||
1837 | if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { | |
1838 | vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); | |
1839 | vmx->segment_cache.bitmask = 0; | |
1840 | } | |
1841 | ret = vmx->segment_cache.bitmask & mask; | |
1842 | vmx->segment_cache.bitmask |= mask; | |
1843 | return ret; | |
1844 | } | |
1845 | ||
1846 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
1847 | { | |
1848 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
1849 | ||
1850 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
1851 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
1852 | return *p; | |
1853 | } | |
1854 | ||
1855 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
1856 | { | |
1857 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
1858 | ||
1859 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
1860 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
1861 | return *p; | |
1862 | } | |
1863 | ||
1864 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
1865 | { | |
1866 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
1867 | ||
1868 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
1869 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
1870 | return *p; | |
1871 | } | |
1872 | ||
1873 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
1874 | { | |
1875 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
1876 | ||
1877 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
1878 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
1879 | return *p; | |
1880 | } | |
1881 | ||
abd3f2d6 AK |
1882 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
1883 | { | |
1884 | u32 eb; | |
1885 | ||
fd7373cc | 1886 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
bd7e5b08 | 1887 | (1u << DB_VECTOR) | (1u << AC_VECTOR); |
fd7373cc JK |
1888 | if ((vcpu->guest_debug & |
1889 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
1890 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
1891 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 1892 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 1893 | eb = ~0; |
089d034e | 1894 | if (enable_ept) |
1439442c | 1895 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
36cf24e0 NHE |
1896 | |
1897 | /* When we are running a nested L2 guest and L1 specified for it a | |
1898 | * certain exception bitmap, we must trap the same exceptions and pass | |
1899 | * them to L1. When running L2, we will only handle the exceptions | |
1900 | * specified above if L1 did not want them. | |
1901 | */ | |
1902 | if (is_guest_mode(vcpu)) | |
1903 | eb |= get_vmcs12(vcpu)->exception_bitmap; | |
1904 | ||
abd3f2d6 AK |
1905 | vmcs_write32(EXCEPTION_BITMAP, eb); |
1906 | } | |
1907 | ||
2961e876 GN |
1908 | static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1909 | unsigned long entry, unsigned long exit) | |
8bf00a52 | 1910 | { |
2961e876 GN |
1911 | vm_entry_controls_clearbit(vmx, entry); |
1912 | vm_exit_controls_clearbit(vmx, exit); | |
8bf00a52 GN |
1913 | } |
1914 | ||
61d2ef2c AK |
1915 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
1916 | { | |
1917 | unsigned i; | |
1918 | struct msr_autoload *m = &vmx->msr_autoload; | |
1919 | ||
8bf00a52 GN |
1920 | switch (msr) { |
1921 | case MSR_EFER: | |
1922 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1923 | clear_atomic_switch_msr_special(vmx, |
1924 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1925 | VM_EXIT_LOAD_IA32_EFER); |
1926 | return; | |
1927 | } | |
1928 | break; | |
1929 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1930 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1931 | clear_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1932 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1933 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
1934 | return; | |
1935 | } | |
1936 | break; | |
110312c8 AK |
1937 | } |
1938 | ||
61d2ef2c AK |
1939 | for (i = 0; i < m->nr; ++i) |
1940 | if (m->guest[i].index == msr) | |
1941 | break; | |
1942 | ||
1943 | if (i == m->nr) | |
1944 | return; | |
1945 | --m->nr; | |
1946 | m->guest[i] = m->guest[m->nr]; | |
1947 | m->host[i] = m->host[m->nr]; | |
1948 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1949 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1950 | } | |
1951 | ||
2961e876 GN |
1952 | static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1953 | unsigned long entry, unsigned long exit, | |
1954 | unsigned long guest_val_vmcs, unsigned long host_val_vmcs, | |
1955 | u64 guest_val, u64 host_val) | |
8bf00a52 GN |
1956 | { |
1957 | vmcs_write64(guest_val_vmcs, guest_val); | |
1958 | vmcs_write64(host_val_vmcs, host_val); | |
2961e876 GN |
1959 | vm_entry_controls_setbit(vmx, entry); |
1960 | vm_exit_controls_setbit(vmx, exit); | |
8bf00a52 GN |
1961 | } |
1962 | ||
61d2ef2c AK |
1963 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
1964 | u64 guest_val, u64 host_val) | |
1965 | { | |
1966 | unsigned i; | |
1967 | struct msr_autoload *m = &vmx->msr_autoload; | |
1968 | ||
8bf00a52 GN |
1969 | switch (msr) { |
1970 | case MSR_EFER: | |
1971 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1972 | add_atomic_switch_msr_special(vmx, |
1973 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1974 | VM_EXIT_LOAD_IA32_EFER, |
1975 | GUEST_IA32_EFER, | |
1976 | HOST_IA32_EFER, | |
1977 | guest_val, host_val); | |
1978 | return; | |
1979 | } | |
1980 | break; | |
1981 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1982 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1983 | add_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1984 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1985 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, | |
1986 | GUEST_IA32_PERF_GLOBAL_CTRL, | |
1987 | HOST_IA32_PERF_GLOBAL_CTRL, | |
1988 | guest_val, host_val); | |
1989 | return; | |
1990 | } | |
1991 | break; | |
7099e2e1 RK |
1992 | case MSR_IA32_PEBS_ENABLE: |
1993 | /* PEBS needs a quiescent period after being disabled (to write | |
1994 | * a record). Disabling PEBS through VMX MSR swapping doesn't | |
1995 | * provide that period, so a CPU could write host's record into | |
1996 | * guest's memory. | |
1997 | */ | |
1998 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
110312c8 AK |
1999 | } |
2000 | ||
61d2ef2c AK |
2001 | for (i = 0; i < m->nr; ++i) |
2002 | if (m->guest[i].index == msr) | |
2003 | break; | |
2004 | ||
e7fc6f93 | 2005 | if (i == NR_AUTOLOAD_MSRS) { |
60266204 | 2006 | printk_once(KERN_WARNING "Not enough msr switch entries. " |
e7fc6f93 GN |
2007 | "Can't add msr %x\n", msr); |
2008 | return; | |
2009 | } else if (i == m->nr) { | |
61d2ef2c AK |
2010 | ++m->nr; |
2011 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
2012 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
2013 | } | |
2014 | ||
2015 | m->guest[i].index = msr; | |
2016 | m->guest[i].value = guest_val; | |
2017 | m->host[i].index = msr; | |
2018 | m->host[i].value = host_val; | |
2019 | } | |
2020 | ||
92c0d900 | 2021 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 2022 | { |
844a5fe2 PB |
2023 | u64 guest_efer = vmx->vcpu.arch.efer; |
2024 | u64 ignore_bits = 0; | |
2025 | ||
2026 | if (!enable_ept) { | |
2027 | /* | |
2028 | * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing | |
2029 | * host CPUID is more efficient than testing guest CPUID | |
2030 | * or CR4. Host SMEP is anyway a requirement for guest SMEP. | |
2031 | */ | |
2032 | if (boot_cpu_has(X86_FEATURE_SMEP)) | |
2033 | guest_efer |= EFER_NX; | |
2034 | else if (!(guest_efer & EFER_NX)) | |
2035 | ignore_bits |= EFER_NX; | |
2036 | } | |
3a34a881 | 2037 | |
51c6cf66 | 2038 | /* |
844a5fe2 | 2039 | * LMA and LME handled by hardware; SCE meaningless outside long mode. |
51c6cf66 | 2040 | */ |
844a5fe2 | 2041 | ignore_bits |= EFER_SCE; |
51c6cf66 AK |
2042 | #ifdef CONFIG_X86_64 |
2043 | ignore_bits |= EFER_LMA | EFER_LME; | |
2044 | /* SCE is meaningful only in long mode on Intel */ | |
2045 | if (guest_efer & EFER_LMA) | |
2046 | ignore_bits &= ~(u64)EFER_SCE; | |
2047 | #endif | |
84ad33ef AK |
2048 | |
2049 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
f6577a5f AL |
2050 | |
2051 | /* | |
2052 | * On EPT, we can't emulate NX, so we must switch EFER atomically. | |
2053 | * On CPUs that support "load IA32_EFER", always switch EFER | |
2054 | * atomically, since it's faster than switching it manually. | |
2055 | */ | |
2056 | if (cpu_has_load_ia32_efer || | |
2057 | (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { | |
84ad33ef AK |
2058 | if (!(guest_efer & EFER_LMA)) |
2059 | guest_efer &= ~EFER_LME; | |
54b98bff AL |
2060 | if (guest_efer != host_efer) |
2061 | add_atomic_switch_msr(vmx, MSR_EFER, | |
2062 | guest_efer, host_efer); | |
84ad33ef | 2063 | return false; |
844a5fe2 PB |
2064 | } else { |
2065 | guest_efer &= ~ignore_bits; | |
2066 | guest_efer |= host_efer & ignore_bits; | |
2067 | ||
2068 | vmx->guest_msrs[efer_offset].data = guest_efer; | |
2069 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; | |
84ad33ef | 2070 | |
844a5fe2 PB |
2071 | return true; |
2072 | } | |
51c6cf66 AK |
2073 | } |
2074 | ||
e28baead AL |
2075 | #ifdef CONFIG_X86_32 |
2076 | /* | |
2077 | * On 32-bit kernels, VM exits still load the FS and GS bases from the | |
2078 | * VMCS rather than the segment table. KVM uses this helper to figure | |
2079 | * out the current bases to poke them into the VMCS before entry. | |
2080 | */ | |
2d49ec72 GN |
2081 | static unsigned long segment_base(u16 selector) |
2082 | { | |
8c2e41f7 | 2083 | struct desc_struct *table; |
2d49ec72 GN |
2084 | unsigned long v; |
2085 | ||
8c2e41f7 | 2086 | if (!(selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
2087 | return 0; |
2088 | ||
45fc8757 | 2089 | table = get_current_gdt_ro(); |
2d49ec72 | 2090 | |
8c2e41f7 | 2091 | if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { |
2d49ec72 GN |
2092 | u16 ldt_selector = kvm_read_ldt(); |
2093 | ||
8c2e41f7 | 2094 | if (!(ldt_selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
2095 | return 0; |
2096 | ||
8c2e41f7 | 2097 | table = (struct desc_struct *)segment_base(ldt_selector); |
2d49ec72 | 2098 | } |
8c2e41f7 | 2099 | v = get_desc_base(&table[selector >> 3]); |
2d49ec72 GN |
2100 | return v; |
2101 | } | |
e28baead | 2102 | #endif |
2d49ec72 | 2103 | |
04d2cc77 | 2104 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 2105 | { |
04d2cc77 | 2106 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 2107 | int i; |
04d2cc77 | 2108 | |
a2fa3e9f | 2109 | if (vmx->host_state.loaded) |
33ed6329 AK |
2110 | return; |
2111 | ||
a2fa3e9f | 2112 | vmx->host_state.loaded = 1; |
33ed6329 AK |
2113 | /* |
2114 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
2115 | * allow segment selectors with cpl > 0 or ti == 1. | |
2116 | */ | |
d6e88aec | 2117 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 2118 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 2119 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 2120 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 2121 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
2122 | vmx->host_state.fs_reload_needed = 0; |
2123 | } else { | |
33ed6329 | 2124 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 2125 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 2126 | } |
9581d442 | 2127 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
2128 | if (!(vmx->host_state.gs_sel & 7)) |
2129 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
2130 | else { |
2131 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 2132 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
2133 | } |
2134 | ||
b2da15ac AK |
2135 | #ifdef CONFIG_X86_64 |
2136 | savesegment(ds, vmx->host_state.ds_sel); | |
2137 | savesegment(es, vmx->host_state.es_sel); | |
2138 | #endif | |
2139 | ||
33ed6329 AK |
2140 | #ifdef CONFIG_X86_64 |
2141 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
2142 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
2143 | #else | |
a2fa3e9f GH |
2144 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
2145 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 2146 | #endif |
707c0874 AK |
2147 | |
2148 | #ifdef CONFIG_X86_64 | |
c8770e7b AK |
2149 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
2150 | if (is_long_mode(&vmx->vcpu)) | |
44ea2b17 | 2151 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
707c0874 | 2152 | #endif |
da8999d3 LJ |
2153 | if (boot_cpu_has(X86_FEATURE_MPX)) |
2154 | rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
26bb0981 AK |
2155 | for (i = 0; i < vmx->save_nmsrs; ++i) |
2156 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
2157 | vmx->guest_msrs[i].data, |
2158 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
2159 | } |
2160 | ||
a9b21b62 | 2161 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 2162 | { |
a2fa3e9f | 2163 | if (!vmx->host_state.loaded) |
33ed6329 AK |
2164 | return; |
2165 | ||
e1beb1d3 | 2166 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 2167 | vmx->host_state.loaded = 0; |
c8770e7b AK |
2168 | #ifdef CONFIG_X86_64 |
2169 | if (is_long_mode(&vmx->vcpu)) | |
2170 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
2171 | #endif | |
152d3f2f | 2172 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 2173 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 2174 | #ifdef CONFIG_X86_64 |
9581d442 | 2175 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
2176 | #else |
2177 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 2178 | #endif |
33ed6329 | 2179 | } |
0a77fe4c AK |
2180 | if (vmx->host_state.fs_reload_needed) |
2181 | loadsegment(fs, vmx->host_state.fs_sel); | |
b2da15ac AK |
2182 | #ifdef CONFIG_X86_64 |
2183 | if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) { | |
2184 | loadsegment(ds, vmx->host_state.ds_sel); | |
2185 | loadsegment(es, vmx->host_state.es_sel); | |
2186 | } | |
b2da15ac | 2187 | #endif |
b7ffc44d | 2188 | invalidate_tss_limit(); |
44ea2b17 | 2189 | #ifdef CONFIG_X86_64 |
c8770e7b | 2190 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 2191 | #endif |
da8999d3 LJ |
2192 | if (vmx->host_state.msr_host_bndcfgs) |
2193 | wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
45fc8757 | 2194 | load_fixmap_gdt(raw_smp_processor_id()); |
33ed6329 AK |
2195 | } |
2196 | ||
a9b21b62 AK |
2197 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
2198 | { | |
2199 | preempt_disable(); | |
2200 | __vmx_load_host_state(vmx); | |
2201 | preempt_enable(); | |
2202 | } | |
2203 | ||
28b835d6 FW |
2204 | static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) |
2205 | { | |
2206 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2207 | struct pi_desc old, new; | |
2208 | unsigned int dest; | |
2209 | ||
31afb2ea PB |
2210 | /* |
2211 | * In case of hot-plug or hot-unplug, we may have to undo | |
2212 | * vmx_vcpu_pi_put even if there is no assigned device. And we | |
2213 | * always keep PI.NDST up to date for simplicity: it makes the | |
2214 | * code easier, and CPU migration is not a fast path. | |
2215 | */ | |
2216 | if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) | |
28b835d6 FW |
2217 | return; |
2218 | ||
31afb2ea PB |
2219 | /* |
2220 | * First handle the simple case where no cmpxchg is necessary; just | |
2221 | * allow posting non-urgent interrupts. | |
2222 | * | |
2223 | * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change | |
2224 | * PI.NDST: pi_post_block will do it for us and the wakeup_handler | |
2225 | * expects the VCPU to be on the blocked_vcpu_list that matches | |
2226 | * PI.NDST. | |
2227 | */ | |
2228 | if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || | |
2229 | vcpu->cpu == cpu) { | |
2230 | pi_clear_sn(pi_desc); | |
28b835d6 | 2231 | return; |
31afb2ea | 2232 | } |
28b835d6 | 2233 | |
31afb2ea | 2234 | /* The full case. */ |
28b835d6 FW |
2235 | do { |
2236 | old.control = new.control = pi_desc->control; | |
2237 | ||
31afb2ea | 2238 | dest = cpu_physical_id(cpu); |
28b835d6 | 2239 | |
31afb2ea PB |
2240 | if (x2apic_enabled()) |
2241 | new.ndst = dest; | |
2242 | else | |
2243 | new.ndst = (dest << 8) & 0xFF00; | |
28b835d6 | 2244 | |
28b835d6 | 2245 | new.sn = 0; |
c0a1666b PB |
2246 | } while (cmpxchg64(&pi_desc->control, old.control, |
2247 | new.control) != old.control); | |
28b835d6 | 2248 | } |
1be0e61c | 2249 | |
c95ba92a PF |
2250 | static void decache_tsc_multiplier(struct vcpu_vmx *vmx) |
2251 | { | |
2252 | vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio; | |
2253 | vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); | |
2254 | } | |
2255 | ||
6aa8b732 AK |
2256 | /* |
2257 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
2258 | * vcpu mutex is already taken. | |
2259 | */ | |
15ad7146 | 2260 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 2261 | { |
a2fa3e9f | 2262 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b80c76ec | 2263 | bool already_loaded = vmx->loaded_vmcs->cpu == cpu; |
6aa8b732 | 2264 | |
b80c76ec | 2265 | if (!already_loaded) { |
fe0e80be | 2266 | loaded_vmcs_clear(vmx->loaded_vmcs); |
92fe13be | 2267 | local_irq_disable(); |
8f536b76 | 2268 | crash_disable_local_vmclear(cpu); |
5a560f8b XG |
2269 | |
2270 | /* | |
2271 | * Read loaded_vmcs->cpu should be before fetching | |
2272 | * loaded_vmcs->loaded_vmcss_on_cpu_link. | |
2273 | * See the comments in __loaded_vmcs_clear(). | |
2274 | */ | |
2275 | smp_rmb(); | |
2276 | ||
d462b819 NHE |
2277 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
2278 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
8f536b76 | 2279 | crash_enable_local_vmclear(cpu); |
92fe13be | 2280 | local_irq_enable(); |
b80c76ec JM |
2281 | } |
2282 | ||
2283 | if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { | |
2284 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; | |
2285 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
2286 | } | |
2287 | ||
2288 | if (!already_loaded) { | |
59c58ceb | 2289 | void *gdt = get_current_gdt_ro(); |
b80c76ec JM |
2290 | unsigned long sysenter_esp; |
2291 | ||
2292 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
92fe13be | 2293 | |
6aa8b732 AK |
2294 | /* |
2295 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
e0c23063 | 2296 | * processors. See 22.2.4. |
6aa8b732 | 2297 | */ |
e0c23063 | 2298 | vmcs_writel(HOST_TR_BASE, |
72f5e08d | 2299 | (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); |
59c58ceb | 2300 | vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ |
6aa8b732 | 2301 | |
b7ffc44d AL |
2302 | /* |
2303 | * VM exits change the host TR limit to 0x67 after a VM | |
2304 | * exit. This is okay, since 0x67 covers everything except | |
2305 | * the IO bitmap and have have code to handle the IO bitmap | |
2306 | * being lost after a VM exit. | |
2307 | */ | |
2308 | BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67); | |
2309 | ||
6aa8b732 AK |
2310 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); |
2311 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
ff2c3a18 | 2312 | |
d462b819 | 2313 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 2314 | } |
28b835d6 | 2315 | |
2680d6da OH |
2316 | /* Setup TSC multiplier */ |
2317 | if (kvm_has_tsc_control && | |
c95ba92a PF |
2318 | vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) |
2319 | decache_tsc_multiplier(vmx); | |
2680d6da | 2320 | |
28b835d6 | 2321 | vmx_vcpu_pi_load(vcpu, cpu); |
1be0e61c | 2322 | vmx->host_pkru = read_pkru(); |
28b835d6 FW |
2323 | } |
2324 | ||
2325 | static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) | |
2326 | { | |
2327 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2328 | ||
2329 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
2330 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
2331 | !kvm_vcpu_apicv_active(vcpu)) | |
28b835d6 FW |
2332 | return; |
2333 | ||
2334 | /* Set SN when the vCPU is preempted */ | |
2335 | if (vcpu->preempted) | |
2336 | pi_set_sn(pi_desc); | |
6aa8b732 AK |
2337 | } |
2338 | ||
2339 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
2340 | { | |
28b835d6 FW |
2341 | vmx_vcpu_pi_put(vcpu); |
2342 | ||
a9b21b62 | 2343 | __vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
2344 | } |
2345 | ||
f244deed WL |
2346 | static bool emulation_required(struct kvm_vcpu *vcpu) |
2347 | { | |
2348 | return emulate_invalid_guest_state && !guest_state_valid(vcpu); | |
2349 | } | |
2350 | ||
edcafe3c AK |
2351 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
2352 | ||
fe3ef05c NHE |
2353 | /* |
2354 | * Return the cr0 value that a nested guest would read. This is a combination | |
2355 | * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by | |
2356 | * its hypervisor (cr0_read_shadow). | |
2357 | */ | |
2358 | static inline unsigned long nested_read_cr0(struct vmcs12 *fields) | |
2359 | { | |
2360 | return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | | |
2361 | (fields->cr0_read_shadow & fields->cr0_guest_host_mask); | |
2362 | } | |
2363 | static inline unsigned long nested_read_cr4(struct vmcs12 *fields) | |
2364 | { | |
2365 | return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | | |
2366 | (fields->cr4_read_shadow & fields->cr4_guest_host_mask); | |
2367 | } | |
2368 | ||
6aa8b732 AK |
2369 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
2370 | { | |
78ac8b47 | 2371 | unsigned long rflags, save_rflags; |
345dcaa8 | 2372 | |
6de12732 AK |
2373 | if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
2374 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); | |
2375 | rflags = vmcs_readl(GUEST_RFLAGS); | |
2376 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
2377 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2378 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
2379 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2380 | } | |
2381 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 | 2382 | } |
6de12732 | 2383 | return to_vmx(vcpu)->rflags; |
6aa8b732 AK |
2384 | } |
2385 | ||
2386 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
2387 | { | |
f244deed WL |
2388 | unsigned long old_rflags = vmx_get_rflags(vcpu); |
2389 | ||
6de12732 AK |
2390 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
2391 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 AK |
2392 | if (to_vmx(vcpu)->rmode.vm86_active) { |
2393 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 2394 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 2395 | } |
6aa8b732 | 2396 | vmcs_writel(GUEST_RFLAGS, rflags); |
f244deed WL |
2397 | |
2398 | if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM) | |
2399 | to_vmx(vcpu)->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
2400 | } |
2401 | ||
37ccdcbe | 2402 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
2403 | { |
2404 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2405 | int ret = 0; | |
2406 | ||
2407 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 2408 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 2409 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 2410 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 | 2411 | |
37ccdcbe | 2412 | return ret; |
2809f5d2 GC |
2413 | } |
2414 | ||
2415 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
2416 | { | |
2417 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2418 | u32 interruptibility = interruptibility_old; | |
2419 | ||
2420 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
2421 | ||
48005f64 | 2422 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 2423 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 2424 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
2425 | interruptibility |= GUEST_INTR_STATE_STI; |
2426 | ||
2427 | if ((interruptibility != interruptibility_old)) | |
2428 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
2429 | } | |
2430 | ||
6aa8b732 AK |
2431 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
2432 | { | |
2433 | unsigned long rip; | |
6aa8b732 | 2434 | |
5fdbf976 | 2435 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 2436 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 2437 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 2438 | |
2809f5d2 GC |
2439 | /* skipping an emulated instruction also counts */ |
2440 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
2441 | } |
2442 | ||
b96fb439 PB |
2443 | static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu, |
2444 | unsigned long exit_qual) | |
2445 | { | |
2446 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2447 | unsigned int nr = vcpu->arch.exception.nr; | |
2448 | u32 intr_info = nr | INTR_INFO_VALID_MASK; | |
2449 | ||
2450 | if (vcpu->arch.exception.has_error_code) { | |
2451 | vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code; | |
2452 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; | |
2453 | } | |
2454 | ||
2455 | if (kvm_exception_is_soft(nr)) | |
2456 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; | |
2457 | else | |
2458 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2459 | ||
2460 | if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) && | |
2461 | vmx_get_nmi_mask(vcpu)) | |
2462 | intr_info |= INTR_INFO_UNBLOCK_NMI; | |
2463 | ||
2464 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual); | |
2465 | } | |
2466 | ||
0b6ac343 NHE |
2467 | /* |
2468 | * KVM wants to inject page-faults which it got to the guest. This function | |
2469 | * checks whether in a nested guest, we need to inject them to L1 or L2. | |
0b6ac343 | 2470 | */ |
bfcf83b1 | 2471 | static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual) |
0b6ac343 NHE |
2472 | { |
2473 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
adfe20fb | 2474 | unsigned int nr = vcpu->arch.exception.nr; |
0b6ac343 | 2475 | |
b96fb439 PB |
2476 | if (nr == PF_VECTOR) { |
2477 | if (vcpu->arch.exception.nested_apf) { | |
bfcf83b1 | 2478 | *exit_qual = vcpu->arch.apf.nested_apf_token; |
b96fb439 PB |
2479 | return 1; |
2480 | } | |
2481 | /* | |
2482 | * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception. | |
2483 | * The fix is to add the ancillary datum (CR2 or DR6) to structs | |
2484 | * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 | |
2485 | * can be written only when inject_pending_event runs. This should be | |
2486 | * conditional on a new capability---if the capability is disabled, | |
2487 | * kvm_multiple_exception would write the ancillary information to | |
2488 | * CR2 or DR6, for backwards ABI-compatibility. | |
2489 | */ | |
2490 | if (nested_vmx_is_page_fault_vmexit(vmcs12, | |
2491 | vcpu->arch.exception.error_code)) { | |
bfcf83b1 | 2492 | *exit_qual = vcpu->arch.cr2; |
b96fb439 PB |
2493 | return 1; |
2494 | } | |
2495 | } else { | |
b96fb439 | 2496 | if (vmcs12->exception_bitmap & (1u << nr)) { |
bfcf83b1 WL |
2497 | if (nr == DB_VECTOR) |
2498 | *exit_qual = vcpu->arch.dr6; | |
2499 | else | |
2500 | *exit_qual = 0; | |
b96fb439 PB |
2501 | return 1; |
2502 | } | |
adfe20fb WL |
2503 | } |
2504 | ||
b96fb439 | 2505 | return 0; |
0b6ac343 NHE |
2506 | } |
2507 | ||
cfcd20e5 | 2508 | static void vmx_queue_exception(struct kvm_vcpu *vcpu) |
298101da | 2509 | { |
77ab6db0 | 2510 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
cfcd20e5 WL |
2511 | unsigned nr = vcpu->arch.exception.nr; |
2512 | bool has_error_code = vcpu->arch.exception.has_error_code; | |
cfcd20e5 | 2513 | u32 error_code = vcpu->arch.exception.error_code; |
8ab2d2e2 | 2514 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 2515 | |
8ab2d2e2 | 2516 | if (has_error_code) { |
77ab6db0 | 2517 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
2518 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
2519 | } | |
77ab6db0 | 2520 | |
7ffd92c5 | 2521 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
2522 | int inc_eip = 0; |
2523 | if (kvm_exception_is_soft(nr)) | |
2524 | inc_eip = vcpu->arch.event_exit_inst_len; | |
2525 | if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) | |
a92601bb | 2526 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
77ab6db0 JK |
2527 | return; |
2528 | } | |
2529 | ||
66fd3f7f GN |
2530 | if (kvm_exception_is_soft(nr)) { |
2531 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2532 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
2533 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
2534 | } else | |
2535 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2536 | ||
2537 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
298101da AK |
2538 | } |
2539 | ||
4e47c7a6 SY |
2540 | static bool vmx_rdtscp_supported(void) |
2541 | { | |
2542 | return cpu_has_vmx_rdtscp(); | |
2543 | } | |
2544 | ||
ad756a16 MJ |
2545 | static bool vmx_invpcid_supported(void) |
2546 | { | |
2547 | return cpu_has_vmx_invpcid() && enable_ept; | |
2548 | } | |
2549 | ||
a75beee6 ED |
2550 | /* |
2551 | * Swap MSR entry in host/guest MSR entry array. | |
2552 | */ | |
8b9cf98c | 2553 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 2554 | { |
26bb0981 | 2555 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
2556 | |
2557 | tmp = vmx->guest_msrs[to]; | |
2558 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
2559 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
2560 | } |
2561 | ||
e38aea3e AK |
2562 | /* |
2563 | * Set up the vmcs to automatically save and restore system | |
2564 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
2565 | * mode, as fiddling with msrs is very expensive. | |
2566 | */ | |
8b9cf98c | 2567 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 2568 | { |
26bb0981 | 2569 | int save_nmsrs, index; |
e38aea3e | 2570 | |
a75beee6 ED |
2571 | save_nmsrs = 0; |
2572 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 2573 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 2574 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 2575 | if (index >= 0) |
8b9cf98c RR |
2576 | move_msr_up(vmx, index, save_nmsrs++); |
2577 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 2578 | if (index >= 0) |
8b9cf98c RR |
2579 | move_msr_up(vmx, index, save_nmsrs++); |
2580 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 2581 | if (index >= 0) |
8b9cf98c | 2582 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 | 2583 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
d6321d49 | 2584 | if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) |
4e47c7a6 | 2585 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 | 2586 | /* |
8c06585d | 2587 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
2588 | * if efer.sce is enabled. |
2589 | */ | |
8c06585d | 2590 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 2591 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 2592 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
2593 | } |
2594 | #endif | |
92c0d900 AK |
2595 | index = __find_msr_index(vmx, MSR_EFER); |
2596 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 2597 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 2598 | |
26bb0981 | 2599 | vmx->save_nmsrs = save_nmsrs; |
5897297b | 2600 | |
8d14695f | 2601 | if (cpu_has_vmx_msr_bitmap()) |
904e14fb | 2602 | vmx_update_msr_bitmap(&vmx->vcpu); |
e38aea3e AK |
2603 | } |
2604 | ||
6aa8b732 AK |
2605 | /* |
2606 | * reads and returns guest's timestamp counter "register" | |
be7b263e HZ |
2607 | * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset |
2608 | * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3 | |
6aa8b732 | 2609 | */ |
be7b263e | 2610 | static u64 guest_read_tsc(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
2611 | { |
2612 | u64 host_tsc, tsc_offset; | |
2613 | ||
4ea1636b | 2614 | host_tsc = rdtsc(); |
6aa8b732 | 2615 | tsc_offset = vmcs_read64(TSC_OFFSET); |
be7b263e | 2616 | return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset; |
6aa8b732 AK |
2617 | } |
2618 | ||
2619 | /* | |
99e3e30a | 2620 | * writes 'offset' into guest's timestamp counter offset register |
6aa8b732 | 2621 | */ |
99e3e30a | 2622 | static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 2623 | { |
27fc51b2 | 2624 | if (is_guest_mode(vcpu)) { |
7991825b | 2625 | /* |
27fc51b2 NHE |
2626 | * We're here if L1 chose not to trap WRMSR to TSC. According |
2627 | * to the spec, this should set L1's TSC; The offset that L1 | |
2628 | * set for L2 remains unchanged, and still needs to be added | |
2629 | * to the newly set TSC to get L2's TSC. | |
7991825b | 2630 | */ |
27fc51b2 | 2631 | struct vmcs12 *vmcs12; |
27fc51b2 NHE |
2632 | /* recalculate vmcs02.TSC_OFFSET: */ |
2633 | vmcs12 = get_vmcs12(vcpu); | |
2634 | vmcs_write64(TSC_OFFSET, offset + | |
2635 | (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ? | |
2636 | vmcs12->tsc_offset : 0)); | |
2637 | } else { | |
489223ed YY |
2638 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2639 | vmcs_read64(TSC_OFFSET), offset); | |
27fc51b2 NHE |
2640 | vmcs_write64(TSC_OFFSET, offset); |
2641 | } | |
6aa8b732 AK |
2642 | } |
2643 | ||
801d3424 NHE |
2644 | /* |
2645 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
2646 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
2647 | * all guests if the "nested" module option is off, and can also be disabled | |
2648 | * for a single guest by disabling its VMX cpuid bit. | |
2649 | */ | |
2650 | static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) | |
2651 | { | |
d6321d49 | 2652 | return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); |
801d3424 NHE |
2653 | } |
2654 | ||
b87a51ae NHE |
2655 | /* |
2656 | * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be | |
2657 | * returned for the various VMX controls MSRs when nested VMX is enabled. | |
2658 | * The same values should also be used to verify that vmcs12 control fields are | |
2659 | * valid during nested entry from L1 to L2. | |
2660 | * Each of these control msrs has a low and high 32-bit half: A low bit is on | |
2661 | * if the corresponding bit in the (32-bit) control field *must* be on, and a | |
2662 | * bit in the high half is on if the corresponding bit in the control field | |
2663 | * may be on. See also vmx_control_verify(). | |
b87a51ae | 2664 | */ |
b9c237bb | 2665 | static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx) |
b87a51ae NHE |
2666 | { |
2667 | /* | |
2668 | * Note that as a general rule, the high half of the MSRs (bits in | |
2669 | * the control fields which may be 1) should be initialized by the | |
2670 | * intersection of the underlying hardware's MSR (i.e., features which | |
2671 | * can be supported) and the list of features we want to expose - | |
2672 | * because they are known to be properly supported in our code. | |
2673 | * Also, usually, the low half of the MSRs (bits which must be 1) can | |
2674 | * be set to 0, meaning that L1 may turn off any of these bits. The | |
2675 | * reason is that if one of these bits is necessary, it will appear | |
2676 | * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control | |
2677 | * fields of vmcs01 and vmcs02, will turn these bits off - and | |
7313c698 | 2678 | * nested_vmx_exit_reflected() will not pass related exits to L1. |
b87a51ae NHE |
2679 | * These rules have exceptions below. |
2680 | */ | |
2681 | ||
2682 | /* pin-based controls */ | |
eabeaacc | 2683 | rdmsr(MSR_IA32_VMX_PINBASED_CTLS, |
b9c237bb WV |
2684 | vmx->nested.nested_vmx_pinbased_ctls_low, |
2685 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
2686 | vmx->nested.nested_vmx_pinbased_ctls_low |= | |
2687 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2688 | vmx->nested.nested_vmx_pinbased_ctls_high &= | |
2689 | PIN_BASED_EXT_INTR_MASK | | |
2690 | PIN_BASED_NMI_EXITING | | |
2691 | PIN_BASED_VIRTUAL_NMIS; | |
2692 | vmx->nested.nested_vmx_pinbased_ctls_high |= | |
2693 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
0238ea91 | 2694 | PIN_BASED_VMX_PREEMPTION_TIMER; |
d62caabb | 2695 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) |
705699a1 WV |
2696 | vmx->nested.nested_vmx_pinbased_ctls_high |= |
2697 | PIN_BASED_POSTED_INTR; | |
b87a51ae | 2698 | |
3dbcd8da | 2699 | /* exit controls */ |
c0dfee58 | 2700 | rdmsr(MSR_IA32_VMX_EXIT_CTLS, |
b9c237bb WV |
2701 | vmx->nested.nested_vmx_exit_ctls_low, |
2702 | vmx->nested.nested_vmx_exit_ctls_high); | |
2703 | vmx->nested.nested_vmx_exit_ctls_low = | |
2704 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
e0ba1a6f | 2705 | |
b9c237bb | 2706 | vmx->nested.nested_vmx_exit_ctls_high &= |
b87a51ae | 2707 | #ifdef CONFIG_X86_64 |
c0dfee58 | 2708 | VM_EXIT_HOST_ADDR_SPACE_SIZE | |
b87a51ae | 2709 | #endif |
f4124500 | 2710 | VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT; |
b9c237bb WV |
2711 | vmx->nested.nested_vmx_exit_ctls_high |= |
2712 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | | |
f4124500 | 2713 | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | |
e0ba1a6f BD |
2714 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; |
2715 | ||
a87036ad | 2716 | if (kvm_mpx_supported()) |
b9c237bb | 2717 | vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; |
b87a51ae | 2718 | |
2996fca0 | 2719 | /* We support free control of debug control saving. */ |
0115f9cb | 2720 | vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS; |
2996fca0 | 2721 | |
b87a51ae NHE |
2722 | /* entry controls */ |
2723 | rdmsr(MSR_IA32_VMX_ENTRY_CTLS, | |
b9c237bb WV |
2724 | vmx->nested.nested_vmx_entry_ctls_low, |
2725 | vmx->nested.nested_vmx_entry_ctls_high); | |
2726 | vmx->nested.nested_vmx_entry_ctls_low = | |
2727 | VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
2728 | vmx->nested.nested_vmx_entry_ctls_high &= | |
57435349 JK |
2729 | #ifdef CONFIG_X86_64 |
2730 | VM_ENTRY_IA32E_MODE | | |
2731 | #endif | |
2732 | VM_ENTRY_LOAD_IA32_PAT; | |
b9c237bb WV |
2733 | vmx->nested.nested_vmx_entry_ctls_high |= |
2734 | (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER); | |
a87036ad | 2735 | if (kvm_mpx_supported()) |
b9c237bb | 2736 | vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; |
57435349 | 2737 | |
2996fca0 | 2738 | /* We support free control of debug control loading. */ |
0115f9cb | 2739 | vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS; |
2996fca0 | 2740 | |
b87a51ae NHE |
2741 | /* cpu-based controls */ |
2742 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, | |
b9c237bb WV |
2743 | vmx->nested.nested_vmx_procbased_ctls_low, |
2744 | vmx->nested.nested_vmx_procbased_ctls_high); | |
2745 | vmx->nested.nested_vmx_procbased_ctls_low = | |
2746 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2747 | vmx->nested.nested_vmx_procbased_ctls_high &= | |
a294c9bb JK |
2748 | CPU_BASED_VIRTUAL_INTR_PENDING | |
2749 | CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING | | |
b87a51ae NHE |
2750 | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | |
2751 | CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | | |
2752 | CPU_BASED_CR3_STORE_EXITING | | |
2753 | #ifdef CONFIG_X86_64 | |
2754 | CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | | |
2755 | #endif | |
2756 | CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | | |
5f3d45e7 MD |
2757 | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG | |
2758 | CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING | | |
2759 | CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING | | |
2760 | CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
b87a51ae NHE |
2761 | /* |
2762 | * We can allow some features even when not supported by the | |
2763 | * hardware. For example, L1 can specify an MSR bitmap - and we | |
2764 | * can use it to avoid exits to L1 - even when L0 runs L2 | |
2765 | * without MSR bitmaps. | |
2766 | */ | |
b9c237bb WV |
2767 | vmx->nested.nested_vmx_procbased_ctls_high |= |
2768 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
560b7ee1 | 2769 | CPU_BASED_USE_MSR_BITMAPS; |
b87a51ae | 2770 | |
3dcdf3ec | 2771 | /* We support free control of CR3 access interception. */ |
0115f9cb | 2772 | vmx->nested.nested_vmx_procbased_ctls_low &= |
3dcdf3ec JK |
2773 | ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); |
2774 | ||
80154d77 PB |
2775 | /* |
2776 | * secondary cpu-based controls. Do not include those that | |
2777 | * depend on CPUID bits, they are added later by vmx_cpuid_update. | |
2778 | */ | |
b87a51ae | 2779 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, |
b9c237bb WV |
2780 | vmx->nested.nested_vmx_secondary_ctls_low, |
2781 | vmx->nested.nested_vmx_secondary_ctls_high); | |
2782 | vmx->nested.nested_vmx_secondary_ctls_low = 0; | |
2783 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
d6851fbe | 2784 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
1b07304c | 2785 | SECONDARY_EXEC_DESC | |
f2b93280 | 2786 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
82f0dd4b | 2787 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
608406e2 | 2788 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
3db13480 | 2789 | SECONDARY_EXEC_WBINVD_EXITING; |
c18911a2 | 2790 | |
afa61f75 NHE |
2791 | if (enable_ept) { |
2792 | /* nested EPT: emulate EPT also to L1 */ | |
b9c237bb | 2793 | vmx->nested.nested_vmx_secondary_ctls_high |= |
0790ec17 | 2794 | SECONDARY_EXEC_ENABLE_EPT; |
b9c237bb | 2795 | vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT | |
7db74265 | 2796 | VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT; |
02120c45 BD |
2797 | if (cpu_has_vmx_ept_execute_only()) |
2798 | vmx->nested.nested_vmx_ept_caps |= | |
2799 | VMX_EPT_EXECUTE_ONLY_BIT; | |
b9c237bb | 2800 | vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept; |
45e11817 | 2801 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT | |
7db74265 PB |
2802 | VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT | |
2803 | VMX_EPT_1GB_PAGE_BIT; | |
03efce6f BD |
2804 | if (enable_ept_ad_bits) { |
2805 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2806 | SECONDARY_EXEC_ENABLE_PML; | |
7461fbc4 | 2807 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT; |
03efce6f | 2808 | } |
1c13bffd | 2809 | } |
afa61f75 | 2810 | |
27c42a1b BD |
2811 | if (cpu_has_vmx_vmfunc()) { |
2812 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2813 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
41ab9372 BD |
2814 | /* |
2815 | * Advertise EPTP switching unconditionally | |
2816 | * since we emulate it | |
2817 | */ | |
575b3a2c WL |
2818 | if (enable_ept) |
2819 | vmx->nested.nested_vmx_vmfunc_controls = | |
2820 | VMX_VMFUNC_EPTP_SWITCHING; | |
27c42a1b BD |
2821 | } |
2822 | ||
ef697a71 PB |
2823 | /* |
2824 | * Old versions of KVM use the single-context version without | |
2825 | * checking for support, so declare that it is supported even | |
2826 | * though it is treated as global context. The alternative is | |
2827 | * not failing the single-context invvpid, and it is worse. | |
2828 | */ | |
63cb6d5f WL |
2829 | if (enable_vpid) { |
2830 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2831 | SECONDARY_EXEC_ENABLE_VPID; | |
089d7b6e | 2832 | vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT | |
bcdde302 | 2833 | VMX_VPID_EXTENT_SUPPORTED_MASK; |
1c13bffd | 2834 | } |
99b83ac8 | 2835 | |
0790ec17 RK |
2836 | if (enable_unrestricted_guest) |
2837 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2838 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
2839 | ||
c18911a2 | 2840 | /* miscellaneous data */ |
b9c237bb WV |
2841 | rdmsr(MSR_IA32_VMX_MISC, |
2842 | vmx->nested.nested_vmx_misc_low, | |
2843 | vmx->nested.nested_vmx_misc_high); | |
2844 | vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA; | |
2845 | vmx->nested.nested_vmx_misc_low |= | |
2846 | VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | | |
f4124500 | 2847 | VMX_MISC_ACTIVITY_HLT; |
b9c237bb | 2848 | vmx->nested.nested_vmx_misc_high = 0; |
62cc6b9d DM |
2849 | |
2850 | /* | |
2851 | * This MSR reports some information about VMX support. We | |
2852 | * should return information about the VMX we emulate for the | |
2853 | * guest, and the VMCS structure we give it - not about the | |
2854 | * VMX support of the underlying hardware. | |
2855 | */ | |
2856 | vmx->nested.nested_vmx_basic = | |
2857 | VMCS12_REVISION | | |
2858 | VMX_BASIC_TRUE_CTLS | | |
2859 | ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | | |
2860 | (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); | |
2861 | ||
2862 | if (cpu_has_vmx_basic_inout()) | |
2863 | vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT; | |
2864 | ||
2865 | /* | |
8322ebbb | 2866 | * These MSRs specify bits which the guest must keep fixed on |
62cc6b9d DM |
2867 | * while L1 is in VMXON mode (in L1's root mode, or running an L2). |
2868 | * We picked the standard core2 setting. | |
2869 | */ | |
2870 | #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) | |
2871 | #define VMXON_CR4_ALWAYSON X86_CR4_VMXE | |
2872 | vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON; | |
62cc6b9d | 2873 | vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON; |
8322ebbb DM |
2874 | |
2875 | /* These MSRs specify bits which the guest must keep fixed off. */ | |
2876 | rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1); | |
2877 | rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1); | |
62cc6b9d DM |
2878 | |
2879 | /* highest index: VMX_PREEMPTION_TIMER_VALUE */ | |
2880 | vmx->nested.nested_vmx_vmcs_enum = 0x2e; | |
b87a51ae NHE |
2881 | } |
2882 | ||
3899152c DM |
2883 | /* |
2884 | * if fixed0[i] == 1: val[i] must be 1 | |
2885 | * if fixed1[i] == 0: val[i] must be 0 | |
2886 | */ | |
2887 | static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1) | |
2888 | { | |
2889 | return ((val & fixed1) | fixed0) == val; | |
b87a51ae NHE |
2890 | } |
2891 | ||
2892 | static inline bool vmx_control_verify(u32 control, u32 low, u32 high) | |
2893 | { | |
3899152c | 2894 | return fixed_bits_valid(control, low, high); |
b87a51ae NHE |
2895 | } |
2896 | ||
2897 | static inline u64 vmx_control_msr(u32 low, u32 high) | |
2898 | { | |
2899 | return low | ((u64)high << 32); | |
2900 | } | |
2901 | ||
62cc6b9d DM |
2902 | static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask) |
2903 | { | |
2904 | superset &= mask; | |
2905 | subset &= mask; | |
2906 | ||
2907 | return (superset | subset) == superset; | |
2908 | } | |
2909 | ||
2910 | static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data) | |
2911 | { | |
2912 | const u64 feature_and_reserved = | |
2913 | /* feature (except bit 48; see below) */ | |
2914 | BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) | | |
2915 | /* reserved */ | |
2916 | BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56); | |
2917 | u64 vmx_basic = vmx->nested.nested_vmx_basic; | |
2918 | ||
2919 | if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved)) | |
2920 | return -EINVAL; | |
2921 | ||
2922 | /* | |
2923 | * KVM does not emulate a version of VMX that constrains physical | |
2924 | * addresses of VMX structures (e.g. VMCS) to 32-bits. | |
2925 | */ | |
2926 | if (data & BIT_ULL(48)) | |
2927 | return -EINVAL; | |
2928 | ||
2929 | if (vmx_basic_vmcs_revision_id(vmx_basic) != | |
2930 | vmx_basic_vmcs_revision_id(data)) | |
2931 | return -EINVAL; | |
2932 | ||
2933 | if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data)) | |
2934 | return -EINVAL; | |
2935 | ||
2936 | vmx->nested.nested_vmx_basic = data; | |
2937 | return 0; | |
2938 | } | |
2939 | ||
2940 | static int | |
2941 | vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
2942 | { | |
2943 | u64 supported; | |
2944 | u32 *lowp, *highp; | |
2945 | ||
2946 | switch (msr_index) { | |
2947 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
2948 | lowp = &vmx->nested.nested_vmx_pinbased_ctls_low; | |
2949 | highp = &vmx->nested.nested_vmx_pinbased_ctls_high; | |
2950 | break; | |
2951 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
2952 | lowp = &vmx->nested.nested_vmx_procbased_ctls_low; | |
2953 | highp = &vmx->nested.nested_vmx_procbased_ctls_high; | |
2954 | break; | |
2955 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
2956 | lowp = &vmx->nested.nested_vmx_exit_ctls_low; | |
2957 | highp = &vmx->nested.nested_vmx_exit_ctls_high; | |
2958 | break; | |
2959 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
2960 | lowp = &vmx->nested.nested_vmx_entry_ctls_low; | |
2961 | highp = &vmx->nested.nested_vmx_entry_ctls_high; | |
2962 | break; | |
2963 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
2964 | lowp = &vmx->nested.nested_vmx_secondary_ctls_low; | |
2965 | highp = &vmx->nested.nested_vmx_secondary_ctls_high; | |
2966 | break; | |
2967 | default: | |
2968 | BUG(); | |
2969 | } | |
2970 | ||
2971 | supported = vmx_control_msr(*lowp, *highp); | |
2972 | ||
2973 | /* Check must-be-1 bits are still 1. */ | |
2974 | if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0))) | |
2975 | return -EINVAL; | |
2976 | ||
2977 | /* Check must-be-0 bits are still 0. */ | |
2978 | if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32))) | |
2979 | return -EINVAL; | |
2980 | ||
2981 | *lowp = data; | |
2982 | *highp = data >> 32; | |
2983 | return 0; | |
2984 | } | |
2985 | ||
2986 | static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data) | |
2987 | { | |
2988 | const u64 feature_and_reserved_bits = | |
2989 | /* feature */ | |
2990 | BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) | | |
2991 | BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) | | |
2992 | /* reserved */ | |
2993 | GENMASK_ULL(13, 9) | BIT_ULL(31); | |
2994 | u64 vmx_misc; | |
2995 | ||
2996 | vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low, | |
2997 | vmx->nested.nested_vmx_misc_high); | |
2998 | ||
2999 | if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits)) | |
3000 | return -EINVAL; | |
3001 | ||
3002 | if ((vmx->nested.nested_vmx_pinbased_ctls_high & | |
3003 | PIN_BASED_VMX_PREEMPTION_TIMER) && | |
3004 | vmx_misc_preemption_timer_rate(data) != | |
3005 | vmx_misc_preemption_timer_rate(vmx_misc)) | |
3006 | return -EINVAL; | |
3007 | ||
3008 | if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc)) | |
3009 | return -EINVAL; | |
3010 | ||
3011 | if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc)) | |
3012 | return -EINVAL; | |
3013 | ||
3014 | if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc)) | |
3015 | return -EINVAL; | |
3016 | ||
3017 | vmx->nested.nested_vmx_misc_low = data; | |
3018 | vmx->nested.nested_vmx_misc_high = data >> 32; | |
3019 | return 0; | |
3020 | } | |
3021 | ||
3022 | static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data) | |
3023 | { | |
3024 | u64 vmx_ept_vpid_cap; | |
3025 | ||
3026 | vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps, | |
3027 | vmx->nested.nested_vmx_vpid_caps); | |
3028 | ||
3029 | /* Every bit is either reserved or a feature bit. */ | |
3030 | if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL)) | |
3031 | return -EINVAL; | |
3032 | ||
3033 | vmx->nested.nested_vmx_ept_caps = data; | |
3034 | vmx->nested.nested_vmx_vpid_caps = data >> 32; | |
3035 | return 0; | |
3036 | } | |
3037 | ||
3038 | static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
3039 | { | |
3040 | u64 *msr; | |
3041 | ||
3042 | switch (msr_index) { | |
3043 | case MSR_IA32_VMX_CR0_FIXED0: | |
3044 | msr = &vmx->nested.nested_vmx_cr0_fixed0; | |
3045 | break; | |
3046 | case MSR_IA32_VMX_CR4_FIXED0: | |
3047 | msr = &vmx->nested.nested_vmx_cr4_fixed0; | |
3048 | break; | |
3049 | default: | |
3050 | BUG(); | |
3051 | } | |
3052 | ||
3053 | /* | |
3054 | * 1 bits (which indicates bits which "must-be-1" during VMX operation) | |
3055 | * must be 1 in the restored value. | |
3056 | */ | |
3057 | if (!is_bitwise_subset(data, *msr, -1ULL)) | |
3058 | return -EINVAL; | |
3059 | ||
3060 | *msr = data; | |
3061 | return 0; | |
3062 | } | |
3063 | ||
3064 | /* | |
3065 | * Called when userspace is restoring VMX MSRs. | |
3066 | * | |
3067 | * Returns 0 on success, non-0 otherwise. | |
3068 | */ | |
3069 | static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
b87a51ae | 3070 | { |
b9c237bb WV |
3071 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3072 | ||
b87a51ae | 3073 | switch (msr_index) { |
b87a51ae | 3074 | case MSR_IA32_VMX_BASIC: |
62cc6b9d DM |
3075 | return vmx_restore_vmx_basic(vmx, data); |
3076 | case MSR_IA32_VMX_PINBASED_CTLS: | |
3077 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
3078 | case MSR_IA32_VMX_EXIT_CTLS: | |
3079 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b87a51ae | 3080 | /* |
62cc6b9d DM |
3081 | * The "non-true" VMX capability MSRs are generated from the |
3082 | * "true" MSRs, so we do not support restoring them directly. | |
3083 | * | |
3084 | * If userspace wants to emulate VMX_BASIC[55]=0, userspace | |
3085 | * should restore the "true" MSRs with the must-be-1 bits | |
3086 | * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND | |
3087 | * DEFAULT SETTINGS". | |
b87a51ae | 3088 | */ |
62cc6b9d DM |
3089 | return -EINVAL; |
3090 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3091 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3092 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3093 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3094 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
3095 | return vmx_restore_control_msr(vmx, msr_index, data); | |
3096 | case MSR_IA32_VMX_MISC: | |
3097 | return vmx_restore_vmx_misc(vmx, data); | |
3098 | case MSR_IA32_VMX_CR0_FIXED0: | |
3099 | case MSR_IA32_VMX_CR4_FIXED0: | |
3100 | return vmx_restore_fixed0_msr(vmx, msr_index, data); | |
3101 | case MSR_IA32_VMX_CR0_FIXED1: | |
3102 | case MSR_IA32_VMX_CR4_FIXED1: | |
3103 | /* | |
3104 | * These MSRs are generated based on the vCPU's CPUID, so we | |
3105 | * do not support restoring them directly. | |
3106 | */ | |
3107 | return -EINVAL; | |
3108 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
3109 | return vmx_restore_vmx_ept_vpid_cap(vmx, data); | |
3110 | case MSR_IA32_VMX_VMCS_ENUM: | |
3111 | vmx->nested.nested_vmx_vmcs_enum = data; | |
3112 | return 0; | |
3113 | default: | |
b87a51ae | 3114 | /* |
62cc6b9d | 3115 | * The rest of the VMX capability MSRs do not support restore. |
b87a51ae | 3116 | */ |
62cc6b9d DM |
3117 | return -EINVAL; |
3118 | } | |
3119 | } | |
3120 | ||
3121 | /* Returns 0 on success, non-0 otherwise. */ | |
3122 | static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
3123 | { | |
3124 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3125 | ||
3126 | switch (msr_index) { | |
3127 | case MSR_IA32_VMX_BASIC: | |
3128 | *pdata = vmx->nested.nested_vmx_basic; | |
b87a51ae NHE |
3129 | break; |
3130 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3131 | case MSR_IA32_VMX_PINBASED_CTLS: | |
b9c237bb WV |
3132 | *pdata = vmx_control_msr( |
3133 | vmx->nested.nested_vmx_pinbased_ctls_low, | |
3134 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
0115f9cb DM |
3135 | if (msr_index == MSR_IA32_VMX_PINBASED_CTLS) |
3136 | *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3137 | break; |
3138 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3139 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
b9c237bb WV |
3140 | *pdata = vmx_control_msr( |
3141 | vmx->nested.nested_vmx_procbased_ctls_low, | |
3142 | vmx->nested.nested_vmx_procbased_ctls_high); | |
0115f9cb DM |
3143 | if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS) |
3144 | *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3145 | break; |
3146 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3147 | case MSR_IA32_VMX_EXIT_CTLS: | |
b9c237bb WV |
3148 | *pdata = vmx_control_msr( |
3149 | vmx->nested.nested_vmx_exit_ctls_low, | |
3150 | vmx->nested.nested_vmx_exit_ctls_high); | |
0115f9cb DM |
3151 | if (msr_index == MSR_IA32_VMX_EXIT_CTLS) |
3152 | *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3153 | break; |
3154 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3155 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b9c237bb WV |
3156 | *pdata = vmx_control_msr( |
3157 | vmx->nested.nested_vmx_entry_ctls_low, | |
3158 | vmx->nested.nested_vmx_entry_ctls_high); | |
0115f9cb DM |
3159 | if (msr_index == MSR_IA32_VMX_ENTRY_CTLS) |
3160 | *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3161 | break; |
3162 | case MSR_IA32_VMX_MISC: | |
b9c237bb WV |
3163 | *pdata = vmx_control_msr( |
3164 | vmx->nested.nested_vmx_misc_low, | |
3165 | vmx->nested.nested_vmx_misc_high); | |
b87a51ae | 3166 | break; |
b87a51ae | 3167 | case MSR_IA32_VMX_CR0_FIXED0: |
62cc6b9d | 3168 | *pdata = vmx->nested.nested_vmx_cr0_fixed0; |
b87a51ae NHE |
3169 | break; |
3170 | case MSR_IA32_VMX_CR0_FIXED1: | |
62cc6b9d | 3171 | *pdata = vmx->nested.nested_vmx_cr0_fixed1; |
b87a51ae NHE |
3172 | break; |
3173 | case MSR_IA32_VMX_CR4_FIXED0: | |
62cc6b9d | 3174 | *pdata = vmx->nested.nested_vmx_cr4_fixed0; |
b87a51ae NHE |
3175 | break; |
3176 | case MSR_IA32_VMX_CR4_FIXED1: | |
62cc6b9d | 3177 | *pdata = vmx->nested.nested_vmx_cr4_fixed1; |
b87a51ae NHE |
3178 | break; |
3179 | case MSR_IA32_VMX_VMCS_ENUM: | |
62cc6b9d | 3180 | *pdata = vmx->nested.nested_vmx_vmcs_enum; |
b87a51ae NHE |
3181 | break; |
3182 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
b9c237bb WV |
3183 | *pdata = vmx_control_msr( |
3184 | vmx->nested.nested_vmx_secondary_ctls_low, | |
3185 | vmx->nested.nested_vmx_secondary_ctls_high); | |
b87a51ae NHE |
3186 | break; |
3187 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
089d7b6e WL |
3188 | *pdata = vmx->nested.nested_vmx_ept_caps | |
3189 | ((u64)vmx->nested.nested_vmx_vpid_caps << 32); | |
b87a51ae | 3190 | break; |
27c42a1b BD |
3191 | case MSR_IA32_VMX_VMFUNC: |
3192 | *pdata = vmx->nested.nested_vmx_vmfunc_controls; | |
3193 | break; | |
b87a51ae | 3194 | default: |
b87a51ae | 3195 | return 1; |
b3897a49 NHE |
3196 | } |
3197 | ||
b87a51ae NHE |
3198 | return 0; |
3199 | } | |
3200 | ||
37e4c997 HZ |
3201 | static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, |
3202 | uint64_t val) | |
3203 | { | |
3204 | uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; | |
3205 | ||
3206 | return !(val & ~valid_bits); | |
3207 | } | |
3208 | ||
6aa8b732 AK |
3209 | /* |
3210 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
3211 | * Returns 0 on success, non-0 otherwise. | |
3212 | * Assumes vcpu_load() was already called. | |
3213 | */ | |
609e36d3 | 3214 | static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3215 | { |
26bb0981 | 3216 | struct shared_msr_entry *msr; |
6aa8b732 | 3217 | |
609e36d3 | 3218 | switch (msr_info->index) { |
05b3e0c2 | 3219 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3220 | case MSR_FS_BASE: |
609e36d3 | 3221 | msr_info->data = vmcs_readl(GUEST_FS_BASE); |
6aa8b732 AK |
3222 | break; |
3223 | case MSR_GS_BASE: | |
609e36d3 | 3224 | msr_info->data = vmcs_readl(GUEST_GS_BASE); |
6aa8b732 | 3225 | break; |
44ea2b17 AK |
3226 | case MSR_KERNEL_GS_BASE: |
3227 | vmx_load_host_state(to_vmx(vcpu)); | |
609e36d3 | 3228 | msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base; |
44ea2b17 | 3229 | break; |
26bb0981 | 3230 | #endif |
6aa8b732 | 3231 | case MSR_EFER: |
609e36d3 | 3232 | return kvm_get_msr_common(vcpu, msr_info); |
af24a4e4 | 3233 | case MSR_IA32_TSC: |
be7b263e | 3234 | msr_info->data = guest_read_tsc(vcpu); |
6aa8b732 AK |
3235 | break; |
3236 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 3237 | msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); |
6aa8b732 AK |
3238 | break; |
3239 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3240 | msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
3241 | break; |
3242 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3243 | msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 3244 | break; |
0dd376e7 | 3245 | case MSR_IA32_BNDCFGS: |
691bd434 | 3246 | if (!kvm_mpx_supported() || |
d6321d49 RK |
3247 | (!msr_info->host_initiated && |
3248 | !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) | |
93c4adc7 | 3249 | return 1; |
609e36d3 | 3250 | msr_info->data = vmcs_read64(GUEST_BNDCFGS); |
0dd376e7 | 3251 | break; |
c45dcc71 AR |
3252 | case MSR_IA32_MCG_EXT_CTL: |
3253 | if (!msr_info->host_initiated && | |
3254 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3255 | FEATURE_CONTROL_LMCE)) | |
cae50139 | 3256 | return 1; |
c45dcc71 AR |
3257 | msr_info->data = vcpu->arch.mcg_ext_ctl; |
3258 | break; | |
cae50139 | 3259 | case MSR_IA32_FEATURE_CONTROL: |
3b84080b | 3260 | msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control; |
cae50139 JK |
3261 | break; |
3262 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
3263 | if (!nested_vmx_allowed(vcpu)) | |
3264 | return 1; | |
609e36d3 | 3265 | return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data); |
20300099 WL |
3266 | case MSR_IA32_XSS: |
3267 | if (!vmx_xsaves_supported()) | |
3268 | return 1; | |
609e36d3 | 3269 | msr_info->data = vcpu->arch.ia32_xss; |
20300099 | 3270 | break; |
4e47c7a6 | 3271 | case MSR_TSC_AUX: |
d6321d49 RK |
3272 | if (!msr_info->host_initiated && |
3273 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) | |
4e47c7a6 SY |
3274 | return 1; |
3275 | /* Otherwise falls through */ | |
6aa8b732 | 3276 | default: |
609e36d3 | 3277 | msr = find_msr_entry(to_vmx(vcpu), msr_info->index); |
3bab1f5d | 3278 | if (msr) { |
609e36d3 | 3279 | msr_info->data = msr->data; |
3bab1f5d | 3280 | break; |
6aa8b732 | 3281 | } |
609e36d3 | 3282 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3283 | } |
3284 | ||
6aa8b732 AK |
3285 | return 0; |
3286 | } | |
3287 | ||
cae50139 JK |
3288 | static void vmx_leave_nested(struct kvm_vcpu *vcpu); |
3289 | ||
6aa8b732 AK |
3290 | /* |
3291 | * Writes msr value into into the appropriate "register". | |
3292 | * Returns 0 on success, non-0 otherwise. | |
3293 | * Assumes vcpu_load() was already called. | |
3294 | */ | |
8fe8ab46 | 3295 | static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3296 | { |
a2fa3e9f | 3297 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 3298 | struct shared_msr_entry *msr; |
2cc51560 | 3299 | int ret = 0; |
8fe8ab46 WA |
3300 | u32 msr_index = msr_info->index; |
3301 | u64 data = msr_info->data; | |
2cc51560 | 3302 | |
6aa8b732 | 3303 | switch (msr_index) { |
3bab1f5d | 3304 | case MSR_EFER: |
8fe8ab46 | 3305 | ret = kvm_set_msr_common(vcpu, msr_info); |
2cc51560 | 3306 | break; |
16175a79 | 3307 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3308 | case MSR_FS_BASE: |
2fb92db1 | 3309 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3310 | vmcs_writel(GUEST_FS_BASE, data); |
3311 | break; | |
3312 | case MSR_GS_BASE: | |
2fb92db1 | 3313 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3314 | vmcs_writel(GUEST_GS_BASE, data); |
3315 | break; | |
44ea2b17 AK |
3316 | case MSR_KERNEL_GS_BASE: |
3317 | vmx_load_host_state(vmx); | |
3318 | vmx->msr_guest_kernel_gs_base = data; | |
3319 | break; | |
6aa8b732 AK |
3320 | #endif |
3321 | case MSR_IA32_SYSENTER_CS: | |
3322 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
3323 | break; | |
3324 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 3325 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
3326 | break; |
3327 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 3328 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 3329 | break; |
0dd376e7 | 3330 | case MSR_IA32_BNDCFGS: |
691bd434 | 3331 | if (!kvm_mpx_supported() || |
d6321d49 RK |
3332 | (!msr_info->host_initiated && |
3333 | !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) | |
93c4adc7 | 3334 | return 1; |
fd8cb433 | 3335 | if (is_noncanonical_address(data & PAGE_MASK, vcpu) || |
4531662d | 3336 | (data & MSR_IA32_BNDCFGS_RSVD)) |
93c4adc7 | 3337 | return 1; |
0dd376e7 LJ |
3338 | vmcs_write64(GUEST_BNDCFGS, data); |
3339 | break; | |
af24a4e4 | 3340 | case MSR_IA32_TSC: |
8fe8ab46 | 3341 | kvm_write_tsc(vcpu, msr_info); |
6aa8b732 | 3342 | break; |
468d472f SY |
3343 | case MSR_IA32_CR_PAT: |
3344 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
4566654b NA |
3345 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) |
3346 | return 1; | |
468d472f SY |
3347 | vmcs_write64(GUEST_IA32_PAT, data); |
3348 | vcpu->arch.pat = data; | |
3349 | break; | |
3350 | } | |
8fe8ab46 | 3351 | ret = kvm_set_msr_common(vcpu, msr_info); |
4e47c7a6 | 3352 | break; |
ba904635 WA |
3353 | case MSR_IA32_TSC_ADJUST: |
3354 | ret = kvm_set_msr_common(vcpu, msr_info); | |
4e47c7a6 | 3355 | break; |
c45dcc71 AR |
3356 | case MSR_IA32_MCG_EXT_CTL: |
3357 | if ((!msr_info->host_initiated && | |
3358 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3359 | FEATURE_CONTROL_LMCE)) || | |
3360 | (data & ~MCG_EXT_CTL_LMCE_EN)) | |
3361 | return 1; | |
3362 | vcpu->arch.mcg_ext_ctl = data; | |
3363 | break; | |
cae50139 | 3364 | case MSR_IA32_FEATURE_CONTROL: |
37e4c997 | 3365 | if (!vmx_feature_control_msr_valid(vcpu, data) || |
3b84080b | 3366 | (to_vmx(vcpu)->msr_ia32_feature_control & |
cae50139 JK |
3367 | FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) |
3368 | return 1; | |
3b84080b | 3369 | vmx->msr_ia32_feature_control = data; |
cae50139 JK |
3370 | if (msr_info->host_initiated && data == 0) |
3371 | vmx_leave_nested(vcpu); | |
3372 | break; | |
3373 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
62cc6b9d DM |
3374 | if (!msr_info->host_initiated) |
3375 | return 1; /* they are read-only */ | |
3376 | if (!nested_vmx_allowed(vcpu)) | |
3377 | return 1; | |
3378 | return vmx_set_vmx_msr(vcpu, msr_index, data); | |
20300099 WL |
3379 | case MSR_IA32_XSS: |
3380 | if (!vmx_xsaves_supported()) | |
3381 | return 1; | |
3382 | /* | |
3383 | * The only supported bit as of Skylake is bit 8, but | |
3384 | * it is not supported on KVM. | |
3385 | */ | |
3386 | if (data != 0) | |
3387 | return 1; | |
3388 | vcpu->arch.ia32_xss = data; | |
3389 | if (vcpu->arch.ia32_xss != host_xss) | |
3390 | add_atomic_switch_msr(vmx, MSR_IA32_XSS, | |
3391 | vcpu->arch.ia32_xss, host_xss); | |
3392 | else | |
3393 | clear_atomic_switch_msr(vmx, MSR_IA32_XSS); | |
3394 | break; | |
4e47c7a6 | 3395 | case MSR_TSC_AUX: |
d6321d49 RK |
3396 | if (!msr_info->host_initiated && |
3397 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) | |
4e47c7a6 SY |
3398 | return 1; |
3399 | /* Check reserved bit, higher 32 bits should be zero */ | |
3400 | if ((data >> 32) != 0) | |
3401 | return 1; | |
3402 | /* Otherwise falls through */ | |
6aa8b732 | 3403 | default: |
8b9cf98c | 3404 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 3405 | if (msr) { |
8b3c3104 | 3406 | u64 old_msr_data = msr->data; |
3bab1f5d | 3407 | msr->data = data; |
2225fd56 AK |
3408 | if (msr - vmx->guest_msrs < vmx->save_nmsrs) { |
3409 | preempt_disable(); | |
8b3c3104 AH |
3410 | ret = kvm_set_shared_msr(msr->index, msr->data, |
3411 | msr->mask); | |
2225fd56 | 3412 | preempt_enable(); |
8b3c3104 AH |
3413 | if (ret) |
3414 | msr->data = old_msr_data; | |
2225fd56 | 3415 | } |
3bab1f5d | 3416 | break; |
6aa8b732 | 3417 | } |
8fe8ab46 | 3418 | ret = kvm_set_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3419 | } |
3420 | ||
2cc51560 | 3421 | return ret; |
6aa8b732 AK |
3422 | } |
3423 | ||
5fdbf976 | 3424 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 3425 | { |
5fdbf976 MT |
3426 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
3427 | switch (reg) { | |
3428 | case VCPU_REGS_RSP: | |
3429 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
3430 | break; | |
3431 | case VCPU_REGS_RIP: | |
3432 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
3433 | break; | |
6de4f3ad AK |
3434 | case VCPU_EXREG_PDPTR: |
3435 | if (enable_ept) | |
3436 | ept_save_pdptrs(vcpu); | |
3437 | break; | |
5fdbf976 MT |
3438 | default: |
3439 | break; | |
3440 | } | |
6aa8b732 AK |
3441 | } |
3442 | ||
6aa8b732 AK |
3443 | static __init int cpu_has_kvm_support(void) |
3444 | { | |
6210e37b | 3445 | return cpu_has_vmx(); |
6aa8b732 AK |
3446 | } |
3447 | ||
3448 | static __init int vmx_disabled_by_bios(void) | |
3449 | { | |
3450 | u64 msr; | |
3451 | ||
3452 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 3453 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 3454 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
3455 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
3456 | && tboot_enabled()) | |
3457 | return 1; | |
23f3e991 | 3458 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 3459 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 3460 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
3461 | && !tboot_enabled()) { |
3462 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 3463 | "activate TXT before enabling KVM\n"); |
cafd6659 | 3464 | return 1; |
f9335afe | 3465 | } |
23f3e991 JC |
3466 | /* launched w/o TXT and VMX disabled */ |
3467 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
3468 | && !tboot_enabled()) | |
3469 | return 1; | |
cafd6659 SW |
3470 | } |
3471 | ||
3472 | return 0; | |
6aa8b732 AK |
3473 | } |
3474 | ||
7725b894 DX |
3475 | static void kvm_cpu_vmxon(u64 addr) |
3476 | { | |
fe0e80be | 3477 | cr4_set_bits(X86_CR4_VMXE); |
1c5ac21a AS |
3478 | intel_pt_handle_vmx(1); |
3479 | ||
7725b894 DX |
3480 | asm volatile (ASM_VMX_VMXON_RAX |
3481 | : : "a"(&addr), "m"(addr) | |
3482 | : "memory", "cc"); | |
3483 | } | |
3484 | ||
13a34e06 | 3485 | static int hardware_enable(void) |
6aa8b732 AK |
3486 | { |
3487 | int cpu = raw_smp_processor_id(); | |
3488 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 3489 | u64 old, test_bits; |
6aa8b732 | 3490 | |
1e02ce4c | 3491 | if (cr4_read_shadow() & X86_CR4_VMXE) |
10474ae8 AG |
3492 | return -EBUSY; |
3493 | ||
d462b819 | 3494 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
bf9f6ac8 FW |
3495 | INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); |
3496 | spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
8f536b76 ZY |
3497 | |
3498 | /* | |
3499 | * Now we can enable the vmclear operation in kdump | |
3500 | * since the loaded_vmcss_on_cpu list on this cpu | |
3501 | * has been initialized. | |
3502 | * | |
3503 | * Though the cpu is not in VMX operation now, there | |
3504 | * is no problem to enable the vmclear operation | |
3505 | * for the loaded_vmcss_on_cpu list is empty! | |
3506 | */ | |
3507 | crash_enable_local_vmclear(cpu); | |
3508 | ||
6aa8b732 | 3509 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
3510 | |
3511 | test_bits = FEATURE_CONTROL_LOCKED; | |
3512 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
3513 | if (tboot_enabled()) | |
3514 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
3515 | ||
3516 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 3517 | /* enable and lock */ |
cafd6659 SW |
3518 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
3519 | } | |
fe0e80be | 3520 | kvm_cpu_vmxon(phys_addr); |
fdf288bf DH |
3521 | if (enable_ept) |
3522 | ept_sync_global(); | |
10474ae8 AG |
3523 | |
3524 | return 0; | |
6aa8b732 AK |
3525 | } |
3526 | ||
d462b819 | 3527 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
3528 | { |
3529 | int cpu = raw_smp_processor_id(); | |
d462b819 | 3530 | struct loaded_vmcs *v, *n; |
543e4243 | 3531 | |
d462b819 NHE |
3532 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
3533 | loaded_vmcss_on_cpu_link) | |
3534 | __loaded_vmcs_clear(v); | |
543e4243 AK |
3535 | } |
3536 | ||
710ff4a8 EH |
3537 | |
3538 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
3539 | * tricks. | |
3540 | */ | |
3541 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 3542 | { |
4ecac3fd | 3543 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
1c5ac21a AS |
3544 | |
3545 | intel_pt_handle_vmx(0); | |
fe0e80be | 3546 | cr4_clear_bits(X86_CR4_VMXE); |
6aa8b732 AK |
3547 | } |
3548 | ||
13a34e06 | 3549 | static void hardware_disable(void) |
710ff4a8 | 3550 | { |
fe0e80be DH |
3551 | vmclear_local_loaded_vmcss(); |
3552 | kvm_cpu_vmxoff(); | |
710ff4a8 EH |
3553 | } |
3554 | ||
1c3d14fe | 3555 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 3556 | u32 msr, u32 *result) |
1c3d14fe YS |
3557 | { |
3558 | u32 vmx_msr_low, vmx_msr_high; | |
3559 | u32 ctl = ctl_min | ctl_opt; | |
3560 | ||
3561 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3562 | ||
3563 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
3564 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
3565 | ||
3566 | /* Ensure minimum (required) set of control bits are supported. */ | |
3567 | if (ctl_min & ~ctl) | |
002c7f7c | 3568 | return -EIO; |
1c3d14fe YS |
3569 | |
3570 | *result = ctl; | |
3571 | return 0; | |
3572 | } | |
3573 | ||
110312c8 AK |
3574 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
3575 | { | |
3576 | u32 vmx_msr_low, vmx_msr_high; | |
3577 | ||
3578 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3579 | return vmx_msr_high & ctl; | |
3580 | } | |
3581 | ||
002c7f7c | 3582 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
3583 | { |
3584 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 3585 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
3586 | u32 _pin_based_exec_control = 0; |
3587 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 3588 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
3589 | u32 _vmexit_control = 0; |
3590 | u32 _vmentry_control = 0; | |
3591 | ||
10166744 | 3592 | min = CPU_BASED_HLT_EXITING | |
1c3d14fe YS |
3593 | #ifdef CONFIG_X86_64 |
3594 | CPU_BASED_CR8_LOAD_EXITING | | |
3595 | CPU_BASED_CR8_STORE_EXITING | | |
3596 | #endif | |
d56f546d SY |
3597 | CPU_BASED_CR3_LOAD_EXITING | |
3598 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
3599 | CPU_BASED_USE_IO_BITMAPS | |
3600 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 3601 | CPU_BASED_USE_TSC_OFFSETING | |
fee84b07 AK |
3602 | CPU_BASED_INVLPG_EXITING | |
3603 | CPU_BASED_RDPMC_EXITING; | |
443381a8 | 3604 | |
668fffa3 MT |
3605 | if (!kvm_mwait_in_guest()) |
3606 | min |= CPU_BASED_MWAIT_EXITING | | |
3607 | CPU_BASED_MONITOR_EXITING; | |
3608 | ||
f78e0e2e | 3609 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 3610 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 3611 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
3612 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
3613 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 3614 | return -EIO; |
6e5d865c YS |
3615 | #ifdef CONFIG_X86_64 |
3616 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3617 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
3618 | ~CPU_BASED_CR8_STORE_EXITING; | |
3619 | #endif | |
f78e0e2e | 3620 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
3621 | min2 = 0; |
3622 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
8d14695f | 3623 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2384d2b3 | 3624 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 3625 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 3626 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 3627 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 | 3628 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
ad756a16 | 3629 | SECONDARY_EXEC_RDTSCP | |
83d4c286 | 3630 | SECONDARY_EXEC_ENABLE_INVPCID | |
c7c9c56c | 3631 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
abc4fc58 | 3632 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
20300099 | 3633 | SECONDARY_EXEC_SHADOW_VMCS | |
843e4330 | 3634 | SECONDARY_EXEC_XSAVES | |
736fdf72 DH |
3635 | SECONDARY_EXEC_RDSEED_EXITING | |
3636 | SECONDARY_EXEC_RDRAND_EXITING | | |
8b3e34e4 | 3637 | SECONDARY_EXEC_ENABLE_PML | |
2a499e49 BD |
3638 | SECONDARY_EXEC_TSC_SCALING | |
3639 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
d56f546d SY |
3640 | if (adjust_vmx_controls(min2, opt2, |
3641 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
3642 | &_cpu_based_2nd_exec_control) < 0) |
3643 | return -EIO; | |
3644 | } | |
3645 | #ifndef CONFIG_X86_64 | |
3646 | if (!(_cpu_based_2nd_exec_control & | |
3647 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
3648 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
3649 | #endif | |
83d4c286 YZ |
3650 | |
3651 | if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3652 | _cpu_based_2nd_exec_control &= ~( | |
8d14695f | 3653 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
c7c9c56c YZ |
3654 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
3655 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
83d4c286 | 3656 | |
61f1dd90 WL |
3657 | rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, |
3658 | &vmx_capability.ept, &vmx_capability.vpid); | |
3659 | ||
d56f546d | 3660 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
3661 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
3662 | enabled */ | |
5fff7d27 GN |
3663 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
3664 | CPU_BASED_CR3_STORE_EXITING | | |
3665 | CPU_BASED_INVLPG_EXITING); | |
61f1dd90 WL |
3666 | } else if (vmx_capability.ept) { |
3667 | vmx_capability.ept = 0; | |
3668 | pr_warn_once("EPT CAP should not exist if not support " | |
3669 | "1-setting enable EPT VM-execution control\n"); | |
3670 | } | |
3671 | if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && | |
3672 | vmx_capability.vpid) { | |
3673 | vmx_capability.vpid = 0; | |
3674 | pr_warn_once("VPID CAP should not exist if not support " | |
3675 | "1-setting enable VPID VM-execution control\n"); | |
d56f546d | 3676 | } |
1c3d14fe | 3677 | |
91fa0f8e | 3678 | min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; |
1c3d14fe YS |
3679 | #ifdef CONFIG_X86_64 |
3680 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
3681 | #endif | |
a547c6db | 3682 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT | |
91fa0f8e | 3683 | VM_EXIT_CLEAR_BNDCFGS; |
1c3d14fe YS |
3684 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
3685 | &_vmexit_control) < 0) | |
002c7f7c | 3686 | return -EIO; |
1c3d14fe | 3687 | |
8a1b4392 PB |
3688 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; |
3689 | opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | | |
3690 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
3691 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
3692 | &_pin_based_exec_control) < 0) | |
3693 | return -EIO; | |
3694 | ||
1c17c3e6 PB |
3695 | if (cpu_has_broken_vmx_preemption_timer()) |
3696 | _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be | 3697 | if (!(_cpu_based_2nd_exec_control & |
91fa0f8e | 3698 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) |
01e439be YZ |
3699 | _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; |
3700 | ||
c845f9c6 | 3701 | min = VM_ENTRY_LOAD_DEBUG_CONTROLS; |
da8999d3 | 3702 | opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS; |
1c3d14fe YS |
3703 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
3704 | &_vmentry_control) < 0) | |
002c7f7c | 3705 | return -EIO; |
6aa8b732 | 3706 | |
c68876fd | 3707 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
3708 | |
3709 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
3710 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 3711 | return -EIO; |
1c3d14fe YS |
3712 | |
3713 | #ifdef CONFIG_X86_64 | |
3714 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
3715 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 3716 | return -EIO; |
1c3d14fe YS |
3717 | #endif |
3718 | ||
3719 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
3720 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 3721 | return -EIO; |
1c3d14fe | 3722 | |
002c7f7c | 3723 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
16cb0255 | 3724 | vmcs_conf->order = get_order(vmcs_conf->size); |
9ac7e3e8 | 3725 | vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; |
002c7f7c | 3726 | vmcs_conf->revision_id = vmx_msr_low; |
1c3d14fe | 3727 | |
002c7f7c YS |
3728 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
3729 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 3730 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
3731 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
3732 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 3733 | |
110312c8 AK |
3734 | cpu_has_load_ia32_efer = |
3735 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3736 | VM_ENTRY_LOAD_IA32_EFER) | |
3737 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3738 | VM_EXIT_LOAD_IA32_EFER); | |
3739 | ||
8bf00a52 GN |
3740 | cpu_has_load_perf_global_ctrl = |
3741 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3742 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
3743 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3744 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
3745 | ||
3746 | /* | |
3747 | * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL | |
bb3541f1 | 3748 | * but due to errata below it can't be used. Workaround is to use |
8bf00a52 GN |
3749 | * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. |
3750 | * | |
3751 | * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] | |
3752 | * | |
3753 | * AAK155 (model 26) | |
3754 | * AAP115 (model 30) | |
3755 | * AAT100 (model 37) | |
3756 | * BC86,AAY89,BD102 (model 44) | |
3757 | * BA97 (model 46) | |
3758 | * | |
3759 | */ | |
3760 | if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) { | |
3761 | switch (boot_cpu_data.x86_model) { | |
3762 | case 26: | |
3763 | case 30: | |
3764 | case 37: | |
3765 | case 44: | |
3766 | case 46: | |
3767 | cpu_has_load_perf_global_ctrl = false; | |
3768 | printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " | |
3769 | "does not work properly. Using workaround\n"); | |
3770 | break; | |
3771 | default: | |
3772 | break; | |
3773 | } | |
3774 | } | |
3775 | ||
782511b0 | 3776 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
20300099 WL |
3777 | rdmsrl(MSR_IA32_XSS, host_xss); |
3778 | ||
1c3d14fe | 3779 | return 0; |
c68876fd | 3780 | } |
6aa8b732 AK |
3781 | |
3782 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
3783 | { | |
3784 | int node = cpu_to_node(cpu); | |
3785 | struct page *pages; | |
3786 | struct vmcs *vmcs; | |
3787 | ||
96db800f | 3788 | pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
3789 | if (!pages) |
3790 | return NULL; | |
3791 | vmcs = page_address(pages); | |
1c3d14fe YS |
3792 | memset(vmcs, 0, vmcs_config.size); |
3793 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
3794 | return vmcs; |
3795 | } | |
3796 | ||
6aa8b732 AK |
3797 | static void free_vmcs(struct vmcs *vmcs) |
3798 | { | |
1c3d14fe | 3799 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
3800 | } |
3801 | ||
d462b819 NHE |
3802 | /* |
3803 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
3804 | */ | |
3805 | static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
3806 | { | |
3807 | if (!loaded_vmcs->vmcs) | |
3808 | return; | |
3809 | loaded_vmcs_clear(loaded_vmcs); | |
3810 | free_vmcs(loaded_vmcs->vmcs); | |
3811 | loaded_vmcs->vmcs = NULL; | |
904e14fb PB |
3812 | if (loaded_vmcs->msr_bitmap) |
3813 | free_page((unsigned long)loaded_vmcs->msr_bitmap); | |
355f4fb1 | 3814 | WARN_ON(loaded_vmcs->shadow_vmcs != NULL); |
d462b819 NHE |
3815 | } |
3816 | ||
f21f165e PB |
3817 | static struct vmcs *alloc_vmcs(void) |
3818 | { | |
3819 | return alloc_vmcs_cpu(raw_smp_processor_id()); | |
3820 | } | |
3821 | ||
3822 | static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
3823 | { | |
3824 | loaded_vmcs->vmcs = alloc_vmcs(); | |
3825 | if (!loaded_vmcs->vmcs) | |
3826 | return -ENOMEM; | |
3827 | ||
3828 | loaded_vmcs->shadow_vmcs = NULL; | |
3829 | loaded_vmcs_init(loaded_vmcs); | |
904e14fb PB |
3830 | |
3831 | if (cpu_has_vmx_msr_bitmap()) { | |
3832 | loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL); | |
3833 | if (!loaded_vmcs->msr_bitmap) | |
3834 | goto out_vmcs; | |
3835 | memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); | |
3836 | } | |
f21f165e | 3837 | return 0; |
904e14fb PB |
3838 | |
3839 | out_vmcs: | |
3840 | free_loaded_vmcs(loaded_vmcs); | |
3841 | return -ENOMEM; | |
f21f165e PB |
3842 | } |
3843 | ||
39959588 | 3844 | static void free_kvm_area(void) |
6aa8b732 AK |
3845 | { |
3846 | int cpu; | |
3847 | ||
3230bb47 | 3848 | for_each_possible_cpu(cpu) { |
6aa8b732 | 3849 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
3850 | per_cpu(vmxarea, cpu) = NULL; |
3851 | } | |
6aa8b732 AK |
3852 | } |
3853 | ||
85fd514e JM |
3854 | enum vmcs_field_type { |
3855 | VMCS_FIELD_TYPE_U16 = 0, | |
3856 | VMCS_FIELD_TYPE_U64 = 1, | |
3857 | VMCS_FIELD_TYPE_U32 = 2, | |
3858 | VMCS_FIELD_TYPE_NATURAL_WIDTH = 3 | |
3859 | }; | |
3860 | ||
3861 | static inline int vmcs_field_type(unsigned long field) | |
3862 | { | |
3863 | if (0x1 & field) /* the *_HIGH fields are all 32 bit */ | |
3864 | return VMCS_FIELD_TYPE_U32; | |
3865 | return (field >> 13) & 0x3 ; | |
3866 | } | |
3867 | ||
3868 | static inline int vmcs_field_readonly(unsigned long field) | |
3869 | { | |
3870 | return (((field >> 10) & 0x3) == 1); | |
3871 | } | |
3872 | ||
fe2b201b BD |
3873 | static void init_vmcs_shadow_fields(void) |
3874 | { | |
3875 | int i, j; | |
3876 | ||
3877 | /* No checks for read only fields yet */ | |
3878 | ||
3879 | for (i = j = 0; i < max_shadow_read_write_fields; i++) { | |
3880 | switch (shadow_read_write_fields[i]) { | |
3881 | case GUEST_BNDCFGS: | |
a87036ad | 3882 | if (!kvm_mpx_supported()) |
fe2b201b BD |
3883 | continue; |
3884 | break; | |
3885 | default: | |
3886 | break; | |
3887 | } | |
3888 | ||
3889 | if (j < i) | |
3890 | shadow_read_write_fields[j] = | |
3891 | shadow_read_write_fields[i]; | |
3892 | j++; | |
3893 | } | |
3894 | max_shadow_read_write_fields = j; | |
3895 | ||
3896 | /* shadowed fields guest access without vmexit */ | |
3897 | for (i = 0; i < max_shadow_read_write_fields; i++) { | |
85fd514e JM |
3898 | unsigned long field = shadow_read_write_fields[i]; |
3899 | ||
3900 | clear_bit(field, vmx_vmwrite_bitmap); | |
3901 | clear_bit(field, vmx_vmread_bitmap); | |
3902 | if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) { | |
3903 | clear_bit(field + 1, vmx_vmwrite_bitmap); | |
3904 | clear_bit(field + 1, vmx_vmread_bitmap); | |
3905 | } | |
3906 | } | |
3907 | for (i = 0; i < max_shadow_read_only_fields; i++) { | |
3908 | unsigned long field = shadow_read_only_fields[i]; | |
3909 | ||
3910 | clear_bit(field, vmx_vmread_bitmap); | |
3911 | if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) | |
3912 | clear_bit(field + 1, vmx_vmread_bitmap); | |
fe2b201b | 3913 | } |
fe2b201b BD |
3914 | } |
3915 | ||
6aa8b732 AK |
3916 | static __init int alloc_kvm_area(void) |
3917 | { | |
3918 | int cpu; | |
3919 | ||
3230bb47 | 3920 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
3921 | struct vmcs *vmcs; |
3922 | ||
3923 | vmcs = alloc_vmcs_cpu(cpu); | |
3924 | if (!vmcs) { | |
3925 | free_kvm_area(); | |
3926 | return -ENOMEM; | |
3927 | } | |
3928 | ||
3929 | per_cpu(vmxarea, cpu) = vmcs; | |
3930 | } | |
3931 | return 0; | |
3932 | } | |
3933 | ||
91b0aa2c | 3934 | static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, |
d99e4152 | 3935 | struct kvm_segment *save) |
6aa8b732 | 3936 | { |
d99e4152 GN |
3937 | if (!emulate_invalid_guest_state) { |
3938 | /* | |
3939 | * CS and SS RPL should be equal during guest entry according | |
3940 | * to VMX spec, but in reality it is not always so. Since vcpu | |
3941 | * is in the middle of the transition from real mode to | |
3942 | * protected mode it is safe to assume that RPL 0 is a good | |
3943 | * default value. | |
3944 | */ | |
3945 | if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) | |
b32a9918 NA |
3946 | save->selector &= ~SEGMENT_RPL_MASK; |
3947 | save->dpl = save->selector & SEGMENT_RPL_MASK; | |
d99e4152 | 3948 | save->s = 1; |
6aa8b732 | 3949 | } |
d99e4152 | 3950 | vmx_set_segment(vcpu, save, seg); |
6aa8b732 AK |
3951 | } |
3952 | ||
3953 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
3954 | { | |
3955 | unsigned long flags; | |
a89a8fb9 | 3956 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3957 | |
d99e4152 GN |
3958 | /* |
3959 | * Update real mode segment cache. It may be not up-to-date if sement | |
3960 | * register was written while vcpu was in a guest mode. | |
3961 | */ | |
3962 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3963 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3964 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3965 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
3966 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); | |
3967 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
3968 | ||
7ffd92c5 | 3969 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 3970 | |
2fb92db1 AK |
3971 | vmx_segment_cache_clear(vmx); |
3972 | ||
f5f7b2fe | 3973 | vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
6aa8b732 AK |
3974 | |
3975 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
3976 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
3977 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
3978 | vmcs_writel(GUEST_RFLAGS, flags); |
3979 | ||
66aee91a RR |
3980 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
3981 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
3982 | |
3983 | update_exception_bitmap(vcpu); | |
3984 | ||
91b0aa2c GN |
3985 | fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); |
3986 | fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); | |
3987 | fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
3988 | fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
3989 | fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
3990 | fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
6aa8b732 AK |
3991 | } |
3992 | ||
f5f7b2fe | 3993 | static void fix_rmode_seg(int seg, struct kvm_segment *save) |
6aa8b732 | 3994 | { |
772e0318 | 3995 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
d99e4152 GN |
3996 | struct kvm_segment var = *save; |
3997 | ||
3998 | var.dpl = 0x3; | |
3999 | if (seg == VCPU_SREG_CS) | |
4000 | var.type = 0x3; | |
4001 | ||
4002 | if (!emulate_invalid_guest_state) { | |
4003 | var.selector = var.base >> 4; | |
4004 | var.base = var.base & 0xffff0; | |
4005 | var.limit = 0xffff; | |
4006 | var.g = 0; | |
4007 | var.db = 0; | |
4008 | var.present = 1; | |
4009 | var.s = 1; | |
4010 | var.l = 0; | |
4011 | var.unusable = 0; | |
4012 | var.type = 0x3; | |
4013 | var.avl = 0; | |
4014 | if (save->base & 0xf) | |
4015 | printk_once(KERN_WARNING "kvm: segment base is not " | |
4016 | "paragraph aligned when entering " | |
4017 | "protected mode (seg=%d)", seg); | |
4018 | } | |
6aa8b732 | 4019 | |
d99e4152 | 4020 | vmcs_write16(sf->selector, var.selector); |
96794e4e | 4021 | vmcs_writel(sf->base, var.base); |
d99e4152 GN |
4022 | vmcs_write32(sf->limit, var.limit); |
4023 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); | |
6aa8b732 AK |
4024 | } |
4025 | ||
4026 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
4027 | { | |
4028 | unsigned long flags; | |
a89a8fb9 | 4029 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 4030 | |
f5f7b2fe AK |
4031 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
4032 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
4033 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
4034 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
4035 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
c6ad1153 GN |
4036 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); |
4037 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
f5f7b2fe | 4038 | |
7ffd92c5 | 4039 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 4040 | |
776e58ea GN |
4041 | /* |
4042 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
4918c6ca | 4043 | * vcpu. Warn the user that an update is overdue. |
776e58ea | 4044 | */ |
4918c6ca | 4045 | if (!vcpu->kvm->arch.tss_addr) |
776e58ea GN |
4046 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " |
4047 | "called before entering vcpu\n"); | |
776e58ea | 4048 | |
2fb92db1 AK |
4049 | vmx_segment_cache_clear(vmx); |
4050 | ||
4918c6ca | 4051 | vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr); |
6aa8b732 | 4052 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
6aa8b732 AK |
4053 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
4054 | ||
4055 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 4056 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 4057 | |
053de044 | 4058 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
4059 | |
4060 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 4061 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
4062 | update_exception_bitmap(vcpu); |
4063 | ||
d99e4152 GN |
4064 | fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); |
4065 | fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); | |
4066 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
4067 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
4068 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
4069 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
b246dd5d | 4070 | |
8668a3c4 | 4071 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
4072 | } |
4073 | ||
401d10de AS |
4074 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
4075 | { | |
4076 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
4077 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
4078 | ||
4079 | if (!msr) | |
4080 | return; | |
401d10de | 4081 | |
44ea2b17 AK |
4082 | /* |
4083 | * Force kernel_gs_base reloading before EFER changes, as control | |
4084 | * of this msr depends on is_long_mode(). | |
4085 | */ | |
4086 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 4087 | vcpu->arch.efer = efer; |
401d10de | 4088 | if (efer & EFER_LMA) { |
2961e876 | 4089 | vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
4090 | msr->data = efer; |
4091 | } else { | |
2961e876 | 4092 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
4093 | |
4094 | msr->data = efer & ~EFER_LME; | |
4095 | } | |
4096 | setup_msrs(vmx); | |
4097 | } | |
4098 | ||
05b3e0c2 | 4099 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
4100 | |
4101 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
4102 | { | |
4103 | u32 guest_tr_ar; | |
4104 | ||
2fb92db1 AK |
4105 | vmx_segment_cache_clear(to_vmx(vcpu)); |
4106 | ||
6aa8b732 | 4107 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
4d283ec9 | 4108 | if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { |
bd80158a JK |
4109 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
4110 | __func__); | |
6aa8b732 | 4111 | vmcs_write32(GUEST_TR_AR_BYTES, |
4d283ec9 AL |
4112 | (guest_tr_ar & ~VMX_AR_TYPE_MASK) |
4113 | | VMX_AR_TYPE_BUSY_64_TSS); | |
6aa8b732 | 4114 | } |
da38f438 | 4115 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
4116 | } |
4117 | ||
4118 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
4119 | { | |
2961e876 | 4120 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
da38f438 | 4121 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
4122 | } |
4123 | ||
4124 | #endif | |
4125 | ||
dd5f5341 | 4126 | static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid) |
2384d2b3 | 4127 | { |
dd180b3e XG |
4128 | if (enable_ept) { |
4129 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
4130 | return; | |
995f00a6 | 4131 | ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa)); |
f0b98c02 JM |
4132 | } else { |
4133 | vpid_sync_context(vpid); | |
dd180b3e | 4134 | } |
2384d2b3 SY |
4135 | } |
4136 | ||
dd5f5341 WL |
4137 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
4138 | { | |
4139 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid); | |
4140 | } | |
4141 | ||
fb6c8198 JM |
4142 | static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu) |
4143 | { | |
4144 | if (enable_ept) | |
4145 | vmx_flush_tlb(vcpu); | |
4146 | } | |
4147 | ||
e8467fda AK |
4148 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
4149 | { | |
4150 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
4151 | ||
4152 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
4153 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
4154 | } | |
4155 | ||
aff48baa AK |
4156 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
4157 | { | |
4158 | if (enable_ept && is_paging(vcpu)) | |
4159 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
4160 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
4161 | } | |
4162 | ||
25c4c276 | 4163 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 4164 | { |
fc78f519 AK |
4165 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
4166 | ||
4167 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
4168 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
4169 | } |
4170 | ||
1439442c SY |
4171 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
4172 | { | |
d0d538b9 GN |
4173 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4174 | ||
6de4f3ad AK |
4175 | if (!test_bit(VCPU_EXREG_PDPTR, |
4176 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
4177 | return; | |
4178 | ||
1439442c | 4179 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
4180 | vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); |
4181 | vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); | |
4182 | vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); | |
4183 | vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); | |
1439442c SY |
4184 | } |
4185 | } | |
4186 | ||
8f5d549f AK |
4187 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
4188 | { | |
d0d538b9 GN |
4189 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4190 | ||
8f5d549f | 4191 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
4192 | mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
4193 | mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
4194 | mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
4195 | mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 4196 | } |
6de4f3ad AK |
4197 | |
4198 | __set_bit(VCPU_EXREG_PDPTR, | |
4199 | (unsigned long *)&vcpu->arch.regs_avail); | |
4200 | __set_bit(VCPU_EXREG_PDPTR, | |
4201 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
4202 | } |
4203 | ||
3899152c DM |
4204 | static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) |
4205 | { | |
4206 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0; | |
4207 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1; | |
4208 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
4209 | ||
4210 | if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high & | |
4211 | SECONDARY_EXEC_UNRESTRICTED_GUEST && | |
4212 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) | |
4213 | fixed0 &= ~(X86_CR0_PE | X86_CR0_PG); | |
4214 | ||
4215 | return fixed_bits_valid(val, fixed0, fixed1); | |
4216 | } | |
4217 | ||
4218 | static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4219 | { | |
4220 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0; | |
4221 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1; | |
4222 | ||
4223 | return fixed_bits_valid(val, fixed0, fixed1); | |
4224 | } | |
4225 | ||
4226 | static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4227 | { | |
4228 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0; | |
4229 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1; | |
4230 | ||
4231 | return fixed_bits_valid(val, fixed0, fixed1); | |
4232 | } | |
4233 | ||
4234 | /* No difference in the restrictions on guest and host CR4 in VMX operation. */ | |
4235 | #define nested_guest_cr4_valid nested_cr4_valid | |
4236 | #define nested_host_cr4_valid nested_cr4_valid | |
4237 | ||
5e1746d6 | 4238 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1439442c SY |
4239 | |
4240 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
4241 | unsigned long cr0, | |
4242 | struct kvm_vcpu *vcpu) | |
4243 | { | |
5233dd51 MT |
4244 | if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
4245 | vmx_decache_cr3(vcpu); | |
1439442c SY |
4246 | if (!(cr0 & X86_CR0_PG)) { |
4247 | /* From paging/starting to nonpaging */ | |
4248 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4249 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
4250 | (CPU_BASED_CR3_LOAD_EXITING | |
4251 | CPU_BASED_CR3_STORE_EXITING)); | |
4252 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4253 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
4254 | } else if (!is_paging(vcpu)) { |
4255 | /* From nonpaging to paging */ | |
4256 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4257 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
4258 | ~(CPU_BASED_CR3_LOAD_EXITING | |
4259 | CPU_BASED_CR3_STORE_EXITING)); | |
4260 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4261 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 4262 | } |
95eb84a7 SY |
4263 | |
4264 | if (!(cr0 & X86_CR0_WP)) | |
4265 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
4266 | } |
4267 | ||
6aa8b732 AK |
4268 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
4269 | { | |
7ffd92c5 | 4270 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
4271 | unsigned long hw_cr0; |
4272 | ||
5037878e | 4273 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK); |
3a624e29 | 4274 | if (enable_unrestricted_guest) |
5037878e | 4275 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; |
218e763f | 4276 | else { |
5037878e | 4277 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; |
1439442c | 4278 | |
218e763f GN |
4279 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
4280 | enter_pmode(vcpu); | |
6aa8b732 | 4281 | |
218e763f GN |
4282 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
4283 | enter_rmode(vcpu); | |
4284 | } | |
6aa8b732 | 4285 | |
05b3e0c2 | 4286 | #ifdef CONFIG_X86_64 |
f6801dff | 4287 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 4288 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 4289 | enter_lmode(vcpu); |
707d92fa | 4290 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
4291 | exit_lmode(vcpu); |
4292 | } | |
4293 | #endif | |
4294 | ||
089d034e | 4295 | if (enable_ept) |
1439442c SY |
4296 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
4297 | ||
6aa8b732 | 4298 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 4299 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 4300 | vcpu->arch.cr0 = cr0; |
14168786 GN |
4301 | |
4302 | /* depends on vcpu->arch.cr0 to be set to a new value */ | |
4303 | vmx->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
4304 | } |
4305 | ||
855feb67 YZ |
4306 | static int get_ept_level(struct kvm_vcpu *vcpu) |
4307 | { | |
4308 | if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) | |
4309 | return 5; | |
4310 | return 4; | |
4311 | } | |
4312 | ||
995f00a6 | 4313 | static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) |
1439442c | 4314 | { |
855feb67 YZ |
4315 | u64 eptp = VMX_EPTP_MT_WB; |
4316 | ||
4317 | eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; | |
1439442c | 4318 | |
995f00a6 PF |
4319 | if (enable_ept_ad_bits && |
4320 | (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) | |
bb97a016 | 4321 | eptp |= VMX_EPTP_AD_ENABLE_BIT; |
1439442c SY |
4322 | eptp |= (root_hpa & PAGE_MASK); |
4323 | ||
4324 | return eptp; | |
4325 | } | |
4326 | ||
6aa8b732 AK |
4327 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
4328 | { | |
1439442c SY |
4329 | unsigned long guest_cr3; |
4330 | u64 eptp; | |
4331 | ||
4332 | guest_cr3 = cr3; | |
089d034e | 4333 | if (enable_ept) { |
995f00a6 | 4334 | eptp = construct_eptp(vcpu, cr3); |
1439442c | 4335 | vmcs_write64(EPT_POINTER, eptp); |
59ab5a8f JK |
4336 | if (is_paging(vcpu) || is_guest_mode(vcpu)) |
4337 | guest_cr3 = kvm_read_cr3(vcpu); | |
4338 | else | |
4339 | guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr; | |
7c93be44 | 4340 | ept_load_pdptrs(vcpu); |
1439442c SY |
4341 | } |
4342 | ||
2384d2b3 | 4343 | vmx_flush_tlb(vcpu); |
1439442c | 4344 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
4345 | } |
4346 | ||
5e1746d6 | 4347 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 4348 | { |
085e68ee BS |
4349 | /* |
4350 | * Pass through host's Machine Check Enable value to hw_cr4, which | |
4351 | * is in force while we are in guest mode. Do not let guests control | |
4352 | * this bit, even if host CR4.MCE == 0. | |
4353 | */ | |
4354 | unsigned long hw_cr4 = | |
4355 | (cr4_read_shadow() & X86_CR4_MCE) | | |
4356 | (cr4 & ~X86_CR4_MCE) | | |
4357 | (to_vmx(vcpu)->rmode.vm86_active ? | |
4358 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1439442c | 4359 | |
5e1746d6 NHE |
4360 | if (cr4 & X86_CR4_VMXE) { |
4361 | /* | |
4362 | * To use VMXON (and later other VMX instructions), a guest | |
4363 | * must first be able to turn on cr4.VMXE (see handle_vmon()). | |
4364 | * So basically the check on whether to allow nested VMX | |
4365 | * is here. | |
4366 | */ | |
4367 | if (!nested_vmx_allowed(vcpu)) | |
4368 | return 1; | |
1a0d74e6 | 4369 | } |
3899152c DM |
4370 | |
4371 | if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) | |
5e1746d6 NHE |
4372 | return 1; |
4373 | ||
ad312c7c | 4374 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
4375 | if (enable_ept) { |
4376 | if (!is_paging(vcpu)) { | |
4377 | hw_cr4 &= ~X86_CR4_PAE; | |
4378 | hw_cr4 |= X86_CR4_PSE; | |
4379 | } else if (!(cr4 & X86_CR4_PAE)) { | |
4380 | hw_cr4 &= ~X86_CR4_PAE; | |
4381 | } | |
4382 | } | |
1439442c | 4383 | |
656ec4a4 RK |
4384 | if (!enable_unrestricted_guest && !is_paging(vcpu)) |
4385 | /* | |
ddba2628 HH |
4386 | * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in |
4387 | * hardware. To emulate this behavior, SMEP/SMAP/PKU needs | |
4388 | * to be manually disabled when guest switches to non-paging | |
4389 | * mode. | |
4390 | * | |
4391 | * If !enable_unrestricted_guest, the CPU is always running | |
4392 | * with CR0.PG=1 and CR4 needs to be modified. | |
4393 | * If enable_unrestricted_guest, the CPU automatically | |
4394 | * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. | |
656ec4a4 | 4395 | */ |
ddba2628 | 4396 | hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); |
656ec4a4 | 4397 | |
1439442c SY |
4398 | vmcs_writel(CR4_READ_SHADOW, cr4); |
4399 | vmcs_writel(GUEST_CR4, hw_cr4); | |
5e1746d6 | 4400 | return 0; |
6aa8b732 AK |
4401 | } |
4402 | ||
6aa8b732 AK |
4403 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
4404 | struct kvm_segment *var, int seg) | |
4405 | { | |
a9179499 | 4406 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
4407 | u32 ar; |
4408 | ||
c6ad1153 | 4409 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
f5f7b2fe | 4410 | *var = vmx->rmode.segs[seg]; |
a9179499 | 4411 | if (seg == VCPU_SREG_TR |
2fb92db1 | 4412 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
f5f7b2fe | 4413 | return; |
1390a28b AK |
4414 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4415 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4416 | return; | |
a9179499 | 4417 | } |
2fb92db1 AK |
4418 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4419 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
4420 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4421 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
03617c18 | 4422 | var->unusable = (ar >> 16) & 1; |
6aa8b732 AK |
4423 | var->type = ar & 15; |
4424 | var->s = (ar >> 4) & 1; | |
4425 | var->dpl = (ar >> 5) & 3; | |
03617c18 GN |
4426 | /* |
4427 | * Some userspaces do not preserve unusable property. Since usable | |
4428 | * segment has to be present according to VMX spec we can use present | |
4429 | * property to amend userspace bug by making unusable segment always | |
4430 | * nonpresent. vmx_segment_access_rights() already marks nonpresent | |
4431 | * segment as unusable. | |
4432 | */ | |
4433 | var->present = !var->unusable; | |
6aa8b732 AK |
4434 | var->avl = (ar >> 12) & 1; |
4435 | var->l = (ar >> 13) & 1; | |
4436 | var->db = (ar >> 14) & 1; | |
4437 | var->g = (ar >> 15) & 1; | |
6aa8b732 AK |
4438 | } |
4439 | ||
a9179499 AK |
4440 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4441 | { | |
a9179499 AK |
4442 | struct kvm_segment s; |
4443 | ||
4444 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
4445 | vmx_get_segment(vcpu, &s, seg); | |
4446 | return s.base; | |
4447 | } | |
2fb92db1 | 4448 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
4449 | } |
4450 | ||
b09408d0 | 4451 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 4452 | { |
b09408d0 MT |
4453 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4454 | ||
ae9fedc7 | 4455 | if (unlikely(vmx->rmode.vm86_active)) |
2e4d2653 | 4456 | return 0; |
ae9fedc7 PB |
4457 | else { |
4458 | int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); | |
4d283ec9 | 4459 | return VMX_AR_DPL(ar); |
69c73028 | 4460 | } |
69c73028 AK |
4461 | } |
4462 | ||
653e3108 | 4463 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 4464 | { |
6aa8b732 AK |
4465 | u32 ar; |
4466 | ||
f0495f9b | 4467 | if (var->unusable || !var->present) |
6aa8b732 AK |
4468 | ar = 1 << 16; |
4469 | else { | |
4470 | ar = var->type & 15; | |
4471 | ar |= (var->s & 1) << 4; | |
4472 | ar |= (var->dpl & 3) << 5; | |
4473 | ar |= (var->present & 1) << 7; | |
4474 | ar |= (var->avl & 1) << 12; | |
4475 | ar |= (var->l & 1) << 13; | |
4476 | ar |= (var->db & 1) << 14; | |
4477 | ar |= (var->g & 1) << 15; | |
4478 | } | |
653e3108 AK |
4479 | |
4480 | return ar; | |
4481 | } | |
4482 | ||
4483 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
4484 | struct kvm_segment *var, int seg) | |
4485 | { | |
7ffd92c5 | 4486 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
772e0318 | 4487 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
653e3108 | 4488 | |
2fb92db1 AK |
4489 | vmx_segment_cache_clear(vmx); |
4490 | ||
1ecd50a9 GN |
4491 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
4492 | vmx->rmode.segs[seg] = *var; | |
4493 | if (seg == VCPU_SREG_TR) | |
4494 | vmcs_write16(sf->selector, var->selector); | |
4495 | else if (var->s) | |
4496 | fix_rmode_seg(seg, &vmx->rmode.segs[seg]); | |
d99e4152 | 4497 | goto out; |
653e3108 | 4498 | } |
1ecd50a9 | 4499 | |
653e3108 AK |
4500 | vmcs_writel(sf->base, var->base); |
4501 | vmcs_write32(sf->limit, var->limit); | |
4502 | vmcs_write16(sf->selector, var->selector); | |
3a624e29 NK |
4503 | |
4504 | /* | |
4505 | * Fix the "Accessed" bit in AR field of segment registers for older | |
4506 | * qemu binaries. | |
4507 | * IA32 arch specifies that at the time of processor reset the | |
4508 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
0fa06071 | 4509 | * is setting it to 0 in the userland code. This causes invalid guest |
3a624e29 NK |
4510 | * state vmexit when "unrestricted guest" mode is turned on. |
4511 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
4512 | * tree. Newer qemu binaries with that qemu fix would not need this | |
4513 | * kvm hack. | |
4514 | */ | |
4515 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
f924d66d | 4516 | var->type |= 0x1; /* Accessed */ |
3a624e29 | 4517 | |
f924d66d | 4518 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); |
d99e4152 GN |
4519 | |
4520 | out: | |
98eb2f8b | 4521 | vmx->emulation_required = emulation_required(vcpu); |
6aa8b732 AK |
4522 | } |
4523 | ||
6aa8b732 AK |
4524 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
4525 | { | |
2fb92db1 | 4526 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
4527 | |
4528 | *db = (ar >> 14) & 1; | |
4529 | *l = (ar >> 13) & 1; | |
4530 | } | |
4531 | ||
89a27f4d | 4532 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4533 | { |
89a27f4d GN |
4534 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
4535 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
4536 | } |
4537 | ||
89a27f4d | 4538 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4539 | { |
89a27f4d GN |
4540 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
4541 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
4542 | } |
4543 | ||
89a27f4d | 4544 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4545 | { |
89a27f4d GN |
4546 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
4547 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
4548 | } |
4549 | ||
89a27f4d | 4550 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4551 | { |
89a27f4d GN |
4552 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
4553 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
4554 | } |
4555 | ||
648dfaa7 MG |
4556 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
4557 | { | |
4558 | struct kvm_segment var; | |
4559 | u32 ar; | |
4560 | ||
4561 | vmx_get_segment(vcpu, &var, seg); | |
07f42f5f | 4562 | var.dpl = 0x3; |
0647f4aa GN |
4563 | if (seg == VCPU_SREG_CS) |
4564 | var.type = 0x3; | |
648dfaa7 MG |
4565 | ar = vmx_segment_access_rights(&var); |
4566 | ||
4567 | if (var.base != (var.selector << 4)) | |
4568 | return false; | |
89efbed0 | 4569 | if (var.limit != 0xffff) |
648dfaa7 | 4570 | return false; |
07f42f5f | 4571 | if (ar != 0xf3) |
648dfaa7 MG |
4572 | return false; |
4573 | ||
4574 | return true; | |
4575 | } | |
4576 | ||
4577 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
4578 | { | |
4579 | struct kvm_segment cs; | |
4580 | unsigned int cs_rpl; | |
4581 | ||
4582 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
b32a9918 | 4583 | cs_rpl = cs.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4584 | |
1872a3f4 AK |
4585 | if (cs.unusable) |
4586 | return false; | |
4d283ec9 | 4587 | if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) |
648dfaa7 MG |
4588 | return false; |
4589 | if (!cs.s) | |
4590 | return false; | |
4d283ec9 | 4591 | if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
4592 | if (cs.dpl > cs_rpl) |
4593 | return false; | |
1872a3f4 | 4594 | } else { |
648dfaa7 MG |
4595 | if (cs.dpl != cs_rpl) |
4596 | return false; | |
4597 | } | |
4598 | if (!cs.present) | |
4599 | return false; | |
4600 | ||
4601 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
4602 | return true; | |
4603 | } | |
4604 | ||
4605 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
4606 | { | |
4607 | struct kvm_segment ss; | |
4608 | unsigned int ss_rpl; | |
4609 | ||
4610 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
b32a9918 | 4611 | ss_rpl = ss.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4612 | |
1872a3f4 AK |
4613 | if (ss.unusable) |
4614 | return true; | |
4615 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
4616 | return false; |
4617 | if (!ss.s) | |
4618 | return false; | |
4619 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
4620 | return false; | |
4621 | if (!ss.present) | |
4622 | return false; | |
4623 | ||
4624 | return true; | |
4625 | } | |
4626 | ||
4627 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
4628 | { | |
4629 | struct kvm_segment var; | |
4630 | unsigned int rpl; | |
4631 | ||
4632 | vmx_get_segment(vcpu, &var, seg); | |
b32a9918 | 4633 | rpl = var.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4634 | |
1872a3f4 AK |
4635 | if (var.unusable) |
4636 | return true; | |
648dfaa7 MG |
4637 | if (!var.s) |
4638 | return false; | |
4639 | if (!var.present) | |
4640 | return false; | |
4d283ec9 | 4641 | if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { |
648dfaa7 MG |
4642 | if (var.dpl < rpl) /* DPL < RPL */ |
4643 | return false; | |
4644 | } | |
4645 | ||
4646 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
4647 | * rights flags | |
4648 | */ | |
4649 | return true; | |
4650 | } | |
4651 | ||
4652 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
4653 | { | |
4654 | struct kvm_segment tr; | |
4655 | ||
4656 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
4657 | ||
1872a3f4 AK |
4658 | if (tr.unusable) |
4659 | return false; | |
b32a9918 | 4660 | if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 | 4661 | return false; |
1872a3f4 | 4662 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
4663 | return false; |
4664 | if (!tr.present) | |
4665 | return false; | |
4666 | ||
4667 | return true; | |
4668 | } | |
4669 | ||
4670 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
4671 | { | |
4672 | struct kvm_segment ldtr; | |
4673 | ||
4674 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
4675 | ||
1872a3f4 AK |
4676 | if (ldtr.unusable) |
4677 | return true; | |
b32a9918 | 4678 | if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 MG |
4679 | return false; |
4680 | if (ldtr.type != 2) | |
4681 | return false; | |
4682 | if (!ldtr.present) | |
4683 | return false; | |
4684 | ||
4685 | return true; | |
4686 | } | |
4687 | ||
4688 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
4689 | { | |
4690 | struct kvm_segment cs, ss; | |
4691 | ||
4692 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
4693 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
4694 | ||
b32a9918 NA |
4695 | return ((cs.selector & SEGMENT_RPL_MASK) == |
4696 | (ss.selector & SEGMENT_RPL_MASK)); | |
648dfaa7 MG |
4697 | } |
4698 | ||
4699 | /* | |
4700 | * Check if guest state is valid. Returns true if valid, false if | |
4701 | * not. | |
4702 | * We assume that registers are always usable | |
4703 | */ | |
4704 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
4705 | { | |
c5e97c80 GN |
4706 | if (enable_unrestricted_guest) |
4707 | return true; | |
4708 | ||
648dfaa7 | 4709 | /* real mode guest state checks */ |
f13882d8 | 4710 | if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { |
648dfaa7 MG |
4711 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
4712 | return false; | |
4713 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
4714 | return false; | |
4715 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
4716 | return false; | |
4717 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
4718 | return false; | |
4719 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
4720 | return false; | |
4721 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
4722 | return false; | |
4723 | } else { | |
4724 | /* protected mode guest state checks */ | |
4725 | if (!cs_ss_rpl_check(vcpu)) | |
4726 | return false; | |
4727 | if (!code_segment_valid(vcpu)) | |
4728 | return false; | |
4729 | if (!stack_segment_valid(vcpu)) | |
4730 | return false; | |
4731 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
4732 | return false; | |
4733 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
4734 | return false; | |
4735 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
4736 | return false; | |
4737 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
4738 | return false; | |
4739 | if (!tr_valid(vcpu)) | |
4740 | return false; | |
4741 | if (!ldtr_valid(vcpu)) | |
4742 | return false; | |
4743 | } | |
4744 | /* TODO: | |
4745 | * - Add checks on RIP | |
4746 | * - Add checks on RFLAGS | |
4747 | */ | |
4748 | ||
4749 | return true; | |
4750 | } | |
4751 | ||
5fa99cbe JM |
4752 | static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa) |
4753 | { | |
4754 | return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu)); | |
4755 | } | |
4756 | ||
d77c26fc | 4757 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 4758 | { |
40dcaa9f | 4759 | gfn_t fn; |
195aefde | 4760 | u16 data = 0; |
1f755a82 | 4761 | int idx, r; |
6aa8b732 | 4762 | |
40dcaa9f | 4763 | idx = srcu_read_lock(&kvm->srcu); |
4918c6ca | 4764 | fn = kvm->arch.tss_addr >> PAGE_SHIFT; |
195aefde IE |
4765 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4766 | if (r < 0) | |
10589a46 | 4767 | goto out; |
195aefde | 4768 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
4769 | r = kvm_write_guest_page(kvm, fn++, &data, |
4770 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 4771 | if (r < 0) |
10589a46 | 4772 | goto out; |
195aefde IE |
4773 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
4774 | if (r < 0) | |
10589a46 | 4775 | goto out; |
195aefde IE |
4776 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4777 | if (r < 0) | |
10589a46 | 4778 | goto out; |
195aefde | 4779 | data = ~0; |
10589a46 MT |
4780 | r = kvm_write_guest_page(kvm, fn, &data, |
4781 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
4782 | sizeof(u8)); | |
10589a46 | 4783 | out: |
40dcaa9f | 4784 | srcu_read_unlock(&kvm->srcu, idx); |
1f755a82 | 4785 | return r; |
6aa8b732 AK |
4786 | } |
4787 | ||
b7ebfb05 SY |
4788 | static int init_rmode_identity_map(struct kvm *kvm) |
4789 | { | |
f51770ed | 4790 | int i, idx, r = 0; |
ba049e93 | 4791 | kvm_pfn_t identity_map_pfn; |
b7ebfb05 SY |
4792 | u32 tmp; |
4793 | ||
a255d479 TC |
4794 | /* Protect kvm->arch.ept_identity_pagetable_done. */ |
4795 | mutex_lock(&kvm->slots_lock); | |
4796 | ||
f51770ed | 4797 | if (likely(kvm->arch.ept_identity_pagetable_done)) |
a255d479 | 4798 | goto out2; |
a255d479 | 4799 | |
d8a6e365 DH |
4800 | if (!kvm->arch.ept_identity_map_addr) |
4801 | kvm->arch.ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
b927a3ce | 4802 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
a255d479 | 4803 | |
d8a6e365 DH |
4804 | r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, |
4805 | kvm->arch.ept_identity_map_addr, PAGE_SIZE); | |
f51770ed | 4806 | if (r < 0) |
a255d479 TC |
4807 | goto out2; |
4808 | ||
40dcaa9f | 4809 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
4810 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
4811 | if (r < 0) | |
4812 | goto out; | |
4813 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
4814 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
4815 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
4816 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
4817 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
4818 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
4819 | if (r < 0) | |
4820 | goto out; | |
4821 | } | |
4822 | kvm->arch.ept_identity_pagetable_done = true; | |
f51770ed | 4823 | |
b7ebfb05 | 4824 | out: |
40dcaa9f | 4825 | srcu_read_unlock(&kvm->srcu, idx); |
a255d479 TC |
4826 | |
4827 | out2: | |
4828 | mutex_unlock(&kvm->slots_lock); | |
f51770ed | 4829 | return r; |
b7ebfb05 SY |
4830 | } |
4831 | ||
6aa8b732 AK |
4832 | static void seg_setup(int seg) |
4833 | { | |
772e0318 | 4834 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
3a624e29 | 4835 | unsigned int ar; |
6aa8b732 AK |
4836 | |
4837 | vmcs_write16(sf->selector, 0); | |
4838 | vmcs_writel(sf->base, 0); | |
4839 | vmcs_write32(sf->limit, 0xffff); | |
d54d07b2 GN |
4840 | ar = 0x93; |
4841 | if (seg == VCPU_SREG_CS) | |
4842 | ar |= 0x08; /* code segment */ | |
3a624e29 NK |
4843 | |
4844 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
4845 | } |
4846 | ||
f78e0e2e SY |
4847 | static int alloc_apic_access_page(struct kvm *kvm) |
4848 | { | |
4484141a | 4849 | struct page *page; |
f78e0e2e SY |
4850 | int r = 0; |
4851 | ||
79fac95e | 4852 | mutex_lock(&kvm->slots_lock); |
c24ae0dc | 4853 | if (kvm->arch.apic_access_page_done) |
f78e0e2e | 4854 | goto out; |
1d8007bd PB |
4855 | r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, |
4856 | APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); | |
f78e0e2e SY |
4857 | if (r) |
4858 | goto out; | |
72dc67a6 | 4859 | |
73a6d941 | 4860 | page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
4484141a XG |
4861 | if (is_error_page(page)) { |
4862 | r = -EFAULT; | |
4863 | goto out; | |
4864 | } | |
4865 | ||
c24ae0dc TC |
4866 | /* |
4867 | * Do not pin the page in memory, so that memory hot-unplug | |
4868 | * is able to migrate it. | |
4869 | */ | |
4870 | put_page(page); | |
4871 | kvm->arch.apic_access_page_done = true; | |
f78e0e2e | 4872 | out: |
79fac95e | 4873 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
4874 | return r; |
4875 | } | |
4876 | ||
991e7a0e | 4877 | static int allocate_vpid(void) |
2384d2b3 SY |
4878 | { |
4879 | int vpid; | |
4880 | ||
919818ab | 4881 | if (!enable_vpid) |
991e7a0e | 4882 | return 0; |
2384d2b3 SY |
4883 | spin_lock(&vmx_vpid_lock); |
4884 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
991e7a0e | 4885 | if (vpid < VMX_NR_VPIDS) |
2384d2b3 | 4886 | __set_bit(vpid, vmx_vpid_bitmap); |
991e7a0e WL |
4887 | else |
4888 | vpid = 0; | |
2384d2b3 | 4889 | spin_unlock(&vmx_vpid_lock); |
991e7a0e | 4890 | return vpid; |
2384d2b3 SY |
4891 | } |
4892 | ||
991e7a0e | 4893 | static void free_vpid(int vpid) |
cdbecfc3 | 4894 | { |
991e7a0e | 4895 | if (!enable_vpid || vpid == 0) |
cdbecfc3 LJ |
4896 | return; |
4897 | spin_lock(&vmx_vpid_lock); | |
991e7a0e | 4898 | __clear_bit(vpid, vmx_vpid_bitmap); |
cdbecfc3 LJ |
4899 | spin_unlock(&vmx_vpid_lock); |
4900 | } | |
4901 | ||
904e14fb PB |
4902 | static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, |
4903 | u32 msr, int type) | |
25c5f225 | 4904 | { |
3e7c73e9 | 4905 | int f = sizeof(unsigned long); |
25c5f225 SY |
4906 | |
4907 | if (!cpu_has_vmx_msr_bitmap()) | |
4908 | return; | |
4909 | ||
4910 | /* | |
4911 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4912 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4913 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4914 | */ | |
25c5f225 | 4915 | if (msr <= 0x1fff) { |
8d14695f YZ |
4916 | if (type & MSR_TYPE_R) |
4917 | /* read-low */ | |
4918 | __clear_bit(msr, msr_bitmap + 0x000 / f); | |
4919 | ||
4920 | if (type & MSR_TYPE_W) | |
4921 | /* write-low */ | |
4922 | __clear_bit(msr, msr_bitmap + 0x800 / f); | |
4923 | ||
25c5f225 SY |
4924 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
4925 | msr &= 0x1fff; | |
8d14695f YZ |
4926 | if (type & MSR_TYPE_R) |
4927 | /* read-high */ | |
4928 | __clear_bit(msr, msr_bitmap + 0x400 / f); | |
4929 | ||
4930 | if (type & MSR_TYPE_W) | |
4931 | /* write-high */ | |
4932 | __clear_bit(msr, msr_bitmap + 0xc00 / f); | |
4933 | ||
4934 | } | |
4935 | } | |
4936 | ||
904e14fb PB |
4937 | static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, |
4938 | u32 msr, int type) | |
4939 | { | |
4940 | int f = sizeof(unsigned long); | |
4941 | ||
4942 | if (!cpu_has_vmx_msr_bitmap()) | |
4943 | return; | |
4944 | ||
4945 | /* | |
4946 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4947 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4948 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4949 | */ | |
4950 | if (msr <= 0x1fff) { | |
4951 | if (type & MSR_TYPE_R) | |
4952 | /* read-low */ | |
4953 | __set_bit(msr, msr_bitmap + 0x000 / f); | |
4954 | ||
4955 | if (type & MSR_TYPE_W) | |
4956 | /* write-low */ | |
4957 | __set_bit(msr, msr_bitmap + 0x800 / f); | |
4958 | ||
4959 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
4960 | msr &= 0x1fff; | |
4961 | if (type & MSR_TYPE_R) | |
4962 | /* read-high */ | |
4963 | __set_bit(msr, msr_bitmap + 0x400 / f); | |
4964 | ||
4965 | if (type & MSR_TYPE_W) | |
4966 | /* write-high */ | |
4967 | __set_bit(msr, msr_bitmap + 0xc00 / f); | |
4968 | ||
4969 | } | |
4970 | } | |
4971 | ||
4972 | static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap, | |
4973 | u32 msr, int type, bool value) | |
4974 | { | |
4975 | if (value) | |
4976 | vmx_enable_intercept_for_msr(msr_bitmap, msr, type); | |
4977 | else | |
4978 | vmx_disable_intercept_for_msr(msr_bitmap, msr, type); | |
4979 | } | |
4980 | ||
f2b93280 WV |
4981 | /* |
4982 | * If a msr is allowed by L0, we should check whether it is allowed by L1. | |
4983 | * The corresponding bit will be cleared unless both of L0 and L1 allow it. | |
4984 | */ | |
4985 | static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1, | |
4986 | unsigned long *msr_bitmap_nested, | |
4987 | u32 msr, int type) | |
4988 | { | |
4989 | int f = sizeof(unsigned long); | |
4990 | ||
4991 | if (!cpu_has_vmx_msr_bitmap()) { | |
4992 | WARN_ON(1); | |
4993 | return; | |
4994 | } | |
4995 | ||
4996 | /* | |
4997 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4998 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4999 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
5000 | */ | |
5001 | if (msr <= 0x1fff) { | |
5002 | if (type & MSR_TYPE_R && | |
5003 | !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) | |
5004 | /* read-low */ | |
5005 | __clear_bit(msr, msr_bitmap_nested + 0x000 / f); | |
5006 | ||
5007 | if (type & MSR_TYPE_W && | |
5008 | !test_bit(msr, msr_bitmap_l1 + 0x800 / f)) | |
5009 | /* write-low */ | |
5010 | __clear_bit(msr, msr_bitmap_nested + 0x800 / f); | |
5011 | ||
5012 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
5013 | msr &= 0x1fff; | |
5014 | if (type & MSR_TYPE_R && | |
5015 | !test_bit(msr, msr_bitmap_l1 + 0x400 / f)) | |
5016 | /* read-high */ | |
5017 | __clear_bit(msr, msr_bitmap_nested + 0x400 / f); | |
5018 | ||
5019 | if (type & MSR_TYPE_W && | |
5020 | !test_bit(msr, msr_bitmap_l1 + 0xc00 / f)) | |
5021 | /* write-high */ | |
5022 | __clear_bit(msr, msr_bitmap_nested + 0xc00 / f); | |
5023 | ||
5024 | } | |
5025 | } | |
5026 | ||
904e14fb | 5027 | static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) |
5897297b | 5028 | { |
904e14fb PB |
5029 | u8 mode = 0; |
5030 | ||
5031 | if (cpu_has_secondary_exec_ctrls() && | |
5032 | (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) & | |
5033 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { | |
5034 | mode |= MSR_BITMAP_MODE_X2APIC; | |
5035 | if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) | |
5036 | mode |= MSR_BITMAP_MODE_X2APIC_APICV; | |
5037 | } | |
5038 | ||
5039 | if (is_long_mode(vcpu)) | |
5040 | mode |= MSR_BITMAP_MODE_LM; | |
5041 | ||
5042 | return mode; | |
8d14695f YZ |
5043 | } |
5044 | ||
904e14fb PB |
5045 | #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4)) |
5046 | ||
5047 | static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, | |
5048 | u8 mode) | |
8d14695f | 5049 | { |
904e14fb PB |
5050 | int msr; |
5051 | ||
5052 | for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { | |
5053 | unsigned word = msr / BITS_PER_LONG; | |
5054 | msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; | |
5055 | msr_bitmap[word + (0x800 / sizeof(long))] = ~0; | |
5056 | } | |
5057 | ||
5058 | if (mode & MSR_BITMAP_MODE_X2APIC) { | |
5059 | /* | |
5060 | * TPR reads and writes can be virtualized even if virtual interrupt | |
5061 | * delivery is not in use. | |
5062 | */ | |
5063 | vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); | |
5064 | if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { | |
5065 | vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); | |
5066 | vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); | |
5067 | vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); | |
5068 | } | |
f6e90f9e | 5069 | } |
5897297b AK |
5070 | } |
5071 | ||
904e14fb PB |
5072 | static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) |
5073 | { | |
5074 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5075 | unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; | |
5076 | u8 mode = vmx_msr_bitmap_mode(vcpu); | |
5077 | u8 changed = mode ^ vmx->msr_bitmap_mode; | |
5078 | ||
5079 | if (!changed) | |
5080 | return; | |
5081 | ||
5082 | vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW, | |
5083 | !(mode & MSR_BITMAP_MODE_LM)); | |
5084 | ||
5085 | if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) | |
5086 | vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); | |
5087 | ||
5088 | vmx->msr_bitmap_mode = mode; | |
5089 | } | |
5090 | ||
b2a05fef | 5091 | static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu) |
d50ab6c1 | 5092 | { |
d62caabb | 5093 | return enable_apicv; |
d50ab6c1 PB |
5094 | } |
5095 | ||
c9f04407 DM |
5096 | static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu) |
5097 | { | |
5098 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
5099 | gfn_t gfn; | |
5100 | ||
5101 | /* | |
5102 | * Don't need to mark the APIC access page dirty; it is never | |
5103 | * written to by the CPU during APIC virtualization. | |
5104 | */ | |
5105 | ||
5106 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
5107 | gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT; | |
5108 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
5109 | } | |
5110 | ||
5111 | if (nested_cpu_has_posted_intr(vmcs12)) { | |
5112 | gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT; | |
5113 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
5114 | } | |
5115 | } | |
5116 | ||
5117 | ||
6342c50a | 5118 | static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu) |
705699a1 WV |
5119 | { |
5120 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5121 | int max_irr; | |
5122 | void *vapic_page; | |
5123 | u16 status; | |
5124 | ||
c9f04407 DM |
5125 | if (!vmx->nested.pi_desc || !vmx->nested.pi_pending) |
5126 | return; | |
705699a1 | 5127 | |
c9f04407 DM |
5128 | vmx->nested.pi_pending = false; |
5129 | if (!pi_test_and_clear_on(vmx->nested.pi_desc)) | |
5130 | return; | |
705699a1 | 5131 | |
c9f04407 DM |
5132 | max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256); |
5133 | if (max_irr != 256) { | |
705699a1 | 5134 | vapic_page = kmap(vmx->nested.virtual_apic_page); |
705699a1 WV |
5135 | __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page); |
5136 | kunmap(vmx->nested.virtual_apic_page); | |
5137 | ||
5138 | status = vmcs_read16(GUEST_INTR_STATUS); | |
5139 | if ((u8)max_irr > ((u8)status & 0xff)) { | |
5140 | status &= ~0xff; | |
5141 | status |= (u8)max_irr; | |
5142 | vmcs_write16(GUEST_INTR_STATUS, status); | |
5143 | } | |
5144 | } | |
c9f04407 DM |
5145 | |
5146 | nested_mark_vmcs12_pages_dirty(vcpu); | |
705699a1 WV |
5147 | } |
5148 | ||
06a5524f WV |
5149 | static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, |
5150 | bool nested) | |
21bc8dc5 RK |
5151 | { |
5152 | #ifdef CONFIG_SMP | |
06a5524f WV |
5153 | int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; |
5154 | ||
21bc8dc5 | 5155 | if (vcpu->mode == IN_GUEST_MODE) { |
28b835d6 | 5156 | /* |
5753743f HZ |
5157 | * The vector of interrupt to be delivered to vcpu had |
5158 | * been set in PIR before this function. | |
5159 | * | |
5160 | * Following cases will be reached in this block, and | |
5161 | * we always send a notification event in all cases as | |
5162 | * explained below. | |
5163 | * | |
5164 | * Case 1: vcpu keeps in non-root mode. Sending a | |
5165 | * notification event posts the interrupt to vcpu. | |
5166 | * | |
5167 | * Case 2: vcpu exits to root mode and is still | |
5168 | * runnable. PIR will be synced to vIRR before the | |
5169 | * next vcpu entry. Sending a notification event in | |
5170 | * this case has no effect, as vcpu is not in root | |
5171 | * mode. | |
28b835d6 | 5172 | * |
5753743f HZ |
5173 | * Case 3: vcpu exits to root mode and is blocked. |
5174 | * vcpu_block() has already synced PIR to vIRR and | |
5175 | * never blocks vcpu if vIRR is not cleared. Therefore, | |
5176 | * a blocked vcpu here does not wait for any requested | |
5177 | * interrupts in PIR, and sending a notification event | |
5178 | * which has no effect is safe here. | |
28b835d6 | 5179 | */ |
28b835d6 | 5180 | |
06a5524f | 5181 | apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); |
21bc8dc5 RK |
5182 | return true; |
5183 | } | |
5184 | #endif | |
5185 | return false; | |
5186 | } | |
5187 | ||
705699a1 WV |
5188 | static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, |
5189 | int vector) | |
5190 | { | |
5191 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5192 | ||
5193 | if (is_guest_mode(vcpu) && | |
5194 | vector == vmx->nested.posted_intr_nv) { | |
5195 | /* the PIR and ON have been set by L1. */ | |
06a5524f | 5196 | kvm_vcpu_trigger_posted_interrupt(vcpu, true); |
705699a1 WV |
5197 | /* |
5198 | * If a posted intr is not recognized by hardware, | |
5199 | * we will accomplish it in the next vmentry. | |
5200 | */ | |
5201 | vmx->nested.pi_pending = true; | |
5202 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5203 | return 0; | |
5204 | } | |
5205 | return -1; | |
5206 | } | |
a20ed54d YZ |
5207 | /* |
5208 | * Send interrupt to vcpu via posted interrupt way. | |
5209 | * 1. If target vcpu is running(non-root mode), send posted interrupt | |
5210 | * notification to vcpu and hardware will sync PIR to vIRR atomically. | |
5211 | * 2. If target vcpu isn't running(root mode), kick it to pick up the | |
5212 | * interrupt from PIR in next vmentry. | |
5213 | */ | |
5214 | static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) | |
5215 | { | |
5216 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5217 | int r; | |
5218 | ||
705699a1 WV |
5219 | r = vmx_deliver_nested_posted_interrupt(vcpu, vector); |
5220 | if (!r) | |
5221 | return; | |
5222 | ||
a20ed54d YZ |
5223 | if (pi_test_and_set_pir(vector, &vmx->pi_desc)) |
5224 | return; | |
5225 | ||
b95234c8 PB |
5226 | /* If a previous notification has sent the IPI, nothing to do. */ |
5227 | if (pi_test_and_set_on(&vmx->pi_desc)) | |
5228 | return; | |
5229 | ||
06a5524f | 5230 | if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) |
a20ed54d YZ |
5231 | kvm_vcpu_kick(vcpu); |
5232 | } | |
5233 | ||
a3a8ff8e NHE |
5234 | /* |
5235 | * Set up the vmcs's constant host-state fields, i.e., host-state fields that | |
5236 | * will not change in the lifetime of the guest. | |
5237 | * Note that host-state that does change is set elsewhere. E.g., host-state | |
5238 | * that is set differently for each CPU is set in vmx_vcpu_load(), not here. | |
5239 | */ | |
a547c6db | 5240 | static void vmx_set_constant_host_state(struct vcpu_vmx *vmx) |
a3a8ff8e NHE |
5241 | { |
5242 | u32 low32, high32; | |
5243 | unsigned long tmpl; | |
5244 | struct desc_ptr dt; | |
d6e41f11 | 5245 | unsigned long cr0, cr3, cr4; |
a3a8ff8e | 5246 | |
04ac88ab AL |
5247 | cr0 = read_cr0(); |
5248 | WARN_ON(cr0 & X86_CR0_TS); | |
5249 | vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ | |
d6e41f11 AL |
5250 | |
5251 | /* | |
5252 | * Save the most likely value for this task's CR3 in the VMCS. | |
5253 | * We can't use __get_current_cr3_fast() because we're not atomic. | |
5254 | */ | |
6c690ee1 | 5255 | cr3 = __read_cr3(); |
d6e41f11 | 5256 | vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ |
44889942 | 5257 | vmx->loaded_vmcs->vmcs_host_cr3 = cr3; |
a3a8ff8e | 5258 | |
d974baa3 | 5259 | /* Save the most likely value for this task's CR4 in the VMCS. */ |
1e02ce4c | 5260 | cr4 = cr4_read_shadow(); |
d974baa3 | 5261 | vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ |
44889942 | 5262 | vmx->loaded_vmcs->vmcs_host_cr4 = cr4; |
d974baa3 | 5263 | |
a3a8ff8e | 5264 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ |
b2da15ac AK |
5265 | #ifdef CONFIG_X86_64 |
5266 | /* | |
5267 | * Load null selectors, so we can avoid reloading them in | |
5268 | * __vmx_load_host_state(), in case userspace uses the null selectors | |
5269 | * too (the expected case). | |
5270 | */ | |
5271 | vmcs_write16(HOST_DS_SELECTOR, 0); | |
5272 | vmcs_write16(HOST_ES_SELECTOR, 0); | |
5273 | #else | |
a3a8ff8e NHE |
5274 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5275 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
b2da15ac | 5276 | #endif |
a3a8ff8e NHE |
5277 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5278 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
5279 | ||
87930019 | 5280 | store_idt(&dt); |
a3a8ff8e | 5281 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ |
a547c6db | 5282 | vmx->host_idt_base = dt.address; |
a3a8ff8e | 5283 | |
83287ea4 | 5284 | vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */ |
a3a8ff8e NHE |
5285 | |
5286 | rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); | |
5287 | vmcs_write32(HOST_IA32_SYSENTER_CS, low32); | |
5288 | rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); | |
5289 | vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ | |
5290 | ||
5291 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { | |
5292 | rdmsr(MSR_IA32_CR_PAT, low32, high32); | |
5293 | vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); | |
5294 | } | |
5295 | } | |
5296 | ||
bf8179a0 NHE |
5297 | static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) |
5298 | { | |
5299 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; | |
5300 | if (enable_ept) | |
5301 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
fe3ef05c NHE |
5302 | if (is_guest_mode(&vmx->vcpu)) |
5303 | vmx->vcpu.arch.cr4_guest_owned_bits &= | |
5304 | ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; | |
bf8179a0 NHE |
5305 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
5306 | } | |
5307 | ||
01e439be YZ |
5308 | static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) |
5309 | { | |
5310 | u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; | |
5311 | ||
d62caabb | 5312 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
01e439be | 5313 | pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; |
d02fcf50 PB |
5314 | |
5315 | if (!enable_vnmi) | |
5316 | pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; | |
5317 | ||
64672c95 YJ |
5318 | /* Enable the preemption timer dynamically */ |
5319 | pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
5320 | return pin_based_exec_ctrl; |
5321 | } | |
5322 | ||
d62caabb AS |
5323 | static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
5324 | { | |
5325 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5326 | ||
5327 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); | |
3ce424e4 RK |
5328 | if (cpu_has_secondary_exec_ctrls()) { |
5329 | if (kvm_vcpu_apicv_active(vcpu)) | |
5330 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
5331 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5332 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5333 | else | |
5334 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
5335 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5336 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5337 | } | |
5338 | ||
5339 | if (cpu_has_vmx_msr_bitmap()) | |
904e14fb | 5340 | vmx_update_msr_bitmap(vcpu); |
d62caabb AS |
5341 | } |
5342 | ||
bf8179a0 NHE |
5343 | static u32 vmx_exec_control(struct vcpu_vmx *vmx) |
5344 | { | |
5345 | u32 exec_control = vmcs_config.cpu_based_exec_ctrl; | |
d16c293e PB |
5346 | |
5347 | if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) | |
5348 | exec_control &= ~CPU_BASED_MOV_DR_EXITING; | |
5349 | ||
35754c98 | 5350 | if (!cpu_need_tpr_shadow(&vmx->vcpu)) { |
bf8179a0 NHE |
5351 | exec_control &= ~CPU_BASED_TPR_SHADOW; |
5352 | #ifdef CONFIG_X86_64 | |
5353 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
5354 | CPU_BASED_CR8_LOAD_EXITING; | |
5355 | #endif | |
5356 | } | |
5357 | if (!enable_ept) | |
5358 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
5359 | CPU_BASED_CR3_LOAD_EXITING | | |
5360 | CPU_BASED_INVLPG_EXITING; | |
5361 | return exec_control; | |
5362 | } | |
5363 | ||
45ec368c | 5364 | static bool vmx_rdrand_supported(void) |
bf8179a0 | 5365 | { |
45ec368c | 5366 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
736fdf72 | 5367 | SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5368 | } |
5369 | ||
75f4fc8d JM |
5370 | static bool vmx_rdseed_supported(void) |
5371 | { | |
5372 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
736fdf72 | 5373 | SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5374 | } |
5375 | ||
80154d77 | 5376 | static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) |
bf8179a0 | 5377 | { |
80154d77 PB |
5378 | struct kvm_vcpu *vcpu = &vmx->vcpu; |
5379 | ||
bf8179a0 | 5380 | u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; |
80154d77 | 5381 | if (!cpu_need_virtualize_apic_accesses(vcpu)) |
bf8179a0 NHE |
5382 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
5383 | if (vmx->vpid == 0) | |
5384 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
5385 | if (!enable_ept) { | |
5386 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
5387 | enable_unrestricted_guest = 0; | |
ad756a16 MJ |
5388 | /* Enable INVPCID for non-ept guests may cause performance regression. */ |
5389 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
bf8179a0 NHE |
5390 | } |
5391 | if (!enable_unrestricted_guest) | |
5392 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
5393 | if (!ple_gap) | |
5394 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
80154d77 | 5395 | if (!kvm_vcpu_apicv_active(vcpu)) |
c7c9c56c YZ |
5396 | exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | |
5397 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
8d14695f | 5398 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; |
abc4fc58 AG |
5399 | /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD |
5400 | (handle_vmptrld). | |
5401 | We can NOT enable shadow_vmcs here because we don't have yet | |
5402 | a current VMCS12 | |
5403 | */ | |
5404 | exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
a3eaa864 KH |
5405 | |
5406 | if (!enable_pml) | |
5407 | exec_control &= ~SECONDARY_EXEC_ENABLE_PML; | |
843e4330 | 5408 | |
3db13480 PB |
5409 | if (vmx_xsaves_supported()) { |
5410 | /* Exposing XSAVES only when XSAVE is exposed */ | |
5411 | bool xsaves_enabled = | |
5412 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && | |
5413 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); | |
5414 | ||
5415 | if (!xsaves_enabled) | |
5416 | exec_control &= ~SECONDARY_EXEC_XSAVES; | |
5417 | ||
5418 | if (nested) { | |
5419 | if (xsaves_enabled) | |
5420 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5421 | SECONDARY_EXEC_XSAVES; | |
5422 | else | |
5423 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5424 | ~SECONDARY_EXEC_XSAVES; | |
5425 | } | |
5426 | } | |
5427 | ||
80154d77 PB |
5428 | if (vmx_rdtscp_supported()) { |
5429 | bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); | |
5430 | if (!rdtscp_enabled) | |
5431 | exec_control &= ~SECONDARY_EXEC_RDTSCP; | |
5432 | ||
5433 | if (nested) { | |
5434 | if (rdtscp_enabled) | |
5435 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5436 | SECONDARY_EXEC_RDTSCP; | |
5437 | else | |
5438 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5439 | ~SECONDARY_EXEC_RDTSCP; | |
5440 | } | |
5441 | } | |
5442 | ||
5443 | if (vmx_invpcid_supported()) { | |
5444 | /* Exposing INVPCID only when PCID is exposed */ | |
5445 | bool invpcid_enabled = | |
5446 | guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && | |
5447 | guest_cpuid_has(vcpu, X86_FEATURE_PCID); | |
5448 | ||
5449 | if (!invpcid_enabled) { | |
5450 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
5451 | guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); | |
5452 | } | |
5453 | ||
5454 | if (nested) { | |
5455 | if (invpcid_enabled) | |
5456 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5457 | SECONDARY_EXEC_ENABLE_INVPCID; | |
5458 | else | |
5459 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5460 | ~SECONDARY_EXEC_ENABLE_INVPCID; | |
5461 | } | |
5462 | } | |
5463 | ||
45ec368c JM |
5464 | if (vmx_rdrand_supported()) { |
5465 | bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); | |
5466 | if (rdrand_enabled) | |
736fdf72 | 5467 | exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5468 | |
5469 | if (nested) { | |
5470 | if (rdrand_enabled) | |
5471 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
736fdf72 | 5472 | SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5473 | else |
5474 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
736fdf72 | 5475 | ~SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5476 | } |
5477 | } | |
5478 | ||
75f4fc8d JM |
5479 | if (vmx_rdseed_supported()) { |
5480 | bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); | |
5481 | if (rdseed_enabled) | |
736fdf72 | 5482 | exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5483 | |
5484 | if (nested) { | |
5485 | if (rdseed_enabled) | |
5486 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
736fdf72 | 5487 | SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5488 | else |
5489 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
736fdf72 | 5490 | ~SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5491 | } |
5492 | } | |
5493 | ||
80154d77 | 5494 | vmx->secondary_exec_control = exec_control; |
bf8179a0 NHE |
5495 | } |
5496 | ||
ce88decf XG |
5497 | static void ept_set_mmio_spte_mask(void) |
5498 | { | |
5499 | /* | |
5500 | * EPT Misconfigurations can be generated if the value of bits 2:0 | |
5501 | * of an EPT paging-structure entry is 110b (write/execute). | |
ce88decf | 5502 | */ |
dcdca5fe PF |
5503 | kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, |
5504 | VMX_EPT_MISCONFIG_WX_VALUE); | |
ce88decf XG |
5505 | } |
5506 | ||
f53cd63c | 5507 | #define VMX_XSS_EXIT_BITMAP 0 |
6aa8b732 AK |
5508 | /* |
5509 | * Sets up the vmcs for emulated real mode. | |
5510 | */ | |
12d79917 | 5511 | static void vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 5512 | { |
2e4ce7f5 | 5513 | #ifdef CONFIG_X86_64 |
6aa8b732 | 5514 | unsigned long a; |
2e4ce7f5 | 5515 | #endif |
6aa8b732 | 5516 | int i; |
6aa8b732 | 5517 | |
6aa8b732 | 5518 | /* I/O */ |
3e7c73e9 AK |
5519 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
5520 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 5521 | |
4607c2d7 AG |
5522 | if (enable_shadow_vmcs) { |
5523 | vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); | |
5524 | vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); | |
5525 | } | |
25c5f225 | 5526 | if (cpu_has_vmx_msr_bitmap()) |
904e14fb | 5527 | vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); |
25c5f225 | 5528 | |
6aa8b732 AK |
5529 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
5530 | ||
6aa8b732 | 5531 | /* Control */ |
01e439be | 5532 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); |
64672c95 | 5533 | vmx->hv_deadline_tsc = -1; |
6e5d865c | 5534 | |
bf8179a0 | 5535 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx)); |
6aa8b732 | 5536 | |
dfa169bb | 5537 | if (cpu_has_secondary_exec_ctrls()) { |
80154d77 | 5538 | vmx_compute_secondary_exec_control(vmx); |
bf8179a0 | 5539 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, |
80154d77 | 5540 | vmx->secondary_exec_control); |
dfa169bb | 5541 | } |
f78e0e2e | 5542 | |
d62caabb | 5543 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) { |
c7c9c56c YZ |
5544 | vmcs_write64(EOI_EXIT_BITMAP0, 0); |
5545 | vmcs_write64(EOI_EXIT_BITMAP1, 0); | |
5546 | vmcs_write64(EOI_EXIT_BITMAP2, 0); | |
5547 | vmcs_write64(EOI_EXIT_BITMAP3, 0); | |
5548 | ||
5549 | vmcs_write16(GUEST_INTR_STATUS, 0); | |
01e439be | 5550 | |
0bcf261c | 5551 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
01e439be | 5552 | vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); |
c7c9c56c YZ |
5553 | } |
5554 | ||
4b8d54f9 ZE |
5555 | if (ple_gap) { |
5556 | vmcs_write32(PLE_GAP, ple_gap); | |
a7653ecd RK |
5557 | vmx->ple_window = ple_window; |
5558 | vmx->ple_window_dirty = true; | |
4b8d54f9 ZE |
5559 | } |
5560 | ||
c3707958 XG |
5561 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
5562 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
6aa8b732 AK |
5563 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
5564 | ||
9581d442 AK |
5565 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
5566 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
a547c6db | 5567 | vmx_set_constant_host_state(vmx); |
05b3e0c2 | 5568 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
5569 | rdmsrl(MSR_FS_BASE, a); |
5570 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
5571 | rdmsrl(MSR_GS_BASE, a); | |
5572 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
5573 | #else | |
5574 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
5575 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
5576 | #endif | |
5577 | ||
2a499e49 BD |
5578 | if (cpu_has_vmx_vmfunc()) |
5579 | vmcs_write64(VM_FUNCTION_CONTROL, 0); | |
5580 | ||
2cc51560 ED |
5581 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
5582 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
61d2ef2c | 5583 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); |
2cc51560 | 5584 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
61d2ef2c | 5585 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); |
6aa8b732 | 5586 | |
74545705 RK |
5587 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) |
5588 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); | |
468d472f | 5589 | |
03916db9 | 5590 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { |
6aa8b732 AK |
5591 | u32 index = vmx_msr_index[i]; |
5592 | u32 data_low, data_high; | |
a2fa3e9f | 5593 | int j = vmx->nmsrs; |
6aa8b732 AK |
5594 | |
5595 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
5596 | continue; | |
432bd6cb AK |
5597 | if (wrmsr_safe(index, data_low, data_high) < 0) |
5598 | continue; | |
26bb0981 AK |
5599 | vmx->guest_msrs[j].index = i; |
5600 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 5601 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 5602 | ++vmx->nmsrs; |
6aa8b732 | 5603 | } |
6aa8b732 | 5604 | |
2961e876 GN |
5605 | |
5606 | vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl); | |
6aa8b732 AK |
5607 | |
5608 | /* 22.2.1, 20.8.1 */ | |
2961e876 | 5609 | vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl); |
1c3d14fe | 5610 | |
bd7e5b08 PB |
5611 | vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; |
5612 | vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); | |
5613 | ||
bf8179a0 | 5614 | set_cr4_guest_host_mask(vmx); |
e00c8cf2 | 5615 | |
f53cd63c WL |
5616 | if (vmx_xsaves_supported()) |
5617 | vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); | |
5618 | ||
4e59516a PF |
5619 | if (enable_pml) { |
5620 | ASSERT(vmx->pml_pg); | |
5621 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
5622 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
5623 | } | |
e00c8cf2 AK |
5624 | } |
5625 | ||
d28bc9dd | 5626 | static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e00c8cf2 AK |
5627 | { |
5628 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
58cb628d | 5629 | struct msr_data apic_base_msr; |
d28bc9dd | 5630 | u64 cr0; |
e00c8cf2 | 5631 | |
7ffd92c5 | 5632 | vmx->rmode.vm86_active = 0; |
e00c8cf2 | 5633 | |
ad312c7c | 5634 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
d28bc9dd NA |
5635 | kvm_set_cr8(vcpu, 0); |
5636 | ||
5637 | if (!init_event) { | |
5638 | apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | | |
5639 | MSR_IA32_APICBASE_ENABLE; | |
5640 | if (kvm_vcpu_is_reset_bsp(vcpu)) | |
5641 | apic_base_msr.data |= MSR_IA32_APICBASE_BSP; | |
5642 | apic_base_msr.host_initiated = true; | |
5643 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
5644 | } | |
e00c8cf2 | 5645 | |
2fb92db1 AK |
5646 | vmx_segment_cache_clear(vmx); |
5647 | ||
5706be0d | 5648 | seg_setup(VCPU_SREG_CS); |
66450a21 | 5649 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
f3531054 | 5650 | vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); |
e00c8cf2 AK |
5651 | |
5652 | seg_setup(VCPU_SREG_DS); | |
5653 | seg_setup(VCPU_SREG_ES); | |
5654 | seg_setup(VCPU_SREG_FS); | |
5655 | seg_setup(VCPU_SREG_GS); | |
5656 | seg_setup(VCPU_SREG_SS); | |
5657 | ||
5658 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
5659 | vmcs_writel(GUEST_TR_BASE, 0); | |
5660 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
5661 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
5662 | ||
5663 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
5664 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
5665 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
5666 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
5667 | ||
d28bc9dd NA |
5668 | if (!init_event) { |
5669 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
5670 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
5671 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
5672 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
5673 | } | |
e00c8cf2 | 5674 | |
c37c2873 | 5675 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); |
66450a21 | 5676 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 5677 | |
e00c8cf2 AK |
5678 | vmcs_writel(GUEST_GDTR_BASE, 0); |
5679 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
5680 | ||
5681 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
5682 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
5683 | ||
443381a8 | 5684 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 | 5685 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
f3531054 | 5686 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); |
a554d207 WL |
5687 | if (kvm_mpx_supported()) |
5688 | vmcs_write64(GUEST_BNDCFGS, 0); | |
e00c8cf2 | 5689 | |
e00c8cf2 AK |
5690 | setup_msrs(vmx); |
5691 | ||
6aa8b732 AK |
5692 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
5693 | ||
d28bc9dd | 5694 | if (cpu_has_vmx_tpr_shadow() && !init_event) { |
f78e0e2e | 5695 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); |
35754c98 | 5696 | if (cpu_need_tpr_shadow(vcpu)) |
f78e0e2e | 5697 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, |
d28bc9dd | 5698 | __pa(vcpu->arch.apic->regs)); |
f78e0e2e SY |
5699 | vmcs_write32(TPR_THRESHOLD, 0); |
5700 | } | |
5701 | ||
a73896cb | 5702 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
6aa8b732 | 5703 | |
2384d2b3 SY |
5704 | if (vmx->vpid != 0) |
5705 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
5706 | ||
d28bc9dd | 5707 | cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
d28bc9dd | 5708 | vmx->vcpu.arch.cr0 = cr0; |
f2463247 | 5709 | vmx_set_cr0(vcpu, cr0); /* enter rmode */ |
d28bc9dd | 5710 | vmx_set_cr4(vcpu, 0); |
5690891b | 5711 | vmx_set_efer(vcpu, 0); |
bd7e5b08 | 5712 | |
d28bc9dd | 5713 | update_exception_bitmap(vcpu); |
6aa8b732 | 5714 | |
dd5f5341 | 5715 | vpid_sync_context(vmx->vpid); |
6aa8b732 AK |
5716 | } |
5717 | ||
b6f1250e NHE |
5718 | /* |
5719 | * In nested virtualization, check if L1 asked to exit on external interrupts. | |
5720 | * For most existing hypervisors, this will always return true. | |
5721 | */ | |
5722 | static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) | |
5723 | { | |
5724 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5725 | PIN_BASED_EXT_INTR_MASK; | |
5726 | } | |
5727 | ||
77b0f5d6 BD |
5728 | /* |
5729 | * In nested virtualization, check if L1 has set | |
5730 | * VM_EXIT_ACK_INTR_ON_EXIT | |
5731 | */ | |
5732 | static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) | |
5733 | { | |
5734 | return get_vmcs12(vcpu)->vm_exit_controls & | |
5735 | VM_EXIT_ACK_INTR_ON_EXIT; | |
5736 | } | |
5737 | ||
ea8ceb83 JK |
5738 | static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) |
5739 | { | |
5740 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5741 | PIN_BASED_NMI_EXITING; | |
5742 | } | |
5743 | ||
c9a7953f | 5744 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 5745 | { |
47c0152e PB |
5746 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
5747 | CPU_BASED_VIRTUAL_INTR_PENDING); | |
3b86cd99 JK |
5748 | } |
5749 | ||
c9a7953f | 5750 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 5751 | { |
d02fcf50 | 5752 | if (!enable_vnmi || |
8a1b4392 | 5753 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { |
c9a7953f JK |
5754 | enable_irq_window(vcpu); |
5755 | return; | |
5756 | } | |
3b86cd99 | 5757 | |
47c0152e PB |
5758 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
5759 | CPU_BASED_VIRTUAL_NMI_PENDING); | |
3b86cd99 JK |
5760 | } |
5761 | ||
66fd3f7f | 5762 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 5763 | { |
9c8cba37 | 5764 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
5765 | uint32_t intr; |
5766 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 5767 | |
229456fc | 5768 | trace_kvm_inj_virq(irq); |
2714d1d3 | 5769 | |
fa89a817 | 5770 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 5771 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
5772 | int inc_eip = 0; |
5773 | if (vcpu->arch.interrupt.soft) | |
5774 | inc_eip = vcpu->arch.event_exit_inst_len; | |
5775 | if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) | |
a92601bb | 5776 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
85f455f7 ED |
5777 | return; |
5778 | } | |
66fd3f7f GN |
5779 | intr = irq | INTR_INFO_VALID_MASK; |
5780 | if (vcpu->arch.interrupt.soft) { | |
5781 | intr |= INTR_TYPE_SOFT_INTR; | |
5782 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
5783 | vmx->vcpu.arch.event_exit_inst_len); | |
5784 | } else | |
5785 | intr |= INTR_TYPE_EXT_INTR; | |
5786 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
85f455f7 ED |
5787 | } |
5788 | ||
f08864b4 SY |
5789 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
5790 | { | |
66a5a347 JK |
5791 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5792 | ||
d02fcf50 | 5793 | if (!enable_vnmi) { |
8a1b4392 PB |
5794 | /* |
5795 | * Tracking the NMI-blocked state in software is built upon | |
5796 | * finding the next open IRQ window. This, in turn, depends on | |
5797 | * well-behaving guests: They have to keep IRQs disabled at | |
5798 | * least as long as the NMI handler runs. Otherwise we may | |
5799 | * cause NMI nesting, maybe breaking the guest. But as this is | |
5800 | * highly unlikely, we can live with the residual risk. | |
5801 | */ | |
5802 | vmx->loaded_vmcs->soft_vnmi_blocked = 1; | |
5803 | vmx->loaded_vmcs->vnmi_blocked_time = 0; | |
5804 | } | |
5805 | ||
4c4a6f79 PB |
5806 | ++vcpu->stat.nmi_injections; |
5807 | vmx->loaded_vmcs->nmi_known_unmasked = false; | |
3b86cd99 | 5808 | |
7ffd92c5 | 5809 | if (vmx->rmode.vm86_active) { |
71f9833b | 5810 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) |
a92601bb | 5811 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
66a5a347 JK |
5812 | return; |
5813 | } | |
c5a6d5f7 | 5814 | |
f08864b4 SY |
5815 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
5816 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
5817 | } |
5818 | ||
3cfc3092 JK |
5819 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
5820 | { | |
4c4a6f79 PB |
5821 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5822 | bool masked; | |
5823 | ||
d02fcf50 | 5824 | if (!enable_vnmi) |
8a1b4392 | 5825 | return vmx->loaded_vmcs->soft_vnmi_blocked; |
4c4a6f79 | 5826 | if (vmx->loaded_vmcs->nmi_known_unmasked) |
9d58b931 | 5827 | return false; |
4c4a6f79 PB |
5828 | masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
5829 | vmx->loaded_vmcs->nmi_known_unmasked = !masked; | |
5830 | return masked; | |
3cfc3092 JK |
5831 | } |
5832 | ||
5833 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
5834 | { | |
5835 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5836 | ||
d02fcf50 | 5837 | if (!enable_vnmi) { |
8a1b4392 PB |
5838 | if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { |
5839 | vmx->loaded_vmcs->soft_vnmi_blocked = masked; | |
5840 | vmx->loaded_vmcs->vnmi_blocked_time = 0; | |
5841 | } | |
5842 | } else { | |
5843 | vmx->loaded_vmcs->nmi_known_unmasked = !masked; | |
5844 | if (masked) | |
5845 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5846 | GUEST_INTR_STATE_NMI); | |
5847 | else | |
5848 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5849 | GUEST_INTR_STATE_NMI); | |
5850 | } | |
3cfc3092 JK |
5851 | } |
5852 | ||
2505dc9f JK |
5853 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
5854 | { | |
b6b8a145 JK |
5855 | if (to_vmx(vcpu)->nested.nested_run_pending) |
5856 | return 0; | |
ea8ceb83 | 5857 | |
d02fcf50 | 5858 | if (!enable_vnmi && |
8a1b4392 PB |
5859 | to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) |
5860 | return 0; | |
5861 | ||
2505dc9f JK |
5862 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
5863 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | |
5864 | | GUEST_INTR_STATE_NMI)); | |
5865 | } | |
5866 | ||
78646121 GN |
5867 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
5868 | { | |
b6b8a145 JK |
5869 | return (!to_vmx(vcpu)->nested.nested_run_pending && |
5870 | vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
c4282df9 GN |
5871 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
5872 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
5873 | } |
5874 | ||
cbc94022 IE |
5875 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
5876 | { | |
5877 | int ret; | |
cbc94022 | 5878 | |
1d8007bd PB |
5879 | ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, |
5880 | PAGE_SIZE * 3); | |
cbc94022 IE |
5881 | if (ret) |
5882 | return ret; | |
bfc6d222 | 5883 | kvm->arch.tss_addr = addr; |
1f755a82 | 5884 | return init_rmode_tss(kvm); |
cbc94022 IE |
5885 | } |
5886 | ||
0ca1b4f4 | 5887 | static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) |
6aa8b732 | 5888 | { |
77ab6db0 | 5889 | switch (vec) { |
77ab6db0 | 5890 | case BP_VECTOR: |
c573cd22 JK |
5891 | /* |
5892 | * Update instruction length as we may reinject the exception | |
5893 | * from user space while in guest debugging mode. | |
5894 | */ | |
5895 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
5896 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 | 5897 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
0ca1b4f4 GN |
5898 | return false; |
5899 | /* fall through */ | |
5900 | case DB_VECTOR: | |
5901 | if (vcpu->guest_debug & | |
5902 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
5903 | return false; | |
d0bfb940 JK |
5904 | /* fall through */ |
5905 | case DE_VECTOR: | |
77ab6db0 JK |
5906 | case OF_VECTOR: |
5907 | case BR_VECTOR: | |
5908 | case UD_VECTOR: | |
5909 | case DF_VECTOR: | |
5910 | case SS_VECTOR: | |
5911 | case GP_VECTOR: | |
5912 | case MF_VECTOR: | |
0ca1b4f4 GN |
5913 | return true; |
5914 | break; | |
77ab6db0 | 5915 | } |
0ca1b4f4 GN |
5916 | return false; |
5917 | } | |
5918 | ||
5919 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
5920 | int vec, u32 err_code) | |
5921 | { | |
5922 | /* | |
5923 | * Instruction with address size override prefix opcode 0x67 | |
5924 | * Cause the #SS fault with 0 error code in VM86 mode. | |
5925 | */ | |
5926 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { | |
5927 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) { | |
5928 | if (vcpu->arch.halt_request) { | |
5929 | vcpu->arch.halt_request = 0; | |
5cb56059 | 5930 | return kvm_vcpu_halt(vcpu); |
0ca1b4f4 GN |
5931 | } |
5932 | return 1; | |
5933 | } | |
5934 | return 0; | |
5935 | } | |
5936 | ||
5937 | /* | |
5938 | * Forward all other exceptions that are valid in real mode. | |
5939 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
5940 | * the required debugging infrastructure rework. | |
5941 | */ | |
5942 | kvm_queue_exception(vcpu, vec); | |
5943 | return 1; | |
6aa8b732 AK |
5944 | } |
5945 | ||
a0861c02 AK |
5946 | /* |
5947 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
5948 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
5949 | * We pass a fake environment to the machine check handler because we want | |
5950 | * the guest to be always treated like user space, no matter what context | |
5951 | * it used internally. | |
5952 | */ | |
5953 | static void kvm_machine_check(void) | |
5954 | { | |
5955 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
5956 | struct pt_regs regs = { | |
5957 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
5958 | .flags = X86_EFLAGS_IF, | |
5959 | }; | |
5960 | ||
5961 | do_machine_check(®s, 0); | |
5962 | #endif | |
5963 | } | |
5964 | ||
851ba692 | 5965 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
5966 | { |
5967 | /* already handled by vcpu_run */ | |
5968 | return 1; | |
5969 | } | |
5970 | ||
851ba692 | 5971 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 5972 | { |
1155f76a | 5973 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 5974 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 5975 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 5976 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
5977 | u32 vect_info; |
5978 | enum emulation_result er; | |
5979 | ||
1155f76a | 5980 | vect_info = vmx->idt_vectoring_info; |
88786475 | 5981 | intr_info = vmx->exit_intr_info; |
6aa8b732 | 5982 | |
a0861c02 | 5983 | if (is_machine_check(intr_info)) |
851ba692 | 5984 | return handle_machine_check(vcpu); |
a0861c02 | 5985 | |
ef85b673 | 5986 | if (is_nmi(intr_info)) |
1b6269db | 5987 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc | 5988 | |
7aa81cc0 | 5989 | if (is_invalid_opcode(intr_info)) { |
51d8b661 | 5990 | er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD); |
61cb57c9 LA |
5991 | if (er == EMULATE_USER_EXIT) |
5992 | return 0; | |
7aa81cc0 | 5993 | if (er != EMULATE_DONE) |
7ee5d940 | 5994 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
5995 | return 1; |
5996 | } | |
5997 | ||
6aa8b732 | 5998 | error_code = 0; |
2e11384c | 5999 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 | 6000 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
bf4ca23e XG |
6001 | |
6002 | /* | |
6003 | * The #PF with PFEC.RSVD = 1 indicates the guest is accessing | |
6004 | * MMIO, it is better to report an internal error. | |
6005 | * See the comments in vmx_handle_exit. | |
6006 | */ | |
6007 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
6008 | !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { | |
6009 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6010 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
80f0e95d | 6011 | vcpu->run->internal.ndata = 3; |
bf4ca23e XG |
6012 | vcpu->run->internal.data[0] = vect_info; |
6013 | vcpu->run->internal.data[1] = intr_info; | |
80f0e95d | 6014 | vcpu->run->internal.data[2] = error_code; |
bf4ca23e XG |
6015 | return 0; |
6016 | } | |
6017 | ||
6aa8b732 AK |
6018 | if (is_page_fault(intr_info)) { |
6019 | cr2 = vmcs_readl(EXIT_QUALIFICATION); | |
1261bfa3 WL |
6020 | /* EPT won't cause page fault directly */ |
6021 | WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); | |
d0006530 | 6022 | return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); |
6aa8b732 AK |
6023 | } |
6024 | ||
d0bfb940 | 6025 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
0ca1b4f4 GN |
6026 | |
6027 | if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) | |
6028 | return handle_rmode_exception(vcpu, ex_no, error_code); | |
6029 | ||
42dbaa5a | 6030 | switch (ex_no) { |
54a20552 EN |
6031 | case AC_VECTOR: |
6032 | kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); | |
6033 | return 1; | |
42dbaa5a JK |
6034 | case DB_VECTOR: |
6035 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
6036 | if (!(vcpu->guest_debug & | |
6037 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
8246bf52 | 6038 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 6039 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
fd2a445a HD |
6040 | if (!(dr6 & ~DR6_RESERVED)) /* icebp */ |
6041 | skip_emulated_instruction(vcpu); | |
6042 | ||
42dbaa5a JK |
6043 | kvm_queue_exception(vcpu, DB_VECTOR); |
6044 | return 1; | |
6045 | } | |
6046 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
6047 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
6048 | /* fall through */ | |
6049 | case BP_VECTOR: | |
c573cd22 JK |
6050 | /* |
6051 | * Update instruction length as we may reinject #BP from | |
6052 | * user space while in guest debugging mode. Reading it for | |
6053 | * #DB as well causes no harm, it is not used in that case. | |
6054 | */ | |
6055 | vmx->vcpu.arch.event_exit_inst_len = | |
6056 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 6057 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 6058 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
6059 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
6060 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
6061 | break; |
6062 | default: | |
d0bfb940 JK |
6063 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
6064 | kvm_run->ex.exception = ex_no; | |
6065 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 6066 | break; |
6aa8b732 | 6067 | } |
6aa8b732 AK |
6068 | return 0; |
6069 | } | |
6070 | ||
851ba692 | 6071 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 6072 | { |
1165f5fe | 6073 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
6074 | return 1; |
6075 | } | |
6076 | ||
851ba692 | 6077 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 6078 | { |
851ba692 | 6079 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 6080 | vcpu->mmio_needed = 0; |
988ad74f AK |
6081 | return 0; |
6082 | } | |
6aa8b732 | 6083 | |
851ba692 | 6084 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 6085 | { |
bfdaab09 | 6086 | unsigned long exit_qualification; |
6affcbed | 6087 | int size, in, string, ret; |
039576c0 | 6088 | unsigned port; |
6aa8b732 | 6089 | |
bfdaab09 | 6090 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 6091 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 6092 | in = (exit_qualification & 8) != 0; |
e70669ab | 6093 | |
cf8f70bf | 6094 | ++vcpu->stat.io_exits; |
e70669ab | 6095 | |
cf8f70bf | 6096 | if (string || in) |
51d8b661 | 6097 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 6098 | |
cf8f70bf GN |
6099 | port = exit_qualification >> 16; |
6100 | size = (exit_qualification & 7) + 1; | |
cf8f70bf | 6101 | |
6affcbed KH |
6102 | ret = kvm_skip_emulated_instruction(vcpu); |
6103 | ||
6104 | /* | |
6105 | * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered | |
6106 | * KVM_EXIT_DEBUG here. | |
6107 | */ | |
6108 | return kvm_fast_pio_out(vcpu, size, port) && ret; | |
6aa8b732 AK |
6109 | } |
6110 | ||
102d8325 IM |
6111 | static void |
6112 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
6113 | { | |
6114 | /* | |
6115 | * Patch in the VMCALL instruction: | |
6116 | */ | |
6117 | hypercall[0] = 0x0f; | |
6118 | hypercall[1] = 0x01; | |
6119 | hypercall[2] = 0xc1; | |
102d8325 IM |
6120 | } |
6121 | ||
0fa06071 | 6122 | /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ |
eeadf9e7 NHE |
6123 | static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) |
6124 | { | |
eeadf9e7 | 6125 | if (is_guest_mode(vcpu)) { |
1a0d74e6 JK |
6126 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
6127 | unsigned long orig_val = val; | |
6128 | ||
eeadf9e7 NHE |
6129 | /* |
6130 | * We get here when L2 changed cr0 in a way that did not change | |
6131 | * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), | |
1a0d74e6 JK |
6132 | * but did change L0 shadowed bits. So we first calculate the |
6133 | * effective cr0 value that L1 would like to write into the | |
6134 | * hardware. It consists of the L2-owned bits from the new | |
6135 | * value combined with the L1-owned bits from L1's guest_cr0. | |
eeadf9e7 | 6136 | */ |
1a0d74e6 JK |
6137 | val = (val & ~vmcs12->cr0_guest_host_mask) | |
6138 | (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); | |
6139 | ||
3899152c | 6140 | if (!nested_guest_cr0_valid(vcpu, val)) |
eeadf9e7 | 6141 | return 1; |
1a0d74e6 JK |
6142 | |
6143 | if (kvm_set_cr0(vcpu, val)) | |
6144 | return 1; | |
6145 | vmcs_writel(CR0_READ_SHADOW, orig_val); | |
eeadf9e7 | 6146 | return 0; |
1a0d74e6 JK |
6147 | } else { |
6148 | if (to_vmx(vcpu)->nested.vmxon && | |
3899152c | 6149 | !nested_host_cr0_valid(vcpu, val)) |
1a0d74e6 | 6150 | return 1; |
3899152c | 6151 | |
eeadf9e7 | 6152 | return kvm_set_cr0(vcpu, val); |
1a0d74e6 | 6153 | } |
eeadf9e7 NHE |
6154 | } |
6155 | ||
6156 | static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) | |
6157 | { | |
6158 | if (is_guest_mode(vcpu)) { | |
1a0d74e6 JK |
6159 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
6160 | unsigned long orig_val = val; | |
6161 | ||
6162 | /* analogously to handle_set_cr0 */ | |
6163 | val = (val & ~vmcs12->cr4_guest_host_mask) | | |
6164 | (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); | |
6165 | if (kvm_set_cr4(vcpu, val)) | |
eeadf9e7 | 6166 | return 1; |
1a0d74e6 | 6167 | vmcs_writel(CR4_READ_SHADOW, orig_val); |
eeadf9e7 NHE |
6168 | return 0; |
6169 | } else | |
6170 | return kvm_set_cr4(vcpu, val); | |
6171 | } | |
6172 | ||
851ba692 | 6173 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6174 | { |
229456fc | 6175 | unsigned long exit_qualification, val; |
6aa8b732 AK |
6176 | int cr; |
6177 | int reg; | |
49a9b07e | 6178 | int err; |
6affcbed | 6179 | int ret; |
6aa8b732 | 6180 | |
bfdaab09 | 6181 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
6182 | cr = exit_qualification & 15; |
6183 | reg = (exit_qualification >> 8) & 15; | |
6184 | switch ((exit_qualification >> 4) & 3) { | |
6185 | case 0: /* mov to cr */ | |
1e32c079 | 6186 | val = kvm_register_readl(vcpu, reg); |
229456fc | 6187 | trace_kvm_cr_write(cr, val); |
6aa8b732 AK |
6188 | switch (cr) { |
6189 | case 0: | |
eeadf9e7 | 6190 | err = handle_set_cr0(vcpu, val); |
6affcbed | 6191 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 6192 | case 3: |
2390218b | 6193 | err = kvm_set_cr3(vcpu, val); |
6affcbed | 6194 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 6195 | case 4: |
eeadf9e7 | 6196 | err = handle_set_cr4(vcpu, val); |
6affcbed | 6197 | return kvm_complete_insn_gp(vcpu, err); |
0a5fff19 GN |
6198 | case 8: { |
6199 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
1e32c079 | 6200 | u8 cr8 = (u8)val; |
eea1cff9 | 6201 | err = kvm_set_cr8(vcpu, cr8); |
6affcbed | 6202 | ret = kvm_complete_insn_gp(vcpu, err); |
35754c98 | 6203 | if (lapic_in_kernel(vcpu)) |
6affcbed | 6204 | return ret; |
0a5fff19 | 6205 | if (cr8_prev <= cr8) |
6affcbed KH |
6206 | return ret; |
6207 | /* | |
6208 | * TODO: we might be squashing a | |
6209 | * KVM_GUESTDBG_SINGLESTEP-triggered | |
6210 | * KVM_EXIT_DEBUG here. | |
6211 | */ | |
851ba692 | 6212 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
6213 | return 0; |
6214 | } | |
4b8073e4 | 6215 | } |
6aa8b732 | 6216 | break; |
25c4c276 | 6217 | case 2: /* clts */ |
bd7e5b08 PB |
6218 | WARN_ONCE(1, "Guest should always own CR0.TS"); |
6219 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); | |
4d4ec087 | 6220 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
6affcbed | 6221 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6222 | case 1: /*mov from cr*/ |
6223 | switch (cr) { | |
6224 | case 3: | |
9f8fe504 AK |
6225 | val = kvm_read_cr3(vcpu); |
6226 | kvm_register_write(vcpu, reg, val); | |
6227 | trace_kvm_cr_read(cr, val); | |
6affcbed | 6228 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 | 6229 | case 8: |
229456fc MT |
6230 | val = kvm_get_cr8(vcpu); |
6231 | kvm_register_write(vcpu, reg, val); | |
6232 | trace_kvm_cr_read(cr, val); | |
6affcbed | 6233 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6234 | } |
6235 | break; | |
6236 | case 3: /* lmsw */ | |
a1f83a74 | 6237 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 6238 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 6239 | kvm_lmsw(vcpu, val); |
6aa8b732 | 6240 | |
6affcbed | 6241 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6242 | default: |
6243 | break; | |
6244 | } | |
851ba692 | 6245 | vcpu->run->exit_reason = 0; |
a737f256 | 6246 | vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
6247 | (int)(exit_qualification >> 4) & 3, cr); |
6248 | return 0; | |
6249 | } | |
6250 | ||
851ba692 | 6251 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6252 | { |
bfdaab09 | 6253 | unsigned long exit_qualification; |
16f8a6f9 NA |
6254 | int dr, dr7, reg; |
6255 | ||
6256 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6257 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; | |
6258 | ||
6259 | /* First, if DR does not exist, trigger UD */ | |
6260 | if (!kvm_require_dr(vcpu, dr)) | |
6261 | return 1; | |
6aa8b732 | 6262 | |
f2483415 | 6263 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
6264 | if (!kvm_require_cpl(vcpu, 0)) |
6265 | return 1; | |
16f8a6f9 NA |
6266 | dr7 = vmcs_readl(GUEST_DR7); |
6267 | if (dr7 & DR7_GD) { | |
42dbaa5a JK |
6268 | /* |
6269 | * As the vm-exit takes precedence over the debug trap, we | |
6270 | * need to emulate the latter, either for the host or the | |
6271 | * guest debugging itself. | |
6272 | */ | |
6273 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 | 6274 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
16f8a6f9 | 6275 | vcpu->run->debug.arch.dr7 = dr7; |
82b32774 | 6276 | vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
851ba692 AK |
6277 | vcpu->run->debug.arch.exception = DB_VECTOR; |
6278 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
6279 | return 0; |
6280 | } else { | |
7305eb5d | 6281 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 6282 | vcpu->arch.dr6 |= DR6_BD | DR6_RTM; |
42dbaa5a JK |
6283 | kvm_queue_exception(vcpu, DB_VECTOR); |
6284 | return 1; | |
6285 | } | |
6286 | } | |
6287 | ||
81908bf4 | 6288 | if (vcpu->guest_debug == 0) { |
8f22372f PB |
6289 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6290 | CPU_BASED_MOV_DR_EXITING); | |
81908bf4 PB |
6291 | |
6292 | /* | |
6293 | * No more DR vmexits; force a reload of the debug registers | |
6294 | * and reenter on this instruction. The next vmexit will | |
6295 | * retrieve the full state of the debug registers. | |
6296 | */ | |
6297 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
6298 | return 1; | |
6299 | } | |
6300 | ||
42dbaa5a JK |
6301 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); |
6302 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 | 6303 | unsigned long val; |
4c4d563b JK |
6304 | |
6305 | if (kvm_get_dr(vcpu, dr, &val)) | |
6306 | return 1; | |
6307 | kvm_register_write(vcpu, reg, val); | |
020df079 | 6308 | } else |
5777392e | 6309 | if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) |
4c4d563b JK |
6310 | return 1; |
6311 | ||
6affcbed | 6312 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6313 | } |
6314 | ||
73aaf249 JK |
6315 | static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) |
6316 | { | |
6317 | return vcpu->arch.dr6; | |
6318 | } | |
6319 | ||
6320 | static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) | |
6321 | { | |
6322 | } | |
6323 | ||
81908bf4 PB |
6324 | static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
6325 | { | |
81908bf4 PB |
6326 | get_debugreg(vcpu->arch.db[0], 0); |
6327 | get_debugreg(vcpu->arch.db[1], 1); | |
6328 | get_debugreg(vcpu->arch.db[2], 2); | |
6329 | get_debugreg(vcpu->arch.db[3], 3); | |
6330 | get_debugreg(vcpu->arch.dr6, 6); | |
6331 | vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); | |
6332 | ||
6333 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
8f22372f | 6334 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING); |
81908bf4 PB |
6335 | } |
6336 | ||
020df079 GN |
6337 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
6338 | { | |
6339 | vmcs_writel(GUEST_DR7, val); | |
6340 | } | |
6341 | ||
851ba692 | 6342 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 6343 | { |
6a908b62 | 6344 | return kvm_emulate_cpuid(vcpu); |
6aa8b732 AK |
6345 | } |
6346 | ||
851ba692 | 6347 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6348 | { |
ad312c7c | 6349 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
609e36d3 | 6350 | struct msr_data msr_info; |
6aa8b732 | 6351 | |
609e36d3 PB |
6352 | msr_info.index = ecx; |
6353 | msr_info.host_initiated = false; | |
6354 | if (vmx_get_msr(vcpu, &msr_info)) { | |
59200273 | 6355 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 6356 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6357 | return 1; |
6358 | } | |
6359 | ||
609e36d3 | 6360 | trace_kvm_msr_read(ecx, msr_info.data); |
2714d1d3 | 6361 | |
6aa8b732 | 6362 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
609e36d3 PB |
6363 | vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u; |
6364 | vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u; | |
6affcbed | 6365 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6366 | } |
6367 | ||
851ba692 | 6368 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6369 | { |
8fe8ab46 | 6370 | struct msr_data msr; |
ad312c7c ZX |
6371 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6372 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
6373 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 6374 | |
8fe8ab46 WA |
6375 | msr.data = data; |
6376 | msr.index = ecx; | |
6377 | msr.host_initiated = false; | |
854e8bb1 | 6378 | if (kvm_set_msr(vcpu, &msr) != 0) { |
59200273 | 6379 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 6380 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6381 | return 1; |
6382 | } | |
6383 | ||
59200273 | 6384 | trace_kvm_msr_write(ecx, data); |
6affcbed | 6385 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6386 | } |
6387 | ||
851ba692 | 6388 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 6389 | { |
eb90f341 | 6390 | kvm_apic_update_ppr(vcpu); |
6e5d865c YS |
6391 | return 1; |
6392 | } | |
6393 | ||
851ba692 | 6394 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 6395 | { |
47c0152e PB |
6396 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6397 | CPU_BASED_VIRTUAL_INTR_PENDING); | |
2714d1d3 | 6398 | |
3842d135 AK |
6399 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6400 | ||
a26bf12a | 6401 | ++vcpu->stat.irq_window_exits; |
6aa8b732 AK |
6402 | return 1; |
6403 | } | |
6404 | ||
851ba692 | 6405 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 | 6406 | { |
d3bef15f | 6407 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
6408 | } |
6409 | ||
851ba692 | 6410 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 6411 | { |
0d9c055e | 6412 | return kvm_emulate_hypercall(vcpu); |
c21415e8 IM |
6413 | } |
6414 | ||
ec25d5e6 GN |
6415 | static int handle_invd(struct kvm_vcpu *vcpu) |
6416 | { | |
51d8b661 | 6417 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
6418 | } |
6419 | ||
851ba692 | 6420 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 6421 | { |
f9c617f6 | 6422 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
6423 | |
6424 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
6affcbed | 6425 | return kvm_skip_emulated_instruction(vcpu); |
a7052897 MT |
6426 | } |
6427 | ||
fee84b07 AK |
6428 | static int handle_rdpmc(struct kvm_vcpu *vcpu) |
6429 | { | |
6430 | int err; | |
6431 | ||
6432 | err = kvm_rdpmc(vcpu); | |
6affcbed | 6433 | return kvm_complete_insn_gp(vcpu, err); |
fee84b07 AK |
6434 | } |
6435 | ||
851ba692 | 6436 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 | 6437 | { |
6affcbed | 6438 | return kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
6439 | } |
6440 | ||
2acf923e DC |
6441 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
6442 | { | |
6443 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
6444 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6445 | ||
6446 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
6affcbed | 6447 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e DC |
6448 | return 1; |
6449 | } | |
6450 | ||
f53cd63c WL |
6451 | static int handle_xsaves(struct kvm_vcpu *vcpu) |
6452 | { | |
6affcbed | 6453 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6454 | WARN(1, "this should never happen\n"); |
6455 | return 1; | |
6456 | } | |
6457 | ||
6458 | static int handle_xrstors(struct kvm_vcpu *vcpu) | |
6459 | { | |
6affcbed | 6460 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6461 | WARN(1, "this should never happen\n"); |
6462 | return 1; | |
6463 | } | |
6464 | ||
851ba692 | 6465 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 6466 | { |
58fbbf26 KT |
6467 | if (likely(fasteoi)) { |
6468 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6469 | int access_type, offset; | |
6470 | ||
6471 | access_type = exit_qualification & APIC_ACCESS_TYPE; | |
6472 | offset = exit_qualification & APIC_ACCESS_OFFSET; | |
6473 | /* | |
6474 | * Sane guest uses MOV to write EOI, with written value | |
6475 | * not cared. So make a short-circuit here by avoiding | |
6476 | * heavy instruction emulation. | |
6477 | */ | |
6478 | if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && | |
6479 | (offset == APIC_EOI)) { | |
6480 | kvm_lapic_set_eoi(vcpu); | |
6affcbed | 6481 | return kvm_skip_emulated_instruction(vcpu); |
58fbbf26 KT |
6482 | } |
6483 | } | |
51d8b661 | 6484 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
6485 | } |
6486 | ||
c7c9c56c YZ |
6487 | static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) |
6488 | { | |
6489 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6490 | int vector = exit_qualification & 0xff; | |
6491 | ||
6492 | /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ | |
6493 | kvm_apic_set_eoi_accelerated(vcpu, vector); | |
6494 | return 1; | |
6495 | } | |
6496 | ||
83d4c286 YZ |
6497 | static int handle_apic_write(struct kvm_vcpu *vcpu) |
6498 | { | |
6499 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6500 | u32 offset = exit_qualification & 0xfff; | |
6501 | ||
6502 | /* APIC-write VM exit is trap-like and thus no need to adjust IP */ | |
6503 | kvm_apic_write_nodecode(vcpu, offset); | |
6504 | return 1; | |
6505 | } | |
6506 | ||
851ba692 | 6507 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 6508 | { |
60637aac | 6509 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 6510 | unsigned long exit_qualification; |
e269fb21 JK |
6511 | bool has_error_code = false; |
6512 | u32 error_code = 0; | |
37817f29 | 6513 | u16 tss_selector; |
7f3d35fd | 6514 | int reason, type, idt_v, idt_index; |
64a7ec06 GN |
6515 | |
6516 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
7f3d35fd | 6517 | idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); |
64a7ec06 | 6518 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); |
37817f29 IE |
6519 | |
6520 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6521 | ||
6522 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
6523 | if (reason == TASK_SWITCH_GATE && idt_v) { |
6524 | switch (type) { | |
6525 | case INTR_TYPE_NMI_INTR: | |
6526 | vcpu->arch.nmi_injected = false; | |
654f06fc | 6527 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
6528 | break; |
6529 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 6530 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
6531 | kvm_clear_interrupt_queue(vcpu); |
6532 | break; | |
6533 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
6534 | if (vmx->idt_vectoring_info & |
6535 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
6536 | has_error_code = true; | |
6537 | error_code = | |
6538 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
6539 | } | |
6540 | /* fall through */ | |
64a7ec06 GN |
6541 | case INTR_TYPE_SOFT_EXCEPTION: |
6542 | kvm_clear_exception_queue(vcpu); | |
6543 | break; | |
6544 | default: | |
6545 | break; | |
6546 | } | |
60637aac | 6547 | } |
37817f29 IE |
6548 | tss_selector = exit_qualification; |
6549 | ||
64a7ec06 GN |
6550 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
6551 | type != INTR_TYPE_EXT_INTR && | |
6552 | type != INTR_TYPE_NMI_INTR)) | |
6553 | skip_emulated_instruction(vcpu); | |
6554 | ||
7f3d35fd KW |
6555 | if (kvm_task_switch(vcpu, tss_selector, |
6556 | type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason, | |
6557 | has_error_code, error_code) == EMULATE_FAIL) { | |
acb54517 GN |
6558 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
6559 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6560 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 6561 | return 0; |
acb54517 | 6562 | } |
42dbaa5a | 6563 | |
42dbaa5a JK |
6564 | /* |
6565 | * TODO: What about debug traps on tss switch? | |
6566 | * Are we supposed to inject them and update dr6? | |
6567 | */ | |
6568 | ||
6569 | return 1; | |
37817f29 IE |
6570 | } |
6571 | ||
851ba692 | 6572 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 6573 | { |
f9c617f6 | 6574 | unsigned long exit_qualification; |
1439442c | 6575 | gpa_t gpa; |
eebed243 | 6576 | u64 error_code; |
1439442c | 6577 | |
f9c617f6 | 6578 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c | 6579 | |
0be9c7a8 GN |
6580 | /* |
6581 | * EPT violation happened while executing iret from NMI, | |
6582 | * "blocked by NMI" bit has to be set before next VM entry. | |
6583 | * There are errata that may cause this bit to not be set: | |
6584 | * AAK134, BY25. | |
6585 | */ | |
bcd1c294 | 6586 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && |
d02fcf50 | 6587 | enable_vnmi && |
bcd1c294 | 6588 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
0be9c7a8 GN |
6589 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); |
6590 | ||
1439442c | 6591 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
229456fc | 6592 | trace_kvm_page_fault(gpa, exit_qualification); |
4f5982a5 | 6593 | |
27959a44 | 6594 | /* Is it a read fault? */ |
ab22a473 | 6595 | error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) |
27959a44 JS |
6596 | ? PFERR_USER_MASK : 0; |
6597 | /* Is it a write fault? */ | |
ab22a473 | 6598 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) |
27959a44 JS |
6599 | ? PFERR_WRITE_MASK : 0; |
6600 | /* Is it a fetch fault? */ | |
ab22a473 | 6601 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) |
27959a44 JS |
6602 | ? PFERR_FETCH_MASK : 0; |
6603 | /* ept page table entry is present? */ | |
6604 | error_code |= (exit_qualification & | |
6605 | (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | | |
6606 | EPT_VIOLATION_EXECUTABLE)) | |
6607 | ? PFERR_PRESENT_MASK : 0; | |
4f5982a5 | 6608 | |
eebed243 PB |
6609 | error_code |= (exit_qualification & 0x100) != 0 ? |
6610 | PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; | |
25d92081 | 6611 | |
25d92081 | 6612 | vcpu->arch.exit_qualification = exit_qualification; |
4f5982a5 | 6613 | return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); |
1439442c SY |
6614 | } |
6615 | ||
851ba692 | 6616 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 | 6617 | { |
f735d4af | 6618 | int ret; |
68f89400 MT |
6619 | gpa_t gpa; |
6620 | ||
9034e6e8 PB |
6621 | /* |
6622 | * A nested guest cannot optimize MMIO vmexits, because we have an | |
6623 | * nGPA here instead of the required GPA. | |
6624 | */ | |
68f89400 | 6625 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
9034e6e8 PB |
6626 | if (!is_guest_mode(vcpu) && |
6627 | !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { | |
931c33b1 | 6628 | trace_kvm_fast_mmio(gpa); |
6affcbed | 6629 | return kvm_skip_emulated_instruction(vcpu); |
68c3b4d1 | 6630 | } |
68f89400 | 6631 | |
e08d26f0 PB |
6632 | ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); |
6633 | if (ret >= 0) | |
6634 | return ret; | |
ce88decf XG |
6635 | |
6636 | /* It is the real ept misconfig */ | |
f735d4af | 6637 | WARN_ON(1); |
68f89400 | 6638 | |
851ba692 AK |
6639 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
6640 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
6641 | |
6642 | return 0; | |
6643 | } | |
6644 | ||
851ba692 | 6645 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 | 6646 | { |
d02fcf50 | 6647 | WARN_ON_ONCE(!enable_vnmi); |
47c0152e PB |
6648 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6649 | CPU_BASED_VIRTUAL_NMI_PENDING); | |
f08864b4 | 6650 | ++vcpu->stat.nmi_window_exits; |
3842d135 | 6651 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
6652 | |
6653 | return 1; | |
6654 | } | |
6655 | ||
80ced186 | 6656 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 6657 | { |
8b3079a5 AK |
6658 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6659 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 6660 | int ret = 1; |
49e9d557 AK |
6661 | u32 cpu_exec_ctrl; |
6662 | bool intr_window_requested; | |
b8405c18 | 6663 | unsigned count = 130; |
49e9d557 AK |
6664 | |
6665 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
6666 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 | 6667 | |
98eb2f8b | 6668 | while (vmx->emulation_required && count-- != 0) { |
bdea48e3 | 6669 | if (intr_window_requested && vmx_interrupt_allowed(vcpu)) |
49e9d557 AK |
6670 | return handle_interrupt_window(&vmx->vcpu); |
6671 | ||
72875d8a | 6672 | if (kvm_test_request(KVM_REQ_EVENT, vcpu)) |
de87dcdd AK |
6673 | return 1; |
6674 | ||
9b8ae637 | 6675 | err = emulate_instruction(vcpu, 0); |
ea953ef0 | 6676 | |
ac0a48c3 | 6677 | if (err == EMULATE_USER_EXIT) { |
94452b9e | 6678 | ++vcpu->stat.mmio_exits; |
80ced186 MG |
6679 | ret = 0; |
6680 | goto out; | |
6681 | } | |
1d5a4d9b | 6682 | |
de5f70e0 AK |
6683 | if (err != EMULATE_DONE) { |
6684 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6685 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6686 | vcpu->run->internal.ndata = 0; | |
6d77dbfc | 6687 | return 0; |
de5f70e0 | 6688 | } |
ea953ef0 | 6689 | |
8d76c49e GN |
6690 | if (vcpu->arch.halt_request) { |
6691 | vcpu->arch.halt_request = 0; | |
5cb56059 | 6692 | ret = kvm_vcpu_halt(vcpu); |
8d76c49e GN |
6693 | goto out; |
6694 | } | |
6695 | ||
ea953ef0 | 6696 | if (signal_pending(current)) |
80ced186 | 6697 | goto out; |
ea953ef0 MG |
6698 | if (need_resched()) |
6699 | schedule(); | |
6700 | } | |
6701 | ||
80ced186 MG |
6702 | out: |
6703 | return ret; | |
ea953ef0 MG |
6704 | } |
6705 | ||
b4a2d31d RK |
6706 | static int __grow_ple_window(int val) |
6707 | { | |
6708 | if (ple_window_grow < 1) | |
6709 | return ple_window; | |
6710 | ||
6711 | val = min(val, ple_window_actual_max); | |
6712 | ||
6713 | if (ple_window_grow < ple_window) | |
6714 | val *= ple_window_grow; | |
6715 | else | |
6716 | val += ple_window_grow; | |
6717 | ||
6718 | return val; | |
6719 | } | |
6720 | ||
6721 | static int __shrink_ple_window(int val, int modifier, int minimum) | |
6722 | { | |
6723 | if (modifier < 1) | |
6724 | return ple_window; | |
6725 | ||
6726 | if (modifier < ple_window) | |
6727 | val /= modifier; | |
6728 | else | |
6729 | val -= modifier; | |
6730 | ||
6731 | return max(val, minimum); | |
6732 | } | |
6733 | ||
6734 | static void grow_ple_window(struct kvm_vcpu *vcpu) | |
6735 | { | |
6736 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6737 | int old = vmx->ple_window; | |
6738 | ||
6739 | vmx->ple_window = __grow_ple_window(old); | |
6740 | ||
6741 | if (vmx->ple_window != old) | |
6742 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6743 | |
6744 | trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6745 | } |
6746 | ||
6747 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
6748 | { | |
6749 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6750 | int old = vmx->ple_window; | |
6751 | ||
6752 | vmx->ple_window = __shrink_ple_window(old, | |
6753 | ple_window_shrink, ple_window); | |
6754 | ||
6755 | if (vmx->ple_window != old) | |
6756 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6757 | |
6758 | trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6759 | } |
6760 | ||
6761 | /* | |
6762 | * ple_window_actual_max is computed to be one grow_ple_window() below | |
6763 | * ple_window_max. (See __grow_ple_window for the reason.) | |
6764 | * This prevents overflows, because ple_window_max is int. | |
6765 | * ple_window_max effectively rounded down to a multiple of ple_window_grow in | |
6766 | * this process. | |
6767 | * ple_window_max is also prevented from setting vmx->ple_window < ple_window. | |
6768 | */ | |
6769 | static void update_ple_window_actual_max(void) | |
6770 | { | |
6771 | ple_window_actual_max = | |
6772 | __shrink_ple_window(max(ple_window_max, ple_window), | |
6773 | ple_window_grow, INT_MIN); | |
6774 | } | |
6775 | ||
bf9f6ac8 FW |
6776 | /* |
6777 | * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. | |
6778 | */ | |
6779 | static void wakeup_handler(void) | |
6780 | { | |
6781 | struct kvm_vcpu *vcpu; | |
6782 | int cpu = smp_processor_id(); | |
6783 | ||
6784 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6785 | list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), | |
6786 | blocked_vcpu_list) { | |
6787 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
6788 | ||
6789 | if (pi_test_on(pi_desc) == 1) | |
6790 | kvm_vcpu_kick(vcpu); | |
6791 | } | |
6792 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6793 | } | |
6794 | ||
f160c7b7 JS |
6795 | void vmx_enable_tdp(void) |
6796 | { | |
6797 | kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, | |
6798 | enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, | |
6799 | enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, | |
6800 | 0ull, VMX_EPT_EXECUTABLE_MASK, | |
6801 | cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, | |
d0ec49d4 | 6802 | VMX_EPT_RWX_MASK, 0ull); |
f160c7b7 JS |
6803 | |
6804 | ept_set_mmio_spte_mask(); | |
6805 | kvm_enable_tdp(); | |
6806 | } | |
6807 | ||
f2c7648d TC |
6808 | static __init int hardware_setup(void) |
6809 | { | |
904e14fb | 6810 | int r = -ENOMEM, i; |
34a1cd60 TC |
6811 | |
6812 | rdmsrl_safe(MSR_EFER, &host_efer); | |
6813 | ||
6814 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) | |
6815 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
6816 | ||
23611332 RK |
6817 | for (i = 0; i < VMX_BITMAP_NR; i++) { |
6818 | vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6819 | if (!vmx_bitmap[i]) | |
6820 | goto out; | |
6821 | } | |
34a1cd60 | 6822 | |
34a1cd60 TC |
6823 | memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); |
6824 | memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); | |
6825 | ||
34a1cd60 | 6826 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); |
34a1cd60 TC |
6827 | |
6828 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); | |
6829 | ||
34a1cd60 TC |
6830 | if (setup_vmcs_config(&vmcs_config) < 0) { |
6831 | r = -EIO; | |
23611332 | 6832 | goto out; |
baa03522 | 6833 | } |
f2c7648d TC |
6834 | |
6835 | if (boot_cpu_has(X86_FEATURE_NX)) | |
6836 | kvm_enable_efer_bits(EFER_NX); | |
6837 | ||
08d839c4 WL |
6838 | if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || |
6839 | !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) | |
f2c7648d | 6840 | enable_vpid = 0; |
08d839c4 | 6841 | |
f2c7648d TC |
6842 | if (!cpu_has_vmx_shadow_vmcs()) |
6843 | enable_shadow_vmcs = 0; | |
6844 | if (enable_shadow_vmcs) | |
6845 | init_vmcs_shadow_fields(); | |
6846 | ||
6847 | if (!cpu_has_vmx_ept() || | |
42aa53b4 | 6848 | !cpu_has_vmx_ept_4levels() || |
f5f51586 | 6849 | !cpu_has_vmx_ept_mt_wb() || |
8ad8182e | 6850 | !cpu_has_vmx_invept_global()) |
f2c7648d | 6851 | enable_ept = 0; |
f2c7648d | 6852 | |
fce6ac4c | 6853 | if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) |
f2c7648d TC |
6854 | enable_ept_ad_bits = 0; |
6855 | ||
8ad8182e | 6856 | if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) |
f2c7648d TC |
6857 | enable_unrestricted_guest = 0; |
6858 | ||
ad15a296 | 6859 | if (!cpu_has_vmx_flexpriority()) |
f2c7648d TC |
6860 | flexpriority_enabled = 0; |
6861 | ||
d02fcf50 PB |
6862 | if (!cpu_has_virtual_nmis()) |
6863 | enable_vnmi = 0; | |
6864 | ||
ad15a296 PB |
6865 | /* |
6866 | * set_apic_access_page_addr() is used to reload apic access | |
6867 | * page upon invalidation. No need to do anything if not | |
6868 | * using the APIC_ACCESS_ADDR VMCS field. | |
6869 | */ | |
6870 | if (!flexpriority_enabled) | |
f2c7648d | 6871 | kvm_x86_ops->set_apic_access_page_addr = NULL; |
f2c7648d TC |
6872 | |
6873 | if (!cpu_has_vmx_tpr_shadow()) | |
6874 | kvm_x86_ops->update_cr8_intercept = NULL; | |
6875 | ||
6876 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) | |
6877 | kvm_disable_largepages(); | |
6878 | ||
0f107682 | 6879 | if (!cpu_has_vmx_ple()) { |
f2c7648d | 6880 | ple_gap = 0; |
0f107682 WL |
6881 | ple_window = 0; |
6882 | ple_window_grow = 0; | |
6883 | ple_window_max = 0; | |
6884 | ple_window_shrink = 0; | |
6885 | } | |
f2c7648d | 6886 | |
76dfafd5 | 6887 | if (!cpu_has_vmx_apicv()) { |
f2c7648d | 6888 | enable_apicv = 0; |
76dfafd5 PB |
6889 | kvm_x86_ops->sync_pir_to_irr = NULL; |
6890 | } | |
f2c7648d | 6891 | |
64903d61 HZ |
6892 | if (cpu_has_vmx_tsc_scaling()) { |
6893 | kvm_has_tsc_control = true; | |
6894 | kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; | |
6895 | kvm_tsc_scaling_ratio_frac_bits = 48; | |
6896 | } | |
6897 | ||
04bb92e4 WL |
6898 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
6899 | ||
f160c7b7 JS |
6900 | if (enable_ept) |
6901 | vmx_enable_tdp(); | |
6902 | else | |
baa03522 TC |
6903 | kvm_disable_tdp(); |
6904 | ||
6905 | update_ple_window_actual_max(); | |
6906 | ||
843e4330 KH |
6907 | /* |
6908 | * Only enable PML when hardware supports PML feature, and both EPT | |
6909 | * and EPT A/D bit features are enabled -- PML depends on them to work. | |
6910 | */ | |
6911 | if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) | |
6912 | enable_pml = 0; | |
6913 | ||
6914 | if (!enable_pml) { | |
6915 | kvm_x86_ops->slot_enable_log_dirty = NULL; | |
6916 | kvm_x86_ops->slot_disable_log_dirty = NULL; | |
6917 | kvm_x86_ops->flush_log_dirty = NULL; | |
6918 | kvm_x86_ops->enable_log_dirty_pt_masked = NULL; | |
6919 | } | |
6920 | ||
64672c95 YJ |
6921 | if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) { |
6922 | u64 vmx_msr; | |
6923 | ||
6924 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
6925 | cpu_preemption_timer_multi = | |
6926 | vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; | |
6927 | } else { | |
6928 | kvm_x86_ops->set_hv_timer = NULL; | |
6929 | kvm_x86_ops->cancel_hv_timer = NULL; | |
6930 | } | |
6931 | ||
bf9f6ac8 FW |
6932 | kvm_set_posted_intr_wakeup_handler(wakeup_handler); |
6933 | ||
c45dcc71 AR |
6934 | kvm_mce_cap_supported |= MCG_LMCE_P; |
6935 | ||
f2c7648d | 6936 | return alloc_kvm_area(); |
34a1cd60 | 6937 | |
34a1cd60 | 6938 | out: |
23611332 RK |
6939 | for (i = 0; i < VMX_BITMAP_NR; i++) |
6940 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 TC |
6941 | |
6942 | return r; | |
f2c7648d TC |
6943 | } |
6944 | ||
6945 | static __exit void hardware_unsetup(void) | |
6946 | { | |
23611332 RK |
6947 | int i; |
6948 | ||
6949 | for (i = 0; i < VMX_BITMAP_NR; i++) | |
6950 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 | 6951 | |
f2c7648d TC |
6952 | free_kvm_area(); |
6953 | } | |
6954 | ||
4b8d54f9 ZE |
6955 | /* |
6956 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
6957 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
6958 | */ | |
9fb41ba8 | 6959 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 | 6960 | { |
b4a2d31d RK |
6961 | if (ple_gap) |
6962 | grow_ple_window(vcpu); | |
6963 | ||
de63ad4c LM |
6964 | /* |
6965 | * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" | |
6966 | * VM-execution control is ignored if CPL > 0. OTOH, KVM | |
6967 | * never set PAUSE_EXITING and just set PLE if supported, | |
6968 | * so the vcpu must be CPL=0 if it gets a PAUSE exit. | |
6969 | */ | |
6970 | kvm_vcpu_on_spin(vcpu, true); | |
6affcbed | 6971 | return kvm_skip_emulated_instruction(vcpu); |
4b8d54f9 ZE |
6972 | } |
6973 | ||
87c00572 | 6974 | static int handle_nop(struct kvm_vcpu *vcpu) |
59708670 | 6975 | { |
6affcbed | 6976 | return kvm_skip_emulated_instruction(vcpu); |
59708670 SY |
6977 | } |
6978 | ||
87c00572 GS |
6979 | static int handle_mwait(struct kvm_vcpu *vcpu) |
6980 | { | |
6981 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
6982 | return handle_nop(vcpu); | |
6983 | } | |
6984 | ||
45ec368c JM |
6985 | static int handle_invalid_op(struct kvm_vcpu *vcpu) |
6986 | { | |
6987 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6988 | return 1; | |
6989 | } | |
6990 | ||
5f3d45e7 MD |
6991 | static int handle_monitor_trap(struct kvm_vcpu *vcpu) |
6992 | { | |
6993 | return 1; | |
6994 | } | |
6995 | ||
87c00572 GS |
6996 | static int handle_monitor(struct kvm_vcpu *vcpu) |
6997 | { | |
6998 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
6999 | return handle_nop(vcpu); | |
7000 | } | |
7001 | ||
0658fbaa ACL |
7002 | /* |
7003 | * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), | |
7004 | * set the success or error code of an emulated VMX instruction, as specified | |
7005 | * by Vol 2B, VMX Instruction Reference, "Conventions". | |
7006 | */ | |
7007 | static void nested_vmx_succeed(struct kvm_vcpu *vcpu) | |
7008 | { | |
7009 | vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) | |
7010 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
7011 | X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); | |
7012 | } | |
7013 | ||
7014 | static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu) | |
7015 | { | |
7016 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
7017 | & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | | |
7018 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
7019 | | X86_EFLAGS_CF); | |
7020 | } | |
7021 | ||
145c28dd | 7022 | static void nested_vmx_failValid(struct kvm_vcpu *vcpu, |
0658fbaa ACL |
7023 | u32 vm_instruction_error) |
7024 | { | |
7025 | if (to_vmx(vcpu)->nested.current_vmptr == -1ull) { | |
7026 | /* | |
7027 | * failValid writes the error number to the current VMCS, which | |
7028 | * can't be done there isn't a current VMCS. | |
7029 | */ | |
7030 | nested_vmx_failInvalid(vcpu); | |
7031 | return; | |
7032 | } | |
7033 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
7034 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
7035 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
7036 | | X86_EFLAGS_ZF); | |
7037 | get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; | |
7038 | /* | |
7039 | * We don't need to force a shadow sync because | |
7040 | * VM_INSTRUCTION_ERROR is not shadowed | |
7041 | */ | |
7042 | } | |
145c28dd | 7043 | |
ff651cb6 WV |
7044 | static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator) |
7045 | { | |
7046 | /* TODO: not to reset guest simply here. */ | |
7047 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
bbe41b95 | 7048 | pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator); |
ff651cb6 WV |
7049 | } |
7050 | ||
f4124500 JK |
7051 | static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) |
7052 | { | |
7053 | struct vcpu_vmx *vmx = | |
7054 | container_of(timer, struct vcpu_vmx, nested.preemption_timer); | |
7055 | ||
7056 | vmx->nested.preemption_timer_expired = true; | |
7057 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); | |
7058 | kvm_vcpu_kick(&vmx->vcpu); | |
7059 | ||
7060 | return HRTIMER_NORESTART; | |
7061 | } | |
7062 | ||
19677e32 BD |
7063 | /* |
7064 | * Decode the memory-address operand of a vmx instruction, as recorded on an | |
7065 | * exit caused by such an instruction (run by a guest hypervisor). | |
7066 | * On success, returns 0. When the operand is invalid, returns 1 and throws | |
7067 | * #UD or #GP. | |
7068 | */ | |
7069 | static int get_vmx_mem_address(struct kvm_vcpu *vcpu, | |
7070 | unsigned long exit_qualification, | |
f9eb4af6 | 7071 | u32 vmx_instruction_info, bool wr, gva_t *ret) |
19677e32 | 7072 | { |
f9eb4af6 EK |
7073 | gva_t off; |
7074 | bool exn; | |
7075 | struct kvm_segment s; | |
7076 | ||
19677e32 BD |
7077 | /* |
7078 | * According to Vol. 3B, "Information for VM Exits Due to Instruction | |
7079 | * Execution", on an exit, vmx_instruction_info holds most of the | |
7080 | * addressing components of the operand. Only the displacement part | |
7081 | * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). | |
7082 | * For how an actual address is calculated from all these components, | |
7083 | * refer to Vol. 1, "Operand Addressing". | |
7084 | */ | |
7085 | int scaling = vmx_instruction_info & 3; | |
7086 | int addr_size = (vmx_instruction_info >> 7) & 7; | |
7087 | bool is_reg = vmx_instruction_info & (1u << 10); | |
7088 | int seg_reg = (vmx_instruction_info >> 15) & 7; | |
7089 | int index_reg = (vmx_instruction_info >> 18) & 0xf; | |
7090 | bool index_is_valid = !(vmx_instruction_info & (1u << 22)); | |
7091 | int base_reg = (vmx_instruction_info >> 23) & 0xf; | |
7092 | bool base_is_valid = !(vmx_instruction_info & (1u << 27)); | |
7093 | ||
7094 | if (is_reg) { | |
7095 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7096 | return 1; | |
7097 | } | |
7098 | ||
7099 | /* Addr = segment_base + offset */ | |
7100 | /* offset = base + [index * scale] + displacement */ | |
f9eb4af6 | 7101 | off = exit_qualification; /* holds the displacement */ |
19677e32 | 7102 | if (base_is_valid) |
f9eb4af6 | 7103 | off += kvm_register_read(vcpu, base_reg); |
19677e32 | 7104 | if (index_is_valid) |
f9eb4af6 EK |
7105 | off += kvm_register_read(vcpu, index_reg)<<scaling; |
7106 | vmx_get_segment(vcpu, &s, seg_reg); | |
7107 | *ret = s.base + off; | |
19677e32 BD |
7108 | |
7109 | if (addr_size == 1) /* 32 bit */ | |
7110 | *ret &= 0xffffffff; | |
7111 | ||
f9eb4af6 EK |
7112 | /* Checks for #GP/#SS exceptions. */ |
7113 | exn = false; | |
ff30ef40 QC |
7114 | if (is_long_mode(vcpu)) { |
7115 | /* Long mode: #GP(0)/#SS(0) if the memory address is in a | |
7116 | * non-canonical form. This is the only check on the memory | |
7117 | * destination for long mode! | |
7118 | */ | |
fd8cb433 | 7119 | exn = is_noncanonical_address(*ret, vcpu); |
ff30ef40 | 7120 | } else if (is_protmode(vcpu)) { |
f9eb4af6 EK |
7121 | /* Protected mode: apply checks for segment validity in the |
7122 | * following order: | |
7123 | * - segment type check (#GP(0) may be thrown) | |
7124 | * - usability check (#GP(0)/#SS(0)) | |
7125 | * - limit check (#GP(0)/#SS(0)) | |
7126 | */ | |
7127 | if (wr) | |
7128 | /* #GP(0) if the destination operand is located in a | |
7129 | * read-only data segment or any code segment. | |
7130 | */ | |
7131 | exn = ((s.type & 0xa) == 0 || (s.type & 8)); | |
7132 | else | |
7133 | /* #GP(0) if the source operand is located in an | |
7134 | * execute-only code segment | |
7135 | */ | |
7136 | exn = ((s.type & 0xa) == 8); | |
ff30ef40 QC |
7137 | if (exn) { |
7138 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
7139 | return 1; | |
7140 | } | |
f9eb4af6 EK |
7141 | /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. |
7142 | */ | |
7143 | exn = (s.unusable != 0); | |
7144 | /* Protected mode: #GP(0)/#SS(0) if the memory | |
7145 | * operand is outside the segment limit. | |
7146 | */ | |
7147 | exn = exn || (off + sizeof(u64) > s.limit); | |
7148 | } | |
7149 | if (exn) { | |
7150 | kvm_queue_exception_e(vcpu, | |
7151 | seg_reg == VCPU_SREG_SS ? | |
7152 | SS_VECTOR : GP_VECTOR, | |
7153 | 0); | |
7154 | return 1; | |
7155 | } | |
7156 | ||
19677e32 BD |
7157 | return 0; |
7158 | } | |
7159 | ||
cbf71279 | 7160 | static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer) |
3573e22c BD |
7161 | { |
7162 | gva_t gva; | |
3573e22c | 7163 | struct x86_exception e; |
3573e22c BD |
7164 | |
7165 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7166 | vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva)) |
3573e22c BD |
7167 | return 1; |
7168 | ||
cbf71279 RK |
7169 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer, |
7170 | sizeof(*vmpointer), &e)) { | |
3573e22c BD |
7171 | kvm_inject_page_fault(vcpu, &e); |
7172 | return 1; | |
7173 | } | |
7174 | ||
3573e22c BD |
7175 | return 0; |
7176 | } | |
7177 | ||
e29acc55 JM |
7178 | static int enter_vmx_operation(struct kvm_vcpu *vcpu) |
7179 | { | |
7180 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7181 | struct vmcs *shadow_vmcs; | |
f21f165e | 7182 | int r; |
e29acc55 | 7183 | |
f21f165e PB |
7184 | r = alloc_loaded_vmcs(&vmx->nested.vmcs02); |
7185 | if (r < 0) | |
de3a0021 | 7186 | goto out_vmcs02; |
e29acc55 JM |
7187 | |
7188 | vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL); | |
7189 | if (!vmx->nested.cached_vmcs12) | |
7190 | goto out_cached_vmcs12; | |
7191 | ||
7192 | if (enable_shadow_vmcs) { | |
7193 | shadow_vmcs = alloc_vmcs(); | |
7194 | if (!shadow_vmcs) | |
7195 | goto out_shadow_vmcs; | |
7196 | /* mark vmcs as shadow */ | |
7197 | shadow_vmcs->revision_id |= (1u << 31); | |
7198 | /* init shadow vmcs */ | |
7199 | vmcs_clear(shadow_vmcs); | |
7200 | vmx->vmcs01.shadow_vmcs = shadow_vmcs; | |
7201 | } | |
7202 | ||
e29acc55 JM |
7203 | hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, |
7204 | HRTIMER_MODE_REL_PINNED); | |
7205 | vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; | |
7206 | ||
7207 | vmx->nested.vmxon = true; | |
7208 | return 0; | |
7209 | ||
7210 | out_shadow_vmcs: | |
7211 | kfree(vmx->nested.cached_vmcs12); | |
7212 | ||
7213 | out_cached_vmcs12: | |
de3a0021 | 7214 | free_loaded_vmcs(&vmx->nested.vmcs02); |
e29acc55 | 7215 | |
de3a0021 | 7216 | out_vmcs02: |
e29acc55 JM |
7217 | return -ENOMEM; |
7218 | } | |
7219 | ||
ec378aee NHE |
7220 | /* |
7221 | * Emulate the VMXON instruction. | |
7222 | * Currently, we just remember that VMX is active, and do not save or even | |
7223 | * inspect the argument to VMXON (the so-called "VMXON pointer") because we | |
7224 | * do not currently need to store anything in that guest-allocated memory | |
7225 | * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their | |
7226 | * argument is different from the VMXON pointer (which the spec says they do). | |
7227 | */ | |
7228 | static int handle_vmon(struct kvm_vcpu *vcpu) | |
7229 | { | |
e29acc55 | 7230 | int ret; |
cbf71279 RK |
7231 | gpa_t vmptr; |
7232 | struct page *page; | |
ec378aee | 7233 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b3897a49 NHE |
7234 | const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED |
7235 | | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
ec378aee | 7236 | |
70f3aac9 JM |
7237 | /* |
7238 | * The Intel VMX Instruction Reference lists a bunch of bits that are | |
7239 | * prerequisite to running VMXON, most notably cr4.VMXE must be set to | |
7240 | * 1 (see vmx_set_cr4() for when we allow the guest to set this). | |
7241 | * Otherwise, we should fail with #UD. But most faulting conditions | |
7242 | * have already been checked by hardware, prior to the VM-exit for | |
7243 | * VMXON. We do test guest cr4.VMXE because processor CR4 always has | |
7244 | * that bit set to 1 in non-root mode. | |
ec378aee | 7245 | */ |
70f3aac9 | 7246 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) { |
ec378aee NHE |
7247 | kvm_queue_exception(vcpu, UD_VECTOR); |
7248 | return 1; | |
7249 | } | |
7250 | ||
145c28dd AG |
7251 | if (vmx->nested.vmxon) { |
7252 | nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); | |
6affcbed | 7253 | return kvm_skip_emulated_instruction(vcpu); |
145c28dd | 7254 | } |
b3897a49 | 7255 | |
3b84080b | 7256 | if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES) |
b3897a49 NHE |
7257 | != VMXON_NEEDED_FEATURES) { |
7258 | kvm_inject_gp(vcpu, 0); | |
7259 | return 1; | |
7260 | } | |
7261 | ||
cbf71279 | 7262 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
21e7fbe7 | 7263 | return 1; |
cbf71279 RK |
7264 | |
7265 | /* | |
7266 | * SDM 3: 24.11.5 | |
7267 | * The first 4 bytes of VMXON region contain the supported | |
7268 | * VMCS revision identifier | |
7269 | * | |
7270 | * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case; | |
7271 | * which replaces physical address width with 32 | |
7272 | */ | |
7273 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { | |
7274 | nested_vmx_failInvalid(vcpu); | |
7275 | return kvm_skip_emulated_instruction(vcpu); | |
7276 | } | |
7277 | ||
5e2f30b7 DH |
7278 | page = kvm_vcpu_gpa_to_page(vcpu, vmptr); |
7279 | if (is_error_page(page)) { | |
cbf71279 RK |
7280 | nested_vmx_failInvalid(vcpu); |
7281 | return kvm_skip_emulated_instruction(vcpu); | |
7282 | } | |
7283 | if (*(u32 *)kmap(page) != VMCS12_REVISION) { | |
7284 | kunmap(page); | |
53a70daf | 7285 | kvm_release_page_clean(page); |
cbf71279 RK |
7286 | nested_vmx_failInvalid(vcpu); |
7287 | return kvm_skip_emulated_instruction(vcpu); | |
7288 | } | |
7289 | kunmap(page); | |
53a70daf | 7290 | kvm_release_page_clean(page); |
cbf71279 RK |
7291 | |
7292 | vmx->nested.vmxon_ptr = vmptr; | |
e29acc55 JM |
7293 | ret = enter_vmx_operation(vcpu); |
7294 | if (ret) | |
7295 | return ret; | |
ec378aee | 7296 | |
a25eb114 | 7297 | nested_vmx_succeed(vcpu); |
6affcbed | 7298 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7299 | } |
7300 | ||
7301 | /* | |
7302 | * Intel's VMX Instruction Reference specifies a common set of prerequisites | |
7303 | * for running VMX instructions (except VMXON, whose prerequisites are | |
7304 | * slightly different). It also specifies what exception to inject otherwise. | |
70f3aac9 JM |
7305 | * Note that many of these exceptions have priority over VM exits, so they |
7306 | * don't have to be checked again here. | |
ec378aee NHE |
7307 | */ |
7308 | static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) | |
7309 | { | |
70f3aac9 | 7310 | if (!to_vmx(vcpu)->nested.vmxon) { |
ec378aee NHE |
7311 | kvm_queue_exception(vcpu, UD_VECTOR); |
7312 | return 0; | |
7313 | } | |
ec378aee NHE |
7314 | return 1; |
7315 | } | |
7316 | ||
8ca44e88 DM |
7317 | static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx) |
7318 | { | |
7319 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS); | |
7320 | vmcs_write64(VMCS_LINK_POINTER, -1ull); | |
7321 | } | |
7322 | ||
e7953d7f AG |
7323 | static inline void nested_release_vmcs12(struct vcpu_vmx *vmx) |
7324 | { | |
9a2a05b9 PB |
7325 | if (vmx->nested.current_vmptr == -1ull) |
7326 | return; | |
7327 | ||
012f83cb | 7328 | if (enable_shadow_vmcs) { |
9a2a05b9 PB |
7329 | /* copy to memory all shadowed fields in case |
7330 | they were modified */ | |
7331 | copy_shadow_to_vmcs12(vmx); | |
7332 | vmx->nested.sync_shadow_vmcs = false; | |
8ca44e88 | 7333 | vmx_disable_shadow_vmcs(vmx); |
012f83cb | 7334 | } |
705699a1 | 7335 | vmx->nested.posted_intr_nv = -1; |
4f2777bc DM |
7336 | |
7337 | /* Flush VMCS12 to guest memory */ | |
9f744c59 PB |
7338 | kvm_vcpu_write_guest_page(&vmx->vcpu, |
7339 | vmx->nested.current_vmptr >> PAGE_SHIFT, | |
7340 | vmx->nested.cached_vmcs12, 0, VMCS12_SIZE); | |
4f2777bc | 7341 | |
9a2a05b9 | 7342 | vmx->nested.current_vmptr = -1ull; |
e7953d7f AG |
7343 | } |
7344 | ||
ec378aee NHE |
7345 | /* |
7346 | * Free whatever needs to be freed from vmx->nested when L1 goes down, or | |
7347 | * just stops using VMX. | |
7348 | */ | |
7349 | static void free_nested(struct vcpu_vmx *vmx) | |
7350 | { | |
b7455825 | 7351 | if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon) |
ec378aee | 7352 | return; |
9a2a05b9 | 7353 | |
ec378aee | 7354 | vmx->nested.vmxon = false; |
b7455825 | 7355 | vmx->nested.smm.vmxon = false; |
5c614b35 | 7356 | free_vpid(vmx->nested.vpid02); |
8ca44e88 DM |
7357 | vmx->nested.posted_intr_nv = -1; |
7358 | vmx->nested.current_vmptr = -1ull; | |
355f4fb1 | 7359 | if (enable_shadow_vmcs) { |
8ca44e88 | 7360 | vmx_disable_shadow_vmcs(vmx); |
355f4fb1 JM |
7361 | vmcs_clear(vmx->vmcs01.shadow_vmcs); |
7362 | free_vmcs(vmx->vmcs01.shadow_vmcs); | |
7363 | vmx->vmcs01.shadow_vmcs = NULL; | |
7364 | } | |
4f2777bc | 7365 | kfree(vmx->nested.cached_vmcs12); |
de3a0021 | 7366 | /* Unpin physical memory we referred to in the vmcs02 */ |
fe3ef05c | 7367 | if (vmx->nested.apic_access_page) { |
53a70daf | 7368 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
48d89b92 | 7369 | vmx->nested.apic_access_page = NULL; |
fe3ef05c | 7370 | } |
a7c0b07d | 7371 | if (vmx->nested.virtual_apic_page) { |
53a70daf | 7372 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
48d89b92 | 7373 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 7374 | } |
705699a1 WV |
7375 | if (vmx->nested.pi_desc_page) { |
7376 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 7377 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
705699a1 WV |
7378 | vmx->nested.pi_desc_page = NULL; |
7379 | vmx->nested.pi_desc = NULL; | |
7380 | } | |
ff2f6fe9 | 7381 | |
de3a0021 | 7382 | free_loaded_vmcs(&vmx->nested.vmcs02); |
ec378aee NHE |
7383 | } |
7384 | ||
7385 | /* Emulate the VMXOFF instruction */ | |
7386 | static int handle_vmoff(struct kvm_vcpu *vcpu) | |
7387 | { | |
7388 | if (!nested_vmx_check_permission(vcpu)) | |
7389 | return 1; | |
7390 | free_nested(to_vmx(vcpu)); | |
a25eb114 | 7391 | nested_vmx_succeed(vcpu); |
6affcbed | 7392 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7393 | } |
7394 | ||
27d6c865 NHE |
7395 | /* Emulate the VMCLEAR instruction */ |
7396 | static int handle_vmclear(struct kvm_vcpu *vcpu) | |
7397 | { | |
7398 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
587d7e72 | 7399 | u32 zero = 0; |
27d6c865 | 7400 | gpa_t vmptr; |
27d6c865 NHE |
7401 | |
7402 | if (!nested_vmx_check_permission(vcpu)) | |
7403 | return 1; | |
7404 | ||
cbf71279 | 7405 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
27d6c865 | 7406 | return 1; |
27d6c865 | 7407 | |
cbf71279 RK |
7408 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { |
7409 | nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS); | |
7410 | return kvm_skip_emulated_instruction(vcpu); | |
7411 | } | |
7412 | ||
7413 | if (vmptr == vmx->nested.vmxon_ptr) { | |
7414 | nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER); | |
7415 | return kvm_skip_emulated_instruction(vcpu); | |
7416 | } | |
7417 | ||
9a2a05b9 | 7418 | if (vmptr == vmx->nested.current_vmptr) |
e7953d7f | 7419 | nested_release_vmcs12(vmx); |
27d6c865 | 7420 | |
587d7e72 JM |
7421 | kvm_vcpu_write_guest(vcpu, |
7422 | vmptr + offsetof(struct vmcs12, launch_state), | |
7423 | &zero, sizeof(zero)); | |
27d6c865 | 7424 | |
27d6c865 | 7425 | nested_vmx_succeed(vcpu); |
6affcbed | 7426 | return kvm_skip_emulated_instruction(vcpu); |
27d6c865 NHE |
7427 | } |
7428 | ||
cd232ad0 NHE |
7429 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch); |
7430 | ||
7431 | /* Emulate the VMLAUNCH instruction */ | |
7432 | static int handle_vmlaunch(struct kvm_vcpu *vcpu) | |
7433 | { | |
7434 | return nested_vmx_run(vcpu, true); | |
7435 | } | |
7436 | ||
7437 | /* Emulate the VMRESUME instruction */ | |
7438 | static int handle_vmresume(struct kvm_vcpu *vcpu) | |
7439 | { | |
7440 | ||
7441 | return nested_vmx_run(vcpu, false); | |
7442 | } | |
7443 | ||
49f705c5 NHE |
7444 | /* |
7445 | * Read a vmcs12 field. Since these can have varying lengths and we return | |
7446 | * one type, we chose the biggest type (u64) and zero-extend the return value | |
7447 | * to that size. Note that the caller, handle_vmread, might need to use only | |
7448 | * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of | |
7449 | * 64-bit fields are to be returned). | |
7450 | */ | |
a2ae9df7 PB |
7451 | static inline int vmcs12_read_any(struct kvm_vcpu *vcpu, |
7452 | unsigned long field, u64 *ret) | |
49f705c5 NHE |
7453 | { |
7454 | short offset = vmcs_field_to_offset(field); | |
7455 | char *p; | |
7456 | ||
7457 | if (offset < 0) | |
a2ae9df7 | 7458 | return offset; |
49f705c5 NHE |
7459 | |
7460 | p = ((char *)(get_vmcs12(vcpu))) + offset; | |
7461 | ||
7462 | switch (vmcs_field_type(field)) { | |
7463 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7464 | *ret = *((natural_width *)p); | |
a2ae9df7 | 7465 | return 0; |
49f705c5 NHE |
7466 | case VMCS_FIELD_TYPE_U16: |
7467 | *ret = *((u16 *)p); | |
a2ae9df7 | 7468 | return 0; |
49f705c5 NHE |
7469 | case VMCS_FIELD_TYPE_U32: |
7470 | *ret = *((u32 *)p); | |
a2ae9df7 | 7471 | return 0; |
49f705c5 NHE |
7472 | case VMCS_FIELD_TYPE_U64: |
7473 | *ret = *((u64 *)p); | |
a2ae9df7 | 7474 | return 0; |
49f705c5 | 7475 | default: |
a2ae9df7 PB |
7476 | WARN_ON(1); |
7477 | return -ENOENT; | |
49f705c5 NHE |
7478 | } |
7479 | } | |
7480 | ||
20b97fea | 7481 | |
a2ae9df7 PB |
7482 | static inline int vmcs12_write_any(struct kvm_vcpu *vcpu, |
7483 | unsigned long field, u64 field_value){ | |
20b97fea AG |
7484 | short offset = vmcs_field_to_offset(field); |
7485 | char *p = ((char *) get_vmcs12(vcpu)) + offset; | |
7486 | if (offset < 0) | |
a2ae9df7 | 7487 | return offset; |
20b97fea AG |
7488 | |
7489 | switch (vmcs_field_type(field)) { | |
7490 | case VMCS_FIELD_TYPE_U16: | |
7491 | *(u16 *)p = field_value; | |
a2ae9df7 | 7492 | return 0; |
20b97fea AG |
7493 | case VMCS_FIELD_TYPE_U32: |
7494 | *(u32 *)p = field_value; | |
a2ae9df7 | 7495 | return 0; |
20b97fea AG |
7496 | case VMCS_FIELD_TYPE_U64: |
7497 | *(u64 *)p = field_value; | |
a2ae9df7 | 7498 | return 0; |
20b97fea AG |
7499 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: |
7500 | *(natural_width *)p = field_value; | |
a2ae9df7 | 7501 | return 0; |
20b97fea | 7502 | default: |
a2ae9df7 PB |
7503 | WARN_ON(1); |
7504 | return -ENOENT; | |
20b97fea AG |
7505 | } |
7506 | ||
7507 | } | |
7508 | ||
16f5b903 AG |
7509 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) |
7510 | { | |
7511 | int i; | |
7512 | unsigned long field; | |
7513 | u64 field_value; | |
355f4fb1 | 7514 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c2bae893 MK |
7515 | const unsigned long *fields = shadow_read_write_fields; |
7516 | const int num_fields = max_shadow_read_write_fields; | |
16f5b903 | 7517 | |
282da870 JK |
7518 | preempt_disable(); |
7519 | ||
16f5b903 AG |
7520 | vmcs_load(shadow_vmcs); |
7521 | ||
7522 | for (i = 0; i < num_fields; i++) { | |
7523 | field = fields[i]; | |
7524 | switch (vmcs_field_type(field)) { | |
7525 | case VMCS_FIELD_TYPE_U16: | |
7526 | field_value = vmcs_read16(field); | |
7527 | break; | |
7528 | case VMCS_FIELD_TYPE_U32: | |
7529 | field_value = vmcs_read32(field); | |
7530 | break; | |
7531 | case VMCS_FIELD_TYPE_U64: | |
7532 | field_value = vmcs_read64(field); | |
7533 | break; | |
7534 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7535 | field_value = vmcs_readl(field); | |
7536 | break; | |
a2ae9df7 PB |
7537 | default: |
7538 | WARN_ON(1); | |
7539 | continue; | |
16f5b903 AG |
7540 | } |
7541 | vmcs12_write_any(&vmx->vcpu, field, field_value); | |
7542 | } | |
7543 | ||
7544 | vmcs_clear(shadow_vmcs); | |
7545 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
282da870 JK |
7546 | |
7547 | preempt_enable(); | |
16f5b903 AG |
7548 | } |
7549 | ||
c3114420 AG |
7550 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) |
7551 | { | |
c2bae893 MK |
7552 | const unsigned long *fields[] = { |
7553 | shadow_read_write_fields, | |
7554 | shadow_read_only_fields | |
c3114420 | 7555 | }; |
c2bae893 | 7556 | const int max_fields[] = { |
c3114420 AG |
7557 | max_shadow_read_write_fields, |
7558 | max_shadow_read_only_fields | |
7559 | }; | |
7560 | int i, q; | |
7561 | unsigned long field; | |
7562 | u64 field_value = 0; | |
355f4fb1 | 7563 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c3114420 AG |
7564 | |
7565 | vmcs_load(shadow_vmcs); | |
7566 | ||
c2bae893 | 7567 | for (q = 0; q < ARRAY_SIZE(fields); q++) { |
c3114420 AG |
7568 | for (i = 0; i < max_fields[q]; i++) { |
7569 | field = fields[q][i]; | |
7570 | vmcs12_read_any(&vmx->vcpu, field, &field_value); | |
7571 | ||
7572 | switch (vmcs_field_type(field)) { | |
7573 | case VMCS_FIELD_TYPE_U16: | |
7574 | vmcs_write16(field, (u16)field_value); | |
7575 | break; | |
7576 | case VMCS_FIELD_TYPE_U32: | |
7577 | vmcs_write32(field, (u32)field_value); | |
7578 | break; | |
7579 | case VMCS_FIELD_TYPE_U64: | |
7580 | vmcs_write64(field, (u64)field_value); | |
7581 | break; | |
7582 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7583 | vmcs_writel(field, (long)field_value); | |
7584 | break; | |
a2ae9df7 PB |
7585 | default: |
7586 | WARN_ON(1); | |
7587 | break; | |
c3114420 AG |
7588 | } |
7589 | } | |
7590 | } | |
7591 | ||
7592 | vmcs_clear(shadow_vmcs); | |
7593 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
7594 | } | |
7595 | ||
49f705c5 NHE |
7596 | /* |
7597 | * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was | |
7598 | * used before) all generate the same failure when it is missing. | |
7599 | */ | |
7600 | static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu) | |
7601 | { | |
7602 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7603 | if (vmx->nested.current_vmptr == -1ull) { | |
7604 | nested_vmx_failInvalid(vcpu); | |
49f705c5 NHE |
7605 | return 0; |
7606 | } | |
7607 | return 1; | |
7608 | } | |
7609 | ||
7610 | static int handle_vmread(struct kvm_vcpu *vcpu) | |
7611 | { | |
7612 | unsigned long field; | |
7613 | u64 field_value; | |
7614 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7615 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7616 | gva_t gva = 0; | |
7617 | ||
eb277562 | 7618 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
7619 | return 1; |
7620 | ||
6affcbed KH |
7621 | if (!nested_vmx_check_vmcs12(vcpu)) |
7622 | return kvm_skip_emulated_instruction(vcpu); | |
49f705c5 NHE |
7623 | |
7624 | /* Decode instruction info and find the field to read */ | |
27e6fb5d | 7625 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 | 7626 | /* Read the field, zero-extended to a u64 field_value */ |
a2ae9df7 | 7627 | if (vmcs12_read_any(vcpu, field, &field_value) < 0) { |
49f705c5 | 7628 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 7629 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7630 | } |
7631 | /* | |
7632 | * Now copy part of this value to register or memory, as requested. | |
7633 | * Note that the number of bits actually copied is 32 or 64 depending | |
7634 | * on the guest's mode (32 or 64 bit), not on the given field's length. | |
7635 | */ | |
7636 | if (vmx_instruction_info & (1u << 10)) { | |
27e6fb5d | 7637 | kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf), |
49f705c5 NHE |
7638 | field_value); |
7639 | } else { | |
7640 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7641 | vmx_instruction_info, true, &gva)) |
49f705c5 | 7642 | return 1; |
70f3aac9 | 7643 | /* _system ok, as hardware has verified cpl=0 */ |
49f705c5 NHE |
7644 | kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva, |
7645 | &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL); | |
7646 | } | |
7647 | ||
7648 | nested_vmx_succeed(vcpu); | |
6affcbed | 7649 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7650 | } |
7651 | ||
7652 | ||
7653 | static int handle_vmwrite(struct kvm_vcpu *vcpu) | |
7654 | { | |
7655 | unsigned long field; | |
7656 | gva_t gva; | |
7657 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7658 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
49f705c5 NHE |
7659 | /* The value to write might be 32 or 64 bits, depending on L1's long |
7660 | * mode, and eventually we need to write that into a field of several | |
7661 | * possible lengths. The code below first zero-extends the value to 64 | |
6a6256f9 | 7662 | * bit (field_value), and then copies only the appropriate number of |
49f705c5 NHE |
7663 | * bits into the vmcs12 field. |
7664 | */ | |
7665 | u64 field_value = 0; | |
7666 | struct x86_exception e; | |
7667 | ||
eb277562 | 7668 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
7669 | return 1; |
7670 | ||
6affcbed KH |
7671 | if (!nested_vmx_check_vmcs12(vcpu)) |
7672 | return kvm_skip_emulated_instruction(vcpu); | |
eb277562 | 7673 | |
49f705c5 | 7674 | if (vmx_instruction_info & (1u << 10)) |
27e6fb5d | 7675 | field_value = kvm_register_readl(vcpu, |
49f705c5 NHE |
7676 | (((vmx_instruction_info) >> 3) & 0xf)); |
7677 | else { | |
7678 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7679 | vmx_instruction_info, false, &gva)) |
49f705c5 NHE |
7680 | return 1; |
7681 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, | |
27e6fb5d | 7682 | &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) { |
49f705c5 NHE |
7683 | kvm_inject_page_fault(vcpu, &e); |
7684 | return 1; | |
7685 | } | |
7686 | } | |
7687 | ||
7688 | ||
27e6fb5d | 7689 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 NHE |
7690 | if (vmcs_field_readonly(field)) { |
7691 | nested_vmx_failValid(vcpu, | |
7692 | VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); | |
6affcbed | 7693 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7694 | } |
7695 | ||
a2ae9df7 | 7696 | if (vmcs12_write_any(vcpu, field, field_value) < 0) { |
49f705c5 | 7697 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 7698 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7699 | } |
7700 | ||
7701 | nested_vmx_succeed(vcpu); | |
6affcbed | 7702 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7703 | } |
7704 | ||
a8bc284e JM |
7705 | static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr) |
7706 | { | |
7707 | vmx->nested.current_vmptr = vmptr; | |
7708 | if (enable_shadow_vmcs) { | |
7709 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
7710 | SECONDARY_EXEC_SHADOW_VMCS); | |
7711 | vmcs_write64(VMCS_LINK_POINTER, | |
7712 | __pa(vmx->vmcs01.shadow_vmcs)); | |
7713 | vmx->nested.sync_shadow_vmcs = true; | |
7714 | } | |
7715 | } | |
7716 | ||
63846663 NHE |
7717 | /* Emulate the VMPTRLD instruction */ |
7718 | static int handle_vmptrld(struct kvm_vcpu *vcpu) | |
7719 | { | |
7720 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
63846663 | 7721 | gpa_t vmptr; |
63846663 NHE |
7722 | |
7723 | if (!nested_vmx_check_permission(vcpu)) | |
7724 | return 1; | |
7725 | ||
cbf71279 | 7726 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
63846663 | 7727 | return 1; |
63846663 | 7728 | |
cbf71279 RK |
7729 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { |
7730 | nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS); | |
7731 | return kvm_skip_emulated_instruction(vcpu); | |
7732 | } | |
7733 | ||
7734 | if (vmptr == vmx->nested.vmxon_ptr) { | |
7735 | nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER); | |
7736 | return kvm_skip_emulated_instruction(vcpu); | |
7737 | } | |
7738 | ||
63846663 NHE |
7739 | if (vmx->nested.current_vmptr != vmptr) { |
7740 | struct vmcs12 *new_vmcs12; | |
7741 | struct page *page; | |
5e2f30b7 DH |
7742 | page = kvm_vcpu_gpa_to_page(vcpu, vmptr); |
7743 | if (is_error_page(page)) { | |
63846663 | 7744 | nested_vmx_failInvalid(vcpu); |
6affcbed | 7745 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
7746 | } |
7747 | new_vmcs12 = kmap(page); | |
7748 | if (new_vmcs12->revision_id != VMCS12_REVISION) { | |
7749 | kunmap(page); | |
53a70daf | 7750 | kvm_release_page_clean(page); |
63846663 NHE |
7751 | nested_vmx_failValid(vcpu, |
7752 | VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); | |
6affcbed | 7753 | return kvm_skip_emulated_instruction(vcpu); |
63846663 | 7754 | } |
63846663 | 7755 | |
9a2a05b9 | 7756 | nested_release_vmcs12(vmx); |
4f2777bc DM |
7757 | /* |
7758 | * Load VMCS12 from guest memory since it is not already | |
7759 | * cached. | |
7760 | */ | |
9f744c59 PB |
7761 | memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE); |
7762 | kunmap(page); | |
53a70daf | 7763 | kvm_release_page_clean(page); |
9f744c59 | 7764 | |
a8bc284e | 7765 | set_current_vmptr(vmx, vmptr); |
63846663 NHE |
7766 | } |
7767 | ||
7768 | nested_vmx_succeed(vcpu); | |
6affcbed | 7769 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
7770 | } |
7771 | ||
6a4d7550 NHE |
7772 | /* Emulate the VMPTRST instruction */ |
7773 | static int handle_vmptrst(struct kvm_vcpu *vcpu) | |
7774 | { | |
7775 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7776 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7777 | gva_t vmcs_gva; | |
7778 | struct x86_exception e; | |
7779 | ||
7780 | if (!nested_vmx_check_permission(vcpu)) | |
7781 | return 1; | |
7782 | ||
7783 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7784 | vmx_instruction_info, true, &vmcs_gva)) |
6a4d7550 | 7785 | return 1; |
70f3aac9 | 7786 | /* ok to use *_system, as hardware has verified cpl=0 */ |
6a4d7550 NHE |
7787 | if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva, |
7788 | (void *)&to_vmx(vcpu)->nested.current_vmptr, | |
7789 | sizeof(u64), &e)) { | |
7790 | kvm_inject_page_fault(vcpu, &e); | |
7791 | return 1; | |
7792 | } | |
7793 | nested_vmx_succeed(vcpu); | |
6affcbed | 7794 | return kvm_skip_emulated_instruction(vcpu); |
6a4d7550 NHE |
7795 | } |
7796 | ||
bfd0a56b NHE |
7797 | /* Emulate the INVEPT instruction */ |
7798 | static int handle_invept(struct kvm_vcpu *vcpu) | |
7799 | { | |
b9c237bb | 7800 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
bfd0a56b NHE |
7801 | u32 vmx_instruction_info, types; |
7802 | unsigned long type; | |
7803 | gva_t gva; | |
7804 | struct x86_exception e; | |
7805 | struct { | |
7806 | u64 eptp, gpa; | |
7807 | } operand; | |
bfd0a56b | 7808 | |
b9c237bb WV |
7809 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & |
7810 | SECONDARY_EXEC_ENABLE_EPT) || | |
7811 | !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) { | |
bfd0a56b NHE |
7812 | kvm_queue_exception(vcpu, UD_VECTOR); |
7813 | return 1; | |
7814 | } | |
7815 | ||
7816 | if (!nested_vmx_check_permission(vcpu)) | |
7817 | return 1; | |
7818 | ||
bfd0a56b | 7819 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); |
27e6fb5d | 7820 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); |
bfd0a56b | 7821 | |
b9c237bb | 7822 | types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; |
bfd0a56b | 7823 | |
85c856b3 | 7824 | if (type >= 32 || !(types & (1 << type))) { |
bfd0a56b NHE |
7825 | nested_vmx_failValid(vcpu, |
7826 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7827 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
7828 | } |
7829 | ||
7830 | /* According to the Intel VMX instruction reference, the memory | |
7831 | * operand is read even if it isn't needed (e.g., for type==global) | |
7832 | */ | |
7833 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7834 | vmx_instruction_info, false, &gva)) |
bfd0a56b NHE |
7835 | return 1; |
7836 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand, | |
7837 | sizeof(operand), &e)) { | |
7838 | kvm_inject_page_fault(vcpu, &e); | |
7839 | return 1; | |
7840 | } | |
7841 | ||
7842 | switch (type) { | |
bfd0a56b | 7843 | case VMX_EPT_EXTENT_GLOBAL: |
45e11817 BD |
7844 | /* |
7845 | * TODO: track mappings and invalidate | |
7846 | * single context requests appropriately | |
7847 | */ | |
7848 | case VMX_EPT_EXTENT_CONTEXT: | |
bfd0a56b | 7849 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 7850 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
bfd0a56b NHE |
7851 | nested_vmx_succeed(vcpu); |
7852 | break; | |
7853 | default: | |
7854 | BUG_ON(1); | |
7855 | break; | |
7856 | } | |
7857 | ||
6affcbed | 7858 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
7859 | } |
7860 | ||
a642fc30 PM |
7861 | static int handle_invvpid(struct kvm_vcpu *vcpu) |
7862 | { | |
99b83ac8 WL |
7863 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7864 | u32 vmx_instruction_info; | |
7865 | unsigned long type, types; | |
7866 | gva_t gva; | |
7867 | struct x86_exception e; | |
40352605 JM |
7868 | struct { |
7869 | u64 vpid; | |
7870 | u64 gla; | |
7871 | } operand; | |
99b83ac8 WL |
7872 | |
7873 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & | |
7874 | SECONDARY_EXEC_ENABLE_VPID) || | |
7875 | !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) { | |
7876 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7877 | return 1; | |
7878 | } | |
7879 | ||
7880 | if (!nested_vmx_check_permission(vcpu)) | |
7881 | return 1; | |
7882 | ||
7883 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7884 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); | |
7885 | ||
bcdde302 JD |
7886 | types = (vmx->nested.nested_vmx_vpid_caps & |
7887 | VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8; | |
99b83ac8 | 7888 | |
85c856b3 | 7889 | if (type >= 32 || !(types & (1 << type))) { |
99b83ac8 WL |
7890 | nested_vmx_failValid(vcpu, |
7891 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7892 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
7893 | } |
7894 | ||
7895 | /* according to the intel vmx instruction reference, the memory | |
7896 | * operand is read even if it isn't needed (e.g., for type==global) | |
7897 | */ | |
7898 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
7899 | vmx_instruction_info, false, &gva)) | |
7900 | return 1; | |
40352605 JM |
7901 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand, |
7902 | sizeof(operand), &e)) { | |
99b83ac8 WL |
7903 | kvm_inject_page_fault(vcpu, &e); |
7904 | return 1; | |
7905 | } | |
40352605 JM |
7906 | if (operand.vpid >> 16) { |
7907 | nested_vmx_failValid(vcpu, | |
7908 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
7909 | return kvm_skip_emulated_instruction(vcpu); | |
7910 | } | |
99b83ac8 WL |
7911 | |
7912 | switch (type) { | |
bcdde302 | 7913 | case VMX_VPID_EXTENT_INDIVIDUAL_ADDR: |
fd8cb433 | 7914 | if (is_noncanonical_address(operand.gla, vcpu)) { |
40352605 JM |
7915 | nested_vmx_failValid(vcpu, |
7916 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
7917 | return kvm_skip_emulated_instruction(vcpu); | |
7918 | } | |
7919 | /* fall through */ | |
ef697a71 | 7920 | case VMX_VPID_EXTENT_SINGLE_CONTEXT: |
bcdde302 | 7921 | case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL: |
40352605 | 7922 | if (!operand.vpid) { |
bcdde302 JD |
7923 | nested_vmx_failValid(vcpu, |
7924 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7925 | return kvm_skip_emulated_instruction(vcpu); |
bcdde302 JD |
7926 | } |
7927 | break; | |
99b83ac8 | 7928 | case VMX_VPID_EXTENT_ALL_CONTEXT: |
99b83ac8 WL |
7929 | break; |
7930 | default: | |
bcdde302 | 7931 | WARN_ON_ONCE(1); |
6affcbed | 7932 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
7933 | } |
7934 | ||
bcdde302 JD |
7935 | __vmx_flush_tlb(vcpu, vmx->nested.vpid02); |
7936 | nested_vmx_succeed(vcpu); | |
7937 | ||
6affcbed | 7938 | return kvm_skip_emulated_instruction(vcpu); |
a642fc30 PM |
7939 | } |
7940 | ||
843e4330 KH |
7941 | static int handle_pml_full(struct kvm_vcpu *vcpu) |
7942 | { | |
7943 | unsigned long exit_qualification; | |
7944 | ||
7945 | trace_kvm_pml_full(vcpu->vcpu_id); | |
7946 | ||
7947 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7948 | ||
7949 | /* | |
7950 | * PML buffer FULL happened while executing iret from NMI, | |
7951 | * "blocked by NMI" bit has to be set before next VM entry. | |
7952 | */ | |
7953 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && | |
d02fcf50 | 7954 | enable_vnmi && |
843e4330 KH |
7955 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
7956 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
7957 | GUEST_INTR_STATE_NMI); | |
7958 | ||
7959 | /* | |
7960 | * PML buffer already flushed at beginning of VMEXIT. Nothing to do | |
7961 | * here.., and there's no userspace involvement needed for PML. | |
7962 | */ | |
7963 | return 1; | |
7964 | } | |
7965 | ||
64672c95 YJ |
7966 | static int handle_preemption_timer(struct kvm_vcpu *vcpu) |
7967 | { | |
7968 | kvm_lapic_expired_hv_timer(vcpu); | |
7969 | return 1; | |
7970 | } | |
7971 | ||
41ab9372 BD |
7972 | static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address) |
7973 | { | |
7974 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
41ab9372 BD |
7975 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
7976 | ||
7977 | /* Check for memory type validity */ | |
bb97a016 DH |
7978 | switch (address & VMX_EPTP_MT_MASK) { |
7979 | case VMX_EPTP_MT_UC: | |
41ab9372 BD |
7980 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT)) |
7981 | return false; | |
7982 | break; | |
bb97a016 | 7983 | case VMX_EPTP_MT_WB: |
41ab9372 BD |
7984 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT)) |
7985 | return false; | |
7986 | break; | |
7987 | default: | |
7988 | return false; | |
7989 | } | |
7990 | ||
bb97a016 DH |
7991 | /* only 4 levels page-walk length are valid */ |
7992 | if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4) | |
41ab9372 BD |
7993 | return false; |
7994 | ||
7995 | /* Reserved bits should not be set */ | |
7996 | if (address >> maxphyaddr || ((address >> 7) & 0x1f)) | |
7997 | return false; | |
7998 | ||
7999 | /* AD, if set, should be supported */ | |
bb97a016 | 8000 | if (address & VMX_EPTP_AD_ENABLE_BIT) { |
41ab9372 BD |
8001 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT)) |
8002 | return false; | |
8003 | } | |
8004 | ||
8005 | return true; | |
8006 | } | |
8007 | ||
8008 | static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu, | |
8009 | struct vmcs12 *vmcs12) | |
8010 | { | |
8011 | u32 index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
8012 | u64 address; | |
8013 | bool accessed_dirty; | |
8014 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; | |
8015 | ||
8016 | if (!nested_cpu_has_eptp_switching(vmcs12) || | |
8017 | !nested_cpu_has_ept(vmcs12)) | |
8018 | return 1; | |
8019 | ||
8020 | if (index >= VMFUNC_EPTP_ENTRIES) | |
8021 | return 1; | |
8022 | ||
8023 | ||
8024 | if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT, | |
8025 | &address, index * 8, 8)) | |
8026 | return 1; | |
8027 | ||
bb97a016 | 8028 | accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT); |
41ab9372 BD |
8029 | |
8030 | /* | |
8031 | * If the (L2) guest does a vmfunc to the currently | |
8032 | * active ept pointer, we don't have to do anything else | |
8033 | */ | |
8034 | if (vmcs12->ept_pointer != address) { | |
8035 | if (!valid_ept_address(vcpu, address)) | |
8036 | return 1; | |
8037 | ||
8038 | kvm_mmu_unload(vcpu); | |
8039 | mmu->ept_ad = accessed_dirty; | |
8040 | mmu->base_role.ad_disabled = !accessed_dirty; | |
8041 | vmcs12->ept_pointer = address; | |
8042 | /* | |
8043 | * TODO: Check what's the correct approach in case | |
8044 | * mmu reload fails. Currently, we just let the next | |
8045 | * reload potentially fail | |
8046 | */ | |
8047 | kvm_mmu_reload(vcpu); | |
8048 | } | |
8049 | ||
8050 | return 0; | |
8051 | } | |
8052 | ||
2a499e49 BD |
8053 | static int handle_vmfunc(struct kvm_vcpu *vcpu) |
8054 | { | |
27c42a1b BD |
8055 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8056 | struct vmcs12 *vmcs12; | |
8057 | u32 function = vcpu->arch.regs[VCPU_REGS_RAX]; | |
8058 | ||
8059 | /* | |
8060 | * VMFUNC is only supported for nested guests, but we always enable the | |
8061 | * secondary control for simplicity; for non-nested mode, fake that we | |
8062 | * didn't by injecting #UD. | |
8063 | */ | |
8064 | if (!is_guest_mode(vcpu)) { | |
8065 | kvm_queue_exception(vcpu, UD_VECTOR); | |
8066 | return 1; | |
8067 | } | |
8068 | ||
8069 | vmcs12 = get_vmcs12(vcpu); | |
8070 | if ((vmcs12->vm_function_control & (1 << function)) == 0) | |
8071 | goto fail; | |
41ab9372 BD |
8072 | |
8073 | switch (function) { | |
8074 | case 0: | |
8075 | if (nested_vmx_eptp_switching(vcpu, vmcs12)) | |
8076 | goto fail; | |
8077 | break; | |
8078 | default: | |
8079 | goto fail; | |
8080 | } | |
8081 | return kvm_skip_emulated_instruction(vcpu); | |
27c42a1b BD |
8082 | |
8083 | fail: | |
8084 | nested_vmx_vmexit(vcpu, vmx->exit_reason, | |
8085 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8086 | vmcs_readl(EXIT_QUALIFICATION)); | |
2a499e49 BD |
8087 | return 1; |
8088 | } | |
8089 | ||
6aa8b732 AK |
8090 | /* |
8091 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
8092 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
8093 | * to be done to userspace and return 0. | |
8094 | */ | |
772e0318 | 8095 | static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
8096 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
8097 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 8098 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 8099 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 8100 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
8101 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
8102 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
8103 | [EXIT_REASON_CPUID] = handle_cpuid, | |
8104 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
8105 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
8106 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
8107 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 8108 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 8109 | [EXIT_REASON_INVLPG] = handle_invlpg, |
fee84b07 | 8110 | [EXIT_REASON_RDPMC] = handle_rdpmc, |
c21415e8 | 8111 | [EXIT_REASON_VMCALL] = handle_vmcall, |
27d6c865 | 8112 | [EXIT_REASON_VMCLEAR] = handle_vmclear, |
cd232ad0 | 8113 | [EXIT_REASON_VMLAUNCH] = handle_vmlaunch, |
63846663 | 8114 | [EXIT_REASON_VMPTRLD] = handle_vmptrld, |
6a4d7550 | 8115 | [EXIT_REASON_VMPTRST] = handle_vmptrst, |
49f705c5 | 8116 | [EXIT_REASON_VMREAD] = handle_vmread, |
cd232ad0 | 8117 | [EXIT_REASON_VMRESUME] = handle_vmresume, |
49f705c5 | 8118 | [EXIT_REASON_VMWRITE] = handle_vmwrite, |
ec378aee NHE |
8119 | [EXIT_REASON_VMOFF] = handle_vmoff, |
8120 | [EXIT_REASON_VMON] = handle_vmon, | |
f78e0e2e SY |
8121 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
8122 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
83d4c286 | 8123 | [EXIT_REASON_APIC_WRITE] = handle_apic_write, |
c7c9c56c | 8124 | [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, |
e5edaa01 | 8125 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 8126 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 8127 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 8128 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
8129 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
8130 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 8131 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
87c00572 | 8132 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, |
5f3d45e7 | 8133 | [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, |
87c00572 | 8134 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, |
bfd0a56b | 8135 | [EXIT_REASON_INVEPT] = handle_invept, |
a642fc30 | 8136 | [EXIT_REASON_INVVPID] = handle_invvpid, |
45ec368c | 8137 | [EXIT_REASON_RDRAND] = handle_invalid_op, |
75f4fc8d | 8138 | [EXIT_REASON_RDSEED] = handle_invalid_op, |
f53cd63c WL |
8139 | [EXIT_REASON_XSAVES] = handle_xsaves, |
8140 | [EXIT_REASON_XRSTORS] = handle_xrstors, | |
843e4330 | 8141 | [EXIT_REASON_PML_FULL] = handle_pml_full, |
2a499e49 | 8142 | [EXIT_REASON_VMFUNC] = handle_vmfunc, |
64672c95 | 8143 | [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, |
6aa8b732 AK |
8144 | }; |
8145 | ||
8146 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 8147 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 8148 | |
908a7bdd JK |
8149 | static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, |
8150 | struct vmcs12 *vmcs12) | |
8151 | { | |
8152 | unsigned long exit_qualification; | |
8153 | gpa_t bitmap, last_bitmap; | |
8154 | unsigned int port; | |
8155 | int size; | |
8156 | u8 b; | |
8157 | ||
908a7bdd | 8158 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) |
2f0a6397 | 8159 | return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); |
908a7bdd JK |
8160 | |
8161 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8162 | ||
8163 | port = exit_qualification >> 16; | |
8164 | size = (exit_qualification & 7) + 1; | |
8165 | ||
8166 | last_bitmap = (gpa_t)-1; | |
8167 | b = -1; | |
8168 | ||
8169 | while (size > 0) { | |
8170 | if (port < 0x8000) | |
8171 | bitmap = vmcs12->io_bitmap_a; | |
8172 | else if (port < 0x10000) | |
8173 | bitmap = vmcs12->io_bitmap_b; | |
8174 | else | |
1d804d07 | 8175 | return true; |
908a7bdd JK |
8176 | bitmap += (port & 0x7fff) / 8; |
8177 | ||
8178 | if (last_bitmap != bitmap) | |
54bf36aa | 8179 | if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1)) |
1d804d07 | 8180 | return true; |
908a7bdd | 8181 | if (b & (1 << (port & 7))) |
1d804d07 | 8182 | return true; |
908a7bdd JK |
8183 | |
8184 | port++; | |
8185 | size--; | |
8186 | last_bitmap = bitmap; | |
8187 | } | |
8188 | ||
1d804d07 | 8189 | return false; |
908a7bdd JK |
8190 | } |
8191 | ||
644d711a NHE |
8192 | /* |
8193 | * Return 1 if we should exit from L2 to L1 to handle an MSR access access, | |
8194 | * rather than handle it ourselves in L0. I.e., check whether L1 expressed | |
8195 | * disinterest in the current event (read or write a specific MSR) by using an | |
8196 | * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. | |
8197 | */ | |
8198 | static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, | |
8199 | struct vmcs12 *vmcs12, u32 exit_reason) | |
8200 | { | |
8201 | u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
8202 | gpa_t bitmap; | |
8203 | ||
cbd29cb6 | 8204 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
1d804d07 | 8205 | return true; |
644d711a NHE |
8206 | |
8207 | /* | |
8208 | * The MSR_BITMAP page is divided into four 1024-byte bitmaps, | |
8209 | * for the four combinations of read/write and low/high MSR numbers. | |
8210 | * First we need to figure out which of the four to use: | |
8211 | */ | |
8212 | bitmap = vmcs12->msr_bitmap; | |
8213 | if (exit_reason == EXIT_REASON_MSR_WRITE) | |
8214 | bitmap += 2048; | |
8215 | if (msr_index >= 0xc0000000) { | |
8216 | msr_index -= 0xc0000000; | |
8217 | bitmap += 1024; | |
8218 | } | |
8219 | ||
8220 | /* Then read the msr_index'th bit from this bitmap: */ | |
8221 | if (msr_index < 1024*8) { | |
8222 | unsigned char b; | |
54bf36aa | 8223 | if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1)) |
1d804d07 | 8224 | return true; |
644d711a NHE |
8225 | return 1 & (b >> (msr_index & 7)); |
8226 | } else | |
1d804d07 | 8227 | return true; /* let L1 handle the wrong parameter */ |
644d711a NHE |
8228 | } |
8229 | ||
8230 | /* | |
8231 | * Return 1 if we should exit from L2 to L1 to handle a CR access exit, | |
8232 | * rather than handle it ourselves in L0. I.e., check if L1 wanted to | |
8233 | * intercept (via guest_host_mask etc.) the current event. | |
8234 | */ | |
8235 | static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, | |
8236 | struct vmcs12 *vmcs12) | |
8237 | { | |
8238 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8239 | int cr = exit_qualification & 15; | |
e1d39b17 JS |
8240 | int reg; |
8241 | unsigned long val; | |
644d711a NHE |
8242 | |
8243 | switch ((exit_qualification >> 4) & 3) { | |
8244 | case 0: /* mov to cr */ | |
e1d39b17 JS |
8245 | reg = (exit_qualification >> 8) & 15; |
8246 | val = kvm_register_readl(vcpu, reg); | |
644d711a NHE |
8247 | switch (cr) { |
8248 | case 0: | |
8249 | if (vmcs12->cr0_guest_host_mask & | |
8250 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 8251 | return true; |
644d711a NHE |
8252 | break; |
8253 | case 3: | |
8254 | if ((vmcs12->cr3_target_count >= 1 && | |
8255 | vmcs12->cr3_target_value0 == val) || | |
8256 | (vmcs12->cr3_target_count >= 2 && | |
8257 | vmcs12->cr3_target_value1 == val) || | |
8258 | (vmcs12->cr3_target_count >= 3 && | |
8259 | vmcs12->cr3_target_value2 == val) || | |
8260 | (vmcs12->cr3_target_count >= 4 && | |
8261 | vmcs12->cr3_target_value3 == val)) | |
1d804d07 | 8262 | return false; |
644d711a | 8263 | if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) |
1d804d07 | 8264 | return true; |
644d711a NHE |
8265 | break; |
8266 | case 4: | |
8267 | if (vmcs12->cr4_guest_host_mask & | |
8268 | (vmcs12->cr4_read_shadow ^ val)) | |
1d804d07 | 8269 | return true; |
644d711a NHE |
8270 | break; |
8271 | case 8: | |
8272 | if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) | |
1d804d07 | 8273 | return true; |
644d711a NHE |
8274 | break; |
8275 | } | |
8276 | break; | |
8277 | case 2: /* clts */ | |
8278 | if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && | |
8279 | (vmcs12->cr0_read_shadow & X86_CR0_TS)) | |
1d804d07 | 8280 | return true; |
644d711a NHE |
8281 | break; |
8282 | case 1: /* mov from cr */ | |
8283 | switch (cr) { | |
8284 | case 3: | |
8285 | if (vmcs12->cpu_based_vm_exec_control & | |
8286 | CPU_BASED_CR3_STORE_EXITING) | |
1d804d07 | 8287 | return true; |
644d711a NHE |
8288 | break; |
8289 | case 8: | |
8290 | if (vmcs12->cpu_based_vm_exec_control & | |
8291 | CPU_BASED_CR8_STORE_EXITING) | |
1d804d07 | 8292 | return true; |
644d711a NHE |
8293 | break; |
8294 | } | |
8295 | break; | |
8296 | case 3: /* lmsw */ | |
8297 | /* | |
8298 | * lmsw can change bits 1..3 of cr0, and only set bit 0 of | |
8299 | * cr0. Other attempted changes are ignored, with no exit. | |
8300 | */ | |
e1d39b17 | 8301 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
644d711a NHE |
8302 | if (vmcs12->cr0_guest_host_mask & 0xe & |
8303 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 8304 | return true; |
644d711a NHE |
8305 | if ((vmcs12->cr0_guest_host_mask & 0x1) && |
8306 | !(vmcs12->cr0_read_shadow & 0x1) && | |
8307 | (val & 0x1)) | |
1d804d07 | 8308 | return true; |
644d711a NHE |
8309 | break; |
8310 | } | |
1d804d07 | 8311 | return false; |
644d711a NHE |
8312 | } |
8313 | ||
8314 | /* | |
8315 | * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we | |
8316 | * should handle it ourselves in L0 (and then continue L2). Only call this | |
8317 | * when in is_guest_mode (L2). | |
8318 | */ | |
7313c698 | 8319 | static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason) |
644d711a | 8320 | { |
644d711a NHE |
8321 | u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
8322 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8323 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
8324 | ||
4f350c6d JM |
8325 | if (vmx->nested.nested_run_pending) |
8326 | return false; | |
8327 | ||
8328 | if (unlikely(vmx->fail)) { | |
8329 | pr_info_ratelimited("%s failed vm entry %x\n", __func__, | |
8330 | vmcs_read32(VM_INSTRUCTION_ERROR)); | |
8331 | return true; | |
8332 | } | |
542060ea | 8333 | |
c9f04407 DM |
8334 | /* |
8335 | * The host physical addresses of some pages of guest memory | |
de3a0021 JM |
8336 | * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC |
8337 | * Page). The CPU may write to these pages via their host | |
8338 | * physical address while L2 is running, bypassing any | |
8339 | * address-translation-based dirty tracking (e.g. EPT write | |
8340 | * protection). | |
c9f04407 DM |
8341 | * |
8342 | * Mark them dirty on every exit from L2 to prevent them from | |
8343 | * getting out of sync with dirty tracking. | |
8344 | */ | |
8345 | nested_mark_vmcs12_pages_dirty(vcpu); | |
8346 | ||
4f350c6d JM |
8347 | trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason, |
8348 | vmcs_readl(EXIT_QUALIFICATION), | |
8349 | vmx->idt_vectoring_info, | |
8350 | intr_info, | |
8351 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8352 | KVM_ISA_VMX); | |
644d711a NHE |
8353 | |
8354 | switch (exit_reason) { | |
8355 | case EXIT_REASON_EXCEPTION_NMI: | |
ef85b673 | 8356 | if (is_nmi(intr_info)) |
1d804d07 | 8357 | return false; |
644d711a | 8358 | else if (is_page_fault(intr_info)) |
52a5c155 | 8359 | return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept; |
e504c909 | 8360 | else if (is_no_device(intr_info) && |
ccf9844e | 8361 | !(vmcs12->guest_cr0 & X86_CR0_TS)) |
1d804d07 | 8362 | return false; |
6f05485d JK |
8363 | else if (is_debug(intr_info) && |
8364 | vcpu->guest_debug & | |
8365 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
8366 | return false; | |
8367 | else if (is_breakpoint(intr_info) && | |
8368 | vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
8369 | return false; | |
644d711a NHE |
8370 | return vmcs12->exception_bitmap & |
8371 | (1u << (intr_info & INTR_INFO_VECTOR_MASK)); | |
8372 | case EXIT_REASON_EXTERNAL_INTERRUPT: | |
1d804d07 | 8373 | return false; |
644d711a | 8374 | case EXIT_REASON_TRIPLE_FAULT: |
1d804d07 | 8375 | return true; |
644d711a | 8376 | case EXIT_REASON_PENDING_INTERRUPT: |
3b656cf7 | 8377 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING); |
644d711a | 8378 | case EXIT_REASON_NMI_WINDOW: |
3b656cf7 | 8379 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING); |
644d711a | 8380 | case EXIT_REASON_TASK_SWITCH: |
1d804d07 | 8381 | return true; |
644d711a | 8382 | case EXIT_REASON_CPUID: |
1d804d07 | 8383 | return true; |
644d711a NHE |
8384 | case EXIT_REASON_HLT: |
8385 | return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); | |
8386 | case EXIT_REASON_INVD: | |
1d804d07 | 8387 | return true; |
644d711a NHE |
8388 | case EXIT_REASON_INVLPG: |
8389 | return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
8390 | case EXIT_REASON_RDPMC: | |
8391 | return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); | |
a5f46457 | 8392 | case EXIT_REASON_RDRAND: |
736fdf72 | 8393 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING); |
a5f46457 | 8394 | case EXIT_REASON_RDSEED: |
736fdf72 | 8395 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING); |
b3a2a907 | 8396 | case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP: |
644d711a NHE |
8397 | return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); |
8398 | case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: | |
8399 | case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: | |
8400 | case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD: | |
8401 | case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE: | |
8402 | case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: | |
a642fc30 | 8403 | case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: |
644d711a NHE |
8404 | /* |
8405 | * VMX instructions trap unconditionally. This allows L1 to | |
8406 | * emulate them for its L2 guest, i.e., allows 3-level nesting! | |
8407 | */ | |
1d804d07 | 8408 | return true; |
644d711a NHE |
8409 | case EXIT_REASON_CR_ACCESS: |
8410 | return nested_vmx_exit_handled_cr(vcpu, vmcs12); | |
8411 | case EXIT_REASON_DR_ACCESS: | |
8412 | return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); | |
8413 | case EXIT_REASON_IO_INSTRUCTION: | |
908a7bdd | 8414 | return nested_vmx_exit_handled_io(vcpu, vmcs12); |
1b07304c PB |
8415 | case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR: |
8416 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC); | |
644d711a NHE |
8417 | case EXIT_REASON_MSR_READ: |
8418 | case EXIT_REASON_MSR_WRITE: | |
8419 | return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); | |
8420 | case EXIT_REASON_INVALID_STATE: | |
1d804d07 | 8421 | return true; |
644d711a NHE |
8422 | case EXIT_REASON_MWAIT_INSTRUCTION: |
8423 | return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); | |
5f3d45e7 MD |
8424 | case EXIT_REASON_MONITOR_TRAP_FLAG: |
8425 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); | |
644d711a NHE |
8426 | case EXIT_REASON_MONITOR_INSTRUCTION: |
8427 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); | |
8428 | case EXIT_REASON_PAUSE_INSTRUCTION: | |
8429 | return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || | |
8430 | nested_cpu_has2(vmcs12, | |
8431 | SECONDARY_EXEC_PAUSE_LOOP_EXITING); | |
8432 | case EXIT_REASON_MCE_DURING_VMENTRY: | |
1d804d07 | 8433 | return false; |
644d711a | 8434 | case EXIT_REASON_TPR_BELOW_THRESHOLD: |
a7c0b07d | 8435 | return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); |
644d711a NHE |
8436 | case EXIT_REASON_APIC_ACCESS: |
8437 | return nested_cpu_has2(vmcs12, | |
8438 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
82f0dd4b | 8439 | case EXIT_REASON_APIC_WRITE: |
608406e2 WV |
8440 | case EXIT_REASON_EOI_INDUCED: |
8441 | /* apic_write and eoi_induced should exit unconditionally. */ | |
1d804d07 | 8442 | return true; |
644d711a | 8443 | case EXIT_REASON_EPT_VIOLATION: |
2b1be677 NHE |
8444 | /* |
8445 | * L0 always deals with the EPT violation. If nested EPT is | |
8446 | * used, and the nested mmu code discovers that the address is | |
8447 | * missing in the guest EPT table (EPT12), the EPT violation | |
8448 | * will be injected with nested_ept_inject_page_fault() | |
8449 | */ | |
1d804d07 | 8450 | return false; |
644d711a | 8451 | case EXIT_REASON_EPT_MISCONFIG: |
2b1be677 NHE |
8452 | /* |
8453 | * L2 never uses directly L1's EPT, but rather L0's own EPT | |
8454 | * table (shadow on EPT) or a merged EPT table that L0 built | |
8455 | * (EPT on EPT). So any problems with the structure of the | |
8456 | * table is L0's fault. | |
8457 | */ | |
1d804d07 | 8458 | return false; |
90a2db6d PB |
8459 | case EXIT_REASON_INVPCID: |
8460 | return | |
8461 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) && | |
8462 | nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
644d711a NHE |
8463 | case EXIT_REASON_WBINVD: |
8464 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); | |
8465 | case EXIT_REASON_XSETBV: | |
1d804d07 | 8466 | return true; |
81dc01f7 WL |
8467 | case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: |
8468 | /* | |
8469 | * This should never happen, since it is not possible to | |
8470 | * set XSS to a non-zero value---neither in L1 nor in L2. | |
8471 | * If if it were, XSS would have to be checked against | |
8472 | * the XSS exit bitmap in vmcs12. | |
8473 | */ | |
8474 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); | |
55123e3c WL |
8475 | case EXIT_REASON_PREEMPTION_TIMER: |
8476 | return false; | |
ab007cc9 | 8477 | case EXIT_REASON_PML_FULL: |
03efce6f | 8478 | /* We emulate PML support to L1. */ |
ab007cc9 | 8479 | return false; |
2a499e49 BD |
8480 | case EXIT_REASON_VMFUNC: |
8481 | /* VM functions are emulated through L2->L0 vmexits. */ | |
8482 | return false; | |
644d711a | 8483 | default: |
1d804d07 | 8484 | return true; |
644d711a NHE |
8485 | } |
8486 | } | |
8487 | ||
7313c698 PB |
8488 | static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason) |
8489 | { | |
8490 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
8491 | ||
8492 | /* | |
8493 | * At this point, the exit interruption info in exit_intr_info | |
8494 | * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT | |
8495 | * we need to query the in-kernel LAPIC. | |
8496 | */ | |
8497 | WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT); | |
8498 | if ((exit_intr_info & | |
8499 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) == | |
8500 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) { | |
8501 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
8502 | vmcs12->vm_exit_intr_error_code = | |
8503 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
8504 | } | |
8505 | ||
8506 | nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info, | |
8507 | vmcs_readl(EXIT_QUALIFICATION)); | |
8508 | return 1; | |
8509 | } | |
8510 | ||
586f9607 AK |
8511 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
8512 | { | |
8513 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
8514 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
8515 | } | |
8516 | ||
a3eaa864 | 8517 | static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) |
843e4330 | 8518 | { |
a3eaa864 KH |
8519 | if (vmx->pml_pg) { |
8520 | __free_page(vmx->pml_pg); | |
8521 | vmx->pml_pg = NULL; | |
8522 | } | |
843e4330 KH |
8523 | } |
8524 | ||
54bf36aa | 8525 | static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) |
843e4330 | 8526 | { |
54bf36aa | 8527 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
843e4330 KH |
8528 | u64 *pml_buf; |
8529 | u16 pml_idx; | |
8530 | ||
8531 | pml_idx = vmcs_read16(GUEST_PML_INDEX); | |
8532 | ||
8533 | /* Do nothing if PML buffer is empty */ | |
8534 | if (pml_idx == (PML_ENTITY_NUM - 1)) | |
8535 | return; | |
8536 | ||
8537 | /* PML index always points to next available PML buffer entity */ | |
8538 | if (pml_idx >= PML_ENTITY_NUM) | |
8539 | pml_idx = 0; | |
8540 | else | |
8541 | pml_idx++; | |
8542 | ||
8543 | pml_buf = page_address(vmx->pml_pg); | |
8544 | for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { | |
8545 | u64 gpa; | |
8546 | ||
8547 | gpa = pml_buf[pml_idx]; | |
8548 | WARN_ON(gpa & (PAGE_SIZE - 1)); | |
54bf36aa | 8549 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
843e4330 KH |
8550 | } |
8551 | ||
8552 | /* reset PML index */ | |
8553 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
8554 | } | |
8555 | ||
8556 | /* | |
8557 | * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. | |
8558 | * Called before reporting dirty_bitmap to userspace. | |
8559 | */ | |
8560 | static void kvm_flush_pml_buffers(struct kvm *kvm) | |
8561 | { | |
8562 | int i; | |
8563 | struct kvm_vcpu *vcpu; | |
8564 | /* | |
8565 | * We only need to kick vcpu out of guest mode here, as PML buffer | |
8566 | * is flushed at beginning of all VMEXITs, and it's obvious that only | |
8567 | * vcpus running in guest are possible to have unflushed GPAs in PML | |
8568 | * buffer. | |
8569 | */ | |
8570 | kvm_for_each_vcpu(i, vcpu, kvm) | |
8571 | kvm_vcpu_kick(vcpu); | |
8572 | } | |
8573 | ||
4eb64dce PB |
8574 | static void vmx_dump_sel(char *name, uint32_t sel) |
8575 | { | |
8576 | pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", | |
96794e4e | 8577 | name, vmcs_read16(sel), |
4eb64dce PB |
8578 | vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), |
8579 | vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), | |
8580 | vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); | |
8581 | } | |
8582 | ||
8583 | static void vmx_dump_dtsel(char *name, uint32_t limit) | |
8584 | { | |
8585 | pr_err("%s limit=0x%08x, base=0x%016lx\n", | |
8586 | name, vmcs_read32(limit), | |
8587 | vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); | |
8588 | } | |
8589 | ||
8590 | static void dump_vmcs(void) | |
8591 | { | |
8592 | u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); | |
8593 | u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); | |
8594 | u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
8595 | u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); | |
8596 | u32 secondary_exec_control = 0; | |
8597 | unsigned long cr4 = vmcs_readl(GUEST_CR4); | |
f3531054 | 8598 | u64 efer = vmcs_read64(GUEST_IA32_EFER); |
4eb64dce PB |
8599 | int i, n; |
8600 | ||
8601 | if (cpu_has_secondary_exec_ctrls()) | |
8602 | secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8603 | ||
8604 | pr_err("*** Guest State ***\n"); | |
8605 | pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8606 | vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), | |
8607 | vmcs_readl(CR0_GUEST_HOST_MASK)); | |
8608 | pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8609 | cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); | |
8610 | pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); | |
8611 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && | |
8612 | (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) | |
8613 | { | |
845c5b40 PB |
8614 | pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", |
8615 | vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); | |
8616 | pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", | |
8617 | vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); | |
4eb64dce PB |
8618 | } |
8619 | pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", | |
8620 | vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); | |
8621 | pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", | |
8622 | vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); | |
8623 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8624 | vmcs_readl(GUEST_SYSENTER_ESP), | |
8625 | vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); | |
8626 | vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); | |
8627 | vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); | |
8628 | vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); | |
8629 | vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); | |
8630 | vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); | |
8631 | vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); | |
8632 | vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); | |
8633 | vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); | |
8634 | vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); | |
8635 | vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); | |
8636 | if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || | |
8637 | (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) | |
845c5b40 PB |
8638 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8639 | efer, vmcs_read64(GUEST_IA32_PAT)); | |
8640 | pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", | |
8641 | vmcs_read64(GUEST_IA32_DEBUGCTL), | |
4eb64dce PB |
8642 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); |
8643 | if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
845c5b40 PB |
8644 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8645 | vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce | 8646 | if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) |
845c5b40 | 8647 | pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); |
4eb64dce PB |
8648 | pr_err("Interruptibility = %08x ActivityState = %08x\n", |
8649 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), | |
8650 | vmcs_read32(GUEST_ACTIVITY_STATE)); | |
8651 | if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) | |
8652 | pr_err("InterruptStatus = %04x\n", | |
8653 | vmcs_read16(GUEST_INTR_STATUS)); | |
8654 | ||
8655 | pr_err("*** Host State ***\n"); | |
8656 | pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", | |
8657 | vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); | |
8658 | pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", | |
8659 | vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), | |
8660 | vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), | |
8661 | vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), | |
8662 | vmcs_read16(HOST_TR_SELECTOR)); | |
8663 | pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", | |
8664 | vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), | |
8665 | vmcs_readl(HOST_TR_BASE)); | |
8666 | pr_err("GDTBase=%016lx IDTBase=%016lx\n", | |
8667 | vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); | |
8668 | pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", | |
8669 | vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), | |
8670 | vmcs_readl(HOST_CR4)); | |
8671 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8672 | vmcs_readl(HOST_IA32_SYSENTER_ESP), | |
8673 | vmcs_read32(HOST_IA32_SYSENTER_CS), | |
8674 | vmcs_readl(HOST_IA32_SYSENTER_EIP)); | |
8675 | if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) | |
845c5b40 PB |
8676 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8677 | vmcs_read64(HOST_IA32_EFER), | |
8678 | vmcs_read64(HOST_IA32_PAT)); | |
4eb64dce | 8679 | if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
845c5b40 PB |
8680 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8681 | vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce PB |
8682 | |
8683 | pr_err("*** Control State ***\n"); | |
8684 | pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", | |
8685 | pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); | |
8686 | pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); | |
8687 | pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", | |
8688 | vmcs_read32(EXCEPTION_BITMAP), | |
8689 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), | |
8690 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); | |
8691 | pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8692 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
8693 | vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), | |
8694 | vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); | |
8695 | pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8696 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8697 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8698 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
8699 | pr_err(" reason=%08x qualification=%016lx\n", | |
8700 | vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); | |
8701 | pr_err("IDTVectoring: info=%08x errcode=%08x\n", | |
8702 | vmcs_read32(IDT_VECTORING_INFO_FIELD), | |
8703 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
845c5b40 | 8704 | pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); |
8cfe9866 | 8705 | if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) |
845c5b40 PB |
8706 | pr_err("TSC Multiplier = 0x%016llx\n", |
8707 | vmcs_read64(TSC_MULTIPLIER)); | |
4eb64dce PB |
8708 | if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) |
8709 | pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); | |
8710 | if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) | |
8711 | pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); | |
8712 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) | |
845c5b40 | 8713 | pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); |
4eb64dce PB |
8714 | n = vmcs_read32(CR3_TARGET_COUNT); |
8715 | for (i = 0; i + 1 < n; i += 4) | |
8716 | pr_err("CR3 target%u=%016lx target%u=%016lx\n", | |
8717 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), | |
8718 | i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); | |
8719 | if (i < n) | |
8720 | pr_err("CR3 target%u=%016lx\n", | |
8721 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); | |
8722 | if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) | |
8723 | pr_err("PLE Gap=%08x Window=%08x\n", | |
8724 | vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); | |
8725 | if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) | |
8726 | pr_err("Virtual processor ID = 0x%04x\n", | |
8727 | vmcs_read16(VIRTUAL_PROCESSOR_ID)); | |
8728 | } | |
8729 | ||
6aa8b732 AK |
8730 | /* |
8731 | * The guest has exited. See if we can fix it or if we need userspace | |
8732 | * assistance. | |
8733 | */ | |
851ba692 | 8734 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 8735 | { |
29bd8a78 | 8736 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 8737 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 8738 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 8739 | |
8b89fe1f PB |
8740 | trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); |
8741 | ||
843e4330 KH |
8742 | /* |
8743 | * Flush logged GPAs PML buffer, this will make dirty_bitmap more | |
8744 | * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before | |
8745 | * querying dirty_bitmap, we only need to kick all vcpus out of guest | |
8746 | * mode as if vcpus is in root mode, the PML buffer must has been | |
8747 | * flushed already. | |
8748 | */ | |
8749 | if (enable_pml) | |
54bf36aa | 8750 | vmx_flush_pml_buffer(vcpu); |
843e4330 | 8751 | |
80ced186 | 8752 | /* If guest state is invalid, start emulating */ |
14168786 | 8753 | if (vmx->emulation_required) |
80ced186 | 8754 | return handle_invalid_guest_state(vcpu); |
1d5a4d9b | 8755 | |
7313c698 PB |
8756 | if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) |
8757 | return nested_vmx_reflect_vmexit(vcpu, exit_reason); | |
644d711a | 8758 | |
5120702e | 8759 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
4eb64dce | 8760 | dump_vmcs(); |
5120702e MG |
8761 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8762 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
8763 | = exit_reason; | |
8764 | return 0; | |
8765 | } | |
8766 | ||
29bd8a78 | 8767 | if (unlikely(vmx->fail)) { |
851ba692 AK |
8768 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8769 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
8770 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
8771 | return 0; | |
8772 | } | |
6aa8b732 | 8773 | |
b9bf6882 XG |
8774 | /* |
8775 | * Note: | |
8776 | * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by | |
8777 | * delivery event since it indicates guest is accessing MMIO. | |
8778 | * The vm-exit can be triggered again after return to guest that | |
8779 | * will cause infinite loop. | |
8780 | */ | |
d77c26fc | 8781 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 8782 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac | 8783 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
b244c9fc | 8784 | exit_reason != EXIT_REASON_PML_FULL && |
b9bf6882 XG |
8785 | exit_reason != EXIT_REASON_TASK_SWITCH)) { |
8786 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
8787 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; | |
70bcd708 | 8788 | vcpu->run->internal.ndata = 3; |
b9bf6882 XG |
8789 | vcpu->run->internal.data[0] = vectoring_info; |
8790 | vcpu->run->internal.data[1] = exit_reason; | |
70bcd708 PB |
8791 | vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; |
8792 | if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { | |
8793 | vcpu->run->internal.ndata++; | |
8794 | vcpu->run->internal.data[3] = | |
8795 | vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
8796 | } | |
b9bf6882 XG |
8797 | return 0; |
8798 | } | |
3b86cd99 | 8799 | |
d02fcf50 | 8800 | if (unlikely(!enable_vnmi && |
8a1b4392 PB |
8801 | vmx->loaded_vmcs->soft_vnmi_blocked)) { |
8802 | if (vmx_interrupt_allowed(vcpu)) { | |
8803 | vmx->loaded_vmcs->soft_vnmi_blocked = 0; | |
8804 | } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && | |
8805 | vcpu->arch.nmi_pending) { | |
8806 | /* | |
8807 | * This CPU don't support us in finding the end of an | |
8808 | * NMI-blocked window if the guest runs with IRQs | |
8809 | * disabled. So we pull the trigger after 1 s of | |
8810 | * futile waiting, but inform the user about this. | |
8811 | */ | |
8812 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
8813 | "state on VCPU %d after 1 s timeout\n", | |
8814 | __func__, vcpu->vcpu_id); | |
8815 | vmx->loaded_vmcs->soft_vnmi_blocked = 0; | |
8816 | } | |
8817 | } | |
8818 | ||
6aa8b732 AK |
8819 | if (exit_reason < kvm_vmx_max_exit_handlers |
8820 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 8821 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 8822 | else { |
6c6c5e03 RK |
8823 | vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", |
8824 | exit_reason); | |
2bc19dc3 MT |
8825 | kvm_queue_exception(vcpu, UD_VECTOR); |
8826 | return 1; | |
6aa8b732 | 8827 | } |
6aa8b732 AK |
8828 | } |
8829 | ||
95ba8273 | 8830 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 8831 | { |
a7c0b07d WL |
8832 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
8833 | ||
8834 | if (is_guest_mode(vcpu) && | |
8835 | nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
8836 | return; | |
8837 | ||
95ba8273 | 8838 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
8839 | vmcs_write32(TPR_THRESHOLD, 0); |
8840 | return; | |
8841 | } | |
8842 | ||
95ba8273 | 8843 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
8844 | } |
8845 | ||
8d14695f YZ |
8846 | static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
8847 | { | |
8848 | u32 sec_exec_control; | |
8849 | ||
dccbfcf5 RK |
8850 | /* Postpone execution until vmcs01 is the current VMCS. */ |
8851 | if (is_guest_mode(vcpu)) { | |
8852 | to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true; | |
8853 | return; | |
8854 | } | |
8855 | ||
f6e90f9e | 8856 | if (!cpu_has_vmx_virtualize_x2apic_mode()) |
8d14695f YZ |
8857 | return; |
8858 | ||
35754c98 | 8859 | if (!cpu_need_tpr_shadow(vcpu)) |
8d14695f YZ |
8860 | return; |
8861 | ||
8862 | sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8863 | ||
8864 | if (set) { | |
8865 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
8866 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8867 | } else { | |
8868 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8869 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
fb6c8198 | 8870 | vmx_flush_tlb_ept_only(vcpu); |
8d14695f YZ |
8871 | } |
8872 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control); | |
8873 | ||
904e14fb | 8874 | vmx_update_msr_bitmap(vcpu); |
8d14695f YZ |
8875 | } |
8876 | ||
38b99173 TC |
8877 | static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) |
8878 | { | |
8879 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8880 | ||
8881 | /* | |
8882 | * Currently we do not handle the nested case where L2 has an | |
8883 | * APIC access page of its own; that page is still pinned. | |
8884 | * Hence, we skip the case where the VCPU is in guest mode _and_ | |
8885 | * L1 prepared an APIC access page for L2. | |
8886 | * | |
8887 | * For the case where L1 and L2 share the same APIC access page | |
8888 | * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear | |
8889 | * in the vmcs12), this function will only update either the vmcs01 | |
8890 | * or the vmcs02. If the former, the vmcs02 will be updated by | |
8891 | * prepare_vmcs02. If the latter, the vmcs01 will be updated in | |
8892 | * the next L2->L1 exit. | |
8893 | */ | |
8894 | if (!is_guest_mode(vcpu) || | |
4f2777bc | 8895 | !nested_cpu_has2(get_vmcs12(&vmx->vcpu), |
fb6c8198 | 8896 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { |
38b99173 | 8897 | vmcs_write64(APIC_ACCESS_ADDR, hpa); |
fb6c8198 JM |
8898 | vmx_flush_tlb_ept_only(vcpu); |
8899 | } | |
38b99173 TC |
8900 | } |
8901 | ||
67c9dddc | 8902 | static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
c7c9c56c YZ |
8903 | { |
8904 | u16 status; | |
8905 | u8 old; | |
8906 | ||
67c9dddc PB |
8907 | if (max_isr == -1) |
8908 | max_isr = 0; | |
c7c9c56c YZ |
8909 | |
8910 | status = vmcs_read16(GUEST_INTR_STATUS); | |
8911 | old = status >> 8; | |
67c9dddc | 8912 | if (max_isr != old) { |
c7c9c56c | 8913 | status &= 0xff; |
67c9dddc | 8914 | status |= max_isr << 8; |
c7c9c56c YZ |
8915 | vmcs_write16(GUEST_INTR_STATUS, status); |
8916 | } | |
8917 | } | |
8918 | ||
8919 | static void vmx_set_rvi(int vector) | |
8920 | { | |
8921 | u16 status; | |
8922 | u8 old; | |
8923 | ||
4114c27d WW |
8924 | if (vector == -1) |
8925 | vector = 0; | |
8926 | ||
c7c9c56c YZ |
8927 | status = vmcs_read16(GUEST_INTR_STATUS); |
8928 | old = (u8)status & 0xff; | |
8929 | if ((u8)vector != old) { | |
8930 | status &= ~0xff; | |
8931 | status |= (u8)vector; | |
8932 | vmcs_write16(GUEST_INTR_STATUS, status); | |
8933 | } | |
8934 | } | |
8935 | ||
8936 | static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
8937 | { | |
4114c27d WW |
8938 | if (!is_guest_mode(vcpu)) { |
8939 | vmx_set_rvi(max_irr); | |
8940 | return; | |
8941 | } | |
8942 | ||
c7c9c56c YZ |
8943 | if (max_irr == -1) |
8944 | return; | |
8945 | ||
963fee16 | 8946 | /* |
4114c27d WW |
8947 | * In guest mode. If a vmexit is needed, vmx_check_nested_events |
8948 | * handles it. | |
963fee16 | 8949 | */ |
4114c27d | 8950 | if (nested_exit_on_intr(vcpu)) |
963fee16 WL |
8951 | return; |
8952 | ||
963fee16 | 8953 | /* |
4114c27d | 8954 | * Else, fall back to pre-APICv interrupt injection since L2 |
963fee16 WL |
8955 | * is run without virtual interrupt delivery. |
8956 | */ | |
8957 | if (!kvm_event_needs_reinjection(vcpu) && | |
8958 | vmx_interrupt_allowed(vcpu)) { | |
8959 | kvm_queue_interrupt(vcpu, max_irr, false); | |
8960 | vmx_inject_irq(vcpu); | |
8961 | } | |
c7c9c56c YZ |
8962 | } |
8963 | ||
76dfafd5 | 8964 | static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) |
810e6def PB |
8965 | { |
8966 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
76dfafd5 | 8967 | int max_irr; |
810e6def | 8968 | |
76dfafd5 PB |
8969 | WARN_ON(!vcpu->arch.apicv_active); |
8970 | if (pi_test_on(&vmx->pi_desc)) { | |
8971 | pi_clear_on(&vmx->pi_desc); | |
8972 | /* | |
8973 | * IOMMU can write to PIR.ON, so the barrier matters even on UP. | |
8974 | * But on x86 this is just a compiler barrier anyway. | |
8975 | */ | |
8976 | smp_mb__after_atomic(); | |
8977 | max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir); | |
8978 | } else { | |
8979 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
8980 | } | |
8981 | vmx_hwapic_irr_update(vcpu, max_irr); | |
8982 | return max_irr; | |
810e6def PB |
8983 | } |
8984 | ||
6308630b | 8985 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c | 8986 | { |
d62caabb | 8987 | if (!kvm_vcpu_apicv_active(vcpu)) |
3d81bc7e YZ |
8988 | return; |
8989 | ||
c7c9c56c YZ |
8990 | vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); |
8991 | vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); | |
8992 | vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); | |
8993 | vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); | |
8994 | } | |
8995 | ||
967235d3 PB |
8996 | static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) |
8997 | { | |
8998 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8999 | ||
9000 | pi_clear_on(&vmx->pi_desc); | |
9001 | memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); | |
9002 | } | |
9003 | ||
51aa01d1 | 9004 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 9005 | { |
48ae0fb4 JM |
9006 | u32 exit_intr_info = 0; |
9007 | u16 basic_exit_reason = (u16)vmx->exit_reason; | |
00eba012 | 9008 | |
48ae0fb4 JM |
9009 | if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY |
9010 | || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI)) | |
00eba012 AK |
9011 | return; |
9012 | ||
48ae0fb4 JM |
9013 | if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) |
9014 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9015 | vmx->exit_intr_info = exit_intr_info; | |
a0861c02 | 9016 | |
1261bfa3 WL |
9017 | /* if exit due to PF check for async PF */ |
9018 | if (is_page_fault(exit_intr_info)) | |
9019 | vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); | |
9020 | ||
a0861c02 | 9021 | /* Handle machine checks before interrupts are enabled */ |
48ae0fb4 JM |
9022 | if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY || |
9023 | is_machine_check(exit_intr_info)) | |
a0861c02 AK |
9024 | kvm_machine_check(); |
9025 | ||
20f65983 | 9026 | /* We need to handle NMIs before interrupts are enabled */ |
ef85b673 | 9027 | if (is_nmi(exit_intr_info)) { |
ff9d07a0 | 9028 | kvm_before_handle_nmi(&vmx->vcpu); |
20f65983 | 9029 | asm("int $2"); |
ff9d07a0 ZY |
9030 | kvm_after_handle_nmi(&vmx->vcpu); |
9031 | } | |
51aa01d1 | 9032 | } |
20f65983 | 9033 | |
a547c6db YZ |
9034 | static void vmx_handle_external_intr(struct kvm_vcpu *vcpu) |
9035 | { | |
9036 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9037 | ||
a547c6db YZ |
9038 | if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK)) |
9039 | == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) { | |
9040 | unsigned int vector; | |
9041 | unsigned long entry; | |
9042 | gate_desc *desc; | |
9043 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9044 | #ifdef CONFIG_X86_64 | |
9045 | unsigned long tmp; | |
9046 | #endif | |
9047 | ||
9048 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
9049 | desc = (gate_desc *)vmx->host_idt_base + vector; | |
64b163fa | 9050 | entry = gate_offset(desc); |
a547c6db YZ |
9051 | asm volatile( |
9052 | #ifdef CONFIG_X86_64 | |
9053 | "mov %%" _ASM_SP ", %[sp]\n\t" | |
9054 | "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" | |
9055 | "push $%c[ss]\n\t" | |
9056 | "push %[sp]\n\t" | |
9057 | #endif | |
9058 | "pushf\n\t" | |
a547c6db | 9059 | __ASM_SIZE(push) " $%c[cs]\n\t" |
c940a3fb | 9060 | CALL_NOSPEC |
a547c6db YZ |
9061 | : |
9062 | #ifdef CONFIG_X86_64 | |
3f62de5f | 9063 | [sp]"=&r"(tmp), |
a547c6db | 9064 | #endif |
f5caf621 | 9065 | ASM_CALL_CONSTRAINT |
a547c6db | 9066 | : |
c940a3fb | 9067 | THUNK_TARGET(entry), |
a547c6db YZ |
9068 | [ss]"i"(__KERNEL_DS), |
9069 | [cs]"i"(__KERNEL_CS) | |
9070 | ); | |
f2485b3e | 9071 | } |
a547c6db | 9072 | } |
c207aee4 | 9073 | STACK_FRAME_NON_STANDARD(vmx_handle_external_intr); |
a547c6db | 9074 | |
6d396b55 PB |
9075 | static bool vmx_has_high_real_mode_segbase(void) |
9076 | { | |
9077 | return enable_unrestricted_guest || emulate_invalid_guest_state; | |
9078 | } | |
9079 | ||
da8999d3 LJ |
9080 | static bool vmx_mpx_supported(void) |
9081 | { | |
9082 | return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && | |
9083 | (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); | |
9084 | } | |
9085 | ||
55412b2e WL |
9086 | static bool vmx_xsaves_supported(void) |
9087 | { | |
9088 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
9089 | SECONDARY_EXEC_XSAVES; | |
9090 | } | |
9091 | ||
51aa01d1 AK |
9092 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
9093 | { | |
c5ca8e57 | 9094 | u32 exit_intr_info; |
51aa01d1 AK |
9095 | bool unblock_nmi; |
9096 | u8 vector; | |
9097 | bool idtv_info_valid; | |
9098 | ||
9099 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 9100 | |
d02fcf50 | 9101 | if (enable_vnmi) { |
8a1b4392 PB |
9102 | if (vmx->loaded_vmcs->nmi_known_unmasked) |
9103 | return; | |
9104 | /* | |
9105 | * Can't use vmx->exit_intr_info since we're not sure what | |
9106 | * the exit reason is. | |
9107 | */ | |
9108 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9109 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | |
9110 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
9111 | /* | |
9112 | * SDM 3: 27.7.1.2 (September 2008) | |
9113 | * Re-set bit "block by NMI" before VM entry if vmexit caused by | |
9114 | * a guest IRET fault. | |
9115 | * SDM 3: 23.2.2 (September 2008) | |
9116 | * Bit 12 is undefined in any of the following cases: | |
9117 | * If the VM exit sets the valid bit in the IDT-vectoring | |
9118 | * information field. | |
9119 | * If the VM exit is due to a double fault. | |
9120 | */ | |
9121 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && | |
9122 | vector != DF_VECTOR && !idtv_info_valid) | |
9123 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
9124 | GUEST_INTR_STATE_NMI); | |
9125 | else | |
9126 | vmx->loaded_vmcs->nmi_known_unmasked = | |
9127 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | |
9128 | & GUEST_INTR_STATE_NMI); | |
9129 | } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) | |
9130 | vmx->loaded_vmcs->vnmi_blocked_time += | |
9131 | ktime_to_ns(ktime_sub(ktime_get(), | |
9132 | vmx->loaded_vmcs->entry_time)); | |
51aa01d1 AK |
9133 | } |
9134 | ||
3ab66e8a | 9135 | static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, |
83422e17 AK |
9136 | u32 idt_vectoring_info, |
9137 | int instr_len_field, | |
9138 | int error_code_field) | |
51aa01d1 | 9139 | { |
51aa01d1 AK |
9140 | u8 vector; |
9141 | int type; | |
9142 | bool idtv_info_valid; | |
9143 | ||
9144 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 9145 | |
3ab66e8a JK |
9146 | vcpu->arch.nmi_injected = false; |
9147 | kvm_clear_exception_queue(vcpu); | |
9148 | kvm_clear_interrupt_queue(vcpu); | |
37b96e98 GN |
9149 | |
9150 | if (!idtv_info_valid) | |
9151 | return; | |
9152 | ||
3ab66e8a | 9153 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3842d135 | 9154 | |
668f612f AK |
9155 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
9156 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 9157 | |
64a7ec06 | 9158 | switch (type) { |
37b96e98 | 9159 | case INTR_TYPE_NMI_INTR: |
3ab66e8a | 9160 | vcpu->arch.nmi_injected = true; |
668f612f | 9161 | /* |
7b4a25cb | 9162 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
9163 | * Clear bit "block by NMI" before VM entry if a NMI |
9164 | * delivery faulted. | |
668f612f | 9165 | */ |
3ab66e8a | 9166 | vmx_set_nmi_mask(vcpu, false); |
37b96e98 | 9167 | break; |
37b96e98 | 9168 | case INTR_TYPE_SOFT_EXCEPTION: |
3ab66e8a | 9169 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f GN |
9170 | /* fall through */ |
9171 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 9172 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 9173 | u32 err = vmcs_read32(error_code_field); |
851eb667 | 9174 | kvm_requeue_exception_e(vcpu, vector, err); |
35920a35 | 9175 | } else |
851eb667 | 9176 | kvm_requeue_exception(vcpu, vector); |
37b96e98 | 9177 | break; |
66fd3f7f | 9178 | case INTR_TYPE_SOFT_INTR: |
3ab66e8a | 9179 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f | 9180 | /* fall through */ |
37b96e98 | 9181 | case INTR_TYPE_EXT_INTR: |
3ab66e8a | 9182 | kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); |
37b96e98 GN |
9183 | break; |
9184 | default: | |
9185 | break; | |
f7d9238f | 9186 | } |
cf393f75 AK |
9187 | } |
9188 | ||
83422e17 AK |
9189 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
9190 | { | |
3ab66e8a | 9191 | __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, |
83422e17 AK |
9192 | VM_EXIT_INSTRUCTION_LEN, |
9193 | IDT_VECTORING_ERROR_CODE); | |
9194 | } | |
9195 | ||
b463a6f7 AK |
9196 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
9197 | { | |
3ab66e8a | 9198 | __vmx_complete_interrupts(vcpu, |
b463a6f7 AK |
9199 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), |
9200 | VM_ENTRY_INSTRUCTION_LEN, | |
9201 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
9202 | ||
9203 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
9204 | } | |
9205 | ||
d7cd9796 GN |
9206 | static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) |
9207 | { | |
9208 | int i, nr_msrs; | |
9209 | struct perf_guest_switch_msr *msrs; | |
9210 | ||
9211 | msrs = perf_guest_get_msrs(&nr_msrs); | |
9212 | ||
9213 | if (!msrs) | |
9214 | return; | |
9215 | ||
9216 | for (i = 0; i < nr_msrs; i++) | |
9217 | if (msrs[i].host == msrs[i].guest) | |
9218 | clear_atomic_switch_msr(vmx, msrs[i].msr); | |
9219 | else | |
9220 | add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, | |
9221 | msrs[i].host); | |
9222 | } | |
9223 | ||
33365e7a | 9224 | static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu) |
64672c95 YJ |
9225 | { |
9226 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9227 | u64 tscl; | |
9228 | u32 delta_tsc; | |
9229 | ||
9230 | if (vmx->hv_deadline_tsc == -1) | |
9231 | return; | |
9232 | ||
9233 | tscl = rdtsc(); | |
9234 | if (vmx->hv_deadline_tsc > tscl) | |
9235 | /* sure to be 32 bit only because checked on set_hv_timer */ | |
9236 | delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> | |
9237 | cpu_preemption_timer_multi); | |
9238 | else | |
9239 | delta_tsc = 0; | |
9240 | ||
9241 | vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); | |
9242 | } | |
9243 | ||
a3b5ba49 | 9244 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 9245 | { |
a2fa3e9f | 9246 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
d6e41f11 | 9247 | unsigned long debugctlmsr, cr3, cr4; |
104f226b | 9248 | |
8a1b4392 | 9249 | /* Record the guest's net vcpu time for enforced NMI injections. */ |
d02fcf50 | 9250 | if (unlikely(!enable_vnmi && |
8a1b4392 PB |
9251 | vmx->loaded_vmcs->soft_vnmi_blocked)) |
9252 | vmx->loaded_vmcs->entry_time = ktime_get(); | |
9253 | ||
104f226b AK |
9254 | /* Don't enter VMX if guest state is invalid, let the exit handler |
9255 | start emulation until we arrive back to a valid state */ | |
14168786 | 9256 | if (vmx->emulation_required) |
104f226b AK |
9257 | return; |
9258 | ||
a7653ecd RK |
9259 | if (vmx->ple_window_dirty) { |
9260 | vmx->ple_window_dirty = false; | |
9261 | vmcs_write32(PLE_WINDOW, vmx->ple_window); | |
9262 | } | |
9263 | ||
012f83cb AG |
9264 | if (vmx->nested.sync_shadow_vmcs) { |
9265 | copy_vmcs12_to_shadow(vmx); | |
9266 | vmx->nested.sync_shadow_vmcs = false; | |
9267 | } | |
9268 | ||
104f226b AK |
9269 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
9270 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
9271 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
9272 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
9273 | ||
d6e41f11 | 9274 | cr3 = __get_current_cr3_fast(); |
44889942 | 9275 | if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) { |
d6e41f11 | 9276 | vmcs_writel(HOST_CR3, cr3); |
44889942 | 9277 | vmx->loaded_vmcs->vmcs_host_cr3 = cr3; |
d6e41f11 AL |
9278 | } |
9279 | ||
1e02ce4c | 9280 | cr4 = cr4_read_shadow(); |
44889942 | 9281 | if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) { |
d974baa3 | 9282 | vmcs_writel(HOST_CR4, cr4); |
44889942 | 9283 | vmx->loaded_vmcs->vmcs_host_cr4 = cr4; |
d974baa3 AL |
9284 | } |
9285 | ||
104f226b AK |
9286 | /* When single-stepping over STI and MOV SS, we must clear the |
9287 | * corresponding interruptibility bits in the guest state. Otherwise | |
9288 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
9289 | * exceptions being set, but that's not correct for the guest debugging | |
9290 | * case. */ | |
9291 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
9292 | vmx_set_interrupt_shadow(vcpu, 0); | |
9293 | ||
b9dd21e1 PB |
9294 | if (static_cpu_has(X86_FEATURE_PKU) && |
9295 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && | |
9296 | vcpu->arch.pkru != vmx->host_pkru) | |
9297 | __write_pkru(vcpu->arch.pkru); | |
1be0e61c | 9298 | |
d7cd9796 | 9299 | atomic_switch_perf_msrs(vmx); |
2a7921b7 | 9300 | debugctlmsr = get_debugctlmsr(); |
d7cd9796 | 9301 | |
64672c95 YJ |
9302 | vmx_arm_hv_timer(vcpu); |
9303 | ||
d462b819 | 9304 | vmx->__launched = vmx->loaded_vmcs->launched; |
104f226b | 9305 | asm( |
6aa8b732 | 9306 | /* Store host registers */ |
b188c81f AK |
9307 | "push %%" _ASM_DX "; push %%" _ASM_BP ";" |
9308 | "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */ | |
9309 | "push %%" _ASM_CX " \n\t" | |
9310 | "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t" | |
313dbd49 | 9311 | "je 1f \n\t" |
b188c81f | 9312 | "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t" |
4ecac3fd | 9313 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 9314 | "1: \n\t" |
d3edefc0 | 9315 | /* Reload cr2 if changed */ |
b188c81f AK |
9316 | "mov %c[cr2](%0), %%" _ASM_AX " \n\t" |
9317 | "mov %%cr2, %%" _ASM_DX " \n\t" | |
9318 | "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t" | |
d3edefc0 | 9319 | "je 2f \n\t" |
b188c81f | 9320 | "mov %%" _ASM_AX", %%cr2 \n\t" |
d3edefc0 | 9321 | "2: \n\t" |
6aa8b732 | 9322 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 9323 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 9324 | /* Load guest registers. Don't clobber flags. */ |
b188c81f AK |
9325 | "mov %c[rax](%0), %%" _ASM_AX " \n\t" |
9326 | "mov %c[rbx](%0), %%" _ASM_BX " \n\t" | |
9327 | "mov %c[rdx](%0), %%" _ASM_DX " \n\t" | |
9328 | "mov %c[rsi](%0), %%" _ASM_SI " \n\t" | |
9329 | "mov %c[rdi](%0), %%" _ASM_DI " \n\t" | |
9330 | "mov %c[rbp](%0), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 9331 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
9332 | "mov %c[r8](%0), %%r8 \n\t" |
9333 | "mov %c[r9](%0), %%r9 \n\t" | |
9334 | "mov %c[r10](%0), %%r10 \n\t" | |
9335 | "mov %c[r11](%0), %%r11 \n\t" | |
9336 | "mov %c[r12](%0), %%r12 \n\t" | |
9337 | "mov %c[r13](%0), %%r13 \n\t" | |
9338 | "mov %c[r14](%0), %%r14 \n\t" | |
9339 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 9340 | #endif |
b188c81f | 9341 | "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */ |
c801949d | 9342 | |
6aa8b732 | 9343 | /* Enter guest mode */ |
83287ea4 | 9344 | "jne 1f \n\t" |
4ecac3fd | 9345 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
83287ea4 AK |
9346 | "jmp 2f \n\t" |
9347 | "1: " __ex(ASM_VMX_VMRESUME) "\n\t" | |
9348 | "2: " | |
6aa8b732 | 9349 | /* Save guest registers, load host registers, keep flags */ |
b188c81f | 9350 | "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t" |
40712fae | 9351 | "pop %0 \n\t" |
0cb5b306 | 9352 | "setbe %c[fail](%0)\n\t" |
b188c81f AK |
9353 | "mov %%" _ASM_AX ", %c[rax](%0) \n\t" |
9354 | "mov %%" _ASM_BX ", %c[rbx](%0) \n\t" | |
9355 | __ASM_SIZE(pop) " %c[rcx](%0) \n\t" | |
9356 | "mov %%" _ASM_DX ", %c[rdx](%0) \n\t" | |
9357 | "mov %%" _ASM_SI ", %c[rsi](%0) \n\t" | |
9358 | "mov %%" _ASM_DI ", %c[rdi](%0) \n\t" | |
9359 | "mov %%" _ASM_BP ", %c[rbp](%0) \n\t" | |
05b3e0c2 | 9360 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
9361 | "mov %%r8, %c[r8](%0) \n\t" |
9362 | "mov %%r9, %c[r9](%0) \n\t" | |
9363 | "mov %%r10, %c[r10](%0) \n\t" | |
9364 | "mov %%r11, %c[r11](%0) \n\t" | |
9365 | "mov %%r12, %c[r12](%0) \n\t" | |
9366 | "mov %%r13, %c[r13](%0) \n\t" | |
9367 | "mov %%r14, %c[r14](%0) \n\t" | |
9368 | "mov %%r15, %c[r15](%0) \n\t" | |
0cb5b306 JM |
9369 | "xor %%r8d, %%r8d \n\t" |
9370 | "xor %%r9d, %%r9d \n\t" | |
9371 | "xor %%r10d, %%r10d \n\t" | |
9372 | "xor %%r11d, %%r11d \n\t" | |
9373 | "xor %%r12d, %%r12d \n\t" | |
9374 | "xor %%r13d, %%r13d \n\t" | |
9375 | "xor %%r14d, %%r14d \n\t" | |
9376 | "xor %%r15d, %%r15d \n\t" | |
6aa8b732 | 9377 | #endif |
b188c81f AK |
9378 | "mov %%cr2, %%" _ASM_AX " \n\t" |
9379 | "mov %%" _ASM_AX ", %c[cr2](%0) \n\t" | |
c801949d | 9380 | |
0cb5b306 JM |
9381 | "xor %%eax, %%eax \n\t" |
9382 | "xor %%ebx, %%ebx \n\t" | |
9383 | "xor %%esi, %%esi \n\t" | |
9384 | "xor %%edi, %%edi \n\t" | |
b188c81f | 9385 | "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t" |
83287ea4 AK |
9386 | ".pushsection .rodata \n\t" |
9387 | ".global vmx_return \n\t" | |
9388 | "vmx_return: " _ASM_PTR " 2b \n\t" | |
9389 | ".popsection" | |
e08aa78a | 9390 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), |
d462b819 | 9391 | [launched]"i"(offsetof(struct vcpu_vmx, __launched)), |
e08aa78a | 9392 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), |
313dbd49 | 9393 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
9394 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
9395 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
9396 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
9397 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
9398 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
9399 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
9400 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 9401 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
9402 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
9403 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
9404 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
9405 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
9406 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
9407 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
9408 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
9409 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 9410 | #endif |
40712fae AK |
9411 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
9412 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 LV |
9413 | : "cc", "memory" |
9414 | #ifdef CONFIG_X86_64 | |
b188c81f | 9415 | , "rax", "rbx", "rdi", "rsi" |
c2036300 | 9416 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
b188c81f AK |
9417 | #else |
9418 | , "eax", "ebx", "edi", "esi" | |
c2036300 LV |
9419 | #endif |
9420 | ); | |
6aa8b732 | 9421 | |
117cc7a9 DW |
9422 | /* Eliminate branch target predictions from guest mode */ |
9423 | vmexit_fill_RSB(); | |
9424 | ||
2a7921b7 GN |
9425 | /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ |
9426 | if (debugctlmsr) | |
9427 | update_debugctlmsr(debugctlmsr); | |
9428 | ||
aa67f609 AK |
9429 | #ifndef CONFIG_X86_64 |
9430 | /* | |
9431 | * The sysexit path does not restore ds/es, so we must set them to | |
9432 | * a reasonable value ourselves. | |
9433 | * | |
9434 | * We can't defer this to vmx_load_host_state() since that function | |
9435 | * may be executed in interrupt context, which saves and restore segments | |
9436 | * around it, nullifying its effect. | |
9437 | */ | |
9438 | loadsegment(ds, __USER_DS); | |
9439 | loadsegment(es, __USER_DS); | |
9440 | #endif | |
9441 | ||
6de4f3ad | 9442 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
6de12732 | 9443 | | (1 << VCPU_EXREG_RFLAGS) |
aff48baa | 9444 | | (1 << VCPU_EXREG_PDPTR) |
2fb92db1 | 9445 | | (1 << VCPU_EXREG_SEGMENTS) |
aff48baa | 9446 | | (1 << VCPU_EXREG_CR3)); |
5fdbf976 MT |
9447 | vcpu->arch.regs_dirty = 0; |
9448 | ||
1be0e61c XG |
9449 | /* |
9450 | * eager fpu is enabled if PKEY is supported and CR4 is switched | |
9451 | * back on host, so it is safe to read guest PKRU from current | |
9452 | * XSAVE. | |
9453 | */ | |
b9dd21e1 PB |
9454 | if (static_cpu_has(X86_FEATURE_PKU) && |
9455 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { | |
9456 | vcpu->arch.pkru = __read_pkru(); | |
9457 | if (vcpu->arch.pkru != vmx->host_pkru) | |
1be0e61c | 9458 | __write_pkru(vmx->host_pkru); |
1be0e61c XG |
9459 | } |
9460 | ||
e0b890d3 GN |
9461 | /* |
9462 | * the KVM_REQ_EVENT optimization bit is only on for one entry, and if | |
9463 | * we did not inject a still-pending event to L1 now because of | |
9464 | * nested_run_pending, we need to re-enable this bit. | |
9465 | */ | |
9466 | if (vmx->nested.nested_run_pending) | |
9467 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9468 | ||
9469 | vmx->nested.nested_run_pending = 0; | |
b060ca3b JM |
9470 | vmx->idt_vectoring_info = 0; |
9471 | ||
9472 | vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); | |
9473 | if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) | |
9474 | return; | |
9475 | ||
9476 | vmx->loaded_vmcs->launched = 1; | |
9477 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
e0b890d3 | 9478 | |
51aa01d1 AK |
9479 | vmx_complete_atomic_exit(vmx); |
9480 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 9481 | vmx_complete_interrupts(vmx); |
6aa8b732 | 9482 | } |
c207aee4 | 9483 | STACK_FRAME_NON_STANDARD(vmx_vcpu_run); |
6aa8b732 | 9484 | |
1279a6b1 | 9485 | static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs) |
4fa7734c PB |
9486 | { |
9487 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9488 | int cpu; | |
9489 | ||
1279a6b1 | 9490 | if (vmx->loaded_vmcs == vmcs) |
4fa7734c PB |
9491 | return; |
9492 | ||
9493 | cpu = get_cpu(); | |
1279a6b1 | 9494 | vmx->loaded_vmcs = vmcs; |
4fa7734c PB |
9495 | vmx_vcpu_put(vcpu); |
9496 | vmx_vcpu_load(vcpu, cpu); | |
4fa7734c PB |
9497 | put_cpu(); |
9498 | } | |
9499 | ||
2f1fe811 JM |
9500 | /* |
9501 | * Ensure that the current vmcs of the logical processor is the | |
9502 | * vmcs01 of the vcpu before calling free_nested(). | |
9503 | */ | |
9504 | static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu) | |
9505 | { | |
9506 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9507 | int r; | |
9508 | ||
9509 | r = vcpu_load(vcpu); | |
9510 | BUG_ON(r); | |
1279a6b1 | 9511 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
2f1fe811 JM |
9512 | free_nested(vmx); |
9513 | vcpu_put(vcpu); | |
9514 | } | |
9515 | ||
6aa8b732 AK |
9516 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
9517 | { | |
fb3f0f51 RR |
9518 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
9519 | ||
843e4330 | 9520 | if (enable_pml) |
a3eaa864 | 9521 | vmx_destroy_pml_buffer(vmx); |
991e7a0e | 9522 | free_vpid(vmx->vpid); |
4fa7734c | 9523 | leave_guest_mode(vcpu); |
2f1fe811 | 9524 | vmx_free_vcpu_nested(vcpu); |
4fa7734c | 9525 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 RR |
9526 | kfree(vmx->guest_msrs); |
9527 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 9528 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
9529 | } |
9530 | ||
fb3f0f51 | 9531 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 9532 | { |
fb3f0f51 | 9533 | int err; |
c16f862d | 9534 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
904e14fb | 9535 | unsigned long *msr_bitmap; |
15ad7146 | 9536 | int cpu; |
6aa8b732 | 9537 | |
a2fa3e9f | 9538 | if (!vmx) |
fb3f0f51 RR |
9539 | return ERR_PTR(-ENOMEM); |
9540 | ||
991e7a0e | 9541 | vmx->vpid = allocate_vpid(); |
2384d2b3 | 9542 | |
fb3f0f51 RR |
9543 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
9544 | if (err) | |
9545 | goto free_vcpu; | |
965b58a5 | 9546 | |
4e59516a PF |
9547 | err = -ENOMEM; |
9548 | ||
9549 | /* | |
9550 | * If PML is turned on, failure on enabling PML just results in failure | |
9551 | * of creating the vcpu, therefore we can simplify PML logic (by | |
9552 | * avoiding dealing with cases, such as enabling PML partially on vcpus | |
9553 | * for the guest, etc. | |
9554 | */ | |
9555 | if (enable_pml) { | |
9556 | vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
9557 | if (!vmx->pml_pg) | |
9558 | goto uninit_vcpu; | |
9559 | } | |
9560 | ||
a2fa3e9f | 9561 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
03916db9 PB |
9562 | BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0]) |
9563 | > PAGE_SIZE); | |
0123be42 | 9564 | |
4e59516a PF |
9565 | if (!vmx->guest_msrs) |
9566 | goto free_pml; | |
965b58a5 | 9567 | |
f21f165e PB |
9568 | err = alloc_loaded_vmcs(&vmx->vmcs01); |
9569 | if (err < 0) | |
fb3f0f51 | 9570 | goto free_msrs; |
a2fa3e9f | 9571 | |
904e14fb PB |
9572 | msr_bitmap = vmx->vmcs01.msr_bitmap; |
9573 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); | |
9574 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); | |
9575 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); | |
9576 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); | |
9577 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); | |
9578 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); | |
9579 | vmx->msr_bitmap_mode = 0; | |
9580 | ||
f21f165e | 9581 | vmx->loaded_vmcs = &vmx->vmcs01; |
15ad7146 AK |
9582 | cpu = get_cpu(); |
9583 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 9584 | vmx->vcpu.cpu = cpu; |
12d79917 | 9585 | vmx_vcpu_setup(vmx); |
fb3f0f51 | 9586 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 9587 | put_cpu(); |
35754c98 | 9588 | if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
be6d05cf JK |
9589 | err = alloc_apic_access_page(kvm); |
9590 | if (err) | |
5e4a0b3c | 9591 | goto free_vmcs; |
a63cb560 | 9592 | } |
fb3f0f51 | 9593 | |
b927a3ce | 9594 | if (enable_ept) { |
f51770ed TC |
9595 | err = init_rmode_identity_map(kvm); |
9596 | if (err) | |
93ea5388 | 9597 | goto free_vmcs; |
b927a3ce | 9598 | } |
b7ebfb05 | 9599 | |
5c614b35 | 9600 | if (nested) { |
b9c237bb | 9601 | nested_vmx_setup_ctls_msrs(vmx); |
5c614b35 WL |
9602 | vmx->nested.vpid02 = allocate_vpid(); |
9603 | } | |
b9c237bb | 9604 | |
705699a1 | 9605 | vmx->nested.posted_intr_nv = -1; |
a9d30f33 | 9606 | vmx->nested.current_vmptr = -1ull; |
a9d30f33 | 9607 | |
37e4c997 HZ |
9608 | vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED; |
9609 | ||
31afb2ea PB |
9610 | /* |
9611 | * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR | |
9612 | * or POSTED_INTR_WAKEUP_VECTOR. | |
9613 | */ | |
9614 | vmx->pi_desc.nv = POSTED_INTR_VECTOR; | |
9615 | vmx->pi_desc.sn = 1; | |
9616 | ||
fb3f0f51 RR |
9617 | return &vmx->vcpu; |
9618 | ||
9619 | free_vmcs: | |
5c614b35 | 9620 | free_vpid(vmx->nested.vpid02); |
5f3fbc34 | 9621 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 | 9622 | free_msrs: |
fb3f0f51 | 9623 | kfree(vmx->guest_msrs); |
4e59516a PF |
9624 | free_pml: |
9625 | vmx_destroy_pml_buffer(vmx); | |
fb3f0f51 RR |
9626 | uninit_vcpu: |
9627 | kvm_vcpu_uninit(&vmx->vcpu); | |
9628 | free_vcpu: | |
991e7a0e | 9629 | free_vpid(vmx->vpid); |
a4770347 | 9630 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 9631 | return ERR_PTR(err); |
6aa8b732 AK |
9632 | } |
9633 | ||
002c7f7c YS |
9634 | static void __init vmx_check_processor_compat(void *rtn) |
9635 | { | |
9636 | struct vmcs_config vmcs_conf; | |
9637 | ||
9638 | *(int *)rtn = 0; | |
9639 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
9640 | *(int *)rtn = -EIO; | |
9641 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
9642 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
9643 | smp_processor_id()); | |
9644 | *(int *)rtn = -EIO; | |
9645 | } | |
9646 | } | |
9647 | ||
4b12f0de | 9648 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 9649 | { |
b18d5431 XG |
9650 | u8 cache; |
9651 | u64 ipat = 0; | |
4b12f0de | 9652 | |
522c68c4 | 9653 | /* For VT-d and EPT combination |
606decd6 | 9654 | * 1. MMIO: always map as UC |
522c68c4 SY |
9655 | * 2. EPT with VT-d: |
9656 | * a. VT-d without snooping control feature: can't guarantee the | |
606decd6 | 9657 | * result, try to trust guest. |
522c68c4 SY |
9658 | * b. VT-d with snooping control feature: snooping control feature of |
9659 | * VT-d engine can guarantee the cache correctness. Just set it | |
9660 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 9661 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
9662 | * consistent with host MTRR |
9663 | */ | |
606decd6 PB |
9664 | if (is_mmio) { |
9665 | cache = MTRR_TYPE_UNCACHABLE; | |
9666 | goto exit; | |
9667 | } | |
9668 | ||
9669 | if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { | |
b18d5431 XG |
9670 | ipat = VMX_EPT_IPAT_BIT; |
9671 | cache = MTRR_TYPE_WRBACK; | |
9672 | goto exit; | |
9673 | } | |
9674 | ||
9675 | if (kvm_read_cr0(vcpu) & X86_CR0_CD) { | |
9676 | ipat = VMX_EPT_IPAT_BIT; | |
0da029ed | 9677 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) |
fb279950 XG |
9678 | cache = MTRR_TYPE_WRBACK; |
9679 | else | |
9680 | cache = MTRR_TYPE_UNCACHABLE; | |
b18d5431 XG |
9681 | goto exit; |
9682 | } | |
9683 | ||
ff53604b | 9684 | cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); |
b18d5431 XG |
9685 | |
9686 | exit: | |
9687 | return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; | |
64d4d521 SY |
9688 | } |
9689 | ||
17cc3935 | 9690 | static int vmx_get_lpage_level(void) |
344f414f | 9691 | { |
878403b7 SY |
9692 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
9693 | return PT_DIRECTORY_LEVEL; | |
9694 | else | |
9695 | /* For shadow and EPT supported 1GB page */ | |
9696 | return PT_PDPE_LEVEL; | |
344f414f JR |
9697 | } |
9698 | ||
feda805f XG |
9699 | static void vmcs_set_secondary_exec_control(u32 new_ctl) |
9700 | { | |
9701 | /* | |
9702 | * These bits in the secondary execution controls field | |
9703 | * are dynamic, the others are mostly based on the hypervisor | |
9704 | * architecture and the guest's CPUID. Do not touch the | |
9705 | * dynamic bits. | |
9706 | */ | |
9707 | u32 mask = | |
9708 | SECONDARY_EXEC_SHADOW_VMCS | | |
9709 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | | |
9710 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
9711 | ||
9712 | u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
9713 | ||
9714 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
9715 | (new_ctl & ~mask) | (cur_ctl & mask)); | |
9716 | } | |
9717 | ||
8322ebbb DM |
9718 | /* |
9719 | * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits | |
9720 | * (indicating "allowed-1") if they are supported in the guest's CPUID. | |
9721 | */ | |
9722 | static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) | |
9723 | { | |
9724 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9725 | struct kvm_cpuid_entry2 *entry; | |
9726 | ||
9727 | vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff; | |
9728 | vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE; | |
9729 | ||
9730 | #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ | |
9731 | if (entry && (entry->_reg & (_cpuid_mask))) \ | |
9732 | vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \ | |
9733 | } while (0) | |
9734 | ||
9735 | entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); | |
9736 | cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME)); | |
9737 | cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME)); | |
9738 | cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC)); | |
9739 | cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE)); | |
9740 | cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE)); | |
9741 | cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE)); | |
9742 | cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE)); | |
9743 | cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE)); | |
9744 | cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR)); | |
9745 | cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM)); | |
9746 | cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX)); | |
9747 | cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX)); | |
9748 | cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID)); | |
9749 | cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE)); | |
9750 | ||
9751 | entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); | |
9752 | cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE)); | |
9753 | cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP)); | |
9754 | cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP)); | |
9755 | cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU)); | |
c4ad77e0 | 9756 | cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP)); |
8322ebbb DM |
9757 | |
9758 | #undef cr4_fixed1_update | |
9759 | } | |
9760 | ||
0e851880 SY |
9761 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
9762 | { | |
4e47c7a6 | 9763 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4e47c7a6 | 9764 | |
80154d77 PB |
9765 | if (cpu_has_secondary_exec_ctrls()) { |
9766 | vmx_compute_secondary_exec_control(vmx); | |
9767 | vmcs_set_secondary_exec_control(vmx->secondary_exec_control); | |
ad756a16 | 9768 | } |
8b3e34e4 | 9769 | |
37e4c997 HZ |
9770 | if (nested_vmx_allowed(vcpu)) |
9771 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
9772 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
9773 | else | |
9774 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
9775 | ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
8322ebbb DM |
9776 | |
9777 | if (nested_vmx_allowed(vcpu)) | |
9778 | nested_vmx_cr_fixed1_bits_update(vcpu); | |
0e851880 SY |
9779 | } |
9780 | ||
d4330ef2 JR |
9781 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
9782 | { | |
7b8050f5 NHE |
9783 | if (func == 1 && nested) |
9784 | entry->ecx |= bit(X86_FEATURE_VMX); | |
d4330ef2 JR |
9785 | } |
9786 | ||
25d92081 YZ |
9787 | static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, |
9788 | struct x86_exception *fault) | |
9789 | { | |
533558bc | 9790 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
c5f983f6 | 9791 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
533558bc | 9792 | u32 exit_reason; |
c5f983f6 | 9793 | unsigned long exit_qualification = vcpu->arch.exit_qualification; |
25d92081 | 9794 | |
c5f983f6 BD |
9795 | if (vmx->nested.pml_full) { |
9796 | exit_reason = EXIT_REASON_PML_FULL; | |
9797 | vmx->nested.pml_full = false; | |
9798 | exit_qualification &= INTR_INFO_UNBLOCK_NMI; | |
9799 | } else if (fault->error_code & PFERR_RSVD_MASK) | |
533558bc | 9800 | exit_reason = EXIT_REASON_EPT_MISCONFIG; |
25d92081 | 9801 | else |
533558bc | 9802 | exit_reason = EXIT_REASON_EPT_VIOLATION; |
c5f983f6 BD |
9803 | |
9804 | nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification); | |
25d92081 YZ |
9805 | vmcs12->guest_physical_address = fault->address; |
9806 | } | |
9807 | ||
995f00a6 PF |
9808 | static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu) |
9809 | { | |
bb97a016 | 9810 | return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT; |
995f00a6 PF |
9811 | } |
9812 | ||
155a97a3 NHE |
9813 | /* Callbacks for nested_ept_init_mmu_context: */ |
9814 | ||
9815 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu) | |
9816 | { | |
9817 | /* return the page table to be shadowed - in our case, EPT12 */ | |
9818 | return get_vmcs12(vcpu)->ept_pointer; | |
9819 | } | |
9820 | ||
ae1e2d10 | 9821 | static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) |
155a97a3 | 9822 | { |
ad896af0 | 9823 | WARN_ON(mmu_is_nested(vcpu)); |
a057e0e2 | 9824 | if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu))) |
ae1e2d10 PB |
9825 | return 1; |
9826 | ||
9827 | kvm_mmu_unload(vcpu); | |
ad896af0 | 9828 | kvm_init_shadow_ept_mmu(vcpu, |
b9c237bb | 9829 | to_vmx(vcpu)->nested.nested_vmx_ept_caps & |
ae1e2d10 | 9830 | VMX_EPT_EXECUTE_ONLY_BIT, |
a057e0e2 | 9831 | nested_ept_ad_enabled(vcpu)); |
155a97a3 NHE |
9832 | vcpu->arch.mmu.set_cr3 = vmx_set_cr3; |
9833 | vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3; | |
9834 | vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault; | |
9835 | ||
9836 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
ae1e2d10 | 9837 | return 0; |
155a97a3 NHE |
9838 | } |
9839 | ||
9840 | static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
9841 | { | |
9842 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
9843 | } | |
9844 | ||
19d5f10b EK |
9845 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, |
9846 | u16 error_code) | |
9847 | { | |
9848 | bool inequality, bit; | |
9849 | ||
9850 | bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0; | |
9851 | inequality = | |
9852 | (error_code & vmcs12->page_fault_error_code_mask) != | |
9853 | vmcs12->page_fault_error_code_match; | |
9854 | return inequality ^ bit; | |
9855 | } | |
9856 | ||
feaf0c7d GN |
9857 | static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, |
9858 | struct x86_exception *fault) | |
9859 | { | |
9860 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
9861 | ||
9862 | WARN_ON(!is_guest_mode(vcpu)); | |
9863 | ||
305d0ab4 WL |
9864 | if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) && |
9865 | !to_vmx(vcpu)->nested.nested_run_pending) { | |
b96fb439 PB |
9866 | vmcs12->vm_exit_intr_error_code = fault->error_code; |
9867 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
9868 | PF_VECTOR | INTR_TYPE_HARD_EXCEPTION | | |
9869 | INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK, | |
9870 | fault->address); | |
7313c698 | 9871 | } else { |
feaf0c7d | 9872 | kvm_inject_page_fault(vcpu, fault); |
7313c698 | 9873 | } |
feaf0c7d GN |
9874 | } |
9875 | ||
6beb7bd5 JM |
9876 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, |
9877 | struct vmcs12 *vmcs12); | |
9878 | ||
9879 | static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu, | |
a2bcba50 WL |
9880 | struct vmcs12 *vmcs12) |
9881 | { | |
9882 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5e2f30b7 | 9883 | struct page *page; |
6beb7bd5 | 9884 | u64 hpa; |
a2bcba50 WL |
9885 | |
9886 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
a2bcba50 WL |
9887 | /* |
9888 | * Translate L1 physical address to host physical | |
9889 | * address for vmcs02. Keep the page pinned, so this | |
9890 | * physical address remains valid. We keep a reference | |
9891 | * to it so we can release it later. | |
9892 | */ | |
5e2f30b7 | 9893 | if (vmx->nested.apic_access_page) { /* shouldn't happen */ |
53a70daf | 9894 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
5e2f30b7 DH |
9895 | vmx->nested.apic_access_page = NULL; |
9896 | } | |
9897 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr); | |
6beb7bd5 JM |
9898 | /* |
9899 | * If translation failed, no matter: This feature asks | |
9900 | * to exit when accessing the given address, and if it | |
9901 | * can never be accessed, this feature won't do | |
9902 | * anything anyway. | |
9903 | */ | |
5e2f30b7 DH |
9904 | if (!is_error_page(page)) { |
9905 | vmx->nested.apic_access_page = page; | |
6beb7bd5 JM |
9906 | hpa = page_to_phys(vmx->nested.apic_access_page); |
9907 | vmcs_write64(APIC_ACCESS_ADDR, hpa); | |
9908 | } else { | |
9909 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
9910 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
9911 | } | |
9912 | } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) && | |
9913 | cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { | |
9914 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
9915 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
9916 | kvm_vcpu_reload_apic_access_page(vcpu); | |
a2bcba50 | 9917 | } |
a7c0b07d WL |
9918 | |
9919 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
5e2f30b7 | 9920 | if (vmx->nested.virtual_apic_page) { /* shouldn't happen */ |
53a70daf | 9921 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
5e2f30b7 DH |
9922 | vmx->nested.virtual_apic_page = NULL; |
9923 | } | |
9924 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr); | |
a7c0b07d WL |
9925 | |
9926 | /* | |
6beb7bd5 JM |
9927 | * If translation failed, VM entry will fail because |
9928 | * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull. | |
9929 | * Failing the vm entry is _not_ what the processor | |
9930 | * does but it's basically the only possibility we | |
9931 | * have. We could still enter the guest if CR8 load | |
9932 | * exits are enabled, CR8 store exits are enabled, and | |
9933 | * virtualize APIC access is disabled; in this case | |
9934 | * the processor would never use the TPR shadow and we | |
9935 | * could simply clear the bit from the execution | |
9936 | * control. But such a configuration is useless, so | |
9937 | * let's keep the code simple. | |
a7c0b07d | 9938 | */ |
5e2f30b7 DH |
9939 | if (!is_error_page(page)) { |
9940 | vmx->nested.virtual_apic_page = page; | |
6beb7bd5 JM |
9941 | hpa = page_to_phys(vmx->nested.virtual_apic_page); |
9942 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa); | |
9943 | } | |
a7c0b07d WL |
9944 | } |
9945 | ||
705699a1 | 9946 | if (nested_cpu_has_posted_intr(vmcs12)) { |
705699a1 WV |
9947 | if (vmx->nested.pi_desc_page) { /* shouldn't happen */ |
9948 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 9949 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
5e2f30b7 | 9950 | vmx->nested.pi_desc_page = NULL; |
705699a1 | 9951 | } |
5e2f30b7 DH |
9952 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr); |
9953 | if (is_error_page(page)) | |
6beb7bd5 | 9954 | return; |
5e2f30b7 DH |
9955 | vmx->nested.pi_desc_page = page; |
9956 | vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page); | |
705699a1 WV |
9957 | vmx->nested.pi_desc = |
9958 | (struct pi_desc *)((void *)vmx->nested.pi_desc + | |
9959 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
9960 | (PAGE_SIZE - 1))); | |
6beb7bd5 JM |
9961 | vmcs_write64(POSTED_INTR_DESC_ADDR, |
9962 | page_to_phys(vmx->nested.pi_desc_page) + | |
9963 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
9964 | (PAGE_SIZE - 1))); | |
705699a1 | 9965 | } |
6beb7bd5 JM |
9966 | if (cpu_has_vmx_msr_bitmap() && |
9967 | nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) && | |
9968 | nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) | |
9969 | ; | |
9970 | else | |
9971 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, | |
9972 | CPU_BASED_USE_MSR_BITMAPS); | |
a2bcba50 WL |
9973 | } |
9974 | ||
f4124500 JK |
9975 | static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu) |
9976 | { | |
9977 | u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value; | |
9978 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9979 | ||
9980 | if (vcpu->arch.virtual_tsc_khz == 0) | |
9981 | return; | |
9982 | ||
9983 | /* Make sure short timeouts reliably trigger an immediate vmexit. | |
9984 | * hrtimer_start does not guarantee this. */ | |
9985 | if (preemption_timeout <= 1) { | |
9986 | vmx_preemption_timer_fn(&vmx->nested.preemption_timer); | |
9987 | return; | |
9988 | } | |
9989 | ||
9990 | preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
9991 | preemption_timeout *= 1000000; | |
9992 | do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); | |
9993 | hrtimer_start(&vmx->nested.preemption_timer, | |
9994 | ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL); | |
9995 | } | |
9996 | ||
56a20510 JM |
9997 | static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu, |
9998 | struct vmcs12 *vmcs12) | |
9999 | { | |
10000 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) | |
10001 | return 0; | |
10002 | ||
10003 | if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) || | |
10004 | !page_address_valid(vcpu, vmcs12->io_bitmap_b)) | |
10005 | return -EINVAL; | |
10006 | ||
10007 | return 0; | |
10008 | } | |
10009 | ||
3af18d9c WV |
10010 | static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, |
10011 | struct vmcs12 *vmcs12) | |
10012 | { | |
3af18d9c WV |
10013 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
10014 | return 0; | |
10015 | ||
5fa99cbe | 10016 | if (!page_address_valid(vcpu, vmcs12->msr_bitmap)) |
3af18d9c WV |
10017 | return -EINVAL; |
10018 | ||
10019 | return 0; | |
10020 | } | |
10021 | ||
712b12d7 JM |
10022 | static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu, |
10023 | struct vmcs12 *vmcs12) | |
10024 | { | |
10025 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
10026 | return 0; | |
10027 | ||
10028 | if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr)) | |
10029 | return -EINVAL; | |
10030 | ||
10031 | return 0; | |
10032 | } | |
10033 | ||
3af18d9c WV |
10034 | /* |
10035 | * Merge L0's and L1's MSR bitmap, return false to indicate that | |
10036 | * we do not use the hardware. | |
10037 | */ | |
10038 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, | |
10039 | struct vmcs12 *vmcs12) | |
10040 | { | |
82f0dd4b | 10041 | int msr; |
f2b93280 | 10042 | struct page *page; |
d048c098 | 10043 | unsigned long *msr_bitmap_l1; |
904e14fb | 10044 | unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap; |
f2b93280 | 10045 | |
d048c098 | 10046 | /* This shortcut is ok because we support only x2APIC MSRs so far. */ |
f2b93280 WV |
10047 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12)) |
10048 | return false; | |
10049 | ||
5e2f30b7 DH |
10050 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap); |
10051 | if (is_error_page(page)) | |
f2b93280 | 10052 | return false; |
d048c098 | 10053 | msr_bitmap_l1 = (unsigned long *)kmap(page); |
f2b93280 | 10054 | |
d048c098 RK |
10055 | memset(msr_bitmap_l0, 0xff, PAGE_SIZE); |
10056 | ||
f2b93280 | 10057 | if (nested_cpu_has_virt_x2apic_mode(vmcs12)) { |
82f0dd4b WV |
10058 | if (nested_cpu_has_apic_reg_virt(vmcs12)) |
10059 | for (msr = 0x800; msr <= 0x8ff; msr++) | |
10060 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 10061 | msr_bitmap_l1, msr_bitmap_l0, |
82f0dd4b | 10062 | msr, MSR_TYPE_R); |
d048c098 RK |
10063 | |
10064 | nested_vmx_disable_intercept_for_msr( | |
10065 | msr_bitmap_l1, msr_bitmap_l0, | |
f2b93280 WV |
10066 | APIC_BASE_MSR + (APIC_TASKPRI >> 4), |
10067 | MSR_TYPE_R | MSR_TYPE_W); | |
d048c098 | 10068 | |
608406e2 | 10069 | if (nested_cpu_has_vid(vmcs12)) { |
608406e2 | 10070 | nested_vmx_disable_intercept_for_msr( |
d048c098 | 10071 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
10072 | APIC_BASE_MSR + (APIC_EOI >> 4), |
10073 | MSR_TYPE_W); | |
10074 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 10075 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
10076 | APIC_BASE_MSR + (APIC_SELF_IPI >> 4), |
10077 | MSR_TYPE_W); | |
10078 | } | |
82f0dd4b | 10079 | } |
f2b93280 | 10080 | kunmap(page); |
53a70daf | 10081 | kvm_release_page_clean(page); |
f2b93280 WV |
10082 | |
10083 | return true; | |
10084 | } | |
10085 | ||
10086 | static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu, | |
10087 | struct vmcs12 *vmcs12) | |
10088 | { | |
82f0dd4b | 10089 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && |
608406e2 | 10090 | !nested_cpu_has_apic_reg_virt(vmcs12) && |
705699a1 WV |
10091 | !nested_cpu_has_vid(vmcs12) && |
10092 | !nested_cpu_has_posted_intr(vmcs12)) | |
f2b93280 WV |
10093 | return 0; |
10094 | ||
10095 | /* | |
10096 | * If virtualize x2apic mode is enabled, | |
10097 | * virtualize apic access must be disabled. | |
10098 | */ | |
82f0dd4b WV |
10099 | if (nested_cpu_has_virt_x2apic_mode(vmcs12) && |
10100 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
f2b93280 WV |
10101 | return -EINVAL; |
10102 | ||
608406e2 WV |
10103 | /* |
10104 | * If virtual interrupt delivery is enabled, | |
10105 | * we must exit on external interrupts. | |
10106 | */ | |
10107 | if (nested_cpu_has_vid(vmcs12) && | |
10108 | !nested_exit_on_intr(vcpu)) | |
10109 | return -EINVAL; | |
10110 | ||
705699a1 WV |
10111 | /* |
10112 | * bits 15:8 should be zero in posted_intr_nv, | |
10113 | * the descriptor address has been already checked | |
10114 | * in nested_get_vmcs12_pages. | |
10115 | */ | |
10116 | if (nested_cpu_has_posted_intr(vmcs12) && | |
10117 | (!nested_cpu_has_vid(vmcs12) || | |
10118 | !nested_exit_intr_ack_set(vcpu) || | |
10119 | vmcs12->posted_intr_nv & 0xff00)) | |
10120 | return -EINVAL; | |
10121 | ||
f2b93280 WV |
10122 | /* tpr shadow is needed by all apicv features. */ |
10123 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
10124 | return -EINVAL; | |
10125 | ||
10126 | return 0; | |
3af18d9c WV |
10127 | } |
10128 | ||
e9ac033e EK |
10129 | static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu, |
10130 | unsigned long count_field, | |
92d71bc6 | 10131 | unsigned long addr_field) |
ff651cb6 | 10132 | { |
92d71bc6 | 10133 | int maxphyaddr; |
e9ac033e EK |
10134 | u64 count, addr; |
10135 | ||
10136 | if (vmcs12_read_any(vcpu, count_field, &count) || | |
10137 | vmcs12_read_any(vcpu, addr_field, &addr)) { | |
10138 | WARN_ON(1); | |
10139 | return -EINVAL; | |
10140 | } | |
10141 | if (count == 0) | |
10142 | return 0; | |
92d71bc6 | 10143 | maxphyaddr = cpuid_maxphyaddr(vcpu); |
e9ac033e EK |
10144 | if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr || |
10145 | (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) { | |
bbe41b95 | 10146 | pr_debug_ratelimited( |
e9ac033e EK |
10147 | "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)", |
10148 | addr_field, maxphyaddr, count, addr); | |
10149 | return -EINVAL; | |
10150 | } | |
10151 | return 0; | |
10152 | } | |
10153 | ||
10154 | static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu, | |
10155 | struct vmcs12 *vmcs12) | |
10156 | { | |
e9ac033e EK |
10157 | if (vmcs12->vm_exit_msr_load_count == 0 && |
10158 | vmcs12->vm_exit_msr_store_count == 0 && | |
10159 | vmcs12->vm_entry_msr_load_count == 0) | |
10160 | return 0; /* Fast path */ | |
e9ac033e | 10161 | if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT, |
92d71bc6 | 10162 | VM_EXIT_MSR_LOAD_ADDR) || |
e9ac033e | 10163 | nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT, |
92d71bc6 | 10164 | VM_EXIT_MSR_STORE_ADDR) || |
e9ac033e | 10165 | nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT, |
92d71bc6 | 10166 | VM_ENTRY_MSR_LOAD_ADDR)) |
e9ac033e EK |
10167 | return -EINVAL; |
10168 | return 0; | |
10169 | } | |
10170 | ||
c5f983f6 BD |
10171 | static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu, |
10172 | struct vmcs12 *vmcs12) | |
10173 | { | |
10174 | u64 address = vmcs12->pml_address; | |
10175 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
10176 | ||
10177 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) { | |
10178 | if (!nested_cpu_has_ept(vmcs12) || | |
10179 | !IS_ALIGNED(address, 4096) || | |
10180 | address >> maxphyaddr) | |
10181 | return -EINVAL; | |
10182 | } | |
10183 | ||
10184 | return 0; | |
10185 | } | |
10186 | ||
e9ac033e EK |
10187 | static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu, |
10188 | struct vmx_msr_entry *e) | |
10189 | { | |
10190 | /* x2APIC MSR accesses are not allowed */ | |
8a9781f7 | 10191 | if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8) |
e9ac033e EK |
10192 | return -EINVAL; |
10193 | if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */ | |
10194 | e->index == MSR_IA32_UCODE_REV) | |
10195 | return -EINVAL; | |
10196 | if (e->reserved != 0) | |
ff651cb6 WV |
10197 | return -EINVAL; |
10198 | return 0; | |
10199 | } | |
10200 | ||
e9ac033e EK |
10201 | static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu, |
10202 | struct vmx_msr_entry *e) | |
ff651cb6 WV |
10203 | { |
10204 | if (e->index == MSR_FS_BASE || | |
10205 | e->index == MSR_GS_BASE || | |
e9ac033e EK |
10206 | e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */ |
10207 | nested_vmx_msr_check_common(vcpu, e)) | |
10208 | return -EINVAL; | |
10209 | return 0; | |
10210 | } | |
10211 | ||
10212 | static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu, | |
10213 | struct vmx_msr_entry *e) | |
10214 | { | |
10215 | if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */ | |
10216 | nested_vmx_msr_check_common(vcpu, e)) | |
ff651cb6 WV |
10217 | return -EINVAL; |
10218 | return 0; | |
10219 | } | |
10220 | ||
10221 | /* | |
10222 | * Load guest's/host's msr at nested entry/exit. | |
10223 | * return 0 for success, entry index for failure. | |
10224 | */ | |
10225 | static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
10226 | { | |
10227 | u32 i; | |
10228 | struct vmx_msr_entry e; | |
10229 | struct msr_data msr; | |
10230 | ||
10231 | msr.host_initiated = false; | |
10232 | for (i = 0; i < count; i++) { | |
54bf36aa PB |
10233 | if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e), |
10234 | &e, sizeof(e))) { | |
bbe41b95 | 10235 | pr_debug_ratelimited( |
e9ac033e EK |
10236 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
10237 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 10238 | goto fail; |
e9ac033e EK |
10239 | } |
10240 | if (nested_vmx_load_msr_check(vcpu, &e)) { | |
bbe41b95 | 10241 | pr_debug_ratelimited( |
e9ac033e EK |
10242 | "%s check failed (%u, 0x%x, 0x%x)\n", |
10243 | __func__, i, e.index, e.reserved); | |
10244 | goto fail; | |
10245 | } | |
ff651cb6 WV |
10246 | msr.index = e.index; |
10247 | msr.data = e.value; | |
e9ac033e | 10248 | if (kvm_set_msr(vcpu, &msr)) { |
bbe41b95 | 10249 | pr_debug_ratelimited( |
e9ac033e EK |
10250 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
10251 | __func__, i, e.index, e.value); | |
ff651cb6 | 10252 | goto fail; |
e9ac033e | 10253 | } |
ff651cb6 WV |
10254 | } |
10255 | return 0; | |
10256 | fail: | |
10257 | return i + 1; | |
10258 | } | |
10259 | ||
10260 | static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
10261 | { | |
10262 | u32 i; | |
10263 | struct vmx_msr_entry e; | |
10264 | ||
10265 | for (i = 0; i < count; i++) { | |
609e36d3 | 10266 | struct msr_data msr_info; |
54bf36aa PB |
10267 | if (kvm_vcpu_read_guest(vcpu, |
10268 | gpa + i * sizeof(e), | |
10269 | &e, 2 * sizeof(u32))) { | |
bbe41b95 | 10270 | pr_debug_ratelimited( |
e9ac033e EK |
10271 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
10272 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 10273 | return -EINVAL; |
e9ac033e EK |
10274 | } |
10275 | if (nested_vmx_store_msr_check(vcpu, &e)) { | |
bbe41b95 | 10276 | pr_debug_ratelimited( |
e9ac033e EK |
10277 | "%s check failed (%u, 0x%x, 0x%x)\n", |
10278 | __func__, i, e.index, e.reserved); | |
ff651cb6 | 10279 | return -EINVAL; |
e9ac033e | 10280 | } |
609e36d3 PB |
10281 | msr_info.host_initiated = false; |
10282 | msr_info.index = e.index; | |
10283 | if (kvm_get_msr(vcpu, &msr_info)) { | |
bbe41b95 | 10284 | pr_debug_ratelimited( |
e9ac033e EK |
10285 | "%s cannot read MSR (%u, 0x%x)\n", |
10286 | __func__, i, e.index); | |
10287 | return -EINVAL; | |
10288 | } | |
54bf36aa PB |
10289 | if (kvm_vcpu_write_guest(vcpu, |
10290 | gpa + i * sizeof(e) + | |
10291 | offsetof(struct vmx_msr_entry, value), | |
10292 | &msr_info.data, sizeof(msr_info.data))) { | |
bbe41b95 | 10293 | pr_debug_ratelimited( |
e9ac033e | 10294 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
609e36d3 | 10295 | __func__, i, e.index, msr_info.data); |
e9ac033e EK |
10296 | return -EINVAL; |
10297 | } | |
ff651cb6 WV |
10298 | } |
10299 | return 0; | |
10300 | } | |
10301 | ||
1dc35dac LP |
10302 | static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val) |
10303 | { | |
10304 | unsigned long invalid_mask; | |
10305 | ||
10306 | invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu); | |
10307 | return (val & invalid_mask) == 0; | |
10308 | } | |
10309 | ||
9ed38ffa LP |
10310 | /* |
10311 | * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are | |
10312 | * emulating VM entry into a guest with EPT enabled. | |
10313 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code | |
10314 | * is assigned to entry_failure_code on failure. | |
10315 | */ | |
10316 | static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept, | |
ca0bde28 | 10317 | u32 *entry_failure_code) |
9ed38ffa | 10318 | { |
9ed38ffa | 10319 | if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) { |
1dc35dac | 10320 | if (!nested_cr3_valid(vcpu, cr3)) { |
9ed38ffa LP |
10321 | *entry_failure_code = ENTRY_FAIL_DEFAULT; |
10322 | return 1; | |
10323 | } | |
10324 | ||
10325 | /* | |
10326 | * If PAE paging and EPT are both on, CR3 is not used by the CPU and | |
10327 | * must not be dereferenced. | |
10328 | */ | |
10329 | if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) && | |
10330 | !nested_ept) { | |
10331 | if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) { | |
10332 | *entry_failure_code = ENTRY_FAIL_PDPTE; | |
10333 | return 1; | |
10334 | } | |
10335 | } | |
10336 | ||
10337 | vcpu->arch.cr3 = cr3; | |
10338 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
10339 | } | |
10340 | ||
10341 | kvm_mmu_reset_context(vcpu); | |
10342 | return 0; | |
10343 | } | |
10344 | ||
fe3ef05c NHE |
10345 | /* |
10346 | * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested | |
10347 | * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it | |
b4619660 | 10348 | * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 |
fe3ef05c NHE |
10349 | * guest in a way that will both be appropriate to L1's requests, and our |
10350 | * needs. In addition to modifying the active vmcs (which is vmcs02), this | |
10351 | * function also has additional necessary side-effects, like setting various | |
10352 | * vcpu->arch fields. | |
ee146c1c LP |
10353 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code |
10354 | * is assigned to entry_failure_code on failure. | |
fe3ef05c | 10355 | */ |
ee146c1c | 10356 | static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, |
ca0bde28 | 10357 | bool from_vmentry, u32 *entry_failure_code) |
fe3ef05c NHE |
10358 | { |
10359 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
03efce6f | 10360 | u32 exec_control, vmcs12_exec_ctrl; |
fe3ef05c NHE |
10361 | |
10362 | vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); | |
10363 | vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); | |
10364 | vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); | |
10365 | vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); | |
10366 | vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); | |
10367 | vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); | |
10368 | vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); | |
10369 | vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); | |
10370 | vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); | |
10371 | vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); | |
10372 | vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); | |
10373 | vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); | |
10374 | vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); | |
10375 | vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); | |
10376 | vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); | |
10377 | vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); | |
10378 | vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); | |
10379 | vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); | |
10380 | vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); | |
10381 | vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); | |
10382 | vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); | |
10383 | vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); | |
10384 | vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); | |
10385 | vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); | |
10386 | vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); | |
10387 | vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); | |
10388 | vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); | |
10389 | vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); | |
10390 | vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); | |
10391 | vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); | |
10392 | vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); | |
10393 | vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); | |
10394 | vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); | |
10395 | vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); | |
10396 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); | |
10397 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); | |
10398 | ||
cf8b84f4 JM |
10399 | if (from_vmentry && |
10400 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) { | |
2996fca0 JK |
10401 | kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); |
10402 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); | |
10403 | } else { | |
10404 | kvm_set_dr(vcpu, 7, vcpu->arch.dr7); | |
10405 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl); | |
10406 | } | |
cf8b84f4 JM |
10407 | if (from_vmentry) { |
10408 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
10409 | vmcs12->vm_entry_intr_info_field); | |
10410 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
10411 | vmcs12->vm_entry_exception_error_code); | |
10412 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
10413 | vmcs12->vm_entry_instruction_len); | |
10414 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
10415 | vmcs12->guest_interruptibility_info); | |
2d6144e3 WL |
10416 | vmx->loaded_vmcs->nmi_known_unmasked = |
10417 | !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI); | |
cf8b84f4 JM |
10418 | } else { |
10419 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
10420 | } | |
fe3ef05c | 10421 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); |
63fbf59f | 10422 | vmx_set_rflags(vcpu, vmcs12->guest_rflags); |
fe3ef05c NHE |
10423 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, |
10424 | vmcs12->guest_pending_dbg_exceptions); | |
10425 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); | |
10426 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); | |
10427 | ||
81dc01f7 WL |
10428 | if (nested_cpu_has_xsaves(vmcs12)) |
10429 | vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); | |
fe3ef05c NHE |
10430 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
10431 | ||
f4124500 | 10432 | exec_control = vmcs12->pin_based_vm_exec_control; |
9314006d PB |
10433 | |
10434 | /* Preemption timer setting is only taken from vmcs01. */ | |
705699a1 | 10435 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; |
9314006d PB |
10436 | exec_control |= vmcs_config.pin_based_exec_ctrl; |
10437 | if (vmx->hv_deadline_tsc == -1) | |
10438 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
705699a1 | 10439 | |
9314006d | 10440 | /* Posted interrupts setting is only taken from vmcs12. */ |
705699a1 | 10441 | if (nested_cpu_has_posted_intr(vmcs12)) { |
705699a1 WV |
10442 | vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv; |
10443 | vmx->nested.pi_pending = false; | |
06a5524f | 10444 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR); |
6beb7bd5 | 10445 | } else { |
705699a1 | 10446 | exec_control &= ~PIN_BASED_POSTED_INTR; |
6beb7bd5 | 10447 | } |
705699a1 | 10448 | |
f4124500 | 10449 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control); |
fe3ef05c | 10450 | |
f4124500 JK |
10451 | vmx->nested.preemption_timer_expired = false; |
10452 | if (nested_cpu_has_preemption_timer(vmcs12)) | |
10453 | vmx_start_preemption_timer(vcpu); | |
0238ea91 | 10454 | |
fe3ef05c NHE |
10455 | /* |
10456 | * Whether page-faults are trapped is determined by a combination of | |
10457 | * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. | |
10458 | * If enable_ept, L0 doesn't care about page faults and we should | |
10459 | * set all of these to L1's desires. However, if !enable_ept, L0 does | |
10460 | * care about (at least some) page faults, and because it is not easy | |
10461 | * (if at all possible?) to merge L0 and L1's desires, we simply ask | |
10462 | * to exit on each and every L2 page fault. This is done by setting | |
10463 | * MASK=MATCH=0 and (see below) EB.PF=1. | |
10464 | * Note that below we don't need special code to set EB.PF beyond the | |
10465 | * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, | |
10466 | * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when | |
10467 | * !enable_ept, EB.PF is 1, so the "or" will always be 1. | |
fe3ef05c NHE |
10468 | */ |
10469 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, | |
10470 | enable_ept ? vmcs12->page_fault_error_code_mask : 0); | |
10471 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, | |
10472 | enable_ept ? vmcs12->page_fault_error_code_match : 0); | |
10473 | ||
10474 | if (cpu_has_secondary_exec_ctrls()) { | |
80154d77 | 10475 | exec_control = vmx->secondary_exec_control; |
e2821620 | 10476 | |
fe3ef05c | 10477 | /* Take the following fields only from vmcs12 */ |
696dfd95 | 10478 | exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
90a2db6d | 10479 | SECONDARY_EXEC_ENABLE_INVPCID | |
b3a2a907 | 10480 | SECONDARY_EXEC_RDTSCP | |
3db13480 | 10481 | SECONDARY_EXEC_XSAVES | |
696dfd95 | 10482 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
27c42a1b BD |
10483 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
10484 | SECONDARY_EXEC_ENABLE_VMFUNC); | |
fe3ef05c | 10485 | if (nested_cpu_has(vmcs12, |
03efce6f BD |
10486 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) { |
10487 | vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control & | |
10488 | ~SECONDARY_EXEC_ENABLE_PML; | |
10489 | exec_control |= vmcs12_exec_ctrl; | |
10490 | } | |
fe3ef05c | 10491 | |
27c42a1b BD |
10492 | /* All VMFUNCs are currently emulated through L0 vmexits. */ |
10493 | if (exec_control & SECONDARY_EXEC_ENABLE_VMFUNC) | |
10494 | vmcs_write64(VM_FUNCTION_CONTROL, 0); | |
10495 | ||
608406e2 WV |
10496 | if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { |
10497 | vmcs_write64(EOI_EXIT_BITMAP0, | |
10498 | vmcs12->eoi_exit_bitmap0); | |
10499 | vmcs_write64(EOI_EXIT_BITMAP1, | |
10500 | vmcs12->eoi_exit_bitmap1); | |
10501 | vmcs_write64(EOI_EXIT_BITMAP2, | |
10502 | vmcs12->eoi_exit_bitmap2); | |
10503 | vmcs_write64(EOI_EXIT_BITMAP3, | |
10504 | vmcs12->eoi_exit_bitmap3); | |
10505 | vmcs_write16(GUEST_INTR_STATUS, | |
10506 | vmcs12->guest_intr_status); | |
10507 | } | |
10508 | ||
6beb7bd5 JM |
10509 | /* |
10510 | * Write an illegal value to APIC_ACCESS_ADDR. Later, | |
10511 | * nested_get_vmcs12_pages will either fix it up or | |
10512 | * remove the VM execution control. | |
10513 | */ | |
10514 | if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) | |
10515 | vmcs_write64(APIC_ACCESS_ADDR, -1ull); | |
10516 | ||
fe3ef05c NHE |
10517 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
10518 | } | |
10519 | ||
10520 | ||
10521 | /* | |
10522 | * Set host-state according to L0's settings (vmcs12 is irrelevant here) | |
10523 | * Some constant fields are set here by vmx_set_constant_host_state(). | |
10524 | * Other fields are different per CPU, and will be set later when | |
10525 | * vmx_vcpu_load() is called, and when vmx_save_host_state() is called. | |
10526 | */ | |
a547c6db | 10527 | vmx_set_constant_host_state(vmx); |
fe3ef05c | 10528 | |
83bafef1 JM |
10529 | /* |
10530 | * Set the MSR load/store lists to match L0's settings. | |
10531 | */ | |
10532 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); | |
10533 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
10534 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); | |
10535 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
10536 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); | |
10537 | ||
fe3ef05c NHE |
10538 | /* |
10539 | * HOST_RSP is normally set correctly in vmx_vcpu_run() just before | |
10540 | * entry, but only if the current (host) sp changed from the value | |
10541 | * we wrote last (vmx->host_rsp). This cache is no longer relevant | |
10542 | * if we switch vmcs, and rather than hold a separate cache per vmcs, | |
10543 | * here we just force the write to happen on entry. | |
10544 | */ | |
10545 | vmx->host_rsp = 0; | |
10546 | ||
10547 | exec_control = vmx_exec_control(vmx); /* L0's desires */ | |
10548 | exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
10549 | exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
10550 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
10551 | exec_control |= vmcs12->cpu_based_vm_exec_control; | |
a7c0b07d | 10552 | |
6beb7bd5 JM |
10553 | /* |
10554 | * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if | |
10555 | * nested_get_vmcs12_pages can't fix it up, the illegal value | |
10556 | * will result in a VM entry failure. | |
10557 | */ | |
a7c0b07d | 10558 | if (exec_control & CPU_BASED_TPR_SHADOW) { |
6beb7bd5 | 10559 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull); |
a7c0b07d | 10560 | vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); |
51aa68e7 JM |
10561 | } else { |
10562 | #ifdef CONFIG_X86_64 | |
10563 | exec_control |= CPU_BASED_CR8_LOAD_EXITING | | |
10564 | CPU_BASED_CR8_STORE_EXITING; | |
10565 | #endif | |
a7c0b07d WL |
10566 | } |
10567 | ||
fe3ef05c | 10568 | /* |
3af18d9c | 10569 | * Merging of IO bitmap not currently supported. |
fe3ef05c NHE |
10570 | * Rather, exit every time. |
10571 | */ | |
fe3ef05c NHE |
10572 | exec_control &= ~CPU_BASED_USE_IO_BITMAPS; |
10573 | exec_control |= CPU_BASED_UNCOND_IO_EXITING; | |
10574 | ||
10575 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
10576 | ||
10577 | /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the | |
10578 | * bitwise-or of what L1 wants to trap for L2, and what we want to | |
10579 | * trap. Note that CR0.TS also needs updating - we do this later. | |
10580 | */ | |
10581 | update_exception_bitmap(vcpu); | |
10582 | vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; | |
10583 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
10584 | ||
8049d651 NHE |
10585 | /* L2->L1 exit controls are emulated - the hardware exit is to L0 so |
10586 | * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER | |
10587 | * bits are further modified by vmx_set_efer() below. | |
10588 | */ | |
f4124500 | 10589 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
8049d651 NHE |
10590 | |
10591 | /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are | |
10592 | * emulated by vmx_set_efer(), below. | |
10593 | */ | |
2961e876 | 10594 | vm_entry_controls_init(vmx, |
8049d651 NHE |
10595 | (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER & |
10596 | ~VM_ENTRY_IA32E_MODE) | | |
fe3ef05c NHE |
10597 | (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE)); |
10598 | ||
cf8b84f4 JM |
10599 | if (from_vmentry && |
10600 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) { | |
fe3ef05c | 10601 | vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); |
44811c02 | 10602 | vcpu->arch.pat = vmcs12->guest_ia32_pat; |
cf8b84f4 | 10603 | } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { |
fe3ef05c | 10604 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); |
cf8b84f4 | 10605 | } |
fe3ef05c NHE |
10606 | |
10607 | set_cr4_guest_host_mask(vmx); | |
10608 | ||
cf8b84f4 JM |
10609 | if (from_vmentry && |
10610 | vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) | |
36be0b9d PB |
10611 | vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); |
10612 | ||
27fc51b2 NHE |
10613 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
10614 | vmcs_write64(TSC_OFFSET, | |
ea26e4ec | 10615 | vcpu->arch.tsc_offset + vmcs12->tsc_offset); |
27fc51b2 | 10616 | else |
ea26e4ec | 10617 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
c95ba92a PF |
10618 | if (kvm_has_tsc_control) |
10619 | decache_tsc_multiplier(vmx); | |
fe3ef05c | 10620 | |
904e14fb PB |
10621 | if (cpu_has_vmx_msr_bitmap()) |
10622 | vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap)); | |
10623 | ||
fe3ef05c NHE |
10624 | if (enable_vpid) { |
10625 | /* | |
5c614b35 WL |
10626 | * There is no direct mapping between vpid02 and vpid12, the |
10627 | * vpid02 is per-vCPU for L0 and reused while the value of | |
10628 | * vpid12 is changed w/ one invvpid during nested vmentry. | |
10629 | * The vpid12 is allocated by L1 for L2, so it will not | |
10630 | * influence global bitmap(for vpid01 and vpid02 allocation) | |
10631 | * even if spawn a lot of nested vCPUs. | |
fe3ef05c | 10632 | */ |
5c614b35 WL |
10633 | if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) { |
10634 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02); | |
10635 | if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) { | |
10636 | vmx->nested.last_vpid = vmcs12->virtual_processor_id; | |
10637 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02); | |
10638 | } | |
10639 | } else { | |
10640 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
10641 | vmx_flush_tlb(vcpu); | |
10642 | } | |
10643 | ||
fe3ef05c NHE |
10644 | } |
10645 | ||
1fb883bb LP |
10646 | if (enable_pml) { |
10647 | /* | |
10648 | * Conceptually we want to copy the PML address and index from | |
10649 | * vmcs01 here, and then back to vmcs01 on nested vmexit. But, | |
10650 | * since we always flush the log on each vmexit, this happens | |
10651 | * to be equivalent to simply resetting the fields in vmcs02. | |
10652 | */ | |
10653 | ASSERT(vmx->pml_pg); | |
10654 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
10655 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
10656 | } | |
10657 | ||
155a97a3 | 10658 | if (nested_cpu_has_ept(vmcs12)) { |
ae1e2d10 PB |
10659 | if (nested_ept_init_mmu_context(vcpu)) { |
10660 | *entry_failure_code = ENTRY_FAIL_DEFAULT; | |
10661 | return 1; | |
10662 | } | |
fb6c8198 JM |
10663 | } else if (nested_cpu_has2(vmcs12, |
10664 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
10665 | vmx_flush_tlb_ept_only(vcpu); | |
155a97a3 NHE |
10666 | } |
10667 | ||
fe3ef05c | 10668 | /* |
bd7e5b08 PB |
10669 | * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those |
10670 | * bits which we consider mandatory enabled. | |
fe3ef05c NHE |
10671 | * The CR0_READ_SHADOW is what L2 should have expected to read given |
10672 | * the specifications by L1; It's not enough to take | |
10673 | * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we | |
10674 | * have more bits than L1 expected. | |
10675 | */ | |
10676 | vmx_set_cr0(vcpu, vmcs12->guest_cr0); | |
10677 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
10678 | ||
10679 | vmx_set_cr4(vcpu, vmcs12->guest_cr4); | |
10680 | vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); | |
10681 | ||
cf8b84f4 JM |
10682 | if (from_vmentry && |
10683 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) | |
5a6a9748 DM |
10684 | vcpu->arch.efer = vmcs12->guest_ia32_efer; |
10685 | else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) | |
10686 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); | |
10687 | else | |
10688 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
10689 | /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ | |
10690 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
10691 | ||
9ed38ffa | 10692 | /* Shadow page tables on either EPT or shadow page tables. */ |
7ad658b6 | 10693 | if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12), |
9ed38ffa LP |
10694 | entry_failure_code)) |
10695 | return 1; | |
7ca29de2 | 10696 | |
feaf0c7d GN |
10697 | if (!enable_ept) |
10698 | vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; | |
10699 | ||
3633cfc3 NHE |
10700 | /* |
10701 | * L1 may access the L2's PDPTR, so save them to construct vmcs12 | |
10702 | */ | |
10703 | if (enable_ept) { | |
10704 | vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); | |
10705 | vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); | |
10706 | vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); | |
10707 | vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); | |
10708 | } | |
10709 | ||
fe3ef05c NHE |
10710 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp); |
10711 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip); | |
ee146c1c | 10712 | return 0; |
fe3ef05c NHE |
10713 | } |
10714 | ||
ca0bde28 | 10715 | static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) |
cd232ad0 | 10716 | { |
cd232ad0 | 10717 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7c177938 | 10718 | |
6dfacadd | 10719 | if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && |
ca0bde28 JM |
10720 | vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) |
10721 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
26539bd0 | 10722 | |
56a20510 JM |
10723 | if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12)) |
10724 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10725 | ||
ca0bde28 JM |
10726 | if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) |
10727 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
7c177938 | 10728 | |
712b12d7 JM |
10729 | if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12)) |
10730 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10731 | ||
ca0bde28 JM |
10732 | if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) |
10733 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
f2b93280 | 10734 | |
ca0bde28 JM |
10735 | if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) |
10736 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
e9ac033e | 10737 | |
c5f983f6 BD |
10738 | if (nested_vmx_check_pml_controls(vcpu, vmcs12)) |
10739 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10740 | ||
7c177938 | 10741 | if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, |
0115f9cb | 10742 | vmx->nested.nested_vmx_procbased_ctls_low, |
b9c237bb | 10743 | vmx->nested.nested_vmx_procbased_ctls_high) || |
2e5b0bd9 JM |
10744 | (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && |
10745 | !vmx_control_verify(vmcs12->secondary_vm_exec_control, | |
10746 | vmx->nested.nested_vmx_secondary_ctls_low, | |
10747 | vmx->nested.nested_vmx_secondary_ctls_high)) || | |
7c177938 | 10748 | !vmx_control_verify(vmcs12->pin_based_vm_exec_control, |
b9c237bb WV |
10749 | vmx->nested.nested_vmx_pinbased_ctls_low, |
10750 | vmx->nested.nested_vmx_pinbased_ctls_high) || | |
7c177938 | 10751 | !vmx_control_verify(vmcs12->vm_exit_controls, |
0115f9cb | 10752 | vmx->nested.nested_vmx_exit_ctls_low, |
b9c237bb | 10753 | vmx->nested.nested_vmx_exit_ctls_high) || |
7c177938 | 10754 | !vmx_control_verify(vmcs12->vm_entry_controls, |
0115f9cb | 10755 | vmx->nested.nested_vmx_entry_ctls_low, |
b9c237bb | 10756 | vmx->nested.nested_vmx_entry_ctls_high)) |
ca0bde28 | 10757 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; |
7c177938 | 10758 | |
41ab9372 BD |
10759 | if (nested_cpu_has_vmfunc(vmcs12)) { |
10760 | if (vmcs12->vm_function_control & | |
10761 | ~vmx->nested.nested_vmx_vmfunc_controls) | |
10762 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10763 | ||
10764 | if (nested_cpu_has_eptp_switching(vmcs12)) { | |
10765 | if (!nested_cpu_has_ept(vmcs12) || | |
10766 | !page_address_valid(vcpu, vmcs12->eptp_list_address)) | |
10767 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10768 | } | |
10769 | } | |
27c42a1b | 10770 | |
c7c2c709 JM |
10771 | if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) |
10772 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10773 | ||
3899152c | 10774 | if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) || |
1dc35dac | 10775 | !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) || |
ca0bde28 JM |
10776 | !nested_cr3_valid(vcpu, vmcs12->host_cr3)) |
10777 | return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; | |
10778 | ||
10779 | return 0; | |
10780 | } | |
10781 | ||
10782 | static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
10783 | u32 *exit_qual) | |
10784 | { | |
10785 | bool ia32e; | |
10786 | ||
10787 | *exit_qual = ENTRY_FAIL_DEFAULT; | |
7c177938 | 10788 | |
3899152c | 10789 | if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) || |
ca0bde28 | 10790 | !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)) |
b428018a | 10791 | return 1; |
ca0bde28 JM |
10792 | |
10793 | if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) && | |
10794 | vmcs12->vmcs_link_pointer != -1ull) { | |
10795 | *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR; | |
b428018a | 10796 | return 1; |
7c177938 NHE |
10797 | } |
10798 | ||
384bb783 | 10799 | /* |
cb0c8cda | 10800 | * If the load IA32_EFER VM-entry control is 1, the following checks |
384bb783 JK |
10801 | * are performed on the field for the IA32_EFER MSR: |
10802 | * - Bits reserved in the IA32_EFER MSR must be 0. | |
10803 | * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of | |
10804 | * the IA-32e mode guest VM-exit control. It must also be identical | |
10805 | * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to | |
10806 | * CR0.PG) is 1. | |
10807 | */ | |
ca0bde28 JM |
10808 | if (to_vmx(vcpu)->nested.nested_run_pending && |
10809 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) { | |
384bb783 JK |
10810 | ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; |
10811 | if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) || | |
10812 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) || | |
10813 | ((vmcs12->guest_cr0 & X86_CR0_PG) && | |
ca0bde28 | 10814 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) |
b428018a | 10815 | return 1; |
384bb783 JK |
10816 | } |
10817 | ||
10818 | /* | |
10819 | * If the load IA32_EFER VM-exit control is 1, bits reserved in the | |
10820 | * IA32_EFER MSR must be 0 in the field for that register. In addition, | |
10821 | * the values of the LMA and LME bits in the field must each be that of | |
10822 | * the host address-space size VM-exit control. | |
10823 | */ | |
10824 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { | |
10825 | ia32e = (vmcs12->vm_exit_controls & | |
10826 | VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0; | |
10827 | if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) || | |
10828 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) || | |
ca0bde28 | 10829 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) |
b428018a | 10830 | return 1; |
ca0bde28 JM |
10831 | } |
10832 | ||
f1b026a3 WL |
10833 | if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) && |
10834 | (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) || | |
10835 | (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD))) | |
10836 | return 1; | |
10837 | ||
ca0bde28 JM |
10838 | return 0; |
10839 | } | |
10840 | ||
858e25c0 JM |
10841 | static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry) |
10842 | { | |
10843 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10844 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
858e25c0 JM |
10845 | u32 msr_entry_idx; |
10846 | u32 exit_qual; | |
10847 | ||
858e25c0 JM |
10848 | enter_guest_mode(vcpu); |
10849 | ||
10850 | if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) | |
10851 | vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
10852 | ||
de3a0021 | 10853 | vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02); |
858e25c0 JM |
10854 | vmx_segment_cache_clear(vmx); |
10855 | ||
10856 | if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) { | |
10857 | leave_guest_mode(vcpu); | |
1279a6b1 | 10858 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
858e25c0 JM |
10859 | nested_vmx_entry_failure(vcpu, vmcs12, |
10860 | EXIT_REASON_INVALID_STATE, exit_qual); | |
10861 | return 1; | |
10862 | } | |
10863 | ||
10864 | nested_get_vmcs12_pages(vcpu, vmcs12); | |
10865 | ||
10866 | msr_entry_idx = nested_vmx_load_msr(vcpu, | |
10867 | vmcs12->vm_entry_msr_load_addr, | |
10868 | vmcs12->vm_entry_msr_load_count); | |
10869 | if (msr_entry_idx) { | |
10870 | leave_guest_mode(vcpu); | |
1279a6b1 | 10871 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
858e25c0 JM |
10872 | nested_vmx_entry_failure(vcpu, vmcs12, |
10873 | EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx); | |
10874 | return 1; | |
10875 | } | |
10876 | ||
858e25c0 JM |
10877 | /* |
10878 | * Note no nested_vmx_succeed or nested_vmx_fail here. At this point | |
10879 | * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet | |
10880 | * returned as far as L1 is concerned. It will only return (and set | |
10881 | * the success flag) when L2 exits (see nested_vmx_vmexit()). | |
10882 | */ | |
10883 | return 0; | |
10884 | } | |
10885 | ||
ca0bde28 JM |
10886 | /* |
10887 | * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 | |
10888 | * for running an L2 nested guest. | |
10889 | */ | |
10890 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) | |
10891 | { | |
10892 | struct vmcs12 *vmcs12; | |
10893 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
b3f1dfb6 | 10894 | u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu); |
ca0bde28 JM |
10895 | u32 exit_qual; |
10896 | int ret; | |
10897 | ||
10898 | if (!nested_vmx_check_permission(vcpu)) | |
10899 | return 1; | |
10900 | ||
10901 | if (!nested_vmx_check_vmcs12(vcpu)) | |
10902 | goto out; | |
10903 | ||
10904 | vmcs12 = get_vmcs12(vcpu); | |
10905 | ||
10906 | if (enable_shadow_vmcs) | |
10907 | copy_shadow_to_vmcs12(vmx); | |
10908 | ||
10909 | /* | |
10910 | * The nested entry process starts with enforcing various prerequisites | |
10911 | * on vmcs12 as required by the Intel SDM, and act appropriately when | |
10912 | * they fail: As the SDM explains, some conditions should cause the | |
10913 | * instruction to fail, while others will cause the instruction to seem | |
10914 | * to succeed, but return an EXIT_REASON_INVALID_STATE. | |
10915 | * To speed up the normal (success) code path, we should avoid checking | |
10916 | * for misconfigurations which will anyway be caught by the processor | |
10917 | * when using the merged vmcs02. | |
10918 | */ | |
b3f1dfb6 JM |
10919 | if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) { |
10920 | nested_vmx_failValid(vcpu, | |
10921 | VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS); | |
10922 | goto out; | |
10923 | } | |
10924 | ||
ca0bde28 JM |
10925 | if (vmcs12->launch_state == launch) { |
10926 | nested_vmx_failValid(vcpu, | |
10927 | launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS | |
10928 | : VMXERR_VMRESUME_NONLAUNCHED_VMCS); | |
10929 | goto out; | |
10930 | } | |
10931 | ||
10932 | ret = check_vmentry_prereqs(vcpu, vmcs12); | |
10933 | if (ret) { | |
10934 | nested_vmx_failValid(vcpu, ret); | |
10935 | goto out; | |
10936 | } | |
10937 | ||
10938 | /* | |
10939 | * After this point, the trap flag no longer triggers a singlestep trap | |
10940 | * on the vm entry instructions; don't call kvm_skip_emulated_instruction. | |
10941 | * This is not 100% correct; for performance reasons, we delegate most | |
10942 | * of the checks on host state to the processor. If those fail, | |
10943 | * the singlestep trap is missed. | |
10944 | */ | |
10945 | skip_emulated_instruction(vcpu); | |
10946 | ||
10947 | ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual); | |
10948 | if (ret) { | |
10949 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10950 | EXIT_REASON_INVALID_STATE, exit_qual); | |
10951 | return 1; | |
384bb783 JK |
10952 | } |
10953 | ||
7c177938 NHE |
10954 | /* |
10955 | * We're finally done with prerequisite checking, and can start with | |
10956 | * the nested entry. | |
10957 | */ | |
10958 | ||
858e25c0 JM |
10959 | ret = enter_vmx_non_root_mode(vcpu, true); |
10960 | if (ret) | |
10961 | return ret; | |
ff651cb6 | 10962 | |
6dfacadd | 10963 | if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) |
5cb56059 | 10964 | return kvm_vcpu_halt(vcpu); |
6dfacadd | 10965 | |
7af40ad3 JK |
10966 | vmx->nested.nested_run_pending = 1; |
10967 | ||
cd232ad0 | 10968 | return 1; |
eb277562 KH |
10969 | |
10970 | out: | |
6affcbed | 10971 | return kvm_skip_emulated_instruction(vcpu); |
cd232ad0 NHE |
10972 | } |
10973 | ||
4704d0be NHE |
10974 | /* |
10975 | * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date | |
10976 | * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK). | |
10977 | * This function returns the new value we should put in vmcs12.guest_cr0. | |
10978 | * It's not enough to just return the vmcs02 GUEST_CR0. Rather, | |
10979 | * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now | |
10980 | * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 | |
10981 | * didn't trap the bit, because if L1 did, so would L0). | |
10982 | * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have | |
10983 | * been modified by L2, and L1 knows it. So just leave the old value of | |
10984 | * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 | |
10985 | * isn't relevant, because if L0 traps this bit it can set it to anything. | |
10986 | * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have | |
10987 | * changed these bits, and therefore they need to be updated, but L0 | |
10988 | * didn't necessarily allow them to be changed in GUEST_CR0 - and rather | |
10989 | * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. | |
10990 | */ | |
10991 | static inline unsigned long | |
10992 | vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
10993 | { | |
10994 | return | |
10995 | /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | | |
10996 | /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | | |
10997 | /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | | |
10998 | vcpu->arch.cr0_guest_owned_bits)); | |
10999 | } | |
11000 | ||
11001 | static inline unsigned long | |
11002 | vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
11003 | { | |
11004 | return | |
11005 | /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | | |
11006 | /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | | |
11007 | /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | | |
11008 | vcpu->arch.cr4_guest_owned_bits)); | |
11009 | } | |
11010 | ||
5f3d5799 JK |
11011 | static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, |
11012 | struct vmcs12 *vmcs12) | |
11013 | { | |
11014 | u32 idt_vectoring; | |
11015 | unsigned int nr; | |
11016 | ||
664f8e26 | 11017 | if (vcpu->arch.exception.injected) { |
5f3d5799 JK |
11018 | nr = vcpu->arch.exception.nr; |
11019 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
11020 | ||
11021 | if (kvm_exception_is_soft(nr)) { | |
11022 | vmcs12->vm_exit_instruction_len = | |
11023 | vcpu->arch.event_exit_inst_len; | |
11024 | idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; | |
11025 | } else | |
11026 | idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; | |
11027 | ||
11028 | if (vcpu->arch.exception.has_error_code) { | |
11029 | idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; | |
11030 | vmcs12->idt_vectoring_error_code = | |
11031 | vcpu->arch.exception.error_code; | |
11032 | } | |
11033 | ||
11034 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
cd2633c5 | 11035 | } else if (vcpu->arch.nmi_injected) { |
5f3d5799 JK |
11036 | vmcs12->idt_vectoring_info_field = |
11037 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; | |
11038 | } else if (vcpu->arch.interrupt.pending) { | |
11039 | nr = vcpu->arch.interrupt.nr; | |
11040 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
11041 | ||
11042 | if (vcpu->arch.interrupt.soft) { | |
11043 | idt_vectoring |= INTR_TYPE_SOFT_INTR; | |
11044 | vmcs12->vm_entry_instruction_len = | |
11045 | vcpu->arch.event_exit_inst_len; | |
11046 | } else | |
11047 | idt_vectoring |= INTR_TYPE_EXT_INTR; | |
11048 | ||
11049 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
11050 | } | |
11051 | } | |
11052 | ||
b6b8a145 JK |
11053 | static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) |
11054 | { | |
11055 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
bfcf83b1 | 11056 | unsigned long exit_qual; |
917dc606 LA |
11057 | bool block_nested_events = |
11058 | vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu); | |
acc9ab60 | 11059 | |
bfcf83b1 WL |
11060 | if (vcpu->arch.exception.pending && |
11061 | nested_vmx_check_exception(vcpu, &exit_qual)) { | |
917dc606 | 11062 | if (block_nested_events) |
bfcf83b1 WL |
11063 | return -EBUSY; |
11064 | nested_vmx_inject_exception_vmexit(vcpu, exit_qual); | |
11065 | vcpu->arch.exception.pending = false; | |
11066 | return 0; | |
11067 | } | |
11068 | ||
f4124500 JK |
11069 | if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && |
11070 | vmx->nested.preemption_timer_expired) { | |
917dc606 | 11071 | if (block_nested_events) |
f4124500 JK |
11072 | return -EBUSY; |
11073 | nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); | |
11074 | return 0; | |
11075 | } | |
11076 | ||
b6b8a145 | 11077 | if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) { |
917dc606 | 11078 | if (block_nested_events) |
b6b8a145 JK |
11079 | return -EBUSY; |
11080 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
11081 | NMI_VECTOR | INTR_TYPE_NMI_INTR | | |
11082 | INTR_INFO_VALID_MASK, 0); | |
11083 | /* | |
11084 | * The NMI-triggered VM exit counts as injection: | |
11085 | * clear this one and block further NMIs. | |
11086 | */ | |
11087 | vcpu->arch.nmi_pending = 0; | |
11088 | vmx_set_nmi_mask(vcpu, true); | |
11089 | return 0; | |
11090 | } | |
11091 | ||
11092 | if ((kvm_cpu_has_interrupt(vcpu) || external_intr) && | |
11093 | nested_exit_on_intr(vcpu)) { | |
917dc606 | 11094 | if (block_nested_events) |
b6b8a145 JK |
11095 | return -EBUSY; |
11096 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); | |
705699a1 | 11097 | return 0; |
b6b8a145 JK |
11098 | } |
11099 | ||
6342c50a DH |
11100 | vmx_complete_nested_posted_interrupt(vcpu); |
11101 | return 0; | |
b6b8a145 JK |
11102 | } |
11103 | ||
f4124500 JK |
11104 | static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) |
11105 | { | |
11106 | ktime_t remaining = | |
11107 | hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); | |
11108 | u64 value; | |
11109 | ||
11110 | if (ktime_to_ns(remaining) <= 0) | |
11111 | return 0; | |
11112 | ||
11113 | value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; | |
11114 | do_div(value, 1000000); | |
11115 | return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
11116 | } | |
11117 | ||
4704d0be | 11118 | /* |
cf8b84f4 JM |
11119 | * Update the guest state fields of vmcs12 to reflect changes that |
11120 | * occurred while L2 was running. (The "IA-32e mode guest" bit of the | |
11121 | * VM-entry controls is also updated, since this is really a guest | |
11122 | * state bit.) | |
4704d0be | 11123 | */ |
cf8b84f4 | 11124 | static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) |
4704d0be | 11125 | { |
4704d0be NHE |
11126 | vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); |
11127 | vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); | |
11128 | ||
4704d0be NHE |
11129 | vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); |
11130 | vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP); | |
11131 | vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); | |
11132 | ||
11133 | vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); | |
11134 | vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); | |
11135 | vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); | |
11136 | vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); | |
11137 | vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); | |
11138 | vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); | |
11139 | vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); | |
11140 | vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); | |
11141 | vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); | |
11142 | vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); | |
11143 | vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
11144 | vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); | |
11145 | vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); | |
11146 | vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); | |
11147 | vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); | |
11148 | vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); | |
11149 | vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
11150 | vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
11151 | vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); | |
11152 | vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); | |
11153 | vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); | |
11154 | vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); | |
11155 | vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); | |
11156 | vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); | |
11157 | vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); | |
11158 | vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); | |
11159 | vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); | |
11160 | vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); | |
11161 | vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); | |
11162 | vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); | |
11163 | vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); | |
11164 | vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); | |
11165 | vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); | |
11166 | vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); | |
11167 | vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); | |
11168 | vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); | |
11169 | ||
4704d0be NHE |
11170 | vmcs12->guest_interruptibility_info = |
11171 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
11172 | vmcs12->guest_pending_dbg_exceptions = | |
11173 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); | |
3edf1e69 JK |
11174 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
11175 | vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; | |
11176 | else | |
11177 | vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; | |
4704d0be | 11178 | |
f4124500 JK |
11179 | if (nested_cpu_has_preemption_timer(vmcs12)) { |
11180 | if (vmcs12->vm_exit_controls & | |
11181 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER) | |
11182 | vmcs12->vmx_preemption_timer_value = | |
11183 | vmx_get_preemption_timer_value(vcpu); | |
11184 | hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); | |
11185 | } | |
7854cbca | 11186 | |
3633cfc3 NHE |
11187 | /* |
11188 | * In some cases (usually, nested EPT), L2 is allowed to change its | |
11189 | * own CR3 without exiting. If it has changed it, we must keep it. | |
11190 | * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined | |
11191 | * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. | |
11192 | * | |
11193 | * Additionally, restore L2's PDPTR to vmcs12. | |
11194 | */ | |
11195 | if (enable_ept) { | |
f3531054 | 11196 | vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3); |
3633cfc3 NHE |
11197 | vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); |
11198 | vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); | |
11199 | vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); | |
11200 | vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); | |
11201 | } | |
11202 | ||
d281e13b | 11203 | vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS); |
119a9c01 | 11204 | |
608406e2 WV |
11205 | if (nested_cpu_has_vid(vmcs12)) |
11206 | vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS); | |
11207 | ||
c18911a2 JK |
11208 | vmcs12->vm_entry_controls = |
11209 | (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | | |
2961e876 | 11210 | (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); |
c18911a2 | 11211 | |
2996fca0 JK |
11212 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) { |
11213 | kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); | |
11214 | vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
11215 | } | |
11216 | ||
4704d0be NHE |
11217 | /* TODO: These cannot have changed unless we have MSR bitmaps and |
11218 | * the relevant bit asks not to trap the change */ | |
b8c07d55 | 11219 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) |
4704d0be | 11220 | vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT); |
10ba54a5 JK |
11221 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) |
11222 | vmcs12->guest_ia32_efer = vcpu->arch.efer; | |
4704d0be NHE |
11223 | vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS); |
11224 | vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP); | |
11225 | vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP); | |
a87036ad | 11226 | if (kvm_mpx_supported()) |
36be0b9d | 11227 | vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); |
cf8b84f4 JM |
11228 | } |
11229 | ||
11230 | /* | |
11231 | * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits | |
11232 | * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), | |
11233 | * and this function updates it to reflect the changes to the guest state while | |
11234 | * L2 was running (and perhaps made some exits which were handled directly by L0 | |
11235 | * without going back to L1), and to reflect the exit reason. | |
11236 | * Note that we do not have to copy here all VMCS fields, just those that | |
11237 | * could have changed by the L2 guest or the exit - i.e., the guest-state and | |
11238 | * exit-information fields only. Other fields are modified by L1 with VMWRITE, | |
11239 | * which already writes to vmcs12 directly. | |
11240 | */ | |
11241 | static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
11242 | u32 exit_reason, u32 exit_intr_info, | |
11243 | unsigned long exit_qualification) | |
11244 | { | |
11245 | /* update guest state fields: */ | |
11246 | sync_vmcs12(vcpu, vmcs12); | |
4704d0be NHE |
11247 | |
11248 | /* update exit information fields: */ | |
11249 | ||
533558bc JK |
11250 | vmcs12->vm_exit_reason = exit_reason; |
11251 | vmcs12->exit_qualification = exit_qualification; | |
533558bc | 11252 | vmcs12->vm_exit_intr_info = exit_intr_info; |
7313c698 | 11253 | |
5f3d5799 | 11254 | vmcs12->idt_vectoring_info_field = 0; |
4704d0be NHE |
11255 | vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
11256 | vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
11257 | ||
5f3d5799 | 11258 | if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { |
7cdc2d62 JM |
11259 | vmcs12->launch_state = 1; |
11260 | ||
5f3d5799 JK |
11261 | /* vm_entry_intr_info_field is cleared on exit. Emulate this |
11262 | * instead of reading the real value. */ | |
4704d0be | 11263 | vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; |
5f3d5799 JK |
11264 | |
11265 | /* | |
11266 | * Transfer the event that L0 or L1 may wanted to inject into | |
11267 | * L2 to IDT_VECTORING_INFO_FIELD. | |
11268 | */ | |
11269 | vmcs12_save_pending_event(vcpu, vmcs12); | |
11270 | } | |
11271 | ||
11272 | /* | |
11273 | * Drop what we picked up for L2 via vmx_complete_interrupts. It is | |
11274 | * preserved above and would only end up incorrectly in L1. | |
11275 | */ | |
11276 | vcpu->arch.nmi_injected = false; | |
11277 | kvm_clear_exception_queue(vcpu); | |
11278 | kvm_clear_interrupt_queue(vcpu); | |
4704d0be NHE |
11279 | } |
11280 | ||
5af41573 WL |
11281 | static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu, |
11282 | struct vmcs12 *vmcs12) | |
11283 | { | |
11284 | u32 entry_failure_code; | |
11285 | ||
11286 | nested_ept_uninit_mmu_context(vcpu); | |
11287 | ||
11288 | /* | |
11289 | * Only PDPTE load can fail as the value of cr3 was checked on entry and | |
11290 | * couldn't have changed. | |
11291 | */ | |
11292 | if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code)) | |
11293 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL); | |
11294 | ||
11295 | if (!enable_ept) | |
11296 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
11297 | } | |
11298 | ||
4704d0be NHE |
11299 | /* |
11300 | * A part of what we need to when the nested L2 guest exits and we want to | |
11301 | * run its L1 parent, is to reset L1's guest state to the host state specified | |
11302 | * in vmcs12. | |
11303 | * This function is to be called not only on normal nested exit, but also on | |
11304 | * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry | |
11305 | * Failures During or After Loading Guest State"). | |
11306 | * This function should be called when the active VMCS is L1's (vmcs01). | |
11307 | */ | |
733568f9 JK |
11308 | static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, |
11309 | struct vmcs12 *vmcs12) | |
4704d0be | 11310 | { |
21feb4eb ACL |
11311 | struct kvm_segment seg; |
11312 | ||
4704d0be NHE |
11313 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) |
11314 | vcpu->arch.efer = vmcs12->host_ia32_efer; | |
d1fa0352 | 11315 | else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) |
4704d0be NHE |
11316 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
11317 | else | |
11318 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
11319 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
11320 | ||
11321 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp); | |
11322 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip); | |
1adfa76a | 11323 | vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); |
4704d0be NHE |
11324 | /* |
11325 | * Note that calling vmx_set_cr0 is important, even if cr0 hasn't | |
bd7e5b08 PB |
11326 | * actually changed, because vmx_set_cr0 refers to efer set above. |
11327 | * | |
11328 | * CR0_GUEST_HOST_MASK is already set in the original vmcs01 | |
11329 | * (KVM doesn't change it); | |
4704d0be | 11330 | */ |
bd7e5b08 | 11331 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
9e3e4dbf | 11332 | vmx_set_cr0(vcpu, vmcs12->host_cr0); |
4704d0be | 11333 | |
bd7e5b08 | 11334 | /* Same as above - no reason to call set_cr4_guest_host_mask(). */ |
4704d0be | 11335 | vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); |
8eb3f87d | 11336 | vmx_set_cr4(vcpu, vmcs12->host_cr4); |
4704d0be | 11337 | |
5af41573 | 11338 | load_vmcs12_mmu_host_state(vcpu, vmcs12); |
feaf0c7d | 11339 | |
4704d0be NHE |
11340 | if (enable_vpid) { |
11341 | /* | |
11342 | * Trivially support vpid by letting L2s share their parent | |
11343 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
11344 | * each L2 its own vpid and exposing the vpid feature to L1. | |
11345 | */ | |
11346 | vmx_flush_tlb(vcpu); | |
11347 | } | |
06a5524f WV |
11348 | /* Restore posted intr vector. */ |
11349 | if (nested_cpu_has_posted_intr(vmcs12)) | |
11350 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); | |
4704d0be NHE |
11351 | |
11352 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); | |
11353 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); | |
11354 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); | |
11355 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); | |
11356 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); | |
21f2d551 LP |
11357 | vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF); |
11358 | vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF); | |
4704d0be | 11359 | |
36be0b9d PB |
11360 | /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ |
11361 | if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) | |
11362 | vmcs_write64(GUEST_BNDCFGS, 0); | |
11363 | ||
44811c02 | 11364 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { |
4704d0be | 11365 | vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); |
44811c02 JK |
11366 | vcpu->arch.pat = vmcs12->host_ia32_pat; |
11367 | } | |
4704d0be NHE |
11368 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
11369 | vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, | |
11370 | vmcs12->host_ia32_perf_global_ctrl); | |
503cd0c5 | 11371 | |
21feb4eb ACL |
11372 | /* Set L1 segment info according to Intel SDM |
11373 | 27.5.2 Loading Host Segment and Descriptor-Table Registers */ | |
11374 | seg = (struct kvm_segment) { | |
11375 | .base = 0, | |
11376 | .limit = 0xFFFFFFFF, | |
11377 | .selector = vmcs12->host_cs_selector, | |
11378 | .type = 11, | |
11379 | .present = 1, | |
11380 | .s = 1, | |
11381 | .g = 1 | |
11382 | }; | |
11383 | if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) | |
11384 | seg.l = 1; | |
11385 | else | |
11386 | seg.db = 1; | |
11387 | vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); | |
11388 | seg = (struct kvm_segment) { | |
11389 | .base = 0, | |
11390 | .limit = 0xFFFFFFFF, | |
11391 | .type = 3, | |
11392 | .present = 1, | |
11393 | .s = 1, | |
11394 | .db = 1, | |
11395 | .g = 1 | |
11396 | }; | |
11397 | seg.selector = vmcs12->host_ds_selector; | |
11398 | vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); | |
11399 | seg.selector = vmcs12->host_es_selector; | |
11400 | vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); | |
11401 | seg.selector = vmcs12->host_ss_selector; | |
11402 | vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); | |
11403 | seg.selector = vmcs12->host_fs_selector; | |
11404 | seg.base = vmcs12->host_fs_base; | |
11405 | vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); | |
11406 | seg.selector = vmcs12->host_gs_selector; | |
11407 | seg.base = vmcs12->host_gs_base; | |
11408 | vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); | |
11409 | seg = (struct kvm_segment) { | |
205befd9 | 11410 | .base = vmcs12->host_tr_base, |
21feb4eb ACL |
11411 | .limit = 0x67, |
11412 | .selector = vmcs12->host_tr_selector, | |
11413 | .type = 11, | |
11414 | .present = 1 | |
11415 | }; | |
11416 | vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); | |
11417 | ||
503cd0c5 JK |
11418 | kvm_set_dr(vcpu, 7, 0x400); |
11419 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
ff651cb6 | 11420 | |
3af18d9c | 11421 | if (cpu_has_vmx_msr_bitmap()) |
904e14fb | 11422 | vmx_update_msr_bitmap(vcpu); |
3af18d9c | 11423 | |
ff651cb6 WV |
11424 | if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr, |
11425 | vmcs12->vm_exit_msr_load_count)) | |
11426 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); | |
4704d0be NHE |
11427 | } |
11428 | ||
11429 | /* | |
11430 | * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 | |
11431 | * and modify vmcs12 to make it see what it would expect to see there if | |
11432 | * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) | |
11433 | */ | |
533558bc JK |
11434 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
11435 | u32 exit_intr_info, | |
11436 | unsigned long exit_qualification) | |
4704d0be NHE |
11437 | { |
11438 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4704d0be NHE |
11439 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
11440 | ||
5f3d5799 JK |
11441 | /* trying to cancel vmlaunch/vmresume is a bug */ |
11442 | WARN_ON_ONCE(vmx->nested.nested_run_pending); | |
11443 | ||
4f350c6d JM |
11444 | /* |
11445 | * The only expected VM-instruction error is "VM entry with | |
11446 | * invalid control field(s)." Anything else indicates a | |
11447 | * problem with L0. | |
11448 | */ | |
11449 | WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) != | |
11450 | VMXERR_ENTRY_INVALID_CONTROL_FIELD)); | |
11451 | ||
4704d0be | 11452 | leave_guest_mode(vcpu); |
4704d0be | 11453 | |
4f350c6d | 11454 | if (likely(!vmx->fail)) { |
72e9cbdb LP |
11455 | if (exit_reason == -1) |
11456 | sync_vmcs12(vcpu, vmcs12); | |
11457 | else | |
11458 | prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info, | |
11459 | exit_qualification); | |
ff651cb6 | 11460 | |
4f350c6d JM |
11461 | if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr, |
11462 | vmcs12->vm_exit_msr_store_count)) | |
11463 | nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL); | |
11464 | } | |
cf3215d9 | 11465 | |
1279a6b1 | 11466 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
8391ce44 PB |
11467 | vm_entry_controls_reset_shadow(vmx); |
11468 | vm_exit_controls_reset_shadow(vmx); | |
36c3cc42 JK |
11469 | vmx_segment_cache_clear(vmx); |
11470 | ||
9314006d | 11471 | /* Update any VMCS fields that might have changed while L2 ran */ |
83bafef1 JM |
11472 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr); |
11473 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
ea26e4ec | 11474 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
9314006d PB |
11475 | if (vmx->hv_deadline_tsc == -1) |
11476 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11477 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
11478 | else | |
11479 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11480 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c95ba92a PF |
11481 | if (kvm_has_tsc_control) |
11482 | decache_tsc_multiplier(vmx); | |
4704d0be | 11483 | |
dccbfcf5 RK |
11484 | if (vmx->nested.change_vmcs01_virtual_x2apic_mode) { |
11485 | vmx->nested.change_vmcs01_virtual_x2apic_mode = false; | |
11486 | vmx_set_virtual_x2apic_mode(vcpu, | |
11487 | vcpu->arch.apic_base & X2APIC_ENABLE); | |
fb6c8198 JM |
11488 | } else if (!nested_cpu_has_ept(vmcs12) && |
11489 | nested_cpu_has2(vmcs12, | |
11490 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
11491 | vmx_flush_tlb_ept_only(vcpu); | |
dccbfcf5 | 11492 | } |
4704d0be NHE |
11493 | |
11494 | /* This is needed for same reason as it was needed in prepare_vmcs02 */ | |
11495 | vmx->host_rsp = 0; | |
11496 | ||
11497 | /* Unpin physical memory we referred to in vmcs02 */ | |
11498 | if (vmx->nested.apic_access_page) { | |
53a70daf | 11499 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
48d89b92 | 11500 | vmx->nested.apic_access_page = NULL; |
4704d0be | 11501 | } |
a7c0b07d | 11502 | if (vmx->nested.virtual_apic_page) { |
53a70daf | 11503 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
48d89b92 | 11504 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 11505 | } |
705699a1 WV |
11506 | if (vmx->nested.pi_desc_page) { |
11507 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 11508 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
705699a1 WV |
11509 | vmx->nested.pi_desc_page = NULL; |
11510 | vmx->nested.pi_desc = NULL; | |
11511 | } | |
4704d0be | 11512 | |
38b99173 TC |
11513 | /* |
11514 | * We are now running in L2, mmu_notifier will force to reload the | |
11515 | * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1. | |
11516 | */ | |
c83b6d15 | 11517 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
38b99173 | 11518 | |
72e9cbdb | 11519 | if (enable_shadow_vmcs && exit_reason != -1) |
012f83cb | 11520 | vmx->nested.sync_shadow_vmcs = true; |
b6b8a145 JK |
11521 | |
11522 | /* in case we halted in L2 */ | |
11523 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4f350c6d JM |
11524 | |
11525 | if (likely(!vmx->fail)) { | |
11526 | /* | |
11527 | * TODO: SDM says that with acknowledge interrupt on | |
11528 | * exit, bit 31 of the VM-exit interrupt information | |
11529 | * (valid interrupt) is always set to 1 on | |
11530 | * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't | |
11531 | * need kvm_cpu_has_interrupt(). See the commit | |
11532 | * message for details. | |
11533 | */ | |
11534 | if (nested_exit_intr_ack_set(vcpu) && | |
11535 | exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT && | |
11536 | kvm_cpu_has_interrupt(vcpu)) { | |
11537 | int irq = kvm_cpu_get_interrupt(vcpu); | |
11538 | WARN_ON(irq < 0); | |
11539 | vmcs12->vm_exit_intr_info = irq | | |
11540 | INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; | |
11541 | } | |
11542 | ||
72e9cbdb LP |
11543 | if (exit_reason != -1) |
11544 | trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, | |
11545 | vmcs12->exit_qualification, | |
11546 | vmcs12->idt_vectoring_info_field, | |
11547 | vmcs12->vm_exit_intr_info, | |
11548 | vmcs12->vm_exit_intr_error_code, | |
11549 | KVM_ISA_VMX); | |
4f350c6d JM |
11550 | |
11551 | load_vmcs12_host_state(vcpu, vmcs12); | |
11552 | ||
11553 | return; | |
11554 | } | |
11555 | ||
11556 | /* | |
11557 | * After an early L2 VM-entry failure, we're now back | |
11558 | * in L1 which thinks it just finished a VMLAUNCH or | |
11559 | * VMRESUME instruction, so we need to set the failure | |
11560 | * flag and the VM-instruction error field of the VMCS | |
11561 | * accordingly. | |
11562 | */ | |
11563 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
5af41573 WL |
11564 | |
11565 | load_vmcs12_mmu_host_state(vcpu, vmcs12); | |
11566 | ||
4f350c6d JM |
11567 | /* |
11568 | * The emulated instruction was already skipped in | |
11569 | * nested_vmx_run, but the updated RIP was never | |
11570 | * written back to the vmcs01. | |
11571 | */ | |
11572 | skip_emulated_instruction(vcpu); | |
11573 | vmx->fail = 0; | |
4704d0be NHE |
11574 | } |
11575 | ||
42124925 JK |
11576 | /* |
11577 | * Forcibly leave nested mode in order to be able to reset the VCPU later on. | |
11578 | */ | |
11579 | static void vmx_leave_nested(struct kvm_vcpu *vcpu) | |
11580 | { | |
2f707d97 WL |
11581 | if (is_guest_mode(vcpu)) { |
11582 | to_vmx(vcpu)->nested.nested_run_pending = 0; | |
533558bc | 11583 | nested_vmx_vmexit(vcpu, -1, 0, 0); |
2f707d97 | 11584 | } |
42124925 JK |
11585 | free_nested(to_vmx(vcpu)); |
11586 | } | |
11587 | ||
7c177938 NHE |
11588 | /* |
11589 | * L1's failure to enter L2 is a subset of a normal exit, as explained in | |
11590 | * 23.7 "VM-entry failures during or after loading guest state" (this also | |
11591 | * lists the acceptable exit-reason and exit-qualification parameters). | |
11592 | * It should only be called before L2 actually succeeded to run, and when | |
11593 | * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss). | |
11594 | */ | |
11595 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, | |
11596 | struct vmcs12 *vmcs12, | |
11597 | u32 reason, unsigned long qualification) | |
11598 | { | |
11599 | load_vmcs12_host_state(vcpu, vmcs12); | |
11600 | vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY; | |
11601 | vmcs12->exit_qualification = qualification; | |
11602 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
11603 | if (enable_shadow_vmcs) |
11604 | to_vmx(vcpu)->nested.sync_shadow_vmcs = true; | |
7c177938 NHE |
11605 | } |
11606 | ||
8a76d7f2 JR |
11607 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
11608 | struct x86_instruction_info *info, | |
11609 | enum x86_intercept_stage stage) | |
11610 | { | |
11611 | return X86EMUL_CONTINUE; | |
11612 | } | |
11613 | ||
64672c95 YJ |
11614 | #ifdef CONFIG_X86_64 |
11615 | /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ | |
11616 | static inline int u64_shl_div_u64(u64 a, unsigned int shift, | |
11617 | u64 divisor, u64 *result) | |
11618 | { | |
11619 | u64 low = a << shift, high = a >> (64 - shift); | |
11620 | ||
11621 | /* To avoid the overflow on divq */ | |
11622 | if (high >= divisor) | |
11623 | return 1; | |
11624 | ||
11625 | /* Low hold the result, high hold rem which is discarded */ | |
11626 | asm("divq %2\n\t" : "=a" (low), "=d" (high) : | |
11627 | "rm" (divisor), "0" (low), "1" (high)); | |
11628 | *result = low; | |
11629 | ||
11630 | return 0; | |
11631 | } | |
11632 | ||
11633 | static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc) | |
11634 | { | |
11635 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9175d2e9 PB |
11636 | u64 tscl = rdtsc(); |
11637 | u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); | |
11638 | u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; | |
64672c95 YJ |
11639 | |
11640 | /* Convert to host delta tsc if tsc scaling is enabled */ | |
11641 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && | |
11642 | u64_shl_div_u64(delta_tsc, | |
11643 | kvm_tsc_scaling_ratio_frac_bits, | |
11644 | vcpu->arch.tsc_scaling_ratio, | |
11645 | &delta_tsc)) | |
11646 | return -ERANGE; | |
11647 | ||
11648 | /* | |
11649 | * If the delta tsc can't fit in the 32 bit after the multi shift, | |
11650 | * we can't use the preemption timer. | |
11651 | * It's possible that it fits on later vmentries, but checking | |
11652 | * on every vmentry is costly so we just use an hrtimer. | |
11653 | */ | |
11654 | if (delta_tsc >> (cpu_preemption_timer_multi + 32)) | |
11655 | return -ERANGE; | |
11656 | ||
11657 | vmx->hv_deadline_tsc = tscl + delta_tsc; | |
11658 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11659 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c8533544 WL |
11660 | |
11661 | return delta_tsc == 0; | |
64672c95 YJ |
11662 | } |
11663 | ||
11664 | static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) | |
11665 | { | |
11666 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
11667 | vmx->hv_deadline_tsc = -1; | |
11668 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11669 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
11670 | } | |
11671 | #endif | |
11672 | ||
48d89b92 | 11673 | static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) |
ae97a3b8 | 11674 | { |
b4a2d31d RK |
11675 | if (ple_gap) |
11676 | shrink_ple_window(vcpu); | |
ae97a3b8 RK |
11677 | } |
11678 | ||
843e4330 KH |
11679 | static void vmx_slot_enable_log_dirty(struct kvm *kvm, |
11680 | struct kvm_memory_slot *slot) | |
11681 | { | |
11682 | kvm_mmu_slot_leaf_clear_dirty(kvm, slot); | |
11683 | kvm_mmu_slot_largepage_remove_write_access(kvm, slot); | |
11684 | } | |
11685 | ||
11686 | static void vmx_slot_disable_log_dirty(struct kvm *kvm, | |
11687 | struct kvm_memory_slot *slot) | |
11688 | { | |
11689 | kvm_mmu_slot_set_dirty(kvm, slot); | |
11690 | } | |
11691 | ||
11692 | static void vmx_flush_log_dirty(struct kvm *kvm) | |
11693 | { | |
11694 | kvm_flush_pml_buffers(kvm); | |
11695 | } | |
11696 | ||
c5f983f6 BD |
11697 | static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) |
11698 | { | |
11699 | struct vmcs12 *vmcs12; | |
11700 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
11701 | gpa_t gpa; | |
11702 | struct page *page = NULL; | |
11703 | u64 *pml_address; | |
11704 | ||
11705 | if (is_guest_mode(vcpu)) { | |
11706 | WARN_ON_ONCE(vmx->nested.pml_full); | |
11707 | ||
11708 | /* | |
11709 | * Check if PML is enabled for the nested guest. | |
11710 | * Whether eptp bit 6 is set is already checked | |
11711 | * as part of A/D emulation. | |
11712 | */ | |
11713 | vmcs12 = get_vmcs12(vcpu); | |
11714 | if (!nested_cpu_has_pml(vmcs12)) | |
11715 | return 0; | |
11716 | ||
4769886b | 11717 | if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { |
c5f983f6 BD |
11718 | vmx->nested.pml_full = true; |
11719 | return 1; | |
11720 | } | |
11721 | ||
11722 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; | |
11723 | ||
5e2f30b7 DH |
11724 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address); |
11725 | if (is_error_page(page)) | |
c5f983f6 BD |
11726 | return 0; |
11727 | ||
11728 | pml_address = kmap(page); | |
11729 | pml_address[vmcs12->guest_pml_index--] = gpa; | |
11730 | kunmap(page); | |
53a70daf | 11731 | kvm_release_page_clean(page); |
c5f983f6 BD |
11732 | } |
11733 | ||
11734 | return 0; | |
11735 | } | |
11736 | ||
843e4330 KH |
11737 | static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, |
11738 | struct kvm_memory_slot *memslot, | |
11739 | gfn_t offset, unsigned long mask) | |
11740 | { | |
11741 | kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); | |
11742 | } | |
11743 | ||
cd39e117 PB |
11744 | static void __pi_post_block(struct kvm_vcpu *vcpu) |
11745 | { | |
11746 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
11747 | struct pi_desc old, new; | |
11748 | unsigned int dest; | |
cd39e117 PB |
11749 | |
11750 | do { | |
11751 | old.control = new.control = pi_desc->control; | |
8b306e2f PB |
11752 | WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, |
11753 | "Wakeup handler not enabled while the VCPU is blocked\n"); | |
cd39e117 PB |
11754 | |
11755 | dest = cpu_physical_id(vcpu->cpu); | |
11756 | ||
11757 | if (x2apic_enabled()) | |
11758 | new.ndst = dest; | |
11759 | else | |
11760 | new.ndst = (dest << 8) & 0xFF00; | |
11761 | ||
cd39e117 PB |
11762 | /* set 'NV' to 'notification vector' */ |
11763 | new.nv = POSTED_INTR_VECTOR; | |
c0a1666b PB |
11764 | } while (cmpxchg64(&pi_desc->control, old.control, |
11765 | new.control) != old.control); | |
cd39e117 | 11766 | |
8b306e2f PB |
11767 | if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { |
11768 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
cd39e117 | 11769 | list_del(&vcpu->blocked_vcpu_list); |
8b306e2f | 11770 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); |
cd39e117 PB |
11771 | vcpu->pre_pcpu = -1; |
11772 | } | |
11773 | } | |
11774 | ||
bf9f6ac8 FW |
11775 | /* |
11776 | * This routine does the following things for vCPU which is going | |
11777 | * to be blocked if VT-d PI is enabled. | |
11778 | * - Store the vCPU to the wakeup list, so when interrupts happen | |
11779 | * we can find the right vCPU to wake up. | |
11780 | * - Change the Posted-interrupt descriptor as below: | |
11781 | * 'NDST' <-- vcpu->pre_pcpu | |
11782 | * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR | |
11783 | * - If 'ON' is set during this process, which means at least one | |
11784 | * interrupt is posted for this vCPU, we cannot block it, in | |
11785 | * this case, return 1, otherwise, return 0. | |
11786 | * | |
11787 | */ | |
bc22512b | 11788 | static int pi_pre_block(struct kvm_vcpu *vcpu) |
bf9f6ac8 | 11789 | { |
bf9f6ac8 FW |
11790 | unsigned int dest; |
11791 | struct pi_desc old, new; | |
11792 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
11793 | ||
11794 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
11795 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
11796 | !kvm_vcpu_apicv_active(vcpu)) | |
bf9f6ac8 FW |
11797 | return 0; |
11798 | ||
8b306e2f PB |
11799 | WARN_ON(irqs_disabled()); |
11800 | local_irq_disable(); | |
11801 | if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { | |
11802 | vcpu->pre_pcpu = vcpu->cpu; | |
11803 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
11804 | list_add_tail(&vcpu->blocked_vcpu_list, | |
11805 | &per_cpu(blocked_vcpu_on_cpu, | |
11806 | vcpu->pre_pcpu)); | |
11807 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
11808 | } | |
bf9f6ac8 FW |
11809 | |
11810 | do { | |
11811 | old.control = new.control = pi_desc->control; | |
11812 | ||
bf9f6ac8 FW |
11813 | WARN((pi_desc->sn == 1), |
11814 | "Warning: SN field of posted-interrupts " | |
11815 | "is set before blocking\n"); | |
11816 | ||
11817 | /* | |
11818 | * Since vCPU can be preempted during this process, | |
11819 | * vcpu->cpu could be different with pre_pcpu, we | |
11820 | * need to set pre_pcpu as the destination of wakeup | |
11821 | * notification event, then we can find the right vCPU | |
11822 | * to wakeup in wakeup handler if interrupts happen | |
11823 | * when the vCPU is in blocked state. | |
11824 | */ | |
11825 | dest = cpu_physical_id(vcpu->pre_pcpu); | |
11826 | ||
11827 | if (x2apic_enabled()) | |
11828 | new.ndst = dest; | |
11829 | else | |
11830 | new.ndst = (dest << 8) & 0xFF00; | |
11831 | ||
11832 | /* set 'NV' to 'wakeup vector' */ | |
11833 | new.nv = POSTED_INTR_WAKEUP_VECTOR; | |
c0a1666b PB |
11834 | } while (cmpxchg64(&pi_desc->control, old.control, |
11835 | new.control) != old.control); | |
bf9f6ac8 | 11836 | |
8b306e2f PB |
11837 | /* We should not block the vCPU if an interrupt is posted for it. */ |
11838 | if (pi_test_on(pi_desc) == 1) | |
11839 | __pi_post_block(vcpu); | |
11840 | ||
11841 | local_irq_enable(); | |
11842 | return (vcpu->pre_pcpu == -1); | |
bf9f6ac8 FW |
11843 | } |
11844 | ||
bc22512b YJ |
11845 | static int vmx_pre_block(struct kvm_vcpu *vcpu) |
11846 | { | |
11847 | if (pi_pre_block(vcpu)) | |
11848 | return 1; | |
11849 | ||
64672c95 YJ |
11850 | if (kvm_lapic_hv_timer_in_use(vcpu)) |
11851 | kvm_lapic_switch_to_sw_timer(vcpu); | |
11852 | ||
bc22512b YJ |
11853 | return 0; |
11854 | } | |
11855 | ||
11856 | static void pi_post_block(struct kvm_vcpu *vcpu) | |
bf9f6ac8 | 11857 | { |
8b306e2f | 11858 | if (vcpu->pre_pcpu == -1) |
bf9f6ac8 FW |
11859 | return; |
11860 | ||
8b306e2f PB |
11861 | WARN_ON(irqs_disabled()); |
11862 | local_irq_disable(); | |
cd39e117 | 11863 | __pi_post_block(vcpu); |
8b306e2f | 11864 | local_irq_enable(); |
bf9f6ac8 FW |
11865 | } |
11866 | ||
bc22512b YJ |
11867 | static void vmx_post_block(struct kvm_vcpu *vcpu) |
11868 | { | |
64672c95 YJ |
11869 | if (kvm_x86_ops->set_hv_timer) |
11870 | kvm_lapic_switch_to_hv_timer(vcpu); | |
11871 | ||
bc22512b YJ |
11872 | pi_post_block(vcpu); |
11873 | } | |
11874 | ||
efc64404 FW |
11875 | /* |
11876 | * vmx_update_pi_irte - set IRTE for Posted-Interrupts | |
11877 | * | |
11878 | * @kvm: kvm | |
11879 | * @host_irq: host irq of the interrupt | |
11880 | * @guest_irq: gsi of the interrupt | |
11881 | * @set: set or unset PI | |
11882 | * returns 0 on success, < 0 on failure | |
11883 | */ | |
11884 | static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
11885 | uint32_t guest_irq, bool set) | |
11886 | { | |
11887 | struct kvm_kernel_irq_routing_entry *e; | |
11888 | struct kvm_irq_routing_table *irq_rt; | |
11889 | struct kvm_lapic_irq irq; | |
11890 | struct kvm_vcpu *vcpu; | |
11891 | struct vcpu_data vcpu_info; | |
3a8b0677 | 11892 | int idx, ret = 0; |
efc64404 FW |
11893 | |
11894 | if (!kvm_arch_has_assigned_device(kvm) || | |
a0052191 YZ |
11895 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
11896 | !kvm_vcpu_apicv_active(kvm->vcpus[0])) | |
efc64404 FW |
11897 | return 0; |
11898 | ||
11899 | idx = srcu_read_lock(&kvm->irq_srcu); | |
11900 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
3a8b0677 JS |
11901 | if (guest_irq >= irq_rt->nr_rt_entries || |
11902 | hlist_empty(&irq_rt->map[guest_irq])) { | |
11903 | pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", | |
11904 | guest_irq, irq_rt->nr_rt_entries); | |
11905 | goto out; | |
11906 | } | |
efc64404 FW |
11907 | |
11908 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
11909 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
11910 | continue; | |
11911 | /* | |
11912 | * VT-d PI cannot support posting multicast/broadcast | |
11913 | * interrupts to a vCPU, we still use interrupt remapping | |
11914 | * for these kind of interrupts. | |
11915 | * | |
11916 | * For lowest-priority interrupts, we only support | |
11917 | * those with single CPU as the destination, e.g. user | |
11918 | * configures the interrupts via /proc/irq or uses | |
11919 | * irqbalance to make the interrupts single-CPU. | |
11920 | * | |
11921 | * We will support full lowest-priority interrupt later. | |
11922 | */ | |
11923 | ||
37131313 | 11924 | kvm_set_msi_irq(kvm, e, &irq); |
23a1c257 FW |
11925 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { |
11926 | /* | |
11927 | * Make sure the IRTE is in remapped mode if | |
11928 | * we don't handle it in posted mode. | |
11929 | */ | |
11930 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
11931 | if (ret < 0) { | |
11932 | printk(KERN_INFO | |
11933 | "failed to back to remapped mode, irq: %u\n", | |
11934 | host_irq); | |
11935 | goto out; | |
11936 | } | |
11937 | ||
efc64404 | 11938 | continue; |
23a1c257 | 11939 | } |
efc64404 FW |
11940 | |
11941 | vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); | |
11942 | vcpu_info.vector = irq.vector; | |
11943 | ||
b6ce9780 | 11944 | trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi, |
efc64404 FW |
11945 | vcpu_info.vector, vcpu_info.pi_desc_addr, set); |
11946 | ||
11947 | if (set) | |
11948 | ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); | |
dc91f2eb | 11949 | else |
efc64404 | 11950 | ret = irq_set_vcpu_affinity(host_irq, NULL); |
efc64404 FW |
11951 | |
11952 | if (ret < 0) { | |
11953 | printk(KERN_INFO "%s: failed to update PI IRTE\n", | |
11954 | __func__); | |
11955 | goto out; | |
11956 | } | |
11957 | } | |
11958 | ||
11959 | ret = 0; | |
11960 | out: | |
11961 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
11962 | return ret; | |
11963 | } | |
11964 | ||
c45dcc71 AR |
11965 | static void vmx_setup_mce(struct kvm_vcpu *vcpu) |
11966 | { | |
11967 | if (vcpu->arch.mcg_cap & MCG_LMCE_P) | |
11968 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
11969 | FEATURE_CONTROL_LMCE; | |
11970 | else | |
11971 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
11972 | ~FEATURE_CONTROL_LMCE; | |
11973 | } | |
11974 | ||
72d7b374 LP |
11975 | static int vmx_smi_allowed(struct kvm_vcpu *vcpu) |
11976 | { | |
72e9cbdb LP |
11977 | /* we need a nested vmexit to enter SMM, postpone if run is pending */ |
11978 | if (to_vmx(vcpu)->nested.nested_run_pending) | |
11979 | return 0; | |
72d7b374 LP |
11980 | return 1; |
11981 | } | |
11982 | ||
0234bf88 LP |
11983 | static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) |
11984 | { | |
72e9cbdb LP |
11985 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
11986 | ||
11987 | vmx->nested.smm.guest_mode = is_guest_mode(vcpu); | |
11988 | if (vmx->nested.smm.guest_mode) | |
11989 | nested_vmx_vmexit(vcpu, -1, 0, 0); | |
11990 | ||
11991 | vmx->nested.smm.vmxon = vmx->nested.vmxon; | |
11992 | vmx->nested.vmxon = false; | |
0234bf88 LP |
11993 | return 0; |
11994 | } | |
11995 | ||
11996 | static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase) | |
11997 | { | |
72e9cbdb LP |
11998 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
11999 | int ret; | |
12000 | ||
12001 | if (vmx->nested.smm.vmxon) { | |
12002 | vmx->nested.vmxon = true; | |
12003 | vmx->nested.smm.vmxon = false; | |
12004 | } | |
12005 | ||
12006 | if (vmx->nested.smm.guest_mode) { | |
12007 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
12008 | ret = enter_vmx_non_root_mode(vcpu, false); | |
12009 | vcpu->arch.hflags |= HF_SMM_MASK; | |
12010 | if (ret) | |
12011 | return ret; | |
12012 | ||
12013 | vmx->nested.smm.guest_mode = false; | |
12014 | } | |
0234bf88 LP |
12015 | return 0; |
12016 | } | |
12017 | ||
cc3d967f LP |
12018 | static int enable_smi_window(struct kvm_vcpu *vcpu) |
12019 | { | |
12020 | return 0; | |
12021 | } | |
12022 | ||
404f6aac | 12023 | static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { |
6aa8b732 AK |
12024 | .cpu_has_kvm_support = cpu_has_kvm_support, |
12025 | .disabled_by_bios = vmx_disabled_by_bios, | |
12026 | .hardware_setup = hardware_setup, | |
12027 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 12028 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
12029 | .hardware_enable = hardware_enable, |
12030 | .hardware_disable = hardware_disable, | |
04547156 | 12031 | .cpu_has_accelerated_tpr = report_flexpriority, |
6d396b55 | 12032 | .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase, |
6aa8b732 AK |
12033 | |
12034 | .vcpu_create = vmx_create_vcpu, | |
12035 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 12036 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 12037 | |
04d2cc77 | 12038 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
12039 | .vcpu_load = vmx_vcpu_load, |
12040 | .vcpu_put = vmx_vcpu_put, | |
12041 | ||
a96036b8 | 12042 | .update_bp_intercept = update_exception_bitmap, |
6aa8b732 AK |
12043 | .get_msr = vmx_get_msr, |
12044 | .set_msr = vmx_set_msr, | |
12045 | .get_segment_base = vmx_get_segment_base, | |
12046 | .get_segment = vmx_get_segment, | |
12047 | .set_segment = vmx_set_segment, | |
2e4d2653 | 12048 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 12049 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 12050 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 12051 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 12052 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 12053 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
12054 | .set_cr3 = vmx_set_cr3, |
12055 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 12056 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
12057 | .get_idt = vmx_get_idt, |
12058 | .set_idt = vmx_set_idt, | |
12059 | .get_gdt = vmx_get_gdt, | |
12060 | .set_gdt = vmx_set_gdt, | |
73aaf249 JK |
12061 | .get_dr6 = vmx_get_dr6, |
12062 | .set_dr6 = vmx_set_dr6, | |
020df079 | 12063 | .set_dr7 = vmx_set_dr7, |
81908bf4 | 12064 | .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, |
5fdbf976 | 12065 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
12066 | .get_rflags = vmx_get_rflags, |
12067 | .set_rflags = vmx_set_rflags, | |
be94f6b7 | 12068 | |
6aa8b732 | 12069 | .tlb_flush = vmx_flush_tlb, |
6aa8b732 | 12070 | |
6aa8b732 | 12071 | .run = vmx_vcpu_run, |
6062d012 | 12072 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 12073 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
12074 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
12075 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 12076 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 12077 | .set_irq = vmx_inject_irq, |
95ba8273 | 12078 | .set_nmi = vmx_inject_nmi, |
298101da | 12079 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 12080 | .cancel_injection = vmx_cancel_injection, |
78646121 | 12081 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 12082 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
12083 | .get_nmi_mask = vmx_get_nmi_mask, |
12084 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
12085 | .enable_nmi_window = enable_nmi_window, |
12086 | .enable_irq_window = enable_irq_window, | |
12087 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 12088 | .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode, |
38b99173 | 12089 | .set_apic_access_page_addr = vmx_set_apic_access_page_addr, |
d62caabb AS |
12090 | .get_enable_apicv = vmx_get_enable_apicv, |
12091 | .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, | |
c7c9c56c | 12092 | .load_eoi_exitmap = vmx_load_eoi_exitmap, |
967235d3 | 12093 | .apicv_post_state_restore = vmx_apicv_post_state_restore, |
c7c9c56c YZ |
12094 | .hwapic_irr_update = vmx_hwapic_irr_update, |
12095 | .hwapic_isr_update = vmx_hwapic_isr_update, | |
a20ed54d YZ |
12096 | .sync_pir_to_irr = vmx_sync_pir_to_irr, |
12097 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, | |
95ba8273 | 12098 | |
cbc94022 | 12099 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 12100 | .get_tdp_level = get_ept_level, |
4b12f0de | 12101 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 12102 | |
586f9607 | 12103 | .get_exit_info = vmx_get_exit_info, |
586f9607 | 12104 | |
17cc3935 | 12105 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
12106 | |
12107 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
12108 | |
12109 | .rdtscp_supported = vmx_rdtscp_supported, | |
ad756a16 | 12110 | .invpcid_supported = vmx_invpcid_supported, |
d4330ef2 JR |
12111 | |
12112 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
12113 | |
12114 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a ZA |
12115 | |
12116 | .write_tsc_offset = vmx_write_tsc_offset, | |
1c97f0a0 JR |
12117 | |
12118 | .set_tdp_cr3 = vmx_set_cr3, | |
8a76d7f2 JR |
12119 | |
12120 | .check_intercept = vmx_check_intercept, | |
a547c6db | 12121 | .handle_external_intr = vmx_handle_external_intr, |
da8999d3 | 12122 | .mpx_supported = vmx_mpx_supported, |
55412b2e | 12123 | .xsaves_supported = vmx_xsaves_supported, |
b6b8a145 JK |
12124 | |
12125 | .check_nested_events = vmx_check_nested_events, | |
ae97a3b8 RK |
12126 | |
12127 | .sched_in = vmx_sched_in, | |
843e4330 KH |
12128 | |
12129 | .slot_enable_log_dirty = vmx_slot_enable_log_dirty, | |
12130 | .slot_disable_log_dirty = vmx_slot_disable_log_dirty, | |
12131 | .flush_log_dirty = vmx_flush_log_dirty, | |
12132 | .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, | |
c5f983f6 | 12133 | .write_log_dirty = vmx_write_pml_buffer, |
25462f7f | 12134 | |
bf9f6ac8 FW |
12135 | .pre_block = vmx_pre_block, |
12136 | .post_block = vmx_post_block, | |
12137 | ||
25462f7f | 12138 | .pmu_ops = &intel_pmu_ops, |
efc64404 FW |
12139 | |
12140 | .update_pi_irte = vmx_update_pi_irte, | |
64672c95 YJ |
12141 | |
12142 | #ifdef CONFIG_X86_64 | |
12143 | .set_hv_timer = vmx_set_hv_timer, | |
12144 | .cancel_hv_timer = vmx_cancel_hv_timer, | |
12145 | #endif | |
c45dcc71 AR |
12146 | |
12147 | .setup_mce = vmx_setup_mce, | |
0234bf88 | 12148 | |
72d7b374 | 12149 | .smi_allowed = vmx_smi_allowed, |
0234bf88 LP |
12150 | .pre_enter_smm = vmx_pre_enter_smm, |
12151 | .pre_leave_smm = vmx_pre_leave_smm, | |
cc3d967f | 12152 | .enable_smi_window = enable_smi_window, |
6aa8b732 AK |
12153 | }; |
12154 | ||
12155 | static int __init vmx_init(void) | |
12156 | { | |
34a1cd60 TC |
12157 | int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
12158 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
fdef3ad1 | 12159 | if (r) |
34a1cd60 | 12160 | return r; |
25c5f225 | 12161 | |
2965faa5 | 12162 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
12163 | rcu_assign_pointer(crash_vmclear_loaded_vmcss, |
12164 | crash_vmclear_local_loaded_vmcss); | |
12165 | #endif | |
12166 | ||
fdef3ad1 | 12167 | return 0; |
6aa8b732 AK |
12168 | } |
12169 | ||
12170 | static void __exit vmx_exit(void) | |
12171 | { | |
2965faa5 | 12172 | #ifdef CONFIG_KEXEC_CORE |
3b63a43f | 12173 | RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); |
8f536b76 ZY |
12174 | synchronize_rcu(); |
12175 | #endif | |
12176 | ||
cb498ea2 | 12177 | kvm_exit(); |
6aa8b732 AK |
12178 | } |
12179 | ||
12180 | module_init(vmx_init) | |
12181 | module_exit(vmx_exit) |