]>
Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
8 | * | |
9 | * Authors: | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
17 | ||
85f455f7 | 18 | #include "irq.h" |
6aa8b732 | 19 | #include "vmx.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
edf88417 | 22 | #include <linux/kvm_host.h> |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/mm.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
c7addb90 | 28 | #include <linux/moduleparam.h> |
5fdbf976 | 29 | #include "kvm_cache_regs.h" |
35920a35 | 30 | #include "x86.h" |
e495606d | 31 | |
6aa8b732 | 32 | #include <asm/io.h> |
3b3be0d1 | 33 | #include <asm/desc.h> |
6aa8b732 | 34 | |
4ecac3fd AK |
35 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
36 | ||
6aa8b732 AK |
37 | MODULE_AUTHOR("Qumranet"); |
38 | MODULE_LICENSE("GPL"); | |
39 | ||
c7addb90 AK |
40 | static int bypass_guest_pf = 1; |
41 | module_param(bypass_guest_pf, bool, 0); | |
42 | ||
2384d2b3 SY |
43 | static int enable_vpid = 1; |
44 | module_param(enable_vpid, bool, 0); | |
45 | ||
4c9fc8ef AK |
46 | static int flexpriority_enabled = 1; |
47 | module_param(flexpriority_enabled, bool, 0); | |
48 | ||
1439442c | 49 | static int enable_ept = 1; |
d56f546d SY |
50 | module_param(enable_ept, bool, 0); |
51 | ||
04fa4d32 MG |
52 | static int emulate_invalid_guest_state = 0; |
53 | module_param(emulate_invalid_guest_state, bool, 0); | |
54 | ||
a2fa3e9f GH |
55 | struct vmcs { |
56 | u32 revision_id; | |
57 | u32 abort; | |
58 | char data[0]; | |
59 | }; | |
60 | ||
61 | struct vcpu_vmx { | |
fb3f0f51 | 62 | struct kvm_vcpu vcpu; |
543e4243 | 63 | struct list_head local_vcpus_link; |
313dbd49 | 64 | unsigned long host_rsp; |
a2fa3e9f | 65 | int launched; |
29bd8a78 | 66 | u8 fail; |
1155f76a | 67 | u32 idt_vectoring_info; |
a2fa3e9f GH |
68 | struct kvm_msr_entry *guest_msrs; |
69 | struct kvm_msr_entry *host_msrs; | |
70 | int nmsrs; | |
71 | int save_nmsrs; | |
72 | int msr_offset_efer; | |
73 | #ifdef CONFIG_X86_64 | |
74 | int msr_offset_kernel_gs_base; | |
75 | #endif | |
76 | struct vmcs *vmcs; | |
77 | struct { | |
78 | int loaded; | |
79 | u16 fs_sel, gs_sel, ldt_sel; | |
152d3f2f LV |
80 | int gs_ldt_reload_needed; |
81 | int fs_reload_needed; | |
51c6cf66 | 82 | int guest_efer_loaded; |
d77c26fc | 83 | } host_state; |
9c8cba37 AK |
84 | struct { |
85 | struct { | |
86 | bool pending; | |
87 | u8 vector; | |
88 | unsigned rip; | |
89 | } irq; | |
90 | } rmode; | |
2384d2b3 | 91 | int vpid; |
04fa4d32 | 92 | bool emulation_required; |
3b86cd99 JK |
93 | |
94 | /* Support for vnmi-less CPUs */ | |
95 | int soft_vnmi_blocked; | |
96 | ktime_t entry_time; | |
97 | s64 vnmi_blocked_time; | |
a2fa3e9f GH |
98 | }; |
99 | ||
100 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) | |
101 | { | |
fb3f0f51 | 102 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
103 | } |
104 | ||
b7ebfb05 | 105 | static int init_rmode(struct kvm *kvm); |
4e1096d2 | 106 | static u64 construct_eptp(unsigned long root_hpa); |
75880a01 | 107 | |
6aa8b732 AK |
108 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
109 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
543e4243 | 110 | static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu); |
6aa8b732 | 111 | |
fdef3ad1 HQ |
112 | static struct page *vmx_io_bitmap_a; |
113 | static struct page *vmx_io_bitmap_b; | |
25c5f225 | 114 | static struct page *vmx_msr_bitmap; |
fdef3ad1 | 115 | |
2384d2b3 SY |
116 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
117 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
118 | ||
1c3d14fe | 119 | static struct vmcs_config { |
6aa8b732 AK |
120 | int size; |
121 | int order; | |
122 | u32 revision_id; | |
1c3d14fe YS |
123 | u32 pin_based_exec_ctrl; |
124 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 125 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
126 | u32 vmexit_ctrl; |
127 | u32 vmentry_ctrl; | |
128 | } vmcs_config; | |
6aa8b732 | 129 | |
d56f546d SY |
130 | struct vmx_capability { |
131 | u32 ept; | |
132 | u32 vpid; | |
133 | } vmx_capability; | |
134 | ||
6aa8b732 AK |
135 | #define VMX_SEGMENT_FIELD(seg) \ |
136 | [VCPU_SREG_##seg] = { \ | |
137 | .selector = GUEST_##seg##_SELECTOR, \ | |
138 | .base = GUEST_##seg##_BASE, \ | |
139 | .limit = GUEST_##seg##_LIMIT, \ | |
140 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
141 | } | |
142 | ||
143 | static struct kvm_vmx_segment_field { | |
144 | unsigned selector; | |
145 | unsigned base; | |
146 | unsigned limit; | |
147 | unsigned ar_bytes; | |
148 | } kvm_vmx_segment_fields[] = { | |
149 | VMX_SEGMENT_FIELD(CS), | |
150 | VMX_SEGMENT_FIELD(DS), | |
151 | VMX_SEGMENT_FIELD(ES), | |
152 | VMX_SEGMENT_FIELD(FS), | |
153 | VMX_SEGMENT_FIELD(GS), | |
154 | VMX_SEGMENT_FIELD(SS), | |
155 | VMX_SEGMENT_FIELD(TR), | |
156 | VMX_SEGMENT_FIELD(LDTR), | |
157 | }; | |
158 | ||
4d56c8a7 AK |
159 | /* |
160 | * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it | |
161 | * away by decrementing the array size. | |
162 | */ | |
6aa8b732 | 163 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 164 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
165 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE, |
166 | #endif | |
167 | MSR_EFER, MSR_K6_STAR, | |
168 | }; | |
9d8f549d | 169 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 170 | |
a2fa3e9f GH |
171 | static void load_msrs(struct kvm_msr_entry *e, int n) |
172 | { | |
173 | int i; | |
174 | ||
175 | for (i = 0; i < n; ++i) | |
176 | wrmsrl(e[i].index, e[i].data); | |
177 | } | |
178 | ||
179 | static void save_msrs(struct kvm_msr_entry *e, int n) | |
180 | { | |
181 | int i; | |
182 | ||
183 | for (i = 0; i < n; ++i) | |
184 | rdmsrl(e[i].index, e[i].data); | |
185 | } | |
186 | ||
6aa8b732 AK |
187 | static inline int is_page_fault(u32 intr_info) |
188 | { | |
189 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
190 | INTR_INFO_VALID_MASK)) == | |
191 | (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); | |
192 | } | |
193 | ||
2ab455cc AL |
194 | static inline int is_no_device(u32 intr_info) |
195 | { | |
196 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
197 | INTR_INFO_VALID_MASK)) == | |
198 | (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); | |
199 | } | |
200 | ||
7aa81cc0 AL |
201 | static inline int is_invalid_opcode(u32 intr_info) |
202 | { | |
203 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
204 | INTR_INFO_VALID_MASK)) == | |
205 | (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); | |
206 | } | |
207 | ||
6aa8b732 AK |
208 | static inline int is_external_interrupt(u32 intr_info) |
209 | { | |
210 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
211 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
212 | } | |
213 | ||
25c5f225 SY |
214 | static inline int cpu_has_vmx_msr_bitmap(void) |
215 | { | |
216 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS); | |
217 | } | |
218 | ||
6e5d865c YS |
219 | static inline int cpu_has_vmx_tpr_shadow(void) |
220 | { | |
221 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW); | |
222 | } | |
223 | ||
224 | static inline int vm_need_tpr_shadow(struct kvm *kvm) | |
225 | { | |
226 | return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm))); | |
227 | } | |
228 | ||
f78e0e2e SY |
229 | static inline int cpu_has_secondary_exec_ctrls(void) |
230 | { | |
231 | return (vmcs_config.cpu_based_exec_ctrl & | |
232 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); | |
233 | } | |
234 | ||
774ead3a | 235 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 236 | { |
4c9fc8ef AK |
237 | return flexpriority_enabled |
238 | && (vmcs_config.cpu_based_2nd_exec_ctrl & | |
239 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
f78e0e2e SY |
240 | } |
241 | ||
d56f546d SY |
242 | static inline int cpu_has_vmx_invept_individual_addr(void) |
243 | { | |
244 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT)); | |
245 | } | |
246 | ||
247 | static inline int cpu_has_vmx_invept_context(void) | |
248 | { | |
249 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT)); | |
250 | } | |
251 | ||
252 | static inline int cpu_has_vmx_invept_global(void) | |
253 | { | |
254 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT)); | |
255 | } | |
256 | ||
257 | static inline int cpu_has_vmx_ept(void) | |
258 | { | |
259 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
260 | SECONDARY_EXEC_ENABLE_EPT); | |
261 | } | |
262 | ||
263 | static inline int vm_need_ept(void) | |
264 | { | |
265 | return (cpu_has_vmx_ept() && enable_ept); | |
266 | } | |
267 | ||
f78e0e2e SY |
268 | static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm) |
269 | { | |
270 | return ((cpu_has_vmx_virtualize_apic_accesses()) && | |
271 | (irqchip_in_kernel(kvm))); | |
272 | } | |
273 | ||
2384d2b3 SY |
274 | static inline int cpu_has_vmx_vpid(void) |
275 | { | |
276 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
277 | SECONDARY_EXEC_ENABLE_VPID); | |
278 | } | |
279 | ||
f08864b4 SY |
280 | static inline int cpu_has_virtual_nmis(void) |
281 | { | |
282 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
283 | } | |
284 | ||
8b9cf98c | 285 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
286 | { |
287 | int i; | |
288 | ||
a2fa3e9f GH |
289 | for (i = 0; i < vmx->nmsrs; ++i) |
290 | if (vmx->guest_msrs[i].index == msr) | |
a75beee6 ED |
291 | return i; |
292 | return -1; | |
293 | } | |
294 | ||
2384d2b3 SY |
295 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
296 | { | |
297 | struct { | |
298 | u64 vpid : 16; | |
299 | u64 rsvd : 48; | |
300 | u64 gva; | |
301 | } operand = { vpid, 0, gva }; | |
302 | ||
4ecac3fd | 303 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
304 | /* CF==1 or ZF==1 --> rc = -1 */ |
305 | "; ja 1f ; ud2 ; 1:" | |
306 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
307 | } | |
308 | ||
1439442c SY |
309 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
310 | { | |
311 | struct { | |
312 | u64 eptp, gpa; | |
313 | } operand = {eptp, gpa}; | |
314 | ||
4ecac3fd | 315 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
316 | /* CF==1 or ZF==1 --> rc = -1 */ |
317 | "; ja 1f ; ud2 ; 1:\n" | |
318 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
319 | } | |
320 | ||
8b9cf98c | 321 | static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
322 | { |
323 | int i; | |
324 | ||
8b9cf98c | 325 | i = __find_msr_index(vmx, msr); |
a75beee6 | 326 | if (i >= 0) |
a2fa3e9f | 327 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 328 | return NULL; |
7725f0ba AK |
329 | } |
330 | ||
6aa8b732 AK |
331 | static void vmcs_clear(struct vmcs *vmcs) |
332 | { | |
333 | u64 phys_addr = __pa(vmcs); | |
334 | u8 error; | |
335 | ||
4ecac3fd | 336 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
6aa8b732 AK |
337 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) |
338 | : "cc", "memory"); | |
339 | if (error) | |
340 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
341 | vmcs, phys_addr); | |
342 | } | |
343 | ||
344 | static void __vcpu_clear(void *arg) | |
345 | { | |
8b9cf98c | 346 | struct vcpu_vmx *vmx = arg; |
d3b2c338 | 347 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 348 | |
8b9cf98c | 349 | if (vmx->vcpu.cpu == cpu) |
a2fa3e9f GH |
350 | vmcs_clear(vmx->vmcs); |
351 | if (per_cpu(current_vmcs, cpu) == vmx->vmcs) | |
6aa8b732 | 352 | per_cpu(current_vmcs, cpu) = NULL; |
ad312c7c | 353 | rdtscll(vmx->vcpu.arch.host_tsc); |
543e4243 AK |
354 | list_del(&vmx->local_vcpus_link); |
355 | vmx->vcpu.cpu = -1; | |
356 | vmx->launched = 0; | |
6aa8b732 AK |
357 | } |
358 | ||
8b9cf98c | 359 | static void vcpu_clear(struct vcpu_vmx *vmx) |
8d0be2b3 | 360 | { |
eae5ecb5 AK |
361 | if (vmx->vcpu.cpu == -1) |
362 | return; | |
8691e5a8 | 363 | smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1); |
8d0be2b3 AK |
364 | } |
365 | ||
2384d2b3 SY |
366 | static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx) |
367 | { | |
368 | if (vmx->vpid == 0) | |
369 | return; | |
370 | ||
371 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); | |
372 | } | |
373 | ||
1439442c SY |
374 | static inline void ept_sync_global(void) |
375 | { | |
376 | if (cpu_has_vmx_invept_global()) | |
377 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
378 | } | |
379 | ||
380 | static inline void ept_sync_context(u64 eptp) | |
381 | { | |
382 | if (vm_need_ept()) { | |
383 | if (cpu_has_vmx_invept_context()) | |
384 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
385 | else | |
386 | ept_sync_global(); | |
387 | } | |
388 | } | |
389 | ||
390 | static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa) | |
391 | { | |
392 | if (vm_need_ept()) { | |
393 | if (cpu_has_vmx_invept_individual_addr()) | |
394 | __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR, | |
395 | eptp, gpa); | |
396 | else | |
397 | ept_sync_context(eptp); | |
398 | } | |
399 | } | |
400 | ||
6aa8b732 AK |
401 | static unsigned long vmcs_readl(unsigned long field) |
402 | { | |
403 | unsigned long value; | |
404 | ||
4ecac3fd | 405 | asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX) |
6aa8b732 AK |
406 | : "=a"(value) : "d"(field) : "cc"); |
407 | return value; | |
408 | } | |
409 | ||
410 | static u16 vmcs_read16(unsigned long field) | |
411 | { | |
412 | return vmcs_readl(field); | |
413 | } | |
414 | ||
415 | static u32 vmcs_read32(unsigned long field) | |
416 | { | |
417 | return vmcs_readl(field); | |
418 | } | |
419 | ||
420 | static u64 vmcs_read64(unsigned long field) | |
421 | { | |
05b3e0c2 | 422 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
423 | return vmcs_readl(field); |
424 | #else | |
425 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
426 | #endif | |
427 | } | |
428 | ||
e52de1b8 AK |
429 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
430 | { | |
431 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
432 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
433 | dump_stack(); | |
434 | } | |
435 | ||
6aa8b732 AK |
436 | static void vmcs_writel(unsigned long field, unsigned long value) |
437 | { | |
438 | u8 error; | |
439 | ||
4ecac3fd | 440 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 441 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
442 | if (unlikely(error)) |
443 | vmwrite_error(field, value); | |
6aa8b732 AK |
444 | } |
445 | ||
446 | static void vmcs_write16(unsigned long field, u16 value) | |
447 | { | |
448 | vmcs_writel(field, value); | |
449 | } | |
450 | ||
451 | static void vmcs_write32(unsigned long field, u32 value) | |
452 | { | |
453 | vmcs_writel(field, value); | |
454 | } | |
455 | ||
456 | static void vmcs_write64(unsigned long field, u64 value) | |
457 | { | |
6aa8b732 | 458 | vmcs_writel(field, value); |
7682f2d0 | 459 | #ifndef CONFIG_X86_64 |
6aa8b732 AK |
460 | asm volatile (""); |
461 | vmcs_writel(field+1, value >> 32); | |
462 | #endif | |
463 | } | |
464 | ||
2ab455cc AL |
465 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
466 | { | |
467 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
468 | } | |
469 | ||
470 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
471 | { | |
472 | vmcs_writel(field, vmcs_readl(field) | mask); | |
473 | } | |
474 | ||
abd3f2d6 AK |
475 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
476 | { | |
477 | u32 eb; | |
478 | ||
7aa81cc0 | 479 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR); |
abd3f2d6 AK |
480 | if (!vcpu->fpu_active) |
481 | eb |= 1u << NM_VECTOR; | |
482 | if (vcpu->guest_debug.enabled) | |
19bd8afd | 483 | eb |= 1u << DB_VECTOR; |
ad312c7c | 484 | if (vcpu->arch.rmode.active) |
abd3f2d6 | 485 | eb = ~0; |
1439442c SY |
486 | if (vm_need_ept()) |
487 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ | |
abd3f2d6 AK |
488 | vmcs_write32(EXCEPTION_BITMAP, eb); |
489 | } | |
490 | ||
33ed6329 AK |
491 | static void reload_tss(void) |
492 | { | |
33ed6329 AK |
493 | /* |
494 | * VT restores TR but not its size. Useless. | |
495 | */ | |
496 | struct descriptor_table gdt; | |
a5f61300 | 497 | struct desc_struct *descs; |
33ed6329 | 498 | |
d6e88aec | 499 | kvm_get_gdt(&gdt); |
33ed6329 AK |
500 | descs = (void *)gdt.base; |
501 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ | |
502 | load_TR_desc(); | |
33ed6329 AK |
503 | } |
504 | ||
8b9cf98c | 505 | static void load_transition_efer(struct vcpu_vmx *vmx) |
2cc51560 | 506 | { |
a2fa3e9f | 507 | int efer_offset = vmx->msr_offset_efer; |
51c6cf66 AK |
508 | u64 host_efer = vmx->host_msrs[efer_offset].data; |
509 | u64 guest_efer = vmx->guest_msrs[efer_offset].data; | |
510 | u64 ignore_bits; | |
511 | ||
512 | if (efer_offset < 0) | |
513 | return; | |
514 | /* | |
515 | * NX is emulated; LMA and LME handled by hardware; SCE meaninless | |
516 | * outside long mode | |
517 | */ | |
518 | ignore_bits = EFER_NX | EFER_SCE; | |
519 | #ifdef CONFIG_X86_64 | |
520 | ignore_bits |= EFER_LMA | EFER_LME; | |
521 | /* SCE is meaningful only in long mode on Intel */ | |
522 | if (guest_efer & EFER_LMA) | |
523 | ignore_bits &= ~(u64)EFER_SCE; | |
524 | #endif | |
525 | if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits)) | |
526 | return; | |
2cc51560 | 527 | |
51c6cf66 AK |
528 | vmx->host_state.guest_efer_loaded = 1; |
529 | guest_efer &= ~ignore_bits; | |
530 | guest_efer |= host_efer & ignore_bits; | |
531 | wrmsrl(MSR_EFER, guest_efer); | |
8b9cf98c | 532 | vmx->vcpu.stat.efer_reload++; |
2cc51560 ED |
533 | } |
534 | ||
51c6cf66 AK |
535 | static void reload_host_efer(struct vcpu_vmx *vmx) |
536 | { | |
537 | if (vmx->host_state.guest_efer_loaded) { | |
538 | vmx->host_state.guest_efer_loaded = 0; | |
539 | load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1); | |
540 | } | |
541 | } | |
542 | ||
04d2cc77 | 543 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 544 | { |
04d2cc77 AK |
545 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
546 | ||
a2fa3e9f | 547 | if (vmx->host_state.loaded) |
33ed6329 AK |
548 | return; |
549 | ||
a2fa3e9f | 550 | vmx->host_state.loaded = 1; |
33ed6329 AK |
551 | /* |
552 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
553 | * allow segment selectors with cpl > 0 or ti == 1. | |
554 | */ | |
d6e88aec | 555 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 556 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
d6e88aec | 557 | vmx->host_state.fs_sel = kvm_read_fs(); |
152d3f2f | 558 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 559 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
560 | vmx->host_state.fs_reload_needed = 0; |
561 | } else { | |
33ed6329 | 562 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 563 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 564 | } |
d6e88aec | 565 | vmx->host_state.gs_sel = kvm_read_gs(); |
a2fa3e9f GH |
566 | if (!(vmx->host_state.gs_sel & 7)) |
567 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
568 | else { |
569 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 570 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
571 | } |
572 | ||
573 | #ifdef CONFIG_X86_64 | |
574 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
575 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
576 | #else | |
a2fa3e9f GH |
577 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
578 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 579 | #endif |
707c0874 AK |
580 | |
581 | #ifdef CONFIG_X86_64 | |
d77c26fc | 582 | if (is_long_mode(&vmx->vcpu)) |
a2fa3e9f GH |
583 | save_msrs(vmx->host_msrs + |
584 | vmx->msr_offset_kernel_gs_base, 1); | |
d77c26fc | 585 | |
707c0874 | 586 | #endif |
a2fa3e9f | 587 | load_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
51c6cf66 | 588 | load_transition_efer(vmx); |
33ed6329 AK |
589 | } |
590 | ||
a9b21b62 | 591 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 592 | { |
15ad7146 | 593 | unsigned long flags; |
33ed6329 | 594 | |
a2fa3e9f | 595 | if (!vmx->host_state.loaded) |
33ed6329 AK |
596 | return; |
597 | ||
e1beb1d3 | 598 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 599 | vmx->host_state.loaded = 0; |
152d3f2f | 600 | if (vmx->host_state.fs_reload_needed) |
d6e88aec | 601 | kvm_load_fs(vmx->host_state.fs_sel); |
152d3f2f | 602 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 603 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 AK |
604 | /* |
605 | * If we have to reload gs, we must take care to | |
606 | * preserve our gs base. | |
607 | */ | |
15ad7146 | 608 | local_irq_save(flags); |
d6e88aec | 609 | kvm_load_gs(vmx->host_state.gs_sel); |
33ed6329 AK |
610 | #ifdef CONFIG_X86_64 |
611 | wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE)); | |
612 | #endif | |
15ad7146 | 613 | local_irq_restore(flags); |
33ed6329 | 614 | } |
152d3f2f | 615 | reload_tss(); |
a2fa3e9f GH |
616 | save_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
617 | load_msrs(vmx->host_msrs, vmx->save_nmsrs); | |
51c6cf66 | 618 | reload_host_efer(vmx); |
33ed6329 AK |
619 | } |
620 | ||
a9b21b62 AK |
621 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
622 | { | |
623 | preempt_disable(); | |
624 | __vmx_load_host_state(vmx); | |
625 | preempt_enable(); | |
626 | } | |
627 | ||
6aa8b732 AK |
628 | /* |
629 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
630 | * vcpu mutex is already taken. | |
631 | */ | |
15ad7146 | 632 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 633 | { |
a2fa3e9f GH |
634 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
635 | u64 phys_addr = __pa(vmx->vmcs); | |
019960ae | 636 | u64 tsc_this, delta, new_offset; |
6aa8b732 | 637 | |
a3d7f85f | 638 | if (vcpu->cpu != cpu) { |
8b9cf98c | 639 | vcpu_clear(vmx); |
2f599714 | 640 | kvm_migrate_timers(vcpu); |
2384d2b3 | 641 | vpid_sync_vcpu_all(vmx); |
543e4243 AK |
642 | local_irq_disable(); |
643 | list_add(&vmx->local_vcpus_link, | |
644 | &per_cpu(vcpus_on_cpu, cpu)); | |
645 | local_irq_enable(); | |
a3d7f85f | 646 | } |
6aa8b732 | 647 | |
a2fa3e9f | 648 | if (per_cpu(current_vmcs, cpu) != vmx->vmcs) { |
6aa8b732 AK |
649 | u8 error; |
650 | ||
a2fa3e9f | 651 | per_cpu(current_vmcs, cpu) = vmx->vmcs; |
4ecac3fd | 652 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" |
6aa8b732 AK |
653 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) |
654 | : "cc"); | |
655 | if (error) | |
656 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
a2fa3e9f | 657 | vmx->vmcs, phys_addr); |
6aa8b732 AK |
658 | } |
659 | ||
660 | if (vcpu->cpu != cpu) { | |
661 | struct descriptor_table dt; | |
662 | unsigned long sysenter_esp; | |
663 | ||
664 | vcpu->cpu = cpu; | |
665 | /* | |
666 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
667 | * processors. | |
668 | */ | |
d6e88aec AK |
669 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
670 | kvm_get_gdt(&dt); | |
6aa8b732 AK |
671 | vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */ |
672 | ||
673 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
674 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
7700270e AK |
675 | |
676 | /* | |
677 | * Make sure the time stamp counter is monotonous. | |
678 | */ | |
679 | rdtscll(tsc_this); | |
019960ae AK |
680 | if (tsc_this < vcpu->arch.host_tsc) { |
681 | delta = vcpu->arch.host_tsc - tsc_this; | |
682 | new_offset = vmcs_read64(TSC_OFFSET) + delta; | |
683 | vmcs_write64(TSC_OFFSET, new_offset); | |
684 | } | |
6aa8b732 | 685 | } |
6aa8b732 AK |
686 | } |
687 | ||
688 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
689 | { | |
a9b21b62 | 690 | __vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
691 | } |
692 | ||
5fd86fcf AK |
693 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
694 | { | |
695 | if (vcpu->fpu_active) | |
696 | return; | |
697 | vcpu->fpu_active = 1; | |
707d92fa | 698 | vmcs_clear_bits(GUEST_CR0, X86_CR0_TS); |
ad312c7c | 699 | if (vcpu->arch.cr0 & X86_CR0_TS) |
707d92fa | 700 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
701 | update_exception_bitmap(vcpu); |
702 | } | |
703 | ||
704 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) | |
705 | { | |
706 | if (!vcpu->fpu_active) | |
707 | return; | |
708 | vcpu->fpu_active = 0; | |
707d92fa | 709 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
710 | update_exception_bitmap(vcpu); |
711 | } | |
712 | ||
6aa8b732 AK |
713 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
714 | { | |
715 | return vmcs_readl(GUEST_RFLAGS); | |
716 | } | |
717 | ||
718 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
719 | { | |
ad312c7c | 720 | if (vcpu->arch.rmode.active) |
053de044 | 721 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
722 | vmcs_writel(GUEST_RFLAGS, rflags); |
723 | } | |
724 | ||
725 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
726 | { | |
727 | unsigned long rip; | |
728 | u32 interruptibility; | |
729 | ||
5fdbf976 | 730 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 731 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 732 | kvm_rip_write(vcpu, rip); |
6aa8b732 AK |
733 | |
734 | /* | |
735 | * We emulated an instruction, so temporary interrupt blocking | |
736 | * should be removed, if set. | |
737 | */ | |
738 | interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
739 | if (interruptibility & 3) | |
740 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
741 | interruptibility & ~3); | |
ad312c7c | 742 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
743 | } |
744 | ||
298101da AK |
745 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
746 | bool has_error_code, u32 error_code) | |
747 | { | |
77ab6db0 JK |
748 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
749 | ||
750 | if (has_error_code) | |
751 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); | |
752 | ||
753 | if (vcpu->arch.rmode.active) { | |
754 | vmx->rmode.irq.pending = true; | |
755 | vmx->rmode.irq.vector = nr; | |
756 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); | |
757 | if (nr == BP_VECTOR) | |
758 | vmx->rmode.irq.rip++; | |
759 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
760 | nr | INTR_TYPE_SOFT_INTR | |
761 | | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0) | |
762 | | INTR_INFO_VALID_MASK); | |
763 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
764 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); | |
765 | return; | |
766 | } | |
767 | ||
298101da AK |
768 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
769 | nr | INTR_TYPE_EXCEPTION | |
2e11384c | 770 | | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0) |
298101da | 771 | | INTR_INFO_VALID_MASK); |
298101da AK |
772 | } |
773 | ||
774 | static bool vmx_exception_injected(struct kvm_vcpu *vcpu) | |
775 | { | |
35920a35 | 776 | return false; |
298101da AK |
777 | } |
778 | ||
a75beee6 ED |
779 | /* |
780 | * Swap MSR entry in host/guest MSR entry array. | |
781 | */ | |
54e11fa1 | 782 | #ifdef CONFIG_X86_64 |
8b9cf98c | 783 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 784 | { |
a2fa3e9f GH |
785 | struct kvm_msr_entry tmp; |
786 | ||
787 | tmp = vmx->guest_msrs[to]; | |
788 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
789 | vmx->guest_msrs[from] = tmp; | |
790 | tmp = vmx->host_msrs[to]; | |
791 | vmx->host_msrs[to] = vmx->host_msrs[from]; | |
792 | vmx->host_msrs[from] = tmp; | |
a75beee6 | 793 | } |
54e11fa1 | 794 | #endif |
a75beee6 | 795 | |
e38aea3e AK |
796 | /* |
797 | * Set up the vmcs to automatically save and restore system | |
798 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
799 | * mode, as fiddling with msrs is very expensive. | |
800 | */ | |
8b9cf98c | 801 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 802 | { |
2cc51560 | 803 | int save_nmsrs; |
e38aea3e | 804 | |
33f9c505 | 805 | vmx_load_host_state(vmx); |
a75beee6 ED |
806 | save_nmsrs = 0; |
807 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 808 | if (is_long_mode(&vmx->vcpu)) { |
2cc51560 ED |
809 | int index; |
810 | ||
8b9cf98c | 811 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 812 | if (index >= 0) |
8b9cf98c RR |
813 | move_msr_up(vmx, index, save_nmsrs++); |
814 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 815 | if (index >= 0) |
8b9cf98c RR |
816 | move_msr_up(vmx, index, save_nmsrs++); |
817 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 818 | if (index >= 0) |
8b9cf98c RR |
819 | move_msr_up(vmx, index, save_nmsrs++); |
820 | index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE); | |
a75beee6 | 821 | if (index >= 0) |
8b9cf98c | 822 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
823 | /* |
824 | * MSR_K6_STAR is only needed on long mode guests, and only | |
825 | * if efer.sce is enabled. | |
826 | */ | |
8b9cf98c | 827 | index = __find_msr_index(vmx, MSR_K6_STAR); |
ad312c7c | 828 | if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE)) |
8b9cf98c | 829 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
830 | } |
831 | #endif | |
a2fa3e9f | 832 | vmx->save_nmsrs = save_nmsrs; |
e38aea3e | 833 | |
4d56c8a7 | 834 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 835 | vmx->msr_offset_kernel_gs_base = |
8b9cf98c | 836 | __find_msr_index(vmx, MSR_KERNEL_GS_BASE); |
4d56c8a7 | 837 | #endif |
8b9cf98c | 838 | vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER); |
e38aea3e AK |
839 | } |
840 | ||
6aa8b732 AK |
841 | /* |
842 | * reads and returns guest's timestamp counter "register" | |
843 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
844 | */ | |
845 | static u64 guest_read_tsc(void) | |
846 | { | |
847 | u64 host_tsc, tsc_offset; | |
848 | ||
849 | rdtscll(host_tsc); | |
850 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
851 | return host_tsc + tsc_offset; | |
852 | } | |
853 | ||
854 | /* | |
855 | * writes 'guest_tsc' into guest's timestamp counter "register" | |
856 | * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc | |
857 | */ | |
858 | static void guest_write_tsc(u64 guest_tsc) | |
859 | { | |
860 | u64 host_tsc; | |
861 | ||
862 | rdtscll(host_tsc); | |
863 | vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc); | |
864 | } | |
865 | ||
6aa8b732 AK |
866 | /* |
867 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
868 | * Returns 0 on success, non-0 otherwise. | |
869 | * Assumes vcpu_load() was already called. | |
870 | */ | |
871 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
872 | { | |
873 | u64 data; | |
a2fa3e9f | 874 | struct kvm_msr_entry *msr; |
6aa8b732 AK |
875 | |
876 | if (!pdata) { | |
877 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
878 | return -EINVAL; | |
879 | } | |
880 | ||
881 | switch (msr_index) { | |
05b3e0c2 | 882 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
883 | case MSR_FS_BASE: |
884 | data = vmcs_readl(GUEST_FS_BASE); | |
885 | break; | |
886 | case MSR_GS_BASE: | |
887 | data = vmcs_readl(GUEST_GS_BASE); | |
888 | break; | |
889 | case MSR_EFER: | |
3bab1f5d | 890 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
891 | #endif |
892 | case MSR_IA32_TIME_STAMP_COUNTER: | |
893 | data = guest_read_tsc(); | |
894 | break; | |
895 | case MSR_IA32_SYSENTER_CS: | |
896 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
897 | break; | |
898 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 899 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
900 | break; |
901 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 902 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 903 | break; |
6aa8b732 | 904 | default: |
8b9cf98c | 905 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d AK |
906 | if (msr) { |
907 | data = msr->data; | |
908 | break; | |
6aa8b732 | 909 | } |
3bab1f5d | 910 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
911 | } |
912 | ||
913 | *pdata = data; | |
914 | return 0; | |
915 | } | |
916 | ||
917 | /* | |
918 | * Writes msr value into into the appropriate "register". | |
919 | * Returns 0 on success, non-0 otherwise. | |
920 | * Assumes vcpu_load() was already called. | |
921 | */ | |
922 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
923 | { | |
a2fa3e9f GH |
924 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
925 | struct kvm_msr_entry *msr; | |
2cc51560 ED |
926 | int ret = 0; |
927 | ||
6aa8b732 | 928 | switch (msr_index) { |
05b3e0c2 | 929 | #ifdef CONFIG_X86_64 |
3bab1f5d | 930 | case MSR_EFER: |
a9b21b62 | 931 | vmx_load_host_state(vmx); |
2cc51560 | 932 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
2cc51560 | 933 | break; |
6aa8b732 AK |
934 | case MSR_FS_BASE: |
935 | vmcs_writel(GUEST_FS_BASE, data); | |
936 | break; | |
937 | case MSR_GS_BASE: | |
938 | vmcs_writel(GUEST_GS_BASE, data); | |
939 | break; | |
940 | #endif | |
941 | case MSR_IA32_SYSENTER_CS: | |
942 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
943 | break; | |
944 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 945 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
946 | break; |
947 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 948 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 949 | break; |
d27d4aca | 950 | case MSR_IA32_TIME_STAMP_COUNTER: |
6aa8b732 | 951 | guest_write_tsc(data); |
efa67e0d CL |
952 | break; |
953 | case MSR_P6_PERFCTR0: | |
954 | case MSR_P6_PERFCTR1: | |
955 | case MSR_P6_EVNTSEL0: | |
956 | case MSR_P6_EVNTSEL1: | |
957 | /* | |
958 | * Just discard all writes to the performance counters; this | |
959 | * should keep both older linux and windows 64-bit guests | |
960 | * happy | |
961 | */ | |
962 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data); | |
963 | ||
6aa8b732 | 964 | break; |
468d472f SY |
965 | case MSR_IA32_CR_PAT: |
966 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
967 | vmcs_write64(GUEST_IA32_PAT, data); | |
968 | vcpu->arch.pat = data; | |
969 | break; | |
970 | } | |
971 | /* Otherwise falls through to kvm_set_msr_common */ | |
6aa8b732 | 972 | default: |
a9b21b62 | 973 | vmx_load_host_state(vmx); |
8b9cf98c | 974 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d AK |
975 | if (msr) { |
976 | msr->data = data; | |
977 | break; | |
6aa8b732 | 978 | } |
2cc51560 | 979 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
980 | } |
981 | ||
2cc51560 | 982 | return ret; |
6aa8b732 AK |
983 | } |
984 | ||
5fdbf976 | 985 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 986 | { |
5fdbf976 MT |
987 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
988 | switch (reg) { | |
989 | case VCPU_REGS_RSP: | |
990 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
991 | break; | |
992 | case VCPU_REGS_RIP: | |
993 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
994 | break; | |
995 | default: | |
996 | break; | |
997 | } | |
6aa8b732 AK |
998 | } |
999 | ||
1000 | static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
1001 | { | |
1002 | unsigned long dr7 = 0x400; | |
6aa8b732 AK |
1003 | int old_singlestep; |
1004 | ||
6aa8b732 AK |
1005 | old_singlestep = vcpu->guest_debug.singlestep; |
1006 | ||
1007 | vcpu->guest_debug.enabled = dbg->enabled; | |
1008 | if (vcpu->guest_debug.enabled) { | |
1009 | int i; | |
1010 | ||
1011 | dr7 |= 0x200; /* exact */ | |
1012 | for (i = 0; i < 4; ++i) { | |
1013 | if (!dbg->breakpoints[i].enabled) | |
1014 | continue; | |
1015 | vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address; | |
1016 | dr7 |= 2 << (i*2); /* global enable */ | |
1017 | dr7 |= 0 << (i*4+16); /* execution breakpoint */ | |
1018 | } | |
1019 | ||
6aa8b732 | 1020 | vcpu->guest_debug.singlestep = dbg->singlestep; |
abd3f2d6 | 1021 | } else |
6aa8b732 | 1022 | vcpu->guest_debug.singlestep = 0; |
6aa8b732 AK |
1023 | |
1024 | if (old_singlestep && !vcpu->guest_debug.singlestep) { | |
1025 | unsigned long flags; | |
1026 | ||
1027 | flags = vmcs_readl(GUEST_RFLAGS); | |
1028 | flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1029 | vmcs_writel(GUEST_RFLAGS, flags); | |
1030 | } | |
1031 | ||
abd3f2d6 | 1032 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
1033 | vmcs_writel(GUEST_DR7, dr7); |
1034 | ||
1035 | return 0; | |
1036 | } | |
1037 | ||
2a8067f1 ED |
1038 | static int vmx_get_irq(struct kvm_vcpu *vcpu) |
1039 | { | |
f7d9238f AK |
1040 | if (!vcpu->arch.interrupt.pending) |
1041 | return -1; | |
1042 | return vcpu->arch.interrupt.nr; | |
2a8067f1 ED |
1043 | } |
1044 | ||
6aa8b732 AK |
1045 | static __init int cpu_has_kvm_support(void) |
1046 | { | |
1047 | unsigned long ecx = cpuid_ecx(1); | |
1048 | return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */ | |
1049 | } | |
1050 | ||
1051 | static __init int vmx_disabled_by_bios(void) | |
1052 | { | |
1053 | u64 msr; | |
1054 | ||
1055 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
9ea542fa SY |
1056 | return (msr & (FEATURE_CONTROL_LOCKED | |
1057 | FEATURE_CONTROL_VMXON_ENABLED)) | |
1058 | == FEATURE_CONTROL_LOCKED; | |
62b3ffb8 | 1059 | /* locked but not enabled */ |
6aa8b732 AK |
1060 | } |
1061 | ||
774c47f1 | 1062 | static void hardware_enable(void *garbage) |
6aa8b732 AK |
1063 | { |
1064 | int cpu = raw_smp_processor_id(); | |
1065 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
1066 | u64 old; | |
1067 | ||
543e4243 | 1068 | INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu)); |
6aa8b732 | 1069 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
9ea542fa SY |
1070 | if ((old & (FEATURE_CONTROL_LOCKED | |
1071 | FEATURE_CONTROL_VMXON_ENABLED)) | |
1072 | != (FEATURE_CONTROL_LOCKED | | |
1073 | FEATURE_CONTROL_VMXON_ENABLED)) | |
6aa8b732 | 1074 | /* enable and lock */ |
62b3ffb8 | 1075 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | |
9ea542fa SY |
1076 | FEATURE_CONTROL_LOCKED | |
1077 | FEATURE_CONTROL_VMXON_ENABLED); | |
66aee91a | 1078 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
4ecac3fd AK |
1079 | asm volatile (ASM_VMX_VMXON_RAX |
1080 | : : "a"(&phys_addr), "m"(phys_addr) | |
6aa8b732 AK |
1081 | : "memory", "cc"); |
1082 | } | |
1083 | ||
543e4243 AK |
1084 | static void vmclear_local_vcpus(void) |
1085 | { | |
1086 | int cpu = raw_smp_processor_id(); | |
1087 | struct vcpu_vmx *vmx, *n; | |
1088 | ||
1089 | list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu), | |
1090 | local_vcpus_link) | |
1091 | __vcpu_clear(vmx); | |
1092 | } | |
1093 | ||
6aa8b732 AK |
1094 | static void hardware_disable(void *garbage) |
1095 | { | |
543e4243 | 1096 | vmclear_local_vcpus(); |
4ecac3fd | 1097 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
e693d71b | 1098 | write_cr4(read_cr4() & ~X86_CR4_VMXE); |
6aa8b732 AK |
1099 | } |
1100 | ||
1c3d14fe | 1101 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 1102 | u32 msr, u32 *result) |
1c3d14fe YS |
1103 | { |
1104 | u32 vmx_msr_low, vmx_msr_high; | |
1105 | u32 ctl = ctl_min | ctl_opt; | |
1106 | ||
1107 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
1108 | ||
1109 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
1110 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
1111 | ||
1112 | /* Ensure minimum (required) set of control bits are supported. */ | |
1113 | if (ctl_min & ~ctl) | |
002c7f7c | 1114 | return -EIO; |
1c3d14fe YS |
1115 | |
1116 | *result = ctl; | |
1117 | return 0; | |
1118 | } | |
1119 | ||
002c7f7c | 1120 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
1121 | { |
1122 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 1123 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
1124 | u32 _pin_based_exec_control = 0; |
1125 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 1126 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
1127 | u32 _vmexit_control = 0; |
1128 | u32 _vmentry_control = 0; | |
1129 | ||
1130 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
f08864b4 | 1131 | opt = PIN_BASED_VIRTUAL_NMIS; |
1c3d14fe YS |
1132 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
1133 | &_pin_based_exec_control) < 0) | |
002c7f7c | 1134 | return -EIO; |
1c3d14fe YS |
1135 | |
1136 | min = CPU_BASED_HLT_EXITING | | |
1137 | #ifdef CONFIG_X86_64 | |
1138 | CPU_BASED_CR8_LOAD_EXITING | | |
1139 | CPU_BASED_CR8_STORE_EXITING | | |
1140 | #endif | |
d56f546d SY |
1141 | CPU_BASED_CR3_LOAD_EXITING | |
1142 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
1143 | CPU_BASED_USE_IO_BITMAPS | |
1144 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 MT |
1145 | CPU_BASED_USE_TSC_OFFSETING | |
1146 | CPU_BASED_INVLPG_EXITING; | |
f78e0e2e | 1147 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 1148 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 1149 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
1150 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
1151 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 1152 | return -EIO; |
6e5d865c YS |
1153 | #ifdef CONFIG_X86_64 |
1154 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
1155 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
1156 | ~CPU_BASED_CR8_STORE_EXITING; | |
1157 | #endif | |
f78e0e2e | 1158 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
1159 | min2 = 0; |
1160 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
2384d2b3 | 1161 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d SY |
1162 | SECONDARY_EXEC_ENABLE_VPID | |
1163 | SECONDARY_EXEC_ENABLE_EPT; | |
1164 | if (adjust_vmx_controls(min2, opt2, | |
1165 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
1166 | &_cpu_based_2nd_exec_control) < 0) |
1167 | return -EIO; | |
1168 | } | |
1169 | #ifndef CONFIG_X86_64 | |
1170 | if (!(_cpu_based_2nd_exec_control & | |
1171 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
1172 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1173 | #endif | |
d56f546d | 1174 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
1175 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
1176 | enabled */ | |
d56f546d | 1177 | min &= ~(CPU_BASED_CR3_LOAD_EXITING | |
a7052897 MT |
1178 | CPU_BASED_CR3_STORE_EXITING | |
1179 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
1180 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
1181 | &_cpu_based_exec_control) < 0) | |
1182 | return -EIO; | |
1183 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, | |
1184 | vmx_capability.ept, vmx_capability.vpid); | |
1185 | } | |
1c3d14fe YS |
1186 | |
1187 | min = 0; | |
1188 | #ifdef CONFIG_X86_64 | |
1189 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
1190 | #endif | |
468d472f | 1191 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT; |
1c3d14fe YS |
1192 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
1193 | &_vmexit_control) < 0) | |
002c7f7c | 1194 | return -EIO; |
1c3d14fe | 1195 | |
468d472f SY |
1196 | min = 0; |
1197 | opt = VM_ENTRY_LOAD_IA32_PAT; | |
1c3d14fe YS |
1198 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
1199 | &_vmentry_control) < 0) | |
002c7f7c | 1200 | return -EIO; |
6aa8b732 | 1201 | |
c68876fd | 1202 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
1203 | |
1204 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
1205 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 1206 | return -EIO; |
1c3d14fe YS |
1207 | |
1208 | #ifdef CONFIG_X86_64 | |
1209 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
1210 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 1211 | return -EIO; |
1c3d14fe YS |
1212 | #endif |
1213 | ||
1214 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
1215 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 1216 | return -EIO; |
1c3d14fe | 1217 | |
002c7f7c YS |
1218 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
1219 | vmcs_conf->order = get_order(vmcs_config.size); | |
1220 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 1221 | |
002c7f7c YS |
1222 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
1223 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 1224 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
1225 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
1226 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe YS |
1227 | |
1228 | return 0; | |
c68876fd | 1229 | } |
6aa8b732 AK |
1230 | |
1231 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
1232 | { | |
1233 | int node = cpu_to_node(cpu); | |
1234 | struct page *pages; | |
1235 | struct vmcs *vmcs; | |
1236 | ||
1c3d14fe | 1237 | pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
1238 | if (!pages) |
1239 | return NULL; | |
1240 | vmcs = page_address(pages); | |
1c3d14fe YS |
1241 | memset(vmcs, 0, vmcs_config.size); |
1242 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
1243 | return vmcs; |
1244 | } | |
1245 | ||
1246 | static struct vmcs *alloc_vmcs(void) | |
1247 | { | |
d3b2c338 | 1248 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
1249 | } |
1250 | ||
1251 | static void free_vmcs(struct vmcs *vmcs) | |
1252 | { | |
1c3d14fe | 1253 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
1254 | } |
1255 | ||
39959588 | 1256 | static void free_kvm_area(void) |
6aa8b732 AK |
1257 | { |
1258 | int cpu; | |
1259 | ||
1260 | for_each_online_cpu(cpu) | |
1261 | free_vmcs(per_cpu(vmxarea, cpu)); | |
1262 | } | |
1263 | ||
6aa8b732 AK |
1264 | static __init int alloc_kvm_area(void) |
1265 | { | |
1266 | int cpu; | |
1267 | ||
1268 | for_each_online_cpu(cpu) { | |
1269 | struct vmcs *vmcs; | |
1270 | ||
1271 | vmcs = alloc_vmcs_cpu(cpu); | |
1272 | if (!vmcs) { | |
1273 | free_kvm_area(); | |
1274 | return -ENOMEM; | |
1275 | } | |
1276 | ||
1277 | per_cpu(vmxarea, cpu) = vmcs; | |
1278 | } | |
1279 | return 0; | |
1280 | } | |
1281 | ||
1282 | static __init int hardware_setup(void) | |
1283 | { | |
002c7f7c YS |
1284 | if (setup_vmcs_config(&vmcs_config) < 0) |
1285 | return -EIO; | |
50a37eb4 JR |
1286 | |
1287 | if (boot_cpu_has(X86_FEATURE_NX)) | |
1288 | kvm_enable_efer_bits(EFER_NX); | |
1289 | ||
6aa8b732 AK |
1290 | return alloc_kvm_area(); |
1291 | } | |
1292 | ||
1293 | static __exit void hardware_unsetup(void) | |
1294 | { | |
1295 | free_kvm_area(); | |
1296 | } | |
1297 | ||
6aa8b732 AK |
1298 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
1299 | { | |
1300 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1301 | ||
6af11b9e | 1302 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
1303 | vmcs_write16(sf->selector, save->selector); |
1304 | vmcs_writel(sf->base, save->base); | |
1305 | vmcs_write32(sf->limit, save->limit); | |
1306 | vmcs_write32(sf->ar_bytes, save->ar); | |
1307 | } else { | |
1308 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
1309 | << AR_DPL_SHIFT; | |
1310 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
1311 | } | |
1312 | } | |
1313 | ||
1314 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
1315 | { | |
1316 | unsigned long flags; | |
a89a8fb9 | 1317 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 1318 | |
a89a8fb9 | 1319 | vmx->emulation_required = 1; |
ad312c7c | 1320 | vcpu->arch.rmode.active = 0; |
6aa8b732 | 1321 | |
ad312c7c ZX |
1322 | vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base); |
1323 | vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit); | |
1324 | vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar); | |
6aa8b732 AK |
1325 | |
1326 | flags = vmcs_readl(GUEST_RFLAGS); | |
053de044 | 1327 | flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM); |
ad312c7c | 1328 | flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT); |
6aa8b732 AK |
1329 | vmcs_writel(GUEST_RFLAGS, flags); |
1330 | ||
66aee91a RR |
1331 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
1332 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
1333 | |
1334 | update_exception_bitmap(vcpu); | |
1335 | ||
a89a8fb9 MG |
1336 | if (emulate_invalid_guest_state) |
1337 | return; | |
1338 | ||
ad312c7c ZX |
1339 | fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es); |
1340 | fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1341 | fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1342 | fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
6aa8b732 AK |
1343 | |
1344 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
1345 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
1346 | ||
1347 | vmcs_write16(GUEST_CS_SELECTOR, | |
1348 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
1349 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1350 | } | |
1351 | ||
d77c26fc | 1352 | static gva_t rmode_tss_base(struct kvm *kvm) |
6aa8b732 | 1353 | { |
bfc6d222 | 1354 | if (!kvm->arch.tss_addr) { |
cbc94022 IE |
1355 | gfn_t base_gfn = kvm->memslots[0].base_gfn + |
1356 | kvm->memslots[0].npages - 3; | |
1357 | return base_gfn << PAGE_SHIFT; | |
1358 | } | |
bfc6d222 | 1359 | return kvm->arch.tss_addr; |
6aa8b732 AK |
1360 | } |
1361 | ||
1362 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
1363 | { | |
1364 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1365 | ||
1366 | save->selector = vmcs_read16(sf->selector); | |
1367 | save->base = vmcs_readl(sf->base); | |
1368 | save->limit = vmcs_read32(sf->limit); | |
1369 | save->ar = vmcs_read32(sf->ar_bytes); | |
15b00f32 JK |
1370 | vmcs_write16(sf->selector, save->base >> 4); |
1371 | vmcs_write32(sf->base, save->base & 0xfffff); | |
6aa8b732 AK |
1372 | vmcs_write32(sf->limit, 0xffff); |
1373 | vmcs_write32(sf->ar_bytes, 0xf3); | |
1374 | } | |
1375 | ||
1376 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
1377 | { | |
1378 | unsigned long flags; | |
a89a8fb9 | 1379 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 1380 | |
a89a8fb9 | 1381 | vmx->emulation_required = 1; |
ad312c7c | 1382 | vcpu->arch.rmode.active = 1; |
6aa8b732 | 1383 | |
ad312c7c | 1384 | vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE); |
6aa8b732 AK |
1385 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); |
1386 | ||
ad312c7c | 1387 | vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); |
6aa8b732 AK |
1388 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
1389 | ||
ad312c7c | 1390 | vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); |
6aa8b732 AK |
1391 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
1392 | ||
1393 | flags = vmcs_readl(GUEST_RFLAGS); | |
ad312c7c ZX |
1394 | vcpu->arch.rmode.save_iopl |
1395 | = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
6aa8b732 | 1396 | |
053de044 | 1397 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
1398 | |
1399 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 1400 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
1401 | update_exception_bitmap(vcpu); |
1402 | ||
a89a8fb9 MG |
1403 | if (emulate_invalid_guest_state) |
1404 | goto continue_rmode; | |
1405 | ||
6aa8b732 AK |
1406 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); |
1407 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
1408 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
1409 | ||
1410 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 1411 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
1412 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
1413 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
1414 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
1415 | ||
ad312c7c ZX |
1416 | fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es); |
1417 | fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1418 | fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1419 | fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
75880a01 | 1420 | |
a89a8fb9 | 1421 | continue_rmode: |
8668a3c4 | 1422 | kvm_mmu_reset_context(vcpu); |
b7ebfb05 | 1423 | init_rmode(vcpu->kvm); |
6aa8b732 AK |
1424 | } |
1425 | ||
05b3e0c2 | 1426 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1427 | |
1428 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
1429 | { | |
1430 | u32 guest_tr_ar; | |
1431 | ||
1432 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1433 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
1434 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
b8688d51 | 1435 | __func__); |
6aa8b732 AK |
1436 | vmcs_write32(GUEST_TR_AR_BYTES, |
1437 | (guest_tr_ar & ~AR_TYPE_MASK) | |
1438 | | AR_TYPE_BUSY_64_TSS); | |
1439 | } | |
1440 | ||
ad312c7c | 1441 | vcpu->arch.shadow_efer |= EFER_LMA; |
6aa8b732 | 1442 | |
8b9cf98c | 1443 | find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1444 | vmcs_write32(VM_ENTRY_CONTROLS, |
1445 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1446 | | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1447 | } |
1448 | ||
1449 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
1450 | { | |
ad312c7c | 1451 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
6aa8b732 AK |
1452 | |
1453 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1454 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1455 | & ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1456 | } |
1457 | ||
1458 | #endif | |
1459 | ||
2384d2b3 SY |
1460 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
1461 | { | |
1462 | vpid_sync_vcpu_all(to_vmx(vcpu)); | |
4e1096d2 SY |
1463 | if (vm_need_ept()) |
1464 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); | |
2384d2b3 SY |
1465 | } |
1466 | ||
25c4c276 | 1467 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 1468 | { |
ad312c7c ZX |
1469 | vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK; |
1470 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK; | |
399badf3 AK |
1471 | } |
1472 | ||
1439442c SY |
1473 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
1474 | { | |
1475 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1476 | if (!load_pdptrs(vcpu, vcpu->arch.cr3)) { | |
1477 | printk(KERN_ERR "EPT: Fail to load pdptrs!\n"); | |
1478 | return; | |
1479 | } | |
1480 | vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]); | |
1481 | vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]); | |
1482 | vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]); | |
1483 | vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]); | |
1484 | } | |
1485 | } | |
1486 | ||
1487 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); | |
1488 | ||
1489 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
1490 | unsigned long cr0, | |
1491 | struct kvm_vcpu *vcpu) | |
1492 | { | |
1493 | if (!(cr0 & X86_CR0_PG)) { | |
1494 | /* From paging/starting to nonpaging */ | |
1495 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1496 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
1497 | (CPU_BASED_CR3_LOAD_EXITING | |
1498 | CPU_BASED_CR3_STORE_EXITING)); | |
1499 | vcpu->arch.cr0 = cr0; | |
1500 | vmx_set_cr4(vcpu, vcpu->arch.cr4); | |
1501 | *hw_cr0 |= X86_CR0_PE | X86_CR0_PG; | |
1502 | *hw_cr0 &= ~X86_CR0_WP; | |
1503 | } else if (!is_paging(vcpu)) { | |
1504 | /* From nonpaging to paging */ | |
1505 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1506 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
1507 | ~(CPU_BASED_CR3_LOAD_EXITING | |
1508 | CPU_BASED_CR3_STORE_EXITING)); | |
1509 | vcpu->arch.cr0 = cr0; | |
1510 | vmx_set_cr4(vcpu, vcpu->arch.cr4); | |
1511 | if (!(vcpu->arch.cr0 & X86_CR0_WP)) | |
1512 | *hw_cr0 &= ~X86_CR0_WP; | |
1513 | } | |
1514 | } | |
1515 | ||
1516 | static void ept_update_paging_mode_cr4(unsigned long *hw_cr4, | |
1517 | struct kvm_vcpu *vcpu) | |
1518 | { | |
1519 | if (!is_paging(vcpu)) { | |
1520 | *hw_cr4 &= ~X86_CR4_PAE; | |
1521 | *hw_cr4 |= X86_CR4_PSE; | |
1522 | } else if (!(vcpu->arch.cr4 & X86_CR4_PAE)) | |
1523 | *hw_cr4 &= ~X86_CR4_PAE; | |
1524 | } | |
1525 | ||
6aa8b732 AK |
1526 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1527 | { | |
1439442c SY |
1528 | unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | |
1529 | KVM_VM_CR0_ALWAYS_ON; | |
1530 | ||
5fd86fcf AK |
1531 | vmx_fpu_deactivate(vcpu); |
1532 | ||
ad312c7c | 1533 | if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1534 | enter_pmode(vcpu); |
1535 | ||
ad312c7c | 1536 | if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1537 | enter_rmode(vcpu); |
1538 | ||
05b3e0c2 | 1539 | #ifdef CONFIG_X86_64 |
ad312c7c | 1540 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 1541 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 1542 | enter_lmode(vcpu); |
707d92fa | 1543 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
1544 | exit_lmode(vcpu); |
1545 | } | |
1546 | #endif | |
1547 | ||
1439442c SY |
1548 | if (vm_need_ept()) |
1549 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); | |
1550 | ||
6aa8b732 | 1551 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 1552 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 1553 | vcpu->arch.cr0 = cr0; |
5fd86fcf | 1554 | |
707d92fa | 1555 | if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE)) |
5fd86fcf | 1556 | vmx_fpu_activate(vcpu); |
6aa8b732 AK |
1557 | } |
1558 | ||
1439442c SY |
1559 | static u64 construct_eptp(unsigned long root_hpa) |
1560 | { | |
1561 | u64 eptp; | |
1562 | ||
1563 | /* TODO write the value reading from MSR */ | |
1564 | eptp = VMX_EPT_DEFAULT_MT | | |
1565 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
1566 | eptp |= (root_hpa & PAGE_MASK); | |
1567 | ||
1568 | return eptp; | |
1569 | } | |
1570 | ||
6aa8b732 AK |
1571 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
1572 | { | |
1439442c SY |
1573 | unsigned long guest_cr3; |
1574 | u64 eptp; | |
1575 | ||
1576 | guest_cr3 = cr3; | |
1577 | if (vm_need_ept()) { | |
1578 | eptp = construct_eptp(cr3); | |
1579 | vmcs_write64(EPT_POINTER, eptp); | |
1580 | ept_sync_context(eptp); | |
1581 | ept_load_pdptrs(vcpu); | |
1582 | guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 : | |
1583 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
1584 | } | |
1585 | ||
2384d2b3 | 1586 | vmx_flush_tlb(vcpu); |
1439442c | 1587 | vmcs_writel(GUEST_CR3, guest_cr3); |
ad312c7c | 1588 | if (vcpu->arch.cr0 & X86_CR0_PE) |
5fd86fcf | 1589 | vmx_fpu_deactivate(vcpu); |
6aa8b732 AK |
1590 | } |
1591 | ||
1592 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1593 | { | |
1439442c SY |
1594 | unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ? |
1595 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1596 | ||
ad312c7c | 1597 | vcpu->arch.cr4 = cr4; |
1439442c SY |
1598 | if (vm_need_ept()) |
1599 | ept_update_paging_mode_cr4(&hw_cr4, vcpu); | |
1600 | ||
1601 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
1602 | vmcs_writel(GUEST_CR4, hw_cr4); | |
6aa8b732 AK |
1603 | } |
1604 | ||
6aa8b732 AK |
1605 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
1606 | { | |
8b9cf98c RR |
1607 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1608 | struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); | |
6aa8b732 | 1609 | |
ad312c7c | 1610 | vcpu->arch.shadow_efer = efer; |
9f62e19a JR |
1611 | if (!msr) |
1612 | return; | |
6aa8b732 AK |
1613 | if (efer & EFER_LMA) { |
1614 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1615 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
1e4e6e00 | 1616 | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1617 | msr->data = efer; |
1618 | ||
1619 | } else { | |
1620 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1621 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
1e4e6e00 | 1622 | ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1623 | |
1624 | msr->data = efer & ~EFER_LME; | |
1625 | } | |
8b9cf98c | 1626 | setup_msrs(vmx); |
6aa8b732 AK |
1627 | } |
1628 | ||
6aa8b732 AK |
1629 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
1630 | { | |
1631 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1632 | ||
1633 | return vmcs_readl(sf->base); | |
1634 | } | |
1635 | ||
1636 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
1637 | struct kvm_segment *var, int seg) | |
1638 | { | |
1639 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1640 | u32 ar; | |
1641 | ||
1642 | var->base = vmcs_readl(sf->base); | |
1643 | var->limit = vmcs_read32(sf->limit); | |
1644 | var->selector = vmcs_read16(sf->selector); | |
1645 | ar = vmcs_read32(sf->ar_bytes); | |
1646 | if (ar & AR_UNUSABLE_MASK) | |
1647 | ar = 0; | |
1648 | var->type = ar & 15; | |
1649 | var->s = (ar >> 4) & 1; | |
1650 | var->dpl = (ar >> 5) & 3; | |
1651 | var->present = (ar >> 7) & 1; | |
1652 | var->avl = (ar >> 12) & 1; | |
1653 | var->l = (ar >> 13) & 1; | |
1654 | var->db = (ar >> 14) & 1; | |
1655 | var->g = (ar >> 15) & 1; | |
1656 | var->unusable = (ar >> 16) & 1; | |
1657 | } | |
1658 | ||
2e4d2653 IE |
1659 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
1660 | { | |
1661 | struct kvm_segment kvm_seg; | |
1662 | ||
1663 | if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */ | |
1664 | return 0; | |
1665 | ||
1666 | if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */ | |
1667 | return 3; | |
1668 | ||
1669 | vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS); | |
1670 | return kvm_seg.selector & 3; | |
1671 | } | |
1672 | ||
653e3108 | 1673 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 1674 | { |
6aa8b732 AK |
1675 | u32 ar; |
1676 | ||
653e3108 | 1677 | if (var->unusable) |
6aa8b732 AK |
1678 | ar = 1 << 16; |
1679 | else { | |
1680 | ar = var->type & 15; | |
1681 | ar |= (var->s & 1) << 4; | |
1682 | ar |= (var->dpl & 3) << 5; | |
1683 | ar |= (var->present & 1) << 7; | |
1684 | ar |= (var->avl & 1) << 12; | |
1685 | ar |= (var->l & 1) << 13; | |
1686 | ar |= (var->db & 1) << 14; | |
1687 | ar |= (var->g & 1) << 15; | |
1688 | } | |
f7fbf1fd UL |
1689 | if (ar == 0) /* a 0 value means unusable */ |
1690 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
1691 | |
1692 | return ar; | |
1693 | } | |
1694 | ||
1695 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
1696 | struct kvm_segment *var, int seg) | |
1697 | { | |
1698 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1699 | u32 ar; | |
1700 | ||
ad312c7c ZX |
1701 | if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) { |
1702 | vcpu->arch.rmode.tr.selector = var->selector; | |
1703 | vcpu->arch.rmode.tr.base = var->base; | |
1704 | vcpu->arch.rmode.tr.limit = var->limit; | |
1705 | vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var); | |
653e3108 AK |
1706 | return; |
1707 | } | |
1708 | vmcs_writel(sf->base, var->base); | |
1709 | vmcs_write32(sf->limit, var->limit); | |
1710 | vmcs_write16(sf->selector, var->selector); | |
ad312c7c | 1711 | if (vcpu->arch.rmode.active && var->s) { |
653e3108 AK |
1712 | /* |
1713 | * Hack real-mode segments into vm86 compatibility. | |
1714 | */ | |
1715 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
1716 | vmcs_writel(sf->base, 0xf0000); | |
1717 | ar = 0xf3; | |
1718 | } else | |
1719 | ar = vmx_segment_access_rights(var); | |
6aa8b732 AK |
1720 | vmcs_write32(sf->ar_bytes, ar); |
1721 | } | |
1722 | ||
6aa8b732 AK |
1723 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
1724 | { | |
1725 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
1726 | ||
1727 | *db = (ar >> 14) & 1; | |
1728 | *l = (ar >> 13) & 1; | |
1729 | } | |
1730 | ||
1731 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1732 | { | |
1733 | dt->limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
1734 | dt->base = vmcs_readl(GUEST_IDTR_BASE); | |
1735 | } | |
1736 | ||
1737 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1738 | { | |
1739 | vmcs_write32(GUEST_IDTR_LIMIT, dt->limit); | |
1740 | vmcs_writel(GUEST_IDTR_BASE, dt->base); | |
1741 | } | |
1742 | ||
1743 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1744 | { | |
1745 | dt->limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
1746 | dt->base = vmcs_readl(GUEST_GDTR_BASE); | |
1747 | } | |
1748 | ||
1749 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1750 | { | |
1751 | vmcs_write32(GUEST_GDTR_LIMIT, dt->limit); | |
1752 | vmcs_writel(GUEST_GDTR_BASE, dt->base); | |
1753 | } | |
1754 | ||
648dfaa7 MG |
1755 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
1756 | { | |
1757 | struct kvm_segment var; | |
1758 | u32 ar; | |
1759 | ||
1760 | vmx_get_segment(vcpu, &var, seg); | |
1761 | ar = vmx_segment_access_rights(&var); | |
1762 | ||
1763 | if (var.base != (var.selector << 4)) | |
1764 | return false; | |
1765 | if (var.limit != 0xffff) | |
1766 | return false; | |
1767 | if (ar != 0xf3) | |
1768 | return false; | |
1769 | ||
1770 | return true; | |
1771 | } | |
1772 | ||
1773 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
1774 | { | |
1775 | struct kvm_segment cs; | |
1776 | unsigned int cs_rpl; | |
1777 | ||
1778 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
1779 | cs_rpl = cs.selector & SELECTOR_RPL_MASK; | |
1780 | ||
1781 | if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK)) | |
1782 | return false; | |
1783 | if (!cs.s) | |
1784 | return false; | |
1785 | if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) { | |
1786 | if (cs.dpl > cs_rpl) | |
1787 | return false; | |
1788 | } else if (cs.type & AR_TYPE_CODE_MASK) { | |
1789 | if (cs.dpl != cs_rpl) | |
1790 | return false; | |
1791 | } | |
1792 | if (!cs.present) | |
1793 | return false; | |
1794 | ||
1795 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
1796 | return true; | |
1797 | } | |
1798 | ||
1799 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
1800 | { | |
1801 | struct kvm_segment ss; | |
1802 | unsigned int ss_rpl; | |
1803 | ||
1804 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
1805 | ss_rpl = ss.selector & SELECTOR_RPL_MASK; | |
1806 | ||
1807 | if ((ss.type != 3) || (ss.type != 7)) | |
1808 | return false; | |
1809 | if (!ss.s) | |
1810 | return false; | |
1811 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
1812 | return false; | |
1813 | if (!ss.present) | |
1814 | return false; | |
1815 | ||
1816 | return true; | |
1817 | } | |
1818 | ||
1819 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
1820 | { | |
1821 | struct kvm_segment var; | |
1822 | unsigned int rpl; | |
1823 | ||
1824 | vmx_get_segment(vcpu, &var, seg); | |
1825 | rpl = var.selector & SELECTOR_RPL_MASK; | |
1826 | ||
1827 | if (!var.s) | |
1828 | return false; | |
1829 | if (!var.present) | |
1830 | return false; | |
1831 | if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) { | |
1832 | if (var.dpl < rpl) /* DPL < RPL */ | |
1833 | return false; | |
1834 | } | |
1835 | ||
1836 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
1837 | * rights flags | |
1838 | */ | |
1839 | return true; | |
1840 | } | |
1841 | ||
1842 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
1843 | { | |
1844 | struct kvm_segment tr; | |
1845 | ||
1846 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
1847 | ||
1848 | if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */ | |
1849 | return false; | |
1850 | if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */ | |
1851 | return false; | |
1852 | if (!tr.present) | |
1853 | return false; | |
1854 | ||
1855 | return true; | |
1856 | } | |
1857 | ||
1858 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
1859 | { | |
1860 | struct kvm_segment ldtr; | |
1861 | ||
1862 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
1863 | ||
1864 | if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */ | |
1865 | return false; | |
1866 | if (ldtr.type != 2) | |
1867 | return false; | |
1868 | if (!ldtr.present) | |
1869 | return false; | |
1870 | ||
1871 | return true; | |
1872 | } | |
1873 | ||
1874 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
1875 | { | |
1876 | struct kvm_segment cs, ss; | |
1877 | ||
1878 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
1879 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
1880 | ||
1881 | return ((cs.selector & SELECTOR_RPL_MASK) == | |
1882 | (ss.selector & SELECTOR_RPL_MASK)); | |
1883 | } | |
1884 | ||
1885 | /* | |
1886 | * Check if guest state is valid. Returns true if valid, false if | |
1887 | * not. | |
1888 | * We assume that registers are always usable | |
1889 | */ | |
1890 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
1891 | { | |
1892 | /* real mode guest state checks */ | |
1893 | if (!(vcpu->arch.cr0 & X86_CR0_PE)) { | |
1894 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) | |
1895 | return false; | |
1896 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
1897 | return false; | |
1898 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
1899 | return false; | |
1900 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
1901 | return false; | |
1902 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
1903 | return false; | |
1904 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
1905 | return false; | |
1906 | } else { | |
1907 | /* protected mode guest state checks */ | |
1908 | if (!cs_ss_rpl_check(vcpu)) | |
1909 | return false; | |
1910 | if (!code_segment_valid(vcpu)) | |
1911 | return false; | |
1912 | if (!stack_segment_valid(vcpu)) | |
1913 | return false; | |
1914 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
1915 | return false; | |
1916 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
1917 | return false; | |
1918 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
1919 | return false; | |
1920 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
1921 | return false; | |
1922 | if (!tr_valid(vcpu)) | |
1923 | return false; | |
1924 | if (!ldtr_valid(vcpu)) | |
1925 | return false; | |
1926 | } | |
1927 | /* TODO: | |
1928 | * - Add checks on RIP | |
1929 | * - Add checks on RFLAGS | |
1930 | */ | |
1931 | ||
1932 | return true; | |
1933 | } | |
1934 | ||
d77c26fc | 1935 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 1936 | { |
6aa8b732 | 1937 | gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT; |
195aefde | 1938 | u16 data = 0; |
10589a46 | 1939 | int ret = 0; |
195aefde | 1940 | int r; |
6aa8b732 | 1941 | |
195aefde IE |
1942 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1943 | if (r < 0) | |
10589a46 | 1944 | goto out; |
195aefde | 1945 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
1946 | r = kvm_write_guest_page(kvm, fn++, &data, |
1947 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 1948 | if (r < 0) |
10589a46 | 1949 | goto out; |
195aefde IE |
1950 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
1951 | if (r < 0) | |
10589a46 | 1952 | goto out; |
195aefde IE |
1953 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1954 | if (r < 0) | |
10589a46 | 1955 | goto out; |
195aefde | 1956 | data = ~0; |
10589a46 MT |
1957 | r = kvm_write_guest_page(kvm, fn, &data, |
1958 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
1959 | sizeof(u8)); | |
195aefde | 1960 | if (r < 0) |
10589a46 MT |
1961 | goto out; |
1962 | ||
1963 | ret = 1; | |
1964 | out: | |
10589a46 | 1965 | return ret; |
6aa8b732 AK |
1966 | } |
1967 | ||
b7ebfb05 SY |
1968 | static int init_rmode_identity_map(struct kvm *kvm) |
1969 | { | |
1970 | int i, r, ret; | |
1971 | pfn_t identity_map_pfn; | |
1972 | u32 tmp; | |
1973 | ||
1974 | if (!vm_need_ept()) | |
1975 | return 1; | |
1976 | if (unlikely(!kvm->arch.ept_identity_pagetable)) { | |
1977 | printk(KERN_ERR "EPT: identity-mapping pagetable " | |
1978 | "haven't been allocated!\n"); | |
1979 | return 0; | |
1980 | } | |
1981 | if (likely(kvm->arch.ept_identity_pagetable_done)) | |
1982 | return 1; | |
1983 | ret = 0; | |
1984 | identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT; | |
1985 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); | |
1986 | if (r < 0) | |
1987 | goto out; | |
1988 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
1989 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
1990 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
1991 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
1992 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
1993 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
1994 | if (r < 0) | |
1995 | goto out; | |
1996 | } | |
1997 | kvm->arch.ept_identity_pagetable_done = true; | |
1998 | ret = 1; | |
1999 | out: | |
2000 | return ret; | |
2001 | } | |
2002 | ||
6aa8b732 AK |
2003 | static void seg_setup(int seg) |
2004 | { | |
2005 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
2006 | ||
2007 | vmcs_write16(sf->selector, 0); | |
2008 | vmcs_writel(sf->base, 0); | |
2009 | vmcs_write32(sf->limit, 0xffff); | |
a16b20da | 2010 | vmcs_write32(sf->ar_bytes, 0xf3); |
6aa8b732 AK |
2011 | } |
2012 | ||
f78e0e2e SY |
2013 | static int alloc_apic_access_page(struct kvm *kvm) |
2014 | { | |
2015 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2016 | int r = 0; | |
2017 | ||
72dc67a6 | 2018 | down_write(&kvm->slots_lock); |
bfc6d222 | 2019 | if (kvm->arch.apic_access_page) |
f78e0e2e SY |
2020 | goto out; |
2021 | kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
2022 | kvm_userspace_mem.flags = 0; | |
2023 | kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL; | |
2024 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
2025 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2026 | if (r) | |
2027 | goto out; | |
72dc67a6 | 2028 | |
bfc6d222 | 2029 | kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00); |
f78e0e2e | 2030 | out: |
72dc67a6 | 2031 | up_write(&kvm->slots_lock); |
f78e0e2e SY |
2032 | return r; |
2033 | } | |
2034 | ||
b7ebfb05 SY |
2035 | static int alloc_identity_pagetable(struct kvm *kvm) |
2036 | { | |
2037 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2038 | int r = 0; | |
2039 | ||
2040 | down_write(&kvm->slots_lock); | |
2041 | if (kvm->arch.ept_identity_pagetable) | |
2042 | goto out; | |
2043 | kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
2044 | kvm_userspace_mem.flags = 0; | |
2045 | kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
2046 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
2047 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2048 | if (r) | |
2049 | goto out; | |
2050 | ||
b7ebfb05 SY |
2051 | kvm->arch.ept_identity_pagetable = gfn_to_page(kvm, |
2052 | VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT); | |
b7ebfb05 SY |
2053 | out: |
2054 | up_write(&kvm->slots_lock); | |
2055 | return r; | |
2056 | } | |
2057 | ||
2384d2b3 SY |
2058 | static void allocate_vpid(struct vcpu_vmx *vmx) |
2059 | { | |
2060 | int vpid; | |
2061 | ||
2062 | vmx->vpid = 0; | |
2063 | if (!enable_vpid || !cpu_has_vmx_vpid()) | |
2064 | return; | |
2065 | spin_lock(&vmx_vpid_lock); | |
2066 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
2067 | if (vpid < VMX_NR_VPIDS) { | |
2068 | vmx->vpid = vpid; | |
2069 | __set_bit(vpid, vmx_vpid_bitmap); | |
2070 | } | |
2071 | spin_unlock(&vmx_vpid_lock); | |
2072 | } | |
2073 | ||
8b2cf73c | 2074 | static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr) |
25c5f225 SY |
2075 | { |
2076 | void *va; | |
2077 | ||
2078 | if (!cpu_has_vmx_msr_bitmap()) | |
2079 | return; | |
2080 | ||
2081 | /* | |
2082 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
2083 | * have the write-low and read-high bitmap offsets the wrong way round. | |
2084 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
2085 | */ | |
2086 | va = kmap(msr_bitmap); | |
2087 | if (msr <= 0x1fff) { | |
2088 | __clear_bit(msr, va + 0x000); /* read-low */ | |
2089 | __clear_bit(msr, va + 0x800); /* write-low */ | |
2090 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
2091 | msr &= 0x1fff; | |
2092 | __clear_bit(msr, va + 0x400); /* read-high */ | |
2093 | __clear_bit(msr, va + 0xc00); /* write-high */ | |
2094 | } | |
2095 | kunmap(msr_bitmap); | |
2096 | } | |
2097 | ||
6aa8b732 AK |
2098 | /* |
2099 | * Sets up the vmcs for emulated real mode. | |
2100 | */ | |
8b9cf98c | 2101 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 2102 | { |
468d472f | 2103 | u32 host_sysenter_cs, msr_low, msr_high; |
6aa8b732 | 2104 | u32 junk; |
468d472f | 2105 | u64 host_pat; |
6aa8b732 AK |
2106 | unsigned long a; |
2107 | struct descriptor_table dt; | |
2108 | int i; | |
cd2276a7 | 2109 | unsigned long kvm_vmx_return; |
6e5d865c | 2110 | u32 exec_control; |
6aa8b732 | 2111 | |
6aa8b732 | 2112 | /* I/O */ |
fdef3ad1 HQ |
2113 | vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a)); |
2114 | vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b)); | |
6aa8b732 | 2115 | |
25c5f225 SY |
2116 | if (cpu_has_vmx_msr_bitmap()) |
2117 | vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap)); | |
2118 | ||
6aa8b732 AK |
2119 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
2120 | ||
6aa8b732 | 2121 | /* Control */ |
1c3d14fe YS |
2122 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, |
2123 | vmcs_config.pin_based_exec_ctrl); | |
6e5d865c YS |
2124 | |
2125 | exec_control = vmcs_config.cpu_based_exec_ctrl; | |
2126 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { | |
2127 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
2128 | #ifdef CONFIG_X86_64 | |
2129 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
2130 | CPU_BASED_CR8_LOAD_EXITING; | |
2131 | #endif | |
2132 | } | |
d56f546d SY |
2133 | if (!vm_need_ept()) |
2134 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
83dbc83a MT |
2135 | CPU_BASED_CR3_LOAD_EXITING | |
2136 | CPU_BASED_INVLPG_EXITING; | |
6e5d865c | 2137 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); |
6aa8b732 | 2138 | |
83ff3b9d SY |
2139 | if (cpu_has_secondary_exec_ctrls()) { |
2140 | exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
2141 | if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2142 | exec_control &= | |
2143 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
2384d2b3 SY |
2144 | if (vmx->vpid == 0) |
2145 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
d56f546d SY |
2146 | if (!vm_need_ept()) |
2147 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
83ff3b9d SY |
2148 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
2149 | } | |
f78e0e2e | 2150 | |
c7addb90 AK |
2151 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf); |
2152 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf); | |
6aa8b732 AK |
2153 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
2154 | ||
2155 | vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */ | |
2156 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ | |
2157 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
2158 | ||
2159 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
2160 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
2161 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
d6e88aec AK |
2162 | vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */ |
2163 | vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */ | |
6aa8b732 | 2164 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
05b3e0c2 | 2165 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2166 | rdmsrl(MSR_FS_BASE, a); |
2167 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
2168 | rdmsrl(MSR_GS_BASE, a); | |
2169 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
2170 | #else | |
2171 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
2172 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
2173 | #endif | |
2174 | ||
2175 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
2176 | ||
d6e88aec | 2177 | kvm_get_idt(&dt); |
6aa8b732 AK |
2178 | vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */ |
2179 | ||
d77c26fc | 2180 | asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); |
cd2276a7 | 2181 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ |
2cc51560 ED |
2182 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
2183 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
2184 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); | |
6aa8b732 AK |
2185 | |
2186 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
2187 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
2188 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
2189 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
2190 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
2191 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
2192 | ||
468d472f SY |
2193 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { |
2194 | rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high); | |
2195 | host_pat = msr_low | ((u64) msr_high << 32); | |
2196 | vmcs_write64(HOST_IA32_PAT, host_pat); | |
2197 | } | |
2198 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
2199 | rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high); | |
2200 | host_pat = msr_low | ((u64) msr_high << 32); | |
2201 | /* Write the default value follow host pat */ | |
2202 | vmcs_write64(GUEST_IA32_PAT, host_pat); | |
2203 | /* Keep arch.pat sync with GUEST_IA32_PAT */ | |
2204 | vmx->vcpu.arch.pat = host_pat; | |
2205 | } | |
2206 | ||
6aa8b732 AK |
2207 | for (i = 0; i < NR_VMX_MSR; ++i) { |
2208 | u32 index = vmx_msr_index[i]; | |
2209 | u32 data_low, data_high; | |
2210 | u64 data; | |
a2fa3e9f | 2211 | int j = vmx->nmsrs; |
6aa8b732 AK |
2212 | |
2213 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
2214 | continue; | |
432bd6cb AK |
2215 | if (wrmsr_safe(index, data_low, data_high) < 0) |
2216 | continue; | |
6aa8b732 | 2217 | data = data_low | ((u64)data_high << 32); |
a2fa3e9f GH |
2218 | vmx->host_msrs[j].index = index; |
2219 | vmx->host_msrs[j].reserved = 0; | |
2220 | vmx->host_msrs[j].data = data; | |
2221 | vmx->guest_msrs[j] = vmx->host_msrs[j]; | |
2222 | ++vmx->nmsrs; | |
6aa8b732 | 2223 | } |
6aa8b732 | 2224 | |
1c3d14fe | 2225 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
2226 | |
2227 | /* 22.2.1, 20.8.1 */ | |
1c3d14fe YS |
2228 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); |
2229 | ||
e00c8cf2 AK |
2230 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
2231 | vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK); | |
2232 | ||
f78e0e2e | 2233 | |
e00c8cf2 AK |
2234 | return 0; |
2235 | } | |
2236 | ||
b7ebfb05 SY |
2237 | static int init_rmode(struct kvm *kvm) |
2238 | { | |
2239 | if (!init_rmode_tss(kvm)) | |
2240 | return 0; | |
2241 | if (!init_rmode_identity_map(kvm)) | |
2242 | return 0; | |
2243 | return 1; | |
2244 | } | |
2245 | ||
e00c8cf2 AK |
2246 | static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) |
2247 | { | |
2248 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2249 | u64 msr; | |
2250 | int ret; | |
2251 | ||
5fdbf976 | 2252 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)); |
3200f405 | 2253 | down_read(&vcpu->kvm->slots_lock); |
b7ebfb05 | 2254 | if (!init_rmode(vmx->vcpu.kvm)) { |
e00c8cf2 AK |
2255 | ret = -ENOMEM; |
2256 | goto out; | |
2257 | } | |
2258 | ||
ad312c7c | 2259 | vmx->vcpu.arch.rmode.active = 0; |
e00c8cf2 | 2260 | |
3b86cd99 JK |
2261 | vmx->soft_vnmi_blocked = 0; |
2262 | ||
ad312c7c | 2263 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
2d3ad1f4 | 2264 | kvm_set_cr8(&vmx->vcpu, 0); |
e00c8cf2 AK |
2265 | msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
2266 | if (vmx->vcpu.vcpu_id == 0) | |
2267 | msr |= MSR_IA32_APICBASE_BSP; | |
2268 | kvm_set_apic_base(&vmx->vcpu, msr); | |
2269 | ||
2270 | fx_init(&vmx->vcpu); | |
2271 | ||
5706be0d | 2272 | seg_setup(VCPU_SREG_CS); |
e00c8cf2 AK |
2273 | /* |
2274 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
2275 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
2276 | */ | |
2277 | if (vmx->vcpu.vcpu_id == 0) { | |
2278 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); | |
2279 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
2280 | } else { | |
ad312c7c ZX |
2281 | vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8); |
2282 | vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12); | |
e00c8cf2 | 2283 | } |
e00c8cf2 AK |
2284 | |
2285 | seg_setup(VCPU_SREG_DS); | |
2286 | seg_setup(VCPU_SREG_ES); | |
2287 | seg_setup(VCPU_SREG_FS); | |
2288 | seg_setup(VCPU_SREG_GS); | |
2289 | seg_setup(VCPU_SREG_SS); | |
2290 | ||
2291 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
2292 | vmcs_writel(GUEST_TR_BASE, 0); | |
2293 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
2294 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
2295 | ||
2296 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
2297 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
2298 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
2299 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
2300 | ||
2301 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
2302 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
2303 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
2304 | ||
2305 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
2306 | if (vmx->vcpu.vcpu_id == 0) | |
5fdbf976 | 2307 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 2308 | else |
5fdbf976 MT |
2309 | kvm_rip_write(vcpu, 0); |
2310 | kvm_register_write(vcpu, VCPU_REGS_RSP, 0); | |
e00c8cf2 AK |
2311 | |
2312 | /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */ | |
2313 | vmcs_writel(GUEST_DR7, 0x400); | |
2314 | ||
2315 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
2316 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
2317 | ||
2318 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
2319 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
2320 | ||
2321 | vmcs_write32(GUEST_ACTIVITY_STATE, 0); | |
2322 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); | |
2323 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
2324 | ||
2325 | guest_write_tsc(0); | |
2326 | ||
2327 | /* Special registers */ | |
2328 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
2329 | ||
2330 | setup_msrs(vmx); | |
2331 | ||
6aa8b732 AK |
2332 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
2333 | ||
f78e0e2e SY |
2334 | if (cpu_has_vmx_tpr_shadow()) { |
2335 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); | |
2336 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
2337 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
ad312c7c | 2338 | page_to_phys(vmx->vcpu.arch.apic->regs_page)); |
f78e0e2e SY |
2339 | vmcs_write32(TPR_THRESHOLD, 0); |
2340 | } | |
2341 | ||
2342 | if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2343 | vmcs_write64(APIC_ACCESS_ADDR, | |
bfc6d222 | 2344 | page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); |
6aa8b732 | 2345 | |
2384d2b3 SY |
2346 | if (vmx->vpid != 0) |
2347 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
2348 | ||
ad312c7c ZX |
2349 | vmx->vcpu.arch.cr0 = 0x60000010; |
2350 | vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */ | |
8b9cf98c | 2351 | vmx_set_cr4(&vmx->vcpu, 0); |
8b9cf98c | 2352 | vmx_set_efer(&vmx->vcpu, 0); |
8b9cf98c RR |
2353 | vmx_fpu_activate(&vmx->vcpu); |
2354 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 | 2355 | |
2384d2b3 SY |
2356 | vpid_sync_vcpu_all(vmx); |
2357 | ||
3200f405 | 2358 | ret = 0; |
6aa8b732 | 2359 | |
a89a8fb9 MG |
2360 | /* HACK: Don't enable emulation on guest boot/reset */ |
2361 | vmx->emulation_required = 0; | |
2362 | ||
6aa8b732 | 2363 | out: |
3200f405 | 2364 | up_read(&vcpu->kvm->slots_lock); |
6aa8b732 AK |
2365 | return ret; |
2366 | } | |
2367 | ||
3b86cd99 JK |
2368 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
2369 | { | |
2370 | u32 cpu_based_vm_exec_control; | |
2371 | ||
2372 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2373 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
2374 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2375 | } | |
2376 | ||
2377 | static void enable_nmi_window(struct kvm_vcpu *vcpu) | |
2378 | { | |
2379 | u32 cpu_based_vm_exec_control; | |
2380 | ||
2381 | if (!cpu_has_virtual_nmis()) { | |
2382 | enable_irq_window(vcpu); | |
2383 | return; | |
2384 | } | |
2385 | ||
2386 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2387 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
2388 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2389 | } | |
2390 | ||
85f455f7 ED |
2391 | static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq) |
2392 | { | |
9c8cba37 AK |
2393 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2394 | ||
2714d1d3 FEL |
2395 | KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler); |
2396 | ||
fa89a817 | 2397 | ++vcpu->stat.irq_injections; |
ad312c7c | 2398 | if (vcpu->arch.rmode.active) { |
9c8cba37 AK |
2399 | vmx->rmode.irq.pending = true; |
2400 | vmx->rmode.irq.vector = irq; | |
5fdbf976 | 2401 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); |
9c5623e3 AK |
2402 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
2403 | irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK); | |
2404 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
5fdbf976 | 2405 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); |
85f455f7 ED |
2406 | return; |
2407 | } | |
2408 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2409 | irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
2410 | } | |
2411 | ||
f08864b4 SY |
2412 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
2413 | { | |
66a5a347 JK |
2414 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2415 | ||
3b86cd99 JK |
2416 | if (!cpu_has_virtual_nmis()) { |
2417 | /* | |
2418 | * Tracking the NMI-blocked state in software is built upon | |
2419 | * finding the next open IRQ window. This, in turn, depends on | |
2420 | * well-behaving guests: They have to keep IRQs disabled at | |
2421 | * least as long as the NMI handler runs. Otherwise we may | |
2422 | * cause NMI nesting, maybe breaking the guest. But as this is | |
2423 | * highly unlikely, we can live with the residual risk. | |
2424 | */ | |
2425 | vmx->soft_vnmi_blocked = 1; | |
2426 | vmx->vnmi_blocked_time = 0; | |
2427 | } | |
2428 | ||
487b391d | 2429 | ++vcpu->stat.nmi_injections; |
66a5a347 JK |
2430 | if (vcpu->arch.rmode.active) { |
2431 | vmx->rmode.irq.pending = true; | |
2432 | vmx->rmode.irq.vector = NMI_VECTOR; | |
2433 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); | |
2434 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2435 | NMI_VECTOR | INTR_TYPE_SOFT_INTR | | |
2436 | INTR_INFO_VALID_MASK); | |
2437 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
2438 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); | |
2439 | return; | |
2440 | } | |
f08864b4 SY |
2441 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
2442 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
2443 | } |
2444 | ||
33f089ca JK |
2445 | static void vmx_update_window_states(struct kvm_vcpu *vcpu) |
2446 | { | |
2447 | u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2448 | ||
2449 | vcpu->arch.nmi_window_open = | |
2450 | !(guest_intr & (GUEST_INTR_STATE_STI | | |
2451 | GUEST_INTR_STATE_MOV_SS | | |
2452 | GUEST_INTR_STATE_NMI)); | |
3b86cd99 JK |
2453 | if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked) |
2454 | vcpu->arch.nmi_window_open = 0; | |
33f089ca JK |
2455 | |
2456 | vcpu->arch.interrupt_window_open = | |
2457 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
2458 | !(guest_intr & (GUEST_INTR_STATE_STI | | |
2459 | GUEST_INTR_STATE_MOV_SS))); | |
2460 | } | |
2461 | ||
6aa8b732 AK |
2462 | static void kvm_do_inject_irq(struct kvm_vcpu *vcpu) |
2463 | { | |
ad312c7c ZX |
2464 | int word_index = __ffs(vcpu->arch.irq_summary); |
2465 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
2466 | int irq = word_index * BITS_PER_LONG + bit_index; |
2467 | ||
ad312c7c ZX |
2468 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
2469 | if (!vcpu->arch.irq_pending[word_index]) | |
2470 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
ecfc79c7 | 2471 | kvm_queue_interrupt(vcpu, irq); |
6aa8b732 AK |
2472 | } |
2473 | ||
f460ee43 JK |
2474 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
2475 | struct kvm_run *kvm_run) | |
2476 | { | |
2477 | vmx_update_window_states(vcpu); | |
2478 | ||
3b86cd99 JK |
2479 | if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) { |
2480 | if (vcpu->arch.nmi_window_open) { | |
2481 | vcpu->arch.nmi_pending = false; | |
2482 | vcpu->arch.nmi_injected = true; | |
2483 | } else { | |
2484 | enable_nmi_window(vcpu); | |
487b391d JK |
2485 | return; |
2486 | } | |
3b86cd99 JK |
2487 | } |
2488 | if (vcpu->arch.nmi_injected) { | |
2489 | vmx_inject_nmi(vcpu); | |
2490 | if (vcpu->arch.nmi_pending || kvm_run->request_nmi_window) | |
487b391d | 2491 | enable_nmi_window(vcpu); |
3b86cd99 JK |
2492 | else if (vcpu->arch.irq_summary |
2493 | || kvm_run->request_interrupt_window) | |
2494 | enable_irq_window(vcpu); | |
2495 | return; | |
487b391d | 2496 | } |
3b86cd99 JK |
2497 | if (!vcpu->arch.nmi_window_open || kvm_run->request_nmi_window) |
2498 | enable_nmi_window(vcpu); | |
487b391d | 2499 | |
f460ee43 JK |
2500 | if (vcpu->arch.interrupt_window_open) { |
2501 | if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending) | |
2502 | kvm_do_inject_irq(vcpu); | |
2503 | ||
2504 | if (vcpu->arch.interrupt.pending) | |
2505 | vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr); | |
2506 | } | |
ad312c7c ZX |
2507 | if (!vcpu->arch.interrupt_window_open && |
2508 | (vcpu->arch.irq_summary || kvm_run->request_interrupt_window)) | |
f460ee43 | 2509 | enable_irq_window(vcpu); |
6aa8b732 AK |
2510 | } |
2511 | ||
cbc94022 IE |
2512 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
2513 | { | |
2514 | int ret; | |
2515 | struct kvm_userspace_memory_region tss_mem = { | |
6fe63979 | 2516 | .slot = TSS_PRIVATE_MEMSLOT, |
cbc94022 IE |
2517 | .guest_phys_addr = addr, |
2518 | .memory_size = PAGE_SIZE * 3, | |
2519 | .flags = 0, | |
2520 | }; | |
2521 | ||
2522 | ret = kvm_set_memory_region(kvm, &tss_mem, 0); | |
2523 | if (ret) | |
2524 | return ret; | |
bfc6d222 | 2525 | kvm->arch.tss_addr = addr; |
cbc94022 IE |
2526 | return 0; |
2527 | } | |
2528 | ||
6aa8b732 AK |
2529 | static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu) |
2530 | { | |
2531 | struct kvm_guest_debug *dbg = &vcpu->guest_debug; | |
2532 | ||
2533 | set_debugreg(dbg->bp[0], 0); | |
2534 | set_debugreg(dbg->bp[1], 1); | |
2535 | set_debugreg(dbg->bp[2], 2); | |
2536 | set_debugreg(dbg->bp[3], 3); | |
2537 | ||
2538 | if (dbg->singlestep) { | |
2539 | unsigned long flags; | |
2540 | ||
2541 | flags = vmcs_readl(GUEST_RFLAGS); | |
2542 | flags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
2543 | vmcs_writel(GUEST_RFLAGS, flags); | |
2544 | } | |
2545 | } | |
2546 | ||
2547 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
2548 | int vec, u32 err_code) | |
2549 | { | |
b3f37707 NK |
2550 | /* |
2551 | * Instruction with address size override prefix opcode 0x67 | |
2552 | * Cause the #SS fault with 0 error code in VM86 mode. | |
2553 | */ | |
2554 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
3427318f | 2555 | if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE) |
6aa8b732 | 2556 | return 1; |
77ab6db0 JK |
2557 | /* |
2558 | * Forward all other exceptions that are valid in real mode. | |
2559 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
2560 | * the required debugging infrastructure rework. | |
2561 | */ | |
2562 | switch (vec) { | |
2563 | case DE_VECTOR: | |
2564 | case DB_VECTOR: | |
2565 | case BP_VECTOR: | |
2566 | case OF_VECTOR: | |
2567 | case BR_VECTOR: | |
2568 | case UD_VECTOR: | |
2569 | case DF_VECTOR: | |
2570 | case SS_VECTOR: | |
2571 | case GP_VECTOR: | |
2572 | case MF_VECTOR: | |
2573 | kvm_queue_exception(vcpu, vec); | |
2574 | return 1; | |
2575 | } | |
6aa8b732 AK |
2576 | return 0; |
2577 | } | |
2578 | ||
2579 | static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2580 | { | |
1155f76a | 2581 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
2582 | u32 intr_info, error_code; |
2583 | unsigned long cr2, rip; | |
2584 | u32 vect_info; | |
2585 | enum emulation_result er; | |
2586 | ||
1155f76a | 2587 | vect_info = vmx->idt_vectoring_info; |
6aa8b732 AK |
2588 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
2589 | ||
2590 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
d77c26fc | 2591 | !is_page_fault(intr_info)) |
6aa8b732 | 2592 | printk(KERN_ERR "%s: unexpected, vectoring info 0x%x " |
b8688d51 | 2593 | "intr info 0x%x\n", __func__, vect_info, intr_info); |
6aa8b732 | 2594 | |
85f455f7 | 2595 | if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) { |
6aa8b732 | 2596 | int irq = vect_info & VECTORING_INFO_VECTOR_MASK; |
ad312c7c ZX |
2597 | set_bit(irq, vcpu->arch.irq_pending); |
2598 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
2599 | } |
2600 | ||
e4a41889 | 2601 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR) |
1b6269db | 2602 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc AL |
2603 | |
2604 | if (is_no_device(intr_info)) { | |
5fd86fcf | 2605 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
2606 | return 1; |
2607 | } | |
2608 | ||
7aa81cc0 | 2609 | if (is_invalid_opcode(intr_info)) { |
571008da | 2610 | er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 2611 | if (er != EMULATE_DONE) |
7ee5d940 | 2612 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
2613 | return 1; |
2614 | } | |
2615 | ||
6aa8b732 | 2616 | error_code = 0; |
5fdbf976 | 2617 | rip = kvm_rip_read(vcpu); |
2e11384c | 2618 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 AK |
2619 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
2620 | if (is_page_fault(intr_info)) { | |
1439442c SY |
2621 | /* EPT won't cause page fault directly */ |
2622 | if (vm_need_ept()) | |
2623 | BUG(); | |
6aa8b732 | 2624 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
2714d1d3 FEL |
2625 | KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2, |
2626 | (u32)((u64)cr2 >> 32), handler); | |
f7d9238f | 2627 | if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending) |
577bdc49 | 2628 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
3067714c | 2629 | return kvm_mmu_page_fault(vcpu, cr2, error_code); |
6aa8b732 AK |
2630 | } |
2631 | ||
ad312c7c | 2632 | if (vcpu->arch.rmode.active && |
6aa8b732 | 2633 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, |
72d6e5a0 | 2634 | error_code)) { |
ad312c7c ZX |
2635 | if (vcpu->arch.halt_request) { |
2636 | vcpu->arch.halt_request = 0; | |
72d6e5a0 AK |
2637 | return kvm_emulate_halt(vcpu); |
2638 | } | |
6aa8b732 | 2639 | return 1; |
72d6e5a0 | 2640 | } |
6aa8b732 | 2641 | |
d77c26fc MD |
2642 | if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == |
2643 | (INTR_TYPE_EXCEPTION | 1)) { | |
6aa8b732 AK |
2644 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2645 | return 0; | |
2646 | } | |
2647 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; | |
2648 | kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK; | |
2649 | kvm_run->ex.error_code = error_code; | |
2650 | return 0; | |
2651 | } | |
2652 | ||
2653 | static int handle_external_interrupt(struct kvm_vcpu *vcpu, | |
2654 | struct kvm_run *kvm_run) | |
2655 | { | |
1165f5fe | 2656 | ++vcpu->stat.irq_exits; |
2714d1d3 | 2657 | KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler); |
6aa8b732 AK |
2658 | return 1; |
2659 | } | |
2660 | ||
988ad74f AK |
2661 | static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2662 | { | |
2663 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2664 | return 0; | |
2665 | } | |
6aa8b732 | 2666 | |
6aa8b732 AK |
2667 | static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2668 | { | |
bfdaab09 | 2669 | unsigned long exit_qualification; |
039576c0 AK |
2670 | int size, down, in, string, rep; |
2671 | unsigned port; | |
6aa8b732 | 2672 | |
1165f5fe | 2673 | ++vcpu->stat.io_exits; |
bfdaab09 | 2674 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 2675 | string = (exit_qualification & 16) != 0; |
e70669ab LV |
2676 | |
2677 | if (string) { | |
3427318f LV |
2678 | if (emulate_instruction(vcpu, |
2679 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
2680 | return 0; |
2681 | return 1; | |
2682 | } | |
2683 | ||
2684 | size = (exit_qualification & 7) + 1; | |
2685 | in = (exit_qualification & 8) != 0; | |
039576c0 | 2686 | down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0; |
039576c0 AK |
2687 | rep = (exit_qualification & 32) != 0; |
2688 | port = exit_qualification >> 16; | |
e70669ab | 2689 | |
3090dd73 | 2690 | return kvm_emulate_pio(vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
2691 | } |
2692 | ||
102d8325 IM |
2693 | static void |
2694 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
2695 | { | |
2696 | /* | |
2697 | * Patch in the VMCALL instruction: | |
2698 | */ | |
2699 | hypercall[0] = 0x0f; | |
2700 | hypercall[1] = 0x01; | |
2701 | hypercall[2] = 0xc1; | |
102d8325 IM |
2702 | } |
2703 | ||
6aa8b732 AK |
2704 | static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2705 | { | |
bfdaab09 | 2706 | unsigned long exit_qualification; |
6aa8b732 AK |
2707 | int cr; |
2708 | int reg; | |
2709 | ||
bfdaab09 | 2710 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2711 | cr = exit_qualification & 15; |
2712 | reg = (exit_qualification >> 8) & 15; | |
2713 | switch ((exit_qualification >> 4) & 3) { | |
2714 | case 0: /* mov to cr */ | |
5fdbf976 MT |
2715 | KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, |
2716 | (u32)kvm_register_read(vcpu, reg), | |
2717 | (u32)((u64)kvm_register_read(vcpu, reg) >> 32), | |
2718 | handler); | |
6aa8b732 AK |
2719 | switch (cr) { |
2720 | case 0: | |
5fdbf976 | 2721 | kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 AK |
2722 | skip_emulated_instruction(vcpu); |
2723 | return 1; | |
2724 | case 3: | |
5fdbf976 | 2725 | kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 AK |
2726 | skip_emulated_instruction(vcpu); |
2727 | return 1; | |
2728 | case 4: | |
5fdbf976 | 2729 | kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 AK |
2730 | skip_emulated_instruction(vcpu); |
2731 | return 1; | |
2732 | case 8: | |
5fdbf976 | 2733 | kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 | 2734 | skip_emulated_instruction(vcpu); |
e5314067 AK |
2735 | if (irqchip_in_kernel(vcpu->kvm)) |
2736 | return 1; | |
253abdee YS |
2737 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2738 | return 0; | |
6aa8b732 AK |
2739 | }; |
2740 | break; | |
25c4c276 | 2741 | case 2: /* clts */ |
5fd86fcf | 2742 | vmx_fpu_deactivate(vcpu); |
ad312c7c ZX |
2743 | vcpu->arch.cr0 &= ~X86_CR0_TS; |
2744 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf | 2745 | vmx_fpu_activate(vcpu); |
2714d1d3 | 2746 | KVMTRACE_0D(CLTS, vcpu, handler); |
25c4c276 AL |
2747 | skip_emulated_instruction(vcpu); |
2748 | return 1; | |
6aa8b732 AK |
2749 | case 1: /*mov from cr*/ |
2750 | switch (cr) { | |
2751 | case 3: | |
5fdbf976 | 2752 | kvm_register_write(vcpu, reg, vcpu->arch.cr3); |
2714d1d3 | 2753 | KVMTRACE_3D(CR_READ, vcpu, (u32)cr, |
5fdbf976 MT |
2754 | (u32)kvm_register_read(vcpu, reg), |
2755 | (u32)((u64)kvm_register_read(vcpu, reg) >> 32), | |
2714d1d3 | 2756 | handler); |
6aa8b732 AK |
2757 | skip_emulated_instruction(vcpu); |
2758 | return 1; | |
2759 | case 8: | |
5fdbf976 | 2760 | kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu)); |
2714d1d3 | 2761 | KVMTRACE_2D(CR_READ, vcpu, (u32)cr, |
5fdbf976 | 2762 | (u32)kvm_register_read(vcpu, reg), handler); |
6aa8b732 AK |
2763 | skip_emulated_instruction(vcpu); |
2764 | return 1; | |
2765 | } | |
2766 | break; | |
2767 | case 3: /* lmsw */ | |
2d3ad1f4 | 2768 | kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f); |
6aa8b732 AK |
2769 | |
2770 | skip_emulated_instruction(vcpu); | |
2771 | return 1; | |
2772 | default: | |
2773 | break; | |
2774 | } | |
2775 | kvm_run->exit_reason = 0; | |
f0242478 | 2776 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
2777 | (int)(exit_qualification >> 4) & 3, cr); |
2778 | return 0; | |
2779 | } | |
2780 | ||
2781 | static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2782 | { | |
bfdaab09 | 2783 | unsigned long exit_qualification; |
6aa8b732 AK |
2784 | unsigned long val; |
2785 | int dr, reg; | |
2786 | ||
2787 | /* | |
2788 | * FIXME: this code assumes the host is debugging the guest. | |
2789 | * need to deal with guest debugging itself too. | |
2790 | */ | |
bfdaab09 | 2791 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2792 | dr = exit_qualification & 7; |
2793 | reg = (exit_qualification >> 8) & 15; | |
6aa8b732 AK |
2794 | if (exit_qualification & 16) { |
2795 | /* mov from dr */ | |
2796 | switch (dr) { | |
2797 | case 6: | |
2798 | val = 0xffff0ff0; | |
2799 | break; | |
2800 | case 7: | |
2801 | val = 0x400; | |
2802 | break; | |
2803 | default: | |
2804 | val = 0; | |
2805 | } | |
5fdbf976 | 2806 | kvm_register_write(vcpu, reg, val); |
2714d1d3 | 2807 | KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler); |
6aa8b732 AK |
2808 | } else { |
2809 | /* mov to dr */ | |
2810 | } | |
6aa8b732 AK |
2811 | skip_emulated_instruction(vcpu); |
2812 | return 1; | |
2813 | } | |
2814 | ||
2815 | static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2816 | { | |
06465c5a AK |
2817 | kvm_emulate_cpuid(vcpu); |
2818 | return 1; | |
6aa8b732 AK |
2819 | } |
2820 | ||
2821 | static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2822 | { | |
ad312c7c | 2823 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2824 | u64 data; |
2825 | ||
2826 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
c1a5d4f9 | 2827 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
2828 | return 1; |
2829 | } | |
2830 | ||
2714d1d3 FEL |
2831 | KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32), |
2832 | handler); | |
2833 | ||
6aa8b732 | 2834 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
ad312c7c ZX |
2835 | vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u; |
2836 | vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
6aa8b732 AK |
2837 | skip_emulated_instruction(vcpu); |
2838 | return 1; | |
2839 | } | |
2840 | ||
2841 | static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2842 | { | |
ad312c7c ZX |
2843 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
2844 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
2845 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 2846 | |
2714d1d3 FEL |
2847 | KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32), |
2848 | handler); | |
2849 | ||
6aa8b732 | 2850 | if (vmx_set_msr(vcpu, ecx, data) != 0) { |
c1a5d4f9 | 2851 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
2852 | return 1; |
2853 | } | |
2854 | ||
2855 | skip_emulated_instruction(vcpu); | |
2856 | return 1; | |
2857 | } | |
2858 | ||
6e5d865c YS |
2859 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu, |
2860 | struct kvm_run *kvm_run) | |
2861 | { | |
2862 | return 1; | |
2863 | } | |
2864 | ||
6aa8b732 AK |
2865 | static int handle_interrupt_window(struct kvm_vcpu *vcpu, |
2866 | struct kvm_run *kvm_run) | |
2867 | { | |
85f455f7 ED |
2868 | u32 cpu_based_vm_exec_control; |
2869 | ||
2870 | /* clear pending irq */ | |
2871 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2872 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
2873 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 FEL |
2874 | |
2875 | KVMTRACE_0D(PEND_INTR, vcpu, handler); | |
a26bf12a | 2876 | ++vcpu->stat.irq_window_exits; |
2714d1d3 | 2877 | |
c1150d8c DL |
2878 | /* |
2879 | * If the user space waits to inject interrupts, exit as soon as | |
2880 | * possible | |
2881 | */ | |
2882 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 2883 | !vcpu->arch.irq_summary) { |
c1150d8c | 2884 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
c1150d8c DL |
2885 | return 0; |
2886 | } | |
6aa8b732 AK |
2887 | return 1; |
2888 | } | |
2889 | ||
2890 | static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2891 | { | |
2892 | skip_emulated_instruction(vcpu); | |
d3bef15f | 2893 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
2894 | } |
2895 | ||
c21415e8 IM |
2896 | static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2897 | { | |
510043da | 2898 | skip_emulated_instruction(vcpu); |
7aa81cc0 AL |
2899 | kvm_emulate_hypercall(vcpu); |
2900 | return 1; | |
c21415e8 IM |
2901 | } |
2902 | ||
a7052897 MT |
2903 | static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2904 | { | |
2905 | u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2906 | ||
2907 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
2908 | skip_emulated_instruction(vcpu); | |
2909 | return 1; | |
2910 | } | |
2911 | ||
e5edaa01 ED |
2912 | static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2913 | { | |
2914 | skip_emulated_instruction(vcpu); | |
2915 | /* TODO: Add support for VT-d/pass-through device */ | |
2916 | return 1; | |
2917 | } | |
2918 | ||
f78e0e2e SY |
2919 | static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2920 | { | |
2921 | u64 exit_qualification; | |
2922 | enum emulation_result er; | |
2923 | unsigned long offset; | |
2924 | ||
2925 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2926 | offset = exit_qualification & 0xffful; | |
2927 | ||
2928 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
2929 | ||
2930 | if (er != EMULATE_DONE) { | |
2931 | printk(KERN_ERR | |
2932 | "Fail to handle apic access vmexit! Offset is 0x%lx\n", | |
2933 | offset); | |
2934 | return -ENOTSUPP; | |
2935 | } | |
2936 | return 1; | |
2937 | } | |
2938 | ||
37817f29 IE |
2939 | static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2940 | { | |
60637aac | 2941 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 IE |
2942 | unsigned long exit_qualification; |
2943 | u16 tss_selector; | |
2944 | int reason; | |
2945 | ||
2946 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
2947 | ||
2948 | reason = (u32)exit_qualification >> 30; | |
60637aac JK |
2949 | if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected && |
2950 | (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && | |
2951 | (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK) | |
2952 | == INTR_TYPE_NMI_INTR) { | |
2953 | vcpu->arch.nmi_injected = false; | |
2954 | if (cpu_has_virtual_nmis()) | |
2955 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
2956 | GUEST_INTR_STATE_NMI); | |
2957 | } | |
37817f29 IE |
2958 | tss_selector = exit_qualification; |
2959 | ||
2960 | return kvm_task_switch(vcpu, tss_selector, reason); | |
2961 | } | |
2962 | ||
1439442c SY |
2963 | static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2964 | { | |
2965 | u64 exit_qualification; | |
2966 | enum emulation_result er; | |
2967 | gpa_t gpa; | |
2968 | unsigned long hva; | |
2969 | int gla_validity; | |
2970 | int r; | |
2971 | ||
2972 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2973 | ||
2974 | if (exit_qualification & (1 << 6)) { | |
2975 | printk(KERN_ERR "EPT: GPA exceeds GAW!\n"); | |
2976 | return -ENOTSUPP; | |
2977 | } | |
2978 | ||
2979 | gla_validity = (exit_qualification >> 7) & 0x3; | |
2980 | if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) { | |
2981 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | |
2982 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
2983 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
2984 | (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS)); | |
2985 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", | |
2986 | (long unsigned int)exit_qualification); | |
2987 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
2988 | kvm_run->hw.hardware_exit_reason = 0; | |
2989 | return -ENOTSUPP; | |
2990 | } | |
2991 | ||
2992 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
2993 | hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT); | |
2994 | if (!kvm_is_error_hva(hva)) { | |
2995 | r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0); | |
2996 | if (r < 0) { | |
2997 | printk(KERN_ERR "EPT: Not enough memory!\n"); | |
2998 | return -ENOMEM; | |
2999 | } | |
3000 | return 1; | |
3001 | } else { | |
3002 | /* must be MMIO */ | |
3003 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
3004 | ||
3005 | if (er == EMULATE_FAIL) { | |
3006 | printk(KERN_ERR | |
3007 | "EPT: Fail to handle EPT violation vmexit!er is %d\n", | |
3008 | er); | |
3009 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
3010 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
3011 | (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS)); | |
3012 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", | |
3013 | (long unsigned int)exit_qualification); | |
3014 | return -ENOTSUPP; | |
3015 | } else if (er == EMULATE_DO_MMIO) | |
3016 | return 0; | |
3017 | } | |
3018 | return 1; | |
3019 | } | |
3020 | ||
f08864b4 SY |
3021 | static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
3022 | { | |
3023 | u32 cpu_based_vm_exec_control; | |
3024 | ||
3025 | /* clear pending NMI */ | |
3026 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
3027 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
3028 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
3029 | ++vcpu->stat.nmi_window_exits; | |
3030 | ||
487b391d JK |
3031 | /* |
3032 | * If the user space waits to inject a NMI, exit as soon as possible | |
3033 | */ | |
3034 | if (kvm_run->request_nmi_window && !vcpu->arch.nmi_pending) { | |
3035 | kvm_run->exit_reason = KVM_EXIT_NMI_WINDOW_OPEN; | |
3036 | return 0; | |
3037 | } | |
3038 | ||
f08864b4 SY |
3039 | return 1; |
3040 | } | |
3041 | ||
ea953ef0 MG |
3042 | static void handle_invalid_guest_state(struct kvm_vcpu *vcpu, |
3043 | struct kvm_run *kvm_run) | |
3044 | { | |
3045 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3046 | int err; | |
3047 | ||
3048 | preempt_enable(); | |
3049 | local_irq_enable(); | |
3050 | ||
3051 | while (!guest_state_valid(vcpu)) { | |
3052 | err = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
3053 | ||
3054 | switch (err) { | |
3055 | case EMULATE_DONE: | |
3056 | break; | |
3057 | case EMULATE_DO_MMIO: | |
3058 | kvm_report_emulation_failure(vcpu, "mmio"); | |
3059 | /* TODO: Handle MMIO */ | |
3060 | return; | |
3061 | default: | |
3062 | kvm_report_emulation_failure(vcpu, "emulation failure"); | |
3063 | return; | |
3064 | } | |
3065 | ||
3066 | if (signal_pending(current)) | |
3067 | break; | |
3068 | if (need_resched()) | |
3069 | schedule(); | |
3070 | } | |
3071 | ||
3072 | local_irq_disable(); | |
3073 | preempt_disable(); | |
3074 | ||
3075 | /* Guest state should be valid now, no more emulation should be needed */ | |
3076 | vmx->emulation_required = 0; | |
3077 | } | |
3078 | ||
6aa8b732 AK |
3079 | /* |
3080 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
3081 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
3082 | * to be done to userspace and return 0. | |
3083 | */ | |
3084 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, | |
3085 | struct kvm_run *kvm_run) = { | |
3086 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, | |
3087 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 3088 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 3089 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 3090 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
3091 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
3092 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
3093 | [EXIT_REASON_CPUID] = handle_cpuid, | |
3094 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
3095 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
3096 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
3097 | [EXIT_REASON_HLT] = handle_halt, | |
a7052897 | 3098 | [EXIT_REASON_INVLPG] = handle_invlpg, |
c21415e8 | 3099 | [EXIT_REASON_VMCALL] = handle_vmcall, |
f78e0e2e SY |
3100 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
3101 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
e5edaa01 | 3102 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
37817f29 | 3103 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
1439442c | 3104 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
6aa8b732 AK |
3105 | }; |
3106 | ||
3107 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 3108 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 AK |
3109 | |
3110 | /* | |
3111 | * The guest has exited. See if we can fix it or if we need userspace | |
3112 | * assistance. | |
3113 | */ | |
3114 | static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |
3115 | { | |
6aa8b732 | 3116 | u32 exit_reason = vmcs_read32(VM_EXIT_REASON); |
29bd8a78 | 3117 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1155f76a | 3118 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 3119 | |
5fdbf976 MT |
3120 | KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu), |
3121 | (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit); | |
2714d1d3 | 3122 | |
1439442c SY |
3123 | /* Access CR3 don't cause VMExit in paging mode, so we need |
3124 | * to sync with guest real CR3. */ | |
3125 | if (vm_need_ept() && is_paging(vcpu)) { | |
3126 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
3127 | ept_load_pdptrs(vcpu); | |
3128 | } | |
3129 | ||
29bd8a78 AK |
3130 | if (unlikely(vmx->fail)) { |
3131 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3132 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3133 | = vmcs_read32(VM_INSTRUCTION_ERROR); | |
3134 | return 0; | |
3135 | } | |
6aa8b732 | 3136 | |
d77c26fc | 3137 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 3138 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac JK |
3139 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
3140 | exit_reason != EXIT_REASON_TASK_SWITCH)) | |
3141 | printk(KERN_WARNING "%s: unexpected, valid vectoring info " | |
3142 | "(0x%x) and exit reason is 0x%x\n", | |
3143 | __func__, vectoring_info, exit_reason); | |
3b86cd99 JK |
3144 | |
3145 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) { | |
3146 | if (vcpu->arch.interrupt_window_open) { | |
3147 | vmx->soft_vnmi_blocked = 0; | |
3148 | vcpu->arch.nmi_window_open = 1; | |
3149 | } else if (vmx->vnmi_blocked_time > 1000000000LL && | |
3150 | (kvm_run->request_nmi_window || vcpu->arch.nmi_pending)) { | |
3151 | /* | |
3152 | * This CPU don't support us in finding the end of an | |
3153 | * NMI-blocked window if the guest runs with IRQs | |
3154 | * disabled. So we pull the trigger after 1 s of | |
3155 | * futile waiting, but inform the user about this. | |
3156 | */ | |
3157 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
3158 | "state on VCPU %d after 1 s timeout\n", | |
3159 | __func__, vcpu->vcpu_id); | |
3160 | vmx->soft_vnmi_blocked = 0; | |
3161 | vmx->vcpu.arch.nmi_window_open = 1; | |
3162 | } | |
3163 | ||
3164 | /* | |
3165 | * If the user space waits to inject an NNI, exit ASAP | |
3166 | */ | |
3167 | if (vcpu->arch.nmi_window_open && kvm_run->request_nmi_window | |
3168 | && !vcpu->arch.nmi_pending) { | |
3169 | kvm_run->exit_reason = KVM_EXIT_NMI_WINDOW_OPEN; | |
3170 | ++vcpu->stat.nmi_window_exits; | |
3171 | return 0; | |
3172 | } | |
3173 | } | |
3174 | ||
6aa8b732 AK |
3175 | if (exit_reason < kvm_vmx_max_exit_handlers |
3176 | && kvm_vmx_exit_handlers[exit_reason]) | |
3177 | return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run); | |
3178 | else { | |
3179 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
3180 | kvm_run->hw.hardware_exit_reason = exit_reason; | |
3181 | } | |
3182 | return 0; | |
3183 | } | |
3184 | ||
6e5d865c YS |
3185 | static void update_tpr_threshold(struct kvm_vcpu *vcpu) |
3186 | { | |
3187 | int max_irr, tpr; | |
3188 | ||
3189 | if (!vm_need_tpr_shadow(vcpu->kvm)) | |
3190 | return; | |
3191 | ||
3192 | if (!kvm_lapic_enabled(vcpu) || | |
3193 | ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) { | |
3194 | vmcs_write32(TPR_THRESHOLD, 0); | |
3195 | return; | |
3196 | } | |
3197 | ||
3198 | tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4; | |
3199 | vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4); | |
3200 | } | |
3201 | ||
cf393f75 AK |
3202 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
3203 | { | |
3204 | u32 exit_intr_info; | |
668f612f | 3205 | u32 idt_vectoring_info; |
cf393f75 AK |
3206 | bool unblock_nmi; |
3207 | u8 vector; | |
668f612f AK |
3208 | int type; |
3209 | bool idtv_info_valid; | |
35920a35 | 3210 | u32 error; |
cf393f75 AK |
3211 | |
3212 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
3213 | if (cpu_has_virtual_nmis()) { | |
3214 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | |
3215 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
3216 | /* | |
3217 | * SDM 3: 25.7.1.2 | |
3218 | * Re-set bit "block by NMI" before VM entry if vmexit caused by | |
3219 | * a guest IRET fault. | |
3220 | */ | |
3221 | if (unblock_nmi && vector != DF_VECTOR) | |
3222 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
3223 | GUEST_INTR_STATE_NMI); | |
3b86cd99 JK |
3224 | } else if (unlikely(vmx->soft_vnmi_blocked)) |
3225 | vmx->vnmi_blocked_time += | |
3226 | ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time)); | |
668f612f AK |
3227 | |
3228 | idt_vectoring_info = vmx->idt_vectoring_info; | |
3229 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
3230 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; | |
3231 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
3232 | if (vmx->vcpu.arch.nmi_injected) { | |
3233 | /* | |
3234 | * SDM 3: 25.7.1.2 | |
3235 | * Clear bit "block by NMI" before VM entry if a NMI delivery | |
3236 | * faulted. | |
3237 | */ | |
3238 | if (idtv_info_valid && type == INTR_TYPE_NMI_INTR) | |
3239 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
3240 | GUEST_INTR_STATE_NMI); | |
3241 | else | |
3242 | vmx->vcpu.arch.nmi_injected = false; | |
3243 | } | |
35920a35 AK |
3244 | kvm_clear_exception_queue(&vmx->vcpu); |
3245 | if (idtv_info_valid && type == INTR_TYPE_EXCEPTION) { | |
3246 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { | |
3247 | error = vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
3248 | kvm_queue_exception_e(&vmx->vcpu, vector, error); | |
3249 | } else | |
3250 | kvm_queue_exception(&vmx->vcpu, vector); | |
3251 | vmx->idt_vectoring_info = 0; | |
3252 | } | |
f7d9238f AK |
3253 | kvm_clear_interrupt_queue(&vmx->vcpu); |
3254 | if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) { | |
3255 | kvm_queue_interrupt(&vmx->vcpu, vector); | |
3256 | vmx->idt_vectoring_info = 0; | |
3257 | } | |
cf393f75 AK |
3258 | } |
3259 | ||
85f455f7 ED |
3260 | static void vmx_intr_assist(struct kvm_vcpu *vcpu) |
3261 | { | |
6e5d865c YS |
3262 | update_tpr_threshold(vcpu); |
3263 | ||
33f089ca JK |
3264 | vmx_update_window_states(vcpu); |
3265 | ||
3b86cd99 JK |
3266 | if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) { |
3267 | if (vcpu->arch.interrupt.pending) { | |
3268 | enable_nmi_window(vcpu); | |
3269 | } else if (vcpu->arch.nmi_window_open) { | |
3270 | vcpu->arch.nmi_pending = false; | |
3271 | vcpu->arch.nmi_injected = true; | |
3272 | } else { | |
3273 | enable_nmi_window(vcpu); | |
f08864b4 SY |
3274 | return; |
3275 | } | |
f08864b4 | 3276 | } |
3b86cd99 JK |
3277 | if (vcpu->arch.nmi_injected) { |
3278 | vmx_inject_nmi(vcpu); | |
3279 | if (vcpu->arch.nmi_pending) | |
3280 | enable_nmi_window(vcpu); | |
3281 | else if (kvm_cpu_has_interrupt(vcpu)) | |
3282 | enable_irq_window(vcpu); | |
3283 | return; | |
3284 | } | |
f7d9238f | 3285 | if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) { |
33f089ca | 3286 | if (vcpu->arch.interrupt_window_open) |
f7d9238f AK |
3287 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu)); |
3288 | else | |
3289 | enable_irq_window(vcpu); | |
3290 | } | |
3291 | if (vcpu->arch.interrupt.pending) { | |
3292 | vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr); | |
3293 | kvm_timer_intr_post(vcpu, vcpu->arch.interrupt.nr); | |
3294 | } | |
85f455f7 ED |
3295 | } |
3296 | ||
9c8cba37 AK |
3297 | /* |
3298 | * Failure to inject an interrupt should give us the information | |
3299 | * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs | |
3300 | * when fetching the interrupt redirection bitmap in the real-mode | |
3301 | * tss, this doesn't happen. So we do it ourselves. | |
3302 | */ | |
3303 | static void fixup_rmode_irq(struct vcpu_vmx *vmx) | |
3304 | { | |
3305 | vmx->rmode.irq.pending = 0; | |
5fdbf976 | 3306 | if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip) |
9c8cba37 | 3307 | return; |
5fdbf976 | 3308 | kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip); |
9c8cba37 AK |
3309 | if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) { |
3310 | vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK; | |
3311 | vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR; | |
3312 | return; | |
3313 | } | |
3314 | vmx->idt_vectoring_info = | |
3315 | VECTORING_INFO_VALID_MASK | |
3316 | | INTR_TYPE_EXT_INTR | |
3317 | | vmx->rmode.irq.vector; | |
3318 | } | |
3319 | ||
c801949d AK |
3320 | #ifdef CONFIG_X86_64 |
3321 | #define R "r" | |
3322 | #define Q "q" | |
3323 | #else | |
3324 | #define R "e" | |
3325 | #define Q "l" | |
3326 | #endif | |
3327 | ||
04d2cc77 | 3328 | static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6aa8b732 | 3329 | { |
a2fa3e9f | 3330 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1b6269db | 3331 | u32 intr_info; |
e6adf283 | 3332 | |
3b86cd99 JK |
3333 | /* Record the guest's net vcpu time for enforced NMI injections. */ |
3334 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) | |
3335 | vmx->entry_time = ktime_get(); | |
3336 | ||
a89a8fb9 MG |
3337 | /* Handle invalid guest state instead of entering VMX */ |
3338 | if (vmx->emulation_required && emulate_invalid_guest_state) { | |
3339 | handle_invalid_guest_state(vcpu, kvm_run); | |
3340 | return; | |
3341 | } | |
3342 | ||
5fdbf976 MT |
3343 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
3344 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
3345 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
3346 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
3347 | ||
e6adf283 AK |
3348 | /* |
3349 | * Loading guest fpu may have cleared host cr0.ts | |
3350 | */ | |
3351 | vmcs_writel(HOST_CR0, read_cr0()); | |
3352 | ||
d77c26fc | 3353 | asm( |
6aa8b732 | 3354 | /* Store host registers */ |
c801949d AK |
3355 | "push %%"R"dx; push %%"R"bp;" |
3356 | "push %%"R"cx \n\t" | |
313dbd49 AK |
3357 | "cmp %%"R"sp, %c[host_rsp](%0) \n\t" |
3358 | "je 1f \n\t" | |
3359 | "mov %%"R"sp, %c[host_rsp](%0) \n\t" | |
4ecac3fd | 3360 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 3361 | "1: \n\t" |
6aa8b732 | 3362 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 3363 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 3364 | /* Load guest registers. Don't clobber flags. */ |
c801949d AK |
3365 | "mov %c[cr2](%0), %%"R"ax \n\t" |
3366 | "mov %%"R"ax, %%cr2 \n\t" | |
3367 | "mov %c[rax](%0), %%"R"ax \n\t" | |
3368 | "mov %c[rbx](%0), %%"R"bx \n\t" | |
3369 | "mov %c[rdx](%0), %%"R"dx \n\t" | |
3370 | "mov %c[rsi](%0), %%"R"si \n\t" | |
3371 | "mov %c[rdi](%0), %%"R"di \n\t" | |
3372 | "mov %c[rbp](%0), %%"R"bp \n\t" | |
05b3e0c2 | 3373 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
3374 | "mov %c[r8](%0), %%r8 \n\t" |
3375 | "mov %c[r9](%0), %%r9 \n\t" | |
3376 | "mov %c[r10](%0), %%r10 \n\t" | |
3377 | "mov %c[r11](%0), %%r11 \n\t" | |
3378 | "mov %c[r12](%0), %%r12 \n\t" | |
3379 | "mov %c[r13](%0), %%r13 \n\t" | |
3380 | "mov %c[r14](%0), %%r14 \n\t" | |
3381 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 3382 | #endif |
c801949d AK |
3383 | "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */ |
3384 | ||
6aa8b732 | 3385 | /* Enter guest mode */ |
cd2276a7 | 3386 | "jne .Llaunched \n\t" |
4ecac3fd | 3387 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
cd2276a7 | 3388 | "jmp .Lkvm_vmx_return \n\t" |
4ecac3fd | 3389 | ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t" |
cd2276a7 | 3390 | ".Lkvm_vmx_return: " |
6aa8b732 | 3391 | /* Save guest registers, load host registers, keep flags */ |
c801949d AK |
3392 | "xchg %0, (%%"R"sp) \n\t" |
3393 | "mov %%"R"ax, %c[rax](%0) \n\t" | |
3394 | "mov %%"R"bx, %c[rbx](%0) \n\t" | |
3395 | "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t" | |
3396 | "mov %%"R"dx, %c[rdx](%0) \n\t" | |
3397 | "mov %%"R"si, %c[rsi](%0) \n\t" | |
3398 | "mov %%"R"di, %c[rdi](%0) \n\t" | |
3399 | "mov %%"R"bp, %c[rbp](%0) \n\t" | |
05b3e0c2 | 3400 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
3401 | "mov %%r8, %c[r8](%0) \n\t" |
3402 | "mov %%r9, %c[r9](%0) \n\t" | |
3403 | "mov %%r10, %c[r10](%0) \n\t" | |
3404 | "mov %%r11, %c[r11](%0) \n\t" | |
3405 | "mov %%r12, %c[r12](%0) \n\t" | |
3406 | "mov %%r13, %c[r13](%0) \n\t" | |
3407 | "mov %%r14, %c[r14](%0) \n\t" | |
3408 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 3409 | #endif |
c801949d AK |
3410 | "mov %%cr2, %%"R"ax \n\t" |
3411 | "mov %%"R"ax, %c[cr2](%0) \n\t" | |
3412 | ||
3413 | "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t" | |
e08aa78a AK |
3414 | "setbe %c[fail](%0) \n\t" |
3415 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), | |
3416 | [launched]"i"(offsetof(struct vcpu_vmx, launched)), | |
3417 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), | |
313dbd49 | 3418 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
3419 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
3420 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
3421 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3422 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3423 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3424 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3425 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 3426 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3427 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
3428 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
3429 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
3430 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
3431 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
3432 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
3433 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
3434 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 3435 | #endif |
ad312c7c | 3436 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)) |
c2036300 | 3437 | : "cc", "memory" |
c801949d | 3438 | , R"bx", R"di", R"si" |
c2036300 | 3439 | #ifdef CONFIG_X86_64 |
c2036300 LV |
3440 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
3441 | #endif | |
3442 | ); | |
6aa8b732 | 3443 | |
5fdbf976 MT |
3444 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)); |
3445 | vcpu->arch.regs_dirty = 0; | |
3446 | ||
1155f76a | 3447 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
9c8cba37 AK |
3448 | if (vmx->rmode.irq.pending) |
3449 | fixup_rmode_irq(vmx); | |
1155f76a | 3450 | |
33f089ca | 3451 | vmx_update_window_states(vcpu); |
6aa8b732 | 3452 | |
d77c26fc | 3453 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
15ad7146 | 3454 | vmx->launched = 1; |
1b6269db AK |
3455 | |
3456 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
3457 | ||
3458 | /* We need to handle NMIs before interrupts are enabled */ | |
e4a41889 | 3459 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR && |
f08864b4 | 3460 | (intr_info & INTR_INFO_VALID_MASK)) { |
2714d1d3 | 3461 | KVMTRACE_0D(NMI, vcpu, handler); |
1b6269db | 3462 | asm("int $2"); |
2714d1d3 | 3463 | } |
cf393f75 AK |
3464 | |
3465 | vmx_complete_interrupts(vmx); | |
6aa8b732 AK |
3466 | } |
3467 | ||
c801949d AK |
3468 | #undef R |
3469 | #undef Q | |
3470 | ||
6aa8b732 AK |
3471 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) |
3472 | { | |
a2fa3e9f GH |
3473 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3474 | ||
3475 | if (vmx->vmcs) { | |
543e4243 | 3476 | vcpu_clear(vmx); |
a2fa3e9f GH |
3477 | free_vmcs(vmx->vmcs); |
3478 | vmx->vmcs = NULL; | |
6aa8b732 AK |
3479 | } |
3480 | } | |
3481 | ||
3482 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
3483 | { | |
fb3f0f51 RR |
3484 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3485 | ||
2384d2b3 SY |
3486 | spin_lock(&vmx_vpid_lock); |
3487 | if (vmx->vpid != 0) | |
3488 | __clear_bit(vmx->vpid, vmx_vpid_bitmap); | |
3489 | spin_unlock(&vmx_vpid_lock); | |
6aa8b732 | 3490 | vmx_free_vmcs(vcpu); |
fb3f0f51 RR |
3491 | kfree(vmx->host_msrs); |
3492 | kfree(vmx->guest_msrs); | |
3493 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 3494 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
3495 | } |
3496 | ||
fb3f0f51 | 3497 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 3498 | { |
fb3f0f51 | 3499 | int err; |
c16f862d | 3500 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 3501 | int cpu; |
6aa8b732 | 3502 | |
a2fa3e9f | 3503 | if (!vmx) |
fb3f0f51 RR |
3504 | return ERR_PTR(-ENOMEM); |
3505 | ||
2384d2b3 SY |
3506 | allocate_vpid(vmx); |
3507 | ||
fb3f0f51 RR |
3508 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
3509 | if (err) | |
3510 | goto free_vcpu; | |
965b58a5 | 3511 | |
a2fa3e9f | 3512 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
fb3f0f51 RR |
3513 | if (!vmx->guest_msrs) { |
3514 | err = -ENOMEM; | |
3515 | goto uninit_vcpu; | |
3516 | } | |
965b58a5 | 3517 | |
a2fa3e9f GH |
3518 | vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
3519 | if (!vmx->host_msrs) | |
fb3f0f51 | 3520 | goto free_guest_msrs; |
965b58a5 | 3521 | |
a2fa3e9f GH |
3522 | vmx->vmcs = alloc_vmcs(); |
3523 | if (!vmx->vmcs) | |
fb3f0f51 | 3524 | goto free_msrs; |
a2fa3e9f GH |
3525 | |
3526 | vmcs_clear(vmx->vmcs); | |
3527 | ||
15ad7146 AK |
3528 | cpu = get_cpu(); |
3529 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
8b9cf98c | 3530 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 3531 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 3532 | put_cpu(); |
fb3f0f51 RR |
3533 | if (err) |
3534 | goto free_vmcs; | |
5e4a0b3c MT |
3535 | if (vm_need_virtualize_apic_accesses(kvm)) |
3536 | if (alloc_apic_access_page(kvm) != 0) | |
3537 | goto free_vmcs; | |
fb3f0f51 | 3538 | |
b7ebfb05 SY |
3539 | if (vm_need_ept()) |
3540 | if (alloc_identity_pagetable(kvm) != 0) | |
3541 | goto free_vmcs; | |
3542 | ||
fb3f0f51 RR |
3543 | return &vmx->vcpu; |
3544 | ||
3545 | free_vmcs: | |
3546 | free_vmcs(vmx->vmcs); | |
3547 | free_msrs: | |
3548 | kfree(vmx->host_msrs); | |
3549 | free_guest_msrs: | |
3550 | kfree(vmx->guest_msrs); | |
3551 | uninit_vcpu: | |
3552 | kvm_vcpu_uninit(&vmx->vcpu); | |
3553 | free_vcpu: | |
a4770347 | 3554 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 3555 | return ERR_PTR(err); |
6aa8b732 AK |
3556 | } |
3557 | ||
002c7f7c YS |
3558 | static void __init vmx_check_processor_compat(void *rtn) |
3559 | { | |
3560 | struct vmcs_config vmcs_conf; | |
3561 | ||
3562 | *(int *)rtn = 0; | |
3563 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
3564 | *(int *)rtn = -EIO; | |
3565 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
3566 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
3567 | smp_processor_id()); | |
3568 | *(int *)rtn = -EIO; | |
3569 | } | |
3570 | } | |
3571 | ||
67253af5 SY |
3572 | static int get_ept_level(void) |
3573 | { | |
3574 | return VMX_EPT_DEFAULT_GAW + 1; | |
3575 | } | |
3576 | ||
64d4d521 SY |
3577 | static int vmx_get_mt_mask_shift(void) |
3578 | { | |
3579 | return VMX_EPT_MT_EPTE_SHIFT; | |
3580 | } | |
3581 | ||
cbdd1bea | 3582 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
3583 | .cpu_has_kvm_support = cpu_has_kvm_support, |
3584 | .disabled_by_bios = vmx_disabled_by_bios, | |
3585 | .hardware_setup = hardware_setup, | |
3586 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 3587 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
3588 | .hardware_enable = hardware_enable, |
3589 | .hardware_disable = hardware_disable, | |
774ead3a | 3590 | .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses, |
6aa8b732 AK |
3591 | |
3592 | .vcpu_create = vmx_create_vcpu, | |
3593 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 3594 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 3595 | |
04d2cc77 | 3596 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
3597 | .vcpu_load = vmx_vcpu_load, |
3598 | .vcpu_put = vmx_vcpu_put, | |
3599 | ||
3600 | .set_guest_debug = set_guest_debug, | |
04d2cc77 | 3601 | .guest_debug_pre = kvm_guest_debug_pre, |
6aa8b732 AK |
3602 | .get_msr = vmx_get_msr, |
3603 | .set_msr = vmx_set_msr, | |
3604 | .get_segment_base = vmx_get_segment_base, | |
3605 | .get_segment = vmx_get_segment, | |
3606 | .set_segment = vmx_set_segment, | |
2e4d2653 | 3607 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 3608 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
25c4c276 | 3609 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 3610 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
3611 | .set_cr3 = vmx_set_cr3, |
3612 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 3613 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
3614 | .get_idt = vmx_get_idt, |
3615 | .set_idt = vmx_set_idt, | |
3616 | .get_gdt = vmx_get_gdt, | |
3617 | .set_gdt = vmx_set_gdt, | |
5fdbf976 | 3618 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
3619 | .get_rflags = vmx_get_rflags, |
3620 | .set_rflags = vmx_set_rflags, | |
3621 | ||
3622 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 3623 | |
6aa8b732 | 3624 | .run = vmx_vcpu_run, |
04d2cc77 | 3625 | .handle_exit = kvm_handle_exit, |
6aa8b732 | 3626 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 3627 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 ED |
3628 | .get_irq = vmx_get_irq, |
3629 | .set_irq = vmx_inject_irq, | |
298101da AK |
3630 | .queue_exception = vmx_queue_exception, |
3631 | .exception_injected = vmx_exception_injected, | |
04d2cc77 AK |
3632 | .inject_pending_irq = vmx_intr_assist, |
3633 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
3634 | |
3635 | .set_tss_addr = vmx_set_tss_addr, | |
67253af5 | 3636 | .get_tdp_level = get_ept_level, |
64d4d521 | 3637 | .get_mt_mask_shift = vmx_get_mt_mask_shift, |
6aa8b732 AK |
3638 | }; |
3639 | ||
3640 | static int __init vmx_init(void) | |
3641 | { | |
25c5f225 | 3642 | void *va; |
fdef3ad1 HQ |
3643 | int r; |
3644 | ||
3645 | vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
3646 | if (!vmx_io_bitmap_a) | |
3647 | return -ENOMEM; | |
3648 | ||
3649 | vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
3650 | if (!vmx_io_bitmap_b) { | |
3651 | r = -ENOMEM; | |
3652 | goto out; | |
3653 | } | |
3654 | ||
25c5f225 SY |
3655 | vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); |
3656 | if (!vmx_msr_bitmap) { | |
3657 | r = -ENOMEM; | |
3658 | goto out1; | |
3659 | } | |
3660 | ||
fdef3ad1 HQ |
3661 | /* |
3662 | * Allow direct access to the PC debug port (it is often used for I/O | |
3663 | * delays, but the vmexits simply slow things down). | |
3664 | */ | |
25c5f225 SY |
3665 | va = kmap(vmx_io_bitmap_a); |
3666 | memset(va, 0xff, PAGE_SIZE); | |
3667 | clear_bit(0x80, va); | |
cd0536d7 | 3668 | kunmap(vmx_io_bitmap_a); |
fdef3ad1 | 3669 | |
25c5f225 SY |
3670 | va = kmap(vmx_io_bitmap_b); |
3671 | memset(va, 0xff, PAGE_SIZE); | |
cd0536d7 | 3672 | kunmap(vmx_io_bitmap_b); |
fdef3ad1 | 3673 | |
25c5f225 SY |
3674 | va = kmap(vmx_msr_bitmap); |
3675 | memset(va, 0xff, PAGE_SIZE); | |
3676 | kunmap(vmx_msr_bitmap); | |
3677 | ||
2384d2b3 SY |
3678 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
3679 | ||
cb498ea2 | 3680 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE); |
fdef3ad1 | 3681 | if (r) |
25c5f225 SY |
3682 | goto out2; |
3683 | ||
3684 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE); | |
3685 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE); | |
3686 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS); | |
3687 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP); | |
3688 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP); | |
fdef3ad1 | 3689 | |
5fdbcb9d | 3690 | if (vm_need_ept()) { |
1439442c | 3691 | bypass_guest_pf = 0; |
5fdbcb9d SY |
3692 | kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK | |
3693 | VMX_EPT_WRITABLE_MASK | | |
928d4bf7 | 3694 | VMX_EPT_IGMT_BIT); |
534e38b4 | 3695 | kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, |
64d4d521 SY |
3696 | VMX_EPT_EXECUTABLE_MASK, |
3697 | VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT); | |
5fdbcb9d SY |
3698 | kvm_enable_tdp(); |
3699 | } else | |
3700 | kvm_disable_tdp(); | |
1439442c | 3701 | |
c7addb90 AK |
3702 | if (bypass_guest_pf) |
3703 | kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull); | |
3704 | ||
1439442c SY |
3705 | ept_sync_global(); |
3706 | ||
fdef3ad1 HQ |
3707 | return 0; |
3708 | ||
25c5f225 SY |
3709 | out2: |
3710 | __free_page(vmx_msr_bitmap); | |
fdef3ad1 HQ |
3711 | out1: |
3712 | __free_page(vmx_io_bitmap_b); | |
3713 | out: | |
3714 | __free_page(vmx_io_bitmap_a); | |
3715 | return r; | |
6aa8b732 AK |
3716 | } |
3717 | ||
3718 | static void __exit vmx_exit(void) | |
3719 | { | |
25c5f225 | 3720 | __free_page(vmx_msr_bitmap); |
fdef3ad1 HQ |
3721 | __free_page(vmx_io_bitmap_b); |
3722 | __free_page(vmx_io_bitmap_a); | |
3723 | ||
cb498ea2 | 3724 | kvm_exit(); |
6aa8b732 AK |
3725 | } |
3726 | ||
3727 | module_init(vmx_init) | |
3728 | module_exit(vmx_exit) |