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KVM: x86: mmu: do not use return to tail-call functions that return void
[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
20300099
WL		 102static u64 __read_mostly host_xss;
103
5037878e
GN		 104#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
105#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 106#define KVM_VM_CR0_ALWAYS_ON \
107 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 108#define KVM_CR4_GUEST_OWNED_BITS \
109 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 110 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 111
cdc0e244
AK		 112#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
113#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
114
78ac8b47
AK		 115#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
116
f4124500
JK		 117#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
118
4b8d54f9
ZE		 119/*
120 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
121 * ple_gap: upper bound on the amount of time between two successive
122 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 123 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 124 * ple_window: upper bound on the amount of time a guest is allowed to execute
125 * in a PAUSE loop. Tests indicate that most spinlocks are held for
126 * less than 2^12 cycles
127 * Time is measured based on a counter that runs at the same rate as the TSC,
128 * refer SDM volume 3b section 21.6.13 & 22.1.3.
129 */
b4a2d31d
RK		 130#define KVM_VMX_DEFAULT_PLE_GAP 128
131#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
132#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
133#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
134#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
135 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
136
4b8d54f9
ZE		 137static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
138module_param(ple_gap, int, S_IRUGO);
139
140static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
141module_param(ple_window, int, S_IRUGO);
142
b4a2d31d
RK		 143/* Default doubles per-vcpu window every exit. */
144static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
145module_param(ple_window_grow, int, S_IRUGO);
146
147/* Default resets per-vcpu window every exit to ple_window. */
148static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
149module_param(ple_window_shrink, int, S_IRUGO);
150
151/* Default is to compute the maximum so we can never overflow. */
152static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
153static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
154module_param(ple_window_max, int, S_IRUGO);
155
83287ea4
AK		 156extern const ulong vmx_return;
157
8bf00a52 158#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 159#define VMCS02_POOL_SIZE 1
61d2ef2c 160
a2fa3e9f
GH		 161struct vmcs {
162 u32 revision_id;
163 u32 abort;
164 char data[0];
165};
166
d462b819
NHE		 167/*
168 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
169 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
170 * loaded on this CPU (so we can clear them if the CPU goes down).
171 */
172struct loaded_vmcs {
173 struct vmcs *vmcs;
174 int cpu;
175 int launched;
176 struct list_head loaded_vmcss_on_cpu_link;
177};
178
26bb0981
AK		 179struct shared_msr_entry {
180 unsigned index;
181 u64 data;
d5696725 182 u64 mask;
26bb0981
AK		 183};
184
a9d30f33
NHE		 185/*
186 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
187 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
188 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
189 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
190 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
191 * More than one of these structures may exist, if L1 runs multiple L2 guests.
192 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
193 * underlying hardware which will be used to run L2.
194 * This structure is packed to ensure that its layout is identical across
195 * machines (necessary for live migration).
196 * If there are changes in this struct, VMCS12_REVISION must be changed.
197 */
22bd0358 198typedef u64 natural_width;
a9d30f33
NHE		 199struct __packed vmcs12 {
200 /* According to the Intel spec, a VMCS region must start with the
201 * following two fields. Then follow implementation-specific data.
202 */
203 u32 revision_id;
204 u32 abort;
22bd0358 205
27d6c865
NHE		 206 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
207 u32 padding[7]; /* room for future expansion */
208
22bd0358
NHE		 209 u64 io_bitmap_a;
210 u64 io_bitmap_b;
211 u64 msr_bitmap;
212 u64 vm_exit_msr_store_addr;
213 u64 vm_exit_msr_load_addr;
214 u64 vm_entry_msr_load_addr;
215 u64 tsc_offset;
216 u64 virtual_apic_page_addr;
217 u64 apic_access_addr;
218 u64 ept_pointer;
81dc01f7 219 u64 xss_exit_bitmap;
22bd0358
NHE		 220 u64 guest_physical_address;
221 u64 vmcs_link_pointer;
222 u64 guest_ia32_debugctl;
223 u64 guest_ia32_pat;
224 u64 guest_ia32_efer;
225 u64 guest_ia32_perf_global_ctrl;
226 u64 guest_pdptr0;
227 u64 guest_pdptr1;
228 u64 guest_pdptr2;
229 u64 guest_pdptr3;
36be0b9d 230 u64 guest_bndcfgs;
22bd0358
NHE		 231 u64 host_ia32_pat;
232 u64 host_ia32_efer;
233 u64 host_ia32_perf_global_ctrl;
234 u64 padding64[8]; /* room for future expansion */
235 /*
236 * To allow migration of L1 (complete with its L2 guests) between
237 * machines of different natural widths (32 or 64 bit), we cannot have
238 * unsigned long fields with no explict size. We use u64 (aliased
239 * natural_width) instead. Luckily, x86 is little-endian.
240 */
241 natural_width cr0_guest_host_mask;
242 natural_width cr4_guest_host_mask;
243 natural_width cr0_read_shadow;
244 natural_width cr4_read_shadow;
245 natural_width cr3_target_value0;
246 natural_width cr3_target_value1;
247 natural_width cr3_target_value2;
248 natural_width cr3_target_value3;
249 natural_width exit_qualification;
250 natural_width guest_linear_address;
251 natural_width guest_cr0;
252 natural_width guest_cr3;
253 natural_width guest_cr4;
254 natural_width guest_es_base;
255 natural_width guest_cs_base;
256 natural_width guest_ss_base;
257 natural_width guest_ds_base;
258 natural_width guest_fs_base;
259 natural_width guest_gs_base;
260 natural_width guest_ldtr_base;
261 natural_width guest_tr_base;
262 natural_width guest_gdtr_base;
263 natural_width guest_idtr_base;
264 natural_width guest_dr7;
265 natural_width guest_rsp;
266 natural_width guest_rip;
267 natural_width guest_rflags;
268 natural_width guest_pending_dbg_exceptions;
269 natural_width guest_sysenter_esp;
270 natural_width guest_sysenter_eip;
271 natural_width host_cr0;
272 natural_width host_cr3;
273 natural_width host_cr4;
274 natural_width host_fs_base;
275 natural_width host_gs_base;
276 natural_width host_tr_base;
277 natural_width host_gdtr_base;
278 natural_width host_idtr_base;
279 natural_width host_ia32_sysenter_esp;
280 natural_width host_ia32_sysenter_eip;
281 natural_width host_rsp;
282 natural_width host_rip;
283 natural_width paddingl[8]; /* room for future expansion */
284 u32 pin_based_vm_exec_control;
285 u32 cpu_based_vm_exec_control;
286 u32 exception_bitmap;
287 u32 page_fault_error_code_mask;
288 u32 page_fault_error_code_match;
289 u32 cr3_target_count;
290 u32 vm_exit_controls;
291 u32 vm_exit_msr_store_count;
292 u32 vm_exit_msr_load_count;
293 u32 vm_entry_controls;
294 u32 vm_entry_msr_load_count;
295 u32 vm_entry_intr_info_field;
296 u32 vm_entry_exception_error_code;
297 u32 vm_entry_instruction_len;
298 u32 tpr_threshold;
299 u32 secondary_vm_exec_control;
300 u32 vm_instruction_error;
301 u32 vm_exit_reason;
302 u32 vm_exit_intr_info;
303 u32 vm_exit_intr_error_code;
304 u32 idt_vectoring_info_field;
305 u32 idt_vectoring_error_code;
306 u32 vm_exit_instruction_len;
307 u32 vmx_instruction_info;
308 u32 guest_es_limit;
309 u32 guest_cs_limit;
310 u32 guest_ss_limit;
311 u32 guest_ds_limit;
312 u32 guest_fs_limit;
313 u32 guest_gs_limit;
314 u32 guest_ldtr_limit;
315 u32 guest_tr_limit;
316 u32 guest_gdtr_limit;
317 u32 guest_idtr_limit;
318 u32 guest_es_ar_bytes;
319 u32 guest_cs_ar_bytes;
320 u32 guest_ss_ar_bytes;
321 u32 guest_ds_ar_bytes;
322 u32 guest_fs_ar_bytes;
323 u32 guest_gs_ar_bytes;
324 u32 guest_ldtr_ar_bytes;
325 u32 guest_tr_ar_bytes;
326 u32 guest_interruptibility_info;
327 u32 guest_activity_state;
328 u32 guest_sysenter_cs;
329 u32 host_ia32_sysenter_cs;
0238ea91
JK		 330 u32 vmx_preemption_timer_value;
331 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 332 u16 virtual_processor_id;
333 u16 guest_es_selector;
334 u16 guest_cs_selector;
335 u16 guest_ss_selector;
336 u16 guest_ds_selector;
337 u16 guest_fs_selector;
338 u16 guest_gs_selector;
339 u16 guest_ldtr_selector;
340 u16 guest_tr_selector;
341 u16 host_es_selector;
342 u16 host_cs_selector;
343 u16 host_ss_selector;
344 u16 host_ds_selector;
345 u16 host_fs_selector;
346 u16 host_gs_selector;
347 u16 host_tr_selector;
a9d30f33
NHE		 348};
349
350/*
351 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
352 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
353 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
354 */
355#define VMCS12_REVISION 0x11e57ed0
356
357/*
358 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
359 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
360 * current implementation, 4K are reserved to avoid future complications.
361 */
362#define VMCS12_SIZE 0x1000
363
ff2f6fe9
NHE		 364/* Used to remember the last vmcs02 used for some recently used vmcs12s */
365struct vmcs02_list {
366 struct list_head list;
367 gpa_t vmptr;
368 struct loaded_vmcs vmcs02;
369};
370
ec378aee
NHE		 371/*
372 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
373 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
374 */
375struct nested_vmx {
376 /* Has the level1 guest done vmxon? */
377 bool vmxon;
3573e22c 378 gpa_t vmxon_ptr;
a9d30f33
NHE		 379
380 /* The guest-physical address of the current VMCS L1 keeps for L2 */
381 gpa_t current_vmptr;
382 /* The host-usable pointer to the above */
383 struct page *current_vmcs12_page;
384 struct vmcs12 *current_vmcs12;
8de48833 385 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 386 /*
387 * Indicates if the shadow vmcs must be updated with the
388 * data hold by vmcs12
389 */
390 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 391
392 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
393 struct list_head vmcs02_pool;
394 int vmcs02_num;
fe3ef05c 395 u64 vmcs01_tsc_offset;
644d711a
NHE		 396 /* L2 must run next, and mustn't decide to exit to L1. */
397 bool nested_run_pending;
fe3ef05c
NHE		 398 /*
399 * Guest pages referred to in vmcs02 with host-physical pointers, so
400 * we must keep them pinned while L2 runs.
401 */
402 struct page *apic_access_page;
a7c0b07d 403 struct page *virtual_apic_page;
b3897a49 404 u64 msr_ia32_feature_control;
f4124500
JK		 405
406 struct hrtimer preemption_timer;
407 bool preemption_timer_expired;
2996fca0
JK		 408
409 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
410 u64 vmcs01_debugctl;
ec378aee
NHE		 411};
412
01e439be
YZ		 413#define POSTED_INTR_ON 0
414/* Posted-Interrupt Descriptor */
415struct pi_desc {
416 u32 pir[8]; /* Posted interrupt requested */
417 u32 control; /* bit 0 of control is outstanding notification bit */
418 u32 rsvd[7];
419} __aligned(64);
420
a20ed54d
YZ		 421static bool pi_test_and_set_on(struct pi_desc *pi_desc)
422{
423 return test_and_set_bit(POSTED_INTR_ON,
424 (unsigned long *)&pi_desc->control);
425}
426
427static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
428{
429 return test_and_clear_bit(POSTED_INTR_ON,
430 (unsigned long *)&pi_desc->control);
431}
432
433static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
434{
435 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
436}
437
7c6a98df
MT		 438static int pi_test_pir(int vector, struct pi_desc *pi_desc)
439{
440 return test_bit(vector, (unsigned long *)pi_desc->pir);
441}
442
a2fa3e9f 443struct vcpu_vmx {
fb3f0f51 444 struct kvm_vcpu vcpu;
313dbd49 445 unsigned long host_rsp;
29bd8a78 446 u8 fail;
9d58b931 447 bool nmi_known_unmasked;
51aa01d1 448 u32 exit_intr_info;
1155f76a 449 u32 idt_vectoring_info;
6de12732 450 ulong rflags;
26bb0981 451 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 452 int nmsrs;
453 int save_nmsrs;
a547c6db 454 unsigned long host_idt_base;
a2fa3e9f 455#ifdef CONFIG_X86_64
44ea2b17
AK		 456 u64 msr_host_kernel_gs_base;
457 u64 msr_guest_kernel_gs_base;
a2fa3e9f 458#endif
2961e876
GN		 459 u32 vm_entry_controls_shadow;
460 u32 vm_exit_controls_shadow;
d462b819
NHE		 461 /*
462 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
463 * non-nested (L1) guest, it always points to vmcs01. For a nested
464 * guest (L2), it points to a different VMCS.
465 */
466 struct loaded_vmcs vmcs01;
467 struct loaded_vmcs *loaded_vmcs;
468 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 469 struct msr_autoload {
470 unsigned nr;
471 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
472 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
473 } msr_autoload;
a2fa3e9f
GH		 474 struct {
475 int loaded;
476 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 477#ifdef CONFIG_X86_64
478 u16 ds_sel, es_sel;
479#endif
152d3f2f
LV		 480 int gs_ldt_reload_needed;
481 int fs_reload_needed;
da8999d3 482 u64 msr_host_bndcfgs;
d974baa3 483 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 484 } host_state;
9c8cba37 485 struct {
7ffd92c5 486 int vm86_active;
78ac8b47 487 ulong save_rflags;
f5f7b2fe
AK		 488 struct kvm_segment segs[8];
489 } rmode;
490 struct {
491 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 492 struct kvm_save_segment {
493 u16 selector;
494 unsigned long base;
495 u32 limit;
496 u32 ar;
f5f7b2fe 497 } seg[8];
2fb92db1 498 } segment_cache;
2384d2b3 499 int vpid;
04fa4d32 500 bool emulation_required;
3b86cd99
JK		 501
502 /* Support for vnmi-less CPUs */
503 int soft_vnmi_blocked;
504 ktime_t entry_time;
505 s64 vnmi_blocked_time;
a0861c02 506 u32 exit_reason;
4e47c7a6
SY		 507
508 bool rdtscp_enabled;
ec378aee 509
01e439be
YZ		 510 /* Posted interrupt descriptor */
511 struct pi_desc pi_desc;
512
ec378aee
NHE		 513 /* Support for a guest hypervisor (nested VMX) */
514 struct nested_vmx nested;
a7653ecd
RK		 515
516 /* Dynamic PLE window. */
517 int ple_window;
518 bool ple_window_dirty;
a2fa3e9f
GH		 519};
520
2fb92db1
AK		 521enum segment_cache_field {
522 SEG_FIELD_SEL = 0,
523 SEG_FIELD_BASE = 1,
524 SEG_FIELD_LIMIT = 2,
525 SEG_FIELD_AR = 3,
526
527 SEG_FIELD_NR = 4
528};
529
a2fa3e9f
GH		 530static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
531{
fb3f0f51 532 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 533}
534
22bd0358
NHE		 535#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
536#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
537#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
538 [number##_HIGH] = VMCS12_OFFSET(name)+4
539
4607c2d7 540
fe2b201b 541static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 542 /*
543 * We do NOT shadow fields that are modified when L0
544 * traps and emulates any vmx instruction (e.g. VMPTRLD,
545 * VMXON...) executed by L1.
546 * For example, VM_INSTRUCTION_ERROR is read
547 * by L1 if a vmx instruction fails (part of the error path).
548 * Note the code assumes this logic. If for some reason
549 * we start shadowing these fields then we need to
550 * force a shadow sync when L0 emulates vmx instructions
551 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
552 * by nested_vmx_failValid)
553 */
554 VM_EXIT_REASON,
555 VM_EXIT_INTR_INFO,
556 VM_EXIT_INSTRUCTION_LEN,
557 IDT_VECTORING_INFO_FIELD,
558 IDT_VECTORING_ERROR_CODE,
559 VM_EXIT_INTR_ERROR_CODE,
560 EXIT_QUALIFICATION,
561 GUEST_LINEAR_ADDRESS,
562 GUEST_PHYSICAL_ADDRESS
563};
fe2b201b 564static int max_shadow_read_only_fields =
4607c2d7
AG		 565 ARRAY_SIZE(shadow_read_only_fields);
566
fe2b201b 567static unsigned long shadow_read_write_fields[] = {
a7c0b07d 568 TPR_THRESHOLD,
4607c2d7
AG		 569 GUEST_RIP,
570 GUEST_RSP,
571 GUEST_CR0,
572 GUEST_CR3,
573 GUEST_CR4,
574 GUEST_INTERRUPTIBILITY_INFO,
575 GUEST_RFLAGS,
576 GUEST_CS_SELECTOR,
577 GUEST_CS_AR_BYTES,
578 GUEST_CS_LIMIT,
579 GUEST_CS_BASE,
580 GUEST_ES_BASE,
36be0b9d 581 GUEST_BNDCFGS,
4607c2d7
AG		 582 CR0_GUEST_HOST_MASK,
583 CR0_READ_SHADOW,
584 CR4_READ_SHADOW,
585 TSC_OFFSET,
586 EXCEPTION_BITMAP,
587 CPU_BASED_VM_EXEC_CONTROL,
588 VM_ENTRY_EXCEPTION_ERROR_CODE,
589 VM_ENTRY_INTR_INFO_FIELD,
590 VM_ENTRY_INSTRUCTION_LEN,
591 VM_ENTRY_EXCEPTION_ERROR_CODE,
592 HOST_FS_BASE,
593 HOST_GS_BASE,
594 HOST_FS_SELECTOR,
595 HOST_GS_SELECTOR
596};
fe2b201b 597static int max_shadow_read_write_fields =
4607c2d7
AG		 598 ARRAY_SIZE(shadow_read_write_fields);
599
772e0318 600static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 601 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
602 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
603 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
604 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
605 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
606 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
607 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
608 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
609 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
610 FIELD(HOST_ES_SELECTOR, host_es_selector),
611 FIELD(HOST_CS_SELECTOR, host_cs_selector),
612 FIELD(HOST_SS_SELECTOR, host_ss_selector),
613 FIELD(HOST_DS_SELECTOR, host_ds_selector),
614 FIELD(HOST_FS_SELECTOR, host_fs_selector),
615 FIELD(HOST_GS_SELECTOR, host_gs_selector),
616 FIELD(HOST_TR_SELECTOR, host_tr_selector),
617 FIELD64(IO_BITMAP_A, io_bitmap_a),
618 FIELD64(IO_BITMAP_B, io_bitmap_b),
619 FIELD64(MSR_BITMAP, msr_bitmap),
620 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
621 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
622 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
623 FIELD64(TSC_OFFSET, tsc_offset),
624 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
625 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
626 FIELD64(EPT_POINTER, ept_pointer),
81dc01f7 627 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 628 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
629 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
630 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
631 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
632 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
633 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
634 FIELD64(GUEST_PDPTR0, guest_pdptr0),
635 FIELD64(GUEST_PDPTR1, guest_pdptr1),
636 FIELD64(GUEST_PDPTR2, guest_pdptr2),
637 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 638 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 639 FIELD64(HOST_IA32_PAT, host_ia32_pat),
640 FIELD64(HOST_IA32_EFER, host_ia32_efer),
641 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
642 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
643 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
644 FIELD(EXCEPTION_BITMAP, exception_bitmap),
645 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
646 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
647 FIELD(CR3_TARGET_COUNT, cr3_target_count),
648 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
649 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
650 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
651 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
652 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
653 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
654 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
655 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
656 FIELD(TPR_THRESHOLD, tpr_threshold),
657 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
658 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
659 FIELD(VM_EXIT_REASON, vm_exit_reason),
660 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
661 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
662 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
663 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
664 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
665 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
666 FIELD(GUEST_ES_LIMIT, guest_es_limit),
667 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
668 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
669 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
670 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
671 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
672 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
673 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
674 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
675 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
676 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
677 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
678 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
679 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
680 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
681 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
682 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
683 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
684 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
685 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
686 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
687 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 688 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 689 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
690 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
691 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
692 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
693 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
694 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
695 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
696 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
697 FIELD(EXIT_QUALIFICATION, exit_qualification),
698 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
699 FIELD(GUEST_CR0, guest_cr0),
700 FIELD(GUEST_CR3, guest_cr3),
701 FIELD(GUEST_CR4, guest_cr4),
702 FIELD(GUEST_ES_BASE, guest_es_base),
703 FIELD(GUEST_CS_BASE, guest_cs_base),
704 FIELD(GUEST_SS_BASE, guest_ss_base),
705 FIELD(GUEST_DS_BASE, guest_ds_base),
706 FIELD(GUEST_FS_BASE, guest_fs_base),
707 FIELD(GUEST_GS_BASE, guest_gs_base),
708 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
709 FIELD(GUEST_TR_BASE, guest_tr_base),
710 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
711 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
712 FIELD(GUEST_DR7, guest_dr7),
713 FIELD(GUEST_RSP, guest_rsp),
714 FIELD(GUEST_RIP, guest_rip),
715 FIELD(GUEST_RFLAGS, guest_rflags),
716 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
717 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
718 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
719 FIELD(HOST_CR0, host_cr0),
720 FIELD(HOST_CR3, host_cr3),
721 FIELD(HOST_CR4, host_cr4),
722 FIELD(HOST_FS_BASE, host_fs_base),
723 FIELD(HOST_GS_BASE, host_gs_base),
724 FIELD(HOST_TR_BASE, host_tr_base),
725 FIELD(HOST_GDTR_BASE, host_gdtr_base),
726 FIELD(HOST_IDTR_BASE, host_idtr_base),
727 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
728 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
729 FIELD(HOST_RSP, host_rsp),
730 FIELD(HOST_RIP, host_rip),
731};
22bd0358
NHE		 732
733static inline short vmcs_field_to_offset(unsigned long field)
734{
a2ae9df7
PB		 735 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
736
737 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
738 vmcs_field_to_offset_table[field] == 0)
739 return -ENOENT;
740
22bd0358
NHE		 741 return vmcs_field_to_offset_table[field];
742}
743
a9d30f33
NHE		 744static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
745{
746 return to_vmx(vcpu)->nested.current_vmcs12;
747}
748
749static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
750{
751 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 752 if (is_error_page(page))
a9d30f33 753 return NULL;
32cad84f 754
a9d30f33
NHE		 755 return page;
756}
757
758static void nested_release_page(struct page *page)
759{
760 kvm_release_page_dirty(page);
761}
762
763static void nested_release_page_clean(struct page *page)
764{
765 kvm_release_page_clean(page);
766}
767
bfd0a56b 768static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 769static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 770static void kvm_cpu_vmxon(u64 addr);
771static void kvm_cpu_vmxoff(void);
93c4adc7 772static bool vmx_mpx_supported(void);
f53cd63c 773static bool vmx_xsaves_supported(void);
776e58ea 774static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 775static void vmx_set_segment(struct kvm_vcpu *vcpu,
776 struct kvm_segment *var, int seg);
777static void vmx_get_segment(struct kvm_vcpu *vcpu,
778 struct kvm_segment *var, int seg);
d99e4152
GN		 779static bool guest_state_valid(struct kvm_vcpu *vcpu);
780static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 781static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 782static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 783static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 784static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 785
6aa8b732
AK		 786static DEFINE_PER_CPU(struct vmcs *, vmxarea);
787static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 788/*
789 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
790 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
791 */
792static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 793static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 794
3e7c73e9
AK		 795static unsigned long *vmx_io_bitmap_a;
796static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 797static unsigned long *vmx_msr_bitmap_legacy;
798static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 799static unsigned long *vmx_msr_bitmap_legacy_x2apic;
800static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 801static unsigned long *vmx_vmread_bitmap;
802static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 803
110312c8 804static bool cpu_has_load_ia32_efer;
8bf00a52 805static bool cpu_has_load_perf_global_ctrl;
110312c8 806
2384d2b3
SY		 807static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
808static DEFINE_SPINLOCK(vmx_vpid_lock);
809
1c3d14fe 810static struct vmcs_config {
6aa8b732
AK		 811 int size;
812 int order;
813 u32 revision_id;
1c3d14fe
YS		 814 u32 pin_based_exec_ctrl;
815 u32 cpu_based_exec_ctrl;
f78e0e2e 816 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 817 u32 vmexit_ctrl;
818 u32 vmentry_ctrl;
819} vmcs_config;
6aa8b732 820
efff9e53 821static struct vmx_capability {
d56f546d
SY		 822 u32 ept;
823 u32 vpid;
824} vmx_capability;
825
6aa8b732
AK		 826#define VMX_SEGMENT_FIELD(seg) \
827 [VCPU_SREG_##seg] = { \
828 .selector = GUEST_##seg##_SELECTOR, \
829 .base = GUEST_##seg##_BASE, \
830 .limit = GUEST_##seg##_LIMIT, \
831 .ar_bytes = GUEST_##seg##_AR_BYTES, \
832 }
833
772e0318 834static const struct kvm_vmx_segment_field {
6aa8b732
AK		 835 unsigned selector;
836 unsigned base;
837 unsigned limit;
838 unsigned ar_bytes;
839} kvm_vmx_segment_fields[] = {
840 VMX_SEGMENT_FIELD(CS),
841 VMX_SEGMENT_FIELD(DS),
842 VMX_SEGMENT_FIELD(ES),
843 VMX_SEGMENT_FIELD(FS),
844 VMX_SEGMENT_FIELD(GS),
845 VMX_SEGMENT_FIELD(SS),
846 VMX_SEGMENT_FIELD(TR),
847 VMX_SEGMENT_FIELD(LDTR),
848};
849
26bb0981
AK		 850static u64 host_efer;
851
6de4f3ad
AK		 852static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
853
4d56c8a7 854/*
8c06585d 855 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 856 * away by decrementing the array size.
857 */
6aa8b732 858static const u32 vmx_msr_index[] = {
05b3e0c2 859#ifdef CONFIG_X86_64
44ea2b17 860 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 861#endif
8c06585d 862 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 863};
6aa8b732 864
31299944 865static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 866{
867 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
868 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 869 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 870}
871
31299944 872static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 873{
874 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
875 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 876 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 877}
878
31299944 879static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 880{
881 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
882 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 883 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 884}
885
31299944 886static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 887{
888 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
889 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
890}
891
31299944 892static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 893{
894 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
895 INTR_INFO_VALID_MASK)) ==
896 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
897}
898
31299944 899static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 900{
04547156 901 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 902}
903
31299944 904static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 905{
04547156 906 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 907}
908
31299944 909static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 910{
04547156 911 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 912}
913
31299944 914static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 915{
04547156
SY		 916 return vmcs_config.cpu_based_exec_ctrl &
917 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 918}
919
774ead3a 920static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 921{
04547156
SY		 922 return vmcs_config.cpu_based_2nd_exec_ctrl &
923 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
924}
925
8d14695f
YZ		 926static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
927{
928 return vmcs_config.cpu_based_2nd_exec_ctrl &
929 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
930}
931
83d4c286
YZ		 932static inline bool cpu_has_vmx_apic_register_virt(void)
933{
934 return vmcs_config.cpu_based_2nd_exec_ctrl &
935 SECONDARY_EXEC_APIC_REGISTER_VIRT;
936}
937
c7c9c56c
YZ		 938static inline bool cpu_has_vmx_virtual_intr_delivery(void)
939{
940 return vmcs_config.cpu_based_2nd_exec_ctrl &
941 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
942}
943
01e439be
YZ		 944static inline bool cpu_has_vmx_posted_intr(void)
945{
946 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
947}
948
949static inline bool cpu_has_vmx_apicv(void)
950{
951 return cpu_has_vmx_apic_register_virt() &&
952 cpu_has_vmx_virtual_intr_delivery() &&
953 cpu_has_vmx_posted_intr();
954}
955
04547156
SY		 956static inline bool cpu_has_vmx_flexpriority(void)
957{
958 return cpu_has_vmx_tpr_shadow() &&
959 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 960}
961
e799794e
MT		 962static inline bool cpu_has_vmx_ept_execute_only(void)
963{
31299944 964 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 965}
966
967static inline bool cpu_has_vmx_eptp_uncacheable(void)
968{
31299944 969 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 970}
971
972static inline bool cpu_has_vmx_eptp_writeback(void)
973{
31299944 974 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 975}
976
977static inline bool cpu_has_vmx_ept_2m_page(void)
978{
31299944 979 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 980}
981
878403b7
SY		 982static inline bool cpu_has_vmx_ept_1g_page(void)
983{
31299944 984 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 985}
986
4bc9b982
SY		 987static inline bool cpu_has_vmx_ept_4levels(void)
988{
989 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
990}
991
83c3a331
XH		 992static inline bool cpu_has_vmx_ept_ad_bits(void)
993{
994 return vmx_capability.ept & VMX_EPT_AD_BIT;
995}
996
31299944 997static inline bool cpu_has_vmx_invept_context(void)
d56f546d 998{
31299944 999 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1000}
1001
31299944 1002static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1003{
31299944 1004 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1005}
1006
518c8aee
GJ		 1007static inline bool cpu_has_vmx_invvpid_single(void)
1008{
1009 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1010}
1011
b9d762fa
GJ		 1012static inline bool cpu_has_vmx_invvpid_global(void)
1013{
1014 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1015}
1016
31299944 1017static inline bool cpu_has_vmx_ept(void)
d56f546d 1018{
04547156
SY		 1019 return vmcs_config.cpu_based_2nd_exec_ctrl &
1020 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1021}
1022
31299944 1023static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1024{
1025 return vmcs_config.cpu_based_2nd_exec_ctrl &
1026 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1027}
1028
31299944 1029static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1030{
1031 return vmcs_config.cpu_based_2nd_exec_ctrl &
1032 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1033}
1034
31299944 1035static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1036{
6d3e435e 1037 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1038}
1039
31299944 1040static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1041{
04547156
SY		 1042 return vmcs_config.cpu_based_2nd_exec_ctrl &
1043 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1044}
1045
31299944 1046static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1047{
1048 return vmcs_config.cpu_based_2nd_exec_ctrl &
1049 SECONDARY_EXEC_RDTSCP;
1050}
1051
ad756a16
MJ		 1052static inline bool cpu_has_vmx_invpcid(void)
1053{
1054 return vmcs_config.cpu_based_2nd_exec_ctrl &
1055 SECONDARY_EXEC_ENABLE_INVPCID;
1056}
1057
31299944 1058static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1059{
1060 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1061}
1062
f5f48ee1
SY		 1063static inline bool cpu_has_vmx_wbinvd_exit(void)
1064{
1065 return vmcs_config.cpu_based_2nd_exec_ctrl &
1066 SECONDARY_EXEC_WBINVD_EXITING;
1067}
1068
abc4fc58
AG		 1069static inline bool cpu_has_vmx_shadow_vmcs(void)
1070{
1071 u64 vmx_msr;
1072 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1073 /* check if the cpu supports writing r/o exit information fields */
1074 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1075 return false;
1076
1077 return vmcs_config.cpu_based_2nd_exec_ctrl &
1078 SECONDARY_EXEC_SHADOW_VMCS;
1079}
1080
04547156
SY		 1081static inline bool report_flexpriority(void)
1082{
1083 return flexpriority_enabled;
1084}
1085
fe3ef05c
NHE		 1086static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1087{
1088 return vmcs12->cpu_based_vm_exec_control & bit;
1089}
1090
1091static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1092{
1093 return (vmcs12->cpu_based_vm_exec_control &
1094 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1095 (vmcs12->secondary_vm_exec_control & bit);
1096}
1097
f5c4368f 1098static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1099{
1100 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1101}
1102
f4124500
JK		 1103static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1104{
1105 return vmcs12->pin_based_vm_exec_control &
1106 PIN_BASED_VMX_PREEMPTION_TIMER;
1107}
1108
155a97a3
NHE		 1109static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1110{
1111 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1112}
1113
81dc01f7
WL		 1114static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1115{
1116 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1117 vmx_xsaves_supported();
1118}
1119
644d711a
NHE		 1120static inline bool is_exception(u32 intr_info)
1121{
1122 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1123 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1124}
1125
533558bc
JK		 1126static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1127 u32 exit_intr_info,
1128 unsigned long exit_qualification);
7c177938
NHE		 1129static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1130 struct vmcs12 *vmcs12,
1131 u32 reason, unsigned long qualification);
1132
8b9cf98c 1133static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1134{
1135 int i;
1136
a2fa3e9f 1137 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1138 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1139 return i;
1140 return -1;
1141}
1142
2384d2b3
SY		 1143static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1144{
1145 struct {
1146 u64 vpid : 16;
1147 u64 rsvd : 48;
1148 u64 gva;
1149 } operand = { vpid, 0, gva };
1150
4ecac3fd 1151 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1152 /* CF==1 or ZF==1 --> rc = -1 */
1153 "; ja 1f ; ud2 ; 1:"
1154 : : "a"(&operand), "c"(ext) : "cc", "memory");
1155}
1156
1439442c
SY		 1157static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1158{
1159 struct {
1160 u64 eptp, gpa;
1161 } operand = {eptp, gpa};
1162
4ecac3fd 1163 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1164 /* CF==1 or ZF==1 --> rc = -1 */
1165 "; ja 1f ; ud2 ; 1:\n"
1166 : : "a" (&operand), "c" (ext) : "cc", "memory");
1167}
1168
26bb0981 1169static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1170{
1171 int i;
1172
8b9cf98c 1173 i = __find_msr_index(vmx, msr);
a75beee6 1174 if (i >= 0)
a2fa3e9f 1175 return &vmx->guest_msrs[i];
8b6d44c7 1176 return NULL;
7725f0ba
AK		 1177}
1178
6aa8b732
AK		 1179static void vmcs_clear(struct vmcs *vmcs)
1180{
1181 u64 phys_addr = __pa(vmcs);
1182 u8 error;
1183
4ecac3fd 1184 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1185 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1186 : "cc", "memory");
1187 if (error)
1188 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1189 vmcs, phys_addr);
1190}
1191
d462b819
NHE		 1192static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1193{
1194 vmcs_clear(loaded_vmcs->vmcs);
1195 loaded_vmcs->cpu = -1;
1196 loaded_vmcs->launched = 0;
1197}
1198
7725b894
DX		 1199static void vmcs_load(struct vmcs *vmcs)
1200{
1201 u64 phys_addr = __pa(vmcs);
1202 u8 error;
1203
1204 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1205 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1206 : "cc", "memory");
1207 if (error)
2844d849 1208 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1209 vmcs, phys_addr);
1210}
1211
8f536b76
ZY		 1212#ifdef CONFIG_KEXEC
1213/*
1214 * This bitmap is used to indicate whether the vmclear
1215 * operation is enabled on all cpus. All disabled by
1216 * default.
1217 */
1218static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1219
1220static inline void crash_enable_local_vmclear(int cpu)
1221{
1222 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1223}
1224
1225static inline void crash_disable_local_vmclear(int cpu)
1226{
1227 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1228}
1229
1230static inline int crash_local_vmclear_enabled(int cpu)
1231{
1232 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1233}
1234
1235static void crash_vmclear_local_loaded_vmcss(void)
1236{
1237 int cpu = raw_smp_processor_id();
1238 struct loaded_vmcs *v;
1239
1240 if (!crash_local_vmclear_enabled(cpu))
1241 return;
1242
1243 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1244 loaded_vmcss_on_cpu_link)
1245 vmcs_clear(v->vmcs);
1246}
1247#else
1248static inline void crash_enable_local_vmclear(int cpu) { }
1249static inline void crash_disable_local_vmclear(int cpu) { }
1250#endif /* CONFIG_KEXEC */
1251
d462b819 1252static void __loaded_vmcs_clear(void *arg)
6aa8b732 1253{
d462b819 1254 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1255 int cpu = raw_smp_processor_id();
6aa8b732 1256
d462b819
NHE		 1257 if (loaded_vmcs->cpu != cpu)
1258 return; /* vcpu migration can race with cpu offline */
1259 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1260 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1261 crash_disable_local_vmclear(cpu);
d462b819 1262 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1263
1264 /*
1265 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1266 * is before setting loaded_vmcs->vcpu to -1 which is done in
1267 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1268 * then adds the vmcs into percpu list before it is deleted.
1269 */
1270 smp_wmb();
1271
d462b819 1272 loaded_vmcs_init(loaded_vmcs);
8f536b76 1273 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1274}
1275
d462b819 1276static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1277{
e6c7d321
XG		 1278 int cpu = loaded_vmcs->cpu;
1279
1280 if (cpu != -1)
1281 smp_call_function_single(cpu,
1282 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1283}
1284
1760dd49 1285static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1286{
1287 if (vmx->vpid == 0)
1288 return;
1289
518c8aee
GJ		 1290 if (cpu_has_vmx_invvpid_single())
1291 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1292}
1293
b9d762fa
GJ		 1294static inline void vpid_sync_vcpu_global(void)
1295{
1296 if (cpu_has_vmx_invvpid_global())
1297 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1298}
1299
1300static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1301{
1302 if (cpu_has_vmx_invvpid_single())
1760dd49 1303 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1304 else
1305 vpid_sync_vcpu_global();
1306}
1307
1439442c
SY		 1308static inline void ept_sync_global(void)
1309{
1310 if (cpu_has_vmx_invept_global())
1311 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1312}
1313
1314static inline void ept_sync_context(u64 eptp)
1315{
089d034e 1316 if (enable_ept) {
1439442c
SY		 1317 if (cpu_has_vmx_invept_context())
1318 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1319 else
1320 ept_sync_global();
1321 }
1322}
1323
96304217 1324static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1325{
5e520e62 1326 unsigned long value;
6aa8b732 1327
5e520e62
AK		 1328 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1329 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1330 return value;
1331}
1332
96304217 1333static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1334{
1335 return vmcs_readl(field);
1336}
1337
96304217 1338static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1339{
1340 return vmcs_readl(field);
1341}
1342
96304217 1343static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1344{
05b3e0c2 1345#ifdef CONFIG_X86_64
6aa8b732
AK		 1346 return vmcs_readl(field);
1347#else
1348 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1349#endif
1350}
1351
e52de1b8
AK		 1352static noinline void vmwrite_error(unsigned long field, unsigned long value)
1353{
1354 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1355 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1356 dump_stack();
1357}
1358
6aa8b732
AK		 1359static void vmcs_writel(unsigned long field, unsigned long value)
1360{
1361 u8 error;
1362
4ecac3fd 1363 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1364 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1365 if (unlikely(error))
1366 vmwrite_error(field, value);
6aa8b732
AK		 1367}
1368
1369static void vmcs_write16(unsigned long field, u16 value)
1370{
1371 vmcs_writel(field, value);
1372}
1373
1374static void vmcs_write32(unsigned long field, u32 value)
1375{
1376 vmcs_writel(field, value);
1377}
1378
1379static void vmcs_write64(unsigned long field, u64 value)
1380{
6aa8b732 1381 vmcs_writel(field, value);
7682f2d0 1382#ifndef CONFIG_X86_64
6aa8b732
AK		 1383 asm volatile ("");
1384 vmcs_writel(field+1, value >> 32);
1385#endif
1386}
1387
2ab455cc
AL		 1388static void vmcs_clear_bits(unsigned long field, u32 mask)
1389{
1390 vmcs_writel(field, vmcs_readl(field) & ~mask);
1391}
1392
1393static void vmcs_set_bits(unsigned long field, u32 mask)
1394{
1395 vmcs_writel(field, vmcs_readl(field) | mask);
1396}
1397
2961e876
GN		 1398static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1399{
1400 vmcs_write32(VM_ENTRY_CONTROLS, val);
1401 vmx->vm_entry_controls_shadow = val;
1402}
1403
1404static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1405{
1406 if (vmx->vm_entry_controls_shadow != val)
1407 vm_entry_controls_init(vmx, val);
1408}
1409
1410static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1411{
1412 return vmx->vm_entry_controls_shadow;
1413}
1414
1415
1416static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1417{
1418 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1419}
1420
1421static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1422{
1423 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1424}
1425
1426static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1427{
1428 vmcs_write32(VM_EXIT_CONTROLS, val);
1429 vmx->vm_exit_controls_shadow = val;
1430}
1431
1432static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1433{
1434 if (vmx->vm_exit_controls_shadow != val)
1435 vm_exit_controls_init(vmx, val);
1436}
1437
1438static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1439{
1440 return vmx->vm_exit_controls_shadow;
1441}
1442
1443
1444static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1445{
1446 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1447}
1448
1449static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1450{
1451 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1452}
1453
2fb92db1
AK		 1454static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1455{
1456 vmx->segment_cache.bitmask = 0;
1457}
1458
1459static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1460 unsigned field)
1461{
1462 bool ret;
1463 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1464
1465 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1466 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1467 vmx->segment_cache.bitmask = 0;
1468 }
1469 ret = vmx->segment_cache.bitmask & mask;
1470 vmx->segment_cache.bitmask |= mask;
1471 return ret;
1472}
1473
1474static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1475{
1476 u16 *p = &vmx->segment_cache.seg[seg].selector;
1477
1478 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1479 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1480 return *p;
1481}
1482
1483static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1484{
1485 ulong *p = &vmx->segment_cache.seg[seg].base;
1486
1487 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1488 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1489 return *p;
1490}
1491
1492static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1493{
1494 u32 *p = &vmx->segment_cache.seg[seg].limit;
1495
1496 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1497 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1498 return *p;
1499}
1500
1501static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1502{
1503 u32 *p = &vmx->segment_cache.seg[seg].ar;
1504
1505 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1506 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1507 return *p;
1508}
1509
abd3f2d6
AK		 1510static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1511{
1512 u32 eb;
1513
fd7373cc
JK		 1514 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1515 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1516 if ((vcpu->guest_debug &
1517 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1518 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1519 eb |= 1u << BP_VECTOR;
7ffd92c5 1520 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1521 eb = ~0;
089d034e 1522 if (enable_ept)
1439442c 1523 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1524 if (vcpu->fpu_active)
1525 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1526
1527 /* When we are running a nested L2 guest and L1 specified for it a
1528 * certain exception bitmap, we must trap the same exceptions and pass
1529 * them to L1. When running L2, we will only handle the exceptions
1530 * specified above if L1 did not want them.
1531 */
1532 if (is_guest_mode(vcpu))
1533 eb |= get_vmcs12(vcpu)->exception_bitmap;
1534
abd3f2d6
AK		 1535 vmcs_write32(EXCEPTION_BITMAP, eb);
1536}
1537
2961e876
GN		 1538static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1539 unsigned long entry, unsigned long exit)
8bf00a52 1540{
2961e876
GN		 1541 vm_entry_controls_clearbit(vmx, entry);
1542 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1543}
1544
61d2ef2c
AK		 1545static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1546{
1547 unsigned i;
1548 struct msr_autoload *m = &vmx->msr_autoload;
1549
8bf00a52
GN		 1550 switch (msr) {
1551 case MSR_EFER:
1552 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1553 clear_atomic_switch_msr_special(vmx,
1554 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1555 VM_EXIT_LOAD_IA32_EFER);
1556 return;
1557 }
1558 break;
1559 case MSR_CORE_PERF_GLOBAL_CTRL:
1560 if (cpu_has_load_perf_global_ctrl) {
2961e876 1561 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1562 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1563 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1564 return;
1565 }
1566 break;
110312c8
AK		 1567 }
1568
61d2ef2c
AK		 1569 for (i = 0; i < m->nr; ++i)
1570 if (m->guest[i].index == msr)
1571 break;
1572
1573 if (i == m->nr)
1574 return;
1575 --m->nr;
1576 m->guest[i] = m->guest[m->nr];
1577 m->host[i] = m->host[m->nr];
1578 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1579 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1580}
1581
2961e876
GN		 1582static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1583 unsigned long entry, unsigned long exit,
1584 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1585 u64 guest_val, u64 host_val)
8bf00a52
GN		 1586{
1587 vmcs_write64(guest_val_vmcs, guest_val);
1588 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1589 vm_entry_controls_setbit(vmx, entry);
1590 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1591}
1592
61d2ef2c
AK		 1593static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1594 u64 guest_val, u64 host_val)
1595{
1596 unsigned i;
1597 struct msr_autoload *m = &vmx->msr_autoload;
1598
8bf00a52
GN		 1599 switch (msr) {
1600 case MSR_EFER:
1601 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1602 add_atomic_switch_msr_special(vmx,
1603 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1604 VM_EXIT_LOAD_IA32_EFER,
1605 GUEST_IA32_EFER,
1606 HOST_IA32_EFER,
1607 guest_val, host_val);
1608 return;
1609 }
1610 break;
1611 case MSR_CORE_PERF_GLOBAL_CTRL:
1612 if (cpu_has_load_perf_global_ctrl) {
2961e876 1613 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1614 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1615 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1616 GUEST_IA32_PERF_GLOBAL_CTRL,
1617 HOST_IA32_PERF_GLOBAL_CTRL,
1618 guest_val, host_val);
1619 return;
1620 }
1621 break;
110312c8
AK		 1622 }
1623
61d2ef2c
AK		 1624 for (i = 0; i < m->nr; ++i)
1625 if (m->guest[i].index == msr)
1626 break;
1627
e7fc6f93 1628 if (i == NR_AUTOLOAD_MSRS) {
60266204 1629 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1630 "Can't add msr %x\n", msr);
1631 return;
1632 } else if (i == m->nr) {
61d2ef2c
AK		 1633 ++m->nr;
1634 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1635 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1636 }
1637
1638 m->guest[i].index = msr;
1639 m->guest[i].value = guest_val;
1640 m->host[i].index = msr;
1641 m->host[i].value = host_val;
1642}
1643
33ed6329
AK		 1644static void reload_tss(void)
1645{
33ed6329
AK		 1646 /*
1647 * VT restores TR but not its size. Useless.
1648 */
89cbc767 1649 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1650 struct desc_struct *descs;
33ed6329 1651
d359192f 1652 descs = (void *)gdt->address;
33ed6329
AK		 1653 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1654 load_TR_desc();
33ed6329
AK		 1655}
1656
92c0d900 1657static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1658{
3a34a881 1659 u64 guest_efer;
51c6cf66
AK		 1660 u64 ignore_bits;
1661
f6801dff 1662 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1663
51c6cf66 1664 /*
0fa06071 1665 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1666 * outside long mode
1667 */
1668 ignore_bits = EFER_NX | EFER_SCE;
1669#ifdef CONFIG_X86_64
1670 ignore_bits |= EFER_LMA | EFER_LME;
1671 /* SCE is meaningful only in long mode on Intel */
1672 if (guest_efer & EFER_LMA)
1673 ignore_bits &= ~(u64)EFER_SCE;
1674#endif
51c6cf66
AK		 1675 guest_efer &= ~ignore_bits;
1676 guest_efer |= host_efer & ignore_bits;
26bb0981 1677 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1678 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1679
1680 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1681
1682 /*
1683 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1684 * On CPUs that support "load IA32_EFER", always switch EFER
1685 * atomically, since it's faster than switching it manually.
1686 */
1687 if (cpu_has_load_ia32_efer ||
1688 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1689 guest_efer = vmx->vcpu.arch.efer;
1690 if (!(guest_efer & EFER_LMA))
1691 guest_efer &= ~EFER_LME;
54b98bff
AL		 1692 if (guest_efer != host_efer)
1693 add_atomic_switch_msr(vmx, MSR_EFER,
1694 guest_efer, host_efer);
84ad33ef
AK		 1695 return false;
1696 }
1697
26bb0981 1698 return true;
51c6cf66
AK		 1699}
1700
2d49ec72
GN		 1701static unsigned long segment_base(u16 selector)
1702{
89cbc767 1703 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1704 struct desc_struct *d;
1705 unsigned long table_base;
1706 unsigned long v;
1707
1708 if (!(selector & ~3))
1709 return 0;
1710
d359192f 1711 table_base = gdt->address;
2d49ec72
GN		 1712
1713 if (selector & 4) { /* from ldt */
1714 u16 ldt_selector = kvm_read_ldt();
1715
1716 if (!(ldt_selector & ~3))
1717 return 0;
1718
1719 table_base = segment_base(ldt_selector);
1720 }
1721 d = (struct desc_struct *)(table_base + (selector & ~7));
1722 v = get_desc_base(d);
1723#ifdef CONFIG_X86_64
1724 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1725 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1726#endif
1727 return v;
1728}
1729
1730static inline unsigned long kvm_read_tr_base(void)
1731{
1732 u16 tr;
1733 asm("str %0" : "=g"(tr));
1734 return segment_base(tr);
1735}
1736
04d2cc77 1737static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1738{
04d2cc77 1739 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1740 int i;
04d2cc77 1741
a2fa3e9f 1742 if (vmx->host_state.loaded)
33ed6329
AK		 1743 return;
1744
a2fa3e9f 1745 vmx->host_state.loaded = 1;
33ed6329
AK		 1746 /*
1747 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1748 * allow segment selectors with cpl > 0 or ti == 1.
1749 */
d6e88aec 1750 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1751 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1752 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1753 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1754 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1755 vmx->host_state.fs_reload_needed = 0;
1756 } else {
33ed6329 1757 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1758 vmx->host_state.fs_reload_needed = 1;
33ed6329 1759 }
9581d442 1760 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1761 if (!(vmx->host_state.gs_sel & 7))
1762 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1763 else {
1764 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1765 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1766 }
1767
b2da15ac
AK		 1768#ifdef CONFIG_X86_64
1769 savesegment(ds, vmx->host_state.ds_sel);
1770 savesegment(es, vmx->host_state.es_sel);
1771#endif
1772
33ed6329
AK		 1773#ifdef CONFIG_X86_64
1774 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1775 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1776#else
a2fa3e9f
GH		 1777 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1778 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1779#endif
707c0874
AK		 1780
1781#ifdef CONFIG_X86_64
c8770e7b
AK		 1782 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1783 if (is_long_mode(&vmx->vcpu))
44ea2b17 1784 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1785#endif
da8999d3
LJ		 1786 if (boot_cpu_has(X86_FEATURE_MPX))
1787 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1788 for (i = 0; i < vmx->save_nmsrs; ++i)
1789 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1790 vmx->guest_msrs[i].data,
1791 vmx->guest_msrs[i].mask);
33ed6329
AK		 1792}
1793
a9b21b62 1794static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1795{
a2fa3e9f 1796 if (!vmx->host_state.loaded)
33ed6329
AK		 1797 return;
1798
e1beb1d3 1799 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1800 vmx->host_state.loaded = 0;
c8770e7b
AK		 1801#ifdef CONFIG_X86_64
1802 if (is_long_mode(&vmx->vcpu))
1803 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1804#endif
152d3f2f 1805 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1806 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1807#ifdef CONFIG_X86_64
9581d442 1808 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1809#else
1810 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1811#endif
33ed6329 1812 }
0a77fe4c
AK		 1813 if (vmx->host_state.fs_reload_needed)
1814 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1815#ifdef CONFIG_X86_64
1816 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1817 loadsegment(ds, vmx->host_state.ds_sel);
1818 loadsegment(es, vmx->host_state.es_sel);
1819 }
b2da15ac 1820#endif
152d3f2f 1821 reload_tss();
44ea2b17 1822#ifdef CONFIG_X86_64
c8770e7b 1823 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1824#endif
da8999d3
LJ		 1825 if (vmx->host_state.msr_host_bndcfgs)
1826 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1827 /*
1828 * If the FPU is not active (through the host task or
1829 * the guest vcpu), then restore the cr0.TS bit.
1830 */
1831 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1832 stts();
89cbc767 1833 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1834}
1835
a9b21b62
AK		 1836static void vmx_load_host_state(struct vcpu_vmx *vmx)
1837{
1838 preempt_disable();
1839 __vmx_load_host_state(vmx);
1840 preempt_enable();
1841}
1842
6aa8b732
AK		 1843/*
1844 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1845 * vcpu mutex is already taken.
1846 */
15ad7146 1847static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1848{
a2fa3e9f 1849 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1850 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1851
4610c9cc
DX		 1852 if (!vmm_exclusive)
1853 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1854 else if (vmx->loaded_vmcs->cpu != cpu)
1855 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1856
d462b819
NHE		 1857 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1858 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1859 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1860 }
1861
d462b819 1862 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1863 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1864 unsigned long sysenter_esp;
1865
a8eeb04a 1866 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1867 local_irq_disable();
8f536b76 1868 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1869
1870 /*
1871 * Read loaded_vmcs->cpu should be before fetching
1872 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1873 * See the comments in __loaded_vmcs_clear().
1874 */
1875 smp_rmb();
1876
d462b819
NHE		 1877 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1878 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1879 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1880 local_irq_enable();
1881
6aa8b732
AK		 1882 /*
1883 * Linux uses per-cpu TSS and GDT, so set these when switching
1884 * processors.
1885 */
d6e88aec 1886 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1887 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1888
1889 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1890 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1891 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1892 }
6aa8b732
AK		 1893}
1894
1895static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1896{
a9b21b62 1897 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1898 if (!vmm_exclusive) {
d462b819
NHE		 1899 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1900 vcpu->cpu = -1;
4610c9cc
DX		 1901 kvm_cpu_vmxoff();
1902 }
6aa8b732
AK		 1903}
1904
5fd86fcf
AK		 1905static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1906{
81231c69
AK		 1907 ulong cr0;
1908
5fd86fcf
AK		 1909 if (vcpu->fpu_active)
1910 return;
1911 vcpu->fpu_active = 1;
81231c69
AK		 1912 cr0 = vmcs_readl(GUEST_CR0);
1913 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1914 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1915 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1916 update_exception_bitmap(vcpu);
edcafe3c 1917 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1918 if (is_guest_mode(vcpu))
1919 vcpu->arch.cr0_guest_owned_bits &=
1920 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1921 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1922}
1923
edcafe3c
AK		 1924static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1925
fe3ef05c
NHE		 1926/*
1927 * Return the cr0 value that a nested guest would read. This is a combination
1928 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1929 * its hypervisor (cr0_read_shadow).
1930 */
1931static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1932{
1933 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1934 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1935}
1936static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1937{
1938 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1939 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1940}
1941
5fd86fcf
AK		 1942static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1943{
36cf24e0
NHE		 1944 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1945 * set this *before* calling this function.
1946 */
edcafe3c 1947 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1948 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1949 update_exception_bitmap(vcpu);
edcafe3c
AK		 1950 vcpu->arch.cr0_guest_owned_bits = 0;
1951 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1952 if (is_guest_mode(vcpu)) {
1953 /*
1954 * L1's specified read shadow might not contain the TS bit,
1955 * so now that we turned on shadowing of this bit, we need to
1956 * set this bit of the shadow. Like in nested_vmx_run we need
1957 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1958 * up-to-date here because we just decached cr0.TS (and we'll
1959 * only update vmcs12->guest_cr0 on nested exit).
1960 */
1961 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1962 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1963 (vcpu->arch.cr0 & X86_CR0_TS);
1964 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1965 } else
1966 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1967}
1968
6aa8b732
AK		 1969static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1970{
78ac8b47 1971 unsigned long rflags, save_rflags;
345dcaa8 1972
6de12732
AK		 1973 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1974 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1975 rflags = vmcs_readl(GUEST_RFLAGS);
1976 if (to_vmx(vcpu)->rmode.vm86_active) {
1977 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1978 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1979 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1980 }
1981 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1982 }
6de12732 1983 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1984}
1985
1986static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1987{
6de12732
AK		 1988 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1989 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1990 if (to_vmx(vcpu)->rmode.vm86_active) {
1991 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1992 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1993 }
6aa8b732
AK		 1994 vmcs_writel(GUEST_RFLAGS, rflags);
1995}
1996
37ccdcbe 1997static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1998{
1999 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2000 int ret = 0;
2001
2002 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2003 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2004 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2005 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2006
37ccdcbe 2007 return ret;
2809f5d2
GC		 2008}
2009
2010static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2011{
2012 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2013 u32 interruptibility = interruptibility_old;
2014
2015 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2016
48005f64 2017 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2018 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2019 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2020 interruptibility |= GUEST_INTR_STATE_STI;
2021
2022 if ((interruptibility != interruptibility_old))
2023 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2024}
2025
6aa8b732
AK		 2026static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2027{
2028 unsigned long rip;
6aa8b732 2029
5fdbf976 2030 rip = kvm_rip_read(vcpu);
6aa8b732 2031 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2032 kvm_rip_write(vcpu, rip);
6aa8b732 2033
2809f5d2
GC		 2034 /* skipping an emulated instruction also counts */
2035 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2036}
2037
0b6ac343
NHE		 2038/*
2039 * KVM wants to inject page-faults which it got to the guest. This function
2040 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2041 */
e011c663 2042static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2043{
2044 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2045
e011c663 2046 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2047 return 0;
2048
533558bc
JK		 2049 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2050 vmcs_read32(VM_EXIT_INTR_INFO),
2051 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2052 return 1;
2053}
2054
298101da 2055static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2056 bool has_error_code, u32 error_code,
2057 bool reinject)
298101da 2058{
77ab6db0 2059 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2060 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2061
e011c663
GN		 2062 if (!reinject && is_guest_mode(vcpu) &&
2063 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2064 return;
2065
8ab2d2e2 2066 if (has_error_code) {
77ab6db0 2067 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2068 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2069 }
77ab6db0 2070
7ffd92c5 2071 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2072 int inc_eip = 0;
2073 if (kvm_exception_is_soft(nr))
2074 inc_eip = vcpu->arch.event_exit_inst_len;
2075 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2076 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2077 return;
2078 }
2079
66fd3f7f
GN		 2080 if (kvm_exception_is_soft(nr)) {
2081 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2082 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2083 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2084 } else
2085 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2086
2087 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2088}
2089
4e47c7a6
SY		 2090static bool vmx_rdtscp_supported(void)
2091{
2092 return cpu_has_vmx_rdtscp();
2093}
2094
ad756a16
MJ		 2095static bool vmx_invpcid_supported(void)
2096{
2097 return cpu_has_vmx_invpcid() && enable_ept;
2098}
2099
a75beee6
ED		 2100/*
2101 * Swap MSR entry in host/guest MSR entry array.
2102 */
8b9cf98c 2103static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2104{
26bb0981 2105 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2106
2107 tmp = vmx->guest_msrs[to];
2108 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2109 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2110}
2111
8d14695f
YZ		 2112static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2113{
2114 unsigned long *msr_bitmap;
2115
2116 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2117 if (is_long_mode(vcpu))
2118 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2119 else
2120 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2121 } else {
2122 if (is_long_mode(vcpu))
2123 msr_bitmap = vmx_msr_bitmap_longmode;
2124 else
2125 msr_bitmap = vmx_msr_bitmap_legacy;
2126 }
2127
2128 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2129}
2130
e38aea3e
AK		 2131/*
2132 * Set up the vmcs to automatically save and restore system
2133 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2134 * mode, as fiddling with msrs is very expensive.
2135 */
8b9cf98c 2136static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2137{
26bb0981 2138 int save_nmsrs, index;
e38aea3e 2139
a75beee6
ED		 2140 save_nmsrs = 0;
2141#ifdef CONFIG_X86_64
8b9cf98c 2142 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2143 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2144 if (index >= 0)
8b9cf98c
RR		 2145 move_msr_up(vmx, index, save_nmsrs++);
2146 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2147 if (index >= 0)
8b9cf98c
RR		 2148 move_msr_up(vmx, index, save_nmsrs++);
2149 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2150 if (index >= 0)
8b9cf98c 2151 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2152 index = __find_msr_index(vmx, MSR_TSC_AUX);
2153 if (index >= 0 && vmx->rdtscp_enabled)
2154 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2155 /*
8c06585d 2156 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2157 * if efer.sce is enabled.
2158 */
8c06585d 2159 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2160 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2161 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2162 }
2163#endif
92c0d900
AK		 2164 index = __find_msr_index(vmx, MSR_EFER);
2165 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2166 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2167
26bb0981 2168 vmx->save_nmsrs = save_nmsrs;
5897297b 2169
8d14695f
YZ		 2170 if (cpu_has_vmx_msr_bitmap())
2171 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2172}
2173
6aa8b732
AK		 2174/*
2175 * reads and returns guest's timestamp counter "register"
2176 * guest_tsc = host_tsc + tsc_offset -- 21.3
2177 */
2178static u64 guest_read_tsc(void)
2179{
2180 u64 host_tsc, tsc_offset;
2181
2182 rdtscll(host_tsc);
2183 tsc_offset = vmcs_read64(TSC_OFFSET);
2184 return host_tsc + tsc_offset;
2185}
2186
d5c1785d
NHE		 2187/*
2188 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2189 * counter, even if a nested guest (L2) is currently running.
2190 */
48d89b92 2191static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2192{
886b470c 2193 u64 tsc_offset;
d5c1785d 2194
d5c1785d
NHE		 2195 tsc_offset = is_guest_mode(vcpu) ?
2196 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2197 vmcs_read64(TSC_OFFSET);
2198 return host_tsc + tsc_offset;
2199}
2200
4051b188 2201/*
cc578287
ZA		 2202 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2203 * software catchup for faster rates on slower CPUs.
4051b188 2204 */
cc578287 2205static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2206{
cc578287
ZA		 2207 if (!scale)
2208 return;
2209
2210 if (user_tsc_khz > tsc_khz) {
2211 vcpu->arch.tsc_catchup = 1;
2212 vcpu->arch.tsc_always_catchup = 1;
2213 } else
2214 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2215}
2216
ba904635
WA		 2217static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2218{
2219 return vmcs_read64(TSC_OFFSET);
2220}
2221
6aa8b732 2222/*
99e3e30a 2223 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2224 */
99e3e30a 2225static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2226{
27fc51b2 2227 if (is_guest_mode(vcpu)) {
7991825b 2228 /*
27fc51b2
NHE		 2229 * We're here if L1 chose not to trap WRMSR to TSC. According
2230 * to the spec, this should set L1's TSC; The offset that L1
2231 * set for L2 remains unchanged, and still needs to be added
2232 * to the newly set TSC to get L2's TSC.
7991825b 2233 */
27fc51b2
NHE		 2234 struct vmcs12 *vmcs12;
2235 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2236 /* recalculate vmcs02.TSC_OFFSET: */
2237 vmcs12 = get_vmcs12(vcpu);
2238 vmcs_write64(TSC_OFFSET, offset +
2239 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2240 vmcs12->tsc_offset : 0));
2241 } else {
489223ed
YY		 2242 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2243 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2244 vmcs_write64(TSC_OFFSET, offset);
2245 }
6aa8b732
AK		 2246}
2247
f1e2b260 2248static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2249{
2250 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2251
e48672fa 2252 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2253 if (is_guest_mode(vcpu)) {
2254 /* Even when running L2, the adjustment needs to apply to L1 */
2255 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2256 } else
2257 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2258 offset + adjustment);
e48672fa
ZA		 2259}
2260
857e4099
JR		 2261static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2262{
2263 return target_tsc - native_read_tsc();
2264}
2265
801d3424
NHE		 2266static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2267{
2268 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2269 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2270}
2271
2272/*
2273 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2274 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2275 * all guests if the "nested" module option is off, and can also be disabled
2276 * for a single guest by disabling its VMX cpuid bit.
2277 */
2278static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2279{
2280 return nested && guest_cpuid_has_vmx(vcpu);
2281}
2282
b87a51ae
NHE		 2283/*
2284 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2285 * returned for the various VMX controls MSRs when nested VMX is enabled.
2286 * The same values should also be used to verify that vmcs12 control fields are
2287 * valid during nested entry from L1 to L2.
2288 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2289 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2290 * bit in the high half is on if the corresponding bit in the control field
2291 * may be on. See also vmx_control_verify().
2292 * TODO: allow these variables to be modified (downgraded) by module options
2293 * or other means.
2294 */
2295static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2296static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2297static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2298static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2299static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2300static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2301static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2302static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2303static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2304static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2305static __init void nested_vmx_setup_ctls_msrs(void)
2306{
2307 /*
2308 * Note that as a general rule, the high half of the MSRs (bits in
2309 * the control fields which may be 1) should be initialized by the
2310 * intersection of the underlying hardware's MSR (i.e., features which
2311 * can be supported) and the list of features we want to expose -
2312 * because they are known to be properly supported in our code.
2313 * Also, usually, the low half of the MSRs (bits which must be 1) can
2314 * be set to 0, meaning that L1 may turn off any of these bits. The
2315 * reason is that if one of these bits is necessary, it will appear
2316 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2317 * fields of vmcs01 and vmcs02, will turn these bits off - and
2318 * nested_vmx_exit_handled() will not pass related exits to L1.
2319 * These rules have exceptions below.
2320 */
2321
2322 /* pin-based controls */
eabeaacc
JK		 2323 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2324 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2325 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2326 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2327 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2328 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2329 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2330
3dbcd8da 2331 /* exit controls */
c0dfee58
ACL		 2332 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2333 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2334 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2335
c0dfee58 2336 nested_vmx_exit_ctls_high &=
b87a51ae 2337#ifdef CONFIG_X86_64
c0dfee58 2338 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2339#endif
f4124500
JK		 2340 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2341 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2342 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2343 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2344
36be0b9d
PB		 2345 if (vmx_mpx_supported())
2346 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2347
2996fca0
JK		 2348 /* We support free control of debug control saving. */
2349 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2350 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2351
b87a51ae
NHE		 2352 /* entry controls */
2353 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2354 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2355 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2356 nested_vmx_entry_ctls_high &=
57435349
JK		 2357#ifdef CONFIG_X86_64
2358 VM_ENTRY_IA32E_MODE |
2359#endif
2360 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2361 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2362 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2363 if (vmx_mpx_supported())
2364 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2365
2996fca0
JK		 2366 /* We support free control of debug control loading. */
2367 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2368 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2369
b87a51ae
NHE		 2370 /* cpu-based controls */
2371 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2372 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2373 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2374 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2375 CPU_BASED_VIRTUAL_INTR_PENDING |
2376 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2377 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2378 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2379 CPU_BASED_CR3_STORE_EXITING |
2380#ifdef CONFIG_X86_64
2381 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2382#endif
2383 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2384 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2385 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2386 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2387 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2388 /*
2389 * We can allow some features even when not supported by the
2390 * hardware. For example, L1 can specify an MSR bitmap - and we
2391 * can use it to avoid exits to L1 - even when L0 runs L2
2392 * without MSR bitmaps.
2393 */
560b7ee1
JK		 2394 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2395 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2396
3dcdf3ec
JK		 2397 /* We support free control of CR3 access interception. */
2398 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2399 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2400
b87a51ae
NHE		 2401 /* secondary cpu-based controls */
2402 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2403 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2404 nested_vmx_secondary_ctls_low = 0;
2405 nested_vmx_secondary_ctls_high &=
d6851fbe 2406 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
81dc01f7
WL		 2407 SECONDARY_EXEC_WBINVD_EXITING |
2408 SECONDARY_EXEC_XSAVES;
c18911a2 2409
afa61f75
NHE		 2410 if (enable_ept) {
2411 /* nested EPT: emulate EPT also to L1 */
78051e3b
BD		 2412 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT |
2413 SECONDARY_EXEC_UNRESTRICTED_GUEST;
ca72d970 2414 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2415 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2416 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2417 nested_vmx_ept_caps &= vmx_capability.ept;
2418 /*
4b855078
BD		 2419 * For nested guests, we don't do anything specific
2420 * for single context invalidation. Hence, only advertise
2421 * support for global context invalidation.
afa61f75 2422 */
4b855078 2423 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2424 } else
2425 nested_vmx_ept_caps = 0;
2426
c18911a2
JK		 2427 /* miscellaneous data */
2428 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2429 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2430 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2431 VMX_MISC_ACTIVITY_HLT;
c18911a2 2432 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2433}
2434
2435static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2436{
2437 /*
2438 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2439 */
2440 return ((control & high) | low) == control;
2441}
2442
2443static inline u64 vmx_control_msr(u32 low, u32 high)
2444{
2445 return low | ((u64)high << 32);
2446}
2447
cae50139 2448/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2449static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2450{
b87a51ae 2451 switch (msr_index) {
b87a51ae
NHE		 2452 case MSR_IA32_VMX_BASIC:
2453 /*
2454 * This MSR reports some information about VMX support. We
2455 * should return information about the VMX we emulate for the
2456 * guest, and the VMCS structure we give it - not about the
2457 * VMX support of the underlying hardware.
2458 */
3dbcd8da 2459 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2460 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2461 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2462 break;
2463 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2464 case MSR_IA32_VMX_PINBASED_CTLS:
2465 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2466 nested_vmx_pinbased_ctls_high);
2467 break;
2468 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2469 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2470 nested_vmx_procbased_ctls_high);
2471 break;
b87a51ae
NHE		 2472 case MSR_IA32_VMX_PROCBASED_CTLS:
2473 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2474 nested_vmx_procbased_ctls_high);
2475 break;
2476 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2477 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2478 nested_vmx_exit_ctls_high);
2479 break;
b87a51ae
NHE		 2480 case MSR_IA32_VMX_EXIT_CTLS:
2481 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2482 nested_vmx_exit_ctls_high);
2483 break;
2484 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2485 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2486 nested_vmx_entry_ctls_high);
2487 break;
b87a51ae
NHE		 2488 case MSR_IA32_VMX_ENTRY_CTLS:
2489 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2490 nested_vmx_entry_ctls_high);
2491 break;
2492 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2493 *pdata = vmx_control_msr(nested_vmx_misc_low,
2494 nested_vmx_misc_high);
b87a51ae
NHE		 2495 break;
2496 /*
2497 * These MSRs specify bits which the guest must keep fixed (on or off)
2498 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2499 * We picked the standard core2 setting.
2500 */
2501#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2502#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2503 case MSR_IA32_VMX_CR0_FIXED0:
2504 *pdata = VMXON_CR0_ALWAYSON;
2505 break;
2506 case MSR_IA32_VMX_CR0_FIXED1:
2507 *pdata = -1ULL;
2508 break;
2509 case MSR_IA32_VMX_CR4_FIXED0:
2510 *pdata = VMXON_CR4_ALWAYSON;
2511 break;
2512 case MSR_IA32_VMX_CR4_FIXED1:
2513 *pdata = -1ULL;
2514 break;
2515 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2516 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2517 break;
2518 case MSR_IA32_VMX_PROCBASED_CTLS2:
2519 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2520 nested_vmx_secondary_ctls_high);
2521 break;
2522 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2523 /* Currently, no nested vpid support */
2524 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2525 break;
2526 default:
b87a51ae 2527 return 1;
b3897a49
NHE		 2528 }
2529
b87a51ae
NHE		 2530 return 0;
2531}
2532
6aa8b732
AK		 2533/*
2534 * Reads an msr value (of 'msr_index') into 'pdata'.
2535 * Returns 0 on success, non-0 otherwise.
2536 * Assumes vcpu_load() was already called.
2537 */
2538static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2539{
2540 u64 data;
26bb0981 2541 struct shared_msr_entry *msr;
6aa8b732
AK		 2542
2543 if (!pdata) {
2544 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2545 return -EINVAL;
2546 }
2547
2548 switch (msr_index) {
05b3e0c2 2549#ifdef CONFIG_X86_64
6aa8b732
AK		 2550 case MSR_FS_BASE:
2551 data = vmcs_readl(GUEST_FS_BASE);
2552 break;
2553 case MSR_GS_BASE:
2554 data = vmcs_readl(GUEST_GS_BASE);
2555 break;
44ea2b17
AK		 2556 case MSR_KERNEL_GS_BASE:
2557 vmx_load_host_state(to_vmx(vcpu));
2558 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2559 break;
26bb0981 2560#endif
6aa8b732 2561 case MSR_EFER:
3bab1f5d 2562 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2563 case MSR_IA32_TSC:
6aa8b732
AK		 2564 data = guest_read_tsc();
2565 break;
2566 case MSR_IA32_SYSENTER_CS:
2567 data = vmcs_read32(GUEST_SYSENTER_CS);
2568 break;
2569 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2570 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2571 break;
2572 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2573 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2574 break;
0dd376e7 2575 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2576 if (!vmx_mpx_supported())
2577 return 1;
0dd376e7
LJ		 2578 data = vmcs_read64(GUEST_BNDCFGS);
2579 break;
cae50139
JK		 2580 case MSR_IA32_FEATURE_CONTROL:
2581 if (!nested_vmx_allowed(vcpu))
2582 return 1;
2583 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2584 break;
2585 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2586 if (!nested_vmx_allowed(vcpu))
2587 return 1;
2588 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
20300099
WL		 2589 case MSR_IA32_XSS:
2590 if (!vmx_xsaves_supported())
2591 return 1;
2592 data = vcpu->arch.ia32_xss;
2593 break;
4e47c7a6
SY		 2594 case MSR_TSC_AUX:
2595 if (!to_vmx(vcpu)->rdtscp_enabled)
2596 return 1;
2597 /* Otherwise falls through */
6aa8b732 2598 default:
8b9cf98c 2599 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2600 if (msr) {
2601 data = msr->data;
2602 break;
6aa8b732 2603 }
3bab1f5d 2604 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2605 }
2606
2607 *pdata = data;
2608 return 0;
2609}
2610
cae50139
JK		 2611static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2612
6aa8b732
AK		 2613/*
2614 * Writes msr value into into the appropriate "register".
2615 * Returns 0 on success, non-0 otherwise.
2616 * Assumes vcpu_load() was already called.
2617 */
8fe8ab46 2618static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2619{
a2fa3e9f 2620 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2621 struct shared_msr_entry *msr;
2cc51560 2622 int ret = 0;
8fe8ab46
WA		 2623 u32 msr_index = msr_info->index;
2624 u64 data = msr_info->data;
2cc51560 2625
6aa8b732 2626 switch (msr_index) {
3bab1f5d 2627 case MSR_EFER:
8fe8ab46 2628 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2629 break;
16175a79 2630#ifdef CONFIG_X86_64
6aa8b732 2631 case MSR_FS_BASE:
2fb92db1 2632 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2633 vmcs_writel(GUEST_FS_BASE, data);
2634 break;
2635 case MSR_GS_BASE:
2fb92db1 2636 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2637 vmcs_writel(GUEST_GS_BASE, data);
2638 break;
44ea2b17
AK		 2639 case MSR_KERNEL_GS_BASE:
2640 vmx_load_host_state(vmx);
2641 vmx->msr_guest_kernel_gs_base = data;
2642 break;
6aa8b732
AK		 2643#endif
2644 case MSR_IA32_SYSENTER_CS:
2645 vmcs_write32(GUEST_SYSENTER_CS, data);
2646 break;
2647 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2648 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2649 break;
2650 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2651 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2652 break;
0dd376e7 2653 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2654 if (!vmx_mpx_supported())
2655 return 1;
0dd376e7
LJ		 2656 vmcs_write64(GUEST_BNDCFGS, data);
2657 break;
af24a4e4 2658 case MSR_IA32_TSC:
8fe8ab46 2659 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2660 break;
468d472f
SY		 2661 case MSR_IA32_CR_PAT:
2662 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2663 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2664 return 1;
468d472f
SY		 2665 vmcs_write64(GUEST_IA32_PAT, data);
2666 vcpu->arch.pat = data;
2667 break;
2668 }
8fe8ab46 2669 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2670 break;
ba904635
WA		 2671 case MSR_IA32_TSC_ADJUST:
2672 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2673 break;
cae50139
JK		 2674 case MSR_IA32_FEATURE_CONTROL:
2675 if (!nested_vmx_allowed(vcpu) ||
2676 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2677 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2678 return 1;
2679 vmx->nested.msr_ia32_feature_control = data;
2680 if (msr_info->host_initiated && data == 0)
2681 vmx_leave_nested(vcpu);
2682 break;
2683 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2684 return 1; /* they are read-only */
20300099
WL		 2685 case MSR_IA32_XSS:
2686 if (!vmx_xsaves_supported())
2687 return 1;
2688 /*
2689 * The only supported bit as of Skylake is bit 8, but
2690 * it is not supported on KVM.
2691 */
2692 if (data != 0)
2693 return 1;
2694 vcpu->arch.ia32_xss = data;
2695 if (vcpu->arch.ia32_xss != host_xss)
2696 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2697 vcpu->arch.ia32_xss, host_xss);
2698 else
2699 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2700 break;
4e47c7a6
SY		 2701 case MSR_TSC_AUX:
2702 if (!vmx->rdtscp_enabled)
2703 return 1;
2704 /* Check reserved bit, higher 32 bits should be zero */
2705 if ((data >> 32) != 0)
2706 return 1;
2707 /* Otherwise falls through */
6aa8b732 2708 default:
8b9cf98c 2709 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2710 if (msr) {
8b3c3104 2711 u64 old_msr_data = msr->data;
3bab1f5d 2712 msr->data = data;
2225fd56
AK		 2713 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2714 preempt_disable();
8b3c3104
AH		 2715 ret = kvm_set_shared_msr(msr->index, msr->data,
2716 msr->mask);
2225fd56 2717 preempt_enable();
8b3c3104
AH		 2718 if (ret)
2719 msr->data = old_msr_data;
2225fd56 2720 }
3bab1f5d 2721 break;
6aa8b732 2722 }
8fe8ab46 2723 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2724 }
2725
2cc51560 2726 return ret;
6aa8b732
AK		 2727}
2728
5fdbf976 2729static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2730{
5fdbf976
MT		 2731 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2732 switch (reg) {
2733 case VCPU_REGS_RSP:
2734 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2735 break;
2736 case VCPU_REGS_RIP:
2737 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2738 break;
6de4f3ad
AK		 2739 case VCPU_EXREG_PDPTR:
2740 if (enable_ept)
2741 ept_save_pdptrs(vcpu);
2742 break;
5fdbf976
MT		 2743 default:
2744 break;
2745 }
6aa8b732
AK		 2746}
2747
6aa8b732
AK		 2748static __init int cpu_has_kvm_support(void)
2749{
6210e37b 2750 return cpu_has_vmx();
6aa8b732
AK		 2751}
2752
2753static __init int vmx_disabled_by_bios(void)
2754{
2755 u64 msr;
2756
2757 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2758 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2759 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2760 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2761 && tboot_enabled())
2762 return 1;
23f3e991 2763 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2764 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2765 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2766 && !tboot_enabled()) {
2767 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2768 "activate TXT before enabling KVM\n");
cafd6659 2769 return 1;
f9335afe 2770 }
23f3e991
JC		 2771 /* launched w/o TXT and VMX disabled */
2772 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2773 && !tboot_enabled())
2774 return 1;
cafd6659
SW		 2775 }
2776
2777 return 0;
6aa8b732
AK		 2778}
2779
7725b894
DX		 2780static void kvm_cpu_vmxon(u64 addr)
2781{
2782 asm volatile (ASM_VMX_VMXON_RAX
2783 : : "a"(&addr), "m"(addr)
2784 : "memory", "cc");
2785}
2786
13a34e06 2787static int hardware_enable(void)
6aa8b732
AK		 2788{
2789 int cpu = raw_smp_processor_id();
2790 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2791 u64 old, test_bits;
6aa8b732 2792
10474ae8
AG		 2793 if (read_cr4() & X86_CR4_VMXE)
2794 return -EBUSY;
2795
d462b819 2796 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2797
2798 /*
2799 * Now we can enable the vmclear operation in kdump
2800 * since the loaded_vmcss_on_cpu list on this cpu
2801 * has been initialized.
2802 *
2803 * Though the cpu is not in VMX operation now, there
2804 * is no problem to enable the vmclear operation
2805 * for the loaded_vmcss_on_cpu list is empty!
2806 */
2807 crash_enable_local_vmclear(cpu);
2808
6aa8b732 2809 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2810
2811 test_bits = FEATURE_CONTROL_LOCKED;
2812 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2813 if (tboot_enabled())
2814 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2815
2816 if ((old & test_bits) != test_bits) {
6aa8b732 2817 /* enable and lock */
cafd6659
SW		 2818 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2819 }
66aee91a 2820 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2821
4610c9cc
DX		 2822 if (vmm_exclusive) {
2823 kvm_cpu_vmxon(phys_addr);
2824 ept_sync_global();
2825 }
10474ae8 2826
89cbc767 2827 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2828
10474ae8 2829 return 0;
6aa8b732
AK		 2830}
2831
d462b819 2832static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2833{
2834 int cpu = raw_smp_processor_id();
d462b819 2835 struct loaded_vmcs *v, *n;
543e4243 2836
d462b819
NHE		 2837 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2838 loaded_vmcss_on_cpu_link)
2839 __loaded_vmcs_clear(v);
543e4243
AK		 2840}
2841
710ff4a8
EH		 2842
2843/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2844 * tricks.
2845 */
2846static void kvm_cpu_vmxoff(void)
6aa8b732 2847{
4ecac3fd 2848 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2849}
2850
13a34e06 2851static void hardware_disable(void)
710ff4a8 2852{
4610c9cc 2853 if (vmm_exclusive) {
d462b819 2854 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2855 kvm_cpu_vmxoff();
2856 }
7725b894 2857 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2858}
2859
1c3d14fe 2860static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2861 u32 msr, u32 *result)
1c3d14fe
YS		 2862{
2863 u32 vmx_msr_low, vmx_msr_high;
2864 u32 ctl = ctl_min | ctl_opt;
2865
2866 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2867
2868 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2869 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2870
2871 /* Ensure minimum (required) set of control bits are supported. */
2872 if (ctl_min & ~ctl)
002c7f7c 2873 return -EIO;
1c3d14fe
YS		 2874
2875 *result = ctl;
2876 return 0;
2877}
2878
110312c8
AK		 2879static __init bool allow_1_setting(u32 msr, u32 ctl)
2880{
2881 u32 vmx_msr_low, vmx_msr_high;
2882
2883 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2884 return vmx_msr_high & ctl;
2885}
2886
002c7f7c 2887static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2888{
2889 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2890 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2891 u32 _pin_based_exec_control = 0;
2892 u32 _cpu_based_exec_control = 0;
f78e0e2e 2893 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2894 u32 _vmexit_control = 0;
2895 u32 _vmentry_control = 0;
2896
10166744 2897 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2898#ifdef CONFIG_X86_64
2899 CPU_BASED_CR8_LOAD_EXITING |
2900 CPU_BASED_CR8_STORE_EXITING |
2901#endif
d56f546d
SY		 2902 CPU_BASED_CR3_LOAD_EXITING |
2903 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2904 CPU_BASED_USE_IO_BITMAPS |
2905 CPU_BASED_MOV_DR_EXITING |
a7052897 2906 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2907 CPU_BASED_MWAIT_EXITING |
2908 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2909 CPU_BASED_INVLPG_EXITING |
2910 CPU_BASED_RDPMC_EXITING;
443381a8 2911
f78e0e2e 2912 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2913 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2914 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2915 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2916 &_cpu_based_exec_control) < 0)
002c7f7c 2917 return -EIO;
6e5d865c
YS		 2918#ifdef CONFIG_X86_64
2919 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2920 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2921 ~CPU_BASED_CR8_STORE_EXITING;
2922#endif
f78e0e2e 2923 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2924 min2 = 0;
2925 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2926 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2927 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2928 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2929 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2930 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2931 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2932 SECONDARY_EXEC_RDTSCP |
83d4c286 2933 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2934 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 2935 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099
WL		 2936 SECONDARY_EXEC_SHADOW_VMCS |
2937 SECONDARY_EXEC_XSAVES;
d56f546d
SY		 2938 if (adjust_vmx_controls(min2, opt2,
2939 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2940 &_cpu_based_2nd_exec_control) < 0)
2941 return -EIO;
2942 }
2943#ifndef CONFIG_X86_64
2944 if (!(_cpu_based_2nd_exec_control &
2945 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2946 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2947#endif
83d4c286
YZ		 2948
2949 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2950 _cpu_based_2nd_exec_control &= ~(
8d14695f 2951 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2952 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2953 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2954
d56f546d 2955 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2956 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2957 enabled */
5fff7d27
GN		 2958 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2959 CPU_BASED_CR3_STORE_EXITING |
2960 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2961 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2962 vmx_capability.ept, vmx_capability.vpid);
2963 }
1c3d14fe 2964
81908bf4 2965 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2966#ifdef CONFIG_X86_64
2967 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2968#endif
a547c6db 2969 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2970 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2971 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2972 &_vmexit_control) < 0)
002c7f7c 2973 return -EIO;
1c3d14fe 2974
01e439be
YZ		 2975 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2976 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2977 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2978 &_pin_based_exec_control) < 0)
2979 return -EIO;
2980
2981 if (!(_cpu_based_2nd_exec_control &
2982 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2983 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2984 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2985
c845f9c6 2986 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2987 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2988 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2989 &_vmentry_control) < 0)
002c7f7c 2990 return -EIO;
6aa8b732 2991
c68876fd 2992 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2993
2994 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2995 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2996 return -EIO;
1c3d14fe
YS		 2997
2998#ifdef CONFIG_X86_64
2999 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3000 if (vmx_msr_high & (1u<<16))
002c7f7c 3001 return -EIO;
1c3d14fe
YS		 3002#endif
3003
3004 /* Require Write-Back (WB) memory type for VMCS accesses. */
3005 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3006 return -EIO;
1c3d14fe 3007
002c7f7c
YS		 3008 vmcs_conf->size = vmx_msr_high & 0x1fff;
3009 vmcs_conf->order = get_order(vmcs_config.size);
3010 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3011
002c7f7c
YS		 3012 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3013 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3014 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3015 vmcs_conf->vmexit_ctrl = _vmexit_control;
3016 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3017
110312c8
AK		 3018 cpu_has_load_ia32_efer =
3019 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3020 VM_ENTRY_LOAD_IA32_EFER)
3021 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3022 VM_EXIT_LOAD_IA32_EFER);
3023
8bf00a52
GN		 3024 cpu_has_load_perf_global_ctrl =
3025 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3026 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3027 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3028 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3029
3030 /*
3031 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3032 * but due to arrata below it can't be used. Workaround is to use
3033 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3034 *
3035 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3036 *
3037 * AAK155 (model 26)
3038 * AAP115 (model 30)
3039 * AAT100 (model 37)
3040 * BC86,AAY89,BD102 (model 44)
3041 * BA97 (model 46)
3042 *
3043 */
3044 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3045 switch (boot_cpu_data.x86_model) {
3046 case 26:
3047 case 30:
3048 case 37:
3049 case 44:
3050 case 46:
3051 cpu_has_load_perf_global_ctrl = false;
3052 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3053 "does not work properly. Using workaround\n");
3054 break;
3055 default:
3056 break;
3057 }
3058 }
3059
20300099
WL		 3060 if (cpu_has_xsaves)
3061 rdmsrl(MSR_IA32_XSS, host_xss);
3062
1c3d14fe 3063 return 0;
c68876fd 3064}
6aa8b732
AK		 3065
3066static struct vmcs *alloc_vmcs_cpu(int cpu)
3067{
3068 int node = cpu_to_node(cpu);
3069 struct page *pages;
3070 struct vmcs *vmcs;
3071
6484eb3e 3072 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3073 if (!pages)
3074 return NULL;
3075 vmcs = page_address(pages);
1c3d14fe
YS		 3076 memset(vmcs, 0, vmcs_config.size);
3077 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3078 return vmcs;
3079}
3080
3081static struct vmcs *alloc_vmcs(void)
3082{
d3b2c338 3083 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3084}
3085
3086static void free_vmcs(struct vmcs *vmcs)
3087{
1c3d14fe 3088 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3089}
3090
d462b819
NHE		 3091/*
3092 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3093 */
3094static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3095{
3096 if (!loaded_vmcs->vmcs)
3097 return;
3098 loaded_vmcs_clear(loaded_vmcs);
3099 free_vmcs(loaded_vmcs->vmcs);
3100 loaded_vmcs->vmcs = NULL;
3101}
3102
39959588 3103static void free_kvm_area(void)
6aa8b732
AK		 3104{
3105 int cpu;
3106
3230bb47 3107 for_each_possible_cpu(cpu) {
6aa8b732 3108 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3109 per_cpu(vmxarea, cpu) = NULL;
3110 }
6aa8b732
AK		 3111}
3112
fe2b201b
BD		 3113static void init_vmcs_shadow_fields(void)
3114{
3115 int i, j;
3116
3117 /* No checks for read only fields yet */
3118
3119 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3120 switch (shadow_read_write_fields[i]) {
3121 case GUEST_BNDCFGS:
3122 if (!vmx_mpx_supported())
3123 continue;
3124 break;
3125 default:
3126 break;
3127 }
3128
3129 if (j < i)
3130 shadow_read_write_fields[j] =
3131 shadow_read_write_fields[i];
3132 j++;
3133 }
3134 max_shadow_read_write_fields = j;
3135
3136 /* shadowed fields guest access without vmexit */
3137 for (i = 0; i < max_shadow_read_write_fields; i++) {
3138 clear_bit(shadow_read_write_fields[i],
3139 vmx_vmwrite_bitmap);
3140 clear_bit(shadow_read_write_fields[i],
3141 vmx_vmread_bitmap);
3142 }
3143 for (i = 0; i < max_shadow_read_only_fields; i++)
3144 clear_bit(shadow_read_only_fields[i],
3145 vmx_vmread_bitmap);
3146}
3147
6aa8b732
AK		 3148static __init int alloc_kvm_area(void)
3149{
3150 int cpu;
3151
3230bb47 3152 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3153 struct vmcs *vmcs;
3154
3155 vmcs = alloc_vmcs_cpu(cpu);
3156 if (!vmcs) {
3157 free_kvm_area();
3158 return -ENOMEM;
3159 }
3160
3161 per_cpu(vmxarea, cpu) = vmcs;
3162 }
3163 return 0;
3164}
3165
14168786
GN		 3166static bool emulation_required(struct kvm_vcpu *vcpu)
3167{
3168 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3169}
3170
91b0aa2c 3171static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3172 struct kvm_segment *save)
6aa8b732 3173{
d99e4152
GN		 3174 if (!emulate_invalid_guest_state) {
3175 /*
3176 * CS and SS RPL should be equal during guest entry according
3177 * to VMX spec, but in reality it is not always so. Since vcpu
3178 * is in the middle of the transition from real mode to
3179 * protected mode it is safe to assume that RPL 0 is a good
3180 * default value.
3181 */
3182 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3183 save->selector &= ~SELECTOR_RPL_MASK;
3184 save->dpl = save->selector & SELECTOR_RPL_MASK;
3185 save->s = 1;
6aa8b732 3186 }
d99e4152 3187 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3188}
3189
3190static void enter_pmode(struct kvm_vcpu *vcpu)
3191{
3192 unsigned long flags;
a89a8fb9 3193 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3194
d99e4152
GN		 3195 /*
3196 * Update real mode segment cache. It may be not up-to-date if sement
3197 * register was written while vcpu was in a guest mode.
3198 */
3199 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3200 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3201 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3202 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3203 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3204 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3205
7ffd92c5 3206 vmx->rmode.vm86_active = 0;
6aa8b732 3207
2fb92db1
AK		 3208 vmx_segment_cache_clear(vmx);
3209
f5f7b2fe 3210 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3211
3212 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3213 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3214 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3215 vmcs_writel(GUEST_RFLAGS, flags);
3216
66aee91a
RR		 3217 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3218 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3219
3220 update_exception_bitmap(vcpu);
3221
91b0aa2c
GN		 3222 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3223 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3224 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3225 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3226 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3227 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3228}
3229
f5f7b2fe 3230static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3231{
772e0318 3232 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3233 struct kvm_segment var = *save;
3234
3235 var.dpl = 0x3;
3236 if (seg == VCPU_SREG_CS)
3237 var.type = 0x3;
3238
3239 if (!emulate_invalid_guest_state) {
3240 var.selector = var.base >> 4;
3241 var.base = var.base & 0xffff0;
3242 var.limit = 0xffff;
3243 var.g = 0;
3244 var.db = 0;
3245 var.present = 1;
3246 var.s = 1;
3247 var.l = 0;
3248 var.unusable = 0;
3249 var.type = 0x3;
3250 var.avl = 0;
3251 if (save->base & 0xf)
3252 printk_once(KERN_WARNING "kvm: segment base is not "
3253 "paragraph aligned when entering "
3254 "protected mode (seg=%d)", seg);
3255 }
6aa8b732 3256
d99e4152
GN		 3257 vmcs_write16(sf->selector, var.selector);
3258 vmcs_write32(sf->base, var.base);
3259 vmcs_write32(sf->limit, var.limit);
3260 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3261}
3262
3263static void enter_rmode(struct kvm_vcpu *vcpu)
3264{
3265 unsigned long flags;
a89a8fb9 3266 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3267
f5f7b2fe
AK		 3268 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3269 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3270 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3271 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3272 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3273 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3274 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3275
7ffd92c5 3276 vmx->rmode.vm86_active = 1;
6aa8b732 3277
776e58ea
GN		 3278 /*
3279 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3280 * vcpu. Warn the user that an update is overdue.
776e58ea 3281 */
4918c6ca 3282 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3283 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3284 "called before entering vcpu\n");
776e58ea 3285
2fb92db1
AK		 3286 vmx_segment_cache_clear(vmx);
3287
4918c6ca 3288 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3289 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3290 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3291
3292 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3293 vmx->rmode.save_rflags = flags;
6aa8b732 3294
053de044 3295 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3296
3297 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3298 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3299 update_exception_bitmap(vcpu);
3300
d99e4152
GN		 3301 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3302 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3303 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3304 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3305 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3306 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3307
8668a3c4 3308 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3309}
3310
401d10de
AS		 3311static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3312{
3313 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3314 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3315
3316 if (!msr)
3317 return;
401d10de 3318
44ea2b17
AK		 3319 /*
3320 * Force kernel_gs_base reloading before EFER changes, as control
3321 * of this msr depends on is_long_mode().
3322 */
3323 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3324 vcpu->arch.efer = efer;
401d10de 3325 if (efer & EFER_LMA) {
2961e876 3326 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3327 msr->data = efer;
3328 } else {
2961e876 3329 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3330
3331 msr->data = efer & ~EFER_LME;
3332 }
3333 setup_msrs(vmx);
3334}
3335
05b3e0c2 3336#ifdef CONFIG_X86_64
6aa8b732
AK		 3337
3338static void enter_lmode(struct kvm_vcpu *vcpu)
3339{
3340 u32 guest_tr_ar;
3341
2fb92db1
AK		 3342 vmx_segment_cache_clear(to_vmx(vcpu));
3343
6aa8b732
AK		 3344 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3345 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3346 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3347 __func__);
6aa8b732
AK		 3348 vmcs_write32(GUEST_TR_AR_BYTES,
3349 (guest_tr_ar & ~AR_TYPE_MASK)
3350 | AR_TYPE_BUSY_64_TSS);
3351 }
da38f438 3352 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3353}
3354
3355static void exit_lmode(struct kvm_vcpu *vcpu)
3356{
2961e876 3357 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3358 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3359}
3360
3361#endif
3362
2384d2b3
SY		 3363static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3364{
b9d762fa 3365 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3366 if (enable_ept) {
3367 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3368 return;
4e1096d2 3369 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3370 }
2384d2b3
SY		 3371}
3372
e8467fda
AK		 3373static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3374{
3375 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3376
3377 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3378 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3379}
3380
aff48baa
AK		 3381static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3382{
3383 if (enable_ept && is_paging(vcpu))
3384 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3385 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3386}
3387
25c4c276 3388static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3389{
fc78f519
AK		 3390 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3391
3392 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3393 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3394}
3395
1439442c
SY		 3396static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3397{
d0d538b9
GN		 3398 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3399
6de4f3ad
AK		 3400 if (!test_bit(VCPU_EXREG_PDPTR,
3401 (unsigned long *)&vcpu->arch.regs_dirty))
3402 return;
3403
1439442c 3404 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3405 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3406 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3407 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3408 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3409 }
3410}
3411
8f5d549f
AK		 3412static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3413{
d0d538b9
GN		 3414 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3415
8f5d549f 3416 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3417 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3418 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3419 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3420 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3421 }
6de4f3ad
AK		 3422
3423 __set_bit(VCPU_EXREG_PDPTR,
3424 (unsigned long *)&vcpu->arch.regs_avail);
3425 __set_bit(VCPU_EXREG_PDPTR,
3426 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3427}
3428
5e1746d6 3429static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3430
3431static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3432 unsigned long cr0,
3433 struct kvm_vcpu *vcpu)
3434{
5233dd51
MT		 3435 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3436 vmx_decache_cr3(vcpu);
1439442c
SY		 3437 if (!(cr0 & X86_CR0_PG)) {
3438 /* From paging/starting to nonpaging */
3439 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3440 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3441 (CPU_BASED_CR3_LOAD_EXITING |
3442 CPU_BASED_CR3_STORE_EXITING));
3443 vcpu->arch.cr0 = cr0;
fc78f519 3444 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3445 } else if (!is_paging(vcpu)) {
3446 /* From nonpaging to paging */
3447 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3448 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3449 ~(CPU_BASED_CR3_LOAD_EXITING |
3450 CPU_BASED_CR3_STORE_EXITING));
3451 vcpu->arch.cr0 = cr0;
fc78f519 3452 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3453 }
95eb84a7
SY		 3454
3455 if (!(cr0 & X86_CR0_WP))
3456 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3457}
3458
6aa8b732
AK		 3459static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3460{
7ffd92c5 3461 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3462 unsigned long hw_cr0;
3463
5037878e 3464 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3465 if (enable_unrestricted_guest)
5037878e 3466 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3467 else {
5037878e 3468 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3469
218e763f
GN		 3470 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3471 enter_pmode(vcpu);
6aa8b732 3472
218e763f
GN		 3473 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3474 enter_rmode(vcpu);
3475 }
6aa8b732 3476
05b3e0c2 3477#ifdef CONFIG_X86_64
f6801dff 3478 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3479 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3480 enter_lmode(vcpu);
707d92fa 3481 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3482 exit_lmode(vcpu);
3483 }
3484#endif
3485
089d034e 3486 if (enable_ept)
1439442c
SY		 3487 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3488
02daab21 3489 if (!vcpu->fpu_active)
81231c69 3490 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3491
6aa8b732 3492 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3493 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3494 vcpu->arch.cr0 = cr0;
14168786
GN		 3495
3496 /* depends on vcpu->arch.cr0 to be set to a new value */
3497 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3498}
3499
1439442c
SY		 3500static u64 construct_eptp(unsigned long root_hpa)
3501{
3502 u64 eptp;
3503
3504 /* TODO write the value reading from MSR */
3505 eptp = VMX_EPT_DEFAULT_MT |
3506 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3507 if (enable_ept_ad_bits)
3508 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3509 eptp |= (root_hpa & PAGE_MASK);
3510
3511 return eptp;
3512}
3513
6aa8b732
AK		 3514static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3515{
1439442c
SY		 3516 unsigned long guest_cr3;
3517 u64 eptp;
3518
3519 guest_cr3 = cr3;
089d034e 3520 if (enable_ept) {
1439442c
SY		 3521 eptp = construct_eptp(cr3);
3522 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3523 if (is_paging(vcpu) || is_guest_mode(vcpu))
3524 guest_cr3 = kvm_read_cr3(vcpu);
3525 else
3526 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3527 ept_load_pdptrs(vcpu);
1439442c
SY		 3528 }
3529
2384d2b3 3530 vmx_flush_tlb(vcpu);
1439442c 3531 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3532}
3533
5e1746d6 3534static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3535{
7ffd92c5 3536 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3537 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3538
5e1746d6
NHE		 3539 if (cr4 & X86_CR4_VMXE) {
3540 /*
3541 * To use VMXON (and later other VMX instructions), a guest
3542 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3543 * So basically the check on whether to allow nested VMX
3544 * is here.
3545 */
3546 if (!nested_vmx_allowed(vcpu))
3547 return 1;
1a0d74e6
JK		 3548 }
3549 if (to_vmx(vcpu)->nested.vmxon &&
3550 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3551 return 1;
3552
ad312c7c 3553 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3554 if (enable_ept) {
3555 if (!is_paging(vcpu)) {
3556 hw_cr4 &= ~X86_CR4_PAE;
3557 hw_cr4 |= X86_CR4_PSE;
c08800a5 3558 /*
e1e746b3
FW		 3559 * SMEP/SMAP is disabled if CPU is in non-paging mode
3560 * in hardware. However KVM always uses paging mode to
c08800a5 3561 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3562 * To emulate this behavior, SMEP/SMAP needs to be
3563 * manually disabled when guest switches to non-paging
3564 * mode.
c08800a5 3565 */
e1e746b3 3566 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3567 } else if (!(cr4 & X86_CR4_PAE)) {
3568 hw_cr4 &= ~X86_CR4_PAE;
3569 }
3570 }
1439442c
SY		 3571
3572 vmcs_writel(CR4_READ_SHADOW, cr4);
3573 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3574 return 0;
6aa8b732
AK		 3575}
3576
6aa8b732
AK		 3577static void vmx_get_segment(struct kvm_vcpu *vcpu,
3578 struct kvm_segment *var, int seg)
3579{
a9179499 3580 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3581 u32 ar;
3582
c6ad1153 3583 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3584 *var = vmx->rmode.segs[seg];
a9179499 3585 if (seg == VCPU_SREG_TR
2fb92db1 3586 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3587 return;
1390a28b
AK		 3588 var->base = vmx_read_guest_seg_base(vmx, seg);
3589 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3590 return;
a9179499 3591 }
2fb92db1
AK		 3592 var->base = vmx_read_guest_seg_base(vmx, seg);
3593 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3594 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3595 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3596 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3597 var->type = ar & 15;
3598 var->s = (ar >> 4) & 1;
3599 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3600 /*
3601 * Some userspaces do not preserve unusable property. Since usable
3602 * segment has to be present according to VMX spec we can use present
3603 * property to amend userspace bug by making unusable segment always
3604 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3605 * segment as unusable.
3606 */
3607 var->present = !var->unusable;
6aa8b732
AK		 3608 var->avl = (ar >> 12) & 1;
3609 var->l = (ar >> 13) & 1;
3610 var->db = (ar >> 14) & 1;
3611 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3612}
3613
a9179499
AK		 3614static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3615{
a9179499
AK		 3616 struct kvm_segment s;
3617
3618 if (to_vmx(vcpu)->rmode.vm86_active) {
3619 vmx_get_segment(vcpu, &s, seg);
3620 return s.base;
3621 }
2fb92db1 3622 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3623}
3624
b09408d0 3625static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3626{
b09408d0
MT		 3627 struct vcpu_vmx *vmx = to_vmx(vcpu);
3628
ae9fedc7 3629 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3630 return 0;
ae9fedc7
PB		 3631 else {
3632 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3633 return AR_DPL(ar);
69c73028 3634 }
69c73028
AK		 3635}
3636
653e3108 3637static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3638{
6aa8b732
AK		 3639 u32 ar;
3640
f0495f9b 3641 if (var->unusable || !var->present)
6aa8b732
AK		 3642 ar = 1 << 16;
3643 else {
3644 ar = var->type & 15;
3645 ar |= (var->s & 1) << 4;
3646 ar |= (var->dpl & 3) << 5;
3647 ar |= (var->present & 1) << 7;
3648 ar |= (var->avl & 1) << 12;
3649 ar |= (var->l & 1) << 13;
3650 ar |= (var->db & 1) << 14;
3651 ar |= (var->g & 1) << 15;
3652 }
653e3108
AK		 3653
3654 return ar;
3655}
3656
3657static void vmx_set_segment(struct kvm_vcpu *vcpu,
3658 struct kvm_segment *var, int seg)
3659{
7ffd92c5 3660 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3661 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3662
2fb92db1
AK		 3663 vmx_segment_cache_clear(vmx);
3664
1ecd50a9
GN		 3665 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3666 vmx->rmode.segs[seg] = *var;
3667 if (seg == VCPU_SREG_TR)
3668 vmcs_write16(sf->selector, var->selector);
3669 else if (var->s)
3670 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3671 goto out;
653e3108 3672 }
1ecd50a9 3673
653e3108
AK		 3674 vmcs_writel(sf->base, var->base);
3675 vmcs_write32(sf->limit, var->limit);
3676 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3677
3678 /*
3679 * Fix the "Accessed" bit in AR field of segment registers for older
3680 * qemu binaries.
3681 * IA32 arch specifies that at the time of processor reset the
3682 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3683 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3684 * state vmexit when "unrestricted guest" mode is turned on.
3685 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3686 * tree. Newer qemu binaries with that qemu fix would not need this
3687 * kvm hack.
3688 */
3689 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3690 var->type |= 0x1; /* Accessed */
3a624e29 3691
f924d66d 3692 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3693
3694out:
98eb2f8b 3695 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3696}
3697
6aa8b732
AK		 3698static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3699{
2fb92db1 3700 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3701
3702 *db = (ar >> 14) & 1;
3703 *l = (ar >> 13) & 1;
3704}
3705
89a27f4d 3706static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3707{
89a27f4d
GN		 3708 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3709 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3710}
3711
89a27f4d 3712static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3713{
89a27f4d
GN		 3714 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3715 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3716}
3717
89a27f4d 3718static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3719{
89a27f4d
GN		 3720 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3721 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3722}
3723
89a27f4d 3724static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3725{
89a27f4d
GN		 3726 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3727 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3728}
3729
648dfaa7
MG		 3730static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3731{
3732 struct kvm_segment var;
3733 u32 ar;
3734
3735 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3736 var.dpl = 0x3;
0647f4aa
GN		 3737 if (seg == VCPU_SREG_CS)
3738 var.type = 0x3;
648dfaa7
MG		 3739 ar = vmx_segment_access_rights(&var);
3740
3741 if (var.base != (var.selector << 4))
3742 return false;
89efbed0 3743 if (var.limit != 0xffff)
648dfaa7 3744 return false;
07f42f5f 3745 if (ar != 0xf3)
648dfaa7
MG		 3746 return false;
3747
3748 return true;
3749}
3750
3751static bool code_segment_valid(struct kvm_vcpu *vcpu)
3752{
3753 struct kvm_segment cs;
3754 unsigned int cs_rpl;
3755
3756 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3757 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3758
1872a3f4
AK		 3759 if (cs.unusable)
3760 return false;
648dfaa7
MG		 3761 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3762 return false;
3763 if (!cs.s)
3764 return false;
1872a3f4 3765 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3766 if (cs.dpl > cs_rpl)
3767 return false;
1872a3f4 3768 } else {
648dfaa7
MG		 3769 if (cs.dpl != cs_rpl)
3770 return false;
3771 }
3772 if (!cs.present)
3773 return false;
3774
3775 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3776 return true;
3777}
3778
3779static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3780{
3781 struct kvm_segment ss;
3782 unsigned int ss_rpl;
3783
3784 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3785 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3786
1872a3f4
AK		 3787 if (ss.unusable)
3788 return true;
3789 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3790 return false;
3791 if (!ss.s)
3792 return false;
3793 if (ss.dpl != ss_rpl) /* DPL != RPL */
3794 return false;
3795 if (!ss.present)
3796 return false;
3797
3798 return true;
3799}
3800
3801static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3802{
3803 struct kvm_segment var;
3804 unsigned int rpl;
3805
3806 vmx_get_segment(vcpu, &var, seg);
3807 rpl = var.selector & SELECTOR_RPL_MASK;
3808
1872a3f4
AK		 3809 if (var.unusable)
3810 return true;
648dfaa7
MG		 3811 if (!var.s)
3812 return false;
3813 if (!var.present)
3814 return false;
3815 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3816 if (var.dpl < rpl) /* DPL < RPL */
3817 return false;
3818 }
3819
3820 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3821 * rights flags
3822 */
3823 return true;
3824}
3825
3826static bool tr_valid(struct kvm_vcpu *vcpu)
3827{
3828 struct kvm_segment tr;
3829
3830 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3831
1872a3f4
AK		 3832 if (tr.unusable)
3833 return false;
648dfaa7
MG		 3834 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3835 return false;
1872a3f4 3836 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3837 return false;
3838 if (!tr.present)
3839 return false;
3840
3841 return true;
3842}
3843
3844static bool ldtr_valid(struct kvm_vcpu *vcpu)
3845{
3846 struct kvm_segment ldtr;
3847
3848 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3849
1872a3f4
AK		 3850 if (ldtr.unusable)
3851 return true;
648dfaa7
MG		 3852 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3853 return false;
3854 if (ldtr.type != 2)
3855 return false;
3856 if (!ldtr.present)
3857 return false;
3858
3859 return true;
3860}
3861
3862static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3863{
3864 struct kvm_segment cs, ss;
3865
3866 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3867 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3868
3869 return ((cs.selector & SELECTOR_RPL_MASK) ==
3870 (ss.selector & SELECTOR_RPL_MASK));
3871}
3872
3873/*
3874 * Check if guest state is valid. Returns true if valid, false if
3875 * not.
3876 * We assume that registers are always usable
3877 */
3878static bool guest_state_valid(struct kvm_vcpu *vcpu)
3879{
c5e97c80
GN		 3880 if (enable_unrestricted_guest)
3881 return true;
3882
648dfaa7 3883 /* real mode guest state checks */
f13882d8 3884 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3885 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3886 return false;
3887 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3888 return false;
3889 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3890 return false;
3891 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3892 return false;
3893 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3894 return false;
3895 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3896 return false;
3897 } else {
3898 /* protected mode guest state checks */
3899 if (!cs_ss_rpl_check(vcpu))
3900 return false;
3901 if (!code_segment_valid(vcpu))
3902 return false;
3903 if (!stack_segment_valid(vcpu))
3904 return false;
3905 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3906 return false;
3907 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3908 return false;
3909 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3910 return false;
3911 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3912 return false;
3913 if (!tr_valid(vcpu))
3914 return false;
3915 if (!ldtr_valid(vcpu))
3916 return false;
3917 }
3918 /* TODO:
3919 * - Add checks on RIP
3920 * - Add checks on RFLAGS
3921 */
3922
3923 return true;
3924}
3925
d77c26fc 3926static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3927{
40dcaa9f 3928 gfn_t fn;
195aefde 3929 u16 data = 0;
1f755a82 3930 int idx, r;
6aa8b732 3931
40dcaa9f 3932 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3933 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3934 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3935 if (r < 0)
10589a46 3936 goto out;
195aefde 3937 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3938 r = kvm_write_guest_page(kvm, fn++, &data,
3939 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3940 if (r < 0)
10589a46 3941 goto out;
195aefde
IE		 3942 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3943 if (r < 0)
10589a46 3944 goto out;
195aefde
IE		 3945 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3946 if (r < 0)
10589a46 3947 goto out;
195aefde 3948 data = ~0;
10589a46
MT		 3949 r = kvm_write_guest_page(kvm, fn, &data,
3950 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3951 sizeof(u8));
10589a46 3952out:
40dcaa9f 3953 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3954 return r;
6aa8b732
AK		 3955}
3956
b7ebfb05
SY		 3957static int init_rmode_identity_map(struct kvm *kvm)
3958{
f51770ed 3959 int i, idx, r = 0;
b7ebfb05
SY		 3960 pfn_t identity_map_pfn;
3961 u32 tmp;
3962
089d034e 3963 if (!enable_ept)
f51770ed 3964 return 0;
a255d479
TC		 3965
3966 /* Protect kvm->arch.ept_identity_pagetable_done. */
3967 mutex_lock(&kvm->slots_lock);
3968
f51770ed 3969 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 3970 goto out2;
a255d479 3971
b927a3ce 3972 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 3973
3974 r = alloc_identity_pagetable(kvm);
f51770ed 3975 if (r < 0)
a255d479
TC		 3976 goto out2;
3977
40dcaa9f 3978 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3979 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3980 if (r < 0)
3981 goto out;
3982 /* Set up identity-mapping pagetable for EPT in real mode */
3983 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3984 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3985 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3986 r = kvm_write_guest_page(kvm, identity_map_pfn,
3987 &tmp, i * sizeof(tmp), sizeof(tmp));
3988 if (r < 0)
3989 goto out;
3990 }
3991 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 3992
b7ebfb05 3993out:
40dcaa9f 3994 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 3995
3996out2:
3997 mutex_unlock(&kvm->slots_lock);
f51770ed 3998 return r;
b7ebfb05
SY		 3999}
4000
6aa8b732
AK		 4001static void seg_setup(int seg)
4002{
772e0318 4003 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4004 unsigned int ar;
6aa8b732
AK		 4005
4006 vmcs_write16(sf->selector, 0);
4007 vmcs_writel(sf->base, 0);
4008 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4009 ar = 0x93;
4010 if (seg == VCPU_SREG_CS)
4011 ar |= 0x08; /* code segment */
3a624e29
NK		 4012
4013 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4014}
4015
f78e0e2e
SY		 4016static int alloc_apic_access_page(struct kvm *kvm)
4017{
4484141a 4018 struct page *page;
f78e0e2e
SY		 4019 struct kvm_userspace_memory_region kvm_userspace_mem;
4020 int r = 0;
4021
79fac95e 4022 mutex_lock(&kvm->slots_lock);
c24ae0dc 4023 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4024 goto out;
4025 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4026 kvm_userspace_mem.flags = 0;
73a6d941 4027 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4028 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4029 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4030 if (r)
4031 goto out;
72dc67a6 4032
73a6d941 4033 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4034 if (is_error_page(page)) {
4035 r = -EFAULT;
4036 goto out;
4037 }
4038
c24ae0dc
TC		 4039 /*
4040 * Do not pin the page in memory, so that memory hot-unplug
4041 * is able to migrate it.
4042 */
4043 put_page(page);
4044 kvm->arch.apic_access_page_done = true;
f78e0e2e 4045out:
79fac95e 4046 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4047 return r;
4048}
4049
b7ebfb05
SY		 4050static int alloc_identity_pagetable(struct kvm *kvm)
4051{
a255d479
TC		 4052 /* Called with kvm->slots_lock held. */
4053
b7ebfb05
SY		 4054 struct kvm_userspace_memory_region kvm_userspace_mem;
4055 int r = 0;
4056
a255d479
TC		 4057 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4058
b7ebfb05
SY		 4059 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4060 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4061 kvm_userspace_mem.guest_phys_addr =
4062 kvm->arch.ept_identity_map_addr;
b7ebfb05 4063 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4064 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4065
b7ebfb05
SY		 4066 return r;
4067}
4068
2384d2b3
SY		 4069static void allocate_vpid(struct vcpu_vmx *vmx)
4070{
4071 int vpid;
4072
4073 vmx->vpid = 0;
919818ab 4074 if (!enable_vpid)
2384d2b3
SY		 4075 return;
4076 spin_lock(&vmx_vpid_lock);
4077 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4078 if (vpid < VMX_NR_VPIDS) {
4079 vmx->vpid = vpid;
4080 __set_bit(vpid, vmx_vpid_bitmap);
4081 }
4082 spin_unlock(&vmx_vpid_lock);
4083}
4084
cdbecfc3
LJ		 4085static void free_vpid(struct vcpu_vmx *vmx)
4086{
4087 if (!enable_vpid)
4088 return;
4089 spin_lock(&vmx_vpid_lock);
4090 if (vmx->vpid != 0)
4091 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4092 spin_unlock(&vmx_vpid_lock);
4093}
4094
8d14695f
YZ		 4095#define MSR_TYPE_R 1
4096#define MSR_TYPE_W 2
4097static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4098 u32 msr, int type)
25c5f225 4099{
3e7c73e9 4100 int f = sizeof(unsigned long);
25c5f225
SY		 4101
4102 if (!cpu_has_vmx_msr_bitmap())
4103 return;
4104
4105 /*
4106 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4107 * have the write-low and read-high bitmap offsets the wrong way round.
4108 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4109 */
25c5f225 4110 if (msr <= 0x1fff) {
8d14695f
YZ		 4111 if (type & MSR_TYPE_R)
4112 /* read-low */
4113 __clear_bit(msr, msr_bitmap + 0x000 / f);
4114
4115 if (type & MSR_TYPE_W)
4116 /* write-low */
4117 __clear_bit(msr, msr_bitmap + 0x800 / f);
4118
25c5f225
SY		 4119 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4120 msr &= 0x1fff;
8d14695f
YZ		 4121 if (type & MSR_TYPE_R)
4122 /* read-high */
4123 __clear_bit(msr, msr_bitmap + 0x400 / f);
4124
4125 if (type & MSR_TYPE_W)
4126 /* write-high */
4127 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4128
4129 }
4130}
4131
4132static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4133 u32 msr, int type)
4134{
4135 int f = sizeof(unsigned long);
4136
4137 if (!cpu_has_vmx_msr_bitmap())
4138 return;
4139
4140 /*
4141 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4142 * have the write-low and read-high bitmap offsets the wrong way round.
4143 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4144 */
4145 if (msr <= 0x1fff) {
4146 if (type & MSR_TYPE_R)
4147 /* read-low */
4148 __set_bit(msr, msr_bitmap + 0x000 / f);
4149
4150 if (type & MSR_TYPE_W)
4151 /* write-low */
4152 __set_bit(msr, msr_bitmap + 0x800 / f);
4153
4154 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4155 msr &= 0x1fff;
4156 if (type & MSR_TYPE_R)
4157 /* read-high */
4158 __set_bit(msr, msr_bitmap + 0x400 / f);
4159
4160 if (type & MSR_TYPE_W)
4161 /* write-high */
4162 __set_bit(msr, msr_bitmap + 0xc00 / f);
4163
25c5f225 4164 }
25c5f225
SY		 4165}
4166
5897297b
AK		 4167static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4168{
4169 if (!longmode_only)
8d14695f
YZ		 4170 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4171 msr, MSR_TYPE_R | MSR_TYPE_W);
4172 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4173 msr, MSR_TYPE_R | MSR_TYPE_W);
4174}
4175
4176static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4177{
4178 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4179 msr, MSR_TYPE_R);
4180 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4181 msr, MSR_TYPE_R);
4182}
4183
4184static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4185{
4186 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4187 msr, MSR_TYPE_R);
4188 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4189 msr, MSR_TYPE_R);
4190}
4191
4192static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4193{
4194 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4195 msr, MSR_TYPE_W);
4196 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4197 msr, MSR_TYPE_W);
5897297b
AK		 4198}
4199
01e439be
YZ		 4200static int vmx_vm_has_apicv(struct kvm *kvm)
4201{
4202 return enable_apicv && irqchip_in_kernel(kvm);
4203}
4204
a20ed54d
YZ		 4205/*
4206 * Send interrupt to vcpu via posted interrupt way.
4207 * 1. If target vcpu is running(non-root mode), send posted interrupt
4208 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4209 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4210 * interrupt from PIR in next vmentry.
4211 */
4212static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4213{
4214 struct vcpu_vmx *vmx = to_vmx(vcpu);
4215 int r;
4216
4217 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4218 return;
4219
4220 r = pi_test_and_set_on(&vmx->pi_desc);
4221 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4222#ifdef CONFIG_SMP
a20ed54d
YZ		 4223 if (!r && (vcpu->mode == IN_GUEST_MODE))
4224 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4225 POSTED_INTR_VECTOR);
4226 else
6ffbbbba 4227#endif
a20ed54d
YZ		 4228 kvm_vcpu_kick(vcpu);
4229}
4230
4231static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4232{
4233 struct vcpu_vmx *vmx = to_vmx(vcpu);
4234
4235 if (!pi_test_and_clear_on(&vmx->pi_desc))
4236 return;
4237
4238 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4239}
4240
4241static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4242{
4243 return;
4244}
4245
a3a8ff8e
NHE		 4246/*
4247 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4248 * will not change in the lifetime of the guest.
4249 * Note that host-state that does change is set elsewhere. E.g., host-state
4250 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4251 */
a547c6db 4252static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4253{
4254 u32 low32, high32;
4255 unsigned long tmpl;
4256 struct desc_ptr dt;
d974baa3 4257 unsigned long cr4;
a3a8ff8e 4258
b1a74bf8 4259 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4260 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4261
d974baa3
AL		 4262 /* Save the most likely value for this task's CR4 in the VMCS. */
4263 cr4 = read_cr4();
4264 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4265 vmx->host_state.vmcs_host_cr4 = cr4;
4266
a3a8ff8e 4267 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4268#ifdef CONFIG_X86_64
4269 /*
4270 * Load null selectors, so we can avoid reloading them in
4271 * __vmx_load_host_state(), in case userspace uses the null selectors
4272 * too (the expected case).
4273 */
4274 vmcs_write16(HOST_DS_SELECTOR, 0);
4275 vmcs_write16(HOST_ES_SELECTOR, 0);
4276#else
a3a8ff8e
NHE		 4277 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4278 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4279#endif
a3a8ff8e
NHE		 4280 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4281 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4282
4283 native_store_idt(&dt);
4284 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4285 vmx->host_idt_base = dt.address;
a3a8ff8e 4286
83287ea4 4287 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4288
4289 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4290 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4291 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4292 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4293
4294 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4295 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4296 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4297 }
4298}
4299
bf8179a0
NHE		 4300static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4301{
4302 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4303 if (enable_ept)
4304 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4305 if (is_guest_mode(&vmx->vcpu))
4306 vmx->vcpu.arch.cr4_guest_owned_bits &=
4307 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4308 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4309}
4310
01e439be
YZ		 4311static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4312{
4313 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4314
4315 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4316 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4317 return pin_based_exec_ctrl;
4318}
4319
bf8179a0
NHE		 4320static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4321{
4322 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4323
4324 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4325 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4326
bf8179a0
NHE		 4327 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4328 exec_control &= ~CPU_BASED_TPR_SHADOW;
4329#ifdef CONFIG_X86_64
4330 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4331 CPU_BASED_CR8_LOAD_EXITING;
4332#endif
4333 }
4334 if (!enable_ept)
4335 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4336 CPU_BASED_CR3_LOAD_EXITING |
4337 CPU_BASED_INVLPG_EXITING;
4338 return exec_control;
4339}
4340
4341static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4342{
4343 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4344 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4345 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4346 if (vmx->vpid == 0)
4347 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4348 if (!enable_ept) {
4349 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4350 enable_unrestricted_guest = 0;
ad756a16
MJ		 4351 /* Enable INVPCID for non-ept guests may cause performance regression. */
4352 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4353 }
4354 if (!enable_unrestricted_guest)
4355 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4356 if (!ple_gap)
4357 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4358 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4359 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4360 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4361 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4362 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4363 (handle_vmptrld).
4364 We can NOT enable shadow_vmcs here because we don't have yet
4365 a current VMCS12
4366 */
4367 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4368 return exec_control;
4369}
4370
ce88decf
XG		 4371static void ept_set_mmio_spte_mask(void)
4372{
4373 /*
4374 * EPT Misconfigurations can be generated if the value of bits 2:0
4375 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4376 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4377 * spte.
4378 */
885032b9 4379 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4380}
4381
f53cd63c 4382#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4383/*
4384 * Sets up the vmcs for emulated real mode.
4385 */
8b9cf98c 4386static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4387{
2e4ce7f5 4388#ifdef CONFIG_X86_64
6aa8b732 4389 unsigned long a;
2e4ce7f5 4390#endif
6aa8b732 4391 int i;
6aa8b732 4392
6aa8b732 4393 /* I/O */
3e7c73e9
AK		 4394 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4395 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4396
4607c2d7
AG		 4397 if (enable_shadow_vmcs) {
4398 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4399 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4400 }
25c5f225 4401 if (cpu_has_vmx_msr_bitmap())
5897297b 4402 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4403
6aa8b732
AK		 4404 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4405
6aa8b732 4406 /* Control */
01e439be 4407 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4408
bf8179a0 4409 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4410
83ff3b9d 4411 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4412 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4413 vmx_secondary_exec_control(vmx));
83ff3b9d 4414 }
f78e0e2e 4415
01e439be 4416 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4417 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4418 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4419 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4420 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4421
4422 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4423
4424 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4425 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4426 }
4427
4b8d54f9
ZE		 4428 if (ple_gap) {
4429 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4430 vmx->ple_window = ple_window;
4431 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4432 }
4433
c3707958
XG		 4434 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4435 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4436 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4437
9581d442
AK		 4438 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4439 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4440 vmx_set_constant_host_state(vmx);
05b3e0c2 4441#ifdef CONFIG_X86_64
6aa8b732
AK		 4442 rdmsrl(MSR_FS_BASE, a);
4443 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4444 rdmsrl(MSR_GS_BASE, a);
4445 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4446#else
4447 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4448 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4449#endif
4450
2cc51560
ED		 4451 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4452 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4453 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4454 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4455 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4456
468d472f 4457 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4458 u32 msr_low, msr_high;
4459 u64 host_pat;
468d472f
SY		 4460 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4461 host_pat = msr_low | ((u64) msr_high << 32);
4462 /* Write the default value follow host pat */
4463 vmcs_write64(GUEST_IA32_PAT, host_pat);
4464 /* Keep arch.pat sync with GUEST_IA32_PAT */
4465 vmx->vcpu.arch.pat = host_pat;
4466 }
4467
03916db9 4468 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4469 u32 index = vmx_msr_index[i];
4470 u32 data_low, data_high;
a2fa3e9f 4471 int j = vmx->nmsrs;
6aa8b732
AK		 4472
4473 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4474 continue;
432bd6cb
AK		 4475 if (wrmsr_safe(index, data_low, data_high) < 0)
4476 continue;
26bb0981
AK		 4477 vmx->guest_msrs[j].index = i;
4478 vmx->guest_msrs[j].data = 0;
d5696725 4479 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4480 ++vmx->nmsrs;
6aa8b732 4481 }
6aa8b732 4482
2961e876
GN		 4483
4484 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4485
4486 /* 22.2.1, 20.8.1 */
2961e876 4487 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4488
e00c8cf2 4489 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4490 set_cr4_guest_host_mask(vmx);
e00c8cf2 4491
f53cd63c
WL		 4492 if (vmx_xsaves_supported())
4493 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4494
e00c8cf2
AK		 4495 return 0;
4496}
4497
57f252f2 4498static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4499{
4500 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4501 struct msr_data apic_base_msr;
e00c8cf2 4502
7ffd92c5 4503 vmx->rmode.vm86_active = 0;
e00c8cf2 4504
3b86cd99
JK		 4505 vmx->soft_vnmi_blocked = 0;
4506
ad312c7c 4507 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4508 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4509 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4510 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4511 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4512 apic_base_msr.host_initiated = true;
4513 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4514
2fb92db1
AK		 4515 vmx_segment_cache_clear(vmx);
4516
5706be0d 4517 seg_setup(VCPU_SREG_CS);
66450a21 4518 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4519 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4520
4521 seg_setup(VCPU_SREG_DS);
4522 seg_setup(VCPU_SREG_ES);
4523 seg_setup(VCPU_SREG_FS);
4524 seg_setup(VCPU_SREG_GS);
4525 seg_setup(VCPU_SREG_SS);
4526
4527 vmcs_write16(GUEST_TR_SELECTOR, 0);
4528 vmcs_writel(GUEST_TR_BASE, 0);
4529 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4530 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4531
4532 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4533 vmcs_writel(GUEST_LDTR_BASE, 0);
4534 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4535 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4536
4537 vmcs_write32(GUEST_SYSENTER_CS, 0);
4538 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4539 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4540
4541 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4542 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4543
e00c8cf2
AK		 4544 vmcs_writel(GUEST_GDTR_BASE, 0);
4545 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4546
4547 vmcs_writel(GUEST_IDTR_BASE, 0);
4548 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4549
443381a8 4550 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4551 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4552 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4553
e00c8cf2
AK		 4554 /* Special registers */
4555 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4556
4557 setup_msrs(vmx);
4558
6aa8b732
AK		 4559 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4560
f78e0e2e
SY		 4561 if (cpu_has_vmx_tpr_shadow()) {
4562 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4563 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4564 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4565 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4566 vmcs_write32(TPR_THRESHOLD, 0);
4567 }
4568
a73896cb 4569 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4570
01e439be
YZ		 4571 if (vmx_vm_has_apicv(vcpu->kvm))
4572 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4573
2384d2b3
SY		 4574 if (vmx->vpid != 0)
4575 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4576
fa40052c 4577 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4578 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4579 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4580 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4581 vmx_fpu_activate(&vmx->vcpu);
4582 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4583
b9d762fa 4584 vpid_sync_context(vmx);
6aa8b732
AK		 4585}
4586
b6f1250e
NHE		 4587/*
4588 * In nested virtualization, check if L1 asked to exit on external interrupts.
4589 * For most existing hypervisors, this will always return true.
4590 */
4591static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4592{
4593 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4594 PIN_BASED_EXT_INTR_MASK;
4595}
4596
77b0f5d6
BD		 4597/*
4598 * In nested virtualization, check if L1 has set
4599 * VM_EXIT_ACK_INTR_ON_EXIT
4600 */
4601static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4602{
4603 return get_vmcs12(vcpu)->vm_exit_controls &
4604 VM_EXIT_ACK_INTR_ON_EXIT;
4605}
4606
ea8ceb83
JK		 4607static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4608{
4609 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4610 PIN_BASED_NMI_EXITING;
4611}
4612
c9a7953f 4613static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4614{
4615 u32 cpu_based_vm_exec_control;
730dca42 4616
3b86cd99
JK		 4617 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4618 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4619 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4620}
4621
c9a7953f 4622static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4623{
4624 u32 cpu_based_vm_exec_control;
4625
c9a7953f
JK		 4626 if (!cpu_has_virtual_nmis() ||
4627 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4628 enable_irq_window(vcpu);
4629 return;
4630 }
3b86cd99
JK		 4631
4632 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4633 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4634 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4635}
4636
66fd3f7f 4637static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4638{
9c8cba37 4639 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4640 uint32_t intr;
4641 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4642
229456fc 4643 trace_kvm_inj_virq(irq);
2714d1d3 4644
fa89a817 4645 ++vcpu->stat.irq_injections;
7ffd92c5 4646 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4647 int inc_eip = 0;
4648 if (vcpu->arch.interrupt.soft)
4649 inc_eip = vcpu->arch.event_exit_inst_len;
4650 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4651 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4652 return;
4653 }
66fd3f7f
GN		 4654 intr = irq | INTR_INFO_VALID_MASK;
4655 if (vcpu->arch.interrupt.soft) {
4656 intr |= INTR_TYPE_SOFT_INTR;
4657 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4658 vmx->vcpu.arch.event_exit_inst_len);
4659 } else
4660 intr |= INTR_TYPE_EXT_INTR;
4661 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4662}
4663
f08864b4
SY		 4664static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4665{
66a5a347
JK		 4666 struct vcpu_vmx *vmx = to_vmx(vcpu);
4667
0b6ac343
NHE		 4668 if (is_guest_mode(vcpu))
4669 return;
4670
3b86cd99
JK		 4671 if (!cpu_has_virtual_nmis()) {
4672 /*
4673 * Tracking the NMI-blocked state in software is built upon
4674 * finding the next open IRQ window. This, in turn, depends on
4675 * well-behaving guests: They have to keep IRQs disabled at
4676 * least as long as the NMI handler runs. Otherwise we may
4677 * cause NMI nesting, maybe breaking the guest. But as this is
4678 * highly unlikely, we can live with the residual risk.
4679 */
4680 vmx->soft_vnmi_blocked = 1;
4681 vmx->vnmi_blocked_time = 0;
4682 }
4683
487b391d 4684 ++vcpu->stat.nmi_injections;
9d58b931 4685 vmx->nmi_known_unmasked = false;
7ffd92c5 4686 if (vmx->rmode.vm86_active) {
71f9833b 4687 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4688 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4689 return;
4690 }
f08864b4
SY		 4691 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4692 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4693}
4694
3cfc3092
JK		 4695static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4696{
4697 if (!cpu_has_virtual_nmis())
4698 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4699 if (to_vmx(vcpu)->nmi_known_unmasked)
4700 return false;
c332c83a 4701 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4702}
4703
4704static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4705{
4706 struct vcpu_vmx *vmx = to_vmx(vcpu);
4707
4708 if (!cpu_has_virtual_nmis()) {
4709 if (vmx->soft_vnmi_blocked != masked) {
4710 vmx->soft_vnmi_blocked = masked;
4711 vmx->vnmi_blocked_time = 0;
4712 }
4713 } else {
9d58b931 4714 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4715 if (masked)
4716 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4717 GUEST_INTR_STATE_NMI);
4718 else
4719 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4720 GUEST_INTR_STATE_NMI);
4721 }
4722}
4723
2505dc9f
JK		 4724static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4725{
b6b8a145
JK		 4726 if (to_vmx(vcpu)->nested.nested_run_pending)
4727 return 0;
ea8ceb83 4728
2505dc9f
JK		 4729 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4730 return 0;
4731
4732 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4733 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4734 | GUEST_INTR_STATE_NMI));
4735}
4736
78646121
GN		 4737static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4738{
b6b8a145
JK		 4739 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4740 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4741 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4742 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4743}
4744
cbc94022
IE		 4745static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4746{
4747 int ret;
4748 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4749 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4750 .guest_phys_addr = addr,
4751 .memory_size = PAGE_SIZE * 3,
4752 .flags = 0,
4753 };
4754
47ae31e2 4755 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4756 if (ret)
4757 return ret;
bfc6d222 4758 kvm->arch.tss_addr = addr;
1f755a82 4759 return init_rmode_tss(kvm);
cbc94022
IE		 4760}
4761
0ca1b4f4 4762static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4763{
77ab6db0 4764 switch (vec) {
77ab6db0 4765 case BP_VECTOR:
c573cd22
JK		 4766 /*
4767 * Update instruction length as we may reinject the exception
4768 * from user space while in guest debugging mode.
4769 */
4770 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4771 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4772 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4773 return false;
4774 /* fall through */
4775 case DB_VECTOR:
4776 if (vcpu->guest_debug &
4777 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4778 return false;
d0bfb940
JK		 4779 /* fall through */
4780 case DE_VECTOR:
77ab6db0
JK		 4781 case OF_VECTOR:
4782 case BR_VECTOR:
4783 case UD_VECTOR:
4784 case DF_VECTOR:
4785 case SS_VECTOR:
4786 case GP_VECTOR:
4787 case MF_VECTOR:
0ca1b4f4
GN		 4788 return true;
4789 break;
77ab6db0 4790 }
0ca1b4f4
GN		 4791 return false;
4792}
4793
4794static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4795 int vec, u32 err_code)
4796{
4797 /*
4798 * Instruction with address size override prefix opcode 0x67
4799 * Cause the #SS fault with 0 error code in VM86 mode.
4800 */
4801 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4802 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4803 if (vcpu->arch.halt_request) {
4804 vcpu->arch.halt_request = 0;
4805 return kvm_emulate_halt(vcpu);
4806 }
4807 return 1;
4808 }
4809 return 0;
4810 }
4811
4812 /*
4813 * Forward all other exceptions that are valid in real mode.
4814 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4815 * the required debugging infrastructure rework.
4816 */
4817 kvm_queue_exception(vcpu, vec);
4818 return 1;
6aa8b732
AK		 4819}
4820
a0861c02
AK		 4821/*
4822 * Trigger machine check on the host. We assume all the MSRs are already set up
4823 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4824 * We pass a fake environment to the machine check handler because we want
4825 * the guest to be always treated like user space, no matter what context
4826 * it used internally.
4827 */
4828static void kvm_machine_check(void)
4829{
4830#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4831 struct pt_regs regs = {
4832 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4833 .flags = X86_EFLAGS_IF,
4834 };
4835
4836 do_machine_check(&regs, 0);
4837#endif
4838}
4839
851ba692 4840static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4841{
4842 /* already handled by vcpu_run */
4843 return 1;
4844}
4845
851ba692 4846static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4847{
1155f76a 4848 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4849 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4850 u32 intr_info, ex_no, error_code;
42dbaa5a 4851 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4852 u32 vect_info;
4853 enum emulation_result er;
4854
1155f76a 4855 vect_info = vmx->idt_vectoring_info;
88786475 4856 intr_info = vmx->exit_intr_info;
6aa8b732 4857
a0861c02 4858 if (is_machine_check(intr_info))
851ba692 4859 return handle_machine_check(vcpu);
a0861c02 4860
e4a41889 4861 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4862 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4863
4864 if (is_no_device(intr_info)) {
5fd86fcf 4865 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4866 return 1;
4867 }
4868
7aa81cc0 4869 if (is_invalid_opcode(intr_info)) {
51d8b661 4870 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4871 if (er != EMULATE_DONE)
7ee5d940 4872 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4873 return 1;
4874 }
4875
6aa8b732 4876 error_code = 0;
2e11384c 4877 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4878 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4879
4880 /*
4881 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4882 * MMIO, it is better to report an internal error.
4883 * See the comments in vmx_handle_exit.
4884 */
4885 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4886 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4887 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4888 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4889 vcpu->run->internal.ndata = 2;
4890 vcpu->run->internal.data[0] = vect_info;
4891 vcpu->run->internal.data[1] = intr_info;
4892 return 0;
4893 }
4894
6aa8b732 4895 if (is_page_fault(intr_info)) {
1439442c 4896 /* EPT won't cause page fault directly */
cf3ace79 4897 BUG_ON(enable_ept);
6aa8b732 4898 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4899 trace_kvm_page_fault(cr2, error_code);
4900
3298b75c 4901 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4902 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4903 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4904 }
4905
d0bfb940 4906 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4907
4908 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4909 return handle_rmode_exception(vcpu, ex_no, error_code);
4910
42dbaa5a
JK		 4911 switch (ex_no) {
4912 case DB_VECTOR:
4913 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4914 if (!(vcpu->guest_debug &
4915 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4916 vcpu->arch.dr6 &= ~15;
6f43ed01 4917 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 4918 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4919 skip_emulated_instruction(vcpu);
4920
42dbaa5a
JK		 4921 kvm_queue_exception(vcpu, DB_VECTOR);
4922 return 1;
4923 }
4924 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4925 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4926 /* fall through */
4927 case BP_VECTOR:
c573cd22
JK		 4928 /*
4929 * Update instruction length as we may reinject #BP from
4930 * user space while in guest debugging mode. Reading it for
4931 * #DB as well causes no harm, it is not used in that case.
4932 */
4933 vmx->vcpu.arch.event_exit_inst_len =
4934 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4935 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4936 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4937 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4938 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4939 break;
4940 default:
d0bfb940
JK		 4941 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4942 kvm_run->ex.exception = ex_no;
4943 kvm_run->ex.error_code = error_code;
42dbaa5a 4944 break;
6aa8b732 4945 }
6aa8b732
AK		 4946 return 0;
4947}
4948
851ba692 4949static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4950{
1165f5fe 4951 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4952 return 1;
4953}
4954
851ba692 4955static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4956{
851ba692 4957 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4958 return 0;
4959}
6aa8b732 4960
851ba692 4961static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4962{
bfdaab09 4963 unsigned long exit_qualification;
34c33d16 4964 int size, in, string;
039576c0 4965 unsigned port;
6aa8b732 4966
bfdaab09 4967 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4968 string = (exit_qualification & 16) != 0;
cf8f70bf 4969 in = (exit_qualification & 8) != 0;
e70669ab 4970
cf8f70bf 4971 ++vcpu->stat.io_exits;
e70669ab 4972
cf8f70bf 4973 if (string || in)
51d8b661 4974 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4975
cf8f70bf
GN		 4976 port = exit_qualification >> 16;
4977 size = (exit_qualification & 7) + 1;
e93f36bc 4978 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4979
4980 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4981}
4982
102d8325
IM		 4983static void
4984vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4985{
4986 /*
4987 * Patch in the VMCALL instruction:
4988 */
4989 hypercall[0] = 0x0f;
4990 hypercall[1] = 0x01;
4991 hypercall[2] = 0xc1;
102d8325
IM		 4992}
4993
92fbc7b1
JK		 4994static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4995{
4996 unsigned long always_on = VMXON_CR0_ALWAYSON;
4997
4998 if (nested_vmx_secondary_ctls_high &
4999 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5000 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5001 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5002 return (val & always_on) == always_on;
5003}
5004
0fa06071 5005/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5006static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5007{
eeadf9e7 5008 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5009 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5010 unsigned long orig_val = val;
5011
eeadf9e7
NHE		 5012 /*
5013 * We get here when L2 changed cr0 in a way that did not change
5014 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5015 * but did change L0 shadowed bits. So we first calculate the
5016 * effective cr0 value that L1 would like to write into the
5017 * hardware. It consists of the L2-owned bits from the new
5018 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5019 */
1a0d74e6
JK		 5020 val = (val & ~vmcs12->cr0_guest_host_mask) |
5021 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5022
92fbc7b1 5023 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 5024 return 1;
1a0d74e6
JK		 5025
5026 if (kvm_set_cr0(vcpu, val))
5027 return 1;
5028 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5029 return 0;
1a0d74e6
JK		 5030 } else {
5031 if (to_vmx(vcpu)->nested.vmxon &&
5032 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5033 return 1;
eeadf9e7 5034 return kvm_set_cr0(vcpu, val);
1a0d74e6 5035 }
eeadf9e7
NHE		 5036}
5037
5038static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5039{
5040 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5041 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5042 unsigned long orig_val = val;
5043
5044 /* analogously to handle_set_cr0 */
5045 val = (val & ~vmcs12->cr4_guest_host_mask) |
5046 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5047 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5048 return 1;
1a0d74e6 5049 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5050 return 0;
5051 } else
5052 return kvm_set_cr4(vcpu, val);
5053}
5054
5055/* called to set cr0 as approriate for clts instruction exit. */
5056static void handle_clts(struct kvm_vcpu *vcpu)
5057{
5058 if (is_guest_mode(vcpu)) {
5059 /*
5060 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5061 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5062 * just pretend it's off (also in arch.cr0 for fpu_activate).
5063 */
5064 vmcs_writel(CR0_READ_SHADOW,
5065 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5066 vcpu->arch.cr0 &= ~X86_CR0_TS;
5067 } else
5068 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5069}
5070
851ba692 5071static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5072{
229456fc 5073 unsigned long exit_qualification, val;
6aa8b732
AK		 5074 int cr;
5075 int reg;
49a9b07e 5076 int err;
6aa8b732 5077
bfdaab09 5078 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5079 cr = exit_qualification & 15;
5080 reg = (exit_qualification >> 8) & 15;
5081 switch ((exit_qualification >> 4) & 3) {
5082 case 0: /* mov to cr */
1e32c079 5083 val = kvm_register_readl(vcpu, reg);
229456fc 5084 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5085 switch (cr) {
5086 case 0:
eeadf9e7 5087 err = handle_set_cr0(vcpu, val);
db8fcefa 5088 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5089 return 1;
5090 case 3:
2390218b 5091 err = kvm_set_cr3(vcpu, val);
db8fcefa 5092 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5093 return 1;
5094 case 4:
eeadf9e7 5095 err = handle_set_cr4(vcpu, val);
db8fcefa 5096 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5097 return 1;
0a5fff19
GN		 5098 case 8: {
5099 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5100 u8 cr8 = (u8)val;
eea1cff9 5101 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5102 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5103 if (irqchip_in_kernel(vcpu->kvm))
5104 return 1;
5105 if (cr8_prev <= cr8)
5106 return 1;
851ba692 5107 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5108 return 0;
5109 }
4b8073e4 5110 }
6aa8b732 5111 break;
25c4c276 5112 case 2: /* clts */
eeadf9e7 5113 handle_clts(vcpu);
4d4ec087 5114 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5115 skip_emulated_instruction(vcpu);
6b52d186 5116 vmx_fpu_activate(vcpu);
25c4c276 5117 return 1;
6aa8b732
AK		 5118 case 1: /*mov from cr*/
5119 switch (cr) {
5120 case 3:
9f8fe504
AK		 5121 val = kvm_read_cr3(vcpu);
5122 kvm_register_write(vcpu, reg, val);
5123 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5124 skip_emulated_instruction(vcpu);
5125 return 1;
5126 case 8:
229456fc
MT		 5127 val = kvm_get_cr8(vcpu);
5128 kvm_register_write(vcpu, reg, val);
5129 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5130 skip_emulated_instruction(vcpu);
5131 return 1;
5132 }
5133 break;
5134 case 3: /* lmsw */
a1f83a74 5135 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5136 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5137 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5138
5139 skip_emulated_instruction(vcpu);
5140 return 1;
5141 default:
5142 break;
5143 }
851ba692 5144 vcpu->run->exit_reason = 0;
a737f256 5145 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5146 (int)(exit_qualification >> 4) & 3, cr);
5147 return 0;
5148}
5149
851ba692 5150static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5151{
bfdaab09 5152 unsigned long exit_qualification;
16f8a6f9
NA		 5153 int dr, dr7, reg;
5154
5155 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5156 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5157
5158 /* First, if DR does not exist, trigger UD */
5159 if (!kvm_require_dr(vcpu, dr))
5160 return 1;
6aa8b732 5161
f2483415 5162 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5163 if (!kvm_require_cpl(vcpu, 0))
5164 return 1;
16f8a6f9
NA		 5165 dr7 = vmcs_readl(GUEST_DR7);
5166 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5167 /*
5168 * As the vm-exit takes precedence over the debug trap, we
5169 * need to emulate the latter, either for the host or the
5170 * guest debugging itself.
5171 */
5172 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5173 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5174 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5175 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5176 vcpu->run->debug.arch.exception = DB_VECTOR;
5177 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5178 return 0;
5179 } else {
7305eb5d 5180 vcpu->arch.dr6 &= ~15;
6f43ed01 5181 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5182 kvm_queue_exception(vcpu, DB_VECTOR);
5183 return 1;
5184 }
5185 }
5186
81908bf4
PB		 5187 if (vcpu->guest_debug == 0) {
5188 u32 cpu_based_vm_exec_control;
5189
5190 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5191 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5192 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5193
5194 /*
5195 * No more DR vmexits; force a reload of the debug registers
5196 * and reenter on this instruction. The next vmexit will
5197 * retrieve the full state of the debug registers.
5198 */
5199 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5200 return 1;
5201 }
5202
42dbaa5a
JK		 5203 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5204 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5205 unsigned long val;
4c4d563b
JK		 5206
5207 if (kvm_get_dr(vcpu, dr, &val))
5208 return 1;
5209 kvm_register_write(vcpu, reg, val);
020df079 5210 } else
5777392e 5211 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5212 return 1;
5213
6aa8b732
AK		 5214 skip_emulated_instruction(vcpu);
5215 return 1;
5216}
5217
73aaf249
JK		 5218static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5219{
5220 return vcpu->arch.dr6;
5221}
5222
5223static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5224{
5225}
5226
81908bf4
PB		 5227static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5228{
5229 u32 cpu_based_vm_exec_control;
5230
5231 get_debugreg(vcpu->arch.db[0], 0);
5232 get_debugreg(vcpu->arch.db[1], 1);
5233 get_debugreg(vcpu->arch.db[2], 2);
5234 get_debugreg(vcpu->arch.db[3], 3);
5235 get_debugreg(vcpu->arch.dr6, 6);
5236 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5237
5238 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5239
5240 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5241 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5242 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5243}
5244
020df079
GN		 5245static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5246{
5247 vmcs_writel(GUEST_DR7, val);
5248}
5249
851ba692 5250static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5251{
06465c5a
AK		 5252 kvm_emulate_cpuid(vcpu);
5253 return 1;
6aa8b732
AK		 5254}
5255
851ba692 5256static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5257{
ad312c7c 5258 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5259 u64 data;
5260
5261 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5262 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5263 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5264 return 1;
5265 }
5266
229456fc 5267 trace_kvm_msr_read(ecx, data);
2714d1d3 5268
6aa8b732 5269 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5270 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5271 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5272 skip_emulated_instruction(vcpu);
5273 return 1;
5274}
5275
851ba692 5276static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5277{
8fe8ab46 5278 struct msr_data msr;
ad312c7c
ZX		 5279 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5280 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5281 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5282
8fe8ab46
WA		 5283 msr.data = data;
5284 msr.index = ecx;
5285 msr.host_initiated = false;
854e8bb1 5286 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5287 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5288 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5289 return 1;
5290 }
5291
59200273 5292 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5293 skip_emulated_instruction(vcpu);
5294 return 1;
5295}
5296
851ba692 5297static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5298{
3842d135 5299 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5300 return 1;
5301}
5302
851ba692 5303static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5304{
85f455f7
ED		 5305 u32 cpu_based_vm_exec_control;
5306
5307 /* clear pending irq */
5308 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5309 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5310 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5311
3842d135
AK		 5312 kvm_make_request(KVM_REQ_EVENT, vcpu);
5313
a26bf12a 5314 ++vcpu->stat.irq_window_exits;
2714d1d3 5315
c1150d8c
DL		 5316 /*
5317 * If the user space waits to inject interrupts, exit as soon as
5318 * possible
5319 */
8061823a 5320 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5321 vcpu->run->request_interrupt_window &&
8061823a 5322 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5323 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5324 return 0;
5325 }
6aa8b732
AK		 5326 return 1;
5327}
5328
851ba692 5329static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5330{
5331 skip_emulated_instruction(vcpu);
d3bef15f 5332 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5333}
5334
851ba692 5335static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5336{
510043da 5337 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5338 kvm_emulate_hypercall(vcpu);
5339 return 1;
c21415e8
IM		 5340}
5341
ec25d5e6
GN		 5342static int handle_invd(struct kvm_vcpu *vcpu)
5343{
51d8b661 5344 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5345}
5346
851ba692 5347static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5348{
f9c617f6 5349 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5350
5351 kvm_mmu_invlpg(vcpu, exit_qualification);
5352 skip_emulated_instruction(vcpu);
5353 return 1;
5354}
5355
fee84b07
AK		 5356static int handle_rdpmc(struct kvm_vcpu *vcpu)
5357{
5358 int err;
5359
5360 err = kvm_rdpmc(vcpu);
5361 kvm_complete_insn_gp(vcpu, err);
5362
5363 return 1;
5364}
5365
851ba692 5366static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5367{
5368 skip_emulated_instruction(vcpu);
f5f48ee1 5369 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5370 return 1;
5371}
5372
2acf923e
DC		 5373static int handle_xsetbv(struct kvm_vcpu *vcpu)
5374{
5375 u64 new_bv = kvm_read_edx_eax(vcpu);
5376 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5377
5378 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5379 skip_emulated_instruction(vcpu);
5380 return 1;
5381}
5382
f53cd63c
WL		 5383static int handle_xsaves(struct kvm_vcpu *vcpu)
5384{
5385 skip_emulated_instruction(vcpu);
5386 WARN(1, "this should never happen\n");
5387 return 1;
5388}
5389
5390static int handle_xrstors(struct kvm_vcpu *vcpu)
5391{
5392 skip_emulated_instruction(vcpu);
5393 WARN(1, "this should never happen\n");
5394 return 1;
5395}
5396
851ba692 5397static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5398{
58fbbf26
KT		 5399 if (likely(fasteoi)) {
5400 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5401 int access_type, offset;
5402
5403 access_type = exit_qualification & APIC_ACCESS_TYPE;
5404 offset = exit_qualification & APIC_ACCESS_OFFSET;
5405 /*
5406 * Sane guest uses MOV to write EOI, with written value
5407 * not cared. So make a short-circuit here by avoiding
5408 * heavy instruction emulation.
5409 */
5410 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5411 (offset == APIC_EOI)) {
5412 kvm_lapic_set_eoi(vcpu);
5413 skip_emulated_instruction(vcpu);
5414 return 1;
5415 }
5416 }
51d8b661 5417 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5418}
5419
c7c9c56c
YZ		 5420static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5421{
5422 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5423 int vector = exit_qualification & 0xff;
5424
5425 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5426 kvm_apic_set_eoi_accelerated(vcpu, vector);
5427 return 1;
5428}
5429
83d4c286
YZ		 5430static int handle_apic_write(struct kvm_vcpu *vcpu)
5431{
5432 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5433 u32 offset = exit_qualification & 0xfff;
5434
5435 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5436 kvm_apic_write_nodecode(vcpu, offset);
5437 return 1;
5438}
5439
851ba692 5440static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5441{
60637aac 5442 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5443 unsigned long exit_qualification;
e269fb21
JK		 5444 bool has_error_code = false;
5445 u32 error_code = 0;
37817f29 5446 u16 tss_selector;
7f3d35fd 5447 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5448
5449 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5450 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5451 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5452
5453 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5454
5455 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5456 if (reason == TASK_SWITCH_GATE && idt_v) {
5457 switch (type) {
5458 case INTR_TYPE_NMI_INTR:
5459 vcpu->arch.nmi_injected = false;
654f06fc 5460 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5461 break;
5462 case INTR_TYPE_EXT_INTR:
66fd3f7f 5463 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5464 kvm_clear_interrupt_queue(vcpu);
5465 break;
5466 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5467 if (vmx->idt_vectoring_info &
5468 VECTORING_INFO_DELIVER_CODE_MASK) {
5469 has_error_code = true;
5470 error_code =
5471 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5472 }
5473 /* fall through */
64a7ec06
GN		 5474 case INTR_TYPE_SOFT_EXCEPTION:
5475 kvm_clear_exception_queue(vcpu);
5476 break;
5477 default:
5478 break;
5479 }
60637aac 5480 }
37817f29
IE		 5481 tss_selector = exit_qualification;
5482
64a7ec06
GN		 5483 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5484 type != INTR_TYPE_EXT_INTR &&
5485 type != INTR_TYPE_NMI_INTR))
5486 skip_emulated_instruction(vcpu);
5487
7f3d35fd
KW		 5488 if (kvm_task_switch(vcpu, tss_selector,
5489 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5490 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5491 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5492 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5493 vcpu->run->internal.ndata = 0;
42dbaa5a 5494 return 0;
acb54517 5495 }
42dbaa5a
JK		 5496
5497 /* clear all local breakpoint enable flags */
0e8a0996 5498 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
42dbaa5a
JK		 5499
5500 /*
5501 * TODO: What about debug traps on tss switch?
5502 * Are we supposed to inject them and update dr6?
5503 */
5504
5505 return 1;
37817f29
IE		 5506}
5507
851ba692 5508static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5509{
f9c617f6 5510 unsigned long exit_qualification;
1439442c 5511 gpa_t gpa;
4f5982a5 5512 u32 error_code;
1439442c 5513 int gla_validity;
1439442c 5514
f9c617f6 5515 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5516
1439442c
SY		 5517 gla_validity = (exit_qualification >> 7) & 0x3;
5518 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5519 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5520 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5521 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5522 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5523 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5524 (long unsigned int)exit_qualification);
851ba692
AK		 5525 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5526 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5527 return 0;
1439442c
SY		 5528 }
5529
0be9c7a8
GN		 5530 /*
5531 * EPT violation happened while executing iret from NMI,
5532 * "blocked by NMI" bit has to be set before next VM entry.
5533 * There are errata that may cause this bit to not be set:
5534 * AAK134, BY25.
5535 */
bcd1c294
GN		 5536 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5537 cpu_has_virtual_nmis() &&
5538 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5539 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5540
1439442c 5541 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5542 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5543
5544 /* It is a write fault? */
81ed33e4 5545 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5546 /* It is a fetch fault? */
81ed33e4 5547 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5548 /* ept page table is present? */
81ed33e4 5549 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5550
25d92081
YZ		 5551 vcpu->arch.exit_qualification = exit_qualification;
5552
4f5982a5 5553 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5554}
5555
68f89400
MT		 5556static u64 ept_rsvd_mask(u64 spte, int level)
5557{
5558 int i;
5559 u64 mask = 0;
5560
5561 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5562 mask |= (1ULL << i);
5563
a32e8459 5564 if (level == 4)
68f89400
MT		 5565 /* bits 7:3 reserved */
5566 mask |= 0xf8;
a32e8459
WL		 5567 else if (spte & (1ULL << 7))
5568 /*
5569 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5570 * level == 1 if the hypervisor is using the ignored bit 7.
5571 */
5572 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5573 else if (level > 1)
5574 /* bits 6:3 reserved */
5575 mask |= 0x78;
68f89400
MT		 5576
5577 return mask;
5578}
5579
5580static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5581 int level)
5582{
5583 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5584
5585 /* 010b (write-only) */
5586 WARN_ON((spte & 0x7) == 0x2);
5587
5588 /* 110b (write/execute) */
5589 WARN_ON((spte & 0x7) == 0x6);
5590
5591 /* 100b (execute-only) and value not supported by logical processor */
5592 if (!cpu_has_vmx_ept_execute_only())
5593 WARN_ON((spte & 0x7) == 0x4);
5594
5595 /* not 000b */
5596 if ((spte & 0x7)) {
5597 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5598
5599 if (rsvd_bits != 0) {
5600 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5601 __func__, rsvd_bits);
5602 WARN_ON(1);
5603 }
5604
a32e8459
WL		 5605 /* bits 5:3 are _not_ reserved for large page or leaf page */
5606 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5607 u64 ept_mem_type = (spte & 0x38) >> 3;
5608
5609 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5610 ept_mem_type == 7) {
5611 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5612 __func__, ept_mem_type);
5613 WARN_ON(1);
5614 }
5615 }
5616 }
5617}
5618
851ba692 5619static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5620{
5621 u64 sptes[4];
ce88decf 5622 int nr_sptes, i, ret;
68f89400
MT		 5623 gpa_t gpa;
5624
5625 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5626 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5627 skip_emulated_instruction(vcpu);
5628 return 1;
5629 }
68f89400 5630
ce88decf 5631 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5632 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5633 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5634 EMULATE_DONE;
f8f55942
XG		 5635
5636 if (unlikely(ret == RET_MMIO_PF_INVALID))
5637 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5638
b37fbea6 5639 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5640 return 1;
5641
5642 /* It is the real ept misconfig */
68f89400
MT		 5643 printk(KERN_ERR "EPT: Misconfiguration.\n");
5644 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5645
5646 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5647
5648 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5649 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5650
851ba692
AK		 5651 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5652 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5653
5654 return 0;
5655}
5656
851ba692 5657static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5658{
5659 u32 cpu_based_vm_exec_control;
5660
5661 /* clear pending NMI */
5662 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5663 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5664 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5665 ++vcpu->stat.nmi_window_exits;
3842d135 5666 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5667
5668 return 1;
5669}
5670
80ced186 5671static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5672{
8b3079a5
AK		 5673 struct vcpu_vmx *vmx = to_vmx(vcpu);
5674 enum emulation_result err = EMULATE_DONE;
80ced186 5675 int ret = 1;
49e9d557
AK		 5676 u32 cpu_exec_ctrl;
5677 bool intr_window_requested;
b8405c18 5678 unsigned count = 130;
49e9d557
AK		 5679
5680 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5681 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5682
98eb2f8b 5683 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5684 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5685 return handle_interrupt_window(&vmx->vcpu);
5686
de87dcdd
AK		 5687 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5688 return 1;
5689
991eebf9 5690 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5691
ac0a48c3 5692 if (err == EMULATE_USER_EXIT) {
94452b9e 5693 ++vcpu->stat.mmio_exits;
80ced186
MG		 5694 ret = 0;
5695 goto out;
5696 }
1d5a4d9b 5697
de5f70e0
AK		 5698 if (err != EMULATE_DONE) {
5699 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5700 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5701 vcpu->run->internal.ndata = 0;
6d77dbfc 5702 return 0;
de5f70e0 5703 }
ea953ef0 5704
8d76c49e
GN		 5705 if (vcpu->arch.halt_request) {
5706 vcpu->arch.halt_request = 0;
5707 ret = kvm_emulate_halt(vcpu);
5708 goto out;
5709 }
5710
ea953ef0 5711 if (signal_pending(current))
80ced186 5712 goto out;
ea953ef0
MG		 5713 if (need_resched())
5714 schedule();
5715 }
5716
80ced186
MG		 5717out:
5718 return ret;
ea953ef0
MG		 5719}
5720
b4a2d31d
RK		 5721static int __grow_ple_window(int val)
5722{
5723 if (ple_window_grow < 1)
5724 return ple_window;
5725
5726 val = min(val, ple_window_actual_max);
5727
5728 if (ple_window_grow < ple_window)
5729 val *= ple_window_grow;
5730 else
5731 val += ple_window_grow;
5732
5733 return val;
5734}
5735
5736static int __shrink_ple_window(int val, int modifier, int minimum)
5737{
5738 if (modifier < 1)
5739 return ple_window;
5740
5741 if (modifier < ple_window)
5742 val /= modifier;
5743 else
5744 val -= modifier;
5745
5746 return max(val, minimum);
5747}
5748
5749static void grow_ple_window(struct kvm_vcpu *vcpu)
5750{
5751 struct vcpu_vmx *vmx = to_vmx(vcpu);
5752 int old = vmx->ple_window;
5753
5754 vmx->ple_window = __grow_ple_window(old);
5755
5756 if (vmx->ple_window != old)
5757 vmx->ple_window_dirty = true;
7b46268d
RK		 5758
5759 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5760}
5761
5762static void shrink_ple_window(struct kvm_vcpu *vcpu)
5763{
5764 struct vcpu_vmx *vmx = to_vmx(vcpu);
5765 int old = vmx->ple_window;
5766
5767 vmx->ple_window = __shrink_ple_window(old,
5768 ple_window_shrink, ple_window);
5769
5770 if (vmx->ple_window != old)
5771 vmx->ple_window_dirty = true;
7b46268d
RK		 5772
5773 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5774}
5775
5776/*
5777 * ple_window_actual_max is computed to be one grow_ple_window() below
5778 * ple_window_max. (See __grow_ple_window for the reason.)
5779 * This prevents overflows, because ple_window_max is int.
5780 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5781 * this process.
5782 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5783 */
5784static void update_ple_window_actual_max(void)
5785{
5786 ple_window_actual_max =
5787 __shrink_ple_window(max(ple_window_max, ple_window),
5788 ple_window_grow, INT_MIN);
5789}
5790
f2c7648d
TC		 5791static __init int hardware_setup(void)
5792{
34a1cd60
TC		 5793 int r = -ENOMEM, i, msr;
5794
5795 rdmsrl_safe(MSR_EFER, &host_efer);
5796
5797 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5798 kvm_define_shared_msr(i, vmx_msr_index[i]);
5799
5800 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5801 if (!vmx_io_bitmap_a)
5802 return r;
5803
5804 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5805 if (!vmx_io_bitmap_b)
5806 goto out;
5807
5808 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5809 if (!vmx_msr_bitmap_legacy)
5810 goto out1;
5811
5812 vmx_msr_bitmap_legacy_x2apic =
5813 (unsigned long *)__get_free_page(GFP_KERNEL);
5814 if (!vmx_msr_bitmap_legacy_x2apic)
5815 goto out2;
5816
5817 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5818 if (!vmx_msr_bitmap_longmode)
5819 goto out3;
5820
5821 vmx_msr_bitmap_longmode_x2apic =
5822 (unsigned long *)__get_free_page(GFP_KERNEL);
5823 if (!vmx_msr_bitmap_longmode_x2apic)
5824 goto out4;
5825 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5826 if (!vmx_vmread_bitmap)
5827 goto out5;
5828
5829 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5830 if (!vmx_vmwrite_bitmap)
5831 goto out6;
5832
5833 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5834 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5835
5836 /*
5837 * Allow direct access to the PC debug port (it is often used for I/O
5838 * delays, but the vmexits simply slow things down).
5839 */
5840 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5841 clear_bit(0x80, vmx_io_bitmap_a);
5842
5843 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5844
5845 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5846 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
5847
34a1cd60
TC		 5848 if (setup_vmcs_config(&vmcs_config) < 0) {
5849 r = -EIO;
5850 goto out7;
baa03522 5851 }
f2c7648d
TC		 5852
5853 if (boot_cpu_has(X86_FEATURE_NX))
5854 kvm_enable_efer_bits(EFER_NX);
5855
5856 if (!cpu_has_vmx_vpid())
5857 enable_vpid = 0;
5858 if (!cpu_has_vmx_shadow_vmcs())
5859 enable_shadow_vmcs = 0;
5860 if (enable_shadow_vmcs)
5861 init_vmcs_shadow_fields();
5862
5863 if (!cpu_has_vmx_ept() ||
5864 !cpu_has_vmx_ept_4levels()) {
5865 enable_ept = 0;
5866 enable_unrestricted_guest = 0;
5867 enable_ept_ad_bits = 0;
5868 }
5869
5870 if (!cpu_has_vmx_ept_ad_bits())
5871 enable_ept_ad_bits = 0;
5872
5873 if (!cpu_has_vmx_unrestricted_guest())
5874 enable_unrestricted_guest = 0;
5875
5876 if (!cpu_has_vmx_flexpriority()) {
5877 flexpriority_enabled = 0;
5878
5879 /*
5880 * set_apic_access_page_addr() is used to reload apic access
5881 * page upon invalidation. No need to do anything if the
5882 * processor does not have the APIC_ACCESS_ADDR VMCS field.
5883 */
5884 kvm_x86_ops->set_apic_access_page_addr = NULL;
5885 }
5886
5887 if (!cpu_has_vmx_tpr_shadow())
5888 kvm_x86_ops->update_cr8_intercept = NULL;
5889
5890 if (enable_ept && !cpu_has_vmx_ept_2m_page())
5891 kvm_disable_largepages();
5892
5893 if (!cpu_has_vmx_ple())
5894 ple_gap = 0;
5895
5896 if (!cpu_has_vmx_apicv())
5897 enable_apicv = 0;
5898
5899 if (enable_apicv)
5900 kvm_x86_ops->update_cr8_intercept = NULL;
5901 else {
5902 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 5903 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d 5904 kvm_x86_ops->deliver_posted_interrupt = NULL;
7c6a98df 5905 kvm_x86_ops->test_posted_interrupt = NULL;
f2c7648d
TC		 5906 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
5907 }
5908
5909 if (nested)
5910 nested_vmx_setup_ctls_msrs();
5911
baa03522
TC		 5912 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
5913 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
5914 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
5915 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
5916 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
5917 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
5918 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
5919
5920 memcpy(vmx_msr_bitmap_legacy_x2apic,
5921 vmx_msr_bitmap_legacy, PAGE_SIZE);
5922 memcpy(vmx_msr_bitmap_longmode_x2apic,
5923 vmx_msr_bitmap_longmode, PAGE_SIZE);
5924
5925 if (enable_apicv) {
5926 for (msr = 0x800; msr <= 0x8ff; msr++)
5927 vmx_disable_intercept_msr_read_x2apic(msr);
5928
5929 /* According SDM, in x2apic mode, the whole id reg is used.
5930 * But in KVM, it only use the highest eight bits. Need to
5931 * intercept it */
5932 vmx_enable_intercept_msr_read_x2apic(0x802);
5933 /* TMCCT */
5934 vmx_enable_intercept_msr_read_x2apic(0x839);
5935 /* TPR */
5936 vmx_disable_intercept_msr_write_x2apic(0x808);
5937 /* EOI */
5938 vmx_disable_intercept_msr_write_x2apic(0x80b);
5939 /* SELF-IPI */
5940 vmx_disable_intercept_msr_write_x2apic(0x83f);
5941 }
5942
5943 if (enable_ept) {
5944 kvm_mmu_set_mask_ptes(0ull,
5945 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
5946 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
5947 0ull, VMX_EPT_EXECUTABLE_MASK);
5948 ept_set_mmio_spte_mask();
5949 kvm_enable_tdp();
5950 } else
5951 kvm_disable_tdp();
5952
5953 update_ple_window_actual_max();
5954
f2c7648d 5955 return alloc_kvm_area();
34a1cd60
TC		 5956
5957out7:
5958 free_page((unsigned long)vmx_vmwrite_bitmap);
5959out6:
5960 free_page((unsigned long)vmx_vmread_bitmap);
5961out5:
5962 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5963out4:
5964 free_page((unsigned long)vmx_msr_bitmap_longmode);
5965out3:
5966 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5967out2:
5968 free_page((unsigned long)vmx_msr_bitmap_legacy);
5969out1:
5970 free_page((unsigned long)vmx_io_bitmap_b);
5971out:
5972 free_page((unsigned long)vmx_io_bitmap_a);
5973
5974 return r;
f2c7648d
TC		 5975}
5976
5977static __exit void hardware_unsetup(void)
5978{
34a1cd60
TC		 5979 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5980 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5981 free_page((unsigned long)vmx_msr_bitmap_legacy);
5982 free_page((unsigned long)vmx_msr_bitmap_longmode);
5983 free_page((unsigned long)vmx_io_bitmap_b);
5984 free_page((unsigned long)vmx_io_bitmap_a);
5985 free_page((unsigned long)vmx_vmwrite_bitmap);
5986 free_page((unsigned long)vmx_vmread_bitmap);
5987
f2c7648d
TC		 5988 free_kvm_area();
5989}
5990
4b8d54f9
ZE		 5991/*
5992 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5993 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5994 */
9fb41ba8 5995static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5996{
b4a2d31d
RK		 5997 if (ple_gap)
5998 grow_ple_window(vcpu);
5999
4b8d54f9
ZE		 6000 skip_emulated_instruction(vcpu);
6001 kvm_vcpu_on_spin(vcpu);
6002
6003 return 1;
6004}
6005
87c00572 6006static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6007{
87c00572 6008 skip_emulated_instruction(vcpu);
59708670
SY		 6009 return 1;
6010}
6011
87c00572
GS		 6012static int handle_mwait(struct kvm_vcpu *vcpu)
6013{
6014 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6015 return handle_nop(vcpu);
6016}
6017
6018static int handle_monitor(struct kvm_vcpu *vcpu)
6019{
6020 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6021 return handle_nop(vcpu);
6022}
6023
ff2f6fe9
NHE		 6024/*
6025 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6026 * We could reuse a single VMCS for all the L2 guests, but we also want the
6027 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6028 * allows keeping them loaded on the processor, and in the future will allow
6029 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6030 * every entry if they never change.
6031 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6032 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6033 *
6034 * The following functions allocate and free a vmcs02 in this pool.
6035 */
6036
6037/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6038static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6039{
6040 struct vmcs02_list *item;
6041 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6042 if (item->vmptr == vmx->nested.current_vmptr) {
6043 list_move(&item->list, &vmx->nested.vmcs02_pool);
6044 return &item->vmcs02;
6045 }
6046
6047 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6048 /* Recycle the least recently used VMCS. */
6049 item = list_entry(vmx->nested.vmcs02_pool.prev,
6050 struct vmcs02_list, list);
6051 item->vmptr = vmx->nested.current_vmptr;
6052 list_move(&item->list, &vmx->nested.vmcs02_pool);
6053 return &item->vmcs02;
6054 }
6055
6056 /* Create a new VMCS */
0fa24ce3 6057 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6058 if (!item)
6059 return NULL;
6060 item->vmcs02.vmcs = alloc_vmcs();
6061 if (!item->vmcs02.vmcs) {
6062 kfree(item);
6063 return NULL;
6064 }
6065 loaded_vmcs_init(&item->vmcs02);
6066 item->vmptr = vmx->nested.current_vmptr;
6067 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6068 vmx->nested.vmcs02_num++;
6069 return &item->vmcs02;
6070}
6071
6072/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6073static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6074{
6075 struct vmcs02_list *item;
6076 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6077 if (item->vmptr == vmptr) {
6078 free_loaded_vmcs(&item->vmcs02);
6079 list_del(&item->list);
6080 kfree(item);
6081 vmx->nested.vmcs02_num--;
6082 return;
6083 }
6084}
6085
6086/*
6087 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6088 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6089 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6090 */
6091static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6092{
6093 struct vmcs02_list *item, *n;
4fa7734c
PB		 6094
6095 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6096 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6097 /*
6098 * Something will leak if the above WARN triggers. Better than
6099 * a use-after-free.
6100 */
6101 if (vmx->loaded_vmcs == &item->vmcs02)
6102 continue;
6103
6104 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6105 list_del(&item->list);
6106 kfree(item);
4fa7734c 6107 vmx->nested.vmcs02_num--;
ff2f6fe9 6108 }
ff2f6fe9
NHE		 6109}
6110
0658fbaa
ACL		 6111/*
6112 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6113 * set the success or error code of an emulated VMX instruction, as specified
6114 * by Vol 2B, VMX Instruction Reference, "Conventions".
6115 */
6116static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6117{
6118 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6119 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6120 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6121}
6122
6123static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6124{
6125 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6126 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6127 X86_EFLAGS_SF | X86_EFLAGS_OF))
6128 | X86_EFLAGS_CF);
6129}
6130
145c28dd 6131static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6132 u32 vm_instruction_error)
6133{
6134 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6135 /*
6136 * failValid writes the error number to the current VMCS, which
6137 * can't be done there isn't a current VMCS.
6138 */
6139 nested_vmx_failInvalid(vcpu);
6140 return;
6141 }
6142 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6143 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6144 X86_EFLAGS_SF | X86_EFLAGS_OF))
6145 | X86_EFLAGS_ZF);
6146 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6147 /*
6148 * We don't need to force a shadow sync because
6149 * VM_INSTRUCTION_ERROR is not shadowed
6150 */
6151}
145c28dd 6152
ff651cb6
WV		 6153static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6154{
6155 /* TODO: not to reset guest simply here. */
6156 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6157 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6158}
6159
f4124500
JK		 6160static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6161{
6162 struct vcpu_vmx *vmx =
6163 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6164
6165 vmx->nested.preemption_timer_expired = true;
6166 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6167 kvm_vcpu_kick(&vmx->vcpu);
6168
6169 return HRTIMER_NORESTART;
6170}
6171
19677e32
BD		 6172/*
6173 * Decode the memory-address operand of a vmx instruction, as recorded on an
6174 * exit caused by such an instruction (run by a guest hypervisor).
6175 * On success, returns 0. When the operand is invalid, returns 1 and throws
6176 * #UD or #GP.
6177 */
6178static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6179 unsigned long exit_qualification,
6180 u32 vmx_instruction_info, gva_t *ret)
6181{
6182 /*
6183 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6184 * Execution", on an exit, vmx_instruction_info holds most of the
6185 * addressing components of the operand. Only the displacement part
6186 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6187 * For how an actual address is calculated from all these components,
6188 * refer to Vol. 1, "Operand Addressing".
6189 */
6190 int scaling = vmx_instruction_info & 3;
6191 int addr_size = (vmx_instruction_info >> 7) & 7;
6192 bool is_reg = vmx_instruction_info & (1u << 10);
6193 int seg_reg = (vmx_instruction_info >> 15) & 7;
6194 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6195 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6196 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6197 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6198
6199 if (is_reg) {
6200 kvm_queue_exception(vcpu, UD_VECTOR);
6201 return 1;
6202 }
6203
6204 /* Addr = segment_base + offset */
6205 /* offset = base + [index * scale] + displacement */
6206 *ret = vmx_get_segment_base(vcpu, seg_reg);
6207 if (base_is_valid)
6208 *ret += kvm_register_read(vcpu, base_reg);
6209 if (index_is_valid)
6210 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6211 *ret += exit_qualification; /* holds the displacement */
6212
6213 if (addr_size == 1) /* 32 bit */
6214 *ret &= 0xffffffff;
6215
6216 /*
6217 * TODO: throw #GP (and return 1) in various cases that the VM*
6218 * instructions require it - e.g., offset beyond segment limit,
6219 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6220 * address, and so on. Currently these are not checked.
6221 */
6222 return 0;
6223}
6224
3573e22c
BD		 6225/*
6226 * This function performs the various checks including
6227 * - if it's 4KB aligned
6228 * - No bits beyond the physical address width are set
6229 * - Returns 0 on success or else 1
4291b588 6230 * (Intel SDM Section 30.3)
3573e22c 6231 */
4291b588
BD		 6232static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6233 gpa_t *vmpointer)
3573e22c
BD		 6234{
6235 gva_t gva;
6236 gpa_t vmptr;
6237 struct x86_exception e;
6238 struct page *page;
6239 struct vcpu_vmx *vmx = to_vmx(vcpu);
6240 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6241
6242 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6243 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6244 return 1;
6245
6246 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6247 sizeof(vmptr), &e)) {
6248 kvm_inject_page_fault(vcpu, &e);
6249 return 1;
6250 }
6251
6252 switch (exit_reason) {
6253 case EXIT_REASON_VMON:
6254 /*
6255 * SDM 3: 24.11.5
6256 * The first 4 bytes of VMXON region contain the supported
6257 * VMCS revision identifier
6258 *
6259 * Note - IA32_VMX_BASIC[48] will never be 1
6260 * for the nested case;
6261 * which replaces physical address width with 32
6262 *
6263 */
bc39c4db 6264 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6265 nested_vmx_failInvalid(vcpu);
6266 skip_emulated_instruction(vcpu);
6267 return 1;
6268 }
6269
6270 page = nested_get_page(vcpu, vmptr);
6271 if (page == NULL ||
6272 *(u32 *)kmap(page) != VMCS12_REVISION) {
6273 nested_vmx_failInvalid(vcpu);
6274 kunmap(page);
6275 skip_emulated_instruction(vcpu);
6276 return 1;
6277 }
6278 kunmap(page);
6279 vmx->nested.vmxon_ptr = vmptr;
6280 break;
4291b588 6281 case EXIT_REASON_VMCLEAR:
bc39c4db 6282 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6283 nested_vmx_failValid(vcpu,
6284 VMXERR_VMCLEAR_INVALID_ADDRESS);
6285 skip_emulated_instruction(vcpu);
6286 return 1;
6287 }
6288
6289 if (vmptr == vmx->nested.vmxon_ptr) {
6290 nested_vmx_failValid(vcpu,
6291 VMXERR_VMCLEAR_VMXON_POINTER);
6292 skip_emulated_instruction(vcpu);
6293 return 1;
6294 }
6295 break;
6296 case EXIT_REASON_VMPTRLD:
bc39c4db 6297 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6298 nested_vmx_failValid(vcpu,
6299 VMXERR_VMPTRLD_INVALID_ADDRESS);
6300 skip_emulated_instruction(vcpu);
6301 return 1;
6302 }
3573e22c 6303
4291b588
BD		 6304 if (vmptr == vmx->nested.vmxon_ptr) {
6305 nested_vmx_failValid(vcpu,
6306 VMXERR_VMCLEAR_VMXON_POINTER);
6307 skip_emulated_instruction(vcpu);
6308 return 1;
6309 }
6310 break;
3573e22c
BD		 6311 default:
6312 return 1; /* shouldn't happen */
6313 }
6314
4291b588
BD		 6315 if (vmpointer)
6316 *vmpointer = vmptr;
3573e22c
BD		 6317 return 0;
6318}
6319
ec378aee
NHE		 6320/*
6321 * Emulate the VMXON instruction.
6322 * Currently, we just remember that VMX is active, and do not save or even
6323 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6324 * do not currently need to store anything in that guest-allocated memory
6325 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6326 * argument is different from the VMXON pointer (which the spec says they do).
6327 */
6328static int handle_vmon(struct kvm_vcpu *vcpu)
6329{
6330 struct kvm_segment cs;
6331 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6332 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6333 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6334 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6335
6336 /* The Intel VMX Instruction Reference lists a bunch of bits that
6337 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6338 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6339 * Otherwise, we should fail with #UD. We test these now:
6340 */
6341 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6342 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6343 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6344 kvm_queue_exception(vcpu, UD_VECTOR);
6345 return 1;
6346 }
6347
6348 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6349 if (is_long_mode(vcpu) && !cs.l) {
6350 kvm_queue_exception(vcpu, UD_VECTOR);
6351 return 1;
6352 }
6353
6354 if (vmx_get_cpl(vcpu)) {
6355 kvm_inject_gp(vcpu, 0);
6356 return 1;
6357 }
3573e22c 6358
4291b588 6359 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6360 return 1;
6361
145c28dd
AG		 6362 if (vmx->nested.vmxon) {
6363 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6364 skip_emulated_instruction(vcpu);
6365 return 1;
6366 }
b3897a49
NHE		 6367
6368 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6369 != VMXON_NEEDED_FEATURES) {
6370 kvm_inject_gp(vcpu, 0);
6371 return 1;
6372 }
6373
8de48833
AG		 6374 if (enable_shadow_vmcs) {
6375 shadow_vmcs = alloc_vmcs();
6376 if (!shadow_vmcs)
6377 return -ENOMEM;
6378 /* mark vmcs as shadow */
6379 shadow_vmcs->revision_id |= (1u << 31);
6380 /* init shadow vmcs */
6381 vmcs_clear(shadow_vmcs);
6382 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6383 }
ec378aee 6384
ff2f6fe9
NHE		 6385 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6386 vmx->nested.vmcs02_num = 0;
6387
f4124500
JK		 6388 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6389 HRTIMER_MODE_REL);
6390 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6391
ec378aee
NHE		 6392 vmx->nested.vmxon = true;
6393
6394 skip_emulated_instruction(vcpu);
a25eb114 6395 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6396 return 1;
6397}
6398
6399/*
6400 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6401 * for running VMX instructions (except VMXON, whose prerequisites are
6402 * slightly different). It also specifies what exception to inject otherwise.
6403 */
6404static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6405{
6406 struct kvm_segment cs;
6407 struct vcpu_vmx *vmx = to_vmx(vcpu);
6408
6409 if (!vmx->nested.vmxon) {
6410 kvm_queue_exception(vcpu, UD_VECTOR);
6411 return 0;
6412 }
6413
6414 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6415 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6416 (is_long_mode(vcpu) && !cs.l)) {
6417 kvm_queue_exception(vcpu, UD_VECTOR);
6418 return 0;
6419 }
6420
6421 if (vmx_get_cpl(vcpu)) {
6422 kvm_inject_gp(vcpu, 0);
6423 return 0;
6424 }
6425
6426 return 1;
6427}
6428
e7953d7f
AG		 6429static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6430{
8a1b9dd0 6431 u32 exec_control;
9a2a05b9
PB		 6432 if (vmx->nested.current_vmptr == -1ull)
6433 return;
6434
6435 /* current_vmptr and current_vmcs12 are always set/reset together */
6436 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6437 return;
6438
012f83cb 6439 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6440 /* copy to memory all shadowed fields in case
6441 they were modified */
6442 copy_shadow_to_vmcs12(vmx);
6443 vmx->nested.sync_shadow_vmcs = false;
6444 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6445 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6446 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6447 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6448 }
e7953d7f
AG		 6449 kunmap(vmx->nested.current_vmcs12_page);
6450 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6451 vmx->nested.current_vmptr = -1ull;
6452 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6453}
6454
ec378aee
NHE		 6455/*
6456 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6457 * just stops using VMX.
6458 */
6459static void free_nested(struct vcpu_vmx *vmx)
6460{
6461 if (!vmx->nested.vmxon)
6462 return;
9a2a05b9 6463
ec378aee 6464 vmx->nested.vmxon = false;
9a2a05b9 6465 nested_release_vmcs12(vmx);
e7953d7f
AG		 6466 if (enable_shadow_vmcs)
6467 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6468 /* Unpin physical memory we referred to in current vmcs02 */
6469 if (vmx->nested.apic_access_page) {
6470 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6471 vmx->nested.apic_access_page = NULL;
fe3ef05c 6472 }
a7c0b07d
WL		 6473 if (vmx->nested.virtual_apic_page) {
6474 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6475 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6476 }
ff2f6fe9
NHE		 6477
6478 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6479}
6480
6481/* Emulate the VMXOFF instruction */
6482static int handle_vmoff(struct kvm_vcpu *vcpu)
6483{
6484 if (!nested_vmx_check_permission(vcpu))
6485 return 1;
6486 free_nested(to_vmx(vcpu));
6487 skip_emulated_instruction(vcpu);
a25eb114 6488 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6489 return 1;
6490}
6491
27d6c865
NHE		 6492/* Emulate the VMCLEAR instruction */
6493static int handle_vmclear(struct kvm_vcpu *vcpu)
6494{
6495 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6496 gpa_t vmptr;
6497 struct vmcs12 *vmcs12;
6498 struct page *page;
27d6c865
NHE		 6499
6500 if (!nested_vmx_check_permission(vcpu))
6501 return 1;
6502
4291b588 6503 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6504 return 1;
27d6c865 6505
9a2a05b9 6506 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6507 nested_release_vmcs12(vmx);
27d6c865
NHE		 6508
6509 page = nested_get_page(vcpu, vmptr);
6510 if (page == NULL) {
6511 /*
6512 * For accurate processor emulation, VMCLEAR beyond available
6513 * physical memory should do nothing at all. However, it is
6514 * possible that a nested vmx bug, not a guest hypervisor bug,
6515 * resulted in this case, so let's shut down before doing any
6516 * more damage:
6517 */
6518 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6519 return 1;
6520 }
6521 vmcs12 = kmap(page);
6522 vmcs12->launch_state = 0;
6523 kunmap(page);
6524 nested_release_page(page);
6525
6526 nested_free_vmcs02(vmx, vmptr);
6527
6528 skip_emulated_instruction(vcpu);
6529 nested_vmx_succeed(vcpu);
6530 return 1;
6531}
6532
cd232ad0
NHE		 6533static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6534
6535/* Emulate the VMLAUNCH instruction */
6536static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6537{
6538 return nested_vmx_run(vcpu, true);
6539}
6540
6541/* Emulate the VMRESUME instruction */
6542static int handle_vmresume(struct kvm_vcpu *vcpu)
6543{
6544
6545 return nested_vmx_run(vcpu, false);
6546}
6547
49f705c5
NHE		 6548enum vmcs_field_type {
6549 VMCS_FIELD_TYPE_U16 = 0,
6550 VMCS_FIELD_TYPE_U64 = 1,
6551 VMCS_FIELD_TYPE_U32 = 2,
6552 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6553};
6554
6555static inline int vmcs_field_type(unsigned long field)
6556{
6557 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6558 return VMCS_FIELD_TYPE_U32;
6559 return (field >> 13) & 0x3 ;
6560}
6561
6562static inline int vmcs_field_readonly(unsigned long field)
6563{
6564 return (((field >> 10) & 0x3) == 1);
6565}
6566
6567/*
6568 * Read a vmcs12 field. Since these can have varying lengths and we return
6569 * one type, we chose the biggest type (u64) and zero-extend the return value
6570 * to that size. Note that the caller, handle_vmread, might need to use only
6571 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6572 * 64-bit fields are to be returned).
6573 */
a2ae9df7
PB		 6574static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6575 unsigned long field, u64 *ret)
49f705c5
NHE		 6576{
6577 short offset = vmcs_field_to_offset(field);
6578 char *p;
6579
6580 if (offset < 0)
a2ae9df7 6581 return offset;
49f705c5
NHE		 6582
6583 p = ((char *)(get_vmcs12(vcpu))) + offset;
6584
6585 switch (vmcs_field_type(field)) {
6586 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6587 *ret = *((natural_width *)p);
a2ae9df7 6588 return 0;
49f705c5
NHE		 6589 case VMCS_FIELD_TYPE_U16:
6590 *ret = *((u16 *)p);
a2ae9df7 6591 return 0;
49f705c5
NHE		 6592 case VMCS_FIELD_TYPE_U32:
6593 *ret = *((u32 *)p);
a2ae9df7 6594 return 0;
49f705c5
NHE		 6595 case VMCS_FIELD_TYPE_U64:
6596 *ret = *((u64 *)p);
a2ae9df7 6597 return 0;
49f705c5 6598 default:
a2ae9df7
PB		 6599 WARN_ON(1);
6600 return -ENOENT;
49f705c5
NHE		 6601 }
6602}
6603
20b97fea 6604
a2ae9df7
PB		 6605static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6606 unsigned long field, u64 field_value){
20b97fea
AG		 6607 short offset = vmcs_field_to_offset(field);
6608 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6609 if (offset < 0)
a2ae9df7 6610 return offset;
20b97fea
AG		 6611
6612 switch (vmcs_field_type(field)) {
6613 case VMCS_FIELD_TYPE_U16:
6614 *(u16 *)p = field_value;
a2ae9df7 6615 return 0;
20b97fea
AG		 6616 case VMCS_FIELD_TYPE_U32:
6617 *(u32 *)p = field_value;
a2ae9df7 6618 return 0;
20b97fea
AG		 6619 case VMCS_FIELD_TYPE_U64:
6620 *(u64 *)p = field_value;
a2ae9df7 6621 return 0;
20b97fea
AG		 6622 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6623 *(natural_width *)p = field_value;
a2ae9df7 6624 return 0;
20b97fea 6625 default:
a2ae9df7
PB		 6626 WARN_ON(1);
6627 return -ENOENT;
20b97fea
AG		 6628 }
6629
6630}
6631
16f5b903
AG		 6632static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6633{
6634 int i;
6635 unsigned long field;
6636 u64 field_value;
6637 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6638 const unsigned long *fields = shadow_read_write_fields;
6639 const int num_fields = max_shadow_read_write_fields;
16f5b903 6640
282da870
JK		 6641 preempt_disable();
6642
16f5b903
AG		 6643 vmcs_load(shadow_vmcs);
6644
6645 for (i = 0; i < num_fields; i++) {
6646 field = fields[i];
6647 switch (vmcs_field_type(field)) {
6648 case VMCS_FIELD_TYPE_U16:
6649 field_value = vmcs_read16(field);
6650 break;
6651 case VMCS_FIELD_TYPE_U32:
6652 field_value = vmcs_read32(field);
6653 break;
6654 case VMCS_FIELD_TYPE_U64:
6655 field_value = vmcs_read64(field);
6656 break;
6657 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6658 field_value = vmcs_readl(field);
6659 break;
a2ae9df7
PB		 6660 default:
6661 WARN_ON(1);
6662 continue;
16f5b903
AG		 6663 }
6664 vmcs12_write_any(&vmx->vcpu, field, field_value);
6665 }
6666
6667 vmcs_clear(shadow_vmcs);
6668 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6669
6670 preempt_enable();
16f5b903
AG		 6671}
6672
c3114420
AG		 6673static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6674{
c2bae893
MK		 6675 const unsigned long *fields[] = {
6676 shadow_read_write_fields,
6677 shadow_read_only_fields
c3114420 6678 };
c2bae893 6679 const int max_fields[] = {
c3114420
AG		 6680 max_shadow_read_write_fields,
6681 max_shadow_read_only_fields
6682 };
6683 int i, q;
6684 unsigned long field;
6685 u64 field_value = 0;
6686 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6687
6688 vmcs_load(shadow_vmcs);
6689
c2bae893 6690 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6691 for (i = 0; i < max_fields[q]; i++) {
6692 field = fields[q][i];
6693 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6694
6695 switch (vmcs_field_type(field)) {
6696 case VMCS_FIELD_TYPE_U16:
6697 vmcs_write16(field, (u16)field_value);
6698 break;
6699 case VMCS_FIELD_TYPE_U32:
6700 vmcs_write32(field, (u32)field_value);
6701 break;
6702 case VMCS_FIELD_TYPE_U64:
6703 vmcs_write64(field, (u64)field_value);
6704 break;
6705 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6706 vmcs_writel(field, (long)field_value);
6707 break;
a2ae9df7
PB		 6708 default:
6709 WARN_ON(1);
6710 break;
c3114420
AG		 6711 }
6712 }
6713 }
6714
6715 vmcs_clear(shadow_vmcs);
6716 vmcs_load(vmx->loaded_vmcs->vmcs);
6717}
6718
49f705c5
NHE		 6719/*
6720 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6721 * used before) all generate the same failure when it is missing.
6722 */
6723static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6724{
6725 struct vcpu_vmx *vmx = to_vmx(vcpu);
6726 if (vmx->nested.current_vmptr == -1ull) {
6727 nested_vmx_failInvalid(vcpu);
6728 skip_emulated_instruction(vcpu);
6729 return 0;
6730 }
6731 return 1;
6732}
6733
6734static int handle_vmread(struct kvm_vcpu *vcpu)
6735{
6736 unsigned long field;
6737 u64 field_value;
6738 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6739 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6740 gva_t gva = 0;
6741
6742 if (!nested_vmx_check_permission(vcpu) ||
6743 !nested_vmx_check_vmcs12(vcpu))
6744 return 1;
6745
6746 /* Decode instruction info and find the field to read */
27e6fb5d 6747 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6748 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6749 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6750 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6751 skip_emulated_instruction(vcpu);
6752 return 1;
6753 }
6754 /*
6755 * Now copy part of this value to register or memory, as requested.
6756 * Note that the number of bits actually copied is 32 or 64 depending
6757 * on the guest's mode (32 or 64 bit), not on the given field's length.
6758 */
6759 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6760 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6761 field_value);
6762 } else {
6763 if (get_vmx_mem_address(vcpu, exit_qualification,
6764 vmx_instruction_info, &gva))
6765 return 1;
6766 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6767 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6768 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6769 }
6770
6771 nested_vmx_succeed(vcpu);
6772 skip_emulated_instruction(vcpu);
6773 return 1;
6774}
6775
6776
6777static int handle_vmwrite(struct kvm_vcpu *vcpu)
6778{
6779 unsigned long field;
6780 gva_t gva;
6781 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6782 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6783 /* The value to write might be 32 or 64 bits, depending on L1's long
6784 * mode, and eventually we need to write that into a field of several
6785 * possible lengths. The code below first zero-extends the value to 64
6786 * bit (field_value), and then copies only the approriate number of
6787 * bits into the vmcs12 field.
6788 */
6789 u64 field_value = 0;
6790 struct x86_exception e;
6791
6792 if (!nested_vmx_check_permission(vcpu) ||
6793 !nested_vmx_check_vmcs12(vcpu))
6794 return 1;
6795
6796 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6797 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6798 (((vmx_instruction_info) >> 3) & 0xf));
6799 else {
6800 if (get_vmx_mem_address(vcpu, exit_qualification,
6801 vmx_instruction_info, &gva))
6802 return 1;
6803 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6804 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6805 kvm_inject_page_fault(vcpu, &e);
6806 return 1;
6807 }
6808 }
6809
6810
27e6fb5d 6811 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6812 if (vmcs_field_readonly(field)) {
6813 nested_vmx_failValid(vcpu,
6814 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6815 skip_emulated_instruction(vcpu);
6816 return 1;
6817 }
6818
a2ae9df7 6819 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 6820 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6821 skip_emulated_instruction(vcpu);
6822 return 1;
6823 }
6824
6825 nested_vmx_succeed(vcpu);
6826 skip_emulated_instruction(vcpu);
6827 return 1;
6828}
6829
63846663
NHE		 6830/* Emulate the VMPTRLD instruction */
6831static int handle_vmptrld(struct kvm_vcpu *vcpu)
6832{
6833 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6834 gpa_t vmptr;
8a1b9dd0 6835 u32 exec_control;
63846663
NHE		 6836
6837 if (!nested_vmx_check_permission(vcpu))
6838 return 1;
6839
4291b588 6840 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6841 return 1;
63846663
NHE		 6842
6843 if (vmx->nested.current_vmptr != vmptr) {
6844 struct vmcs12 *new_vmcs12;
6845 struct page *page;
6846 page = nested_get_page(vcpu, vmptr);
6847 if (page == NULL) {
6848 nested_vmx_failInvalid(vcpu);
6849 skip_emulated_instruction(vcpu);
6850 return 1;
6851 }
6852 new_vmcs12 = kmap(page);
6853 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6854 kunmap(page);
6855 nested_release_page_clean(page);
6856 nested_vmx_failValid(vcpu,
6857 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6858 skip_emulated_instruction(vcpu);
6859 return 1;
6860 }
63846663 6861
9a2a05b9 6862 nested_release_vmcs12(vmx);
63846663
NHE		 6863 vmx->nested.current_vmptr = vmptr;
6864 vmx->nested.current_vmcs12 = new_vmcs12;
6865 vmx->nested.current_vmcs12_page = page;
012f83cb 6866 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6867 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6868 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6869 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6870 vmcs_write64(VMCS_LINK_POINTER,
6871 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6872 vmx->nested.sync_shadow_vmcs = true;
6873 }
63846663
NHE		 6874 }
6875
6876 nested_vmx_succeed(vcpu);
6877 skip_emulated_instruction(vcpu);
6878 return 1;
6879}
6880
6a4d7550
NHE		 6881/* Emulate the VMPTRST instruction */
6882static int handle_vmptrst(struct kvm_vcpu *vcpu)
6883{
6884 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6885 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6886 gva_t vmcs_gva;
6887 struct x86_exception e;
6888
6889 if (!nested_vmx_check_permission(vcpu))
6890 return 1;
6891
6892 if (get_vmx_mem_address(vcpu, exit_qualification,
6893 vmx_instruction_info, &vmcs_gva))
6894 return 1;
6895 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6896 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6897 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6898 sizeof(u64), &e)) {
6899 kvm_inject_page_fault(vcpu, &e);
6900 return 1;
6901 }
6902 nested_vmx_succeed(vcpu);
6903 skip_emulated_instruction(vcpu);
6904 return 1;
6905}
6906
bfd0a56b
NHE		 6907/* Emulate the INVEPT instruction */
6908static int handle_invept(struct kvm_vcpu *vcpu)
6909{
6910 u32 vmx_instruction_info, types;
6911 unsigned long type;
6912 gva_t gva;
6913 struct x86_exception e;
6914 struct {
6915 u64 eptp, gpa;
6916 } operand;
bfd0a56b
NHE		 6917
6918 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6919 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6920 kvm_queue_exception(vcpu, UD_VECTOR);
6921 return 1;
6922 }
6923
6924 if (!nested_vmx_check_permission(vcpu))
6925 return 1;
6926
6927 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6928 kvm_queue_exception(vcpu, UD_VECTOR);
6929 return 1;
6930 }
6931
6932 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 6933 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b
NHE		 6934
6935 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6936
6937 if (!(types & (1UL << type))) {
6938 nested_vmx_failValid(vcpu,
6939 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6940 return 1;
6941 }
6942
6943 /* According to the Intel VMX instruction reference, the memory
6944 * operand is read even if it isn't needed (e.g., for type==global)
6945 */
6946 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6947 vmx_instruction_info, &gva))
6948 return 1;
6949 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6950 sizeof(operand), &e)) {
6951 kvm_inject_page_fault(vcpu, &e);
6952 return 1;
6953 }
6954
6955 switch (type) {
bfd0a56b
NHE		 6956 case VMX_EPT_EXTENT_GLOBAL:
6957 kvm_mmu_sync_roots(vcpu);
77c3913b 6958 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 6959 nested_vmx_succeed(vcpu);
6960 break;
6961 default:
4b855078 6962 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6963 BUG_ON(1);
6964 break;
6965 }
6966
6967 skip_emulated_instruction(vcpu);
6968 return 1;
6969}
6970
a642fc30
PM		 6971static int handle_invvpid(struct kvm_vcpu *vcpu)
6972{
6973 kvm_queue_exception(vcpu, UD_VECTOR);
6974 return 1;
6975}
6976
7c6a98df
MT		 6977static bool vmx_test_pir(struct kvm_vcpu *vcpu, int vector)
6978{
6979 struct vcpu_vmx *vmx = to_vmx(vcpu);
6980
6981 return pi_test_pir(vector, &vmx->pi_desc);
6982}
6983
6aa8b732
AK		 6984/*
6985 * The exit handlers return 1 if the exit was handled fully and guest execution
6986 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6987 * to be done to userspace and return 0.
6988 */
772e0318 6989static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6990 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6991 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6992 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6993 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6994 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6995 [EXIT_REASON_CR_ACCESS] = handle_cr,
6996 [EXIT_REASON_DR_ACCESS] = handle_dr,
6997 [EXIT_REASON_CPUID] = handle_cpuid,
6998 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6999 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7000 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7001 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7002 [EXIT_REASON_INVD] = handle_invd,
a7052897 7003 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7004 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7005 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7006 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7007 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7008 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7009 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7010 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7011 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7012 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7013 [EXIT_REASON_VMOFF] = handle_vmoff,
7014 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7015 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7016 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7017 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7018 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7019 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7020 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7021 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7022 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7023 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7024 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7025 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 7026 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7027 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7028 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7029 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7030 [EXIT_REASON_XSAVES] = handle_xsaves,
7031 [EXIT_REASON_XRSTORS] = handle_xrstors,
6aa8b732
AK		 7032};
7033
7034static const int kvm_vmx_max_exit_handlers =
50a3485c 7035 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7036
908a7bdd
JK		 7037static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7038 struct vmcs12 *vmcs12)
7039{
7040 unsigned long exit_qualification;
7041 gpa_t bitmap, last_bitmap;
7042 unsigned int port;
7043 int size;
7044 u8 b;
7045
908a7bdd 7046 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7047 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7048
7049 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7050
7051 port = exit_qualification >> 16;
7052 size = (exit_qualification & 7) + 1;
7053
7054 last_bitmap = (gpa_t)-1;
7055 b = -1;
7056
7057 while (size > 0) {
7058 if (port < 0x8000)
7059 bitmap = vmcs12->io_bitmap_a;
7060 else if (port < 0x10000)
7061 bitmap = vmcs12->io_bitmap_b;
7062 else
7063 return 1;
7064 bitmap += (port & 0x7fff) / 8;
7065
7066 if (last_bitmap != bitmap)
7067 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7068 return 1;
7069 if (b & (1 << (port & 7)))
7070 return 1;
7071
7072 port++;
7073 size--;
7074 last_bitmap = bitmap;
7075 }
7076
7077 return 0;
7078}
7079
644d711a
NHE		 7080/*
7081 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7082 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7083 * disinterest in the current event (read or write a specific MSR) by using an
7084 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7085 */
7086static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7087 struct vmcs12 *vmcs12, u32 exit_reason)
7088{
7089 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7090 gpa_t bitmap;
7091
cbd29cb6 7092 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 7093 return 1;
7094
7095 /*
7096 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7097 * for the four combinations of read/write and low/high MSR numbers.
7098 * First we need to figure out which of the four to use:
7099 */
7100 bitmap = vmcs12->msr_bitmap;
7101 if (exit_reason == EXIT_REASON_MSR_WRITE)
7102 bitmap += 2048;
7103 if (msr_index >= 0xc0000000) {
7104 msr_index -= 0xc0000000;
7105 bitmap += 1024;
7106 }
7107
7108 /* Then read the msr_index'th bit from this bitmap: */
7109 if (msr_index < 1024*8) {
7110 unsigned char b;
bd31a7f5
JK		 7111 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7112 return 1;
644d711a
NHE		 7113 return 1 & (b >> (msr_index & 7));
7114 } else
7115 return 1; /* let L1 handle the wrong parameter */
7116}
7117
7118/*
7119 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7120 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7121 * intercept (via guest_host_mask etc.) the current event.
7122 */
7123static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7124 struct vmcs12 *vmcs12)
7125{
7126 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7127 int cr = exit_qualification & 15;
7128 int reg = (exit_qualification >> 8) & 15;
1e32c079 7129 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7130
7131 switch ((exit_qualification >> 4) & 3) {
7132 case 0: /* mov to cr */
7133 switch (cr) {
7134 case 0:
7135 if (vmcs12->cr0_guest_host_mask &
7136 (val ^ vmcs12->cr0_read_shadow))
7137 return 1;
7138 break;
7139 case 3:
7140 if ((vmcs12->cr3_target_count >= 1 &&
7141 vmcs12->cr3_target_value0 == val) ||
7142 (vmcs12->cr3_target_count >= 2 &&
7143 vmcs12->cr3_target_value1 == val) ||
7144 (vmcs12->cr3_target_count >= 3 &&
7145 vmcs12->cr3_target_value2 == val) ||
7146 (vmcs12->cr3_target_count >= 4 &&
7147 vmcs12->cr3_target_value3 == val))
7148 return 0;
7149 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7150 return 1;
7151 break;
7152 case 4:
7153 if (vmcs12->cr4_guest_host_mask &
7154 (vmcs12->cr4_read_shadow ^ val))
7155 return 1;
7156 break;
7157 case 8:
7158 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7159 return 1;
7160 break;
7161 }
7162 break;
7163 case 2: /* clts */
7164 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7165 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7166 return 1;
7167 break;
7168 case 1: /* mov from cr */
7169 switch (cr) {
7170 case 3:
7171 if (vmcs12->cpu_based_vm_exec_control &
7172 CPU_BASED_CR3_STORE_EXITING)
7173 return 1;
7174 break;
7175 case 8:
7176 if (vmcs12->cpu_based_vm_exec_control &
7177 CPU_BASED_CR8_STORE_EXITING)
7178 return 1;
7179 break;
7180 }
7181 break;
7182 case 3: /* lmsw */
7183 /*
7184 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7185 * cr0. Other attempted changes are ignored, with no exit.
7186 */
7187 if (vmcs12->cr0_guest_host_mask & 0xe &
7188 (val ^ vmcs12->cr0_read_shadow))
7189 return 1;
7190 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7191 !(vmcs12->cr0_read_shadow & 0x1) &&
7192 (val & 0x1))
7193 return 1;
7194 break;
7195 }
7196 return 0;
7197}
7198
7199/*
7200 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7201 * should handle it ourselves in L0 (and then continue L2). Only call this
7202 * when in is_guest_mode (L2).
7203 */
7204static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7205{
644d711a
NHE		 7206 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7207 struct vcpu_vmx *vmx = to_vmx(vcpu);
7208 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7209 u32 exit_reason = vmx->exit_reason;
644d711a 7210
542060ea
JK		 7211 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7212 vmcs_readl(EXIT_QUALIFICATION),
7213 vmx->idt_vectoring_info,
7214 intr_info,
7215 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7216 KVM_ISA_VMX);
7217
644d711a
NHE		 7218 if (vmx->nested.nested_run_pending)
7219 return 0;
7220
7221 if (unlikely(vmx->fail)) {
bd80158a
JK		 7222 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7223 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 7224 return 1;
7225 }
7226
7227 switch (exit_reason) {
7228 case EXIT_REASON_EXCEPTION_NMI:
7229 if (!is_exception(intr_info))
7230 return 0;
7231 else if (is_page_fault(intr_info))
7232 return enable_ept;
e504c909 7233 else if (is_no_device(intr_info) &&
ccf9844e 7234 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 7235 return 0;
644d711a
NHE		 7236 return vmcs12->exception_bitmap &
7237 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7238 case EXIT_REASON_EXTERNAL_INTERRUPT:
7239 return 0;
7240 case EXIT_REASON_TRIPLE_FAULT:
7241 return 1;
7242 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7243 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7244 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7245 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 7246 case EXIT_REASON_TASK_SWITCH:
7247 return 1;
7248 case EXIT_REASON_CPUID:
bc613494
MT		 7249 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7250 return 0;
644d711a
NHE		 7251 return 1;
7252 case EXIT_REASON_HLT:
7253 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7254 case EXIT_REASON_INVD:
7255 return 1;
7256 case EXIT_REASON_INVLPG:
7257 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7258 case EXIT_REASON_RDPMC:
7259 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7260 case EXIT_REASON_RDTSC:
7261 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7262 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7263 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7264 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7265 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7266 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7267 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7268 /*
7269 * VMX instructions trap unconditionally. This allows L1 to
7270 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7271 */
7272 return 1;
7273 case EXIT_REASON_CR_ACCESS:
7274 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7275 case EXIT_REASON_DR_ACCESS:
7276 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7277 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7278 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7279 case EXIT_REASON_MSR_READ:
7280 case EXIT_REASON_MSR_WRITE:
7281 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7282 case EXIT_REASON_INVALID_STATE:
7283 return 1;
7284 case EXIT_REASON_MWAIT_INSTRUCTION:
7285 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7286 case EXIT_REASON_MONITOR_INSTRUCTION:
7287 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7288 case EXIT_REASON_PAUSE_INSTRUCTION:
7289 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7290 nested_cpu_has2(vmcs12,
7291 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7292 case EXIT_REASON_MCE_DURING_VMENTRY:
7293 return 0;
7294 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7295 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7296 case EXIT_REASON_APIC_ACCESS:
7297 return nested_cpu_has2(vmcs12,
7298 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7299 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7300 /*
7301 * L0 always deals with the EPT violation. If nested EPT is
7302 * used, and the nested mmu code discovers that the address is
7303 * missing in the guest EPT table (EPT12), the EPT violation
7304 * will be injected with nested_ept_inject_page_fault()
7305 */
7306 return 0;
644d711a 7307 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7308 /*
7309 * L2 never uses directly L1's EPT, but rather L0's own EPT
7310 * table (shadow on EPT) or a merged EPT table that L0 built
7311 * (EPT on EPT). So any problems with the structure of the
7312 * table is L0's fault.
7313 */
644d711a
NHE		 7314 return 0;
7315 case EXIT_REASON_WBINVD:
7316 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7317 case EXIT_REASON_XSETBV:
7318 return 1;
81dc01f7
WL		 7319 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7320 /*
7321 * This should never happen, since it is not possible to
7322 * set XSS to a non-zero value---neither in L1 nor in L2.
7323 * If if it were, XSS would have to be checked against
7324 * the XSS exit bitmap in vmcs12.
7325 */
7326 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
644d711a
NHE		 7327 default:
7328 return 1;
7329 }
7330}
7331
586f9607
AK		 7332static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7333{
7334 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7335 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7336}
7337
6aa8b732
AK		 7338/*
7339 * The guest has exited. See if we can fix it or if we need userspace
7340 * assistance.
7341 */
851ba692 7342static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7343{
29bd8a78 7344 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7345 u32 exit_reason = vmx->exit_reason;
1155f76a 7346 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7347
80ced186 7348 /* If guest state is invalid, start emulating */
14168786 7349 if (vmx->emulation_required)
80ced186 7350 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7351
644d711a 7352 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7353 nested_vmx_vmexit(vcpu, exit_reason,
7354 vmcs_read32(VM_EXIT_INTR_INFO),
7355 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7356 return 1;
7357 }
7358
5120702e
MG		 7359 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7360 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7361 vcpu->run->fail_entry.hardware_entry_failure_reason
7362 = exit_reason;
7363 return 0;
7364 }
7365
29bd8a78 7366 if (unlikely(vmx->fail)) {
851ba692
AK		 7367 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7368 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7369 = vmcs_read32(VM_INSTRUCTION_ERROR);
7370 return 0;
7371 }
6aa8b732 7372
b9bf6882
XG		 7373 /*
7374 * Note:
7375 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7376 * delivery event since it indicates guest is accessing MMIO.
7377 * The vm-exit can be triggered again after return to guest that
7378 * will cause infinite loop.
7379 */
d77c26fc 7380 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7381 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7382 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7383 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7384 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7385 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7386 vcpu->run->internal.ndata = 2;
7387 vcpu->run->internal.data[0] = vectoring_info;
7388 vcpu->run->internal.data[1] = exit_reason;
7389 return 0;
7390 }
3b86cd99 7391
644d711a
NHE		 7392 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7393 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7394 get_vmcs12(vcpu))))) {
c4282df9 7395 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7396 vmx->soft_vnmi_blocked = 0;
3b86cd99 7397 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7398 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7399 /*
7400 * This CPU don't support us in finding the end of an
7401 * NMI-blocked window if the guest runs with IRQs
7402 * disabled. So we pull the trigger after 1 s of
7403 * futile waiting, but inform the user about this.
7404 */
7405 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7406 "state on VCPU %d after 1 s timeout\n",
7407 __func__, vcpu->vcpu_id);
7408 vmx->soft_vnmi_blocked = 0;
3b86cd99 7409 }
3b86cd99
JK		 7410 }
7411
6aa8b732
AK		 7412 if (exit_reason < kvm_vmx_max_exit_handlers
7413 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7414 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7415 else {
2bc19dc3
MT		 7416 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7417 kvm_queue_exception(vcpu, UD_VECTOR);
7418 return 1;
6aa8b732 7419 }
6aa8b732
AK		 7420}
7421
95ba8273 7422static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7423{
a7c0b07d
WL		 7424 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7425
7426 if (is_guest_mode(vcpu) &&
7427 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7428 return;
7429
95ba8273 7430 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7431 vmcs_write32(TPR_THRESHOLD, 0);
7432 return;
7433 }
7434
95ba8273 7435 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7436}
7437
8d14695f
YZ		 7438static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7439{
7440 u32 sec_exec_control;
7441
7442 /*
7443 * There is not point to enable virtualize x2apic without enable
7444 * apicv
7445 */
c7c9c56c
YZ		 7446 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7447 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7448 return;
7449
7450 if (!vm_need_tpr_shadow(vcpu->kvm))
7451 return;
7452
7453 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7454
7455 if (set) {
7456 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7457 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7458 } else {
7459 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7460 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7461 }
7462 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7463
7464 vmx_set_msr_bitmap(vcpu);
7465}
7466
38b99173
TC		 7467static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7468{
7469 struct vcpu_vmx *vmx = to_vmx(vcpu);
7470
7471 /*
7472 * Currently we do not handle the nested case where L2 has an
7473 * APIC access page of its own; that page is still pinned.
7474 * Hence, we skip the case where the VCPU is in guest mode _and_
7475 * L1 prepared an APIC access page for L2.
7476 *
7477 * For the case where L1 and L2 share the same APIC access page
7478 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7479 * in the vmcs12), this function will only update either the vmcs01
7480 * or the vmcs02. If the former, the vmcs02 will be updated by
7481 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7482 * the next L2->L1 exit.
7483 */
7484 if (!is_guest_mode(vcpu) ||
7485 !nested_cpu_has2(vmx->nested.current_vmcs12,
7486 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7487 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7488}
7489
c7c9c56c
YZ		 7490static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7491{
7492 u16 status;
7493 u8 old;
7494
c7c9c56c
YZ		 7495 if (isr == -1)
7496 isr = 0;
7497
7498 status = vmcs_read16(GUEST_INTR_STATUS);
7499 old = status >> 8;
7500 if (isr != old) {
7501 status &= 0xff;
7502 status |= isr << 8;
7503 vmcs_write16(GUEST_INTR_STATUS, status);
7504 }
7505}
7506
7507static void vmx_set_rvi(int vector)
7508{
7509 u16 status;
7510 u8 old;
7511
4114c27d
WW		 7512 if (vector == -1)
7513 vector = 0;
7514
c7c9c56c
YZ		 7515 status = vmcs_read16(GUEST_INTR_STATUS);
7516 old = (u8)status & 0xff;
7517 if ((u8)vector != old) {
7518 status &= ~0xff;
7519 status |= (u8)vector;
7520 vmcs_write16(GUEST_INTR_STATUS, status);
7521 }
7522}
7523
7524static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7525{
4114c27d
WW		 7526 if (!is_guest_mode(vcpu)) {
7527 vmx_set_rvi(max_irr);
7528 return;
7529 }
7530
c7c9c56c
YZ		 7531 if (max_irr == -1)
7532 return;
7533
963fee16 7534 /*
4114c27d
WW		 7535 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7536 * handles it.
963fee16 7537 */
4114c27d 7538 if (nested_exit_on_intr(vcpu))
963fee16
WL		 7539 return;
7540
963fee16 7541 /*
4114c27d 7542 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 7543 * is run without virtual interrupt delivery.
7544 */
7545 if (!kvm_event_needs_reinjection(vcpu) &&
7546 vmx_interrupt_allowed(vcpu)) {
7547 kvm_queue_interrupt(vcpu, max_irr, false);
7548 vmx_inject_irq(vcpu);
7549 }
c7c9c56c
YZ		 7550}
7551
7552static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7553{
3d81bc7e
YZ		 7554 if (!vmx_vm_has_apicv(vcpu->kvm))
7555 return;
7556
c7c9c56c
YZ		 7557 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7558 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7559 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7560 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7561}
7562
51aa01d1 7563static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7564{
00eba012
AK		 7565 u32 exit_intr_info;
7566
7567 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7568 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7569 return;
7570
c5ca8e57 7571 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7572 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7573
7574 /* Handle machine checks before interrupts are enabled */
00eba012 7575 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7576 kvm_machine_check();
7577
20f65983 7578 /* We need to handle NMIs before interrupts are enabled */
00eba012 7579 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7580 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7581 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7582 asm("int $2");
ff9d07a0
ZY		 7583 kvm_after_handle_nmi(&vmx->vcpu);
7584 }
51aa01d1 7585}
20f65983 7586
a547c6db
YZ		 7587static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7588{
7589 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7590
7591 /*
7592 * If external interrupt exists, IF bit is set in rflags/eflags on the
7593 * interrupt stack frame, and interrupt will be enabled on a return
7594 * from interrupt handler.
7595 */
7596 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7597 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7598 unsigned int vector;
7599 unsigned long entry;
7600 gate_desc *desc;
7601 struct vcpu_vmx *vmx = to_vmx(vcpu);
7602#ifdef CONFIG_X86_64
7603 unsigned long tmp;
7604#endif
7605
7606 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7607 desc = (gate_desc *)vmx->host_idt_base + vector;
7608 entry = gate_offset(*desc);
7609 asm volatile(
7610#ifdef CONFIG_X86_64
7611 "mov %%" _ASM_SP ", %[sp]\n\t"
7612 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7613 "push $%c[ss]\n\t"
7614 "push %[sp]\n\t"
7615#endif
7616 "pushf\n\t"
7617 "orl $0x200, (%%" _ASM_SP ")\n\t"
7618 __ASM_SIZE(push) " $%c[cs]\n\t"
7619 "call *%[entry]\n\t"
7620 :
7621#ifdef CONFIG_X86_64
7622 [sp]"=&r"(tmp)
7623#endif
7624 :
7625 [entry]"r"(entry),
7626 [ss]"i"(__KERNEL_DS),
7627 [cs]"i"(__KERNEL_CS)
7628 );
7629 } else
7630 local_irq_enable();
7631}
7632
da8999d3
LJ		 7633static bool vmx_mpx_supported(void)
7634{
7635 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7636 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7637}
7638
55412b2e
WL		 7639static bool vmx_xsaves_supported(void)
7640{
7641 return vmcs_config.cpu_based_2nd_exec_ctrl &
7642 SECONDARY_EXEC_XSAVES;
7643}
7644
51aa01d1
AK		 7645static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7646{
c5ca8e57 7647 u32 exit_intr_info;
51aa01d1
AK		 7648 bool unblock_nmi;
7649 u8 vector;
7650 bool idtv_info_valid;
7651
7652 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7653
cf393f75 7654 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7655 if (vmx->nmi_known_unmasked)
7656 return;
c5ca8e57
AK		 7657 /*
7658 * Can't use vmx->exit_intr_info since we're not sure what
7659 * the exit reason is.
7660 */
7661 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7662 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7663 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7664 /*
7b4a25cb 7665 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7666 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7667 * a guest IRET fault.
7b4a25cb
GN		 7668 * SDM 3: 23.2.2 (September 2008)
7669 * Bit 12 is undefined in any of the following cases:
7670 * If the VM exit sets the valid bit in the IDT-vectoring
7671 * information field.
7672 * If the VM exit is due to a double fault.
cf393f75 7673 */
7b4a25cb
GN		 7674 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7675 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7676 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7677 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7678 else
7679 vmx->nmi_known_unmasked =
7680 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7681 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7682 } else if (unlikely(vmx->soft_vnmi_blocked))
7683 vmx->vnmi_blocked_time +=
7684 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7685}
7686
3ab66e8a 7687static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7688 u32 idt_vectoring_info,
7689 int instr_len_field,
7690 int error_code_field)
51aa01d1 7691{
51aa01d1
AK		 7692 u8 vector;
7693 int type;
7694 bool idtv_info_valid;
7695
7696 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7697
3ab66e8a
JK		 7698 vcpu->arch.nmi_injected = false;
7699 kvm_clear_exception_queue(vcpu);
7700 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7701
7702 if (!idtv_info_valid)
7703 return;
7704
3ab66e8a 7705 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7706
668f612f
AK		 7707 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7708 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7709
64a7ec06 7710 switch (type) {
37b96e98 7711 case INTR_TYPE_NMI_INTR:
3ab66e8a 7712 vcpu->arch.nmi_injected = true;
668f612f 7713 /*
7b4a25cb 7714 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7715 * Clear bit "block by NMI" before VM entry if a NMI
7716 * delivery faulted.
668f612f 7717 */
3ab66e8a 7718 vmx_set_nmi_mask(vcpu, false);
37b96e98 7719 break;
37b96e98 7720 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7721 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7722 /* fall through */
7723 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7724 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7725 u32 err = vmcs_read32(error_code_field);
851eb667 7726 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7727 } else
851eb667 7728 kvm_requeue_exception(vcpu, vector);
37b96e98 7729 break;
66fd3f7f 7730 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7731 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7732 /* fall through */
37b96e98 7733 case INTR_TYPE_EXT_INTR:
3ab66e8a 7734 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7735 break;
7736 default:
7737 break;
f7d9238f 7738 }
cf393f75
AK		 7739}
7740
83422e17
AK		 7741static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7742{
3ab66e8a 7743 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7744 VM_EXIT_INSTRUCTION_LEN,
7745 IDT_VECTORING_ERROR_CODE);
7746}
7747
b463a6f7
AK		 7748static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7749{
3ab66e8a 7750 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7751 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7752 VM_ENTRY_INSTRUCTION_LEN,
7753 VM_ENTRY_EXCEPTION_ERROR_CODE);
7754
7755 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7756}
7757
d7cd9796
GN		 7758static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7759{
7760 int i, nr_msrs;
7761 struct perf_guest_switch_msr *msrs;
7762
7763 msrs = perf_guest_get_msrs(&nr_msrs);
7764
7765 if (!msrs)
7766 return;
7767
7768 for (i = 0; i < nr_msrs; i++)
7769 if (msrs[i].host == msrs[i].guest)
7770 clear_atomic_switch_msr(vmx, msrs[i].msr);
7771 else
7772 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7773 msrs[i].host);
7774}
7775
a3b5ba49 7776static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7777{
a2fa3e9f 7778 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 7779 unsigned long debugctlmsr, cr4;
104f226b
AK		 7780
7781 /* Record the guest's net vcpu time for enforced NMI injections. */
7782 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7783 vmx->entry_time = ktime_get();
7784
7785 /* Don't enter VMX if guest state is invalid, let the exit handler
7786 start emulation until we arrive back to a valid state */
14168786 7787 if (vmx->emulation_required)
104f226b
AK		 7788 return;
7789
a7653ecd
RK		 7790 if (vmx->ple_window_dirty) {
7791 vmx->ple_window_dirty = false;
7792 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7793 }
7794
012f83cb
AG		 7795 if (vmx->nested.sync_shadow_vmcs) {
7796 copy_vmcs12_to_shadow(vmx);
7797 vmx->nested.sync_shadow_vmcs = false;
7798 }
7799
104f226b
AK		 7800 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7801 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7802 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7803 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7804
d974baa3
AL		 7805 cr4 = read_cr4();
7806 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
7807 vmcs_writel(HOST_CR4, cr4);
7808 vmx->host_state.vmcs_host_cr4 = cr4;
7809 }
7810
104f226b
AK		 7811 /* When single-stepping over STI and MOV SS, we must clear the
7812 * corresponding interruptibility bits in the guest state. Otherwise
7813 * vmentry fails as it then expects bit 14 (BS) in pending debug
7814 * exceptions being set, but that's not correct for the guest debugging
7815 * case. */
7816 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7817 vmx_set_interrupt_shadow(vcpu, 0);
7818
d7cd9796 7819 atomic_switch_perf_msrs(vmx);
2a7921b7 7820 debugctlmsr = get_debugctlmsr();
d7cd9796 7821
d462b819 7822 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7823 asm(
6aa8b732 7824 /* Store host registers */
b188c81f
AK		 7825 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7826 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7827 "push %%" _ASM_CX " \n\t"
7828 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7829 "je 1f \n\t"
b188c81f 7830 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7831 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7832 "1: \n\t"
d3edefc0 7833 /* Reload cr2 if changed */
b188c81f
AK		 7834 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7835 "mov %%cr2, %%" _ASM_DX " \n\t"
7836 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7837 "je 2f \n\t"
b188c81f 7838 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7839 "2: \n\t"
6aa8b732 7840 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7841 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7842 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7843 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7844 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7845 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7846 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7847 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7848 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7849#ifdef CONFIG_X86_64
e08aa78a
AK		 7850 "mov %c[r8](%0), %%r8 \n\t"
7851 "mov %c[r9](%0), %%r9 \n\t"
7852 "mov %c[r10](%0), %%r10 \n\t"
7853 "mov %c[r11](%0), %%r11 \n\t"
7854 "mov %c[r12](%0), %%r12 \n\t"
7855 "mov %c[r13](%0), %%r13 \n\t"
7856 "mov %c[r14](%0), %%r14 \n\t"
7857 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7858#endif
b188c81f 7859 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7860
6aa8b732 7861 /* Enter guest mode */
83287ea4 7862 "jne 1f \n\t"
4ecac3fd 7863 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7864 "jmp 2f \n\t"
7865 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7866 "2: "
6aa8b732 7867 /* Save guest registers, load host registers, keep flags */
b188c81f 7868 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7869 "pop %0 \n\t"
b188c81f
AK		 7870 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7871 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7872 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7873 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7874 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7875 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7876 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7877#ifdef CONFIG_X86_64
e08aa78a
AK		 7878 "mov %%r8, %c[r8](%0) \n\t"
7879 "mov %%r9, %c[r9](%0) \n\t"
7880 "mov %%r10, %c[r10](%0) \n\t"
7881 "mov %%r11, %c[r11](%0) \n\t"
7882 "mov %%r12, %c[r12](%0) \n\t"
7883 "mov %%r13, %c[r13](%0) \n\t"
7884 "mov %%r14, %c[r14](%0) \n\t"
7885 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7886#endif
b188c81f
AK		 7887 "mov %%cr2, %%" _ASM_AX " \n\t"
7888 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7889
b188c81f 7890 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7891 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7892 ".pushsection .rodata \n\t"
7893 ".global vmx_return \n\t"
7894 "vmx_return: " _ASM_PTR " 2b \n\t"
7895 ".popsection"
e08aa78a 7896 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7897 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7898 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7899 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7900 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7901 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7902 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7903 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7904 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7905 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7906 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7907#ifdef CONFIG_X86_64
ad312c7c
ZX		 7908 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7909 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7910 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7911 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7912 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7913 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7914 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7915 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7916#endif
40712fae
AK		 7917 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7918 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7919 : "cc", "memory"
7920#ifdef CONFIG_X86_64
b188c81f 7921 , "rax", "rbx", "rdi", "rsi"
c2036300 7922 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7923#else
7924 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7925#endif
7926 );
6aa8b732 7927
2a7921b7
GN		 7928 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7929 if (debugctlmsr)
7930 update_debugctlmsr(debugctlmsr);
7931
aa67f609
AK		 7932#ifndef CONFIG_X86_64
7933 /*
7934 * The sysexit path does not restore ds/es, so we must set them to
7935 * a reasonable value ourselves.
7936 *
7937 * We can't defer this to vmx_load_host_state() since that function
7938 * may be executed in interrupt context, which saves and restore segments
7939 * around it, nullifying its effect.
7940 */
7941 loadsegment(ds, __USER_DS);
7942 loadsegment(es, __USER_DS);
7943#endif
7944
6de4f3ad 7945 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7946 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7947 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7948 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7949 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7950 vcpu->arch.regs_dirty = 0;
7951
1155f76a
AK		 7952 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7953
d462b819 7954 vmx->loaded_vmcs->launched = 1;
1b6269db 7955
51aa01d1 7956 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7957 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7958
e0b890d3
GN		 7959 /*
7960 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7961 * we did not inject a still-pending event to L1 now because of
7962 * nested_run_pending, we need to re-enable this bit.
7963 */
7964 if (vmx->nested.nested_run_pending)
7965 kvm_make_request(KVM_REQ_EVENT, vcpu);
7966
7967 vmx->nested.nested_run_pending = 0;
7968
51aa01d1
AK		 7969 vmx_complete_atomic_exit(vmx);
7970 vmx_recover_nmi_blocking(vmx);
cf393f75 7971 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7972}
7973
4fa7734c
PB		 7974static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7975{
7976 struct vcpu_vmx *vmx = to_vmx(vcpu);
7977 int cpu;
7978
7979 if (vmx->loaded_vmcs == &vmx->vmcs01)
7980 return;
7981
7982 cpu = get_cpu();
7983 vmx->loaded_vmcs = &vmx->vmcs01;
7984 vmx_vcpu_put(vcpu);
7985 vmx_vcpu_load(vcpu, cpu);
7986 vcpu->cpu = cpu;
7987 put_cpu();
7988}
7989
6aa8b732
AK		 7990static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7991{
fb3f0f51
RR		 7992 struct vcpu_vmx *vmx = to_vmx(vcpu);
7993
cdbecfc3 7994 free_vpid(vmx);
4fa7734c
PB		 7995 leave_guest_mode(vcpu);
7996 vmx_load_vmcs01(vcpu);
26a865f4 7997 free_nested(vmx);
4fa7734c 7998 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7999 kfree(vmx->guest_msrs);
8000 kvm_vcpu_uninit(vcpu);
a4770347 8001 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8002}
8003
fb3f0f51 8004static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8005{
fb3f0f51 8006 int err;
c16f862d 8007 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8008 int cpu;
6aa8b732 8009
a2fa3e9f 8010 if (!vmx)
fb3f0f51
RR		 8011 return ERR_PTR(-ENOMEM);
8012
2384d2b3
SY		 8013 allocate_vpid(vmx);
8014
fb3f0f51
RR		 8015 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8016 if (err)
8017 goto free_vcpu;
965b58a5 8018
a2fa3e9f 8019 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8020 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8021 > PAGE_SIZE);
0123be42 8022
be6d05cf 8023 err = -ENOMEM;
fb3f0f51 8024 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8025 goto uninit_vcpu;
8026 }
965b58a5 8027
d462b819
NHE		 8028 vmx->loaded_vmcs = &vmx->vmcs01;
8029 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8030 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8031 goto free_msrs;
d462b819
NHE		 8032 if (!vmm_exclusive)
8033 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8034 loaded_vmcs_init(vmx->loaded_vmcs);
8035 if (!vmm_exclusive)
8036 kvm_cpu_vmxoff();
a2fa3e9f 8037
15ad7146
AK		 8038 cpu = get_cpu();
8039 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8040 vmx->vcpu.cpu = cpu;
8b9cf98c 8041 err = vmx_vcpu_setup(vmx);
fb3f0f51 8042 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8043 put_cpu();
fb3f0f51
RR		 8044 if (err)
8045 goto free_vmcs;
a63cb560 8046 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 8047 err = alloc_apic_access_page(kvm);
8048 if (err)
5e4a0b3c 8049 goto free_vmcs;
a63cb560 8050 }
fb3f0f51 8051
b927a3ce
SY		 8052 if (enable_ept) {
8053 if (!kvm->arch.ept_identity_map_addr)
8054 kvm->arch.ept_identity_map_addr =
8055 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8056 err = init_rmode_identity_map(kvm);
8057 if (err)
93ea5388 8058 goto free_vmcs;
b927a3ce 8059 }
b7ebfb05 8060
a9d30f33
NHE		 8061 vmx->nested.current_vmptr = -1ull;
8062 vmx->nested.current_vmcs12 = NULL;
8063
fb3f0f51
RR		 8064 return &vmx->vcpu;
8065
8066free_vmcs:
5f3fbc34 8067 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8068free_msrs:
fb3f0f51
RR		 8069 kfree(vmx->guest_msrs);
8070uninit_vcpu:
8071 kvm_vcpu_uninit(&vmx->vcpu);
8072free_vcpu:
cdbecfc3 8073 free_vpid(vmx);
a4770347 8074 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8075 return ERR_PTR(err);
6aa8b732
AK		 8076}
8077
002c7f7c
YS		 8078static void __init vmx_check_processor_compat(void *rtn)
8079{
8080 struct vmcs_config vmcs_conf;
8081
8082 *(int *)rtn = 0;
8083 if (setup_vmcs_config(&vmcs_conf) < 0)
8084 *(int *)rtn = -EIO;
8085 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8086 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8087 smp_processor_id());
8088 *(int *)rtn = -EIO;
8089 }
8090}
8091
67253af5
SY		 8092static int get_ept_level(void)
8093{
8094 return VMX_EPT_DEFAULT_GAW + 1;
8095}
8096
4b12f0de 8097static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8098{
4b12f0de
SY		 8099 u64 ret;
8100
522c68c4
SY		 8101 /* For VT-d and EPT combination
8102 * 1. MMIO: always map as UC
8103 * 2. EPT with VT-d:
8104 * a. VT-d without snooping control feature: can't guarantee the
8105 * result, try to trust guest.
8106 * b. VT-d with snooping control feature: snooping control feature of
8107 * VT-d engine can guarantee the cache correctness. Just set it
8108 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8109 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8110 * consistent with host MTRR
8111 */
4b12f0de
SY		 8112 if (is_mmio)
8113 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 8114 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 8115 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8116 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 8117 else
522c68c4 8118 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 8119 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 8120
8121 return ret;
64d4d521
SY		 8122}
8123
17cc3935 8124static int vmx_get_lpage_level(void)
344f414f 8125{
878403b7
SY		 8126 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8127 return PT_DIRECTORY_LEVEL;
8128 else
8129 /* For shadow and EPT supported 1GB page */
8130 return PT_PDPE_LEVEL;
344f414f
JR		 8131}
8132
0e851880
SY		 8133static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8134{
4e47c7a6
SY		 8135 struct kvm_cpuid_entry2 *best;
8136 struct vcpu_vmx *vmx = to_vmx(vcpu);
8137 u32 exec_control;
8138
8139 vmx->rdtscp_enabled = false;
8140 if (vmx_rdtscp_supported()) {
8141 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8142 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8143 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8144 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8145 vmx->rdtscp_enabled = true;
8146 else {
8147 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8148 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8149 exec_control);
8150 }
8151 }
8152 }
ad756a16 8153
ad756a16
MJ		 8154 /* Exposing INVPCID only when PCID is exposed */
8155 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8156 if (vmx_invpcid_supported() &&
4f977045 8157 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8158 guest_cpuid_has_pcid(vcpu)) {
29282fde 8159 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8160 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8161 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8162 exec_control);
8163 } else {
29282fde
TI		 8164 if (cpu_has_secondary_exec_ctrls()) {
8165 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8166 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8167 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8168 exec_control);
8169 }
ad756a16 8170 if (best)
4f977045 8171 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8172 }
0e851880
SY		 8173}
8174
d4330ef2
JR		 8175static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8176{
7b8050f5
NHE		 8177 if (func == 1 && nested)
8178 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8179}
8180
25d92081
YZ		 8181static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8182 struct x86_exception *fault)
8183{
533558bc
JK		 8184 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8185 u32 exit_reason;
25d92081
YZ		 8186
8187 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8188 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8189 else
533558bc
JK		 8190 exit_reason = EXIT_REASON_EPT_VIOLATION;
8191 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8192 vmcs12->guest_physical_address = fault->address;
8193}
8194
155a97a3
NHE		 8195/* Callbacks for nested_ept_init_mmu_context: */
8196
8197static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8198{
8199 /* return the page table to be shadowed - in our case, EPT12 */
8200 return get_vmcs12(vcpu)->ept_pointer;
8201}
8202
8a3c1a33 8203static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8204{
8a3c1a33 8205 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 8206 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
8207
8208 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8209 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8210 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8211
8212 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8213}
8214
8215static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8216{
8217 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8218}
8219
19d5f10b
EK		 8220static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8221 u16 error_code)
8222{
8223 bool inequality, bit;
8224
8225 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8226 inequality =
8227 (error_code & vmcs12->page_fault_error_code_mask) !=
8228 vmcs12->page_fault_error_code_match;
8229 return inequality ^ bit;
8230}
8231
feaf0c7d
GN		 8232static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8233 struct x86_exception *fault)
8234{
8235 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8236
8237 WARN_ON(!is_guest_mode(vcpu));
8238
19d5f10b 8239 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8240 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8241 vmcs_read32(VM_EXIT_INTR_INFO),
8242 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8243 else
8244 kvm_inject_page_fault(vcpu, fault);
8245}
8246
a2bcba50
WL		 8247static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8248 struct vmcs12 *vmcs12)
8249{
8250 struct vcpu_vmx *vmx = to_vmx(vcpu);
8251
8252 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 8253 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 8254 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 8255 return false;
8256
8257 /*
8258 * Translate L1 physical address to host physical
8259 * address for vmcs02. Keep the page pinned, so this
8260 * physical address remains valid. We keep a reference
8261 * to it so we can release it later.
8262 */
8263 if (vmx->nested.apic_access_page) /* shouldn't happen */
8264 nested_release_page(vmx->nested.apic_access_page);
8265 vmx->nested.apic_access_page =
8266 nested_get_page(vcpu, vmcs12->apic_access_addr);
8267 }
a7c0b07d
WL		 8268
8269 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8270 /* TODO: Also verify bits beyond physical address width are 0 */
8271 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8272 return false;
8273
8274 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8275 nested_release_page(vmx->nested.virtual_apic_page);
8276 vmx->nested.virtual_apic_page =
8277 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8278
8279 /*
8280 * Failing the vm entry is _not_ what the processor does
8281 * but it's basically the only possibility we have.
8282 * We could still enter the guest if CR8 load exits are
8283 * enabled, CR8 store exits are enabled, and virtualize APIC
8284 * access is disabled; in this case the processor would never
8285 * use the TPR shadow and we could simply clear the bit from
8286 * the execution control. But such a configuration is useless,
8287 * so let's keep the code simple.
8288 */
8289 if (!vmx->nested.virtual_apic_page)
8290 return false;
8291 }
8292
a2bcba50
WL		 8293 return true;
8294}
8295
f4124500
JK		 8296static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8297{
8298 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8299 struct vcpu_vmx *vmx = to_vmx(vcpu);
8300
8301 if (vcpu->arch.virtual_tsc_khz == 0)
8302 return;
8303
8304 /* Make sure short timeouts reliably trigger an immediate vmexit.
8305 * hrtimer_start does not guarantee this. */
8306 if (preemption_timeout <= 1) {
8307 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8308 return;
8309 }
8310
8311 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8312 preemption_timeout *= 1000000;
8313 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8314 hrtimer_start(&vmx->nested.preemption_timer,
8315 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8316}
8317
e9ac033e
EK		 8318static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8319 unsigned long count_field,
8320 unsigned long addr_field,
8321 int maxphyaddr)
ff651cb6 8322{
e9ac033e
EK		 8323 u64 count, addr;
8324
8325 if (vmcs12_read_any(vcpu, count_field, &count) ||
8326 vmcs12_read_any(vcpu, addr_field, &addr)) {
8327 WARN_ON(1);
8328 return -EINVAL;
8329 }
8330 if (count == 0)
8331 return 0;
8332 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8333 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8334 pr_warn_ratelimited(
8335 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8336 addr_field, maxphyaddr, count, addr);
8337 return -EINVAL;
8338 }
8339 return 0;
8340}
8341
8342static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8343 struct vmcs12 *vmcs12)
8344{
8345 int maxphyaddr;
8346
8347 if (vmcs12->vm_exit_msr_load_count == 0 &&
8348 vmcs12->vm_exit_msr_store_count == 0 &&
8349 vmcs12->vm_entry_msr_load_count == 0)
8350 return 0; /* Fast path */
8351 maxphyaddr = cpuid_maxphyaddr(vcpu);
8352 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8353 VM_EXIT_MSR_LOAD_ADDR, maxphyaddr) ||
8354 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8355 VM_EXIT_MSR_STORE_ADDR, maxphyaddr) ||
8356 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8357 VM_ENTRY_MSR_LOAD_ADDR, maxphyaddr))
8358 return -EINVAL;
8359 return 0;
8360}
8361
8362static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8363 struct vmx_msr_entry *e)
8364{
8365 /* x2APIC MSR accesses are not allowed */
8366 if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8367 return -EINVAL;
8368 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8369 e->index == MSR_IA32_UCODE_REV)
8370 return -EINVAL;
8371 if (e->reserved != 0)
ff651cb6
WV		 8372 return -EINVAL;
8373 return 0;
8374}
8375
e9ac033e
EK		 8376static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8377 struct vmx_msr_entry *e)
ff651cb6
WV		 8378{
8379 if (e->index == MSR_FS_BASE ||
8380 e->index == MSR_GS_BASE ||
e9ac033e
EK		 8381 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8382 nested_vmx_msr_check_common(vcpu, e))
8383 return -EINVAL;
8384 return 0;
8385}
8386
8387static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8388 struct vmx_msr_entry *e)
8389{
8390 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8391 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 8392 return -EINVAL;
8393 return 0;
8394}
8395
8396/*
8397 * Load guest's/host's msr at nested entry/exit.
8398 * return 0 for success, entry index for failure.
8399 */
8400static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8401{
8402 u32 i;
8403 struct vmx_msr_entry e;
8404 struct msr_data msr;
8405
8406 msr.host_initiated = false;
8407 for (i = 0; i < count; i++) {
e9ac033e
EK		 8408 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8409 &e, sizeof(e))) {
8410 pr_warn_ratelimited(
8411 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8412 __func__, i, gpa + i * sizeof(e));
ff651cb6 8413 goto fail;
e9ac033e
EK		 8414 }
8415 if (nested_vmx_load_msr_check(vcpu, &e)) {
8416 pr_warn_ratelimited(
8417 "%s check failed (%u, 0x%x, 0x%x)\n",
8418 __func__, i, e.index, e.reserved);
8419 goto fail;
8420 }
ff651cb6
WV		 8421 msr.index = e.index;
8422 msr.data = e.value;
e9ac033e
EK		 8423 if (kvm_set_msr(vcpu, &msr)) {
8424 pr_warn_ratelimited(
8425 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8426 __func__, i, e.index, e.value);
ff651cb6 8427 goto fail;
e9ac033e 8428 }
ff651cb6
WV		 8429 }
8430 return 0;
8431fail:
8432 return i + 1;
8433}
8434
8435static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8436{
8437 u32 i;
8438 struct vmx_msr_entry e;
8439
8440 for (i = 0; i < count; i++) {
e9ac033e
EK		 8441 if (kvm_read_guest(vcpu->kvm,
8442 gpa + i * sizeof(e),
8443 &e, 2 * sizeof(u32))) {
8444 pr_warn_ratelimited(
8445 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8446 __func__, i, gpa + i * sizeof(e));
ff651cb6 8447 return -EINVAL;
e9ac033e
EK		 8448 }
8449 if (nested_vmx_store_msr_check(vcpu, &e)) {
8450 pr_warn_ratelimited(
8451 "%s check failed (%u, 0x%x, 0x%x)\n",
8452 __func__, i, e.index, e.reserved);
ff651cb6 8453 return -EINVAL;
e9ac033e
EK		 8454 }
8455 if (kvm_get_msr(vcpu, e.index, &e.value)) {
8456 pr_warn_ratelimited(
8457 "%s cannot read MSR (%u, 0x%x)\n",
8458 __func__, i, e.index);
8459 return -EINVAL;
8460 }
8461 if (kvm_write_guest(vcpu->kvm,
8462 gpa + i * sizeof(e) +
ff651cb6 8463 offsetof(struct vmx_msr_entry, value),
e9ac033e
EK		 8464 &e.value, sizeof(e.value))) {
8465 pr_warn_ratelimited(
8466 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8467 __func__, i, e.index, e.value);
8468 return -EINVAL;
8469 }
ff651cb6
WV		 8470 }
8471 return 0;
8472}
8473
fe3ef05c
NHE		 8474/*
8475 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8476 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 8477 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 8478 * guest in a way that will both be appropriate to L1's requests, and our
8479 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8480 * function also has additional necessary side-effects, like setting various
8481 * vcpu->arch fields.
8482 */
8483static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8484{
8485 struct vcpu_vmx *vmx = to_vmx(vcpu);
8486 u32 exec_control;
8487
8488 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8489 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8490 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8491 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8492 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8493 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8494 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8495 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8496 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8497 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8498 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8499 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8500 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8501 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8502 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8503 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8504 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8505 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8506 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8507 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8508 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8509 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8510 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8511 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8512 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8513 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8514 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8515 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8516 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8517 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8518 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8519 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8520 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8521 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8522 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8523 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8524
2996fca0
JK		 8525 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8526 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8527 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8528 } else {
8529 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8530 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8531 }
fe3ef05c
NHE		 8532 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8533 vmcs12->vm_entry_intr_info_field);
8534 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8535 vmcs12->vm_entry_exception_error_code);
8536 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8537 vmcs12->vm_entry_instruction_len);
8538 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8539 vmcs12->guest_interruptibility_info);
fe3ef05c 8540 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8541 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8542 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8543 vmcs12->guest_pending_dbg_exceptions);
8544 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8545 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8546
81dc01f7
WL		 8547 if (nested_cpu_has_xsaves(vmcs12))
8548 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 8549 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8550
f4124500
JK		 8551 exec_control = vmcs12->pin_based_vm_exec_control;
8552 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8553 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8554 PIN_BASED_POSTED_INTR);
f4124500 8555 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8556
f4124500
JK		 8557 vmx->nested.preemption_timer_expired = false;
8558 if (nested_cpu_has_preemption_timer(vmcs12))
8559 vmx_start_preemption_timer(vcpu);
0238ea91 8560
fe3ef05c
NHE		 8561 /*
8562 * Whether page-faults are trapped is determined by a combination of
8563 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8564 * If enable_ept, L0 doesn't care about page faults and we should
8565 * set all of these to L1's desires. However, if !enable_ept, L0 does
8566 * care about (at least some) page faults, and because it is not easy
8567 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8568 * to exit on each and every L2 page fault. This is done by setting
8569 * MASK=MATCH=0 and (see below) EB.PF=1.
8570 * Note that below we don't need special code to set EB.PF beyond the
8571 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8572 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8573 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8574 *
8575 * A problem with this approach (when !enable_ept) is that L1 may be
8576 * injected with more page faults than it asked for. This could have
8577 * caused problems, but in practice existing hypervisors don't care.
8578 * To fix this, we will need to emulate the PFEC checking (on the L1
8579 * page tables), using walk_addr(), when injecting PFs to L1.
8580 */
8581 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8582 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8583 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8584 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8585
8586 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8587 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8588 if (!vmx->rdtscp_enabled)
8589 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8590 /* Take the following fields only from vmcs12 */
696dfd95
PB		 8591 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8592 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8593 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 8594 if (nested_cpu_has(vmcs12,
8595 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8596 exec_control |= vmcs12->secondary_vm_exec_control;
8597
8598 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 8599 /*
8600 * If translation failed, no matter: This feature asks
8601 * to exit when accessing the given address, and if it
8602 * can never be accessed, this feature won't do
8603 * anything anyway.
8604 */
8605 if (!vmx->nested.apic_access_page)
8606 exec_control &=
8607 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8608 else
8609 vmcs_write64(APIC_ACCESS_ADDR,
8610 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 8611 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8612 exec_control |=
8613 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 8614 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 8615 }
8616
8617 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8618 }
8619
8620
8621 /*
8622 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8623 * Some constant fields are set here by vmx_set_constant_host_state().
8624 * Other fields are different per CPU, and will be set later when
8625 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8626 */
a547c6db 8627 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8628
8629 /*
8630 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8631 * entry, but only if the current (host) sp changed from the value
8632 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8633 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8634 * here we just force the write to happen on entry.
8635 */
8636 vmx->host_rsp = 0;
8637
8638 exec_control = vmx_exec_control(vmx); /* L0's desires */
8639 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8640 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8641 exec_control &= ~CPU_BASED_TPR_SHADOW;
8642 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 8643
8644 if (exec_control & CPU_BASED_TPR_SHADOW) {
8645 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8646 page_to_phys(vmx->nested.virtual_apic_page));
8647 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8648 }
8649
fe3ef05c
NHE		 8650 /*
8651 * Merging of IO and MSR bitmaps not currently supported.
8652 * Rather, exit every time.
8653 */
8654 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8655 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8656 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8657
8658 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8659
8660 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8661 * bitwise-or of what L1 wants to trap for L2, and what we want to
8662 * trap. Note that CR0.TS also needs updating - we do this later.
8663 */
8664 update_exception_bitmap(vcpu);
8665 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8666 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8667
8049d651
NHE		 8668 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8669 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8670 * bits are further modified by vmx_set_efer() below.
8671 */
f4124500 8672 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8673
8674 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8675 * emulated by vmx_set_efer(), below.
8676 */
2961e876 8677 vm_entry_controls_init(vmx,
8049d651
NHE		 8678 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8679 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8680 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8681
44811c02 8682 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8683 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8684 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8685 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8686 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8687
8688
8689 set_cr4_guest_host_mask(vmx);
8690
36be0b9d
PB		 8691 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8692 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8693
27fc51b2
NHE		 8694 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8695 vmcs_write64(TSC_OFFSET,
8696 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8697 else
8698 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8699
8700 if (enable_vpid) {
8701 /*
8702 * Trivially support vpid by letting L2s share their parent
8703 * L1's vpid. TODO: move to a more elaborate solution, giving
8704 * each L2 its own vpid and exposing the vpid feature to L1.
8705 */
8706 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8707 vmx_flush_tlb(vcpu);
8708 }
8709
155a97a3
NHE		 8710 if (nested_cpu_has_ept(vmcs12)) {
8711 kvm_mmu_unload(vcpu);
8712 nested_ept_init_mmu_context(vcpu);
8713 }
8714
fe3ef05c
NHE		 8715 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8716 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8717 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8718 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8719 else
8720 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8721 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8722 vmx_set_efer(vcpu, vcpu->arch.efer);
8723
8724 /*
8725 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8726 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8727 * The CR0_READ_SHADOW is what L2 should have expected to read given
8728 * the specifications by L1; It's not enough to take
8729 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8730 * have more bits than L1 expected.
8731 */
8732 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8733 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8734
8735 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8736 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8737
8738 /* shadow page tables on either EPT or shadow page tables */
8739 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8740 kvm_mmu_reset_context(vcpu);
8741
feaf0c7d
GN		 8742 if (!enable_ept)
8743 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8744
3633cfc3
NHE		 8745 /*
8746 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8747 */
8748 if (enable_ept) {
8749 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8750 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8751 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8752 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8753 }
8754
fe3ef05c
NHE		 8755 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8756 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8757}
8758
cd232ad0
NHE		 8759/*
8760 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8761 * for running an L2 nested guest.
8762 */
8763static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8764{
8765 struct vmcs12 *vmcs12;
8766 struct vcpu_vmx *vmx = to_vmx(vcpu);
8767 int cpu;
8768 struct loaded_vmcs *vmcs02;
384bb783 8769 bool ia32e;
ff651cb6 8770 u32 msr_entry_idx;
cd232ad0
NHE		 8771
8772 if (!nested_vmx_check_permission(vcpu) ||
8773 !nested_vmx_check_vmcs12(vcpu))
8774 return 1;
8775
8776 skip_emulated_instruction(vcpu);
8777 vmcs12 = get_vmcs12(vcpu);
8778
012f83cb
AG		 8779 if (enable_shadow_vmcs)
8780 copy_shadow_to_vmcs12(vmx);
8781
7c177938
NHE		 8782 /*
8783 * The nested entry process starts with enforcing various prerequisites
8784 * on vmcs12 as required by the Intel SDM, and act appropriately when
8785 * they fail: As the SDM explains, some conditions should cause the
8786 * instruction to fail, while others will cause the instruction to seem
8787 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8788 * To speed up the normal (success) code path, we should avoid checking
8789 * for misconfigurations which will anyway be caught by the processor
8790 * when using the merged vmcs02.
8791 */
8792 if (vmcs12->launch_state == launch) {
8793 nested_vmx_failValid(vcpu,
8794 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8795 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8796 return 1;
8797 }
8798
6dfacadd
JK		 8799 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8800 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8801 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8802 return 1;
8803 }
8804
7c177938 8805 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8806 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8807 /*TODO: Also verify bits beyond physical address width are 0*/
8808 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8809 return 1;
8810 }
8811
a2bcba50 8812 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 8813 /*TODO: Also verify bits beyond physical address width are 0*/
8814 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8815 return 1;
8816 }
8817
e9ac033e
EK		 8818 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
8819 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8820 return 1;
8821 }
8822
7c177938 8823 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8824 nested_vmx_true_procbased_ctls_low,
8825 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8826 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8827 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8828 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8829 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8830 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 8831 nested_vmx_true_exit_ctls_low,
8832 nested_vmx_exit_ctls_high) ||
7c177938 8833 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 8834 nested_vmx_true_entry_ctls_low,
8835 nested_vmx_entry_ctls_high))
7c177938
NHE		 8836 {
8837 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8838 return 1;
8839 }
8840
8841 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8842 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8843 nested_vmx_failValid(vcpu,
8844 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8845 return 1;
8846 }
8847
92fbc7b1 8848 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8849 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8850 nested_vmx_entry_failure(vcpu, vmcs12,
8851 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8852 return 1;
8853 }
8854 if (vmcs12->vmcs_link_pointer != -1ull) {
8855 nested_vmx_entry_failure(vcpu, vmcs12,
8856 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8857 return 1;
8858 }
8859
384bb783 8860 /*
cb0c8cda 8861 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8862 * are performed on the field for the IA32_EFER MSR:
8863 * - Bits reserved in the IA32_EFER MSR must be 0.
8864 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8865 * the IA-32e mode guest VM-exit control. It must also be identical
8866 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8867 * CR0.PG) is 1.
8868 */
8869 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8870 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8871 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8872 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8873 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8874 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8875 nested_vmx_entry_failure(vcpu, vmcs12,
8876 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8877 return 1;
8878 }
8879 }
8880
8881 /*
8882 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8883 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8884 * the values of the LMA and LME bits in the field must each be that of
8885 * the host address-space size VM-exit control.
8886 */
8887 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8888 ia32e = (vmcs12->vm_exit_controls &
8889 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8890 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8891 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8892 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8893 nested_vmx_entry_failure(vcpu, vmcs12,
8894 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8895 return 1;
8896 }
8897 }
8898
7c177938
NHE		 8899 /*
8900 * We're finally done with prerequisite checking, and can start with
8901 * the nested entry.
8902 */
8903
cd232ad0
NHE		 8904 vmcs02 = nested_get_current_vmcs02(vmx);
8905 if (!vmcs02)
8906 return -ENOMEM;
8907
8908 enter_guest_mode(vcpu);
8909
8910 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8911
2996fca0
JK		 8912 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8913 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8914
cd232ad0
NHE		 8915 cpu = get_cpu();
8916 vmx->loaded_vmcs = vmcs02;
8917 vmx_vcpu_put(vcpu);
8918 vmx_vcpu_load(vcpu, cpu);
8919 vcpu->cpu = cpu;
8920 put_cpu();
8921
36c3cc42
JK		 8922 vmx_segment_cache_clear(vmx);
8923
cd232ad0
NHE		 8924 prepare_vmcs02(vcpu, vmcs12);
8925
ff651cb6
WV		 8926 msr_entry_idx = nested_vmx_load_msr(vcpu,
8927 vmcs12->vm_entry_msr_load_addr,
8928 vmcs12->vm_entry_msr_load_count);
8929 if (msr_entry_idx) {
8930 leave_guest_mode(vcpu);
8931 vmx_load_vmcs01(vcpu);
8932 nested_vmx_entry_failure(vcpu, vmcs12,
8933 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
8934 return 1;
8935 }
8936
8937 vmcs12->launch_state = 1;
8938
6dfacadd
JK		 8939 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8940 return kvm_emulate_halt(vcpu);
8941
7af40ad3
JK		 8942 vmx->nested.nested_run_pending = 1;
8943
cd232ad0
NHE		 8944 /*
8945 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8946 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8947 * returned as far as L1 is concerned. It will only return (and set
8948 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8949 */
8950 return 1;
8951}
8952
4704d0be
NHE		 8953/*
8954 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8955 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8956 * This function returns the new value we should put in vmcs12.guest_cr0.
8957 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8958 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8959 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8960 * didn't trap the bit, because if L1 did, so would L0).
8961 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8962 * been modified by L2, and L1 knows it. So just leave the old value of
8963 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8964 * isn't relevant, because if L0 traps this bit it can set it to anything.
8965 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8966 * changed these bits, and therefore they need to be updated, but L0
8967 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8968 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8969 */
8970static inline unsigned long
8971vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8972{
8973 return
8974 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8975 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8976 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8977 vcpu->arch.cr0_guest_owned_bits));
8978}
8979
8980static inline unsigned long
8981vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8982{
8983 return
8984 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8985 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8986 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8987 vcpu->arch.cr4_guest_owned_bits));
8988}
8989
5f3d5799
JK		 8990static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8991 struct vmcs12 *vmcs12)
8992{
8993 u32 idt_vectoring;
8994 unsigned int nr;
8995
851eb667 8996 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8997 nr = vcpu->arch.exception.nr;
8998 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8999
9000 if (kvm_exception_is_soft(nr)) {
9001 vmcs12->vm_exit_instruction_len =
9002 vcpu->arch.event_exit_inst_len;
9003 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9004 } else
9005 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9006
9007 if (vcpu->arch.exception.has_error_code) {
9008 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9009 vmcs12->idt_vectoring_error_code =
9010 vcpu->arch.exception.error_code;
9011 }
9012
9013 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9014 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9015 vmcs12->idt_vectoring_info_field =
9016 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9017 } else if (vcpu->arch.interrupt.pending) {
9018 nr = vcpu->arch.interrupt.nr;
9019 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9020
9021 if (vcpu->arch.interrupt.soft) {
9022 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9023 vmcs12->vm_entry_instruction_len =
9024 vcpu->arch.event_exit_inst_len;
9025 } else
9026 idt_vectoring |= INTR_TYPE_EXT_INTR;
9027
9028 vmcs12->idt_vectoring_info_field = idt_vectoring;
9029 }
9030}
9031
b6b8a145
JK		 9032static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9033{
9034 struct vcpu_vmx *vmx = to_vmx(vcpu);
9035
f4124500
JK		 9036 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9037 vmx->nested.preemption_timer_expired) {
9038 if (vmx->nested.nested_run_pending)
9039 return -EBUSY;
9040 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9041 return 0;
9042 }
9043
b6b8a145 9044 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9045 if (vmx->nested.nested_run_pending ||
9046 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9047 return -EBUSY;
9048 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9049 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9050 INTR_INFO_VALID_MASK, 0);
9051 /*
9052 * The NMI-triggered VM exit counts as injection:
9053 * clear this one and block further NMIs.
9054 */
9055 vcpu->arch.nmi_pending = 0;
9056 vmx_set_nmi_mask(vcpu, true);
9057 return 0;
9058 }
9059
9060 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9061 nested_exit_on_intr(vcpu)) {
9062 if (vmx->nested.nested_run_pending)
9063 return -EBUSY;
9064 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
9065 }
9066
9067 return 0;
9068}
9069
f4124500
JK		 9070static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9071{
9072 ktime_t remaining =
9073 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9074 u64 value;
9075
9076 if (ktime_to_ns(remaining) <= 0)
9077 return 0;
9078
9079 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9080 do_div(value, 1000000);
9081 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9082}
9083
4704d0be
NHE		 9084/*
9085 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9086 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9087 * and this function updates it to reflect the changes to the guest state while
9088 * L2 was running (and perhaps made some exits which were handled directly by L0
9089 * without going back to L1), and to reflect the exit reason.
9090 * Note that we do not have to copy here all VMCS fields, just those that
9091 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9092 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9093 * which already writes to vmcs12 directly.
9094 */
533558bc
JK		 9095static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9096 u32 exit_reason, u32 exit_intr_info,
9097 unsigned long exit_qualification)
4704d0be
NHE		 9098{
9099 /* update guest state fields: */
9100 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9101 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9102
4704d0be
NHE		 9103 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9104 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9105 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9106
9107 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9108 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9109 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9110 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9111 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9112 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9113 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9114 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9115 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9116 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9117 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9118 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9119 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9120 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9121 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9122 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9123 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9124 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9125 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9126 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9127 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9128 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9129 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9130 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9131 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9132 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9133 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9134 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9135 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9136 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9137 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9138 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9139 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9140 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9141 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9142 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9143
4704d0be
NHE		 9144 vmcs12->guest_interruptibility_info =
9145 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9146 vmcs12->guest_pending_dbg_exceptions =
9147 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9148 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9149 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9150 else
9151 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9152
f4124500
JK		 9153 if (nested_cpu_has_preemption_timer(vmcs12)) {
9154 if (vmcs12->vm_exit_controls &
9155 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9156 vmcs12->vmx_preemption_timer_value =
9157 vmx_get_preemption_timer_value(vcpu);
9158 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9159 }
7854cbca 9160
3633cfc3
NHE		 9161 /*
9162 * In some cases (usually, nested EPT), L2 is allowed to change its
9163 * own CR3 without exiting. If it has changed it, we must keep it.
9164 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9165 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9166 *
9167 * Additionally, restore L2's PDPTR to vmcs12.
9168 */
9169 if (enable_ept) {
9170 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9171 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9172 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9173 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9174 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9175 }
9176
c18911a2
JK		 9177 vmcs12->vm_entry_controls =
9178 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9179 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9180
2996fca0
JK		 9181 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9182 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9183 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9184 }
9185
4704d0be
NHE		 9186 /* TODO: These cannot have changed unless we have MSR bitmaps and
9187 * the relevant bit asks not to trap the change */
b8c07d55 9188 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9189 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9190 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9191 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 9192 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9193 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9194 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 9195 if (vmx_mpx_supported())
9196 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 9197 if (nested_cpu_has_xsaves(vmcs12))
9198 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 9199
9200 /* update exit information fields: */
9201
533558bc
JK		 9202 vmcs12->vm_exit_reason = exit_reason;
9203 vmcs12->exit_qualification = exit_qualification;
4704d0be 9204
533558bc 9205 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 9206 if ((vmcs12->vm_exit_intr_info &
9207 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9208 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9209 vmcs12->vm_exit_intr_error_code =
9210 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 9211 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 9212 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9213 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9214
5f3d5799
JK		 9215 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9216 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9217 * instead of reading the real value. */
4704d0be 9218 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 9219
9220 /*
9221 * Transfer the event that L0 or L1 may wanted to inject into
9222 * L2 to IDT_VECTORING_INFO_FIELD.
9223 */
9224 vmcs12_save_pending_event(vcpu, vmcs12);
9225 }
9226
9227 /*
9228 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9229 * preserved above and would only end up incorrectly in L1.
9230 */
9231 vcpu->arch.nmi_injected = false;
9232 kvm_clear_exception_queue(vcpu);
9233 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 9234}
9235
9236/*
9237 * A part of what we need to when the nested L2 guest exits and we want to
9238 * run its L1 parent, is to reset L1's guest state to the host state specified
9239 * in vmcs12.
9240 * This function is to be called not only on normal nested exit, but also on
9241 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9242 * Failures During or After Loading Guest State").
9243 * This function should be called when the active VMCS is L1's (vmcs01).
9244 */
733568f9
JK		 9245static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9246 struct vmcs12 *vmcs12)
4704d0be 9247{
21feb4eb
ACL		 9248 struct kvm_segment seg;
9249
4704d0be
NHE		 9250 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9251 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 9252 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 9253 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9254 else
9255 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9256 vmx_set_efer(vcpu, vcpu->arch.efer);
9257
9258 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9259 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 9260 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 9261 /*
9262 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9263 * actually changed, because it depends on the current state of
9264 * fpu_active (which may have changed).
9265 * Note that vmx_set_cr0 refers to efer set above.
9266 */
9e3e4dbf 9267 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 9268 /*
9269 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9270 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9271 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9272 */
9273 update_exception_bitmap(vcpu);
9274 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9275 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9276
9277 /*
9278 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9279 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9280 */
9281 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9282 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9283
29bf08f1 9284 nested_ept_uninit_mmu_context(vcpu);
155a97a3 9285
4704d0be
NHE		 9286 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9287 kvm_mmu_reset_context(vcpu);
9288
feaf0c7d
GN		 9289 if (!enable_ept)
9290 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9291
4704d0be
NHE		 9292 if (enable_vpid) {
9293 /*
9294 * Trivially support vpid by letting L2s share their parent
9295 * L1's vpid. TODO: move to a more elaborate solution, giving
9296 * each L2 its own vpid and exposing the vpid feature to L1.
9297 */
9298 vmx_flush_tlb(vcpu);
9299 }
9300
9301
9302 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9303 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9304 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9305 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9306 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 9307
36be0b9d
PB		 9308 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9309 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9310 vmcs_write64(GUEST_BNDCFGS, 0);
9311
44811c02 9312 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 9313 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 9314 vcpu->arch.pat = vmcs12->host_ia32_pat;
9315 }
4704d0be
NHE		 9316 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9317 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9318 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 9319
21feb4eb
ACL		 9320 /* Set L1 segment info according to Intel SDM
9321 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9322 seg = (struct kvm_segment) {
9323 .base = 0,
9324 .limit = 0xFFFFFFFF,
9325 .selector = vmcs12->host_cs_selector,
9326 .type = 11,
9327 .present = 1,
9328 .s = 1,
9329 .g = 1
9330 };
9331 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9332 seg.l = 1;
9333 else
9334 seg.db = 1;
9335 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9336 seg = (struct kvm_segment) {
9337 .base = 0,
9338 .limit = 0xFFFFFFFF,
9339 .type = 3,
9340 .present = 1,
9341 .s = 1,
9342 .db = 1,
9343 .g = 1
9344 };
9345 seg.selector = vmcs12->host_ds_selector;
9346 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9347 seg.selector = vmcs12->host_es_selector;
9348 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9349 seg.selector = vmcs12->host_ss_selector;
9350 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9351 seg.selector = vmcs12->host_fs_selector;
9352 seg.base = vmcs12->host_fs_base;
9353 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9354 seg.selector = vmcs12->host_gs_selector;
9355 seg.base = vmcs12->host_gs_base;
9356 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9357 seg = (struct kvm_segment) {
205befd9 9358 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 9359 .limit = 0x67,
9360 .selector = vmcs12->host_tr_selector,
9361 .type = 11,
9362 .present = 1
9363 };
9364 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9365
503cd0c5
JK		 9366 kvm_set_dr(vcpu, 7, 0x400);
9367 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6
WV		 9368
9369 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9370 vmcs12->vm_exit_msr_load_count))
9371 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 9372}
9373
9374/*
9375 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9376 * and modify vmcs12 to make it see what it would expect to see there if
9377 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9378 */
533558bc
JK		 9379static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9380 u32 exit_intr_info,
9381 unsigned long exit_qualification)
4704d0be
NHE		 9382{
9383 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 9384 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9385
5f3d5799
JK		 9386 /* trying to cancel vmlaunch/vmresume is a bug */
9387 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9388
4704d0be 9389 leave_guest_mode(vcpu);
533558bc
JK		 9390 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9391 exit_qualification);
4704d0be 9392
ff651cb6
WV		 9393 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
9394 vmcs12->vm_exit_msr_store_count))
9395 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
9396
f3380ca5
WL		 9397 vmx_load_vmcs01(vcpu);
9398
77b0f5d6
BD		 9399 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9400 && nested_exit_intr_ack_set(vcpu)) {
9401 int irq = kvm_cpu_get_interrupt(vcpu);
9402 WARN_ON(irq < 0);
9403 vmcs12->vm_exit_intr_info = irq |
9404 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9405 }
9406
542060ea
JK		 9407 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9408 vmcs12->exit_qualification,
9409 vmcs12->idt_vectoring_info_field,
9410 vmcs12->vm_exit_intr_info,
9411 vmcs12->vm_exit_intr_error_code,
9412 KVM_ISA_VMX);
4704d0be 9413
2961e876
GN		 9414 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
9415 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 9416 vmx_segment_cache_clear(vmx);
9417
4704d0be
NHE		 9418 /* if no vmcs02 cache requested, remove the one we used */
9419 if (VMCS02_POOL_SIZE == 0)
9420 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
9421
9422 load_vmcs12_host_state(vcpu, vmcs12);
9423
27fc51b2 9424 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 9425 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9426
9427 /* This is needed for same reason as it was needed in prepare_vmcs02 */
9428 vmx->host_rsp = 0;
9429
9430 /* Unpin physical memory we referred to in vmcs02 */
9431 if (vmx->nested.apic_access_page) {
9432 nested_release_page(vmx->nested.apic_access_page);
48d89b92 9433 vmx->nested.apic_access_page = NULL;
4704d0be 9434 }
a7c0b07d
WL		 9435 if (vmx->nested.virtual_apic_page) {
9436 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 9437 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 9438 }
4704d0be 9439
38b99173
TC		 9440 /*
9441 * We are now running in L2, mmu_notifier will force to reload the
9442 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9443 */
9444 kvm_vcpu_reload_apic_access_page(vcpu);
9445
4704d0be
NHE		 9446 /*
9447 * Exiting from L2 to L1, we're now back to L1 which thinks it just
9448 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9449 * success or failure flag accordingly.
9450 */
9451 if (unlikely(vmx->fail)) {
9452 vmx->fail = 0;
9453 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
9454 } else
9455 nested_vmx_succeed(vcpu);
012f83cb
AG		 9456 if (enable_shadow_vmcs)
9457 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 9458
9459 /* in case we halted in L2 */
9460 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 9461}
9462
42124925
JK		 9463/*
9464 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9465 */
9466static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9467{
9468 if (is_guest_mode(vcpu))
533558bc 9469 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 9470 free_nested(to_vmx(vcpu));
9471}
9472
7c177938
NHE		 9473/*
9474 * L1's failure to enter L2 is a subset of a normal exit, as explained in
9475 * 23.7 "VM-entry failures during or after loading guest state" (this also
9476 * lists the acceptable exit-reason and exit-qualification parameters).
9477 * It should only be called before L2 actually succeeded to run, and when
9478 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9479 */
9480static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9481 struct vmcs12 *vmcs12,
9482 u32 reason, unsigned long qualification)
9483{
9484 load_vmcs12_host_state(vcpu, vmcs12);
9485 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9486 vmcs12->exit_qualification = qualification;
9487 nested_vmx_succeed(vcpu);
012f83cb
AG		 9488 if (enable_shadow_vmcs)
9489 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 9490}
9491
8a76d7f2
JR		 9492static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9493 struct x86_instruction_info *info,
9494 enum x86_intercept_stage stage)
9495{
9496 return X86EMUL_CONTINUE;
9497}
9498
48d89b92 9499static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 9500{
b4a2d31d
RK		 9501 if (ple_gap)
9502 shrink_ple_window(vcpu);
ae97a3b8
RK		 9503}
9504
cbdd1bea 9505static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 9506 .cpu_has_kvm_support = cpu_has_kvm_support,
9507 .disabled_by_bios = vmx_disabled_by_bios,
9508 .hardware_setup = hardware_setup,
9509 .hardware_unsetup = hardware_unsetup,
002c7f7c 9510 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 9511 .hardware_enable = hardware_enable,
9512 .hardware_disable = hardware_disable,
04547156 9513 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 9514
9515 .vcpu_create = vmx_create_vcpu,
9516 .vcpu_free = vmx_free_vcpu,
04d2cc77 9517 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 9518
04d2cc77 9519 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 9520 .vcpu_load = vmx_vcpu_load,
9521 .vcpu_put = vmx_vcpu_put,
9522
c8639010 9523 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 9524 .get_msr = vmx_get_msr,
9525 .set_msr = vmx_set_msr,
9526 .get_segment_base = vmx_get_segment_base,
9527 .get_segment = vmx_get_segment,
9528 .set_segment = vmx_set_segment,
2e4d2653 9529 .get_cpl = vmx_get_cpl,
6aa8b732 9530 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 9531 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 9532 .decache_cr3 = vmx_decache_cr3,
25c4c276 9533 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 9534 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 9535 .set_cr3 = vmx_set_cr3,
9536 .set_cr4 = vmx_set_cr4,
6aa8b732 9537 .set_efer = vmx_set_efer,
6aa8b732
AK		 9538 .get_idt = vmx_get_idt,
9539 .set_idt = vmx_set_idt,
9540 .get_gdt = vmx_get_gdt,
9541 .set_gdt = vmx_set_gdt,
73aaf249
JK		 9542 .get_dr6 = vmx_get_dr6,
9543 .set_dr6 = vmx_set_dr6,
020df079 9544 .set_dr7 = vmx_set_dr7,
81908bf4 9545 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 9546 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 9547 .get_rflags = vmx_get_rflags,
9548 .set_rflags = vmx_set_rflags,
02daab21 9549 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 9550
9551 .tlb_flush = vmx_flush_tlb,
6aa8b732 9552
6aa8b732 9553 .run = vmx_vcpu_run,
6062d012 9554 .handle_exit = vmx_handle_exit,
6aa8b732 9555 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 9556 .set_interrupt_shadow = vmx_set_interrupt_shadow,
9557 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 9558 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 9559 .set_irq = vmx_inject_irq,
95ba8273 9560 .set_nmi = vmx_inject_nmi,
298101da 9561 .queue_exception = vmx_queue_exception,
b463a6f7 9562 .cancel_injection = vmx_cancel_injection,
78646121 9563 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 9564 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 9565 .get_nmi_mask = vmx_get_nmi_mask,
9566 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 9567 .enable_nmi_window = enable_nmi_window,
9568 .enable_irq_window = enable_irq_window,
9569 .update_cr8_intercept = update_cr8_intercept,
8d14695f 9570 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 9571 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 9572 .vm_has_apicv = vmx_vm_has_apicv,
9573 .load_eoi_exitmap = vmx_load_eoi_exitmap,
9574 .hwapic_irr_update = vmx_hwapic_irr_update,
9575 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 9576 .sync_pir_to_irr = vmx_sync_pir_to_irr,
9577 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7c6a98df 9578 .test_posted_interrupt = vmx_test_pir,
95ba8273 9579
cbc94022 9580 .set_tss_addr = vmx_set_tss_addr,
67253af5 9581 .get_tdp_level = get_ept_level,
4b12f0de 9582 .get_mt_mask = vmx_get_mt_mask,
229456fc 9583
586f9607 9584 .get_exit_info = vmx_get_exit_info,
586f9607 9585
17cc3935 9586 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 9587
9588 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 9589
9590 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 9591 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 9592
9593 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 9594
9595 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 9596
4051b188 9597 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 9598 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 9599 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 9600 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 9601 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 9602 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 9603
9604 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 9605
9606 .check_intercept = vmx_check_intercept,
a547c6db 9607 .handle_external_intr = vmx_handle_external_intr,
da8999d3 9608 .mpx_supported = vmx_mpx_supported,
55412b2e 9609 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 9610
9611 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 9612
9613 .sched_in = vmx_sched_in,
6aa8b732
AK		 9614};
9615
9616static int __init vmx_init(void)
9617{
34a1cd60
TC		 9618 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9619 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9620 if (r)
34a1cd60 9621 return r;
25c5f225 9622
8f536b76
ZY		 9623#ifdef CONFIG_KEXEC
9624 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9625 crash_vmclear_local_loaded_vmcss);
9626#endif
9627
fdef3ad1 9628 return 0;
6aa8b732
AK		 9629}
9630
9631static void __exit vmx_exit(void)
9632{
8f536b76 9633#ifdef CONFIG_KEXEC
3b63a43f 9634 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 9635 synchronize_rcu();
9636#endif
9637
cb498ea2 9638 kvm_exit();
6aa8b732
AK		 9639}
9640
9641module_init(vmx_init)
9642module_exit(vmx_exit)
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