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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
88197e6a | 21 | #include "ioapic.h" |
1d737c8a | 22 | #include "mmu.h" |
7837699f | 23 | #include "i8254.h" |
37817f29 | 24 | #include "tss.h" |
5fdbf976 | 25 | #include "kvm_cache_regs.h" |
2f728d66 | 26 | #include "kvm_emulate.h" |
26eef70c | 27 | #include "x86.h" |
00b27a3e | 28 | #include "cpuid.h" |
474a5bb9 | 29 | #include "pmu.h" |
e83d5887 | 30 | #include "hyperv.h" |
8df14af4 | 31 | #include "lapic.h" |
313a3dc7 | 32 | |
18068523 | 33 | #include <linux/clocksource.h> |
4d5c5d0f | 34 | #include <linux/interrupt.h> |
313a3dc7 CO |
35 | #include <linux/kvm.h> |
36 | #include <linux/fs.h> | |
37 | #include <linux/vmalloc.h> | |
1767e931 PG |
38 | #include <linux/export.h> |
39 | #include <linux/moduleparam.h> | |
0de10343 | 40 | #include <linux/mman.h> |
2bacc55c | 41 | #include <linux/highmem.h> |
19de40a8 | 42 | #include <linux/iommu.h> |
62c476c7 | 43 | #include <linux/intel-iommu.h> |
c8076604 | 44 | #include <linux/cpufreq.h> |
18863bdd | 45 | #include <linux/user-return-notifier.h> |
a983fb23 | 46 | #include <linux/srcu.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
ff9d07a0 | 48 | #include <linux/perf_event.h> |
7bee342a | 49 | #include <linux/uaccess.h> |
af585b92 | 50 | #include <linux/hash.h> |
a1b60c1c | 51 | #include <linux/pci.h> |
16e8d74d MT |
52 | #include <linux/timekeeper_internal.h> |
53 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
54 | #include <linux/kvm_irqfd.h> |
55 | #include <linux/irqbypass.h> | |
3905f9ad | 56 | #include <linux/sched/stat.h> |
0c5f81da | 57 | #include <linux/sched/isolation.h> |
d0ec49d4 | 58 | #include <linux/mem_encrypt.h> |
72c3c0fe | 59 | #include <linux/entry-kvm.h> |
3905f9ad | 60 | |
aec51dc4 | 61 | #include <trace/events/kvm.h> |
2ed152af | 62 | |
24f1e32c | 63 | #include <asm/debugreg.h> |
d825ed0a | 64 | #include <asm/msr.h> |
a5f61300 | 65 | #include <asm/desc.h> |
890ca9ae | 66 | #include <asm/mce.h> |
f89e32e0 | 67 | #include <linux/kernel_stat.h> |
78f7f1e5 | 68 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 69 | #include <asm/pvclock.h> |
217fc9cf | 70 | #include <asm/div64.h> |
efc64404 | 71 | #include <asm/irq_remapping.h> |
b0c39dc6 | 72 | #include <asm/mshyperv.h> |
0092e434 | 73 | #include <asm/hypervisor.h> |
9715092f | 74 | #include <asm/tlbflush.h> |
bf8c55d8 | 75 | #include <asm/intel_pt.h> |
b3dc0695 | 76 | #include <asm/emulate_prefix.h> |
dd2cb348 | 77 | #include <clocksource/hyperv_timer.h> |
043405e1 | 78 | |
d1898b73 DH |
79 | #define CREATE_TRACE_POINTS |
80 | #include "trace.h" | |
81 | ||
313a3dc7 | 82 | #define MAX_IO_MSRS 256 |
890ca9ae | 83 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
84 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
85 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 86 | |
0f65dd70 | 87 | #define emul_to_vcpu(ctxt) \ |
c9b8b07c | 88 | ((struct kvm_vcpu *)(ctxt)->vcpu) |
0f65dd70 | 89 | |
50a37eb4 JR |
90 | /* EFER defaults: |
91 | * - enable syscall per default because its emulated by KVM | |
92 | * - enable LME and LMA per default on 64 bit KVM | |
93 | */ | |
94 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
95 | static |
96 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 97 | #else |
1260edbe | 98 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 99 | #endif |
313a3dc7 | 100 | |
b11306b5 SC |
101 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
102 | ||
c519265f RK |
103 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
104 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 105 | |
cb142eb7 | 106 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 107 | static void process_nmi(struct kvm_vcpu *vcpu); |
1f7becf1 | 108 | static void process_smi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 109 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 110 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
111 | static void store_regs(struct kvm_vcpu *vcpu); |
112 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 113 | |
afaf0b2f | 114 | struct kvm_x86_ops kvm_x86_ops __read_mostly; |
5fdbf976 | 115 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 116 | |
893590c7 | 117 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 118 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 119 | |
fab0aa3b EM |
120 | static bool __read_mostly report_ignored_msrs = true; |
121 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); | |
122 | ||
4c27625b | 123 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
124 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
125 | ||
630994b3 MT |
126 | static bool __read_mostly kvmclock_periodic_sync = true; |
127 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
128 | ||
893590c7 | 129 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 130 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 131 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 132 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
133 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
134 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
135 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
136 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
137 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
138 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
92a1f12d | 139 | |
cc578287 | 140 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 141 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
142 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
143 | ||
c3941d9e SC |
144 | /* |
145 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
146 | * adaptive tuning starting from default advancment of 1000ns. '0' disables | |
147 | * advancement entirely. Any other value is used as-is and disables adaptive | |
148 | * tuning, i.e. allows priveleged userspace to set an exact advancement time. | |
149 | */ | |
150 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 151 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 152 | |
52004014 FW |
153 | static bool __read_mostly vector_hashing = true; |
154 | module_param(vector_hashing, bool, S_IRUGO); | |
155 | ||
c4ae60e4 LA |
156 | bool __read_mostly enable_vmware_backdoor = false; |
157 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
158 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
159 | ||
6c86eedc WL |
160 | static bool __read_mostly force_emulation_prefix = false; |
161 | module_param(force_emulation_prefix, bool, S_IRUGO); | |
162 | ||
0c5f81da WL |
163 | int __read_mostly pi_inject_timer = -1; |
164 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
165 | ||
7e34fbd0 SC |
166 | /* |
167 | * Restoring the host value for MSRs that are only consumed when running in | |
168 | * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU | |
169 | * returns to userspace, i.e. the kernel can run with the guest's value. | |
170 | */ | |
171 | #define KVM_MAX_NR_USER_RETURN_MSRS 16 | |
18863bdd | 172 | |
7e34fbd0 | 173 | struct kvm_user_return_msrs_global { |
18863bdd | 174 | int nr; |
7e34fbd0 | 175 | u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
176 | }; |
177 | ||
7e34fbd0 | 178 | struct kvm_user_return_msrs { |
18863bdd AK |
179 | struct user_return_notifier urn; |
180 | bool registered; | |
7e34fbd0 | 181 | struct kvm_user_return_msr_values { |
2bf78fa7 SY |
182 | u64 host; |
183 | u64 curr; | |
7e34fbd0 | 184 | } values[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
185 | }; |
186 | ||
7e34fbd0 SC |
187 | static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global; |
188 | static struct kvm_user_return_msrs __percpu *user_return_msrs; | |
18863bdd | 189 | |
cfc48181 SC |
190 | #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ |
191 | | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | |
192 | | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | |
193 | | XFEATURE_MASK_PKRU) | |
194 | ||
91661989 SC |
195 | u64 __read_mostly host_efer; |
196 | EXPORT_SYMBOL_GPL(host_efer); | |
197 | ||
b96e6506 | 198 | bool __read_mostly allow_smaller_maxphyaddr = 0; |
3edd6839 MG |
199 | EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); |
200 | ||
86137773 TL |
201 | u64 __read_mostly host_xss; |
202 | EXPORT_SYMBOL_GPL(host_xss); | |
408e9a31 PB |
203 | u64 __read_mostly supported_xss; |
204 | EXPORT_SYMBOL_GPL(supported_xss); | |
139a12cf | 205 | |
417bc304 | 206 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
812756a8 EGE |
207 | VCPU_STAT("pf_fixed", pf_fixed), |
208 | VCPU_STAT("pf_guest", pf_guest), | |
209 | VCPU_STAT("tlb_flush", tlb_flush), | |
210 | VCPU_STAT("invlpg", invlpg), | |
211 | VCPU_STAT("exits", exits), | |
212 | VCPU_STAT("io_exits", io_exits), | |
213 | VCPU_STAT("mmio_exits", mmio_exits), | |
214 | VCPU_STAT("signal_exits", signal_exits), | |
215 | VCPU_STAT("irq_window", irq_window_exits), | |
216 | VCPU_STAT("nmi_window", nmi_window_exits), | |
217 | VCPU_STAT("halt_exits", halt_exits), | |
218 | VCPU_STAT("halt_successful_poll", halt_successful_poll), | |
219 | VCPU_STAT("halt_attempted_poll", halt_attempted_poll), | |
220 | VCPU_STAT("halt_poll_invalid", halt_poll_invalid), | |
221 | VCPU_STAT("halt_wakeup", halt_wakeup), | |
222 | VCPU_STAT("hypercalls", hypercalls), | |
223 | VCPU_STAT("request_irq", request_irq_exits), | |
224 | VCPU_STAT("irq_exits", irq_exits), | |
225 | VCPU_STAT("host_state_reload", host_state_reload), | |
226 | VCPU_STAT("fpu_reload", fpu_reload), | |
227 | VCPU_STAT("insn_emulation", insn_emulation), | |
228 | VCPU_STAT("insn_emulation_fail", insn_emulation_fail), | |
229 | VCPU_STAT("irq_injections", irq_injections), | |
230 | VCPU_STAT("nmi_injections", nmi_injections), | |
231 | VCPU_STAT("req_event", req_event), | |
232 | VCPU_STAT("l1d_flush", l1d_flush), | |
cb953129 DM |
233 | VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns), |
234 | VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns), | |
812756a8 EGE |
235 | VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped), |
236 | VM_STAT("mmu_pte_write", mmu_pte_write), | |
237 | VM_STAT("mmu_pte_updated", mmu_pte_updated), | |
238 | VM_STAT("mmu_pde_zapped", mmu_pde_zapped), | |
239 | VM_STAT("mmu_flooded", mmu_flooded), | |
240 | VM_STAT("mmu_recycled", mmu_recycled), | |
241 | VM_STAT("mmu_cache_miss", mmu_cache_miss), | |
242 | VM_STAT("mmu_unsync", mmu_unsync), | |
243 | VM_STAT("remote_tlb_flush", remote_tlb_flush), | |
244 | VM_STAT("largepages", lpages, .mode = 0444), | |
245 | VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444), | |
246 | VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions), | |
417bc304 HB |
247 | { NULL } |
248 | }; | |
249 | ||
2acf923e | 250 | u64 __read_mostly host_xcr0; |
cfc48181 SC |
251 | u64 __read_mostly supported_xcr0; |
252 | EXPORT_SYMBOL_GPL(supported_xcr0); | |
2acf923e | 253 | |
80fbd280 | 254 | static struct kmem_cache *x86_fpu_cache; |
b666a4b6 | 255 | |
c9b8b07c SC |
256 | static struct kmem_cache *x86_emulator_cache; |
257 | ||
6abe9c13 PX |
258 | /* |
259 | * When called, it means the previous get/set msr reached an invalid msr. | |
cc4cb017 | 260 | * Return true if we want to ignore/silent this failed msr access. |
6abe9c13 | 261 | */ |
cc4cb017 ML |
262 | static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr, |
263 | u64 data, bool write) | |
6abe9c13 PX |
264 | { |
265 | const char *op = write ? "wrmsr" : "rdmsr"; | |
266 | ||
267 | if (ignore_msrs) { | |
268 | if (report_ignored_msrs) | |
d383b314 TI |
269 | kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", |
270 | op, msr, data); | |
6abe9c13 | 271 | /* Mask the error */ |
cc4cb017 | 272 | return true; |
6abe9c13 | 273 | } else { |
d383b314 TI |
274 | kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", |
275 | op, msr, data); | |
cc4cb017 | 276 | return false; |
6abe9c13 PX |
277 | } |
278 | } | |
279 | ||
c9b8b07c SC |
280 | static struct kmem_cache *kvm_alloc_emulator_cache(void) |
281 | { | |
06add254 SC |
282 | unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); |
283 | unsigned int size = sizeof(struct x86_emulate_ctxt); | |
284 | ||
285 | return kmem_cache_create_usercopy("x86_emulator", size, | |
c9b8b07c | 286 | __alignof__(struct x86_emulate_ctxt), |
06add254 SC |
287 | SLAB_ACCOUNT, useroffset, |
288 | size - useroffset, NULL); | |
c9b8b07c SC |
289 | } |
290 | ||
b6785def | 291 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 292 | |
af585b92 GN |
293 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
294 | { | |
295 | int i; | |
dd03bcaa | 296 | for (i = 0; i < ASYNC_PF_PER_VCPU; i++) |
af585b92 GN |
297 | vcpu->arch.apf.gfns[i] = ~0; |
298 | } | |
299 | ||
18863bdd AK |
300 | static void kvm_on_user_return(struct user_return_notifier *urn) |
301 | { | |
302 | unsigned slot; | |
7e34fbd0 SC |
303 | struct kvm_user_return_msrs *msrs |
304 | = container_of(urn, struct kvm_user_return_msrs, urn); | |
305 | struct kvm_user_return_msr_values *values; | |
1650b4eb IA |
306 | unsigned long flags; |
307 | ||
308 | /* | |
309 | * Disabling irqs at this point since the following code could be | |
310 | * interrupted and executed through kvm_arch_hardware_disable() | |
311 | */ | |
312 | local_irq_save(flags); | |
7e34fbd0 SC |
313 | if (msrs->registered) { |
314 | msrs->registered = false; | |
1650b4eb IA |
315 | user_return_notifier_unregister(urn); |
316 | } | |
317 | local_irq_restore(flags); | |
7e34fbd0 SC |
318 | for (slot = 0; slot < user_return_msrs_global.nr; ++slot) { |
319 | values = &msrs->values[slot]; | |
2bf78fa7 | 320 | if (values->host != values->curr) { |
7e34fbd0 | 321 | wrmsrl(user_return_msrs_global.msrs[slot], values->host); |
2bf78fa7 | 322 | values->curr = values->host; |
18863bdd AK |
323 | } |
324 | } | |
18863bdd AK |
325 | } |
326 | ||
7e34fbd0 | 327 | void kvm_define_user_return_msr(unsigned slot, u32 msr) |
2bf78fa7 | 328 | { |
7e34fbd0 SC |
329 | BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS); |
330 | user_return_msrs_global.msrs[slot] = msr; | |
331 | if (slot >= user_return_msrs_global.nr) | |
332 | user_return_msrs_global.nr = slot + 1; | |
18863bdd | 333 | } |
7e34fbd0 | 334 | EXPORT_SYMBOL_GPL(kvm_define_user_return_msr); |
18863bdd | 335 | |
7e34fbd0 | 336 | static void kvm_user_return_msr_cpu_online(void) |
18863bdd | 337 | { |
05c19c2f | 338 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 339 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
05c19c2f SC |
340 | u64 value; |
341 | int i; | |
18863bdd | 342 | |
7e34fbd0 SC |
343 | for (i = 0; i < user_return_msrs_global.nr; ++i) { |
344 | rdmsrl_safe(user_return_msrs_global.msrs[i], &value); | |
345 | msrs->values[i].host = value; | |
346 | msrs->values[i].curr = value; | |
05c19c2f | 347 | } |
18863bdd AK |
348 | } |
349 | ||
7e34fbd0 | 350 | int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 351 | { |
013f6a5d | 352 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 353 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
8b3c3104 | 354 | int err; |
18863bdd | 355 | |
7e34fbd0 SC |
356 | value = (value & mask) | (msrs->values[slot].host & ~mask); |
357 | if (value == msrs->values[slot].curr) | |
8b3c3104 | 358 | return 0; |
7e34fbd0 | 359 | err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value); |
8b3c3104 AH |
360 | if (err) |
361 | return 1; | |
362 | ||
7e34fbd0 SC |
363 | msrs->values[slot].curr = value; |
364 | if (!msrs->registered) { | |
365 | msrs->urn.on_user_return = kvm_on_user_return; | |
366 | user_return_notifier_register(&msrs->urn); | |
367 | msrs->registered = true; | |
18863bdd | 368 | } |
8b3c3104 | 369 | return 0; |
18863bdd | 370 | } |
7e34fbd0 | 371 | EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); |
18863bdd | 372 | |
13a34e06 | 373 | static void drop_user_return_notifiers(void) |
3548bab5 | 374 | { |
013f6a5d | 375 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 376 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
3548bab5 | 377 | |
7e34fbd0 SC |
378 | if (msrs->registered) |
379 | kvm_on_user_return(&msrs->urn); | |
3548bab5 AK |
380 | } |
381 | ||
6866b83e CO |
382 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
383 | { | |
8a5a87d9 | 384 | return vcpu->arch.apic_base; |
6866b83e CO |
385 | } |
386 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
387 | ||
58871649 JM |
388 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
389 | { | |
390 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
391 | } | |
392 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
393 | ||
58cb628d JK |
394 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
395 | { | |
58871649 JM |
396 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
397 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
d6321d49 RK |
398 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | |
399 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); | |
58cb628d | 400 | |
58871649 | 401 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 402 | return 1; |
58871649 JM |
403 | if (!msr_info->host_initiated) { |
404 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
405 | return 1; | |
406 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
407 | return 1; | |
408 | } | |
58cb628d JK |
409 | |
410 | kvm_lapic_set_base(vcpu, msr_info->data); | |
4abaffce | 411 | kvm_recalculate_apic_map(vcpu->kvm); |
58cb628d | 412 | return 0; |
6866b83e CO |
413 | } |
414 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
415 | ||
3ebccdf3 | 416 | asmlinkage __visible noinstr void kvm_spurious_fault(void) |
e3ba45b8 GL |
417 | { |
418 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 419 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
420 | } |
421 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
422 | ||
3fd28fce ED |
423 | #define EXCPT_BENIGN 0 |
424 | #define EXCPT_CONTRIBUTORY 1 | |
425 | #define EXCPT_PF 2 | |
426 | ||
427 | static int exception_class(int vector) | |
428 | { | |
429 | switch (vector) { | |
430 | case PF_VECTOR: | |
431 | return EXCPT_PF; | |
432 | case DE_VECTOR: | |
433 | case TS_VECTOR: | |
434 | case NP_VECTOR: | |
435 | case SS_VECTOR: | |
436 | case GP_VECTOR: | |
437 | return EXCPT_CONTRIBUTORY; | |
438 | default: | |
439 | break; | |
440 | } | |
441 | return EXCPT_BENIGN; | |
442 | } | |
443 | ||
d6e8c854 NA |
444 | #define EXCPT_FAULT 0 |
445 | #define EXCPT_TRAP 1 | |
446 | #define EXCPT_ABORT 2 | |
447 | #define EXCPT_INTERRUPT 3 | |
448 | ||
449 | static int exception_type(int vector) | |
450 | { | |
451 | unsigned int mask; | |
452 | ||
453 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
454 | return EXCPT_INTERRUPT; | |
455 | ||
456 | mask = 1 << vector; | |
457 | ||
458 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
459 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
460 | return EXCPT_TRAP; | |
461 | ||
462 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
463 | return EXCPT_ABORT; | |
464 | ||
465 | /* Reserved exceptions will result in fault */ | |
466 | return EXCPT_FAULT; | |
467 | } | |
468 | ||
da998b46 JM |
469 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
470 | { | |
471 | unsigned nr = vcpu->arch.exception.nr; | |
472 | bool has_payload = vcpu->arch.exception.has_payload; | |
473 | unsigned long payload = vcpu->arch.exception.payload; | |
474 | ||
475 | if (!has_payload) | |
476 | return; | |
477 | ||
478 | switch (nr) { | |
f10c729f JM |
479 | case DB_VECTOR: |
480 | /* | |
481 | * "Certain debug exceptions may clear bit 0-3. The | |
482 | * remaining contents of the DR6 register are never | |
483 | * cleared by the processor". | |
484 | */ | |
485 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
486 | /* | |
487 | * DR6.RTM is set by all #DB exceptions that don't clear it. | |
488 | */ | |
489 | vcpu->arch.dr6 |= DR6_RTM; | |
490 | vcpu->arch.dr6 |= payload; | |
491 | /* | |
492 | * Bit 16 should be set in the payload whenever the #DB | |
493 | * exception should clear DR6.RTM. This makes the payload | |
494 | * compatible with the pending debug exceptions under VMX. | |
495 | * Though not currently documented in the SDM, this also | |
496 | * makes the payload compatible with the exit qualification | |
497 | * for #DB exceptions under VMX. | |
498 | */ | |
499 | vcpu->arch.dr6 ^= payload & DR6_RTM; | |
307f1cfa OU |
500 | |
501 | /* | |
502 | * The #DB payload is defined as compatible with the 'pending | |
503 | * debug exceptions' field under VMX, not DR6. While bit 12 is | |
504 | * defined in the 'pending debug exceptions' field (enabled | |
505 | * breakpoint), it is reserved and must be zero in DR6. | |
506 | */ | |
507 | vcpu->arch.dr6 &= ~BIT(12); | |
f10c729f | 508 | break; |
da998b46 JM |
509 | case PF_VECTOR: |
510 | vcpu->arch.cr2 = payload; | |
511 | break; | |
512 | } | |
513 | ||
514 | vcpu->arch.exception.has_payload = false; | |
515 | vcpu->arch.exception.payload = 0; | |
516 | } | |
517 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
518 | ||
3fd28fce | 519 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 520 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 521 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
522 | { |
523 | u32 prev_nr; | |
524 | int class1, class2; | |
525 | ||
3842d135 AK |
526 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
527 | ||
664f8e26 | 528 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 529 | queue: |
3ffb2468 NA |
530 | if (has_error && !is_protmode(vcpu)) |
531 | has_error = false; | |
664f8e26 WL |
532 | if (reinject) { |
533 | /* | |
534 | * On vmentry, vcpu->arch.exception.pending is only | |
535 | * true if an event injection was blocked by | |
536 | * nested_run_pending. In that case, however, | |
537 | * vcpu_enter_guest requests an immediate exit, | |
538 | * and the guest shouldn't proceed far enough to | |
539 | * need reinjection. | |
540 | */ | |
541 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
542 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
543 | if (WARN_ON_ONCE(has_payload)) { |
544 | /* | |
545 | * A reinjected event has already | |
546 | * delivered its payload. | |
547 | */ | |
548 | has_payload = false; | |
549 | payload = 0; | |
550 | } | |
664f8e26 WL |
551 | } else { |
552 | vcpu->arch.exception.pending = true; | |
553 | vcpu->arch.exception.injected = false; | |
554 | } | |
3fd28fce ED |
555 | vcpu->arch.exception.has_error_code = has_error; |
556 | vcpu->arch.exception.nr = nr; | |
557 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
558 | vcpu->arch.exception.has_payload = has_payload; |
559 | vcpu->arch.exception.payload = payload; | |
a06230b6 | 560 | if (!is_guest_mode(vcpu)) |
da998b46 | 561 | kvm_deliver_exception_payload(vcpu); |
3fd28fce ED |
562 | return; |
563 | } | |
564 | ||
565 | /* to check exception */ | |
566 | prev_nr = vcpu->arch.exception.nr; | |
567 | if (prev_nr == DF_VECTOR) { | |
568 | /* triple fault -> shutdown */ | |
a8eeb04a | 569 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
570 | return; |
571 | } | |
572 | class1 = exception_class(prev_nr); | |
573 | class2 = exception_class(nr); | |
574 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
575 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
576 | /* |
577 | * Generate double fault per SDM Table 5-5. Set | |
578 | * exception.pending = true so that the double fault | |
579 | * can trigger a nested vmexit. | |
580 | */ | |
3fd28fce | 581 | vcpu->arch.exception.pending = true; |
664f8e26 | 582 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
583 | vcpu->arch.exception.has_error_code = true; |
584 | vcpu->arch.exception.nr = DF_VECTOR; | |
585 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
586 | vcpu->arch.exception.has_payload = false; |
587 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
588 | } else |
589 | /* replace previous exception with a new one in a hope | |
590 | that instruction re-execution will regenerate lost | |
591 | exception */ | |
592 | goto queue; | |
593 | } | |
594 | ||
298101da AK |
595 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
596 | { | |
91e86d22 | 597 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
598 | } |
599 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
600 | ||
ce7ddec4 JR |
601 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
602 | { | |
91e86d22 | 603 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
604 | } |
605 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
606 | ||
4d5523cf PB |
607 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
608 | unsigned long payload) | |
f10c729f JM |
609 | { |
610 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
611 | } | |
4d5523cf | 612 | EXPORT_SYMBOL_GPL(kvm_queue_exception_p); |
f10c729f | 613 | |
da998b46 JM |
614 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
615 | u32 error_code, unsigned long payload) | |
616 | { | |
617 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
618 | true, payload, false); | |
619 | } | |
620 | ||
6affcbed | 621 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 622 | { |
db8fcefa AP |
623 | if (err) |
624 | kvm_inject_gp(vcpu, 0); | |
625 | else | |
6affcbed KH |
626 | return kvm_skip_emulated_instruction(vcpu); |
627 | ||
628 | return 1; | |
db8fcefa AP |
629 | } |
630 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 631 | |
6389ee94 | 632 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
633 | { |
634 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
635 | vcpu->arch.exception.nested_apf = |
636 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 637 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 638 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
639 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
640 | } else { | |
641 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
642 | fault->address); | |
643 | } | |
c3c91fee | 644 | } |
27d6c865 | 645 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 646 | |
53b3d8e9 SC |
647 | bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
648 | struct x86_exception *fault) | |
d4f8cf66 | 649 | { |
0cd665bd | 650 | struct kvm_mmu *fault_mmu; |
53b3d8e9 SC |
651 | WARN_ON_ONCE(fault->vector != PF_VECTOR); |
652 | ||
0cd665bd PB |
653 | fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : |
654 | vcpu->arch.walk_mmu; | |
ef54bcfe | 655 | |
ee1fa209 JS |
656 | /* |
657 | * Invalidate the TLB entry for the faulting address, if it exists, | |
658 | * else the access will fault indefinitely (and to emulate hardware). | |
659 | */ | |
660 | if ((fault->error_code & PFERR_PRESENT_MASK) && | |
661 | !(fault->error_code & PFERR_RSVD_MASK)) | |
662 | kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, | |
663 | fault_mmu->root_hpa); | |
664 | ||
665 | fault_mmu->inject_page_fault(vcpu, fault); | |
ef54bcfe | 666 | return fault->nested_page_fault; |
d4f8cf66 | 667 | } |
53b3d8e9 | 668 | EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); |
d4f8cf66 | 669 | |
3419ffc8 SY |
670 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
671 | { | |
7460fb4a AK |
672 | atomic_inc(&vcpu->arch.nmi_queued); |
673 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
674 | } |
675 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
676 | ||
298101da AK |
677 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
678 | { | |
91e86d22 | 679 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
680 | } |
681 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
682 | ||
ce7ddec4 JR |
683 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
684 | { | |
91e86d22 | 685 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
686 | } |
687 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
688 | ||
0a79b009 AK |
689 | /* |
690 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
691 | * a #GP and return false. | |
692 | */ | |
693 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 694 | { |
afaf0b2f | 695 | if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl) |
0a79b009 AK |
696 | return true; |
697 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
698 | return false; | |
298101da | 699 | } |
0a79b009 | 700 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 701 | |
16f8a6f9 NA |
702 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
703 | { | |
704 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
705 | return true; | |
706 | ||
707 | kvm_queue_exception(vcpu, UD_VECTOR); | |
708 | return false; | |
709 | } | |
710 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
711 | ||
ec92fe44 JR |
712 | /* |
713 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 714 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
715 | * can read from guest physical or from the guest's guest physical memory. |
716 | */ | |
717 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
718 | gfn_t ngfn, void *data, int offset, int len, | |
719 | u32 access) | |
720 | { | |
54987b7a | 721 | struct x86_exception exception; |
ec92fe44 JR |
722 | gfn_t real_gfn; |
723 | gpa_t ngpa; | |
724 | ||
725 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 726 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
727 | if (real_gfn == UNMAPPED_GVA) |
728 | return -EFAULT; | |
729 | ||
730 | real_gfn = gpa_to_gfn(real_gfn); | |
731 | ||
54bf36aa | 732 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
733 | } |
734 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
735 | ||
69b0049a | 736 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
737 | void *data, int offset, int len, u32 access) |
738 | { | |
739 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
740 | data, offset, len, access); | |
741 | } | |
742 | ||
16cfacc8 SC |
743 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
744 | { | |
745 | return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) | | |
746 | rsvd_bits(1, 2); | |
747 | } | |
748 | ||
a03490ed | 749 | /* |
16cfacc8 | 750 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 751 | */ |
ff03a073 | 752 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
753 | { |
754 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
755 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
756 | int i; | |
757 | int ret; | |
ff03a073 | 758 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 759 | |
ff03a073 JR |
760 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
761 | offset * sizeof(u64), sizeof(pdpte), | |
762 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
763 | if (ret < 0) { |
764 | ret = 0; | |
765 | goto out; | |
766 | } | |
767 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
812f30b2 | 768 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 769 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
a03490ed CO |
770 | ret = 0; |
771 | goto out; | |
772 | } | |
773 | } | |
774 | ret = 1; | |
775 | ||
ff03a073 | 776 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
cb3c1e2f SC |
777 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); |
778 | ||
a03490ed | 779 | out: |
a03490ed CO |
780 | |
781 | return ret; | |
782 | } | |
cc4b6871 | 783 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 784 | |
9ed38ffa | 785 | bool pdptrs_changed(struct kvm_vcpu *vcpu) |
d835dfec | 786 | { |
ff03a073 | 787 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
3d06b8bf JR |
788 | int offset; |
789 | gfn_t gfn; | |
d835dfec AK |
790 | int r; |
791 | ||
bf03d4f9 | 792 | if (!is_pae_paging(vcpu)) |
d835dfec AK |
793 | return false; |
794 | ||
cb3c1e2f | 795 | if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) |
6de4f3ad AK |
796 | return true; |
797 | ||
a512177e PB |
798 | gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; |
799 | offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
800 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
801 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec | 802 | if (r < 0) |
7f7f0d9c | 803 | return true; |
d835dfec | 804 | |
7f7f0d9c | 805 | return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 806 | } |
9ed38ffa | 807 | EXPORT_SYMBOL_GPL(pdptrs_changed); |
d835dfec | 808 | |
f27ad38a TL |
809 | void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) |
810 | { | |
811 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; | |
812 | ||
813 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { | |
814 | kvm_clear_async_pf_completion_queue(vcpu); | |
815 | kvm_async_pf_hash_reset(vcpu); | |
816 | } | |
817 | ||
818 | if ((cr0 ^ old_cr0) & update_bits) | |
819 | kvm_mmu_reset_context(vcpu); | |
820 | ||
821 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && | |
822 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
823 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
824 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); | |
825 | } | |
826 | EXPORT_SYMBOL_GPL(kvm_post_set_cr0); | |
827 | ||
49a9b07e | 828 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 829 | { |
aad82703 | 830 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d42e3fae | 831 | unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; |
aad82703 | 832 | |
f9a48e6a AK |
833 | cr0 |= X86_CR0_ET; |
834 | ||
ab344828 | 835 | #ifdef CONFIG_X86_64 |
0f12244f GN |
836 | if (cr0 & 0xffffffff00000000UL) |
837 | return 1; | |
ab344828 GN |
838 | #endif |
839 | ||
840 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 841 | |
0f12244f GN |
842 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
843 | return 1; | |
a03490ed | 844 | |
0f12244f GN |
845 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
846 | return 1; | |
a03490ed | 847 | |
a03490ed | 848 | #ifdef CONFIG_X86_64 |
05487215 SC |
849 | if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && |
850 | (cr0 & X86_CR0_PG)) { | |
851 | int cs_db, cs_l; | |
852 | ||
853 | if (!is_pae(vcpu)) | |
854 | return 1; | |
855 | kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
856 | if (cs_l) | |
0f12244f | 857 | return 1; |
a03490ed | 858 | } |
05487215 SC |
859 | #endif |
860 | if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && | |
861 | is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && | |
862 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) | |
863 | return 1; | |
a03490ed | 864 | |
ad756a16 MJ |
865 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
866 | return 1; | |
867 | ||
afaf0b2f | 868 | kvm_x86_ops.set_cr0(vcpu, cr0); |
a03490ed | 869 | |
f27ad38a | 870 | kvm_post_set_cr0(vcpu, old_cr0, cr0); |
b18d5431 | 871 | |
0f12244f GN |
872 | return 0; |
873 | } | |
2d3ad1f4 | 874 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 875 | |
2d3ad1f4 | 876 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 877 | { |
49a9b07e | 878 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 879 | } |
2d3ad1f4 | 880 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 881 | |
139a12cf | 882 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 883 | { |
16809ecd TL |
884 | if (vcpu->arch.guest_state_protected) |
885 | return; | |
886 | ||
139a12cf AL |
887 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
888 | ||
889 | if (vcpu->arch.xcr0 != host_xcr0) | |
890 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
891 | ||
892 | if (vcpu->arch.xsaves_enabled && | |
893 | vcpu->arch.ia32_xss != host_xss) | |
894 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
895 | } | |
37486135 BM |
896 | |
897 | if (static_cpu_has(X86_FEATURE_PKU) && | |
898 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
899 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && | |
900 | vcpu->arch.pkru != vcpu->arch.host_pkru) | |
901 | __write_pkru(vcpu->arch.pkru); | |
42bdf991 | 902 | } |
139a12cf | 903 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 904 | |
139a12cf | 905 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 906 | { |
16809ecd TL |
907 | if (vcpu->arch.guest_state_protected) |
908 | return; | |
909 | ||
37486135 BM |
910 | if (static_cpu_has(X86_FEATURE_PKU) && |
911 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
912 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { | |
913 | vcpu->arch.pkru = rdpkru(); | |
914 | if (vcpu->arch.pkru != vcpu->arch.host_pkru) | |
915 | __write_pkru(vcpu->arch.host_pkru); | |
916 | } | |
917 | ||
139a12cf AL |
918 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
919 | ||
920 | if (vcpu->arch.xcr0 != host_xcr0) | |
921 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
922 | ||
923 | if (vcpu->arch.xsaves_enabled && | |
924 | vcpu->arch.ia32_xss != host_xss) | |
925 | wrmsrl(MSR_IA32_XSS, host_xss); | |
926 | } | |
927 | ||
42bdf991 | 928 | } |
139a12cf | 929 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 930 | |
69b0049a | 931 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 932 | { |
56c103ec LJ |
933 | u64 xcr0 = xcr; |
934 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 935 | u64 valid_bits; |
2acf923e DC |
936 | |
937 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
938 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
939 | return 1; | |
d91cab78 | 940 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 941 | return 1; |
d91cab78 | 942 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 943 | return 1; |
46c34cb0 PB |
944 | |
945 | /* | |
946 | * Do not allow the guest to set bits that we do not support | |
947 | * saving. However, xcr0 bit 0 is always set, even if the | |
948 | * emulated CPU does not support XSAVE (see fx_init). | |
949 | */ | |
d91cab78 | 950 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 951 | if (xcr0 & ~valid_bits) |
2acf923e | 952 | return 1; |
46c34cb0 | 953 | |
d91cab78 DH |
954 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
955 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
956 | return 1; |
957 | ||
d91cab78 DH |
958 | if (xcr0 & XFEATURE_MASK_AVX512) { |
959 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 960 | return 1; |
d91cab78 | 961 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
962 | return 1; |
963 | } | |
2acf923e | 964 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 965 | |
d91cab78 | 966 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
aedbaf4f | 967 | kvm_update_cpuid_runtime(vcpu); |
2acf923e DC |
968 | return 0; |
969 | } | |
970 | ||
971 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
972 | { | |
afaf0b2f | 973 | if (kvm_x86_ops.get_cpl(vcpu) != 0 || |
764bcbc5 | 974 | __kvm_set_xcr(vcpu, index, xcr)) { |
2acf923e DC |
975 | kvm_inject_gp(vcpu, 0); |
976 | return 1; | |
977 | } | |
978 | return 0; | |
979 | } | |
980 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
981 | ||
ee69c92b | 982 | bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 983 | { |
b11306b5 | 984 | if (cr4 & cr4_reserved_bits) |
ee69c92b | 985 | return false; |
b9baba86 | 986 | |
b899c132 | 987 | if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) |
ee69c92b | 988 | return false; |
3ca94192 | 989 | |
ee69c92b | 990 | return kvm_x86_ops.is_valid_cr4(vcpu, cr4); |
3ca94192 | 991 | } |
ee69c92b | 992 | EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); |
3ca94192 | 993 | |
5b51cb13 TL |
994 | void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) |
995 | { | |
996 | unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
997 | X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; | |
998 | ||
999 | if (((cr4 ^ old_cr4) & mmu_role_bits) || | |
1000 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
1001 | kvm_mmu_reset_context(vcpu); | |
3ca94192 | 1002 | } |
5b51cb13 | 1003 | EXPORT_SYMBOL_GPL(kvm_post_set_cr4); |
3ca94192 WL |
1004 | |
1005 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1006 | { | |
1007 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
1008 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
cb957adb | 1009 | X86_CR4_SMEP; |
3ca94192 | 1010 | |
ee69c92b | 1011 | if (!kvm_is_valid_cr4(vcpu, cr4)) |
ae3e61e1 PB |
1012 | return 1; |
1013 | ||
a03490ed | 1014 | if (is_long_mode(vcpu)) { |
0f12244f GN |
1015 | if (!(cr4 & X86_CR4_PAE)) |
1016 | return 1; | |
d74fcfc1 SC |
1017 | if ((cr4 ^ old_cr4) & X86_CR4_LA57) |
1018 | return 1; | |
a2edf57f AK |
1019 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
1020 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
1021 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
1022 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
1023 | return 1; |
1024 | ||
ad756a16 | 1025 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 1026 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
1027 | return 1; |
1028 | ||
1029 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
1030 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
1031 | return 1; | |
1032 | } | |
1033 | ||
c2fe3cd4 | 1034 | kvm_x86_ops.set_cr4(vcpu, cr4); |
a03490ed | 1035 | |
5b51cb13 | 1036 | kvm_post_set_cr4(vcpu, old_cr4, cr4); |
2acf923e | 1037 | |
0f12244f GN |
1038 | return 0; |
1039 | } | |
2d3ad1f4 | 1040 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 1041 | |
2390218b | 1042 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 1043 | { |
ade61e28 | 1044 | bool skip_tlb_flush = false; |
ac146235 | 1045 | #ifdef CONFIG_X86_64 |
c19986fe JS |
1046 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
1047 | ||
ade61e28 | 1048 | if (pcid_enabled) { |
208320ba JS |
1049 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
1050 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
ade61e28 | 1051 | } |
ac146235 | 1052 | #endif |
9d88fca7 | 1053 | |
9f8fe504 | 1054 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
956bf353 JS |
1055 | if (!skip_tlb_flush) { |
1056 | kvm_mmu_sync_roots(vcpu); | |
eeeb4f67 | 1057 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
956bf353 | 1058 | } |
0f12244f | 1059 | return 0; |
d835dfec AK |
1060 | } |
1061 | ||
d1cd3ce9 | 1062 | if (is_long_mode(vcpu) && |
0107973a | 1063 | (cr3 & vcpu->arch.cr3_lm_rsvd_bits)) |
d1cd3ce9 | 1064 | return 1; |
bf03d4f9 PB |
1065 | else if (is_pae_paging(vcpu) && |
1066 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 1067 | return 1; |
a03490ed | 1068 | |
be01e8e2 | 1069 | kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush); |
0f12244f | 1070 | vcpu->arch.cr3 = cr3; |
cb3c1e2f | 1071 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
7c390d35 | 1072 | |
0f12244f GN |
1073 | return 0; |
1074 | } | |
2d3ad1f4 | 1075 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1076 | |
eea1cff9 | 1077 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1078 | { |
0f12244f GN |
1079 | if (cr8 & CR8_RESERVED_BITS) |
1080 | return 1; | |
35754c98 | 1081 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1082 | kvm_lapic_set_tpr(vcpu, cr8); |
1083 | else | |
ad312c7c | 1084 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1085 | return 0; |
1086 | } | |
2d3ad1f4 | 1087 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1088 | |
2d3ad1f4 | 1089 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1090 | { |
35754c98 | 1091 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1092 | return kvm_lapic_get_cr8(vcpu); |
1093 | else | |
ad312c7c | 1094 | return vcpu->arch.cr8; |
a03490ed | 1095 | } |
2d3ad1f4 | 1096 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1097 | |
ae561ede NA |
1098 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1099 | { | |
1100 | int i; | |
1101 | ||
1102 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1103 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1104 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
1105 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
1106 | } | |
1107 | } | |
1108 | ||
7c86663b | 1109 | void kvm_update_dr7(struct kvm_vcpu *vcpu) |
c8639010 JK |
1110 | { |
1111 | unsigned long dr7; | |
1112 | ||
1113 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1114 | dr7 = vcpu->arch.guest_debug_dr7; | |
1115 | else | |
1116 | dr7 = vcpu->arch.dr7; | |
afaf0b2f | 1117 | kvm_x86_ops.set_dr7(vcpu, dr7); |
360b948d PB |
1118 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1119 | if (dr7 & DR7_BP_EN_MASK) | |
1120 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 | 1121 | } |
7c86663b | 1122 | EXPORT_SYMBOL_GPL(kvm_update_dr7); |
c8639010 | 1123 | |
6f43ed01 NA |
1124 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1125 | { | |
1126 | u64 fixed = DR6_FIXED_1; | |
1127 | ||
d6321d49 | 1128 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 NA |
1129 | fixed |= DR6_RTM; |
1130 | return fixed; | |
1131 | } | |
1132 | ||
338dbc97 | 1133 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1134 | { |
ea740059 MP |
1135 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1136 | ||
020df079 GN |
1137 | switch (dr) { |
1138 | case 0 ... 3: | |
ea740059 | 1139 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1140 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1141 | vcpu->arch.eff_db[dr] = val; | |
1142 | break; | |
1143 | case 4: | |
020df079 | 1144 | case 6: |
f5f6145e | 1145 | if (!kvm_dr6_valid(val)) |
338dbc97 | 1146 | return -1; /* #GP */ |
6f43ed01 | 1147 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
020df079 GN |
1148 | break; |
1149 | case 5: | |
020df079 | 1150 | default: /* 7 */ |
b91991bf | 1151 | if (!kvm_dr7_valid(val)) |
338dbc97 | 1152 | return -1; /* #GP */ |
020df079 | 1153 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1154 | kvm_update_dr7(vcpu); |
020df079 GN |
1155 | break; |
1156 | } | |
1157 | ||
1158 | return 0; | |
1159 | } | |
338dbc97 GN |
1160 | |
1161 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
1162 | { | |
16f8a6f9 | 1163 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 1164 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
1165 | return 1; |
1166 | } | |
1167 | return 0; | |
338dbc97 | 1168 | } |
020df079 GN |
1169 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
1170 | ||
16f8a6f9 | 1171 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1172 | { |
ea740059 MP |
1173 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1174 | ||
020df079 GN |
1175 | switch (dr) { |
1176 | case 0 ... 3: | |
ea740059 | 1177 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1178 | break; |
1179 | case 4: | |
020df079 | 1180 | case 6: |
5679b803 | 1181 | *val = vcpu->arch.dr6; |
020df079 GN |
1182 | break; |
1183 | case 5: | |
020df079 GN |
1184 | default: /* 7 */ |
1185 | *val = vcpu->arch.dr7; | |
1186 | break; | |
1187 | } | |
338dbc97 GN |
1188 | return 0; |
1189 | } | |
020df079 GN |
1190 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1191 | ||
022cd0e8 AK |
1192 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
1193 | { | |
de3cd117 | 1194 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 AK |
1195 | u64 data; |
1196 | int err; | |
1197 | ||
c6702c9d | 1198 | err = kvm_pmu_rdpmc(vcpu, ecx, &data); |
022cd0e8 AK |
1199 | if (err) |
1200 | return err; | |
de3cd117 SC |
1201 | kvm_rax_write(vcpu, (u32)data); |
1202 | kvm_rdx_write(vcpu, data >> 32); | |
022cd0e8 AK |
1203 | return err; |
1204 | } | |
1205 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
1206 | ||
043405e1 CO |
1207 | /* |
1208 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1209 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1210 | * | |
7a5ee6ed CQ |
1211 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) |
1212 | * extract the supported MSRs from the related const lists. | |
1213 | * msrs_to_save is selected from the msrs_to_save_all to reflect the | |
e3267cbb | 1214 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
7a5ee6ed | 1215 | * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs |
62ef68bb | 1216 | * may depend on host virtualization features rather than host cpu features. |
043405e1 | 1217 | */ |
e3267cbb | 1218 | |
7a5ee6ed | 1219 | static const u32 msrs_to_save_all[] = { |
043405e1 | 1220 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1221 | MSR_STAR, |
043405e1 CO |
1222 | #ifdef CONFIG_X86_64 |
1223 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1224 | #endif | |
b3897a49 | 1225 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1226 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1227 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1228 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1229 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1230 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1231 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1232 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1233 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1234 | MSR_IA32_UMWAIT_CONTROL, |
1235 | ||
e2ada66e JM |
1236 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
1237 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, | |
1238 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, | |
1239 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1240 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, | |
1241 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1242 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1243 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
1244 | MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, | |
1245 | MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, | |
1246 | MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, | |
1247 | MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, | |
1248 | MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, | |
e2ada66e JM |
1249 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1250 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1251 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1252 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
1253 | MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, | |
1254 | MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, | |
1255 | MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, | |
1256 | MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, | |
1257 | MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, | |
043405e1 CO |
1258 | }; |
1259 | ||
7a5ee6ed | 1260 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; |
043405e1 CO |
1261 | static unsigned num_msrs_to_save; |
1262 | ||
7a5ee6ed | 1263 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1264 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1265 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1266 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1267 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1268 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1269 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1270 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1271 | HV_X64_MSR_RESET, |
11c4b1ca | 1272 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1273 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1274 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1275 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1276 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1277 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1278 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
f97f5a56 JD |
1279 | HV_X64_MSR_SYNDBG_OPTIONS, |
1280 | HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, | |
1281 | HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, | |
1282 | HV_X64_MSR_SYNDBG_PENDING_BUFFER, | |
a2e164e7 VK |
1283 | |
1284 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
557a961a | 1285 | MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, |
62ef68bb | 1286 | |
ba904635 | 1287 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 1288 | MSR_IA32_TSCDEADLINE, |
2bdb76c0 | 1289 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1290 | MSR_IA32_PERF_CAPABILITIES, |
043405e1 | 1291 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1292 | MSR_IA32_MCG_STATUS, |
1293 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1294 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1295 | MSR_IA32_SMBASE, |
52797bf9 | 1296 | MSR_SMI_COUNT, |
db2336a8 KH |
1297 | MSR_PLATFORM_INFO, |
1298 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1299 | MSR_AMD64_VIRT_SPEC_CTRL, |
6c6a2ab9 | 1300 | MSR_IA32_POWER_CTL, |
99634e3e | 1301 | MSR_IA32_UCODE_REV, |
191c8137 | 1302 | |
95c5c7c7 PB |
1303 | /* |
1304 | * The following list leaves out MSRs whose values are determined | |
1305 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1306 | * We always support the "true" VMX control MSRs, even if the host | |
1307 | * processor does not, so I am putting these registers here rather | |
7a5ee6ed | 1308 | * than in msrs_to_save_all. |
95c5c7c7 PB |
1309 | */ |
1310 | MSR_IA32_VMX_BASIC, | |
1311 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1312 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1313 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1314 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1315 | MSR_IA32_VMX_MISC, | |
1316 | MSR_IA32_VMX_CR0_FIXED0, | |
1317 | MSR_IA32_VMX_CR4_FIXED0, | |
1318 | MSR_IA32_VMX_VMCS_ENUM, | |
1319 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1320 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1321 | MSR_IA32_VMX_VMFUNC, | |
1322 | ||
191c8137 | 1323 | MSR_K7_HWCR, |
2d5ba19b | 1324 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1325 | }; |
1326 | ||
7a5ee6ed | 1327 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1328 | static unsigned num_emulated_msrs; |
1329 | ||
801e459a TL |
1330 | /* |
1331 | * List of msr numbers which are used to expose MSR-based features that | |
1332 | * can be used by a hypervisor to validate requested CPU features. | |
1333 | */ | |
7a5ee6ed | 1334 | static const u32 msr_based_features_all[] = { |
1389309c PB |
1335 | MSR_IA32_VMX_BASIC, |
1336 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1337 | MSR_IA32_VMX_PINBASED_CTLS, | |
1338 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1339 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1340 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1341 | MSR_IA32_VMX_EXIT_CTLS, | |
1342 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1343 | MSR_IA32_VMX_ENTRY_CTLS, | |
1344 | MSR_IA32_VMX_MISC, | |
1345 | MSR_IA32_VMX_CR0_FIXED0, | |
1346 | MSR_IA32_VMX_CR0_FIXED1, | |
1347 | MSR_IA32_VMX_CR4_FIXED0, | |
1348 | MSR_IA32_VMX_CR4_FIXED1, | |
1349 | MSR_IA32_VMX_VMCS_ENUM, | |
1350 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1351 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1352 | MSR_IA32_VMX_VMFUNC, | |
1353 | ||
d1d93fa9 | 1354 | MSR_F10H_DECFG, |
518e7b94 | 1355 | MSR_IA32_UCODE_REV, |
cd283252 | 1356 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1357 | MSR_IA32_PERF_CAPABILITIES, |
801e459a TL |
1358 | }; |
1359 | ||
7a5ee6ed | 1360 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; |
801e459a TL |
1361 | static unsigned int num_msr_based_features; |
1362 | ||
4d22c17c | 1363 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1364 | { |
4d22c17c | 1365 | u64 data = 0; |
5b76a3cf | 1366 | |
4d22c17c XL |
1367 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1368 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf | 1369 | |
b8e8c830 PB |
1370 | /* |
1371 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1372 | * the nested hypervisor runs with NX huge pages. If it is not, | |
1373 | * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other | |
1374 | * L1 guests, so it need not worry about its own (L2) guests. | |
1375 | */ | |
1376 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1377 | ||
5b76a3cf PB |
1378 | /* |
1379 | * If we're doing cache flushes (either "always" or "cond") | |
1380 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1381 | * If an outer hypervisor is doing the cache flush for us | |
1382 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1383 | * capability to the guest too, and if EPT is disabled we're not | |
1384 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1385 | * require a nested hypervisor to do a flush of its own. | |
1386 | */ | |
1387 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1388 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1389 | ||
0c54914d PB |
1390 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1391 | data |= ARCH_CAP_RDCL_NO; | |
1392 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1393 | data |= ARCH_CAP_SSB_NO; | |
1394 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1395 | data |= ARCH_CAP_MDS_NO; | |
1396 | ||
e1d38b63 | 1397 | /* |
c11f83e0 PB |
1398 | * On TAA affected systems: |
1399 | * - nothing to do if TSX is disabled on the host. | |
1400 | * - we emulate TSX_CTRL if present on the host. | |
1401 | * This lets the guest use VERW to clear CPU buffers. | |
e1d38b63 | 1402 | */ |
cbbaa272 | 1403 | if (!boot_cpu_has(X86_FEATURE_RTM)) |
c11f83e0 | 1404 | data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR); |
cbbaa272 PB |
1405 | else if (!boot_cpu_has_bug(X86_BUG_TAA)) |
1406 | data |= ARCH_CAP_TAA_NO; | |
e1d38b63 | 1407 | |
5b76a3cf PB |
1408 | return data; |
1409 | } | |
5b76a3cf | 1410 | |
66421c1e WL |
1411 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1412 | { | |
1413 | switch (msr->index) { | |
cd283252 | 1414 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1415 | msr->data = kvm_get_arch_capabilities(); |
1416 | break; | |
1417 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1418 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1419 | break; |
66421c1e | 1420 | default: |
12bc2132 | 1421 | return kvm_x86_ops.get_msr_feature(msr); |
66421c1e WL |
1422 | } |
1423 | return 0; | |
1424 | } | |
1425 | ||
801e459a TL |
1426 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1427 | { | |
1428 | struct kvm_msr_entry msr; | |
66421c1e | 1429 | int r; |
801e459a TL |
1430 | |
1431 | msr.index = index; | |
66421c1e | 1432 | r = kvm_get_msr_feature(&msr); |
12bc2132 PX |
1433 | |
1434 | if (r == KVM_MSR_RET_INVALID) { | |
1435 | /* Unconditionally clear the output for simplicity */ | |
1436 | *data = 0; | |
cc4cb017 ML |
1437 | if (kvm_msr_ignored_check(vcpu, index, 0, false)) |
1438 | r = 0; | |
12bc2132 PX |
1439 | } |
1440 | ||
66421c1e WL |
1441 | if (r) |
1442 | return r; | |
801e459a TL |
1443 | |
1444 | *data = msr.data; | |
1445 | ||
1446 | return 0; | |
1447 | } | |
1448 | ||
11988499 | 1449 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1450 | { |
1b4d56b8 | 1451 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1452 | return false; |
1b2fd70c | 1453 | |
1b4d56b8 | 1454 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1455 | return false; |
d8017474 | 1456 | |
0a629563 SC |
1457 | if (efer & (EFER_LME | EFER_LMA) && |
1458 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1459 | return false; | |
1460 | ||
1461 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1462 | return false; | |
d8017474 | 1463 | |
384bb783 | 1464 | return true; |
11988499 SC |
1465 | |
1466 | } | |
1467 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1468 | { | |
1469 | if (efer & efer_reserved_bits) | |
1470 | return false; | |
1471 | ||
1472 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1473 | } |
1474 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1475 | ||
11988499 | 1476 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1477 | { |
1478 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1479 | u64 efer = msr_info->data; |
72f211ec | 1480 | int r; |
384bb783 | 1481 | |
11988499 | 1482 | if (efer & efer_reserved_bits) |
66f61c92 | 1483 | return 1; |
384bb783 | 1484 | |
11988499 SC |
1485 | if (!msr_info->host_initiated) { |
1486 | if (!__kvm_valid_efer(vcpu, efer)) | |
1487 | return 1; | |
1488 | ||
1489 | if (is_paging(vcpu) && | |
1490 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1491 | return 1; | |
1492 | } | |
384bb783 | 1493 | |
15c4a640 | 1494 | efer &= ~EFER_LMA; |
f6801dff | 1495 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1496 | |
72f211ec ML |
1497 | r = kvm_x86_ops.set_efer(vcpu, efer); |
1498 | if (r) { | |
1499 | WARN_ON(r > 0); | |
1500 | return r; | |
1501 | } | |
a3d204e2 | 1502 | |
aad82703 SY |
1503 | /* Update reserved bits */ |
1504 | if ((efer ^ old_efer) & EFER_NX) | |
1505 | kvm_mmu_reset_context(vcpu); | |
1506 | ||
b69e8cae | 1507 | return 0; |
15c4a640 CO |
1508 | } |
1509 | ||
f2b4b7dd JR |
1510 | void kvm_enable_efer_bits(u64 mask) |
1511 | { | |
1512 | efer_reserved_bits &= ~mask; | |
1513 | } | |
1514 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1515 | ||
51de8151 AG |
1516 | bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) |
1517 | { | |
1a155254 AG |
1518 | struct kvm *kvm = vcpu->kvm; |
1519 | struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges; | |
1520 | u32 count = kvm->arch.msr_filter.count; | |
1521 | u32 i; | |
1522 | bool r = kvm->arch.msr_filter.default_allow; | |
1523 | int idx; | |
1524 | ||
9389b9d5 SC |
1525 | /* MSR filtering not set up or x2APIC enabled, allow everything */ |
1526 | if (!count || (index >= 0x800 && index <= 0x8ff)) | |
1a155254 AG |
1527 | return true; |
1528 | ||
1529 | /* Prevent collision with set_msr_filter */ | |
1530 | idx = srcu_read_lock(&kvm->srcu); | |
1531 | ||
1532 | for (i = 0; i < count; i++) { | |
1533 | u32 start = ranges[i].base; | |
1534 | u32 end = start + ranges[i].nmsrs; | |
1535 | u32 flags = ranges[i].flags; | |
1536 | unsigned long *bitmap = ranges[i].bitmap; | |
1537 | ||
1538 | if ((index >= start) && (index < end) && (flags & type)) { | |
1539 | r = !!test_bit(index - start, bitmap); | |
1540 | break; | |
1541 | } | |
1542 | } | |
1543 | ||
1544 | srcu_read_unlock(&kvm->srcu, idx); | |
1545 | ||
1546 | return r; | |
51de8151 AG |
1547 | } |
1548 | EXPORT_SYMBOL_GPL(kvm_msr_allowed); | |
1549 | ||
15c4a640 | 1550 | /* |
f20935d8 SC |
1551 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1552 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1553 | * Returns 0 on success, non-0 otherwise. |
1554 | * Assumes vcpu_load() was already called. | |
1555 | */ | |
f20935d8 SC |
1556 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1557 | bool host_initiated) | |
15c4a640 | 1558 | { |
f20935d8 SC |
1559 | struct msr_data msr; |
1560 | ||
1a155254 | 1561 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) |
cc4cb017 | 1562 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1563 | |
f20935d8 | 1564 | switch (index) { |
854e8bb1 NA |
1565 | case MSR_FS_BASE: |
1566 | case MSR_GS_BASE: | |
1567 | case MSR_KERNEL_GS_BASE: | |
1568 | case MSR_CSTAR: | |
1569 | case MSR_LSTAR: | |
f20935d8 | 1570 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1571 | return 1; |
1572 | break; | |
1573 | case MSR_IA32_SYSENTER_EIP: | |
1574 | case MSR_IA32_SYSENTER_ESP: | |
1575 | /* | |
1576 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1577 | * non-canonical address is written on Intel but not on | |
1578 | * AMD (which ignores the top 32-bits, because it does | |
1579 | * not implement 64-bit SYSENTER). | |
1580 | * | |
1581 | * 64-bit code should hence be able to write a non-canonical | |
1582 | * value on AMD. Making the address canonical ensures that | |
1583 | * vmentry does not fail on Intel after writing a non-canonical | |
1584 | * value, and that something deterministic happens if the guest | |
1585 | * invokes 64-bit SYSENTER. | |
1586 | */ | |
f20935d8 | 1587 | data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); |
854e8bb1 | 1588 | } |
f20935d8 SC |
1589 | |
1590 | msr.data = data; | |
1591 | msr.index = index; | |
1592 | msr.host_initiated = host_initiated; | |
1593 | ||
afaf0b2f | 1594 | return kvm_x86_ops.set_msr(vcpu, &msr); |
15c4a640 CO |
1595 | } |
1596 | ||
6abe9c13 PX |
1597 | static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, |
1598 | u32 index, u64 data, bool host_initiated) | |
1599 | { | |
1600 | int ret = __kvm_set_msr(vcpu, index, data, host_initiated); | |
1601 | ||
1602 | if (ret == KVM_MSR_RET_INVALID) | |
cc4cb017 ML |
1603 | if (kvm_msr_ignored_check(vcpu, index, data, true)) |
1604 | ret = 0; | |
6abe9c13 PX |
1605 | |
1606 | return ret; | |
1607 | } | |
1608 | ||
313a3dc7 | 1609 | /* |
f20935d8 SC |
1610 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1611 | * checks are bypassed if @host_initiated is %true. | |
1612 | * Returns 0 on success, non-0 otherwise. | |
1613 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1614 | */ |
edef5c36 PB |
1615 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1616 | bool host_initiated) | |
609e36d3 PB |
1617 | { |
1618 | struct msr_data msr; | |
f20935d8 | 1619 | int ret; |
609e36d3 | 1620 | |
1a155254 | 1621 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) |
cc4cb017 | 1622 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1623 | |
609e36d3 | 1624 | msr.index = index; |
f20935d8 | 1625 | msr.host_initiated = host_initiated; |
609e36d3 | 1626 | |
afaf0b2f | 1627 | ret = kvm_x86_ops.get_msr(vcpu, &msr); |
f20935d8 SC |
1628 | if (!ret) |
1629 | *data = msr.data; | |
1630 | return ret; | |
609e36d3 PB |
1631 | } |
1632 | ||
6abe9c13 PX |
1633 | static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, |
1634 | u32 index, u64 *data, bool host_initiated) | |
1635 | { | |
1636 | int ret = __kvm_get_msr(vcpu, index, data, host_initiated); | |
1637 | ||
1638 | if (ret == KVM_MSR_RET_INVALID) { | |
1639 | /* Unconditionally clear *data for simplicity */ | |
1640 | *data = 0; | |
cc4cb017 ML |
1641 | if (kvm_msr_ignored_check(vcpu, index, 0, false)) |
1642 | ret = 0; | |
6abe9c13 PX |
1643 | } |
1644 | ||
1645 | return ret; | |
1646 | } | |
1647 | ||
f20935d8 | 1648 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1649 | { |
6abe9c13 | 1650 | return kvm_get_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1651 | } |
1652 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1653 | |
f20935d8 SC |
1654 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1655 | { | |
6abe9c13 | 1656 | return kvm_set_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1657 | } |
1658 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1659 | ||
8b474427 | 1660 | static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) |
1ae09954 | 1661 | { |
8b474427 PB |
1662 | int err = vcpu->run->msr.error; |
1663 | if (!err) { | |
1ae09954 AG |
1664 | kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); |
1665 | kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); | |
1666 | } | |
1667 | ||
f9a4d621 | 1668 | return kvm_x86_ops.complete_emulated_msr(vcpu, err); |
1ae09954 AG |
1669 | } |
1670 | ||
1671 | static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) | |
1672 | { | |
f9a4d621 | 1673 | return kvm_x86_ops.complete_emulated_msr(vcpu, vcpu->run->msr.error); |
1ae09954 AG |
1674 | } |
1675 | ||
1676 | static u64 kvm_msr_reason(int r) | |
1677 | { | |
1678 | switch (r) { | |
cc4cb017 | 1679 | case KVM_MSR_RET_INVALID: |
1ae09954 | 1680 | return KVM_MSR_EXIT_REASON_UNKNOWN; |
cc4cb017 | 1681 | case KVM_MSR_RET_FILTERED: |
1a155254 | 1682 | return KVM_MSR_EXIT_REASON_FILTER; |
1ae09954 AG |
1683 | default: |
1684 | return KVM_MSR_EXIT_REASON_INVAL; | |
1685 | } | |
1686 | } | |
1687 | ||
1688 | static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, | |
1689 | u32 exit_reason, u64 data, | |
1690 | int (*completion)(struct kvm_vcpu *vcpu), | |
1691 | int r) | |
1692 | { | |
1693 | u64 msr_reason = kvm_msr_reason(r); | |
1694 | ||
1695 | /* Check if the user wanted to know about this MSR fault */ | |
1696 | if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) | |
1697 | return 0; | |
1698 | ||
1699 | vcpu->run->exit_reason = exit_reason; | |
1700 | vcpu->run->msr.error = 0; | |
1701 | memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); | |
1702 | vcpu->run->msr.reason = msr_reason; | |
1703 | vcpu->run->msr.index = index; | |
1704 | vcpu->run->msr.data = data; | |
1705 | vcpu->arch.complete_userspace_io = completion; | |
1706 | ||
1707 | return 1; | |
1708 | } | |
1709 | ||
1710 | static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) | |
1711 | { | |
1712 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, | |
1713 | complete_emulated_rdmsr, r); | |
1714 | } | |
1715 | ||
1716 | static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) | |
1717 | { | |
1718 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, | |
1719 | complete_emulated_wrmsr, r); | |
1720 | } | |
1721 | ||
1edce0a9 SC |
1722 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
1723 | { | |
1724 | u32 ecx = kvm_rcx_read(vcpu); | |
1725 | u64 data; | |
1ae09954 AG |
1726 | int r; |
1727 | ||
1728 | r = kvm_get_msr(vcpu, ecx, &data); | |
1edce0a9 | 1729 | |
1ae09954 AG |
1730 | /* MSR read failed? See if we should ask user space */ |
1731 | if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { | |
1732 | /* Bounce to user space */ | |
1733 | return 0; | |
1734 | } | |
1735 | ||
8b474427 PB |
1736 | if (!r) { |
1737 | trace_kvm_msr_read(ecx, data); | |
1738 | ||
1739 | kvm_rax_write(vcpu, data & -1u); | |
1740 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
1741 | } else { | |
1edce0a9 | 1742 | trace_kvm_msr_read_ex(ecx); |
1edce0a9 SC |
1743 | } |
1744 | ||
f9a4d621 | 1745 | return kvm_x86_ops.complete_emulated_msr(vcpu, r); |
1edce0a9 SC |
1746 | } |
1747 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
1748 | ||
1749 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
1750 | { | |
1751 | u32 ecx = kvm_rcx_read(vcpu); | |
1752 | u64 data = kvm_read_edx_eax(vcpu); | |
1ae09954 | 1753 | int r; |
1edce0a9 | 1754 | |
1ae09954 AG |
1755 | r = kvm_set_msr(vcpu, ecx, data); |
1756 | ||
1757 | /* MSR write failed? See if we should ask user space */ | |
7dffecaf | 1758 | if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) |
1ae09954 AG |
1759 | /* Bounce to user space */ |
1760 | return 0; | |
7dffecaf ML |
1761 | |
1762 | /* Signal all other negative errors to userspace */ | |
1763 | if (r < 0) | |
1764 | return r; | |
1ae09954 | 1765 | |
8b474427 PB |
1766 | if (!r) |
1767 | trace_kvm_msr_write(ecx, data); | |
1768 | else | |
1edce0a9 | 1769 | trace_kvm_msr_write_ex(ecx, data); |
1edce0a9 | 1770 | |
f9a4d621 | 1771 | return kvm_x86_ops.complete_emulated_msr(vcpu, r); |
1edce0a9 SC |
1772 | } |
1773 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
1774 | ||
5a9f5443 WL |
1775 | bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) |
1776 | { | |
1777 | return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || | |
72c3c0fe | 1778 | xfer_to_guest_mode_work_pending(); |
5a9f5443 WL |
1779 | } |
1780 | EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request); | |
1781 | ||
1e9e2622 WL |
1782 | /* |
1783 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
1784 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
1785 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
1786 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
1787 | * other cases which must be called after interrupts are enabled on the host. | |
1788 | */ | |
1789 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
1790 | { | |
e1be9ac8 WL |
1791 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) |
1792 | return 1; | |
1793 | ||
1794 | if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && | |
1e9e2622 | 1795 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && |
4064a4c6 WL |
1796 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && |
1797 | ((u32)(data >> 32) != X2APIC_BROADCAST)) { | |
1e9e2622 | 1798 | |
d5361678 WL |
1799 | data &= ~(1 << 12); |
1800 | kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); | |
1e9e2622 | 1801 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); |
d5361678 WL |
1802 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); |
1803 | trace_kvm_apic_write(APIC_ICR, (u32)data); | |
1804 | return 0; | |
1e9e2622 WL |
1805 | } |
1806 | ||
1807 | return 1; | |
1808 | } | |
1809 | ||
ae95f566 WL |
1810 | static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) |
1811 | { | |
1812 | if (!kvm_can_use_hv_timer(vcpu)) | |
1813 | return 1; | |
1814 | ||
1815 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
1816 | return 0; | |
1817 | } | |
1818 | ||
404d5d7b | 1819 | fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) |
1e9e2622 WL |
1820 | { |
1821 | u32 msr = kvm_rcx_read(vcpu); | |
8a1038de | 1822 | u64 data; |
404d5d7b | 1823 | fastpath_t ret = EXIT_FASTPATH_NONE; |
1e9e2622 WL |
1824 | |
1825 | switch (msr) { | |
1826 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
8a1038de | 1827 | data = kvm_read_edx_eax(vcpu); |
404d5d7b WL |
1828 | if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { |
1829 | kvm_skip_emulated_instruction(vcpu); | |
1830 | ret = EXIT_FASTPATH_EXIT_HANDLED; | |
80bc97f2 | 1831 | } |
1e9e2622 | 1832 | break; |
ae95f566 WL |
1833 | case MSR_IA32_TSCDEADLINE: |
1834 | data = kvm_read_edx_eax(vcpu); | |
1835 | if (!handle_fastpath_set_tscdeadline(vcpu, data)) { | |
1836 | kvm_skip_emulated_instruction(vcpu); | |
1837 | ret = EXIT_FASTPATH_REENTER_GUEST; | |
1838 | } | |
1839 | break; | |
1e9e2622 | 1840 | default: |
404d5d7b | 1841 | break; |
1e9e2622 WL |
1842 | } |
1843 | ||
404d5d7b | 1844 | if (ret != EXIT_FASTPATH_NONE) |
1e9e2622 | 1845 | trace_kvm_msr_write(msr, data); |
1e9e2622 | 1846 | |
404d5d7b | 1847 | return ret; |
1e9e2622 WL |
1848 | } |
1849 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
1850 | ||
f20935d8 SC |
1851 | /* |
1852 | * Adapt set_msr() to msr_io()'s calling convention | |
1853 | */ | |
1854 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1855 | { | |
6abe9c13 | 1856 | return kvm_get_msr_ignored_check(vcpu, index, data, true); |
f20935d8 SC |
1857 | } |
1858 | ||
1859 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1860 | { | |
6abe9c13 | 1861 | return kvm_set_msr_ignored_check(vcpu, index, *data, true); |
313a3dc7 CO |
1862 | } |
1863 | ||
16e8d74d | 1864 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
1865 | struct pvclock_clock { |
1866 | int vclock_mode; | |
1867 | u64 cycle_last; | |
1868 | u64 mask; | |
1869 | u32 mult; | |
1870 | u32 shift; | |
917f9475 PB |
1871 | u64 base_cycles; |
1872 | u64 offset; | |
53fafdbb MT |
1873 | }; |
1874 | ||
16e8d74d MT |
1875 | struct pvclock_gtod_data { |
1876 | seqcount_t seq; | |
1877 | ||
53fafdbb MT |
1878 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
1879 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 1880 | |
917f9475 | 1881 | ktime_t offs_boot; |
55dd00a7 | 1882 | u64 wall_time_sec; |
16e8d74d MT |
1883 | }; |
1884 | ||
1885 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1886 | ||
1887 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1888 | { | |
1889 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
1890 | ||
1891 | write_seqcount_begin(&vdata->seq); | |
1892 | ||
1893 | /* copy pvclock gtod data */ | |
b95a8a27 | 1894 | vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; |
876e7881 PZ |
1895 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; |
1896 | vdata->clock.mask = tk->tkr_mono.mask; | |
1897 | vdata->clock.mult = tk->tkr_mono.mult; | |
1898 | vdata->clock.shift = tk->tkr_mono.shift; | |
917f9475 PB |
1899 | vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; |
1900 | vdata->clock.offset = tk->tkr_mono.base; | |
16e8d74d | 1901 | |
b95a8a27 | 1902 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; |
53fafdbb MT |
1903 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; |
1904 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
1905 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
1906 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
917f9475 PB |
1907 | vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; |
1908 | vdata->raw_clock.offset = tk->tkr_raw.base; | |
16e8d74d | 1909 | |
55dd00a7 MT |
1910 | vdata->wall_time_sec = tk->xtime_sec; |
1911 | ||
917f9475 | 1912 | vdata->offs_boot = tk->offs_boot; |
53fafdbb | 1913 | |
16e8d74d MT |
1914 | write_seqcount_end(&vdata->seq); |
1915 | } | |
8171cd68 PB |
1916 | |
1917 | static s64 get_kvmclock_base_ns(void) | |
1918 | { | |
1919 | /* Count up from boot time, but with the frequency of the raw clock. */ | |
1920 | return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); | |
1921 | } | |
1922 | #else | |
1923 | static s64 get_kvmclock_base_ns(void) | |
1924 | { | |
1925 | /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ | |
1926 | return ktime_get_boottime_ns(); | |
1927 | } | |
16e8d74d MT |
1928 | #endif |
1929 | ||
18068523 GOC |
1930 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1931 | { | |
9ed3c444 AK |
1932 | int version; |
1933 | int r; | |
50d0a0f9 | 1934 | struct pvclock_wall_clock wc; |
8171cd68 | 1935 | u64 wall_nsec; |
18068523 | 1936 | |
210dfd93 OU |
1937 | kvm->arch.wall_clock = wall_clock; |
1938 | ||
18068523 GOC |
1939 | if (!wall_clock) |
1940 | return; | |
1941 | ||
9ed3c444 AK |
1942 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1943 | if (r) | |
1944 | return; | |
1945 | ||
1946 | if (version & 1) | |
1947 | ++version; /* first time write, random junk */ | |
1948 | ||
1949 | ++version; | |
18068523 | 1950 | |
1dab1345 NK |
1951 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
1952 | return; | |
18068523 | 1953 | |
50d0a0f9 GH |
1954 | /* |
1955 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1956 | * system time (updated by kvm_guest_time_update below) to the |
8171cd68 | 1957 | * wall clock specified here. We do the reverse here. |
50d0a0f9 | 1958 | */ |
8171cd68 | 1959 | wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); |
50d0a0f9 | 1960 | |
8171cd68 PB |
1961 | wc.nsec = do_div(wall_nsec, 1000000000); |
1962 | wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ | |
50d0a0f9 | 1963 | wc.version = version; |
18068523 GOC |
1964 | |
1965 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1966 | ||
1967 | version++; | |
1968 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1969 | } |
1970 | ||
5b9bb0eb OU |
1971 | static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, |
1972 | bool old_msr, bool host_initiated) | |
1973 | { | |
1974 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
1975 | ||
1976 | if (vcpu->vcpu_id == 0 && !host_initiated) { | |
1e293d1a | 1977 | if (ka->boot_vcpu_runs_old_kvmclock != old_msr) |
5b9bb0eb OU |
1978 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1979 | ||
1980 | ka->boot_vcpu_runs_old_kvmclock = old_msr; | |
1981 | } | |
1982 | ||
1983 | vcpu->arch.time = system_time; | |
1984 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
1985 | ||
1986 | /* we verify if the enable bit is set... */ | |
1987 | vcpu->arch.pv_time_enabled = false; | |
1988 | if (!(system_time & 1)) | |
1989 | return; | |
1990 | ||
1991 | if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
1992 | &vcpu->arch.pv_time, system_time & ~1ULL, | |
1993 | sizeof(struct pvclock_vcpu_time_info))) | |
1994 | vcpu->arch.pv_time_enabled = true; | |
1995 | ||
1996 | return; | |
1997 | } | |
1998 | ||
50d0a0f9 GH |
1999 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
2000 | { | |
b51012de PB |
2001 | do_shl32_div32(dividend, divisor); |
2002 | return dividend; | |
50d0a0f9 GH |
2003 | } |
2004 | ||
3ae13faa | 2005 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 2006 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 2007 | { |
5f4e3f88 | 2008 | uint64_t scaled64; |
50d0a0f9 GH |
2009 | int32_t shift = 0; |
2010 | uint64_t tps64; | |
2011 | uint32_t tps32; | |
2012 | ||
3ae13faa PB |
2013 | tps64 = base_hz; |
2014 | scaled64 = scaled_hz; | |
50933623 | 2015 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
2016 | tps64 >>= 1; |
2017 | shift--; | |
2018 | } | |
2019 | ||
2020 | tps32 = (uint32_t)tps64; | |
50933623 JK |
2021 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
2022 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
2023 | scaled64 >>= 1; |
2024 | else | |
2025 | tps32 <<= 1; | |
50d0a0f9 GH |
2026 | shift++; |
2027 | } | |
2028 | ||
5f4e3f88 ZA |
2029 | *pshift = shift; |
2030 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
2031 | } |
2032 | ||
d828199e | 2033 | #ifdef CONFIG_X86_64 |
16e8d74d | 2034 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 2035 | #endif |
16e8d74d | 2036 | |
c8076604 | 2037 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 2038 | static unsigned long max_tsc_khz; |
c8076604 | 2039 | |
cc578287 | 2040 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 2041 | { |
cc578287 ZA |
2042 | u64 v = (u64)khz * (1000000 + ppm); |
2043 | do_div(v, 1000000); | |
2044 | return v; | |
1e993611 JR |
2045 | } |
2046 | ||
381d585c HZ |
2047 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
2048 | { | |
2049 | u64 ratio; | |
2050 | ||
2051 | /* Guest TSC same frequency as host TSC? */ | |
2052 | if (!scale) { | |
2053 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
2054 | return 0; | |
2055 | } | |
2056 | ||
2057 | /* TSC scaling supported? */ | |
2058 | if (!kvm_has_tsc_control) { | |
2059 | if (user_tsc_khz > tsc_khz) { | |
2060 | vcpu->arch.tsc_catchup = 1; | |
2061 | vcpu->arch.tsc_always_catchup = 1; | |
2062 | return 0; | |
2063 | } else { | |
3f16a5c3 | 2064 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
2065 | return -1; |
2066 | } | |
2067 | } | |
2068 | ||
2069 | /* TSC scaling required - calculate ratio */ | |
2070 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
2071 | user_tsc_khz, tsc_khz); | |
2072 | ||
2073 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
3f16a5c3 PB |
2074 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
2075 | user_tsc_khz); | |
381d585c HZ |
2076 | return -1; |
2077 | } | |
2078 | ||
2079 | vcpu->arch.tsc_scaling_ratio = ratio; | |
2080 | return 0; | |
2081 | } | |
2082 | ||
4941b8cb | 2083 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 2084 | { |
cc578287 ZA |
2085 | u32 thresh_lo, thresh_hi; |
2086 | int use_scaling = 0; | |
217fc9cf | 2087 | |
03ba32ca | 2088 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 2089 | if (user_tsc_khz == 0) { |
ad721883 HZ |
2090 | /* set tsc_scaling_ratio to a safe value */ |
2091 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
381d585c | 2092 | return -1; |
ad721883 | 2093 | } |
03ba32ca | 2094 | |
c285545f | 2095 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 2096 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
2097 | &vcpu->arch.virtual_tsc_shift, |
2098 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 2099 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
2100 | |
2101 | /* | |
2102 | * Compute the variation in TSC rate which is acceptable | |
2103 | * within the range of tolerance and decide if the | |
2104 | * rate being applied is within that bounds of the hardware | |
2105 | * rate. If so, no scaling or compensation need be done. | |
2106 | */ | |
2107 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
2108 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
2109 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
2110 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
2111 | use_scaling = 1; |
2112 | } | |
4941b8cb | 2113 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
2114 | } |
2115 | ||
2116 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
2117 | { | |
e26101b1 | 2118 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
2119 | vcpu->arch.virtual_tsc_mult, |
2120 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 2121 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
2122 | return tsc; |
2123 | } | |
2124 | ||
b0c39dc6 VK |
2125 | static inline int gtod_is_based_on_tsc(int mode) |
2126 | { | |
b95a8a27 | 2127 | return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; |
b0c39dc6 VK |
2128 | } |
2129 | ||
69b0049a | 2130 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
2131 | { |
2132 | #ifdef CONFIG_X86_64 | |
2133 | bool vcpus_matched; | |
b48aa97e MT |
2134 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2135 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2136 | ||
2137 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2138 | atomic_read(&vcpu->kvm->online_vcpus)); | |
2139 | ||
7f187922 MT |
2140 | /* |
2141 | * Once the masterclock is enabled, always perform request in | |
2142 | * order to update it. | |
2143 | * | |
2144 | * In order to enable masterclock, the host clocksource must be TSC | |
2145 | * and the vcpus need to have matched TSCs. When that happens, | |
2146 | * perform request to enable masterclock. | |
2147 | */ | |
2148 | if (ka->use_master_clock || | |
b0c39dc6 | 2149 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
2150 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2151 | ||
2152 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
2153 | atomic_read(&vcpu->kvm->online_vcpus), | |
2154 | ka->use_master_clock, gtod->clock.vclock_mode); | |
2155 | #endif | |
2156 | } | |
2157 | ||
35181e86 HZ |
2158 | /* |
2159 | * Multiply tsc by a fixed point number represented by ratio. | |
2160 | * | |
2161 | * The most significant 64-N bits (mult) of ratio represent the | |
2162 | * integral part of the fixed point number; the remaining N bits | |
2163 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
2164 | * point number (mult + frac * 2^(-N)). | |
2165 | * | |
2166 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
2167 | */ | |
2168 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
2169 | { | |
2170 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
2171 | } | |
2172 | ||
2173 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
2174 | { | |
2175 | u64 _tsc = tsc; | |
2176 | u64 ratio = vcpu->arch.tsc_scaling_ratio; | |
2177 | ||
2178 | if (ratio != kvm_default_tsc_scaling_ratio) | |
2179 | _tsc = __scale_tsc(ratio, tsc); | |
2180 | ||
2181 | return _tsc; | |
2182 | } | |
2183 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
2184 | ||
07c1419a HZ |
2185 | static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
2186 | { | |
2187 | u64 tsc; | |
2188 | ||
2189 | tsc = kvm_scale_tsc(vcpu, rdtsc()); | |
2190 | ||
2191 | return target_tsc - tsc; | |
2192 | } | |
2193 | ||
4ba76538 HZ |
2194 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
2195 | { | |
56ba77a4 | 2196 | return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc); |
4ba76538 HZ |
2197 | } |
2198 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
2199 | ||
a545ab6a LC |
2200 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
2201 | { | |
56ba77a4 | 2202 | vcpu->arch.l1_tsc_offset = offset; |
afaf0b2f | 2203 | vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset); |
a545ab6a LC |
2204 | } |
2205 | ||
b0c39dc6 VK |
2206 | static inline bool kvm_check_tsc_unstable(void) |
2207 | { | |
2208 | #ifdef CONFIG_X86_64 | |
2209 | /* | |
2210 | * TSC is marked unstable when we're running on Hyper-V, | |
2211 | * 'TSC page' clocksource is good. | |
2212 | */ | |
b95a8a27 | 2213 | if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) |
b0c39dc6 VK |
2214 | return false; |
2215 | #endif | |
2216 | return check_tsc_unstable(); | |
2217 | } | |
2218 | ||
0c899c25 | 2219 | static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) |
99e3e30a ZA |
2220 | { |
2221 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 2222 | u64 offset, ns, elapsed; |
99e3e30a | 2223 | unsigned long flags; |
b48aa97e | 2224 | bool matched; |
0d3da0d2 | 2225 | bool already_matched; |
c5e8ec8e | 2226 | bool synchronizing = false; |
99e3e30a | 2227 | |
038f8c11 | 2228 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
07c1419a | 2229 | offset = kvm_compute_tsc_offset(vcpu, data); |
8171cd68 | 2230 | ns = get_kvmclock_base_ns(); |
f38e098f | 2231 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 2232 | |
03ba32ca | 2233 | if (vcpu->arch.virtual_tsc_khz) { |
0c899c25 | 2234 | if (data == 0) { |
bd8fab39 DP |
2235 | /* |
2236 | * detection of vcpu initialization -- need to sync | |
2237 | * with other vCPUs. This particularly helps to keep | |
2238 | * kvm_clock stable after CPU hotplug | |
2239 | */ | |
2240 | synchronizing = true; | |
2241 | } else { | |
2242 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
2243 | nsec_to_cycles(vcpu, elapsed); | |
2244 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
2245 | /* | |
2246 | * Special case: TSC write with a small delta (1 second) | |
2247 | * of virtual cycle time against real time is | |
2248 | * interpreted as an attempt to synchronize the CPU. | |
2249 | */ | |
2250 | synchronizing = data < tsc_exp + tsc_hz && | |
2251 | data + tsc_hz > tsc_exp; | |
2252 | } | |
c5e8ec8e | 2253 | } |
f38e098f ZA |
2254 | |
2255 | /* | |
5d3cb0f6 ZA |
2256 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
2257 | * TSC, we add elapsed time in this computation. We could let the | |
2258 | * compensation code attempt to catch up if we fall behind, but | |
2259 | * it's better to try to match offsets from the beginning. | |
2260 | */ | |
c5e8ec8e | 2261 | if (synchronizing && |
5d3cb0f6 | 2262 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 2263 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 2264 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 2265 | } else { |
857e4099 | 2266 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 2267 | data += delta; |
07c1419a | 2268 | offset = kvm_compute_tsc_offset(vcpu, data); |
f38e098f | 2269 | } |
b48aa97e | 2270 | matched = true; |
0d3da0d2 | 2271 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
2272 | } else { |
2273 | /* | |
2274 | * We split periods of matched TSC writes into generations. | |
2275 | * For each generation, we track the original measured | |
2276 | * nanosecond time, offset, and write, so if TSCs are in | |
2277 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 2278 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
2279 | * |
2280 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2281 | */ | |
2282 | kvm->arch.cur_tsc_generation++; | |
2283 | kvm->arch.cur_tsc_nsec = ns; | |
2284 | kvm->arch.cur_tsc_write = data; | |
2285 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 2286 | matched = false; |
f38e098f | 2287 | } |
e26101b1 ZA |
2288 | |
2289 | /* | |
2290 | * We also track th most recent recorded KHZ, write and time to | |
2291 | * allow the matching interval to be extended at each write. | |
2292 | */ | |
f38e098f ZA |
2293 | kvm->arch.last_tsc_nsec = ns; |
2294 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 2295 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 2296 | |
b183aa58 | 2297 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
2298 | |
2299 | /* Keep track of which generation this VCPU has synchronized to */ | |
2300 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2301 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2302 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2303 | ||
a545ab6a | 2304 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
e26101b1 | 2305 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
b48aa97e MT |
2306 | |
2307 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 2308 | if (!matched) { |
b48aa97e | 2309 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
2310 | } else if (!already_matched) { |
2311 | kvm->arch.nr_vcpus_matched_tsc++; | |
2312 | } | |
b48aa97e MT |
2313 | |
2314 | kvm_track_tsc_matching(vcpu); | |
2315 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 2316 | } |
e26101b1 | 2317 | |
58ea6767 HZ |
2318 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2319 | s64 adjustment) | |
2320 | { | |
56ba77a4 | 2321 | u64 tsc_offset = vcpu->arch.l1_tsc_offset; |
326e7425 | 2322 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); |
58ea6767 HZ |
2323 | } |
2324 | ||
2325 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2326 | { | |
2327 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) | |
2328 | WARN_ON(adjustment < 0); | |
2329 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); | |
ea26e4ec | 2330 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2331 | } |
2332 | ||
d828199e MT |
2333 | #ifdef CONFIG_X86_64 |
2334 | ||
a5a1d1c2 | 2335 | static u64 read_tsc(void) |
d828199e | 2336 | { |
a5a1d1c2 | 2337 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2338 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2339 | |
2340 | if (likely(ret >= last)) | |
2341 | return ret; | |
2342 | ||
2343 | /* | |
2344 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2345 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2346 | * very likely) and there's a data dependence, so force GCC |
2347 | * to generate a branch instead. I don't barrier() because | |
2348 | * we don't actually need a barrier, and if this function | |
2349 | * ever gets inlined it will generate worse code. | |
2350 | */ | |
2351 | asm volatile (""); | |
2352 | return last; | |
2353 | } | |
2354 | ||
53fafdbb MT |
2355 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2356 | int *mode) | |
d828199e MT |
2357 | { |
2358 | long v; | |
b0c39dc6 VK |
2359 | u64 tsc_pg_val; |
2360 | ||
53fafdbb | 2361 | switch (clock->vclock_mode) { |
b95a8a27 | 2362 | case VDSO_CLOCKMODE_HVCLOCK: |
b0c39dc6 VK |
2363 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), |
2364 | tsc_timestamp); | |
2365 | if (tsc_pg_val != U64_MAX) { | |
2366 | /* TSC page valid */ | |
b95a8a27 | 2367 | *mode = VDSO_CLOCKMODE_HVCLOCK; |
53fafdbb MT |
2368 | v = (tsc_pg_val - clock->cycle_last) & |
2369 | clock->mask; | |
b0c39dc6 VK |
2370 | } else { |
2371 | /* TSC page invalid */ | |
b95a8a27 | 2372 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 VK |
2373 | } |
2374 | break; | |
b95a8a27 TG |
2375 | case VDSO_CLOCKMODE_TSC: |
2376 | *mode = VDSO_CLOCKMODE_TSC; | |
b0c39dc6 | 2377 | *tsc_timestamp = read_tsc(); |
53fafdbb MT |
2378 | v = (*tsc_timestamp - clock->cycle_last) & |
2379 | clock->mask; | |
b0c39dc6 VK |
2380 | break; |
2381 | default: | |
b95a8a27 | 2382 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 | 2383 | } |
d828199e | 2384 | |
b95a8a27 | 2385 | if (*mode == VDSO_CLOCKMODE_NONE) |
b0c39dc6 | 2386 | *tsc_timestamp = v = 0; |
d828199e | 2387 | |
53fafdbb | 2388 | return v * clock->mult; |
d828199e MT |
2389 | } |
2390 | ||
53fafdbb | 2391 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2392 | { |
cbcf2dd3 | 2393 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2394 | unsigned long seq; |
d828199e | 2395 | int mode; |
cbcf2dd3 | 2396 | u64 ns; |
d828199e | 2397 | |
d828199e MT |
2398 | do { |
2399 | seq = read_seqcount_begin(>od->seq); | |
917f9475 | 2400 | ns = gtod->raw_clock.base_cycles; |
53fafdbb | 2401 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); |
917f9475 PB |
2402 | ns >>= gtod->raw_clock.shift; |
2403 | ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); | |
d828199e | 2404 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2405 | *t = ns; |
d828199e MT |
2406 | |
2407 | return mode; | |
2408 | } | |
2409 | ||
899a31f5 | 2410 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2411 | { |
2412 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2413 | unsigned long seq; | |
2414 | int mode; | |
2415 | u64 ns; | |
2416 | ||
2417 | do { | |
2418 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 | 2419 | ts->tv_sec = gtod->wall_time_sec; |
917f9475 | 2420 | ns = gtod->clock.base_cycles; |
53fafdbb | 2421 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2422 | ns >>= gtod->clock.shift; |
2423 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2424 | ||
2425 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2426 | ts->tv_nsec = ns; | |
2427 | ||
2428 | return mode; | |
2429 | } | |
2430 | ||
b0c39dc6 VK |
2431 | /* returns true if host is using TSC based clocksource */ |
2432 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2433 | { |
d828199e | 2434 | /* checked again under seqlock below */ |
b0c39dc6 | 2435 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2436 | return false; |
2437 | ||
53fafdbb | 2438 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2439 | tsc_timestamp)); |
d828199e | 2440 | } |
55dd00a7 | 2441 | |
b0c39dc6 | 2442 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2443 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2444 | u64 *tsc_timestamp) |
55dd00a7 MT |
2445 | { |
2446 | /* checked again under seqlock below */ | |
b0c39dc6 | 2447 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2448 | return false; |
2449 | ||
b0c39dc6 | 2450 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2451 | } |
d828199e MT |
2452 | #endif |
2453 | ||
2454 | /* | |
2455 | * | |
b48aa97e MT |
2456 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2457 | * across virtual CPUs, the following condition is possible. | |
2458 | * Each numbered line represents an event visible to both | |
d828199e MT |
2459 | * CPUs at the next numbered event. |
2460 | * | |
2461 | * "timespecX" represents host monotonic time. "tscX" represents | |
2462 | * RDTSC value. | |
2463 | * | |
2464 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2465 | * | |
2466 | * 1. read timespec0,tsc0 | |
2467 | * 2. | timespec1 = timespec0 + N | |
2468 | * | tsc1 = tsc0 + M | |
2469 | * 3. transition to guest | transition to guest | |
2470 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2471 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2472 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2473 | * | |
2474 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2475 | * | |
2476 | * - ret0 < ret1 | |
2477 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2478 | * ... | |
2479 | * - 0 < N - M => M < N | |
2480 | * | |
2481 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2482 | * always the case (the difference between two distinct xtime instances | |
2483 | * might be smaller then the difference between corresponding TSC reads, | |
2484 | * when updating guest vcpus pvclock areas). | |
2485 | * | |
2486 | * To avoid that problem, do not allow visibility of distinct | |
2487 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2488 | * copy of host monotonic time values. Update that master copy | |
2489 | * in lockstep. | |
2490 | * | |
b48aa97e | 2491 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2492 | * |
2493 | */ | |
2494 | ||
2495 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2496 | { | |
2497 | #ifdef CONFIG_X86_64 | |
2498 | struct kvm_arch *ka = &kvm->arch; | |
2499 | int vclock_mode; | |
b48aa97e MT |
2500 | bool host_tsc_clocksource, vcpus_matched; |
2501 | ||
2502 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2503 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2504 | |
2505 | /* | |
2506 | * If the host uses TSC clock, then passthrough TSC as stable | |
2507 | * to the guest. | |
2508 | */ | |
b48aa97e | 2509 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2510 | &ka->master_kernel_ns, |
2511 | &ka->master_cycle_now); | |
2512 | ||
16a96021 | 2513 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2514 | && !ka->backwards_tsc_observed |
54750f2c | 2515 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2516 | |
d828199e MT |
2517 | if (ka->use_master_clock) |
2518 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2519 | ||
2520 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2521 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2522 | vcpus_matched); | |
d828199e MT |
2523 | #endif |
2524 | } | |
2525 | ||
2860c4b1 PB |
2526 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2527 | { | |
2528 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2529 | } | |
2530 | ||
2e762ff7 MT |
2531 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
2532 | { | |
2533 | #ifdef CONFIG_X86_64 | |
2534 | int i; | |
2535 | struct kvm_vcpu *vcpu; | |
2536 | struct kvm_arch *ka = &kvm->arch; | |
2537 | ||
2538 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2539 | kvm_make_mclock_inprogress_request(kvm); | |
2540 | /* no guest entries from this point */ | |
2541 | pvclock_update_vm_gtod_copy(kvm); | |
2542 | ||
2543 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 2544 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2545 | |
2546 | /* guest entries allowed */ | |
2547 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2548 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
2549 | |
2550 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2551 | #endif | |
2552 | } | |
2553 | ||
e891a32e | 2554 | u64 get_kvmclock_ns(struct kvm *kvm) |
108b249c | 2555 | { |
108b249c | 2556 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2557 | struct pvclock_vcpu_time_info hv_clock; |
e2c2206a | 2558 | u64 ret; |
108b249c | 2559 | |
8b953440 PB |
2560 | spin_lock(&ka->pvclock_gtod_sync_lock); |
2561 | if (!ka->use_master_clock) { | |
2562 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
8171cd68 | 2563 | return get_kvmclock_base_ns() + ka->kvmclock_offset; |
108b249c PB |
2564 | } |
2565 | ||
8b953440 PB |
2566 | hv_clock.tsc_timestamp = ka->master_cycle_now; |
2567 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
2568 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2569 | ||
e2c2206a WL |
2570 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2571 | get_cpu(); | |
2572 | ||
e70b57a6 WL |
2573 | if (__this_cpu_read(cpu_tsc_khz)) { |
2574 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, | |
2575 | &hv_clock.tsc_shift, | |
2576 | &hv_clock.tsc_to_system_mul); | |
2577 | ret = __pvclock_read_cycles(&hv_clock, rdtsc()); | |
2578 | } else | |
8171cd68 | 2579 | ret = get_kvmclock_base_ns() + ka->kvmclock_offset; |
e2c2206a WL |
2580 | |
2581 | put_cpu(); | |
2582 | ||
2583 | return ret; | |
108b249c PB |
2584 | } |
2585 | ||
0d6dd2ff PB |
2586 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v) |
2587 | { | |
2588 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
2589 | struct pvclock_vcpu_time_info guest_hv_clock; | |
2590 | ||
4e335d9e | 2591 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
0d6dd2ff PB |
2592 | &guest_hv_clock, sizeof(guest_hv_clock)))) |
2593 | return; | |
2594 | ||
2595 | /* This VCPU is paused, but it's legal for a guest to read another | |
2596 | * VCPU's kvmclock, so we really have to follow the specification where | |
2597 | * it says that version is odd if data is being modified, and even after | |
2598 | * it is consistent. | |
2599 | * | |
2600 | * Version field updates must be kept separate. This is because | |
2601 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
2602 | * writes within a string instruction are weakly ordered. So there | |
2603 | * are three writes overall. | |
2604 | * | |
2605 | * As a small optimization, only write the version field in the first | |
2606 | * and third write. The vcpu->pv_time cache is still valid, because the | |
2607 | * version field is the first in the struct. | |
2608 | */ | |
2609 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
2610 | ||
51c4b8bb LA |
2611 | if (guest_hv_clock.version & 1) |
2612 | ++guest_hv_clock.version; /* first time write, random junk */ | |
2613 | ||
0d6dd2ff | 2614 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
4e335d9e PB |
2615 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2616 | &vcpu->hv_clock, | |
2617 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2618 | |
2619 | smp_wmb(); | |
2620 | ||
2621 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
2622 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
2623 | ||
2624 | if (vcpu->pvclock_set_guest_stopped_request) { | |
2625 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
2626 | vcpu->pvclock_set_guest_stopped_request = false; | |
2627 | } | |
2628 | ||
2629 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
2630 | ||
4e335d9e PB |
2631 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2632 | &vcpu->hv_clock, | |
2633 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
2634 | |
2635 | smp_wmb(); | |
2636 | ||
2637 | vcpu->hv_clock.version++; | |
4e335d9e PB |
2638 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2639 | &vcpu->hv_clock, | |
2640 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2641 | } |
2642 | ||
34c238a1 | 2643 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 2644 | { |
78db6a50 | 2645 | unsigned long flags, tgt_tsc_khz; |
18068523 | 2646 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 2647 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 2648 | s64 kernel_ns; |
d828199e | 2649 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 2650 | u8 pvclock_flags; |
d828199e MT |
2651 | bool use_master_clock; |
2652 | ||
2653 | kernel_ns = 0; | |
2654 | host_tsc = 0; | |
18068523 | 2655 | |
d828199e MT |
2656 | /* |
2657 | * If the host uses TSC clock, then passthrough TSC as stable | |
2658 | * to the guest. | |
2659 | */ | |
2660 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2661 | use_master_clock = ka->use_master_clock; | |
2662 | if (use_master_clock) { | |
2663 | host_tsc = ka->master_cycle_now; | |
2664 | kernel_ns = ka->master_kernel_ns; | |
2665 | } | |
2666 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
2667 | |
2668 | /* Keep irq disabled to prevent changes to the clock */ | |
2669 | local_irq_save(flags); | |
78db6a50 PB |
2670 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2671 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2672 | local_irq_restore(flags); |
2673 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2674 | return 1; | |
2675 | } | |
d828199e | 2676 | if (!use_master_clock) { |
4ea1636b | 2677 | host_tsc = rdtsc(); |
8171cd68 | 2678 | kernel_ns = get_kvmclock_base_ns(); |
d828199e MT |
2679 | } |
2680 | ||
4ba76538 | 2681 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2682 | |
c285545f ZA |
2683 | /* |
2684 | * We may have to catch up the TSC to match elapsed wall clock | |
2685 | * time for two reasons, even if kvmclock is used. | |
2686 | * 1) CPU could have been running below the maximum TSC rate | |
2687 | * 2) Broken TSC compensation resets the base at each VCPU | |
2688 | * entry to avoid unknown leaps of TSC even when running | |
2689 | * again on the same CPU. This may cause apparent elapsed | |
2690 | * time to disappear, and the guest to stand still or run | |
2691 | * very slowly. | |
2692 | */ | |
2693 | if (vcpu->tsc_catchup) { | |
2694 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
2695 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 2696 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
2697 | tsc_timestamp = tsc; |
2698 | } | |
50d0a0f9 GH |
2699 | } |
2700 | ||
18068523 GOC |
2701 | local_irq_restore(flags); |
2702 | ||
0d6dd2ff | 2703 | /* With all the info we got, fill in the values */ |
18068523 | 2704 | |
78db6a50 PB |
2705 | if (kvm_has_tsc_control) |
2706 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); | |
2707 | ||
2708 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 2709 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
2710 | &vcpu->hv_clock.tsc_shift, |
2711 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 2712 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
2713 | } |
2714 | ||
1d5f066e | 2715 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 2716 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 2717 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 2718 | |
d828199e | 2719 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 2720 | pvclock_flags = 0; |
d828199e MT |
2721 | if (use_master_clock) |
2722 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
2723 | ||
78c0337a MT |
2724 | vcpu->hv_clock.flags = pvclock_flags; |
2725 | ||
095cf55d PB |
2726 | if (vcpu->pv_time_enabled) |
2727 | kvm_setup_pvclock_page(v); | |
2728 | if (v == kvm_get_vcpu(v->kvm, 0)) | |
2729 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); | |
8cfdc000 | 2730 | return 0; |
c8076604 GH |
2731 | } |
2732 | ||
0061d53d MT |
2733 | /* |
2734 | * kvmclock updates which are isolated to a given vcpu, such as | |
2735 | * vcpu->cpu migration, should not allow system_timestamp from | |
2736 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
2737 | * correction applies to one vcpu's system_timestamp but not | |
2738 | * the others. | |
2739 | * | |
2740 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
2741 | * We need to rate-limit these requests though, as they can |
2742 | * considerably slow guests that have a large number of vcpus. | |
2743 | * The time for a remote vcpu to update its kvmclock is bound | |
2744 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
2745 | */ |
2746 | ||
7e44e449 AJ |
2747 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
2748 | ||
2749 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
2750 | { |
2751 | int i; | |
7e44e449 AJ |
2752 | struct delayed_work *dwork = to_delayed_work(work); |
2753 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2754 | kvmclock_update_work); | |
2755 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
2756 | struct kvm_vcpu *vcpu; |
2757 | ||
2758 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 2759 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
2760 | kvm_vcpu_kick(vcpu); |
2761 | } | |
2762 | } | |
2763 | ||
7e44e449 AJ |
2764 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
2765 | { | |
2766 | struct kvm *kvm = v->kvm; | |
2767 | ||
105b21bb | 2768 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
2769 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
2770 | KVMCLOCK_UPDATE_DELAY); | |
2771 | } | |
2772 | ||
332967a3 AJ |
2773 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
2774 | ||
2775 | static void kvmclock_sync_fn(struct work_struct *work) | |
2776 | { | |
2777 | struct delayed_work *dwork = to_delayed_work(work); | |
2778 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2779 | kvmclock_sync_work); | |
2780 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
2781 | ||
630994b3 MT |
2782 | if (!kvmclock_periodic_sync) |
2783 | return; | |
2784 | ||
332967a3 AJ |
2785 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
2786 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
2787 | KVMCLOCK_SYNC_PERIOD); | |
2788 | } | |
2789 | ||
191c8137 BP |
2790 | /* |
2791 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
2792 | */ | |
2793 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
2794 | { | |
2795 | /* McStatusWrEn enabled? */ | |
23493d0a | 2796 | if (guest_cpuid_is_amd_or_hygon(vcpu)) |
191c8137 BP |
2797 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); |
2798 | ||
2799 | return false; | |
2800 | } | |
2801 | ||
9ffd986c | 2802 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2803 | { |
890ca9ae HY |
2804 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2805 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
2806 | u32 msr = msr_info->index; |
2807 | u64 data = msr_info->data; | |
890ca9ae | 2808 | |
15c4a640 | 2809 | switch (msr) { |
15c4a640 | 2810 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 2811 | vcpu->arch.mcg_status = data; |
15c4a640 | 2812 | break; |
c7ac679c | 2813 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
2814 | if (!(mcg_cap & MCG_CTL_P) && |
2815 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
2816 | return 1; |
2817 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 2818 | return 1; |
890ca9ae HY |
2819 | vcpu->arch.mcg_ctl = data; |
2820 | break; | |
2821 | default: | |
2822 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2823 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
2824 | u32 offset = array_index_nospec( |
2825 | msr - MSR_IA32_MC0_CTL, | |
2826 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
2827 | ||
114be429 AP |
2828 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
2829 | * some Linux kernels though clear bit 10 in bank 4 to | |
2830 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
2831 | * this to avoid an uncatched #GP in the guest | |
2832 | */ | |
890ca9ae | 2833 | if ((offset & 0x3) == 0 && |
114be429 | 2834 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 2835 | return -1; |
191c8137 BP |
2836 | |
2837 | /* MCi_STATUS */ | |
9ffd986c | 2838 | if (!msr_info->host_initiated && |
191c8137 BP |
2839 | (offset & 0x3) == 1 && data != 0) { |
2840 | if (!can_set_mci_status(vcpu)) | |
2841 | return -1; | |
2842 | } | |
2843 | ||
890ca9ae HY |
2844 | vcpu->arch.mce_banks[offset] = data; |
2845 | break; | |
2846 | } | |
2847 | return 1; | |
2848 | } | |
2849 | return 0; | |
2850 | } | |
2851 | ||
ffde22ac ES |
2852 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
2853 | { | |
2854 | struct kvm *kvm = vcpu->kvm; | |
2855 | int lm = is_long_mode(vcpu); | |
2856 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
2857 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
2858 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
2859 | : kvm->arch.xen_hvm_config.blob_size_32; | |
2860 | u32 page_num = data & ~PAGE_MASK; | |
2861 | u64 page_addr = data & PAGE_MASK; | |
2862 | u8 *page; | |
ffde22ac | 2863 | |
ffde22ac | 2864 | if (page_num >= blob_size) |
36385ccc ML |
2865 | return 1; |
2866 | ||
ff5c2c03 | 2867 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
36385ccc ML |
2868 | if (IS_ERR(page)) |
2869 | return PTR_ERR(page); | |
2870 | ||
2871 | if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) { | |
2872 | kfree(page); | |
2873 | return 1; | |
ff5c2c03 | 2874 | } |
36385ccc | 2875 | return 0; |
ffde22ac ES |
2876 | } |
2877 | ||
2635b5c4 VK |
2878 | static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) |
2879 | { | |
2880 | u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; | |
2881 | ||
2882 | return (vcpu->arch.apf.msr_en_val & mask) == mask; | |
2883 | } | |
2884 | ||
344d9588 GN |
2885 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
2886 | { | |
2887 | gpa_t gpa = data & ~0x3f; | |
2888 | ||
2635b5c4 VK |
2889 | /* Bits 4:5 are reserved, Should be zero */ |
2890 | if (data & 0x30) | |
344d9588 GN |
2891 | return 1; |
2892 | ||
66570e96 OU |
2893 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && |
2894 | (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) | |
2895 | return 1; | |
2896 | ||
2897 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && | |
2898 | (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) | |
2899 | return 1; | |
2900 | ||
9d3c447c | 2901 | if (!lapic_in_kernel(vcpu)) |
d831de17 | 2902 | return data ? 1 : 0; |
9d3c447c | 2903 | |
2635b5c4 | 2904 | vcpu->arch.apf.msr_en_val = data; |
344d9588 | 2905 | |
2635b5c4 | 2906 | if (!kvm_pv_async_pf_enabled(vcpu)) { |
344d9588 GN |
2907 | kvm_clear_async_pf_completion_queue(vcpu); |
2908 | kvm_async_pf_hash_reset(vcpu); | |
2909 | return 0; | |
2910 | } | |
2911 | ||
4e335d9e | 2912 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
68fd66f1 | 2913 | sizeof(u64))) |
344d9588 GN |
2914 | return 1; |
2915 | ||
6adba527 | 2916 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 2917 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
2635b5c4 | 2918 | |
344d9588 | 2919 | kvm_async_pf_wakeup_all(vcpu); |
2635b5c4 VK |
2920 | |
2921 | return 0; | |
2922 | } | |
2923 | ||
2924 | static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) | |
2925 | { | |
2926 | /* Bits 8-63 are reserved */ | |
2927 | if (data >> 8) | |
2928 | return 1; | |
2929 | ||
2930 | if (!lapic_in_kernel(vcpu)) | |
2931 | return 1; | |
2932 | ||
2933 | vcpu->arch.apf.msr_int_val = data; | |
2934 | ||
2935 | vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; | |
2936 | ||
344d9588 GN |
2937 | return 0; |
2938 | } | |
2939 | ||
12f9a48f GC |
2940 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2941 | { | |
0b79459b | 2942 | vcpu->arch.pv_time_enabled = false; |
49dedf0d | 2943 | vcpu->arch.time = 0; |
12f9a48f GC |
2944 | } |
2945 | ||
7780938c | 2946 | static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) |
f38a7b75 WL |
2947 | { |
2948 | ++vcpu->stat.tlb_flush; | |
7780938c | 2949 | kvm_x86_ops.tlb_flush_all(vcpu); |
f38a7b75 WL |
2950 | } |
2951 | ||
0baedd79 VK |
2952 | static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) |
2953 | { | |
2954 | ++vcpu->stat.tlb_flush; | |
2955 | kvm_x86_ops.tlb_flush_guest(vcpu); | |
2956 | } | |
2957 | ||
c9aaa895 GC |
2958 | static void record_steal_time(struct kvm_vcpu *vcpu) |
2959 | { | |
b0431382 BO |
2960 | struct kvm_host_map map; |
2961 | struct kvm_steal_time *st; | |
2962 | ||
c9aaa895 GC |
2963 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
2964 | return; | |
2965 | ||
b0431382 BO |
2966 | /* -EAGAIN is returned in atomic context so we can just return. */ |
2967 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, | |
2968 | &map, &vcpu->arch.st.cache, false)) | |
c9aaa895 GC |
2969 | return; |
2970 | ||
b0431382 BO |
2971 | st = map.hva + |
2972 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
2973 | ||
f38a7b75 WL |
2974 | /* |
2975 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
2976 | * expensive IPIs. | |
2977 | */ | |
66570e96 OU |
2978 | if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { |
2979 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, | |
2980 | st->preempted & KVM_VCPU_FLUSH_TLB); | |
2981 | if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB) | |
2982 | kvm_vcpu_flush_tlb_guest(vcpu); | |
2983 | } | |
0b9f6c46 | 2984 | |
a6bd811f | 2985 | vcpu->arch.st.preempted = 0; |
35f3fae1 | 2986 | |
b0431382 BO |
2987 | if (st->version & 1) |
2988 | st->version += 1; /* first time write, random junk */ | |
35f3fae1 | 2989 | |
b0431382 | 2990 | st->version += 1; |
35f3fae1 WL |
2991 | |
2992 | smp_wmb(); | |
2993 | ||
b0431382 | 2994 | st->steal += current->sched_info.run_delay - |
c54cdf14 LC |
2995 | vcpu->arch.st.last_steal; |
2996 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
35f3fae1 | 2997 | |
35f3fae1 WL |
2998 | smp_wmb(); |
2999 | ||
b0431382 | 3000 | st->version += 1; |
c9aaa895 | 3001 | |
b0431382 | 3002 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); |
c9aaa895 GC |
3003 | } |
3004 | ||
8fe8ab46 | 3005 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3006 | { |
5753785f | 3007 | bool pr = false; |
8fe8ab46 WA |
3008 | u32 msr = msr_info->index; |
3009 | u64 data = msr_info->data; | |
5753785f | 3010 | |
15c4a640 | 3011 | switch (msr) { |
2e32b719 | 3012 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
3013 | case MSR_IA32_UCODE_WRITE: |
3014 | case MSR_VM_HSAVE_PA: | |
3015 | case MSR_AMD64_PATCH_LOADER: | |
3016 | case MSR_AMD64_BU_CFG2: | |
405a353a | 3017 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3018 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
3019 | break; |
3020 | ||
518e7b94 WL |
3021 | case MSR_IA32_UCODE_REV: |
3022 | if (msr_info->host_initiated) | |
3023 | vcpu->arch.microcode_version = data; | |
3024 | break; | |
0cf9135b SC |
3025 | case MSR_IA32_ARCH_CAPABILITIES: |
3026 | if (!msr_info->host_initiated) | |
3027 | return 1; | |
3028 | vcpu->arch.arch_capabilities = data; | |
3029 | break; | |
d574c539 VK |
3030 | case MSR_IA32_PERF_CAPABILITIES: { |
3031 | struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; | |
3032 | ||
3033 | if (!msr_info->host_initiated) | |
3034 | return 1; | |
3035 | if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) | |
3036 | return 1; | |
3037 | if (data & ~msr_ent.data) | |
3038 | return 1; | |
3039 | ||
3040 | vcpu->arch.perf_capabilities = data; | |
3041 | ||
3042 | return 0; | |
3043 | } | |
15c4a640 | 3044 | case MSR_EFER: |
11988499 | 3045 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
3046 | case MSR_K7_HWCR: |
3047 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 3048 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 3049 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
3050 | |
3051 | /* Handle McStatusWrEn */ | |
3052 | if (data == BIT_ULL(18)) { | |
3053 | vcpu->arch.msr_hwcr = data; | |
3054 | } else if (data != 0) { | |
a737f256 CD |
3055 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
3056 | data); | |
8f1589d9 AP |
3057 | return 1; |
3058 | } | |
15c4a640 | 3059 | break; |
f7c6d140 AP |
3060 | case MSR_FAM10H_MMIO_CONF_BASE: |
3061 | if (data != 0) { | |
a737f256 CD |
3062 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
3063 | "0x%llx\n", data); | |
f7c6d140 AP |
3064 | return 1; |
3065 | } | |
15c4a640 | 3066 | break; |
b5e2fec0 AG |
3067 | case MSR_IA32_DEBUGCTLMSR: |
3068 | if (!data) { | |
3069 | /* We support the non-activated case already */ | |
3070 | break; | |
3071 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
3072 | /* Values other than LBR and BTF are vendor-specific, | |
3073 | thus reserved and should throw a #GP */ | |
3074 | return 1; | |
2cdef91c PG |
3075 | } else if (report_ignored_msrs) |
3076 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
3077 | __func__, data); | |
b5e2fec0 | 3078 | break; |
9ba075a6 | 3079 | case 0x200 ... 0x2ff: |
ff53604b | 3080 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 3081 | case MSR_IA32_APICBASE: |
58cb628d | 3082 | return kvm_set_apic_base(vcpu, msr_info); |
bf10bd0b | 3083 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
0105d1a5 | 3084 | return kvm_x2apic_msr_write(vcpu, msr, data); |
a3e06bbe LJ |
3085 | case MSR_IA32_TSCDEADLINE: |
3086 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
3087 | break; | |
ba904635 | 3088 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 3089 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 3090 | if (!msr_info->host_initiated) { |
d913b904 | 3091 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 3092 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
3093 | } |
3094 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
3095 | } | |
3096 | break; | |
15c4a640 | 3097 | case MSR_IA32_MISC_ENABLE: |
511a8556 WL |
3098 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
3099 | ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { | |
3100 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) | |
3101 | return 1; | |
3102 | vcpu->arch.ia32_misc_enable_msr = data; | |
aedbaf4f | 3103 | kvm_update_cpuid_runtime(vcpu); |
511a8556 WL |
3104 | } else { |
3105 | vcpu->arch.ia32_misc_enable_msr = data; | |
3106 | } | |
15c4a640 | 3107 | break; |
64d60670 PB |
3108 | case MSR_IA32_SMBASE: |
3109 | if (!msr_info->host_initiated) | |
3110 | return 1; | |
3111 | vcpu->arch.smbase = data; | |
3112 | break; | |
73f624f4 PB |
3113 | case MSR_IA32_POWER_CTL: |
3114 | vcpu->arch.msr_ia32_power_ctl = data; | |
3115 | break; | |
dd259935 | 3116 | case MSR_IA32_TSC: |
0c899c25 PB |
3117 | if (msr_info->host_initiated) { |
3118 | kvm_synchronize_tsc(vcpu, data); | |
3119 | } else { | |
3120 | u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; | |
3121 | adjust_tsc_offset_guest(vcpu, adj); | |
3122 | vcpu->arch.ia32_tsc_adjust_msr += adj; | |
3123 | } | |
dd259935 | 3124 | break; |
864e2ab2 AL |
3125 | case MSR_IA32_XSS: |
3126 | if (!msr_info->host_initiated && | |
3127 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3128 | return 1; | |
3129 | /* | |
a1bead2a SC |
3130 | * KVM supports exposing PT to the guest, but does not support |
3131 | * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than | |
3132 | * XSAVES/XRSTORS to save/restore PT MSRs. | |
864e2ab2 | 3133 | */ |
408e9a31 | 3134 | if (data & ~supported_xss) |
864e2ab2 AL |
3135 | return 1; |
3136 | vcpu->arch.ia32_xss = data; | |
3137 | break; | |
52797bf9 LA |
3138 | case MSR_SMI_COUNT: |
3139 | if (!msr_info->host_initiated) | |
3140 | return 1; | |
3141 | vcpu->arch.smi_count = data; | |
3142 | break; | |
11c6bffa | 3143 | case MSR_KVM_WALL_CLOCK_NEW: |
66570e96 OU |
3144 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3145 | return 1; | |
3146 | ||
3147 | kvm_write_wall_clock(vcpu->kvm, data); | |
3148 | break; | |
18068523 | 3149 | case MSR_KVM_WALL_CLOCK: |
66570e96 OU |
3150 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3151 | return 1; | |
3152 | ||
18068523 GOC |
3153 | kvm_write_wall_clock(vcpu->kvm, data); |
3154 | break; | |
11c6bffa | 3155 | case MSR_KVM_SYSTEM_TIME_NEW: |
66570e96 OU |
3156 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3157 | return 1; | |
3158 | ||
5b9bb0eb OU |
3159 | kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); |
3160 | break; | |
3161 | case MSR_KVM_SYSTEM_TIME: | |
66570e96 OU |
3162 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3163 | return 1; | |
3164 | ||
3165 | kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); | |
18068523 | 3166 | break; |
344d9588 | 3167 | case MSR_KVM_ASYNC_PF_EN: |
66570e96 OU |
3168 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3169 | return 1; | |
3170 | ||
344d9588 GN |
3171 | if (kvm_pv_enable_async_pf(vcpu, data)) |
3172 | return 1; | |
3173 | break; | |
2635b5c4 | 3174 | case MSR_KVM_ASYNC_PF_INT: |
66570e96 OU |
3175 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3176 | return 1; | |
3177 | ||
2635b5c4 VK |
3178 | if (kvm_pv_enable_async_pf_int(vcpu, data)) |
3179 | return 1; | |
3180 | break; | |
557a961a | 3181 | case MSR_KVM_ASYNC_PF_ACK: |
66570e96 OU |
3182 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3183 | return 1; | |
557a961a VK |
3184 | if (data & 0x1) { |
3185 | vcpu->arch.apf.pageready_pending = false; | |
3186 | kvm_check_async_pf_completion(vcpu); | |
3187 | } | |
3188 | break; | |
c9aaa895 | 3189 | case MSR_KVM_STEAL_TIME: |
66570e96 OU |
3190 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3191 | return 1; | |
c9aaa895 GC |
3192 | |
3193 | if (unlikely(!sched_info_on())) | |
3194 | return 1; | |
3195 | ||
3196 | if (data & KVM_STEAL_RESERVED_MASK) | |
3197 | return 1; | |
3198 | ||
c9aaa895 GC |
3199 | vcpu->arch.st.msr_val = data; |
3200 | ||
3201 | if (!(data & KVM_MSR_ENABLED)) | |
3202 | break; | |
3203 | ||
c9aaa895 GC |
3204 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
3205 | ||
3206 | break; | |
ae7a2a3f | 3207 | case MSR_KVM_PV_EOI_EN: |
66570e96 OU |
3208 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3209 | return 1; | |
3210 | ||
72bbf935 | 3211 | if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
3212 | return 1; |
3213 | break; | |
c9aaa895 | 3214 | |
2d5ba19b | 3215 | case MSR_KVM_POLL_CONTROL: |
66570e96 OU |
3216 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3217 | return 1; | |
3218 | ||
2d5ba19b MT |
3219 | /* only enable bit supported */ |
3220 | if (data & (-1ULL << 1)) | |
3221 | return 1; | |
3222 | ||
3223 | vcpu->arch.msr_kvm_poll_control = data; | |
3224 | break; | |
3225 | ||
890ca9ae HY |
3226 | case MSR_IA32_MCG_CTL: |
3227 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3228 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 3229 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 3230 | |
6912ac32 WH |
3231 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
3232 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
df561f66 GS |
3233 | pr = true; |
3234 | fallthrough; | |
6912ac32 WH |
3235 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3236 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3237 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3238 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
3239 | |
3240 | if (pr || data != 0) | |
a737f256 CD |
3241 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
3242 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 3243 | break; |
84e0cefa JS |
3244 | case MSR_K7_CLK_CTL: |
3245 | /* | |
3246 | * Ignore all writes to this no longer documented MSR. | |
3247 | * Writes are only relevant for old K7 processors, | |
3248 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 3249 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
3250 | * affected processor models on the command line, hence |
3251 | * the need to ignore the workaround. | |
3252 | */ | |
3253 | break; | |
55cd8e5a | 3254 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3255 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3256 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3257 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3258 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3259 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3260 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3261 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3262 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
3263 | return kvm_hv_set_msr_common(vcpu, msr, data, |
3264 | msr_info->host_initiated); | |
91c9c3ed | 3265 | case MSR_IA32_BBL_CR_CTL3: |
3266 | /* Drop writes to this legacy MSR -- see rdmsr | |
3267 | * counterpart for further detail. | |
3268 | */ | |
fab0aa3b EM |
3269 | if (report_ignored_msrs) |
3270 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
3271 | msr, data); | |
91c9c3ed | 3272 | break; |
2b036c6b | 3273 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3274 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3275 | return 1; |
3276 | vcpu->arch.osvw.length = data; | |
3277 | break; | |
3278 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3279 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3280 | return 1; |
3281 | vcpu->arch.osvw.status = data; | |
3282 | break; | |
db2336a8 KH |
3283 | case MSR_PLATFORM_INFO: |
3284 | if (!msr_info->host_initiated || | |
db2336a8 KH |
3285 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
3286 | cpuid_fault_enabled(vcpu))) | |
3287 | return 1; | |
3288 | vcpu->arch.msr_platform_info = data; | |
3289 | break; | |
3290 | case MSR_MISC_FEATURES_ENABLES: | |
3291 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
3292 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
3293 | !supports_cpuid_fault(vcpu))) | |
3294 | return 1; | |
3295 | vcpu->arch.msr_misc_features_enables = data; | |
3296 | break; | |
15c4a640 | 3297 | default: |
ffde22ac ES |
3298 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
3299 | return xen_hvm_config(vcpu, data); | |
c6702c9d | 3300 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3301 | return kvm_pmu_set_msr(vcpu, msr_info); |
6abe9c13 | 3302 | return KVM_MSR_RET_INVALID; |
15c4a640 CO |
3303 | } |
3304 | return 0; | |
3305 | } | |
3306 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
3307 | ||
44883f01 | 3308 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
3309 | { |
3310 | u64 data; | |
890ca9ae HY |
3311 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3312 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
3313 | |
3314 | switch (msr) { | |
15c4a640 CO |
3315 | case MSR_IA32_P5_MC_ADDR: |
3316 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
3317 | data = 0; |
3318 | break; | |
15c4a640 | 3319 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
3320 | data = vcpu->arch.mcg_cap; |
3321 | break; | |
c7ac679c | 3322 | case MSR_IA32_MCG_CTL: |
44883f01 | 3323 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
3324 | return 1; |
3325 | data = vcpu->arch.mcg_ctl; | |
3326 | break; | |
3327 | case MSR_IA32_MCG_STATUS: | |
3328 | data = vcpu->arch.mcg_status; | |
3329 | break; | |
3330 | default: | |
3331 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3332 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3333 | u32 offset = array_index_nospec( |
3334 | msr - MSR_IA32_MC0_CTL, | |
3335 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3336 | ||
890ca9ae HY |
3337 | data = vcpu->arch.mce_banks[offset]; |
3338 | break; | |
3339 | } | |
3340 | return 1; | |
3341 | } | |
3342 | *pdata = data; | |
3343 | return 0; | |
3344 | } | |
3345 | ||
609e36d3 | 3346 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 3347 | { |
609e36d3 | 3348 | switch (msr_info->index) { |
890ca9ae | 3349 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 3350 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
3351 | case MSR_IA32_DEBUGCTLMSR: |
3352 | case MSR_IA32_LASTBRANCHFROMIP: | |
3353 | case MSR_IA32_LASTBRANCHTOIP: | |
3354 | case MSR_IA32_LASTINTFROMIP: | |
3355 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd | 3356 | case MSR_K8_SYSCFG: |
3afb1121 PB |
3357 | case MSR_K8_TSEG_ADDR: |
3358 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 3359 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 3360 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 3361 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 3362 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 3363 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 3364 | case MSR_IA32_PERF_CTL: |
405a353a | 3365 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3366 | case MSR_F15H_EX_CFG: |
2ca1a06a VS |
3367 | /* |
3368 | * Intel Sandy Bridge CPUs must support the RAPL (running average power | |
3369 | * limit) MSRs. Just return 0, as we do not want to expose the host | |
3370 | * data here. Do not conditionalize this on CPUID, as KVM does not do | |
3371 | * so for existing CPU-specific MSRs. | |
3372 | */ | |
3373 | case MSR_RAPL_POWER_UNIT: | |
3374 | case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ | |
3375 | case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ | |
3376 | case MSR_PKG_ENERGY_STATUS: /* Total package */ | |
3377 | case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ | |
609e36d3 | 3378 | msr_info->data = 0; |
15c4a640 | 3379 | break; |
c51eb52b | 3380 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
6912ac32 WH |
3381 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3382 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
3383 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
3384 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3385 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3386 | return kvm_pmu_get_msr(vcpu, msr_info); |
609e36d3 | 3387 | msr_info->data = 0; |
5753785f | 3388 | break; |
742bc670 | 3389 | case MSR_IA32_UCODE_REV: |
518e7b94 | 3390 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 3391 | break; |
0cf9135b SC |
3392 | case MSR_IA32_ARCH_CAPABILITIES: |
3393 | if (!msr_info->host_initiated && | |
3394 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3395 | return 1; | |
3396 | msr_info->data = vcpu->arch.arch_capabilities; | |
3397 | break; | |
d574c539 VK |
3398 | case MSR_IA32_PERF_CAPABILITIES: |
3399 | if (!msr_info->host_initiated && | |
3400 | !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) | |
3401 | return 1; | |
3402 | msr_info->data = vcpu->arch.perf_capabilities; | |
3403 | break; | |
73f624f4 PB |
3404 | case MSR_IA32_POWER_CTL: |
3405 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
3406 | break; | |
cc5b54dd ML |
3407 | case MSR_IA32_TSC: { |
3408 | /* | |
3409 | * Intel SDM states that MSR_IA32_TSC read adds the TSC offset | |
3410 | * even when not intercepted. AMD manual doesn't explicitly | |
3411 | * state this but appears to behave the same. | |
3412 | * | |
ee6fa053 | 3413 | * On userspace reads and writes, however, we unconditionally |
c0623f5e | 3414 | * return L1's TSC value to ensure backwards-compatible |
ee6fa053 | 3415 | * behavior for migration. |
cc5b54dd ML |
3416 | */ |
3417 | u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset : | |
3418 | vcpu->arch.tsc_offset; | |
3419 | ||
3420 | msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset; | |
dd259935 | 3421 | break; |
cc5b54dd | 3422 | } |
9ba075a6 | 3423 | case MSR_MTRRcap: |
9ba075a6 | 3424 | case 0x200 ... 0x2ff: |
ff53604b | 3425 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 3426 | case 0xcd: /* fsb frequency */ |
609e36d3 | 3427 | msr_info->data = 3; |
15c4a640 | 3428 | break; |
7b914098 JS |
3429 | /* |
3430 | * MSR_EBC_FREQUENCY_ID | |
3431 | * Conservative value valid for even the basic CPU models. | |
3432 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
3433 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
3434 | * and 266MHz for model 3, or 4. Set Core Clock | |
3435 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
3436 | * 31:24) even though these are only valid for CPU | |
3437 | * models > 2, however guests may end up dividing or | |
3438 | * multiplying by zero otherwise. | |
3439 | */ | |
3440 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 3441 | msr_info->data = 1 << 24; |
7b914098 | 3442 | break; |
15c4a640 | 3443 | case MSR_IA32_APICBASE: |
609e36d3 | 3444 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 3445 | break; |
bf10bd0b | 3446 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
609e36d3 | 3447 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
a3e06bbe | 3448 | case MSR_IA32_TSCDEADLINE: |
609e36d3 | 3449 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 3450 | break; |
ba904635 | 3451 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 3452 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 3453 | break; |
15c4a640 | 3454 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 3455 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 3456 | break; |
64d60670 PB |
3457 | case MSR_IA32_SMBASE: |
3458 | if (!msr_info->host_initiated) | |
3459 | return 1; | |
3460 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 3461 | break; |
52797bf9 LA |
3462 | case MSR_SMI_COUNT: |
3463 | msr_info->data = vcpu->arch.smi_count; | |
3464 | break; | |
847f0ad8 AG |
3465 | case MSR_IA32_PERF_STATUS: |
3466 | /* TSC increment by tick */ | |
609e36d3 | 3467 | msr_info->data = 1000ULL; |
847f0ad8 | 3468 | /* CPU multiplier */ |
b0996ae4 | 3469 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 3470 | break; |
15c4a640 | 3471 | case MSR_EFER: |
609e36d3 | 3472 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 3473 | break; |
18068523 | 3474 | case MSR_KVM_WALL_CLOCK: |
1930e5dd OU |
3475 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3476 | return 1; | |
3477 | ||
3478 | msr_info->data = vcpu->kvm->arch.wall_clock; | |
3479 | break; | |
11c6bffa | 3480 | case MSR_KVM_WALL_CLOCK_NEW: |
1930e5dd OU |
3481 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3482 | return 1; | |
3483 | ||
609e36d3 | 3484 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
3485 | break; |
3486 | case MSR_KVM_SYSTEM_TIME: | |
1930e5dd OU |
3487 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3488 | return 1; | |
3489 | ||
3490 | msr_info->data = vcpu->arch.time; | |
3491 | break; | |
11c6bffa | 3492 | case MSR_KVM_SYSTEM_TIME_NEW: |
1930e5dd OU |
3493 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3494 | return 1; | |
3495 | ||
609e36d3 | 3496 | msr_info->data = vcpu->arch.time; |
18068523 | 3497 | break; |
344d9588 | 3498 | case MSR_KVM_ASYNC_PF_EN: |
1930e5dd OU |
3499 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3500 | return 1; | |
3501 | ||
2635b5c4 VK |
3502 | msr_info->data = vcpu->arch.apf.msr_en_val; |
3503 | break; | |
3504 | case MSR_KVM_ASYNC_PF_INT: | |
1930e5dd OU |
3505 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3506 | return 1; | |
3507 | ||
2635b5c4 | 3508 | msr_info->data = vcpu->arch.apf.msr_int_val; |
344d9588 | 3509 | break; |
557a961a | 3510 | case MSR_KVM_ASYNC_PF_ACK: |
1930e5dd OU |
3511 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3512 | return 1; | |
3513 | ||
557a961a VK |
3514 | msr_info->data = 0; |
3515 | break; | |
c9aaa895 | 3516 | case MSR_KVM_STEAL_TIME: |
1930e5dd OU |
3517 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3518 | return 1; | |
3519 | ||
609e36d3 | 3520 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 3521 | break; |
1d92128f | 3522 | case MSR_KVM_PV_EOI_EN: |
1930e5dd OU |
3523 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3524 | return 1; | |
3525 | ||
609e36d3 | 3526 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 3527 | break; |
2d5ba19b | 3528 | case MSR_KVM_POLL_CONTROL: |
1930e5dd OU |
3529 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3530 | return 1; | |
3531 | ||
2d5ba19b MT |
3532 | msr_info->data = vcpu->arch.msr_kvm_poll_control; |
3533 | break; | |
890ca9ae HY |
3534 | case MSR_IA32_P5_MC_ADDR: |
3535 | case MSR_IA32_P5_MC_TYPE: | |
3536 | case MSR_IA32_MCG_CAP: | |
3537 | case MSR_IA32_MCG_CTL: | |
3538 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3539 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
3540 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
3541 | msr_info->host_initiated); | |
864e2ab2 AL |
3542 | case MSR_IA32_XSS: |
3543 | if (!msr_info->host_initiated && | |
3544 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3545 | return 1; | |
3546 | msr_info->data = vcpu->arch.ia32_xss; | |
3547 | break; | |
84e0cefa JS |
3548 | case MSR_K7_CLK_CTL: |
3549 | /* | |
3550 | * Provide expected ramp-up count for K7. All other | |
3551 | * are set to zero, indicating minimum divisors for | |
3552 | * every field. | |
3553 | * | |
3554 | * This prevents guest kernels on AMD host with CPU | |
3555 | * type 6, model 8 and higher from exploding due to | |
3556 | * the rdmsr failing. | |
3557 | */ | |
609e36d3 | 3558 | msr_info->data = 0x20000000; |
84e0cefa | 3559 | break; |
55cd8e5a | 3560 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3561 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3562 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3563 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3564 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3565 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3566 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3567 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3568 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 3569 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
3570 | msr_info->index, &msr_info->data, |
3571 | msr_info->host_initiated); | |
91c9c3ed | 3572 | case MSR_IA32_BBL_CR_CTL3: |
3573 | /* This legacy MSR exists but isn't fully documented in current | |
3574 | * silicon. It is however accessed by winxp in very narrow | |
3575 | * scenarios where it sets bit #19, itself documented as | |
3576 | * a "reserved" bit. Best effort attempt to source coherent | |
3577 | * read data here should the balance of the register be | |
3578 | * interpreted by the guest: | |
3579 | * | |
3580 | * L2 cache control register 3: 64GB range, 256KB size, | |
3581 | * enabled, latency 0x1, configured | |
3582 | */ | |
609e36d3 | 3583 | msr_info->data = 0xbe702111; |
91c9c3ed | 3584 | break; |
2b036c6b | 3585 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3586 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3587 | return 1; |
609e36d3 | 3588 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
3589 | break; |
3590 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3591 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3592 | return 1; |
609e36d3 | 3593 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 3594 | break; |
db2336a8 | 3595 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
3596 | if (!msr_info->host_initiated && |
3597 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
3598 | return 1; | |
db2336a8 KH |
3599 | msr_info->data = vcpu->arch.msr_platform_info; |
3600 | break; | |
3601 | case MSR_MISC_FEATURES_ENABLES: | |
3602 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
3603 | break; | |
191c8137 BP |
3604 | case MSR_K7_HWCR: |
3605 | msr_info->data = vcpu->arch.msr_hwcr; | |
3606 | break; | |
15c4a640 | 3607 | default: |
c6702c9d | 3608 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3609 | return kvm_pmu_get_msr(vcpu, msr_info); |
6abe9c13 | 3610 | return KVM_MSR_RET_INVALID; |
15c4a640 | 3611 | } |
15c4a640 CO |
3612 | return 0; |
3613 | } | |
3614 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
3615 | ||
313a3dc7 CO |
3616 | /* |
3617 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
3618 | * | |
3619 | * @return number of msrs set successfully. | |
3620 | */ | |
3621 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
3622 | struct kvm_msr_entry *entries, | |
3623 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3624 | unsigned index, u64 *data)) | |
3625 | { | |
801e459a | 3626 | int i; |
313a3dc7 | 3627 | |
313a3dc7 CO |
3628 | for (i = 0; i < msrs->nmsrs; ++i) |
3629 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
3630 | break; | |
3631 | ||
313a3dc7 CO |
3632 | return i; |
3633 | } | |
3634 | ||
3635 | /* | |
3636 | * Read or write a bunch of msrs. Parameters are user addresses. | |
3637 | * | |
3638 | * @return number of msrs set successfully. | |
3639 | */ | |
3640 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
3641 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3642 | unsigned index, u64 *data), | |
3643 | int writeback) | |
3644 | { | |
3645 | struct kvm_msrs msrs; | |
3646 | struct kvm_msr_entry *entries; | |
3647 | int r, n; | |
3648 | unsigned size; | |
3649 | ||
3650 | r = -EFAULT; | |
0e96f31e | 3651 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
3652 | goto out; |
3653 | ||
3654 | r = -E2BIG; | |
3655 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
3656 | goto out; | |
3657 | ||
313a3dc7 | 3658 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
3659 | entries = memdup_user(user_msrs->entries, size); |
3660 | if (IS_ERR(entries)) { | |
3661 | r = PTR_ERR(entries); | |
313a3dc7 | 3662 | goto out; |
ff5c2c03 | 3663 | } |
313a3dc7 CO |
3664 | |
3665 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
3666 | if (r < 0) | |
3667 | goto out_free; | |
3668 | ||
3669 | r = -EFAULT; | |
3670 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
3671 | goto out_free; | |
3672 | ||
3673 | r = n; | |
3674 | ||
3675 | out_free: | |
7a73c028 | 3676 | kfree(entries); |
313a3dc7 CO |
3677 | out: |
3678 | return r; | |
3679 | } | |
3680 | ||
4d5422ce WL |
3681 | static inline bool kvm_can_mwait_in_guest(void) |
3682 | { | |
3683 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
3684 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
3685 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
3686 | } |
3687 | ||
c21d54f0 VK |
3688 | static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, |
3689 | struct kvm_cpuid2 __user *cpuid_arg) | |
3690 | { | |
3691 | struct kvm_cpuid2 cpuid; | |
3692 | int r; | |
3693 | ||
3694 | r = -EFAULT; | |
3695 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
3696 | return r; | |
3697 | ||
3698 | r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
3699 | if (r) | |
3700 | return r; | |
3701 | ||
3702 | r = -EFAULT; | |
3703 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
3704 | return r; | |
3705 | ||
3706 | return 0; | |
3707 | } | |
3708 | ||
784aa3d7 | 3709 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 3710 | { |
4d5422ce | 3711 | int r = 0; |
018d00d2 ZX |
3712 | |
3713 | switch (ext) { | |
3714 | case KVM_CAP_IRQCHIP: | |
3715 | case KVM_CAP_HLT: | |
3716 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 3717 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 3718 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 3719 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 3720 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 3721 | case KVM_CAP_PIT: |
a28e4f5a | 3722 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 3723 | case KVM_CAP_MP_STATE: |
ed848624 | 3724 | case KVM_CAP_SYNC_MMU: |
a355c85c | 3725 | case KVM_CAP_USER_NMI: |
52d939a0 | 3726 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 3727 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 3728 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 3729 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 3730 | case KVM_CAP_PIT2: |
e9f42757 | 3731 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 3732 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 3733 | case KVM_CAP_XEN_HVM: |
3cfc3092 | 3734 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 3735 | case KVM_CAP_HYPERV: |
10388a07 | 3736 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 3737 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 3738 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 3739 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 3740 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 3741 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 3742 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 3743 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 3744 | case KVM_CAP_HYPERV_CPUID: |
c21d54f0 | 3745 | case KVM_CAP_SYS_HYPERV_CPUID: |
ab9f4ecb | 3746 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 3747 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 3748 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 3749 | case KVM_CAP_XSAVE: |
344d9588 | 3750 | case KVM_CAP_ASYNC_PF: |
72de5fa4 | 3751 | case KVM_CAP_ASYNC_PF_INT: |
92a1f12d | 3752 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 3753 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 3754 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 3755 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 3756 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 3757 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 3758 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 3759 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 3760 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 3761 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 3762 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 3763 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 3764 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 3765 | case KVM_CAP_EXCEPTION_PAYLOAD: |
b9b2782c | 3766 | case KVM_CAP_SET_GUEST_DEBUG: |
1aa561b1 | 3767 | case KVM_CAP_LAST_CPU: |
1ae09954 | 3768 | case KVM_CAP_X86_USER_SPACE_MSR: |
1a155254 | 3769 | case KVM_CAP_X86_MSR_FILTER: |
66570e96 | 3770 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
018d00d2 ZX |
3771 | r = 1; |
3772 | break; | |
01643c51 KH |
3773 | case KVM_CAP_SYNC_REGS: |
3774 | r = KVM_SYNC_X86_VALID_FIELDS; | |
3775 | break; | |
e3fd9a93 PB |
3776 | case KVM_CAP_ADJUST_CLOCK: |
3777 | r = KVM_CLOCK_TSC_STABLE; | |
3778 | break; | |
4d5422ce | 3779 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
3780 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
3781 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
3782 | if(kvm_can_mwait_in_guest()) |
3783 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 3784 | break; |
6d396b55 PB |
3785 | case KVM_CAP_X86_SMM: |
3786 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
3787 | * and SMM handlers might indeed rely on 4G segment limits, | |
3788 | * so do not report SMM to be available if real mode is | |
3789 | * emulated via vm86 mode. Still, do not go to great lengths | |
3790 | * to avoid userspace's usage of the feature, because it is a | |
3791 | * fringe case that is not enabled except via specific settings | |
3792 | * of the module parameters. | |
3793 | */ | |
5719455f | 3794 | r = kvm_x86_ops.has_emulated_msr(kvm, MSR_IA32_SMBASE); |
6d396b55 | 3795 | break; |
774ead3a | 3796 | case KVM_CAP_VAPIC: |
afaf0b2f | 3797 | r = !kvm_x86_ops.cpu_has_accelerated_tpr(); |
774ead3a | 3798 | break; |
f725230a | 3799 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
3800 | r = KVM_SOFT_MAX_VCPUS; |
3801 | break; | |
3802 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
3803 | r = KVM_MAX_VCPUS; |
3804 | break; | |
a86cb413 TH |
3805 | case KVM_CAP_MAX_VCPU_ID: |
3806 | r = KVM_MAX_VCPU_ID; | |
3807 | break; | |
a68a6a72 MT |
3808 | case KVM_CAP_PV_MMU: /* obsolete */ |
3809 | r = 0; | |
2f333bcb | 3810 | break; |
890ca9ae HY |
3811 | case KVM_CAP_MCE: |
3812 | r = KVM_MAX_MCE_BANKS; | |
3813 | break; | |
2d5b5a66 | 3814 | case KVM_CAP_XCRS: |
d366bf7e | 3815 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 3816 | break; |
92a1f12d JR |
3817 | case KVM_CAP_TSC_CONTROL: |
3818 | r = kvm_has_tsc_control; | |
3819 | break; | |
37131313 RK |
3820 | case KVM_CAP_X2APIC_API: |
3821 | r = KVM_X2APIC_API_VALID_FLAGS; | |
3822 | break; | |
8fcc4b59 | 3823 | case KVM_CAP_NESTED_STATE: |
33b22172 PB |
3824 | r = kvm_x86_ops.nested_ops->get_state ? |
3825 | kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; | |
8fcc4b59 | 3826 | break; |
344c6c80 | 3827 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 3828 | r = kvm_x86_ops.enable_direct_tlbflush != NULL; |
5a0165f6 VK |
3829 | break; |
3830 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
33b22172 | 3831 | r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; |
344c6c80 | 3832 | break; |
3edd6839 MG |
3833 | case KVM_CAP_SMALLER_MAXPHYADDR: |
3834 | r = (int) allow_smaller_maxphyaddr; | |
3835 | break; | |
004a0124 AJ |
3836 | case KVM_CAP_STEAL_TIME: |
3837 | r = sched_info_on(); | |
3838 | break; | |
018d00d2 | 3839 | default: |
018d00d2 ZX |
3840 | break; |
3841 | } | |
3842 | return r; | |
3843 | ||
3844 | } | |
3845 | ||
043405e1 CO |
3846 | long kvm_arch_dev_ioctl(struct file *filp, |
3847 | unsigned int ioctl, unsigned long arg) | |
3848 | { | |
3849 | void __user *argp = (void __user *)arg; | |
3850 | long r; | |
3851 | ||
3852 | switch (ioctl) { | |
3853 | case KVM_GET_MSR_INDEX_LIST: { | |
3854 | struct kvm_msr_list __user *user_msr_list = argp; | |
3855 | struct kvm_msr_list msr_list; | |
3856 | unsigned n; | |
3857 | ||
3858 | r = -EFAULT; | |
0e96f31e | 3859 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
3860 | goto out; |
3861 | n = msr_list.nmsrs; | |
62ef68bb | 3862 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 3863 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
3864 | goto out; |
3865 | r = -E2BIG; | |
e125e7b6 | 3866 | if (n < msr_list.nmsrs) |
043405e1 CO |
3867 | goto out; |
3868 | r = -EFAULT; | |
3869 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
3870 | num_msrs_to_save * sizeof(u32))) | |
3871 | goto out; | |
e125e7b6 | 3872 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 3873 | &emulated_msrs, |
62ef68bb | 3874 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
3875 | goto out; |
3876 | r = 0; | |
3877 | break; | |
3878 | } | |
9c15bb1d BP |
3879 | case KVM_GET_SUPPORTED_CPUID: |
3880 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
3881 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
3882 | struct kvm_cpuid2 cpuid; | |
3883 | ||
3884 | r = -EFAULT; | |
0e96f31e | 3885 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 3886 | goto out; |
9c15bb1d BP |
3887 | |
3888 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
3889 | ioctl); | |
674eea0f AK |
3890 | if (r) |
3891 | goto out; | |
3892 | ||
3893 | r = -EFAULT; | |
0e96f31e | 3894 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
3895 | goto out; |
3896 | r = 0; | |
3897 | break; | |
3898 | } | |
cf6c26ec | 3899 | case KVM_X86_GET_MCE_CAP_SUPPORTED: |
890ca9ae | 3900 | r = -EFAULT; |
c45dcc71 AR |
3901 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
3902 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
3903 | goto out; |
3904 | r = 0; | |
3905 | break; | |
801e459a TL |
3906 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
3907 | struct kvm_msr_list __user *user_msr_list = argp; | |
3908 | struct kvm_msr_list msr_list; | |
3909 | unsigned int n; | |
3910 | ||
3911 | r = -EFAULT; | |
3912 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
3913 | goto out; | |
3914 | n = msr_list.nmsrs; | |
3915 | msr_list.nmsrs = num_msr_based_features; | |
3916 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
3917 | goto out; | |
3918 | r = -E2BIG; | |
3919 | if (n < msr_list.nmsrs) | |
3920 | goto out; | |
3921 | r = -EFAULT; | |
3922 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
3923 | num_msr_based_features * sizeof(u32))) | |
3924 | goto out; | |
3925 | r = 0; | |
3926 | break; | |
3927 | } | |
3928 | case KVM_GET_MSRS: | |
3929 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
3930 | break; | |
c21d54f0 VK |
3931 | case KVM_GET_SUPPORTED_HV_CPUID: |
3932 | r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); | |
3933 | break; | |
043405e1 CO |
3934 | default: |
3935 | r = -EINVAL; | |
cf6c26ec | 3936 | break; |
043405e1 CO |
3937 | } |
3938 | out: | |
3939 | return r; | |
3940 | } | |
3941 | ||
f5f48ee1 SY |
3942 | static void wbinvd_ipi(void *garbage) |
3943 | { | |
3944 | wbinvd(); | |
3945 | } | |
3946 | ||
3947 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
3948 | { | |
e0f0bbc5 | 3949 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
3950 | } |
3951 | ||
313a3dc7 CO |
3952 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
3953 | { | |
f5f48ee1 SY |
3954 | /* Address WBINVD may be executed by guest */ |
3955 | if (need_emulate_wbinvd(vcpu)) { | |
afaf0b2f | 3956 | if (kvm_x86_ops.has_wbinvd_exit()) |
f5f48ee1 SY |
3957 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); |
3958 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
3959 | smp_call_function_single(vcpu->cpu, | |
3960 | wbinvd_ipi, NULL, 1); | |
3961 | } | |
3962 | ||
afaf0b2f | 3963 | kvm_x86_ops.vcpu_load(vcpu, cpu); |
8f6055cb | 3964 | |
37486135 BM |
3965 | /* Save host pkru register if supported */ |
3966 | vcpu->arch.host_pkru = read_pkru(); | |
3967 | ||
0dd6a6ed ZA |
3968 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
3969 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
3970 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
3971 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 3972 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 3973 | } |
8f6055cb | 3974 | |
b0c39dc6 | 3975 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 3976 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 3977 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
3978 | if (tsc_delta < 0) |
3979 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 3980 | |
b0c39dc6 | 3981 | if (kvm_check_tsc_unstable()) { |
07c1419a | 3982 | u64 offset = kvm_compute_tsc_offset(vcpu, |
b183aa58 | 3983 | vcpu->arch.last_guest_tsc); |
a545ab6a | 3984 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 3985 | vcpu->arch.tsc_catchup = 1; |
c285545f | 3986 | } |
a749e247 PB |
3987 | |
3988 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
3989 | kvm_lapic_restart_hv_timer(vcpu); | |
3990 | ||
d98d07ca MT |
3991 | /* |
3992 | * On a host with synchronized TSC, there is no need to update | |
3993 | * kvmclock on vcpu->cpu migration | |
3994 | */ | |
3995 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 3996 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 3997 | if (vcpu->cpu != cpu) |
1bd2009e | 3998 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 3999 | vcpu->cpu = cpu; |
6b7d7e76 | 4000 | } |
c9aaa895 | 4001 | |
c9aaa895 | 4002 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
4003 | } |
4004 | ||
0b9f6c46 PX |
4005 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
4006 | { | |
b0431382 BO |
4007 | struct kvm_host_map map; |
4008 | struct kvm_steal_time *st; | |
4009 | ||
0b9f6c46 PX |
4010 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
4011 | return; | |
4012 | ||
a6bd811f | 4013 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
4014 | return; |
4015 | ||
b0431382 BO |
4016 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, |
4017 | &vcpu->arch.st.cache, true)) | |
4018 | return; | |
4019 | ||
4020 | st = map.hva + | |
4021 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
0b9f6c46 | 4022 | |
a6bd811f | 4023 | st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; |
0b9f6c46 | 4024 | |
b0431382 | 4025 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); |
0b9f6c46 PX |
4026 | } |
4027 | ||
313a3dc7 CO |
4028 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
4029 | { | |
cc0d907c | 4030 | int idx; |
de63ad4c | 4031 | |
f1c6366e | 4032 | if (vcpu->preempted && !vcpu->arch.guest_state_protected) |
afaf0b2f | 4033 | vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu); |
de63ad4c | 4034 | |
931f261b AA |
4035 | /* |
4036 | * Disable page faults because we're in atomic context here. | |
4037 | * kvm_write_guest_offset_cached() would call might_fault() | |
4038 | * that relies on pagefault_disable() to tell if there's a | |
4039 | * bug. NOTE: the write to guest memory may not go through if | |
4040 | * during postcopy live migration or if there's heavy guest | |
4041 | * paging. | |
4042 | */ | |
4043 | pagefault_disable(); | |
cc0d907c AA |
4044 | /* |
4045 | * kvm_memslots() will be called by | |
4046 | * kvm_write_guest_offset_cached() so take the srcu lock. | |
4047 | */ | |
4048 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
0b9f6c46 | 4049 | kvm_steal_time_set_preempted(vcpu); |
cc0d907c | 4050 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
931f261b | 4051 | pagefault_enable(); |
afaf0b2f | 4052 | kvm_x86_ops.vcpu_put(vcpu); |
4ea1636b | 4053 | vcpu->arch.last_host_tsc = rdtsc(); |
efdab992 | 4054 | /* |
f9dcf08e RK |
4055 | * If userspace has set any breakpoints or watchpoints, dr6 is restored |
4056 | * on every vmexit, but if not, we might have a stale dr6 from the | |
4057 | * guest. do_debug expects dr6 to be cleared after it runs, do the same. | |
efdab992 | 4058 | */ |
f9dcf08e | 4059 | set_debugreg(0, 6); |
313a3dc7 CO |
4060 | } |
4061 | ||
313a3dc7 CO |
4062 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
4063 | struct kvm_lapic_state *s) | |
4064 | { | |
fa59cc00 | 4065 | if (vcpu->arch.apicv_active) |
afaf0b2f | 4066 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
d62caabb | 4067 | |
a92e2543 | 4068 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
4069 | } |
4070 | ||
4071 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
4072 | struct kvm_lapic_state *s) | |
4073 | { | |
a92e2543 RK |
4074 | int r; |
4075 | ||
4076 | r = kvm_apic_set_state(vcpu, s); | |
4077 | if (r) | |
4078 | return r; | |
cb142eb7 | 4079 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
4080 | |
4081 | return 0; | |
4082 | } | |
4083 | ||
127a457a MG |
4084 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
4085 | { | |
71cc849b PB |
4086 | /* |
4087 | * We can accept userspace's request for interrupt injection | |
4088 | * as long as we have a place to store the interrupt number. | |
4089 | * The actual injection will happen when the CPU is able to | |
4090 | * deliver the interrupt. | |
4091 | */ | |
4092 | if (kvm_cpu_has_extint(vcpu)) | |
4093 | return false; | |
4094 | ||
4095 | /* Acknowledging ExtINT does not happen if LINT0 is masked. */ | |
127a457a MG |
4096 | return (!lapic_in_kernel(vcpu) || |
4097 | kvm_apic_accept_pic_intr(vcpu)); | |
4098 | } | |
4099 | ||
782d422b MG |
4100 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) |
4101 | { | |
4102 | return kvm_arch_interrupt_allowed(vcpu) && | |
782d422b MG |
4103 | kvm_cpu_accept_dm_intr(vcpu); |
4104 | } | |
4105 | ||
f77bc6a4 ZX |
4106 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
4107 | struct kvm_interrupt *irq) | |
4108 | { | |
02cdb50f | 4109 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 4110 | return -EINVAL; |
1c1a9ce9 SR |
4111 | |
4112 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
4113 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
4114 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4115 | return 0; | |
4116 | } | |
4117 | ||
4118 | /* | |
4119 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
4120 | * fail for in-kernel 8259. | |
4121 | */ | |
4122 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 4123 | return -ENXIO; |
f77bc6a4 | 4124 | |
1c1a9ce9 SR |
4125 | if (vcpu->arch.pending_external_vector != -1) |
4126 | return -EEXIST; | |
f77bc6a4 | 4127 | |
1c1a9ce9 | 4128 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 4129 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
4130 | return 0; |
4131 | } | |
4132 | ||
c4abb7c9 JK |
4133 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
4134 | { | |
c4abb7c9 | 4135 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
4136 | |
4137 | return 0; | |
4138 | } | |
4139 | ||
f077825a PB |
4140 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
4141 | { | |
64d60670 PB |
4142 | kvm_make_request(KVM_REQ_SMI, vcpu); |
4143 | ||
f077825a PB |
4144 | return 0; |
4145 | } | |
4146 | ||
b209749f AK |
4147 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
4148 | struct kvm_tpr_access_ctl *tac) | |
4149 | { | |
4150 | if (tac->flags) | |
4151 | return -EINVAL; | |
4152 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
4153 | return 0; | |
4154 | } | |
4155 | ||
890ca9ae HY |
4156 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
4157 | u64 mcg_cap) | |
4158 | { | |
4159 | int r; | |
4160 | unsigned bank_num = mcg_cap & 0xff, bank; | |
4161 | ||
4162 | r = -EINVAL; | |
c4e0e4ab | 4163 | if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) |
890ca9ae | 4164 | goto out; |
c45dcc71 | 4165 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
4166 | goto out; |
4167 | r = 0; | |
4168 | vcpu->arch.mcg_cap = mcg_cap; | |
4169 | /* Init IA32_MCG_CTL to all 1s */ | |
4170 | if (mcg_cap & MCG_CTL_P) | |
4171 | vcpu->arch.mcg_ctl = ~(u64)0; | |
4172 | /* Init IA32_MCi_CTL to all 1s */ | |
4173 | for (bank = 0; bank < bank_num; bank++) | |
4174 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 | 4175 | |
afaf0b2f | 4176 | kvm_x86_ops.setup_mce(vcpu); |
890ca9ae HY |
4177 | out: |
4178 | return r; | |
4179 | } | |
4180 | ||
4181 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
4182 | struct kvm_x86_mce *mce) | |
4183 | { | |
4184 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
4185 | unsigned bank_num = mcg_cap & 0xff; | |
4186 | u64 *banks = vcpu->arch.mce_banks; | |
4187 | ||
4188 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
4189 | return -EINVAL; | |
4190 | /* | |
4191 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
4192 | * reporting is disabled | |
4193 | */ | |
4194 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
4195 | vcpu->arch.mcg_ctl != ~(u64)0) | |
4196 | return 0; | |
4197 | banks += 4 * mce->bank; | |
4198 | /* | |
4199 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
4200 | * reporting is disabled for the bank | |
4201 | */ | |
4202 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
4203 | return 0; | |
4204 | if (mce->status & MCI_STATUS_UC) { | |
4205 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 4206 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 4207 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
4208 | return 0; |
4209 | } | |
4210 | if (banks[1] & MCI_STATUS_VAL) | |
4211 | mce->status |= MCI_STATUS_OVER; | |
4212 | banks[2] = mce->addr; | |
4213 | banks[3] = mce->misc; | |
4214 | vcpu->arch.mcg_status = mce->mcg_status; | |
4215 | banks[1] = mce->status; | |
4216 | kvm_queue_exception(vcpu, MC_VECTOR); | |
4217 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
4218 | || !(banks[1] & MCI_STATUS_UC)) { | |
4219 | if (banks[1] & MCI_STATUS_VAL) | |
4220 | mce->status |= MCI_STATUS_OVER; | |
4221 | banks[2] = mce->addr; | |
4222 | banks[3] = mce->misc; | |
4223 | banks[1] = mce->status; | |
4224 | } else | |
4225 | banks[1] |= MCI_STATUS_OVER; | |
4226 | return 0; | |
4227 | } | |
4228 | ||
3cfc3092 JK |
4229 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
4230 | struct kvm_vcpu_events *events) | |
4231 | { | |
7460fb4a | 4232 | process_nmi(vcpu); |
59073aaf | 4233 | |
1f7becf1 JZ |
4234 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
4235 | process_smi(vcpu); | |
4236 | ||
a06230b6 OU |
4237 | /* |
4238 | * In guest mode, payload delivery should be deferred, | |
4239 | * so that the L1 hypervisor can intercept #PF before | |
4240 | * CR2 is modified (or intercept #DB before DR6 is | |
4241 | * modified under nVMX). Unless the per-VM capability, | |
4242 | * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of | |
4243 | * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we | |
4244 | * opportunistically defer the exception payload, deliver it if the | |
4245 | * capability hasn't been requested before processing a | |
4246 | * KVM_GET_VCPU_EVENTS. | |
4247 | */ | |
4248 | if (!vcpu->kvm->arch.exception_payload_enabled && | |
4249 | vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) | |
4250 | kvm_deliver_exception_payload(vcpu); | |
4251 | ||
664f8e26 | 4252 | /* |
59073aaf JM |
4253 | * The API doesn't provide the instruction length for software |
4254 | * exceptions, so don't report them. As long as the guest RIP | |
4255 | * isn't advanced, we should expect to encounter the exception | |
4256 | * again. | |
664f8e26 | 4257 | */ |
59073aaf JM |
4258 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
4259 | events->exception.injected = 0; | |
4260 | events->exception.pending = 0; | |
4261 | } else { | |
4262 | events->exception.injected = vcpu->arch.exception.injected; | |
4263 | events->exception.pending = vcpu->arch.exception.pending; | |
4264 | /* | |
4265 | * For ABI compatibility, deliberately conflate | |
4266 | * pending and injected exceptions when | |
4267 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
4268 | */ | |
4269 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4270 | events->exception.injected |= | |
4271 | vcpu->arch.exception.pending; | |
4272 | } | |
3cfc3092 JK |
4273 | events->exception.nr = vcpu->arch.exception.nr; |
4274 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
4275 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
4276 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
4277 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 4278 | |
03b82a30 | 4279 | events->interrupt.injected = |
04140b41 | 4280 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 4281 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 4282 | events->interrupt.soft = 0; |
afaf0b2f | 4283 | events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); |
3cfc3092 JK |
4284 | |
4285 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 4286 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
afaf0b2f | 4287 | events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu); |
97e69aa6 | 4288 | events->nmi.pad = 0; |
3cfc3092 | 4289 | |
66450a21 | 4290 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 4291 | |
f077825a PB |
4292 | events->smi.smm = is_smm(vcpu); |
4293 | events->smi.pending = vcpu->arch.smi_pending; | |
4294 | events->smi.smm_inside_nmi = | |
4295 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
4296 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
4297 | ||
dab4b911 | 4298 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
4299 | | KVM_VCPUEVENT_VALID_SHADOW |
4300 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
4301 | if (vcpu->kvm->arch.exception_payload_enabled) |
4302 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
4303 | ||
97e69aa6 | 4304 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
4305 | } |
4306 | ||
c5833c7a | 4307 | static void kvm_smm_changed(struct kvm_vcpu *vcpu); |
6ef4e07e | 4308 | |
3cfc3092 JK |
4309 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
4310 | struct kvm_vcpu_events *events) | |
4311 | { | |
dab4b911 | 4312 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 4313 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 4314 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf JM |
4315 | | KVM_VCPUEVENT_VALID_SMM |
4316 | | KVM_VCPUEVENT_VALID_PAYLOAD)) | |
3cfc3092 JK |
4317 | return -EINVAL; |
4318 | ||
59073aaf JM |
4319 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
4320 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4321 | return -EINVAL; | |
4322 | if (events->exception.pending) | |
4323 | events->exception.injected = 0; | |
4324 | else | |
4325 | events->exception_has_payload = 0; | |
4326 | } else { | |
4327 | events->exception.pending = 0; | |
4328 | events->exception_has_payload = 0; | |
4329 | } | |
4330 | ||
4331 | if ((events->exception.injected || events->exception.pending) && | |
4332 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
4333 | return -EINVAL; |
4334 | ||
28bf2888 DH |
4335 | /* INITs are latched while in SMM */ |
4336 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
4337 | (events->smi.smm || events->smi.pending) && | |
4338 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
4339 | return -EINVAL; | |
4340 | ||
7460fb4a | 4341 | process_nmi(vcpu); |
59073aaf JM |
4342 | vcpu->arch.exception.injected = events->exception.injected; |
4343 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
4344 | vcpu->arch.exception.nr = events->exception.nr; |
4345 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
4346 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
4347 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
4348 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 4349 | |
04140b41 | 4350 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
4351 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
4352 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 | 4353 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
afaf0b2f | 4354 | kvm_x86_ops.set_interrupt_shadow(vcpu, |
48005f64 | 4355 | events->interrupt.shadow); |
3cfc3092 JK |
4356 | |
4357 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
4358 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
4359 | vcpu->arch.nmi_pending = events->nmi.pending; | |
afaf0b2f | 4360 | kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked); |
3cfc3092 | 4361 | |
66450a21 | 4362 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 4363 | lapic_in_kernel(vcpu)) |
66450a21 | 4364 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 4365 | |
f077825a | 4366 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
c5833c7a SC |
4367 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { |
4368 | if (events->smi.smm) | |
4369 | vcpu->arch.hflags |= HF_SMM_MASK; | |
4370 | else | |
4371 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
4372 | kvm_smm_changed(vcpu); | |
4373 | } | |
6ef4e07e | 4374 | |
f077825a | 4375 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
4376 | |
4377 | if (events->smi.smm) { | |
4378 | if (events->smi.smm_inside_nmi) | |
4379 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 4380 | else |
f4ef1910 | 4381 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
4382 | } |
4383 | ||
4384 | if (lapic_in_kernel(vcpu)) { | |
4385 | if (events->smi.latched_init) | |
4386 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
4387 | else | |
4388 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
4389 | } |
4390 | } | |
4391 | ||
3842d135 AK |
4392 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
4393 | ||
3cfc3092 JK |
4394 | return 0; |
4395 | } | |
4396 | ||
a1efbe77 JK |
4397 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
4398 | struct kvm_debugregs *dbgregs) | |
4399 | { | |
73aaf249 JK |
4400 | unsigned long val; |
4401 | ||
a1efbe77 | 4402 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 4403 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 4404 | dbgregs->dr6 = val; |
a1efbe77 JK |
4405 | dbgregs->dr7 = vcpu->arch.dr7; |
4406 | dbgregs->flags = 0; | |
97e69aa6 | 4407 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
4408 | } |
4409 | ||
4410 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
4411 | struct kvm_debugregs *dbgregs) | |
4412 | { | |
4413 | if (dbgregs->flags) | |
4414 | return -EINVAL; | |
4415 | ||
d14bdb55 PB |
4416 | if (dbgregs->dr6 & ~0xffffffffull) |
4417 | return -EINVAL; | |
4418 | if (dbgregs->dr7 & ~0xffffffffull) | |
4419 | return -EINVAL; | |
4420 | ||
a1efbe77 | 4421 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 4422 | kvm_update_dr0123(vcpu); |
a1efbe77 JK |
4423 | vcpu->arch.dr6 = dbgregs->dr6; |
4424 | vcpu->arch.dr7 = dbgregs->dr7; | |
9926c9fd | 4425 | kvm_update_dr7(vcpu); |
a1efbe77 | 4426 | |
a1efbe77 JK |
4427 | return 0; |
4428 | } | |
4429 | ||
df1daba7 PB |
4430 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
4431 | ||
4432 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
4433 | { | |
b666a4b6 | 4434 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
400e4b20 | 4435 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
4436 | u64 valid; |
4437 | ||
4438 | /* | |
4439 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4440 | * leaves 0 and 1 in the loop below. | |
4441 | */ | |
4442 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
4443 | ||
4444 | /* Set XSTATE_BV */ | |
00c87e9a | 4445 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
4446 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
4447 | ||
4448 | /* | |
4449 | * Copy each region from the possibly compacted offset to the | |
4450 | * non-compacted offset. | |
4451 | */ | |
d91cab78 | 4452 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4453 | while (valid) { |
abd16d68 SAS |
4454 | u64 xfeature_mask = valid & -valid; |
4455 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
4456 | void *src = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
4457 | |
4458 | if (src) { | |
4459 | u32 size, offset, ecx, edx; | |
abd16d68 | 4460 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 4461 | &size, &offset, &ecx, &edx); |
abd16d68 | 4462 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
4463 | memcpy(dest + offset, &vcpu->arch.pkru, |
4464 | sizeof(vcpu->arch.pkru)); | |
4465 | else | |
4466 | memcpy(dest + offset, src, size); | |
4467 | ||
df1daba7 PB |
4468 | } |
4469 | ||
abd16d68 | 4470 | valid -= xfeature_mask; |
df1daba7 PB |
4471 | } |
4472 | } | |
4473 | ||
4474 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
4475 | { | |
b666a4b6 | 4476 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
df1daba7 PB |
4477 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
4478 | u64 valid; | |
4479 | ||
4480 | /* | |
4481 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4482 | * leaves 0 and 1 in the loop below. | |
4483 | */ | |
4484 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
4485 | ||
4486 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 4487 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 4488 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 4489 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
4490 | |
4491 | /* | |
4492 | * Copy each region from the non-compacted offset to the | |
4493 | * possibly compacted offset. | |
4494 | */ | |
d91cab78 | 4495 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4496 | while (valid) { |
abd16d68 SAS |
4497 | u64 xfeature_mask = valid & -valid; |
4498 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
4499 | void *dest = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
4500 | |
4501 | if (dest) { | |
4502 | u32 size, offset, ecx, edx; | |
abd16d68 | 4503 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 4504 | &size, &offset, &ecx, &edx); |
abd16d68 | 4505 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
4506 | memcpy(&vcpu->arch.pkru, src + offset, |
4507 | sizeof(vcpu->arch.pkru)); | |
4508 | else | |
4509 | memcpy(dest, src + offset, size); | |
ee4100da | 4510 | } |
df1daba7 | 4511 | |
abd16d68 | 4512 | valid -= xfeature_mask; |
df1daba7 PB |
4513 | } |
4514 | } | |
4515 | ||
2d5b5a66 SY |
4516 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
4517 | struct kvm_xsave *guest_xsave) | |
4518 | { | |
ed02b213 TL |
4519 | if (!vcpu->arch.guest_fpu) |
4520 | return; | |
4521 | ||
d366bf7e | 4522 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
4523 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
4524 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 4525 | } else { |
2d5b5a66 | 4526 | memcpy(guest_xsave->region, |
b666a4b6 | 4527 | &vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4528 | sizeof(struct fxregs_state)); |
2d5b5a66 | 4529 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 4530 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
4531 | } |
4532 | } | |
4533 | ||
a575813b WL |
4534 | #define XSAVE_MXCSR_OFFSET 24 |
4535 | ||
2d5b5a66 SY |
4536 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
4537 | struct kvm_xsave *guest_xsave) | |
4538 | { | |
ed02b213 TL |
4539 | u64 xstate_bv; |
4540 | u32 mxcsr; | |
4541 | ||
4542 | if (!vcpu->arch.guest_fpu) | |
4543 | return 0; | |
4544 | ||
4545 | xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
4546 | mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; | |
2d5b5a66 | 4547 | |
d366bf7e | 4548 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
4549 | /* |
4550 | * Here we allow setting states that are not present in | |
4551 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
4552 | * with old userspace. | |
4553 | */ | |
cfc48181 | 4554 | if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) |
d7876f1b | 4555 | return -EINVAL; |
df1daba7 | 4556 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 4557 | } else { |
a575813b WL |
4558 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
4559 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 4560 | return -EINVAL; |
b666a4b6 | 4561 | memcpy(&vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4562 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
4563 | } |
4564 | return 0; | |
4565 | } | |
4566 | ||
4567 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
4568 | struct kvm_xcrs *guest_xcrs) | |
4569 | { | |
d366bf7e | 4570 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
4571 | guest_xcrs->nr_xcrs = 0; |
4572 | return; | |
4573 | } | |
4574 | ||
4575 | guest_xcrs->nr_xcrs = 1; | |
4576 | guest_xcrs->flags = 0; | |
4577 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
4578 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
4579 | } | |
4580 | ||
4581 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
4582 | struct kvm_xcrs *guest_xcrs) | |
4583 | { | |
4584 | int i, r = 0; | |
4585 | ||
d366bf7e | 4586 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
4587 | return -EINVAL; |
4588 | ||
4589 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
4590 | return -EINVAL; | |
4591 | ||
4592 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
4593 | /* Only support XCR0 currently */ | |
c67a04cb | 4594 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 4595 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 4596 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
4597 | break; |
4598 | } | |
4599 | if (r) | |
4600 | r = -EINVAL; | |
4601 | return r; | |
4602 | } | |
4603 | ||
1c0b28c2 EM |
4604 | /* |
4605 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
4606 | * stopped by the hypervisor. This function will be called from the host only. | |
4607 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
4608 | * does not support pv clocks. | |
4609 | */ | |
4610 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
4611 | { | |
0b79459b | 4612 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 4613 | return -EINVAL; |
51d59c6b | 4614 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
4615 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
4616 | return 0; | |
4617 | } | |
4618 | ||
5c919412 AS |
4619 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
4620 | struct kvm_enable_cap *cap) | |
4621 | { | |
57b119da VK |
4622 | int r; |
4623 | uint16_t vmcs_version; | |
4624 | void __user *user_ptr; | |
4625 | ||
5c919412 AS |
4626 | if (cap->flags) |
4627 | return -EINVAL; | |
4628 | ||
4629 | switch (cap->cap) { | |
efc479e6 RK |
4630 | case KVM_CAP_HYPERV_SYNIC2: |
4631 | if (cap->args[0]) | |
4632 | return -EINVAL; | |
df561f66 | 4633 | fallthrough; |
b2869f28 | 4634 | |
5c919412 | 4635 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
4636 | if (!irqchip_in_kernel(vcpu->kvm)) |
4637 | return -EINVAL; | |
efc479e6 RK |
4638 | return kvm_hv_activate_synic(vcpu, cap->cap == |
4639 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 4640 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
33b22172 | 4641 | if (!kvm_x86_ops.nested_ops->enable_evmcs) |
5158917c | 4642 | return -ENOTTY; |
33b22172 | 4643 | r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); |
57b119da VK |
4644 | if (!r) { |
4645 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
4646 | if (copy_to_user(user_ptr, &vmcs_version, | |
4647 | sizeof(vmcs_version))) | |
4648 | r = -EFAULT; | |
4649 | } | |
4650 | return r; | |
344c6c80 | 4651 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4652 | if (!kvm_x86_ops.enable_direct_tlbflush) |
344c6c80 TL |
4653 | return -ENOTTY; |
4654 | ||
afaf0b2f | 4655 | return kvm_x86_ops.enable_direct_tlbflush(vcpu); |
57b119da | 4656 | |
66570e96 OU |
4657 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
4658 | vcpu->arch.pv_cpuid.enforce = cap->args[0]; | |
01b4f510 OU |
4659 | if (vcpu->arch.pv_cpuid.enforce) |
4660 | kvm_update_pv_runtime(vcpu); | |
66570e96 OU |
4661 | |
4662 | return 0; | |
4663 | ||
5c919412 AS |
4664 | default: |
4665 | return -EINVAL; | |
4666 | } | |
4667 | } | |
4668 | ||
313a3dc7 CO |
4669 | long kvm_arch_vcpu_ioctl(struct file *filp, |
4670 | unsigned int ioctl, unsigned long arg) | |
4671 | { | |
4672 | struct kvm_vcpu *vcpu = filp->private_data; | |
4673 | void __user *argp = (void __user *)arg; | |
4674 | int r; | |
d1ac91d8 AK |
4675 | union { |
4676 | struct kvm_lapic_state *lapic; | |
4677 | struct kvm_xsave *xsave; | |
4678 | struct kvm_xcrs *xcrs; | |
4679 | void *buffer; | |
4680 | } u; | |
4681 | ||
9b062471 CD |
4682 | vcpu_load(vcpu); |
4683 | ||
d1ac91d8 | 4684 | u.buffer = NULL; |
313a3dc7 CO |
4685 | switch (ioctl) { |
4686 | case KVM_GET_LAPIC: { | |
2204ae3c | 4687 | r = -EINVAL; |
bce87cce | 4688 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4689 | goto out; |
254272ce BG |
4690 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
4691 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 4692 | |
b772ff36 | 4693 | r = -ENOMEM; |
d1ac91d8 | 4694 | if (!u.lapic) |
b772ff36 | 4695 | goto out; |
d1ac91d8 | 4696 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4697 | if (r) |
4698 | goto out; | |
4699 | r = -EFAULT; | |
d1ac91d8 | 4700 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
4701 | goto out; |
4702 | r = 0; | |
4703 | break; | |
4704 | } | |
4705 | case KVM_SET_LAPIC: { | |
2204ae3c | 4706 | r = -EINVAL; |
bce87cce | 4707 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4708 | goto out; |
ff5c2c03 | 4709 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
4710 | if (IS_ERR(u.lapic)) { |
4711 | r = PTR_ERR(u.lapic); | |
4712 | goto out_nofree; | |
4713 | } | |
ff5c2c03 | 4714 | |
d1ac91d8 | 4715 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4716 | break; |
4717 | } | |
f77bc6a4 ZX |
4718 | case KVM_INTERRUPT: { |
4719 | struct kvm_interrupt irq; | |
4720 | ||
4721 | r = -EFAULT; | |
0e96f31e | 4722 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
4723 | goto out; |
4724 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
4725 | break; |
4726 | } | |
c4abb7c9 JK |
4727 | case KVM_NMI: { |
4728 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
4729 | break; |
4730 | } | |
f077825a PB |
4731 | case KVM_SMI: { |
4732 | r = kvm_vcpu_ioctl_smi(vcpu); | |
4733 | break; | |
4734 | } | |
313a3dc7 CO |
4735 | case KVM_SET_CPUID: { |
4736 | struct kvm_cpuid __user *cpuid_arg = argp; | |
4737 | struct kvm_cpuid cpuid; | |
4738 | ||
4739 | r = -EFAULT; | |
0e96f31e | 4740 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
4741 | goto out; |
4742 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
4743 | break; |
4744 | } | |
07716717 DK |
4745 | case KVM_SET_CPUID2: { |
4746 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4747 | struct kvm_cpuid2 cpuid; | |
4748 | ||
4749 | r = -EFAULT; | |
0e96f31e | 4750 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4751 | goto out; |
4752 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 4753 | cpuid_arg->entries); |
07716717 DK |
4754 | break; |
4755 | } | |
4756 | case KVM_GET_CPUID2: { | |
4757 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4758 | struct kvm_cpuid2 cpuid; | |
4759 | ||
4760 | r = -EFAULT; | |
0e96f31e | 4761 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4762 | goto out; |
4763 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 4764 | cpuid_arg->entries); |
07716717 DK |
4765 | if (r) |
4766 | goto out; | |
4767 | r = -EFAULT; | |
0e96f31e | 4768 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
4769 | goto out; |
4770 | r = 0; | |
4771 | break; | |
4772 | } | |
801e459a TL |
4773 | case KVM_GET_MSRS: { |
4774 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 4775 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 4776 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4777 | break; |
801e459a TL |
4778 | } |
4779 | case KVM_SET_MSRS: { | |
4780 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 4781 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 4782 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4783 | break; |
801e459a | 4784 | } |
b209749f AK |
4785 | case KVM_TPR_ACCESS_REPORTING: { |
4786 | struct kvm_tpr_access_ctl tac; | |
4787 | ||
4788 | r = -EFAULT; | |
0e96f31e | 4789 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
4790 | goto out; |
4791 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
4792 | if (r) | |
4793 | goto out; | |
4794 | r = -EFAULT; | |
0e96f31e | 4795 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
4796 | goto out; |
4797 | r = 0; | |
4798 | break; | |
4799 | }; | |
b93463aa AK |
4800 | case KVM_SET_VAPIC_ADDR: { |
4801 | struct kvm_vapic_addr va; | |
7301d6ab | 4802 | int idx; |
b93463aa AK |
4803 | |
4804 | r = -EINVAL; | |
35754c98 | 4805 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
4806 | goto out; |
4807 | r = -EFAULT; | |
0e96f31e | 4808 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 4809 | goto out; |
7301d6ab | 4810 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 4811 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 4812 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
4813 | break; |
4814 | } | |
890ca9ae HY |
4815 | case KVM_X86_SETUP_MCE: { |
4816 | u64 mcg_cap; | |
4817 | ||
4818 | r = -EFAULT; | |
0e96f31e | 4819 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
4820 | goto out; |
4821 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
4822 | break; | |
4823 | } | |
4824 | case KVM_X86_SET_MCE: { | |
4825 | struct kvm_x86_mce mce; | |
4826 | ||
4827 | r = -EFAULT; | |
0e96f31e | 4828 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
4829 | goto out; |
4830 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
4831 | break; | |
4832 | } | |
3cfc3092 JK |
4833 | case KVM_GET_VCPU_EVENTS: { |
4834 | struct kvm_vcpu_events events; | |
4835 | ||
4836 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
4837 | ||
4838 | r = -EFAULT; | |
4839 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
4840 | break; | |
4841 | r = 0; | |
4842 | break; | |
4843 | } | |
4844 | case KVM_SET_VCPU_EVENTS: { | |
4845 | struct kvm_vcpu_events events; | |
4846 | ||
4847 | r = -EFAULT; | |
4848 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
4849 | break; | |
4850 | ||
4851 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
4852 | break; | |
4853 | } | |
a1efbe77 JK |
4854 | case KVM_GET_DEBUGREGS: { |
4855 | struct kvm_debugregs dbgregs; | |
4856 | ||
4857 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
4858 | ||
4859 | r = -EFAULT; | |
4860 | if (copy_to_user(argp, &dbgregs, | |
4861 | sizeof(struct kvm_debugregs))) | |
4862 | break; | |
4863 | r = 0; | |
4864 | break; | |
4865 | } | |
4866 | case KVM_SET_DEBUGREGS: { | |
4867 | struct kvm_debugregs dbgregs; | |
4868 | ||
4869 | r = -EFAULT; | |
4870 | if (copy_from_user(&dbgregs, argp, | |
4871 | sizeof(struct kvm_debugregs))) | |
4872 | break; | |
4873 | ||
4874 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
4875 | break; | |
4876 | } | |
2d5b5a66 | 4877 | case KVM_GET_XSAVE: { |
254272ce | 4878 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4879 | r = -ENOMEM; |
d1ac91d8 | 4880 | if (!u.xsave) |
2d5b5a66 SY |
4881 | break; |
4882 | ||
d1ac91d8 | 4883 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4884 | |
4885 | r = -EFAULT; | |
d1ac91d8 | 4886 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
4887 | break; |
4888 | r = 0; | |
4889 | break; | |
4890 | } | |
4891 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 4892 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
4893 | if (IS_ERR(u.xsave)) { |
4894 | r = PTR_ERR(u.xsave); | |
4895 | goto out_nofree; | |
4896 | } | |
2d5b5a66 | 4897 | |
d1ac91d8 | 4898 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4899 | break; |
4900 | } | |
4901 | case KVM_GET_XCRS: { | |
254272ce | 4902 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4903 | r = -ENOMEM; |
d1ac91d8 | 4904 | if (!u.xcrs) |
2d5b5a66 SY |
4905 | break; |
4906 | ||
d1ac91d8 | 4907 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4908 | |
4909 | r = -EFAULT; | |
d1ac91d8 | 4910 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
4911 | sizeof(struct kvm_xcrs))) |
4912 | break; | |
4913 | r = 0; | |
4914 | break; | |
4915 | } | |
4916 | case KVM_SET_XCRS: { | |
ff5c2c03 | 4917 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
4918 | if (IS_ERR(u.xcrs)) { |
4919 | r = PTR_ERR(u.xcrs); | |
4920 | goto out_nofree; | |
4921 | } | |
2d5b5a66 | 4922 | |
d1ac91d8 | 4923 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4924 | break; |
4925 | } | |
92a1f12d JR |
4926 | case KVM_SET_TSC_KHZ: { |
4927 | u32 user_tsc_khz; | |
4928 | ||
4929 | r = -EINVAL; | |
92a1f12d JR |
4930 | user_tsc_khz = (u32)arg; |
4931 | ||
26769f96 MT |
4932 | if (kvm_has_tsc_control && |
4933 | user_tsc_khz >= kvm_max_guest_tsc_khz) | |
92a1f12d JR |
4934 | goto out; |
4935 | ||
cc578287 ZA |
4936 | if (user_tsc_khz == 0) |
4937 | user_tsc_khz = tsc_khz; | |
4938 | ||
381d585c HZ |
4939 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
4940 | r = 0; | |
92a1f12d | 4941 | |
92a1f12d JR |
4942 | goto out; |
4943 | } | |
4944 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 4945 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
4946 | goto out; |
4947 | } | |
1c0b28c2 EM |
4948 | case KVM_KVMCLOCK_CTRL: { |
4949 | r = kvm_set_guest_paused(vcpu); | |
4950 | goto out; | |
4951 | } | |
5c919412 AS |
4952 | case KVM_ENABLE_CAP: { |
4953 | struct kvm_enable_cap cap; | |
4954 | ||
4955 | r = -EFAULT; | |
4956 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
4957 | goto out; | |
4958 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
4959 | break; | |
4960 | } | |
8fcc4b59 JM |
4961 | case KVM_GET_NESTED_STATE: { |
4962 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
4963 | u32 user_data_size; | |
4964 | ||
4965 | r = -EINVAL; | |
33b22172 | 4966 | if (!kvm_x86_ops.nested_ops->get_state) |
8fcc4b59 JM |
4967 | break; |
4968 | ||
4969 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 4970 | r = -EFAULT; |
8fcc4b59 | 4971 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 4972 | break; |
8fcc4b59 | 4973 | |
33b22172 PB |
4974 | r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, |
4975 | user_data_size); | |
8fcc4b59 | 4976 | if (r < 0) |
26b471c7 | 4977 | break; |
8fcc4b59 JM |
4978 | |
4979 | if (r > user_data_size) { | |
4980 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
4981 | r = -EFAULT; |
4982 | else | |
4983 | r = -E2BIG; | |
4984 | break; | |
8fcc4b59 | 4985 | } |
26b471c7 | 4986 | |
8fcc4b59 JM |
4987 | r = 0; |
4988 | break; | |
4989 | } | |
4990 | case KVM_SET_NESTED_STATE: { | |
4991 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
4992 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 4993 | int idx; |
8fcc4b59 JM |
4994 | |
4995 | r = -EINVAL; | |
33b22172 | 4996 | if (!kvm_x86_ops.nested_ops->set_state) |
8fcc4b59 JM |
4997 | break; |
4998 | ||
26b471c7 | 4999 | r = -EFAULT; |
8fcc4b59 | 5000 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 5001 | break; |
8fcc4b59 | 5002 | |
26b471c7 | 5003 | r = -EINVAL; |
8fcc4b59 | 5004 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 5005 | break; |
8fcc4b59 JM |
5006 | |
5007 | if (kvm_state.flags & | |
8cab6507 | 5008 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
cc440cda PB |
5009 | | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING |
5010 | | KVM_STATE_NESTED_GIF_SET)) | |
26b471c7 | 5011 | break; |
8fcc4b59 JM |
5012 | |
5013 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
5014 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
5015 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 5016 | break; |
8fcc4b59 | 5017 | |
ad5996d9 | 5018 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
33b22172 | 5019 | r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 5020 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
5021 | break; |
5022 | } | |
c21d54f0 VK |
5023 | case KVM_GET_SUPPORTED_HV_CPUID: |
5024 | r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); | |
2bc39970 | 5025 | break; |
313a3dc7 CO |
5026 | default: |
5027 | r = -EINVAL; | |
5028 | } | |
5029 | out: | |
d1ac91d8 | 5030 | kfree(u.buffer); |
9b062471 CD |
5031 | out_nofree: |
5032 | vcpu_put(vcpu); | |
313a3dc7 CO |
5033 | return r; |
5034 | } | |
5035 | ||
1499fa80 | 5036 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
5037 | { |
5038 | return VM_FAULT_SIGBUS; | |
5039 | } | |
5040 | ||
1fe779f8 CO |
5041 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
5042 | { | |
5043 | int ret; | |
5044 | ||
5045 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 5046 | return -EINVAL; |
afaf0b2f | 5047 | ret = kvm_x86_ops.set_tss_addr(kvm, addr); |
1fe779f8 CO |
5048 | return ret; |
5049 | } | |
5050 | ||
b927a3ce SY |
5051 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
5052 | u64 ident_addr) | |
5053 | { | |
afaf0b2f | 5054 | return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr); |
b927a3ce SY |
5055 | } |
5056 | ||
1fe779f8 | 5057 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 5058 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
5059 | { |
5060 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
5061 | return -EINVAL; | |
5062 | ||
79fac95e | 5063 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
5064 | |
5065 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 5066 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 5067 | |
79fac95e | 5068 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
5069 | return 0; |
5070 | } | |
5071 | ||
bc8a3d89 | 5072 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 5073 | { |
39de71ec | 5074 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
5075 | } |
5076 | ||
1fe779f8 CO |
5077 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
5078 | { | |
90bca052 | 5079 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5080 | int r; |
5081 | ||
5082 | r = 0; | |
5083 | switch (chip->chip_id) { | |
5084 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 5085 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
5086 | sizeof(struct kvm_pic_state)); |
5087 | break; | |
5088 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 5089 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
5090 | sizeof(struct kvm_pic_state)); |
5091 | break; | |
5092 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5093 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5094 | break; |
5095 | default: | |
5096 | r = -EINVAL; | |
5097 | break; | |
5098 | } | |
5099 | return r; | |
5100 | } | |
5101 | ||
5102 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
5103 | { | |
90bca052 | 5104 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5105 | int r; |
5106 | ||
5107 | r = 0; | |
5108 | switch (chip->chip_id) { | |
5109 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
5110 | spin_lock(&pic->lock); |
5111 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 5112 | sizeof(struct kvm_pic_state)); |
90bca052 | 5113 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5114 | break; |
5115 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
5116 | spin_lock(&pic->lock); |
5117 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 5118 | sizeof(struct kvm_pic_state)); |
90bca052 | 5119 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5120 | break; |
5121 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5122 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5123 | break; |
5124 | default: | |
5125 | r = -EINVAL; | |
5126 | break; | |
5127 | } | |
90bca052 | 5128 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
5129 | return r; |
5130 | } | |
5131 | ||
e0f63cb9 SY |
5132 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
5133 | { | |
34f3941c RK |
5134 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
5135 | ||
5136 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
5137 | ||
5138 | mutex_lock(&kps->lock); | |
5139 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
5140 | mutex_unlock(&kps->lock); | |
2da29bcc | 5141 | return 0; |
e0f63cb9 SY |
5142 | } |
5143 | ||
5144 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
5145 | { | |
0185604c | 5146 | int i; |
09edea72 RK |
5147 | struct kvm_pit *pit = kvm->arch.vpit; |
5148 | ||
5149 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 5150 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 5151 | for (i = 0; i < 3; i++) |
09edea72 RK |
5152 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
5153 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 5154 | return 0; |
e9f42757 BK |
5155 | } |
5156 | ||
5157 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5158 | { | |
e9f42757 BK |
5159 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
5160 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
5161 | sizeof(ps->channels)); | |
5162 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
5163 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 5164 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 5165 | return 0; |
e9f42757 BK |
5166 | } |
5167 | ||
5168 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5169 | { | |
2da29bcc | 5170 | int start = 0; |
0185604c | 5171 | int i; |
e9f42757 | 5172 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
5173 | struct kvm_pit *pit = kvm->arch.vpit; |
5174 | ||
5175 | mutex_lock(&pit->pit_state.lock); | |
5176 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
5177 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
5178 | if (!prev_legacy && cur_legacy) | |
5179 | start = 1; | |
09edea72 RK |
5180 | memcpy(&pit->pit_state.channels, &ps->channels, |
5181 | sizeof(pit->pit_state.channels)); | |
5182 | pit->pit_state.flags = ps->flags; | |
0185604c | 5183 | for (i = 0; i < 3; i++) |
09edea72 | 5184 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 5185 | start && i == 0); |
09edea72 | 5186 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 5187 | return 0; |
e0f63cb9 SY |
5188 | } |
5189 | ||
52d939a0 MT |
5190 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
5191 | struct kvm_reinject_control *control) | |
5192 | { | |
71474e2f RK |
5193 | struct kvm_pit *pit = kvm->arch.vpit; |
5194 | ||
71474e2f RK |
5195 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
5196 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
5197 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
5198 | */ | |
5199 | mutex_lock(&pit->pit_state.lock); | |
5200 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
5201 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 5202 | |
52d939a0 MT |
5203 | return 0; |
5204 | } | |
5205 | ||
0dff0846 | 5206 | void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) |
5bb064dc | 5207 | { |
88178fd4 KH |
5208 | /* |
5209 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
5210 | */ | |
afaf0b2f SC |
5211 | if (kvm_x86_ops.flush_log_dirty) |
5212 | kvm_x86_ops.flush_log_dirty(kvm); | |
5bb064dc ZX |
5213 | } |
5214 | ||
aa2fbe6d YZ |
5215 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
5216 | bool line_status) | |
23d43cf9 CD |
5217 | { |
5218 | if (!irqchip_in_kernel(kvm)) | |
5219 | return -ENXIO; | |
5220 | ||
5221 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
5222 | irq_event->irq, irq_event->level, |
5223 | line_status); | |
23d43cf9 CD |
5224 | return 0; |
5225 | } | |
5226 | ||
e5d83c74 PB |
5227 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
5228 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
5229 | { |
5230 | int r; | |
5231 | ||
5232 | if (cap->flags) | |
5233 | return -EINVAL; | |
5234 | ||
5235 | switch (cap->cap) { | |
5236 | case KVM_CAP_DISABLE_QUIRKS: | |
5237 | kvm->arch.disabled_quirks = cap->args[0]; | |
5238 | r = 0; | |
5239 | break; | |
49df6397 SR |
5240 | case KVM_CAP_SPLIT_IRQCHIP: { |
5241 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
5242 | r = -EINVAL; |
5243 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
5244 | goto split_irqchip_unlock; | |
49df6397 SR |
5245 | r = -EEXIST; |
5246 | if (irqchip_in_kernel(kvm)) | |
5247 | goto split_irqchip_unlock; | |
557abc40 | 5248 | if (kvm->created_vcpus) |
49df6397 SR |
5249 | goto split_irqchip_unlock; |
5250 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 5251 | if (r) |
49df6397 SR |
5252 | goto split_irqchip_unlock; |
5253 | /* Pairs with irqchip_in_kernel. */ | |
5254 | smp_wmb(); | |
49776faf | 5255 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 5256 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
5257 | r = 0; |
5258 | split_irqchip_unlock: | |
5259 | mutex_unlock(&kvm->lock); | |
5260 | break; | |
5261 | } | |
37131313 RK |
5262 | case KVM_CAP_X2APIC_API: |
5263 | r = -EINVAL; | |
5264 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
5265 | break; | |
5266 | ||
5267 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
5268 | kvm->arch.x2apic_format = true; | |
c519265f RK |
5269 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
5270 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
5271 | |
5272 | r = 0; | |
5273 | break; | |
4d5422ce WL |
5274 | case KVM_CAP_X86_DISABLE_EXITS: |
5275 | r = -EINVAL; | |
5276 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
5277 | break; | |
5278 | ||
5279 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
5280 | kvm_can_mwait_in_guest()) | |
5281 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 5282 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 5283 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
5284 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
5285 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
5286 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
5287 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
5288 | r = 0; |
5289 | break; | |
6fbbde9a DS |
5290 | case KVM_CAP_MSR_PLATFORM_INFO: |
5291 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
5292 | r = 0; | |
c4f55198 JM |
5293 | break; |
5294 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
5295 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
5296 | r = 0; | |
6fbbde9a | 5297 | break; |
1ae09954 AG |
5298 | case KVM_CAP_X86_USER_SPACE_MSR: |
5299 | kvm->arch.user_space_msr_mask = cap->args[0]; | |
5300 | r = 0; | |
5301 | break; | |
90de4a18 NA |
5302 | default: |
5303 | r = -EINVAL; | |
5304 | break; | |
5305 | } | |
5306 | return r; | |
5307 | } | |
5308 | ||
1a155254 AG |
5309 | static void kvm_clear_msr_filter(struct kvm *kvm) |
5310 | { | |
5311 | u32 i; | |
5312 | u32 count = kvm->arch.msr_filter.count; | |
5313 | struct msr_bitmap_range ranges[16]; | |
5314 | ||
5315 | mutex_lock(&kvm->lock); | |
5316 | kvm->arch.msr_filter.count = 0; | |
5317 | memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0])); | |
5318 | mutex_unlock(&kvm->lock); | |
5319 | synchronize_srcu(&kvm->srcu); | |
5320 | ||
5321 | for (i = 0; i < count; i++) | |
5322 | kfree(ranges[i].bitmap); | |
5323 | } | |
5324 | ||
5325 | static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range) | |
5326 | { | |
5327 | struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges; | |
5328 | struct msr_bitmap_range range; | |
5329 | unsigned long *bitmap = NULL; | |
5330 | size_t bitmap_size; | |
5331 | int r; | |
5332 | ||
5333 | if (!user_range->nmsrs) | |
5334 | return 0; | |
5335 | ||
5336 | bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); | |
5337 | if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) | |
5338 | return -EINVAL; | |
5339 | ||
5340 | bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); | |
5341 | if (IS_ERR(bitmap)) | |
5342 | return PTR_ERR(bitmap); | |
5343 | ||
5344 | range = (struct msr_bitmap_range) { | |
5345 | .flags = user_range->flags, | |
5346 | .base = user_range->base, | |
5347 | .nmsrs = user_range->nmsrs, | |
5348 | .bitmap = bitmap, | |
5349 | }; | |
5350 | ||
5351 | if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) { | |
5352 | r = -EINVAL; | |
5353 | goto err; | |
5354 | } | |
5355 | ||
5356 | if (!range.flags) { | |
5357 | r = -EINVAL; | |
5358 | goto err; | |
5359 | } | |
5360 | ||
5361 | /* Everything ok, add this range identifier to our global pool */ | |
5362 | ranges[kvm->arch.msr_filter.count] = range; | |
5363 | /* Make sure we filled the array before we tell anyone to walk it */ | |
5364 | smp_wmb(); | |
5365 | kvm->arch.msr_filter.count++; | |
5366 | ||
5367 | return 0; | |
5368 | err: | |
5369 | kfree(bitmap); | |
5370 | return r; | |
5371 | } | |
5372 | ||
5373 | static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) | |
5374 | { | |
5375 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
5376 | struct kvm_msr_filter filter; | |
5377 | bool default_allow; | |
5378 | int r = 0; | |
043248b3 | 5379 | bool empty = true; |
1a155254 AG |
5380 | u32 i; |
5381 | ||
5382 | if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) | |
5383 | return -EFAULT; | |
5384 | ||
043248b3 PB |
5385 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) |
5386 | empty &= !filter.ranges[i].nmsrs; | |
1a155254 AG |
5387 | |
5388 | default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); | |
043248b3 PB |
5389 | if (empty && !default_allow) |
5390 | return -EINVAL; | |
5391 | ||
5392 | kvm_clear_msr_filter(kvm); | |
5393 | ||
1a155254 AG |
5394 | kvm->arch.msr_filter.default_allow = default_allow; |
5395 | ||
5396 | /* | |
5397 | * Protect from concurrent calls to this function that could trigger | |
5398 | * a TOCTOU violation on kvm->arch.msr_filter.count. | |
5399 | */ | |
5400 | mutex_lock(&kvm->lock); | |
5401 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { | |
5402 | r = kvm_add_msr_filter(kvm, &filter.ranges[i]); | |
5403 | if (r) | |
5404 | break; | |
5405 | } | |
5406 | ||
5407 | kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); | |
5408 | mutex_unlock(&kvm->lock); | |
5409 | ||
5410 | return r; | |
5411 | } | |
5412 | ||
1fe779f8 CO |
5413 | long kvm_arch_vm_ioctl(struct file *filp, |
5414 | unsigned int ioctl, unsigned long arg) | |
5415 | { | |
5416 | struct kvm *kvm = filp->private_data; | |
5417 | void __user *argp = (void __user *)arg; | |
367e1319 | 5418 | int r = -ENOTTY; |
f0d66275 DH |
5419 | /* |
5420 | * This union makes it completely explicit to gcc-3.x | |
5421 | * that these two variables' stack usage should be | |
5422 | * combined, not added together. | |
5423 | */ | |
5424 | union { | |
5425 | struct kvm_pit_state ps; | |
e9f42757 | 5426 | struct kvm_pit_state2 ps2; |
c5ff41ce | 5427 | struct kvm_pit_config pit_config; |
f0d66275 | 5428 | } u; |
1fe779f8 CO |
5429 | |
5430 | switch (ioctl) { | |
5431 | case KVM_SET_TSS_ADDR: | |
5432 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 5433 | break; |
b927a3ce SY |
5434 | case KVM_SET_IDENTITY_MAP_ADDR: { |
5435 | u64 ident_addr; | |
5436 | ||
1af1ac91 DH |
5437 | mutex_lock(&kvm->lock); |
5438 | r = -EINVAL; | |
5439 | if (kvm->created_vcpus) | |
5440 | goto set_identity_unlock; | |
b927a3ce | 5441 | r = -EFAULT; |
0e96f31e | 5442 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 5443 | goto set_identity_unlock; |
b927a3ce | 5444 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
5445 | set_identity_unlock: |
5446 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
5447 | break; |
5448 | } | |
1fe779f8 CO |
5449 | case KVM_SET_NR_MMU_PAGES: |
5450 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
5451 | break; |
5452 | case KVM_GET_NR_MMU_PAGES: | |
5453 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
5454 | break; | |
3ddea128 | 5455 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 5456 | mutex_lock(&kvm->lock); |
09941366 | 5457 | |
3ddea128 | 5458 | r = -EEXIST; |
35e6eaa3 | 5459 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 5460 | goto create_irqchip_unlock; |
09941366 | 5461 | |
3e515705 | 5462 | r = -EINVAL; |
557abc40 | 5463 | if (kvm->created_vcpus) |
3e515705 | 5464 | goto create_irqchip_unlock; |
09941366 RK |
5465 | |
5466 | r = kvm_pic_init(kvm); | |
5467 | if (r) | |
3ddea128 | 5468 | goto create_irqchip_unlock; |
09941366 RK |
5469 | |
5470 | r = kvm_ioapic_init(kvm); | |
5471 | if (r) { | |
09941366 | 5472 | kvm_pic_destroy(kvm); |
3ddea128 | 5473 | goto create_irqchip_unlock; |
09941366 RK |
5474 | } |
5475 | ||
399ec807 AK |
5476 | r = kvm_setup_default_irq_routing(kvm); |
5477 | if (r) { | |
72bb2fcd | 5478 | kvm_ioapic_destroy(kvm); |
09941366 | 5479 | kvm_pic_destroy(kvm); |
71ba994c | 5480 | goto create_irqchip_unlock; |
399ec807 | 5481 | } |
49776faf | 5482 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 5483 | smp_wmb(); |
49776faf | 5484 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
5485 | create_irqchip_unlock: |
5486 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 5487 | break; |
3ddea128 | 5488 | } |
7837699f | 5489 | case KVM_CREATE_PIT: |
c5ff41ce JK |
5490 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
5491 | goto create_pit; | |
5492 | case KVM_CREATE_PIT2: | |
5493 | r = -EFAULT; | |
5494 | if (copy_from_user(&u.pit_config, argp, | |
5495 | sizeof(struct kvm_pit_config))) | |
5496 | goto out; | |
5497 | create_pit: | |
250715a6 | 5498 | mutex_lock(&kvm->lock); |
269e05e4 AK |
5499 | r = -EEXIST; |
5500 | if (kvm->arch.vpit) | |
5501 | goto create_pit_unlock; | |
7837699f | 5502 | r = -ENOMEM; |
c5ff41ce | 5503 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
5504 | if (kvm->arch.vpit) |
5505 | r = 0; | |
269e05e4 | 5506 | create_pit_unlock: |
250715a6 | 5507 | mutex_unlock(&kvm->lock); |
7837699f | 5508 | break; |
1fe779f8 CO |
5509 | case KVM_GET_IRQCHIP: { |
5510 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5511 | struct kvm_irqchip *chip; |
1fe779f8 | 5512 | |
ff5c2c03 SL |
5513 | chip = memdup_user(argp, sizeof(*chip)); |
5514 | if (IS_ERR(chip)) { | |
5515 | r = PTR_ERR(chip); | |
1fe779f8 | 5516 | goto out; |
ff5c2c03 SL |
5517 | } |
5518 | ||
1fe779f8 | 5519 | r = -ENXIO; |
826da321 | 5520 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5521 | goto get_irqchip_out; |
5522 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 5523 | if (r) |
f0d66275 | 5524 | goto get_irqchip_out; |
1fe779f8 | 5525 | r = -EFAULT; |
0e96f31e | 5526 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 5527 | goto get_irqchip_out; |
1fe779f8 | 5528 | r = 0; |
f0d66275 DH |
5529 | get_irqchip_out: |
5530 | kfree(chip); | |
1fe779f8 CO |
5531 | break; |
5532 | } | |
5533 | case KVM_SET_IRQCHIP: { | |
5534 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5535 | struct kvm_irqchip *chip; |
1fe779f8 | 5536 | |
ff5c2c03 SL |
5537 | chip = memdup_user(argp, sizeof(*chip)); |
5538 | if (IS_ERR(chip)) { | |
5539 | r = PTR_ERR(chip); | |
1fe779f8 | 5540 | goto out; |
ff5c2c03 SL |
5541 | } |
5542 | ||
1fe779f8 | 5543 | r = -ENXIO; |
826da321 | 5544 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5545 | goto set_irqchip_out; |
5546 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
5547 | set_irqchip_out: |
5548 | kfree(chip); | |
1fe779f8 CO |
5549 | break; |
5550 | } | |
e0f63cb9 | 5551 | case KVM_GET_PIT: { |
e0f63cb9 | 5552 | r = -EFAULT; |
f0d66275 | 5553 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5554 | goto out; |
5555 | r = -ENXIO; | |
5556 | if (!kvm->arch.vpit) | |
5557 | goto out; | |
f0d66275 | 5558 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
5559 | if (r) |
5560 | goto out; | |
5561 | r = -EFAULT; | |
f0d66275 | 5562 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5563 | goto out; |
5564 | r = 0; | |
5565 | break; | |
5566 | } | |
5567 | case KVM_SET_PIT: { | |
e0f63cb9 | 5568 | r = -EFAULT; |
0e96f31e | 5569 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 | 5570 | goto out; |
7289fdb5 | 5571 | mutex_lock(&kvm->lock); |
e0f63cb9 SY |
5572 | r = -ENXIO; |
5573 | if (!kvm->arch.vpit) | |
7289fdb5 | 5574 | goto set_pit_out; |
f0d66275 | 5575 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
7289fdb5 SR |
5576 | set_pit_out: |
5577 | mutex_unlock(&kvm->lock); | |
e0f63cb9 SY |
5578 | break; |
5579 | } | |
e9f42757 BK |
5580 | case KVM_GET_PIT2: { |
5581 | r = -ENXIO; | |
5582 | if (!kvm->arch.vpit) | |
5583 | goto out; | |
5584 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
5585 | if (r) | |
5586 | goto out; | |
5587 | r = -EFAULT; | |
5588 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
5589 | goto out; | |
5590 | r = 0; | |
5591 | break; | |
5592 | } | |
5593 | case KVM_SET_PIT2: { | |
5594 | r = -EFAULT; | |
5595 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
5596 | goto out; | |
7289fdb5 | 5597 | mutex_lock(&kvm->lock); |
e9f42757 BK |
5598 | r = -ENXIO; |
5599 | if (!kvm->arch.vpit) | |
7289fdb5 | 5600 | goto set_pit2_out; |
e9f42757 | 5601 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); |
7289fdb5 SR |
5602 | set_pit2_out: |
5603 | mutex_unlock(&kvm->lock); | |
e9f42757 BK |
5604 | break; |
5605 | } | |
52d939a0 MT |
5606 | case KVM_REINJECT_CONTROL: { |
5607 | struct kvm_reinject_control control; | |
5608 | r = -EFAULT; | |
5609 | if (copy_from_user(&control, argp, sizeof(control))) | |
5610 | goto out; | |
cad23e72 ML |
5611 | r = -ENXIO; |
5612 | if (!kvm->arch.vpit) | |
5613 | goto out; | |
52d939a0 | 5614 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
5615 | break; |
5616 | } | |
d71ba788 PB |
5617 | case KVM_SET_BOOT_CPU_ID: |
5618 | r = 0; | |
5619 | mutex_lock(&kvm->lock); | |
557abc40 | 5620 | if (kvm->created_vcpus) |
d71ba788 PB |
5621 | r = -EBUSY; |
5622 | else | |
5623 | kvm->arch.bsp_vcpu_id = arg; | |
5624 | mutex_unlock(&kvm->lock); | |
5625 | break; | |
ffde22ac | 5626 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 5627 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 5628 | r = -EFAULT; |
51776043 | 5629 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac ES |
5630 | goto out; |
5631 | r = -EINVAL; | |
51776043 | 5632 | if (xhc.flags) |
ffde22ac | 5633 | goto out; |
51776043 | 5634 | memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); |
ffde22ac ES |
5635 | r = 0; |
5636 | break; | |
5637 | } | |
afbcf7ab | 5638 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
5639 | struct kvm_clock_data user_ns; |
5640 | u64 now_ns; | |
afbcf7ab GC |
5641 | |
5642 | r = -EFAULT; | |
5643 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
5644 | goto out; | |
5645 | ||
5646 | r = -EINVAL; | |
5647 | if (user_ns.flags) | |
5648 | goto out; | |
5649 | ||
5650 | r = 0; | |
0bc48bea RK |
5651 | /* |
5652 | * TODO: userspace has to take care of races with VCPU_RUN, so | |
5653 | * kvm_gen_update_masterclock() can be cut down to locked | |
5654 | * pvclock_update_vm_gtod_copy(). | |
5655 | */ | |
5656 | kvm_gen_update_masterclock(kvm); | |
e891a32e | 5657 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5658 | kvm->arch.kvmclock_offset += user_ns.clock - now_ns; |
0bc48bea | 5659 | kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); |
afbcf7ab GC |
5660 | break; |
5661 | } | |
5662 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
5663 | struct kvm_clock_data user_ns; |
5664 | u64 now_ns; | |
5665 | ||
e891a32e | 5666 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5667 | user_ns.clock = now_ns; |
e3fd9a93 | 5668 | user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; |
97e69aa6 | 5669 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
5670 | |
5671 | r = -EFAULT; | |
5672 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
5673 | goto out; | |
5674 | r = 0; | |
5675 | break; | |
5676 | } | |
5acc5c06 BS |
5677 | case KVM_MEMORY_ENCRYPT_OP: { |
5678 | r = -ENOTTY; | |
afaf0b2f SC |
5679 | if (kvm_x86_ops.mem_enc_op) |
5680 | r = kvm_x86_ops.mem_enc_op(kvm, argp); | |
5acc5c06 BS |
5681 | break; |
5682 | } | |
69eaedee BS |
5683 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
5684 | struct kvm_enc_region region; | |
5685 | ||
5686 | r = -EFAULT; | |
5687 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5688 | goto out; | |
5689 | ||
5690 | r = -ENOTTY; | |
afaf0b2f SC |
5691 | if (kvm_x86_ops.mem_enc_reg_region) |
5692 | r = kvm_x86_ops.mem_enc_reg_region(kvm, ®ion); | |
69eaedee BS |
5693 | break; |
5694 | } | |
5695 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
5696 | struct kvm_enc_region region; | |
5697 | ||
5698 | r = -EFAULT; | |
5699 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5700 | goto out; | |
5701 | ||
5702 | r = -ENOTTY; | |
afaf0b2f SC |
5703 | if (kvm_x86_ops.mem_enc_unreg_region) |
5704 | r = kvm_x86_ops.mem_enc_unreg_region(kvm, ®ion); | |
69eaedee BS |
5705 | break; |
5706 | } | |
faeb7833 RK |
5707 | case KVM_HYPERV_EVENTFD: { |
5708 | struct kvm_hyperv_eventfd hvevfd; | |
5709 | ||
5710 | r = -EFAULT; | |
5711 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
5712 | goto out; | |
5713 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
5714 | break; | |
5715 | } | |
66bb8a06 EH |
5716 | case KVM_SET_PMU_EVENT_FILTER: |
5717 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
5718 | break; | |
1a155254 AG |
5719 | case KVM_X86_SET_MSR_FILTER: |
5720 | r = kvm_vm_ioctl_set_msr_filter(kvm, argp); | |
5721 | break; | |
1fe779f8 | 5722 | default: |
ad6260da | 5723 | r = -ENOTTY; |
1fe779f8 CO |
5724 | } |
5725 | out: | |
5726 | return r; | |
5727 | } | |
5728 | ||
a16b043c | 5729 | static void kvm_init_msr_list(void) |
043405e1 | 5730 | { |
24c29b7a | 5731 | struct x86_pmu_capability x86_pmu; |
043405e1 | 5732 | u32 dummy[2]; |
7a5ee6ed | 5733 | unsigned i; |
043405e1 | 5734 | |
e2ada66e | 5735 | BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, |
7a5ee6ed | 5736 | "Please update the fixed PMCs in msrs_to_saved_all[]"); |
24c29b7a PB |
5737 | |
5738 | perf_get_x86_pmu_capability(&x86_pmu); | |
e2ada66e | 5739 | |
6cbee2b9 XL |
5740 | num_msrs_to_save = 0; |
5741 | num_emulated_msrs = 0; | |
5742 | num_msr_based_features = 0; | |
5743 | ||
7a5ee6ed CQ |
5744 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { |
5745 | if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) | |
043405e1 | 5746 | continue; |
93c4adc7 PB |
5747 | |
5748 | /* | |
5749 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 5750 | * to the guests in some cases. |
93c4adc7 | 5751 | */ |
7a5ee6ed | 5752 | switch (msrs_to_save_all[i]) { |
93c4adc7 | 5753 | case MSR_IA32_BNDCFGS: |
503234b3 | 5754 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
5755 | continue; |
5756 | break; | |
9dbe6cf9 | 5757 | case MSR_TSC_AUX: |
13908510 | 5758 | if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) |
9dbe6cf9 PB |
5759 | continue; |
5760 | break; | |
f4cfcd2d ML |
5761 | case MSR_IA32_UMWAIT_CONTROL: |
5762 | if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) | |
5763 | continue; | |
5764 | break; | |
bf8c55d8 CP |
5765 | case MSR_IA32_RTIT_CTL: |
5766 | case MSR_IA32_RTIT_STATUS: | |
7b874c26 | 5767 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) |
bf8c55d8 CP |
5768 | continue; |
5769 | break; | |
5770 | case MSR_IA32_RTIT_CR3_MATCH: | |
7b874c26 | 5771 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
5772 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) |
5773 | continue; | |
5774 | break; | |
5775 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
5776 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
7b874c26 | 5777 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
5778 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && |
5779 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
5780 | continue; | |
5781 | break; | |
7cb85fc4 | 5782 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: |
7b874c26 | 5783 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
7a5ee6ed | 5784 | msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= |
bf8c55d8 CP |
5785 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) |
5786 | continue; | |
5787 | break; | |
cf05a67b | 5788 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: |
7a5ee6ed | 5789 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= |
24c29b7a PB |
5790 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
5791 | continue; | |
5792 | break; | |
cf05a67b | 5793 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: |
7a5ee6ed | 5794 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= |
24c29b7a PB |
5795 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
5796 | continue; | |
7cb85fc4 | 5797 | break; |
93c4adc7 PB |
5798 | default: |
5799 | break; | |
5800 | } | |
5801 | ||
7a5ee6ed | 5802 | msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; |
043405e1 | 5803 | } |
62ef68bb | 5804 | |
7a5ee6ed | 5805 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
5719455f | 5806 | if (!kvm_x86_ops.has_emulated_msr(NULL, emulated_msrs_all[i])) |
bc226f07 | 5807 | continue; |
62ef68bb | 5808 | |
7a5ee6ed | 5809 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 5810 | } |
801e459a | 5811 | |
7a5ee6ed | 5812 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { |
801e459a TL |
5813 | struct kvm_msr_entry msr; |
5814 | ||
7a5ee6ed | 5815 | msr.index = msr_based_features_all[i]; |
66421c1e | 5816 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
5817 | continue; |
5818 | ||
7a5ee6ed | 5819 | msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; |
801e459a | 5820 | } |
043405e1 CO |
5821 | } |
5822 | ||
bda9020e MT |
5823 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
5824 | const void *v) | |
bbd9b64e | 5825 | { |
70252a10 AK |
5826 | int handled = 0; |
5827 | int n; | |
5828 | ||
5829 | do { | |
5830 | n = min(len, 8); | |
bce87cce | 5831 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5832 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
5833 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
5834 | break; |
5835 | handled += n; | |
5836 | addr += n; | |
5837 | len -= n; | |
5838 | v += n; | |
5839 | } while (len); | |
bbd9b64e | 5840 | |
70252a10 | 5841 | return handled; |
bbd9b64e CO |
5842 | } |
5843 | ||
bda9020e | 5844 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 5845 | { |
70252a10 AK |
5846 | int handled = 0; |
5847 | int n; | |
5848 | ||
5849 | do { | |
5850 | n = min(len, 8); | |
bce87cce | 5851 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5852 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
5853 | addr, n, v)) | |
5854 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 5855 | break; |
e39d200f | 5856 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
5857 | handled += n; |
5858 | addr += n; | |
5859 | len -= n; | |
5860 | v += n; | |
5861 | } while (len); | |
bbd9b64e | 5862 | |
70252a10 | 5863 | return handled; |
bbd9b64e CO |
5864 | } |
5865 | ||
2dafc6c2 GN |
5866 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
5867 | struct kvm_segment *var, int seg) | |
5868 | { | |
afaf0b2f | 5869 | kvm_x86_ops.set_segment(vcpu, var, seg); |
2dafc6c2 GN |
5870 | } |
5871 | ||
5872 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
5873 | struct kvm_segment *var, int seg) | |
5874 | { | |
afaf0b2f | 5875 | kvm_x86_ops.get_segment(vcpu, var, seg); |
2dafc6c2 GN |
5876 | } |
5877 | ||
54987b7a PB |
5878 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
5879 | struct x86_exception *exception) | |
02f59dc9 JR |
5880 | { |
5881 | gpa_t t_gpa; | |
02f59dc9 JR |
5882 | |
5883 | BUG_ON(!mmu_is_nested(vcpu)); | |
5884 | ||
5885 | /* NPT walks are always user-walks */ | |
5886 | access |= PFERR_USER_MASK; | |
44dd3ffa | 5887 | t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
5888 | |
5889 | return t_gpa; | |
5890 | } | |
5891 | ||
ab9ae313 AK |
5892 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
5893 | struct x86_exception *exception) | |
1871c602 | 5894 | { |
afaf0b2f | 5895 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
ab9ae313 | 5896 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5897 | } |
5898 | ||
ab9ae313 AK |
5899 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
5900 | struct x86_exception *exception) | |
1871c602 | 5901 | { |
afaf0b2f | 5902 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 5903 | access |= PFERR_FETCH_MASK; |
ab9ae313 | 5904 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5905 | } |
5906 | ||
ab9ae313 AK |
5907 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
5908 | struct x86_exception *exception) | |
1871c602 | 5909 | { |
afaf0b2f | 5910 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 5911 | access |= PFERR_WRITE_MASK; |
ab9ae313 | 5912 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5913 | } |
5914 | ||
5915 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
5916 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
5917 | struct x86_exception *exception) | |
1871c602 | 5918 | { |
ab9ae313 | 5919 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
5920 | } |
5921 | ||
5922 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
5923 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 5924 | struct x86_exception *exception) |
bbd9b64e CO |
5925 | { |
5926 | void *data = val; | |
10589a46 | 5927 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
5928 | |
5929 | while (bytes) { | |
14dfe855 | 5930 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 5931 | exception); |
bbd9b64e | 5932 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 5933 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
5934 | int ret; |
5935 | ||
bcc55cba | 5936 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 5937 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
5938 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
5939 | offset, toread); | |
10589a46 | 5940 | if (ret < 0) { |
c3cd7ffa | 5941 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
5942 | goto out; |
5943 | } | |
bbd9b64e | 5944 | |
77c2002e IE |
5945 | bytes -= toread; |
5946 | data += toread; | |
5947 | addr += toread; | |
bbd9b64e | 5948 | } |
10589a46 | 5949 | out: |
10589a46 | 5950 | return r; |
bbd9b64e | 5951 | } |
77c2002e | 5952 | |
1871c602 | 5953 | /* used for instruction fetching */ |
0f65dd70 AK |
5954 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
5955 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 5956 | struct x86_exception *exception) |
1871c602 | 5957 | { |
0f65dd70 | 5958 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
afaf0b2f | 5959 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
5960 | unsigned offset; |
5961 | int ret; | |
0f65dd70 | 5962 | |
44583cba PB |
5963 | /* Inline kvm_read_guest_virt_helper for speed. */ |
5964 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
5965 | exception); | |
5966 | if (unlikely(gpa == UNMAPPED_GVA)) | |
5967 | return X86EMUL_PROPAGATE_FAULT; | |
5968 | ||
5969 | offset = addr & (PAGE_SIZE-1); | |
5970 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
5971 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
5972 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
5973 | offset, bytes); | |
44583cba PB |
5974 | if (unlikely(ret < 0)) |
5975 | return X86EMUL_IO_NEEDED; | |
5976 | ||
5977 | return X86EMUL_CONTINUE; | |
1871c602 GN |
5978 | } |
5979 | ||
ce14e868 | 5980 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 5981 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 5982 | struct x86_exception *exception) |
1871c602 | 5983 | { |
afaf0b2f | 5984 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 5985 | |
353c0956 PB |
5986 | /* |
5987 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
5988 | * is returned, but our callers are not ready for that and they blindly | |
5989 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
5990 | * uninitialized kernel stack memory into cr2 and error code. | |
5991 | */ | |
5992 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 5993 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 5994 | exception); |
1871c602 | 5995 | } |
064aea77 | 5996 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 5997 | |
ce14e868 PB |
5998 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
5999 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 6000 | struct x86_exception *exception, bool system) |
1871c602 | 6001 | { |
0f65dd70 | 6002 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3c9fa24c PB |
6003 | u32 access = 0; |
6004 | ||
afaf0b2f | 6005 | if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) |
3c9fa24c PB |
6006 | access |= PFERR_USER_MASK; |
6007 | ||
6008 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
6009 | } |
6010 | ||
7a036a6f RK |
6011 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
6012 | unsigned long addr, void *val, unsigned int bytes) | |
6013 | { | |
6014 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6015 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
6016 | ||
6017 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
6018 | } | |
6019 | ||
ce14e868 PB |
6020 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
6021 | struct kvm_vcpu *vcpu, u32 access, | |
6022 | struct x86_exception *exception) | |
77c2002e IE |
6023 | { |
6024 | void *data = val; | |
6025 | int r = X86EMUL_CONTINUE; | |
6026 | ||
6027 | while (bytes) { | |
14dfe855 | 6028 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
ce14e868 | 6029 | access, |
ab9ae313 | 6030 | exception); |
77c2002e IE |
6031 | unsigned offset = addr & (PAGE_SIZE-1); |
6032 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
6033 | int ret; | |
6034 | ||
bcc55cba | 6035 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6036 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 6037 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 6038 | if (ret < 0) { |
c3cd7ffa | 6039 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
6040 | goto out; |
6041 | } | |
6042 | ||
6043 | bytes -= towrite; | |
6044 | data += towrite; | |
6045 | addr += towrite; | |
6046 | } | |
6047 | out: | |
6048 | return r; | |
6049 | } | |
ce14e868 PB |
6050 | |
6051 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
6052 | unsigned int bytes, struct x86_exception *exception, |
6053 | bool system) | |
ce14e868 PB |
6054 | { |
6055 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
3c9fa24c PB |
6056 | u32 access = PFERR_WRITE_MASK; |
6057 | ||
afaf0b2f | 6058 | if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) |
3c9fa24c | 6059 | access |= PFERR_USER_MASK; |
ce14e868 PB |
6060 | |
6061 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 6062 | access, exception); |
ce14e868 PB |
6063 | } |
6064 | ||
6065 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
6066 | unsigned int bytes, struct x86_exception *exception) | |
6067 | { | |
c595ceee PB |
6068 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
6069 | vcpu->arch.l1tf_flush_l1d = true; | |
6070 | ||
ce14e868 PB |
6071 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
6072 | PFERR_WRITE_MASK, exception); | |
6073 | } | |
6a4d7550 | 6074 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 6075 | |
082d06ed WL |
6076 | int handle_ud(struct kvm_vcpu *vcpu) |
6077 | { | |
b3dc0695 | 6078 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
6c86eedc | 6079 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
6080 | char sig[5]; /* ud2; .ascii "kvm" */ |
6081 | struct x86_exception e; | |
6082 | ||
09e3e2a1 SC |
6083 | if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, NULL, 0))) |
6084 | return 1; | |
6085 | ||
6c86eedc | 6086 | if (force_emulation_prefix && |
3c9fa24c PB |
6087 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
6088 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 6089 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
6c86eedc | 6090 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 6091 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 6092 | } |
082d06ed | 6093 | |
60fc3d02 | 6094 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
6095 | } |
6096 | EXPORT_SYMBOL_GPL(handle_ud); | |
6097 | ||
0f89b207 TL |
6098 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6099 | gpa_t gpa, bool write) | |
6100 | { | |
6101 | /* For APIC access vmexit */ | |
6102 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6103 | return 1; | |
6104 | ||
6105 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
6106 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
6107 | return 1; | |
6108 | } | |
6109 | ||
6110 | return 0; | |
6111 | } | |
6112 | ||
af7cc7d1 XG |
6113 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6114 | gpa_t *gpa, struct x86_exception *exception, | |
6115 | bool write) | |
6116 | { | |
afaf0b2f | 6117 | u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
97d64b78 | 6118 | | (write ? PFERR_WRITE_MASK : 0); |
af7cc7d1 | 6119 | |
be94f6b7 HH |
6120 | /* |
6121 | * currently PKRU is only applied to ept enabled guest so | |
6122 | * there is no pkey in EPT page table for L1 guest or EPT | |
6123 | * shadow page table for L2 guest. | |
6124 | */ | |
97d64b78 | 6125 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 | 6126 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
871bd034 | 6127 | vcpu->arch.mmio_access, 0, access)) { |
bebb106a XG |
6128 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
6129 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 6130 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
6131 | return 1; |
6132 | } | |
6133 | ||
af7cc7d1 XG |
6134 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
6135 | ||
6136 | if (*gpa == UNMAPPED_GVA) | |
6137 | return -1; | |
6138 | ||
0f89b207 | 6139 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
6140 | } |
6141 | ||
3200f405 | 6142 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 6143 | const void *val, int bytes) |
bbd9b64e CO |
6144 | { |
6145 | int ret; | |
6146 | ||
54bf36aa | 6147 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 6148 | if (ret < 0) |
bbd9b64e | 6149 | return 0; |
0eb05bf2 | 6150 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
6151 | return 1; |
6152 | } | |
6153 | ||
77d197b2 XG |
6154 | struct read_write_emulator_ops { |
6155 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
6156 | int bytes); | |
6157 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6158 | void *val, int bytes); | |
6159 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6160 | int bytes, void *val); | |
6161 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6162 | void *val, int bytes); | |
6163 | bool write; | |
6164 | }; | |
6165 | ||
6166 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
6167 | { | |
6168 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 6169 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 6170 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
6171 | vcpu->mmio_read_completed = 0; |
6172 | return 1; | |
6173 | } | |
6174 | ||
6175 | return 0; | |
6176 | } | |
6177 | ||
6178 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6179 | void *val, int bytes) | |
6180 | { | |
54bf36aa | 6181 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
6182 | } |
6183 | ||
6184 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6185 | void *val, int bytes) | |
6186 | { | |
6187 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
6188 | } | |
6189 | ||
6190 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
6191 | { | |
e39d200f | 6192 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
6193 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
6194 | } | |
6195 | ||
6196 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6197 | void *val, int bytes) | |
6198 | { | |
e39d200f | 6199 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
6200 | return X86EMUL_IO_NEEDED; |
6201 | } | |
6202 | ||
6203 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6204 | void *val, int bytes) | |
6205 | { | |
f78146b0 AK |
6206 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
6207 | ||
87da7e66 | 6208 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
6209 | return X86EMUL_CONTINUE; |
6210 | } | |
6211 | ||
0fbe9b0b | 6212 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
6213 | .read_write_prepare = read_prepare, |
6214 | .read_write_emulate = read_emulate, | |
6215 | .read_write_mmio = vcpu_mmio_read, | |
6216 | .read_write_exit_mmio = read_exit_mmio, | |
6217 | }; | |
6218 | ||
0fbe9b0b | 6219 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
6220 | .read_write_emulate = write_emulate, |
6221 | .read_write_mmio = write_mmio, | |
6222 | .read_write_exit_mmio = write_exit_mmio, | |
6223 | .write = true, | |
6224 | }; | |
6225 | ||
22388a3c XG |
6226 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
6227 | unsigned int bytes, | |
6228 | struct x86_exception *exception, | |
6229 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 6230 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6231 | { |
af7cc7d1 XG |
6232 | gpa_t gpa; |
6233 | int handled, ret; | |
22388a3c | 6234 | bool write = ops->write; |
f78146b0 | 6235 | struct kvm_mmio_fragment *frag; |
c9b8b07c | 6236 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
0f89b207 TL |
6237 | |
6238 | /* | |
6239 | * If the exit was due to a NPF we may already have a GPA. | |
6240 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
6241 | * Note, this cannot be used on string operations since string | |
6242 | * operation using rep will only have the initial GPA from the NPF | |
6243 | * occurred. | |
6244 | */ | |
744e699c SC |
6245 | if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && |
6246 | (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { | |
6247 | gpa = ctxt->gpa_val; | |
618232e2 BS |
6248 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); |
6249 | } else { | |
6250 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
6251 | if (ret < 0) | |
6252 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 6253 | } |
10589a46 | 6254 | |
618232e2 | 6255 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
6256 | return X86EMUL_CONTINUE; |
6257 | ||
bbd9b64e CO |
6258 | /* |
6259 | * Is this MMIO handled locally? | |
6260 | */ | |
22388a3c | 6261 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 6262 | if (handled == bytes) |
bbd9b64e | 6263 | return X86EMUL_CONTINUE; |
bbd9b64e | 6264 | |
70252a10 AK |
6265 | gpa += handled; |
6266 | bytes -= handled; | |
6267 | val += handled; | |
6268 | ||
87da7e66 XG |
6269 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
6270 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
6271 | frag->gpa = gpa; | |
6272 | frag->data = val; | |
6273 | frag->len = bytes; | |
f78146b0 | 6274 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
6275 | } |
6276 | ||
52eb5a6d XL |
6277 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
6278 | unsigned long addr, | |
22388a3c XG |
6279 | void *val, unsigned int bytes, |
6280 | struct x86_exception *exception, | |
0fbe9b0b | 6281 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6282 | { |
0f65dd70 | 6283 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
6284 | gpa_t gpa; |
6285 | int rc; | |
6286 | ||
6287 | if (ops->read_write_prepare && | |
6288 | ops->read_write_prepare(vcpu, val, bytes)) | |
6289 | return X86EMUL_CONTINUE; | |
6290 | ||
6291 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 6292 | |
bbd9b64e CO |
6293 | /* Crossing a page boundary? */ |
6294 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 6295 | int now; |
bbd9b64e CO |
6296 | |
6297 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
6298 | rc = emulator_read_write_onepage(addr, val, now, exception, |
6299 | vcpu, ops); | |
6300 | ||
bbd9b64e CO |
6301 | if (rc != X86EMUL_CONTINUE) |
6302 | return rc; | |
6303 | addr += now; | |
bac15531 NA |
6304 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6305 | addr = (u32)addr; | |
bbd9b64e CO |
6306 | val += now; |
6307 | bytes -= now; | |
6308 | } | |
22388a3c | 6309 | |
f78146b0 AK |
6310 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
6311 | vcpu, ops); | |
6312 | if (rc != X86EMUL_CONTINUE) | |
6313 | return rc; | |
6314 | ||
6315 | if (!vcpu->mmio_nr_fragments) | |
6316 | return rc; | |
6317 | ||
6318 | gpa = vcpu->mmio_fragments[0].gpa; | |
6319 | ||
6320 | vcpu->mmio_needed = 1; | |
6321 | vcpu->mmio_cur_fragment = 0; | |
6322 | ||
87da7e66 | 6323 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
6324 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
6325 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
6326 | vcpu->run->mmio.phys_addr = gpa; | |
6327 | ||
6328 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
6329 | } |
6330 | ||
6331 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
6332 | unsigned long addr, | |
6333 | void *val, | |
6334 | unsigned int bytes, | |
6335 | struct x86_exception *exception) | |
6336 | { | |
6337 | return emulator_read_write(ctxt, addr, val, bytes, | |
6338 | exception, &read_emultor); | |
6339 | } | |
6340 | ||
52eb5a6d | 6341 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
6342 | unsigned long addr, |
6343 | const void *val, | |
6344 | unsigned int bytes, | |
6345 | struct x86_exception *exception) | |
6346 | { | |
6347 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
6348 | exception, &write_emultor); | |
bbd9b64e | 6349 | } |
bbd9b64e | 6350 | |
daea3e73 AK |
6351 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
6352 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
6353 | ||
6354 | #ifdef CONFIG_X86_64 | |
6355 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
6356 | #else | |
6357 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 6358 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
6359 | #endif |
6360 | ||
0f65dd70 AK |
6361 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
6362 | unsigned long addr, | |
bbd9b64e CO |
6363 | const void *old, |
6364 | const void *new, | |
6365 | unsigned int bytes, | |
0f65dd70 | 6366 | struct x86_exception *exception) |
bbd9b64e | 6367 | { |
42e35f80 | 6368 | struct kvm_host_map map; |
0f65dd70 | 6369 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
9de6fe3c | 6370 | u64 page_line_mask; |
daea3e73 | 6371 | gpa_t gpa; |
daea3e73 AK |
6372 | char *kaddr; |
6373 | bool exchanged; | |
2bacc55c | 6374 | |
daea3e73 AK |
6375 | /* guests cmpxchg8b have to be emulated atomically */ |
6376 | if (bytes > 8 || (bytes & (bytes - 1))) | |
6377 | goto emul_write; | |
10589a46 | 6378 | |
daea3e73 | 6379 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 6380 | |
daea3e73 AK |
6381 | if (gpa == UNMAPPED_GVA || |
6382 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6383 | goto emul_write; | |
2bacc55c | 6384 | |
9de6fe3c XL |
6385 | /* |
6386 | * Emulate the atomic as a straight write to avoid #AC if SLD is | |
6387 | * enabled in the host and the access splits a cache line. | |
6388 | */ | |
6389 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
6390 | page_line_mask = ~(cache_line_size() - 1); | |
6391 | else | |
6392 | page_line_mask = PAGE_MASK; | |
6393 | ||
6394 | if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) | |
daea3e73 | 6395 | goto emul_write; |
72dc67a6 | 6396 | |
42e35f80 | 6397 | if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) |
c19b8bd6 | 6398 | goto emul_write; |
72dc67a6 | 6399 | |
42e35f80 KA |
6400 | kaddr = map.hva + offset_in_page(gpa); |
6401 | ||
daea3e73 AK |
6402 | switch (bytes) { |
6403 | case 1: | |
6404 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
6405 | break; | |
6406 | case 2: | |
6407 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
6408 | break; | |
6409 | case 4: | |
6410 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
6411 | break; | |
6412 | case 8: | |
6413 | exchanged = CMPXCHG64(kaddr, old, new); | |
6414 | break; | |
6415 | default: | |
6416 | BUG(); | |
2bacc55c | 6417 | } |
42e35f80 KA |
6418 | |
6419 | kvm_vcpu_unmap(vcpu, &map, true); | |
daea3e73 AK |
6420 | |
6421 | if (!exchanged) | |
6422 | return X86EMUL_CMPXCHG_FAILED; | |
6423 | ||
0eb05bf2 | 6424 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
6425 | |
6426 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 6427 | |
3200f405 | 6428 | emul_write: |
daea3e73 | 6429 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 6430 | |
0f65dd70 | 6431 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
6432 | } |
6433 | ||
cf8f70bf GN |
6434 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
6435 | { | |
cbfc6c91 | 6436 | int r = 0, i; |
cf8f70bf | 6437 | |
cbfc6c91 WL |
6438 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
6439 | if (vcpu->arch.pio.in) | |
6440 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
6441 | vcpu->arch.pio.size, pd); | |
6442 | else | |
6443 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
6444 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
6445 | pd); | |
6446 | if (r) | |
6447 | break; | |
6448 | pd += vcpu->arch.pio.size; | |
6449 | } | |
cf8f70bf GN |
6450 | return r; |
6451 | } | |
6452 | ||
6f6fbe98 XG |
6453 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
6454 | unsigned short port, void *val, | |
6455 | unsigned int count, bool in) | |
cf8f70bf | 6456 | { |
cf8f70bf | 6457 | vcpu->arch.pio.port = port; |
6f6fbe98 | 6458 | vcpu->arch.pio.in = in; |
7972995b | 6459 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
6460 | vcpu->arch.pio.size = size; |
6461 | ||
6462 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 6463 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6464 | return 1; |
6465 | } | |
6466 | ||
6467 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 6468 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
6469 | vcpu->run->io.size = size; |
6470 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
6471 | vcpu->run->io.count = count; | |
6472 | vcpu->run->io.port = port; | |
6473 | ||
6474 | return 0; | |
6475 | } | |
6476 | ||
2e3bb4d8 SC |
6477 | static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
6478 | unsigned short port, void *val, unsigned int count) | |
cf8f70bf | 6479 | { |
6f6fbe98 | 6480 | int ret; |
ca1d4a9e | 6481 | |
6f6fbe98 XG |
6482 | if (vcpu->arch.pio.count) |
6483 | goto data_avail; | |
cf8f70bf | 6484 | |
cbfc6c91 WL |
6485 | memset(vcpu->arch.pio_data, 0, size * count); |
6486 | ||
6f6fbe98 XG |
6487 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
6488 | if (ret) { | |
6489 | data_avail: | |
6490 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 6491 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 6492 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6493 | return 1; |
6494 | } | |
6495 | ||
cf8f70bf GN |
6496 | return 0; |
6497 | } | |
6498 | ||
2e3bb4d8 SC |
6499 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
6500 | int size, unsigned short port, void *val, | |
6501 | unsigned int count) | |
6f6fbe98 | 6502 | { |
2e3bb4d8 | 6503 | return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); |
6f6fbe98 | 6504 | |
2e3bb4d8 | 6505 | } |
6f6fbe98 | 6506 | |
2e3bb4d8 SC |
6507 | static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, |
6508 | unsigned short port, const void *val, | |
6509 | unsigned int count) | |
6510 | { | |
6f6fbe98 | 6511 | memcpy(vcpu->arch.pio_data, val, size * count); |
1171903d | 6512 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
6513 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
6514 | } | |
6515 | ||
2e3bb4d8 SC |
6516 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
6517 | int size, unsigned short port, | |
6518 | const void *val, unsigned int count) | |
6519 | { | |
6520 | return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); | |
6521 | } | |
6522 | ||
bbd9b64e CO |
6523 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
6524 | { | |
afaf0b2f | 6525 | return kvm_x86_ops.get_segment_base(vcpu, seg); |
bbd9b64e CO |
6526 | } |
6527 | ||
3cb16fe7 | 6528 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 6529 | { |
3cb16fe7 | 6530 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
6531 | } |
6532 | ||
ae6a2375 | 6533 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
6534 | { |
6535 | if (!need_emulate_wbinvd(vcpu)) | |
6536 | return X86EMUL_CONTINUE; | |
6537 | ||
afaf0b2f | 6538 | if (kvm_x86_ops.has_wbinvd_exit()) { |
2eec7343 JK |
6539 | int cpu = get_cpu(); |
6540 | ||
6541 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
6542 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
6543 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 6544 | put_cpu(); |
f5f48ee1 | 6545 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
6546 | } else |
6547 | wbinvd(); | |
f5f48ee1 SY |
6548 | return X86EMUL_CONTINUE; |
6549 | } | |
5cb56059 JS |
6550 | |
6551 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
6552 | { | |
6affcbed KH |
6553 | kvm_emulate_wbinvd_noskip(vcpu); |
6554 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 6555 | } |
f5f48ee1 SY |
6556 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
6557 | ||
5cb56059 JS |
6558 | |
6559 | ||
bcaf5cc5 AK |
6560 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
6561 | { | |
5cb56059 | 6562 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
6563 | } |
6564 | ||
52eb5a6d XL |
6565 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6566 | unsigned long *dest) | |
bbd9b64e | 6567 | { |
16f8a6f9 | 6568 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
6569 | } |
6570 | ||
52eb5a6d XL |
6571 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6572 | unsigned long value) | |
bbd9b64e | 6573 | { |
338dbc97 | 6574 | |
717746e3 | 6575 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
6576 | } |
6577 | ||
52a46617 | 6578 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 6579 | { |
52a46617 | 6580 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
6581 | } |
6582 | ||
717746e3 | 6583 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 6584 | { |
717746e3 | 6585 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
6586 | unsigned long value; |
6587 | ||
6588 | switch (cr) { | |
6589 | case 0: | |
6590 | value = kvm_read_cr0(vcpu); | |
6591 | break; | |
6592 | case 2: | |
6593 | value = vcpu->arch.cr2; | |
6594 | break; | |
6595 | case 3: | |
9f8fe504 | 6596 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
6597 | break; |
6598 | case 4: | |
6599 | value = kvm_read_cr4(vcpu); | |
6600 | break; | |
6601 | case 8: | |
6602 | value = kvm_get_cr8(vcpu); | |
6603 | break; | |
6604 | default: | |
a737f256 | 6605 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
6606 | return 0; |
6607 | } | |
6608 | ||
6609 | return value; | |
6610 | } | |
6611 | ||
717746e3 | 6612 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 6613 | { |
717746e3 | 6614 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
6615 | int res = 0; |
6616 | ||
52a46617 GN |
6617 | switch (cr) { |
6618 | case 0: | |
49a9b07e | 6619 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
6620 | break; |
6621 | case 2: | |
6622 | vcpu->arch.cr2 = val; | |
6623 | break; | |
6624 | case 3: | |
2390218b | 6625 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
6626 | break; |
6627 | case 4: | |
a83b29c6 | 6628 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
6629 | break; |
6630 | case 8: | |
eea1cff9 | 6631 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
6632 | break; |
6633 | default: | |
a737f256 | 6634 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 6635 | res = -1; |
52a46617 | 6636 | } |
0f12244f GN |
6637 | |
6638 | return res; | |
52a46617 GN |
6639 | } |
6640 | ||
717746e3 | 6641 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 6642 | { |
afaf0b2f | 6643 | return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
6644 | } |
6645 | ||
4bff1e86 | 6646 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 6647 | { |
afaf0b2f | 6648 | kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
6649 | } |
6650 | ||
4bff1e86 | 6651 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 6652 | { |
afaf0b2f | 6653 | kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
6654 | } |
6655 | ||
1ac9d0cf AK |
6656 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
6657 | { | |
afaf0b2f | 6658 | kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
6659 | } |
6660 | ||
6661 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
6662 | { | |
afaf0b2f | 6663 | kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
6664 | } |
6665 | ||
4bff1e86 AK |
6666 | static unsigned long emulator_get_cached_segment_base( |
6667 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 6668 | { |
4bff1e86 | 6669 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
6670 | } |
6671 | ||
1aa36616 AK |
6672 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
6673 | struct desc_struct *desc, u32 *base3, | |
6674 | int seg) | |
2dafc6c2 GN |
6675 | { |
6676 | struct kvm_segment var; | |
6677 | ||
4bff1e86 | 6678 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 6679 | *selector = var.selector; |
2dafc6c2 | 6680 | |
378a8b09 GN |
6681 | if (var.unusable) { |
6682 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
6683 | if (base3) |
6684 | *base3 = 0; | |
2dafc6c2 | 6685 | return false; |
378a8b09 | 6686 | } |
2dafc6c2 GN |
6687 | |
6688 | if (var.g) | |
6689 | var.limit >>= 12; | |
6690 | set_desc_limit(desc, var.limit); | |
6691 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
6692 | #ifdef CONFIG_X86_64 |
6693 | if (base3) | |
6694 | *base3 = var.base >> 32; | |
6695 | #endif | |
2dafc6c2 GN |
6696 | desc->type = var.type; |
6697 | desc->s = var.s; | |
6698 | desc->dpl = var.dpl; | |
6699 | desc->p = var.present; | |
6700 | desc->avl = var.avl; | |
6701 | desc->l = var.l; | |
6702 | desc->d = var.db; | |
6703 | desc->g = var.g; | |
6704 | ||
6705 | return true; | |
6706 | } | |
6707 | ||
1aa36616 AK |
6708 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
6709 | struct desc_struct *desc, u32 base3, | |
6710 | int seg) | |
2dafc6c2 | 6711 | { |
4bff1e86 | 6712 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
6713 | struct kvm_segment var; |
6714 | ||
1aa36616 | 6715 | var.selector = selector; |
2dafc6c2 | 6716 | var.base = get_desc_base(desc); |
5601d05b GN |
6717 | #ifdef CONFIG_X86_64 |
6718 | var.base |= ((u64)base3) << 32; | |
6719 | #endif | |
2dafc6c2 GN |
6720 | var.limit = get_desc_limit(desc); |
6721 | if (desc->g) | |
6722 | var.limit = (var.limit << 12) | 0xfff; | |
6723 | var.type = desc->type; | |
2dafc6c2 GN |
6724 | var.dpl = desc->dpl; |
6725 | var.db = desc->d; | |
6726 | var.s = desc->s; | |
6727 | var.l = desc->l; | |
6728 | var.g = desc->g; | |
6729 | var.avl = desc->avl; | |
6730 | var.present = desc->p; | |
6731 | var.unusable = !var.present; | |
6732 | var.padding = 0; | |
6733 | ||
6734 | kvm_set_segment(vcpu, &var, seg); | |
6735 | return; | |
6736 | } | |
6737 | ||
717746e3 AK |
6738 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
6739 | u32 msr_index, u64 *pdata) | |
6740 | { | |
1ae09954 AG |
6741 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6742 | int r; | |
6743 | ||
6744 | r = kvm_get_msr(vcpu, msr_index, pdata); | |
6745 | ||
6746 | if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { | |
6747 | /* Bounce to user space */ | |
6748 | return X86EMUL_IO_NEEDED; | |
6749 | } | |
6750 | ||
6751 | return r; | |
717746e3 AK |
6752 | } |
6753 | ||
6754 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
6755 | u32 msr_index, u64 data) | |
6756 | { | |
1ae09954 AG |
6757 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6758 | int r; | |
6759 | ||
6760 | r = kvm_set_msr(vcpu, msr_index, data); | |
6761 | ||
6762 | if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { | |
6763 | /* Bounce to user space */ | |
6764 | return X86EMUL_IO_NEEDED; | |
6765 | } | |
6766 | ||
6767 | return r; | |
717746e3 AK |
6768 | } |
6769 | ||
64d60670 PB |
6770 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
6771 | { | |
6772 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6773 | ||
6774 | return vcpu->arch.smbase; | |
6775 | } | |
6776 | ||
6777 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
6778 | { | |
6779 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6780 | ||
6781 | vcpu->arch.smbase = smbase; | |
6782 | } | |
6783 | ||
67f4d428 NA |
6784 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
6785 | u32 pmc) | |
6786 | { | |
98ff80f5 | 6787 | return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
6788 | } |
6789 | ||
222d21aa AK |
6790 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
6791 | u32 pmc, u64 *pdata) | |
6792 | { | |
c6702c9d | 6793 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
6794 | } |
6795 | ||
6c3287f7 AK |
6796 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
6797 | { | |
6798 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
6799 | } | |
6800 | ||
2953538e | 6801 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 6802 | struct x86_instruction_info *info, |
c4f035c6 AK |
6803 | enum x86_intercept_stage stage) |
6804 | { | |
afaf0b2f | 6805 | return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage, |
21f1b8f2 | 6806 | &ctxt->exception); |
c4f035c6 AK |
6807 | } |
6808 | ||
e911eb3b | 6809 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
f91af517 SC |
6810 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, |
6811 | bool exact_only) | |
bdb42f5a | 6812 | { |
f91af517 | 6813 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); |
bdb42f5a SB |
6814 | } |
6815 | ||
5ae78e95 SC |
6816 | static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) |
6817 | { | |
6818 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); | |
6819 | } | |
6820 | ||
6821 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) | |
6822 | { | |
6823 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
6824 | } | |
6825 | ||
6826 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
6827 | { | |
6828 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
6829 | } | |
6830 | ||
dd856efa AK |
6831 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
6832 | { | |
6833 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
6834 | } | |
6835 | ||
6836 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
6837 | { | |
6838 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
6839 | } | |
6840 | ||
801806d9 NA |
6841 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
6842 | { | |
afaf0b2f | 6843 | kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked); |
801806d9 NA |
6844 | } |
6845 | ||
6ed071f0 LP |
6846 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
6847 | { | |
6848 | return emul_to_vcpu(ctxt)->arch.hflags; | |
6849 | } | |
6850 | ||
6851 | static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) | |
6852 | { | |
c5833c7a | 6853 | emul_to_vcpu(ctxt)->arch.hflags = emul_flags; |
6ed071f0 LP |
6854 | } |
6855 | ||
ed19321f SC |
6856 | static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, |
6857 | const char *smstate) | |
0234bf88 | 6858 | { |
afaf0b2f | 6859 | return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
6860 | } |
6861 | ||
c5833c7a SC |
6862 | static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) |
6863 | { | |
6864 | kvm_smm_changed(emul_to_vcpu(ctxt)); | |
6865 | } | |
6866 | ||
02d4160f VK |
6867 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
6868 | { | |
6869 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
6870 | } | |
6871 | ||
0225fb50 | 6872 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
6873 | .read_gpr = emulator_read_gpr, |
6874 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
6875 | .read_std = emulator_read_std, |
6876 | .write_std = emulator_write_std, | |
7a036a6f | 6877 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 6878 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
6879 | .read_emulated = emulator_read_emulated, |
6880 | .write_emulated = emulator_write_emulated, | |
6881 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 6882 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
6883 | .pio_in_emulated = emulator_pio_in_emulated, |
6884 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
6885 | .get_segment = emulator_get_segment, |
6886 | .set_segment = emulator_set_segment, | |
5951c442 | 6887 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 6888 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 6889 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
6890 | .set_gdt = emulator_set_gdt, |
6891 | .set_idt = emulator_set_idt, | |
52a46617 GN |
6892 | .get_cr = emulator_get_cr, |
6893 | .set_cr = emulator_set_cr, | |
9c537244 | 6894 | .cpl = emulator_get_cpl, |
35aa5375 GN |
6895 | .get_dr = emulator_get_dr, |
6896 | .set_dr = emulator_set_dr, | |
64d60670 PB |
6897 | .get_smbase = emulator_get_smbase, |
6898 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
6899 | .set_msr = emulator_set_msr, |
6900 | .get_msr = emulator_get_msr, | |
67f4d428 | 6901 | .check_pmc = emulator_check_pmc, |
222d21aa | 6902 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 6903 | .halt = emulator_halt, |
bcaf5cc5 | 6904 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 6905 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 6906 | .intercept = emulator_intercept, |
bdb42f5a | 6907 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
6908 | .guest_has_long_mode = emulator_guest_has_long_mode, |
6909 | .guest_has_movbe = emulator_guest_has_movbe, | |
6910 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
801806d9 | 6911 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 LP |
6912 | .get_hflags = emulator_get_hflags, |
6913 | .set_hflags = emulator_set_hflags, | |
0234bf88 | 6914 | .pre_leave_smm = emulator_pre_leave_smm, |
c5833c7a | 6915 | .post_leave_smm = emulator_post_leave_smm, |
02d4160f | 6916 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
6917 | }; |
6918 | ||
95cb2295 GN |
6919 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
6920 | { | |
afaf0b2f | 6921 | u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); |
95cb2295 GN |
6922 | /* |
6923 | * an sti; sti; sequence only disable interrupts for the first | |
6924 | * instruction. So, if the last instruction, be it emulated or | |
6925 | * not, left the system with the INT_STI flag enabled, it | |
6926 | * means that the last instruction is an sti. We should not | |
6927 | * leave the flag on in this case. The same goes for mov ss | |
6928 | */ | |
37ccdcbe PB |
6929 | if (int_shadow & mask) |
6930 | mask = 0; | |
6addfc42 | 6931 | if (unlikely(int_shadow || mask)) { |
afaf0b2f | 6932 | kvm_x86_ops.set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
6933 | if (!mask) |
6934 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6935 | } | |
95cb2295 GN |
6936 | } |
6937 | ||
ef54bcfe | 6938 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f | 6939 | { |
c9b8b07c | 6940 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
da9cb575 | 6941 | if (ctxt->exception.vector == PF_VECTOR) |
53b3d8e9 | 6942 | return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); |
ef54bcfe PB |
6943 | |
6944 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
6945 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
6946 | ctxt->exception.error_code); | |
54b8486f | 6947 | else |
da9cb575 | 6948 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 6949 | return false; |
54b8486f GN |
6950 | } |
6951 | ||
c9b8b07c SC |
6952 | static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) |
6953 | { | |
6954 | struct x86_emulate_ctxt *ctxt; | |
6955 | ||
6956 | ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); | |
6957 | if (!ctxt) { | |
6958 | pr_err("kvm: failed to allocate vcpu's emulator\n"); | |
6959 | return NULL; | |
6960 | } | |
6961 | ||
6962 | ctxt->vcpu = vcpu; | |
6963 | ctxt->ops = &emulate_ops; | |
6964 | vcpu->arch.emulate_ctxt = ctxt; | |
6965 | ||
6966 | return ctxt; | |
6967 | } | |
6968 | ||
8ec4722d MG |
6969 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
6970 | { | |
c9b8b07c | 6971 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d MG |
6972 | int cs_db, cs_l; |
6973 | ||
afaf0b2f | 6974 | kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
8ec4722d | 6975 | |
744e699c | 6976 | ctxt->gpa_available = false; |
adf52235 | 6977 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
6978 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
6979 | ||
adf52235 TY |
6980 | ctxt->eip = kvm_rip_read(vcpu); |
6981 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
6982 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 6983 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
6984 | cs_db ? X86EMUL_MODE_PROT32 : |
6985 | X86EMUL_MODE_PROT16; | |
a584539b | 6986 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
6987 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
6988 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 6989 | |
dd856efa | 6990 | init_decode_cache(ctxt); |
7ae441ea | 6991 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
6992 | } |
6993 | ||
9497e1f2 | 6994 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 6995 | { |
c9b8b07c | 6996 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
63995653 MG |
6997 | int ret; |
6998 | ||
6999 | init_emulate_ctxt(vcpu); | |
7000 | ||
9dac77fa AK |
7001 | ctxt->op_bytes = 2; |
7002 | ctxt->ad_bytes = 2; | |
7003 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 7004 | ret = emulate_int_real(ctxt, irq); |
63995653 | 7005 | |
9497e1f2 SC |
7006 | if (ret != X86EMUL_CONTINUE) { |
7007 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
7008 | } else { | |
7009 | ctxt->eip = ctxt->_eip; | |
7010 | kvm_rip_write(vcpu, ctxt->eip); | |
7011 | kvm_set_rflags(vcpu, ctxt->eflags); | |
7012 | } | |
63995653 MG |
7013 | } |
7014 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
7015 | ||
e2366171 | 7016 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 7017 | { |
6d77dbfc GN |
7018 | ++vcpu->stat.insn_emulation_fail; |
7019 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 7020 | |
42cbf068 SC |
7021 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
7022 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7023 | return 1; |
42cbf068 | 7024 | } |
e2366171 | 7025 | |
738fece4 SC |
7026 | if (emulation_type & EMULTYPE_SKIP) { |
7027 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7028 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7029 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7030 | return 0; |
738fece4 SC |
7031 | } |
7032 | ||
22da61c9 SC |
7033 | kvm_queue_exception(vcpu, UD_VECTOR); |
7034 | ||
afaf0b2f | 7035 | if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) { |
fc3a9157 JR |
7036 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
7037 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7038 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7039 | return 0; |
fc3a9157 | 7040 | } |
e2366171 | 7041 | |
60fc3d02 | 7042 | return 1; |
6d77dbfc GN |
7043 | } |
7044 | ||
736c291c | 7045 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 GN |
7046 | bool write_fault_to_shadow_pgtable, |
7047 | int emulation_type) | |
a6f177ef | 7048 | { |
736c291c | 7049 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 7050 | kvm_pfn_t pfn; |
a6f177ef | 7051 | |
92daa48b | 7052 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
991eebf9 GN |
7053 | return false; |
7054 | ||
92daa48b SC |
7055 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7056 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7057 | return false; |
7058 | ||
44dd3ffa | 7059 | if (!vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7060 | /* |
7061 | * Write permission should be allowed since only | |
7062 | * write access need to be emulated. | |
7063 | */ | |
736c291c | 7064 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 7065 | |
95b3cf69 XG |
7066 | /* |
7067 | * If the mapping is invalid in guest, let cpu retry | |
7068 | * it to generate fault. | |
7069 | */ | |
7070 | if (gpa == UNMAPPED_GVA) | |
7071 | return true; | |
7072 | } | |
a6f177ef | 7073 | |
8e3d9d06 XG |
7074 | /* |
7075 | * Do not retry the unhandleable instruction if it faults on the | |
7076 | * readonly host memory, otherwise it will goto a infinite loop: | |
7077 | * retry instruction -> write #PF -> emulation fail -> retry | |
7078 | * instruction -> ... | |
7079 | */ | |
7080 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
7081 | |
7082 | /* | |
7083 | * If the instruction failed on the error pfn, it can not be fixed, | |
7084 | * report the error to userspace. | |
7085 | */ | |
7086 | if (is_error_noslot_pfn(pfn)) | |
7087 | return false; | |
7088 | ||
7089 | kvm_release_pfn_clean(pfn); | |
7090 | ||
7091 | /* The instructions are well-emulated on direct mmu. */ | |
44dd3ffa | 7092 | if (vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7093 | unsigned int indirect_shadow_pages; |
7094 | ||
7095 | spin_lock(&vcpu->kvm->mmu_lock); | |
7096 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
7097 | spin_unlock(&vcpu->kvm->mmu_lock); | |
7098 | ||
7099 | if (indirect_shadow_pages) | |
7100 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
7101 | ||
a6f177ef | 7102 | return true; |
8e3d9d06 | 7103 | } |
a6f177ef | 7104 | |
95b3cf69 XG |
7105 | /* |
7106 | * if emulation was due to access to shadowed page table | |
7107 | * and it failed try to unshadow page and re-enter the | |
7108 | * guest to let CPU execute the instruction. | |
7109 | */ | |
7110 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
7111 | |
7112 | /* | |
7113 | * If the access faults on its page table, it can not | |
7114 | * be fixed by unprotecting shadow page and it should | |
7115 | * be reported to userspace. | |
7116 | */ | |
7117 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
7118 | } |
7119 | ||
1cb3f3ae | 7120 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 7121 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
7122 | { |
7123 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 7124 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
7125 | |
7126 | last_retry_eip = vcpu->arch.last_retry_eip; | |
7127 | last_retry_addr = vcpu->arch.last_retry_addr; | |
7128 | ||
7129 | /* | |
7130 | * If the emulation is caused by #PF and it is non-page_table | |
7131 | * writing instruction, it means the VM-EXIT is caused by shadow | |
7132 | * page protected, we can zap the shadow page and retry this | |
7133 | * instruction directly. | |
7134 | * | |
7135 | * Note: if the guest uses a non-page-table modifying instruction | |
7136 | * on the PDE that points to the instruction, then we will unmap | |
7137 | * the instruction and go to an infinite loop. So, we cache the | |
7138 | * last retried eip and the last fault address, if we meet the eip | |
7139 | * and the address again, we can break out of the potential infinite | |
7140 | * loop. | |
7141 | */ | |
7142 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
7143 | ||
92daa48b | 7144 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
1cb3f3ae XG |
7145 | return false; |
7146 | ||
92daa48b SC |
7147 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7148 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7149 | return false; |
7150 | ||
1cb3f3ae XG |
7151 | if (x86_page_table_writing_insn(ctxt)) |
7152 | return false; | |
7153 | ||
736c291c | 7154 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
7155 | return false; |
7156 | ||
7157 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 7158 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 7159 | |
44dd3ffa | 7160 | if (!vcpu->arch.mmu->direct_map) |
736c291c | 7161 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 7162 | |
22368028 | 7163 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
7164 | |
7165 | return true; | |
7166 | } | |
7167 | ||
716d51ab GN |
7168 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
7169 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
7170 | ||
64d60670 | 7171 | static void kvm_smm_changed(struct kvm_vcpu *vcpu) |
a584539b | 7172 | { |
64d60670 | 7173 | if (!(vcpu->arch.hflags & HF_SMM_MASK)) { |
660a5d51 PB |
7174 | /* This is a good place to trace that we are exiting SMM. */ |
7175 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); | |
7176 | ||
c43203ca PB |
7177 | /* Process a latched INIT or SMI, if any. */ |
7178 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 | 7179 | } |
699023e2 PB |
7180 | |
7181 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
7182 | } |
7183 | ||
4a1e10d5 PB |
7184 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
7185 | unsigned long *db) | |
7186 | { | |
7187 | u32 dr6 = 0; | |
7188 | int i; | |
7189 | u32 enable, rwlen; | |
7190 | ||
7191 | enable = dr7; | |
7192 | rwlen = dr7 >> 16; | |
7193 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
7194 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
7195 | dr6 |= (1 << i); | |
7196 | return dr6; | |
7197 | } | |
7198 | ||
120c2c4f | 7199 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
7200 | { |
7201 | struct kvm_run *kvm_run = vcpu->run; | |
7202 | ||
c8401dda PB |
7203 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
7204 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; | |
d5d260c5 | 7205 | kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
c8401dda PB |
7206 | kvm_run->debug.arch.exception = DB_VECTOR; |
7207 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7208 | return 0; |
663f4c61 | 7209 | } |
120c2c4f | 7210 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 7211 | return 1; |
663f4c61 PB |
7212 | } |
7213 | ||
6affcbed KH |
7214 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
7215 | { | |
afaf0b2f | 7216 | unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); |
f8ea7c60 | 7217 | int r; |
6affcbed | 7218 | |
afaf0b2f | 7219 | r = kvm_x86_ops.skip_emulated_instruction(vcpu); |
60fc3d02 | 7220 | if (unlikely(!r)) |
f8ea7c60 | 7221 | return 0; |
c8401dda PB |
7222 | |
7223 | /* | |
7224 | * rflags is the old, "raw" value of the flags. The new value has | |
7225 | * not been saved yet. | |
7226 | * | |
7227 | * This is correct even for TF set by the guest, because "the | |
7228 | * processor will not generate this exception after the instruction | |
7229 | * that sets the TF flag". | |
7230 | */ | |
7231 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 7232 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 7233 | return r; |
6affcbed KH |
7234 | } |
7235 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
7236 | ||
4a1e10d5 PB |
7237 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
7238 | { | |
4a1e10d5 PB |
7239 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
7240 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
7241 | struct kvm_run *kvm_run = vcpu->run; |
7242 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
7243 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7244 | vcpu->arch.guest_debug_dr7, |
7245 | vcpu->arch.eff_db); | |
7246 | ||
7247 | if (dr6 != 0) { | |
6f43ed01 | 7248 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 7249 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
7250 | kvm_run->debug.arch.exception = DB_VECTOR; |
7251 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7252 | *r = 0; |
4a1e10d5 PB |
7253 | return true; |
7254 | } | |
7255 | } | |
7256 | ||
4161a569 NA |
7257 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
7258 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
7259 | unsigned long eip = kvm_get_linear_rip(vcpu); |
7260 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7261 | vcpu->arch.dr7, |
7262 | vcpu->arch.db); | |
7263 | ||
7264 | if (dr6 != 0) { | |
4d5523cf | 7265 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
60fc3d02 | 7266 | *r = 1; |
4a1e10d5 PB |
7267 | return true; |
7268 | } | |
7269 | } | |
7270 | ||
7271 | return false; | |
7272 | } | |
7273 | ||
04789b66 LA |
7274 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
7275 | { | |
2d7921c4 AM |
7276 | switch (ctxt->opcode_len) { |
7277 | case 1: | |
7278 | switch (ctxt->b) { | |
7279 | case 0xe4: /* IN */ | |
7280 | case 0xe5: | |
7281 | case 0xec: | |
7282 | case 0xed: | |
7283 | case 0xe6: /* OUT */ | |
7284 | case 0xe7: | |
7285 | case 0xee: | |
7286 | case 0xef: | |
7287 | case 0x6c: /* INS */ | |
7288 | case 0x6d: | |
7289 | case 0x6e: /* OUTS */ | |
7290 | case 0x6f: | |
7291 | return true; | |
7292 | } | |
7293 | break; | |
7294 | case 2: | |
7295 | switch (ctxt->b) { | |
7296 | case 0x33: /* RDPMC */ | |
7297 | return true; | |
7298 | } | |
7299 | break; | |
04789b66 LA |
7300 | } |
7301 | ||
7302 | return false; | |
7303 | } | |
7304 | ||
736c291c SC |
7305 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
7306 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 7307 | { |
95cb2295 | 7308 | int r; |
c9b8b07c | 7309 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
7ae441ea | 7310 | bool writeback = true; |
09e3e2a1 SC |
7311 | bool write_fault_to_spt; |
7312 | ||
7313 | if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, insn, insn_len))) | |
7314 | return 1; | |
bbd9b64e | 7315 | |
c595ceee PB |
7316 | vcpu->arch.l1tf_flush_l1d = true; |
7317 | ||
93c05d3e XG |
7318 | /* |
7319 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
7320 | * never reused. | |
7321 | */ | |
09e3e2a1 | 7322 | write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
93c05d3e | 7323 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
26eef70c | 7324 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 7325 | |
571008da | 7326 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 7327 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
7328 | |
7329 | /* | |
7330 | * We will reenter on the same instruction since | |
7331 | * we do not set complete_userspace_io. This does not | |
7332 | * handle watchpoints yet, those would be handled in | |
7333 | * the emulate_ops. | |
7334 | */ | |
d391f120 VK |
7335 | if (!(emulation_type & EMULTYPE_SKIP) && |
7336 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
4a1e10d5 PB |
7337 | return r; |
7338 | ||
9d74191a TY |
7339 | ctxt->interruptibility = 0; |
7340 | ctxt->have_exception = false; | |
e0ad0b47 | 7341 | ctxt->exception.vector = -1; |
9d74191a | 7342 | ctxt->perm_ok = false; |
bbd9b64e | 7343 | |
b51e974f | 7344 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 7345 | |
9d74191a | 7346 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 7347 | |
e46479f8 | 7348 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 7349 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 7350 | if (r != EMULATION_OK) { |
b4000606 | 7351 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
7352 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
7353 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 7354 | return 1; |
c83fad65 | 7355 | } |
736c291c SC |
7356 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
7357 | write_fault_to_spt, | |
7358 | emulation_type)) | |
60fc3d02 | 7359 | return 1; |
8530a79c | 7360 | if (ctxt->have_exception) { |
c8848cee JD |
7361 | /* |
7362 | * #UD should result in just EMULATION_FAILED, and trap-like | |
7363 | * exception should not be encountered during decode. | |
7364 | */ | |
7365 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
7366 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 7367 | inject_emulated_exception(vcpu); |
60fc3d02 | 7368 | return 1; |
8530a79c | 7369 | } |
e2366171 | 7370 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7371 | } |
7372 | } | |
7373 | ||
42cbf068 SC |
7374 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
7375 | !is_vmware_backdoor_opcode(ctxt)) { | |
7376 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7377 | return 1; |
42cbf068 | 7378 | } |
04789b66 | 7379 | |
1957aa63 SC |
7380 | /* |
7381 | * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks | |
7382 | * for kvm_skip_emulated_instruction(). The caller is responsible for | |
7383 | * updating interruptibility state and injecting single-step #DBs. | |
7384 | */ | |
ba8afb6b | 7385 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 7386 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
7387 | if (ctxt->eflags & X86_EFLAGS_RF) |
7388 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 7389 | return 1; |
ba8afb6b GN |
7390 | } |
7391 | ||
736c291c | 7392 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 7393 | return 1; |
1cb3f3ae | 7394 | |
7ae441ea | 7395 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 7396 | changes registers values during IO operation */ |
7ae441ea GN |
7397 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
7398 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 7399 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 7400 | } |
4d2179e1 | 7401 | |
5cd21917 | 7402 | restart: |
92daa48b SC |
7403 | if (emulation_type & EMULTYPE_PF) { |
7404 | /* Save the faulting GPA (cr2) in the address field */ | |
7405 | ctxt->exception.address = cr2_or_gpa; | |
7406 | ||
7407 | /* With shadow page tables, cr2 contains a GVA or nGPA. */ | |
7408 | if (vcpu->arch.mmu->direct_map) { | |
744e699c SC |
7409 | ctxt->gpa_available = true; |
7410 | ctxt->gpa_val = cr2_or_gpa; | |
92daa48b SC |
7411 | } |
7412 | } else { | |
7413 | /* Sanitize the address out of an abundance of paranoia. */ | |
7414 | ctxt->exception.address = 0; | |
7415 | } | |
0f89b207 | 7416 | |
9d74191a | 7417 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 7418 | |
775fde86 | 7419 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 7420 | return 1; |
775fde86 | 7421 | |
d2ddd1c4 | 7422 | if (r == EMULATION_FAILED) { |
736c291c | 7423 | if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, |
991eebf9 | 7424 | emulation_type)) |
60fc3d02 | 7425 | return 1; |
c3cd7ffa | 7426 | |
e2366171 | 7427 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7428 | } |
7429 | ||
9d74191a | 7430 | if (ctxt->have_exception) { |
60fc3d02 | 7431 | r = 1; |
ef54bcfe PB |
7432 | if (inject_emulated_exception(vcpu)) |
7433 | return r; | |
d2ddd1c4 | 7434 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
7435 | if (!vcpu->arch.pio.in) { |
7436 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 7437 | vcpu->arch.pio.count = 0; |
0912c977 | 7438 | } else { |
7ae441ea | 7439 | writeback = false; |
716d51ab GN |
7440 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
7441 | } | |
60fc3d02 | 7442 | r = 0; |
7ae441ea | 7443 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
7444 | ++vcpu->stat.mmio_exits; |
7445 | ||
7ae441ea GN |
7446 | if (!vcpu->mmio_is_write) |
7447 | writeback = false; | |
60fc3d02 | 7448 | r = 0; |
716d51ab | 7449 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 7450 | } else if (r == EMULATION_RESTART) |
5cd21917 | 7451 | goto restart; |
d2ddd1c4 | 7452 | else |
60fc3d02 | 7453 | r = 1; |
f850e2e6 | 7454 | |
7ae441ea | 7455 | if (writeback) { |
afaf0b2f | 7456 | unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); |
9d74191a | 7457 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 7458 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
38827dbd | 7459 | if (!ctxt->have_exception || |
75ee23b3 SC |
7460 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
7461 | kvm_rip_write(vcpu, ctxt->eip); | |
384dea1c | 7462 | if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) |
120c2c4f | 7463 | r = kvm_vcpu_do_singlestep(vcpu); |
afaf0b2f SC |
7464 | if (kvm_x86_ops.update_emulated_instruction) |
7465 | kvm_x86_ops.update_emulated_instruction(vcpu); | |
38827dbd | 7466 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 7467 | } |
6addfc42 PB |
7468 | |
7469 | /* | |
7470 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
7471 | * do nothing, and it will be requested again as soon as | |
7472 | * the shadow expires. But we still need to check here, | |
7473 | * because POPF has no interrupt shadow. | |
7474 | */ | |
7475 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
7476 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
7477 | } else |
7478 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
7479 | |
7480 | return r; | |
de7d789a | 7481 | } |
c60658d1 SC |
7482 | |
7483 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
7484 | { | |
7485 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
7486 | } | |
7487 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
7488 | ||
7489 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
7490 | void *insn, int insn_len) | |
7491 | { | |
7492 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
7493 | } | |
7494 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 7495 | |
8764ed55 SC |
7496 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
7497 | { | |
7498 | vcpu->arch.pio.count = 0; | |
7499 | return 1; | |
7500 | } | |
7501 | ||
45def77e SC |
7502 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
7503 | { | |
7504 | vcpu->arch.pio.count = 0; | |
7505 | ||
7506 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
7507 | return 1; | |
7508 | ||
7509 | return kvm_skip_emulated_instruction(vcpu); | |
7510 | } | |
7511 | ||
dca7f128 SC |
7512 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
7513 | unsigned short port) | |
de7d789a | 7514 | { |
de3cd117 | 7515 | unsigned long val = kvm_rax_read(vcpu); |
2e3bb4d8 SC |
7516 | int ret = emulator_pio_out(vcpu, size, port, &val, 1); |
7517 | ||
8764ed55 SC |
7518 | if (ret) |
7519 | return ret; | |
45def77e | 7520 | |
8764ed55 SC |
7521 | /* |
7522 | * Workaround userspace that relies on old KVM behavior of %rip being | |
7523 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
7524 | */ | |
7525 | if (port == 0x7e && | |
7526 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
7527 | vcpu->arch.complete_userspace_io = | |
7528 | complete_fast_pio_out_port_0x7e; | |
7529 | kvm_skip_emulated_instruction(vcpu); | |
7530 | } else { | |
45def77e SC |
7531 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
7532 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
7533 | } | |
8764ed55 | 7534 | return 0; |
de7d789a | 7535 | } |
de7d789a | 7536 | |
8370c3d0 TL |
7537 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
7538 | { | |
7539 | unsigned long val; | |
7540 | ||
7541 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
7542 | BUG_ON(vcpu->arch.pio.count != 1); | |
7543 | ||
45def77e SC |
7544 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
7545 | vcpu->arch.pio.count = 0; | |
7546 | return 1; | |
7547 | } | |
7548 | ||
8370c3d0 | 7549 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 7550 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
7551 | |
7552 | /* | |
2e3bb4d8 | 7553 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform |
8370c3d0 TL |
7554 | * the copy and tracing |
7555 | */ | |
2e3bb4d8 | 7556 | emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); |
de3cd117 | 7557 | kvm_rax_write(vcpu, val); |
8370c3d0 | 7558 | |
45def77e | 7559 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
7560 | } |
7561 | ||
dca7f128 SC |
7562 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
7563 | unsigned short port) | |
8370c3d0 TL |
7564 | { |
7565 | unsigned long val; | |
7566 | int ret; | |
7567 | ||
7568 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 7569 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 7570 | |
2e3bb4d8 | 7571 | ret = emulator_pio_in(vcpu, size, port, &val, 1); |
8370c3d0 | 7572 | if (ret) { |
de3cd117 | 7573 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
7574 | return ret; |
7575 | } | |
7576 | ||
45def77e | 7577 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
7578 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
7579 | ||
7580 | return 0; | |
7581 | } | |
dca7f128 SC |
7582 | |
7583 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
7584 | { | |
45def77e | 7585 | int ret; |
dca7f128 | 7586 | |
dca7f128 | 7587 | if (in) |
45def77e | 7588 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 7589 | else |
45def77e SC |
7590 | ret = kvm_fast_pio_out(vcpu, size, port); |
7591 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
7592 | } |
7593 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 7594 | |
251a5fd6 | 7595 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 7596 | { |
0a3aee0d | 7597 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 7598 | return 0; |
8cfdc000 ZA |
7599 | } |
7600 | ||
7601 | static void tsc_khz_changed(void *data) | |
c8076604 | 7602 | { |
8cfdc000 ZA |
7603 | struct cpufreq_freqs *freq = data; |
7604 | unsigned long khz = 0; | |
7605 | ||
7606 | if (data) | |
7607 | khz = freq->new; | |
7608 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
7609 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
7610 | if (!khz) | |
7611 | khz = tsc_khz; | |
0a3aee0d | 7612 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
7613 | } |
7614 | ||
5fa4ec9c | 7615 | #ifdef CONFIG_X86_64 |
0092e434 VK |
7616 | static void kvm_hyperv_tsc_notifier(void) |
7617 | { | |
0092e434 VK |
7618 | struct kvm *kvm; |
7619 | struct kvm_vcpu *vcpu; | |
7620 | int cpu; | |
7621 | ||
0d9ce162 | 7622 | mutex_lock(&kvm_lock); |
0092e434 VK |
7623 | list_for_each_entry(kvm, &vm_list, vm_list) |
7624 | kvm_make_mclock_inprogress_request(kvm); | |
7625 | ||
7626 | hyperv_stop_tsc_emulation(); | |
7627 | ||
7628 | /* TSC frequency always matches when on Hyper-V */ | |
7629 | for_each_present_cpu(cpu) | |
7630 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
7631 | kvm_max_guest_tsc_khz = tsc_khz; | |
7632 | ||
7633 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
7634 | struct kvm_arch *ka = &kvm->arch; | |
7635 | ||
7636 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
7637 | ||
7638 | pvclock_update_vm_gtod_copy(kvm); | |
7639 | ||
7640 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
7641 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
7642 | ||
7643 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
7644 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); | |
7645 | ||
7646 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
7647 | } | |
0d9ce162 | 7648 | mutex_unlock(&kvm_lock); |
0092e434 | 7649 | } |
5fa4ec9c | 7650 | #endif |
0092e434 | 7651 | |
df24014a | 7652 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 7653 | { |
c8076604 GH |
7654 | struct kvm *kvm; |
7655 | struct kvm_vcpu *vcpu; | |
7656 | int i, send_ipi = 0; | |
7657 | ||
8cfdc000 ZA |
7658 | /* |
7659 | * We allow guests to temporarily run on slowing clocks, | |
7660 | * provided we notify them after, or to run on accelerating | |
7661 | * clocks, provided we notify them before. Thus time never | |
7662 | * goes backwards. | |
7663 | * | |
7664 | * However, we have a problem. We can't atomically update | |
7665 | * the frequency of a given CPU from this function; it is | |
7666 | * merely a notifier, which can be called from any CPU. | |
7667 | * Changing the TSC frequency at arbitrary points in time | |
7668 | * requires a recomputation of local variables related to | |
7669 | * the TSC for each VCPU. We must flag these local variables | |
7670 | * to be updated and be sure the update takes place with the | |
7671 | * new frequency before any guests proceed. | |
7672 | * | |
7673 | * Unfortunately, the combination of hotplug CPU and frequency | |
7674 | * change creates an intractable locking scenario; the order | |
7675 | * of when these callouts happen is undefined with respect to | |
7676 | * CPU hotplug, and they can race with each other. As such, | |
7677 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
7678 | * undefined; you can actually have a CPU frequency change take | |
7679 | * place in between the computation of X and the setting of the | |
7680 | * variable. To protect against this problem, all updates of | |
7681 | * the per_cpu tsc_khz variable are done in an interrupt | |
7682 | * protected IPI, and all callers wishing to update the value | |
7683 | * must wait for a synchronous IPI to complete (which is trivial | |
7684 | * if the caller is on the CPU already). This establishes the | |
7685 | * necessary total order on variable updates. | |
7686 | * | |
7687 | * Note that because a guest time update may take place | |
7688 | * anytime after the setting of the VCPU's request bit, the | |
7689 | * correct TSC value must be set before the request. However, | |
7690 | * to ensure the update actually makes it to any guest which | |
7691 | * starts running in hardware virtualization between the set | |
7692 | * and the acquisition of the spinlock, we must also ping the | |
7693 | * CPU after setting the request bit. | |
7694 | * | |
7695 | */ | |
7696 | ||
df24014a | 7697 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 7698 | |
0d9ce162 | 7699 | mutex_lock(&kvm_lock); |
c8076604 | 7700 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 7701 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 7702 | if (vcpu->cpu != cpu) |
c8076604 | 7703 | continue; |
c285545f | 7704 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 7705 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 7706 | send_ipi = 1; |
c8076604 GH |
7707 | } |
7708 | } | |
0d9ce162 | 7709 | mutex_unlock(&kvm_lock); |
c8076604 GH |
7710 | |
7711 | if (freq->old < freq->new && send_ipi) { | |
7712 | /* | |
7713 | * We upscale the frequency. Must make the guest | |
7714 | * doesn't see old kvmclock values while running with | |
7715 | * the new frequency, otherwise we risk the guest sees | |
7716 | * time go backwards. | |
7717 | * | |
7718 | * In case we update the frequency for another cpu | |
7719 | * (which might be in guest context) send an interrupt | |
7720 | * to kick the cpu out of guest context. Next time | |
7721 | * guest context is entered kvmclock will be updated, | |
7722 | * so the guest will not see stale values. | |
7723 | */ | |
df24014a | 7724 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 7725 | } |
df24014a VK |
7726 | } |
7727 | ||
7728 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
7729 | void *data) | |
7730 | { | |
7731 | struct cpufreq_freqs *freq = data; | |
7732 | int cpu; | |
7733 | ||
7734 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
7735 | return 0; | |
7736 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
7737 | return 0; | |
7738 | ||
7739 | for_each_cpu(cpu, freq->policy->cpus) | |
7740 | __kvmclock_cpufreq_notifier(freq, cpu); | |
7741 | ||
c8076604 GH |
7742 | return 0; |
7743 | } | |
7744 | ||
7745 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
7746 | .notifier_call = kvmclock_cpufreq_notifier |
7747 | }; | |
7748 | ||
251a5fd6 | 7749 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 7750 | { |
251a5fd6 SAS |
7751 | tsc_khz_changed(NULL); |
7752 | return 0; | |
8cfdc000 ZA |
7753 | } |
7754 | ||
b820cc0c ZA |
7755 | static void kvm_timer_init(void) |
7756 | { | |
c285545f | 7757 | max_tsc_khz = tsc_khz; |
460dd42e | 7758 | |
b820cc0c | 7759 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f | 7760 | #ifdef CONFIG_CPU_FREQ |
aaec7c03 | 7761 | struct cpufreq_policy *policy; |
758f588d BP |
7762 | int cpu; |
7763 | ||
3e26f230 | 7764 | cpu = get_cpu(); |
aaec7c03 | 7765 | policy = cpufreq_cpu_get(cpu); |
9a11997e WL |
7766 | if (policy) { |
7767 | if (policy->cpuinfo.max_freq) | |
7768 | max_tsc_khz = policy->cpuinfo.max_freq; | |
7769 | cpufreq_cpu_put(policy); | |
7770 | } | |
3e26f230 | 7771 | put_cpu(); |
c285545f | 7772 | #endif |
b820cc0c ZA |
7773 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
7774 | CPUFREQ_TRANSITION_NOTIFIER); | |
7775 | } | |
460dd42e | 7776 | |
73c1b41e | 7777 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 7778 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
7779 | } |
7780 | ||
dd60d217 AK |
7781 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
7782 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 7783 | |
f5132b01 | 7784 | int kvm_is_in_guest(void) |
ff9d07a0 | 7785 | { |
086c9855 | 7786 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
7787 | } |
7788 | ||
7789 | static int kvm_is_user_mode(void) | |
7790 | { | |
7791 | int user_mode = 3; | |
dcf46b94 | 7792 | |
086c9855 | 7793 | if (__this_cpu_read(current_vcpu)) |
afaf0b2f | 7794 | user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu)); |
dcf46b94 | 7795 | |
ff9d07a0 ZY |
7796 | return user_mode != 0; |
7797 | } | |
7798 | ||
7799 | static unsigned long kvm_get_guest_ip(void) | |
7800 | { | |
7801 | unsigned long ip = 0; | |
dcf46b94 | 7802 | |
086c9855 AS |
7803 | if (__this_cpu_read(current_vcpu)) |
7804 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 7805 | |
ff9d07a0 ZY |
7806 | return ip; |
7807 | } | |
7808 | ||
8479e04e LK |
7809 | static void kvm_handle_intel_pt_intr(void) |
7810 | { | |
7811 | struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); | |
7812 | ||
7813 | kvm_make_request(KVM_REQ_PMI, vcpu); | |
7814 | __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, | |
7815 | (unsigned long *)&vcpu->arch.pmu.global_status); | |
7816 | } | |
7817 | ||
ff9d07a0 ZY |
7818 | static struct perf_guest_info_callbacks kvm_guest_cbs = { |
7819 | .is_in_guest = kvm_is_in_guest, | |
7820 | .is_user_mode = kvm_is_user_mode, | |
7821 | .get_guest_ip = kvm_get_guest_ip, | |
8479e04e | 7822 | .handle_intel_pt_intr = kvm_handle_intel_pt_intr, |
ff9d07a0 ZY |
7823 | }; |
7824 | ||
16e8d74d MT |
7825 | #ifdef CONFIG_X86_64 |
7826 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
7827 | { | |
d828199e MT |
7828 | struct kvm *kvm; |
7829 | ||
7830 | struct kvm_vcpu *vcpu; | |
7831 | int i; | |
7832 | ||
0d9ce162 | 7833 | mutex_lock(&kvm_lock); |
d828199e MT |
7834 | list_for_each_entry(kvm, &vm_list, vm_list) |
7835 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 7836 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 7837 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 7838 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
7839 | } |
7840 | ||
7841 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
7842 | ||
7843 | /* | |
7844 | * Notification about pvclock gtod data update. | |
7845 | */ | |
7846 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
7847 | void *priv) | |
7848 | { | |
7849 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
7850 | struct timekeeper *tk = priv; | |
7851 | ||
7852 | update_pvclock_gtod(tk); | |
7853 | ||
7854 | /* disable master clock if host does not trust, or does not | |
b0c39dc6 | 7855 | * use, TSC based clocksource. |
16e8d74d | 7856 | */ |
b0c39dc6 | 7857 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d MT |
7858 | atomic_read(&kvm_guest_has_master_clock) != 0) |
7859 | queue_work(system_long_wq, &pvclock_gtod_work); | |
7860 | ||
7861 | return 0; | |
7862 | } | |
7863 | ||
7864 | static struct notifier_block pvclock_gtod_notifier = { | |
7865 | .notifier_call = pvclock_gtod_notify, | |
7866 | }; | |
7867 | #endif | |
7868 | ||
f8c16bba | 7869 | int kvm_arch_init(void *opaque) |
043405e1 | 7870 | { |
d008dfdb | 7871 | struct kvm_x86_init_ops *ops = opaque; |
b820cc0c | 7872 | int r; |
f8c16bba | 7873 | |
afaf0b2f | 7874 | if (kvm_x86_ops.hardware_enable) { |
f8c16bba | 7875 | printk(KERN_ERR "kvm: already loaded the other module\n"); |
56c6d28a ZX |
7876 | r = -EEXIST; |
7877 | goto out; | |
f8c16bba ZX |
7878 | } |
7879 | ||
7880 | if (!ops->cpu_has_kvm_support()) { | |
ef935c25 | 7881 | pr_err_ratelimited("kvm: no hardware support\n"); |
56c6d28a ZX |
7882 | r = -EOPNOTSUPP; |
7883 | goto out; | |
f8c16bba ZX |
7884 | } |
7885 | if (ops->disabled_by_bios()) { | |
ef935c25 | 7886 | pr_err_ratelimited("kvm: disabled by bios\n"); |
56c6d28a ZX |
7887 | r = -EOPNOTSUPP; |
7888 | goto out; | |
f8c16bba ZX |
7889 | } |
7890 | ||
b666a4b6 MO |
7891 | /* |
7892 | * KVM explicitly assumes that the guest has an FPU and | |
7893 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
7894 | * vCPU's FPU state as a fxregs_state struct. | |
7895 | */ | |
7896 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
7897 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
7898 | r = -EOPNOTSUPP; | |
7899 | goto out; | |
7900 | } | |
7901 | ||
013f6a5d | 7902 | r = -ENOMEM; |
ed8e4812 | 7903 | x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), |
b666a4b6 MO |
7904 | __alignof__(struct fpu), SLAB_ACCOUNT, |
7905 | NULL); | |
7906 | if (!x86_fpu_cache) { | |
7907 | printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); | |
7908 | goto out; | |
7909 | } | |
7910 | ||
c9b8b07c SC |
7911 | x86_emulator_cache = kvm_alloc_emulator_cache(); |
7912 | if (!x86_emulator_cache) { | |
7913 | pr_err("kvm: failed to allocate cache for x86 emulator\n"); | |
7914 | goto out_free_x86_fpu_cache; | |
7915 | } | |
7916 | ||
7e34fbd0 SC |
7917 | user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); |
7918 | if (!user_return_msrs) { | |
7919 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); | |
c9b8b07c | 7920 | goto out_free_x86_emulator_cache; |
013f6a5d MT |
7921 | } |
7922 | ||
97db56ce AK |
7923 | r = kvm_mmu_module_init(); |
7924 | if (r) | |
013f6a5d | 7925 | goto out_free_percpu; |
97db56ce | 7926 | |
7b52345e | 7927 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
ffb128c8 | 7928 | PT_DIRTY_MASK, PT64_NX_MASK, 0, |
d0ec49d4 | 7929 | PT_PRESENT_MASK, 0, sme_me_mask); |
b820cc0c | 7930 | kvm_timer_init(); |
c8076604 | 7931 | |
ff9d07a0 ZY |
7932 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
7933 | ||
cfc48181 | 7934 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
2acf923e | 7935 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
cfc48181 SC |
7936 | supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; |
7937 | } | |
2acf923e | 7938 | |
c5cc421b | 7939 | kvm_lapic_init(); |
0c5f81da WL |
7940 | if (pi_inject_timer == -1) |
7941 | pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); | |
16e8d74d MT |
7942 | #ifdef CONFIG_X86_64 |
7943 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 7944 | |
5fa4ec9c | 7945 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 7946 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
7947 | #endif |
7948 | ||
f8c16bba | 7949 | return 0; |
56c6d28a | 7950 | |
013f6a5d | 7951 | out_free_percpu: |
7e34fbd0 | 7952 | free_percpu(user_return_msrs); |
c9b8b07c SC |
7953 | out_free_x86_emulator_cache: |
7954 | kmem_cache_destroy(x86_emulator_cache); | |
b666a4b6 MO |
7955 | out_free_x86_fpu_cache: |
7956 | kmem_cache_destroy(x86_fpu_cache); | |
56c6d28a | 7957 | out: |
56c6d28a | 7958 | return r; |
043405e1 | 7959 | } |
8776e519 | 7960 | |
f8c16bba ZX |
7961 | void kvm_arch_exit(void) |
7962 | { | |
0092e434 | 7963 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 7964 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
7965 | clear_hv_tscchange_cb(); |
7966 | #endif | |
cef84c30 | 7967 | kvm_lapic_exit(); |
ff9d07a0 ZY |
7968 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
7969 | ||
888d256e JK |
7970 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
7971 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
7972 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 7973 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
7974 | #ifdef CONFIG_X86_64 |
7975 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
7976 | #endif | |
afaf0b2f | 7977 | kvm_x86_ops.hardware_enable = NULL; |
56c6d28a | 7978 | kvm_mmu_module_exit(); |
7e34fbd0 | 7979 | free_percpu(user_return_msrs); |
b666a4b6 | 7980 | kmem_cache_destroy(x86_fpu_cache); |
56c6d28a | 7981 | } |
f8c16bba | 7982 | |
872f36eb | 7983 | static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) |
8776e519 HB |
7984 | { |
7985 | ++vcpu->stat.halt_exits; | |
35754c98 | 7986 | if (lapic_in_kernel(vcpu)) { |
647daca2 | 7987 | vcpu->arch.mp_state = state; |
8776e519 HB |
7988 | return 1; |
7989 | } else { | |
647daca2 | 7990 | vcpu->run->exit_reason = reason; |
8776e519 HB |
7991 | return 0; |
7992 | } | |
7993 | } | |
647daca2 TL |
7994 | |
7995 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) | |
7996 | { | |
7997 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); | |
7998 | } | |
5cb56059 JS |
7999 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
8000 | ||
8001 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
8002 | { | |
6affcbed KH |
8003 | int ret = kvm_skip_emulated_instruction(vcpu); |
8004 | /* | |
8005 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
8006 | * KVM_EXIT_DEBUG here. | |
8007 | */ | |
8008 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 8009 | } |
8776e519 HB |
8010 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
8011 | ||
647daca2 TL |
8012 | int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) |
8013 | { | |
8014 | int ret = kvm_skip_emulated_instruction(vcpu); | |
8015 | ||
8016 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; | |
8017 | } | |
8018 | EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); | |
8019 | ||
8ef81a9a | 8020 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8021 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
8022 | unsigned long clock_type) | |
8023 | { | |
8024 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 8025 | struct timespec64 ts; |
80fbd89c | 8026 | u64 cycle; |
55dd00a7 MT |
8027 | int ret; |
8028 | ||
8029 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
8030 | return -KVM_EOPNOTSUPP; | |
8031 | ||
8032 | if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) | |
8033 | return -KVM_EOPNOTSUPP; | |
8034 | ||
8035 | clock_pairing.sec = ts.tv_sec; | |
8036 | clock_pairing.nsec = ts.tv_nsec; | |
8037 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
8038 | clock_pairing.flags = 0; | |
bcbfbd8e | 8039 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
8040 | |
8041 | ret = 0; | |
8042 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
8043 | sizeof(struct kvm_clock_pairing))) | |
8044 | ret = -KVM_EFAULT; | |
8045 | ||
8046 | return ret; | |
8047 | } | |
8ef81a9a | 8048 | #endif |
55dd00a7 | 8049 | |
6aef266c SV |
8050 | /* |
8051 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
8052 | * | |
8053 | * @apicid - apicid of vcpu to be kicked. | |
8054 | */ | |
8055 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
8056 | { | |
24d2166b | 8057 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 8058 | |
150a84fe | 8059 | lapic_irq.shorthand = APIC_DEST_NOSHORT; |
c96001c5 | 8060 | lapic_irq.dest_mode = APIC_DEST_PHYSICAL; |
ebd28fcb | 8061 | lapic_irq.level = 0; |
24d2166b | 8062 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 8063 | lapic_irq.msi_redir_hint = false; |
6aef266c | 8064 | |
24d2166b | 8065 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 8066 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
8067 | } |
8068 | ||
4e19c36f SS |
8069 | bool kvm_apicv_activated(struct kvm *kvm) |
8070 | { | |
8071 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
8072 | } | |
8073 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
8074 | ||
8075 | void kvm_apicv_init(struct kvm *kvm, bool enable) | |
8076 | { | |
8077 | if (enable) | |
8078 | clear_bit(APICV_INHIBIT_REASON_DISABLE, | |
8079 | &kvm->arch.apicv_inhibit_reasons); | |
8080 | else | |
8081 | set_bit(APICV_INHIBIT_REASON_DISABLE, | |
8082 | &kvm->arch.apicv_inhibit_reasons); | |
8083 | } | |
8084 | EXPORT_SYMBOL_GPL(kvm_apicv_init); | |
8085 | ||
71506297 WL |
8086 | static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) |
8087 | { | |
8088 | struct kvm_vcpu *target = NULL; | |
8089 | struct kvm_apic_map *map; | |
8090 | ||
8091 | rcu_read_lock(); | |
8092 | map = rcu_dereference(kvm->arch.apic_map); | |
8093 | ||
8094 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
8095 | target = map->phys_map[dest_id]->vcpu; | |
8096 | ||
8097 | rcu_read_unlock(); | |
8098 | ||
266e85a5 | 8099 | if (target && READ_ONCE(target->ready)) |
71506297 WL |
8100 | kvm_vcpu_yield_to(target); |
8101 | } | |
8102 | ||
8776e519 HB |
8103 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
8104 | { | |
8105 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 8106 | int op_64_bit; |
8776e519 | 8107 | |
696ca779 RK |
8108 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
8109 | return kvm_hv_hypercall(vcpu); | |
55cd8e5a | 8110 | |
de3cd117 SC |
8111 | nr = kvm_rax_read(vcpu); |
8112 | a0 = kvm_rbx_read(vcpu); | |
8113 | a1 = kvm_rcx_read(vcpu); | |
8114 | a2 = kvm_rdx_read(vcpu); | |
8115 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 8116 | |
229456fc | 8117 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 8118 | |
a449c7aa NA |
8119 | op_64_bit = is_64_bit_mode(vcpu); |
8120 | if (!op_64_bit) { | |
8776e519 HB |
8121 | nr &= 0xFFFFFFFF; |
8122 | a0 &= 0xFFFFFFFF; | |
8123 | a1 &= 0xFFFFFFFF; | |
8124 | a2 &= 0xFFFFFFFF; | |
8125 | a3 &= 0xFFFFFFFF; | |
8126 | } | |
8127 | ||
afaf0b2f | 8128 | if (kvm_x86_ops.get_cpl(vcpu) != 0) { |
07708c4a | 8129 | ret = -KVM_EPERM; |
696ca779 | 8130 | goto out; |
07708c4a JK |
8131 | } |
8132 | ||
66570e96 OU |
8133 | ret = -KVM_ENOSYS; |
8134 | ||
8776e519 | 8135 | switch (nr) { |
b93463aa AK |
8136 | case KVM_HC_VAPIC_POLL_IRQ: |
8137 | ret = 0; | |
8138 | break; | |
6aef266c | 8139 | case KVM_HC_KICK_CPU: |
66570e96 OU |
8140 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) |
8141 | break; | |
8142 | ||
6aef266c | 8143 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); |
266e85a5 | 8144 | kvm_sched_yield(vcpu->kvm, a1); |
6aef266c SV |
8145 | ret = 0; |
8146 | break; | |
8ef81a9a | 8147 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8148 | case KVM_HC_CLOCK_PAIRING: |
8149 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
8150 | break; | |
1ed199a4 | 8151 | #endif |
4180bf1b | 8152 | case KVM_HC_SEND_IPI: |
66570e96 OU |
8153 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) |
8154 | break; | |
8155 | ||
4180bf1b WL |
8156 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); |
8157 | break; | |
71506297 | 8158 | case KVM_HC_SCHED_YIELD: |
66570e96 OU |
8159 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) |
8160 | break; | |
8161 | ||
71506297 WL |
8162 | kvm_sched_yield(vcpu->kvm, a0); |
8163 | ret = 0; | |
8164 | break; | |
8776e519 HB |
8165 | default: |
8166 | ret = -KVM_ENOSYS; | |
8167 | break; | |
8168 | } | |
696ca779 | 8169 | out: |
a449c7aa NA |
8170 | if (!op_64_bit) |
8171 | ret = (u32)ret; | |
de3cd117 | 8172 | kvm_rax_write(vcpu, ret); |
6356ee0c | 8173 | |
f11c3a8d | 8174 | ++vcpu->stat.hypercalls; |
6356ee0c | 8175 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
8176 | } |
8177 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
8178 | ||
b6785def | 8179 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 8180 | { |
d6aa1000 | 8181 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 8182 | char instruction[3]; |
5fdbf976 | 8183 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 8184 | |
afaf0b2f | 8185 | kvm_x86_ops.patch_hypercall(vcpu, instruction); |
8776e519 | 8186 | |
ce2e852e DV |
8187 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
8188 | &ctxt->exception); | |
8776e519 HB |
8189 | } |
8190 | ||
851ba692 | 8191 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8192 | { |
782d422b MG |
8193 | return vcpu->run->request_interrupt_window && |
8194 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
8195 | } |
8196 | ||
851ba692 | 8197 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8198 | { |
851ba692 AK |
8199 | struct kvm_run *kvm_run = vcpu->run; |
8200 | ||
f1c6366e TL |
8201 | /* |
8202 | * if_flag is obsolete and useless, so do not bother | |
8203 | * setting it for SEV-ES guests. Userspace can just | |
8204 | * use kvm_run->ready_for_interrupt_injection. | |
8205 | */ | |
8206 | kvm_run->if_flag = !vcpu->arch.guest_state_protected | |
8207 | && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; | |
8208 | ||
f077825a | 8209 | kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; |
2d3ad1f4 | 8210 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 8211 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
8212 | kvm_run->ready_for_interrupt_injection = |
8213 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 8214 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
b6c7a5dc HB |
8215 | } |
8216 | ||
95ba8273 GN |
8217 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
8218 | { | |
8219 | int max_irr, tpr; | |
8220 | ||
afaf0b2f | 8221 | if (!kvm_x86_ops.update_cr8_intercept) |
95ba8273 GN |
8222 | return; |
8223 | ||
bce87cce | 8224 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
8225 | return; |
8226 | ||
d62caabb AS |
8227 | if (vcpu->arch.apicv_active) |
8228 | return; | |
8229 | ||
8db3baa2 GN |
8230 | if (!vcpu->arch.apic->vapic_addr) |
8231 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
8232 | else | |
8233 | max_irr = -1; | |
95ba8273 GN |
8234 | |
8235 | if (max_irr != -1) | |
8236 | max_irr >>= 4; | |
8237 | ||
8238 | tpr = kvm_lapic_get_cr8(vcpu); | |
8239 | ||
afaf0b2f | 8240 | kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr); |
95ba8273 GN |
8241 | } |
8242 | ||
c9d40913 | 8243 | static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) |
95ba8273 | 8244 | { |
b6b8a145 | 8245 | int r; |
c6b22f59 | 8246 | bool can_inject = true; |
b6b8a145 | 8247 | |
95ba8273 | 8248 | /* try to reinject previous events if any */ |
664f8e26 | 8249 | |
c6b22f59 | 8250 | if (vcpu->arch.exception.injected) { |
afaf0b2f | 8251 | kvm_x86_ops.queue_exception(vcpu); |
c6b22f59 PB |
8252 | can_inject = false; |
8253 | } | |
664f8e26 | 8254 | /* |
a042c26f LA |
8255 | * Do not inject an NMI or interrupt if there is a pending |
8256 | * exception. Exceptions and interrupts are recognized at | |
8257 | * instruction boundaries, i.e. the start of an instruction. | |
8258 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
8259 | * NMIs and interrupts, i.e. traps are recognized before an | |
8260 | * NMI/interrupt that's pending on the same instruction. | |
8261 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
8262 | * priority, but are only generated (pended) during instruction | |
8263 | * execution, i.e. a pending fault-like exception means the | |
8264 | * fault occurred on the *previous* instruction and must be | |
8265 | * serviced prior to recognizing any new events in order to | |
8266 | * fully complete the previous instruction. | |
664f8e26 | 8267 | */ |
1a680e35 | 8268 | else if (!vcpu->arch.exception.pending) { |
c6b22f59 | 8269 | if (vcpu->arch.nmi_injected) { |
afaf0b2f | 8270 | kvm_x86_ops.set_nmi(vcpu); |
c6b22f59 PB |
8271 | can_inject = false; |
8272 | } else if (vcpu->arch.interrupt.injected) { | |
afaf0b2f | 8273 | kvm_x86_ops.set_irq(vcpu); |
c6b22f59 PB |
8274 | can_inject = false; |
8275 | } | |
664f8e26 WL |
8276 | } |
8277 | ||
3b82b8d7 SC |
8278 | WARN_ON_ONCE(vcpu->arch.exception.injected && |
8279 | vcpu->arch.exception.pending); | |
8280 | ||
1a680e35 LA |
8281 | /* |
8282 | * Call check_nested_events() even if we reinjected a previous event | |
8283 | * in order for caller to determine if it should require immediate-exit | |
8284 | * from L2 to L1 due to pending L1 events which require exit | |
8285 | * from L2 to L1. | |
8286 | */ | |
56083bdf | 8287 | if (is_guest_mode(vcpu)) { |
33b22172 | 8288 | r = kvm_x86_ops.nested_ops->check_events(vcpu); |
c9d40913 PB |
8289 | if (r < 0) |
8290 | goto busy; | |
664f8e26 WL |
8291 | } |
8292 | ||
8293 | /* try to inject new event if pending */ | |
b59bb7bd | 8294 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
8295 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
8296 | vcpu->arch.exception.has_error_code, | |
8297 | vcpu->arch.exception.error_code); | |
d6e8c854 | 8298 | |
664f8e26 WL |
8299 | vcpu->arch.exception.pending = false; |
8300 | vcpu->arch.exception.injected = true; | |
8301 | ||
d6e8c854 NA |
8302 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
8303 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
8304 | X86_EFLAGS_RF); | |
8305 | ||
f10c729f | 8306 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
f10c729f JM |
8307 | kvm_deliver_exception_payload(vcpu); |
8308 | if (vcpu->arch.dr7 & DR7_GD) { | |
8309 | vcpu->arch.dr7 &= ~DR7_GD; | |
8310 | kvm_update_dr7(vcpu); | |
8311 | } | |
6bdf0662 NA |
8312 | } |
8313 | ||
afaf0b2f | 8314 | kvm_x86_ops.queue_exception(vcpu); |
c6b22f59 | 8315 | can_inject = false; |
1a680e35 LA |
8316 | } |
8317 | ||
c9d40913 PB |
8318 | /* |
8319 | * Finally, inject interrupt events. If an event cannot be injected | |
8320 | * due to architectural conditions (e.g. IF=0) a window-open exit | |
8321 | * will re-request KVM_REQ_EVENT. Sometimes however an event is pending | |
8322 | * and can architecturally be injected, but we cannot do it right now: | |
8323 | * an interrupt could have arrived just now and we have to inject it | |
8324 | * as a vmexit, or there could already an event in the queue, which is | |
8325 | * indicated by can_inject. In that case we request an immediate exit | |
8326 | * in order to make progress and get back here for another iteration. | |
8327 | * The kvm_x86_ops hooks communicate this by returning -EBUSY. | |
8328 | */ | |
8329 | if (vcpu->arch.smi_pending) { | |
8330 | r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY; | |
8331 | if (r < 0) | |
8332 | goto busy; | |
8333 | if (r) { | |
8334 | vcpu->arch.smi_pending = false; | |
8335 | ++vcpu->arch.smi_count; | |
8336 | enter_smm(vcpu); | |
8337 | can_inject = false; | |
8338 | } else | |
8339 | kvm_x86_ops.enable_smi_window(vcpu); | |
8340 | } | |
8341 | ||
8342 | if (vcpu->arch.nmi_pending) { | |
8343 | r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY; | |
8344 | if (r < 0) | |
8345 | goto busy; | |
8346 | if (r) { | |
8347 | --vcpu->arch.nmi_pending; | |
8348 | vcpu->arch.nmi_injected = true; | |
8349 | kvm_x86_ops.set_nmi(vcpu); | |
8350 | can_inject = false; | |
8351 | WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0); | |
8352 | } | |
8353 | if (vcpu->arch.nmi_pending) | |
8354 | kvm_x86_ops.enable_nmi_window(vcpu); | |
8355 | } | |
1a680e35 | 8356 | |
c9d40913 PB |
8357 | if (kvm_cpu_has_injectable_intr(vcpu)) { |
8358 | r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY; | |
8359 | if (r < 0) | |
8360 | goto busy; | |
8361 | if (r) { | |
8362 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); | |
8363 | kvm_x86_ops.set_irq(vcpu); | |
8364 | WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0); | |
8365 | } | |
8366 | if (kvm_cpu_has_injectable_intr(vcpu)) | |
8367 | kvm_x86_ops.enable_irq_window(vcpu); | |
95ba8273 | 8368 | } |
ee2cd4b7 | 8369 | |
c9d40913 PB |
8370 | if (is_guest_mode(vcpu) && |
8371 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
8372 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
8373 | *req_immediate_exit = true; | |
8374 | ||
8375 | WARN_ON(vcpu->arch.exception.pending); | |
8376 | return; | |
8377 | ||
8378 | busy: | |
8379 | *req_immediate_exit = true; | |
8380 | return; | |
95ba8273 GN |
8381 | } |
8382 | ||
7460fb4a AK |
8383 | static void process_nmi(struct kvm_vcpu *vcpu) |
8384 | { | |
8385 | unsigned limit = 2; | |
8386 | ||
8387 | /* | |
8388 | * x86 is limited to one NMI running, and one NMI pending after it. | |
8389 | * If an NMI is already in progress, limit further NMIs to just one. | |
8390 | * Otherwise, allow two (and we'll inject the first one immediately). | |
8391 | */ | |
afaf0b2f | 8392 | if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) |
7460fb4a AK |
8393 | limit = 1; |
8394 | ||
8395 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
8396 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
8397 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8398 | } | |
8399 | ||
ee2cd4b7 | 8400 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
8401 | { |
8402 | u32 flags = 0; | |
8403 | flags |= seg->g << 23; | |
8404 | flags |= seg->db << 22; | |
8405 | flags |= seg->l << 21; | |
8406 | flags |= seg->avl << 20; | |
8407 | flags |= seg->present << 15; | |
8408 | flags |= seg->dpl << 13; | |
8409 | flags |= seg->s << 12; | |
8410 | flags |= seg->type << 8; | |
8411 | return flags; | |
8412 | } | |
8413 | ||
ee2cd4b7 | 8414 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
8415 | { |
8416 | struct kvm_segment seg; | |
8417 | int offset; | |
8418 | ||
8419 | kvm_get_segment(vcpu, &seg, n); | |
8420 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
8421 | ||
8422 | if (n < 3) | |
8423 | offset = 0x7f84 + n * 12; | |
8424 | else | |
8425 | offset = 0x7f2c + (n - 3) * 12; | |
8426 | ||
8427 | put_smstate(u32, buf, offset + 8, seg.base); | |
8428 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 8429 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
8430 | } |
8431 | ||
efbb288a | 8432 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 8433 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
8434 | { |
8435 | struct kvm_segment seg; | |
8436 | int offset; | |
8437 | u16 flags; | |
8438 | ||
8439 | kvm_get_segment(vcpu, &seg, n); | |
8440 | offset = 0x7e00 + n * 16; | |
8441 | ||
ee2cd4b7 | 8442 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
8443 | put_smstate(u16, buf, offset, seg.selector); |
8444 | put_smstate(u16, buf, offset + 2, flags); | |
8445 | put_smstate(u32, buf, offset + 4, seg.limit); | |
8446 | put_smstate(u64, buf, offset + 8, seg.base); | |
8447 | } | |
efbb288a | 8448 | #endif |
660a5d51 | 8449 | |
ee2cd4b7 | 8450 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
8451 | { |
8452 | struct desc_ptr dt; | |
8453 | struct kvm_segment seg; | |
8454 | unsigned long val; | |
8455 | int i; | |
8456 | ||
8457 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
8458 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
8459 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
8460 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
8461 | ||
8462 | for (i = 0; i < 8; i++) | |
8463 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); | |
8464 | ||
8465 | kvm_get_dr(vcpu, 6, &val); | |
8466 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
8467 | kvm_get_dr(vcpu, 7, &val); | |
8468 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
8469 | ||
8470 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
8471 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
8472 | put_smstate(u32, buf, 0x7f64, seg.base); | |
8473 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 8474 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
8475 | |
8476 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
8477 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
8478 | put_smstate(u32, buf, 0x7f80, seg.base); | |
8479 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 8480 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 | 8481 | |
afaf0b2f | 8482 | kvm_x86_ops.get_gdt(vcpu, &dt); |
660a5d51 PB |
8483 | put_smstate(u32, buf, 0x7f74, dt.address); |
8484 | put_smstate(u32, buf, 0x7f70, dt.size); | |
8485 | ||
afaf0b2f | 8486 | kvm_x86_ops.get_idt(vcpu, &dt); |
660a5d51 PB |
8487 | put_smstate(u32, buf, 0x7f58, dt.address); |
8488 | put_smstate(u32, buf, 0x7f54, dt.size); | |
8489 | ||
8490 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 8491 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
8492 | |
8493 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
8494 | ||
8495 | /* revision id */ | |
8496 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
8497 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
8498 | } | |
8499 | ||
b68f3cc7 | 8500 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 8501 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 8502 | { |
660a5d51 PB |
8503 | struct desc_ptr dt; |
8504 | struct kvm_segment seg; | |
8505 | unsigned long val; | |
8506 | int i; | |
8507 | ||
8508 | for (i = 0; i < 16; i++) | |
8509 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); | |
8510 | ||
8511 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
8512 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
8513 | ||
8514 | kvm_get_dr(vcpu, 6, &val); | |
8515 | put_smstate(u64, buf, 0x7f68, val); | |
8516 | kvm_get_dr(vcpu, 7, &val); | |
8517 | put_smstate(u64, buf, 0x7f60, val); | |
8518 | ||
8519 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
8520 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
8521 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
8522 | ||
8523 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
8524 | ||
8525 | /* revision id */ | |
8526 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
8527 | ||
8528 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
8529 | ||
8530 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
8531 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 8532 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
8533 | put_smstate(u32, buf, 0x7e94, seg.limit); |
8534 | put_smstate(u64, buf, 0x7e98, seg.base); | |
8535 | ||
afaf0b2f | 8536 | kvm_x86_ops.get_idt(vcpu, &dt); |
660a5d51 PB |
8537 | put_smstate(u32, buf, 0x7e84, dt.size); |
8538 | put_smstate(u64, buf, 0x7e88, dt.address); | |
8539 | ||
8540 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
8541 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 8542 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
8543 | put_smstate(u32, buf, 0x7e74, seg.limit); |
8544 | put_smstate(u64, buf, 0x7e78, seg.base); | |
8545 | ||
afaf0b2f | 8546 | kvm_x86_ops.get_gdt(vcpu, &dt); |
660a5d51 PB |
8547 | put_smstate(u32, buf, 0x7e64, dt.size); |
8548 | put_smstate(u64, buf, 0x7e68, dt.address); | |
8549 | ||
8550 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 8551 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 8552 | } |
b68f3cc7 | 8553 | #endif |
660a5d51 | 8554 | |
ee2cd4b7 | 8555 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 8556 | { |
660a5d51 | 8557 | struct kvm_segment cs, ds; |
18c3626e | 8558 | struct desc_ptr dt; |
660a5d51 PB |
8559 | char buf[512]; |
8560 | u32 cr0; | |
8561 | ||
660a5d51 | 8562 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); |
660a5d51 | 8563 | memset(buf, 0, 512); |
b68f3cc7 | 8564 | #ifdef CONFIG_X86_64 |
d6321d49 | 8565 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 8566 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 8567 | else |
b68f3cc7 | 8568 | #endif |
ee2cd4b7 | 8569 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 8570 | |
0234bf88 LP |
8571 | /* |
8572 | * Give pre_enter_smm() a chance to make ISA-specific changes to the | |
8573 | * vCPU state (e.g. leave guest mode) after we've saved the state into | |
8574 | * the SMM state-save area. | |
8575 | */ | |
afaf0b2f | 8576 | kvm_x86_ops.pre_enter_smm(vcpu, buf); |
0234bf88 LP |
8577 | |
8578 | vcpu->arch.hflags |= HF_SMM_MASK; | |
54bf36aa | 8579 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 | 8580 | |
afaf0b2f | 8581 | if (kvm_x86_ops.get_nmi_mask(vcpu)) |
660a5d51 PB |
8582 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; |
8583 | else | |
afaf0b2f | 8584 | kvm_x86_ops.set_nmi_mask(vcpu, true); |
660a5d51 PB |
8585 | |
8586 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
8587 | kvm_rip_write(vcpu, 0x8000); | |
8588 | ||
8589 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
afaf0b2f | 8590 | kvm_x86_ops.set_cr0(vcpu, cr0); |
660a5d51 PB |
8591 | vcpu->arch.cr0 = cr0; |
8592 | ||
afaf0b2f | 8593 | kvm_x86_ops.set_cr4(vcpu, 0); |
660a5d51 | 8594 | |
18c3626e PB |
8595 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
8596 | dt.address = dt.size = 0; | |
afaf0b2f | 8597 | kvm_x86_ops.set_idt(vcpu, &dt); |
18c3626e | 8598 | |
660a5d51 PB |
8599 | __kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
8600 | ||
8601 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
8602 | cs.base = vcpu->arch.smbase; | |
8603 | ||
8604 | ds.selector = 0; | |
8605 | ds.base = 0; | |
8606 | ||
8607 | cs.limit = ds.limit = 0xffffffff; | |
8608 | cs.type = ds.type = 0x3; | |
8609 | cs.dpl = ds.dpl = 0; | |
8610 | cs.db = ds.db = 0; | |
8611 | cs.s = ds.s = 1; | |
8612 | cs.l = ds.l = 0; | |
8613 | cs.g = ds.g = 1; | |
8614 | cs.avl = ds.avl = 0; | |
8615 | cs.present = ds.present = 1; | |
8616 | cs.unusable = ds.unusable = 0; | |
8617 | cs.padding = ds.padding = 0; | |
8618 | ||
8619 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
8620 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
8621 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
8622 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
8623 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
8624 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
8625 | ||
b68f3cc7 | 8626 | #ifdef CONFIG_X86_64 |
d6321d49 | 8627 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
afaf0b2f | 8628 | kvm_x86_ops.set_efer(vcpu, 0); |
b68f3cc7 | 8629 | #endif |
660a5d51 | 8630 | |
aedbaf4f | 8631 | kvm_update_cpuid_runtime(vcpu); |
660a5d51 | 8632 | kvm_mmu_reset_context(vcpu); |
64d60670 PB |
8633 | } |
8634 | ||
ee2cd4b7 | 8635 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
8636 | { |
8637 | vcpu->arch.smi_pending = true; | |
8638 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8639 | } | |
8640 | ||
7ee30bc1 NNL |
8641 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
8642 | unsigned long *vcpu_bitmap) | |
8643 | { | |
8644 | cpumask_var_t cpus; | |
7ee30bc1 NNL |
8645 | |
8646 | zalloc_cpumask_var(&cpus, GFP_ATOMIC); | |
8647 | ||
db5a95ec | 8648 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, |
54163a34 | 8649 | NULL, vcpu_bitmap, cpus); |
7ee30bc1 NNL |
8650 | |
8651 | free_cpumask_var(cpus); | |
8652 | } | |
8653 | ||
2860c4b1 PB |
8654 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
8655 | { | |
8656 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
8657 | } | |
8658 | ||
8df14af4 SS |
8659 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
8660 | { | |
8661 | if (!lapic_in_kernel(vcpu)) | |
8662 | return; | |
8663 | ||
8664 | vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); | |
8665 | kvm_apic_update_apicv(vcpu); | |
afaf0b2f | 8666 | kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu); |
8df14af4 SS |
8667 | } |
8668 | EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); | |
8669 | ||
8670 | /* | |
8671 | * NOTE: Do not hold any lock prior to calling this. | |
8672 | * | |
8673 | * In particular, kvm_request_apicv_update() expects kvm->srcu not to be | |
8674 | * locked, because it calls __x86_set_memory_region() which does | |
8675 | * synchronize_srcu(&kvm->srcu). | |
8676 | */ | |
8677 | void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) | |
8678 | { | |
7d611233 | 8679 | struct kvm_vcpu *except; |
8e205a6b PB |
8680 | unsigned long old, new, expected; |
8681 | ||
afaf0b2f SC |
8682 | if (!kvm_x86_ops.check_apicv_inhibit_reasons || |
8683 | !kvm_x86_ops.check_apicv_inhibit_reasons(bit)) | |
ef8efd7a SS |
8684 | return; |
8685 | ||
8e205a6b PB |
8686 | old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); |
8687 | do { | |
8688 | expected = new = old; | |
8689 | if (activate) | |
8690 | __clear_bit(bit, &new); | |
8691 | else | |
8692 | __set_bit(bit, &new); | |
8693 | if (new == old) | |
8694 | break; | |
8695 | old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); | |
8696 | } while (old != expected); | |
8697 | ||
8698 | if (!!old == !!new) | |
8699 | return; | |
8df14af4 | 8700 | |
24bbf74c | 8701 | trace_kvm_apicv_update_request(activate, bit); |
afaf0b2f SC |
8702 | if (kvm_x86_ops.pre_update_apicv_exec_ctrl) |
8703 | kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate); | |
7d611233 SS |
8704 | |
8705 | /* | |
8706 | * Sending request to update APICV for all other vcpus, | |
8707 | * while update the calling vcpu immediately instead of | |
8708 | * waiting for another #VMEXIT to handle the request. | |
8709 | */ | |
8710 | except = kvm_get_running_vcpu(); | |
8711 | kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE, | |
8712 | except); | |
8713 | if (except) | |
8714 | kvm_vcpu_update_apicv(except); | |
8df14af4 SS |
8715 | } |
8716 | EXPORT_SYMBOL_GPL(kvm_request_apicv_update); | |
8717 | ||
3d81bc7e | 8718 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 8719 | { |
dcbd3e49 | 8720 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 8721 | return; |
c7c9c56c | 8722 | |
6308630b | 8723 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 8724 | |
b053b2ae | 8725 | if (irqchip_split(vcpu->kvm)) |
6308630b | 8726 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 8727 | else { |
fa59cc00 | 8728 | if (vcpu->arch.apicv_active) |
afaf0b2f | 8729 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
e97f852f WL |
8730 | if (ioapic_in_kernel(vcpu->kvm)) |
8731 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 8732 | } |
e40ff1d6 LA |
8733 | |
8734 | if (is_guest_mode(vcpu)) | |
8735 | vcpu->arch.load_eoi_exitmap_pending = true; | |
8736 | else | |
8737 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
8738 | } | |
8739 | ||
8740 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
8741 | { | |
8742 | u64 eoi_exit_bitmap[4]; | |
8743 | ||
8744 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
8745 | return; | |
8746 | ||
5c919412 AS |
8747 | bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, |
8748 | vcpu_to_synic(vcpu)->vec_bitmap, 256); | |
afaf0b2f | 8749 | kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap); |
c7c9c56c YZ |
8750 | } |
8751 | ||
e649b3f0 ET |
8752 | void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
8753 | unsigned long start, unsigned long end) | |
b1394e74 RK |
8754 | { |
8755 | unsigned long apic_address; | |
8756 | ||
8757 | /* | |
8758 | * The physical address of apic access page is stored in the VMCS. | |
8759 | * Update it when it becomes invalid. | |
8760 | */ | |
8761 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
8762 | if (start <= apic_address && apic_address < end) | |
8763 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
8764 | } | |
8765 | ||
4256f43f TC |
8766 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
8767 | { | |
35754c98 | 8768 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
8769 | return; |
8770 | ||
afaf0b2f | 8771 | if (!kvm_x86_ops.set_apic_access_page_addr) |
4256f43f TC |
8772 | return; |
8773 | ||
a4148b7c | 8774 | kvm_x86_ops.set_apic_access_page_addr(vcpu); |
4256f43f | 8775 | } |
4256f43f | 8776 | |
d264ee0c SC |
8777 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
8778 | { | |
8779 | smp_send_reschedule(vcpu->cpu); | |
8780 | } | |
8781 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
8782 | ||
9357d939 | 8783 | /* |
362c698f | 8784 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
8785 | * exiting to the userspace. Otherwise, the value will be returned to the |
8786 | * userspace. | |
8787 | */ | |
851ba692 | 8788 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
8789 | { |
8790 | int r; | |
62a193ed MG |
8791 | bool req_int_win = |
8792 | dm_request_for_irq_injection(vcpu) && | |
8793 | kvm_cpu_accept_dm_intr(vcpu); | |
404d5d7b | 8794 | fastpath_t exit_fastpath; |
62a193ed | 8795 | |
730dca42 | 8796 | bool req_immediate_exit = false; |
b6c7a5dc | 8797 | |
fb04a1ed PX |
8798 | /* Forbid vmenter if vcpu dirty ring is soft-full */ |
8799 | if (unlikely(vcpu->kvm->dirty_ring_size && | |
8800 | kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { | |
8801 | vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; | |
8802 | trace_kvm_dirty_ring_exit(vcpu); | |
8803 | r = 0; | |
8804 | goto out; | |
8805 | } | |
8806 | ||
2fa6e1e1 | 8807 | if (kvm_request_pending(vcpu)) { |
729c15c2 | 8808 | if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { |
f2c7ef3b ML |
8809 | if (WARN_ON_ONCE(!is_guest_mode(vcpu))) |
8810 | ; | |
8811 | else if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { | |
671ddc70 JM |
8812 | r = 0; |
8813 | goto out; | |
8814 | } | |
8815 | } | |
a8eeb04a | 8816 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 8817 | kvm_mmu_unload(vcpu); |
a8eeb04a | 8818 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 8819 | __kvm_migrate_timers(vcpu); |
d828199e MT |
8820 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
8821 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
8822 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
8823 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
8824 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
8825 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
8826 | if (unlikely(r)) |
8827 | goto out; | |
8828 | } | |
a8eeb04a | 8829 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 8830 | kvm_mmu_sync_roots(vcpu); |
727a7e27 PB |
8831 | if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) |
8832 | kvm_mmu_load_pgd(vcpu); | |
eeeb4f67 | 8833 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { |
7780938c | 8834 | kvm_vcpu_flush_tlb_all(vcpu); |
eeeb4f67 SC |
8835 | |
8836 | /* Flushing all ASIDs flushes the current ASID... */ | |
8837 | kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
8838 | } | |
8839 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) | |
8840 | kvm_vcpu_flush_tlb_current(vcpu); | |
0baedd79 VK |
8841 | if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu)) |
8842 | kvm_vcpu_flush_tlb_guest(vcpu); | |
eeeb4f67 | 8843 | |
a8eeb04a | 8844 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 8845 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
8846 | r = 0; |
8847 | goto out; | |
8848 | } | |
a8eeb04a | 8849 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 8850 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 8851 | vcpu->mmio_needed = 0; |
71c4dfaf JR |
8852 | r = 0; |
8853 | goto out; | |
8854 | } | |
af585b92 GN |
8855 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
8856 | /* Page is swapped out. Do synthetic halt */ | |
8857 | vcpu->arch.apf.halted = true; | |
8858 | r = 1; | |
8859 | goto out; | |
8860 | } | |
c9aaa895 GC |
8861 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
8862 | record_steal_time(vcpu); | |
64d60670 PB |
8863 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
8864 | process_smi(vcpu); | |
7460fb4a AK |
8865 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
8866 | process_nmi(vcpu); | |
f5132b01 | 8867 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 8868 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 8869 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 8870 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
8871 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
8872 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
8873 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 8874 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
8875 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
8876 | vcpu->run->eoi.vector = | |
8877 | vcpu->arch.pending_ioapic_eoi; | |
8878 | r = 0; | |
8879 | goto out; | |
8880 | } | |
8881 | } | |
3d81bc7e YZ |
8882 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
8883 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
8884 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
8885 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
8886 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
8887 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
8888 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
8889 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
8890 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
8891 | r = 0; | |
8892 | goto out; | |
8893 | } | |
e516cebb AS |
8894 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
8895 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
8896 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
8897 | r = 0; | |
8898 | goto out; | |
8899 | } | |
db397571 AS |
8900 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
8901 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; | |
8902 | vcpu->run->hyperv = vcpu->arch.hyperv.exit; | |
8903 | r = 0; | |
8904 | goto out; | |
8905 | } | |
f3b138c5 AS |
8906 | |
8907 | /* | |
8908 | * KVM_REQ_HV_STIMER has to be processed after | |
8909 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
8910 | * depend on the guest clock being up-to-date | |
8911 | */ | |
1f4b34f8 AS |
8912 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
8913 | kvm_hv_process_stimers(vcpu); | |
8df14af4 SS |
8914 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
8915 | kvm_vcpu_update_apicv(vcpu); | |
557a961a VK |
8916 | if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) |
8917 | kvm_check_async_pf_completion(vcpu); | |
1a155254 AG |
8918 | if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) |
8919 | kvm_x86_ops.msr_filter_changed(vcpu); | |
2f52d58c | 8920 | } |
b93463aa | 8921 | |
b463a6f7 | 8922 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
0f1e261e | 8923 | ++vcpu->stat.req_event; |
66450a21 JK |
8924 | kvm_apic_accept_events(vcpu); |
8925 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
8926 | r = 1; | |
8927 | goto out; | |
8928 | } | |
8929 | ||
c9d40913 PB |
8930 | inject_pending_event(vcpu, &req_immediate_exit); |
8931 | if (req_int_win) | |
8932 | kvm_x86_ops.enable_irq_window(vcpu); | |
b463a6f7 AK |
8933 | |
8934 | if (kvm_lapic_enabled(vcpu)) { | |
8935 | update_cr8_intercept(vcpu); | |
8936 | kvm_lapic_sync_to_vapic(vcpu); | |
8937 | } | |
8938 | } | |
8939 | ||
d8368af8 AK |
8940 | r = kvm_mmu_reload(vcpu); |
8941 | if (unlikely(r)) { | |
d905c069 | 8942 | goto cancel_injection; |
d8368af8 AK |
8943 | } |
8944 | ||
b6c7a5dc HB |
8945 | preempt_disable(); |
8946 | ||
afaf0b2f | 8947 | kvm_x86_ops.prepare_guest_switch(vcpu); |
b95234c8 PB |
8948 | |
8949 | /* | |
8950 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
8951 | * IPI are then delayed after guest entry, which ensures that they | |
8952 | * result in virtual interrupt delivery. | |
8953 | */ | |
8954 | local_irq_disable(); | |
6b7e2d09 XG |
8955 | vcpu->mode = IN_GUEST_MODE; |
8956 | ||
01b71917 MT |
8957 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
8958 | ||
0f127d12 | 8959 | /* |
b95234c8 | 8960 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 8961 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 8962 | * |
81b01667 | 8963 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
8964 | * pairs with the memory barrier implicit in pi_test_and_set_on |
8965 | * (see vmx_deliver_posted_interrupt). | |
8966 | * | |
8967 | * 3) This also orders the write to mode from any reads to the page | |
8968 | * tables done while the VCPU is running. Please see the comment | |
8969 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 8970 | */ |
01b71917 | 8971 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 8972 | |
b95234c8 PB |
8973 | /* |
8974 | * This handles the case where a posted interrupt was | |
8975 | * notified with kvm_vcpu_kick. | |
8976 | */ | |
fa59cc00 | 8977 | if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) |
afaf0b2f | 8978 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
32f88400 | 8979 | |
5a9f5443 | 8980 | if (kvm_vcpu_exit_request(vcpu)) { |
6b7e2d09 | 8981 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 8982 | smp_wmb(); |
6c142801 AK |
8983 | local_irq_enable(); |
8984 | preempt_enable(); | |
01b71917 | 8985 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 8986 | r = 1; |
d905c069 | 8987 | goto cancel_injection; |
6c142801 AK |
8988 | } |
8989 | ||
c43203ca PB |
8990 | if (req_immediate_exit) { |
8991 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
afaf0b2f | 8992 | kvm_x86_ops.request_immediate_exit(vcpu); |
c43203ca | 8993 | } |
d6185f20 | 8994 | |
b2d52255 | 8995 | trace_kvm_entry(vcpu); |
b6c7a5dc | 8996 | |
2620fe26 SC |
8997 | fpregs_assert_state_consistent(); |
8998 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
8999 | switch_fpu_return(); | |
5f409e20 | 9000 | |
42dbaa5a | 9001 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
9002 | set_debugreg(0, 7); |
9003 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
9004 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
9005 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
9006 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 9007 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 9008 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 9009 | } |
b6c7a5dc | 9010 | |
a9ab13ff | 9011 | exit_fastpath = kvm_x86_ops.run(vcpu); |
b6c7a5dc | 9012 | |
c77fb5fe PB |
9013 | /* |
9014 | * Do this here before restoring debug registers on the host. And | |
9015 | * since we do this before handling the vmexit, a DR access vmexit | |
9016 | * can (a) read the correct value of the debug registers, (b) set | |
9017 | * KVM_DEBUGREG_WONT_EXIT again. | |
9018 | */ | |
9019 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe | 9020 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
afaf0b2f | 9021 | kvm_x86_ops.sync_dirty_debug_regs(vcpu); |
70e4da7a | 9022 | kvm_update_dr0123(vcpu); |
70e4da7a PB |
9023 | kvm_update_dr7(vcpu); |
9024 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; | |
c77fb5fe PB |
9025 | } |
9026 | ||
24f1e32c FW |
9027 | /* |
9028 | * If the guest has used debug registers, at least dr7 | |
9029 | * will be disabled while returning to the host. | |
9030 | * If we don't have active breakpoints in the host, we don't | |
9031 | * care about the messed up debug address registers. But if | |
9032 | * we have some of them active, restore the old state. | |
9033 | */ | |
59d8eb53 | 9034 | if (hw_breakpoint_active()) |
24f1e32c | 9035 | hw_breakpoint_restore(); |
42dbaa5a | 9036 | |
c967118d | 9037 | vcpu->arch.last_vmentry_cpu = vcpu->cpu; |
4ba76538 | 9038 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 9039 | |
6b7e2d09 | 9040 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9041 | smp_wmb(); |
a547c6db | 9042 | |
a9ab13ff | 9043 | kvm_x86_ops.handle_exit_irqoff(vcpu); |
b6c7a5dc | 9044 | |
d7a08882 SC |
9045 | /* |
9046 | * Consume any pending interrupts, including the possible source of | |
9047 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
9048 | * An instruction is required after local_irq_enable() to fully unblock | |
9049 | * interrupts on processors that implement an interrupt shadow, the | |
9050 | * stat.exits increment will do nicely. | |
9051 | */ | |
9052 | kvm_before_interrupt(vcpu); | |
9053 | local_irq_enable(); | |
b6c7a5dc | 9054 | ++vcpu->stat.exits; |
d7a08882 SC |
9055 | local_irq_disable(); |
9056 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 9057 | |
ec0671d5 WL |
9058 | if (lapic_in_kernel(vcpu)) { |
9059 | s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; | |
9060 | if (delta != S64_MIN) { | |
9061 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); | |
9062 | vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; | |
9063 | } | |
9064 | } | |
b6c7a5dc | 9065 | |
f2485b3e | 9066 | local_irq_enable(); |
b6c7a5dc HB |
9067 | preempt_enable(); |
9068 | ||
f656ce01 | 9069 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 9070 | |
b6c7a5dc HB |
9071 | /* |
9072 | * Profile KVM exit RIPs: | |
9073 | */ | |
9074 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
9075 | unsigned long rip = kvm_rip_read(vcpu); |
9076 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
9077 | } |
9078 | ||
cc578287 ZA |
9079 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
9080 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 9081 | |
5cfb1d5a MT |
9082 | if (vcpu->arch.apic_attention) |
9083 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 9084 | |
afaf0b2f | 9085 | r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath); |
d905c069 MT |
9086 | return r; |
9087 | ||
9088 | cancel_injection: | |
8081ad06 SC |
9089 | if (req_immediate_exit) |
9090 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
afaf0b2f | 9091 | kvm_x86_ops.cancel_injection(vcpu); |
ae7a2a3f MT |
9092 | if (unlikely(vcpu->arch.apic_attention)) |
9093 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
9094 | out: |
9095 | return r; | |
9096 | } | |
b6c7a5dc | 9097 | |
362c698f PB |
9098 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
9099 | { | |
bf9f6ac8 | 9100 | if (!kvm_arch_vcpu_runnable(vcpu) && |
afaf0b2f | 9101 | (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) { |
9c8fd1ba PB |
9102 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
9103 | kvm_vcpu_block(vcpu); | |
9104 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 | 9105 | |
afaf0b2f SC |
9106 | if (kvm_x86_ops.post_block) |
9107 | kvm_x86_ops.post_block(vcpu); | |
bf9f6ac8 | 9108 | |
9c8fd1ba PB |
9109 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
9110 | return 1; | |
9111 | } | |
362c698f PB |
9112 | |
9113 | kvm_apic_accept_events(vcpu); | |
9114 | switch(vcpu->arch.mp_state) { | |
9115 | case KVM_MP_STATE_HALTED: | |
647daca2 | 9116 | case KVM_MP_STATE_AP_RESET_HOLD: |
362c698f PB |
9117 | vcpu->arch.pv.pv_unhalted = false; |
9118 | vcpu->arch.mp_state = | |
9119 | KVM_MP_STATE_RUNNABLE; | |
df561f66 | 9120 | fallthrough; |
362c698f PB |
9121 | case KVM_MP_STATE_RUNNABLE: |
9122 | vcpu->arch.apf.halted = false; | |
9123 | break; | |
9124 | case KVM_MP_STATE_INIT_RECEIVED: | |
9125 | break; | |
9126 | default: | |
9127 | return -EINTR; | |
362c698f PB |
9128 | } |
9129 | return 1; | |
9130 | } | |
09cec754 | 9131 | |
5d9bc648 PB |
9132 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
9133 | { | |
56083bdf | 9134 | if (is_guest_mode(vcpu)) |
33b22172 | 9135 | kvm_x86_ops.nested_ops->check_events(vcpu); |
0ad3bed6 | 9136 | |
5d9bc648 PB |
9137 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
9138 | !vcpu->arch.apf.halted); | |
9139 | } | |
9140 | ||
362c698f | 9141 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
9142 | { |
9143 | int r; | |
f656ce01 | 9144 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 9145 | |
f656ce01 | 9146 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
c595ceee | 9147 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 9148 | |
362c698f | 9149 | for (;;) { |
58f800d5 | 9150 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 9151 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 9152 | } else { |
362c698f | 9153 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
9154 | } |
9155 | ||
09cec754 GN |
9156 | if (r <= 0) |
9157 | break; | |
9158 | ||
72875d8a | 9159 | kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); |
09cec754 GN |
9160 | if (kvm_cpu_has_pending_timer(vcpu)) |
9161 | kvm_inject_pending_timer_irqs(vcpu); | |
9162 | ||
782d422b MG |
9163 | if (dm_request_for_irq_injection(vcpu) && |
9164 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
9165 | r = 0; |
9166 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 9167 | ++vcpu->stat.request_irq_exits; |
362c698f | 9168 | break; |
09cec754 | 9169 | } |
af585b92 | 9170 | |
f3020b88 | 9171 | if (__xfer_to_guest_mode_work_pending()) { |
f656ce01 | 9172 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
72c3c0fe TG |
9173 | r = xfer_to_guest_mode_handle_work(vcpu); |
9174 | if (r) | |
9175 | return r; | |
f656ce01 | 9176 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 9177 | } |
b6c7a5dc HB |
9178 | } |
9179 | ||
f656ce01 | 9180 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
9181 | |
9182 | return r; | |
9183 | } | |
9184 | ||
716d51ab GN |
9185 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
9186 | { | |
9187 | int r; | |
60fc3d02 | 9188 | |
716d51ab | 9189 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
0ce97a2b | 9190 | r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab | 9191 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
60fc3d02 | 9192 | return r; |
716d51ab GN |
9193 | } |
9194 | ||
9195 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
9196 | { | |
9197 | BUG_ON(!vcpu->arch.pio.count); | |
9198 | ||
9199 | return complete_emulated_io(vcpu); | |
9200 | } | |
9201 | ||
f78146b0 AK |
9202 | /* |
9203 | * Implements the following, as a state machine: | |
9204 | * | |
9205 | * read: | |
9206 | * for each fragment | |
87da7e66 XG |
9207 | * for each mmio piece in the fragment |
9208 | * write gpa, len | |
9209 | * exit | |
9210 | * copy data | |
f78146b0 AK |
9211 | * execute insn |
9212 | * | |
9213 | * write: | |
9214 | * for each fragment | |
87da7e66 XG |
9215 | * for each mmio piece in the fragment |
9216 | * write gpa, len | |
9217 | * copy data | |
9218 | * exit | |
f78146b0 | 9219 | */ |
716d51ab | 9220 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
9221 | { |
9222 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 9223 | struct kvm_mmio_fragment *frag; |
87da7e66 | 9224 | unsigned len; |
5287f194 | 9225 | |
716d51ab | 9226 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 9227 | |
716d51ab | 9228 | /* Complete previous fragment */ |
87da7e66 XG |
9229 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
9230 | len = min(8u, frag->len); | |
716d51ab | 9231 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
9232 | memcpy(frag->data, run->mmio.data, len); |
9233 | ||
9234 | if (frag->len <= 8) { | |
9235 | /* Switch to the next fragment. */ | |
9236 | frag++; | |
9237 | vcpu->mmio_cur_fragment++; | |
9238 | } else { | |
9239 | /* Go forward to the next mmio piece. */ | |
9240 | frag->data += len; | |
9241 | frag->gpa += len; | |
9242 | frag->len -= len; | |
9243 | } | |
9244 | ||
a08d3b3b | 9245 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 9246 | vcpu->mmio_needed = 0; |
0912c977 PB |
9247 | |
9248 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 9249 | if (vcpu->mmio_is_write) |
716d51ab GN |
9250 | return 1; |
9251 | vcpu->mmio_read_completed = 1; | |
9252 | return complete_emulated_io(vcpu); | |
9253 | } | |
87da7e66 | 9254 | |
716d51ab GN |
9255 | run->exit_reason = KVM_EXIT_MMIO; |
9256 | run->mmio.phys_addr = frag->gpa; | |
9257 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
9258 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
9259 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
9260 | run->mmio.is_write = vcpu->mmio_is_write; |
9261 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
9262 | return 0; | |
5287f194 AK |
9263 | } |
9264 | ||
c9aef3b8 SC |
9265 | static void kvm_save_current_fpu(struct fpu *fpu) |
9266 | { | |
9267 | /* | |
9268 | * If the target FPU state is not resident in the CPU registers, just | |
9269 | * memcpy() from current, else save CPU state directly to the target. | |
9270 | */ | |
9271 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9272 | memcpy(&fpu->state, ¤t->thread.fpu.state, | |
9273 | fpu_kernel_xstate_size); | |
9274 | else | |
9275 | copy_fpregs_to_fpstate(fpu); | |
9276 | } | |
9277 | ||
822f312d SAS |
9278 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
9279 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
9280 | { | |
5f409e20 RR |
9281 | fpregs_lock(); |
9282 | ||
c9aef3b8 SC |
9283 | kvm_save_current_fpu(vcpu->arch.user_fpu); |
9284 | ||
ed02b213 TL |
9285 | /* |
9286 | * Guests with protected state can't have it set by the hypervisor, | |
9287 | * so skip trying to set it. | |
9288 | */ | |
9289 | if (vcpu->arch.guest_fpu) | |
9290 | /* PKRU is separately restored in kvm_x86_ops.run. */ | |
9291 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, | |
9292 | ~XFEATURE_MASK_PKRU); | |
5f409e20 RR |
9293 | |
9294 | fpregs_mark_activate(); | |
9295 | fpregs_unlock(); | |
9296 | ||
822f312d SAS |
9297 | trace_kvm_fpu(1); |
9298 | } | |
9299 | ||
9300 | /* When vcpu_run ends, restore user space FPU context. */ | |
9301 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
9302 | { | |
5f409e20 RR |
9303 | fpregs_lock(); |
9304 | ||
ed02b213 TL |
9305 | /* |
9306 | * Guests with protected state can't have it read by the hypervisor, | |
9307 | * so skip trying to save it. | |
9308 | */ | |
9309 | if (vcpu->arch.guest_fpu) | |
9310 | kvm_save_current_fpu(vcpu->arch.guest_fpu); | |
c9aef3b8 | 9311 | |
d9a710e5 | 9312 | copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); |
5f409e20 RR |
9313 | |
9314 | fpregs_mark_activate(); | |
9315 | fpregs_unlock(); | |
9316 | ||
822f312d SAS |
9317 | ++vcpu->stat.fpu_reload; |
9318 | trace_kvm_fpu(0); | |
9319 | } | |
9320 | ||
1b94f6f8 | 9321 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) |
b6c7a5dc | 9322 | { |
1b94f6f8 | 9323 | struct kvm_run *kvm_run = vcpu->run; |
b6c7a5dc | 9324 | int r; |
b6c7a5dc | 9325 | |
accb757d | 9326 | vcpu_load(vcpu); |
20b7035c | 9327 | kvm_sigset_activate(vcpu); |
5663d8f9 PX |
9328 | kvm_load_guest_fpu(vcpu); |
9329 | ||
a4535290 | 9330 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
9331 | if (kvm_run->immediate_exit) { |
9332 | r = -EINTR; | |
9333 | goto out; | |
9334 | } | |
b6c7a5dc | 9335 | kvm_vcpu_block(vcpu); |
66450a21 | 9336 | kvm_apic_accept_events(vcpu); |
72875d8a | 9337 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 9338 | r = -EAGAIN; |
a0595000 JS |
9339 | if (signal_pending(current)) { |
9340 | r = -EINTR; | |
1b94f6f8 | 9341 | kvm_run->exit_reason = KVM_EXIT_INTR; |
a0595000 JS |
9342 | ++vcpu->stat.signal_exits; |
9343 | } | |
ac9f6dc0 | 9344 | goto out; |
b6c7a5dc HB |
9345 | } |
9346 | ||
1b94f6f8 | 9347 | if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { |
01643c51 KH |
9348 | r = -EINVAL; |
9349 | goto out; | |
9350 | } | |
9351 | ||
1b94f6f8 | 9352 | if (kvm_run->kvm_dirty_regs) { |
01643c51 KH |
9353 | r = sync_regs(vcpu); |
9354 | if (r != 0) | |
9355 | goto out; | |
9356 | } | |
9357 | ||
b6c7a5dc | 9358 | /* re-sync apic's tpr */ |
35754c98 | 9359 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
9360 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
9361 | r = -EINVAL; | |
9362 | goto out; | |
9363 | } | |
9364 | } | |
b6c7a5dc | 9365 | |
716d51ab GN |
9366 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
9367 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
9368 | vcpu->arch.complete_userspace_io = NULL; | |
9369 | r = cui(vcpu); | |
9370 | if (r <= 0) | |
5663d8f9 | 9371 | goto out; |
716d51ab GN |
9372 | } else |
9373 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 9374 | |
460df4c1 PB |
9375 | if (kvm_run->immediate_exit) |
9376 | r = -EINTR; | |
9377 | else | |
9378 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
9379 | |
9380 | out: | |
5663d8f9 | 9381 | kvm_put_guest_fpu(vcpu); |
1b94f6f8 | 9382 | if (kvm_run->kvm_valid_regs) |
01643c51 | 9383 | store_regs(vcpu); |
f1d86e46 | 9384 | post_kvm_run_save(vcpu); |
20b7035c | 9385 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 9386 | |
accb757d | 9387 | vcpu_put(vcpu); |
b6c7a5dc HB |
9388 | return r; |
9389 | } | |
9390 | ||
01643c51 | 9391 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 9392 | { |
7ae441ea GN |
9393 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
9394 | /* | |
9395 | * We are here if userspace calls get_regs() in the middle of | |
9396 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 9397 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
9398 | * that usually, but some bad designed PV devices (vmware |
9399 | * backdoor interface) need this to work | |
9400 | */ | |
c9b8b07c | 9401 | emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); |
7ae441ea GN |
9402 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
9403 | } | |
de3cd117 SC |
9404 | regs->rax = kvm_rax_read(vcpu); |
9405 | regs->rbx = kvm_rbx_read(vcpu); | |
9406 | regs->rcx = kvm_rcx_read(vcpu); | |
9407 | regs->rdx = kvm_rdx_read(vcpu); | |
9408 | regs->rsi = kvm_rsi_read(vcpu); | |
9409 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 9410 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 9411 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 9412 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
9413 | regs->r8 = kvm_r8_read(vcpu); |
9414 | regs->r9 = kvm_r9_read(vcpu); | |
9415 | regs->r10 = kvm_r10_read(vcpu); | |
9416 | regs->r11 = kvm_r11_read(vcpu); | |
9417 | regs->r12 = kvm_r12_read(vcpu); | |
9418 | regs->r13 = kvm_r13_read(vcpu); | |
9419 | regs->r14 = kvm_r14_read(vcpu); | |
9420 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
9421 | #endif |
9422 | ||
5fdbf976 | 9423 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 9424 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 9425 | } |
b6c7a5dc | 9426 | |
01643c51 KH |
9427 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
9428 | { | |
9429 | vcpu_load(vcpu); | |
9430 | __get_regs(vcpu, regs); | |
1fc9b76b | 9431 | vcpu_put(vcpu); |
b6c7a5dc HB |
9432 | return 0; |
9433 | } | |
9434 | ||
01643c51 | 9435 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 9436 | { |
7ae441ea GN |
9437 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
9438 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
9439 | ||
de3cd117 SC |
9440 | kvm_rax_write(vcpu, regs->rax); |
9441 | kvm_rbx_write(vcpu, regs->rbx); | |
9442 | kvm_rcx_write(vcpu, regs->rcx); | |
9443 | kvm_rdx_write(vcpu, regs->rdx); | |
9444 | kvm_rsi_write(vcpu, regs->rsi); | |
9445 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 9446 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 9447 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 9448 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
9449 | kvm_r8_write(vcpu, regs->r8); |
9450 | kvm_r9_write(vcpu, regs->r9); | |
9451 | kvm_r10_write(vcpu, regs->r10); | |
9452 | kvm_r11_write(vcpu, regs->r11); | |
9453 | kvm_r12_write(vcpu, regs->r12); | |
9454 | kvm_r13_write(vcpu, regs->r13); | |
9455 | kvm_r14_write(vcpu, regs->r14); | |
9456 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
9457 | #endif |
9458 | ||
5fdbf976 | 9459 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 9460 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 9461 | |
b4f14abd JK |
9462 | vcpu->arch.exception.pending = false; |
9463 | ||
3842d135 | 9464 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 9465 | } |
3842d135 | 9466 | |
01643c51 KH |
9467 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
9468 | { | |
9469 | vcpu_load(vcpu); | |
9470 | __set_regs(vcpu, regs); | |
875656fe | 9471 | vcpu_put(vcpu); |
b6c7a5dc HB |
9472 | return 0; |
9473 | } | |
9474 | ||
b6c7a5dc HB |
9475 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
9476 | { | |
9477 | struct kvm_segment cs; | |
9478 | ||
3e6e0aab | 9479 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
9480 | *db = cs.db; |
9481 | *l = cs.l; | |
9482 | } | |
9483 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
9484 | ||
01643c51 | 9485 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 9486 | { |
89a27f4d | 9487 | struct desc_ptr dt; |
b6c7a5dc | 9488 | |
5265713a TL |
9489 | if (vcpu->arch.guest_state_protected) |
9490 | goto skip_protected_regs; | |
9491 | ||
3e6e0aab GT |
9492 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
9493 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
9494 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
9495 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
9496 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
9497 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 9498 | |
3e6e0aab GT |
9499 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
9500 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 9501 | |
afaf0b2f | 9502 | kvm_x86_ops.get_idt(vcpu, &dt); |
89a27f4d GN |
9503 | sregs->idt.limit = dt.size; |
9504 | sregs->idt.base = dt.address; | |
afaf0b2f | 9505 | kvm_x86_ops.get_gdt(vcpu, &dt); |
89a27f4d GN |
9506 | sregs->gdt.limit = dt.size; |
9507 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 9508 | |
ad312c7c | 9509 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 9510 | sregs->cr3 = kvm_read_cr3(vcpu); |
5265713a TL |
9511 | |
9512 | skip_protected_regs: | |
9513 | sregs->cr0 = kvm_read_cr0(vcpu); | |
fc78f519 | 9514 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 9515 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 9516 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
9517 | sregs->apic_base = kvm_get_apic_base(vcpu); |
9518 | ||
0e96f31e | 9519 | memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); |
b6c7a5dc | 9520 | |
04140b41 | 9521 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
9522 | set_bit(vcpu->arch.interrupt.nr, |
9523 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 9524 | } |
16d7a191 | 9525 | |
01643c51 KH |
9526 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
9527 | struct kvm_sregs *sregs) | |
9528 | { | |
9529 | vcpu_load(vcpu); | |
9530 | __get_sregs(vcpu, sregs); | |
bcdec41c | 9531 | vcpu_put(vcpu); |
b6c7a5dc HB |
9532 | return 0; |
9533 | } | |
9534 | ||
62d9f0db MT |
9535 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
9536 | struct kvm_mp_state *mp_state) | |
9537 | { | |
fd232561 | 9538 | vcpu_load(vcpu); |
f958bd23 SC |
9539 | if (kvm_mpx_supported()) |
9540 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 9541 | |
66450a21 | 9542 | kvm_apic_accept_events(vcpu); |
647daca2 TL |
9543 | if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || |
9544 | vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && | |
9545 | vcpu->arch.pv.pv_unhalted) | |
6aef266c SV |
9546 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; |
9547 | else | |
9548 | mp_state->mp_state = vcpu->arch.mp_state; | |
9549 | ||
f958bd23 SC |
9550 | if (kvm_mpx_supported()) |
9551 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 9552 | vcpu_put(vcpu); |
62d9f0db MT |
9553 | return 0; |
9554 | } | |
9555 | ||
9556 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
9557 | struct kvm_mp_state *mp_state) | |
9558 | { | |
e83dff5e CD |
9559 | int ret = -EINVAL; |
9560 | ||
9561 | vcpu_load(vcpu); | |
9562 | ||
bce87cce | 9563 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 9564 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 9565 | goto out; |
66450a21 | 9566 | |
27cbe7d6 LA |
9567 | /* |
9568 | * KVM_MP_STATE_INIT_RECEIVED means the processor is in | |
9569 | * INIT state; latched init should be reported using | |
9570 | * KVM_SET_VCPU_EVENTS, so reject it here. | |
9571 | */ | |
9572 | if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && | |
28bf2888 DH |
9573 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
9574 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 9575 | goto out; |
28bf2888 | 9576 | |
66450a21 JK |
9577 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
9578 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
9579 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
9580 | } else | |
9581 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 9582 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
9583 | |
9584 | ret = 0; | |
9585 | out: | |
9586 | vcpu_put(vcpu); | |
9587 | return ret; | |
62d9f0db MT |
9588 | } |
9589 | ||
7f3d35fd KW |
9590 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
9591 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 9592 | { |
c9b8b07c | 9593 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d | 9594 | int ret; |
e01c2426 | 9595 | |
8ec4722d | 9596 | init_emulate_ctxt(vcpu); |
c697518a | 9597 | |
7f3d35fd | 9598 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 9599 | has_error_code, error_code); |
1051778f SC |
9600 | if (ret) { |
9601 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
9602 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
9603 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 9604 | return 0; |
1051778f | 9605 | } |
37817f29 | 9606 | |
9d74191a TY |
9607 | kvm_rip_write(vcpu, ctxt->eip); |
9608 | kvm_set_rflags(vcpu, ctxt->eflags); | |
60fc3d02 | 9609 | return 1; |
37817f29 IE |
9610 | } |
9611 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
9612 | ||
ee69c92b | 9613 | static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 9614 | { |
37b95951 | 9615 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
9616 | /* |
9617 | * When EFER.LME and CR0.PG are set, the processor is in | |
9618 | * 64-bit mode (though maybe in a 32-bit code segment). | |
9619 | * CR4.PAE and EFER.LMA must be set. | |
9620 | */ | |
ee69c92b SC |
9621 | if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) |
9622 | return false; | |
f2981033 LT |
9623 | } else { |
9624 | /* | |
9625 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
9626 | * segment cannot be 64-bit. | |
9627 | */ | |
9628 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
ee69c92b | 9629 | return false; |
f2981033 LT |
9630 | } |
9631 | ||
ee69c92b | 9632 | return kvm_is_valid_cr4(vcpu, sregs->cr4); |
f2981033 LT |
9633 | } |
9634 | ||
01643c51 | 9635 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 9636 | { |
58cb628d | 9637 | struct msr_data apic_base_msr; |
b6c7a5dc | 9638 | int mmu_reset_needed = 0; |
63f42e02 | 9639 | int pending_vec, max_bits, idx; |
89a27f4d | 9640 | struct desc_ptr dt; |
b4ef9d4e CD |
9641 | int ret = -EINVAL; |
9642 | ||
ee69c92b | 9643 | if (!kvm_is_valid_sregs(vcpu, sregs)) |
8dbfb2bf | 9644 | goto out; |
f2981033 | 9645 | |
d3802286 JM |
9646 | apic_base_msr.data = sregs->apic_base; |
9647 | apic_base_msr.host_initiated = true; | |
9648 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
b4ef9d4e | 9649 | goto out; |
6d1068b3 | 9650 | |
5265713a TL |
9651 | if (vcpu->arch.guest_state_protected) |
9652 | goto skip_protected_regs; | |
9653 | ||
89a27f4d GN |
9654 | dt.size = sregs->idt.limit; |
9655 | dt.address = sregs->idt.base; | |
afaf0b2f | 9656 | kvm_x86_ops.set_idt(vcpu, &dt); |
89a27f4d GN |
9657 | dt.size = sregs->gdt.limit; |
9658 | dt.address = sregs->gdt.base; | |
afaf0b2f | 9659 | kvm_x86_ops.set_gdt(vcpu, &dt); |
b6c7a5dc | 9660 | |
ad312c7c | 9661 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 9662 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 9663 | vcpu->arch.cr3 = sregs->cr3; |
cb3c1e2f | 9664 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
b6c7a5dc | 9665 | |
2d3ad1f4 | 9666 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 9667 | |
f6801dff | 9668 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
afaf0b2f | 9669 | kvm_x86_ops.set_efer(vcpu, sregs->efer); |
b6c7a5dc | 9670 | |
4d4ec087 | 9671 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
afaf0b2f | 9672 | kvm_x86_ops.set_cr0(vcpu, sregs->cr0); |
d7306163 | 9673 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 9674 | |
fc78f519 | 9675 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
afaf0b2f | 9676 | kvm_x86_ops.set_cr4(vcpu, sregs->cr4); |
63f42e02 XG |
9677 | |
9678 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
bf03d4f9 | 9679 | if (is_pae_paging(vcpu)) { |
9f8fe504 | 9680 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
9681 | mmu_reset_needed = 1; |
9682 | } | |
63f42e02 | 9683 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
9684 | |
9685 | if (mmu_reset_needed) | |
9686 | kvm_mmu_reset_context(vcpu); | |
9687 | ||
3e6e0aab GT |
9688 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
9689 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
9690 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
9691 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
9692 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
9693 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 9694 | |
3e6e0aab GT |
9695 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
9696 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 9697 | |
5f0269f5 ME |
9698 | update_cr8_intercept(vcpu); |
9699 | ||
9c3e4aab | 9700 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 9701 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 9702 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 9703 | !is_protmode(vcpu)) |
9c3e4aab MT |
9704 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
9705 | ||
5265713a TL |
9706 | skip_protected_regs: |
9707 | max_bits = KVM_NR_INTERRUPTS; | |
9708 | pending_vec = find_first_bit( | |
9709 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
9710 | if (pending_vec < max_bits) { | |
9711 | kvm_queue_interrupt(vcpu, pending_vec, false); | |
9712 | pr_debug("Set back pending irq %d\n", pending_vec); | |
9713 | } | |
9714 | ||
3842d135 AK |
9715 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
9716 | ||
b4ef9d4e CD |
9717 | ret = 0; |
9718 | out: | |
01643c51 KH |
9719 | return ret; |
9720 | } | |
9721 | ||
9722 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
9723 | struct kvm_sregs *sregs) | |
9724 | { | |
9725 | int ret; | |
9726 | ||
9727 | vcpu_load(vcpu); | |
9728 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
9729 | vcpu_put(vcpu); |
9730 | return ret; | |
b6c7a5dc HB |
9731 | } |
9732 | ||
d0bfb940 JK |
9733 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
9734 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 9735 | { |
355be0b9 | 9736 | unsigned long rflags; |
ae675ef0 | 9737 | int i, r; |
b6c7a5dc | 9738 | |
8d4846b9 TL |
9739 | if (vcpu->arch.guest_state_protected) |
9740 | return -EINVAL; | |
9741 | ||
66b56562 CD |
9742 | vcpu_load(vcpu); |
9743 | ||
4f926bf2 JK |
9744 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
9745 | r = -EBUSY; | |
9746 | if (vcpu->arch.exception.pending) | |
2122ff5e | 9747 | goto out; |
4f926bf2 JK |
9748 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
9749 | kvm_queue_exception(vcpu, DB_VECTOR); | |
9750 | else | |
9751 | kvm_queue_exception(vcpu, BP_VECTOR); | |
9752 | } | |
9753 | ||
91586a3b JK |
9754 | /* |
9755 | * Read rflags as long as potentially injected trace flags are still | |
9756 | * filtered out. | |
9757 | */ | |
9758 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
9759 | |
9760 | vcpu->guest_debug = dbg->control; | |
9761 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
9762 | vcpu->guest_debug = 0; | |
9763 | ||
9764 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
9765 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
9766 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 9767 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
9768 | } else { |
9769 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
9770 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 9771 | } |
c8639010 | 9772 | kvm_update_dr7(vcpu); |
ae675ef0 | 9773 | |
f92653ee JK |
9774 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
9775 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
9776 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 9777 | |
91586a3b JK |
9778 | /* |
9779 | * Trigger an rflags update that will inject or remove the trace | |
9780 | * flags. | |
9781 | */ | |
9782 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 9783 | |
6986982f | 9784 | kvm_x86_ops.update_exception_bitmap(vcpu); |
b6c7a5dc | 9785 | |
4f926bf2 | 9786 | r = 0; |
d0bfb940 | 9787 | |
2122ff5e | 9788 | out: |
66b56562 | 9789 | vcpu_put(vcpu); |
b6c7a5dc HB |
9790 | return r; |
9791 | } | |
9792 | ||
8b006791 ZX |
9793 | /* |
9794 | * Translate a guest virtual address to a guest physical address. | |
9795 | */ | |
9796 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
9797 | struct kvm_translation *tr) | |
9798 | { | |
9799 | unsigned long vaddr = tr->linear_address; | |
9800 | gpa_t gpa; | |
f656ce01 | 9801 | int idx; |
8b006791 | 9802 | |
1da5b61d CD |
9803 | vcpu_load(vcpu); |
9804 | ||
f656ce01 | 9805 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 9806 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 9807 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
9808 | tr->physical_address = gpa; |
9809 | tr->valid = gpa != UNMAPPED_GVA; | |
9810 | tr->writeable = 1; | |
9811 | tr->usermode = 0; | |
8b006791 | 9812 | |
1da5b61d | 9813 | vcpu_put(vcpu); |
8b006791 ZX |
9814 | return 0; |
9815 | } | |
9816 | ||
d0752060 HB |
9817 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
9818 | { | |
1393123e | 9819 | struct fxregs_state *fxsave; |
d0752060 | 9820 | |
ed02b213 TL |
9821 | if (!vcpu->arch.guest_fpu) |
9822 | return 0; | |
9823 | ||
1393123e | 9824 | vcpu_load(vcpu); |
d0752060 | 9825 | |
b666a4b6 | 9826 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 HB |
9827 | memcpy(fpu->fpr, fxsave->st_space, 128); |
9828 | fpu->fcw = fxsave->cwd; | |
9829 | fpu->fsw = fxsave->swd; | |
9830 | fpu->ftwx = fxsave->twd; | |
9831 | fpu->last_opcode = fxsave->fop; | |
9832 | fpu->last_ip = fxsave->rip; | |
9833 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 9834 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 9835 | |
1393123e | 9836 | vcpu_put(vcpu); |
d0752060 HB |
9837 | return 0; |
9838 | } | |
9839 | ||
9840 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
9841 | { | |
6a96bc7f CD |
9842 | struct fxregs_state *fxsave; |
9843 | ||
ed02b213 TL |
9844 | if (!vcpu->arch.guest_fpu) |
9845 | return 0; | |
9846 | ||
6a96bc7f CD |
9847 | vcpu_load(vcpu); |
9848 | ||
b666a4b6 | 9849 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 | 9850 | |
d0752060 HB |
9851 | memcpy(fxsave->st_space, fpu->fpr, 128); |
9852 | fxsave->cwd = fpu->fcw; | |
9853 | fxsave->swd = fpu->fsw; | |
9854 | fxsave->twd = fpu->ftwx; | |
9855 | fxsave->fop = fpu->last_opcode; | |
9856 | fxsave->rip = fpu->last_ip; | |
9857 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 9858 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 9859 | |
6a96bc7f | 9860 | vcpu_put(vcpu); |
d0752060 HB |
9861 | return 0; |
9862 | } | |
9863 | ||
01643c51 KH |
9864 | static void store_regs(struct kvm_vcpu *vcpu) |
9865 | { | |
9866 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
9867 | ||
9868 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
9869 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
9870 | ||
9871 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
9872 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
9873 | ||
9874 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
9875 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
9876 | vcpu, &vcpu->run->s.regs.events); | |
9877 | } | |
9878 | ||
9879 | static int sync_regs(struct kvm_vcpu *vcpu) | |
9880 | { | |
9881 | if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) | |
9882 | return -EINVAL; | |
9883 | ||
9884 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { | |
9885 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
9886 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
9887 | } | |
9888 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
9889 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
9890 | return -EINVAL; | |
9891 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
9892 | } | |
9893 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
9894 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
9895 | vcpu, &vcpu->run->s.regs.events)) | |
9896 | return -EINVAL; | |
9897 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
9898 | } | |
9899 | ||
9900 | return 0; | |
9901 | } | |
9902 | ||
0ee6a517 | 9903 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 9904 | { |
ed02b213 TL |
9905 | if (!vcpu->arch.guest_fpu) |
9906 | return; | |
9907 | ||
b666a4b6 | 9908 | fpstate_init(&vcpu->arch.guest_fpu->state); |
782511b0 | 9909 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
b666a4b6 | 9910 | vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = |
df1daba7 | 9911 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 9912 | |
2acf923e DC |
9913 | /* |
9914 | * Ensure guest xcr0 is valid for loading | |
9915 | */ | |
d91cab78 | 9916 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 9917 | |
ad312c7c | 9918 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 9919 | } |
d0752060 | 9920 | |
ed02b213 TL |
9921 | void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) |
9922 | { | |
9923 | if (vcpu->arch.guest_fpu) { | |
9924 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
9925 | vcpu->arch.guest_fpu = NULL; | |
9926 | } | |
9927 | } | |
9928 | EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); | |
9929 | ||
897cc38e | 9930 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 9931 | { |
897cc38e SC |
9932 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
9933 | pr_warn_once("kvm: SMP vm created on host with unstable TSC; " | |
9934 | "guest TSC will not be reliable\n"); | |
7f1ea208 | 9935 | |
897cc38e | 9936 | return 0; |
e9b11c17 ZX |
9937 | } |
9938 | ||
e529ef66 | 9939 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 9940 | { |
95a0d01e SC |
9941 | struct page *page; |
9942 | int r; | |
c447e76b | 9943 | |
95a0d01e SC |
9944 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
9945 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
9946 | else | |
9947 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 9948 | |
95a0d01e | 9949 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c447e76b | 9950 | |
95a0d01e SC |
9951 | r = kvm_mmu_create(vcpu); |
9952 | if (r < 0) | |
9953 | return r; | |
9954 | ||
9955 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
9956 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
9957 | if (r < 0) | |
9958 | goto fail_mmu_destroy; | |
4e19c36f SS |
9959 | if (kvm_apicv_activated(vcpu->kvm)) |
9960 | vcpu->arch.apicv_active = true; | |
95a0d01e SC |
9961 | } else |
9962 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
9963 | ||
9964 | r = -ENOMEM; | |
9965 | ||
93bb59ca | 9966 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); |
95a0d01e SC |
9967 | if (!page) |
9968 | goto fail_free_lapic; | |
9969 | vcpu->arch.pio_data = page_address(page); | |
9970 | ||
9971 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, | |
9972 | GFP_KERNEL_ACCOUNT); | |
9973 | if (!vcpu->arch.mce_banks) | |
9974 | goto fail_free_pio_data; | |
9975 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
9976 | ||
9977 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
9978 | GFP_KERNEL_ACCOUNT)) | |
9979 | goto fail_free_mce_banks; | |
9980 | ||
c9b8b07c SC |
9981 | if (!alloc_emulate_ctxt(vcpu)) |
9982 | goto free_wbinvd_dirty_mask; | |
9983 | ||
95a0d01e SC |
9984 | vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, |
9985 | GFP_KERNEL_ACCOUNT); | |
9986 | if (!vcpu->arch.user_fpu) { | |
9987 | pr_err("kvm: failed to allocate userspace's fpu\n"); | |
c9b8b07c | 9988 | goto free_emulate_ctxt; |
95a0d01e SC |
9989 | } |
9990 | ||
9991 | vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, | |
9992 | GFP_KERNEL_ACCOUNT); | |
9993 | if (!vcpu->arch.guest_fpu) { | |
9994 | pr_err("kvm: failed to allocate vcpu's fpu\n"); | |
9995 | goto free_user_fpu; | |
9996 | } | |
9997 | fx_init(vcpu); | |
9998 | ||
95a0d01e SC |
9999 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
10000 | ||
10001 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
10002 | ||
10003 | kvm_async_pf_hash_reset(vcpu); | |
10004 | kvm_pmu_init(vcpu); | |
10005 | ||
10006 | vcpu->arch.pending_external_vector = -1; | |
10007 | vcpu->arch.preempted_in_kernel = false; | |
10008 | ||
10009 | kvm_hv_vcpu_init(vcpu); | |
10010 | ||
afaf0b2f | 10011 | r = kvm_x86_ops.vcpu_create(vcpu); |
95a0d01e SC |
10012 | if (r) |
10013 | goto free_guest_fpu; | |
e9b11c17 | 10014 | |
0cf9135b | 10015 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 10016 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
19efffa2 | 10017 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 10018 | vcpu_load(vcpu); |
d28bc9dd | 10019 | kvm_vcpu_reset(vcpu, false); |
e1732991 | 10020 | kvm_init_mmu(vcpu, false); |
e9b11c17 | 10021 | vcpu_put(vcpu); |
ec7660cc | 10022 | return 0; |
95a0d01e SC |
10023 | |
10024 | free_guest_fpu: | |
ed02b213 | 10025 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10026 | free_user_fpu: |
10027 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
c9b8b07c SC |
10028 | free_emulate_ctxt: |
10029 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); | |
95a0d01e SC |
10030 | free_wbinvd_dirty_mask: |
10031 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
10032 | fail_free_mce_banks: | |
10033 | kfree(vcpu->arch.mce_banks); | |
10034 | fail_free_pio_data: | |
10035 | free_page((unsigned long)vcpu->arch.pio_data); | |
10036 | fail_free_lapic: | |
10037 | kvm_free_lapic(vcpu); | |
10038 | fail_mmu_destroy: | |
10039 | kvm_mmu_destroy(vcpu); | |
10040 | return r; | |
e9b11c17 ZX |
10041 | } |
10042 | ||
31928aa5 | 10043 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 10044 | { |
332967a3 | 10045 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 10046 | |
d3457c87 RK |
10047 | kvm_hv_vcpu_postcreate(vcpu); |
10048 | ||
ec7660cc | 10049 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 10050 | return; |
ec7660cc | 10051 | vcpu_load(vcpu); |
0c899c25 | 10052 | kvm_synchronize_tsc(vcpu, 0); |
42897d86 | 10053 | vcpu_put(vcpu); |
2d5ba19b MT |
10054 | |
10055 | /* poll control enabled by default */ | |
10056 | vcpu->arch.msr_kvm_poll_control = 1; | |
10057 | ||
ec7660cc | 10058 | mutex_unlock(&vcpu->mutex); |
42897d86 | 10059 | |
b34de572 WL |
10060 | if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) |
10061 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
10062 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
10063 | } |
10064 | ||
d40ccc62 | 10065 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 10066 | { |
4cbc418a | 10067 | struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; |
95a0d01e | 10068 | int idx; |
344d9588 | 10069 | |
4cbc418a PB |
10070 | kvm_release_pfn(cache->pfn, cache->dirty, cache); |
10071 | ||
50b143e1 | 10072 | kvmclock_reset(vcpu); |
e9b11c17 | 10073 | |
afaf0b2f | 10074 | kvm_x86_ops.vcpu_free(vcpu); |
50b143e1 | 10075 | |
c9b8b07c | 10076 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); |
50b143e1 SC |
10077 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
10078 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
ed02b213 | 10079 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10080 | |
10081 | kvm_hv_vcpu_uninit(vcpu); | |
10082 | kvm_pmu_destroy(vcpu); | |
10083 | kfree(vcpu->arch.mce_banks); | |
10084 | kvm_free_lapic(vcpu); | |
10085 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
10086 | kvm_mmu_destroy(vcpu); | |
10087 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
10088 | free_page((unsigned long)vcpu->arch.pio_data); | |
255cbecf | 10089 | kvfree(vcpu->arch.cpuid_entries); |
95a0d01e SC |
10090 | if (!lapic_in_kernel(vcpu)) |
10091 | static_key_slow_dec(&kvm_no_apic_vcpu); | |
e9b11c17 ZX |
10092 | } |
10093 | ||
d28bc9dd | 10094 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 10095 | { |
b7e31be3 RK |
10096 | kvm_lapic_reset(vcpu, init_event); |
10097 | ||
e69fab5d PB |
10098 | vcpu->arch.hflags = 0; |
10099 | ||
c43203ca | 10100 | vcpu->arch.smi_pending = 0; |
52797bf9 | 10101 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
10102 | atomic_set(&vcpu->arch.nmi_queued, 0); |
10103 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 10104 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
10105 | kvm_clear_interrupt_queue(vcpu); |
10106 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 10107 | |
42dbaa5a | 10108 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 10109 | kvm_update_dr0123(vcpu); |
6f43ed01 | 10110 | vcpu->arch.dr6 = DR6_INIT; |
42dbaa5a | 10111 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 10112 | kvm_update_dr7(vcpu); |
42dbaa5a | 10113 | |
1119022c NA |
10114 | vcpu->arch.cr2 = 0; |
10115 | ||
3842d135 | 10116 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2635b5c4 VK |
10117 | vcpu->arch.apf.msr_en_val = 0; |
10118 | vcpu->arch.apf.msr_int_val = 0; | |
c9aaa895 | 10119 | vcpu->arch.st.msr_val = 0; |
3842d135 | 10120 | |
12f9a48f GC |
10121 | kvmclock_reset(vcpu); |
10122 | ||
af585b92 GN |
10123 | kvm_clear_async_pf_completion_queue(vcpu); |
10124 | kvm_async_pf_hash_reset(vcpu); | |
10125 | vcpu->arch.apf.halted = false; | |
3842d135 | 10126 | |
ed02b213 | 10127 | if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { |
a554d207 WL |
10128 | void *mpx_state_buffer; |
10129 | ||
10130 | /* | |
10131 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
10132 | * called with loaded FPU and does not let userspace fix the state. | |
10133 | */ | |
f775b13e RR |
10134 | if (init_event) |
10135 | kvm_put_guest_fpu(vcpu); | |
b666a4b6 | 10136 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10137 | XFEATURE_BNDREGS); |
a554d207 WL |
10138 | if (mpx_state_buffer) |
10139 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
b666a4b6 | 10140 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10141 | XFEATURE_BNDCSR); |
a554d207 WL |
10142 | if (mpx_state_buffer) |
10143 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
10144 | if (init_event) |
10145 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
10146 | } |
10147 | ||
64d60670 | 10148 | if (!init_event) { |
d28bc9dd | 10149 | kvm_pmu_reset(vcpu); |
64d60670 | 10150 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 10151 | |
db2336a8 | 10152 | vcpu->arch.msr_misc_features_enables = 0; |
a554d207 WL |
10153 | |
10154 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; | |
64d60670 | 10155 | } |
f5132b01 | 10156 | |
66f7b72e JS |
10157 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
10158 | vcpu->arch.regs_avail = ~0; | |
10159 | vcpu->arch.regs_dirty = ~0; | |
10160 | ||
a554d207 WL |
10161 | vcpu->arch.ia32_xss = 0; |
10162 | ||
afaf0b2f | 10163 | kvm_x86_ops.vcpu_reset(vcpu, init_event); |
e9b11c17 ZX |
10164 | } |
10165 | ||
2b4a273b | 10166 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
10167 | { |
10168 | struct kvm_segment cs; | |
10169 | ||
10170 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
10171 | cs.selector = vector << 8; | |
10172 | cs.base = vector << 12; | |
10173 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
10174 | kvm_rip_write(vcpu, 0); | |
e9b11c17 | 10175 | } |
647daca2 | 10176 | EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); |
e9b11c17 | 10177 | |
13a34e06 | 10178 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 10179 | { |
ca84d1a2 ZA |
10180 | struct kvm *kvm; |
10181 | struct kvm_vcpu *vcpu; | |
10182 | int i; | |
0dd6a6ed ZA |
10183 | int ret; |
10184 | u64 local_tsc; | |
10185 | u64 max_tsc = 0; | |
10186 | bool stable, backwards_tsc = false; | |
18863bdd | 10187 | |
7e34fbd0 | 10188 | kvm_user_return_msr_cpu_online(); |
afaf0b2f | 10189 | ret = kvm_x86_ops.hardware_enable(); |
0dd6a6ed ZA |
10190 | if (ret != 0) |
10191 | return ret; | |
10192 | ||
4ea1636b | 10193 | local_tsc = rdtsc(); |
b0c39dc6 | 10194 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
10195 | list_for_each_entry(kvm, &vm_list, vm_list) { |
10196 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
10197 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 10198 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10199 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
10200 | backwards_tsc = true; | |
10201 | if (vcpu->arch.last_host_tsc > max_tsc) | |
10202 | max_tsc = vcpu->arch.last_host_tsc; | |
10203 | } | |
10204 | } | |
10205 | } | |
10206 | ||
10207 | /* | |
10208 | * Sometimes, even reliable TSCs go backwards. This happens on | |
10209 | * platforms that reset TSC during suspend or hibernate actions, but | |
10210 | * maintain synchronization. We must compensate. Fortunately, we can | |
10211 | * detect that condition here, which happens early in CPU bringup, | |
10212 | * before any KVM threads can be running. Unfortunately, we can't | |
10213 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
10214 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 10215 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
10216 | * variables that haven't been updated yet. |
10217 | * | |
10218 | * So we simply find the maximum observed TSC above, then record the | |
10219 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
10220 | * the adjustment will be applied. Note that we accumulate | |
10221 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
10222 | * gets a chance to run again. In the event that no KVM threads get a | |
10223 | * chance to run, we will miss the entire elapsed period, as we'll have | |
10224 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
10225 | * loose cycle time. This isn't too big a deal, since the loss will be | |
10226 | * uniform across all VCPUs (not to mention the scenario is extremely | |
10227 | * unlikely). It is possible that a second hibernate recovery happens | |
10228 | * much faster than a first, causing the observed TSC here to be | |
10229 | * smaller; this would require additional padding adjustment, which is | |
10230 | * why we set last_host_tsc to the local tsc observed here. | |
10231 | * | |
10232 | * N.B. - this code below runs only on platforms with reliable TSC, | |
10233 | * as that is the only way backwards_tsc is set above. Also note | |
10234 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
10235 | * have the same delta_cyc adjustment applied if backwards_tsc | |
10236 | * is detected. Note further, this adjustment is only done once, | |
10237 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
10238 | * called multiple times (one for each physical CPU bringup). | |
10239 | * | |
4a969980 | 10240 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
10241 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
10242 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
10243 | * guarantee that they stay in perfect synchronization. | |
10244 | */ | |
10245 | if (backwards_tsc) { | |
10246 | u64 delta_cyc = max_tsc - local_tsc; | |
10247 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 10248 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
10249 | kvm_for_each_vcpu(i, vcpu, kvm) { |
10250 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
10251 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 10252 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10253 | } |
10254 | ||
10255 | /* | |
10256 | * We have to disable TSC offset matching.. if you were | |
10257 | * booting a VM while issuing an S4 host suspend.... | |
10258 | * you may have some problem. Solving this issue is | |
10259 | * left as an exercise to the reader. | |
10260 | */ | |
10261 | kvm->arch.last_tsc_nsec = 0; | |
10262 | kvm->arch.last_tsc_write = 0; | |
10263 | } | |
10264 | ||
10265 | } | |
10266 | return 0; | |
e9b11c17 ZX |
10267 | } |
10268 | ||
13a34e06 | 10269 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 10270 | { |
afaf0b2f | 10271 | kvm_x86_ops.hardware_disable(); |
13a34e06 | 10272 | drop_user_return_notifiers(); |
e9b11c17 ZX |
10273 | } |
10274 | ||
b9904085 | 10275 | int kvm_arch_hardware_setup(void *opaque) |
e9b11c17 | 10276 | { |
d008dfdb | 10277 | struct kvm_x86_init_ops *ops = opaque; |
9e9c3fe4 NA |
10278 | int r; |
10279 | ||
91661989 SC |
10280 | rdmsrl_safe(MSR_EFER, &host_efer); |
10281 | ||
408e9a31 PB |
10282 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
10283 | rdmsrl(MSR_IA32_XSS, host_xss); | |
10284 | ||
d008dfdb | 10285 | r = ops->hardware_setup(); |
9e9c3fe4 NA |
10286 | if (r != 0) |
10287 | return r; | |
10288 | ||
afaf0b2f | 10289 | memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); |
69c6f69a | 10290 | |
408e9a31 PB |
10291 | if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) |
10292 | supported_xss = 0; | |
10293 | ||
139f7425 PB |
10294 | #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) |
10295 | cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); | |
10296 | #undef __kvm_cpu_cap_has | |
b11306b5 | 10297 | |
35181e86 HZ |
10298 | if (kvm_has_tsc_control) { |
10299 | /* | |
10300 | * Make sure the user can only configure tsc_khz values that | |
10301 | * fit into a signed integer. | |
273ba457 | 10302 | * A min value is not calculated because it will always |
35181e86 HZ |
10303 | * be 1 on all machines. |
10304 | */ | |
10305 | u64 max = min(0x7fffffffULL, | |
10306 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
10307 | kvm_max_guest_tsc_khz = max; | |
10308 | ||
ad721883 | 10309 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 10310 | } |
ad721883 | 10311 | |
9e9c3fe4 NA |
10312 | kvm_init_msr_list(); |
10313 | return 0; | |
e9b11c17 ZX |
10314 | } |
10315 | ||
10316 | void kvm_arch_hardware_unsetup(void) | |
10317 | { | |
afaf0b2f | 10318 | kvm_x86_ops.hardware_unsetup(); |
e9b11c17 ZX |
10319 | } |
10320 | ||
b9904085 | 10321 | int kvm_arch_check_processor_compat(void *opaque) |
e9b11c17 | 10322 | { |
f1cdecf5 | 10323 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); |
d008dfdb | 10324 | struct kvm_x86_init_ops *ops = opaque; |
f1cdecf5 SC |
10325 | |
10326 | WARN_ON(!irqs_disabled()); | |
10327 | ||
139f7425 PB |
10328 | if (__cr4_reserved_bits(cpu_has, c) != |
10329 | __cr4_reserved_bits(cpu_has, &boot_cpu_data)) | |
f1cdecf5 SC |
10330 | return -EIO; |
10331 | ||
d008dfdb | 10332 | return ops->check_processor_compatibility(); |
d71ba788 PB |
10333 | } |
10334 | ||
10335 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
10336 | { | |
10337 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
10338 | } | |
10339 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
10340 | ||
10341 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
10342 | { | |
10343 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
10344 | } |
10345 | ||
54e9818f | 10346 | struct static_key kvm_no_apic_vcpu __read_mostly; |
bce87cce | 10347 | EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); |
54e9818f | 10348 | |
e790d9ef RK |
10349 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
10350 | { | |
b35e5548 LX |
10351 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
10352 | ||
c595ceee | 10353 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
10354 | if (pmu->version && unlikely(pmu->event_count)) { |
10355 | pmu->need_cleanup = true; | |
10356 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
10357 | } | |
afaf0b2f | 10358 | kvm_x86_ops.sched_in(vcpu, cpu); |
e790d9ef RK |
10359 | } |
10360 | ||
562b6b08 SC |
10361 | void kvm_arch_free_vm(struct kvm *kvm) |
10362 | { | |
10363 | kfree(kvm->arch.hyperv.hv_pa_pg); | |
10364 | vfree(kvm); | |
e790d9ef RK |
10365 | } |
10366 | ||
562b6b08 | 10367 | |
e08b9637 | 10368 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 10369 | { |
e08b9637 CO |
10370 | if (type) |
10371 | return -EINVAL; | |
10372 | ||
6ef768fa | 10373 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 10374 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
10605204 | 10375 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
1aa9b957 | 10376 | INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); |
4d5c5d0f | 10377 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 10378 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 10379 | |
5550af4d SY |
10380 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
10381 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
10382 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
10383 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
10384 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 10385 | |
038f8c11 | 10386 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 10387 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
10388 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
10389 | ||
8171cd68 | 10390 | kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); |
d828199e | 10391 | pvclock_update_vm_gtod_copy(kvm); |
53f658b3 | 10392 | |
6fbbde9a DS |
10393 | kvm->arch.guest_can_read_msr_platform_info = true; |
10394 | ||
7e44e449 | 10395 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 10396 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 10397 | |
cbc0236a | 10398 | kvm_hv_init_vm(kvm); |
0eb05bf2 | 10399 | kvm_page_track_init(kvm); |
13d268ca | 10400 | kvm_mmu_init_vm(kvm); |
0eb05bf2 | 10401 | |
afaf0b2f | 10402 | return kvm_x86_ops.vm_init(kvm); |
d19a9cd2 ZX |
10403 | } |
10404 | ||
1aa9b957 JS |
10405 | int kvm_arch_post_init_vm(struct kvm *kvm) |
10406 | { | |
10407 | return kvm_mmu_post_init_vm(kvm); | |
10408 | } | |
10409 | ||
d19a9cd2 ZX |
10410 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
10411 | { | |
ec7660cc | 10412 | vcpu_load(vcpu); |
d19a9cd2 ZX |
10413 | kvm_mmu_unload(vcpu); |
10414 | vcpu_put(vcpu); | |
10415 | } | |
10416 | ||
10417 | static void kvm_free_vcpus(struct kvm *kvm) | |
10418 | { | |
10419 | unsigned int i; | |
988a2cae | 10420 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
10421 | |
10422 | /* | |
10423 | * Unpin any mmu pages first. | |
10424 | */ | |
af585b92 GN |
10425 | kvm_for_each_vcpu(i, vcpu, kvm) { |
10426 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 10427 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 10428 | } |
988a2cae | 10429 | kvm_for_each_vcpu(i, vcpu, kvm) |
4543bdc0 | 10430 | kvm_vcpu_destroy(vcpu); |
988a2cae GN |
10431 | |
10432 | mutex_lock(&kvm->lock); | |
10433 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
10434 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 10435 | |
988a2cae GN |
10436 | atomic_set(&kvm->online_vcpus, 0); |
10437 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
10438 | } |
10439 | ||
ad8ba2cd SY |
10440 | void kvm_arch_sync_events(struct kvm *kvm) |
10441 | { | |
332967a3 | 10442 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 10443 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 10444 | kvm_free_pit(kvm); |
ad8ba2cd SY |
10445 | } |
10446 | ||
ff5a983c PX |
10447 | #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) |
10448 | ||
10449 | /** | |
10450 | * __x86_set_memory_region: Setup KVM internal memory slot | |
10451 | * | |
10452 | * @kvm: the kvm pointer to the VM. | |
10453 | * @id: the slot ID to setup. | |
10454 | * @gpa: the GPA to install the slot (unused when @size == 0). | |
10455 | * @size: the size of the slot. Set to zero to uninstall a slot. | |
10456 | * | |
10457 | * This function helps to setup a KVM internal memory slot. Specify | |
10458 | * @size > 0 to install a new slot, while @size == 0 to uninstall a | |
10459 | * slot. The return code can be one of the following: | |
10460 | * | |
10461 | * HVA: on success (uninstall will return a bogus HVA) | |
10462 | * -errno: on error | |
10463 | * | |
10464 | * The caller should always use IS_ERR() to check the return value | |
10465 | * before use. Note, the KVM internal memory slots are guaranteed to | |
10466 | * remain valid and unchanged until the VM is destroyed, i.e., the | |
10467 | * GPA->HVA translation will not change. However, the HVA is a user | |
10468 | * address, i.e. its accessibility is not guaranteed, and must be | |
10469 | * accessed via __copy_{to,from}_user(). | |
10470 | */ | |
10471 | void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, | |
10472 | u32 size) | |
9da0e4d5 PB |
10473 | { |
10474 | int i, r; | |
3f649ab7 | 10475 | unsigned long hva, old_npages; |
f0d648bd | 10476 | struct kvm_memslots *slots = kvm_memslots(kvm); |
0577d1ab | 10477 | struct kvm_memory_slot *slot; |
9da0e4d5 PB |
10478 | |
10479 | /* Called with kvm->slots_lock held. */ | |
1d8007bd | 10480 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
ff5a983c | 10481 | return ERR_PTR_USR(-EINVAL); |
9da0e4d5 | 10482 | |
f0d648bd PB |
10483 | slot = id_to_memslot(slots, id); |
10484 | if (size) { | |
0577d1ab | 10485 | if (slot && slot->npages) |
ff5a983c | 10486 | return ERR_PTR_USR(-EEXIST); |
f0d648bd PB |
10487 | |
10488 | /* | |
10489 | * MAP_SHARED to prevent internal slot pages from being moved | |
10490 | * by fork()/COW. | |
10491 | */ | |
10492 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
10493 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
10494 | if (IS_ERR((void *)hva)) | |
ff5a983c | 10495 | return (void __user *)hva; |
f0d648bd | 10496 | } else { |
0577d1ab | 10497 | if (!slot || !slot->npages) |
f0d648bd PB |
10498 | return 0; |
10499 | ||
0577d1ab | 10500 | old_npages = slot->npages; |
e0135a10 | 10501 | hva = 0; |
f0d648bd PB |
10502 | } |
10503 | ||
9da0e4d5 | 10504 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 10505 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 10506 | |
1d8007bd PB |
10507 | m.slot = id | (i << 16); |
10508 | m.flags = 0; | |
10509 | m.guest_phys_addr = gpa; | |
f0d648bd | 10510 | m.userspace_addr = hva; |
1d8007bd | 10511 | m.memory_size = size; |
9da0e4d5 PB |
10512 | r = __kvm_set_memory_region(kvm, &m); |
10513 | if (r < 0) | |
ff5a983c | 10514 | return ERR_PTR_USR(r); |
9da0e4d5 PB |
10515 | } |
10516 | ||
103c763c | 10517 | if (!size) |
0577d1ab | 10518 | vm_munmap(hva, old_npages * PAGE_SIZE); |
f0d648bd | 10519 | |
ff5a983c | 10520 | return (void __user *)hva; |
9da0e4d5 PB |
10521 | } |
10522 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
10523 | ||
1aa9b957 JS |
10524 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
10525 | { | |
10526 | kvm_mmu_pre_destroy_vm(kvm); | |
10527 | } | |
10528 | ||
d19a9cd2 ZX |
10529 | void kvm_arch_destroy_vm(struct kvm *kvm) |
10530 | { | |
1a155254 AG |
10531 | u32 i; |
10532 | ||
27469d29 AH |
10533 | if (current->mm == kvm->mm) { |
10534 | /* | |
10535 | * Free memory regions allocated on behalf of userspace, | |
10536 | * unless the the memory map has changed due to process exit | |
10537 | * or fd copying. | |
10538 | */ | |
6a3c623b PX |
10539 | mutex_lock(&kvm->slots_lock); |
10540 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
10541 | 0, 0); | |
10542 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
10543 | 0, 0); | |
10544 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
10545 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 10546 | } |
afaf0b2f SC |
10547 | if (kvm_x86_ops.vm_destroy) |
10548 | kvm_x86_ops.vm_destroy(kvm); | |
1a155254 AG |
10549 | for (i = 0; i < kvm->arch.msr_filter.count; i++) |
10550 | kfree(kvm->arch.msr_filter.ranges[i].bitmap); | |
c761159c PX |
10551 | kvm_pic_destroy(kvm); |
10552 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 10553 | kvm_free_vcpus(kvm); |
af1bae54 | 10554 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 10555 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 10556 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 10557 | kvm_page_track_cleanup(kvm); |
cbc0236a | 10558 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 10559 | } |
0de10343 | 10560 | |
e96c81ee | 10561 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
db3fe4eb TY |
10562 | { |
10563 | int i; | |
10564 | ||
d89cc617 | 10565 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
10566 | kvfree(slot->arch.rmap[i]); |
10567 | slot->arch.rmap[i] = NULL; | |
10568 | ||
d89cc617 TY |
10569 | if (i == 0) |
10570 | continue; | |
10571 | ||
e96c81ee SC |
10572 | kvfree(slot->arch.lpage_info[i - 1]); |
10573 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb | 10574 | } |
21ebbeda | 10575 | |
e96c81ee | 10576 | kvm_page_track_free_memslot(slot); |
db3fe4eb TY |
10577 | } |
10578 | ||
0dab98b7 SC |
10579 | static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot, |
10580 | unsigned long npages) | |
db3fe4eb TY |
10581 | { |
10582 | int i; | |
10583 | ||
edd4fa37 SC |
10584 | /* |
10585 | * Clear out the previous array pointers for the KVM_MR_MOVE case. The | |
10586 | * old arrays will be freed by __kvm_set_memory_region() if installing | |
10587 | * the new memslot is successful. | |
10588 | */ | |
10589 | memset(&slot->arch, 0, sizeof(slot->arch)); | |
10590 | ||
d89cc617 | 10591 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
92f94f1e | 10592 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
10593 | unsigned long ugfn; |
10594 | int lpages; | |
d89cc617 | 10595 | int level = i + 1; |
db3fe4eb TY |
10596 | |
10597 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
10598 | slot->base_gfn, level) + 1; | |
10599 | ||
d89cc617 | 10600 | slot->arch.rmap[i] = |
778e1cdd | 10601 | kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), |
254272ce | 10602 | GFP_KERNEL_ACCOUNT); |
d89cc617 | 10603 | if (!slot->arch.rmap[i]) |
77d11309 | 10604 | goto out_free; |
d89cc617 TY |
10605 | if (i == 0) |
10606 | continue; | |
77d11309 | 10607 | |
254272ce | 10608 | linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 10609 | if (!linfo) |
db3fe4eb TY |
10610 | goto out_free; |
10611 | ||
92f94f1e XG |
10612 | slot->arch.lpage_info[i - 1] = linfo; |
10613 | ||
db3fe4eb | 10614 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 10615 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 10616 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 10617 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
10618 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
10619 | /* | |
10620 | * If the gfn and userspace address are not aligned wrt each | |
600087b6 | 10621 | * other, disable large page support for this slot. |
db3fe4eb | 10622 | */ |
600087b6 | 10623 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { |
db3fe4eb TY |
10624 | unsigned long j; |
10625 | ||
10626 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 10627 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
10628 | } |
10629 | } | |
10630 | ||
21ebbeda XG |
10631 | if (kvm_page_track_create_memslot(slot, npages)) |
10632 | goto out_free; | |
10633 | ||
db3fe4eb TY |
10634 | return 0; |
10635 | ||
10636 | out_free: | |
d89cc617 | 10637 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 10638 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
10639 | slot->arch.rmap[i] = NULL; |
10640 | if (i == 0) | |
10641 | continue; | |
10642 | ||
548ef284 | 10643 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 10644 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
10645 | } |
10646 | return -ENOMEM; | |
10647 | } | |
10648 | ||
15248258 | 10649 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 10650 | { |
91724814 BO |
10651 | struct kvm_vcpu *vcpu; |
10652 | int i; | |
10653 | ||
e6dff7d1 TY |
10654 | /* |
10655 | * memslots->generation has been incremented. | |
10656 | * mmio generation may have reached its maximum value. | |
10657 | */ | |
15248258 | 10658 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
10659 | |
10660 | /* Force re-initialization of steal_time cache */ | |
10661 | kvm_for_each_vcpu(i, vcpu, kvm) | |
10662 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
10663 | } |
10664 | ||
f7784b8e MT |
10665 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
10666 | struct kvm_memory_slot *memslot, | |
09170a49 | 10667 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 10668 | enum kvm_mr_change change) |
0de10343 | 10669 | { |
0dab98b7 SC |
10670 | if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) |
10671 | return kvm_alloc_memslot_metadata(memslot, | |
10672 | mem->memory_size >> PAGE_SHIFT); | |
f7784b8e MT |
10673 | return 0; |
10674 | } | |
10675 | ||
88178fd4 | 10676 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
3741679b AY |
10677 | struct kvm_memory_slot *old, |
10678 | struct kvm_memory_slot *new, | |
10679 | enum kvm_mr_change change) | |
88178fd4 | 10680 | { |
3741679b AY |
10681 | /* |
10682 | * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot. | |
10683 | * See comments below. | |
10684 | */ | |
10685 | if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) | |
88178fd4 | 10686 | return; |
88178fd4 KH |
10687 | |
10688 | /* | |
3741679b AY |
10689 | * Dirty logging tracks sptes in 4k granularity, meaning that large |
10690 | * sptes have to be split. If live migration is successful, the guest | |
10691 | * in the source machine will be destroyed and large sptes will be | |
10692 | * created in the destination. However, if the guest continues to run | |
10693 | * in the source machine (for example if live migration fails), small | |
10694 | * sptes will remain around and cause bad performance. | |
88178fd4 | 10695 | * |
3741679b AY |
10696 | * Scan sptes if dirty logging has been stopped, dropping those |
10697 | * which can be collapsed into a single large-page spte. Later | |
10698 | * page faults will create the large-page sptes. | |
88178fd4 | 10699 | * |
3741679b AY |
10700 | * There is no need to do this in any of the following cases: |
10701 | * CREATE: No dirty mappings will already exist. | |
10702 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
10703 | * kvm_arch_flush_shadow_memslot() | |
10704 | */ | |
10705 | if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) && | |
10706 | !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
10707 | kvm_mmu_zap_collapsible_sptes(kvm, new); | |
10708 | ||
10709 | /* | |
10710 | * Enable or disable dirty logging for the slot. | |
88178fd4 | 10711 | * |
3741679b AY |
10712 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old |
10713 | * slot have been zapped so no dirty logging updates are needed for | |
10714 | * the old slot. | |
10715 | * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible | |
10716 | * any mappings that might be created in it will consume the | |
10717 | * properties of the new slot and do not need to be updated here. | |
88178fd4 | 10718 | * |
3741679b AY |
10719 | * When PML is enabled, the kvm_x86_ops dirty logging hooks are |
10720 | * called to enable/disable dirty logging. | |
88178fd4 | 10721 | * |
3741679b AY |
10722 | * When disabling dirty logging with PML enabled, the D-bit is set |
10723 | * for sptes in the slot in order to prevent unnecessary GPA | |
10724 | * logging in the PML buffer (and potential PML buffer full VMEXIT). | |
10725 | * This guarantees leaving PML enabled for the guest's lifetime | |
10726 | * won't have any additional overhead from PML when the guest is | |
10727 | * running with dirty logging disabled. | |
88178fd4 | 10728 | * |
3741679b AY |
10729 | * When enabling dirty logging, large sptes are write-protected |
10730 | * so they can be split on first write. New large sptes cannot | |
10731 | * be created for this slot until the end of the logging. | |
88178fd4 | 10732 | * See the comments in fast_page_fault(). |
3741679b AY |
10733 | * For small sptes, nothing is done if the dirty log is in the |
10734 | * initial-all-set state. Otherwise, depending on whether pml | |
10735 | * is enabled the D-bit or the W-bit will be cleared. | |
88178fd4 KH |
10736 | */ |
10737 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
afaf0b2f SC |
10738 | if (kvm_x86_ops.slot_enable_log_dirty) { |
10739 | kvm_x86_ops.slot_enable_log_dirty(kvm, new); | |
3c9bd400 JZ |
10740 | } else { |
10741 | int level = | |
10742 | kvm_dirty_log_manual_protect_and_init_set(kvm) ? | |
3bae0459 | 10743 | PG_LEVEL_2M : PG_LEVEL_4K; |
3c9bd400 JZ |
10744 | |
10745 | /* | |
10746 | * If we're with initial-all-set, we don't need | |
10747 | * to write protect any small page because | |
10748 | * they're reported as dirty already. However | |
10749 | * we still need to write-protect huge pages | |
10750 | * so that the page split can happen lazily on | |
10751 | * the first write to the huge page. | |
10752 | */ | |
10753 | kvm_mmu_slot_remove_write_access(kvm, new, level); | |
10754 | } | |
88178fd4 | 10755 | } else { |
afaf0b2f SC |
10756 | if (kvm_x86_ops.slot_disable_log_dirty) |
10757 | kvm_x86_ops.slot_disable_log_dirty(kvm, new); | |
88178fd4 KH |
10758 | } |
10759 | } | |
10760 | ||
f7784b8e | 10761 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 10762 | const struct kvm_userspace_memory_region *mem, |
9d4c197c | 10763 | struct kvm_memory_slot *old, |
f36f3f28 | 10764 | const struct kvm_memory_slot *new, |
8482644a | 10765 | enum kvm_mr_change change) |
f7784b8e | 10766 | { |
48c0e4e9 | 10767 | if (!kvm->arch.n_requested_mmu_pages) |
4d66623c WY |
10768 | kvm_mmu_change_mmu_pages(kvm, |
10769 | kvm_mmu_calculate_default_mmu_pages(kvm)); | |
1c91cad4 | 10770 | |
3ea3b7fa | 10771 | /* |
f36f3f28 | 10772 | * FIXME: const-ify all uses of struct kvm_memory_slot. |
c972f3b1 | 10773 | */ |
3741679b | 10774 | kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change); |
21198846 SC |
10775 | |
10776 | /* Free the arrays associated with the old memslot. */ | |
10777 | if (change == KVM_MR_MOVE) | |
e96c81ee | 10778 | kvm_arch_free_memslot(kvm, old); |
0de10343 | 10779 | } |
1d737c8a | 10780 | |
2df72e9b | 10781 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 10782 | { |
7390de1e | 10783 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
10784 | } |
10785 | ||
2df72e9b MT |
10786 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
10787 | struct kvm_memory_slot *slot) | |
10788 | { | |
ae7cd873 | 10789 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
10790 | } |
10791 | ||
e6c67d8c LA |
10792 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
10793 | { | |
10794 | return (is_guest_mode(vcpu) && | |
afaf0b2f SC |
10795 | kvm_x86_ops.guest_apic_has_interrupt && |
10796 | kvm_x86_ops.guest_apic_has_interrupt(vcpu)); | |
e6c67d8c LA |
10797 | } |
10798 | ||
5d9bc648 PB |
10799 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
10800 | { | |
10801 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
10802 | return true; | |
10803 | ||
10804 | if (kvm_apic_has_events(vcpu)) | |
10805 | return true; | |
10806 | ||
10807 | if (vcpu->arch.pv.pv_unhalted) | |
10808 | return true; | |
10809 | ||
a5f01f8e WL |
10810 | if (vcpu->arch.exception.pending) |
10811 | return true; | |
10812 | ||
47a66eed Z |
10813 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
10814 | (vcpu->arch.nmi_pending && | |
c300ab9f | 10815 | kvm_x86_ops.nmi_allowed(vcpu, false))) |
5d9bc648 PB |
10816 | return true; |
10817 | ||
47a66eed | 10818 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
a9fa7cb6 | 10819 | (vcpu->arch.smi_pending && |
c300ab9f | 10820 | kvm_x86_ops.smi_allowed(vcpu, false))) |
73917739 PB |
10821 | return true; |
10822 | ||
5d9bc648 | 10823 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
10824 | (kvm_cpu_has_interrupt(vcpu) || |
10825 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
10826 | return true; |
10827 | ||
1f4b34f8 AS |
10828 | if (kvm_hv_has_stimer_pending(vcpu)) |
10829 | return true; | |
10830 | ||
d2060bd4 SC |
10831 | if (is_guest_mode(vcpu) && |
10832 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
10833 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
10834 | return true; | |
10835 | ||
5d9bc648 PB |
10836 | return false; |
10837 | } | |
10838 | ||
1d737c8a ZX |
10839 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
10840 | { | |
5d9bc648 | 10841 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 10842 | } |
5736199a | 10843 | |
17e433b5 WL |
10844 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
10845 | { | |
10846 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
10847 | return true; | |
10848 | ||
10849 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
10850 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
10851 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
10852 | return true; | |
10853 | ||
afaf0b2f | 10854 | if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu)) |
17e433b5 WL |
10855 | return true; |
10856 | ||
10857 | return false; | |
10858 | } | |
10859 | ||
199b5763 LM |
10860 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
10861 | { | |
de63ad4c | 10862 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
10863 | } |
10864 | ||
b6d33834 | 10865 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 10866 | { |
b6d33834 | 10867 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 10868 | } |
78646121 GN |
10869 | |
10870 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
10871 | { | |
c300ab9f | 10872 | return kvm_x86_ops.interrupt_allowed(vcpu, false); |
78646121 | 10873 | } |
229456fc | 10874 | |
82b32774 | 10875 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 10876 | { |
7ed9abfe TL |
10877 | /* Can't read the RIP when guest state is protected, just return 0 */ |
10878 | if (vcpu->arch.guest_state_protected) | |
10879 | return 0; | |
10880 | ||
82b32774 NA |
10881 | if (is_64_bit_mode(vcpu)) |
10882 | return kvm_rip_read(vcpu); | |
10883 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
10884 | kvm_rip_read(vcpu)); | |
10885 | } | |
10886 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 10887 | |
82b32774 NA |
10888 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
10889 | { | |
10890 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
10891 | } |
10892 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
10893 | ||
94fe45da JK |
10894 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
10895 | { | |
10896 | unsigned long rflags; | |
10897 | ||
afaf0b2f | 10898 | rflags = kvm_x86_ops.get_rflags(vcpu); |
94fe45da | 10899 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
c310bac5 | 10900 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
10901 | return rflags; |
10902 | } | |
10903 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
10904 | ||
6addfc42 | 10905 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
10906 | { |
10907 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 10908 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 10909 | rflags |= X86_EFLAGS_TF; |
afaf0b2f | 10910 | kvm_x86_ops.set_rflags(vcpu, rflags); |
6addfc42 PB |
10911 | } |
10912 | ||
10913 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
10914 | { | |
10915 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 10916 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
10917 | } |
10918 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
10919 | ||
56028d08 GN |
10920 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
10921 | { | |
10922 | int r; | |
10923 | ||
44dd3ffa | 10924 | if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || |
f2e10669 | 10925 | work->wakeup_all) |
56028d08 GN |
10926 | return; |
10927 | ||
10928 | r = kvm_mmu_reload(vcpu); | |
10929 | if (unlikely(r)) | |
10930 | return; | |
10931 | ||
44dd3ffa | 10932 | if (!vcpu->arch.mmu->direct_map && |
d8dd54e0 | 10933 | work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) |
fb67e14f XG |
10934 | return; |
10935 | ||
7a02674d | 10936 | kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); |
56028d08 GN |
10937 | } |
10938 | ||
af585b92 GN |
10939 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
10940 | { | |
dd03bcaa PX |
10941 | BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); |
10942 | ||
af585b92 GN |
10943 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); |
10944 | } | |
10945 | ||
10946 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
10947 | { | |
dd03bcaa | 10948 | return (key + 1) & (ASYNC_PF_PER_VCPU - 1); |
af585b92 GN |
10949 | } |
10950 | ||
10951 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10952 | { | |
10953 | u32 key = kvm_async_pf_hash_fn(gfn); | |
10954 | ||
10955 | while (vcpu->arch.apf.gfns[key] != ~0) | |
10956 | key = kvm_async_pf_next_probe(key); | |
10957 | ||
10958 | vcpu->arch.apf.gfns[key] = gfn; | |
10959 | } | |
10960 | ||
10961 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10962 | { | |
10963 | int i; | |
10964 | u32 key = kvm_async_pf_hash_fn(gfn); | |
10965 | ||
dd03bcaa | 10966 | for (i = 0; i < ASYNC_PF_PER_VCPU && |
c7d28c24 XG |
10967 | (vcpu->arch.apf.gfns[key] != gfn && |
10968 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
10969 | key = kvm_async_pf_next_probe(key); |
10970 | ||
10971 | return key; | |
10972 | } | |
10973 | ||
10974 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10975 | { | |
10976 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
10977 | } | |
10978 | ||
10979 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10980 | { | |
10981 | u32 i, j, k; | |
10982 | ||
10983 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
0fd46044 PX |
10984 | |
10985 | if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) | |
10986 | return; | |
10987 | ||
af585b92 GN |
10988 | while (true) { |
10989 | vcpu->arch.apf.gfns[i] = ~0; | |
10990 | do { | |
10991 | j = kvm_async_pf_next_probe(j); | |
10992 | if (vcpu->arch.apf.gfns[j] == ~0) | |
10993 | return; | |
10994 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
10995 | /* | |
10996 | * k lies cyclically in ]i,j] | |
10997 | * | i.k.j | | |
10998 | * |....j i.k.| or |.k..j i...| | |
10999 | */ | |
11000 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
11001 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
11002 | i = j; | |
11003 | } | |
11004 | } | |
11005 | ||
68fd66f1 | 11006 | static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) |
7c90705b | 11007 | { |
68fd66f1 VK |
11008 | u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; |
11009 | ||
11010 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, | |
11011 | sizeof(reason)); | |
11012 | } | |
11013 | ||
11014 | static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) | |
11015 | { | |
2635b5c4 | 11016 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); |
4e335d9e | 11017 | |
2635b5c4 VK |
11018 | return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, |
11019 | &token, offset, sizeof(token)); | |
11020 | } | |
11021 | ||
11022 | static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) | |
11023 | { | |
11024 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); | |
11025 | u32 val; | |
11026 | ||
11027 | if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, | |
11028 | &val, offset, sizeof(val))) | |
11029 | return false; | |
11030 | ||
11031 | return !val; | |
7c90705b GN |
11032 | } |
11033 | ||
1dfdb45e PB |
11034 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
11035 | { | |
11036 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) | |
11037 | return false; | |
11038 | ||
2635b5c4 VK |
11039 | if (!kvm_pv_async_pf_enabled(vcpu) || |
11040 | (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0)) | |
1dfdb45e PB |
11041 | return false; |
11042 | ||
11043 | return true; | |
11044 | } | |
11045 | ||
11046 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
11047 | { | |
11048 | if (unlikely(!lapic_in_kernel(vcpu) || | |
11049 | kvm_event_needs_reinjection(vcpu) || | |
11050 | vcpu->arch.exception.pending)) | |
11051 | return false; | |
11052 | ||
11053 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
11054 | return false; | |
11055 | ||
11056 | /* | |
11057 | * If interrupts are off we cannot even use an artificial | |
11058 | * halt state. | |
11059 | */ | |
c300ab9f | 11060 | return kvm_arch_interrupt_allowed(vcpu); |
1dfdb45e PB |
11061 | } |
11062 | ||
2a18b7e7 | 11063 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
11064 | struct kvm_async_pf *work) |
11065 | { | |
6389ee94 AK |
11066 | struct x86_exception fault; |
11067 | ||
736c291c | 11068 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 11069 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 11070 | |
1dfdb45e | 11071 | if (kvm_can_deliver_async_pf(vcpu) && |
68fd66f1 | 11072 | !apf_put_user_notpresent(vcpu)) { |
6389ee94 AK |
11073 | fault.vector = PF_VECTOR; |
11074 | fault.error_code_valid = true; | |
11075 | fault.error_code = 0; | |
11076 | fault.nested_page_fault = false; | |
11077 | fault.address = work->arch.token; | |
adfe20fb | 11078 | fault.async_page_fault = true; |
6389ee94 | 11079 | kvm_inject_page_fault(vcpu, &fault); |
2a18b7e7 | 11080 | return true; |
1dfdb45e PB |
11081 | } else { |
11082 | /* | |
11083 | * It is not possible to deliver a paravirtualized asynchronous | |
11084 | * page fault, but putting the guest in an artificial halt state | |
11085 | * can be beneficial nevertheless: if an interrupt arrives, we | |
11086 | * can deliver it timely and perhaps the guest will schedule | |
11087 | * another process. When the instruction that triggered a page | |
11088 | * fault is retried, hopefully the page will be ready in the host. | |
11089 | */ | |
11090 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2a18b7e7 | 11091 | return false; |
7c90705b | 11092 | } |
af585b92 GN |
11093 | } |
11094 | ||
11095 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
11096 | struct kvm_async_pf *work) | |
11097 | { | |
2635b5c4 VK |
11098 | struct kvm_lapic_irq irq = { |
11099 | .delivery_mode = APIC_DM_FIXED, | |
11100 | .vector = vcpu->arch.apf.vec | |
11101 | }; | |
6389ee94 | 11102 | |
f2e10669 | 11103 | if (work->wakeup_all) |
7c90705b GN |
11104 | work->arch.token = ~0; /* broadcast wakeup */ |
11105 | else | |
11106 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 11107 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 11108 | |
2a18b7e7 VK |
11109 | if ((work->wakeup_all || work->notpresent_injected) && |
11110 | kvm_pv_async_pf_enabled(vcpu) && | |
557a961a VK |
11111 | !apf_put_user_ready(vcpu, work->arch.token)) { |
11112 | vcpu->arch.apf.pageready_pending = true; | |
2635b5c4 | 11113 | kvm_apic_set_irq(vcpu, &irq, NULL); |
557a961a | 11114 | } |
2635b5c4 | 11115 | |
e6d53e3b | 11116 | vcpu->arch.apf.halted = false; |
a4fa1635 | 11117 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
11118 | } |
11119 | ||
557a961a VK |
11120 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) |
11121 | { | |
11122 | kvm_make_request(KVM_REQ_APF_READY, vcpu); | |
11123 | if (!vcpu->arch.apf.pageready_pending) | |
11124 | kvm_vcpu_kick(vcpu); | |
11125 | } | |
11126 | ||
7c0ade6c | 11127 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) |
7c90705b | 11128 | { |
2635b5c4 | 11129 | if (!kvm_pv_async_pf_enabled(vcpu)) |
7c90705b GN |
11130 | return true; |
11131 | else | |
2635b5c4 | 11132 | return apf_pageready_slot_free(vcpu); |
af585b92 GN |
11133 | } |
11134 | ||
5544eb9b PB |
11135 | void kvm_arch_start_assignment(struct kvm *kvm) |
11136 | { | |
11137 | atomic_inc(&kvm->arch.assigned_device_count); | |
11138 | } | |
11139 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
11140 | ||
11141 | void kvm_arch_end_assignment(struct kvm *kvm) | |
11142 | { | |
11143 | atomic_dec(&kvm->arch.assigned_device_count); | |
11144 | } | |
11145 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
11146 | ||
11147 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
11148 | { | |
11149 | return atomic_read(&kvm->arch.assigned_device_count); | |
11150 | } | |
11151 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
11152 | ||
e0f0bbc5 AW |
11153 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
11154 | { | |
11155 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
11156 | } | |
11157 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
11158 | ||
11159 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
11160 | { | |
11161 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
11162 | } | |
11163 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
11164 | ||
11165 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
11166 | { | |
11167 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
11168 | } | |
11169 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
11170 | ||
14717e20 AW |
11171 | bool kvm_arch_has_irq_bypass(void) |
11172 | { | |
92735b1b | 11173 | return true; |
14717e20 AW |
11174 | } |
11175 | ||
87276880 FW |
11176 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
11177 | struct irq_bypass_producer *prod) | |
11178 | { | |
11179 | struct kvm_kernel_irqfd *irqfd = | |
11180 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
2edd9cb7 | 11181 | int ret; |
87276880 | 11182 | |
14717e20 | 11183 | irqfd->producer = prod; |
2edd9cb7 ZL |
11184 | kvm_arch_start_assignment(irqfd->kvm); |
11185 | ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, | |
11186 | prod->irq, irqfd->gsi, 1); | |
11187 | ||
11188 | if (ret) | |
11189 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 | 11190 | |
2edd9cb7 | 11191 | return ret; |
87276880 FW |
11192 | } |
11193 | ||
11194 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
11195 | struct irq_bypass_producer *prod) | |
11196 | { | |
11197 | int ret; | |
11198 | struct kvm_kernel_irqfd *irqfd = | |
11199 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
11200 | ||
87276880 FW |
11201 | WARN_ON(irqfd->producer != prod); |
11202 | irqfd->producer = NULL; | |
11203 | ||
11204 | /* | |
11205 | * When producer of consumer is unregistered, we change back to | |
11206 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 11207 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
11208 | * int this case doesn't want to receive the interrupts. |
11209 | */ | |
afaf0b2f | 11210 | ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); |
87276880 FW |
11211 | if (ret) |
11212 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
11213 | " fails: %d\n", irqfd->consumer.token, ret); | |
2edd9cb7 ZL |
11214 | |
11215 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 FW |
11216 | } |
11217 | ||
11218 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
11219 | uint32_t guest_irq, bool set) | |
11220 | { | |
afaf0b2f | 11221 | return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set); |
87276880 FW |
11222 | } |
11223 | ||
52004014 FW |
11224 | bool kvm_vector_hashing_enabled(void) |
11225 | { | |
11226 | return vector_hashing; | |
11227 | } | |
52004014 | 11228 | |
2d5ba19b MT |
11229 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
11230 | { | |
11231 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
11232 | } | |
11233 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
11234 | ||
841c2be0 ML |
11235 | |
11236 | int kvm_spec_ctrl_test_value(u64 value) | |
6441fa61 | 11237 | { |
841c2be0 ML |
11238 | /* |
11239 | * test that setting IA32_SPEC_CTRL to given value | |
11240 | * is allowed by the host processor | |
11241 | */ | |
6441fa61 | 11242 | |
841c2be0 ML |
11243 | u64 saved_value; |
11244 | unsigned long flags; | |
11245 | int ret = 0; | |
6441fa61 | 11246 | |
841c2be0 | 11247 | local_irq_save(flags); |
6441fa61 | 11248 | |
841c2be0 ML |
11249 | if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) |
11250 | ret = 1; | |
11251 | else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) | |
11252 | ret = 1; | |
11253 | else | |
11254 | wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); | |
6441fa61 | 11255 | |
841c2be0 | 11256 | local_irq_restore(flags); |
6441fa61 | 11257 | |
841c2be0 | 11258 | return ret; |
6441fa61 | 11259 | } |
841c2be0 | 11260 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); |
2d5ba19b | 11261 | |
89786147 MG |
11262 | void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) |
11263 | { | |
11264 | struct x86_exception fault; | |
19cf4b7e PB |
11265 | u32 access = error_code & |
11266 | (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); | |
89786147 MG |
11267 | |
11268 | if (!(error_code & PFERR_PRESENT_MASK) || | |
19cf4b7e | 11269 | vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { |
89786147 MG |
11270 | /* |
11271 | * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page | |
11272 | * tables probably do not match the TLB. Just proceed | |
11273 | * with the error code that the processor gave. | |
11274 | */ | |
11275 | fault.vector = PF_VECTOR; | |
11276 | fault.error_code_valid = true; | |
11277 | fault.error_code = error_code; | |
11278 | fault.nested_page_fault = false; | |
11279 | fault.address = gva; | |
11280 | } | |
11281 | vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); | |
6441fa61 | 11282 | } |
89786147 | 11283 | EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); |
2d5ba19b | 11284 | |
3f3393b3 BM |
11285 | /* |
11286 | * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns | |
11287 | * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value | |
11288 | * indicates whether exit to userspace is needed. | |
11289 | */ | |
11290 | int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, | |
11291 | struct x86_exception *e) | |
11292 | { | |
11293 | if (r == X86EMUL_PROPAGATE_FAULT) { | |
11294 | kvm_inject_emulated_page_fault(vcpu, e); | |
11295 | return 1; | |
11296 | } | |
11297 | ||
11298 | /* | |
11299 | * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED | |
11300 | * while handling a VMX instruction KVM could've handled the request | |
11301 | * correctly by exiting to userspace and performing I/O but there | |
11302 | * doesn't seem to be a real use-case behind such requests, just return | |
11303 | * KVM_EXIT_INTERNAL_ERROR for now. | |
11304 | */ | |
11305 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
11306 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
11307 | vcpu->run->internal.ndata = 0; | |
11308 | ||
11309 | return 0; | |
11310 | } | |
11311 | EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); | |
11312 | ||
9715092f BM |
11313 | int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) |
11314 | { | |
11315 | bool pcid_enabled; | |
11316 | struct x86_exception e; | |
11317 | unsigned i; | |
11318 | unsigned long roots_to_free = 0; | |
11319 | struct { | |
11320 | u64 pcid; | |
11321 | u64 gla; | |
11322 | } operand; | |
11323 | int r; | |
11324 | ||
11325 | r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); | |
11326 | if (r != X86EMUL_CONTINUE) | |
11327 | return kvm_handle_memory_failure(vcpu, r, &e); | |
11328 | ||
11329 | if (operand.pcid >> 12 != 0) { | |
11330 | kvm_inject_gp(vcpu, 0); | |
11331 | return 1; | |
11332 | } | |
11333 | ||
11334 | pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); | |
11335 | ||
11336 | switch (type) { | |
11337 | case INVPCID_TYPE_INDIV_ADDR: | |
11338 | if ((!pcid_enabled && (operand.pcid != 0)) || | |
11339 | is_noncanonical_address(operand.gla, vcpu)) { | |
11340 | kvm_inject_gp(vcpu, 0); | |
11341 | return 1; | |
11342 | } | |
11343 | kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); | |
11344 | return kvm_skip_emulated_instruction(vcpu); | |
11345 | ||
11346 | case INVPCID_TYPE_SINGLE_CTXT: | |
11347 | if (!pcid_enabled && (operand.pcid != 0)) { | |
11348 | kvm_inject_gp(vcpu, 0); | |
11349 | return 1; | |
11350 | } | |
11351 | ||
11352 | if (kvm_get_active_pcid(vcpu) == operand.pcid) { | |
11353 | kvm_mmu_sync_roots(vcpu); | |
11354 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
11355 | } | |
11356 | ||
11357 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
11358 | if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd) | |
11359 | == operand.pcid) | |
11360 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
11361 | ||
11362 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); | |
11363 | /* | |
11364 | * If neither the current cr3 nor any of the prev_roots use the | |
11365 | * given PCID, then nothing needs to be done here because a | |
11366 | * resync will happen anyway before switching to any other CR3. | |
11367 | */ | |
11368 | ||
11369 | return kvm_skip_emulated_instruction(vcpu); | |
11370 | ||
11371 | case INVPCID_TYPE_ALL_NON_GLOBAL: | |
11372 | /* | |
11373 | * Currently, KVM doesn't mark global entries in the shadow | |
11374 | * page tables, so a non-global flush just degenerates to a | |
11375 | * global flush. If needed, we could optimize this later by | |
11376 | * keeping track of global entries in shadow page tables. | |
11377 | */ | |
11378 | ||
11379 | fallthrough; | |
11380 | case INVPCID_TYPE_ALL_INCL_GLOBAL: | |
11381 | kvm_mmu_unload(vcpu); | |
11382 | return kvm_skip_emulated_instruction(vcpu); | |
11383 | ||
11384 | default: | |
11385 | BUG(); /* We have already checked above that type <= 3 */ | |
11386 | } | |
11387 | } | |
11388 | EXPORT_SYMBOL_GPL(kvm_handle_invpcid); | |
11389 | ||
8f423a80 TL |
11390 | static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) |
11391 | { | |
11392 | struct kvm_run *run = vcpu->run; | |
11393 | struct kvm_mmio_fragment *frag; | |
11394 | unsigned int len; | |
11395 | ||
11396 | BUG_ON(!vcpu->mmio_needed); | |
11397 | ||
11398 | /* Complete previous fragment */ | |
11399 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; | |
11400 | len = min(8u, frag->len); | |
11401 | if (!vcpu->mmio_is_write) | |
11402 | memcpy(frag->data, run->mmio.data, len); | |
11403 | ||
11404 | if (frag->len <= 8) { | |
11405 | /* Switch to the next fragment. */ | |
11406 | frag++; | |
11407 | vcpu->mmio_cur_fragment++; | |
11408 | } else { | |
11409 | /* Go forward to the next mmio piece. */ | |
11410 | frag->data += len; | |
11411 | frag->gpa += len; | |
11412 | frag->len -= len; | |
11413 | } | |
11414 | ||
11415 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { | |
11416 | vcpu->mmio_needed = 0; | |
11417 | ||
11418 | // VMG change, at this point, we're always done | |
11419 | // RIP has already been advanced | |
11420 | return 1; | |
11421 | } | |
11422 | ||
11423 | // More MMIO is needed | |
11424 | run->mmio.phys_addr = frag->gpa; | |
11425 | run->mmio.len = min(8u, frag->len); | |
11426 | run->mmio.is_write = vcpu->mmio_is_write; | |
11427 | if (run->mmio.is_write) | |
11428 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); | |
11429 | run->exit_reason = KVM_EXIT_MMIO; | |
11430 | ||
11431 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
11432 | ||
11433 | return 0; | |
11434 | } | |
11435 | ||
11436 | int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
11437 | void *data) | |
11438 | { | |
11439 | int handled; | |
11440 | struct kvm_mmio_fragment *frag; | |
11441 | ||
11442 | if (!data) | |
11443 | return -EINVAL; | |
11444 | ||
11445 | handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
11446 | if (handled == bytes) | |
11447 | return 1; | |
11448 | ||
11449 | bytes -= handled; | |
11450 | gpa += handled; | |
11451 | data += handled; | |
11452 | ||
11453 | /*TODO: Check if need to increment number of frags */ | |
11454 | frag = vcpu->mmio_fragments; | |
11455 | vcpu->mmio_nr_fragments = 1; | |
11456 | frag->len = bytes; | |
11457 | frag->gpa = gpa; | |
11458 | frag->data = data; | |
11459 | ||
11460 | vcpu->mmio_needed = 1; | |
11461 | vcpu->mmio_cur_fragment = 0; | |
11462 | ||
11463 | vcpu->run->mmio.phys_addr = gpa; | |
11464 | vcpu->run->mmio.len = min(8u, frag->len); | |
11465 | vcpu->run->mmio.is_write = 1; | |
11466 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); | |
11467 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
11468 | ||
11469 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
11470 | ||
11471 | return 0; | |
11472 | } | |
11473 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); | |
11474 | ||
11475 | int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
11476 | void *data) | |
11477 | { | |
11478 | int handled; | |
11479 | struct kvm_mmio_fragment *frag; | |
11480 | ||
11481 | if (!data) | |
11482 | return -EINVAL; | |
11483 | ||
11484 | handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
11485 | if (handled == bytes) | |
11486 | return 1; | |
11487 | ||
11488 | bytes -= handled; | |
11489 | gpa += handled; | |
11490 | data += handled; | |
11491 | ||
11492 | /*TODO: Check if need to increment number of frags */ | |
11493 | frag = vcpu->mmio_fragments; | |
11494 | vcpu->mmio_nr_fragments = 1; | |
11495 | frag->len = bytes; | |
11496 | frag->gpa = gpa; | |
11497 | frag->data = data; | |
11498 | ||
11499 | vcpu->mmio_needed = 1; | |
11500 | vcpu->mmio_cur_fragment = 0; | |
11501 | ||
11502 | vcpu->run->mmio.phys_addr = gpa; | |
11503 | vcpu->run->mmio.len = min(8u, frag->len); | |
11504 | vcpu->run->mmio.is_write = 0; | |
11505 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
11506 | ||
11507 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
11508 | ||
11509 | return 0; | |
11510 | } | |
11511 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); | |
11512 | ||
7ed9abfe TL |
11513 | static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) |
11514 | { | |
11515 | memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data, | |
11516 | vcpu->arch.pio.count * vcpu->arch.pio.size); | |
11517 | vcpu->arch.pio.count = 0; | |
11518 | ||
11519 | return 1; | |
11520 | } | |
11521 | ||
11522 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, | |
11523 | unsigned int port, void *data, unsigned int count) | |
11524 | { | |
11525 | int ret; | |
11526 | ||
11527 | ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port, | |
11528 | data, count); | |
11529 | if (ret) | |
11530 | return ret; | |
11531 | ||
11532 | vcpu->arch.pio.count = 0; | |
11533 | ||
11534 | return 0; | |
11535 | } | |
11536 | ||
11537 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, | |
11538 | unsigned int port, void *data, unsigned int count) | |
11539 | { | |
11540 | int ret; | |
11541 | ||
11542 | ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port, | |
11543 | data, count); | |
11544 | if (ret) { | |
11545 | vcpu->arch.pio.count = 0; | |
11546 | } else { | |
11547 | vcpu->arch.guest_ins_data = data; | |
11548 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; | |
11549 | } | |
11550 | ||
11551 | return 0; | |
11552 | } | |
11553 | ||
11554 | int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, | |
11555 | unsigned int port, void *data, unsigned int count, | |
11556 | int in) | |
11557 | { | |
11558 | return in ? kvm_sev_es_ins(vcpu, size, port, data, count) | |
11559 | : kvm_sev_es_outs(vcpu, size, port, data, count); | |
11560 | } | |
11561 | EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); | |
11562 | ||
229456fc | 11563 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 11564 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
11565 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
11566 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
11567 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
11568 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 11569 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 11570 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 11571 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 11572 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 11573 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 11574 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 11575 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 11576 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 11577 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 11578 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 11579 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 11580 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
11581 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
11582 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
ab56f8e6 | 11583 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); |
24bbf74c | 11584 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); |
d523ab6b TL |
11585 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); |
11586 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); | |
59e38b58 TL |
11587 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); |
11588 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); |