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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
88197e6a | 21 | #include "ioapic.h" |
1d737c8a | 22 | #include "mmu.h" |
7837699f | 23 | #include "i8254.h" |
37817f29 | 24 | #include "tss.h" |
5fdbf976 | 25 | #include "kvm_cache_regs.h" |
2f728d66 | 26 | #include "kvm_emulate.h" |
26eef70c | 27 | #include "x86.h" |
00b27a3e | 28 | #include "cpuid.h" |
474a5bb9 | 29 | #include "pmu.h" |
e83d5887 | 30 | #include "hyperv.h" |
8df14af4 | 31 | #include "lapic.h" |
23200b7a | 32 | #include "xen.h" |
313a3dc7 | 33 | |
18068523 | 34 | #include <linux/clocksource.h> |
4d5c5d0f | 35 | #include <linux/interrupt.h> |
313a3dc7 CO |
36 | #include <linux/kvm.h> |
37 | #include <linux/fs.h> | |
38 | #include <linux/vmalloc.h> | |
1767e931 PG |
39 | #include <linux/export.h> |
40 | #include <linux/moduleparam.h> | |
0de10343 | 41 | #include <linux/mman.h> |
2bacc55c | 42 | #include <linux/highmem.h> |
19de40a8 | 43 | #include <linux/iommu.h> |
62c476c7 | 44 | #include <linux/intel-iommu.h> |
c8076604 | 45 | #include <linux/cpufreq.h> |
18863bdd | 46 | #include <linux/user-return-notifier.h> |
a983fb23 | 47 | #include <linux/srcu.h> |
5a0e3ad6 | 48 | #include <linux/slab.h> |
ff9d07a0 | 49 | #include <linux/perf_event.h> |
7bee342a | 50 | #include <linux/uaccess.h> |
af585b92 | 51 | #include <linux/hash.h> |
a1b60c1c | 52 | #include <linux/pci.h> |
16e8d74d MT |
53 | #include <linux/timekeeper_internal.h> |
54 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
55 | #include <linux/kvm_irqfd.h> |
56 | #include <linux/irqbypass.h> | |
3905f9ad | 57 | #include <linux/sched/stat.h> |
0c5f81da | 58 | #include <linux/sched/isolation.h> |
d0ec49d4 | 59 | #include <linux/mem_encrypt.h> |
72c3c0fe | 60 | #include <linux/entry-kvm.h> |
3905f9ad | 61 | |
aec51dc4 | 62 | #include <trace/events/kvm.h> |
2ed152af | 63 | |
24f1e32c | 64 | #include <asm/debugreg.h> |
d825ed0a | 65 | #include <asm/msr.h> |
a5f61300 | 66 | #include <asm/desc.h> |
890ca9ae | 67 | #include <asm/mce.h> |
f89e32e0 | 68 | #include <linux/kernel_stat.h> |
78f7f1e5 | 69 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 70 | #include <asm/pvclock.h> |
217fc9cf | 71 | #include <asm/div64.h> |
efc64404 | 72 | #include <asm/irq_remapping.h> |
b0c39dc6 | 73 | #include <asm/mshyperv.h> |
0092e434 | 74 | #include <asm/hypervisor.h> |
9715092f | 75 | #include <asm/tlbflush.h> |
bf8c55d8 | 76 | #include <asm/intel_pt.h> |
b3dc0695 | 77 | #include <asm/emulate_prefix.h> |
fe7e9488 | 78 | #include <asm/sgx.h> |
dd2cb348 | 79 | #include <clocksource/hyperv_timer.h> |
043405e1 | 80 | |
d1898b73 DH |
81 | #define CREATE_TRACE_POINTS |
82 | #include "trace.h" | |
83 | ||
313a3dc7 | 84 | #define MAX_IO_MSRS 256 |
890ca9ae | 85 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
86 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
87 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 88 | |
0f65dd70 | 89 | #define emul_to_vcpu(ctxt) \ |
c9b8b07c | 90 | ((struct kvm_vcpu *)(ctxt)->vcpu) |
0f65dd70 | 91 | |
50a37eb4 JR |
92 | /* EFER defaults: |
93 | * - enable syscall per default because its emulated by KVM | |
94 | * - enable LME and LMA per default on 64 bit KVM | |
95 | */ | |
96 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
97 | static |
98 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 99 | #else |
1260edbe | 100 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 101 | #endif |
313a3dc7 | 102 | |
b11306b5 SC |
103 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
104 | ||
c519265f RK |
105 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
106 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 107 | |
cb142eb7 | 108 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 109 | static void process_nmi(struct kvm_vcpu *vcpu); |
1f7becf1 | 110 | static void process_smi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 111 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 112 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
113 | static void store_regs(struct kvm_vcpu *vcpu); |
114 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 115 | |
afaf0b2f | 116 | struct kvm_x86_ops kvm_x86_ops __read_mostly; |
5fdbf976 | 117 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 118 | |
9af5471b JB |
119 | #define KVM_X86_OP(func) \ |
120 | DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ | |
121 | *(((struct kvm_x86_ops *)0)->func)); | |
122 | #define KVM_X86_OP_NULL KVM_X86_OP | |
123 | #include <asm/kvm-x86-ops.h> | |
124 | EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); | |
125 | EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); | |
126 | EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); | |
127 | ||
893590c7 | 128 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 129 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 130 | |
d855066f | 131 | bool __read_mostly report_ignored_msrs = true; |
fab0aa3b | 132 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); |
d855066f | 133 | EXPORT_SYMBOL_GPL(report_ignored_msrs); |
fab0aa3b | 134 | |
4c27625b | 135 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
136 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
137 | ||
630994b3 MT |
138 | static bool __read_mostly kvmclock_periodic_sync = true; |
139 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
140 | ||
893590c7 | 141 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 142 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 143 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 144 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
145 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
146 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
147 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
148 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
149 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
150 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
fe6b6bc8 CQ |
151 | bool __read_mostly kvm_has_bus_lock_exit; |
152 | EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); | |
92a1f12d | 153 | |
cc578287 | 154 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 155 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
156 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
157 | ||
c3941d9e SC |
158 | /* |
159 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
d9f6e12f | 160 | * adaptive tuning starting from default advancement of 1000ns. '0' disables |
c3941d9e | 161 | * advancement entirely. Any other value is used as-is and disables adaptive |
d9f6e12f | 162 | * tuning, i.e. allows privileged userspace to set an exact advancement time. |
c3941d9e SC |
163 | */ |
164 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 165 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 166 | |
52004014 FW |
167 | static bool __read_mostly vector_hashing = true; |
168 | module_param(vector_hashing, bool, S_IRUGO); | |
169 | ||
c4ae60e4 LA |
170 | bool __read_mostly enable_vmware_backdoor = false; |
171 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
172 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
173 | ||
6c86eedc WL |
174 | static bool __read_mostly force_emulation_prefix = false; |
175 | module_param(force_emulation_prefix, bool, S_IRUGO); | |
176 | ||
0c5f81da WL |
177 | int __read_mostly pi_inject_timer = -1; |
178 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
179 | ||
7e34fbd0 SC |
180 | /* |
181 | * Restoring the host value for MSRs that are only consumed when running in | |
182 | * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU | |
183 | * returns to userspace, i.e. the kernel can run with the guest's value. | |
184 | */ | |
185 | #define KVM_MAX_NR_USER_RETURN_MSRS 16 | |
18863bdd | 186 | |
7e34fbd0 | 187 | struct kvm_user_return_msrs { |
18863bdd AK |
188 | struct user_return_notifier urn; |
189 | bool registered; | |
7e34fbd0 | 190 | struct kvm_user_return_msr_values { |
2bf78fa7 SY |
191 | u64 host; |
192 | u64 curr; | |
7e34fbd0 | 193 | } values[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
194 | }; |
195 | ||
9cc39a5a SC |
196 | u32 __read_mostly kvm_nr_uret_msrs; |
197 | EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); | |
198 | static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; | |
7e34fbd0 | 199 | static struct kvm_user_return_msrs __percpu *user_return_msrs; |
18863bdd | 200 | |
cfc48181 SC |
201 | #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ |
202 | | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | |
203 | | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | |
204 | | XFEATURE_MASK_PKRU) | |
205 | ||
91661989 SC |
206 | u64 __read_mostly host_efer; |
207 | EXPORT_SYMBOL_GPL(host_efer); | |
208 | ||
b96e6506 | 209 | bool __read_mostly allow_smaller_maxphyaddr = 0; |
3edd6839 MG |
210 | EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); |
211 | ||
86137773 TL |
212 | u64 __read_mostly host_xss; |
213 | EXPORT_SYMBOL_GPL(host_xss); | |
408e9a31 PB |
214 | u64 __read_mostly supported_xss; |
215 | EXPORT_SYMBOL_GPL(supported_xss); | |
139a12cf | 216 | |
417bc304 | 217 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
812756a8 EGE |
218 | VCPU_STAT("pf_fixed", pf_fixed), |
219 | VCPU_STAT("pf_guest", pf_guest), | |
220 | VCPU_STAT("tlb_flush", tlb_flush), | |
221 | VCPU_STAT("invlpg", invlpg), | |
222 | VCPU_STAT("exits", exits), | |
223 | VCPU_STAT("io_exits", io_exits), | |
224 | VCPU_STAT("mmio_exits", mmio_exits), | |
225 | VCPU_STAT("signal_exits", signal_exits), | |
226 | VCPU_STAT("irq_window", irq_window_exits), | |
227 | VCPU_STAT("nmi_window", nmi_window_exits), | |
228 | VCPU_STAT("halt_exits", halt_exits), | |
229 | VCPU_STAT("halt_successful_poll", halt_successful_poll), | |
230 | VCPU_STAT("halt_attempted_poll", halt_attempted_poll), | |
231 | VCPU_STAT("halt_poll_invalid", halt_poll_invalid), | |
232 | VCPU_STAT("halt_wakeup", halt_wakeup), | |
233 | VCPU_STAT("hypercalls", hypercalls), | |
234 | VCPU_STAT("request_irq", request_irq_exits), | |
235 | VCPU_STAT("irq_exits", irq_exits), | |
236 | VCPU_STAT("host_state_reload", host_state_reload), | |
237 | VCPU_STAT("fpu_reload", fpu_reload), | |
238 | VCPU_STAT("insn_emulation", insn_emulation), | |
239 | VCPU_STAT("insn_emulation_fail", insn_emulation_fail), | |
240 | VCPU_STAT("irq_injections", irq_injections), | |
241 | VCPU_STAT("nmi_injections", nmi_injections), | |
242 | VCPU_STAT("req_event", req_event), | |
243 | VCPU_STAT("l1d_flush", l1d_flush), | |
cb953129 DM |
244 | VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns), |
245 | VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns), | |
43c11d91 | 246 | VCPU_STAT("nested_run", nested_run), |
4a7132ef WL |
247 | VCPU_STAT("directed_yield_attempted", directed_yield_attempted), |
248 | VCPU_STAT("directed_yield_successful", directed_yield_successful), | |
812756a8 EGE |
249 | VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped), |
250 | VM_STAT("mmu_pte_write", mmu_pte_write), | |
812756a8 EGE |
251 | VM_STAT("mmu_pde_zapped", mmu_pde_zapped), |
252 | VM_STAT("mmu_flooded", mmu_flooded), | |
253 | VM_STAT("mmu_recycled", mmu_recycled), | |
254 | VM_STAT("mmu_cache_miss", mmu_cache_miss), | |
255 | VM_STAT("mmu_unsync", mmu_unsync), | |
256 | VM_STAT("remote_tlb_flush", remote_tlb_flush), | |
257 | VM_STAT("largepages", lpages, .mode = 0444), | |
258 | VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444), | |
259 | VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions), | |
417bc304 HB |
260 | { NULL } |
261 | }; | |
262 | ||
2acf923e | 263 | u64 __read_mostly host_xcr0; |
cfc48181 SC |
264 | u64 __read_mostly supported_xcr0; |
265 | EXPORT_SYMBOL_GPL(supported_xcr0); | |
2acf923e | 266 | |
80fbd280 | 267 | static struct kmem_cache *x86_fpu_cache; |
b666a4b6 | 268 | |
c9b8b07c SC |
269 | static struct kmem_cache *x86_emulator_cache; |
270 | ||
6abe9c13 PX |
271 | /* |
272 | * When called, it means the previous get/set msr reached an invalid msr. | |
cc4cb017 | 273 | * Return true if we want to ignore/silent this failed msr access. |
6abe9c13 | 274 | */ |
d632826f | 275 | static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) |
6abe9c13 PX |
276 | { |
277 | const char *op = write ? "wrmsr" : "rdmsr"; | |
278 | ||
279 | if (ignore_msrs) { | |
280 | if (report_ignored_msrs) | |
d383b314 TI |
281 | kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", |
282 | op, msr, data); | |
6abe9c13 | 283 | /* Mask the error */ |
cc4cb017 | 284 | return true; |
6abe9c13 | 285 | } else { |
d383b314 TI |
286 | kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", |
287 | op, msr, data); | |
cc4cb017 | 288 | return false; |
6abe9c13 PX |
289 | } |
290 | } | |
291 | ||
c9b8b07c SC |
292 | static struct kmem_cache *kvm_alloc_emulator_cache(void) |
293 | { | |
06add254 SC |
294 | unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); |
295 | unsigned int size = sizeof(struct x86_emulate_ctxt); | |
296 | ||
297 | return kmem_cache_create_usercopy("x86_emulator", size, | |
c9b8b07c | 298 | __alignof__(struct x86_emulate_ctxt), |
06add254 SC |
299 | SLAB_ACCOUNT, useroffset, |
300 | size - useroffset, NULL); | |
c9b8b07c SC |
301 | } |
302 | ||
b6785def | 303 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 304 | |
af585b92 GN |
305 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
306 | { | |
307 | int i; | |
dd03bcaa | 308 | for (i = 0; i < ASYNC_PF_PER_VCPU; i++) |
af585b92 GN |
309 | vcpu->arch.apf.gfns[i] = ~0; |
310 | } | |
311 | ||
18863bdd AK |
312 | static void kvm_on_user_return(struct user_return_notifier *urn) |
313 | { | |
314 | unsigned slot; | |
7e34fbd0 SC |
315 | struct kvm_user_return_msrs *msrs |
316 | = container_of(urn, struct kvm_user_return_msrs, urn); | |
317 | struct kvm_user_return_msr_values *values; | |
1650b4eb IA |
318 | unsigned long flags; |
319 | ||
320 | /* | |
321 | * Disabling irqs at this point since the following code could be | |
322 | * interrupted and executed through kvm_arch_hardware_disable() | |
323 | */ | |
324 | local_irq_save(flags); | |
7e34fbd0 SC |
325 | if (msrs->registered) { |
326 | msrs->registered = false; | |
1650b4eb IA |
327 | user_return_notifier_unregister(urn); |
328 | } | |
329 | local_irq_restore(flags); | |
9cc39a5a | 330 | for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { |
7e34fbd0 | 331 | values = &msrs->values[slot]; |
2bf78fa7 | 332 | if (values->host != values->curr) { |
9cc39a5a | 333 | wrmsrl(kvm_uret_msrs_list[slot], values->host); |
2bf78fa7 | 334 | values->curr = values->host; |
18863bdd AK |
335 | } |
336 | } | |
18863bdd AK |
337 | } |
338 | ||
e5fda4bb | 339 | static int kvm_probe_user_return_msr(u32 msr) |
5104d7ff SC |
340 | { |
341 | u64 val; | |
342 | int ret; | |
343 | ||
344 | preempt_disable(); | |
345 | ret = rdmsrl_safe(msr, &val); | |
346 | if (ret) | |
347 | goto out; | |
348 | ret = wrmsrl_safe(msr, val); | |
349 | out: | |
350 | preempt_enable(); | |
351 | return ret; | |
352 | } | |
5104d7ff | 353 | |
e5fda4bb | 354 | int kvm_add_user_return_msr(u32 msr) |
2bf78fa7 | 355 | { |
e5fda4bb SC |
356 | BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); |
357 | ||
358 | if (kvm_probe_user_return_msr(msr)) | |
359 | return -1; | |
360 | ||
361 | kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; | |
362 | return kvm_nr_uret_msrs++; | |
18863bdd | 363 | } |
e5fda4bb | 364 | EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); |
18863bdd | 365 | |
8ea8b8d6 | 366 | int kvm_find_user_return_msr(u32 msr) |
2bf78fa7 | 367 | { |
8ea8b8d6 SC |
368 | int i; |
369 | ||
9cc39a5a SC |
370 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
371 | if (kvm_uret_msrs_list[i] == msr) | |
8ea8b8d6 SC |
372 | return i; |
373 | } | |
374 | return -1; | |
18863bdd | 375 | } |
8ea8b8d6 | 376 | EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); |
18863bdd | 377 | |
7e34fbd0 | 378 | static void kvm_user_return_msr_cpu_online(void) |
18863bdd | 379 | { |
05c19c2f | 380 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 381 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
05c19c2f SC |
382 | u64 value; |
383 | int i; | |
18863bdd | 384 | |
9cc39a5a SC |
385 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
386 | rdmsrl_safe(kvm_uret_msrs_list[i], &value); | |
7e34fbd0 SC |
387 | msrs->values[i].host = value; |
388 | msrs->values[i].curr = value; | |
05c19c2f | 389 | } |
18863bdd AK |
390 | } |
391 | ||
7e34fbd0 | 392 | int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 393 | { |
013f6a5d | 394 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 395 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
8b3c3104 | 396 | int err; |
18863bdd | 397 | |
7e34fbd0 SC |
398 | value = (value & mask) | (msrs->values[slot].host & ~mask); |
399 | if (value == msrs->values[slot].curr) | |
8b3c3104 | 400 | return 0; |
9cc39a5a | 401 | err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); |
8b3c3104 AH |
402 | if (err) |
403 | return 1; | |
404 | ||
7e34fbd0 SC |
405 | msrs->values[slot].curr = value; |
406 | if (!msrs->registered) { | |
407 | msrs->urn.on_user_return = kvm_on_user_return; | |
408 | user_return_notifier_register(&msrs->urn); | |
409 | msrs->registered = true; | |
18863bdd | 410 | } |
8b3c3104 | 411 | return 0; |
18863bdd | 412 | } |
7e34fbd0 | 413 | EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); |
18863bdd | 414 | |
13a34e06 | 415 | static void drop_user_return_notifiers(void) |
3548bab5 | 416 | { |
013f6a5d | 417 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 418 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
3548bab5 | 419 | |
7e34fbd0 SC |
420 | if (msrs->registered) |
421 | kvm_on_user_return(&msrs->urn); | |
3548bab5 AK |
422 | } |
423 | ||
6866b83e CO |
424 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
425 | { | |
8a5a87d9 | 426 | return vcpu->arch.apic_base; |
6866b83e CO |
427 | } |
428 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
429 | ||
58871649 JM |
430 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
431 | { | |
432 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
433 | } | |
434 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
435 | ||
58cb628d JK |
436 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
437 | { | |
58871649 JM |
438 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
439 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
a8ac864a | 440 | u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | |
d6321d49 | 441 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); |
58cb628d | 442 | |
58871649 | 443 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 444 | return 1; |
58871649 JM |
445 | if (!msr_info->host_initiated) { |
446 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
447 | return 1; | |
448 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
449 | return 1; | |
450 | } | |
58cb628d JK |
451 | |
452 | kvm_lapic_set_base(vcpu, msr_info->data); | |
4abaffce | 453 | kvm_recalculate_apic_map(vcpu->kvm); |
58cb628d | 454 | return 0; |
6866b83e CO |
455 | } |
456 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
457 | ||
3ebccdf3 | 458 | asmlinkage __visible noinstr void kvm_spurious_fault(void) |
e3ba45b8 GL |
459 | { |
460 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 461 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
462 | } |
463 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
464 | ||
3fd28fce ED |
465 | #define EXCPT_BENIGN 0 |
466 | #define EXCPT_CONTRIBUTORY 1 | |
467 | #define EXCPT_PF 2 | |
468 | ||
469 | static int exception_class(int vector) | |
470 | { | |
471 | switch (vector) { | |
472 | case PF_VECTOR: | |
473 | return EXCPT_PF; | |
474 | case DE_VECTOR: | |
475 | case TS_VECTOR: | |
476 | case NP_VECTOR: | |
477 | case SS_VECTOR: | |
478 | case GP_VECTOR: | |
479 | return EXCPT_CONTRIBUTORY; | |
480 | default: | |
481 | break; | |
482 | } | |
483 | return EXCPT_BENIGN; | |
484 | } | |
485 | ||
d6e8c854 NA |
486 | #define EXCPT_FAULT 0 |
487 | #define EXCPT_TRAP 1 | |
488 | #define EXCPT_ABORT 2 | |
489 | #define EXCPT_INTERRUPT 3 | |
490 | ||
491 | static int exception_type(int vector) | |
492 | { | |
493 | unsigned int mask; | |
494 | ||
495 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
496 | return EXCPT_INTERRUPT; | |
497 | ||
498 | mask = 1 << vector; | |
499 | ||
500 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
501 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
502 | return EXCPT_TRAP; | |
503 | ||
504 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
505 | return EXCPT_ABORT; | |
506 | ||
507 | /* Reserved exceptions will result in fault */ | |
508 | return EXCPT_FAULT; | |
509 | } | |
510 | ||
da998b46 JM |
511 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
512 | { | |
513 | unsigned nr = vcpu->arch.exception.nr; | |
514 | bool has_payload = vcpu->arch.exception.has_payload; | |
515 | unsigned long payload = vcpu->arch.exception.payload; | |
516 | ||
517 | if (!has_payload) | |
518 | return; | |
519 | ||
520 | switch (nr) { | |
f10c729f JM |
521 | case DB_VECTOR: |
522 | /* | |
523 | * "Certain debug exceptions may clear bit 0-3. The | |
524 | * remaining contents of the DR6 register are never | |
525 | * cleared by the processor". | |
526 | */ | |
527 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
528 | /* | |
9a3ecd5e CQ |
529 | * In order to reflect the #DB exception payload in guest |
530 | * dr6, three components need to be considered: active low | |
531 | * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, | |
532 | * DR6_BS and DR6_BT) | |
533 | * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. | |
534 | * In the target guest dr6: | |
535 | * FIXED_1 bits should always be set. | |
536 | * Active low bits should be cleared if 1-setting in payload. | |
537 | * Active high bits should be set if 1-setting in payload. | |
538 | * | |
539 | * Note, the payload is compatible with the pending debug | |
540 | * exceptions/exit qualification under VMX, that active_low bits | |
541 | * are active high in payload. | |
542 | * So they need to be flipped for DR6. | |
f10c729f | 543 | */ |
9a3ecd5e | 544 | vcpu->arch.dr6 |= DR6_ACTIVE_LOW; |
f10c729f | 545 | vcpu->arch.dr6 |= payload; |
9a3ecd5e | 546 | vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; |
307f1cfa OU |
547 | |
548 | /* | |
549 | * The #DB payload is defined as compatible with the 'pending | |
550 | * debug exceptions' field under VMX, not DR6. While bit 12 is | |
551 | * defined in the 'pending debug exceptions' field (enabled | |
552 | * breakpoint), it is reserved and must be zero in DR6. | |
553 | */ | |
554 | vcpu->arch.dr6 &= ~BIT(12); | |
f10c729f | 555 | break; |
da998b46 JM |
556 | case PF_VECTOR: |
557 | vcpu->arch.cr2 = payload; | |
558 | break; | |
559 | } | |
560 | ||
561 | vcpu->arch.exception.has_payload = false; | |
562 | vcpu->arch.exception.payload = 0; | |
563 | } | |
564 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
565 | ||
3fd28fce | 566 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 567 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 568 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
569 | { |
570 | u32 prev_nr; | |
571 | int class1, class2; | |
572 | ||
3842d135 AK |
573 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
574 | ||
664f8e26 | 575 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 576 | queue: |
664f8e26 WL |
577 | if (reinject) { |
578 | /* | |
579 | * On vmentry, vcpu->arch.exception.pending is only | |
580 | * true if an event injection was blocked by | |
581 | * nested_run_pending. In that case, however, | |
582 | * vcpu_enter_guest requests an immediate exit, | |
583 | * and the guest shouldn't proceed far enough to | |
584 | * need reinjection. | |
585 | */ | |
586 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
587 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
588 | if (WARN_ON_ONCE(has_payload)) { |
589 | /* | |
590 | * A reinjected event has already | |
591 | * delivered its payload. | |
592 | */ | |
593 | has_payload = false; | |
594 | payload = 0; | |
595 | } | |
664f8e26 WL |
596 | } else { |
597 | vcpu->arch.exception.pending = true; | |
598 | vcpu->arch.exception.injected = false; | |
599 | } | |
3fd28fce ED |
600 | vcpu->arch.exception.has_error_code = has_error; |
601 | vcpu->arch.exception.nr = nr; | |
602 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
603 | vcpu->arch.exception.has_payload = has_payload; |
604 | vcpu->arch.exception.payload = payload; | |
a06230b6 | 605 | if (!is_guest_mode(vcpu)) |
da998b46 | 606 | kvm_deliver_exception_payload(vcpu); |
3fd28fce ED |
607 | return; |
608 | } | |
609 | ||
610 | /* to check exception */ | |
611 | prev_nr = vcpu->arch.exception.nr; | |
612 | if (prev_nr == DF_VECTOR) { | |
613 | /* triple fault -> shutdown */ | |
a8eeb04a | 614 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
615 | return; |
616 | } | |
617 | class1 = exception_class(prev_nr); | |
618 | class2 = exception_class(nr); | |
619 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
620 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
621 | /* |
622 | * Generate double fault per SDM Table 5-5. Set | |
623 | * exception.pending = true so that the double fault | |
624 | * can trigger a nested vmexit. | |
625 | */ | |
3fd28fce | 626 | vcpu->arch.exception.pending = true; |
664f8e26 | 627 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
628 | vcpu->arch.exception.has_error_code = true; |
629 | vcpu->arch.exception.nr = DF_VECTOR; | |
630 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
631 | vcpu->arch.exception.has_payload = false; |
632 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
633 | } else |
634 | /* replace previous exception with a new one in a hope | |
635 | that instruction re-execution will regenerate lost | |
636 | exception */ | |
637 | goto queue; | |
638 | } | |
639 | ||
298101da AK |
640 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
641 | { | |
91e86d22 | 642 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
643 | } |
644 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
645 | ||
ce7ddec4 JR |
646 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
647 | { | |
91e86d22 | 648 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
649 | } |
650 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
651 | ||
4d5523cf PB |
652 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
653 | unsigned long payload) | |
f10c729f JM |
654 | { |
655 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
656 | } | |
4d5523cf | 657 | EXPORT_SYMBOL_GPL(kvm_queue_exception_p); |
f10c729f | 658 | |
da998b46 JM |
659 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
660 | u32 error_code, unsigned long payload) | |
661 | { | |
662 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
663 | true, payload, false); | |
664 | } | |
665 | ||
6affcbed | 666 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 667 | { |
db8fcefa AP |
668 | if (err) |
669 | kvm_inject_gp(vcpu, 0); | |
670 | else | |
6affcbed KH |
671 | return kvm_skip_emulated_instruction(vcpu); |
672 | ||
673 | return 1; | |
db8fcefa AP |
674 | } |
675 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 676 | |
6389ee94 | 677 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
678 | { |
679 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
680 | vcpu->arch.exception.nested_apf = |
681 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 682 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 683 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
684 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
685 | } else { | |
686 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
687 | fault->address); | |
688 | } | |
c3c91fee | 689 | } |
27d6c865 | 690 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 691 | |
53b3d8e9 SC |
692 | bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
693 | struct x86_exception *fault) | |
d4f8cf66 | 694 | { |
0cd665bd | 695 | struct kvm_mmu *fault_mmu; |
53b3d8e9 SC |
696 | WARN_ON_ONCE(fault->vector != PF_VECTOR); |
697 | ||
0cd665bd PB |
698 | fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : |
699 | vcpu->arch.walk_mmu; | |
ef54bcfe | 700 | |
ee1fa209 JS |
701 | /* |
702 | * Invalidate the TLB entry for the faulting address, if it exists, | |
703 | * else the access will fault indefinitely (and to emulate hardware). | |
704 | */ | |
705 | if ((fault->error_code & PFERR_PRESENT_MASK) && | |
706 | !(fault->error_code & PFERR_RSVD_MASK)) | |
707 | kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, | |
708 | fault_mmu->root_hpa); | |
709 | ||
710 | fault_mmu->inject_page_fault(vcpu, fault); | |
ef54bcfe | 711 | return fault->nested_page_fault; |
d4f8cf66 | 712 | } |
53b3d8e9 | 713 | EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); |
d4f8cf66 | 714 | |
3419ffc8 SY |
715 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
716 | { | |
7460fb4a AK |
717 | atomic_inc(&vcpu->arch.nmi_queued); |
718 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
719 | } |
720 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
721 | ||
298101da AK |
722 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
723 | { | |
91e86d22 | 724 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
725 | } |
726 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
727 | ||
ce7ddec4 JR |
728 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
729 | { | |
91e86d22 | 730 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
731 | } |
732 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
733 | ||
0a79b009 AK |
734 | /* |
735 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
736 | * a #GP and return false. | |
737 | */ | |
738 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 739 | { |
b3646477 | 740 | if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) |
0a79b009 AK |
741 | return true; |
742 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
743 | return false; | |
298101da | 744 | } |
0a79b009 | 745 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 746 | |
16f8a6f9 NA |
747 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
748 | { | |
749 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
750 | return true; | |
751 | ||
752 | kvm_queue_exception(vcpu, UD_VECTOR); | |
753 | return false; | |
754 | } | |
755 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
756 | ||
ec92fe44 JR |
757 | /* |
758 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 759 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
760 | * can read from guest physical or from the guest's guest physical memory. |
761 | */ | |
762 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
763 | gfn_t ngfn, void *data, int offset, int len, | |
764 | u32 access) | |
765 | { | |
54987b7a | 766 | struct x86_exception exception; |
ec92fe44 JR |
767 | gfn_t real_gfn; |
768 | gpa_t ngpa; | |
769 | ||
770 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 771 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
772 | if (real_gfn == UNMAPPED_GVA) |
773 | return -EFAULT; | |
774 | ||
775 | real_gfn = gpa_to_gfn(real_gfn); | |
776 | ||
54bf36aa | 777 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
778 | } |
779 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
780 | ||
69b0049a | 781 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
782 | void *data, int offset, int len, u32 access) |
783 | { | |
784 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
785 | data, offset, len, access); | |
786 | } | |
787 | ||
16cfacc8 SC |
788 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
789 | { | |
5b7f575c | 790 | return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); |
16cfacc8 SC |
791 | } |
792 | ||
a03490ed | 793 | /* |
16cfacc8 | 794 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 795 | */ |
ff03a073 | 796 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
797 | { |
798 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
799 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
800 | int i; | |
801 | int ret; | |
ff03a073 | 802 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 803 | |
ff03a073 JR |
804 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
805 | offset * sizeof(u64), sizeof(pdpte), | |
806 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
807 | if (ret < 0) { |
808 | ret = 0; | |
809 | goto out; | |
810 | } | |
811 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
812f30b2 | 812 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 813 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
a03490ed CO |
814 | ret = 0; |
815 | goto out; | |
816 | } | |
817 | } | |
818 | ret = 1; | |
819 | ||
ff03a073 | 820 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
cb3c1e2f SC |
821 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); |
822 | ||
a03490ed | 823 | out: |
a03490ed CO |
824 | |
825 | return ret; | |
826 | } | |
cc4b6871 | 827 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 828 | |
9ed38ffa | 829 | bool pdptrs_changed(struct kvm_vcpu *vcpu) |
d835dfec | 830 | { |
ff03a073 | 831 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
3d06b8bf JR |
832 | int offset; |
833 | gfn_t gfn; | |
d835dfec AK |
834 | int r; |
835 | ||
bf03d4f9 | 836 | if (!is_pae_paging(vcpu)) |
d835dfec AK |
837 | return false; |
838 | ||
cb3c1e2f | 839 | if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) |
6de4f3ad AK |
840 | return true; |
841 | ||
a512177e PB |
842 | gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; |
843 | offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
844 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
845 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec | 846 | if (r < 0) |
7f7f0d9c | 847 | return true; |
d835dfec | 848 | |
7f7f0d9c | 849 | return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 850 | } |
9ed38ffa | 851 | EXPORT_SYMBOL_GPL(pdptrs_changed); |
d835dfec | 852 | |
f27ad38a TL |
853 | void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) |
854 | { | |
855 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; | |
856 | ||
857 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { | |
858 | kvm_clear_async_pf_completion_queue(vcpu); | |
859 | kvm_async_pf_hash_reset(vcpu); | |
860 | } | |
861 | ||
862 | if ((cr0 ^ old_cr0) & update_bits) | |
863 | kvm_mmu_reset_context(vcpu); | |
864 | ||
865 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && | |
866 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
867 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
868 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); | |
869 | } | |
870 | EXPORT_SYMBOL_GPL(kvm_post_set_cr0); | |
871 | ||
49a9b07e | 872 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 873 | { |
aad82703 | 874 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d42e3fae | 875 | unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; |
aad82703 | 876 | |
f9a48e6a AK |
877 | cr0 |= X86_CR0_ET; |
878 | ||
ab344828 | 879 | #ifdef CONFIG_X86_64 |
0f12244f GN |
880 | if (cr0 & 0xffffffff00000000UL) |
881 | return 1; | |
ab344828 GN |
882 | #endif |
883 | ||
884 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 885 | |
0f12244f GN |
886 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
887 | return 1; | |
a03490ed | 888 | |
0f12244f GN |
889 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
890 | return 1; | |
a03490ed | 891 | |
a03490ed | 892 | #ifdef CONFIG_X86_64 |
05487215 SC |
893 | if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && |
894 | (cr0 & X86_CR0_PG)) { | |
895 | int cs_db, cs_l; | |
896 | ||
897 | if (!is_pae(vcpu)) | |
898 | return 1; | |
b3646477 | 899 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
05487215 | 900 | if (cs_l) |
0f12244f | 901 | return 1; |
a03490ed | 902 | } |
05487215 SC |
903 | #endif |
904 | if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && | |
905 | is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && | |
906 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) | |
907 | return 1; | |
a03490ed | 908 | |
ad756a16 MJ |
909 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
910 | return 1; | |
911 | ||
b3646477 | 912 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
a03490ed | 913 | |
f27ad38a | 914 | kvm_post_set_cr0(vcpu, old_cr0, cr0); |
b18d5431 | 915 | |
0f12244f GN |
916 | return 0; |
917 | } | |
2d3ad1f4 | 918 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 919 | |
2d3ad1f4 | 920 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 921 | { |
49a9b07e | 922 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 923 | } |
2d3ad1f4 | 924 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 925 | |
139a12cf | 926 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 927 | { |
16809ecd TL |
928 | if (vcpu->arch.guest_state_protected) |
929 | return; | |
930 | ||
139a12cf AL |
931 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
932 | ||
933 | if (vcpu->arch.xcr0 != host_xcr0) | |
934 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
935 | ||
936 | if (vcpu->arch.xsaves_enabled && | |
937 | vcpu->arch.ia32_xss != host_xss) | |
938 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
939 | } | |
37486135 BM |
940 | |
941 | if (static_cpu_has(X86_FEATURE_PKU) && | |
942 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
943 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && | |
944 | vcpu->arch.pkru != vcpu->arch.host_pkru) | |
945 | __write_pkru(vcpu->arch.pkru); | |
42bdf991 | 946 | } |
139a12cf | 947 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 948 | |
139a12cf | 949 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 950 | { |
16809ecd TL |
951 | if (vcpu->arch.guest_state_protected) |
952 | return; | |
953 | ||
37486135 BM |
954 | if (static_cpu_has(X86_FEATURE_PKU) && |
955 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
956 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { | |
957 | vcpu->arch.pkru = rdpkru(); | |
958 | if (vcpu->arch.pkru != vcpu->arch.host_pkru) | |
959 | __write_pkru(vcpu->arch.host_pkru); | |
960 | } | |
961 | ||
139a12cf AL |
962 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
963 | ||
964 | if (vcpu->arch.xcr0 != host_xcr0) | |
965 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
966 | ||
967 | if (vcpu->arch.xsaves_enabled && | |
968 | vcpu->arch.ia32_xss != host_xss) | |
969 | wrmsrl(MSR_IA32_XSS, host_xss); | |
970 | } | |
971 | ||
42bdf991 | 972 | } |
139a12cf | 973 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 974 | |
69b0049a | 975 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 976 | { |
56c103ec LJ |
977 | u64 xcr0 = xcr; |
978 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 979 | u64 valid_bits; |
2acf923e DC |
980 | |
981 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
982 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
983 | return 1; | |
d91cab78 | 984 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 985 | return 1; |
d91cab78 | 986 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 987 | return 1; |
46c34cb0 PB |
988 | |
989 | /* | |
990 | * Do not allow the guest to set bits that we do not support | |
991 | * saving. However, xcr0 bit 0 is always set, even if the | |
992 | * emulated CPU does not support XSAVE (see fx_init). | |
993 | */ | |
d91cab78 | 994 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 995 | if (xcr0 & ~valid_bits) |
2acf923e | 996 | return 1; |
46c34cb0 | 997 | |
d91cab78 DH |
998 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
999 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
1000 | return 1; |
1001 | ||
d91cab78 DH |
1002 | if (xcr0 & XFEATURE_MASK_AVX512) { |
1003 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 1004 | return 1; |
d91cab78 | 1005 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
1006 | return 1; |
1007 | } | |
2acf923e | 1008 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 1009 | |
d91cab78 | 1010 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
aedbaf4f | 1011 | kvm_update_cpuid_runtime(vcpu); |
2acf923e DC |
1012 | return 0; |
1013 | } | |
1014 | ||
92f9895c | 1015 | int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) |
2acf923e | 1016 | { |
92f9895c SC |
1017 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || |
1018 | __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { | |
1019 | kvm_inject_gp(vcpu, 0); | |
1020 | return 1; | |
1021 | } | |
bbefd4fc | 1022 | |
92f9895c | 1023 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e | 1024 | } |
92f9895c | 1025 | EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); |
2acf923e | 1026 | |
ee69c92b | 1027 | bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 1028 | { |
b11306b5 | 1029 | if (cr4 & cr4_reserved_bits) |
ee69c92b | 1030 | return false; |
b9baba86 | 1031 | |
b899c132 | 1032 | if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) |
ee69c92b | 1033 | return false; |
3ca94192 | 1034 | |
b3646477 | 1035 | return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); |
3ca94192 | 1036 | } |
ee69c92b | 1037 | EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); |
3ca94192 | 1038 | |
5b51cb13 TL |
1039 | void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) |
1040 | { | |
1041 | unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
1042 | X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; | |
1043 | ||
1044 | if (((cr4 ^ old_cr4) & mmu_role_bits) || | |
1045 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
1046 | kvm_mmu_reset_context(vcpu); | |
3ca94192 | 1047 | } |
5b51cb13 | 1048 | EXPORT_SYMBOL_GPL(kvm_post_set_cr4); |
3ca94192 WL |
1049 | |
1050 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1051 | { | |
1052 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
1053 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
cb957adb | 1054 | X86_CR4_SMEP; |
3ca94192 | 1055 | |
ee69c92b | 1056 | if (!kvm_is_valid_cr4(vcpu, cr4)) |
ae3e61e1 PB |
1057 | return 1; |
1058 | ||
a03490ed | 1059 | if (is_long_mode(vcpu)) { |
0f12244f GN |
1060 | if (!(cr4 & X86_CR4_PAE)) |
1061 | return 1; | |
d74fcfc1 SC |
1062 | if ((cr4 ^ old_cr4) & X86_CR4_LA57) |
1063 | return 1; | |
a2edf57f AK |
1064 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
1065 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
1066 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
1067 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
1068 | return 1; |
1069 | ||
ad756a16 | 1070 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 1071 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
1072 | return 1; |
1073 | ||
1074 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
1075 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
1076 | return 1; | |
1077 | } | |
1078 | ||
b3646477 | 1079 | static_call(kvm_x86_set_cr4)(vcpu, cr4); |
a03490ed | 1080 | |
5b51cb13 | 1081 | kvm_post_set_cr4(vcpu, old_cr4, cr4); |
2acf923e | 1082 | |
0f12244f GN |
1083 | return 0; |
1084 | } | |
2d3ad1f4 | 1085 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 1086 | |
2390218b | 1087 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 1088 | { |
ade61e28 | 1089 | bool skip_tlb_flush = false; |
ac146235 | 1090 | #ifdef CONFIG_X86_64 |
c19986fe JS |
1091 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
1092 | ||
ade61e28 | 1093 | if (pcid_enabled) { |
208320ba JS |
1094 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
1095 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
ade61e28 | 1096 | } |
ac146235 | 1097 | #endif |
9d88fca7 | 1098 | |
9f8fe504 | 1099 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
956bf353 JS |
1100 | if (!skip_tlb_flush) { |
1101 | kvm_mmu_sync_roots(vcpu); | |
eeeb4f67 | 1102 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
956bf353 | 1103 | } |
0f12244f | 1104 | return 0; |
d835dfec AK |
1105 | } |
1106 | ||
886bbcc7 SC |
1107 | /* |
1108 | * Do not condition the GPA check on long mode, this helper is used to | |
1109 | * stuff CR3, e.g. for RSM emulation, and there is no guarantee that | |
1110 | * the current vCPU mode is accurate. | |
1111 | */ | |
1112 | if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) | |
d1cd3ce9 | 1113 | return 1; |
886bbcc7 SC |
1114 | |
1115 | if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 1116 | return 1; |
a03490ed | 1117 | |
be01e8e2 | 1118 | kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush); |
0f12244f | 1119 | vcpu->arch.cr3 = cr3; |
cb3c1e2f | 1120 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
7c390d35 | 1121 | |
0f12244f GN |
1122 | return 0; |
1123 | } | |
2d3ad1f4 | 1124 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1125 | |
eea1cff9 | 1126 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1127 | { |
0f12244f GN |
1128 | if (cr8 & CR8_RESERVED_BITS) |
1129 | return 1; | |
35754c98 | 1130 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1131 | kvm_lapic_set_tpr(vcpu, cr8); |
1132 | else | |
ad312c7c | 1133 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1134 | return 0; |
1135 | } | |
2d3ad1f4 | 1136 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1137 | |
2d3ad1f4 | 1138 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1139 | { |
35754c98 | 1140 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1141 | return kvm_lapic_get_cr8(vcpu); |
1142 | else | |
ad312c7c | 1143 | return vcpu->arch.cr8; |
a03490ed | 1144 | } |
2d3ad1f4 | 1145 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1146 | |
ae561ede NA |
1147 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1148 | { | |
1149 | int i; | |
1150 | ||
1151 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1152 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1153 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
1154 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
1155 | } | |
1156 | } | |
1157 | ||
7c86663b | 1158 | void kvm_update_dr7(struct kvm_vcpu *vcpu) |
c8639010 JK |
1159 | { |
1160 | unsigned long dr7; | |
1161 | ||
1162 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1163 | dr7 = vcpu->arch.guest_debug_dr7; | |
1164 | else | |
1165 | dr7 = vcpu->arch.dr7; | |
b3646477 | 1166 | static_call(kvm_x86_set_dr7)(vcpu, dr7); |
360b948d PB |
1167 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1168 | if (dr7 & DR7_BP_EN_MASK) | |
1169 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 | 1170 | } |
7c86663b | 1171 | EXPORT_SYMBOL_GPL(kvm_update_dr7); |
c8639010 | 1172 | |
6f43ed01 NA |
1173 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1174 | { | |
1175 | u64 fixed = DR6_FIXED_1; | |
1176 | ||
d6321d49 | 1177 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 | 1178 | fixed |= DR6_RTM; |
e8ea85fb CQ |
1179 | |
1180 | if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) | |
1181 | fixed |= DR6_BUS_LOCK; | |
6f43ed01 NA |
1182 | return fixed; |
1183 | } | |
1184 | ||
996ff542 | 1185 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1186 | { |
ea740059 MP |
1187 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1188 | ||
020df079 GN |
1189 | switch (dr) { |
1190 | case 0 ... 3: | |
ea740059 | 1191 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1192 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1193 | vcpu->arch.eff_db[dr] = val; | |
1194 | break; | |
1195 | case 4: | |
020df079 | 1196 | case 6: |
f5f6145e | 1197 | if (!kvm_dr6_valid(val)) |
996ff542 | 1198 | return 1; /* #GP */ |
6f43ed01 | 1199 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
020df079 GN |
1200 | break; |
1201 | case 5: | |
020df079 | 1202 | default: /* 7 */ |
b91991bf | 1203 | if (!kvm_dr7_valid(val)) |
996ff542 | 1204 | return 1; /* #GP */ |
020df079 | 1205 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1206 | kvm_update_dr7(vcpu); |
020df079 GN |
1207 | break; |
1208 | } | |
1209 | ||
1210 | return 0; | |
1211 | } | |
1212 | EXPORT_SYMBOL_GPL(kvm_set_dr); | |
1213 | ||
29d6ca41 | 1214 | void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1215 | { |
ea740059 MP |
1216 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1217 | ||
020df079 GN |
1218 | switch (dr) { |
1219 | case 0 ... 3: | |
ea740059 | 1220 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1221 | break; |
1222 | case 4: | |
020df079 | 1223 | case 6: |
5679b803 | 1224 | *val = vcpu->arch.dr6; |
020df079 GN |
1225 | break; |
1226 | case 5: | |
020df079 GN |
1227 | default: /* 7 */ |
1228 | *val = vcpu->arch.dr7; | |
1229 | break; | |
1230 | } | |
338dbc97 | 1231 | } |
020df079 GN |
1232 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1233 | ||
c483c454 | 1234 | int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) |
022cd0e8 | 1235 | { |
de3cd117 | 1236 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 | 1237 | u64 data; |
022cd0e8 | 1238 | |
c483c454 SC |
1239 | if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { |
1240 | kvm_inject_gp(vcpu, 0); | |
1241 | return 1; | |
1242 | } | |
1243 | ||
de3cd117 SC |
1244 | kvm_rax_write(vcpu, (u32)data); |
1245 | kvm_rdx_write(vcpu, data >> 32); | |
c483c454 | 1246 | return kvm_skip_emulated_instruction(vcpu); |
022cd0e8 | 1247 | } |
c483c454 | 1248 | EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); |
022cd0e8 | 1249 | |
043405e1 CO |
1250 | /* |
1251 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1252 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1253 | * | |
7a5ee6ed CQ |
1254 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) |
1255 | * extract the supported MSRs from the related const lists. | |
1256 | * msrs_to_save is selected from the msrs_to_save_all to reflect the | |
e3267cbb | 1257 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
7a5ee6ed | 1258 | * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs |
62ef68bb | 1259 | * may depend on host virtualization features rather than host cpu features. |
043405e1 | 1260 | */ |
e3267cbb | 1261 | |
7a5ee6ed | 1262 | static const u32 msrs_to_save_all[] = { |
043405e1 | 1263 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1264 | MSR_STAR, |
043405e1 CO |
1265 | #ifdef CONFIG_X86_64 |
1266 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1267 | #endif | |
b3897a49 | 1268 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1269 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1270 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1271 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1272 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1273 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1274 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1275 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1276 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1277 | MSR_IA32_UMWAIT_CONTROL, |
1278 | ||
e2ada66e JM |
1279 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
1280 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, | |
1281 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, | |
1282 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1283 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, | |
1284 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1285 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1286 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
1287 | MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, | |
1288 | MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, | |
1289 | MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, | |
1290 | MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, | |
1291 | MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, | |
e2ada66e JM |
1292 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1293 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1294 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1295 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
1296 | MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, | |
1297 | MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, | |
1298 | MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, | |
1299 | MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, | |
1300 | MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, | |
043405e1 CO |
1301 | }; |
1302 | ||
7a5ee6ed | 1303 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; |
043405e1 CO |
1304 | static unsigned num_msrs_to_save; |
1305 | ||
7a5ee6ed | 1306 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1307 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1308 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1309 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1310 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1311 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1312 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1313 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1314 | HV_X64_MSR_RESET, |
11c4b1ca | 1315 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1316 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1317 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1318 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1319 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1320 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1321 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
f97f5a56 JD |
1322 | HV_X64_MSR_SYNDBG_OPTIONS, |
1323 | HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, | |
1324 | HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, | |
1325 | HV_X64_MSR_SYNDBG_PENDING_BUFFER, | |
a2e164e7 VK |
1326 | |
1327 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
557a961a | 1328 | MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, |
62ef68bb | 1329 | |
ba904635 | 1330 | MSR_IA32_TSC_ADJUST, |
09141ec0 | 1331 | MSR_IA32_TSC_DEADLINE, |
2bdb76c0 | 1332 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1333 | MSR_IA32_PERF_CAPABILITIES, |
043405e1 | 1334 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1335 | MSR_IA32_MCG_STATUS, |
1336 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1337 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1338 | MSR_IA32_SMBASE, |
52797bf9 | 1339 | MSR_SMI_COUNT, |
db2336a8 KH |
1340 | MSR_PLATFORM_INFO, |
1341 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1342 | MSR_AMD64_VIRT_SPEC_CTRL, |
6c6a2ab9 | 1343 | MSR_IA32_POWER_CTL, |
99634e3e | 1344 | MSR_IA32_UCODE_REV, |
191c8137 | 1345 | |
95c5c7c7 PB |
1346 | /* |
1347 | * The following list leaves out MSRs whose values are determined | |
1348 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1349 | * We always support the "true" VMX control MSRs, even if the host | |
1350 | * processor does not, so I am putting these registers here rather | |
7a5ee6ed | 1351 | * than in msrs_to_save_all. |
95c5c7c7 PB |
1352 | */ |
1353 | MSR_IA32_VMX_BASIC, | |
1354 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1355 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1356 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1357 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1358 | MSR_IA32_VMX_MISC, | |
1359 | MSR_IA32_VMX_CR0_FIXED0, | |
1360 | MSR_IA32_VMX_CR4_FIXED0, | |
1361 | MSR_IA32_VMX_VMCS_ENUM, | |
1362 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1363 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1364 | MSR_IA32_VMX_VMFUNC, | |
1365 | ||
191c8137 | 1366 | MSR_K7_HWCR, |
2d5ba19b | 1367 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1368 | }; |
1369 | ||
7a5ee6ed | 1370 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1371 | static unsigned num_emulated_msrs; |
1372 | ||
801e459a TL |
1373 | /* |
1374 | * List of msr numbers which are used to expose MSR-based features that | |
1375 | * can be used by a hypervisor to validate requested CPU features. | |
1376 | */ | |
7a5ee6ed | 1377 | static const u32 msr_based_features_all[] = { |
1389309c PB |
1378 | MSR_IA32_VMX_BASIC, |
1379 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1380 | MSR_IA32_VMX_PINBASED_CTLS, | |
1381 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1382 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1383 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1384 | MSR_IA32_VMX_EXIT_CTLS, | |
1385 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1386 | MSR_IA32_VMX_ENTRY_CTLS, | |
1387 | MSR_IA32_VMX_MISC, | |
1388 | MSR_IA32_VMX_CR0_FIXED0, | |
1389 | MSR_IA32_VMX_CR0_FIXED1, | |
1390 | MSR_IA32_VMX_CR4_FIXED0, | |
1391 | MSR_IA32_VMX_CR4_FIXED1, | |
1392 | MSR_IA32_VMX_VMCS_ENUM, | |
1393 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1394 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1395 | MSR_IA32_VMX_VMFUNC, | |
1396 | ||
d1d93fa9 | 1397 | MSR_F10H_DECFG, |
518e7b94 | 1398 | MSR_IA32_UCODE_REV, |
cd283252 | 1399 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1400 | MSR_IA32_PERF_CAPABILITIES, |
801e459a TL |
1401 | }; |
1402 | ||
7a5ee6ed | 1403 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; |
801e459a TL |
1404 | static unsigned int num_msr_based_features; |
1405 | ||
4d22c17c | 1406 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1407 | { |
4d22c17c | 1408 | u64 data = 0; |
5b76a3cf | 1409 | |
4d22c17c XL |
1410 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1411 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf | 1412 | |
b8e8c830 PB |
1413 | /* |
1414 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1415 | * the nested hypervisor runs with NX huge pages. If it is not, | |
d9f6e12f | 1416 | * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other |
b8e8c830 PB |
1417 | * L1 guests, so it need not worry about its own (L2) guests. |
1418 | */ | |
1419 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1420 | ||
5b76a3cf PB |
1421 | /* |
1422 | * If we're doing cache flushes (either "always" or "cond") | |
1423 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1424 | * If an outer hypervisor is doing the cache flush for us | |
1425 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1426 | * capability to the guest too, and if EPT is disabled we're not | |
1427 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1428 | * require a nested hypervisor to do a flush of its own. | |
1429 | */ | |
1430 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1431 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1432 | ||
0c54914d PB |
1433 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1434 | data |= ARCH_CAP_RDCL_NO; | |
1435 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1436 | data |= ARCH_CAP_SSB_NO; | |
1437 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1438 | data |= ARCH_CAP_MDS_NO; | |
1439 | ||
7131636e PB |
1440 | if (!boot_cpu_has(X86_FEATURE_RTM)) { |
1441 | /* | |
1442 | * If RTM=0 because the kernel has disabled TSX, the host might | |
1443 | * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 | |
1444 | * and therefore knows that there cannot be TAA) but keep | |
1445 | * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, | |
1446 | * and we want to allow migrating those guests to tsx=off hosts. | |
1447 | */ | |
1448 | data &= ~ARCH_CAP_TAA_NO; | |
1449 | } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { | |
cbbaa272 | 1450 | data |= ARCH_CAP_TAA_NO; |
7131636e PB |
1451 | } else { |
1452 | /* | |
1453 | * Nothing to do here; we emulate TSX_CTRL if present on the | |
1454 | * host so the guest can choose between disabling TSX or | |
1455 | * using VERW to clear CPU buffers. | |
1456 | */ | |
1457 | } | |
e1d38b63 | 1458 | |
5b76a3cf PB |
1459 | return data; |
1460 | } | |
5b76a3cf | 1461 | |
66421c1e WL |
1462 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1463 | { | |
1464 | switch (msr->index) { | |
cd283252 | 1465 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1466 | msr->data = kvm_get_arch_capabilities(); |
1467 | break; | |
1468 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1469 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1470 | break; |
66421c1e | 1471 | default: |
b3646477 | 1472 | return static_call(kvm_x86_get_msr_feature)(msr); |
66421c1e WL |
1473 | } |
1474 | return 0; | |
1475 | } | |
1476 | ||
801e459a TL |
1477 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1478 | { | |
1479 | struct kvm_msr_entry msr; | |
66421c1e | 1480 | int r; |
801e459a TL |
1481 | |
1482 | msr.index = index; | |
66421c1e | 1483 | r = kvm_get_msr_feature(&msr); |
12bc2132 PX |
1484 | |
1485 | if (r == KVM_MSR_RET_INVALID) { | |
1486 | /* Unconditionally clear the output for simplicity */ | |
1487 | *data = 0; | |
d632826f | 1488 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1489 | r = 0; |
12bc2132 PX |
1490 | } |
1491 | ||
66421c1e WL |
1492 | if (r) |
1493 | return r; | |
801e459a TL |
1494 | |
1495 | *data = msr.data; | |
1496 | ||
1497 | return 0; | |
1498 | } | |
1499 | ||
11988499 | 1500 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1501 | { |
1b4d56b8 | 1502 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1503 | return false; |
1b2fd70c | 1504 | |
1b4d56b8 | 1505 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1506 | return false; |
d8017474 | 1507 | |
0a629563 SC |
1508 | if (efer & (EFER_LME | EFER_LMA) && |
1509 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1510 | return false; | |
1511 | ||
1512 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1513 | return false; | |
d8017474 | 1514 | |
384bb783 | 1515 | return true; |
11988499 SC |
1516 | |
1517 | } | |
1518 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1519 | { | |
1520 | if (efer & efer_reserved_bits) | |
1521 | return false; | |
1522 | ||
1523 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1524 | } |
1525 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1526 | ||
11988499 | 1527 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1528 | { |
1529 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1530 | u64 efer = msr_info->data; |
72f211ec | 1531 | int r; |
384bb783 | 1532 | |
11988499 | 1533 | if (efer & efer_reserved_bits) |
66f61c92 | 1534 | return 1; |
384bb783 | 1535 | |
11988499 SC |
1536 | if (!msr_info->host_initiated) { |
1537 | if (!__kvm_valid_efer(vcpu, efer)) | |
1538 | return 1; | |
1539 | ||
1540 | if (is_paging(vcpu) && | |
1541 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1542 | return 1; | |
1543 | } | |
384bb783 | 1544 | |
15c4a640 | 1545 | efer &= ~EFER_LMA; |
f6801dff | 1546 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1547 | |
b3646477 | 1548 | r = static_call(kvm_x86_set_efer)(vcpu, efer); |
72f211ec ML |
1549 | if (r) { |
1550 | WARN_ON(r > 0); | |
1551 | return r; | |
1552 | } | |
a3d204e2 | 1553 | |
aad82703 SY |
1554 | /* Update reserved bits */ |
1555 | if ((efer ^ old_efer) & EFER_NX) | |
1556 | kvm_mmu_reset_context(vcpu); | |
1557 | ||
b69e8cae | 1558 | return 0; |
15c4a640 CO |
1559 | } |
1560 | ||
f2b4b7dd JR |
1561 | void kvm_enable_efer_bits(u64 mask) |
1562 | { | |
1563 | efer_reserved_bits &= ~mask; | |
1564 | } | |
1565 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1566 | ||
51de8151 AG |
1567 | bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) |
1568 | { | |
b318e8de SC |
1569 | struct kvm_x86_msr_filter *msr_filter; |
1570 | struct msr_bitmap_range *ranges; | |
1a155254 | 1571 | struct kvm *kvm = vcpu->kvm; |
b318e8de | 1572 | bool allowed; |
1a155254 | 1573 | int idx; |
b318e8de | 1574 | u32 i; |
1a155254 | 1575 | |
b318e8de SC |
1576 | /* x2APIC MSRs do not support filtering. */ |
1577 | if (index >= 0x800 && index <= 0x8ff) | |
1a155254 AG |
1578 | return true; |
1579 | ||
1a155254 AG |
1580 | idx = srcu_read_lock(&kvm->srcu); |
1581 | ||
b318e8de SC |
1582 | msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); |
1583 | if (!msr_filter) { | |
1584 | allowed = true; | |
1585 | goto out; | |
1586 | } | |
1587 | ||
1588 | allowed = msr_filter->default_allow; | |
1589 | ranges = msr_filter->ranges; | |
1590 | ||
1591 | for (i = 0; i < msr_filter->count; i++) { | |
1a155254 AG |
1592 | u32 start = ranges[i].base; |
1593 | u32 end = start + ranges[i].nmsrs; | |
1594 | u32 flags = ranges[i].flags; | |
1595 | unsigned long *bitmap = ranges[i].bitmap; | |
1596 | ||
1597 | if ((index >= start) && (index < end) && (flags & type)) { | |
b318e8de | 1598 | allowed = !!test_bit(index - start, bitmap); |
1a155254 AG |
1599 | break; |
1600 | } | |
1601 | } | |
1602 | ||
b318e8de | 1603 | out: |
1a155254 AG |
1604 | srcu_read_unlock(&kvm->srcu, idx); |
1605 | ||
b318e8de | 1606 | return allowed; |
51de8151 AG |
1607 | } |
1608 | EXPORT_SYMBOL_GPL(kvm_msr_allowed); | |
1609 | ||
15c4a640 | 1610 | /* |
f20935d8 SC |
1611 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1612 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1613 | * Returns 0 on success, non-0 otherwise. |
1614 | * Assumes vcpu_load() was already called. | |
1615 | */ | |
f20935d8 SC |
1616 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1617 | bool host_initiated) | |
15c4a640 | 1618 | { |
f20935d8 SC |
1619 | struct msr_data msr; |
1620 | ||
1a155254 | 1621 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) |
cc4cb017 | 1622 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1623 | |
f20935d8 | 1624 | switch (index) { |
854e8bb1 NA |
1625 | case MSR_FS_BASE: |
1626 | case MSR_GS_BASE: | |
1627 | case MSR_KERNEL_GS_BASE: | |
1628 | case MSR_CSTAR: | |
1629 | case MSR_LSTAR: | |
f20935d8 | 1630 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1631 | return 1; |
1632 | break; | |
1633 | case MSR_IA32_SYSENTER_EIP: | |
1634 | case MSR_IA32_SYSENTER_ESP: | |
1635 | /* | |
1636 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1637 | * non-canonical address is written on Intel but not on | |
1638 | * AMD (which ignores the top 32-bits, because it does | |
1639 | * not implement 64-bit SYSENTER). | |
1640 | * | |
1641 | * 64-bit code should hence be able to write a non-canonical | |
1642 | * value on AMD. Making the address canonical ensures that | |
1643 | * vmentry does not fail on Intel after writing a non-canonical | |
1644 | * value, and that something deterministic happens if the guest | |
1645 | * invokes 64-bit SYSENTER. | |
1646 | */ | |
f20935d8 | 1647 | data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); |
61a05d44 SC |
1648 | break; |
1649 | case MSR_TSC_AUX: | |
1650 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1651 | return 1; | |
1652 | ||
1653 | if (!host_initiated && | |
1654 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1655 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1656 | return 1; | |
1657 | ||
1658 | /* | |
1659 | * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has | |
1660 | * incomplete and conflicting architectural behavior. Current | |
1661 | * AMD CPUs completely ignore bits 63:32, i.e. they aren't | |
1662 | * reserved and always read as zeros. Enforce Intel's reserved | |
1663 | * bits check if and only if the guest CPU is Intel, and clear | |
1664 | * the bits in all other cases. This ensures cross-vendor | |
1665 | * migration will provide consistent behavior for the guest. | |
1666 | */ | |
1667 | if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) | |
1668 | return 1; | |
1669 | ||
1670 | data = (u32)data; | |
1671 | break; | |
854e8bb1 | 1672 | } |
f20935d8 SC |
1673 | |
1674 | msr.data = data; | |
1675 | msr.index = index; | |
1676 | msr.host_initiated = host_initiated; | |
1677 | ||
b3646477 | 1678 | return static_call(kvm_x86_set_msr)(vcpu, &msr); |
15c4a640 CO |
1679 | } |
1680 | ||
6abe9c13 PX |
1681 | static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, |
1682 | u32 index, u64 data, bool host_initiated) | |
1683 | { | |
1684 | int ret = __kvm_set_msr(vcpu, index, data, host_initiated); | |
1685 | ||
1686 | if (ret == KVM_MSR_RET_INVALID) | |
d632826f | 1687 | if (kvm_msr_ignored_check(index, data, true)) |
cc4cb017 | 1688 | ret = 0; |
6abe9c13 PX |
1689 | |
1690 | return ret; | |
1691 | } | |
1692 | ||
313a3dc7 | 1693 | /* |
f20935d8 SC |
1694 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1695 | * checks are bypassed if @host_initiated is %true. | |
1696 | * Returns 0 on success, non-0 otherwise. | |
1697 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1698 | */ |
edef5c36 PB |
1699 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1700 | bool host_initiated) | |
609e36d3 PB |
1701 | { |
1702 | struct msr_data msr; | |
f20935d8 | 1703 | int ret; |
609e36d3 | 1704 | |
1a155254 | 1705 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) |
cc4cb017 | 1706 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1707 | |
61a05d44 SC |
1708 | switch (index) { |
1709 | case MSR_TSC_AUX: | |
1710 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1711 | return 1; | |
1712 | ||
1713 | if (!host_initiated && | |
1714 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1715 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1716 | return 1; | |
1717 | break; | |
1718 | } | |
1719 | ||
609e36d3 | 1720 | msr.index = index; |
f20935d8 | 1721 | msr.host_initiated = host_initiated; |
609e36d3 | 1722 | |
b3646477 | 1723 | ret = static_call(kvm_x86_get_msr)(vcpu, &msr); |
f20935d8 SC |
1724 | if (!ret) |
1725 | *data = msr.data; | |
1726 | return ret; | |
609e36d3 PB |
1727 | } |
1728 | ||
6abe9c13 PX |
1729 | static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, |
1730 | u32 index, u64 *data, bool host_initiated) | |
1731 | { | |
1732 | int ret = __kvm_get_msr(vcpu, index, data, host_initiated); | |
1733 | ||
1734 | if (ret == KVM_MSR_RET_INVALID) { | |
1735 | /* Unconditionally clear *data for simplicity */ | |
1736 | *data = 0; | |
d632826f | 1737 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1738 | ret = 0; |
6abe9c13 PX |
1739 | } |
1740 | ||
1741 | return ret; | |
1742 | } | |
1743 | ||
f20935d8 | 1744 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1745 | { |
6abe9c13 | 1746 | return kvm_get_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1747 | } |
1748 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1749 | |
f20935d8 SC |
1750 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1751 | { | |
6abe9c13 | 1752 | return kvm_set_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1753 | } |
1754 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1755 | ||
8b474427 | 1756 | static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) |
1ae09954 | 1757 | { |
8b474427 PB |
1758 | int err = vcpu->run->msr.error; |
1759 | if (!err) { | |
1ae09954 AG |
1760 | kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); |
1761 | kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); | |
1762 | } | |
1763 | ||
b3646477 | 1764 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, err); |
1ae09954 AG |
1765 | } |
1766 | ||
1767 | static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) | |
1768 | { | |
b3646477 | 1769 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); |
1ae09954 AG |
1770 | } |
1771 | ||
1772 | static u64 kvm_msr_reason(int r) | |
1773 | { | |
1774 | switch (r) { | |
cc4cb017 | 1775 | case KVM_MSR_RET_INVALID: |
1ae09954 | 1776 | return KVM_MSR_EXIT_REASON_UNKNOWN; |
cc4cb017 | 1777 | case KVM_MSR_RET_FILTERED: |
1a155254 | 1778 | return KVM_MSR_EXIT_REASON_FILTER; |
1ae09954 AG |
1779 | default: |
1780 | return KVM_MSR_EXIT_REASON_INVAL; | |
1781 | } | |
1782 | } | |
1783 | ||
1784 | static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, | |
1785 | u32 exit_reason, u64 data, | |
1786 | int (*completion)(struct kvm_vcpu *vcpu), | |
1787 | int r) | |
1788 | { | |
1789 | u64 msr_reason = kvm_msr_reason(r); | |
1790 | ||
1791 | /* Check if the user wanted to know about this MSR fault */ | |
1792 | if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) | |
1793 | return 0; | |
1794 | ||
1795 | vcpu->run->exit_reason = exit_reason; | |
1796 | vcpu->run->msr.error = 0; | |
1797 | memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); | |
1798 | vcpu->run->msr.reason = msr_reason; | |
1799 | vcpu->run->msr.index = index; | |
1800 | vcpu->run->msr.data = data; | |
1801 | vcpu->arch.complete_userspace_io = completion; | |
1802 | ||
1803 | return 1; | |
1804 | } | |
1805 | ||
1806 | static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) | |
1807 | { | |
1808 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, | |
1809 | complete_emulated_rdmsr, r); | |
1810 | } | |
1811 | ||
1812 | static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) | |
1813 | { | |
1814 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, | |
1815 | complete_emulated_wrmsr, r); | |
1816 | } | |
1817 | ||
1edce0a9 SC |
1818 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
1819 | { | |
1820 | u32 ecx = kvm_rcx_read(vcpu); | |
1821 | u64 data; | |
1ae09954 AG |
1822 | int r; |
1823 | ||
1824 | r = kvm_get_msr(vcpu, ecx, &data); | |
1edce0a9 | 1825 | |
1ae09954 AG |
1826 | /* MSR read failed? See if we should ask user space */ |
1827 | if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { | |
1828 | /* Bounce to user space */ | |
1829 | return 0; | |
1830 | } | |
1831 | ||
8b474427 PB |
1832 | if (!r) { |
1833 | trace_kvm_msr_read(ecx, data); | |
1834 | ||
1835 | kvm_rax_write(vcpu, data & -1u); | |
1836 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
1837 | } else { | |
1edce0a9 | 1838 | trace_kvm_msr_read_ex(ecx); |
1edce0a9 SC |
1839 | } |
1840 | ||
b3646477 | 1841 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
1842 | } |
1843 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
1844 | ||
1845 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
1846 | { | |
1847 | u32 ecx = kvm_rcx_read(vcpu); | |
1848 | u64 data = kvm_read_edx_eax(vcpu); | |
1ae09954 | 1849 | int r; |
1edce0a9 | 1850 | |
1ae09954 AG |
1851 | r = kvm_set_msr(vcpu, ecx, data); |
1852 | ||
1853 | /* MSR write failed? See if we should ask user space */ | |
7dffecaf | 1854 | if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) |
1ae09954 AG |
1855 | /* Bounce to user space */ |
1856 | return 0; | |
7dffecaf ML |
1857 | |
1858 | /* Signal all other negative errors to userspace */ | |
1859 | if (r < 0) | |
1860 | return r; | |
1ae09954 | 1861 | |
8b474427 PB |
1862 | if (!r) |
1863 | trace_kvm_msr_write(ecx, data); | |
1864 | else | |
1edce0a9 | 1865 | trace_kvm_msr_write_ex(ecx, data); |
1edce0a9 | 1866 | |
b3646477 | 1867 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
1868 | } |
1869 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
1870 | ||
5ff3a351 SC |
1871 | int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) |
1872 | { | |
1873 | return kvm_skip_emulated_instruction(vcpu); | |
1874 | } | |
1875 | EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); | |
1876 | ||
1877 | int kvm_emulate_invd(struct kvm_vcpu *vcpu) | |
1878 | { | |
1879 | /* Treat an INVD instruction as a NOP and just skip it. */ | |
1880 | return kvm_emulate_as_nop(vcpu); | |
1881 | } | |
1882 | EXPORT_SYMBOL_GPL(kvm_emulate_invd); | |
1883 | ||
1884 | int kvm_emulate_mwait(struct kvm_vcpu *vcpu) | |
1885 | { | |
1886 | pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); | |
1887 | return kvm_emulate_as_nop(vcpu); | |
1888 | } | |
1889 | EXPORT_SYMBOL_GPL(kvm_emulate_mwait); | |
1890 | ||
1891 | int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) | |
1892 | { | |
1893 | kvm_queue_exception(vcpu, UD_VECTOR); | |
1894 | return 1; | |
1895 | } | |
1896 | EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); | |
1897 | ||
1898 | int kvm_emulate_monitor(struct kvm_vcpu *vcpu) | |
1899 | { | |
1900 | pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); | |
1901 | return kvm_emulate_as_nop(vcpu); | |
1902 | } | |
1903 | EXPORT_SYMBOL_GPL(kvm_emulate_monitor); | |
1904 | ||
d89d04ab | 1905 | static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) |
5a9f5443 | 1906 | { |
4ae7dc97 | 1907 | xfer_to_guest_mode_prepare(); |
5a9f5443 | 1908 | return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || |
72c3c0fe | 1909 | xfer_to_guest_mode_work_pending(); |
5a9f5443 | 1910 | } |
5a9f5443 | 1911 | |
1e9e2622 WL |
1912 | /* |
1913 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
1914 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
1915 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
1916 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
1917 | * other cases which must be called after interrupts are enabled on the host. | |
1918 | */ | |
1919 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
1920 | { | |
e1be9ac8 WL |
1921 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) |
1922 | return 1; | |
1923 | ||
1924 | if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && | |
1e9e2622 | 1925 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && |
4064a4c6 WL |
1926 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && |
1927 | ((u32)(data >> 32) != X2APIC_BROADCAST)) { | |
1e9e2622 | 1928 | |
d5361678 WL |
1929 | data &= ~(1 << 12); |
1930 | kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); | |
1e9e2622 | 1931 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); |
d5361678 WL |
1932 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); |
1933 | trace_kvm_apic_write(APIC_ICR, (u32)data); | |
1934 | return 0; | |
1e9e2622 WL |
1935 | } |
1936 | ||
1937 | return 1; | |
1938 | } | |
1939 | ||
ae95f566 WL |
1940 | static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) |
1941 | { | |
1942 | if (!kvm_can_use_hv_timer(vcpu)) | |
1943 | return 1; | |
1944 | ||
1945 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
1946 | return 0; | |
1947 | } | |
1948 | ||
404d5d7b | 1949 | fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) |
1e9e2622 WL |
1950 | { |
1951 | u32 msr = kvm_rcx_read(vcpu); | |
8a1038de | 1952 | u64 data; |
404d5d7b | 1953 | fastpath_t ret = EXIT_FASTPATH_NONE; |
1e9e2622 WL |
1954 | |
1955 | switch (msr) { | |
1956 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
8a1038de | 1957 | data = kvm_read_edx_eax(vcpu); |
404d5d7b WL |
1958 | if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { |
1959 | kvm_skip_emulated_instruction(vcpu); | |
1960 | ret = EXIT_FASTPATH_EXIT_HANDLED; | |
80bc97f2 | 1961 | } |
1e9e2622 | 1962 | break; |
09141ec0 | 1963 | case MSR_IA32_TSC_DEADLINE: |
ae95f566 WL |
1964 | data = kvm_read_edx_eax(vcpu); |
1965 | if (!handle_fastpath_set_tscdeadline(vcpu, data)) { | |
1966 | kvm_skip_emulated_instruction(vcpu); | |
1967 | ret = EXIT_FASTPATH_REENTER_GUEST; | |
1968 | } | |
1969 | break; | |
1e9e2622 | 1970 | default: |
404d5d7b | 1971 | break; |
1e9e2622 WL |
1972 | } |
1973 | ||
404d5d7b | 1974 | if (ret != EXIT_FASTPATH_NONE) |
1e9e2622 | 1975 | trace_kvm_msr_write(msr, data); |
1e9e2622 | 1976 | |
404d5d7b | 1977 | return ret; |
1e9e2622 WL |
1978 | } |
1979 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
1980 | ||
f20935d8 SC |
1981 | /* |
1982 | * Adapt set_msr() to msr_io()'s calling convention | |
1983 | */ | |
1984 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1985 | { | |
6abe9c13 | 1986 | return kvm_get_msr_ignored_check(vcpu, index, data, true); |
f20935d8 SC |
1987 | } |
1988 | ||
1989 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1990 | { | |
6abe9c13 | 1991 | return kvm_set_msr_ignored_check(vcpu, index, *data, true); |
313a3dc7 CO |
1992 | } |
1993 | ||
16e8d74d | 1994 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
1995 | struct pvclock_clock { |
1996 | int vclock_mode; | |
1997 | u64 cycle_last; | |
1998 | u64 mask; | |
1999 | u32 mult; | |
2000 | u32 shift; | |
917f9475 PB |
2001 | u64 base_cycles; |
2002 | u64 offset; | |
53fafdbb MT |
2003 | }; |
2004 | ||
16e8d74d MT |
2005 | struct pvclock_gtod_data { |
2006 | seqcount_t seq; | |
2007 | ||
53fafdbb MT |
2008 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
2009 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 2010 | |
917f9475 | 2011 | ktime_t offs_boot; |
55dd00a7 | 2012 | u64 wall_time_sec; |
16e8d74d MT |
2013 | }; |
2014 | ||
2015 | static struct pvclock_gtod_data pvclock_gtod_data; | |
2016 | ||
2017 | static void update_pvclock_gtod(struct timekeeper *tk) | |
2018 | { | |
2019 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
2020 | ||
2021 | write_seqcount_begin(&vdata->seq); | |
2022 | ||
2023 | /* copy pvclock gtod data */ | |
b95a8a27 | 2024 | vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; |
876e7881 PZ |
2025 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; |
2026 | vdata->clock.mask = tk->tkr_mono.mask; | |
2027 | vdata->clock.mult = tk->tkr_mono.mult; | |
2028 | vdata->clock.shift = tk->tkr_mono.shift; | |
917f9475 PB |
2029 | vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; |
2030 | vdata->clock.offset = tk->tkr_mono.base; | |
16e8d74d | 2031 | |
b95a8a27 | 2032 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; |
53fafdbb MT |
2033 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; |
2034 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
2035 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
2036 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
917f9475 PB |
2037 | vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; |
2038 | vdata->raw_clock.offset = tk->tkr_raw.base; | |
16e8d74d | 2039 | |
55dd00a7 MT |
2040 | vdata->wall_time_sec = tk->xtime_sec; |
2041 | ||
917f9475 | 2042 | vdata->offs_boot = tk->offs_boot; |
53fafdbb | 2043 | |
16e8d74d MT |
2044 | write_seqcount_end(&vdata->seq); |
2045 | } | |
8171cd68 PB |
2046 | |
2047 | static s64 get_kvmclock_base_ns(void) | |
2048 | { | |
2049 | /* Count up from boot time, but with the frequency of the raw clock. */ | |
2050 | return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); | |
2051 | } | |
2052 | #else | |
2053 | static s64 get_kvmclock_base_ns(void) | |
2054 | { | |
2055 | /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ | |
2056 | return ktime_get_boottime_ns(); | |
2057 | } | |
16e8d74d MT |
2058 | #endif |
2059 | ||
629b5348 | 2060 | void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) |
18068523 | 2061 | { |
9ed3c444 AK |
2062 | int version; |
2063 | int r; | |
50d0a0f9 | 2064 | struct pvclock_wall_clock wc; |
629b5348 | 2065 | u32 wc_sec_hi; |
8171cd68 | 2066 | u64 wall_nsec; |
18068523 GOC |
2067 | |
2068 | if (!wall_clock) | |
2069 | return; | |
2070 | ||
9ed3c444 AK |
2071 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
2072 | if (r) | |
2073 | return; | |
2074 | ||
2075 | if (version & 1) | |
2076 | ++version; /* first time write, random junk */ | |
2077 | ||
2078 | ++version; | |
18068523 | 2079 | |
1dab1345 NK |
2080 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
2081 | return; | |
18068523 | 2082 | |
50d0a0f9 GH |
2083 | /* |
2084 | * The guest calculates current wall clock time by adding | |
34c238a1 | 2085 | * system time (updated by kvm_guest_time_update below) to the |
8171cd68 | 2086 | * wall clock specified here. We do the reverse here. |
50d0a0f9 | 2087 | */ |
8171cd68 | 2088 | wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); |
50d0a0f9 | 2089 | |
8171cd68 PB |
2090 | wc.nsec = do_div(wall_nsec, 1000000000); |
2091 | wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ | |
50d0a0f9 | 2092 | wc.version = version; |
18068523 GOC |
2093 | |
2094 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
2095 | ||
629b5348 JM |
2096 | if (sec_hi_ofs) { |
2097 | wc_sec_hi = wall_nsec >> 32; | |
2098 | kvm_write_guest(kvm, wall_clock + sec_hi_ofs, | |
2099 | &wc_sec_hi, sizeof(wc_sec_hi)); | |
2100 | } | |
2101 | ||
18068523 GOC |
2102 | version++; |
2103 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
2104 | } |
2105 | ||
5b9bb0eb OU |
2106 | static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, |
2107 | bool old_msr, bool host_initiated) | |
2108 | { | |
2109 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
2110 | ||
2111 | if (vcpu->vcpu_id == 0 && !host_initiated) { | |
1e293d1a | 2112 | if (ka->boot_vcpu_runs_old_kvmclock != old_msr) |
5b9bb0eb OU |
2113 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2114 | ||
2115 | ka->boot_vcpu_runs_old_kvmclock = old_msr; | |
2116 | } | |
2117 | ||
2118 | vcpu->arch.time = system_time; | |
2119 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
2120 | ||
2121 | /* we verify if the enable bit is set... */ | |
2122 | vcpu->arch.pv_time_enabled = false; | |
2123 | if (!(system_time & 1)) | |
2124 | return; | |
2125 | ||
2126 | if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
2127 | &vcpu->arch.pv_time, system_time & ~1ULL, | |
2128 | sizeof(struct pvclock_vcpu_time_info))) | |
2129 | vcpu->arch.pv_time_enabled = true; | |
2130 | ||
2131 | return; | |
2132 | } | |
2133 | ||
50d0a0f9 GH |
2134 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
2135 | { | |
b51012de PB |
2136 | do_shl32_div32(dividend, divisor); |
2137 | return dividend; | |
50d0a0f9 GH |
2138 | } |
2139 | ||
3ae13faa | 2140 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 2141 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 2142 | { |
5f4e3f88 | 2143 | uint64_t scaled64; |
50d0a0f9 GH |
2144 | int32_t shift = 0; |
2145 | uint64_t tps64; | |
2146 | uint32_t tps32; | |
2147 | ||
3ae13faa PB |
2148 | tps64 = base_hz; |
2149 | scaled64 = scaled_hz; | |
50933623 | 2150 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
2151 | tps64 >>= 1; |
2152 | shift--; | |
2153 | } | |
2154 | ||
2155 | tps32 = (uint32_t)tps64; | |
50933623 JK |
2156 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
2157 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
2158 | scaled64 >>= 1; |
2159 | else | |
2160 | tps32 <<= 1; | |
50d0a0f9 GH |
2161 | shift++; |
2162 | } | |
2163 | ||
5f4e3f88 ZA |
2164 | *pshift = shift; |
2165 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
2166 | } |
2167 | ||
d828199e | 2168 | #ifdef CONFIG_X86_64 |
16e8d74d | 2169 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 2170 | #endif |
16e8d74d | 2171 | |
c8076604 | 2172 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 2173 | static unsigned long max_tsc_khz; |
c8076604 | 2174 | |
cc578287 | 2175 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 2176 | { |
cc578287 ZA |
2177 | u64 v = (u64)khz * (1000000 + ppm); |
2178 | do_div(v, 1000000); | |
2179 | return v; | |
1e993611 JR |
2180 | } |
2181 | ||
381d585c HZ |
2182 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
2183 | { | |
2184 | u64 ratio; | |
2185 | ||
2186 | /* Guest TSC same frequency as host TSC? */ | |
2187 | if (!scale) { | |
2188 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
2189 | return 0; | |
2190 | } | |
2191 | ||
2192 | /* TSC scaling supported? */ | |
2193 | if (!kvm_has_tsc_control) { | |
2194 | if (user_tsc_khz > tsc_khz) { | |
2195 | vcpu->arch.tsc_catchup = 1; | |
2196 | vcpu->arch.tsc_always_catchup = 1; | |
2197 | return 0; | |
2198 | } else { | |
3f16a5c3 | 2199 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
2200 | return -1; |
2201 | } | |
2202 | } | |
2203 | ||
2204 | /* TSC scaling required - calculate ratio */ | |
2205 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
2206 | user_tsc_khz, tsc_khz); | |
2207 | ||
2208 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
3f16a5c3 PB |
2209 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
2210 | user_tsc_khz); | |
381d585c HZ |
2211 | return -1; |
2212 | } | |
2213 | ||
2214 | vcpu->arch.tsc_scaling_ratio = ratio; | |
2215 | return 0; | |
2216 | } | |
2217 | ||
4941b8cb | 2218 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 2219 | { |
cc578287 ZA |
2220 | u32 thresh_lo, thresh_hi; |
2221 | int use_scaling = 0; | |
217fc9cf | 2222 | |
03ba32ca | 2223 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 2224 | if (user_tsc_khz == 0) { |
ad721883 HZ |
2225 | /* set tsc_scaling_ratio to a safe value */ |
2226 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
381d585c | 2227 | return -1; |
ad721883 | 2228 | } |
03ba32ca | 2229 | |
c285545f | 2230 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 2231 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
2232 | &vcpu->arch.virtual_tsc_shift, |
2233 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 2234 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
2235 | |
2236 | /* | |
2237 | * Compute the variation in TSC rate which is acceptable | |
2238 | * within the range of tolerance and decide if the | |
2239 | * rate being applied is within that bounds of the hardware | |
2240 | * rate. If so, no scaling or compensation need be done. | |
2241 | */ | |
2242 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
2243 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
2244 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
2245 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
2246 | use_scaling = 1; |
2247 | } | |
4941b8cb | 2248 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
2249 | } |
2250 | ||
2251 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
2252 | { | |
e26101b1 | 2253 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
2254 | vcpu->arch.virtual_tsc_mult, |
2255 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 2256 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
2257 | return tsc; |
2258 | } | |
2259 | ||
b0c39dc6 VK |
2260 | static inline int gtod_is_based_on_tsc(int mode) |
2261 | { | |
b95a8a27 | 2262 | return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; |
b0c39dc6 VK |
2263 | } |
2264 | ||
69b0049a | 2265 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
2266 | { |
2267 | #ifdef CONFIG_X86_64 | |
2268 | bool vcpus_matched; | |
b48aa97e MT |
2269 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2270 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2271 | ||
2272 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2273 | atomic_read(&vcpu->kvm->online_vcpus)); | |
2274 | ||
7f187922 MT |
2275 | /* |
2276 | * Once the masterclock is enabled, always perform request in | |
2277 | * order to update it. | |
2278 | * | |
2279 | * In order to enable masterclock, the host clocksource must be TSC | |
2280 | * and the vcpus need to have matched TSCs. When that happens, | |
2281 | * perform request to enable masterclock. | |
2282 | */ | |
2283 | if (ka->use_master_clock || | |
b0c39dc6 | 2284 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
2285 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2286 | ||
2287 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
2288 | atomic_read(&vcpu->kvm->online_vcpus), | |
2289 | ka->use_master_clock, gtod->clock.vclock_mode); | |
2290 | #endif | |
2291 | } | |
2292 | ||
35181e86 HZ |
2293 | /* |
2294 | * Multiply tsc by a fixed point number represented by ratio. | |
2295 | * | |
2296 | * The most significant 64-N bits (mult) of ratio represent the | |
2297 | * integral part of the fixed point number; the remaining N bits | |
2298 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
2299 | * point number (mult + frac * 2^(-N)). | |
2300 | * | |
2301 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
2302 | */ | |
2303 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
2304 | { | |
2305 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
2306 | } | |
2307 | ||
2308 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
2309 | { | |
2310 | u64 _tsc = tsc; | |
2311 | u64 ratio = vcpu->arch.tsc_scaling_ratio; | |
2312 | ||
2313 | if (ratio != kvm_default_tsc_scaling_ratio) | |
2314 | _tsc = __scale_tsc(ratio, tsc); | |
2315 | ||
2316 | return _tsc; | |
2317 | } | |
2318 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
2319 | ||
07c1419a HZ |
2320 | static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
2321 | { | |
2322 | u64 tsc; | |
2323 | ||
2324 | tsc = kvm_scale_tsc(vcpu, rdtsc()); | |
2325 | ||
2326 | return target_tsc - tsc; | |
2327 | } | |
2328 | ||
4ba76538 HZ |
2329 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
2330 | { | |
56ba77a4 | 2331 | return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc); |
4ba76538 HZ |
2332 | } |
2333 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
2334 | ||
a545ab6a LC |
2335 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
2336 | { | |
56ba77a4 | 2337 | vcpu->arch.l1_tsc_offset = offset; |
b3646477 | 2338 | vcpu->arch.tsc_offset = static_call(kvm_x86_write_l1_tsc_offset)(vcpu, offset); |
a545ab6a LC |
2339 | } |
2340 | ||
b0c39dc6 VK |
2341 | static inline bool kvm_check_tsc_unstable(void) |
2342 | { | |
2343 | #ifdef CONFIG_X86_64 | |
2344 | /* | |
2345 | * TSC is marked unstable when we're running on Hyper-V, | |
2346 | * 'TSC page' clocksource is good. | |
2347 | */ | |
b95a8a27 | 2348 | if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) |
b0c39dc6 VK |
2349 | return false; |
2350 | #endif | |
2351 | return check_tsc_unstable(); | |
2352 | } | |
2353 | ||
0c899c25 | 2354 | static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) |
99e3e30a ZA |
2355 | { |
2356 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 2357 | u64 offset, ns, elapsed; |
99e3e30a | 2358 | unsigned long flags; |
b48aa97e | 2359 | bool matched; |
0d3da0d2 | 2360 | bool already_matched; |
c5e8ec8e | 2361 | bool synchronizing = false; |
99e3e30a | 2362 | |
038f8c11 | 2363 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
07c1419a | 2364 | offset = kvm_compute_tsc_offset(vcpu, data); |
8171cd68 | 2365 | ns = get_kvmclock_base_ns(); |
f38e098f | 2366 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 2367 | |
03ba32ca | 2368 | if (vcpu->arch.virtual_tsc_khz) { |
0c899c25 | 2369 | if (data == 0) { |
bd8fab39 DP |
2370 | /* |
2371 | * detection of vcpu initialization -- need to sync | |
2372 | * with other vCPUs. This particularly helps to keep | |
2373 | * kvm_clock stable after CPU hotplug | |
2374 | */ | |
2375 | synchronizing = true; | |
2376 | } else { | |
2377 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
2378 | nsec_to_cycles(vcpu, elapsed); | |
2379 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
2380 | /* | |
2381 | * Special case: TSC write with a small delta (1 second) | |
2382 | * of virtual cycle time against real time is | |
2383 | * interpreted as an attempt to synchronize the CPU. | |
2384 | */ | |
2385 | synchronizing = data < tsc_exp + tsc_hz && | |
2386 | data + tsc_hz > tsc_exp; | |
2387 | } | |
c5e8ec8e | 2388 | } |
f38e098f ZA |
2389 | |
2390 | /* | |
5d3cb0f6 ZA |
2391 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
2392 | * TSC, we add elapsed time in this computation. We could let the | |
2393 | * compensation code attempt to catch up if we fall behind, but | |
2394 | * it's better to try to match offsets from the beginning. | |
2395 | */ | |
c5e8ec8e | 2396 | if (synchronizing && |
5d3cb0f6 | 2397 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 2398 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 2399 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 2400 | } else { |
857e4099 | 2401 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 2402 | data += delta; |
07c1419a | 2403 | offset = kvm_compute_tsc_offset(vcpu, data); |
f38e098f | 2404 | } |
b48aa97e | 2405 | matched = true; |
0d3da0d2 | 2406 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
2407 | } else { |
2408 | /* | |
2409 | * We split periods of matched TSC writes into generations. | |
2410 | * For each generation, we track the original measured | |
2411 | * nanosecond time, offset, and write, so if TSCs are in | |
2412 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 2413 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
2414 | * |
2415 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2416 | */ | |
2417 | kvm->arch.cur_tsc_generation++; | |
2418 | kvm->arch.cur_tsc_nsec = ns; | |
2419 | kvm->arch.cur_tsc_write = data; | |
2420 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 2421 | matched = false; |
f38e098f | 2422 | } |
e26101b1 ZA |
2423 | |
2424 | /* | |
2425 | * We also track th most recent recorded KHZ, write and time to | |
2426 | * allow the matching interval to be extended at each write. | |
2427 | */ | |
f38e098f ZA |
2428 | kvm->arch.last_tsc_nsec = ns; |
2429 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 2430 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 2431 | |
b183aa58 | 2432 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
2433 | |
2434 | /* Keep track of which generation this VCPU has synchronized to */ | |
2435 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2436 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2437 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2438 | ||
a545ab6a | 2439 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
e26101b1 | 2440 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
b48aa97e | 2441 | |
a83829f5 | 2442 | spin_lock_irqsave(&kvm->arch.pvclock_gtod_sync_lock, flags); |
0d3da0d2 | 2443 | if (!matched) { |
b48aa97e | 2444 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
2445 | } else if (!already_matched) { |
2446 | kvm->arch.nr_vcpus_matched_tsc++; | |
2447 | } | |
b48aa97e MT |
2448 | |
2449 | kvm_track_tsc_matching(vcpu); | |
a83829f5 | 2450 | spin_unlock_irqrestore(&kvm->arch.pvclock_gtod_sync_lock, flags); |
99e3e30a | 2451 | } |
e26101b1 | 2452 | |
58ea6767 HZ |
2453 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2454 | s64 adjustment) | |
2455 | { | |
56ba77a4 | 2456 | u64 tsc_offset = vcpu->arch.l1_tsc_offset; |
326e7425 | 2457 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); |
58ea6767 HZ |
2458 | } |
2459 | ||
2460 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2461 | { | |
2462 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) | |
2463 | WARN_ON(adjustment < 0); | |
2464 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); | |
ea26e4ec | 2465 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2466 | } |
2467 | ||
d828199e MT |
2468 | #ifdef CONFIG_X86_64 |
2469 | ||
a5a1d1c2 | 2470 | static u64 read_tsc(void) |
d828199e | 2471 | { |
a5a1d1c2 | 2472 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2473 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2474 | |
2475 | if (likely(ret >= last)) | |
2476 | return ret; | |
2477 | ||
2478 | /* | |
2479 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2480 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2481 | * very likely) and there's a data dependence, so force GCC |
2482 | * to generate a branch instead. I don't barrier() because | |
2483 | * we don't actually need a barrier, and if this function | |
2484 | * ever gets inlined it will generate worse code. | |
2485 | */ | |
2486 | asm volatile (""); | |
2487 | return last; | |
2488 | } | |
2489 | ||
53fafdbb MT |
2490 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2491 | int *mode) | |
d828199e MT |
2492 | { |
2493 | long v; | |
b0c39dc6 VK |
2494 | u64 tsc_pg_val; |
2495 | ||
53fafdbb | 2496 | switch (clock->vclock_mode) { |
b95a8a27 | 2497 | case VDSO_CLOCKMODE_HVCLOCK: |
b0c39dc6 VK |
2498 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), |
2499 | tsc_timestamp); | |
2500 | if (tsc_pg_val != U64_MAX) { | |
2501 | /* TSC page valid */ | |
b95a8a27 | 2502 | *mode = VDSO_CLOCKMODE_HVCLOCK; |
53fafdbb MT |
2503 | v = (tsc_pg_val - clock->cycle_last) & |
2504 | clock->mask; | |
b0c39dc6 VK |
2505 | } else { |
2506 | /* TSC page invalid */ | |
b95a8a27 | 2507 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 VK |
2508 | } |
2509 | break; | |
b95a8a27 TG |
2510 | case VDSO_CLOCKMODE_TSC: |
2511 | *mode = VDSO_CLOCKMODE_TSC; | |
b0c39dc6 | 2512 | *tsc_timestamp = read_tsc(); |
53fafdbb MT |
2513 | v = (*tsc_timestamp - clock->cycle_last) & |
2514 | clock->mask; | |
b0c39dc6 VK |
2515 | break; |
2516 | default: | |
b95a8a27 | 2517 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 | 2518 | } |
d828199e | 2519 | |
b95a8a27 | 2520 | if (*mode == VDSO_CLOCKMODE_NONE) |
b0c39dc6 | 2521 | *tsc_timestamp = v = 0; |
d828199e | 2522 | |
53fafdbb | 2523 | return v * clock->mult; |
d828199e MT |
2524 | } |
2525 | ||
53fafdbb | 2526 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2527 | { |
cbcf2dd3 | 2528 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2529 | unsigned long seq; |
d828199e | 2530 | int mode; |
cbcf2dd3 | 2531 | u64 ns; |
d828199e | 2532 | |
d828199e MT |
2533 | do { |
2534 | seq = read_seqcount_begin(>od->seq); | |
917f9475 | 2535 | ns = gtod->raw_clock.base_cycles; |
53fafdbb | 2536 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); |
917f9475 PB |
2537 | ns >>= gtod->raw_clock.shift; |
2538 | ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); | |
d828199e | 2539 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2540 | *t = ns; |
d828199e MT |
2541 | |
2542 | return mode; | |
2543 | } | |
2544 | ||
899a31f5 | 2545 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2546 | { |
2547 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2548 | unsigned long seq; | |
2549 | int mode; | |
2550 | u64 ns; | |
2551 | ||
2552 | do { | |
2553 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 | 2554 | ts->tv_sec = gtod->wall_time_sec; |
917f9475 | 2555 | ns = gtod->clock.base_cycles; |
53fafdbb | 2556 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2557 | ns >>= gtod->clock.shift; |
2558 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2559 | ||
2560 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2561 | ts->tv_nsec = ns; | |
2562 | ||
2563 | return mode; | |
2564 | } | |
2565 | ||
b0c39dc6 VK |
2566 | /* returns true if host is using TSC based clocksource */ |
2567 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2568 | { |
d828199e | 2569 | /* checked again under seqlock below */ |
b0c39dc6 | 2570 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2571 | return false; |
2572 | ||
53fafdbb | 2573 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2574 | tsc_timestamp)); |
d828199e | 2575 | } |
55dd00a7 | 2576 | |
b0c39dc6 | 2577 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2578 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2579 | u64 *tsc_timestamp) |
55dd00a7 MT |
2580 | { |
2581 | /* checked again under seqlock below */ | |
b0c39dc6 | 2582 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2583 | return false; |
2584 | ||
b0c39dc6 | 2585 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2586 | } |
d828199e MT |
2587 | #endif |
2588 | ||
2589 | /* | |
2590 | * | |
b48aa97e MT |
2591 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2592 | * across virtual CPUs, the following condition is possible. | |
2593 | * Each numbered line represents an event visible to both | |
d828199e MT |
2594 | * CPUs at the next numbered event. |
2595 | * | |
2596 | * "timespecX" represents host monotonic time. "tscX" represents | |
2597 | * RDTSC value. | |
2598 | * | |
2599 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2600 | * | |
2601 | * 1. read timespec0,tsc0 | |
2602 | * 2. | timespec1 = timespec0 + N | |
2603 | * | tsc1 = tsc0 + M | |
2604 | * 3. transition to guest | transition to guest | |
2605 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2606 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2607 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2608 | * | |
2609 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2610 | * | |
2611 | * - ret0 < ret1 | |
2612 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2613 | * ... | |
2614 | * - 0 < N - M => M < N | |
2615 | * | |
2616 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2617 | * always the case (the difference between two distinct xtime instances | |
2618 | * might be smaller then the difference between corresponding TSC reads, | |
2619 | * when updating guest vcpus pvclock areas). | |
2620 | * | |
2621 | * To avoid that problem, do not allow visibility of distinct | |
2622 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2623 | * copy of host monotonic time values. Update that master copy | |
2624 | * in lockstep. | |
2625 | * | |
b48aa97e | 2626 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2627 | * |
2628 | */ | |
2629 | ||
2630 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2631 | { | |
2632 | #ifdef CONFIG_X86_64 | |
2633 | struct kvm_arch *ka = &kvm->arch; | |
2634 | int vclock_mode; | |
b48aa97e MT |
2635 | bool host_tsc_clocksource, vcpus_matched; |
2636 | ||
2637 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2638 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2639 | |
2640 | /* | |
2641 | * If the host uses TSC clock, then passthrough TSC as stable | |
2642 | * to the guest. | |
2643 | */ | |
b48aa97e | 2644 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2645 | &ka->master_kernel_ns, |
2646 | &ka->master_cycle_now); | |
2647 | ||
16a96021 | 2648 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2649 | && !ka->backwards_tsc_observed |
54750f2c | 2650 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2651 | |
d828199e MT |
2652 | if (ka->use_master_clock) |
2653 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2654 | ||
2655 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2656 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2657 | vcpus_matched); | |
d828199e MT |
2658 | #endif |
2659 | } | |
2660 | ||
2860c4b1 PB |
2661 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2662 | { | |
2663 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2664 | } | |
2665 | ||
2e762ff7 MT |
2666 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
2667 | { | |
2668 | #ifdef CONFIG_X86_64 | |
2669 | int i; | |
2670 | struct kvm_vcpu *vcpu; | |
2671 | struct kvm_arch *ka = &kvm->arch; | |
a83829f5 | 2672 | unsigned long flags; |
2e762ff7 | 2673 | |
e880c6ea VK |
2674 | kvm_hv_invalidate_tsc_page(kvm); |
2675 | ||
2e762ff7 | 2676 | kvm_make_mclock_inprogress_request(kvm); |
c2c647f9 | 2677 | |
2e762ff7 | 2678 | /* no guest entries from this point */ |
a83829f5 | 2679 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
2e762ff7 | 2680 | pvclock_update_vm_gtod_copy(kvm); |
a83829f5 | 2681 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
2e762ff7 MT |
2682 | |
2683 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 2684 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2685 | |
2686 | /* guest entries allowed */ | |
2687 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2688 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
2689 | #endif |
2690 | } | |
2691 | ||
e891a32e | 2692 | u64 get_kvmclock_ns(struct kvm *kvm) |
108b249c | 2693 | { |
108b249c | 2694 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2695 | struct pvclock_vcpu_time_info hv_clock; |
a83829f5 | 2696 | unsigned long flags; |
e2c2206a | 2697 | u64 ret; |
108b249c | 2698 | |
a83829f5 | 2699 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
8b953440 | 2700 | if (!ka->use_master_clock) { |
a83829f5 | 2701 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
8171cd68 | 2702 | return get_kvmclock_base_ns() + ka->kvmclock_offset; |
108b249c PB |
2703 | } |
2704 | ||
8b953440 PB |
2705 | hv_clock.tsc_timestamp = ka->master_cycle_now; |
2706 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
a83829f5 | 2707 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
8b953440 | 2708 | |
e2c2206a WL |
2709 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2710 | get_cpu(); | |
2711 | ||
e70b57a6 WL |
2712 | if (__this_cpu_read(cpu_tsc_khz)) { |
2713 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, | |
2714 | &hv_clock.tsc_shift, | |
2715 | &hv_clock.tsc_to_system_mul); | |
2716 | ret = __pvclock_read_cycles(&hv_clock, rdtsc()); | |
2717 | } else | |
8171cd68 | 2718 | ret = get_kvmclock_base_ns() + ka->kvmclock_offset; |
e2c2206a WL |
2719 | |
2720 | put_cpu(); | |
2721 | ||
2722 | return ret; | |
108b249c PB |
2723 | } |
2724 | ||
aa096aa0 JM |
2725 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v, |
2726 | struct gfn_to_hva_cache *cache, | |
2727 | unsigned int offset) | |
0d6dd2ff PB |
2728 | { |
2729 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
2730 | struct pvclock_vcpu_time_info guest_hv_clock; | |
2731 | ||
aa096aa0 JM |
2732 | if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, |
2733 | &guest_hv_clock, offset, sizeof(guest_hv_clock)))) | |
0d6dd2ff PB |
2734 | return; |
2735 | ||
2736 | /* This VCPU is paused, but it's legal for a guest to read another | |
2737 | * VCPU's kvmclock, so we really have to follow the specification where | |
2738 | * it says that version is odd if data is being modified, and even after | |
2739 | * it is consistent. | |
2740 | * | |
2741 | * Version field updates must be kept separate. This is because | |
2742 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
2743 | * writes within a string instruction are weakly ordered. So there | |
2744 | * are three writes overall. | |
2745 | * | |
2746 | * As a small optimization, only write the version field in the first | |
2747 | * and third write. The vcpu->pv_time cache is still valid, because the | |
2748 | * version field is the first in the struct. | |
2749 | */ | |
2750 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
2751 | ||
51c4b8bb LA |
2752 | if (guest_hv_clock.version & 1) |
2753 | ++guest_hv_clock.version; /* first time write, random junk */ | |
2754 | ||
0d6dd2ff | 2755 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
aa096aa0 JM |
2756 | kvm_write_guest_offset_cached(v->kvm, cache, |
2757 | &vcpu->hv_clock, offset, | |
2758 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2759 | |
2760 | smp_wmb(); | |
2761 | ||
2762 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
2763 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
2764 | ||
2765 | if (vcpu->pvclock_set_guest_stopped_request) { | |
2766 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
2767 | vcpu->pvclock_set_guest_stopped_request = false; | |
2768 | } | |
2769 | ||
2770 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
2771 | ||
aa096aa0 JM |
2772 | kvm_write_guest_offset_cached(v->kvm, cache, |
2773 | &vcpu->hv_clock, offset, | |
2774 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
2775 | |
2776 | smp_wmb(); | |
2777 | ||
2778 | vcpu->hv_clock.version++; | |
aa096aa0 JM |
2779 | kvm_write_guest_offset_cached(v->kvm, cache, |
2780 | &vcpu->hv_clock, offset, | |
2781 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2782 | } |
2783 | ||
34c238a1 | 2784 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 2785 | { |
78db6a50 | 2786 | unsigned long flags, tgt_tsc_khz; |
18068523 | 2787 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 2788 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 2789 | s64 kernel_ns; |
d828199e | 2790 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 2791 | u8 pvclock_flags; |
d828199e MT |
2792 | bool use_master_clock; |
2793 | ||
2794 | kernel_ns = 0; | |
2795 | host_tsc = 0; | |
18068523 | 2796 | |
d828199e MT |
2797 | /* |
2798 | * If the host uses TSC clock, then passthrough TSC as stable | |
2799 | * to the guest. | |
2800 | */ | |
a83829f5 | 2801 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
d828199e MT |
2802 | use_master_clock = ka->use_master_clock; |
2803 | if (use_master_clock) { | |
2804 | host_tsc = ka->master_cycle_now; | |
2805 | kernel_ns = ka->master_kernel_ns; | |
2806 | } | |
a83829f5 | 2807 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
c09664bb MT |
2808 | |
2809 | /* Keep irq disabled to prevent changes to the clock */ | |
2810 | local_irq_save(flags); | |
78db6a50 PB |
2811 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2812 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2813 | local_irq_restore(flags); |
2814 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2815 | return 1; | |
2816 | } | |
d828199e | 2817 | if (!use_master_clock) { |
4ea1636b | 2818 | host_tsc = rdtsc(); |
8171cd68 | 2819 | kernel_ns = get_kvmclock_base_ns(); |
d828199e MT |
2820 | } |
2821 | ||
4ba76538 | 2822 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2823 | |
c285545f ZA |
2824 | /* |
2825 | * We may have to catch up the TSC to match elapsed wall clock | |
2826 | * time for two reasons, even if kvmclock is used. | |
2827 | * 1) CPU could have been running below the maximum TSC rate | |
2828 | * 2) Broken TSC compensation resets the base at each VCPU | |
2829 | * entry to avoid unknown leaps of TSC even when running | |
2830 | * again on the same CPU. This may cause apparent elapsed | |
2831 | * time to disappear, and the guest to stand still or run | |
2832 | * very slowly. | |
2833 | */ | |
2834 | if (vcpu->tsc_catchup) { | |
2835 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
2836 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 2837 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
2838 | tsc_timestamp = tsc; |
2839 | } | |
50d0a0f9 GH |
2840 | } |
2841 | ||
18068523 GOC |
2842 | local_irq_restore(flags); |
2843 | ||
0d6dd2ff | 2844 | /* With all the info we got, fill in the values */ |
18068523 | 2845 | |
78db6a50 PB |
2846 | if (kvm_has_tsc_control) |
2847 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); | |
2848 | ||
2849 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 2850 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
2851 | &vcpu->hv_clock.tsc_shift, |
2852 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 2853 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
2854 | } |
2855 | ||
1d5f066e | 2856 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 2857 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 2858 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 2859 | |
d828199e | 2860 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 2861 | pvclock_flags = 0; |
d828199e MT |
2862 | if (use_master_clock) |
2863 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
2864 | ||
78c0337a MT |
2865 | vcpu->hv_clock.flags = pvclock_flags; |
2866 | ||
095cf55d | 2867 | if (vcpu->pv_time_enabled) |
aa096aa0 JM |
2868 | kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); |
2869 | if (vcpu->xen.vcpu_info_set) | |
2870 | kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, | |
2871 | offsetof(struct compat_vcpu_info, time)); | |
f2340cd9 JM |
2872 | if (vcpu->xen.vcpu_time_info_set) |
2873 | kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); | |
095cf55d PB |
2874 | if (v == kvm_get_vcpu(v->kvm, 0)) |
2875 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); | |
8cfdc000 | 2876 | return 0; |
c8076604 GH |
2877 | } |
2878 | ||
0061d53d MT |
2879 | /* |
2880 | * kvmclock updates which are isolated to a given vcpu, such as | |
2881 | * vcpu->cpu migration, should not allow system_timestamp from | |
2882 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
2883 | * correction applies to one vcpu's system_timestamp but not | |
2884 | * the others. | |
2885 | * | |
2886 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
2887 | * We need to rate-limit these requests though, as they can |
2888 | * considerably slow guests that have a large number of vcpus. | |
2889 | * The time for a remote vcpu to update its kvmclock is bound | |
2890 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
2891 | */ |
2892 | ||
7e44e449 AJ |
2893 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
2894 | ||
2895 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
2896 | { |
2897 | int i; | |
7e44e449 AJ |
2898 | struct delayed_work *dwork = to_delayed_work(work); |
2899 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2900 | kvmclock_update_work); | |
2901 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
2902 | struct kvm_vcpu *vcpu; |
2903 | ||
2904 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 2905 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
2906 | kvm_vcpu_kick(vcpu); |
2907 | } | |
2908 | } | |
2909 | ||
7e44e449 AJ |
2910 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
2911 | { | |
2912 | struct kvm *kvm = v->kvm; | |
2913 | ||
105b21bb | 2914 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
2915 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
2916 | KVMCLOCK_UPDATE_DELAY); | |
2917 | } | |
2918 | ||
332967a3 AJ |
2919 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
2920 | ||
2921 | static void kvmclock_sync_fn(struct work_struct *work) | |
2922 | { | |
2923 | struct delayed_work *dwork = to_delayed_work(work); | |
2924 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2925 | kvmclock_sync_work); | |
2926 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
2927 | ||
630994b3 MT |
2928 | if (!kvmclock_periodic_sync) |
2929 | return; | |
2930 | ||
332967a3 AJ |
2931 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
2932 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
2933 | KVMCLOCK_SYNC_PERIOD); | |
2934 | } | |
2935 | ||
191c8137 BP |
2936 | /* |
2937 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
2938 | */ | |
2939 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
2940 | { | |
2941 | /* McStatusWrEn enabled? */ | |
23493d0a | 2942 | if (guest_cpuid_is_amd_or_hygon(vcpu)) |
191c8137 BP |
2943 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); |
2944 | ||
2945 | return false; | |
2946 | } | |
2947 | ||
9ffd986c | 2948 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2949 | { |
890ca9ae HY |
2950 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2951 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
2952 | u32 msr = msr_info->index; |
2953 | u64 data = msr_info->data; | |
890ca9ae | 2954 | |
15c4a640 | 2955 | switch (msr) { |
15c4a640 | 2956 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 2957 | vcpu->arch.mcg_status = data; |
15c4a640 | 2958 | break; |
c7ac679c | 2959 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
2960 | if (!(mcg_cap & MCG_CTL_P) && |
2961 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
2962 | return 1; |
2963 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 2964 | return 1; |
890ca9ae HY |
2965 | vcpu->arch.mcg_ctl = data; |
2966 | break; | |
2967 | default: | |
2968 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2969 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
2970 | u32 offset = array_index_nospec( |
2971 | msr - MSR_IA32_MC0_CTL, | |
2972 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
2973 | ||
114be429 AP |
2974 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
2975 | * some Linux kernels though clear bit 10 in bank 4 to | |
2976 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
2977 | * this to avoid an uncatched #GP in the guest | |
2978 | */ | |
890ca9ae | 2979 | if ((offset & 0x3) == 0 && |
114be429 | 2980 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 2981 | return -1; |
191c8137 BP |
2982 | |
2983 | /* MCi_STATUS */ | |
9ffd986c | 2984 | if (!msr_info->host_initiated && |
191c8137 BP |
2985 | (offset & 0x3) == 1 && data != 0) { |
2986 | if (!can_set_mci_status(vcpu)) | |
2987 | return -1; | |
2988 | } | |
2989 | ||
890ca9ae HY |
2990 | vcpu->arch.mce_banks[offset] = data; |
2991 | break; | |
2992 | } | |
2993 | return 1; | |
2994 | } | |
2995 | return 0; | |
2996 | } | |
2997 | ||
2635b5c4 VK |
2998 | static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) |
2999 | { | |
3000 | u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; | |
3001 | ||
3002 | return (vcpu->arch.apf.msr_en_val & mask) == mask; | |
3003 | } | |
3004 | ||
344d9588 GN |
3005 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
3006 | { | |
3007 | gpa_t gpa = data & ~0x3f; | |
3008 | ||
2635b5c4 VK |
3009 | /* Bits 4:5 are reserved, Should be zero */ |
3010 | if (data & 0x30) | |
344d9588 GN |
3011 | return 1; |
3012 | ||
66570e96 OU |
3013 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && |
3014 | (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) | |
3015 | return 1; | |
3016 | ||
3017 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && | |
3018 | (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) | |
3019 | return 1; | |
3020 | ||
9d3c447c | 3021 | if (!lapic_in_kernel(vcpu)) |
d831de17 | 3022 | return data ? 1 : 0; |
9d3c447c | 3023 | |
2635b5c4 | 3024 | vcpu->arch.apf.msr_en_val = data; |
344d9588 | 3025 | |
2635b5c4 | 3026 | if (!kvm_pv_async_pf_enabled(vcpu)) { |
344d9588 GN |
3027 | kvm_clear_async_pf_completion_queue(vcpu); |
3028 | kvm_async_pf_hash_reset(vcpu); | |
3029 | return 0; | |
3030 | } | |
3031 | ||
4e335d9e | 3032 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
68fd66f1 | 3033 | sizeof(u64))) |
344d9588 GN |
3034 | return 1; |
3035 | ||
6adba527 | 3036 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 3037 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
2635b5c4 | 3038 | |
344d9588 | 3039 | kvm_async_pf_wakeup_all(vcpu); |
2635b5c4 VK |
3040 | |
3041 | return 0; | |
3042 | } | |
3043 | ||
3044 | static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) | |
3045 | { | |
3046 | /* Bits 8-63 are reserved */ | |
3047 | if (data >> 8) | |
3048 | return 1; | |
3049 | ||
3050 | if (!lapic_in_kernel(vcpu)) | |
3051 | return 1; | |
3052 | ||
3053 | vcpu->arch.apf.msr_int_val = data; | |
3054 | ||
3055 | vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; | |
3056 | ||
344d9588 GN |
3057 | return 0; |
3058 | } | |
3059 | ||
12f9a48f GC |
3060 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
3061 | { | |
0b79459b | 3062 | vcpu->arch.pv_time_enabled = false; |
49dedf0d | 3063 | vcpu->arch.time = 0; |
12f9a48f GC |
3064 | } |
3065 | ||
7780938c | 3066 | static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) |
f38a7b75 WL |
3067 | { |
3068 | ++vcpu->stat.tlb_flush; | |
b3646477 | 3069 | static_call(kvm_x86_tlb_flush_all)(vcpu); |
f38a7b75 WL |
3070 | } |
3071 | ||
0baedd79 VK |
3072 | static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) |
3073 | { | |
3074 | ++vcpu->stat.tlb_flush; | |
b53e84ee LJ |
3075 | |
3076 | if (!tdp_enabled) { | |
3077 | /* | |
3078 | * A TLB flush on behalf of the guest is equivalent to | |
3079 | * INVPCID(all), toggling CR4.PGE, etc., which requires | |
3080 | * a forced sync of the shadow page tables. Unload the | |
3081 | * entire MMU here and the subsequent load will sync the | |
3082 | * shadow page tables, and also flush the TLB. | |
3083 | */ | |
3084 | kvm_mmu_unload(vcpu); | |
3085 | return; | |
3086 | } | |
3087 | ||
b3646477 | 3088 | static_call(kvm_x86_tlb_flush_guest)(vcpu); |
0baedd79 VK |
3089 | } |
3090 | ||
c9aaa895 GC |
3091 | static void record_steal_time(struct kvm_vcpu *vcpu) |
3092 | { | |
b0431382 BO |
3093 | struct kvm_host_map map; |
3094 | struct kvm_steal_time *st; | |
3095 | ||
30b5c851 DW |
3096 | if (kvm_xen_msr_enabled(vcpu->kvm)) { |
3097 | kvm_xen_runstate_set_running(vcpu); | |
3098 | return; | |
3099 | } | |
3100 | ||
c9aaa895 GC |
3101 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
3102 | return; | |
3103 | ||
b0431382 BO |
3104 | /* -EAGAIN is returned in atomic context so we can just return. */ |
3105 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, | |
3106 | &map, &vcpu->arch.st.cache, false)) | |
c9aaa895 GC |
3107 | return; |
3108 | ||
b0431382 BO |
3109 | st = map.hva + |
3110 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
3111 | ||
f38a7b75 WL |
3112 | /* |
3113 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
3114 | * expensive IPIs. | |
3115 | */ | |
66570e96 | 3116 | if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { |
af3511ff LJ |
3117 | u8 st_preempted = xchg(&st->preempted, 0); |
3118 | ||
66570e96 | 3119 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, |
af3511ff LJ |
3120 | st_preempted & KVM_VCPU_FLUSH_TLB); |
3121 | if (st_preempted & KVM_VCPU_FLUSH_TLB) | |
66570e96 | 3122 | kvm_vcpu_flush_tlb_guest(vcpu); |
1eff0ada WL |
3123 | } else { |
3124 | st->preempted = 0; | |
66570e96 | 3125 | } |
0b9f6c46 | 3126 | |
a6bd811f | 3127 | vcpu->arch.st.preempted = 0; |
35f3fae1 | 3128 | |
b0431382 BO |
3129 | if (st->version & 1) |
3130 | st->version += 1; /* first time write, random junk */ | |
35f3fae1 | 3131 | |
b0431382 | 3132 | st->version += 1; |
35f3fae1 WL |
3133 | |
3134 | smp_wmb(); | |
3135 | ||
b0431382 | 3136 | st->steal += current->sched_info.run_delay - |
c54cdf14 LC |
3137 | vcpu->arch.st.last_steal; |
3138 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
35f3fae1 | 3139 | |
35f3fae1 WL |
3140 | smp_wmb(); |
3141 | ||
b0431382 | 3142 | st->version += 1; |
c9aaa895 | 3143 | |
b0431382 | 3144 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); |
c9aaa895 GC |
3145 | } |
3146 | ||
8fe8ab46 | 3147 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3148 | { |
5753785f | 3149 | bool pr = false; |
8fe8ab46 WA |
3150 | u32 msr = msr_info->index; |
3151 | u64 data = msr_info->data; | |
5753785f | 3152 | |
1232f8e6 | 3153 | if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) |
23200b7a | 3154 | return kvm_xen_write_hypercall_page(vcpu, data); |
1232f8e6 | 3155 | |
15c4a640 | 3156 | switch (msr) { |
2e32b719 | 3157 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
3158 | case MSR_IA32_UCODE_WRITE: |
3159 | case MSR_VM_HSAVE_PA: | |
3160 | case MSR_AMD64_PATCH_LOADER: | |
3161 | case MSR_AMD64_BU_CFG2: | |
405a353a | 3162 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3163 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
3164 | break; |
3165 | ||
518e7b94 WL |
3166 | case MSR_IA32_UCODE_REV: |
3167 | if (msr_info->host_initiated) | |
3168 | vcpu->arch.microcode_version = data; | |
3169 | break; | |
0cf9135b SC |
3170 | case MSR_IA32_ARCH_CAPABILITIES: |
3171 | if (!msr_info->host_initiated) | |
3172 | return 1; | |
3173 | vcpu->arch.arch_capabilities = data; | |
3174 | break; | |
d574c539 VK |
3175 | case MSR_IA32_PERF_CAPABILITIES: { |
3176 | struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; | |
3177 | ||
3178 | if (!msr_info->host_initiated) | |
3179 | return 1; | |
3180 | if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) | |
3181 | return 1; | |
3182 | if (data & ~msr_ent.data) | |
3183 | return 1; | |
3184 | ||
3185 | vcpu->arch.perf_capabilities = data; | |
3186 | ||
3187 | return 0; | |
3188 | } | |
15c4a640 | 3189 | case MSR_EFER: |
11988499 | 3190 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
3191 | case MSR_K7_HWCR: |
3192 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 3193 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 3194 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
3195 | |
3196 | /* Handle McStatusWrEn */ | |
3197 | if (data == BIT_ULL(18)) { | |
3198 | vcpu->arch.msr_hwcr = data; | |
3199 | } else if (data != 0) { | |
a737f256 CD |
3200 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
3201 | data); | |
8f1589d9 AP |
3202 | return 1; |
3203 | } | |
15c4a640 | 3204 | break; |
f7c6d140 AP |
3205 | case MSR_FAM10H_MMIO_CONF_BASE: |
3206 | if (data != 0) { | |
a737f256 CD |
3207 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
3208 | "0x%llx\n", data); | |
f7c6d140 AP |
3209 | return 1; |
3210 | } | |
15c4a640 | 3211 | break; |
9ba075a6 | 3212 | case 0x200 ... 0x2ff: |
ff53604b | 3213 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 3214 | case MSR_IA32_APICBASE: |
58cb628d | 3215 | return kvm_set_apic_base(vcpu, msr_info); |
bf10bd0b | 3216 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
0105d1a5 | 3217 | return kvm_x2apic_msr_write(vcpu, msr, data); |
09141ec0 | 3218 | case MSR_IA32_TSC_DEADLINE: |
a3e06bbe LJ |
3219 | kvm_set_lapic_tscdeadline_msr(vcpu, data); |
3220 | break; | |
ba904635 | 3221 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 3222 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 3223 | if (!msr_info->host_initiated) { |
d913b904 | 3224 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 3225 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
3226 | } |
3227 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
3228 | } | |
3229 | break; | |
15c4a640 | 3230 | case MSR_IA32_MISC_ENABLE: |
511a8556 WL |
3231 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
3232 | ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { | |
3233 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) | |
3234 | return 1; | |
3235 | vcpu->arch.ia32_misc_enable_msr = data; | |
aedbaf4f | 3236 | kvm_update_cpuid_runtime(vcpu); |
511a8556 WL |
3237 | } else { |
3238 | vcpu->arch.ia32_misc_enable_msr = data; | |
3239 | } | |
15c4a640 | 3240 | break; |
64d60670 PB |
3241 | case MSR_IA32_SMBASE: |
3242 | if (!msr_info->host_initiated) | |
3243 | return 1; | |
3244 | vcpu->arch.smbase = data; | |
3245 | break; | |
73f624f4 PB |
3246 | case MSR_IA32_POWER_CTL: |
3247 | vcpu->arch.msr_ia32_power_ctl = data; | |
3248 | break; | |
dd259935 | 3249 | case MSR_IA32_TSC: |
0c899c25 PB |
3250 | if (msr_info->host_initiated) { |
3251 | kvm_synchronize_tsc(vcpu, data); | |
3252 | } else { | |
3253 | u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; | |
3254 | adjust_tsc_offset_guest(vcpu, adj); | |
3255 | vcpu->arch.ia32_tsc_adjust_msr += adj; | |
3256 | } | |
dd259935 | 3257 | break; |
864e2ab2 AL |
3258 | case MSR_IA32_XSS: |
3259 | if (!msr_info->host_initiated && | |
3260 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3261 | return 1; | |
3262 | /* | |
a1bead2a SC |
3263 | * KVM supports exposing PT to the guest, but does not support |
3264 | * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than | |
3265 | * XSAVES/XRSTORS to save/restore PT MSRs. | |
864e2ab2 | 3266 | */ |
408e9a31 | 3267 | if (data & ~supported_xss) |
864e2ab2 AL |
3268 | return 1; |
3269 | vcpu->arch.ia32_xss = data; | |
3270 | break; | |
52797bf9 LA |
3271 | case MSR_SMI_COUNT: |
3272 | if (!msr_info->host_initiated) | |
3273 | return 1; | |
3274 | vcpu->arch.smi_count = data; | |
3275 | break; | |
11c6bffa | 3276 | case MSR_KVM_WALL_CLOCK_NEW: |
66570e96 OU |
3277 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3278 | return 1; | |
3279 | ||
629b5348 JM |
3280 | vcpu->kvm->arch.wall_clock = data; |
3281 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
66570e96 | 3282 | break; |
18068523 | 3283 | case MSR_KVM_WALL_CLOCK: |
66570e96 OU |
3284 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3285 | return 1; | |
3286 | ||
629b5348 JM |
3287 | vcpu->kvm->arch.wall_clock = data; |
3288 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
18068523 | 3289 | break; |
11c6bffa | 3290 | case MSR_KVM_SYSTEM_TIME_NEW: |
66570e96 OU |
3291 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3292 | return 1; | |
3293 | ||
5b9bb0eb OU |
3294 | kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); |
3295 | break; | |
3296 | case MSR_KVM_SYSTEM_TIME: | |
66570e96 OU |
3297 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3298 | return 1; | |
3299 | ||
3300 | kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); | |
18068523 | 3301 | break; |
344d9588 | 3302 | case MSR_KVM_ASYNC_PF_EN: |
66570e96 OU |
3303 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3304 | return 1; | |
3305 | ||
344d9588 GN |
3306 | if (kvm_pv_enable_async_pf(vcpu, data)) |
3307 | return 1; | |
3308 | break; | |
2635b5c4 | 3309 | case MSR_KVM_ASYNC_PF_INT: |
66570e96 OU |
3310 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3311 | return 1; | |
3312 | ||
2635b5c4 VK |
3313 | if (kvm_pv_enable_async_pf_int(vcpu, data)) |
3314 | return 1; | |
3315 | break; | |
557a961a | 3316 | case MSR_KVM_ASYNC_PF_ACK: |
66570e96 OU |
3317 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3318 | return 1; | |
557a961a VK |
3319 | if (data & 0x1) { |
3320 | vcpu->arch.apf.pageready_pending = false; | |
3321 | kvm_check_async_pf_completion(vcpu); | |
3322 | } | |
3323 | break; | |
c9aaa895 | 3324 | case MSR_KVM_STEAL_TIME: |
66570e96 OU |
3325 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3326 | return 1; | |
c9aaa895 GC |
3327 | |
3328 | if (unlikely(!sched_info_on())) | |
3329 | return 1; | |
3330 | ||
3331 | if (data & KVM_STEAL_RESERVED_MASK) | |
3332 | return 1; | |
3333 | ||
c9aaa895 GC |
3334 | vcpu->arch.st.msr_val = data; |
3335 | ||
3336 | if (!(data & KVM_MSR_ENABLED)) | |
3337 | break; | |
3338 | ||
c9aaa895 GC |
3339 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
3340 | ||
3341 | break; | |
ae7a2a3f | 3342 | case MSR_KVM_PV_EOI_EN: |
66570e96 OU |
3343 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3344 | return 1; | |
3345 | ||
72bbf935 | 3346 | if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
3347 | return 1; |
3348 | break; | |
c9aaa895 | 3349 | |
2d5ba19b | 3350 | case MSR_KVM_POLL_CONTROL: |
66570e96 OU |
3351 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3352 | return 1; | |
3353 | ||
2d5ba19b MT |
3354 | /* only enable bit supported */ |
3355 | if (data & (-1ULL << 1)) | |
3356 | return 1; | |
3357 | ||
3358 | vcpu->arch.msr_kvm_poll_control = data; | |
3359 | break; | |
3360 | ||
890ca9ae HY |
3361 | case MSR_IA32_MCG_CTL: |
3362 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3363 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 3364 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 3365 | |
6912ac32 WH |
3366 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
3367 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
df561f66 GS |
3368 | pr = true; |
3369 | fallthrough; | |
6912ac32 WH |
3370 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3371 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3372 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3373 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
3374 | |
3375 | if (pr || data != 0) | |
a737f256 CD |
3376 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
3377 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 3378 | break; |
84e0cefa JS |
3379 | case MSR_K7_CLK_CTL: |
3380 | /* | |
3381 | * Ignore all writes to this no longer documented MSR. | |
3382 | * Writes are only relevant for old K7 processors, | |
3383 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 3384 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
3385 | * affected processor models on the command line, hence |
3386 | * the need to ignore the workaround. | |
3387 | */ | |
3388 | break; | |
55cd8e5a | 3389 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3390 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3391 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3392 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3393 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3394 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3395 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3396 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3397 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
3398 | return kvm_hv_set_msr_common(vcpu, msr, data, |
3399 | msr_info->host_initiated); | |
91c9c3ed | 3400 | case MSR_IA32_BBL_CR_CTL3: |
3401 | /* Drop writes to this legacy MSR -- see rdmsr | |
3402 | * counterpart for further detail. | |
3403 | */ | |
fab0aa3b EM |
3404 | if (report_ignored_msrs) |
3405 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
3406 | msr, data); | |
91c9c3ed | 3407 | break; |
2b036c6b | 3408 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3409 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3410 | return 1; |
3411 | vcpu->arch.osvw.length = data; | |
3412 | break; | |
3413 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3414 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3415 | return 1; |
3416 | vcpu->arch.osvw.status = data; | |
3417 | break; | |
db2336a8 KH |
3418 | case MSR_PLATFORM_INFO: |
3419 | if (!msr_info->host_initiated || | |
db2336a8 KH |
3420 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
3421 | cpuid_fault_enabled(vcpu))) | |
3422 | return 1; | |
3423 | vcpu->arch.msr_platform_info = data; | |
3424 | break; | |
3425 | case MSR_MISC_FEATURES_ENABLES: | |
3426 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
3427 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
3428 | !supports_cpuid_fault(vcpu))) | |
3429 | return 1; | |
3430 | vcpu->arch.msr_misc_features_enables = data; | |
3431 | break; | |
15c4a640 | 3432 | default: |
c6702c9d | 3433 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3434 | return kvm_pmu_set_msr(vcpu, msr_info); |
6abe9c13 | 3435 | return KVM_MSR_RET_INVALID; |
15c4a640 CO |
3436 | } |
3437 | return 0; | |
3438 | } | |
3439 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
3440 | ||
44883f01 | 3441 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
3442 | { |
3443 | u64 data; | |
890ca9ae HY |
3444 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3445 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
3446 | |
3447 | switch (msr) { | |
15c4a640 CO |
3448 | case MSR_IA32_P5_MC_ADDR: |
3449 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
3450 | data = 0; |
3451 | break; | |
15c4a640 | 3452 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
3453 | data = vcpu->arch.mcg_cap; |
3454 | break; | |
c7ac679c | 3455 | case MSR_IA32_MCG_CTL: |
44883f01 | 3456 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
3457 | return 1; |
3458 | data = vcpu->arch.mcg_ctl; | |
3459 | break; | |
3460 | case MSR_IA32_MCG_STATUS: | |
3461 | data = vcpu->arch.mcg_status; | |
3462 | break; | |
3463 | default: | |
3464 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3465 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3466 | u32 offset = array_index_nospec( |
3467 | msr - MSR_IA32_MC0_CTL, | |
3468 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3469 | ||
890ca9ae HY |
3470 | data = vcpu->arch.mce_banks[offset]; |
3471 | break; | |
3472 | } | |
3473 | return 1; | |
3474 | } | |
3475 | *pdata = data; | |
3476 | return 0; | |
3477 | } | |
3478 | ||
609e36d3 | 3479 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 3480 | { |
609e36d3 | 3481 | switch (msr_info->index) { |
890ca9ae | 3482 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 3483 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
3484 | case MSR_IA32_LASTBRANCHFROMIP: |
3485 | case MSR_IA32_LASTBRANCHTOIP: | |
3486 | case MSR_IA32_LASTINTFROMIP: | |
3487 | case MSR_IA32_LASTINTTOIP: | |
059e5c32 | 3488 | case MSR_AMD64_SYSCFG: |
3afb1121 PB |
3489 | case MSR_K8_TSEG_ADDR: |
3490 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 3491 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 3492 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 3493 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 3494 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 3495 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 3496 | case MSR_IA32_PERF_CTL: |
405a353a | 3497 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3498 | case MSR_F15H_EX_CFG: |
2ca1a06a VS |
3499 | /* |
3500 | * Intel Sandy Bridge CPUs must support the RAPL (running average power | |
3501 | * limit) MSRs. Just return 0, as we do not want to expose the host | |
3502 | * data here. Do not conditionalize this on CPUID, as KVM does not do | |
3503 | * so for existing CPU-specific MSRs. | |
3504 | */ | |
3505 | case MSR_RAPL_POWER_UNIT: | |
3506 | case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ | |
3507 | case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ | |
3508 | case MSR_PKG_ENERGY_STATUS: /* Total package */ | |
3509 | case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ | |
609e36d3 | 3510 | msr_info->data = 0; |
15c4a640 | 3511 | break; |
c51eb52b | 3512 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
c28fa560 VK |
3513 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
3514 | return kvm_pmu_get_msr(vcpu, msr_info); | |
3515 | if (!msr_info->host_initiated) | |
3516 | return 1; | |
3517 | msr_info->data = 0; | |
3518 | break; | |
6912ac32 WH |
3519 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3520 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
3521 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
3522 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3523 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3524 | return kvm_pmu_get_msr(vcpu, msr_info); |
609e36d3 | 3525 | msr_info->data = 0; |
5753785f | 3526 | break; |
742bc670 | 3527 | case MSR_IA32_UCODE_REV: |
518e7b94 | 3528 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 3529 | break; |
0cf9135b SC |
3530 | case MSR_IA32_ARCH_CAPABILITIES: |
3531 | if (!msr_info->host_initiated && | |
3532 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3533 | return 1; | |
3534 | msr_info->data = vcpu->arch.arch_capabilities; | |
3535 | break; | |
d574c539 VK |
3536 | case MSR_IA32_PERF_CAPABILITIES: |
3537 | if (!msr_info->host_initiated && | |
3538 | !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) | |
3539 | return 1; | |
3540 | msr_info->data = vcpu->arch.perf_capabilities; | |
3541 | break; | |
73f624f4 PB |
3542 | case MSR_IA32_POWER_CTL: |
3543 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
3544 | break; | |
cc5b54dd ML |
3545 | case MSR_IA32_TSC: { |
3546 | /* | |
3547 | * Intel SDM states that MSR_IA32_TSC read adds the TSC offset | |
3548 | * even when not intercepted. AMD manual doesn't explicitly | |
3549 | * state this but appears to behave the same. | |
3550 | * | |
ee6fa053 | 3551 | * On userspace reads and writes, however, we unconditionally |
c0623f5e | 3552 | * return L1's TSC value to ensure backwards-compatible |
ee6fa053 | 3553 | * behavior for migration. |
cc5b54dd ML |
3554 | */ |
3555 | u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset : | |
3556 | vcpu->arch.tsc_offset; | |
3557 | ||
3558 | msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset; | |
dd259935 | 3559 | break; |
cc5b54dd | 3560 | } |
9ba075a6 | 3561 | case MSR_MTRRcap: |
9ba075a6 | 3562 | case 0x200 ... 0x2ff: |
ff53604b | 3563 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 3564 | case 0xcd: /* fsb frequency */ |
609e36d3 | 3565 | msr_info->data = 3; |
15c4a640 | 3566 | break; |
7b914098 JS |
3567 | /* |
3568 | * MSR_EBC_FREQUENCY_ID | |
3569 | * Conservative value valid for even the basic CPU models. | |
3570 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
3571 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
3572 | * and 266MHz for model 3, or 4. Set Core Clock | |
3573 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
3574 | * 31:24) even though these are only valid for CPU | |
3575 | * models > 2, however guests may end up dividing or | |
3576 | * multiplying by zero otherwise. | |
3577 | */ | |
3578 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 3579 | msr_info->data = 1 << 24; |
7b914098 | 3580 | break; |
15c4a640 | 3581 | case MSR_IA32_APICBASE: |
609e36d3 | 3582 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 3583 | break; |
bf10bd0b | 3584 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
609e36d3 | 3585 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
09141ec0 | 3586 | case MSR_IA32_TSC_DEADLINE: |
609e36d3 | 3587 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 3588 | break; |
ba904635 | 3589 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 3590 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 3591 | break; |
15c4a640 | 3592 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 3593 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 3594 | break; |
64d60670 PB |
3595 | case MSR_IA32_SMBASE: |
3596 | if (!msr_info->host_initiated) | |
3597 | return 1; | |
3598 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 3599 | break; |
52797bf9 LA |
3600 | case MSR_SMI_COUNT: |
3601 | msr_info->data = vcpu->arch.smi_count; | |
3602 | break; | |
847f0ad8 AG |
3603 | case MSR_IA32_PERF_STATUS: |
3604 | /* TSC increment by tick */ | |
609e36d3 | 3605 | msr_info->data = 1000ULL; |
847f0ad8 | 3606 | /* CPU multiplier */ |
b0996ae4 | 3607 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 3608 | break; |
15c4a640 | 3609 | case MSR_EFER: |
609e36d3 | 3610 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 3611 | break; |
18068523 | 3612 | case MSR_KVM_WALL_CLOCK: |
1930e5dd OU |
3613 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3614 | return 1; | |
3615 | ||
3616 | msr_info->data = vcpu->kvm->arch.wall_clock; | |
3617 | break; | |
11c6bffa | 3618 | case MSR_KVM_WALL_CLOCK_NEW: |
1930e5dd OU |
3619 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3620 | return 1; | |
3621 | ||
609e36d3 | 3622 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
3623 | break; |
3624 | case MSR_KVM_SYSTEM_TIME: | |
1930e5dd OU |
3625 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3626 | return 1; | |
3627 | ||
3628 | msr_info->data = vcpu->arch.time; | |
3629 | break; | |
11c6bffa | 3630 | case MSR_KVM_SYSTEM_TIME_NEW: |
1930e5dd OU |
3631 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3632 | return 1; | |
3633 | ||
609e36d3 | 3634 | msr_info->data = vcpu->arch.time; |
18068523 | 3635 | break; |
344d9588 | 3636 | case MSR_KVM_ASYNC_PF_EN: |
1930e5dd OU |
3637 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3638 | return 1; | |
3639 | ||
2635b5c4 VK |
3640 | msr_info->data = vcpu->arch.apf.msr_en_val; |
3641 | break; | |
3642 | case MSR_KVM_ASYNC_PF_INT: | |
1930e5dd OU |
3643 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3644 | return 1; | |
3645 | ||
2635b5c4 | 3646 | msr_info->data = vcpu->arch.apf.msr_int_val; |
344d9588 | 3647 | break; |
557a961a | 3648 | case MSR_KVM_ASYNC_PF_ACK: |
1930e5dd OU |
3649 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3650 | return 1; | |
3651 | ||
557a961a VK |
3652 | msr_info->data = 0; |
3653 | break; | |
c9aaa895 | 3654 | case MSR_KVM_STEAL_TIME: |
1930e5dd OU |
3655 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3656 | return 1; | |
3657 | ||
609e36d3 | 3658 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 3659 | break; |
1d92128f | 3660 | case MSR_KVM_PV_EOI_EN: |
1930e5dd OU |
3661 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3662 | return 1; | |
3663 | ||
609e36d3 | 3664 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 3665 | break; |
2d5ba19b | 3666 | case MSR_KVM_POLL_CONTROL: |
1930e5dd OU |
3667 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3668 | return 1; | |
3669 | ||
2d5ba19b MT |
3670 | msr_info->data = vcpu->arch.msr_kvm_poll_control; |
3671 | break; | |
890ca9ae HY |
3672 | case MSR_IA32_P5_MC_ADDR: |
3673 | case MSR_IA32_P5_MC_TYPE: | |
3674 | case MSR_IA32_MCG_CAP: | |
3675 | case MSR_IA32_MCG_CTL: | |
3676 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3677 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
3678 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
3679 | msr_info->host_initiated); | |
864e2ab2 AL |
3680 | case MSR_IA32_XSS: |
3681 | if (!msr_info->host_initiated && | |
3682 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3683 | return 1; | |
3684 | msr_info->data = vcpu->arch.ia32_xss; | |
3685 | break; | |
84e0cefa JS |
3686 | case MSR_K7_CLK_CTL: |
3687 | /* | |
3688 | * Provide expected ramp-up count for K7. All other | |
3689 | * are set to zero, indicating minimum divisors for | |
3690 | * every field. | |
3691 | * | |
3692 | * This prevents guest kernels on AMD host with CPU | |
3693 | * type 6, model 8 and higher from exploding due to | |
3694 | * the rdmsr failing. | |
3695 | */ | |
609e36d3 | 3696 | msr_info->data = 0x20000000; |
84e0cefa | 3697 | break; |
55cd8e5a | 3698 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3699 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3700 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3701 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3702 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3703 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3704 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3705 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3706 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 3707 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
3708 | msr_info->index, &msr_info->data, |
3709 | msr_info->host_initiated); | |
91c9c3ed | 3710 | case MSR_IA32_BBL_CR_CTL3: |
3711 | /* This legacy MSR exists but isn't fully documented in current | |
3712 | * silicon. It is however accessed by winxp in very narrow | |
3713 | * scenarios where it sets bit #19, itself documented as | |
3714 | * a "reserved" bit. Best effort attempt to source coherent | |
3715 | * read data here should the balance of the register be | |
3716 | * interpreted by the guest: | |
3717 | * | |
3718 | * L2 cache control register 3: 64GB range, 256KB size, | |
3719 | * enabled, latency 0x1, configured | |
3720 | */ | |
609e36d3 | 3721 | msr_info->data = 0xbe702111; |
91c9c3ed | 3722 | break; |
2b036c6b | 3723 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3724 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3725 | return 1; |
609e36d3 | 3726 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
3727 | break; |
3728 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3729 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3730 | return 1; |
609e36d3 | 3731 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 3732 | break; |
db2336a8 | 3733 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
3734 | if (!msr_info->host_initiated && |
3735 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
3736 | return 1; | |
db2336a8 KH |
3737 | msr_info->data = vcpu->arch.msr_platform_info; |
3738 | break; | |
3739 | case MSR_MISC_FEATURES_ENABLES: | |
3740 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
3741 | break; | |
191c8137 BP |
3742 | case MSR_K7_HWCR: |
3743 | msr_info->data = vcpu->arch.msr_hwcr; | |
3744 | break; | |
15c4a640 | 3745 | default: |
c6702c9d | 3746 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3747 | return kvm_pmu_get_msr(vcpu, msr_info); |
6abe9c13 | 3748 | return KVM_MSR_RET_INVALID; |
15c4a640 | 3749 | } |
15c4a640 CO |
3750 | return 0; |
3751 | } | |
3752 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
3753 | ||
313a3dc7 CO |
3754 | /* |
3755 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
3756 | * | |
3757 | * @return number of msrs set successfully. | |
3758 | */ | |
3759 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
3760 | struct kvm_msr_entry *entries, | |
3761 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3762 | unsigned index, u64 *data)) | |
3763 | { | |
801e459a | 3764 | int i; |
313a3dc7 | 3765 | |
313a3dc7 CO |
3766 | for (i = 0; i < msrs->nmsrs; ++i) |
3767 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
3768 | break; | |
3769 | ||
313a3dc7 CO |
3770 | return i; |
3771 | } | |
3772 | ||
3773 | /* | |
3774 | * Read or write a bunch of msrs. Parameters are user addresses. | |
3775 | * | |
3776 | * @return number of msrs set successfully. | |
3777 | */ | |
3778 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
3779 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3780 | unsigned index, u64 *data), | |
3781 | int writeback) | |
3782 | { | |
3783 | struct kvm_msrs msrs; | |
3784 | struct kvm_msr_entry *entries; | |
3785 | int r, n; | |
3786 | unsigned size; | |
3787 | ||
3788 | r = -EFAULT; | |
0e96f31e | 3789 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
3790 | goto out; |
3791 | ||
3792 | r = -E2BIG; | |
3793 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
3794 | goto out; | |
3795 | ||
313a3dc7 | 3796 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
3797 | entries = memdup_user(user_msrs->entries, size); |
3798 | if (IS_ERR(entries)) { | |
3799 | r = PTR_ERR(entries); | |
313a3dc7 | 3800 | goto out; |
ff5c2c03 | 3801 | } |
313a3dc7 CO |
3802 | |
3803 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
3804 | if (r < 0) | |
3805 | goto out_free; | |
3806 | ||
3807 | r = -EFAULT; | |
3808 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
3809 | goto out_free; | |
3810 | ||
3811 | r = n; | |
3812 | ||
3813 | out_free: | |
7a73c028 | 3814 | kfree(entries); |
313a3dc7 CO |
3815 | out: |
3816 | return r; | |
3817 | } | |
3818 | ||
4d5422ce WL |
3819 | static inline bool kvm_can_mwait_in_guest(void) |
3820 | { | |
3821 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
3822 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
3823 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
3824 | } |
3825 | ||
c21d54f0 VK |
3826 | static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, |
3827 | struct kvm_cpuid2 __user *cpuid_arg) | |
3828 | { | |
3829 | struct kvm_cpuid2 cpuid; | |
3830 | int r; | |
3831 | ||
3832 | r = -EFAULT; | |
3833 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
3834 | return r; | |
3835 | ||
3836 | r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
3837 | if (r) | |
3838 | return r; | |
3839 | ||
3840 | r = -EFAULT; | |
3841 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
3842 | return r; | |
3843 | ||
3844 | return 0; | |
3845 | } | |
3846 | ||
784aa3d7 | 3847 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 3848 | { |
4d5422ce | 3849 | int r = 0; |
018d00d2 ZX |
3850 | |
3851 | switch (ext) { | |
3852 | case KVM_CAP_IRQCHIP: | |
3853 | case KVM_CAP_HLT: | |
3854 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 3855 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 3856 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 3857 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 3858 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 3859 | case KVM_CAP_PIT: |
a28e4f5a | 3860 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 3861 | case KVM_CAP_MP_STATE: |
ed848624 | 3862 | case KVM_CAP_SYNC_MMU: |
a355c85c | 3863 | case KVM_CAP_USER_NMI: |
52d939a0 | 3864 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 3865 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 3866 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 3867 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 3868 | case KVM_CAP_PIT2: |
e9f42757 | 3869 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 3870 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
3cfc3092 | 3871 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 3872 | case KVM_CAP_HYPERV: |
10388a07 | 3873 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 3874 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 3875 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 3876 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 3877 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 3878 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 3879 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 3880 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 3881 | case KVM_CAP_HYPERV_CPUID: |
c21d54f0 | 3882 | case KVM_CAP_SYS_HYPERV_CPUID: |
ab9f4ecb | 3883 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 3884 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 3885 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 3886 | case KVM_CAP_XSAVE: |
344d9588 | 3887 | case KVM_CAP_ASYNC_PF: |
72de5fa4 | 3888 | case KVM_CAP_ASYNC_PF_INT: |
92a1f12d | 3889 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 3890 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 3891 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 3892 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 3893 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 3894 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 3895 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 3896 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 3897 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 3898 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 3899 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 3900 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 3901 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 3902 | case KVM_CAP_EXCEPTION_PAYLOAD: |
b9b2782c | 3903 | case KVM_CAP_SET_GUEST_DEBUG: |
1aa561b1 | 3904 | case KVM_CAP_LAST_CPU: |
1ae09954 | 3905 | case KVM_CAP_X86_USER_SPACE_MSR: |
1a155254 | 3906 | case KVM_CAP_X86_MSR_FILTER: |
66570e96 | 3907 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
fe7e9488 SC |
3908 | #ifdef CONFIG_X86_SGX_KVM |
3909 | case KVM_CAP_SGX_ATTRIBUTE: | |
3910 | #endif | |
54526d1f | 3911 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
018d00d2 ZX |
3912 | r = 1; |
3913 | break; | |
7e582ccb ML |
3914 | case KVM_CAP_SET_GUEST_DEBUG2: |
3915 | return KVM_GUESTDBG_VALID_MASK; | |
b59b153d | 3916 | #ifdef CONFIG_KVM_XEN |
23200b7a JM |
3917 | case KVM_CAP_XEN_HVM: |
3918 | r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | | |
8d4e7e80 DW |
3919 | KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | |
3920 | KVM_XEN_HVM_CONFIG_SHARED_INFO; | |
30b5c851 DW |
3921 | if (sched_info_on()) |
3922 | r |= KVM_XEN_HVM_CONFIG_RUNSTATE; | |
23200b7a | 3923 | break; |
b59b153d | 3924 | #endif |
01643c51 KH |
3925 | case KVM_CAP_SYNC_REGS: |
3926 | r = KVM_SYNC_X86_VALID_FIELDS; | |
3927 | break; | |
e3fd9a93 PB |
3928 | case KVM_CAP_ADJUST_CLOCK: |
3929 | r = KVM_CLOCK_TSC_STABLE; | |
3930 | break; | |
4d5422ce | 3931 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
3932 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
3933 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
3934 | if(kvm_can_mwait_in_guest()) |
3935 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 3936 | break; |
6d396b55 PB |
3937 | case KVM_CAP_X86_SMM: |
3938 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
3939 | * and SMM handlers might indeed rely on 4G segment limits, | |
3940 | * so do not report SMM to be available if real mode is | |
3941 | * emulated via vm86 mode. Still, do not go to great lengths | |
3942 | * to avoid userspace's usage of the feature, because it is a | |
3943 | * fringe case that is not enabled except via specific settings | |
3944 | * of the module parameters. | |
3945 | */ | |
b3646477 | 3946 | r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); |
6d396b55 | 3947 | break; |
774ead3a | 3948 | case KVM_CAP_VAPIC: |
b3646477 | 3949 | r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); |
774ead3a | 3950 | break; |
f725230a | 3951 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
3952 | r = KVM_SOFT_MAX_VCPUS; |
3953 | break; | |
3954 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
3955 | r = KVM_MAX_VCPUS; |
3956 | break; | |
a86cb413 TH |
3957 | case KVM_CAP_MAX_VCPU_ID: |
3958 | r = KVM_MAX_VCPU_ID; | |
3959 | break; | |
a68a6a72 MT |
3960 | case KVM_CAP_PV_MMU: /* obsolete */ |
3961 | r = 0; | |
2f333bcb | 3962 | break; |
890ca9ae HY |
3963 | case KVM_CAP_MCE: |
3964 | r = KVM_MAX_MCE_BANKS; | |
3965 | break; | |
2d5b5a66 | 3966 | case KVM_CAP_XCRS: |
d366bf7e | 3967 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 3968 | break; |
92a1f12d JR |
3969 | case KVM_CAP_TSC_CONTROL: |
3970 | r = kvm_has_tsc_control; | |
3971 | break; | |
37131313 RK |
3972 | case KVM_CAP_X2APIC_API: |
3973 | r = KVM_X2APIC_API_VALID_FLAGS; | |
3974 | break; | |
8fcc4b59 | 3975 | case KVM_CAP_NESTED_STATE: |
33b22172 PB |
3976 | r = kvm_x86_ops.nested_ops->get_state ? |
3977 | kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; | |
8fcc4b59 | 3978 | break; |
344c6c80 | 3979 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 3980 | r = kvm_x86_ops.enable_direct_tlbflush != NULL; |
5a0165f6 VK |
3981 | break; |
3982 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
33b22172 | 3983 | r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; |
344c6c80 | 3984 | break; |
3edd6839 MG |
3985 | case KVM_CAP_SMALLER_MAXPHYADDR: |
3986 | r = (int) allow_smaller_maxphyaddr; | |
3987 | break; | |
004a0124 AJ |
3988 | case KVM_CAP_STEAL_TIME: |
3989 | r = sched_info_on(); | |
3990 | break; | |
fe6b6bc8 CQ |
3991 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
3992 | if (kvm_has_bus_lock_exit) | |
3993 | r = KVM_BUS_LOCK_DETECTION_OFF | | |
3994 | KVM_BUS_LOCK_DETECTION_EXIT; | |
3995 | else | |
3996 | r = 0; | |
3997 | break; | |
018d00d2 | 3998 | default: |
018d00d2 ZX |
3999 | break; |
4000 | } | |
4001 | return r; | |
4002 | ||
4003 | } | |
4004 | ||
043405e1 CO |
4005 | long kvm_arch_dev_ioctl(struct file *filp, |
4006 | unsigned int ioctl, unsigned long arg) | |
4007 | { | |
4008 | void __user *argp = (void __user *)arg; | |
4009 | long r; | |
4010 | ||
4011 | switch (ioctl) { | |
4012 | case KVM_GET_MSR_INDEX_LIST: { | |
4013 | struct kvm_msr_list __user *user_msr_list = argp; | |
4014 | struct kvm_msr_list msr_list; | |
4015 | unsigned n; | |
4016 | ||
4017 | r = -EFAULT; | |
0e96f31e | 4018 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
4019 | goto out; |
4020 | n = msr_list.nmsrs; | |
62ef68bb | 4021 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 4022 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
4023 | goto out; |
4024 | r = -E2BIG; | |
e125e7b6 | 4025 | if (n < msr_list.nmsrs) |
043405e1 CO |
4026 | goto out; |
4027 | r = -EFAULT; | |
4028 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
4029 | num_msrs_to_save * sizeof(u32))) | |
4030 | goto out; | |
e125e7b6 | 4031 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 4032 | &emulated_msrs, |
62ef68bb | 4033 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
4034 | goto out; |
4035 | r = 0; | |
4036 | break; | |
4037 | } | |
9c15bb1d BP |
4038 | case KVM_GET_SUPPORTED_CPUID: |
4039 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
4040 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
4041 | struct kvm_cpuid2 cpuid; | |
4042 | ||
4043 | r = -EFAULT; | |
0e96f31e | 4044 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 4045 | goto out; |
9c15bb1d BP |
4046 | |
4047 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
4048 | ioctl); | |
674eea0f AK |
4049 | if (r) |
4050 | goto out; | |
4051 | ||
4052 | r = -EFAULT; | |
0e96f31e | 4053 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
4054 | goto out; |
4055 | r = 0; | |
4056 | break; | |
4057 | } | |
cf6c26ec | 4058 | case KVM_X86_GET_MCE_CAP_SUPPORTED: |
890ca9ae | 4059 | r = -EFAULT; |
c45dcc71 AR |
4060 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
4061 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
4062 | goto out; |
4063 | r = 0; | |
4064 | break; | |
801e459a TL |
4065 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
4066 | struct kvm_msr_list __user *user_msr_list = argp; | |
4067 | struct kvm_msr_list msr_list; | |
4068 | unsigned int n; | |
4069 | ||
4070 | r = -EFAULT; | |
4071 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
4072 | goto out; | |
4073 | n = msr_list.nmsrs; | |
4074 | msr_list.nmsrs = num_msr_based_features; | |
4075 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
4076 | goto out; | |
4077 | r = -E2BIG; | |
4078 | if (n < msr_list.nmsrs) | |
4079 | goto out; | |
4080 | r = -EFAULT; | |
4081 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
4082 | num_msr_based_features * sizeof(u32))) | |
4083 | goto out; | |
4084 | r = 0; | |
4085 | break; | |
4086 | } | |
4087 | case KVM_GET_MSRS: | |
4088 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
4089 | break; | |
c21d54f0 VK |
4090 | case KVM_GET_SUPPORTED_HV_CPUID: |
4091 | r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); | |
4092 | break; | |
043405e1 CO |
4093 | default: |
4094 | r = -EINVAL; | |
cf6c26ec | 4095 | break; |
043405e1 CO |
4096 | } |
4097 | out: | |
4098 | return r; | |
4099 | } | |
4100 | ||
f5f48ee1 SY |
4101 | static void wbinvd_ipi(void *garbage) |
4102 | { | |
4103 | wbinvd(); | |
4104 | } | |
4105 | ||
4106 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4107 | { | |
e0f0bbc5 | 4108 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
4109 | } |
4110 | ||
313a3dc7 CO |
4111 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
4112 | { | |
f5f48ee1 SY |
4113 | /* Address WBINVD may be executed by guest */ |
4114 | if (need_emulate_wbinvd(vcpu)) { | |
b3646477 | 4115 | if (static_call(kvm_x86_has_wbinvd_exit)()) |
f5f48ee1 SY |
4116 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); |
4117 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
4118 | smp_call_function_single(vcpu->cpu, | |
4119 | wbinvd_ipi, NULL, 1); | |
4120 | } | |
4121 | ||
b3646477 | 4122 | static_call(kvm_x86_vcpu_load)(vcpu, cpu); |
8f6055cb | 4123 | |
37486135 BM |
4124 | /* Save host pkru register if supported */ |
4125 | vcpu->arch.host_pkru = read_pkru(); | |
4126 | ||
0dd6a6ed ZA |
4127 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
4128 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
4129 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
4130 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 4131 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 4132 | } |
8f6055cb | 4133 | |
b0c39dc6 | 4134 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 4135 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 4136 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
4137 | if (tsc_delta < 0) |
4138 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 4139 | |
b0c39dc6 | 4140 | if (kvm_check_tsc_unstable()) { |
07c1419a | 4141 | u64 offset = kvm_compute_tsc_offset(vcpu, |
b183aa58 | 4142 | vcpu->arch.last_guest_tsc); |
a545ab6a | 4143 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 4144 | vcpu->arch.tsc_catchup = 1; |
c285545f | 4145 | } |
a749e247 PB |
4146 | |
4147 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
4148 | kvm_lapic_restart_hv_timer(vcpu); | |
4149 | ||
d98d07ca MT |
4150 | /* |
4151 | * On a host with synchronized TSC, there is no need to update | |
4152 | * kvmclock on vcpu->cpu migration | |
4153 | */ | |
4154 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 4155 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 4156 | if (vcpu->cpu != cpu) |
1bd2009e | 4157 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 4158 | vcpu->cpu = cpu; |
6b7d7e76 | 4159 | } |
c9aaa895 | 4160 | |
c9aaa895 | 4161 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
4162 | } |
4163 | ||
0b9f6c46 PX |
4164 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
4165 | { | |
b0431382 BO |
4166 | struct kvm_host_map map; |
4167 | struct kvm_steal_time *st; | |
4168 | ||
0b9f6c46 PX |
4169 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
4170 | return; | |
4171 | ||
a6bd811f | 4172 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
4173 | return; |
4174 | ||
b0431382 BO |
4175 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, |
4176 | &vcpu->arch.st.cache, true)) | |
9c1a0744 | 4177 | return; |
b0431382 BO |
4178 | |
4179 | st = map.hva + | |
4180 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
0b9f6c46 | 4181 | |
a6bd811f | 4182 | st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; |
0b9f6c46 | 4183 | |
b0431382 | 4184 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); |
0b9f6c46 PX |
4185 | } |
4186 | ||
313a3dc7 CO |
4187 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
4188 | { | |
9c1a0744 WL |
4189 | int idx; |
4190 | ||
f1c6366e | 4191 | if (vcpu->preempted && !vcpu->arch.guest_state_protected) |
b3646477 | 4192 | vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); |
de63ad4c | 4193 | |
9c1a0744 WL |
4194 | /* |
4195 | * Take the srcu lock as memslots will be accessed to check the gfn | |
4196 | * cache generation against the memslots generation. | |
4197 | */ | |
4198 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
30b5c851 DW |
4199 | if (kvm_xen_msr_enabled(vcpu->kvm)) |
4200 | kvm_xen_runstate_set_preempted(vcpu); | |
4201 | else | |
4202 | kvm_steal_time_set_preempted(vcpu); | |
9c1a0744 | 4203 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
30b5c851 | 4204 | |
b3646477 | 4205 | static_call(kvm_x86_vcpu_put)(vcpu); |
4ea1636b | 4206 | vcpu->arch.last_host_tsc = rdtsc(); |
efdab992 | 4207 | /* |
f9dcf08e RK |
4208 | * If userspace has set any breakpoints or watchpoints, dr6 is restored |
4209 | * on every vmexit, but if not, we might have a stale dr6 from the | |
4210 | * guest. do_debug expects dr6 to be cleared after it runs, do the same. | |
efdab992 | 4211 | */ |
f9dcf08e | 4212 | set_debugreg(0, 6); |
313a3dc7 CO |
4213 | } |
4214 | ||
313a3dc7 CO |
4215 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
4216 | struct kvm_lapic_state *s) | |
4217 | { | |
fa59cc00 | 4218 | if (vcpu->arch.apicv_active) |
b3646477 | 4219 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
d62caabb | 4220 | |
a92e2543 | 4221 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
4222 | } |
4223 | ||
4224 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
4225 | struct kvm_lapic_state *s) | |
4226 | { | |
a92e2543 RK |
4227 | int r; |
4228 | ||
4229 | r = kvm_apic_set_state(vcpu, s); | |
4230 | if (r) | |
4231 | return r; | |
cb142eb7 | 4232 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
4233 | |
4234 | return 0; | |
4235 | } | |
4236 | ||
127a457a MG |
4237 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
4238 | { | |
71cc849b PB |
4239 | /* |
4240 | * We can accept userspace's request for interrupt injection | |
4241 | * as long as we have a place to store the interrupt number. | |
4242 | * The actual injection will happen when the CPU is able to | |
4243 | * deliver the interrupt. | |
4244 | */ | |
4245 | if (kvm_cpu_has_extint(vcpu)) | |
4246 | return false; | |
4247 | ||
4248 | /* Acknowledging ExtINT does not happen if LINT0 is masked. */ | |
127a457a MG |
4249 | return (!lapic_in_kernel(vcpu) || |
4250 | kvm_apic_accept_pic_intr(vcpu)); | |
4251 | } | |
4252 | ||
782d422b MG |
4253 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) |
4254 | { | |
4255 | return kvm_arch_interrupt_allowed(vcpu) && | |
782d422b MG |
4256 | kvm_cpu_accept_dm_intr(vcpu); |
4257 | } | |
4258 | ||
f77bc6a4 ZX |
4259 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
4260 | struct kvm_interrupt *irq) | |
4261 | { | |
02cdb50f | 4262 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 4263 | return -EINVAL; |
1c1a9ce9 SR |
4264 | |
4265 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
4266 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
4267 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4268 | return 0; | |
4269 | } | |
4270 | ||
4271 | /* | |
4272 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
4273 | * fail for in-kernel 8259. | |
4274 | */ | |
4275 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 4276 | return -ENXIO; |
f77bc6a4 | 4277 | |
1c1a9ce9 SR |
4278 | if (vcpu->arch.pending_external_vector != -1) |
4279 | return -EEXIST; | |
f77bc6a4 | 4280 | |
1c1a9ce9 | 4281 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 4282 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
4283 | return 0; |
4284 | } | |
4285 | ||
c4abb7c9 JK |
4286 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
4287 | { | |
c4abb7c9 | 4288 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
4289 | |
4290 | return 0; | |
4291 | } | |
4292 | ||
f077825a PB |
4293 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
4294 | { | |
64d60670 PB |
4295 | kvm_make_request(KVM_REQ_SMI, vcpu); |
4296 | ||
f077825a PB |
4297 | return 0; |
4298 | } | |
4299 | ||
b209749f AK |
4300 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
4301 | struct kvm_tpr_access_ctl *tac) | |
4302 | { | |
4303 | if (tac->flags) | |
4304 | return -EINVAL; | |
4305 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
4306 | return 0; | |
4307 | } | |
4308 | ||
890ca9ae HY |
4309 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
4310 | u64 mcg_cap) | |
4311 | { | |
4312 | int r; | |
4313 | unsigned bank_num = mcg_cap & 0xff, bank; | |
4314 | ||
4315 | r = -EINVAL; | |
c4e0e4ab | 4316 | if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) |
890ca9ae | 4317 | goto out; |
c45dcc71 | 4318 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
4319 | goto out; |
4320 | r = 0; | |
4321 | vcpu->arch.mcg_cap = mcg_cap; | |
4322 | /* Init IA32_MCG_CTL to all 1s */ | |
4323 | if (mcg_cap & MCG_CTL_P) | |
4324 | vcpu->arch.mcg_ctl = ~(u64)0; | |
4325 | /* Init IA32_MCi_CTL to all 1s */ | |
4326 | for (bank = 0; bank < bank_num; bank++) | |
4327 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 | 4328 | |
b3646477 | 4329 | static_call(kvm_x86_setup_mce)(vcpu); |
890ca9ae HY |
4330 | out: |
4331 | return r; | |
4332 | } | |
4333 | ||
4334 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
4335 | struct kvm_x86_mce *mce) | |
4336 | { | |
4337 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
4338 | unsigned bank_num = mcg_cap & 0xff; | |
4339 | u64 *banks = vcpu->arch.mce_banks; | |
4340 | ||
4341 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
4342 | return -EINVAL; | |
4343 | /* | |
4344 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
4345 | * reporting is disabled | |
4346 | */ | |
4347 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
4348 | vcpu->arch.mcg_ctl != ~(u64)0) | |
4349 | return 0; | |
4350 | banks += 4 * mce->bank; | |
4351 | /* | |
4352 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
4353 | * reporting is disabled for the bank | |
4354 | */ | |
4355 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
4356 | return 0; | |
4357 | if (mce->status & MCI_STATUS_UC) { | |
4358 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 4359 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 4360 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
4361 | return 0; |
4362 | } | |
4363 | if (banks[1] & MCI_STATUS_VAL) | |
4364 | mce->status |= MCI_STATUS_OVER; | |
4365 | banks[2] = mce->addr; | |
4366 | banks[3] = mce->misc; | |
4367 | vcpu->arch.mcg_status = mce->mcg_status; | |
4368 | banks[1] = mce->status; | |
4369 | kvm_queue_exception(vcpu, MC_VECTOR); | |
4370 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
4371 | || !(banks[1] & MCI_STATUS_UC)) { | |
4372 | if (banks[1] & MCI_STATUS_VAL) | |
4373 | mce->status |= MCI_STATUS_OVER; | |
4374 | banks[2] = mce->addr; | |
4375 | banks[3] = mce->misc; | |
4376 | banks[1] = mce->status; | |
4377 | } else | |
4378 | banks[1] |= MCI_STATUS_OVER; | |
4379 | return 0; | |
4380 | } | |
4381 | ||
3cfc3092 JK |
4382 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
4383 | struct kvm_vcpu_events *events) | |
4384 | { | |
7460fb4a | 4385 | process_nmi(vcpu); |
59073aaf | 4386 | |
1f7becf1 JZ |
4387 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
4388 | process_smi(vcpu); | |
4389 | ||
a06230b6 OU |
4390 | /* |
4391 | * In guest mode, payload delivery should be deferred, | |
4392 | * so that the L1 hypervisor can intercept #PF before | |
4393 | * CR2 is modified (or intercept #DB before DR6 is | |
4394 | * modified under nVMX). Unless the per-VM capability, | |
4395 | * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of | |
4396 | * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we | |
4397 | * opportunistically defer the exception payload, deliver it if the | |
4398 | * capability hasn't been requested before processing a | |
4399 | * KVM_GET_VCPU_EVENTS. | |
4400 | */ | |
4401 | if (!vcpu->kvm->arch.exception_payload_enabled && | |
4402 | vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) | |
4403 | kvm_deliver_exception_payload(vcpu); | |
4404 | ||
664f8e26 | 4405 | /* |
59073aaf JM |
4406 | * The API doesn't provide the instruction length for software |
4407 | * exceptions, so don't report them. As long as the guest RIP | |
4408 | * isn't advanced, we should expect to encounter the exception | |
4409 | * again. | |
664f8e26 | 4410 | */ |
59073aaf JM |
4411 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
4412 | events->exception.injected = 0; | |
4413 | events->exception.pending = 0; | |
4414 | } else { | |
4415 | events->exception.injected = vcpu->arch.exception.injected; | |
4416 | events->exception.pending = vcpu->arch.exception.pending; | |
4417 | /* | |
4418 | * For ABI compatibility, deliberately conflate | |
4419 | * pending and injected exceptions when | |
4420 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
4421 | */ | |
4422 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4423 | events->exception.injected |= | |
4424 | vcpu->arch.exception.pending; | |
4425 | } | |
3cfc3092 JK |
4426 | events->exception.nr = vcpu->arch.exception.nr; |
4427 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
4428 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
4429 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
4430 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 4431 | |
03b82a30 | 4432 | events->interrupt.injected = |
04140b41 | 4433 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 4434 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 4435 | events->interrupt.soft = 0; |
b3646477 | 4436 | events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
3cfc3092 JK |
4437 | |
4438 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 4439 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
b3646477 | 4440 | events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); |
97e69aa6 | 4441 | events->nmi.pad = 0; |
3cfc3092 | 4442 | |
66450a21 | 4443 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 4444 | |
f077825a PB |
4445 | events->smi.smm = is_smm(vcpu); |
4446 | events->smi.pending = vcpu->arch.smi_pending; | |
4447 | events->smi.smm_inside_nmi = | |
4448 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
4449 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
4450 | ||
dab4b911 | 4451 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
4452 | | KVM_VCPUEVENT_VALID_SHADOW |
4453 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
4454 | if (vcpu->kvm->arch.exception_payload_enabled) |
4455 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
4456 | ||
97e69aa6 | 4457 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
4458 | } |
4459 | ||
c5833c7a | 4460 | static void kvm_smm_changed(struct kvm_vcpu *vcpu); |
6ef4e07e | 4461 | |
3cfc3092 JK |
4462 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
4463 | struct kvm_vcpu_events *events) | |
4464 | { | |
dab4b911 | 4465 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 4466 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 4467 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf JM |
4468 | | KVM_VCPUEVENT_VALID_SMM |
4469 | | KVM_VCPUEVENT_VALID_PAYLOAD)) | |
3cfc3092 JK |
4470 | return -EINVAL; |
4471 | ||
59073aaf JM |
4472 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
4473 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4474 | return -EINVAL; | |
4475 | if (events->exception.pending) | |
4476 | events->exception.injected = 0; | |
4477 | else | |
4478 | events->exception_has_payload = 0; | |
4479 | } else { | |
4480 | events->exception.pending = 0; | |
4481 | events->exception_has_payload = 0; | |
4482 | } | |
4483 | ||
4484 | if ((events->exception.injected || events->exception.pending) && | |
4485 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
4486 | return -EINVAL; |
4487 | ||
28bf2888 DH |
4488 | /* INITs are latched while in SMM */ |
4489 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
4490 | (events->smi.smm || events->smi.pending) && | |
4491 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
4492 | return -EINVAL; | |
4493 | ||
7460fb4a | 4494 | process_nmi(vcpu); |
59073aaf JM |
4495 | vcpu->arch.exception.injected = events->exception.injected; |
4496 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
4497 | vcpu->arch.exception.nr = events->exception.nr; |
4498 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
4499 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
4500 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
4501 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 4502 | |
04140b41 | 4503 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
4504 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
4505 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 | 4506 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
b3646477 JB |
4507 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, |
4508 | events->interrupt.shadow); | |
3cfc3092 JK |
4509 | |
4510 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
4511 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
4512 | vcpu->arch.nmi_pending = events->nmi.pending; | |
b3646477 | 4513 | static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); |
3cfc3092 | 4514 | |
66450a21 | 4515 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 4516 | lapic_in_kernel(vcpu)) |
66450a21 | 4517 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 4518 | |
f077825a | 4519 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
c5833c7a SC |
4520 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { |
4521 | if (events->smi.smm) | |
4522 | vcpu->arch.hflags |= HF_SMM_MASK; | |
4523 | else | |
4524 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
4525 | kvm_smm_changed(vcpu); | |
4526 | } | |
6ef4e07e | 4527 | |
f077825a | 4528 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
4529 | |
4530 | if (events->smi.smm) { | |
4531 | if (events->smi.smm_inside_nmi) | |
4532 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 4533 | else |
f4ef1910 | 4534 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
4535 | } |
4536 | ||
4537 | if (lapic_in_kernel(vcpu)) { | |
4538 | if (events->smi.latched_init) | |
4539 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
4540 | else | |
4541 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
4542 | } |
4543 | } | |
4544 | ||
3842d135 AK |
4545 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
4546 | ||
3cfc3092 JK |
4547 | return 0; |
4548 | } | |
4549 | ||
a1efbe77 JK |
4550 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
4551 | struct kvm_debugregs *dbgregs) | |
4552 | { | |
73aaf249 JK |
4553 | unsigned long val; |
4554 | ||
a1efbe77 | 4555 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 4556 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 4557 | dbgregs->dr6 = val; |
a1efbe77 JK |
4558 | dbgregs->dr7 = vcpu->arch.dr7; |
4559 | dbgregs->flags = 0; | |
97e69aa6 | 4560 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
4561 | } |
4562 | ||
4563 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
4564 | struct kvm_debugregs *dbgregs) | |
4565 | { | |
4566 | if (dbgregs->flags) | |
4567 | return -EINVAL; | |
4568 | ||
fd238002 | 4569 | if (!kvm_dr6_valid(dbgregs->dr6)) |
d14bdb55 | 4570 | return -EINVAL; |
fd238002 | 4571 | if (!kvm_dr7_valid(dbgregs->dr7)) |
d14bdb55 PB |
4572 | return -EINVAL; |
4573 | ||
a1efbe77 | 4574 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 4575 | kvm_update_dr0123(vcpu); |
a1efbe77 JK |
4576 | vcpu->arch.dr6 = dbgregs->dr6; |
4577 | vcpu->arch.dr7 = dbgregs->dr7; | |
9926c9fd | 4578 | kvm_update_dr7(vcpu); |
a1efbe77 | 4579 | |
a1efbe77 JK |
4580 | return 0; |
4581 | } | |
4582 | ||
df1daba7 PB |
4583 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
4584 | ||
4585 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
4586 | { | |
b666a4b6 | 4587 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
400e4b20 | 4588 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
4589 | u64 valid; |
4590 | ||
4591 | /* | |
4592 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4593 | * leaves 0 and 1 in the loop below. | |
4594 | */ | |
4595 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
4596 | ||
4597 | /* Set XSTATE_BV */ | |
00c87e9a | 4598 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
4599 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
4600 | ||
4601 | /* | |
4602 | * Copy each region from the possibly compacted offset to the | |
4603 | * non-compacted offset. | |
4604 | */ | |
d91cab78 | 4605 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4606 | while (valid) { |
71ef4533 | 4607 | u32 size, offset, ecx, edx; |
abd16d68 SAS |
4608 | u64 xfeature_mask = valid & -valid; |
4609 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
71ef4533 DH |
4610 | void *src; |
4611 | ||
4612 | cpuid_count(XSTATE_CPUID, xfeature_nr, | |
4613 | &size, &offset, &ecx, &edx); | |
38cfd5e3 | 4614 | |
71ef4533 DH |
4615 | if (xfeature_nr == XFEATURE_PKRU) { |
4616 | memcpy(dest + offset, &vcpu->arch.pkru, | |
4617 | sizeof(vcpu->arch.pkru)); | |
4618 | } else { | |
4619 | src = get_xsave_addr(xsave, xfeature_nr); | |
4620 | if (src) | |
4621 | memcpy(dest + offset, src, size); | |
df1daba7 PB |
4622 | } |
4623 | ||
abd16d68 | 4624 | valid -= xfeature_mask; |
df1daba7 PB |
4625 | } |
4626 | } | |
4627 | ||
4628 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
4629 | { | |
b666a4b6 | 4630 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
df1daba7 PB |
4631 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
4632 | u64 valid; | |
4633 | ||
4634 | /* | |
4635 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4636 | * leaves 0 and 1 in the loop below. | |
4637 | */ | |
4638 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
4639 | ||
4640 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 4641 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 4642 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 4643 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
4644 | |
4645 | /* | |
4646 | * Copy each region from the non-compacted offset to the | |
4647 | * possibly compacted offset. | |
4648 | */ | |
d91cab78 | 4649 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4650 | while (valid) { |
71ef4533 | 4651 | u32 size, offset, ecx, edx; |
abd16d68 SAS |
4652 | u64 xfeature_mask = valid & -valid; |
4653 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
71ef4533 DH |
4654 | |
4655 | cpuid_count(XSTATE_CPUID, xfeature_nr, | |
4656 | &size, &offset, &ecx, &edx); | |
4657 | ||
4658 | if (xfeature_nr == XFEATURE_PKRU) { | |
4659 | memcpy(&vcpu->arch.pkru, src + offset, | |
4660 | sizeof(vcpu->arch.pkru)); | |
4661 | } else { | |
4662 | void *dest = get_xsave_addr(xsave, xfeature_nr); | |
4663 | ||
4664 | if (dest) | |
38cfd5e3 | 4665 | memcpy(dest, src + offset, size); |
ee4100da | 4666 | } |
df1daba7 | 4667 | |
abd16d68 | 4668 | valid -= xfeature_mask; |
df1daba7 PB |
4669 | } |
4670 | } | |
4671 | ||
2d5b5a66 SY |
4672 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
4673 | struct kvm_xsave *guest_xsave) | |
4674 | { | |
ed02b213 TL |
4675 | if (!vcpu->arch.guest_fpu) |
4676 | return; | |
4677 | ||
d366bf7e | 4678 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
4679 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
4680 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 4681 | } else { |
2d5b5a66 | 4682 | memcpy(guest_xsave->region, |
b666a4b6 | 4683 | &vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4684 | sizeof(struct fxregs_state)); |
2d5b5a66 | 4685 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 4686 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
4687 | } |
4688 | } | |
4689 | ||
a575813b WL |
4690 | #define XSAVE_MXCSR_OFFSET 24 |
4691 | ||
2d5b5a66 SY |
4692 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
4693 | struct kvm_xsave *guest_xsave) | |
4694 | { | |
ed02b213 TL |
4695 | u64 xstate_bv; |
4696 | u32 mxcsr; | |
4697 | ||
4698 | if (!vcpu->arch.guest_fpu) | |
4699 | return 0; | |
4700 | ||
4701 | xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
4702 | mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; | |
2d5b5a66 | 4703 | |
d366bf7e | 4704 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
4705 | /* |
4706 | * Here we allow setting states that are not present in | |
4707 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
4708 | * with old userspace. | |
4709 | */ | |
cfc48181 | 4710 | if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) |
d7876f1b | 4711 | return -EINVAL; |
df1daba7 | 4712 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 4713 | } else { |
a575813b WL |
4714 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
4715 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 4716 | return -EINVAL; |
b666a4b6 | 4717 | memcpy(&vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4718 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
4719 | } |
4720 | return 0; | |
4721 | } | |
4722 | ||
4723 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
4724 | struct kvm_xcrs *guest_xcrs) | |
4725 | { | |
d366bf7e | 4726 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
4727 | guest_xcrs->nr_xcrs = 0; |
4728 | return; | |
4729 | } | |
4730 | ||
4731 | guest_xcrs->nr_xcrs = 1; | |
4732 | guest_xcrs->flags = 0; | |
4733 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
4734 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
4735 | } | |
4736 | ||
4737 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
4738 | struct kvm_xcrs *guest_xcrs) | |
4739 | { | |
4740 | int i, r = 0; | |
4741 | ||
d366bf7e | 4742 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
4743 | return -EINVAL; |
4744 | ||
4745 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
4746 | return -EINVAL; | |
4747 | ||
4748 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
4749 | /* Only support XCR0 currently */ | |
c67a04cb | 4750 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 4751 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 4752 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
4753 | break; |
4754 | } | |
4755 | if (r) | |
4756 | r = -EINVAL; | |
4757 | return r; | |
4758 | } | |
4759 | ||
1c0b28c2 EM |
4760 | /* |
4761 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
4762 | * stopped by the hypervisor. This function will be called from the host only. | |
4763 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
4764 | * does not support pv clocks. | |
4765 | */ | |
4766 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
4767 | { | |
0b79459b | 4768 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 4769 | return -EINVAL; |
51d59c6b | 4770 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
4771 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
4772 | return 0; | |
4773 | } | |
4774 | ||
5c919412 AS |
4775 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
4776 | struct kvm_enable_cap *cap) | |
4777 | { | |
57b119da VK |
4778 | int r; |
4779 | uint16_t vmcs_version; | |
4780 | void __user *user_ptr; | |
4781 | ||
5c919412 AS |
4782 | if (cap->flags) |
4783 | return -EINVAL; | |
4784 | ||
4785 | switch (cap->cap) { | |
efc479e6 RK |
4786 | case KVM_CAP_HYPERV_SYNIC2: |
4787 | if (cap->args[0]) | |
4788 | return -EINVAL; | |
df561f66 | 4789 | fallthrough; |
b2869f28 | 4790 | |
5c919412 | 4791 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
4792 | if (!irqchip_in_kernel(vcpu->kvm)) |
4793 | return -EINVAL; | |
efc479e6 RK |
4794 | return kvm_hv_activate_synic(vcpu, cap->cap == |
4795 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 4796 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
33b22172 | 4797 | if (!kvm_x86_ops.nested_ops->enable_evmcs) |
5158917c | 4798 | return -ENOTTY; |
33b22172 | 4799 | r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); |
57b119da VK |
4800 | if (!r) { |
4801 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
4802 | if (copy_to_user(user_ptr, &vmcs_version, | |
4803 | sizeof(vmcs_version))) | |
4804 | r = -EFAULT; | |
4805 | } | |
4806 | return r; | |
344c6c80 | 4807 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4808 | if (!kvm_x86_ops.enable_direct_tlbflush) |
344c6c80 TL |
4809 | return -ENOTTY; |
4810 | ||
b3646477 | 4811 | return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); |
57b119da | 4812 | |
66570e96 OU |
4813 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
4814 | vcpu->arch.pv_cpuid.enforce = cap->args[0]; | |
01b4f510 OU |
4815 | if (vcpu->arch.pv_cpuid.enforce) |
4816 | kvm_update_pv_runtime(vcpu); | |
66570e96 OU |
4817 | |
4818 | return 0; | |
5c919412 AS |
4819 | default: |
4820 | return -EINVAL; | |
4821 | } | |
4822 | } | |
4823 | ||
313a3dc7 CO |
4824 | long kvm_arch_vcpu_ioctl(struct file *filp, |
4825 | unsigned int ioctl, unsigned long arg) | |
4826 | { | |
4827 | struct kvm_vcpu *vcpu = filp->private_data; | |
4828 | void __user *argp = (void __user *)arg; | |
4829 | int r; | |
d1ac91d8 AK |
4830 | union { |
4831 | struct kvm_lapic_state *lapic; | |
4832 | struct kvm_xsave *xsave; | |
4833 | struct kvm_xcrs *xcrs; | |
4834 | void *buffer; | |
4835 | } u; | |
4836 | ||
9b062471 CD |
4837 | vcpu_load(vcpu); |
4838 | ||
d1ac91d8 | 4839 | u.buffer = NULL; |
313a3dc7 CO |
4840 | switch (ioctl) { |
4841 | case KVM_GET_LAPIC: { | |
2204ae3c | 4842 | r = -EINVAL; |
bce87cce | 4843 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4844 | goto out; |
254272ce BG |
4845 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
4846 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 4847 | |
b772ff36 | 4848 | r = -ENOMEM; |
d1ac91d8 | 4849 | if (!u.lapic) |
b772ff36 | 4850 | goto out; |
d1ac91d8 | 4851 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4852 | if (r) |
4853 | goto out; | |
4854 | r = -EFAULT; | |
d1ac91d8 | 4855 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
4856 | goto out; |
4857 | r = 0; | |
4858 | break; | |
4859 | } | |
4860 | case KVM_SET_LAPIC: { | |
2204ae3c | 4861 | r = -EINVAL; |
bce87cce | 4862 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4863 | goto out; |
ff5c2c03 | 4864 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
4865 | if (IS_ERR(u.lapic)) { |
4866 | r = PTR_ERR(u.lapic); | |
4867 | goto out_nofree; | |
4868 | } | |
ff5c2c03 | 4869 | |
d1ac91d8 | 4870 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4871 | break; |
4872 | } | |
f77bc6a4 ZX |
4873 | case KVM_INTERRUPT: { |
4874 | struct kvm_interrupt irq; | |
4875 | ||
4876 | r = -EFAULT; | |
0e96f31e | 4877 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
4878 | goto out; |
4879 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
4880 | break; |
4881 | } | |
c4abb7c9 JK |
4882 | case KVM_NMI: { |
4883 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
4884 | break; |
4885 | } | |
f077825a PB |
4886 | case KVM_SMI: { |
4887 | r = kvm_vcpu_ioctl_smi(vcpu); | |
4888 | break; | |
4889 | } | |
313a3dc7 CO |
4890 | case KVM_SET_CPUID: { |
4891 | struct kvm_cpuid __user *cpuid_arg = argp; | |
4892 | struct kvm_cpuid cpuid; | |
4893 | ||
4894 | r = -EFAULT; | |
0e96f31e | 4895 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
4896 | goto out; |
4897 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
4898 | break; |
4899 | } | |
07716717 DK |
4900 | case KVM_SET_CPUID2: { |
4901 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4902 | struct kvm_cpuid2 cpuid; | |
4903 | ||
4904 | r = -EFAULT; | |
0e96f31e | 4905 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4906 | goto out; |
4907 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 4908 | cpuid_arg->entries); |
07716717 DK |
4909 | break; |
4910 | } | |
4911 | case KVM_GET_CPUID2: { | |
4912 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4913 | struct kvm_cpuid2 cpuid; | |
4914 | ||
4915 | r = -EFAULT; | |
0e96f31e | 4916 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4917 | goto out; |
4918 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 4919 | cpuid_arg->entries); |
07716717 DK |
4920 | if (r) |
4921 | goto out; | |
4922 | r = -EFAULT; | |
0e96f31e | 4923 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
4924 | goto out; |
4925 | r = 0; | |
4926 | break; | |
4927 | } | |
801e459a TL |
4928 | case KVM_GET_MSRS: { |
4929 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 4930 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 4931 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4932 | break; |
801e459a TL |
4933 | } |
4934 | case KVM_SET_MSRS: { | |
4935 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 4936 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 4937 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4938 | break; |
801e459a | 4939 | } |
b209749f AK |
4940 | case KVM_TPR_ACCESS_REPORTING: { |
4941 | struct kvm_tpr_access_ctl tac; | |
4942 | ||
4943 | r = -EFAULT; | |
0e96f31e | 4944 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
4945 | goto out; |
4946 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
4947 | if (r) | |
4948 | goto out; | |
4949 | r = -EFAULT; | |
0e96f31e | 4950 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
4951 | goto out; |
4952 | r = 0; | |
4953 | break; | |
4954 | }; | |
b93463aa AK |
4955 | case KVM_SET_VAPIC_ADDR: { |
4956 | struct kvm_vapic_addr va; | |
7301d6ab | 4957 | int idx; |
b93463aa AK |
4958 | |
4959 | r = -EINVAL; | |
35754c98 | 4960 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
4961 | goto out; |
4962 | r = -EFAULT; | |
0e96f31e | 4963 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 4964 | goto out; |
7301d6ab | 4965 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 4966 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 4967 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
4968 | break; |
4969 | } | |
890ca9ae HY |
4970 | case KVM_X86_SETUP_MCE: { |
4971 | u64 mcg_cap; | |
4972 | ||
4973 | r = -EFAULT; | |
0e96f31e | 4974 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
4975 | goto out; |
4976 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
4977 | break; | |
4978 | } | |
4979 | case KVM_X86_SET_MCE: { | |
4980 | struct kvm_x86_mce mce; | |
4981 | ||
4982 | r = -EFAULT; | |
0e96f31e | 4983 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
4984 | goto out; |
4985 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
4986 | break; | |
4987 | } | |
3cfc3092 JK |
4988 | case KVM_GET_VCPU_EVENTS: { |
4989 | struct kvm_vcpu_events events; | |
4990 | ||
4991 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
4992 | ||
4993 | r = -EFAULT; | |
4994 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
4995 | break; | |
4996 | r = 0; | |
4997 | break; | |
4998 | } | |
4999 | case KVM_SET_VCPU_EVENTS: { | |
5000 | struct kvm_vcpu_events events; | |
5001 | ||
5002 | r = -EFAULT; | |
5003 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
5004 | break; | |
5005 | ||
5006 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
5007 | break; | |
5008 | } | |
a1efbe77 JK |
5009 | case KVM_GET_DEBUGREGS: { |
5010 | struct kvm_debugregs dbgregs; | |
5011 | ||
5012 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
5013 | ||
5014 | r = -EFAULT; | |
5015 | if (copy_to_user(argp, &dbgregs, | |
5016 | sizeof(struct kvm_debugregs))) | |
5017 | break; | |
5018 | r = 0; | |
5019 | break; | |
5020 | } | |
5021 | case KVM_SET_DEBUGREGS: { | |
5022 | struct kvm_debugregs dbgregs; | |
5023 | ||
5024 | r = -EFAULT; | |
5025 | if (copy_from_user(&dbgregs, argp, | |
5026 | sizeof(struct kvm_debugregs))) | |
5027 | break; | |
5028 | ||
5029 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
5030 | break; | |
5031 | } | |
2d5b5a66 | 5032 | case KVM_GET_XSAVE: { |
254272ce | 5033 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5034 | r = -ENOMEM; |
d1ac91d8 | 5035 | if (!u.xsave) |
2d5b5a66 SY |
5036 | break; |
5037 | ||
d1ac91d8 | 5038 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5039 | |
5040 | r = -EFAULT; | |
d1ac91d8 | 5041 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
5042 | break; |
5043 | r = 0; | |
5044 | break; | |
5045 | } | |
5046 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 5047 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
5048 | if (IS_ERR(u.xsave)) { |
5049 | r = PTR_ERR(u.xsave); | |
5050 | goto out_nofree; | |
5051 | } | |
2d5b5a66 | 5052 | |
d1ac91d8 | 5053 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5054 | break; |
5055 | } | |
5056 | case KVM_GET_XCRS: { | |
254272ce | 5057 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5058 | r = -ENOMEM; |
d1ac91d8 | 5059 | if (!u.xcrs) |
2d5b5a66 SY |
5060 | break; |
5061 | ||
d1ac91d8 | 5062 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5063 | |
5064 | r = -EFAULT; | |
d1ac91d8 | 5065 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
5066 | sizeof(struct kvm_xcrs))) |
5067 | break; | |
5068 | r = 0; | |
5069 | break; | |
5070 | } | |
5071 | case KVM_SET_XCRS: { | |
ff5c2c03 | 5072 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
5073 | if (IS_ERR(u.xcrs)) { |
5074 | r = PTR_ERR(u.xcrs); | |
5075 | goto out_nofree; | |
5076 | } | |
2d5b5a66 | 5077 | |
d1ac91d8 | 5078 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5079 | break; |
5080 | } | |
92a1f12d JR |
5081 | case KVM_SET_TSC_KHZ: { |
5082 | u32 user_tsc_khz; | |
5083 | ||
5084 | r = -EINVAL; | |
92a1f12d JR |
5085 | user_tsc_khz = (u32)arg; |
5086 | ||
26769f96 MT |
5087 | if (kvm_has_tsc_control && |
5088 | user_tsc_khz >= kvm_max_guest_tsc_khz) | |
92a1f12d JR |
5089 | goto out; |
5090 | ||
cc578287 ZA |
5091 | if (user_tsc_khz == 0) |
5092 | user_tsc_khz = tsc_khz; | |
5093 | ||
381d585c HZ |
5094 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
5095 | r = 0; | |
92a1f12d | 5096 | |
92a1f12d JR |
5097 | goto out; |
5098 | } | |
5099 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 5100 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
5101 | goto out; |
5102 | } | |
1c0b28c2 EM |
5103 | case KVM_KVMCLOCK_CTRL: { |
5104 | r = kvm_set_guest_paused(vcpu); | |
5105 | goto out; | |
5106 | } | |
5c919412 AS |
5107 | case KVM_ENABLE_CAP: { |
5108 | struct kvm_enable_cap cap; | |
5109 | ||
5110 | r = -EFAULT; | |
5111 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
5112 | goto out; | |
5113 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
5114 | break; | |
5115 | } | |
8fcc4b59 JM |
5116 | case KVM_GET_NESTED_STATE: { |
5117 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5118 | u32 user_data_size; | |
5119 | ||
5120 | r = -EINVAL; | |
33b22172 | 5121 | if (!kvm_x86_ops.nested_ops->get_state) |
8fcc4b59 JM |
5122 | break; |
5123 | ||
5124 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 5125 | r = -EFAULT; |
8fcc4b59 | 5126 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 5127 | break; |
8fcc4b59 | 5128 | |
33b22172 PB |
5129 | r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, |
5130 | user_data_size); | |
8fcc4b59 | 5131 | if (r < 0) |
26b471c7 | 5132 | break; |
8fcc4b59 JM |
5133 | |
5134 | if (r > user_data_size) { | |
5135 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
5136 | r = -EFAULT; |
5137 | else | |
5138 | r = -E2BIG; | |
5139 | break; | |
8fcc4b59 | 5140 | } |
26b471c7 | 5141 | |
8fcc4b59 JM |
5142 | r = 0; |
5143 | break; | |
5144 | } | |
5145 | case KVM_SET_NESTED_STATE: { | |
5146 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5147 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 5148 | int idx; |
8fcc4b59 JM |
5149 | |
5150 | r = -EINVAL; | |
33b22172 | 5151 | if (!kvm_x86_ops.nested_ops->set_state) |
8fcc4b59 JM |
5152 | break; |
5153 | ||
26b471c7 | 5154 | r = -EFAULT; |
8fcc4b59 | 5155 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 5156 | break; |
8fcc4b59 | 5157 | |
26b471c7 | 5158 | r = -EINVAL; |
8fcc4b59 | 5159 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 5160 | break; |
8fcc4b59 JM |
5161 | |
5162 | if (kvm_state.flags & | |
8cab6507 | 5163 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
cc440cda PB |
5164 | | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING |
5165 | | KVM_STATE_NESTED_GIF_SET)) | |
26b471c7 | 5166 | break; |
8fcc4b59 JM |
5167 | |
5168 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
5169 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
5170 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 5171 | break; |
8fcc4b59 | 5172 | |
ad5996d9 | 5173 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
33b22172 | 5174 | r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 5175 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
5176 | break; |
5177 | } | |
c21d54f0 VK |
5178 | case KVM_GET_SUPPORTED_HV_CPUID: |
5179 | r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); | |
2bc39970 | 5180 | break; |
b59b153d | 5181 | #ifdef CONFIG_KVM_XEN |
3e324615 DW |
5182 | case KVM_XEN_VCPU_GET_ATTR: { |
5183 | struct kvm_xen_vcpu_attr xva; | |
5184 | ||
5185 | r = -EFAULT; | |
5186 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
5187 | goto out; | |
5188 | r = kvm_xen_vcpu_get_attr(vcpu, &xva); | |
5189 | if (!r && copy_to_user(argp, &xva, sizeof(xva))) | |
5190 | r = -EFAULT; | |
5191 | break; | |
5192 | } | |
5193 | case KVM_XEN_VCPU_SET_ATTR: { | |
5194 | struct kvm_xen_vcpu_attr xva; | |
5195 | ||
5196 | r = -EFAULT; | |
5197 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
5198 | goto out; | |
5199 | r = kvm_xen_vcpu_set_attr(vcpu, &xva); | |
5200 | break; | |
5201 | } | |
b59b153d | 5202 | #endif |
313a3dc7 CO |
5203 | default: |
5204 | r = -EINVAL; | |
5205 | } | |
5206 | out: | |
d1ac91d8 | 5207 | kfree(u.buffer); |
9b062471 CD |
5208 | out_nofree: |
5209 | vcpu_put(vcpu); | |
313a3dc7 CO |
5210 | return r; |
5211 | } | |
5212 | ||
1499fa80 | 5213 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
5214 | { |
5215 | return VM_FAULT_SIGBUS; | |
5216 | } | |
5217 | ||
1fe779f8 CO |
5218 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
5219 | { | |
5220 | int ret; | |
5221 | ||
5222 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 5223 | return -EINVAL; |
b3646477 | 5224 | ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); |
1fe779f8 CO |
5225 | return ret; |
5226 | } | |
5227 | ||
b927a3ce SY |
5228 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
5229 | u64 ident_addr) | |
5230 | { | |
b3646477 | 5231 | return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); |
b927a3ce SY |
5232 | } |
5233 | ||
1fe779f8 | 5234 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 5235 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
5236 | { |
5237 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
5238 | return -EINVAL; | |
5239 | ||
79fac95e | 5240 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
5241 | |
5242 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 5243 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 5244 | |
79fac95e | 5245 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
5246 | return 0; |
5247 | } | |
5248 | ||
bc8a3d89 | 5249 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 5250 | { |
39de71ec | 5251 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
5252 | } |
5253 | ||
1fe779f8 CO |
5254 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
5255 | { | |
90bca052 | 5256 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5257 | int r; |
5258 | ||
5259 | r = 0; | |
5260 | switch (chip->chip_id) { | |
5261 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 5262 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
5263 | sizeof(struct kvm_pic_state)); |
5264 | break; | |
5265 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 5266 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
5267 | sizeof(struct kvm_pic_state)); |
5268 | break; | |
5269 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5270 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5271 | break; |
5272 | default: | |
5273 | r = -EINVAL; | |
5274 | break; | |
5275 | } | |
5276 | return r; | |
5277 | } | |
5278 | ||
5279 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
5280 | { | |
90bca052 | 5281 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5282 | int r; |
5283 | ||
5284 | r = 0; | |
5285 | switch (chip->chip_id) { | |
5286 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
5287 | spin_lock(&pic->lock); |
5288 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 5289 | sizeof(struct kvm_pic_state)); |
90bca052 | 5290 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5291 | break; |
5292 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
5293 | spin_lock(&pic->lock); |
5294 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 5295 | sizeof(struct kvm_pic_state)); |
90bca052 | 5296 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5297 | break; |
5298 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5299 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5300 | break; |
5301 | default: | |
5302 | r = -EINVAL; | |
5303 | break; | |
5304 | } | |
90bca052 | 5305 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
5306 | return r; |
5307 | } | |
5308 | ||
e0f63cb9 SY |
5309 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
5310 | { | |
34f3941c RK |
5311 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
5312 | ||
5313 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
5314 | ||
5315 | mutex_lock(&kps->lock); | |
5316 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
5317 | mutex_unlock(&kps->lock); | |
2da29bcc | 5318 | return 0; |
e0f63cb9 SY |
5319 | } |
5320 | ||
5321 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
5322 | { | |
0185604c | 5323 | int i; |
09edea72 RK |
5324 | struct kvm_pit *pit = kvm->arch.vpit; |
5325 | ||
5326 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 5327 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 5328 | for (i = 0; i < 3; i++) |
09edea72 RK |
5329 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
5330 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 5331 | return 0; |
e9f42757 BK |
5332 | } |
5333 | ||
5334 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5335 | { | |
e9f42757 BK |
5336 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
5337 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
5338 | sizeof(ps->channels)); | |
5339 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
5340 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 5341 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 5342 | return 0; |
e9f42757 BK |
5343 | } |
5344 | ||
5345 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5346 | { | |
2da29bcc | 5347 | int start = 0; |
0185604c | 5348 | int i; |
e9f42757 | 5349 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
5350 | struct kvm_pit *pit = kvm->arch.vpit; |
5351 | ||
5352 | mutex_lock(&pit->pit_state.lock); | |
5353 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
5354 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
5355 | if (!prev_legacy && cur_legacy) | |
5356 | start = 1; | |
09edea72 RK |
5357 | memcpy(&pit->pit_state.channels, &ps->channels, |
5358 | sizeof(pit->pit_state.channels)); | |
5359 | pit->pit_state.flags = ps->flags; | |
0185604c | 5360 | for (i = 0; i < 3; i++) |
09edea72 | 5361 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 5362 | start && i == 0); |
09edea72 | 5363 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 5364 | return 0; |
e0f63cb9 SY |
5365 | } |
5366 | ||
52d939a0 MT |
5367 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
5368 | struct kvm_reinject_control *control) | |
5369 | { | |
71474e2f RK |
5370 | struct kvm_pit *pit = kvm->arch.vpit; |
5371 | ||
71474e2f RK |
5372 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
5373 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
5374 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
5375 | */ | |
5376 | mutex_lock(&pit->pit_state.lock); | |
5377 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
5378 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 5379 | |
52d939a0 MT |
5380 | return 0; |
5381 | } | |
5382 | ||
0dff0846 | 5383 | void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) |
5bb064dc | 5384 | { |
a018eba5 | 5385 | |
88178fd4 | 5386 | /* |
a018eba5 SC |
5387 | * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called |
5388 | * before reporting dirty_bitmap to userspace. KVM flushes the buffers | |
5389 | * on all VM-Exits, thus we only need to kick running vCPUs to force a | |
5390 | * VM-Exit. | |
88178fd4 | 5391 | */ |
a018eba5 SC |
5392 | struct kvm_vcpu *vcpu; |
5393 | int i; | |
5394 | ||
5395 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5396 | kvm_vcpu_kick(vcpu); | |
5bb064dc ZX |
5397 | } |
5398 | ||
aa2fbe6d YZ |
5399 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
5400 | bool line_status) | |
23d43cf9 CD |
5401 | { |
5402 | if (!irqchip_in_kernel(kvm)) | |
5403 | return -ENXIO; | |
5404 | ||
5405 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
5406 | irq_event->irq, irq_event->level, |
5407 | line_status); | |
23d43cf9 CD |
5408 | return 0; |
5409 | } | |
5410 | ||
e5d83c74 PB |
5411 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
5412 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
5413 | { |
5414 | int r; | |
5415 | ||
5416 | if (cap->flags) | |
5417 | return -EINVAL; | |
5418 | ||
5419 | switch (cap->cap) { | |
5420 | case KVM_CAP_DISABLE_QUIRKS: | |
5421 | kvm->arch.disabled_quirks = cap->args[0]; | |
5422 | r = 0; | |
5423 | break; | |
49df6397 SR |
5424 | case KVM_CAP_SPLIT_IRQCHIP: { |
5425 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
5426 | r = -EINVAL; |
5427 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
5428 | goto split_irqchip_unlock; | |
49df6397 SR |
5429 | r = -EEXIST; |
5430 | if (irqchip_in_kernel(kvm)) | |
5431 | goto split_irqchip_unlock; | |
557abc40 | 5432 | if (kvm->created_vcpus) |
49df6397 SR |
5433 | goto split_irqchip_unlock; |
5434 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 5435 | if (r) |
49df6397 SR |
5436 | goto split_irqchip_unlock; |
5437 | /* Pairs with irqchip_in_kernel. */ | |
5438 | smp_wmb(); | |
49776faf | 5439 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 5440 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
5441 | r = 0; |
5442 | split_irqchip_unlock: | |
5443 | mutex_unlock(&kvm->lock); | |
5444 | break; | |
5445 | } | |
37131313 RK |
5446 | case KVM_CAP_X2APIC_API: |
5447 | r = -EINVAL; | |
5448 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
5449 | break; | |
5450 | ||
5451 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
5452 | kvm->arch.x2apic_format = true; | |
c519265f RK |
5453 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
5454 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
5455 | |
5456 | r = 0; | |
5457 | break; | |
4d5422ce WL |
5458 | case KVM_CAP_X86_DISABLE_EXITS: |
5459 | r = -EINVAL; | |
5460 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
5461 | break; | |
5462 | ||
5463 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
5464 | kvm_can_mwait_in_guest()) | |
5465 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 5466 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 5467 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
5468 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
5469 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
5470 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
5471 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
5472 | r = 0; |
5473 | break; | |
6fbbde9a DS |
5474 | case KVM_CAP_MSR_PLATFORM_INFO: |
5475 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
5476 | r = 0; | |
c4f55198 JM |
5477 | break; |
5478 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
5479 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
5480 | r = 0; | |
6fbbde9a | 5481 | break; |
1ae09954 AG |
5482 | case KVM_CAP_X86_USER_SPACE_MSR: |
5483 | kvm->arch.user_space_msr_mask = cap->args[0]; | |
5484 | r = 0; | |
5485 | break; | |
fe6b6bc8 CQ |
5486 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
5487 | r = -EINVAL; | |
5488 | if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) | |
5489 | break; | |
5490 | ||
5491 | if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && | |
5492 | (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) | |
5493 | break; | |
5494 | ||
5495 | if (kvm_has_bus_lock_exit && | |
5496 | cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) | |
5497 | kvm->arch.bus_lock_detection_enabled = true; | |
5498 | r = 0; | |
5499 | break; | |
fe7e9488 SC |
5500 | #ifdef CONFIG_X86_SGX_KVM |
5501 | case KVM_CAP_SGX_ATTRIBUTE: { | |
5502 | unsigned long allowed_attributes = 0; | |
5503 | ||
5504 | r = sgx_set_attribute(&allowed_attributes, cap->args[0]); | |
5505 | if (r) | |
5506 | break; | |
5507 | ||
5508 | /* KVM only supports the PROVISIONKEY privileged attribute. */ | |
5509 | if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && | |
5510 | !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) | |
5511 | kvm->arch.sgx_provisioning_allowed = true; | |
5512 | else | |
5513 | r = -EINVAL; | |
5514 | break; | |
5515 | } | |
5516 | #endif | |
54526d1f NT |
5517 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
5518 | r = -EINVAL; | |
5519 | if (kvm_x86_ops.vm_copy_enc_context_from) | |
5520 | r = kvm_x86_ops.vm_copy_enc_context_from(kvm, cap->args[0]); | |
5521 | return r; | |
90de4a18 NA |
5522 | default: |
5523 | r = -EINVAL; | |
5524 | break; | |
5525 | } | |
5526 | return r; | |
5527 | } | |
5528 | ||
b318e8de SC |
5529 | static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) |
5530 | { | |
5531 | struct kvm_x86_msr_filter *msr_filter; | |
5532 | ||
5533 | msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); | |
5534 | if (!msr_filter) | |
5535 | return NULL; | |
5536 | ||
5537 | msr_filter->default_allow = default_allow; | |
5538 | return msr_filter; | |
5539 | } | |
5540 | ||
5541 | static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) | |
1a155254 AG |
5542 | { |
5543 | u32 i; | |
1a155254 | 5544 | |
b318e8de SC |
5545 | if (!msr_filter) |
5546 | return; | |
5547 | ||
5548 | for (i = 0; i < msr_filter->count; i++) | |
5549 | kfree(msr_filter->ranges[i].bitmap); | |
1a155254 | 5550 | |
b318e8de | 5551 | kfree(msr_filter); |
1a155254 AG |
5552 | } |
5553 | ||
b318e8de SC |
5554 | static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, |
5555 | struct kvm_msr_filter_range *user_range) | |
1a155254 | 5556 | { |
1a155254 AG |
5557 | unsigned long *bitmap = NULL; |
5558 | size_t bitmap_size; | |
1a155254 AG |
5559 | |
5560 | if (!user_range->nmsrs) | |
5561 | return 0; | |
5562 | ||
aca35288 SC |
5563 | if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) |
5564 | return -EINVAL; | |
5565 | ||
5566 | if (!user_range->flags) | |
5567 | return -EINVAL; | |
5568 | ||
1a155254 AG |
5569 | bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); |
5570 | if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) | |
5571 | return -EINVAL; | |
5572 | ||
5573 | bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); | |
5574 | if (IS_ERR(bitmap)) | |
5575 | return PTR_ERR(bitmap); | |
5576 | ||
aca35288 | 5577 | msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { |
1a155254 AG |
5578 | .flags = user_range->flags, |
5579 | .base = user_range->base, | |
5580 | .nmsrs = user_range->nmsrs, | |
5581 | .bitmap = bitmap, | |
5582 | }; | |
5583 | ||
b318e8de | 5584 | msr_filter->count++; |
1a155254 | 5585 | return 0; |
1a155254 AG |
5586 | } |
5587 | ||
5588 | static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) | |
5589 | { | |
5590 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
b318e8de | 5591 | struct kvm_x86_msr_filter *new_filter, *old_filter; |
1a155254 AG |
5592 | struct kvm_msr_filter filter; |
5593 | bool default_allow; | |
043248b3 | 5594 | bool empty = true; |
b318e8de | 5595 | int r = 0; |
1a155254 AG |
5596 | u32 i; |
5597 | ||
5598 | if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) | |
5599 | return -EFAULT; | |
5600 | ||
043248b3 PB |
5601 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) |
5602 | empty &= !filter.ranges[i].nmsrs; | |
1a155254 AG |
5603 | |
5604 | default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); | |
043248b3 PB |
5605 | if (empty && !default_allow) |
5606 | return -EINVAL; | |
5607 | ||
b318e8de SC |
5608 | new_filter = kvm_alloc_msr_filter(default_allow); |
5609 | if (!new_filter) | |
5610 | return -ENOMEM; | |
1a155254 | 5611 | |
1a155254 | 5612 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { |
b318e8de SC |
5613 | r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); |
5614 | if (r) { | |
5615 | kvm_free_msr_filter(new_filter); | |
5616 | return r; | |
5617 | } | |
1a155254 AG |
5618 | } |
5619 | ||
b318e8de SC |
5620 | mutex_lock(&kvm->lock); |
5621 | ||
5622 | /* The per-VM filter is protected by kvm->lock... */ | |
5623 | old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); | |
5624 | ||
5625 | rcu_assign_pointer(kvm->arch.msr_filter, new_filter); | |
5626 | synchronize_srcu(&kvm->srcu); | |
5627 | ||
5628 | kvm_free_msr_filter(old_filter); | |
5629 | ||
1a155254 AG |
5630 | kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); |
5631 | mutex_unlock(&kvm->lock); | |
5632 | ||
b318e8de | 5633 | return 0; |
1a155254 AG |
5634 | } |
5635 | ||
1fe779f8 CO |
5636 | long kvm_arch_vm_ioctl(struct file *filp, |
5637 | unsigned int ioctl, unsigned long arg) | |
5638 | { | |
5639 | struct kvm *kvm = filp->private_data; | |
5640 | void __user *argp = (void __user *)arg; | |
367e1319 | 5641 | int r = -ENOTTY; |
f0d66275 DH |
5642 | /* |
5643 | * This union makes it completely explicit to gcc-3.x | |
5644 | * that these two variables' stack usage should be | |
5645 | * combined, not added together. | |
5646 | */ | |
5647 | union { | |
5648 | struct kvm_pit_state ps; | |
e9f42757 | 5649 | struct kvm_pit_state2 ps2; |
c5ff41ce | 5650 | struct kvm_pit_config pit_config; |
f0d66275 | 5651 | } u; |
1fe779f8 CO |
5652 | |
5653 | switch (ioctl) { | |
5654 | case KVM_SET_TSS_ADDR: | |
5655 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 5656 | break; |
b927a3ce SY |
5657 | case KVM_SET_IDENTITY_MAP_ADDR: { |
5658 | u64 ident_addr; | |
5659 | ||
1af1ac91 DH |
5660 | mutex_lock(&kvm->lock); |
5661 | r = -EINVAL; | |
5662 | if (kvm->created_vcpus) | |
5663 | goto set_identity_unlock; | |
b927a3ce | 5664 | r = -EFAULT; |
0e96f31e | 5665 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 5666 | goto set_identity_unlock; |
b927a3ce | 5667 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
5668 | set_identity_unlock: |
5669 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
5670 | break; |
5671 | } | |
1fe779f8 CO |
5672 | case KVM_SET_NR_MMU_PAGES: |
5673 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
5674 | break; |
5675 | case KVM_GET_NR_MMU_PAGES: | |
5676 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
5677 | break; | |
3ddea128 | 5678 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 5679 | mutex_lock(&kvm->lock); |
09941366 | 5680 | |
3ddea128 | 5681 | r = -EEXIST; |
35e6eaa3 | 5682 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 5683 | goto create_irqchip_unlock; |
09941366 | 5684 | |
3e515705 | 5685 | r = -EINVAL; |
557abc40 | 5686 | if (kvm->created_vcpus) |
3e515705 | 5687 | goto create_irqchip_unlock; |
09941366 RK |
5688 | |
5689 | r = kvm_pic_init(kvm); | |
5690 | if (r) | |
3ddea128 | 5691 | goto create_irqchip_unlock; |
09941366 RK |
5692 | |
5693 | r = kvm_ioapic_init(kvm); | |
5694 | if (r) { | |
09941366 | 5695 | kvm_pic_destroy(kvm); |
3ddea128 | 5696 | goto create_irqchip_unlock; |
09941366 RK |
5697 | } |
5698 | ||
399ec807 AK |
5699 | r = kvm_setup_default_irq_routing(kvm); |
5700 | if (r) { | |
72bb2fcd | 5701 | kvm_ioapic_destroy(kvm); |
09941366 | 5702 | kvm_pic_destroy(kvm); |
71ba994c | 5703 | goto create_irqchip_unlock; |
399ec807 | 5704 | } |
49776faf | 5705 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 5706 | smp_wmb(); |
49776faf | 5707 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
5708 | create_irqchip_unlock: |
5709 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 5710 | break; |
3ddea128 | 5711 | } |
7837699f | 5712 | case KVM_CREATE_PIT: |
c5ff41ce JK |
5713 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
5714 | goto create_pit; | |
5715 | case KVM_CREATE_PIT2: | |
5716 | r = -EFAULT; | |
5717 | if (copy_from_user(&u.pit_config, argp, | |
5718 | sizeof(struct kvm_pit_config))) | |
5719 | goto out; | |
5720 | create_pit: | |
250715a6 | 5721 | mutex_lock(&kvm->lock); |
269e05e4 AK |
5722 | r = -EEXIST; |
5723 | if (kvm->arch.vpit) | |
5724 | goto create_pit_unlock; | |
7837699f | 5725 | r = -ENOMEM; |
c5ff41ce | 5726 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
5727 | if (kvm->arch.vpit) |
5728 | r = 0; | |
269e05e4 | 5729 | create_pit_unlock: |
250715a6 | 5730 | mutex_unlock(&kvm->lock); |
7837699f | 5731 | break; |
1fe779f8 CO |
5732 | case KVM_GET_IRQCHIP: { |
5733 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5734 | struct kvm_irqchip *chip; |
1fe779f8 | 5735 | |
ff5c2c03 SL |
5736 | chip = memdup_user(argp, sizeof(*chip)); |
5737 | if (IS_ERR(chip)) { | |
5738 | r = PTR_ERR(chip); | |
1fe779f8 | 5739 | goto out; |
ff5c2c03 SL |
5740 | } |
5741 | ||
1fe779f8 | 5742 | r = -ENXIO; |
826da321 | 5743 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5744 | goto get_irqchip_out; |
5745 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 5746 | if (r) |
f0d66275 | 5747 | goto get_irqchip_out; |
1fe779f8 | 5748 | r = -EFAULT; |
0e96f31e | 5749 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 5750 | goto get_irqchip_out; |
1fe779f8 | 5751 | r = 0; |
f0d66275 DH |
5752 | get_irqchip_out: |
5753 | kfree(chip); | |
1fe779f8 CO |
5754 | break; |
5755 | } | |
5756 | case KVM_SET_IRQCHIP: { | |
5757 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5758 | struct kvm_irqchip *chip; |
1fe779f8 | 5759 | |
ff5c2c03 SL |
5760 | chip = memdup_user(argp, sizeof(*chip)); |
5761 | if (IS_ERR(chip)) { | |
5762 | r = PTR_ERR(chip); | |
1fe779f8 | 5763 | goto out; |
ff5c2c03 SL |
5764 | } |
5765 | ||
1fe779f8 | 5766 | r = -ENXIO; |
826da321 | 5767 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5768 | goto set_irqchip_out; |
5769 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
5770 | set_irqchip_out: |
5771 | kfree(chip); | |
1fe779f8 CO |
5772 | break; |
5773 | } | |
e0f63cb9 | 5774 | case KVM_GET_PIT: { |
e0f63cb9 | 5775 | r = -EFAULT; |
f0d66275 | 5776 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5777 | goto out; |
5778 | r = -ENXIO; | |
5779 | if (!kvm->arch.vpit) | |
5780 | goto out; | |
f0d66275 | 5781 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
5782 | if (r) |
5783 | goto out; | |
5784 | r = -EFAULT; | |
f0d66275 | 5785 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5786 | goto out; |
5787 | r = 0; | |
5788 | break; | |
5789 | } | |
5790 | case KVM_SET_PIT: { | |
e0f63cb9 | 5791 | r = -EFAULT; |
0e96f31e | 5792 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 | 5793 | goto out; |
7289fdb5 | 5794 | mutex_lock(&kvm->lock); |
e0f63cb9 SY |
5795 | r = -ENXIO; |
5796 | if (!kvm->arch.vpit) | |
7289fdb5 | 5797 | goto set_pit_out; |
f0d66275 | 5798 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
7289fdb5 SR |
5799 | set_pit_out: |
5800 | mutex_unlock(&kvm->lock); | |
e0f63cb9 SY |
5801 | break; |
5802 | } | |
e9f42757 BK |
5803 | case KVM_GET_PIT2: { |
5804 | r = -ENXIO; | |
5805 | if (!kvm->arch.vpit) | |
5806 | goto out; | |
5807 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
5808 | if (r) | |
5809 | goto out; | |
5810 | r = -EFAULT; | |
5811 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
5812 | goto out; | |
5813 | r = 0; | |
5814 | break; | |
5815 | } | |
5816 | case KVM_SET_PIT2: { | |
5817 | r = -EFAULT; | |
5818 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
5819 | goto out; | |
7289fdb5 | 5820 | mutex_lock(&kvm->lock); |
e9f42757 BK |
5821 | r = -ENXIO; |
5822 | if (!kvm->arch.vpit) | |
7289fdb5 | 5823 | goto set_pit2_out; |
e9f42757 | 5824 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); |
7289fdb5 SR |
5825 | set_pit2_out: |
5826 | mutex_unlock(&kvm->lock); | |
e9f42757 BK |
5827 | break; |
5828 | } | |
52d939a0 MT |
5829 | case KVM_REINJECT_CONTROL: { |
5830 | struct kvm_reinject_control control; | |
5831 | r = -EFAULT; | |
5832 | if (copy_from_user(&control, argp, sizeof(control))) | |
5833 | goto out; | |
cad23e72 ML |
5834 | r = -ENXIO; |
5835 | if (!kvm->arch.vpit) | |
5836 | goto out; | |
52d939a0 | 5837 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
5838 | break; |
5839 | } | |
d71ba788 PB |
5840 | case KVM_SET_BOOT_CPU_ID: |
5841 | r = 0; | |
5842 | mutex_lock(&kvm->lock); | |
557abc40 | 5843 | if (kvm->created_vcpus) |
d71ba788 PB |
5844 | r = -EBUSY; |
5845 | else | |
5846 | kvm->arch.bsp_vcpu_id = arg; | |
5847 | mutex_unlock(&kvm->lock); | |
5848 | break; | |
b59b153d | 5849 | #ifdef CONFIG_KVM_XEN |
ffde22ac | 5850 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 5851 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 5852 | r = -EFAULT; |
51776043 | 5853 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac | 5854 | goto out; |
78e9878c | 5855 | r = kvm_xen_hvm_config(kvm, &xhc); |
ffde22ac ES |
5856 | break; |
5857 | } | |
a76b9641 JM |
5858 | case KVM_XEN_HVM_GET_ATTR: { |
5859 | struct kvm_xen_hvm_attr xha; | |
5860 | ||
5861 | r = -EFAULT; | |
5862 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
ffde22ac | 5863 | goto out; |
a76b9641 JM |
5864 | r = kvm_xen_hvm_get_attr(kvm, &xha); |
5865 | if (!r && copy_to_user(argp, &xha, sizeof(xha))) | |
5866 | r = -EFAULT; | |
5867 | break; | |
5868 | } | |
5869 | case KVM_XEN_HVM_SET_ATTR: { | |
5870 | struct kvm_xen_hvm_attr xha; | |
5871 | ||
5872 | r = -EFAULT; | |
5873 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
5874 | goto out; | |
5875 | r = kvm_xen_hvm_set_attr(kvm, &xha); | |
ffde22ac ES |
5876 | break; |
5877 | } | |
b59b153d | 5878 | #endif |
afbcf7ab | 5879 | case KVM_SET_CLOCK: { |
77fcbe82 | 5880 | struct kvm_arch *ka = &kvm->arch; |
afbcf7ab GC |
5881 | struct kvm_clock_data user_ns; |
5882 | u64 now_ns; | |
afbcf7ab GC |
5883 | |
5884 | r = -EFAULT; | |
5885 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
5886 | goto out; | |
5887 | ||
5888 | r = -EINVAL; | |
5889 | if (user_ns.flags) | |
5890 | goto out; | |
5891 | ||
5892 | r = 0; | |
0bc48bea RK |
5893 | /* |
5894 | * TODO: userspace has to take care of races with VCPU_RUN, so | |
5895 | * kvm_gen_update_masterclock() can be cut down to locked | |
5896 | * pvclock_update_vm_gtod_copy(). | |
5897 | */ | |
5898 | kvm_gen_update_masterclock(kvm); | |
77fcbe82 VK |
5899 | |
5900 | /* | |
5901 | * This pairs with kvm_guest_time_update(): when masterclock is | |
5902 | * in use, we use master_kernel_ns + kvmclock_offset to set | |
5903 | * unsigned 'system_time' so if we use get_kvmclock_ns() (which | |
5904 | * is slightly ahead) here we risk going negative on unsigned | |
5905 | * 'system_time' when 'user_ns.clock' is very small. | |
5906 | */ | |
5907 | spin_lock_irq(&ka->pvclock_gtod_sync_lock); | |
5908 | if (kvm->arch.use_master_clock) | |
5909 | now_ns = ka->master_kernel_ns; | |
5910 | else | |
5911 | now_ns = get_kvmclock_base_ns(); | |
5912 | ka->kvmclock_offset = user_ns.clock - now_ns; | |
5913 | spin_unlock_irq(&ka->pvclock_gtod_sync_lock); | |
5914 | ||
0bc48bea | 5915 | kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); |
afbcf7ab GC |
5916 | break; |
5917 | } | |
5918 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
5919 | struct kvm_clock_data user_ns; |
5920 | u64 now_ns; | |
5921 | ||
e891a32e | 5922 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5923 | user_ns.clock = now_ns; |
e3fd9a93 | 5924 | user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; |
97e69aa6 | 5925 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
5926 | |
5927 | r = -EFAULT; | |
5928 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
5929 | goto out; | |
5930 | r = 0; | |
5931 | break; | |
5932 | } | |
5acc5c06 BS |
5933 | case KVM_MEMORY_ENCRYPT_OP: { |
5934 | r = -ENOTTY; | |
afaf0b2f | 5935 | if (kvm_x86_ops.mem_enc_op) |
b3646477 | 5936 | r = static_call(kvm_x86_mem_enc_op)(kvm, argp); |
5acc5c06 BS |
5937 | break; |
5938 | } | |
69eaedee BS |
5939 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
5940 | struct kvm_enc_region region; | |
5941 | ||
5942 | r = -EFAULT; | |
5943 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5944 | goto out; | |
5945 | ||
5946 | r = -ENOTTY; | |
afaf0b2f | 5947 | if (kvm_x86_ops.mem_enc_reg_region) |
b3646477 | 5948 | r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); |
69eaedee BS |
5949 | break; |
5950 | } | |
5951 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
5952 | struct kvm_enc_region region; | |
5953 | ||
5954 | r = -EFAULT; | |
5955 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5956 | goto out; | |
5957 | ||
5958 | r = -ENOTTY; | |
afaf0b2f | 5959 | if (kvm_x86_ops.mem_enc_unreg_region) |
b3646477 | 5960 | r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); |
69eaedee BS |
5961 | break; |
5962 | } | |
faeb7833 RK |
5963 | case KVM_HYPERV_EVENTFD: { |
5964 | struct kvm_hyperv_eventfd hvevfd; | |
5965 | ||
5966 | r = -EFAULT; | |
5967 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
5968 | goto out; | |
5969 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
5970 | break; | |
5971 | } | |
66bb8a06 EH |
5972 | case KVM_SET_PMU_EVENT_FILTER: |
5973 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
5974 | break; | |
1a155254 AG |
5975 | case KVM_X86_SET_MSR_FILTER: |
5976 | r = kvm_vm_ioctl_set_msr_filter(kvm, argp); | |
5977 | break; | |
1fe779f8 | 5978 | default: |
ad6260da | 5979 | r = -ENOTTY; |
1fe779f8 CO |
5980 | } |
5981 | out: | |
5982 | return r; | |
5983 | } | |
5984 | ||
a16b043c | 5985 | static void kvm_init_msr_list(void) |
043405e1 | 5986 | { |
24c29b7a | 5987 | struct x86_pmu_capability x86_pmu; |
043405e1 | 5988 | u32 dummy[2]; |
7a5ee6ed | 5989 | unsigned i; |
043405e1 | 5990 | |
e2ada66e | 5991 | BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, |
7a5ee6ed | 5992 | "Please update the fixed PMCs in msrs_to_saved_all[]"); |
24c29b7a PB |
5993 | |
5994 | perf_get_x86_pmu_capability(&x86_pmu); | |
e2ada66e | 5995 | |
6cbee2b9 XL |
5996 | num_msrs_to_save = 0; |
5997 | num_emulated_msrs = 0; | |
5998 | num_msr_based_features = 0; | |
5999 | ||
7a5ee6ed CQ |
6000 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { |
6001 | if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) | |
043405e1 | 6002 | continue; |
93c4adc7 PB |
6003 | |
6004 | /* | |
6005 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 6006 | * to the guests in some cases. |
93c4adc7 | 6007 | */ |
7a5ee6ed | 6008 | switch (msrs_to_save_all[i]) { |
93c4adc7 | 6009 | case MSR_IA32_BNDCFGS: |
503234b3 | 6010 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
6011 | continue; |
6012 | break; | |
9dbe6cf9 | 6013 | case MSR_TSC_AUX: |
36fa06f9 SC |
6014 | if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && |
6015 | !kvm_cpu_cap_has(X86_FEATURE_RDPID)) | |
9dbe6cf9 PB |
6016 | continue; |
6017 | break; | |
f4cfcd2d ML |
6018 | case MSR_IA32_UMWAIT_CONTROL: |
6019 | if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) | |
6020 | continue; | |
6021 | break; | |
bf8c55d8 CP |
6022 | case MSR_IA32_RTIT_CTL: |
6023 | case MSR_IA32_RTIT_STATUS: | |
7b874c26 | 6024 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) |
bf8c55d8 CP |
6025 | continue; |
6026 | break; | |
6027 | case MSR_IA32_RTIT_CR3_MATCH: | |
7b874c26 | 6028 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
6029 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) |
6030 | continue; | |
6031 | break; | |
6032 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
6033 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
7b874c26 | 6034 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
6035 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && |
6036 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
6037 | continue; | |
6038 | break; | |
7cb85fc4 | 6039 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: |
7b874c26 | 6040 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
7a5ee6ed | 6041 | msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= |
bf8c55d8 CP |
6042 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) |
6043 | continue; | |
6044 | break; | |
cf05a67b | 6045 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: |
7a5ee6ed | 6046 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= |
24c29b7a PB |
6047 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
6048 | continue; | |
6049 | break; | |
cf05a67b | 6050 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: |
7a5ee6ed | 6051 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= |
24c29b7a PB |
6052 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
6053 | continue; | |
7cb85fc4 | 6054 | break; |
93c4adc7 PB |
6055 | default: |
6056 | break; | |
6057 | } | |
6058 | ||
7a5ee6ed | 6059 | msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; |
043405e1 | 6060 | } |
62ef68bb | 6061 | |
7a5ee6ed | 6062 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
b3646477 | 6063 | if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) |
bc226f07 | 6064 | continue; |
62ef68bb | 6065 | |
7a5ee6ed | 6066 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 6067 | } |
801e459a | 6068 | |
7a5ee6ed | 6069 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { |
801e459a TL |
6070 | struct kvm_msr_entry msr; |
6071 | ||
7a5ee6ed | 6072 | msr.index = msr_based_features_all[i]; |
66421c1e | 6073 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
6074 | continue; |
6075 | ||
7a5ee6ed | 6076 | msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; |
801e459a | 6077 | } |
043405e1 CO |
6078 | } |
6079 | ||
bda9020e MT |
6080 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
6081 | const void *v) | |
bbd9b64e | 6082 | { |
70252a10 AK |
6083 | int handled = 0; |
6084 | int n; | |
6085 | ||
6086 | do { | |
6087 | n = min(len, 8); | |
bce87cce | 6088 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
6089 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
6090 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
6091 | break; |
6092 | handled += n; | |
6093 | addr += n; | |
6094 | len -= n; | |
6095 | v += n; | |
6096 | } while (len); | |
bbd9b64e | 6097 | |
70252a10 | 6098 | return handled; |
bbd9b64e CO |
6099 | } |
6100 | ||
bda9020e | 6101 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 6102 | { |
70252a10 AK |
6103 | int handled = 0; |
6104 | int n; | |
6105 | ||
6106 | do { | |
6107 | n = min(len, 8); | |
bce87cce | 6108 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
6109 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
6110 | addr, n, v)) | |
6111 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 6112 | break; |
e39d200f | 6113 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
6114 | handled += n; |
6115 | addr += n; | |
6116 | len -= n; | |
6117 | v += n; | |
6118 | } while (len); | |
bbd9b64e | 6119 | |
70252a10 | 6120 | return handled; |
bbd9b64e CO |
6121 | } |
6122 | ||
2dafc6c2 GN |
6123 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
6124 | struct kvm_segment *var, int seg) | |
6125 | { | |
b3646477 | 6126 | static_call(kvm_x86_set_segment)(vcpu, var, seg); |
2dafc6c2 GN |
6127 | } |
6128 | ||
6129 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
6130 | struct kvm_segment *var, int seg) | |
6131 | { | |
b3646477 | 6132 | static_call(kvm_x86_get_segment)(vcpu, var, seg); |
2dafc6c2 GN |
6133 | } |
6134 | ||
54987b7a PB |
6135 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
6136 | struct x86_exception *exception) | |
02f59dc9 JR |
6137 | { |
6138 | gpa_t t_gpa; | |
02f59dc9 JR |
6139 | |
6140 | BUG_ON(!mmu_is_nested(vcpu)); | |
6141 | ||
6142 | /* NPT walks are always user-walks */ | |
6143 | access |= PFERR_USER_MASK; | |
44dd3ffa | 6144 | t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
6145 | |
6146 | return t_gpa; | |
6147 | } | |
6148 | ||
ab9ae313 AK |
6149 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
6150 | struct x86_exception *exception) | |
1871c602 | 6151 | { |
b3646477 | 6152 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
ab9ae313 | 6153 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 | 6154 | } |
54f958cd | 6155 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); |
1871c602 | 6156 | |
ab9ae313 AK |
6157 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
6158 | struct x86_exception *exception) | |
1871c602 | 6159 | { |
b3646477 | 6160 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 6161 | access |= PFERR_FETCH_MASK; |
ab9ae313 | 6162 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
6163 | } |
6164 | ||
ab9ae313 AK |
6165 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
6166 | struct x86_exception *exception) | |
1871c602 | 6167 | { |
b3646477 | 6168 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 6169 | access |= PFERR_WRITE_MASK; |
ab9ae313 | 6170 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 | 6171 | } |
54f958cd | 6172 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); |
1871c602 GN |
6173 | |
6174 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
6175 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
6176 | struct x86_exception *exception) | |
1871c602 | 6177 | { |
ab9ae313 | 6178 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
6179 | } |
6180 | ||
6181 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
6182 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 6183 | struct x86_exception *exception) |
bbd9b64e CO |
6184 | { |
6185 | void *data = val; | |
10589a46 | 6186 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
6187 | |
6188 | while (bytes) { | |
14dfe855 | 6189 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 6190 | exception); |
bbd9b64e | 6191 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 6192 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
6193 | int ret; |
6194 | ||
bcc55cba | 6195 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6196 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
6197 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
6198 | offset, toread); | |
10589a46 | 6199 | if (ret < 0) { |
c3cd7ffa | 6200 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
6201 | goto out; |
6202 | } | |
bbd9b64e | 6203 | |
77c2002e IE |
6204 | bytes -= toread; |
6205 | data += toread; | |
6206 | addr += toread; | |
bbd9b64e | 6207 | } |
10589a46 | 6208 | out: |
10589a46 | 6209 | return r; |
bbd9b64e | 6210 | } |
77c2002e | 6211 | |
1871c602 | 6212 | /* used for instruction fetching */ |
0f65dd70 AK |
6213 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
6214 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 6215 | struct x86_exception *exception) |
1871c602 | 6216 | { |
0f65dd70 | 6217 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
b3646477 | 6218 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
6219 | unsigned offset; |
6220 | int ret; | |
0f65dd70 | 6221 | |
44583cba PB |
6222 | /* Inline kvm_read_guest_virt_helper for speed. */ |
6223 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
6224 | exception); | |
6225 | if (unlikely(gpa == UNMAPPED_GVA)) | |
6226 | return X86EMUL_PROPAGATE_FAULT; | |
6227 | ||
6228 | offset = addr & (PAGE_SIZE-1); | |
6229 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
6230 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
6231 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
6232 | offset, bytes); | |
44583cba PB |
6233 | if (unlikely(ret < 0)) |
6234 | return X86EMUL_IO_NEEDED; | |
6235 | ||
6236 | return X86EMUL_CONTINUE; | |
1871c602 GN |
6237 | } |
6238 | ||
ce14e868 | 6239 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 6240 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 6241 | struct x86_exception *exception) |
1871c602 | 6242 | { |
b3646477 | 6243 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 6244 | |
353c0956 PB |
6245 | /* |
6246 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
6247 | * is returned, but our callers are not ready for that and they blindly | |
6248 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
6249 | * uninitialized kernel stack memory into cr2 and error code. | |
6250 | */ | |
6251 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 6252 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 6253 | exception); |
1871c602 | 6254 | } |
064aea77 | 6255 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 6256 | |
ce14e868 PB |
6257 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
6258 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 6259 | struct x86_exception *exception, bool system) |
1871c602 | 6260 | { |
0f65dd70 | 6261 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3c9fa24c PB |
6262 | u32 access = 0; |
6263 | ||
b3646477 | 6264 | if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) |
3c9fa24c PB |
6265 | access |= PFERR_USER_MASK; |
6266 | ||
6267 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
6268 | } |
6269 | ||
7a036a6f RK |
6270 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
6271 | unsigned long addr, void *val, unsigned int bytes) | |
6272 | { | |
6273 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6274 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
6275 | ||
6276 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
6277 | } | |
6278 | ||
ce14e868 PB |
6279 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
6280 | struct kvm_vcpu *vcpu, u32 access, | |
6281 | struct x86_exception *exception) | |
77c2002e IE |
6282 | { |
6283 | void *data = val; | |
6284 | int r = X86EMUL_CONTINUE; | |
6285 | ||
6286 | while (bytes) { | |
14dfe855 | 6287 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
ce14e868 | 6288 | access, |
ab9ae313 | 6289 | exception); |
77c2002e IE |
6290 | unsigned offset = addr & (PAGE_SIZE-1); |
6291 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
6292 | int ret; | |
6293 | ||
bcc55cba | 6294 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6295 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 6296 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 6297 | if (ret < 0) { |
c3cd7ffa | 6298 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
6299 | goto out; |
6300 | } | |
6301 | ||
6302 | bytes -= towrite; | |
6303 | data += towrite; | |
6304 | addr += towrite; | |
6305 | } | |
6306 | out: | |
6307 | return r; | |
6308 | } | |
ce14e868 PB |
6309 | |
6310 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
6311 | unsigned int bytes, struct x86_exception *exception, |
6312 | bool system) | |
ce14e868 PB |
6313 | { |
6314 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
3c9fa24c PB |
6315 | u32 access = PFERR_WRITE_MASK; |
6316 | ||
b3646477 | 6317 | if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) |
3c9fa24c | 6318 | access |= PFERR_USER_MASK; |
ce14e868 PB |
6319 | |
6320 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 6321 | access, exception); |
ce14e868 PB |
6322 | } |
6323 | ||
6324 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
6325 | unsigned int bytes, struct x86_exception *exception) | |
6326 | { | |
c595ceee PB |
6327 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
6328 | vcpu->arch.l1tf_flush_l1d = true; | |
6329 | ||
ce14e868 PB |
6330 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
6331 | PFERR_WRITE_MASK, exception); | |
6332 | } | |
6a4d7550 | 6333 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 6334 | |
082d06ed WL |
6335 | int handle_ud(struct kvm_vcpu *vcpu) |
6336 | { | |
b3dc0695 | 6337 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
6c86eedc | 6338 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
6339 | char sig[5]; /* ud2; .ascii "kvm" */ |
6340 | struct x86_exception e; | |
6341 | ||
b3646477 | 6342 | if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) |
09e3e2a1 SC |
6343 | return 1; |
6344 | ||
6c86eedc | 6345 | if (force_emulation_prefix && |
3c9fa24c PB |
6346 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
6347 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 6348 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
6c86eedc | 6349 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 6350 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 6351 | } |
082d06ed | 6352 | |
60fc3d02 | 6353 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
6354 | } |
6355 | EXPORT_SYMBOL_GPL(handle_ud); | |
6356 | ||
0f89b207 TL |
6357 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6358 | gpa_t gpa, bool write) | |
6359 | { | |
6360 | /* For APIC access vmexit */ | |
6361 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6362 | return 1; | |
6363 | ||
6364 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
6365 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
6366 | return 1; | |
6367 | } | |
6368 | ||
6369 | return 0; | |
6370 | } | |
6371 | ||
af7cc7d1 XG |
6372 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6373 | gpa_t *gpa, struct x86_exception *exception, | |
6374 | bool write) | |
6375 | { | |
b3646477 | 6376 | u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) |
97d64b78 | 6377 | | (write ? PFERR_WRITE_MASK : 0); |
af7cc7d1 | 6378 | |
be94f6b7 HH |
6379 | /* |
6380 | * currently PKRU is only applied to ept enabled guest so | |
6381 | * there is no pkey in EPT page table for L1 guest or EPT | |
6382 | * shadow page table for L2 guest. | |
6383 | */ | |
97d64b78 | 6384 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 | 6385 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
871bd034 | 6386 | vcpu->arch.mmio_access, 0, access)) { |
bebb106a XG |
6387 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
6388 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 6389 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
6390 | return 1; |
6391 | } | |
6392 | ||
af7cc7d1 XG |
6393 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
6394 | ||
6395 | if (*gpa == UNMAPPED_GVA) | |
6396 | return -1; | |
6397 | ||
0f89b207 | 6398 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
6399 | } |
6400 | ||
3200f405 | 6401 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 6402 | const void *val, int bytes) |
bbd9b64e CO |
6403 | { |
6404 | int ret; | |
6405 | ||
54bf36aa | 6406 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 6407 | if (ret < 0) |
bbd9b64e | 6408 | return 0; |
0eb05bf2 | 6409 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
6410 | return 1; |
6411 | } | |
6412 | ||
77d197b2 XG |
6413 | struct read_write_emulator_ops { |
6414 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
6415 | int bytes); | |
6416 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6417 | void *val, int bytes); | |
6418 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6419 | int bytes, void *val); | |
6420 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6421 | void *val, int bytes); | |
6422 | bool write; | |
6423 | }; | |
6424 | ||
6425 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
6426 | { | |
6427 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 6428 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 6429 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
6430 | vcpu->mmio_read_completed = 0; |
6431 | return 1; | |
6432 | } | |
6433 | ||
6434 | return 0; | |
6435 | } | |
6436 | ||
6437 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6438 | void *val, int bytes) | |
6439 | { | |
54bf36aa | 6440 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
6441 | } |
6442 | ||
6443 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6444 | void *val, int bytes) | |
6445 | { | |
6446 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
6447 | } | |
6448 | ||
6449 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
6450 | { | |
e39d200f | 6451 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
6452 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
6453 | } | |
6454 | ||
6455 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6456 | void *val, int bytes) | |
6457 | { | |
e39d200f | 6458 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
6459 | return X86EMUL_IO_NEEDED; |
6460 | } | |
6461 | ||
6462 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6463 | void *val, int bytes) | |
6464 | { | |
f78146b0 AK |
6465 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
6466 | ||
87da7e66 | 6467 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
6468 | return X86EMUL_CONTINUE; |
6469 | } | |
6470 | ||
0fbe9b0b | 6471 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
6472 | .read_write_prepare = read_prepare, |
6473 | .read_write_emulate = read_emulate, | |
6474 | .read_write_mmio = vcpu_mmio_read, | |
6475 | .read_write_exit_mmio = read_exit_mmio, | |
6476 | }; | |
6477 | ||
0fbe9b0b | 6478 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
6479 | .read_write_emulate = write_emulate, |
6480 | .read_write_mmio = write_mmio, | |
6481 | .read_write_exit_mmio = write_exit_mmio, | |
6482 | .write = true, | |
6483 | }; | |
6484 | ||
22388a3c XG |
6485 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
6486 | unsigned int bytes, | |
6487 | struct x86_exception *exception, | |
6488 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 6489 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6490 | { |
af7cc7d1 XG |
6491 | gpa_t gpa; |
6492 | int handled, ret; | |
22388a3c | 6493 | bool write = ops->write; |
f78146b0 | 6494 | struct kvm_mmio_fragment *frag; |
c9b8b07c | 6495 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
0f89b207 TL |
6496 | |
6497 | /* | |
6498 | * If the exit was due to a NPF we may already have a GPA. | |
6499 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
6500 | * Note, this cannot be used on string operations since string | |
6501 | * operation using rep will only have the initial GPA from the NPF | |
6502 | * occurred. | |
6503 | */ | |
744e699c SC |
6504 | if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && |
6505 | (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { | |
6506 | gpa = ctxt->gpa_val; | |
618232e2 BS |
6507 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); |
6508 | } else { | |
6509 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
6510 | if (ret < 0) | |
6511 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 6512 | } |
10589a46 | 6513 | |
618232e2 | 6514 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
6515 | return X86EMUL_CONTINUE; |
6516 | ||
bbd9b64e CO |
6517 | /* |
6518 | * Is this MMIO handled locally? | |
6519 | */ | |
22388a3c | 6520 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 6521 | if (handled == bytes) |
bbd9b64e | 6522 | return X86EMUL_CONTINUE; |
bbd9b64e | 6523 | |
70252a10 AK |
6524 | gpa += handled; |
6525 | bytes -= handled; | |
6526 | val += handled; | |
6527 | ||
87da7e66 XG |
6528 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
6529 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
6530 | frag->gpa = gpa; | |
6531 | frag->data = val; | |
6532 | frag->len = bytes; | |
f78146b0 | 6533 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
6534 | } |
6535 | ||
52eb5a6d XL |
6536 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
6537 | unsigned long addr, | |
22388a3c XG |
6538 | void *val, unsigned int bytes, |
6539 | struct x86_exception *exception, | |
0fbe9b0b | 6540 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6541 | { |
0f65dd70 | 6542 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
6543 | gpa_t gpa; |
6544 | int rc; | |
6545 | ||
6546 | if (ops->read_write_prepare && | |
6547 | ops->read_write_prepare(vcpu, val, bytes)) | |
6548 | return X86EMUL_CONTINUE; | |
6549 | ||
6550 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 6551 | |
bbd9b64e CO |
6552 | /* Crossing a page boundary? */ |
6553 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 6554 | int now; |
bbd9b64e CO |
6555 | |
6556 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
6557 | rc = emulator_read_write_onepage(addr, val, now, exception, |
6558 | vcpu, ops); | |
6559 | ||
bbd9b64e CO |
6560 | if (rc != X86EMUL_CONTINUE) |
6561 | return rc; | |
6562 | addr += now; | |
bac15531 NA |
6563 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6564 | addr = (u32)addr; | |
bbd9b64e CO |
6565 | val += now; |
6566 | bytes -= now; | |
6567 | } | |
22388a3c | 6568 | |
f78146b0 AK |
6569 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
6570 | vcpu, ops); | |
6571 | if (rc != X86EMUL_CONTINUE) | |
6572 | return rc; | |
6573 | ||
6574 | if (!vcpu->mmio_nr_fragments) | |
6575 | return rc; | |
6576 | ||
6577 | gpa = vcpu->mmio_fragments[0].gpa; | |
6578 | ||
6579 | vcpu->mmio_needed = 1; | |
6580 | vcpu->mmio_cur_fragment = 0; | |
6581 | ||
87da7e66 | 6582 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
6583 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
6584 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
6585 | vcpu->run->mmio.phys_addr = gpa; | |
6586 | ||
6587 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
6588 | } |
6589 | ||
6590 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
6591 | unsigned long addr, | |
6592 | void *val, | |
6593 | unsigned int bytes, | |
6594 | struct x86_exception *exception) | |
6595 | { | |
6596 | return emulator_read_write(ctxt, addr, val, bytes, | |
6597 | exception, &read_emultor); | |
6598 | } | |
6599 | ||
52eb5a6d | 6600 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
6601 | unsigned long addr, |
6602 | const void *val, | |
6603 | unsigned int bytes, | |
6604 | struct x86_exception *exception) | |
6605 | { | |
6606 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
6607 | exception, &write_emultor); | |
bbd9b64e | 6608 | } |
bbd9b64e | 6609 | |
daea3e73 AK |
6610 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
6611 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
6612 | ||
6613 | #ifdef CONFIG_X86_64 | |
6614 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
6615 | #else | |
6616 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 6617 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
6618 | #endif |
6619 | ||
0f65dd70 AK |
6620 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
6621 | unsigned long addr, | |
bbd9b64e CO |
6622 | const void *old, |
6623 | const void *new, | |
6624 | unsigned int bytes, | |
0f65dd70 | 6625 | struct x86_exception *exception) |
bbd9b64e | 6626 | { |
42e35f80 | 6627 | struct kvm_host_map map; |
0f65dd70 | 6628 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
9de6fe3c | 6629 | u64 page_line_mask; |
daea3e73 | 6630 | gpa_t gpa; |
daea3e73 AK |
6631 | char *kaddr; |
6632 | bool exchanged; | |
2bacc55c | 6633 | |
daea3e73 AK |
6634 | /* guests cmpxchg8b have to be emulated atomically */ |
6635 | if (bytes > 8 || (bytes & (bytes - 1))) | |
6636 | goto emul_write; | |
10589a46 | 6637 | |
daea3e73 | 6638 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 6639 | |
daea3e73 AK |
6640 | if (gpa == UNMAPPED_GVA || |
6641 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6642 | goto emul_write; | |
2bacc55c | 6643 | |
9de6fe3c XL |
6644 | /* |
6645 | * Emulate the atomic as a straight write to avoid #AC if SLD is | |
6646 | * enabled in the host and the access splits a cache line. | |
6647 | */ | |
6648 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
6649 | page_line_mask = ~(cache_line_size() - 1); | |
6650 | else | |
6651 | page_line_mask = PAGE_MASK; | |
6652 | ||
6653 | if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) | |
daea3e73 | 6654 | goto emul_write; |
72dc67a6 | 6655 | |
42e35f80 | 6656 | if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) |
c19b8bd6 | 6657 | goto emul_write; |
72dc67a6 | 6658 | |
42e35f80 KA |
6659 | kaddr = map.hva + offset_in_page(gpa); |
6660 | ||
daea3e73 AK |
6661 | switch (bytes) { |
6662 | case 1: | |
6663 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
6664 | break; | |
6665 | case 2: | |
6666 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
6667 | break; | |
6668 | case 4: | |
6669 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
6670 | break; | |
6671 | case 8: | |
6672 | exchanged = CMPXCHG64(kaddr, old, new); | |
6673 | break; | |
6674 | default: | |
6675 | BUG(); | |
2bacc55c | 6676 | } |
42e35f80 KA |
6677 | |
6678 | kvm_vcpu_unmap(vcpu, &map, true); | |
daea3e73 AK |
6679 | |
6680 | if (!exchanged) | |
6681 | return X86EMUL_CMPXCHG_FAILED; | |
6682 | ||
0eb05bf2 | 6683 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
6684 | |
6685 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 6686 | |
3200f405 | 6687 | emul_write: |
daea3e73 | 6688 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 6689 | |
0f65dd70 | 6690 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
6691 | } |
6692 | ||
cf8f70bf GN |
6693 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
6694 | { | |
cbfc6c91 | 6695 | int r = 0, i; |
cf8f70bf | 6696 | |
cbfc6c91 WL |
6697 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
6698 | if (vcpu->arch.pio.in) | |
6699 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
6700 | vcpu->arch.pio.size, pd); | |
6701 | else | |
6702 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
6703 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
6704 | pd); | |
6705 | if (r) | |
6706 | break; | |
6707 | pd += vcpu->arch.pio.size; | |
6708 | } | |
cf8f70bf GN |
6709 | return r; |
6710 | } | |
6711 | ||
6f6fbe98 XG |
6712 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
6713 | unsigned short port, void *val, | |
6714 | unsigned int count, bool in) | |
cf8f70bf | 6715 | { |
cf8f70bf | 6716 | vcpu->arch.pio.port = port; |
6f6fbe98 | 6717 | vcpu->arch.pio.in = in; |
7972995b | 6718 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
6719 | vcpu->arch.pio.size = size; |
6720 | ||
6721 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 6722 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6723 | return 1; |
6724 | } | |
6725 | ||
6726 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 6727 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
6728 | vcpu->run->io.size = size; |
6729 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
6730 | vcpu->run->io.count = count; | |
6731 | vcpu->run->io.port = port; | |
6732 | ||
6733 | return 0; | |
6734 | } | |
6735 | ||
2e3bb4d8 SC |
6736 | static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
6737 | unsigned short port, void *val, unsigned int count) | |
cf8f70bf | 6738 | { |
6f6fbe98 | 6739 | int ret; |
ca1d4a9e | 6740 | |
6f6fbe98 XG |
6741 | if (vcpu->arch.pio.count) |
6742 | goto data_avail; | |
cf8f70bf | 6743 | |
cbfc6c91 WL |
6744 | memset(vcpu->arch.pio_data, 0, size * count); |
6745 | ||
6f6fbe98 XG |
6746 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
6747 | if (ret) { | |
6748 | data_avail: | |
6749 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 6750 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 6751 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6752 | return 1; |
6753 | } | |
6754 | ||
cf8f70bf GN |
6755 | return 0; |
6756 | } | |
6757 | ||
2e3bb4d8 SC |
6758 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
6759 | int size, unsigned short port, void *val, | |
6760 | unsigned int count) | |
6f6fbe98 | 6761 | { |
2e3bb4d8 | 6762 | return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); |
6f6fbe98 | 6763 | |
2e3bb4d8 | 6764 | } |
6f6fbe98 | 6765 | |
2e3bb4d8 SC |
6766 | static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, |
6767 | unsigned short port, const void *val, | |
6768 | unsigned int count) | |
6769 | { | |
6f6fbe98 | 6770 | memcpy(vcpu->arch.pio_data, val, size * count); |
1171903d | 6771 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
6772 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
6773 | } | |
6774 | ||
2e3bb4d8 SC |
6775 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
6776 | int size, unsigned short port, | |
6777 | const void *val, unsigned int count) | |
6778 | { | |
6779 | return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); | |
6780 | } | |
6781 | ||
bbd9b64e CO |
6782 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
6783 | { | |
b3646477 | 6784 | return static_call(kvm_x86_get_segment_base)(vcpu, seg); |
bbd9b64e CO |
6785 | } |
6786 | ||
3cb16fe7 | 6787 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 6788 | { |
3cb16fe7 | 6789 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
6790 | } |
6791 | ||
ae6a2375 | 6792 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
6793 | { |
6794 | if (!need_emulate_wbinvd(vcpu)) | |
6795 | return X86EMUL_CONTINUE; | |
6796 | ||
b3646477 | 6797 | if (static_call(kvm_x86_has_wbinvd_exit)()) { |
2eec7343 JK |
6798 | int cpu = get_cpu(); |
6799 | ||
6800 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
c2162e13 | 6801 | on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, |
f5f48ee1 | 6802 | wbinvd_ipi, NULL, 1); |
2eec7343 | 6803 | put_cpu(); |
f5f48ee1 | 6804 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
6805 | } else |
6806 | wbinvd(); | |
f5f48ee1 SY |
6807 | return X86EMUL_CONTINUE; |
6808 | } | |
5cb56059 JS |
6809 | |
6810 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
6811 | { | |
6affcbed KH |
6812 | kvm_emulate_wbinvd_noskip(vcpu); |
6813 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 6814 | } |
f5f48ee1 SY |
6815 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
6816 | ||
5cb56059 JS |
6817 | |
6818 | ||
bcaf5cc5 AK |
6819 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
6820 | { | |
5cb56059 | 6821 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
6822 | } |
6823 | ||
29d6ca41 PB |
6824 | static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6825 | unsigned long *dest) | |
bbd9b64e | 6826 | { |
29d6ca41 | 6827 | kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
6828 | } |
6829 | ||
52eb5a6d XL |
6830 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6831 | unsigned long value) | |
bbd9b64e | 6832 | { |
338dbc97 | 6833 | |
996ff542 | 6834 | return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
6835 | } |
6836 | ||
52a46617 | 6837 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 6838 | { |
52a46617 | 6839 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
6840 | } |
6841 | ||
717746e3 | 6842 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 6843 | { |
717746e3 | 6844 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
6845 | unsigned long value; |
6846 | ||
6847 | switch (cr) { | |
6848 | case 0: | |
6849 | value = kvm_read_cr0(vcpu); | |
6850 | break; | |
6851 | case 2: | |
6852 | value = vcpu->arch.cr2; | |
6853 | break; | |
6854 | case 3: | |
9f8fe504 | 6855 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
6856 | break; |
6857 | case 4: | |
6858 | value = kvm_read_cr4(vcpu); | |
6859 | break; | |
6860 | case 8: | |
6861 | value = kvm_get_cr8(vcpu); | |
6862 | break; | |
6863 | default: | |
a737f256 | 6864 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
6865 | return 0; |
6866 | } | |
6867 | ||
6868 | return value; | |
6869 | } | |
6870 | ||
717746e3 | 6871 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 6872 | { |
717746e3 | 6873 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
6874 | int res = 0; |
6875 | ||
52a46617 GN |
6876 | switch (cr) { |
6877 | case 0: | |
49a9b07e | 6878 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
6879 | break; |
6880 | case 2: | |
6881 | vcpu->arch.cr2 = val; | |
6882 | break; | |
6883 | case 3: | |
2390218b | 6884 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
6885 | break; |
6886 | case 4: | |
a83b29c6 | 6887 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
6888 | break; |
6889 | case 8: | |
eea1cff9 | 6890 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
6891 | break; |
6892 | default: | |
a737f256 | 6893 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 6894 | res = -1; |
52a46617 | 6895 | } |
0f12244f GN |
6896 | |
6897 | return res; | |
52a46617 GN |
6898 | } |
6899 | ||
717746e3 | 6900 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 6901 | { |
b3646477 | 6902 | return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); |
9c537244 GN |
6903 | } |
6904 | ||
4bff1e86 | 6905 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 6906 | { |
b3646477 | 6907 | static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
6908 | } |
6909 | ||
4bff1e86 | 6910 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 6911 | { |
b3646477 | 6912 | static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
6913 | } |
6914 | ||
1ac9d0cf AK |
6915 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
6916 | { | |
b3646477 | 6917 | static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
6918 | } |
6919 | ||
6920 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
6921 | { | |
b3646477 | 6922 | static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
6923 | } |
6924 | ||
4bff1e86 AK |
6925 | static unsigned long emulator_get_cached_segment_base( |
6926 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 6927 | { |
4bff1e86 | 6928 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
6929 | } |
6930 | ||
1aa36616 AK |
6931 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
6932 | struct desc_struct *desc, u32 *base3, | |
6933 | int seg) | |
2dafc6c2 GN |
6934 | { |
6935 | struct kvm_segment var; | |
6936 | ||
4bff1e86 | 6937 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 6938 | *selector = var.selector; |
2dafc6c2 | 6939 | |
378a8b09 GN |
6940 | if (var.unusable) { |
6941 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
6942 | if (base3) |
6943 | *base3 = 0; | |
2dafc6c2 | 6944 | return false; |
378a8b09 | 6945 | } |
2dafc6c2 GN |
6946 | |
6947 | if (var.g) | |
6948 | var.limit >>= 12; | |
6949 | set_desc_limit(desc, var.limit); | |
6950 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
6951 | #ifdef CONFIG_X86_64 |
6952 | if (base3) | |
6953 | *base3 = var.base >> 32; | |
6954 | #endif | |
2dafc6c2 GN |
6955 | desc->type = var.type; |
6956 | desc->s = var.s; | |
6957 | desc->dpl = var.dpl; | |
6958 | desc->p = var.present; | |
6959 | desc->avl = var.avl; | |
6960 | desc->l = var.l; | |
6961 | desc->d = var.db; | |
6962 | desc->g = var.g; | |
6963 | ||
6964 | return true; | |
6965 | } | |
6966 | ||
1aa36616 AK |
6967 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
6968 | struct desc_struct *desc, u32 base3, | |
6969 | int seg) | |
2dafc6c2 | 6970 | { |
4bff1e86 | 6971 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
6972 | struct kvm_segment var; |
6973 | ||
1aa36616 | 6974 | var.selector = selector; |
2dafc6c2 | 6975 | var.base = get_desc_base(desc); |
5601d05b GN |
6976 | #ifdef CONFIG_X86_64 |
6977 | var.base |= ((u64)base3) << 32; | |
6978 | #endif | |
2dafc6c2 GN |
6979 | var.limit = get_desc_limit(desc); |
6980 | if (desc->g) | |
6981 | var.limit = (var.limit << 12) | 0xfff; | |
6982 | var.type = desc->type; | |
2dafc6c2 GN |
6983 | var.dpl = desc->dpl; |
6984 | var.db = desc->d; | |
6985 | var.s = desc->s; | |
6986 | var.l = desc->l; | |
6987 | var.g = desc->g; | |
6988 | var.avl = desc->avl; | |
6989 | var.present = desc->p; | |
6990 | var.unusable = !var.present; | |
6991 | var.padding = 0; | |
6992 | ||
6993 | kvm_set_segment(vcpu, &var, seg); | |
6994 | return; | |
6995 | } | |
6996 | ||
717746e3 AK |
6997 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
6998 | u32 msr_index, u64 *pdata) | |
6999 | { | |
1ae09954 AG |
7000 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7001 | int r; | |
7002 | ||
7003 | r = kvm_get_msr(vcpu, msr_index, pdata); | |
7004 | ||
7005 | if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { | |
7006 | /* Bounce to user space */ | |
7007 | return X86EMUL_IO_NEEDED; | |
7008 | } | |
7009 | ||
7010 | return r; | |
717746e3 AK |
7011 | } |
7012 | ||
7013 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
7014 | u32 msr_index, u64 data) | |
7015 | { | |
1ae09954 AG |
7016 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7017 | int r; | |
7018 | ||
7019 | r = kvm_set_msr(vcpu, msr_index, data); | |
7020 | ||
7021 | if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { | |
7022 | /* Bounce to user space */ | |
7023 | return X86EMUL_IO_NEEDED; | |
7024 | } | |
7025 | ||
7026 | return r; | |
717746e3 AK |
7027 | } |
7028 | ||
64d60670 PB |
7029 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
7030 | { | |
7031 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7032 | ||
7033 | return vcpu->arch.smbase; | |
7034 | } | |
7035 | ||
7036 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
7037 | { | |
7038 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7039 | ||
7040 | vcpu->arch.smbase = smbase; | |
7041 | } | |
7042 | ||
67f4d428 NA |
7043 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
7044 | u32 pmc) | |
7045 | { | |
98ff80f5 | 7046 | return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
7047 | } |
7048 | ||
222d21aa AK |
7049 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
7050 | u32 pmc, u64 *pdata) | |
7051 | { | |
c6702c9d | 7052 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
7053 | } |
7054 | ||
6c3287f7 AK |
7055 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
7056 | { | |
7057 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
7058 | } | |
7059 | ||
2953538e | 7060 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 7061 | struct x86_instruction_info *info, |
c4f035c6 AK |
7062 | enum x86_intercept_stage stage) |
7063 | { | |
b3646477 | 7064 | return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, |
21f1b8f2 | 7065 | &ctxt->exception); |
c4f035c6 AK |
7066 | } |
7067 | ||
e911eb3b | 7068 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
f91af517 SC |
7069 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, |
7070 | bool exact_only) | |
bdb42f5a | 7071 | { |
f91af517 | 7072 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); |
bdb42f5a SB |
7073 | } |
7074 | ||
5ae78e95 SC |
7075 | static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) |
7076 | { | |
7077 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); | |
7078 | } | |
7079 | ||
7080 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) | |
7081 | { | |
7082 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
7083 | } | |
7084 | ||
7085 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
7086 | { | |
7087 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
7088 | } | |
7089 | ||
dd856efa AK |
7090 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
7091 | { | |
27b4a9c4 | 7092 | return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); |
dd856efa AK |
7093 | } |
7094 | ||
7095 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
7096 | { | |
27b4a9c4 | 7097 | kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); |
dd856efa AK |
7098 | } |
7099 | ||
801806d9 NA |
7100 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
7101 | { | |
b3646477 | 7102 | static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); |
801806d9 NA |
7103 | } |
7104 | ||
6ed071f0 LP |
7105 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
7106 | { | |
7107 | return emul_to_vcpu(ctxt)->arch.hflags; | |
7108 | } | |
7109 | ||
7110 | static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) | |
7111 | { | |
78fcb2c9 SC |
7112 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7113 | ||
7114 | vcpu->arch.hflags = emul_flags; | |
7115 | kvm_mmu_reset_context(vcpu); | |
6ed071f0 LP |
7116 | } |
7117 | ||
ed19321f SC |
7118 | static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, |
7119 | const char *smstate) | |
0234bf88 | 7120 | { |
b3646477 | 7121 | return static_call(kvm_x86_pre_leave_smm)(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
7122 | } |
7123 | ||
c5833c7a SC |
7124 | static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) |
7125 | { | |
7126 | kvm_smm_changed(emul_to_vcpu(ctxt)); | |
7127 | } | |
7128 | ||
02d4160f VK |
7129 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
7130 | { | |
7131 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
7132 | } | |
7133 | ||
0225fb50 | 7134 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
7135 | .read_gpr = emulator_read_gpr, |
7136 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
7137 | .read_std = emulator_read_std, |
7138 | .write_std = emulator_write_std, | |
7a036a6f | 7139 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 7140 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
7141 | .read_emulated = emulator_read_emulated, |
7142 | .write_emulated = emulator_write_emulated, | |
7143 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 7144 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
7145 | .pio_in_emulated = emulator_pio_in_emulated, |
7146 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
7147 | .get_segment = emulator_get_segment, |
7148 | .set_segment = emulator_set_segment, | |
5951c442 | 7149 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 7150 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 7151 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
7152 | .set_gdt = emulator_set_gdt, |
7153 | .set_idt = emulator_set_idt, | |
52a46617 GN |
7154 | .get_cr = emulator_get_cr, |
7155 | .set_cr = emulator_set_cr, | |
9c537244 | 7156 | .cpl = emulator_get_cpl, |
35aa5375 GN |
7157 | .get_dr = emulator_get_dr, |
7158 | .set_dr = emulator_set_dr, | |
64d60670 PB |
7159 | .get_smbase = emulator_get_smbase, |
7160 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
7161 | .set_msr = emulator_set_msr, |
7162 | .get_msr = emulator_get_msr, | |
67f4d428 | 7163 | .check_pmc = emulator_check_pmc, |
222d21aa | 7164 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 7165 | .halt = emulator_halt, |
bcaf5cc5 | 7166 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 7167 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 7168 | .intercept = emulator_intercept, |
bdb42f5a | 7169 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
7170 | .guest_has_long_mode = emulator_guest_has_long_mode, |
7171 | .guest_has_movbe = emulator_guest_has_movbe, | |
7172 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
801806d9 | 7173 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 LP |
7174 | .get_hflags = emulator_get_hflags, |
7175 | .set_hflags = emulator_set_hflags, | |
0234bf88 | 7176 | .pre_leave_smm = emulator_pre_leave_smm, |
c5833c7a | 7177 | .post_leave_smm = emulator_post_leave_smm, |
02d4160f | 7178 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
7179 | }; |
7180 | ||
95cb2295 GN |
7181 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
7182 | { | |
b3646477 | 7183 | u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
95cb2295 GN |
7184 | /* |
7185 | * an sti; sti; sequence only disable interrupts for the first | |
7186 | * instruction. So, if the last instruction, be it emulated or | |
7187 | * not, left the system with the INT_STI flag enabled, it | |
7188 | * means that the last instruction is an sti. We should not | |
7189 | * leave the flag on in this case. The same goes for mov ss | |
7190 | */ | |
37ccdcbe PB |
7191 | if (int_shadow & mask) |
7192 | mask = 0; | |
6addfc42 | 7193 | if (unlikely(int_shadow || mask)) { |
b3646477 | 7194 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); |
6addfc42 PB |
7195 | if (!mask) |
7196 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7197 | } | |
95cb2295 GN |
7198 | } |
7199 | ||
ef54bcfe | 7200 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f | 7201 | { |
c9b8b07c | 7202 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
da9cb575 | 7203 | if (ctxt->exception.vector == PF_VECTOR) |
53b3d8e9 | 7204 | return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); |
ef54bcfe PB |
7205 | |
7206 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
7207 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
7208 | ctxt->exception.error_code); | |
54b8486f | 7209 | else |
da9cb575 | 7210 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 7211 | return false; |
54b8486f GN |
7212 | } |
7213 | ||
c9b8b07c SC |
7214 | static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) |
7215 | { | |
7216 | struct x86_emulate_ctxt *ctxt; | |
7217 | ||
7218 | ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); | |
7219 | if (!ctxt) { | |
7220 | pr_err("kvm: failed to allocate vcpu's emulator\n"); | |
7221 | return NULL; | |
7222 | } | |
7223 | ||
7224 | ctxt->vcpu = vcpu; | |
7225 | ctxt->ops = &emulate_ops; | |
7226 | vcpu->arch.emulate_ctxt = ctxt; | |
7227 | ||
7228 | return ctxt; | |
7229 | } | |
7230 | ||
8ec4722d MG |
7231 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
7232 | { | |
c9b8b07c | 7233 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d MG |
7234 | int cs_db, cs_l; |
7235 | ||
b3646477 | 7236 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
8ec4722d | 7237 | |
744e699c | 7238 | ctxt->gpa_available = false; |
adf52235 | 7239 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
7240 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
7241 | ||
adf52235 TY |
7242 | ctxt->eip = kvm_rip_read(vcpu); |
7243 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
7244 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 7245 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
7246 | cs_db ? X86EMUL_MODE_PROT32 : |
7247 | X86EMUL_MODE_PROT16; | |
a584539b | 7248 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
7249 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
7250 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 7251 | |
da6393cd WL |
7252 | ctxt->interruptibility = 0; |
7253 | ctxt->have_exception = false; | |
7254 | ctxt->exception.vector = -1; | |
7255 | ctxt->perm_ok = false; | |
7256 | ||
dd856efa | 7257 | init_decode_cache(ctxt); |
7ae441ea | 7258 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
7259 | } |
7260 | ||
9497e1f2 | 7261 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 7262 | { |
c9b8b07c | 7263 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
63995653 MG |
7264 | int ret; |
7265 | ||
7266 | init_emulate_ctxt(vcpu); | |
7267 | ||
9dac77fa AK |
7268 | ctxt->op_bytes = 2; |
7269 | ctxt->ad_bytes = 2; | |
7270 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 7271 | ret = emulate_int_real(ctxt, irq); |
63995653 | 7272 | |
9497e1f2 SC |
7273 | if (ret != X86EMUL_CONTINUE) { |
7274 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
7275 | } else { | |
7276 | ctxt->eip = ctxt->_eip; | |
7277 | kvm_rip_write(vcpu, ctxt->eip); | |
7278 | kvm_set_rflags(vcpu, ctxt->eflags); | |
7279 | } | |
63995653 MG |
7280 | } |
7281 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
7282 | ||
e2366171 | 7283 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 7284 | { |
6d77dbfc GN |
7285 | ++vcpu->stat.insn_emulation_fail; |
7286 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 7287 | |
42cbf068 SC |
7288 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
7289 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7290 | return 1; |
42cbf068 | 7291 | } |
e2366171 | 7292 | |
738fece4 SC |
7293 | if (emulation_type & EMULTYPE_SKIP) { |
7294 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7295 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7296 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7297 | return 0; |
738fece4 SC |
7298 | } |
7299 | ||
22da61c9 SC |
7300 | kvm_queue_exception(vcpu, UD_VECTOR); |
7301 | ||
b3646477 | 7302 | if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { |
fc3a9157 JR |
7303 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
7304 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7305 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7306 | return 0; |
fc3a9157 | 7307 | } |
e2366171 | 7308 | |
60fc3d02 | 7309 | return 1; |
6d77dbfc GN |
7310 | } |
7311 | ||
736c291c | 7312 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 GN |
7313 | bool write_fault_to_shadow_pgtable, |
7314 | int emulation_type) | |
a6f177ef | 7315 | { |
736c291c | 7316 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 7317 | kvm_pfn_t pfn; |
a6f177ef | 7318 | |
92daa48b | 7319 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
991eebf9 GN |
7320 | return false; |
7321 | ||
92daa48b SC |
7322 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7323 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7324 | return false; |
7325 | ||
44dd3ffa | 7326 | if (!vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7327 | /* |
7328 | * Write permission should be allowed since only | |
7329 | * write access need to be emulated. | |
7330 | */ | |
736c291c | 7331 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 7332 | |
95b3cf69 XG |
7333 | /* |
7334 | * If the mapping is invalid in guest, let cpu retry | |
7335 | * it to generate fault. | |
7336 | */ | |
7337 | if (gpa == UNMAPPED_GVA) | |
7338 | return true; | |
7339 | } | |
a6f177ef | 7340 | |
8e3d9d06 XG |
7341 | /* |
7342 | * Do not retry the unhandleable instruction if it faults on the | |
7343 | * readonly host memory, otherwise it will goto a infinite loop: | |
7344 | * retry instruction -> write #PF -> emulation fail -> retry | |
7345 | * instruction -> ... | |
7346 | */ | |
7347 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
7348 | |
7349 | /* | |
7350 | * If the instruction failed on the error pfn, it can not be fixed, | |
7351 | * report the error to userspace. | |
7352 | */ | |
7353 | if (is_error_noslot_pfn(pfn)) | |
7354 | return false; | |
7355 | ||
7356 | kvm_release_pfn_clean(pfn); | |
7357 | ||
7358 | /* The instructions are well-emulated on direct mmu. */ | |
44dd3ffa | 7359 | if (vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7360 | unsigned int indirect_shadow_pages; |
7361 | ||
531810ca | 7362 | write_lock(&vcpu->kvm->mmu_lock); |
95b3cf69 | 7363 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; |
531810ca | 7364 | write_unlock(&vcpu->kvm->mmu_lock); |
95b3cf69 XG |
7365 | |
7366 | if (indirect_shadow_pages) | |
7367 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
7368 | ||
a6f177ef | 7369 | return true; |
8e3d9d06 | 7370 | } |
a6f177ef | 7371 | |
95b3cf69 XG |
7372 | /* |
7373 | * if emulation was due to access to shadowed page table | |
7374 | * and it failed try to unshadow page and re-enter the | |
7375 | * guest to let CPU execute the instruction. | |
7376 | */ | |
7377 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
7378 | |
7379 | /* | |
7380 | * If the access faults on its page table, it can not | |
7381 | * be fixed by unprotecting shadow page and it should | |
7382 | * be reported to userspace. | |
7383 | */ | |
7384 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
7385 | } |
7386 | ||
1cb3f3ae | 7387 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 7388 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
7389 | { |
7390 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 7391 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
7392 | |
7393 | last_retry_eip = vcpu->arch.last_retry_eip; | |
7394 | last_retry_addr = vcpu->arch.last_retry_addr; | |
7395 | ||
7396 | /* | |
7397 | * If the emulation is caused by #PF and it is non-page_table | |
7398 | * writing instruction, it means the VM-EXIT is caused by shadow | |
7399 | * page protected, we can zap the shadow page and retry this | |
7400 | * instruction directly. | |
7401 | * | |
7402 | * Note: if the guest uses a non-page-table modifying instruction | |
7403 | * on the PDE that points to the instruction, then we will unmap | |
7404 | * the instruction and go to an infinite loop. So, we cache the | |
7405 | * last retried eip and the last fault address, if we meet the eip | |
7406 | * and the address again, we can break out of the potential infinite | |
7407 | * loop. | |
7408 | */ | |
7409 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
7410 | ||
92daa48b | 7411 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
1cb3f3ae XG |
7412 | return false; |
7413 | ||
92daa48b SC |
7414 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7415 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7416 | return false; |
7417 | ||
1cb3f3ae XG |
7418 | if (x86_page_table_writing_insn(ctxt)) |
7419 | return false; | |
7420 | ||
736c291c | 7421 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
7422 | return false; |
7423 | ||
7424 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 7425 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 7426 | |
44dd3ffa | 7427 | if (!vcpu->arch.mmu->direct_map) |
736c291c | 7428 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 7429 | |
22368028 | 7430 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
7431 | |
7432 | return true; | |
7433 | } | |
7434 | ||
716d51ab GN |
7435 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
7436 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
7437 | ||
64d60670 | 7438 | static void kvm_smm_changed(struct kvm_vcpu *vcpu) |
a584539b | 7439 | { |
64d60670 | 7440 | if (!(vcpu->arch.hflags & HF_SMM_MASK)) { |
660a5d51 PB |
7441 | /* This is a good place to trace that we are exiting SMM. */ |
7442 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); | |
7443 | ||
c43203ca PB |
7444 | /* Process a latched INIT or SMI, if any. */ |
7445 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 | 7446 | } |
699023e2 PB |
7447 | |
7448 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
7449 | } |
7450 | ||
4a1e10d5 PB |
7451 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
7452 | unsigned long *db) | |
7453 | { | |
7454 | u32 dr6 = 0; | |
7455 | int i; | |
7456 | u32 enable, rwlen; | |
7457 | ||
7458 | enable = dr7; | |
7459 | rwlen = dr7 >> 16; | |
7460 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
7461 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
7462 | dr6 |= (1 << i); | |
7463 | return dr6; | |
7464 | } | |
7465 | ||
120c2c4f | 7466 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
7467 | { |
7468 | struct kvm_run *kvm_run = vcpu->run; | |
7469 | ||
c8401dda | 7470 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
9a3ecd5e | 7471 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; |
d5d260c5 | 7472 | kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
c8401dda PB |
7473 | kvm_run->debug.arch.exception = DB_VECTOR; |
7474 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7475 | return 0; |
663f4c61 | 7476 | } |
120c2c4f | 7477 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 7478 | return 1; |
663f4c61 PB |
7479 | } |
7480 | ||
6affcbed KH |
7481 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
7482 | { | |
b3646477 | 7483 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
f8ea7c60 | 7484 | int r; |
6affcbed | 7485 | |
b3646477 | 7486 | r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); |
60fc3d02 | 7487 | if (unlikely(!r)) |
f8ea7c60 | 7488 | return 0; |
c8401dda PB |
7489 | |
7490 | /* | |
7491 | * rflags is the old, "raw" value of the flags. The new value has | |
7492 | * not been saved yet. | |
7493 | * | |
7494 | * This is correct even for TF set by the guest, because "the | |
7495 | * processor will not generate this exception after the instruction | |
7496 | * that sets the TF flag". | |
7497 | */ | |
7498 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 7499 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 7500 | return r; |
6affcbed KH |
7501 | } |
7502 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
7503 | ||
4a1e10d5 PB |
7504 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
7505 | { | |
4a1e10d5 PB |
7506 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
7507 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
7508 | struct kvm_run *kvm_run = vcpu->run; |
7509 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
7510 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7511 | vcpu->arch.guest_debug_dr7, |
7512 | vcpu->arch.eff_db); | |
7513 | ||
7514 | if (dr6 != 0) { | |
9a3ecd5e | 7515 | kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; |
82b32774 | 7516 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
7517 | kvm_run->debug.arch.exception = DB_VECTOR; |
7518 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7519 | *r = 0; |
4a1e10d5 PB |
7520 | return true; |
7521 | } | |
7522 | } | |
7523 | ||
4161a569 NA |
7524 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
7525 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
7526 | unsigned long eip = kvm_get_linear_rip(vcpu); |
7527 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7528 | vcpu->arch.dr7, |
7529 | vcpu->arch.db); | |
7530 | ||
7531 | if (dr6 != 0) { | |
4d5523cf | 7532 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
60fc3d02 | 7533 | *r = 1; |
4a1e10d5 PB |
7534 | return true; |
7535 | } | |
7536 | } | |
7537 | ||
7538 | return false; | |
7539 | } | |
7540 | ||
04789b66 LA |
7541 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
7542 | { | |
2d7921c4 AM |
7543 | switch (ctxt->opcode_len) { |
7544 | case 1: | |
7545 | switch (ctxt->b) { | |
7546 | case 0xe4: /* IN */ | |
7547 | case 0xe5: | |
7548 | case 0xec: | |
7549 | case 0xed: | |
7550 | case 0xe6: /* OUT */ | |
7551 | case 0xe7: | |
7552 | case 0xee: | |
7553 | case 0xef: | |
7554 | case 0x6c: /* INS */ | |
7555 | case 0x6d: | |
7556 | case 0x6e: /* OUTS */ | |
7557 | case 0x6f: | |
7558 | return true; | |
7559 | } | |
7560 | break; | |
7561 | case 2: | |
7562 | switch (ctxt->b) { | |
7563 | case 0x33: /* RDPMC */ | |
7564 | return true; | |
7565 | } | |
7566 | break; | |
04789b66 LA |
7567 | } |
7568 | ||
7569 | return false; | |
7570 | } | |
7571 | ||
4aa2691d WH |
7572 | /* |
7573 | * Decode to be emulated instruction. Return EMULATION_OK if success. | |
7574 | */ | |
7575 | int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, | |
7576 | void *insn, int insn_len) | |
7577 | { | |
7578 | int r = EMULATION_OK; | |
7579 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; | |
7580 | ||
7581 | init_emulate_ctxt(vcpu); | |
7582 | ||
7583 | /* | |
7584 | * We will reenter on the same instruction since we do not set | |
7585 | * complete_userspace_io. This does not handle watchpoints yet, | |
7586 | * those would be handled in the emulate_ops. | |
7587 | */ | |
7588 | if (!(emulation_type & EMULTYPE_SKIP) && | |
7589 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
7590 | return r; | |
7591 | ||
b35491e6 | 7592 | r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); |
4aa2691d WH |
7593 | |
7594 | trace_kvm_emulate_insn_start(vcpu); | |
7595 | ++vcpu->stat.insn_emulation; | |
7596 | ||
7597 | return r; | |
7598 | } | |
7599 | EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); | |
7600 | ||
736c291c SC |
7601 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
7602 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 7603 | { |
95cb2295 | 7604 | int r; |
c9b8b07c | 7605 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
7ae441ea | 7606 | bool writeback = true; |
09e3e2a1 SC |
7607 | bool write_fault_to_spt; |
7608 | ||
b3646477 | 7609 | if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) |
09e3e2a1 | 7610 | return 1; |
bbd9b64e | 7611 | |
c595ceee PB |
7612 | vcpu->arch.l1tf_flush_l1d = true; |
7613 | ||
93c05d3e XG |
7614 | /* |
7615 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
7616 | * never reused. | |
7617 | */ | |
09e3e2a1 | 7618 | write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
93c05d3e | 7619 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
8d7d8102 | 7620 | |
571008da | 7621 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
4aa2691d | 7622 | kvm_clear_exception_queue(vcpu); |
4a1e10d5 | 7623 | |
4aa2691d WH |
7624 | r = x86_decode_emulated_instruction(vcpu, emulation_type, |
7625 | insn, insn_len); | |
1d2887e2 | 7626 | if (r != EMULATION_OK) { |
b4000606 | 7627 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
7628 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
7629 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 7630 | return 1; |
c83fad65 | 7631 | } |
736c291c SC |
7632 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
7633 | write_fault_to_spt, | |
7634 | emulation_type)) | |
60fc3d02 | 7635 | return 1; |
8530a79c | 7636 | if (ctxt->have_exception) { |
c8848cee JD |
7637 | /* |
7638 | * #UD should result in just EMULATION_FAILED, and trap-like | |
7639 | * exception should not be encountered during decode. | |
7640 | */ | |
7641 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
7642 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 7643 | inject_emulated_exception(vcpu); |
60fc3d02 | 7644 | return 1; |
8530a79c | 7645 | } |
e2366171 | 7646 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7647 | } |
7648 | } | |
7649 | ||
42cbf068 SC |
7650 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
7651 | !is_vmware_backdoor_opcode(ctxt)) { | |
7652 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7653 | return 1; |
42cbf068 | 7654 | } |
04789b66 | 7655 | |
1957aa63 SC |
7656 | /* |
7657 | * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks | |
7658 | * for kvm_skip_emulated_instruction(). The caller is responsible for | |
7659 | * updating interruptibility state and injecting single-step #DBs. | |
7660 | */ | |
ba8afb6b | 7661 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 7662 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
7663 | if (ctxt->eflags & X86_EFLAGS_RF) |
7664 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 7665 | return 1; |
ba8afb6b GN |
7666 | } |
7667 | ||
736c291c | 7668 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 7669 | return 1; |
1cb3f3ae | 7670 | |
7ae441ea | 7671 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 7672 | changes registers values during IO operation */ |
7ae441ea GN |
7673 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
7674 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 7675 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 7676 | } |
4d2179e1 | 7677 | |
5cd21917 | 7678 | restart: |
92daa48b SC |
7679 | if (emulation_type & EMULTYPE_PF) { |
7680 | /* Save the faulting GPA (cr2) in the address field */ | |
7681 | ctxt->exception.address = cr2_or_gpa; | |
7682 | ||
7683 | /* With shadow page tables, cr2 contains a GVA or nGPA. */ | |
7684 | if (vcpu->arch.mmu->direct_map) { | |
744e699c SC |
7685 | ctxt->gpa_available = true; |
7686 | ctxt->gpa_val = cr2_or_gpa; | |
92daa48b SC |
7687 | } |
7688 | } else { | |
7689 | /* Sanitize the address out of an abundance of paranoia. */ | |
7690 | ctxt->exception.address = 0; | |
7691 | } | |
0f89b207 | 7692 | |
9d74191a | 7693 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 7694 | |
775fde86 | 7695 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 7696 | return 1; |
775fde86 | 7697 | |
d2ddd1c4 | 7698 | if (r == EMULATION_FAILED) { |
736c291c | 7699 | if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, |
991eebf9 | 7700 | emulation_type)) |
60fc3d02 | 7701 | return 1; |
c3cd7ffa | 7702 | |
e2366171 | 7703 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7704 | } |
7705 | ||
9d74191a | 7706 | if (ctxt->have_exception) { |
60fc3d02 | 7707 | r = 1; |
ef54bcfe PB |
7708 | if (inject_emulated_exception(vcpu)) |
7709 | return r; | |
d2ddd1c4 | 7710 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
7711 | if (!vcpu->arch.pio.in) { |
7712 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 7713 | vcpu->arch.pio.count = 0; |
0912c977 | 7714 | } else { |
7ae441ea | 7715 | writeback = false; |
716d51ab GN |
7716 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
7717 | } | |
60fc3d02 | 7718 | r = 0; |
7ae441ea | 7719 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
7720 | ++vcpu->stat.mmio_exits; |
7721 | ||
7ae441ea GN |
7722 | if (!vcpu->mmio_is_write) |
7723 | writeback = false; | |
60fc3d02 | 7724 | r = 0; |
716d51ab | 7725 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 7726 | } else if (r == EMULATION_RESTART) |
5cd21917 | 7727 | goto restart; |
d2ddd1c4 | 7728 | else |
60fc3d02 | 7729 | r = 1; |
f850e2e6 | 7730 | |
7ae441ea | 7731 | if (writeback) { |
b3646477 | 7732 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
9d74191a | 7733 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 7734 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
38827dbd | 7735 | if (!ctxt->have_exception || |
75ee23b3 SC |
7736 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
7737 | kvm_rip_write(vcpu, ctxt->eip); | |
384dea1c | 7738 | if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) |
120c2c4f | 7739 | r = kvm_vcpu_do_singlestep(vcpu); |
afaf0b2f | 7740 | if (kvm_x86_ops.update_emulated_instruction) |
b3646477 | 7741 | static_call(kvm_x86_update_emulated_instruction)(vcpu); |
38827dbd | 7742 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 7743 | } |
6addfc42 PB |
7744 | |
7745 | /* | |
7746 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
7747 | * do nothing, and it will be requested again as soon as | |
7748 | * the shadow expires. But we still need to check here, | |
7749 | * because POPF has no interrupt shadow. | |
7750 | */ | |
7751 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
7752 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
7753 | } else |
7754 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
7755 | |
7756 | return r; | |
de7d789a | 7757 | } |
c60658d1 SC |
7758 | |
7759 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
7760 | { | |
7761 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
7762 | } | |
7763 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
7764 | ||
7765 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
7766 | void *insn, int insn_len) | |
7767 | { | |
7768 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
7769 | } | |
7770 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 7771 | |
8764ed55 SC |
7772 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
7773 | { | |
7774 | vcpu->arch.pio.count = 0; | |
7775 | return 1; | |
7776 | } | |
7777 | ||
45def77e SC |
7778 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
7779 | { | |
7780 | vcpu->arch.pio.count = 0; | |
7781 | ||
7782 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
7783 | return 1; | |
7784 | ||
7785 | return kvm_skip_emulated_instruction(vcpu); | |
7786 | } | |
7787 | ||
dca7f128 SC |
7788 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
7789 | unsigned short port) | |
de7d789a | 7790 | { |
de3cd117 | 7791 | unsigned long val = kvm_rax_read(vcpu); |
2e3bb4d8 SC |
7792 | int ret = emulator_pio_out(vcpu, size, port, &val, 1); |
7793 | ||
8764ed55 SC |
7794 | if (ret) |
7795 | return ret; | |
45def77e | 7796 | |
8764ed55 SC |
7797 | /* |
7798 | * Workaround userspace that relies on old KVM behavior of %rip being | |
7799 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
7800 | */ | |
7801 | if (port == 0x7e && | |
7802 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
7803 | vcpu->arch.complete_userspace_io = | |
7804 | complete_fast_pio_out_port_0x7e; | |
7805 | kvm_skip_emulated_instruction(vcpu); | |
7806 | } else { | |
45def77e SC |
7807 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
7808 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
7809 | } | |
8764ed55 | 7810 | return 0; |
de7d789a | 7811 | } |
de7d789a | 7812 | |
8370c3d0 TL |
7813 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
7814 | { | |
7815 | unsigned long val; | |
7816 | ||
7817 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
7818 | BUG_ON(vcpu->arch.pio.count != 1); | |
7819 | ||
45def77e SC |
7820 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
7821 | vcpu->arch.pio.count = 0; | |
7822 | return 1; | |
7823 | } | |
7824 | ||
8370c3d0 | 7825 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 7826 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
7827 | |
7828 | /* | |
2e3bb4d8 | 7829 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform |
8370c3d0 TL |
7830 | * the copy and tracing |
7831 | */ | |
2e3bb4d8 | 7832 | emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); |
de3cd117 | 7833 | kvm_rax_write(vcpu, val); |
8370c3d0 | 7834 | |
45def77e | 7835 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
7836 | } |
7837 | ||
dca7f128 SC |
7838 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
7839 | unsigned short port) | |
8370c3d0 TL |
7840 | { |
7841 | unsigned long val; | |
7842 | int ret; | |
7843 | ||
7844 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 7845 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 7846 | |
2e3bb4d8 | 7847 | ret = emulator_pio_in(vcpu, size, port, &val, 1); |
8370c3d0 | 7848 | if (ret) { |
de3cd117 | 7849 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
7850 | return ret; |
7851 | } | |
7852 | ||
45def77e | 7853 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
7854 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
7855 | ||
7856 | return 0; | |
7857 | } | |
dca7f128 SC |
7858 | |
7859 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
7860 | { | |
45def77e | 7861 | int ret; |
dca7f128 | 7862 | |
dca7f128 | 7863 | if (in) |
45def77e | 7864 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 7865 | else |
45def77e SC |
7866 | ret = kvm_fast_pio_out(vcpu, size, port); |
7867 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
7868 | } |
7869 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 7870 | |
251a5fd6 | 7871 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 7872 | { |
0a3aee0d | 7873 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 7874 | return 0; |
8cfdc000 ZA |
7875 | } |
7876 | ||
7877 | static void tsc_khz_changed(void *data) | |
c8076604 | 7878 | { |
8cfdc000 ZA |
7879 | struct cpufreq_freqs *freq = data; |
7880 | unsigned long khz = 0; | |
7881 | ||
7882 | if (data) | |
7883 | khz = freq->new; | |
7884 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
7885 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
7886 | if (!khz) | |
7887 | khz = tsc_khz; | |
0a3aee0d | 7888 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
7889 | } |
7890 | ||
5fa4ec9c | 7891 | #ifdef CONFIG_X86_64 |
0092e434 VK |
7892 | static void kvm_hyperv_tsc_notifier(void) |
7893 | { | |
0092e434 VK |
7894 | struct kvm *kvm; |
7895 | struct kvm_vcpu *vcpu; | |
7896 | int cpu; | |
a83829f5 | 7897 | unsigned long flags; |
0092e434 | 7898 | |
0d9ce162 | 7899 | mutex_lock(&kvm_lock); |
0092e434 VK |
7900 | list_for_each_entry(kvm, &vm_list, vm_list) |
7901 | kvm_make_mclock_inprogress_request(kvm); | |
7902 | ||
7903 | hyperv_stop_tsc_emulation(); | |
7904 | ||
7905 | /* TSC frequency always matches when on Hyper-V */ | |
7906 | for_each_present_cpu(cpu) | |
7907 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
7908 | kvm_max_guest_tsc_khz = tsc_khz; | |
7909 | ||
7910 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
7911 | struct kvm_arch *ka = &kvm->arch; | |
7912 | ||
a83829f5 | 7913 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
0092e434 | 7914 | pvclock_update_vm_gtod_copy(kvm); |
a83829f5 | 7915 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
0092e434 VK |
7916 | |
7917 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
7918 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
7919 | ||
7920 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
7921 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); | |
0092e434 | 7922 | } |
0d9ce162 | 7923 | mutex_unlock(&kvm_lock); |
0092e434 | 7924 | } |
5fa4ec9c | 7925 | #endif |
0092e434 | 7926 | |
df24014a | 7927 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 7928 | { |
c8076604 GH |
7929 | struct kvm *kvm; |
7930 | struct kvm_vcpu *vcpu; | |
7931 | int i, send_ipi = 0; | |
7932 | ||
8cfdc000 ZA |
7933 | /* |
7934 | * We allow guests to temporarily run on slowing clocks, | |
7935 | * provided we notify them after, or to run on accelerating | |
7936 | * clocks, provided we notify them before. Thus time never | |
7937 | * goes backwards. | |
7938 | * | |
7939 | * However, we have a problem. We can't atomically update | |
7940 | * the frequency of a given CPU from this function; it is | |
7941 | * merely a notifier, which can be called from any CPU. | |
7942 | * Changing the TSC frequency at arbitrary points in time | |
7943 | * requires a recomputation of local variables related to | |
7944 | * the TSC for each VCPU. We must flag these local variables | |
7945 | * to be updated and be sure the update takes place with the | |
7946 | * new frequency before any guests proceed. | |
7947 | * | |
7948 | * Unfortunately, the combination of hotplug CPU and frequency | |
7949 | * change creates an intractable locking scenario; the order | |
7950 | * of when these callouts happen is undefined with respect to | |
7951 | * CPU hotplug, and they can race with each other. As such, | |
7952 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
7953 | * undefined; you can actually have a CPU frequency change take | |
7954 | * place in between the computation of X and the setting of the | |
7955 | * variable. To protect against this problem, all updates of | |
7956 | * the per_cpu tsc_khz variable are done in an interrupt | |
7957 | * protected IPI, and all callers wishing to update the value | |
7958 | * must wait for a synchronous IPI to complete (which is trivial | |
7959 | * if the caller is on the CPU already). This establishes the | |
7960 | * necessary total order on variable updates. | |
7961 | * | |
7962 | * Note that because a guest time update may take place | |
7963 | * anytime after the setting of the VCPU's request bit, the | |
7964 | * correct TSC value must be set before the request. However, | |
7965 | * to ensure the update actually makes it to any guest which | |
7966 | * starts running in hardware virtualization between the set | |
7967 | * and the acquisition of the spinlock, we must also ping the | |
7968 | * CPU after setting the request bit. | |
7969 | * | |
7970 | */ | |
7971 | ||
df24014a | 7972 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 7973 | |
0d9ce162 | 7974 | mutex_lock(&kvm_lock); |
c8076604 | 7975 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 7976 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 7977 | if (vcpu->cpu != cpu) |
c8076604 | 7978 | continue; |
c285545f | 7979 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 7980 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 7981 | send_ipi = 1; |
c8076604 GH |
7982 | } |
7983 | } | |
0d9ce162 | 7984 | mutex_unlock(&kvm_lock); |
c8076604 GH |
7985 | |
7986 | if (freq->old < freq->new && send_ipi) { | |
7987 | /* | |
7988 | * We upscale the frequency. Must make the guest | |
7989 | * doesn't see old kvmclock values while running with | |
7990 | * the new frequency, otherwise we risk the guest sees | |
7991 | * time go backwards. | |
7992 | * | |
7993 | * In case we update the frequency for another cpu | |
7994 | * (which might be in guest context) send an interrupt | |
7995 | * to kick the cpu out of guest context. Next time | |
7996 | * guest context is entered kvmclock will be updated, | |
7997 | * so the guest will not see stale values. | |
7998 | */ | |
df24014a | 7999 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 8000 | } |
df24014a VK |
8001 | } |
8002 | ||
8003 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
8004 | void *data) | |
8005 | { | |
8006 | struct cpufreq_freqs *freq = data; | |
8007 | int cpu; | |
8008 | ||
8009 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
8010 | return 0; | |
8011 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
8012 | return 0; | |
8013 | ||
8014 | for_each_cpu(cpu, freq->policy->cpus) | |
8015 | __kvmclock_cpufreq_notifier(freq, cpu); | |
8016 | ||
c8076604 GH |
8017 | return 0; |
8018 | } | |
8019 | ||
8020 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
8021 | .notifier_call = kvmclock_cpufreq_notifier |
8022 | }; | |
8023 | ||
251a5fd6 | 8024 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 8025 | { |
251a5fd6 SAS |
8026 | tsc_khz_changed(NULL); |
8027 | return 0; | |
8cfdc000 ZA |
8028 | } |
8029 | ||
b820cc0c ZA |
8030 | static void kvm_timer_init(void) |
8031 | { | |
c285545f | 8032 | max_tsc_khz = tsc_khz; |
460dd42e | 8033 | |
b820cc0c | 8034 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f | 8035 | #ifdef CONFIG_CPU_FREQ |
aaec7c03 | 8036 | struct cpufreq_policy *policy; |
758f588d BP |
8037 | int cpu; |
8038 | ||
3e26f230 | 8039 | cpu = get_cpu(); |
aaec7c03 | 8040 | policy = cpufreq_cpu_get(cpu); |
9a11997e WL |
8041 | if (policy) { |
8042 | if (policy->cpuinfo.max_freq) | |
8043 | max_tsc_khz = policy->cpuinfo.max_freq; | |
8044 | cpufreq_cpu_put(policy); | |
8045 | } | |
3e26f230 | 8046 | put_cpu(); |
c285545f | 8047 | #endif |
b820cc0c ZA |
8048 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
8049 | CPUFREQ_TRANSITION_NOTIFIER); | |
8050 | } | |
460dd42e | 8051 | |
73c1b41e | 8052 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 8053 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
8054 | } |
8055 | ||
dd60d217 AK |
8056 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
8057 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 8058 | |
f5132b01 | 8059 | int kvm_is_in_guest(void) |
ff9d07a0 | 8060 | { |
086c9855 | 8061 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
8062 | } |
8063 | ||
8064 | static int kvm_is_user_mode(void) | |
8065 | { | |
8066 | int user_mode = 3; | |
dcf46b94 | 8067 | |
086c9855 | 8068 | if (__this_cpu_read(current_vcpu)) |
b3646477 | 8069 | user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu)); |
dcf46b94 | 8070 | |
ff9d07a0 ZY |
8071 | return user_mode != 0; |
8072 | } | |
8073 | ||
8074 | static unsigned long kvm_get_guest_ip(void) | |
8075 | { | |
8076 | unsigned long ip = 0; | |
dcf46b94 | 8077 | |
086c9855 AS |
8078 | if (__this_cpu_read(current_vcpu)) |
8079 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 8080 | |
ff9d07a0 ZY |
8081 | return ip; |
8082 | } | |
8083 | ||
8479e04e LK |
8084 | static void kvm_handle_intel_pt_intr(void) |
8085 | { | |
8086 | struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); | |
8087 | ||
8088 | kvm_make_request(KVM_REQ_PMI, vcpu); | |
8089 | __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, | |
8090 | (unsigned long *)&vcpu->arch.pmu.global_status); | |
8091 | } | |
8092 | ||
ff9d07a0 ZY |
8093 | static struct perf_guest_info_callbacks kvm_guest_cbs = { |
8094 | .is_in_guest = kvm_is_in_guest, | |
8095 | .is_user_mode = kvm_is_user_mode, | |
8096 | .get_guest_ip = kvm_get_guest_ip, | |
8479e04e | 8097 | .handle_intel_pt_intr = kvm_handle_intel_pt_intr, |
ff9d07a0 ZY |
8098 | }; |
8099 | ||
16e8d74d MT |
8100 | #ifdef CONFIG_X86_64 |
8101 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
8102 | { | |
d828199e MT |
8103 | struct kvm *kvm; |
8104 | ||
8105 | struct kvm_vcpu *vcpu; | |
8106 | int i; | |
8107 | ||
0d9ce162 | 8108 | mutex_lock(&kvm_lock); |
d828199e MT |
8109 | list_for_each_entry(kvm, &vm_list, vm_list) |
8110 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 8111 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 8112 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 8113 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
8114 | } |
8115 | ||
8116 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
8117 | ||
3f804f6d TG |
8118 | /* |
8119 | * Indirection to move queue_work() out of the tk_core.seq write held | |
8120 | * region to prevent possible deadlocks against time accessors which | |
8121 | * are invoked with work related locks held. | |
8122 | */ | |
8123 | static void pvclock_irq_work_fn(struct irq_work *w) | |
8124 | { | |
8125 | queue_work(system_long_wq, &pvclock_gtod_work); | |
8126 | } | |
8127 | ||
8128 | static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); | |
8129 | ||
16e8d74d MT |
8130 | /* |
8131 | * Notification about pvclock gtod data update. | |
8132 | */ | |
8133 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
8134 | void *priv) | |
8135 | { | |
8136 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
8137 | struct timekeeper *tk = priv; | |
8138 | ||
8139 | update_pvclock_gtod(tk); | |
8140 | ||
3f804f6d TG |
8141 | /* |
8142 | * Disable master clock if host does not trust, or does not use, | |
8143 | * TSC based clocksource. Delegate queue_work() to irq_work as | |
8144 | * this is invoked with tk_core.seq write held. | |
16e8d74d | 8145 | */ |
b0c39dc6 | 8146 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d | 8147 | atomic_read(&kvm_guest_has_master_clock) != 0) |
3f804f6d | 8148 | irq_work_queue(&pvclock_irq_work); |
16e8d74d MT |
8149 | return 0; |
8150 | } | |
8151 | ||
8152 | static struct notifier_block pvclock_gtod_notifier = { | |
8153 | .notifier_call = pvclock_gtod_notify, | |
8154 | }; | |
8155 | #endif | |
8156 | ||
f8c16bba | 8157 | int kvm_arch_init(void *opaque) |
043405e1 | 8158 | { |
d008dfdb | 8159 | struct kvm_x86_init_ops *ops = opaque; |
b820cc0c | 8160 | int r; |
f8c16bba | 8161 | |
afaf0b2f | 8162 | if (kvm_x86_ops.hardware_enable) { |
f8c16bba | 8163 | printk(KERN_ERR "kvm: already loaded the other module\n"); |
56c6d28a ZX |
8164 | r = -EEXIST; |
8165 | goto out; | |
f8c16bba ZX |
8166 | } |
8167 | ||
8168 | if (!ops->cpu_has_kvm_support()) { | |
ef935c25 | 8169 | pr_err_ratelimited("kvm: no hardware support\n"); |
56c6d28a ZX |
8170 | r = -EOPNOTSUPP; |
8171 | goto out; | |
f8c16bba ZX |
8172 | } |
8173 | if (ops->disabled_by_bios()) { | |
ef935c25 | 8174 | pr_err_ratelimited("kvm: disabled by bios\n"); |
56c6d28a ZX |
8175 | r = -EOPNOTSUPP; |
8176 | goto out; | |
f8c16bba ZX |
8177 | } |
8178 | ||
b666a4b6 MO |
8179 | /* |
8180 | * KVM explicitly assumes that the guest has an FPU and | |
8181 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
8182 | * vCPU's FPU state as a fxregs_state struct. | |
8183 | */ | |
8184 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
8185 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
8186 | r = -EOPNOTSUPP; | |
8187 | goto out; | |
8188 | } | |
8189 | ||
013f6a5d | 8190 | r = -ENOMEM; |
ed8e4812 | 8191 | x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), |
b666a4b6 MO |
8192 | __alignof__(struct fpu), SLAB_ACCOUNT, |
8193 | NULL); | |
8194 | if (!x86_fpu_cache) { | |
8195 | printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); | |
8196 | goto out; | |
8197 | } | |
8198 | ||
c9b8b07c SC |
8199 | x86_emulator_cache = kvm_alloc_emulator_cache(); |
8200 | if (!x86_emulator_cache) { | |
8201 | pr_err("kvm: failed to allocate cache for x86 emulator\n"); | |
8202 | goto out_free_x86_fpu_cache; | |
8203 | } | |
8204 | ||
7e34fbd0 SC |
8205 | user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); |
8206 | if (!user_return_msrs) { | |
8207 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); | |
c9b8b07c | 8208 | goto out_free_x86_emulator_cache; |
013f6a5d | 8209 | } |
e5fda4bb | 8210 | kvm_nr_uret_msrs = 0; |
013f6a5d | 8211 | |
97db56ce AK |
8212 | r = kvm_mmu_module_init(); |
8213 | if (r) | |
013f6a5d | 8214 | goto out_free_percpu; |
97db56ce | 8215 | |
b820cc0c | 8216 | kvm_timer_init(); |
c8076604 | 8217 | |
ff9d07a0 ZY |
8218 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
8219 | ||
cfc48181 | 8220 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
2acf923e | 8221 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
cfc48181 SC |
8222 | supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; |
8223 | } | |
2acf923e | 8224 | |
0c5f81da WL |
8225 | if (pi_inject_timer == -1) |
8226 | pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); | |
16e8d74d MT |
8227 | #ifdef CONFIG_X86_64 |
8228 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 8229 | |
5fa4ec9c | 8230 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 8231 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
8232 | #endif |
8233 | ||
f8c16bba | 8234 | return 0; |
56c6d28a | 8235 | |
013f6a5d | 8236 | out_free_percpu: |
7e34fbd0 | 8237 | free_percpu(user_return_msrs); |
c9b8b07c SC |
8238 | out_free_x86_emulator_cache: |
8239 | kmem_cache_destroy(x86_emulator_cache); | |
b666a4b6 MO |
8240 | out_free_x86_fpu_cache: |
8241 | kmem_cache_destroy(x86_fpu_cache); | |
56c6d28a | 8242 | out: |
56c6d28a | 8243 | return r; |
043405e1 | 8244 | } |
8776e519 | 8245 | |
f8c16bba ZX |
8246 | void kvm_arch_exit(void) |
8247 | { | |
0092e434 | 8248 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 8249 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
8250 | clear_hv_tscchange_cb(); |
8251 | #endif | |
cef84c30 | 8252 | kvm_lapic_exit(); |
ff9d07a0 ZY |
8253 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
8254 | ||
888d256e JK |
8255 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
8256 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
8257 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 8258 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
8259 | #ifdef CONFIG_X86_64 |
8260 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
3f804f6d | 8261 | irq_work_sync(&pvclock_irq_work); |
594b27e6 | 8262 | cancel_work_sync(&pvclock_gtod_work); |
16e8d74d | 8263 | #endif |
afaf0b2f | 8264 | kvm_x86_ops.hardware_enable = NULL; |
56c6d28a | 8265 | kvm_mmu_module_exit(); |
7e34fbd0 | 8266 | free_percpu(user_return_msrs); |
dfdc0a71 | 8267 | kmem_cache_destroy(x86_emulator_cache); |
b666a4b6 | 8268 | kmem_cache_destroy(x86_fpu_cache); |
b59b153d | 8269 | #ifdef CONFIG_KVM_XEN |
c462f859 | 8270 | static_key_deferred_flush(&kvm_xen_enabled); |
7d6bbebb | 8271 | WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); |
b59b153d | 8272 | #endif |
56c6d28a | 8273 | } |
f8c16bba | 8274 | |
872f36eb | 8275 | static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) |
8776e519 HB |
8276 | { |
8277 | ++vcpu->stat.halt_exits; | |
35754c98 | 8278 | if (lapic_in_kernel(vcpu)) { |
647daca2 | 8279 | vcpu->arch.mp_state = state; |
8776e519 HB |
8280 | return 1; |
8281 | } else { | |
647daca2 | 8282 | vcpu->run->exit_reason = reason; |
8776e519 HB |
8283 | return 0; |
8284 | } | |
8285 | } | |
647daca2 TL |
8286 | |
8287 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) | |
8288 | { | |
8289 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); | |
8290 | } | |
5cb56059 JS |
8291 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
8292 | ||
8293 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
8294 | { | |
6affcbed KH |
8295 | int ret = kvm_skip_emulated_instruction(vcpu); |
8296 | /* | |
8297 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
8298 | * KVM_EXIT_DEBUG here. | |
8299 | */ | |
8300 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 8301 | } |
8776e519 HB |
8302 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
8303 | ||
647daca2 TL |
8304 | int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) |
8305 | { | |
8306 | int ret = kvm_skip_emulated_instruction(vcpu); | |
8307 | ||
8308 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; | |
8309 | } | |
8310 | EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); | |
8311 | ||
8ef81a9a | 8312 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8313 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
8314 | unsigned long clock_type) | |
8315 | { | |
8316 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 8317 | struct timespec64 ts; |
80fbd89c | 8318 | u64 cycle; |
55dd00a7 MT |
8319 | int ret; |
8320 | ||
8321 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
8322 | return -KVM_EOPNOTSUPP; | |
8323 | ||
7ca7f3b9 | 8324 | if (!kvm_get_walltime_and_clockread(&ts, &cycle)) |
55dd00a7 MT |
8325 | return -KVM_EOPNOTSUPP; |
8326 | ||
8327 | clock_pairing.sec = ts.tv_sec; | |
8328 | clock_pairing.nsec = ts.tv_nsec; | |
8329 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
8330 | clock_pairing.flags = 0; | |
bcbfbd8e | 8331 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
8332 | |
8333 | ret = 0; | |
8334 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
8335 | sizeof(struct kvm_clock_pairing))) | |
8336 | ret = -KVM_EFAULT; | |
8337 | ||
8338 | return ret; | |
8339 | } | |
8ef81a9a | 8340 | #endif |
55dd00a7 | 8341 | |
6aef266c SV |
8342 | /* |
8343 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
8344 | * | |
8345 | * @apicid - apicid of vcpu to be kicked. | |
8346 | */ | |
8347 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
8348 | { | |
24d2166b | 8349 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 8350 | |
150a84fe | 8351 | lapic_irq.shorthand = APIC_DEST_NOSHORT; |
c96001c5 | 8352 | lapic_irq.dest_mode = APIC_DEST_PHYSICAL; |
ebd28fcb | 8353 | lapic_irq.level = 0; |
24d2166b | 8354 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 8355 | lapic_irq.msi_redir_hint = false; |
6aef266c | 8356 | |
24d2166b | 8357 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 8358 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
8359 | } |
8360 | ||
4e19c36f SS |
8361 | bool kvm_apicv_activated(struct kvm *kvm) |
8362 | { | |
8363 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
8364 | } | |
8365 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
8366 | ||
8367 | void kvm_apicv_init(struct kvm *kvm, bool enable) | |
8368 | { | |
8369 | if (enable) | |
8370 | clear_bit(APICV_INHIBIT_REASON_DISABLE, | |
8371 | &kvm->arch.apicv_inhibit_reasons); | |
8372 | else | |
8373 | set_bit(APICV_INHIBIT_REASON_DISABLE, | |
8374 | &kvm->arch.apicv_inhibit_reasons); | |
8375 | } | |
8376 | EXPORT_SYMBOL_GPL(kvm_apicv_init); | |
8377 | ||
4a7132ef | 8378 | static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) |
71506297 WL |
8379 | { |
8380 | struct kvm_vcpu *target = NULL; | |
8381 | struct kvm_apic_map *map; | |
8382 | ||
4a7132ef WL |
8383 | vcpu->stat.directed_yield_attempted++; |
8384 | ||
72b268a8 WL |
8385 | if (single_task_running()) |
8386 | goto no_yield; | |
8387 | ||
71506297 | 8388 | rcu_read_lock(); |
4a7132ef | 8389 | map = rcu_dereference(vcpu->kvm->arch.apic_map); |
71506297 WL |
8390 | |
8391 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
8392 | target = map->phys_map[dest_id]->vcpu; | |
8393 | ||
8394 | rcu_read_unlock(); | |
8395 | ||
4a7132ef WL |
8396 | if (!target || !READ_ONCE(target->ready)) |
8397 | goto no_yield; | |
8398 | ||
a1fa4cbd WL |
8399 | /* Ignore requests to yield to self */ |
8400 | if (vcpu == target) | |
8401 | goto no_yield; | |
8402 | ||
4a7132ef WL |
8403 | if (kvm_vcpu_yield_to(target) <= 0) |
8404 | goto no_yield; | |
8405 | ||
8406 | vcpu->stat.directed_yield_successful++; | |
8407 | ||
8408 | no_yield: | |
8409 | return; | |
71506297 WL |
8410 | } |
8411 | ||
8776e519 HB |
8412 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
8413 | { | |
8414 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 8415 | int op_64_bit; |
8776e519 | 8416 | |
23200b7a JM |
8417 | if (kvm_xen_hypercall_enabled(vcpu->kvm)) |
8418 | return kvm_xen_hypercall(vcpu); | |
8419 | ||
8f014550 | 8420 | if (kvm_hv_hypercall_enabled(vcpu)) |
696ca779 | 8421 | return kvm_hv_hypercall(vcpu); |
55cd8e5a | 8422 | |
de3cd117 SC |
8423 | nr = kvm_rax_read(vcpu); |
8424 | a0 = kvm_rbx_read(vcpu); | |
8425 | a1 = kvm_rcx_read(vcpu); | |
8426 | a2 = kvm_rdx_read(vcpu); | |
8427 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 8428 | |
229456fc | 8429 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 8430 | |
a449c7aa NA |
8431 | op_64_bit = is_64_bit_mode(vcpu); |
8432 | if (!op_64_bit) { | |
8776e519 HB |
8433 | nr &= 0xFFFFFFFF; |
8434 | a0 &= 0xFFFFFFFF; | |
8435 | a1 &= 0xFFFFFFFF; | |
8436 | a2 &= 0xFFFFFFFF; | |
8437 | a3 &= 0xFFFFFFFF; | |
8438 | } | |
8439 | ||
b3646477 | 8440 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { |
07708c4a | 8441 | ret = -KVM_EPERM; |
696ca779 | 8442 | goto out; |
07708c4a JK |
8443 | } |
8444 | ||
66570e96 OU |
8445 | ret = -KVM_ENOSYS; |
8446 | ||
8776e519 | 8447 | switch (nr) { |
b93463aa AK |
8448 | case KVM_HC_VAPIC_POLL_IRQ: |
8449 | ret = 0; | |
8450 | break; | |
6aef266c | 8451 | case KVM_HC_KICK_CPU: |
66570e96 OU |
8452 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) |
8453 | break; | |
8454 | ||
6aef266c | 8455 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); |
4a7132ef | 8456 | kvm_sched_yield(vcpu, a1); |
6aef266c SV |
8457 | ret = 0; |
8458 | break; | |
8ef81a9a | 8459 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8460 | case KVM_HC_CLOCK_PAIRING: |
8461 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
8462 | break; | |
1ed199a4 | 8463 | #endif |
4180bf1b | 8464 | case KVM_HC_SEND_IPI: |
66570e96 OU |
8465 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) |
8466 | break; | |
8467 | ||
4180bf1b WL |
8468 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); |
8469 | break; | |
71506297 | 8470 | case KVM_HC_SCHED_YIELD: |
66570e96 OU |
8471 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) |
8472 | break; | |
8473 | ||
4a7132ef | 8474 | kvm_sched_yield(vcpu, a0); |
71506297 WL |
8475 | ret = 0; |
8476 | break; | |
8776e519 HB |
8477 | default: |
8478 | ret = -KVM_ENOSYS; | |
8479 | break; | |
8480 | } | |
696ca779 | 8481 | out: |
a449c7aa NA |
8482 | if (!op_64_bit) |
8483 | ret = (u32)ret; | |
de3cd117 | 8484 | kvm_rax_write(vcpu, ret); |
6356ee0c | 8485 | |
f11c3a8d | 8486 | ++vcpu->stat.hypercalls; |
6356ee0c | 8487 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
8488 | } |
8489 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
8490 | ||
b6785def | 8491 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 8492 | { |
d6aa1000 | 8493 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 8494 | char instruction[3]; |
5fdbf976 | 8495 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 8496 | |
b3646477 | 8497 | static_call(kvm_x86_patch_hypercall)(vcpu, instruction); |
8776e519 | 8498 | |
ce2e852e DV |
8499 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
8500 | &ctxt->exception); | |
8776e519 HB |
8501 | } |
8502 | ||
851ba692 | 8503 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8504 | { |
782d422b MG |
8505 | return vcpu->run->request_interrupt_window && |
8506 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
8507 | } |
8508 | ||
851ba692 | 8509 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8510 | { |
851ba692 AK |
8511 | struct kvm_run *kvm_run = vcpu->run; |
8512 | ||
f1c6366e TL |
8513 | /* |
8514 | * if_flag is obsolete and useless, so do not bother | |
8515 | * setting it for SEV-ES guests. Userspace can just | |
8516 | * use kvm_run->ready_for_interrupt_injection. | |
8517 | */ | |
8518 | kvm_run->if_flag = !vcpu->arch.guest_state_protected | |
8519 | && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; | |
8520 | ||
2d3ad1f4 | 8521 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 8522 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
8523 | kvm_run->ready_for_interrupt_injection = |
8524 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 8525 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
15aad3be CQ |
8526 | |
8527 | if (is_smm(vcpu)) | |
8528 | kvm_run->flags |= KVM_RUN_X86_SMM; | |
b6c7a5dc HB |
8529 | } |
8530 | ||
95ba8273 GN |
8531 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
8532 | { | |
8533 | int max_irr, tpr; | |
8534 | ||
afaf0b2f | 8535 | if (!kvm_x86_ops.update_cr8_intercept) |
95ba8273 GN |
8536 | return; |
8537 | ||
bce87cce | 8538 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
8539 | return; |
8540 | ||
d62caabb AS |
8541 | if (vcpu->arch.apicv_active) |
8542 | return; | |
8543 | ||
8db3baa2 GN |
8544 | if (!vcpu->arch.apic->vapic_addr) |
8545 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
8546 | else | |
8547 | max_irr = -1; | |
95ba8273 GN |
8548 | |
8549 | if (max_irr != -1) | |
8550 | max_irr >>= 4; | |
8551 | ||
8552 | tpr = kvm_lapic_get_cr8(vcpu); | |
8553 | ||
b3646477 | 8554 | static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); |
95ba8273 GN |
8555 | } |
8556 | ||
b97f0745 | 8557 | |
cb6a32c2 SC |
8558 | int kvm_check_nested_events(struct kvm_vcpu *vcpu) |
8559 | { | |
8560 | if (WARN_ON_ONCE(!is_guest_mode(vcpu))) | |
8561 | return -EIO; | |
8562 | ||
8563 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { | |
8564 | kvm_x86_ops.nested_ops->triple_fault(vcpu); | |
8565 | return 1; | |
8566 | } | |
8567 | ||
8568 | return kvm_x86_ops.nested_ops->check_events(vcpu); | |
8569 | } | |
8570 | ||
b97f0745 ML |
8571 | static void kvm_inject_exception(struct kvm_vcpu *vcpu) |
8572 | { | |
8573 | if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) | |
8574 | vcpu->arch.exception.error_code = false; | |
8575 | static_call(kvm_x86_queue_exception)(vcpu); | |
8576 | } | |
8577 | ||
c9d40913 | 8578 | static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) |
95ba8273 | 8579 | { |
b6b8a145 | 8580 | int r; |
c6b22f59 | 8581 | bool can_inject = true; |
b6b8a145 | 8582 | |
95ba8273 | 8583 | /* try to reinject previous events if any */ |
664f8e26 | 8584 | |
c6b22f59 | 8585 | if (vcpu->arch.exception.injected) { |
b97f0745 | 8586 | kvm_inject_exception(vcpu); |
c6b22f59 PB |
8587 | can_inject = false; |
8588 | } | |
664f8e26 | 8589 | /* |
a042c26f LA |
8590 | * Do not inject an NMI or interrupt if there is a pending |
8591 | * exception. Exceptions and interrupts are recognized at | |
8592 | * instruction boundaries, i.e. the start of an instruction. | |
8593 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
8594 | * NMIs and interrupts, i.e. traps are recognized before an | |
8595 | * NMI/interrupt that's pending on the same instruction. | |
8596 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
8597 | * priority, but are only generated (pended) during instruction | |
8598 | * execution, i.e. a pending fault-like exception means the | |
8599 | * fault occurred on the *previous* instruction and must be | |
8600 | * serviced prior to recognizing any new events in order to | |
8601 | * fully complete the previous instruction. | |
664f8e26 | 8602 | */ |
1a680e35 | 8603 | else if (!vcpu->arch.exception.pending) { |
c6b22f59 | 8604 | if (vcpu->arch.nmi_injected) { |
b3646477 | 8605 | static_call(kvm_x86_set_nmi)(vcpu); |
c6b22f59 PB |
8606 | can_inject = false; |
8607 | } else if (vcpu->arch.interrupt.injected) { | |
b3646477 | 8608 | static_call(kvm_x86_set_irq)(vcpu); |
c6b22f59 PB |
8609 | can_inject = false; |
8610 | } | |
664f8e26 WL |
8611 | } |
8612 | ||
3b82b8d7 SC |
8613 | WARN_ON_ONCE(vcpu->arch.exception.injected && |
8614 | vcpu->arch.exception.pending); | |
8615 | ||
1a680e35 LA |
8616 | /* |
8617 | * Call check_nested_events() even if we reinjected a previous event | |
8618 | * in order for caller to determine if it should require immediate-exit | |
8619 | * from L2 to L1 due to pending L1 events which require exit | |
8620 | * from L2 to L1. | |
8621 | */ | |
56083bdf | 8622 | if (is_guest_mode(vcpu)) { |
cb6a32c2 | 8623 | r = kvm_check_nested_events(vcpu); |
c9d40913 PB |
8624 | if (r < 0) |
8625 | goto busy; | |
664f8e26 WL |
8626 | } |
8627 | ||
8628 | /* try to inject new event if pending */ | |
b59bb7bd | 8629 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
8630 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
8631 | vcpu->arch.exception.has_error_code, | |
8632 | vcpu->arch.exception.error_code); | |
d6e8c854 | 8633 | |
664f8e26 WL |
8634 | vcpu->arch.exception.pending = false; |
8635 | vcpu->arch.exception.injected = true; | |
8636 | ||
d6e8c854 NA |
8637 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
8638 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
8639 | X86_EFLAGS_RF); | |
8640 | ||
f10c729f | 8641 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
f10c729f JM |
8642 | kvm_deliver_exception_payload(vcpu); |
8643 | if (vcpu->arch.dr7 & DR7_GD) { | |
8644 | vcpu->arch.dr7 &= ~DR7_GD; | |
8645 | kvm_update_dr7(vcpu); | |
8646 | } | |
6bdf0662 NA |
8647 | } |
8648 | ||
b97f0745 | 8649 | kvm_inject_exception(vcpu); |
c6b22f59 | 8650 | can_inject = false; |
1a680e35 LA |
8651 | } |
8652 | ||
c9d40913 PB |
8653 | /* |
8654 | * Finally, inject interrupt events. If an event cannot be injected | |
8655 | * due to architectural conditions (e.g. IF=0) a window-open exit | |
8656 | * will re-request KVM_REQ_EVENT. Sometimes however an event is pending | |
8657 | * and can architecturally be injected, but we cannot do it right now: | |
8658 | * an interrupt could have arrived just now and we have to inject it | |
8659 | * as a vmexit, or there could already an event in the queue, which is | |
8660 | * indicated by can_inject. In that case we request an immediate exit | |
8661 | * in order to make progress and get back here for another iteration. | |
8662 | * The kvm_x86_ops hooks communicate this by returning -EBUSY. | |
8663 | */ | |
8664 | if (vcpu->arch.smi_pending) { | |
b3646477 | 8665 | r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 PB |
8666 | if (r < 0) |
8667 | goto busy; | |
8668 | if (r) { | |
8669 | vcpu->arch.smi_pending = false; | |
8670 | ++vcpu->arch.smi_count; | |
8671 | enter_smm(vcpu); | |
8672 | can_inject = false; | |
8673 | } else | |
b3646477 | 8674 | static_call(kvm_x86_enable_smi_window)(vcpu); |
c9d40913 PB |
8675 | } |
8676 | ||
8677 | if (vcpu->arch.nmi_pending) { | |
b3646477 | 8678 | r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 PB |
8679 | if (r < 0) |
8680 | goto busy; | |
8681 | if (r) { | |
8682 | --vcpu->arch.nmi_pending; | |
8683 | vcpu->arch.nmi_injected = true; | |
b3646477 | 8684 | static_call(kvm_x86_set_nmi)(vcpu); |
c9d40913 | 8685 | can_inject = false; |
b3646477 | 8686 | WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); |
c9d40913 PB |
8687 | } |
8688 | if (vcpu->arch.nmi_pending) | |
b3646477 | 8689 | static_call(kvm_x86_enable_nmi_window)(vcpu); |
c9d40913 | 8690 | } |
1a680e35 | 8691 | |
c9d40913 | 8692 | if (kvm_cpu_has_injectable_intr(vcpu)) { |
b3646477 | 8693 | r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; |
c9d40913 PB |
8694 | if (r < 0) |
8695 | goto busy; | |
8696 | if (r) { | |
8697 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); | |
b3646477 JB |
8698 | static_call(kvm_x86_set_irq)(vcpu); |
8699 | WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); | |
c9d40913 PB |
8700 | } |
8701 | if (kvm_cpu_has_injectable_intr(vcpu)) | |
b3646477 | 8702 | static_call(kvm_x86_enable_irq_window)(vcpu); |
95ba8273 | 8703 | } |
ee2cd4b7 | 8704 | |
c9d40913 PB |
8705 | if (is_guest_mode(vcpu) && |
8706 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
8707 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
8708 | *req_immediate_exit = true; | |
8709 | ||
8710 | WARN_ON(vcpu->arch.exception.pending); | |
8711 | return; | |
8712 | ||
8713 | busy: | |
8714 | *req_immediate_exit = true; | |
8715 | return; | |
95ba8273 GN |
8716 | } |
8717 | ||
7460fb4a AK |
8718 | static void process_nmi(struct kvm_vcpu *vcpu) |
8719 | { | |
8720 | unsigned limit = 2; | |
8721 | ||
8722 | /* | |
8723 | * x86 is limited to one NMI running, and one NMI pending after it. | |
8724 | * If an NMI is already in progress, limit further NMIs to just one. | |
8725 | * Otherwise, allow two (and we'll inject the first one immediately). | |
8726 | */ | |
b3646477 | 8727 | if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) |
7460fb4a AK |
8728 | limit = 1; |
8729 | ||
8730 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
8731 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
8732 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8733 | } | |
8734 | ||
ee2cd4b7 | 8735 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
8736 | { |
8737 | u32 flags = 0; | |
8738 | flags |= seg->g << 23; | |
8739 | flags |= seg->db << 22; | |
8740 | flags |= seg->l << 21; | |
8741 | flags |= seg->avl << 20; | |
8742 | flags |= seg->present << 15; | |
8743 | flags |= seg->dpl << 13; | |
8744 | flags |= seg->s << 12; | |
8745 | flags |= seg->type << 8; | |
8746 | return flags; | |
8747 | } | |
8748 | ||
ee2cd4b7 | 8749 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
8750 | { |
8751 | struct kvm_segment seg; | |
8752 | int offset; | |
8753 | ||
8754 | kvm_get_segment(vcpu, &seg, n); | |
8755 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
8756 | ||
8757 | if (n < 3) | |
8758 | offset = 0x7f84 + n * 12; | |
8759 | else | |
8760 | offset = 0x7f2c + (n - 3) * 12; | |
8761 | ||
8762 | put_smstate(u32, buf, offset + 8, seg.base); | |
8763 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 8764 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
8765 | } |
8766 | ||
efbb288a | 8767 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 8768 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
8769 | { |
8770 | struct kvm_segment seg; | |
8771 | int offset; | |
8772 | u16 flags; | |
8773 | ||
8774 | kvm_get_segment(vcpu, &seg, n); | |
8775 | offset = 0x7e00 + n * 16; | |
8776 | ||
ee2cd4b7 | 8777 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
8778 | put_smstate(u16, buf, offset, seg.selector); |
8779 | put_smstate(u16, buf, offset + 2, flags); | |
8780 | put_smstate(u32, buf, offset + 4, seg.limit); | |
8781 | put_smstate(u64, buf, offset + 8, seg.base); | |
8782 | } | |
efbb288a | 8783 | #endif |
660a5d51 | 8784 | |
ee2cd4b7 | 8785 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
8786 | { |
8787 | struct desc_ptr dt; | |
8788 | struct kvm_segment seg; | |
8789 | unsigned long val; | |
8790 | int i; | |
8791 | ||
8792 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
8793 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
8794 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
8795 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
8796 | ||
8797 | for (i = 0; i < 8; i++) | |
27b4a9c4 | 8798 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); |
660a5d51 PB |
8799 | |
8800 | kvm_get_dr(vcpu, 6, &val); | |
8801 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
8802 | kvm_get_dr(vcpu, 7, &val); | |
8803 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
8804 | ||
8805 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
8806 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
8807 | put_smstate(u32, buf, 0x7f64, seg.base); | |
8808 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 8809 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
8810 | |
8811 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
8812 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
8813 | put_smstate(u32, buf, 0x7f80, seg.base); | |
8814 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 8815 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 | 8816 | |
b3646477 | 8817 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
660a5d51 PB |
8818 | put_smstate(u32, buf, 0x7f74, dt.address); |
8819 | put_smstate(u32, buf, 0x7f70, dt.size); | |
8820 | ||
b3646477 | 8821 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
660a5d51 PB |
8822 | put_smstate(u32, buf, 0x7f58, dt.address); |
8823 | put_smstate(u32, buf, 0x7f54, dt.size); | |
8824 | ||
8825 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 8826 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
8827 | |
8828 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
8829 | ||
8830 | /* revision id */ | |
8831 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
8832 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
8833 | } | |
8834 | ||
b68f3cc7 | 8835 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 8836 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 8837 | { |
660a5d51 PB |
8838 | struct desc_ptr dt; |
8839 | struct kvm_segment seg; | |
8840 | unsigned long val; | |
8841 | int i; | |
8842 | ||
8843 | for (i = 0; i < 16; i++) | |
27b4a9c4 | 8844 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); |
660a5d51 PB |
8845 | |
8846 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
8847 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
8848 | ||
8849 | kvm_get_dr(vcpu, 6, &val); | |
8850 | put_smstate(u64, buf, 0x7f68, val); | |
8851 | kvm_get_dr(vcpu, 7, &val); | |
8852 | put_smstate(u64, buf, 0x7f60, val); | |
8853 | ||
8854 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
8855 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
8856 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
8857 | ||
8858 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
8859 | ||
8860 | /* revision id */ | |
8861 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
8862 | ||
8863 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
8864 | ||
8865 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
8866 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 8867 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
8868 | put_smstate(u32, buf, 0x7e94, seg.limit); |
8869 | put_smstate(u64, buf, 0x7e98, seg.base); | |
8870 | ||
b3646477 | 8871 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
660a5d51 PB |
8872 | put_smstate(u32, buf, 0x7e84, dt.size); |
8873 | put_smstate(u64, buf, 0x7e88, dt.address); | |
8874 | ||
8875 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
8876 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 8877 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
8878 | put_smstate(u32, buf, 0x7e74, seg.limit); |
8879 | put_smstate(u64, buf, 0x7e78, seg.base); | |
8880 | ||
b3646477 | 8881 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
660a5d51 PB |
8882 | put_smstate(u32, buf, 0x7e64, dt.size); |
8883 | put_smstate(u64, buf, 0x7e68, dt.address); | |
8884 | ||
8885 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 8886 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 8887 | } |
b68f3cc7 | 8888 | #endif |
660a5d51 | 8889 | |
ee2cd4b7 | 8890 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 8891 | { |
660a5d51 | 8892 | struct kvm_segment cs, ds; |
18c3626e | 8893 | struct desc_ptr dt; |
660a5d51 PB |
8894 | char buf[512]; |
8895 | u32 cr0; | |
8896 | ||
660a5d51 | 8897 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); |
660a5d51 | 8898 | memset(buf, 0, 512); |
b68f3cc7 | 8899 | #ifdef CONFIG_X86_64 |
d6321d49 | 8900 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 8901 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 8902 | else |
b68f3cc7 | 8903 | #endif |
ee2cd4b7 | 8904 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 8905 | |
0234bf88 LP |
8906 | /* |
8907 | * Give pre_enter_smm() a chance to make ISA-specific changes to the | |
8908 | * vCPU state (e.g. leave guest mode) after we've saved the state into | |
8909 | * the SMM state-save area. | |
8910 | */ | |
b3646477 | 8911 | static_call(kvm_x86_pre_enter_smm)(vcpu, buf); |
0234bf88 LP |
8912 | |
8913 | vcpu->arch.hflags |= HF_SMM_MASK; | |
54bf36aa | 8914 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 | 8915 | |
b3646477 | 8916 | if (static_call(kvm_x86_get_nmi_mask)(vcpu)) |
660a5d51 PB |
8917 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; |
8918 | else | |
b3646477 | 8919 | static_call(kvm_x86_set_nmi_mask)(vcpu, true); |
660a5d51 PB |
8920 | |
8921 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
8922 | kvm_rip_write(vcpu, 0x8000); | |
8923 | ||
8924 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
b3646477 | 8925 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
660a5d51 PB |
8926 | vcpu->arch.cr0 = cr0; |
8927 | ||
b3646477 | 8928 | static_call(kvm_x86_set_cr4)(vcpu, 0); |
660a5d51 | 8929 | |
18c3626e PB |
8930 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
8931 | dt.address = dt.size = 0; | |
b3646477 | 8932 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
18c3626e | 8933 | |
996ff542 | 8934 | kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
660a5d51 PB |
8935 | |
8936 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
8937 | cs.base = vcpu->arch.smbase; | |
8938 | ||
8939 | ds.selector = 0; | |
8940 | ds.base = 0; | |
8941 | ||
8942 | cs.limit = ds.limit = 0xffffffff; | |
8943 | cs.type = ds.type = 0x3; | |
8944 | cs.dpl = ds.dpl = 0; | |
8945 | cs.db = ds.db = 0; | |
8946 | cs.s = ds.s = 1; | |
8947 | cs.l = ds.l = 0; | |
8948 | cs.g = ds.g = 1; | |
8949 | cs.avl = ds.avl = 0; | |
8950 | cs.present = ds.present = 1; | |
8951 | cs.unusable = ds.unusable = 0; | |
8952 | cs.padding = ds.padding = 0; | |
8953 | ||
8954 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
8955 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
8956 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
8957 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
8958 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
8959 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
8960 | ||
b68f3cc7 | 8961 | #ifdef CONFIG_X86_64 |
d6321d49 | 8962 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
b3646477 | 8963 | static_call(kvm_x86_set_efer)(vcpu, 0); |
b68f3cc7 | 8964 | #endif |
660a5d51 | 8965 | |
aedbaf4f | 8966 | kvm_update_cpuid_runtime(vcpu); |
660a5d51 | 8967 | kvm_mmu_reset_context(vcpu); |
64d60670 PB |
8968 | } |
8969 | ||
ee2cd4b7 | 8970 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
8971 | { |
8972 | vcpu->arch.smi_pending = true; | |
8973 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8974 | } | |
8975 | ||
7ee30bc1 NNL |
8976 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
8977 | unsigned long *vcpu_bitmap) | |
8978 | { | |
8979 | cpumask_var_t cpus; | |
7ee30bc1 NNL |
8980 | |
8981 | zalloc_cpumask_var(&cpus, GFP_ATOMIC); | |
8982 | ||
db5a95ec | 8983 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, |
54163a34 | 8984 | NULL, vcpu_bitmap, cpus); |
7ee30bc1 NNL |
8985 | |
8986 | free_cpumask_var(cpus); | |
8987 | } | |
8988 | ||
2860c4b1 PB |
8989 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
8990 | { | |
8991 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
8992 | } | |
8993 | ||
8df14af4 SS |
8994 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
8995 | { | |
8996 | if (!lapic_in_kernel(vcpu)) | |
8997 | return; | |
8998 | ||
8999 | vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); | |
9000 | kvm_apic_update_apicv(vcpu); | |
b3646477 | 9001 | static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); |
8df14af4 SS |
9002 | } |
9003 | EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); | |
9004 | ||
9005 | /* | |
9006 | * NOTE: Do not hold any lock prior to calling this. | |
9007 | * | |
9008 | * In particular, kvm_request_apicv_update() expects kvm->srcu not to be | |
9009 | * locked, because it calls __x86_set_memory_region() which does | |
9010 | * synchronize_srcu(&kvm->srcu). | |
9011 | */ | |
9012 | void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) | |
9013 | { | |
7d611233 | 9014 | struct kvm_vcpu *except; |
8e205a6b PB |
9015 | unsigned long old, new, expected; |
9016 | ||
afaf0b2f | 9017 | if (!kvm_x86_ops.check_apicv_inhibit_reasons || |
b3646477 | 9018 | !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) |
ef8efd7a SS |
9019 | return; |
9020 | ||
8e205a6b PB |
9021 | old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); |
9022 | do { | |
9023 | expected = new = old; | |
9024 | if (activate) | |
9025 | __clear_bit(bit, &new); | |
9026 | else | |
9027 | __set_bit(bit, &new); | |
9028 | if (new == old) | |
9029 | break; | |
9030 | old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); | |
9031 | } while (old != expected); | |
9032 | ||
9033 | if (!!old == !!new) | |
9034 | return; | |
8df14af4 | 9035 | |
24bbf74c | 9036 | trace_kvm_apicv_update_request(activate, bit); |
afaf0b2f | 9037 | if (kvm_x86_ops.pre_update_apicv_exec_ctrl) |
b3646477 | 9038 | static_call(kvm_x86_pre_update_apicv_exec_ctrl)(kvm, activate); |
7d611233 SS |
9039 | |
9040 | /* | |
9041 | * Sending request to update APICV for all other vcpus, | |
9042 | * while update the calling vcpu immediately instead of | |
9043 | * waiting for another #VMEXIT to handle the request. | |
9044 | */ | |
9045 | except = kvm_get_running_vcpu(); | |
9046 | kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE, | |
9047 | except); | |
9048 | if (except) | |
9049 | kvm_vcpu_update_apicv(except); | |
8df14af4 SS |
9050 | } |
9051 | EXPORT_SYMBOL_GPL(kvm_request_apicv_update); | |
9052 | ||
3d81bc7e | 9053 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 9054 | { |
dcbd3e49 | 9055 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 9056 | return; |
c7c9c56c | 9057 | |
6308630b | 9058 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 9059 | |
b053b2ae | 9060 | if (irqchip_split(vcpu->kvm)) |
6308630b | 9061 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 9062 | else { |
fa59cc00 | 9063 | if (vcpu->arch.apicv_active) |
b3646477 | 9064 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
e97f852f WL |
9065 | if (ioapic_in_kernel(vcpu->kvm)) |
9066 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 9067 | } |
e40ff1d6 LA |
9068 | |
9069 | if (is_guest_mode(vcpu)) | |
9070 | vcpu->arch.load_eoi_exitmap_pending = true; | |
9071 | else | |
9072 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
9073 | } | |
9074 | ||
9075 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
9076 | { | |
9077 | u64 eoi_exit_bitmap[4]; | |
9078 | ||
9079 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
9080 | return; | |
9081 | ||
f2bc14b6 VK |
9082 | if (to_hv_vcpu(vcpu)) |
9083 | bitmap_or((ulong *)eoi_exit_bitmap, | |
9084 | vcpu->arch.ioapic_handled_vectors, | |
9085 | to_hv_synic(vcpu)->vec_bitmap, 256); | |
9086 | ||
b3646477 | 9087 | static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); |
c7c9c56c YZ |
9088 | } |
9089 | ||
e649b3f0 ET |
9090 | void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
9091 | unsigned long start, unsigned long end) | |
b1394e74 RK |
9092 | { |
9093 | unsigned long apic_address; | |
9094 | ||
9095 | /* | |
9096 | * The physical address of apic access page is stored in the VMCS. | |
9097 | * Update it when it becomes invalid. | |
9098 | */ | |
9099 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
9100 | if (start <= apic_address && apic_address < end) | |
9101 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
9102 | } | |
9103 | ||
4256f43f TC |
9104 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
9105 | { | |
35754c98 | 9106 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
9107 | return; |
9108 | ||
afaf0b2f | 9109 | if (!kvm_x86_ops.set_apic_access_page_addr) |
4256f43f TC |
9110 | return; |
9111 | ||
b3646477 | 9112 | static_call(kvm_x86_set_apic_access_page_addr)(vcpu); |
4256f43f | 9113 | } |
4256f43f | 9114 | |
d264ee0c SC |
9115 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
9116 | { | |
9117 | smp_send_reschedule(vcpu->cpu); | |
9118 | } | |
9119 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
9120 | ||
9357d939 | 9121 | /* |
362c698f | 9122 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
9123 | * exiting to the userspace. Otherwise, the value will be returned to the |
9124 | * userspace. | |
9125 | */ | |
851ba692 | 9126 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
9127 | { |
9128 | int r; | |
62a193ed MG |
9129 | bool req_int_win = |
9130 | dm_request_for_irq_injection(vcpu) && | |
9131 | kvm_cpu_accept_dm_intr(vcpu); | |
404d5d7b | 9132 | fastpath_t exit_fastpath; |
62a193ed | 9133 | |
730dca42 | 9134 | bool req_immediate_exit = false; |
b6c7a5dc | 9135 | |
fb04a1ed PX |
9136 | /* Forbid vmenter if vcpu dirty ring is soft-full */ |
9137 | if (unlikely(vcpu->kvm->dirty_ring_size && | |
9138 | kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { | |
9139 | vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; | |
9140 | trace_kvm_dirty_ring_exit(vcpu); | |
9141 | r = 0; | |
9142 | goto out; | |
9143 | } | |
9144 | ||
2fa6e1e1 | 9145 | if (kvm_request_pending(vcpu)) { |
729c15c2 | 9146 | if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { |
9a78e158 | 9147 | if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { |
671ddc70 JM |
9148 | r = 0; |
9149 | goto out; | |
9150 | } | |
9151 | } | |
a8eeb04a | 9152 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 9153 | kvm_mmu_unload(vcpu); |
a8eeb04a | 9154 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 9155 | __kvm_migrate_timers(vcpu); |
d828199e MT |
9156 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
9157 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
9158 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
9159 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
9160 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
9161 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
9162 | if (unlikely(r)) |
9163 | goto out; | |
9164 | } | |
a8eeb04a | 9165 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 9166 | kvm_mmu_sync_roots(vcpu); |
727a7e27 PB |
9167 | if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) |
9168 | kvm_mmu_load_pgd(vcpu); | |
eeeb4f67 | 9169 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { |
7780938c | 9170 | kvm_vcpu_flush_tlb_all(vcpu); |
eeeb4f67 SC |
9171 | |
9172 | /* Flushing all ASIDs flushes the current ASID... */ | |
9173 | kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
9174 | } | |
9175 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) | |
9176 | kvm_vcpu_flush_tlb_current(vcpu); | |
0baedd79 VK |
9177 | if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu)) |
9178 | kvm_vcpu_flush_tlb_guest(vcpu); | |
eeeb4f67 | 9179 | |
a8eeb04a | 9180 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 9181 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
9182 | r = 0; |
9183 | goto out; | |
9184 | } | |
a8eeb04a | 9185 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
cb6a32c2 SC |
9186 | if (is_guest_mode(vcpu)) { |
9187 | kvm_x86_ops.nested_ops->triple_fault(vcpu); | |
9188 | } else { | |
9189 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; | |
9190 | vcpu->mmio_needed = 0; | |
9191 | r = 0; | |
9192 | goto out; | |
9193 | } | |
71c4dfaf | 9194 | } |
af585b92 GN |
9195 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
9196 | /* Page is swapped out. Do synthetic halt */ | |
9197 | vcpu->arch.apf.halted = true; | |
9198 | r = 1; | |
9199 | goto out; | |
9200 | } | |
c9aaa895 GC |
9201 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
9202 | record_steal_time(vcpu); | |
64d60670 PB |
9203 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
9204 | process_smi(vcpu); | |
7460fb4a AK |
9205 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
9206 | process_nmi(vcpu); | |
f5132b01 | 9207 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 9208 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 9209 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 9210 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
9211 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
9212 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
9213 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 9214 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
9215 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
9216 | vcpu->run->eoi.vector = | |
9217 | vcpu->arch.pending_ioapic_eoi; | |
9218 | r = 0; | |
9219 | goto out; | |
9220 | } | |
9221 | } | |
3d81bc7e YZ |
9222 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
9223 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
9224 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
9225 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
9226 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
9227 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
9228 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
9229 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
9230 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
9231 | r = 0; | |
9232 | goto out; | |
9233 | } | |
e516cebb AS |
9234 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
9235 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
9236 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
9237 | r = 0; | |
9238 | goto out; | |
9239 | } | |
db397571 | 9240 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
9ff5e030 VK |
9241 | struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); |
9242 | ||
db397571 | 9243 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; |
9ff5e030 | 9244 | vcpu->run->hyperv = hv_vcpu->exit; |
db397571 AS |
9245 | r = 0; |
9246 | goto out; | |
9247 | } | |
f3b138c5 AS |
9248 | |
9249 | /* | |
9250 | * KVM_REQ_HV_STIMER has to be processed after | |
9251 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
9252 | * depend on the guest clock being up-to-date | |
9253 | */ | |
1f4b34f8 AS |
9254 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
9255 | kvm_hv_process_stimers(vcpu); | |
8df14af4 SS |
9256 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
9257 | kvm_vcpu_update_apicv(vcpu); | |
557a961a VK |
9258 | if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) |
9259 | kvm_check_async_pf_completion(vcpu); | |
1a155254 | 9260 | if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) |
b3646477 | 9261 | static_call(kvm_x86_msr_filter_changed)(vcpu); |
a85863c2 MS |
9262 | |
9263 | if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) | |
9264 | static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); | |
2f52d58c | 9265 | } |
b93463aa | 9266 | |
40da8ccd DW |
9267 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || |
9268 | kvm_xen_has_interrupt(vcpu)) { | |
0f1e261e | 9269 | ++vcpu->stat.req_event; |
66450a21 JK |
9270 | kvm_apic_accept_events(vcpu); |
9271 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
9272 | r = 1; | |
9273 | goto out; | |
9274 | } | |
9275 | ||
c9d40913 PB |
9276 | inject_pending_event(vcpu, &req_immediate_exit); |
9277 | if (req_int_win) | |
b3646477 | 9278 | static_call(kvm_x86_enable_irq_window)(vcpu); |
b463a6f7 AK |
9279 | |
9280 | if (kvm_lapic_enabled(vcpu)) { | |
9281 | update_cr8_intercept(vcpu); | |
9282 | kvm_lapic_sync_to_vapic(vcpu); | |
9283 | } | |
9284 | } | |
9285 | ||
d8368af8 AK |
9286 | r = kvm_mmu_reload(vcpu); |
9287 | if (unlikely(r)) { | |
d905c069 | 9288 | goto cancel_injection; |
d8368af8 AK |
9289 | } |
9290 | ||
b6c7a5dc HB |
9291 | preempt_disable(); |
9292 | ||
b3646477 | 9293 | static_call(kvm_x86_prepare_guest_switch)(vcpu); |
b95234c8 PB |
9294 | |
9295 | /* | |
9296 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
9297 | * IPI are then delayed after guest entry, which ensures that they | |
9298 | * result in virtual interrupt delivery. | |
9299 | */ | |
9300 | local_irq_disable(); | |
6b7e2d09 XG |
9301 | vcpu->mode = IN_GUEST_MODE; |
9302 | ||
01b71917 MT |
9303 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
9304 | ||
0f127d12 | 9305 | /* |
b95234c8 | 9306 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 9307 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 9308 | * |
81b01667 | 9309 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
9310 | * pairs with the memory barrier implicit in pi_test_and_set_on |
9311 | * (see vmx_deliver_posted_interrupt). | |
9312 | * | |
9313 | * 3) This also orders the write to mode from any reads to the page | |
9314 | * tables done while the VCPU is running. Please see the comment | |
9315 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 9316 | */ |
01b71917 | 9317 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 9318 | |
b95234c8 PB |
9319 | /* |
9320 | * This handles the case where a posted interrupt was | |
9321 | * notified with kvm_vcpu_kick. | |
9322 | */ | |
fa59cc00 | 9323 | if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) |
b3646477 | 9324 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
32f88400 | 9325 | |
5a9f5443 | 9326 | if (kvm_vcpu_exit_request(vcpu)) { |
6b7e2d09 | 9327 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9328 | smp_wmb(); |
6c142801 AK |
9329 | local_irq_enable(); |
9330 | preempt_enable(); | |
01b71917 | 9331 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 9332 | r = 1; |
d905c069 | 9333 | goto cancel_injection; |
6c142801 AK |
9334 | } |
9335 | ||
c43203ca PB |
9336 | if (req_immediate_exit) { |
9337 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 9338 | static_call(kvm_x86_request_immediate_exit)(vcpu); |
c43203ca | 9339 | } |
d6185f20 | 9340 | |
2620fe26 SC |
9341 | fpregs_assert_state_consistent(); |
9342 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9343 | switch_fpu_return(); | |
5f409e20 | 9344 | |
42dbaa5a | 9345 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
9346 | set_debugreg(0, 7); |
9347 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
9348 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
9349 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
9350 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 9351 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 9352 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 9353 | } |
b6c7a5dc | 9354 | |
d89d04ab PB |
9355 | for (;;) { |
9356 | exit_fastpath = static_call(kvm_x86_run)(vcpu); | |
9357 | if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) | |
9358 | break; | |
9359 | ||
9360 | if (unlikely(kvm_vcpu_exit_request(vcpu))) { | |
9361 | exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; | |
9362 | break; | |
9363 | } | |
9364 | ||
9365 | if (vcpu->arch.apicv_active) | |
9366 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); | |
9367 | } | |
b6c7a5dc | 9368 | |
c77fb5fe PB |
9369 | /* |
9370 | * Do this here before restoring debug registers on the host. And | |
9371 | * since we do this before handling the vmexit, a DR access vmexit | |
9372 | * can (a) read the correct value of the debug registers, (b) set | |
9373 | * KVM_DEBUGREG_WONT_EXIT again. | |
9374 | */ | |
9375 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe | 9376 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
b3646477 | 9377 | static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); |
70e4da7a | 9378 | kvm_update_dr0123(vcpu); |
70e4da7a PB |
9379 | kvm_update_dr7(vcpu); |
9380 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; | |
c77fb5fe PB |
9381 | } |
9382 | ||
24f1e32c FW |
9383 | /* |
9384 | * If the guest has used debug registers, at least dr7 | |
9385 | * will be disabled while returning to the host. | |
9386 | * If we don't have active breakpoints in the host, we don't | |
9387 | * care about the messed up debug address registers. But if | |
9388 | * we have some of them active, restore the old state. | |
9389 | */ | |
59d8eb53 | 9390 | if (hw_breakpoint_active()) |
24f1e32c | 9391 | hw_breakpoint_restore(); |
42dbaa5a | 9392 | |
c967118d | 9393 | vcpu->arch.last_vmentry_cpu = vcpu->cpu; |
4ba76538 | 9394 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 9395 | |
6b7e2d09 | 9396 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9397 | smp_wmb(); |
a547c6db | 9398 | |
b3646477 | 9399 | static_call(kvm_x86_handle_exit_irqoff)(vcpu); |
b6c7a5dc | 9400 | |
d7a08882 SC |
9401 | /* |
9402 | * Consume any pending interrupts, including the possible source of | |
9403 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
9404 | * An instruction is required after local_irq_enable() to fully unblock | |
9405 | * interrupts on processors that implement an interrupt shadow, the | |
9406 | * stat.exits increment will do nicely. | |
9407 | */ | |
9408 | kvm_before_interrupt(vcpu); | |
9409 | local_irq_enable(); | |
b6c7a5dc | 9410 | ++vcpu->stat.exits; |
d7a08882 SC |
9411 | local_irq_disable(); |
9412 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 9413 | |
16045714 WL |
9414 | /* |
9415 | * Wait until after servicing IRQs to account guest time so that any | |
9416 | * ticks that occurred while running the guest are properly accounted | |
9417 | * to the guest. Waiting until IRQs are enabled degrades the accuracy | |
9418 | * of accounting via context tracking, but the loss of accuracy is | |
9419 | * acceptable for all known use cases. | |
9420 | */ | |
9421 | vtime_account_guest_exit(); | |
9422 | ||
ec0671d5 WL |
9423 | if (lapic_in_kernel(vcpu)) { |
9424 | s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; | |
9425 | if (delta != S64_MIN) { | |
9426 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); | |
9427 | vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; | |
9428 | } | |
9429 | } | |
b6c7a5dc | 9430 | |
f2485b3e | 9431 | local_irq_enable(); |
b6c7a5dc HB |
9432 | preempt_enable(); |
9433 | ||
f656ce01 | 9434 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 9435 | |
b6c7a5dc HB |
9436 | /* |
9437 | * Profile KVM exit RIPs: | |
9438 | */ | |
9439 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
9440 | unsigned long rip = kvm_rip_read(vcpu); |
9441 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
9442 | } |
9443 | ||
cc578287 ZA |
9444 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
9445 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 9446 | |
5cfb1d5a MT |
9447 | if (vcpu->arch.apic_attention) |
9448 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 9449 | |
b3646477 | 9450 | r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); |
d905c069 MT |
9451 | return r; |
9452 | ||
9453 | cancel_injection: | |
8081ad06 SC |
9454 | if (req_immediate_exit) |
9455 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 9456 | static_call(kvm_x86_cancel_injection)(vcpu); |
ae7a2a3f MT |
9457 | if (unlikely(vcpu->arch.apic_attention)) |
9458 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
9459 | out: |
9460 | return r; | |
9461 | } | |
b6c7a5dc | 9462 | |
362c698f PB |
9463 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
9464 | { | |
bf9f6ac8 | 9465 | if (!kvm_arch_vcpu_runnable(vcpu) && |
b3646477 | 9466 | (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { |
9c8fd1ba PB |
9467 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
9468 | kvm_vcpu_block(vcpu); | |
9469 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 | 9470 | |
afaf0b2f | 9471 | if (kvm_x86_ops.post_block) |
b3646477 | 9472 | static_call(kvm_x86_post_block)(vcpu); |
bf9f6ac8 | 9473 | |
9c8fd1ba PB |
9474 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
9475 | return 1; | |
9476 | } | |
362c698f PB |
9477 | |
9478 | kvm_apic_accept_events(vcpu); | |
9479 | switch(vcpu->arch.mp_state) { | |
9480 | case KVM_MP_STATE_HALTED: | |
647daca2 | 9481 | case KVM_MP_STATE_AP_RESET_HOLD: |
362c698f PB |
9482 | vcpu->arch.pv.pv_unhalted = false; |
9483 | vcpu->arch.mp_state = | |
9484 | KVM_MP_STATE_RUNNABLE; | |
df561f66 | 9485 | fallthrough; |
362c698f PB |
9486 | case KVM_MP_STATE_RUNNABLE: |
9487 | vcpu->arch.apf.halted = false; | |
9488 | break; | |
9489 | case KVM_MP_STATE_INIT_RECEIVED: | |
9490 | break; | |
9491 | default: | |
9492 | return -EINTR; | |
362c698f PB |
9493 | } |
9494 | return 1; | |
9495 | } | |
09cec754 | 9496 | |
5d9bc648 PB |
9497 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
9498 | { | |
56083bdf | 9499 | if (is_guest_mode(vcpu)) |
cb6a32c2 | 9500 | kvm_check_nested_events(vcpu); |
0ad3bed6 | 9501 | |
5d9bc648 PB |
9502 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
9503 | !vcpu->arch.apf.halted); | |
9504 | } | |
9505 | ||
362c698f | 9506 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
9507 | { |
9508 | int r; | |
f656ce01 | 9509 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 9510 | |
f656ce01 | 9511 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
c595ceee | 9512 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 9513 | |
362c698f | 9514 | for (;;) { |
58f800d5 | 9515 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 9516 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 9517 | } else { |
362c698f | 9518 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
9519 | } |
9520 | ||
09cec754 GN |
9521 | if (r <= 0) |
9522 | break; | |
9523 | ||
084071d5 | 9524 | kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); |
09cec754 GN |
9525 | if (kvm_cpu_has_pending_timer(vcpu)) |
9526 | kvm_inject_pending_timer_irqs(vcpu); | |
9527 | ||
782d422b MG |
9528 | if (dm_request_for_irq_injection(vcpu) && |
9529 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
9530 | r = 0; |
9531 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 9532 | ++vcpu->stat.request_irq_exits; |
362c698f | 9533 | break; |
09cec754 | 9534 | } |
af585b92 | 9535 | |
f3020b88 | 9536 | if (__xfer_to_guest_mode_work_pending()) { |
f656ce01 | 9537 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
72c3c0fe TG |
9538 | r = xfer_to_guest_mode_handle_work(vcpu); |
9539 | if (r) | |
9540 | return r; | |
f656ce01 | 9541 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 9542 | } |
b6c7a5dc HB |
9543 | } |
9544 | ||
f656ce01 | 9545 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
9546 | |
9547 | return r; | |
9548 | } | |
9549 | ||
716d51ab GN |
9550 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
9551 | { | |
9552 | int r; | |
60fc3d02 | 9553 | |
716d51ab | 9554 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
0ce97a2b | 9555 | r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab | 9556 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
60fc3d02 | 9557 | return r; |
716d51ab GN |
9558 | } |
9559 | ||
9560 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
9561 | { | |
9562 | BUG_ON(!vcpu->arch.pio.count); | |
9563 | ||
9564 | return complete_emulated_io(vcpu); | |
9565 | } | |
9566 | ||
f78146b0 AK |
9567 | /* |
9568 | * Implements the following, as a state machine: | |
9569 | * | |
9570 | * read: | |
9571 | * for each fragment | |
87da7e66 XG |
9572 | * for each mmio piece in the fragment |
9573 | * write gpa, len | |
9574 | * exit | |
9575 | * copy data | |
f78146b0 AK |
9576 | * execute insn |
9577 | * | |
9578 | * write: | |
9579 | * for each fragment | |
87da7e66 XG |
9580 | * for each mmio piece in the fragment |
9581 | * write gpa, len | |
9582 | * copy data | |
9583 | * exit | |
f78146b0 | 9584 | */ |
716d51ab | 9585 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
9586 | { |
9587 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 9588 | struct kvm_mmio_fragment *frag; |
87da7e66 | 9589 | unsigned len; |
5287f194 | 9590 | |
716d51ab | 9591 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 9592 | |
716d51ab | 9593 | /* Complete previous fragment */ |
87da7e66 XG |
9594 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
9595 | len = min(8u, frag->len); | |
716d51ab | 9596 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
9597 | memcpy(frag->data, run->mmio.data, len); |
9598 | ||
9599 | if (frag->len <= 8) { | |
9600 | /* Switch to the next fragment. */ | |
9601 | frag++; | |
9602 | vcpu->mmio_cur_fragment++; | |
9603 | } else { | |
9604 | /* Go forward to the next mmio piece. */ | |
9605 | frag->data += len; | |
9606 | frag->gpa += len; | |
9607 | frag->len -= len; | |
9608 | } | |
9609 | ||
a08d3b3b | 9610 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 9611 | vcpu->mmio_needed = 0; |
0912c977 PB |
9612 | |
9613 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 9614 | if (vcpu->mmio_is_write) |
716d51ab GN |
9615 | return 1; |
9616 | vcpu->mmio_read_completed = 1; | |
9617 | return complete_emulated_io(vcpu); | |
9618 | } | |
87da7e66 | 9619 | |
716d51ab GN |
9620 | run->exit_reason = KVM_EXIT_MMIO; |
9621 | run->mmio.phys_addr = frag->gpa; | |
9622 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
9623 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
9624 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
9625 | run->mmio.is_write = vcpu->mmio_is_write; |
9626 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
9627 | return 0; | |
5287f194 AK |
9628 | } |
9629 | ||
c9aef3b8 SC |
9630 | static void kvm_save_current_fpu(struct fpu *fpu) |
9631 | { | |
9632 | /* | |
9633 | * If the target FPU state is not resident in the CPU registers, just | |
9634 | * memcpy() from current, else save CPU state directly to the target. | |
9635 | */ | |
9636 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9637 | memcpy(&fpu->state, ¤t->thread.fpu.state, | |
9638 | fpu_kernel_xstate_size); | |
9639 | else | |
ebe7234b | 9640 | save_fpregs_to_fpstate(fpu); |
c9aef3b8 SC |
9641 | } |
9642 | ||
822f312d SAS |
9643 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
9644 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
9645 | { | |
5f409e20 RR |
9646 | fpregs_lock(); |
9647 | ||
c9aef3b8 SC |
9648 | kvm_save_current_fpu(vcpu->arch.user_fpu); |
9649 | ||
ed02b213 TL |
9650 | /* |
9651 | * Guests with protected state can't have it set by the hypervisor, | |
9652 | * so skip trying to set it. | |
9653 | */ | |
9654 | if (vcpu->arch.guest_fpu) | |
9655 | /* PKRU is separately restored in kvm_x86_ops.run. */ | |
9656 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, | |
9657 | ~XFEATURE_MASK_PKRU); | |
5f409e20 RR |
9658 | |
9659 | fpregs_mark_activate(); | |
9660 | fpregs_unlock(); | |
9661 | ||
822f312d SAS |
9662 | trace_kvm_fpu(1); |
9663 | } | |
9664 | ||
9665 | /* When vcpu_run ends, restore user space FPU context. */ | |
9666 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
9667 | { | |
5f409e20 RR |
9668 | fpregs_lock(); |
9669 | ||
ed02b213 TL |
9670 | /* |
9671 | * Guests with protected state can't have it read by the hypervisor, | |
9672 | * so skip trying to save it. | |
9673 | */ | |
9674 | if (vcpu->arch.guest_fpu) | |
9675 | kvm_save_current_fpu(vcpu->arch.guest_fpu); | |
c9aef3b8 | 9676 | |
d9a710e5 | 9677 | copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); |
5f409e20 RR |
9678 | |
9679 | fpregs_mark_activate(); | |
9680 | fpregs_unlock(); | |
9681 | ||
822f312d SAS |
9682 | ++vcpu->stat.fpu_reload; |
9683 | trace_kvm_fpu(0); | |
9684 | } | |
9685 | ||
1b94f6f8 | 9686 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) |
b6c7a5dc | 9687 | { |
1b94f6f8 | 9688 | struct kvm_run *kvm_run = vcpu->run; |
b6c7a5dc | 9689 | int r; |
b6c7a5dc | 9690 | |
accb757d | 9691 | vcpu_load(vcpu); |
20b7035c | 9692 | kvm_sigset_activate(vcpu); |
15aad3be | 9693 | kvm_run->flags = 0; |
5663d8f9 PX |
9694 | kvm_load_guest_fpu(vcpu); |
9695 | ||
a4535290 | 9696 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
9697 | if (kvm_run->immediate_exit) { |
9698 | r = -EINTR; | |
9699 | goto out; | |
9700 | } | |
b6c7a5dc | 9701 | kvm_vcpu_block(vcpu); |
66450a21 | 9702 | kvm_apic_accept_events(vcpu); |
72875d8a | 9703 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 9704 | r = -EAGAIN; |
a0595000 JS |
9705 | if (signal_pending(current)) { |
9706 | r = -EINTR; | |
1b94f6f8 | 9707 | kvm_run->exit_reason = KVM_EXIT_INTR; |
a0595000 JS |
9708 | ++vcpu->stat.signal_exits; |
9709 | } | |
ac9f6dc0 | 9710 | goto out; |
b6c7a5dc HB |
9711 | } |
9712 | ||
1b94f6f8 | 9713 | if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { |
01643c51 KH |
9714 | r = -EINVAL; |
9715 | goto out; | |
9716 | } | |
9717 | ||
1b94f6f8 | 9718 | if (kvm_run->kvm_dirty_regs) { |
01643c51 KH |
9719 | r = sync_regs(vcpu); |
9720 | if (r != 0) | |
9721 | goto out; | |
9722 | } | |
9723 | ||
b6c7a5dc | 9724 | /* re-sync apic's tpr */ |
35754c98 | 9725 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
9726 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
9727 | r = -EINVAL; | |
9728 | goto out; | |
9729 | } | |
9730 | } | |
b6c7a5dc | 9731 | |
716d51ab GN |
9732 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
9733 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
9734 | vcpu->arch.complete_userspace_io = NULL; | |
9735 | r = cui(vcpu); | |
9736 | if (r <= 0) | |
5663d8f9 | 9737 | goto out; |
716d51ab GN |
9738 | } else |
9739 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 9740 | |
460df4c1 PB |
9741 | if (kvm_run->immediate_exit) |
9742 | r = -EINTR; | |
9743 | else | |
9744 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
9745 | |
9746 | out: | |
5663d8f9 | 9747 | kvm_put_guest_fpu(vcpu); |
1b94f6f8 | 9748 | if (kvm_run->kvm_valid_regs) |
01643c51 | 9749 | store_regs(vcpu); |
f1d86e46 | 9750 | post_kvm_run_save(vcpu); |
20b7035c | 9751 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 9752 | |
accb757d | 9753 | vcpu_put(vcpu); |
b6c7a5dc HB |
9754 | return r; |
9755 | } | |
9756 | ||
01643c51 | 9757 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 9758 | { |
7ae441ea GN |
9759 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
9760 | /* | |
9761 | * We are here if userspace calls get_regs() in the middle of | |
9762 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 9763 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
9764 | * that usually, but some bad designed PV devices (vmware |
9765 | * backdoor interface) need this to work | |
9766 | */ | |
c9b8b07c | 9767 | emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); |
7ae441ea GN |
9768 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
9769 | } | |
de3cd117 SC |
9770 | regs->rax = kvm_rax_read(vcpu); |
9771 | regs->rbx = kvm_rbx_read(vcpu); | |
9772 | regs->rcx = kvm_rcx_read(vcpu); | |
9773 | regs->rdx = kvm_rdx_read(vcpu); | |
9774 | regs->rsi = kvm_rsi_read(vcpu); | |
9775 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 9776 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 9777 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 9778 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
9779 | regs->r8 = kvm_r8_read(vcpu); |
9780 | regs->r9 = kvm_r9_read(vcpu); | |
9781 | regs->r10 = kvm_r10_read(vcpu); | |
9782 | regs->r11 = kvm_r11_read(vcpu); | |
9783 | regs->r12 = kvm_r12_read(vcpu); | |
9784 | regs->r13 = kvm_r13_read(vcpu); | |
9785 | regs->r14 = kvm_r14_read(vcpu); | |
9786 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
9787 | #endif |
9788 | ||
5fdbf976 | 9789 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 9790 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 9791 | } |
b6c7a5dc | 9792 | |
01643c51 KH |
9793 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
9794 | { | |
9795 | vcpu_load(vcpu); | |
9796 | __get_regs(vcpu, regs); | |
1fc9b76b | 9797 | vcpu_put(vcpu); |
b6c7a5dc HB |
9798 | return 0; |
9799 | } | |
9800 | ||
01643c51 | 9801 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 9802 | { |
7ae441ea GN |
9803 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
9804 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
9805 | ||
de3cd117 SC |
9806 | kvm_rax_write(vcpu, regs->rax); |
9807 | kvm_rbx_write(vcpu, regs->rbx); | |
9808 | kvm_rcx_write(vcpu, regs->rcx); | |
9809 | kvm_rdx_write(vcpu, regs->rdx); | |
9810 | kvm_rsi_write(vcpu, regs->rsi); | |
9811 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 9812 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 9813 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 9814 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
9815 | kvm_r8_write(vcpu, regs->r8); |
9816 | kvm_r9_write(vcpu, regs->r9); | |
9817 | kvm_r10_write(vcpu, regs->r10); | |
9818 | kvm_r11_write(vcpu, regs->r11); | |
9819 | kvm_r12_write(vcpu, regs->r12); | |
9820 | kvm_r13_write(vcpu, regs->r13); | |
9821 | kvm_r14_write(vcpu, regs->r14); | |
9822 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
9823 | #endif |
9824 | ||
5fdbf976 | 9825 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 9826 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 9827 | |
b4f14abd JK |
9828 | vcpu->arch.exception.pending = false; |
9829 | ||
3842d135 | 9830 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 9831 | } |
3842d135 | 9832 | |
01643c51 KH |
9833 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
9834 | { | |
9835 | vcpu_load(vcpu); | |
9836 | __set_regs(vcpu, regs); | |
875656fe | 9837 | vcpu_put(vcpu); |
b6c7a5dc HB |
9838 | return 0; |
9839 | } | |
9840 | ||
b6c7a5dc HB |
9841 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
9842 | { | |
9843 | struct kvm_segment cs; | |
9844 | ||
3e6e0aab | 9845 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
9846 | *db = cs.db; |
9847 | *l = cs.l; | |
9848 | } | |
9849 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
9850 | ||
01643c51 | 9851 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 9852 | { |
89a27f4d | 9853 | struct desc_ptr dt; |
b6c7a5dc | 9854 | |
5265713a TL |
9855 | if (vcpu->arch.guest_state_protected) |
9856 | goto skip_protected_regs; | |
9857 | ||
3e6e0aab GT |
9858 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
9859 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
9860 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
9861 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
9862 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
9863 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 9864 | |
3e6e0aab GT |
9865 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
9866 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 9867 | |
b3646477 | 9868 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
89a27f4d GN |
9869 | sregs->idt.limit = dt.size; |
9870 | sregs->idt.base = dt.address; | |
b3646477 | 9871 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
89a27f4d GN |
9872 | sregs->gdt.limit = dt.size; |
9873 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 9874 | |
ad312c7c | 9875 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 9876 | sregs->cr3 = kvm_read_cr3(vcpu); |
5265713a TL |
9877 | |
9878 | skip_protected_regs: | |
9879 | sregs->cr0 = kvm_read_cr0(vcpu); | |
fc78f519 | 9880 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 9881 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 9882 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
9883 | sregs->apic_base = kvm_get_apic_base(vcpu); |
9884 | ||
0e96f31e | 9885 | memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); |
b6c7a5dc | 9886 | |
04140b41 | 9887 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
9888 | set_bit(vcpu->arch.interrupt.nr, |
9889 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 9890 | } |
16d7a191 | 9891 | |
01643c51 KH |
9892 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
9893 | struct kvm_sregs *sregs) | |
9894 | { | |
9895 | vcpu_load(vcpu); | |
9896 | __get_sregs(vcpu, sregs); | |
bcdec41c | 9897 | vcpu_put(vcpu); |
b6c7a5dc HB |
9898 | return 0; |
9899 | } | |
9900 | ||
62d9f0db MT |
9901 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
9902 | struct kvm_mp_state *mp_state) | |
9903 | { | |
fd232561 | 9904 | vcpu_load(vcpu); |
f958bd23 SC |
9905 | if (kvm_mpx_supported()) |
9906 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 9907 | |
66450a21 | 9908 | kvm_apic_accept_events(vcpu); |
647daca2 TL |
9909 | if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || |
9910 | vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && | |
9911 | vcpu->arch.pv.pv_unhalted) | |
6aef266c SV |
9912 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; |
9913 | else | |
9914 | mp_state->mp_state = vcpu->arch.mp_state; | |
9915 | ||
f958bd23 SC |
9916 | if (kvm_mpx_supported()) |
9917 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 9918 | vcpu_put(vcpu); |
62d9f0db MT |
9919 | return 0; |
9920 | } | |
9921 | ||
9922 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
9923 | struct kvm_mp_state *mp_state) | |
9924 | { | |
e83dff5e CD |
9925 | int ret = -EINVAL; |
9926 | ||
9927 | vcpu_load(vcpu); | |
9928 | ||
bce87cce | 9929 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 9930 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 9931 | goto out; |
66450a21 | 9932 | |
27cbe7d6 LA |
9933 | /* |
9934 | * KVM_MP_STATE_INIT_RECEIVED means the processor is in | |
9935 | * INIT state; latched init should be reported using | |
9936 | * KVM_SET_VCPU_EVENTS, so reject it here. | |
9937 | */ | |
9938 | if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && | |
28bf2888 DH |
9939 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
9940 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 9941 | goto out; |
28bf2888 | 9942 | |
66450a21 JK |
9943 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
9944 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
9945 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
9946 | } else | |
9947 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 9948 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
9949 | |
9950 | ret = 0; | |
9951 | out: | |
9952 | vcpu_put(vcpu); | |
9953 | return ret; | |
62d9f0db MT |
9954 | } |
9955 | ||
7f3d35fd KW |
9956 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
9957 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 9958 | { |
c9b8b07c | 9959 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d | 9960 | int ret; |
e01c2426 | 9961 | |
8ec4722d | 9962 | init_emulate_ctxt(vcpu); |
c697518a | 9963 | |
7f3d35fd | 9964 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 9965 | has_error_code, error_code); |
1051778f SC |
9966 | if (ret) { |
9967 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
9968 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
9969 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 9970 | return 0; |
1051778f | 9971 | } |
37817f29 | 9972 | |
9d74191a TY |
9973 | kvm_rip_write(vcpu, ctxt->eip); |
9974 | kvm_set_rflags(vcpu, ctxt->eflags); | |
60fc3d02 | 9975 | return 1; |
37817f29 IE |
9976 | } |
9977 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
9978 | ||
ee69c92b | 9979 | static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 9980 | { |
37b95951 | 9981 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
9982 | /* |
9983 | * When EFER.LME and CR0.PG are set, the processor is in | |
9984 | * 64-bit mode (though maybe in a 32-bit code segment). | |
9985 | * CR4.PAE and EFER.LMA must be set. | |
9986 | */ | |
ee69c92b SC |
9987 | if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) |
9988 | return false; | |
ca29e145 | 9989 | if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) |
c1c35cf7 | 9990 | return false; |
f2981033 LT |
9991 | } else { |
9992 | /* | |
9993 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
9994 | * segment cannot be 64-bit. | |
9995 | */ | |
9996 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
ee69c92b | 9997 | return false; |
f2981033 LT |
9998 | } |
9999 | ||
ee69c92b | 10000 | return kvm_is_valid_cr4(vcpu, sregs->cr4); |
f2981033 LT |
10001 | } |
10002 | ||
01643c51 | 10003 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 10004 | { |
58cb628d | 10005 | struct msr_data apic_base_msr; |
b6c7a5dc | 10006 | int mmu_reset_needed = 0; |
63f42e02 | 10007 | int pending_vec, max_bits, idx; |
89a27f4d | 10008 | struct desc_ptr dt; |
b4ef9d4e CD |
10009 | int ret = -EINVAL; |
10010 | ||
ee69c92b | 10011 | if (!kvm_is_valid_sregs(vcpu, sregs)) |
8dbfb2bf | 10012 | goto out; |
f2981033 | 10013 | |
d3802286 JM |
10014 | apic_base_msr.data = sregs->apic_base; |
10015 | apic_base_msr.host_initiated = true; | |
10016 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
b4ef9d4e | 10017 | goto out; |
6d1068b3 | 10018 | |
5265713a TL |
10019 | if (vcpu->arch.guest_state_protected) |
10020 | goto skip_protected_regs; | |
10021 | ||
89a27f4d GN |
10022 | dt.size = sregs->idt.limit; |
10023 | dt.address = sregs->idt.base; | |
b3646477 | 10024 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
89a27f4d GN |
10025 | dt.size = sregs->gdt.limit; |
10026 | dt.address = sregs->gdt.base; | |
b3646477 | 10027 | static_call(kvm_x86_set_gdt)(vcpu, &dt); |
b6c7a5dc | 10028 | |
ad312c7c | 10029 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 10030 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 10031 | vcpu->arch.cr3 = sregs->cr3; |
cb3c1e2f | 10032 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
b6c7a5dc | 10033 | |
2d3ad1f4 | 10034 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 10035 | |
f6801dff | 10036 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b3646477 | 10037 | static_call(kvm_x86_set_efer)(vcpu, sregs->efer); |
b6c7a5dc | 10038 | |
4d4ec087 | 10039 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b3646477 | 10040 | static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); |
d7306163 | 10041 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 10042 | |
fc78f519 | 10043 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b3646477 | 10044 | static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); |
63f42e02 XG |
10045 | |
10046 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
bf03d4f9 | 10047 | if (is_pae_paging(vcpu)) { |
9f8fe504 | 10048 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
10049 | mmu_reset_needed = 1; |
10050 | } | |
63f42e02 | 10051 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
10052 | |
10053 | if (mmu_reset_needed) | |
10054 | kvm_mmu_reset_context(vcpu); | |
10055 | ||
3e6e0aab GT |
10056 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
10057 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
10058 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
10059 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
10060 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
10061 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 10062 | |
3e6e0aab GT |
10063 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
10064 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 10065 | |
5f0269f5 ME |
10066 | update_cr8_intercept(vcpu); |
10067 | ||
9c3e4aab | 10068 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 10069 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 10070 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 10071 | !is_protmode(vcpu)) |
9c3e4aab MT |
10072 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
10073 | ||
5265713a TL |
10074 | skip_protected_regs: |
10075 | max_bits = KVM_NR_INTERRUPTS; | |
10076 | pending_vec = find_first_bit( | |
10077 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
10078 | if (pending_vec < max_bits) { | |
10079 | kvm_queue_interrupt(vcpu, pending_vec, false); | |
10080 | pr_debug("Set back pending irq %d\n", pending_vec); | |
10081 | } | |
10082 | ||
3842d135 AK |
10083 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
10084 | ||
b4ef9d4e CD |
10085 | ret = 0; |
10086 | out: | |
01643c51 KH |
10087 | return ret; |
10088 | } | |
10089 | ||
10090 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
10091 | struct kvm_sregs *sregs) | |
10092 | { | |
10093 | int ret; | |
10094 | ||
10095 | vcpu_load(vcpu); | |
10096 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
10097 | vcpu_put(vcpu); |
10098 | return ret; | |
b6c7a5dc HB |
10099 | } |
10100 | ||
d0bfb940 JK |
10101 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
10102 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 10103 | { |
355be0b9 | 10104 | unsigned long rflags; |
ae675ef0 | 10105 | int i, r; |
b6c7a5dc | 10106 | |
8d4846b9 TL |
10107 | if (vcpu->arch.guest_state_protected) |
10108 | return -EINVAL; | |
10109 | ||
66b56562 CD |
10110 | vcpu_load(vcpu); |
10111 | ||
4f926bf2 JK |
10112 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
10113 | r = -EBUSY; | |
10114 | if (vcpu->arch.exception.pending) | |
2122ff5e | 10115 | goto out; |
4f926bf2 JK |
10116 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
10117 | kvm_queue_exception(vcpu, DB_VECTOR); | |
10118 | else | |
10119 | kvm_queue_exception(vcpu, BP_VECTOR); | |
10120 | } | |
10121 | ||
91586a3b JK |
10122 | /* |
10123 | * Read rflags as long as potentially injected trace flags are still | |
10124 | * filtered out. | |
10125 | */ | |
10126 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
10127 | |
10128 | vcpu->guest_debug = dbg->control; | |
10129 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
10130 | vcpu->guest_debug = 0; | |
10131 | ||
10132 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
10133 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
10134 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 10135 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
10136 | } else { |
10137 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
10138 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 10139 | } |
c8639010 | 10140 | kvm_update_dr7(vcpu); |
ae675ef0 | 10141 | |
f92653ee | 10142 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
e87e46d5 | 10143 | vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); |
94fe45da | 10144 | |
91586a3b JK |
10145 | /* |
10146 | * Trigger an rflags update that will inject or remove the trace | |
10147 | * flags. | |
10148 | */ | |
10149 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 10150 | |
b3646477 | 10151 | static_call(kvm_x86_update_exception_bitmap)(vcpu); |
b6c7a5dc | 10152 | |
4f926bf2 | 10153 | r = 0; |
d0bfb940 | 10154 | |
2122ff5e | 10155 | out: |
66b56562 | 10156 | vcpu_put(vcpu); |
b6c7a5dc HB |
10157 | return r; |
10158 | } | |
10159 | ||
8b006791 ZX |
10160 | /* |
10161 | * Translate a guest virtual address to a guest physical address. | |
10162 | */ | |
10163 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
10164 | struct kvm_translation *tr) | |
10165 | { | |
10166 | unsigned long vaddr = tr->linear_address; | |
10167 | gpa_t gpa; | |
f656ce01 | 10168 | int idx; |
8b006791 | 10169 | |
1da5b61d CD |
10170 | vcpu_load(vcpu); |
10171 | ||
f656ce01 | 10172 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 10173 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 10174 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
10175 | tr->physical_address = gpa; |
10176 | tr->valid = gpa != UNMAPPED_GVA; | |
10177 | tr->writeable = 1; | |
10178 | tr->usermode = 0; | |
8b006791 | 10179 | |
1da5b61d | 10180 | vcpu_put(vcpu); |
8b006791 ZX |
10181 | return 0; |
10182 | } | |
10183 | ||
d0752060 HB |
10184 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
10185 | { | |
1393123e | 10186 | struct fxregs_state *fxsave; |
d0752060 | 10187 | |
ed02b213 TL |
10188 | if (!vcpu->arch.guest_fpu) |
10189 | return 0; | |
10190 | ||
1393123e | 10191 | vcpu_load(vcpu); |
d0752060 | 10192 | |
b666a4b6 | 10193 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 HB |
10194 | memcpy(fpu->fpr, fxsave->st_space, 128); |
10195 | fpu->fcw = fxsave->cwd; | |
10196 | fpu->fsw = fxsave->swd; | |
10197 | fpu->ftwx = fxsave->twd; | |
10198 | fpu->last_opcode = fxsave->fop; | |
10199 | fpu->last_ip = fxsave->rip; | |
10200 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 10201 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 10202 | |
1393123e | 10203 | vcpu_put(vcpu); |
d0752060 HB |
10204 | return 0; |
10205 | } | |
10206 | ||
10207 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
10208 | { | |
6a96bc7f CD |
10209 | struct fxregs_state *fxsave; |
10210 | ||
ed02b213 TL |
10211 | if (!vcpu->arch.guest_fpu) |
10212 | return 0; | |
10213 | ||
6a96bc7f CD |
10214 | vcpu_load(vcpu); |
10215 | ||
b666a4b6 | 10216 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 | 10217 | |
d0752060 HB |
10218 | memcpy(fxsave->st_space, fpu->fpr, 128); |
10219 | fxsave->cwd = fpu->fcw; | |
10220 | fxsave->swd = fpu->fsw; | |
10221 | fxsave->twd = fpu->ftwx; | |
10222 | fxsave->fop = fpu->last_opcode; | |
10223 | fxsave->rip = fpu->last_ip; | |
10224 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 10225 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 10226 | |
6a96bc7f | 10227 | vcpu_put(vcpu); |
d0752060 HB |
10228 | return 0; |
10229 | } | |
10230 | ||
01643c51 KH |
10231 | static void store_regs(struct kvm_vcpu *vcpu) |
10232 | { | |
10233 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
10234 | ||
10235 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
10236 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
10237 | ||
10238 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
10239 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
10240 | ||
10241 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
10242 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
10243 | vcpu, &vcpu->run->s.regs.events); | |
10244 | } | |
10245 | ||
10246 | static int sync_regs(struct kvm_vcpu *vcpu) | |
10247 | { | |
10248 | if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) | |
10249 | return -EINVAL; | |
10250 | ||
10251 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { | |
10252 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
10253 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
10254 | } | |
10255 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
10256 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
10257 | return -EINVAL; | |
10258 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
10259 | } | |
10260 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
10261 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
10262 | vcpu, &vcpu->run->s.regs.events)) | |
10263 | return -EINVAL; | |
10264 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
10265 | } | |
10266 | ||
10267 | return 0; | |
10268 | } | |
10269 | ||
0ee6a517 | 10270 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 10271 | { |
ed02b213 TL |
10272 | if (!vcpu->arch.guest_fpu) |
10273 | return; | |
10274 | ||
b666a4b6 | 10275 | fpstate_init(&vcpu->arch.guest_fpu->state); |
782511b0 | 10276 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
b666a4b6 | 10277 | vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = |
df1daba7 | 10278 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 10279 | |
2acf923e DC |
10280 | /* |
10281 | * Ensure guest xcr0 is valid for loading | |
10282 | */ | |
d91cab78 | 10283 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 10284 | |
ad312c7c | 10285 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 10286 | } |
d0752060 | 10287 | |
ed02b213 TL |
10288 | void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) |
10289 | { | |
10290 | if (vcpu->arch.guest_fpu) { | |
10291 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
10292 | vcpu->arch.guest_fpu = NULL; | |
10293 | } | |
10294 | } | |
10295 | EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); | |
10296 | ||
897cc38e | 10297 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 10298 | { |
897cc38e SC |
10299 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
10300 | pr_warn_once("kvm: SMP vm created on host with unstable TSC; " | |
10301 | "guest TSC will not be reliable\n"); | |
7f1ea208 | 10302 | |
897cc38e | 10303 | return 0; |
e9b11c17 ZX |
10304 | } |
10305 | ||
e529ef66 | 10306 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 10307 | { |
95a0d01e SC |
10308 | struct page *page; |
10309 | int r; | |
c447e76b | 10310 | |
95a0d01e SC |
10311 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
10312 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
10313 | else | |
10314 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 10315 | |
95a0d01e | 10316 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c447e76b | 10317 | |
95a0d01e SC |
10318 | r = kvm_mmu_create(vcpu); |
10319 | if (r < 0) | |
10320 | return r; | |
10321 | ||
10322 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
10323 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
10324 | if (r < 0) | |
10325 | goto fail_mmu_destroy; | |
4e19c36f SS |
10326 | if (kvm_apicv_activated(vcpu->kvm)) |
10327 | vcpu->arch.apicv_active = true; | |
95a0d01e | 10328 | } else |
6e4e3b4d | 10329 | static_branch_inc(&kvm_has_noapic_vcpu); |
95a0d01e SC |
10330 | |
10331 | r = -ENOMEM; | |
10332 | ||
93bb59ca | 10333 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); |
95a0d01e SC |
10334 | if (!page) |
10335 | goto fail_free_lapic; | |
10336 | vcpu->arch.pio_data = page_address(page); | |
10337 | ||
10338 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, | |
10339 | GFP_KERNEL_ACCOUNT); | |
10340 | if (!vcpu->arch.mce_banks) | |
10341 | goto fail_free_pio_data; | |
10342 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
10343 | ||
10344 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
10345 | GFP_KERNEL_ACCOUNT)) | |
10346 | goto fail_free_mce_banks; | |
10347 | ||
c9b8b07c SC |
10348 | if (!alloc_emulate_ctxt(vcpu)) |
10349 | goto free_wbinvd_dirty_mask; | |
10350 | ||
95a0d01e SC |
10351 | vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, |
10352 | GFP_KERNEL_ACCOUNT); | |
10353 | if (!vcpu->arch.user_fpu) { | |
10354 | pr_err("kvm: failed to allocate userspace's fpu\n"); | |
c9b8b07c | 10355 | goto free_emulate_ctxt; |
95a0d01e SC |
10356 | } |
10357 | ||
10358 | vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, | |
10359 | GFP_KERNEL_ACCOUNT); | |
10360 | if (!vcpu->arch.guest_fpu) { | |
10361 | pr_err("kvm: failed to allocate vcpu's fpu\n"); | |
10362 | goto free_user_fpu; | |
10363 | } | |
10364 | fx_init(vcpu); | |
10365 | ||
95a0d01e | 10366 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
a8ac864a | 10367 | vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); |
95a0d01e SC |
10368 | |
10369 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
10370 | ||
10371 | kvm_async_pf_hash_reset(vcpu); | |
10372 | kvm_pmu_init(vcpu); | |
10373 | ||
10374 | vcpu->arch.pending_external_vector = -1; | |
10375 | vcpu->arch.preempted_in_kernel = false; | |
10376 | ||
b3646477 | 10377 | r = static_call(kvm_x86_vcpu_create)(vcpu); |
95a0d01e SC |
10378 | if (r) |
10379 | goto free_guest_fpu; | |
e9b11c17 | 10380 | |
0cf9135b | 10381 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 10382 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
19efffa2 | 10383 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 10384 | vcpu_load(vcpu); |
d28bc9dd | 10385 | kvm_vcpu_reset(vcpu, false); |
e1732991 | 10386 | kvm_init_mmu(vcpu, false); |
e9b11c17 | 10387 | vcpu_put(vcpu); |
ec7660cc | 10388 | return 0; |
95a0d01e SC |
10389 | |
10390 | free_guest_fpu: | |
ed02b213 | 10391 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10392 | free_user_fpu: |
10393 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
c9b8b07c SC |
10394 | free_emulate_ctxt: |
10395 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); | |
95a0d01e SC |
10396 | free_wbinvd_dirty_mask: |
10397 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
10398 | fail_free_mce_banks: | |
10399 | kfree(vcpu->arch.mce_banks); | |
10400 | fail_free_pio_data: | |
10401 | free_page((unsigned long)vcpu->arch.pio_data); | |
10402 | fail_free_lapic: | |
10403 | kvm_free_lapic(vcpu); | |
10404 | fail_mmu_destroy: | |
10405 | kvm_mmu_destroy(vcpu); | |
10406 | return r; | |
e9b11c17 ZX |
10407 | } |
10408 | ||
31928aa5 | 10409 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 10410 | { |
332967a3 | 10411 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 10412 | |
ec7660cc | 10413 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 10414 | return; |
ec7660cc | 10415 | vcpu_load(vcpu); |
0c899c25 | 10416 | kvm_synchronize_tsc(vcpu, 0); |
42897d86 | 10417 | vcpu_put(vcpu); |
2d5ba19b MT |
10418 | |
10419 | /* poll control enabled by default */ | |
10420 | vcpu->arch.msr_kvm_poll_control = 1; | |
10421 | ||
ec7660cc | 10422 | mutex_unlock(&vcpu->mutex); |
42897d86 | 10423 | |
b34de572 WL |
10424 | if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) |
10425 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
10426 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
10427 | } |
10428 | ||
d40ccc62 | 10429 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 10430 | { |
4cbc418a | 10431 | struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; |
95a0d01e | 10432 | int idx; |
344d9588 | 10433 | |
4cbc418a PB |
10434 | kvm_release_pfn(cache->pfn, cache->dirty, cache); |
10435 | ||
50b143e1 | 10436 | kvmclock_reset(vcpu); |
e9b11c17 | 10437 | |
b3646477 | 10438 | static_call(kvm_x86_vcpu_free)(vcpu); |
50b143e1 | 10439 | |
c9b8b07c | 10440 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); |
50b143e1 SC |
10441 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
10442 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
ed02b213 | 10443 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10444 | |
10445 | kvm_hv_vcpu_uninit(vcpu); | |
10446 | kvm_pmu_destroy(vcpu); | |
10447 | kfree(vcpu->arch.mce_banks); | |
10448 | kvm_free_lapic(vcpu); | |
10449 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
10450 | kvm_mmu_destroy(vcpu); | |
10451 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
10452 | free_page((unsigned long)vcpu->arch.pio_data); | |
255cbecf | 10453 | kvfree(vcpu->arch.cpuid_entries); |
95a0d01e | 10454 | if (!lapic_in_kernel(vcpu)) |
6e4e3b4d | 10455 | static_branch_dec(&kvm_has_noapic_vcpu); |
e9b11c17 ZX |
10456 | } |
10457 | ||
d28bc9dd | 10458 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 10459 | { |
b7e31be3 RK |
10460 | kvm_lapic_reset(vcpu, init_event); |
10461 | ||
e69fab5d PB |
10462 | vcpu->arch.hflags = 0; |
10463 | ||
c43203ca | 10464 | vcpu->arch.smi_pending = 0; |
52797bf9 | 10465 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
10466 | atomic_set(&vcpu->arch.nmi_queued, 0); |
10467 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 10468 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
10469 | kvm_clear_interrupt_queue(vcpu); |
10470 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 10471 | |
42dbaa5a | 10472 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 10473 | kvm_update_dr0123(vcpu); |
9a3ecd5e | 10474 | vcpu->arch.dr6 = DR6_ACTIVE_LOW; |
42dbaa5a | 10475 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 10476 | kvm_update_dr7(vcpu); |
42dbaa5a | 10477 | |
1119022c NA |
10478 | vcpu->arch.cr2 = 0; |
10479 | ||
3842d135 | 10480 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2635b5c4 VK |
10481 | vcpu->arch.apf.msr_en_val = 0; |
10482 | vcpu->arch.apf.msr_int_val = 0; | |
c9aaa895 | 10483 | vcpu->arch.st.msr_val = 0; |
3842d135 | 10484 | |
12f9a48f GC |
10485 | kvmclock_reset(vcpu); |
10486 | ||
af585b92 GN |
10487 | kvm_clear_async_pf_completion_queue(vcpu); |
10488 | kvm_async_pf_hash_reset(vcpu); | |
10489 | vcpu->arch.apf.halted = false; | |
3842d135 | 10490 | |
ed02b213 | 10491 | if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { |
a554d207 WL |
10492 | void *mpx_state_buffer; |
10493 | ||
10494 | /* | |
10495 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
10496 | * called with loaded FPU and does not let userspace fix the state. | |
10497 | */ | |
f775b13e RR |
10498 | if (init_event) |
10499 | kvm_put_guest_fpu(vcpu); | |
b666a4b6 | 10500 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10501 | XFEATURE_BNDREGS); |
a554d207 WL |
10502 | if (mpx_state_buffer) |
10503 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
b666a4b6 | 10504 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10505 | XFEATURE_BNDCSR); |
a554d207 WL |
10506 | if (mpx_state_buffer) |
10507 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
10508 | if (init_event) |
10509 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
10510 | } |
10511 | ||
64d60670 | 10512 | if (!init_event) { |
d28bc9dd | 10513 | kvm_pmu_reset(vcpu); |
64d60670 | 10514 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 10515 | |
db2336a8 | 10516 | vcpu->arch.msr_misc_features_enables = 0; |
a554d207 WL |
10517 | |
10518 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; | |
64d60670 | 10519 | } |
f5132b01 | 10520 | |
66f7b72e JS |
10521 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
10522 | vcpu->arch.regs_avail = ~0; | |
10523 | vcpu->arch.regs_dirty = ~0; | |
10524 | ||
a554d207 WL |
10525 | vcpu->arch.ia32_xss = 0; |
10526 | ||
b3646477 | 10527 | static_call(kvm_x86_vcpu_reset)(vcpu, init_event); |
e9b11c17 ZX |
10528 | } |
10529 | ||
2b4a273b | 10530 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
10531 | { |
10532 | struct kvm_segment cs; | |
10533 | ||
10534 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
10535 | cs.selector = vector << 8; | |
10536 | cs.base = vector << 12; | |
10537 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
10538 | kvm_rip_write(vcpu, 0); | |
e9b11c17 | 10539 | } |
647daca2 | 10540 | EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); |
e9b11c17 | 10541 | |
13a34e06 | 10542 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 10543 | { |
ca84d1a2 ZA |
10544 | struct kvm *kvm; |
10545 | struct kvm_vcpu *vcpu; | |
10546 | int i; | |
0dd6a6ed ZA |
10547 | int ret; |
10548 | u64 local_tsc; | |
10549 | u64 max_tsc = 0; | |
10550 | bool stable, backwards_tsc = false; | |
18863bdd | 10551 | |
7e34fbd0 | 10552 | kvm_user_return_msr_cpu_online(); |
b3646477 | 10553 | ret = static_call(kvm_x86_hardware_enable)(); |
0dd6a6ed ZA |
10554 | if (ret != 0) |
10555 | return ret; | |
10556 | ||
4ea1636b | 10557 | local_tsc = rdtsc(); |
b0c39dc6 | 10558 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
10559 | list_for_each_entry(kvm, &vm_list, vm_list) { |
10560 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
10561 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 10562 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10563 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
10564 | backwards_tsc = true; | |
10565 | if (vcpu->arch.last_host_tsc > max_tsc) | |
10566 | max_tsc = vcpu->arch.last_host_tsc; | |
10567 | } | |
10568 | } | |
10569 | } | |
10570 | ||
10571 | /* | |
10572 | * Sometimes, even reliable TSCs go backwards. This happens on | |
10573 | * platforms that reset TSC during suspend or hibernate actions, but | |
10574 | * maintain synchronization. We must compensate. Fortunately, we can | |
10575 | * detect that condition here, which happens early in CPU bringup, | |
10576 | * before any KVM threads can be running. Unfortunately, we can't | |
10577 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
10578 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 10579 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
10580 | * variables that haven't been updated yet. |
10581 | * | |
10582 | * So we simply find the maximum observed TSC above, then record the | |
10583 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
10584 | * the adjustment will be applied. Note that we accumulate | |
10585 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
10586 | * gets a chance to run again. In the event that no KVM threads get a | |
10587 | * chance to run, we will miss the entire elapsed period, as we'll have | |
10588 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
10589 | * loose cycle time. This isn't too big a deal, since the loss will be | |
10590 | * uniform across all VCPUs (not to mention the scenario is extremely | |
10591 | * unlikely). It is possible that a second hibernate recovery happens | |
10592 | * much faster than a first, causing the observed TSC here to be | |
10593 | * smaller; this would require additional padding adjustment, which is | |
10594 | * why we set last_host_tsc to the local tsc observed here. | |
10595 | * | |
10596 | * N.B. - this code below runs only on platforms with reliable TSC, | |
10597 | * as that is the only way backwards_tsc is set above. Also note | |
10598 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
10599 | * have the same delta_cyc adjustment applied if backwards_tsc | |
10600 | * is detected. Note further, this adjustment is only done once, | |
10601 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
10602 | * called multiple times (one for each physical CPU bringup). | |
10603 | * | |
4a969980 | 10604 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
10605 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
10606 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
10607 | * guarantee that they stay in perfect synchronization. | |
10608 | */ | |
10609 | if (backwards_tsc) { | |
10610 | u64 delta_cyc = max_tsc - local_tsc; | |
10611 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 10612 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
10613 | kvm_for_each_vcpu(i, vcpu, kvm) { |
10614 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
10615 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 10616 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10617 | } |
10618 | ||
10619 | /* | |
10620 | * We have to disable TSC offset matching.. if you were | |
10621 | * booting a VM while issuing an S4 host suspend.... | |
10622 | * you may have some problem. Solving this issue is | |
10623 | * left as an exercise to the reader. | |
10624 | */ | |
10625 | kvm->arch.last_tsc_nsec = 0; | |
10626 | kvm->arch.last_tsc_write = 0; | |
10627 | } | |
10628 | ||
10629 | } | |
10630 | return 0; | |
e9b11c17 ZX |
10631 | } |
10632 | ||
13a34e06 | 10633 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 10634 | { |
b3646477 | 10635 | static_call(kvm_x86_hardware_disable)(); |
13a34e06 | 10636 | drop_user_return_notifiers(); |
e9b11c17 ZX |
10637 | } |
10638 | ||
b9904085 | 10639 | int kvm_arch_hardware_setup(void *opaque) |
e9b11c17 | 10640 | { |
d008dfdb | 10641 | struct kvm_x86_init_ops *ops = opaque; |
9e9c3fe4 NA |
10642 | int r; |
10643 | ||
91661989 SC |
10644 | rdmsrl_safe(MSR_EFER, &host_efer); |
10645 | ||
408e9a31 PB |
10646 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
10647 | rdmsrl(MSR_IA32_XSS, host_xss); | |
10648 | ||
d008dfdb | 10649 | r = ops->hardware_setup(); |
9e9c3fe4 NA |
10650 | if (r != 0) |
10651 | return r; | |
10652 | ||
afaf0b2f | 10653 | memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); |
b3646477 | 10654 | kvm_ops_static_call_update(); |
69c6f69a | 10655 | |
408e9a31 PB |
10656 | if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) |
10657 | supported_xss = 0; | |
10658 | ||
139f7425 PB |
10659 | #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) |
10660 | cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); | |
10661 | #undef __kvm_cpu_cap_has | |
b11306b5 | 10662 | |
35181e86 HZ |
10663 | if (kvm_has_tsc_control) { |
10664 | /* | |
10665 | * Make sure the user can only configure tsc_khz values that | |
10666 | * fit into a signed integer. | |
273ba457 | 10667 | * A min value is not calculated because it will always |
35181e86 HZ |
10668 | * be 1 on all machines. |
10669 | */ | |
10670 | u64 max = min(0x7fffffffULL, | |
10671 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
10672 | kvm_max_guest_tsc_khz = max; | |
10673 | ||
ad721883 | 10674 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 10675 | } |
ad721883 | 10676 | |
9e9c3fe4 NA |
10677 | kvm_init_msr_list(); |
10678 | return 0; | |
e9b11c17 ZX |
10679 | } |
10680 | ||
10681 | void kvm_arch_hardware_unsetup(void) | |
10682 | { | |
b3646477 | 10683 | static_call(kvm_x86_hardware_unsetup)(); |
e9b11c17 ZX |
10684 | } |
10685 | ||
b9904085 | 10686 | int kvm_arch_check_processor_compat(void *opaque) |
e9b11c17 | 10687 | { |
f1cdecf5 | 10688 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); |
d008dfdb | 10689 | struct kvm_x86_init_ops *ops = opaque; |
f1cdecf5 SC |
10690 | |
10691 | WARN_ON(!irqs_disabled()); | |
10692 | ||
139f7425 PB |
10693 | if (__cr4_reserved_bits(cpu_has, c) != |
10694 | __cr4_reserved_bits(cpu_has, &boot_cpu_data)) | |
f1cdecf5 SC |
10695 | return -EIO; |
10696 | ||
d008dfdb | 10697 | return ops->check_processor_compatibility(); |
d71ba788 PB |
10698 | } |
10699 | ||
10700 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
10701 | { | |
10702 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
10703 | } | |
10704 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
10705 | ||
10706 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
10707 | { | |
10708 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
10709 | } |
10710 | ||
6e4e3b4d CL |
10711 | __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); |
10712 | EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); | |
54e9818f | 10713 | |
e790d9ef RK |
10714 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
10715 | { | |
b35e5548 LX |
10716 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
10717 | ||
c595ceee | 10718 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
10719 | if (pmu->version && unlikely(pmu->event_count)) { |
10720 | pmu->need_cleanup = true; | |
10721 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
10722 | } | |
b3646477 | 10723 | static_call(kvm_x86_sched_in)(vcpu, cpu); |
e790d9ef RK |
10724 | } |
10725 | ||
562b6b08 SC |
10726 | void kvm_arch_free_vm(struct kvm *kvm) |
10727 | { | |
05f04ae4 | 10728 | kfree(to_kvm_hv(kvm)->hv_pa_pg); |
562b6b08 | 10729 | vfree(kvm); |
e790d9ef RK |
10730 | } |
10731 | ||
562b6b08 | 10732 | |
e08b9637 | 10733 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 10734 | { |
e08b9637 CO |
10735 | if (type) |
10736 | return -EINVAL; | |
10737 | ||
6ef768fa | 10738 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 10739 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
10605204 | 10740 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
1aa9b957 | 10741 | INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); |
4d5c5d0f | 10742 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 10743 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 10744 | |
5550af4d SY |
10745 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
10746 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
10747 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
10748 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
10749 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 10750 | |
038f8c11 | 10751 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 10752 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
10753 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
10754 | ||
8171cd68 | 10755 | kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); |
d828199e | 10756 | pvclock_update_vm_gtod_copy(kvm); |
53f658b3 | 10757 | |
6fbbde9a DS |
10758 | kvm->arch.guest_can_read_msr_platform_info = true; |
10759 | ||
7e44e449 | 10760 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 10761 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 10762 | |
cbc0236a | 10763 | kvm_hv_init_vm(kvm); |
0eb05bf2 | 10764 | kvm_page_track_init(kvm); |
13d268ca | 10765 | kvm_mmu_init_vm(kvm); |
0eb05bf2 | 10766 | |
b3646477 | 10767 | return static_call(kvm_x86_vm_init)(kvm); |
d19a9cd2 ZX |
10768 | } |
10769 | ||
1aa9b957 JS |
10770 | int kvm_arch_post_init_vm(struct kvm *kvm) |
10771 | { | |
10772 | return kvm_mmu_post_init_vm(kvm); | |
10773 | } | |
10774 | ||
d19a9cd2 ZX |
10775 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
10776 | { | |
ec7660cc | 10777 | vcpu_load(vcpu); |
d19a9cd2 ZX |
10778 | kvm_mmu_unload(vcpu); |
10779 | vcpu_put(vcpu); | |
10780 | } | |
10781 | ||
10782 | static void kvm_free_vcpus(struct kvm *kvm) | |
10783 | { | |
10784 | unsigned int i; | |
988a2cae | 10785 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
10786 | |
10787 | /* | |
10788 | * Unpin any mmu pages first. | |
10789 | */ | |
af585b92 GN |
10790 | kvm_for_each_vcpu(i, vcpu, kvm) { |
10791 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 10792 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 10793 | } |
988a2cae | 10794 | kvm_for_each_vcpu(i, vcpu, kvm) |
4543bdc0 | 10795 | kvm_vcpu_destroy(vcpu); |
988a2cae GN |
10796 | |
10797 | mutex_lock(&kvm->lock); | |
10798 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
10799 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 10800 | |
988a2cae GN |
10801 | atomic_set(&kvm->online_vcpus, 0); |
10802 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
10803 | } |
10804 | ||
ad8ba2cd SY |
10805 | void kvm_arch_sync_events(struct kvm *kvm) |
10806 | { | |
332967a3 | 10807 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 10808 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 10809 | kvm_free_pit(kvm); |
ad8ba2cd SY |
10810 | } |
10811 | ||
ff5a983c PX |
10812 | #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) |
10813 | ||
10814 | /** | |
10815 | * __x86_set_memory_region: Setup KVM internal memory slot | |
10816 | * | |
10817 | * @kvm: the kvm pointer to the VM. | |
10818 | * @id: the slot ID to setup. | |
10819 | * @gpa: the GPA to install the slot (unused when @size == 0). | |
10820 | * @size: the size of the slot. Set to zero to uninstall a slot. | |
10821 | * | |
10822 | * This function helps to setup a KVM internal memory slot. Specify | |
10823 | * @size > 0 to install a new slot, while @size == 0 to uninstall a | |
10824 | * slot. The return code can be one of the following: | |
10825 | * | |
10826 | * HVA: on success (uninstall will return a bogus HVA) | |
10827 | * -errno: on error | |
10828 | * | |
10829 | * The caller should always use IS_ERR() to check the return value | |
10830 | * before use. Note, the KVM internal memory slots are guaranteed to | |
10831 | * remain valid and unchanged until the VM is destroyed, i.e., the | |
10832 | * GPA->HVA translation will not change. However, the HVA is a user | |
10833 | * address, i.e. its accessibility is not guaranteed, and must be | |
10834 | * accessed via __copy_{to,from}_user(). | |
10835 | */ | |
10836 | void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, | |
10837 | u32 size) | |
9da0e4d5 PB |
10838 | { |
10839 | int i, r; | |
3f649ab7 | 10840 | unsigned long hva, old_npages; |
f0d648bd | 10841 | struct kvm_memslots *slots = kvm_memslots(kvm); |
0577d1ab | 10842 | struct kvm_memory_slot *slot; |
9da0e4d5 PB |
10843 | |
10844 | /* Called with kvm->slots_lock held. */ | |
1d8007bd | 10845 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
ff5a983c | 10846 | return ERR_PTR_USR(-EINVAL); |
9da0e4d5 | 10847 | |
f0d648bd PB |
10848 | slot = id_to_memslot(slots, id); |
10849 | if (size) { | |
0577d1ab | 10850 | if (slot && slot->npages) |
ff5a983c | 10851 | return ERR_PTR_USR(-EEXIST); |
f0d648bd PB |
10852 | |
10853 | /* | |
10854 | * MAP_SHARED to prevent internal slot pages from being moved | |
10855 | * by fork()/COW. | |
10856 | */ | |
10857 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
10858 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
10859 | if (IS_ERR((void *)hva)) | |
ff5a983c | 10860 | return (void __user *)hva; |
f0d648bd | 10861 | } else { |
0577d1ab | 10862 | if (!slot || !slot->npages) |
46914534 | 10863 | return NULL; |
f0d648bd | 10864 | |
0577d1ab | 10865 | old_npages = slot->npages; |
b66f9bab | 10866 | hva = slot->userspace_addr; |
f0d648bd PB |
10867 | } |
10868 | ||
9da0e4d5 | 10869 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 10870 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 10871 | |
1d8007bd PB |
10872 | m.slot = id | (i << 16); |
10873 | m.flags = 0; | |
10874 | m.guest_phys_addr = gpa; | |
f0d648bd | 10875 | m.userspace_addr = hva; |
1d8007bd | 10876 | m.memory_size = size; |
9da0e4d5 PB |
10877 | r = __kvm_set_memory_region(kvm, &m); |
10878 | if (r < 0) | |
ff5a983c | 10879 | return ERR_PTR_USR(r); |
9da0e4d5 PB |
10880 | } |
10881 | ||
103c763c | 10882 | if (!size) |
0577d1ab | 10883 | vm_munmap(hva, old_npages * PAGE_SIZE); |
f0d648bd | 10884 | |
ff5a983c | 10885 | return (void __user *)hva; |
9da0e4d5 PB |
10886 | } |
10887 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
10888 | ||
1aa9b957 JS |
10889 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
10890 | { | |
10891 | kvm_mmu_pre_destroy_vm(kvm); | |
10892 | } | |
10893 | ||
d19a9cd2 ZX |
10894 | void kvm_arch_destroy_vm(struct kvm *kvm) |
10895 | { | |
27469d29 AH |
10896 | if (current->mm == kvm->mm) { |
10897 | /* | |
10898 | * Free memory regions allocated on behalf of userspace, | |
10899 | * unless the the memory map has changed due to process exit | |
10900 | * or fd copying. | |
10901 | */ | |
6a3c623b PX |
10902 | mutex_lock(&kvm->slots_lock); |
10903 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
10904 | 0, 0); | |
10905 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
10906 | 0, 0); | |
10907 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
10908 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 10909 | } |
b3646477 | 10910 | static_call_cond(kvm_x86_vm_destroy)(kvm); |
b318e8de | 10911 | kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); |
c761159c PX |
10912 | kvm_pic_destroy(kvm); |
10913 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 10914 | kvm_free_vcpus(kvm); |
af1bae54 | 10915 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 10916 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 10917 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 10918 | kvm_page_track_cleanup(kvm); |
7d6bbebb | 10919 | kvm_xen_destroy_vm(kvm); |
cbc0236a | 10920 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 10921 | } |
0de10343 | 10922 | |
e96c81ee | 10923 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
db3fe4eb TY |
10924 | { |
10925 | int i; | |
10926 | ||
d89cc617 | 10927 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
10928 | kvfree(slot->arch.rmap[i]); |
10929 | slot->arch.rmap[i] = NULL; | |
10930 | ||
d89cc617 TY |
10931 | if (i == 0) |
10932 | continue; | |
10933 | ||
e96c81ee SC |
10934 | kvfree(slot->arch.lpage_info[i - 1]); |
10935 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb | 10936 | } |
21ebbeda | 10937 | |
e96c81ee | 10938 | kvm_page_track_free_memslot(slot); |
db3fe4eb TY |
10939 | } |
10940 | ||
0dab98b7 SC |
10941 | static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot, |
10942 | unsigned long npages) | |
db3fe4eb TY |
10943 | { |
10944 | int i; | |
10945 | ||
edd4fa37 SC |
10946 | /* |
10947 | * Clear out the previous array pointers for the KVM_MR_MOVE case. The | |
10948 | * old arrays will be freed by __kvm_set_memory_region() if installing | |
10949 | * the new memslot is successful. | |
10950 | */ | |
10951 | memset(&slot->arch, 0, sizeof(slot->arch)); | |
10952 | ||
d89cc617 | 10953 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
92f94f1e | 10954 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
10955 | unsigned long ugfn; |
10956 | int lpages; | |
d89cc617 | 10957 | int level = i + 1; |
db3fe4eb TY |
10958 | |
10959 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
10960 | slot->base_gfn, level) + 1; | |
10961 | ||
d89cc617 | 10962 | slot->arch.rmap[i] = |
778e1cdd | 10963 | kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), |
254272ce | 10964 | GFP_KERNEL_ACCOUNT); |
d89cc617 | 10965 | if (!slot->arch.rmap[i]) |
77d11309 | 10966 | goto out_free; |
d89cc617 TY |
10967 | if (i == 0) |
10968 | continue; | |
77d11309 | 10969 | |
254272ce | 10970 | linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 10971 | if (!linfo) |
db3fe4eb TY |
10972 | goto out_free; |
10973 | ||
92f94f1e XG |
10974 | slot->arch.lpage_info[i - 1] = linfo; |
10975 | ||
db3fe4eb | 10976 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 10977 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 10978 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 10979 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
10980 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
10981 | /* | |
10982 | * If the gfn and userspace address are not aligned wrt each | |
600087b6 | 10983 | * other, disable large page support for this slot. |
db3fe4eb | 10984 | */ |
600087b6 | 10985 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { |
db3fe4eb TY |
10986 | unsigned long j; |
10987 | ||
10988 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 10989 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
10990 | } |
10991 | } | |
10992 | ||
21ebbeda XG |
10993 | if (kvm_page_track_create_memslot(slot, npages)) |
10994 | goto out_free; | |
10995 | ||
db3fe4eb TY |
10996 | return 0; |
10997 | ||
10998 | out_free: | |
d89cc617 | 10999 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 11000 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
11001 | slot->arch.rmap[i] = NULL; |
11002 | if (i == 0) | |
11003 | continue; | |
11004 | ||
548ef284 | 11005 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 11006 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
11007 | } |
11008 | return -ENOMEM; | |
11009 | } | |
11010 | ||
15248258 | 11011 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 11012 | { |
91724814 BO |
11013 | struct kvm_vcpu *vcpu; |
11014 | int i; | |
11015 | ||
e6dff7d1 TY |
11016 | /* |
11017 | * memslots->generation has been incremented. | |
11018 | * mmio generation may have reached its maximum value. | |
11019 | */ | |
15248258 | 11020 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
11021 | |
11022 | /* Force re-initialization of steal_time cache */ | |
11023 | kvm_for_each_vcpu(i, vcpu, kvm) | |
11024 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
11025 | } |
11026 | ||
f7784b8e MT |
11027 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
11028 | struct kvm_memory_slot *memslot, | |
09170a49 | 11029 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 11030 | enum kvm_mr_change change) |
0de10343 | 11031 | { |
0dab98b7 SC |
11032 | if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) |
11033 | return kvm_alloc_memslot_metadata(memslot, | |
11034 | mem->memory_size >> PAGE_SHIFT); | |
f7784b8e MT |
11035 | return 0; |
11036 | } | |
11037 | ||
a85863c2 MS |
11038 | |
11039 | static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) | |
11040 | { | |
11041 | struct kvm_arch *ka = &kvm->arch; | |
11042 | ||
11043 | if (!kvm_x86_ops.cpu_dirty_log_size) | |
11044 | return; | |
11045 | ||
11046 | if ((enable && ++ka->cpu_dirty_logging_count == 1) || | |
11047 | (!enable && --ka->cpu_dirty_logging_count == 0)) | |
11048 | kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); | |
11049 | ||
11050 | WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); | |
11051 | } | |
11052 | ||
88178fd4 | 11053 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
3741679b AY |
11054 | struct kvm_memory_slot *old, |
11055 | struct kvm_memory_slot *new, | |
11056 | enum kvm_mr_change change) | |
88178fd4 | 11057 | { |
a85863c2 MS |
11058 | bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES; |
11059 | ||
3741679b | 11060 | /* |
a85863c2 MS |
11061 | * Update CPU dirty logging if dirty logging is being toggled. This |
11062 | * applies to all operations. | |
3741679b | 11063 | */ |
a85863c2 MS |
11064 | if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES) |
11065 | kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); | |
88178fd4 KH |
11066 | |
11067 | /* | |
a85863c2 | 11068 | * Nothing more to do for RO slots (which can't be dirtied and can't be |
b6e16ae5 | 11069 | * made writable) or CREATE/MOVE/DELETE of a slot. |
88178fd4 | 11070 | * |
b6e16ae5 | 11071 | * For a memslot with dirty logging disabled: |
3741679b AY |
11072 | * CREATE: No dirty mappings will already exist. |
11073 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
11074 | * kvm_arch_flush_shadow_memslot() | |
b6e16ae5 SC |
11075 | * |
11076 | * For a memslot with dirty logging enabled: | |
11077 | * CREATE: No shadow pages exist, thus nothing to write-protect | |
11078 | * and no dirty bits to clear. | |
11079 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
11080 | * kvm_arch_flush_shadow_memslot(). | |
3741679b | 11081 | */ |
3741679b | 11082 | if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) |
88178fd4 | 11083 | return; |
3741679b AY |
11084 | |
11085 | /* | |
52f46079 SC |
11086 | * READONLY and non-flags changes were filtered out above, and the only |
11087 | * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty | |
11088 | * logging isn't being toggled on or off. | |
88178fd4 | 11089 | */ |
52f46079 SC |
11090 | if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES))) |
11091 | return; | |
11092 | ||
b6e16ae5 SC |
11093 | if (!log_dirty_pages) { |
11094 | /* | |
11095 | * Dirty logging tracks sptes in 4k granularity, meaning that | |
11096 | * large sptes have to be split. If live migration succeeds, | |
11097 | * the guest in the source machine will be destroyed and large | |
11098 | * sptes will be created in the destination. However, if the | |
11099 | * guest continues to run in the source machine (for example if | |
11100 | * live migration fails), small sptes will remain around and | |
11101 | * cause bad performance. | |
11102 | * | |
11103 | * Scan sptes if dirty logging has been stopped, dropping those | |
11104 | * which can be collapsed into a single large-page spte. Later | |
11105 | * page faults will create the large-page sptes. | |
11106 | */ | |
3741679b | 11107 | kvm_mmu_zap_collapsible_sptes(kvm, new); |
b6e16ae5 | 11108 | } else { |
a1419f8b SC |
11109 | /* By default, write-protect everything to log writes. */ |
11110 | int level = PG_LEVEL_4K; | |
11111 | ||
a018eba5 | 11112 | if (kvm_x86_ops.cpu_dirty_log_size) { |
a1419f8b SC |
11113 | /* |
11114 | * Clear all dirty bits, unless pages are treated as | |
11115 | * dirty from the get-go. | |
11116 | */ | |
a018eba5 SC |
11117 | if (!kvm_dirty_log_manual_protect_and_init_set(kvm)) |
11118 | kvm_mmu_slot_leaf_clear_dirty(kvm, new); | |
3c9bd400 | 11119 | |
a1419f8b SC |
11120 | /* |
11121 | * Write-protect large pages on write so that dirty | |
11122 | * logging happens at 4k granularity. No need to | |
11123 | * write-protect small SPTEs since write accesses are | |
11124 | * logged by the CPU via dirty bits. | |
11125 | */ | |
11126 | level = PG_LEVEL_2M; | |
11127 | } else if (kvm_dirty_log_manual_protect_and_init_set(kvm)) { | |
3c9bd400 JZ |
11128 | /* |
11129 | * If we're with initial-all-set, we don't need | |
11130 | * to write protect any small page because | |
11131 | * they're reported as dirty already. However | |
11132 | * we still need to write-protect huge pages | |
11133 | * so that the page split can happen lazily on | |
11134 | * the first write to the huge page. | |
11135 | */ | |
a1419f8b | 11136 | level = PG_LEVEL_2M; |
3c9bd400 | 11137 | } |
a1419f8b | 11138 | kvm_mmu_slot_remove_write_access(kvm, new, level); |
88178fd4 KH |
11139 | } |
11140 | } | |
11141 | ||
f7784b8e | 11142 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 11143 | const struct kvm_userspace_memory_region *mem, |
9d4c197c | 11144 | struct kvm_memory_slot *old, |
f36f3f28 | 11145 | const struct kvm_memory_slot *new, |
8482644a | 11146 | enum kvm_mr_change change) |
f7784b8e | 11147 | { |
48c0e4e9 | 11148 | if (!kvm->arch.n_requested_mmu_pages) |
4d66623c WY |
11149 | kvm_mmu_change_mmu_pages(kvm, |
11150 | kvm_mmu_calculate_default_mmu_pages(kvm)); | |
1c91cad4 | 11151 | |
3ea3b7fa | 11152 | /* |
f36f3f28 | 11153 | * FIXME: const-ify all uses of struct kvm_memory_slot. |
c972f3b1 | 11154 | */ |
3741679b | 11155 | kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change); |
21198846 SC |
11156 | |
11157 | /* Free the arrays associated with the old memslot. */ | |
11158 | if (change == KVM_MR_MOVE) | |
e96c81ee | 11159 | kvm_arch_free_memslot(kvm, old); |
0de10343 | 11160 | } |
1d737c8a | 11161 | |
2df72e9b | 11162 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 11163 | { |
7390de1e | 11164 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
11165 | } |
11166 | ||
2df72e9b MT |
11167 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
11168 | struct kvm_memory_slot *slot) | |
11169 | { | |
ae7cd873 | 11170 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
11171 | } |
11172 | ||
e6c67d8c LA |
11173 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
11174 | { | |
11175 | return (is_guest_mode(vcpu) && | |
afaf0b2f | 11176 | kvm_x86_ops.guest_apic_has_interrupt && |
b3646477 | 11177 | static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); |
e6c67d8c LA |
11178 | } |
11179 | ||
5d9bc648 PB |
11180 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
11181 | { | |
11182 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
11183 | return true; | |
11184 | ||
11185 | if (kvm_apic_has_events(vcpu)) | |
11186 | return true; | |
11187 | ||
11188 | if (vcpu->arch.pv.pv_unhalted) | |
11189 | return true; | |
11190 | ||
a5f01f8e WL |
11191 | if (vcpu->arch.exception.pending) |
11192 | return true; | |
11193 | ||
47a66eed Z |
11194 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
11195 | (vcpu->arch.nmi_pending && | |
b3646477 | 11196 | static_call(kvm_x86_nmi_allowed)(vcpu, false))) |
5d9bc648 PB |
11197 | return true; |
11198 | ||
47a66eed | 11199 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
a9fa7cb6 | 11200 | (vcpu->arch.smi_pending && |
b3646477 | 11201 | static_call(kvm_x86_smi_allowed)(vcpu, false))) |
73917739 PB |
11202 | return true; |
11203 | ||
5d9bc648 | 11204 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
11205 | (kvm_cpu_has_interrupt(vcpu) || |
11206 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
11207 | return true; |
11208 | ||
1f4b34f8 AS |
11209 | if (kvm_hv_has_stimer_pending(vcpu)) |
11210 | return true; | |
11211 | ||
d2060bd4 SC |
11212 | if (is_guest_mode(vcpu) && |
11213 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
11214 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
11215 | return true; | |
11216 | ||
5d9bc648 PB |
11217 | return false; |
11218 | } | |
11219 | ||
1d737c8a ZX |
11220 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
11221 | { | |
5d9bc648 | 11222 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 11223 | } |
5736199a | 11224 | |
10dbdf98 | 11225 | bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) |
17e433b5 | 11226 | { |
b3646477 | 11227 | if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) |
52acd22f WL |
11228 | return true; |
11229 | ||
11230 | return false; | |
11231 | } | |
11232 | ||
17e433b5 WL |
11233 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
11234 | { | |
11235 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
11236 | return true; | |
11237 | ||
11238 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
11239 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
11240 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
11241 | return true; | |
11242 | ||
10dbdf98 | 11243 | return kvm_arch_dy_has_pending_interrupt(vcpu); |
17e433b5 WL |
11244 | } |
11245 | ||
199b5763 LM |
11246 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
11247 | { | |
b86bb11e WL |
11248 | if (vcpu->arch.guest_state_protected) |
11249 | return true; | |
11250 | ||
de63ad4c | 11251 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
11252 | } |
11253 | ||
b6d33834 | 11254 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 11255 | { |
b6d33834 | 11256 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 11257 | } |
78646121 GN |
11258 | |
11259 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
11260 | { | |
b3646477 | 11261 | return static_call(kvm_x86_interrupt_allowed)(vcpu, false); |
78646121 | 11262 | } |
229456fc | 11263 | |
82b32774 | 11264 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 11265 | { |
7ed9abfe TL |
11266 | /* Can't read the RIP when guest state is protected, just return 0 */ |
11267 | if (vcpu->arch.guest_state_protected) | |
11268 | return 0; | |
11269 | ||
82b32774 NA |
11270 | if (is_64_bit_mode(vcpu)) |
11271 | return kvm_rip_read(vcpu); | |
11272 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
11273 | kvm_rip_read(vcpu)); | |
11274 | } | |
11275 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 11276 | |
82b32774 NA |
11277 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
11278 | { | |
11279 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
11280 | } |
11281 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
11282 | ||
94fe45da JK |
11283 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
11284 | { | |
11285 | unsigned long rflags; | |
11286 | ||
b3646477 | 11287 | rflags = static_call(kvm_x86_get_rflags)(vcpu); |
94fe45da | 11288 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
c310bac5 | 11289 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
11290 | return rflags; |
11291 | } | |
11292 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
11293 | ||
6addfc42 | 11294 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
11295 | { |
11296 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 11297 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 11298 | rflags |= X86_EFLAGS_TF; |
b3646477 | 11299 | static_call(kvm_x86_set_rflags)(vcpu, rflags); |
6addfc42 PB |
11300 | } |
11301 | ||
11302 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
11303 | { | |
11304 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 11305 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
11306 | } |
11307 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
11308 | ||
56028d08 GN |
11309 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
11310 | { | |
11311 | int r; | |
11312 | ||
44dd3ffa | 11313 | if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || |
f2e10669 | 11314 | work->wakeup_all) |
56028d08 GN |
11315 | return; |
11316 | ||
11317 | r = kvm_mmu_reload(vcpu); | |
11318 | if (unlikely(r)) | |
11319 | return; | |
11320 | ||
44dd3ffa | 11321 | if (!vcpu->arch.mmu->direct_map && |
d8dd54e0 | 11322 | work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) |
fb67e14f XG |
11323 | return; |
11324 | ||
7a02674d | 11325 | kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); |
56028d08 GN |
11326 | } |
11327 | ||
af585b92 GN |
11328 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
11329 | { | |
dd03bcaa PX |
11330 | BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); |
11331 | ||
af585b92 GN |
11332 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); |
11333 | } | |
11334 | ||
11335 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
11336 | { | |
dd03bcaa | 11337 | return (key + 1) & (ASYNC_PF_PER_VCPU - 1); |
af585b92 GN |
11338 | } |
11339 | ||
11340 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11341 | { | |
11342 | u32 key = kvm_async_pf_hash_fn(gfn); | |
11343 | ||
11344 | while (vcpu->arch.apf.gfns[key] != ~0) | |
11345 | key = kvm_async_pf_next_probe(key); | |
11346 | ||
11347 | vcpu->arch.apf.gfns[key] = gfn; | |
11348 | } | |
11349 | ||
11350 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11351 | { | |
11352 | int i; | |
11353 | u32 key = kvm_async_pf_hash_fn(gfn); | |
11354 | ||
dd03bcaa | 11355 | for (i = 0; i < ASYNC_PF_PER_VCPU && |
c7d28c24 XG |
11356 | (vcpu->arch.apf.gfns[key] != gfn && |
11357 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
11358 | key = kvm_async_pf_next_probe(key); |
11359 | ||
11360 | return key; | |
11361 | } | |
11362 | ||
11363 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11364 | { | |
11365 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
11366 | } | |
11367 | ||
11368 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11369 | { | |
11370 | u32 i, j, k; | |
11371 | ||
11372 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
0fd46044 PX |
11373 | |
11374 | if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) | |
11375 | return; | |
11376 | ||
af585b92 GN |
11377 | while (true) { |
11378 | vcpu->arch.apf.gfns[i] = ~0; | |
11379 | do { | |
11380 | j = kvm_async_pf_next_probe(j); | |
11381 | if (vcpu->arch.apf.gfns[j] == ~0) | |
11382 | return; | |
11383 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
11384 | /* | |
11385 | * k lies cyclically in ]i,j] | |
11386 | * | i.k.j | | |
11387 | * |....j i.k.| or |.k..j i...| | |
11388 | */ | |
11389 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
11390 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
11391 | i = j; | |
11392 | } | |
11393 | } | |
11394 | ||
68fd66f1 | 11395 | static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) |
7c90705b | 11396 | { |
68fd66f1 VK |
11397 | u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; |
11398 | ||
11399 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, | |
11400 | sizeof(reason)); | |
11401 | } | |
11402 | ||
11403 | static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) | |
11404 | { | |
2635b5c4 | 11405 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); |
4e335d9e | 11406 | |
2635b5c4 VK |
11407 | return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, |
11408 | &token, offset, sizeof(token)); | |
11409 | } | |
11410 | ||
11411 | static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) | |
11412 | { | |
11413 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); | |
11414 | u32 val; | |
11415 | ||
11416 | if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, | |
11417 | &val, offset, sizeof(val))) | |
11418 | return false; | |
11419 | ||
11420 | return !val; | |
7c90705b GN |
11421 | } |
11422 | ||
1dfdb45e PB |
11423 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
11424 | { | |
11425 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) | |
11426 | return false; | |
11427 | ||
2635b5c4 | 11428 | if (!kvm_pv_async_pf_enabled(vcpu) || |
b3646477 | 11429 | (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) |
1dfdb45e PB |
11430 | return false; |
11431 | ||
11432 | return true; | |
11433 | } | |
11434 | ||
11435 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
11436 | { | |
11437 | if (unlikely(!lapic_in_kernel(vcpu) || | |
11438 | kvm_event_needs_reinjection(vcpu) || | |
11439 | vcpu->arch.exception.pending)) | |
11440 | return false; | |
11441 | ||
11442 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
11443 | return false; | |
11444 | ||
11445 | /* | |
11446 | * If interrupts are off we cannot even use an artificial | |
11447 | * halt state. | |
11448 | */ | |
c300ab9f | 11449 | return kvm_arch_interrupt_allowed(vcpu); |
1dfdb45e PB |
11450 | } |
11451 | ||
2a18b7e7 | 11452 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
11453 | struct kvm_async_pf *work) |
11454 | { | |
6389ee94 AK |
11455 | struct x86_exception fault; |
11456 | ||
736c291c | 11457 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 11458 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 11459 | |
1dfdb45e | 11460 | if (kvm_can_deliver_async_pf(vcpu) && |
68fd66f1 | 11461 | !apf_put_user_notpresent(vcpu)) { |
6389ee94 AK |
11462 | fault.vector = PF_VECTOR; |
11463 | fault.error_code_valid = true; | |
11464 | fault.error_code = 0; | |
11465 | fault.nested_page_fault = false; | |
11466 | fault.address = work->arch.token; | |
adfe20fb | 11467 | fault.async_page_fault = true; |
6389ee94 | 11468 | kvm_inject_page_fault(vcpu, &fault); |
2a18b7e7 | 11469 | return true; |
1dfdb45e PB |
11470 | } else { |
11471 | /* | |
11472 | * It is not possible to deliver a paravirtualized asynchronous | |
11473 | * page fault, but putting the guest in an artificial halt state | |
11474 | * can be beneficial nevertheless: if an interrupt arrives, we | |
11475 | * can deliver it timely and perhaps the guest will schedule | |
11476 | * another process. When the instruction that triggered a page | |
11477 | * fault is retried, hopefully the page will be ready in the host. | |
11478 | */ | |
11479 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2a18b7e7 | 11480 | return false; |
7c90705b | 11481 | } |
af585b92 GN |
11482 | } |
11483 | ||
11484 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
11485 | struct kvm_async_pf *work) | |
11486 | { | |
2635b5c4 VK |
11487 | struct kvm_lapic_irq irq = { |
11488 | .delivery_mode = APIC_DM_FIXED, | |
11489 | .vector = vcpu->arch.apf.vec | |
11490 | }; | |
6389ee94 | 11491 | |
f2e10669 | 11492 | if (work->wakeup_all) |
7c90705b GN |
11493 | work->arch.token = ~0; /* broadcast wakeup */ |
11494 | else | |
11495 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 11496 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 11497 | |
2a18b7e7 VK |
11498 | if ((work->wakeup_all || work->notpresent_injected) && |
11499 | kvm_pv_async_pf_enabled(vcpu) && | |
557a961a VK |
11500 | !apf_put_user_ready(vcpu, work->arch.token)) { |
11501 | vcpu->arch.apf.pageready_pending = true; | |
2635b5c4 | 11502 | kvm_apic_set_irq(vcpu, &irq, NULL); |
557a961a | 11503 | } |
2635b5c4 | 11504 | |
e6d53e3b | 11505 | vcpu->arch.apf.halted = false; |
a4fa1635 | 11506 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
11507 | } |
11508 | ||
557a961a VK |
11509 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) |
11510 | { | |
11511 | kvm_make_request(KVM_REQ_APF_READY, vcpu); | |
11512 | if (!vcpu->arch.apf.pageready_pending) | |
11513 | kvm_vcpu_kick(vcpu); | |
11514 | } | |
11515 | ||
7c0ade6c | 11516 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) |
7c90705b | 11517 | { |
2635b5c4 | 11518 | if (!kvm_pv_async_pf_enabled(vcpu)) |
7c90705b GN |
11519 | return true; |
11520 | else | |
2f15d027 | 11521 | return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); |
af585b92 GN |
11522 | } |
11523 | ||
5544eb9b PB |
11524 | void kvm_arch_start_assignment(struct kvm *kvm) |
11525 | { | |
57ab8794 MT |
11526 | if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) |
11527 | static_call_cond(kvm_x86_start_assignment)(kvm); | |
5544eb9b PB |
11528 | } |
11529 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
11530 | ||
11531 | void kvm_arch_end_assignment(struct kvm *kvm) | |
11532 | { | |
11533 | atomic_dec(&kvm->arch.assigned_device_count); | |
11534 | } | |
11535 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
11536 | ||
11537 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
11538 | { | |
11539 | return atomic_read(&kvm->arch.assigned_device_count); | |
11540 | } | |
11541 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
11542 | ||
e0f0bbc5 AW |
11543 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
11544 | { | |
11545 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
11546 | } | |
11547 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
11548 | ||
11549 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
11550 | { | |
11551 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
11552 | } | |
11553 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
11554 | ||
11555 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
11556 | { | |
11557 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
11558 | } | |
11559 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
11560 | ||
14717e20 AW |
11561 | bool kvm_arch_has_irq_bypass(void) |
11562 | { | |
92735b1b | 11563 | return true; |
14717e20 AW |
11564 | } |
11565 | ||
87276880 FW |
11566 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
11567 | struct irq_bypass_producer *prod) | |
11568 | { | |
11569 | struct kvm_kernel_irqfd *irqfd = | |
11570 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
2edd9cb7 | 11571 | int ret; |
87276880 | 11572 | |
14717e20 | 11573 | irqfd->producer = prod; |
2edd9cb7 | 11574 | kvm_arch_start_assignment(irqfd->kvm); |
b3646477 | 11575 | ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, |
2edd9cb7 ZL |
11576 | prod->irq, irqfd->gsi, 1); |
11577 | ||
11578 | if (ret) | |
11579 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 | 11580 | |
2edd9cb7 | 11581 | return ret; |
87276880 FW |
11582 | } |
11583 | ||
11584 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
11585 | struct irq_bypass_producer *prod) | |
11586 | { | |
11587 | int ret; | |
11588 | struct kvm_kernel_irqfd *irqfd = | |
11589 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
11590 | ||
87276880 FW |
11591 | WARN_ON(irqfd->producer != prod); |
11592 | irqfd->producer = NULL; | |
11593 | ||
11594 | /* | |
11595 | * When producer of consumer is unregistered, we change back to | |
11596 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 11597 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
11598 | * int this case doesn't want to receive the interrupts. |
11599 | */ | |
b3646477 | 11600 | ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); |
87276880 FW |
11601 | if (ret) |
11602 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
11603 | " fails: %d\n", irqfd->consumer.token, ret); | |
2edd9cb7 ZL |
11604 | |
11605 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 FW |
11606 | } |
11607 | ||
11608 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
11609 | uint32_t guest_irq, bool set) | |
11610 | { | |
b3646477 | 11611 | return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); |
87276880 FW |
11612 | } |
11613 | ||
52004014 FW |
11614 | bool kvm_vector_hashing_enabled(void) |
11615 | { | |
11616 | return vector_hashing; | |
11617 | } | |
52004014 | 11618 | |
2d5ba19b MT |
11619 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
11620 | { | |
11621 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
11622 | } | |
11623 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
11624 | ||
841c2be0 ML |
11625 | |
11626 | int kvm_spec_ctrl_test_value(u64 value) | |
6441fa61 | 11627 | { |
841c2be0 ML |
11628 | /* |
11629 | * test that setting IA32_SPEC_CTRL to given value | |
11630 | * is allowed by the host processor | |
11631 | */ | |
6441fa61 | 11632 | |
841c2be0 ML |
11633 | u64 saved_value; |
11634 | unsigned long flags; | |
11635 | int ret = 0; | |
6441fa61 | 11636 | |
841c2be0 | 11637 | local_irq_save(flags); |
6441fa61 | 11638 | |
841c2be0 ML |
11639 | if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) |
11640 | ret = 1; | |
11641 | else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) | |
11642 | ret = 1; | |
11643 | else | |
11644 | wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); | |
6441fa61 | 11645 | |
841c2be0 | 11646 | local_irq_restore(flags); |
6441fa61 | 11647 | |
841c2be0 | 11648 | return ret; |
6441fa61 | 11649 | } |
841c2be0 | 11650 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); |
2d5ba19b | 11651 | |
89786147 MG |
11652 | void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) |
11653 | { | |
11654 | struct x86_exception fault; | |
19cf4b7e PB |
11655 | u32 access = error_code & |
11656 | (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); | |
89786147 MG |
11657 | |
11658 | if (!(error_code & PFERR_PRESENT_MASK) || | |
19cf4b7e | 11659 | vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { |
89786147 MG |
11660 | /* |
11661 | * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page | |
11662 | * tables probably do not match the TLB. Just proceed | |
11663 | * with the error code that the processor gave. | |
11664 | */ | |
11665 | fault.vector = PF_VECTOR; | |
11666 | fault.error_code_valid = true; | |
11667 | fault.error_code = error_code; | |
11668 | fault.nested_page_fault = false; | |
11669 | fault.address = gva; | |
11670 | } | |
11671 | vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); | |
6441fa61 | 11672 | } |
89786147 | 11673 | EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); |
2d5ba19b | 11674 | |
3f3393b3 BM |
11675 | /* |
11676 | * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns | |
11677 | * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value | |
11678 | * indicates whether exit to userspace is needed. | |
11679 | */ | |
11680 | int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, | |
11681 | struct x86_exception *e) | |
11682 | { | |
11683 | if (r == X86EMUL_PROPAGATE_FAULT) { | |
11684 | kvm_inject_emulated_page_fault(vcpu, e); | |
11685 | return 1; | |
11686 | } | |
11687 | ||
11688 | /* | |
11689 | * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED | |
11690 | * while handling a VMX instruction KVM could've handled the request | |
11691 | * correctly by exiting to userspace and performing I/O but there | |
11692 | * doesn't seem to be a real use-case behind such requests, just return | |
11693 | * KVM_EXIT_INTERNAL_ERROR for now. | |
11694 | */ | |
11695 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
11696 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
11697 | vcpu->run->internal.ndata = 0; | |
11698 | ||
11699 | return 0; | |
11700 | } | |
11701 | EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); | |
11702 | ||
9715092f BM |
11703 | int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) |
11704 | { | |
11705 | bool pcid_enabled; | |
11706 | struct x86_exception e; | |
11707 | unsigned i; | |
11708 | unsigned long roots_to_free = 0; | |
11709 | struct { | |
11710 | u64 pcid; | |
11711 | u64 gla; | |
11712 | } operand; | |
11713 | int r; | |
11714 | ||
11715 | r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); | |
11716 | if (r != X86EMUL_CONTINUE) | |
11717 | return kvm_handle_memory_failure(vcpu, r, &e); | |
11718 | ||
11719 | if (operand.pcid >> 12 != 0) { | |
11720 | kvm_inject_gp(vcpu, 0); | |
11721 | return 1; | |
11722 | } | |
11723 | ||
11724 | pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); | |
11725 | ||
11726 | switch (type) { | |
11727 | case INVPCID_TYPE_INDIV_ADDR: | |
11728 | if ((!pcid_enabled && (operand.pcid != 0)) || | |
11729 | is_noncanonical_address(operand.gla, vcpu)) { | |
11730 | kvm_inject_gp(vcpu, 0); | |
11731 | return 1; | |
11732 | } | |
11733 | kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); | |
11734 | return kvm_skip_emulated_instruction(vcpu); | |
11735 | ||
11736 | case INVPCID_TYPE_SINGLE_CTXT: | |
11737 | if (!pcid_enabled && (operand.pcid != 0)) { | |
11738 | kvm_inject_gp(vcpu, 0); | |
11739 | return 1; | |
11740 | } | |
11741 | ||
11742 | if (kvm_get_active_pcid(vcpu) == operand.pcid) { | |
11743 | kvm_mmu_sync_roots(vcpu); | |
11744 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
11745 | } | |
11746 | ||
11747 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
11748 | if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd) | |
11749 | == operand.pcid) | |
11750 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
11751 | ||
11752 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); | |
11753 | /* | |
11754 | * If neither the current cr3 nor any of the prev_roots use the | |
11755 | * given PCID, then nothing needs to be done here because a | |
11756 | * resync will happen anyway before switching to any other CR3. | |
11757 | */ | |
11758 | ||
11759 | return kvm_skip_emulated_instruction(vcpu); | |
11760 | ||
11761 | case INVPCID_TYPE_ALL_NON_GLOBAL: | |
11762 | /* | |
11763 | * Currently, KVM doesn't mark global entries in the shadow | |
11764 | * page tables, so a non-global flush just degenerates to a | |
11765 | * global flush. If needed, we could optimize this later by | |
11766 | * keeping track of global entries in shadow page tables. | |
11767 | */ | |
11768 | ||
11769 | fallthrough; | |
11770 | case INVPCID_TYPE_ALL_INCL_GLOBAL: | |
f66c53b3 | 11771 | kvm_make_request(KVM_REQ_MMU_RELOAD, vcpu); |
9715092f BM |
11772 | return kvm_skip_emulated_instruction(vcpu); |
11773 | ||
11774 | default: | |
11775 | BUG(); /* We have already checked above that type <= 3 */ | |
11776 | } | |
11777 | } | |
11778 | EXPORT_SYMBOL_GPL(kvm_handle_invpcid); | |
11779 | ||
8f423a80 TL |
11780 | static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) |
11781 | { | |
11782 | struct kvm_run *run = vcpu->run; | |
11783 | struct kvm_mmio_fragment *frag; | |
11784 | unsigned int len; | |
11785 | ||
11786 | BUG_ON(!vcpu->mmio_needed); | |
11787 | ||
11788 | /* Complete previous fragment */ | |
11789 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; | |
11790 | len = min(8u, frag->len); | |
11791 | if (!vcpu->mmio_is_write) | |
11792 | memcpy(frag->data, run->mmio.data, len); | |
11793 | ||
11794 | if (frag->len <= 8) { | |
11795 | /* Switch to the next fragment. */ | |
11796 | frag++; | |
11797 | vcpu->mmio_cur_fragment++; | |
11798 | } else { | |
11799 | /* Go forward to the next mmio piece. */ | |
11800 | frag->data += len; | |
11801 | frag->gpa += len; | |
11802 | frag->len -= len; | |
11803 | } | |
11804 | ||
11805 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { | |
11806 | vcpu->mmio_needed = 0; | |
11807 | ||
11808 | // VMG change, at this point, we're always done | |
11809 | // RIP has already been advanced | |
11810 | return 1; | |
11811 | } | |
11812 | ||
11813 | // More MMIO is needed | |
11814 | run->mmio.phys_addr = frag->gpa; | |
11815 | run->mmio.len = min(8u, frag->len); | |
11816 | run->mmio.is_write = vcpu->mmio_is_write; | |
11817 | if (run->mmio.is_write) | |
11818 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); | |
11819 | run->exit_reason = KVM_EXIT_MMIO; | |
11820 | ||
11821 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
11822 | ||
11823 | return 0; | |
11824 | } | |
11825 | ||
11826 | int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
11827 | void *data) | |
11828 | { | |
11829 | int handled; | |
11830 | struct kvm_mmio_fragment *frag; | |
11831 | ||
11832 | if (!data) | |
11833 | return -EINVAL; | |
11834 | ||
11835 | handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
11836 | if (handled == bytes) | |
11837 | return 1; | |
11838 | ||
11839 | bytes -= handled; | |
11840 | gpa += handled; | |
11841 | data += handled; | |
11842 | ||
11843 | /*TODO: Check if need to increment number of frags */ | |
11844 | frag = vcpu->mmio_fragments; | |
11845 | vcpu->mmio_nr_fragments = 1; | |
11846 | frag->len = bytes; | |
11847 | frag->gpa = gpa; | |
11848 | frag->data = data; | |
11849 | ||
11850 | vcpu->mmio_needed = 1; | |
11851 | vcpu->mmio_cur_fragment = 0; | |
11852 | ||
11853 | vcpu->run->mmio.phys_addr = gpa; | |
11854 | vcpu->run->mmio.len = min(8u, frag->len); | |
11855 | vcpu->run->mmio.is_write = 1; | |
11856 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); | |
11857 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
11858 | ||
11859 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
11860 | ||
11861 | return 0; | |
11862 | } | |
11863 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); | |
11864 | ||
11865 | int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
11866 | void *data) | |
11867 | { | |
11868 | int handled; | |
11869 | struct kvm_mmio_fragment *frag; | |
11870 | ||
11871 | if (!data) | |
11872 | return -EINVAL; | |
11873 | ||
11874 | handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
11875 | if (handled == bytes) | |
11876 | return 1; | |
11877 | ||
11878 | bytes -= handled; | |
11879 | gpa += handled; | |
11880 | data += handled; | |
11881 | ||
11882 | /*TODO: Check if need to increment number of frags */ | |
11883 | frag = vcpu->mmio_fragments; | |
11884 | vcpu->mmio_nr_fragments = 1; | |
11885 | frag->len = bytes; | |
11886 | frag->gpa = gpa; | |
11887 | frag->data = data; | |
11888 | ||
11889 | vcpu->mmio_needed = 1; | |
11890 | vcpu->mmio_cur_fragment = 0; | |
11891 | ||
11892 | vcpu->run->mmio.phys_addr = gpa; | |
11893 | vcpu->run->mmio.len = min(8u, frag->len); | |
11894 | vcpu->run->mmio.is_write = 0; | |
11895 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
11896 | ||
11897 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
11898 | ||
11899 | return 0; | |
11900 | } | |
11901 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); | |
11902 | ||
7ed9abfe TL |
11903 | static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) |
11904 | { | |
11905 | memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data, | |
11906 | vcpu->arch.pio.count * vcpu->arch.pio.size); | |
11907 | vcpu->arch.pio.count = 0; | |
11908 | ||
11909 | return 1; | |
11910 | } | |
11911 | ||
11912 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, | |
11913 | unsigned int port, void *data, unsigned int count) | |
11914 | { | |
11915 | int ret; | |
11916 | ||
11917 | ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port, | |
11918 | data, count); | |
11919 | if (ret) | |
11920 | return ret; | |
11921 | ||
11922 | vcpu->arch.pio.count = 0; | |
11923 | ||
11924 | return 0; | |
11925 | } | |
11926 | ||
11927 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, | |
11928 | unsigned int port, void *data, unsigned int count) | |
11929 | { | |
11930 | int ret; | |
11931 | ||
11932 | ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port, | |
11933 | data, count); | |
11934 | if (ret) { | |
11935 | vcpu->arch.pio.count = 0; | |
11936 | } else { | |
11937 | vcpu->arch.guest_ins_data = data; | |
11938 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; | |
11939 | } | |
11940 | ||
11941 | return 0; | |
11942 | } | |
11943 | ||
11944 | int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, | |
11945 | unsigned int port, void *data, unsigned int count, | |
11946 | int in) | |
11947 | { | |
11948 | return in ? kvm_sev_es_ins(vcpu, size, port, data, count) | |
11949 | : kvm_sev_es_outs(vcpu, size, port, data, count); | |
11950 | } | |
11951 | EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); | |
11952 | ||
d95df951 | 11953 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); |
229456fc | 11954 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 11955 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
11956 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
11957 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
11958 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
11959 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 11960 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 11961 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 11962 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 11963 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 11964 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 11965 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 11966 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 11967 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 11968 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 11969 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 11970 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 11971 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
11972 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
11973 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
ab56f8e6 | 11974 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); |
24bbf74c | 11975 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); |
d523ab6b TL |
11976 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); |
11977 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); | |
59e38b58 TL |
11978 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); |
11979 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); |