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Revert "KVM: allow host header to be included even for !CONFIG_KVM"
[mirror_ubuntu-focal-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
92a1f12d
JR		 97bool kvm_has_tsc_control;
98EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99u32 kvm_max_guest_tsc_khz;
100EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
cc578287
ZA		 102/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103static u32 tsc_tolerance_ppm = 250;
104module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
18863bdd
AK		 106#define KVM_NR_SHARED_MSRS 16
107
108struct kvm_shared_msrs_global {
109 int nr;
2bf78fa7 110 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 111};
112
113struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
2bf78fa7
SY		 116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 120};
121
122static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 123static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 124
417bc304 125struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 138 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 146 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 147 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 155 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 157 { "largepages", VM_STAT(lpages) },
417bc304
HB		 158 { NULL }
159};
160
2acf923e
DC		 161u64 __read_mostly host_xcr0;
162
b6785def 163static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 164
8b6e4547 165static int kvm_vcpu_reset(struct kvm_vcpu *vcpu);
d6aa1000 166
af585b92
GN		 167static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
168{
169 int i;
170 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
171 vcpu->arch.apf.gfns[i] = ~0;
172}
173
18863bdd
AK		 174static void kvm_on_user_return(struct user_return_notifier *urn)
175{
176 unsigned slot;
18863bdd
AK		 177 struct kvm_shared_msrs *locals
178 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 179 struct kvm_shared_msr_values *values;
18863bdd
AK		 180
181 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 182 values = &locals->values[slot];
183 if (values->host != values->curr) {
184 wrmsrl(shared_msrs_global.msrs[slot], values->host);
185 values->curr = values->host;
18863bdd
AK		 186 }
187 }
188 locals->registered = false;
189 user_return_notifier_unregister(urn);
190}
191
2bf78fa7 192static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 193{
18863bdd 194 u64 value;
013f6a5d
MT		 195 unsigned int cpu = smp_processor_id();
196 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 197
2bf78fa7
SY		 198 /* only read, and nobody should modify it at this time,
199 * so don't need lock */
200 if (slot >= shared_msrs_global.nr) {
201 printk(KERN_ERR "kvm: invalid MSR slot!");
202 return;
203 }
204 rdmsrl_safe(msr, &value);
205 smsr->values[slot].host = value;
206 smsr->values[slot].curr = value;
207}
208
209void kvm_define_shared_msr(unsigned slot, u32 msr)
210{
18863bdd
AK		 211 if (slot >= shared_msrs_global.nr)
212 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 213 shared_msrs_global.msrs[slot] = msr;
214 /* we need ensured the shared_msr_global have been updated */
215 smp_wmb();
18863bdd
AK		 216}
217EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
218
219static void kvm_shared_msr_cpu_online(void)
220{
221 unsigned i;
18863bdd
AK		 222
223 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 224 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 225}
226
d5696725 227void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 228{
013f6a5d
MT		 229 unsigned int cpu = smp_processor_id();
230 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 231
2bf78fa7 232 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 233 return;
2bf78fa7
SY		 234 smsr->values[slot].curr = value;
235 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 236 if (!smsr->registered) {
237 smsr->urn.on_user_return = kvm_on_user_return;
238 user_return_notifier_register(&smsr->urn);
239 smsr->registered = true;
240 }
241}
242EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
243
3548bab5
AK		 244static void drop_user_return_notifiers(void *ignore)
245{
013f6a5d
MT		 246 unsigned int cpu = smp_processor_id();
247 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 248
249 if (smsr->registered)
250 kvm_on_user_return(&smsr->urn);
251}
252
6866b83e
CO		 253u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
254{
8a5a87d9 255 return vcpu->arch.apic_base;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_get_apic_base);
258
259void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
260{
261 /* TODO: reserve bits check */
8a5a87d9 262 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 263}
264EXPORT_SYMBOL_GPL(kvm_set_apic_base);
265
3fd28fce
ED		 266#define EXCPT_BENIGN 0
267#define EXCPT_CONTRIBUTORY 1
268#define EXCPT_PF 2
269
270static int exception_class(int vector)
271{
272 switch (vector) {
273 case PF_VECTOR:
274 return EXCPT_PF;
275 case DE_VECTOR:
276 case TS_VECTOR:
277 case NP_VECTOR:
278 case SS_VECTOR:
279 case GP_VECTOR:
280 return EXCPT_CONTRIBUTORY;
281 default:
282 break;
283 }
284 return EXCPT_BENIGN;
285}
286
287static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 288 unsigned nr, bool has_error, u32 error_code,
289 bool reinject)
3fd28fce
ED		 290{
291 u32 prev_nr;
292 int class1, class2;
293
3842d135
AK		 294 kvm_make_request(KVM_REQ_EVENT, vcpu);
295
3fd28fce
ED		 296 if (!vcpu->arch.exception.pending) {
297 queue:
298 vcpu->arch.exception.pending = true;
299 vcpu->arch.exception.has_error_code = has_error;
300 vcpu->arch.exception.nr = nr;
301 vcpu->arch.exception.error_code = error_code;
3f0fd292 302 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 303 return;
304 }
305
306 /* to check exception */
307 prev_nr = vcpu->arch.exception.nr;
308 if (prev_nr == DF_VECTOR) {
309 /* triple fault -> shutdown */
a8eeb04a 310 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 311 return;
312 }
313 class1 = exception_class(prev_nr);
314 class2 = exception_class(nr);
315 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
316 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
317 /* generate double fault per SDM Table 5-5 */
318 vcpu->arch.exception.pending = true;
319 vcpu->arch.exception.has_error_code = true;
320 vcpu->arch.exception.nr = DF_VECTOR;
321 vcpu->arch.exception.error_code = 0;
322 } else
323 /* replace previous exception with a new one in a hope
324 that instruction re-execution will regenerate lost
325 exception */
326 goto queue;
327}
328
298101da
AK		 329void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
ce7ddec4 331 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 332}
333EXPORT_SYMBOL_GPL(kvm_queue_exception);
334
ce7ddec4
JR		 335void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
336{
337 kvm_multiple_exception(vcpu, nr, false, 0, true);
338}
339EXPORT_SYMBOL_GPL(kvm_requeue_exception);
340
db8fcefa 341void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 342{
db8fcefa
AP		 343 if (err)
344 kvm_inject_gp(vcpu, 0);
345 else
346 kvm_x86_ops->skip_emulated_instruction(vcpu);
347}
348EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 349
6389ee94 350void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 351{
352 ++vcpu->stat.pf_guest;
6389ee94
AK		 353 vcpu->arch.cr2 = fault->address;
354 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 355}
27d6c865 356EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 357
6389ee94 358void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 359{
6389ee94
AK		 360 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
361 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 362 else
6389ee94 363 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 364}
365
3419ffc8
SY		 366void kvm_inject_nmi(struct kvm_vcpu *vcpu)
367{
7460fb4a
AK		 368 atomic_inc(&vcpu->arch.nmi_queued);
369 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 370}
371EXPORT_SYMBOL_GPL(kvm_inject_nmi);
372
298101da
AK		 373void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374{
ce7ddec4 375 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 376}
377EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
378
ce7ddec4
JR		 379void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
380{
381 kvm_multiple_exception(vcpu, nr, true, error_code, true);
382}
383EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
384
0a79b009
AK		 385/*
386 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
387 * a #GP and return false.
388 */
389bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 390{
0a79b009
AK		 391 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
392 return true;
393 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
394 return false;
298101da 395}
0a79b009 396EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 397
ec92fe44
JR		 398/*
399 * This function will be used to read from the physical memory of the currently
400 * running guest. The difference to kvm_read_guest_page is that this function
401 * can read from guest physical or from the guest's guest physical memory.
402 */
403int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
404 gfn_t ngfn, void *data, int offset, int len,
405 u32 access)
406{
407 gfn_t real_gfn;
408 gpa_t ngpa;
409
410 ngpa = gfn_to_gpa(ngfn);
411 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
412 if (real_gfn == UNMAPPED_GVA)
413 return -EFAULT;
414
415 real_gfn = gpa_to_gfn(real_gfn);
416
417 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
418}
419EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
420
3d06b8bf
JR		 421int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
422 void *data, int offset, int len, u32 access)
423{
424 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
425 data, offset, len, access);
426}
427
a03490ed
CO		 428/*
429 * Load the pae pdptrs. Return true is they are all valid.
430 */
ff03a073 431int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 432{
433 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
434 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
435 int i;
436 int ret;
ff03a073 437 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 438
ff03a073
JR		 439 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
440 offset * sizeof(u64), sizeof(pdpte),
441 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 442 if (ret < 0) {
443 ret = 0;
444 goto out;
445 }
446 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 447 if (is_present_gpte(pdpte[i]) &&
20c466b5 448 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 449 ret = 0;
450 goto out;
451 }
452 }
453 ret = 1;
454
ff03a073 455 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_avail);
458 __set_bit(VCPU_EXREG_PDPTR,
459 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 460out:
a03490ed
CO		 461
462 return ret;
463}
cc4b6871 464EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 465
d835dfec
AK		 466static bool pdptrs_changed(struct kvm_vcpu *vcpu)
467{
ff03a073 468 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 469 bool changed = true;
3d06b8bf
JR		 470 int offset;
471 gfn_t gfn;
d835dfec
AK		 472 int r;
473
474 if (is_long_mode(vcpu) || !is_pae(vcpu))
475 return false;
476
6de4f3ad
AK		 477 if (!test_bit(VCPU_EXREG_PDPTR,
478 (unsigned long *)&vcpu->arch.regs_avail))
479 return true;
480
9f8fe504
AK		 481 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
482 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 483 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
484 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 485 if (r < 0)
486 goto out;
ff03a073 487 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 488out:
d835dfec
AK		 489
490 return changed;
491}
492
49a9b07e 493int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 494{
aad82703
SY		 495 unsigned long old_cr0 = kvm_read_cr0(vcpu);
496 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
497 X86_CR0_CD | X86_CR0_NW;
498
f9a48e6a
AK		 499 cr0 |= X86_CR0_ET;
500
ab344828 501#ifdef CONFIG_X86_64
0f12244f
GN		 502 if (cr0 & 0xffffffff00000000UL)
503 return 1;
ab344828
GN		 504#endif
505
506 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 507
0f12244f
GN		 508 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
509 return 1;
a03490ed 510
0f12244f
GN		 511 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
512 return 1;
a03490ed
CO		 513
514 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
515#ifdef CONFIG_X86_64
f6801dff 516 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 517 int cs_db, cs_l;
518
0f12244f
GN		 519 if (!is_pae(vcpu))
520 return 1;
a03490ed 521 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 522 if (cs_l)
523 return 1;
a03490ed
CO		 524 } else
525#endif
ff03a073 526 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 527 kvm_read_cr3(vcpu)))
0f12244f 528 return 1;
a03490ed
CO		 529 }
530
ad756a16
MJ		 531 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
532 return 1;
533
a03490ed 534 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 535
d170c419 536 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 537 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 538 kvm_async_pf_hash_reset(vcpu);
539 }
e5f3f027 540
aad82703
SY		 541 if ((cr0 ^ old_cr0) & update_bits)
542 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 543 return 0;
544}
2d3ad1f4 545EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 546
2d3ad1f4 547void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 548{
49a9b07e 549 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 550}
2d3ad1f4 551EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 552
2acf923e
DC		 553int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
554{
555 u64 xcr0;
556
557 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
558 if (index != XCR_XFEATURE_ENABLED_MASK)
559 return 1;
560 xcr0 = xcr;
561 if (kvm_x86_ops->get_cpl(vcpu) != 0)
562 return 1;
563 if (!(xcr0 & XSTATE_FP))
564 return 1;
565 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
566 return 1;
567 if (xcr0 & ~host_xcr0)
568 return 1;
569 vcpu->arch.xcr0 = xcr0;
570 vcpu->guest_xcr0_loaded = 0;
571 return 0;
572}
573
574int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
575{
576 if (__kvm_set_xcr(vcpu, index, xcr)) {
577 kvm_inject_gp(vcpu, 0);
578 return 1;
579 }
580 return 0;
581}
582EXPORT_SYMBOL_GPL(kvm_set_xcr);
583
a83b29c6 584int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 585{
fc78f519 586 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 587 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
588 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 589 if (cr4 & CR4_RESERVED_BITS)
590 return 1;
a03490ed 591
2acf923e
DC		 592 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
593 return 1;
594
c68b734f
YW		 595 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
596 return 1;
597
74dc2b4f
YW		 598 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
599 return 1;
600
a03490ed 601 if (is_long_mode(vcpu)) {
0f12244f
GN		 602 if (!(cr4 & X86_CR4_PAE))
603 return 1;
a2edf57f
AK		 604 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 606 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
607 kvm_read_cr3(vcpu)))
0f12244f
GN		 608 return 1;
609
ad756a16
MJ		 610 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
611 if (!guest_cpuid_has_pcid(vcpu))
612 return 1;
613
614 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
615 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
616 return 1;
617 }
618
5e1746d6 619 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 620 return 1;
a03490ed 621
ad756a16
MJ		 622 if (((cr4 ^ old_cr4) & pdptr_bits) ||
623 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 624 kvm_mmu_reset_context(vcpu);
0f12244f 625
2acf923e 626 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 627 kvm_update_cpuid(vcpu);
2acf923e 628
0f12244f
GN		 629 return 0;
630}
2d3ad1f4 631EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 632
2390218b 633int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 634{
9f8fe504 635 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 636 kvm_mmu_sync_roots(vcpu);
d835dfec 637 kvm_mmu_flush_tlb(vcpu);
0f12244f 638 return 0;
d835dfec
AK		 639 }
640
a03490ed 641 if (is_long_mode(vcpu)) {
471842ec 642 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 643 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
644 return 1;
645 } else
646 if (cr3 & CR3_L_MODE_RESERVED_BITS)
647 return 1;
a03490ed
CO		 648 } else {
649 if (is_pae(vcpu)) {
0f12244f
GN		 650 if (cr3 & CR3_PAE_RESERVED_BITS)
651 return 1;
ff03a073
JR		 652 if (is_paging(vcpu) &&
653 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 654 return 1;
a03490ed
CO		 655 }
656 /*
657 * We don't check reserved bits in nonpae mode, because
658 * this isn't enforced, and VMware depends on this.
659 */
660 }
661
a03490ed
CO		 662 /*
663 * Does the new cr3 value map to physical memory? (Note, we
664 * catch an invalid cr3 even in real-mode, because it would
665 * cause trouble later on when we turn on paging anyway.)
666 *
667 * A real CPU would silently accept an invalid cr3 and would
668 * attempt to use it - with largely undefined (and often hard
669 * to debug) behavior on the guest side.
670 */
671 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 672 return 1;
673 vcpu->arch.cr3 = cr3;
aff48baa 674 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 675 vcpu->arch.mmu.new_cr3(vcpu);
676 return 0;
677}
2d3ad1f4 678EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 679
eea1cff9 680int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 681{
0f12244f
GN		 682 if (cr8 & CR8_RESERVED_BITS)
683 return 1;
a03490ed
CO		 684 if (irqchip_in_kernel(vcpu->kvm))
685 kvm_lapic_set_tpr(vcpu, cr8);
686 else
ad312c7c 687 vcpu->arch.cr8 = cr8;
0f12244f
GN		 688 return 0;
689}
2d3ad1f4 690EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 691
2d3ad1f4 692unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 693{
694 if (irqchip_in_kernel(vcpu->kvm))
695 return kvm_lapic_get_cr8(vcpu);
696 else
ad312c7c 697 return vcpu->arch.cr8;
a03490ed 698}
2d3ad1f4 699EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 700
c8639010
JK		 701static void kvm_update_dr7(struct kvm_vcpu *vcpu)
702{
703 unsigned long dr7;
704
705 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
706 dr7 = vcpu->arch.guest_debug_dr7;
707 else
708 dr7 = vcpu->arch.dr7;
709 kvm_x86_ops->set_dr7(vcpu, dr7);
710 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
711}
712
338dbc97 713static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 714{
715 switch (dr) {
716 case 0 ... 3:
717 vcpu->arch.db[dr] = val;
718 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
719 vcpu->arch.eff_db[dr] = val;
720 break;
721 case 4:
338dbc97
GN		 722 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
723 return 1; /* #UD */
020df079
GN		 724 /* fall through */
725 case 6:
338dbc97
GN		 726 if (val & 0xffffffff00000000ULL)
727 return -1; /* #GP */
020df079
GN		 728 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
729 break;
730 case 5:
338dbc97
GN		 731 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
732 return 1; /* #UD */
020df079
GN		 733 /* fall through */
734 default: /* 7 */
338dbc97
GN		 735 if (val & 0xffffffff00000000ULL)
736 return -1; /* #GP */
020df079 737 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 738 kvm_update_dr7(vcpu);
020df079
GN		 739 break;
740 }
741
742 return 0;
743}
338dbc97
GN		 744
745int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
746{
747 int res;
748
749 res = __kvm_set_dr(vcpu, dr, val);
750 if (res > 0)
751 kvm_queue_exception(vcpu, UD_VECTOR);
752 else if (res < 0)
753 kvm_inject_gp(vcpu, 0);
754
755 return res;
756}
020df079
GN		 757EXPORT_SYMBOL_GPL(kvm_set_dr);
758
338dbc97 759static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 760{
761 switch (dr) {
762 case 0 ... 3:
763 *val = vcpu->arch.db[dr];
764 break;
765 case 4:
338dbc97 766 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 767 return 1;
020df079
GN		 768 /* fall through */
769 case 6:
770 *val = vcpu->arch.dr6;
771 break;
772 case 5:
338dbc97 773 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 774 return 1;
020df079
GN		 775 /* fall through */
776 default: /* 7 */
777 *val = vcpu->arch.dr7;
778 break;
779 }
780
781 return 0;
782}
338dbc97
GN		 783
784int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
785{
786 if (_kvm_get_dr(vcpu, dr, val)) {
787 kvm_queue_exception(vcpu, UD_VECTOR);
788 return 1;
789 }
790 return 0;
791}
020df079
GN		 792EXPORT_SYMBOL_GPL(kvm_get_dr);
793
022cd0e8
AK		 794bool kvm_rdpmc(struct kvm_vcpu *vcpu)
795{
796 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
797 u64 data;
798 int err;
799
800 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
801 if (err)
802 return err;
803 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
804 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
805 return err;
806}
807EXPORT_SYMBOL_GPL(kvm_rdpmc);
808
043405e1
CO		 809/*
810 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
811 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
812 *
813 * This list is modified at module load time to reflect the
e3267cbb
GC		 814 * capabilities of the host cpu. This capabilities test skips MSRs that are
815 * kvm-specific. Those are put in the beginning of the list.
043405e1 816 */
e3267cbb 817
439793d4 818#define KVM_SAVE_MSRS_BEGIN 10
043405e1 819static u32 msrs_to_save[] = {
e3267cbb 820 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 821 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 822 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 823 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 824 MSR_KVM_PV_EOI_EN,
043405e1 825 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 826 MSR_STAR,
043405e1
CO		 827#ifdef CONFIG_X86_64
828 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
829#endif
e90aa41e 830 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 831};
832
833static unsigned num_msrs_to_save;
834
f1d24831 835static const u32 emulated_msrs[] = {
ba904635 836 MSR_IA32_TSC_ADJUST,
a3e06bbe 837 MSR_IA32_TSCDEADLINE,
043405e1 838 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 839 MSR_IA32_MCG_STATUS,
840 MSR_IA32_MCG_CTL,
043405e1
CO		 841};
842
b69e8cae 843static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 844{
aad82703
SY		 845 u64 old_efer = vcpu->arch.efer;
846
b69e8cae
RJ		 847 if (efer & efer_reserved_bits)
848 return 1;
15c4a640
CO		 849
850 if (is_paging(vcpu)
b69e8cae
RJ		 851 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
852 return 1;
15c4a640 853
1b2fd70c
AG		 854 if (efer & EFER_FFXSR) {
855 struct kvm_cpuid_entry2 *feat;
856
857 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 858 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
859 return 1;
1b2fd70c
AG		 860 }
861
d8017474
AG		 862 if (efer & EFER_SVME) {
863 struct kvm_cpuid_entry2 *feat;
864
865 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 866 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
867 return 1;
d8017474
AG		 868 }
869
15c4a640 870 efer &= ~EFER_LMA;
f6801dff 871 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 872
a3d204e2
SY		 873 kvm_x86_ops->set_efer(vcpu, efer);
874
aad82703
SY		 875 /* Update reserved bits */
876 if ((efer ^ old_efer) & EFER_NX)
877 kvm_mmu_reset_context(vcpu);
878
b69e8cae 879 return 0;
15c4a640
CO		 880}
881
f2b4b7dd
JR		 882void kvm_enable_efer_bits(u64 mask)
883{
884 efer_reserved_bits &= ~mask;
885}
886EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
887
888
15c4a640
CO		 889/*
890 * Writes msr value into into the appropriate "register".
891 * Returns 0 on success, non-0 otherwise.
892 * Assumes vcpu_load() was already called.
893 */
8fe8ab46 894int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 895{
8fe8ab46 896 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 897}
898
313a3dc7
CO		 899/*
900 * Adapt set_msr() to msr_io()'s calling convention
901 */
902static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
903{
8fe8ab46
WA		 904 struct msr_data msr;
905
906 msr.data = *data;
907 msr.index = index;
908 msr.host_initiated = true;
909 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 910}
911
16e8d74d
MT		 912#ifdef CONFIG_X86_64
913struct pvclock_gtod_data {
914 seqcount_t seq;
915
916 struct { /* extract of a clocksource struct */
917 int vclock_mode;
918 cycle_t cycle_last;
919 cycle_t mask;
920 u32 mult;
921 u32 shift;
922 } clock;
923
924 /* open coded 'struct timespec' */
925 u64 monotonic_time_snsec;
926 time_t monotonic_time_sec;
927};
928
929static struct pvclock_gtod_data pvclock_gtod_data;
930
931static void update_pvclock_gtod(struct timekeeper *tk)
932{
933 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
934
935 write_seqcount_begin(&vdata->seq);
936
937 /* copy pvclock gtod data */
938 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
939 vdata->clock.cycle_last = tk->clock->cycle_last;
940 vdata->clock.mask = tk->clock->mask;
941 vdata->clock.mult = tk->mult;
942 vdata->clock.shift = tk->shift;
943
944 vdata->monotonic_time_sec = tk->xtime_sec
945 + tk->wall_to_monotonic.tv_sec;
946 vdata->monotonic_time_snsec = tk->xtime_nsec
947 + (tk->wall_to_monotonic.tv_nsec
948 << tk->shift);
949 while (vdata->monotonic_time_snsec >=
950 (((u64)NSEC_PER_SEC) << tk->shift)) {
951 vdata->monotonic_time_snsec -=
952 ((u64)NSEC_PER_SEC) << tk->shift;
953 vdata->monotonic_time_sec++;
954 }
955
956 write_seqcount_end(&vdata->seq);
957}
958#endif
959
960
18068523
GOC		 961static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
962{
9ed3c444
AK		 963 int version;
964 int r;
50d0a0f9 965 struct pvclock_wall_clock wc;
923de3cf 966 struct timespec boot;
18068523
GOC		 967
968 if (!wall_clock)
969 return;
970
9ed3c444
AK		 971 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
972 if (r)
973 return;
974
975 if (version & 1)
976 ++version; /* first time write, random junk */
977
978 ++version;
18068523 979
18068523
GOC		 980 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
981
50d0a0f9
GH		 982 /*
983 * The guest calculates current wall clock time by adding
34c238a1 984 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 985 * wall clock specified here. guest system time equals host
986 * system time for us, thus we must fill in host boot time here.
987 */
923de3cf 988 getboottime(&boot);
50d0a0f9 989
4b648665
BR		 990 if (kvm->arch.kvmclock_offset) {
991 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
992 boot = timespec_sub(boot, ts);
993 }
50d0a0f9
GH		 994 wc.sec = boot.tv_sec;
995 wc.nsec = boot.tv_nsec;
996 wc.version = version;
18068523
GOC		 997
998 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
999
1000 version++;
1001 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1002}
1003
50d0a0f9
GH		 1004static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1005{
1006 uint32_t quotient, remainder;
1007
1008 /* Don't try to replace with do_div(), this one calculates
1009 * "(dividend << 32) / divisor" */
1010 __asm__ ( "divl %4"
1011 : "=a" (quotient), "=d" (remainder)
1012 : "0" (0), "1" (dividend), "r" (divisor) );
1013 return quotient;
1014}
1015
5f4e3f88
ZA		 1016static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1017 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1018{
5f4e3f88 1019 uint64_t scaled64;
50d0a0f9
GH		 1020 int32_t shift = 0;
1021 uint64_t tps64;
1022 uint32_t tps32;
1023
5f4e3f88
ZA		 1024 tps64 = base_khz * 1000LL;
1025 scaled64 = scaled_khz * 1000LL;
50933623 1026 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1027 tps64 >>= 1;
1028 shift--;
1029 }
1030
1031 tps32 = (uint32_t)tps64;
50933623
JK		 1032 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1033 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1034 scaled64 >>= 1;
1035 else
1036 tps32 <<= 1;
50d0a0f9
GH		 1037 shift++;
1038 }
1039
5f4e3f88
ZA		 1040 *pshift = shift;
1041 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1042
5f4e3f88
ZA		 1043 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1044 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1045}
1046
759379dd
ZA		 1047static inline u64 get_kernel_ns(void)
1048{
1049 struct timespec ts;
1050
1051 WARN_ON(preemptible());
1052 ktime_get_ts(&ts);
1053 monotonic_to_bootbased(&ts);
1054 return timespec_to_ns(&ts);
50d0a0f9
GH		 1055}
1056
d828199e 1057#ifdef CONFIG_X86_64
16e8d74d 1058static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1059#endif
16e8d74d 1060
c8076604 1061static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1062unsigned long max_tsc_khz;
c8076604 1063
cc578287 1064static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1065{
cc578287
ZA		 1066 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1067 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1068}
1069
cc578287 1070static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1071{
cc578287
ZA		 1072 u64 v = (u64)khz * (1000000 + ppm);
1073 do_div(v, 1000000);
1074 return v;
1e993611
JR		 1075}
1076
cc578287 1077static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1078{
cc578287
ZA		 1079 u32 thresh_lo, thresh_hi;
1080 int use_scaling = 0;
217fc9cf 1081
c285545f
ZA		 1082 /* Compute a scale to convert nanoseconds in TSC cycles */
1083 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1084 &vcpu->arch.virtual_tsc_shift,
1085 &vcpu->arch.virtual_tsc_mult);
1086 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1087
1088 /*
1089 * Compute the variation in TSC rate which is acceptable
1090 * within the range of tolerance and decide if the
1091 * rate being applied is within that bounds of the hardware
1092 * rate. If so, no scaling or compensation need be done.
1093 */
1094 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1095 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1096 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1097 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1098 use_scaling = 1;
1099 }
1100 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1101}
1102
1103static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1104{
e26101b1 1105 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1106 vcpu->arch.virtual_tsc_mult,
1107 vcpu->arch.virtual_tsc_shift);
e26101b1 1108 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1109 return tsc;
1110}
1111
b48aa97e
MT		 1112void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1113{
1114#ifdef CONFIG_X86_64
1115 bool vcpus_matched;
1116 bool do_request = false;
1117 struct kvm_arch *ka = &vcpu->kvm->arch;
1118 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1119
1120 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1121 atomic_read(&vcpu->kvm->online_vcpus));
1122
1123 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1124 if (!ka->use_master_clock)
1125 do_request = 1;
1126
1127 if (!vcpus_matched && ka->use_master_clock)
1128 do_request = 1;
1129
1130 if (do_request)
1131 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1132
1133 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1134 atomic_read(&vcpu->kvm->online_vcpus),
1135 ka->use_master_clock, gtod->clock.vclock_mode);
1136#endif
1137}
1138
ba904635
WA		 1139static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1140{
1141 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1142 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1143}
1144
8fe8ab46 1145void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1146{
1147 struct kvm *kvm = vcpu->kvm;
f38e098f 1148 u64 offset, ns, elapsed;
99e3e30a 1149 unsigned long flags;
02626b6a 1150 s64 usdiff;
b48aa97e 1151 bool matched;
8fe8ab46 1152 u64 data = msr->data;
99e3e30a 1153
038f8c11 1154 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1155 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1156 ns = get_kernel_ns();
f38e098f 1157 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1158
1159 /* n.b - signed multiplication and division required */
02626b6a 1160 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1161#ifdef CONFIG_X86_64
02626b6a 1162 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6
ZA		 1163#else
1164 /* do_div() only does unsigned */
1165 asm("idivl %2; xor %%edx, %%edx"
02626b6a
MT		 1166 : "=A"(usdiff)
1167 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1168#endif
02626b6a
MT		 1169 do_div(elapsed, 1000);
1170 usdiff -= elapsed;
1171 if (usdiff < 0)
1172 usdiff = -usdiff;
f38e098f
ZA		 1173
1174 /*
5d3cb0f6
ZA		 1175 * Special case: TSC write with a small delta (1 second) of virtual
1176 * cycle time against real time is interpreted as an attempt to
1177 * synchronize the CPU.
1178 *
1179 * For a reliable TSC, we can match TSC offsets, and for an unstable
1180 * TSC, we add elapsed time in this computation. We could let the
1181 * compensation code attempt to catch up if we fall behind, but
1182 * it's better to try to match offsets from the beginning.
1183 */
02626b6a 1184 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1185 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1186 if (!check_tsc_unstable()) {
e26101b1 1187 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1188 pr_debug("kvm: matched tsc offset for %llu\n", data);
1189 } else {
857e4099 1190 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1191 data += delta;
1192 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1193 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1194 }
b48aa97e 1195 matched = true;
e26101b1
ZA		 1196 } else {
1197 /*
1198 * We split periods of matched TSC writes into generations.
1199 * For each generation, we track the original measured
1200 * nanosecond time, offset, and write, so if TSCs are in
1201 * sync, we can match exact offset, and if not, we can match
4a969980 1202 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1203 *
1204 * These values are tracked in kvm->arch.cur_xxx variables.
1205 */
1206 kvm->arch.cur_tsc_generation++;
1207 kvm->arch.cur_tsc_nsec = ns;
1208 kvm->arch.cur_tsc_write = data;
1209 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1210 matched = false;
e26101b1
ZA		 1211 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1212 kvm->arch.cur_tsc_generation, data);
f38e098f 1213 }
e26101b1
ZA		 1214
1215 /*
1216 * We also track th most recent recorded KHZ, write and time to
1217 * allow the matching interval to be extended at each write.
1218 */
f38e098f
ZA		 1219 kvm->arch.last_tsc_nsec = ns;
1220 kvm->arch.last_tsc_write = data;
5d3cb0f6 1221 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1222
1223 /* Reset of TSC must disable overshoot protection below */
1224 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1225 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1226
1227 /* Keep track of which generation this VCPU has synchronized to */
1228 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1229 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1230 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1231
ba904635
WA		 1232 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1233 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1234 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1235 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1236
1237 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1238 if (matched)
1239 kvm->arch.nr_vcpus_matched_tsc++;
1240 else
1241 kvm->arch.nr_vcpus_matched_tsc = 0;
1242
1243 kvm_track_tsc_matching(vcpu);
1244 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1245}
e26101b1 1246
99e3e30a
ZA		 1247EXPORT_SYMBOL_GPL(kvm_write_tsc);
1248
d828199e
MT		 1249#ifdef CONFIG_X86_64
1250
1251static cycle_t read_tsc(void)
1252{
1253 cycle_t ret;
1254 u64 last;
1255
1256 /*
1257 * Empirically, a fence (of type that depends on the CPU)
1258 * before rdtsc is enough to ensure that rdtsc is ordered
1259 * with respect to loads. The various CPU manuals are unclear
1260 * as to whether rdtsc can be reordered with later loads,
1261 * but no one has ever seen it happen.
1262 */
1263 rdtsc_barrier();
1264 ret = (cycle_t)vget_cycles();
1265
1266 last = pvclock_gtod_data.clock.cycle_last;
1267
1268 if (likely(ret >= last))
1269 return ret;
1270
1271 /*
1272 * GCC likes to generate cmov here, but this branch is extremely
1273 * predictable (it's just a funciton of time and the likely is
1274 * very likely) and there's a data dependence, so force GCC
1275 * to generate a branch instead. I don't barrier() because
1276 * we don't actually need a barrier, and if this function
1277 * ever gets inlined it will generate worse code.
1278 */
1279 asm volatile ("");
1280 return last;
1281}
1282
1283static inline u64 vgettsc(cycle_t *cycle_now)
1284{
1285 long v;
1286 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1287
1288 *cycle_now = read_tsc();
1289
1290 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1291 return v * gtod->clock.mult;
1292}
1293
1294static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1295{
1296 unsigned long seq;
1297 u64 ns;
1298 int mode;
1299 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1300
1301 ts->tv_nsec = 0;
1302 do {
1303 seq = read_seqcount_begin(&gtod->seq);
1304 mode = gtod->clock.vclock_mode;
1305 ts->tv_sec = gtod->monotonic_time_sec;
1306 ns = gtod->monotonic_time_snsec;
1307 ns += vgettsc(cycle_now);
1308 ns >>= gtod->clock.shift;
1309 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1310 timespec_add_ns(ts, ns);
1311
1312 return mode;
1313}
1314
1315/* returns true if host is using tsc clocksource */
1316static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1317{
1318 struct timespec ts;
1319
1320 /* checked again under seqlock below */
1321 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1322 return false;
1323
1324 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1325 return false;
1326
1327 monotonic_to_bootbased(&ts);
1328 *kernel_ns = timespec_to_ns(&ts);
1329
1330 return true;
1331}
1332#endif
1333
1334/*
1335 *
b48aa97e
MT		 1336 * Assuming a stable TSC across physical CPUS, and a stable TSC
1337 * across virtual CPUs, the following condition is possible.
1338 * Each numbered line represents an event visible to both
d828199e
MT		 1339 * CPUs at the next numbered event.
1340 *
1341 * "timespecX" represents host monotonic time. "tscX" represents
1342 * RDTSC value.
1343 *
1344 * VCPU0 on CPU0 | VCPU1 on CPU1
1345 *
1346 * 1. read timespec0,tsc0
1347 * 2. | timespec1 = timespec0 + N
1348 * | tsc1 = tsc0 + M
1349 * 3. transition to guest | transition to guest
1350 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1351 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1352 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1353 *
1354 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1355 *
1356 * - ret0 < ret1
1357 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1358 * ...
1359 * - 0 < N - M => M < N
1360 *
1361 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1362 * always the case (the difference between two distinct xtime instances
1363 * might be smaller then the difference between corresponding TSC reads,
1364 * when updating guest vcpus pvclock areas).
1365 *
1366 * To avoid that problem, do not allow visibility of distinct
1367 * system_timestamp/tsc_timestamp values simultaneously: use a master
1368 * copy of host monotonic time values. Update that master copy
1369 * in lockstep.
1370 *
b48aa97e 1371 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1372 *
1373 */
1374
1375static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1376{
1377#ifdef CONFIG_X86_64
1378 struct kvm_arch *ka = &kvm->arch;
1379 int vclock_mode;
b48aa97e
MT		 1380 bool host_tsc_clocksource, vcpus_matched;
1381
1382 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1383 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1384
1385 /*
1386 * If the host uses TSC clock, then passthrough TSC as stable
1387 * to the guest.
1388 */
b48aa97e 1389 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1390 &ka->master_kernel_ns,
1391 &ka->master_cycle_now);
1392
b48aa97e
MT		 1393 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1394
d828199e
MT		 1395 if (ka->use_master_clock)
1396 atomic_set(&kvm_guest_has_master_clock, 1);
1397
1398 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1399 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1400 vcpus_matched);
d828199e
MT		 1401#endif
1402}
1403
34c238a1 1404static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1405{
d828199e 1406 unsigned long flags, this_tsc_khz;
18068523 1407 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1408 struct kvm_arch *ka = &v->kvm->arch;
1d5f066e 1409 s64 kernel_ns, max_kernel_ns;
d828199e 1410 u64 tsc_timestamp, host_tsc;
0b79459b 1411 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1412 u8 pvclock_flags;
d828199e
MT		 1413 bool use_master_clock;
1414
1415 kernel_ns = 0;
1416 host_tsc = 0;
18068523 1417
d828199e
MT		 1418 /*
1419 * If the host uses TSC clock, then passthrough TSC as stable
1420 * to the guest.
1421 */
1422 spin_lock(&ka->pvclock_gtod_sync_lock);
1423 use_master_clock = ka->use_master_clock;
1424 if (use_master_clock) {
1425 host_tsc = ka->master_cycle_now;
1426 kernel_ns = ka->master_kernel_ns;
1427 }
1428 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1429
1430 /* Keep irq disabled to prevent changes to the clock */
1431 local_irq_save(flags);
1432 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1433 if (unlikely(this_tsc_khz == 0)) {
1434 local_irq_restore(flags);
1435 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1436 return 1;
1437 }
d828199e
MT		 1438 if (!use_master_clock) {
1439 host_tsc = native_read_tsc();
1440 kernel_ns = get_kernel_ns();
1441 }
1442
1443 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1444
c285545f
ZA		 1445 /*
1446 * We may have to catch up the TSC to match elapsed wall clock
1447 * time for two reasons, even if kvmclock is used.
1448 * 1) CPU could have been running below the maximum TSC rate
1449 * 2) Broken TSC compensation resets the base at each VCPU
1450 * entry to avoid unknown leaps of TSC even when running
1451 * again on the same CPU. This may cause apparent elapsed
1452 * time to disappear, and the guest to stand still or run
1453 * very slowly.
1454 */
1455 if (vcpu->tsc_catchup) {
1456 u64 tsc = compute_guest_tsc(v, kernel_ns);
1457 if (tsc > tsc_timestamp) {
f1e2b260 1458 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1459 tsc_timestamp = tsc;
1460 }
50d0a0f9
GH		 1461 }
1462
18068523
GOC		 1463 local_irq_restore(flags);
1464
0b79459b 1465 if (!vcpu->pv_time_enabled)
c285545f 1466 return 0;
18068523 1467
1d5f066e
ZA		 1468 /*
1469 * Time as measured by the TSC may go backwards when resetting the base
1470 * tsc_timestamp. The reason for this is that the TSC resolution is
1471 * higher than the resolution of the other clock scales. Thus, many
1472 * possible measurments of the TSC correspond to one measurement of any
1473 * other clock, and so a spread of values is possible. This is not a
1474 * problem for the computation of the nanosecond clock; with TSC rates
1475 * around 1GHZ, there can only be a few cycles which correspond to one
1476 * nanosecond value, and any path through this code will inevitably
1477 * take longer than that. However, with the kernel_ns value itself,
1478 * the precision may be much lower, down to HZ granularity. If the
1479 * first sampling of TSC against kernel_ns ends in the low part of the
1480 * range, and the second in the high end of the range, we can get:
1481 *
1482 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1483 *
1484 * As the sampling errors potentially range in the thousands of cycles,
1485 * it is possible such a time value has already been observed by the
1486 * guest. To protect against this, we must compute the system time as
1487 * observed by the guest and ensure the new system time is greater.
1488 */
1489 max_kernel_ns = 0;
b183aa58 1490 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1491 max_kernel_ns = vcpu->last_guest_tsc -
1492 vcpu->hv_clock.tsc_timestamp;
1493 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1494 vcpu->hv_clock.tsc_to_system_mul,
1495 vcpu->hv_clock.tsc_shift);
1496 max_kernel_ns += vcpu->last_kernel_ns;
1497 }
afbcf7ab 1498
e48672fa 1499 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1500 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1501 &vcpu->hv_clock.tsc_shift,
1502 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1503 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1504 }
1505
d828199e
MT		 1506 /* with a master <monotonic time, tsc value> tuple,
1507 * pvclock clock reads always increase at the (scaled) rate
1508 * of guest TSC - no need to deal with sampling errors.
1509 */
1510 if (!use_master_clock) {
1511 if (max_kernel_ns > kernel_ns)
1512 kernel_ns = max_kernel_ns;
1513 }
8cfdc000 1514 /* With all the info we got, fill in the values */
1d5f066e 1515 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1516 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1517 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1518 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1519
18068523
GOC		 1520 /*
1521 * The interface expects us to write an even number signaling that the
1522 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1523 * state, we just increase by 2 at the end.
18068523 1524 */
50d0a0f9 1525 vcpu->hv_clock.version += 2;
18068523 1526
0b79459b
AH		 1527 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1528 &guest_hv_clock, sizeof(guest_hv_clock))))
1529 return 0;
78c0337a
MT		 1530
1531 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1532 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1533
1534 if (vcpu->pvclock_set_guest_stopped_request) {
1535 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1536 vcpu->pvclock_set_guest_stopped_request = false;
1537 }
1538
d828199e
MT		 1539 /* If the host uses TSC clocksource, then it is stable */
1540 if (use_master_clock)
1541 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1542
78c0337a
MT		 1543 vcpu->hv_clock.flags = pvclock_flags;
1544
0b79459b
AH		 1545 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1546 &vcpu->hv_clock,
1547 sizeof(vcpu->hv_clock));
8cfdc000 1548 return 0;
c8076604
GH		 1549}
1550
9ba075a6
AK		 1551static bool msr_mtrr_valid(unsigned msr)
1552{
1553 switch (msr) {
1554 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1555 case MSR_MTRRfix64K_00000:
1556 case MSR_MTRRfix16K_80000:
1557 case MSR_MTRRfix16K_A0000:
1558 case MSR_MTRRfix4K_C0000:
1559 case MSR_MTRRfix4K_C8000:
1560 case MSR_MTRRfix4K_D0000:
1561 case MSR_MTRRfix4K_D8000:
1562 case MSR_MTRRfix4K_E0000:
1563 case MSR_MTRRfix4K_E8000:
1564 case MSR_MTRRfix4K_F0000:
1565 case MSR_MTRRfix4K_F8000:
1566 case MSR_MTRRdefType:
1567 case MSR_IA32_CR_PAT:
1568 return true;
1569 case 0x2f8:
1570 return true;
1571 }
1572 return false;
1573}
1574
d6289b93
MT		 1575static bool valid_pat_type(unsigned t)
1576{
1577 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1578}
1579
1580static bool valid_mtrr_type(unsigned t)
1581{
1582 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1583}
1584
1585static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1586{
1587 int i;
1588
1589 if (!msr_mtrr_valid(msr))
1590 return false;
1591
1592 if (msr == MSR_IA32_CR_PAT) {
1593 for (i = 0; i < 8; i++)
1594 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1595 return false;
1596 return true;
1597 } else if (msr == MSR_MTRRdefType) {
1598 if (data & ~0xcff)
1599 return false;
1600 return valid_mtrr_type(data & 0xff);
1601 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1602 for (i = 0; i < 8 ; i++)
1603 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1604 return false;
1605 return true;
1606 }
1607
1608 /* variable MTRRs */
1609 return valid_mtrr_type(data & 0xff);
1610}
1611
9ba075a6
AK		 1612static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1613{
0bed3b56
SY		 1614 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1615
d6289b93 1616 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1617 return 1;
1618
0bed3b56
SY		 1619 if (msr == MSR_MTRRdefType) {
1620 vcpu->arch.mtrr_state.def_type = data;
1621 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1622 } else if (msr == MSR_MTRRfix64K_00000)
1623 p[0] = data;
1624 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1625 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1626 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1627 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1628 else if (msr == MSR_IA32_CR_PAT)
1629 vcpu->arch.pat = data;
1630 else { /* Variable MTRRs */
1631 int idx, is_mtrr_mask;
1632 u64 *pt;
1633
1634 idx = (msr - 0x200) / 2;
1635 is_mtrr_mask = msr - 0x200 - 2 * idx;
1636 if (!is_mtrr_mask)
1637 pt =
1638 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1639 else
1640 pt =
1641 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1642 *pt = data;
1643 }
1644
1645 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1646 return 0;
1647}
15c4a640 1648
890ca9ae 1649static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1650{
890ca9ae
HY		 1651 u64 mcg_cap = vcpu->arch.mcg_cap;
1652 unsigned bank_num = mcg_cap & 0xff;
1653
15c4a640 1654 switch (msr) {
15c4a640 1655 case MSR_IA32_MCG_STATUS:
890ca9ae 1656 vcpu->arch.mcg_status = data;
15c4a640 1657 break;
c7ac679c 1658 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1659 if (!(mcg_cap & MCG_CTL_P))
1660 return 1;
1661 if (data != 0 && data != ~(u64)0)
1662 return -1;
1663 vcpu->arch.mcg_ctl = data;
1664 break;
1665 default:
1666 if (msr >= MSR_IA32_MC0_CTL &&
1667 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1668 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1669 /* only 0 or all 1s can be written to IA32_MCi_CTL
1670 * some Linux kernels though clear bit 10 in bank 4 to
1671 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1672 * this to avoid an uncatched #GP in the guest
1673 */
890ca9ae 1674 if ((offset & 0x3) == 0 &&
114be429 1675 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1676 return -1;
1677 vcpu->arch.mce_banks[offset] = data;
1678 break;
1679 }
1680 return 1;
1681 }
1682 return 0;
1683}
1684
ffde22ac
ES		 1685static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1686{
1687 struct kvm *kvm = vcpu->kvm;
1688 int lm = is_long_mode(vcpu);
1689 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1690 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1691 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1692 : kvm->arch.xen_hvm_config.blob_size_32;
1693 u32 page_num = data & ~PAGE_MASK;
1694 u64 page_addr = data & PAGE_MASK;
1695 u8 *page;
1696 int r;
1697
1698 r = -E2BIG;
1699 if (page_num >= blob_size)
1700 goto out;
1701 r = -ENOMEM;
ff5c2c03
SL		 1702 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1703 if (IS_ERR(page)) {
1704 r = PTR_ERR(page);
ffde22ac 1705 goto out;
ff5c2c03 1706 }
ffde22ac
ES		 1707 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1708 goto out_free;
1709 r = 0;
1710out_free:
1711 kfree(page);
1712out:
1713 return r;
1714}
1715
55cd8e5a
GN		 1716static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1717{
1718 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1719}
1720
1721static bool kvm_hv_msr_partition_wide(u32 msr)
1722{
1723 bool r = false;
1724 switch (msr) {
1725 case HV_X64_MSR_GUEST_OS_ID:
1726 case HV_X64_MSR_HYPERCALL:
1727 r = true;
1728 break;
1729 }
1730
1731 return r;
1732}
1733
1734static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1735{
1736 struct kvm *kvm = vcpu->kvm;
1737
1738 switch (msr) {
1739 case HV_X64_MSR_GUEST_OS_ID:
1740 kvm->arch.hv_guest_os_id = data;
1741 /* setting guest os id to zero disables hypercall page */
1742 if (!kvm->arch.hv_guest_os_id)
1743 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1744 break;
1745 case HV_X64_MSR_HYPERCALL: {
1746 u64 gfn;
1747 unsigned long addr;
1748 u8 instructions[4];
1749
1750 /* if guest os id is not set hypercall should remain disabled */
1751 if (!kvm->arch.hv_guest_os_id)
1752 break;
1753 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1754 kvm->arch.hv_hypercall = data;
1755 break;
1756 }
1757 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1758 addr = gfn_to_hva(kvm, gfn);
1759 if (kvm_is_error_hva(addr))
1760 return 1;
1761 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1762 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1763 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1764 return 1;
1765 kvm->arch.hv_hypercall = data;
1766 break;
1767 }
1768 default:
a737f256
CD		 1769 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1770 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1771 return 1;
1772 }
1773 return 0;
1774}
1775
1776static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1777{
10388a07
GN		 1778 switch (msr) {
1779 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1780 unsigned long addr;
55cd8e5a 1781
10388a07
GN		 1782 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1783 vcpu->arch.hv_vapic = data;
1784 break;
1785 }
1786 addr = gfn_to_hva(vcpu->kvm, data >>
1787 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1788 if (kvm_is_error_hva(addr))
1789 return 1;
8b0cedff 1790 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1791 return 1;
1792 vcpu->arch.hv_vapic = data;
1793 break;
1794 }
1795 case HV_X64_MSR_EOI:
1796 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1797 case HV_X64_MSR_ICR:
1798 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1799 case HV_X64_MSR_TPR:
1800 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1801 default:
a737f256
CD		 1802 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1803 "data 0x%llx\n", msr, data);
10388a07
GN		 1804 return 1;
1805 }
1806
1807 return 0;
55cd8e5a
GN		 1808}
1809
344d9588
GN		 1810static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1811{
1812 gpa_t gpa = data & ~0x3f;
1813
4a969980 1814 /* Bits 2:5 are reserved, Should be zero */
6adba527 1815 if (data & 0x3c)
344d9588
GN		 1816 return 1;
1817
1818 vcpu->arch.apf.msr_val = data;
1819
1820 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1821 kvm_clear_async_pf_completion_queue(vcpu);
1822 kvm_async_pf_hash_reset(vcpu);
1823 return 0;
1824 }
1825
1826 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1827 return 1;
1828
6adba527 1829 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1830 kvm_async_pf_wakeup_all(vcpu);
1831 return 0;
1832}
1833
12f9a48f
GC		 1834static void kvmclock_reset(struct kvm_vcpu *vcpu)
1835{
0b79459b 1836 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1837}
1838
c9aaa895
GC		 1839static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1840{
1841 u64 delta;
1842
1843 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1844 return;
1845
1846 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1847 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1848 vcpu->arch.st.accum_steal = delta;
1849}
1850
1851static void record_steal_time(struct kvm_vcpu *vcpu)
1852{
1853 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1854 return;
1855
1856 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1857 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1858 return;
1859
1860 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1861 vcpu->arch.st.steal.version += 2;
1862 vcpu->arch.st.accum_steal = 0;
1863
1864 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1865 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1866}
1867
8fe8ab46 1868int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1869{
5753785f 1870 bool pr = false;
8fe8ab46
WA		 1871 u32 msr = msr_info->index;
1872 u64 data = msr_info->data;
5753785f 1873
15c4a640 1874 switch (msr) {
2e32b719
BP		 1875 case MSR_AMD64_NB_CFG:
1876 case MSR_IA32_UCODE_REV:
1877 case MSR_IA32_UCODE_WRITE:
1878 case MSR_VM_HSAVE_PA:
1879 case MSR_AMD64_PATCH_LOADER:
1880 case MSR_AMD64_BU_CFG2:
1881 break;
1882
15c4a640 1883 case MSR_EFER:
b69e8cae 1884 return set_efer(vcpu, data);
8f1589d9
AP		 1885 case MSR_K7_HWCR:
1886 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1887 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1888 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1889 if (data != 0) {
a737f256
CD		 1890 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1891 data);
8f1589d9
AP		 1892 return 1;
1893 }
15c4a640 1894 break;
f7c6d140
AP		 1895 case MSR_FAM10H_MMIO_CONF_BASE:
1896 if (data != 0) {
a737f256
CD		 1897 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1898 "0x%llx\n", data);
f7c6d140
AP		 1899 return 1;
1900 }
15c4a640 1901 break;
b5e2fec0
AG		 1902 case MSR_IA32_DEBUGCTLMSR:
1903 if (!data) {
1904 /* We support the non-activated case already */
1905 break;
1906 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1907 /* Values other than LBR and BTF are vendor-specific,
1908 thus reserved and should throw a #GP */
1909 return 1;
1910 }
a737f256
CD		 1911 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1912 __func__, data);
b5e2fec0 1913 break;
9ba075a6
AK		 1914 case 0x200 ... 0x2ff:
1915 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1916 case MSR_IA32_APICBASE:
1917 kvm_set_apic_base(vcpu, data);
1918 break;
0105d1a5
GN		 1919 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1920 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1921 case MSR_IA32_TSCDEADLINE:
1922 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1923 break;
ba904635
WA		 1924 case MSR_IA32_TSC_ADJUST:
1925 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1926 if (!msr_info->host_initiated) {
1927 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1928 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1929 }
1930 vcpu->arch.ia32_tsc_adjust_msr = data;
1931 }
1932 break;
15c4a640 1933 case MSR_IA32_MISC_ENABLE:
ad312c7c 1934 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1935 break;
11c6bffa 1936 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1937 case MSR_KVM_WALL_CLOCK:
1938 vcpu->kvm->arch.wall_clock = data;
1939 kvm_write_wall_clock(vcpu->kvm, data);
1940 break;
11c6bffa 1941 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1942 case MSR_KVM_SYSTEM_TIME: {
0b79459b 1943 u64 gpa_offset;
12f9a48f 1944 kvmclock_reset(vcpu);
18068523
GOC		 1945
1946 vcpu->arch.time = data;
c285545f 1947 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1948
1949 /* we verify if the enable bit is set... */
1950 if (!(data & 1))
1951 break;
1952
0b79459b 1953 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 1954
c300aa64 1955 /* Check that the address is 32-byte aligned. */
0b79459b 1956 if (gpa_offset & (sizeof(struct pvclock_vcpu_time_info) - 1))
c300aa64
AH		 1957 break;
1958
0b79459b
AH		 1959 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1960 &vcpu->arch.pv_time, data & ~1ULL))
1961 vcpu->arch.pv_time_enabled = false;
1962 else
1963 vcpu->arch.pv_time_enabled = true;
32cad84f 1964
18068523
GOC		 1965 break;
1966 }
344d9588
GN		 1967 case MSR_KVM_ASYNC_PF_EN:
1968 if (kvm_pv_enable_async_pf(vcpu, data))
1969 return 1;
1970 break;
c9aaa895
GC		 1971 case MSR_KVM_STEAL_TIME:
1972
1973 if (unlikely(!sched_info_on()))
1974 return 1;
1975
1976 if (data & KVM_STEAL_RESERVED_MASK)
1977 return 1;
1978
1979 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1980 data & KVM_STEAL_VALID_BITS))
1981 return 1;
1982
1983 vcpu->arch.st.msr_val = data;
1984
1985 if (!(data & KVM_MSR_ENABLED))
1986 break;
1987
1988 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1989
1990 preempt_disable();
1991 accumulate_steal_time(vcpu);
1992 preempt_enable();
1993
1994 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1995
1996 break;
ae7a2a3f
MT		 1997 case MSR_KVM_PV_EOI_EN:
1998 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1999 return 1;
2000 break;
c9aaa895 2001
890ca9ae
HY		 2002 case MSR_IA32_MCG_CTL:
2003 case MSR_IA32_MCG_STATUS:
2004 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2005 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2006
2007 /* Performance counters are not protected by a CPUID bit,
2008 * so we should check all of them in the generic path for the sake of
2009 * cross vendor migration.
2010 * Writing a zero into the event select MSRs disables them,
2011 * which we perfectly emulate ;-). Any other value should be at least
2012 * reported, some guests depend on them.
2013 */
71db6023
AP		 2014 case MSR_K7_EVNTSEL0:
2015 case MSR_K7_EVNTSEL1:
2016 case MSR_K7_EVNTSEL2:
2017 case MSR_K7_EVNTSEL3:
2018 if (data != 0)
a737f256
CD		 2019 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2020 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2021 break;
2022 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2023 * so we ignore writes to make it happy.
2024 */
71db6023
AP		 2025 case MSR_K7_PERFCTR0:
2026 case MSR_K7_PERFCTR1:
2027 case MSR_K7_PERFCTR2:
2028 case MSR_K7_PERFCTR3:
a737f256
CD		 2029 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2030 "0x%x data 0x%llx\n", msr, data);
71db6023 2031 break;
5753785f
GN		 2032 case MSR_P6_PERFCTR0:
2033 case MSR_P6_PERFCTR1:
2034 pr = true;
2035 case MSR_P6_EVNTSEL0:
2036 case MSR_P6_EVNTSEL1:
2037 if (kvm_pmu_msr(vcpu, msr))
2038 return kvm_pmu_set_msr(vcpu, msr, data);
2039
2040 if (pr || data != 0)
a737f256
CD		 2041 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2042 "0x%x data 0x%llx\n", msr, data);
5753785f 2043 break;
84e0cefa
JS		 2044 case MSR_K7_CLK_CTL:
2045 /*
2046 * Ignore all writes to this no longer documented MSR.
2047 * Writes are only relevant for old K7 processors,
2048 * all pre-dating SVM, but a recommended workaround from
4a969980 2049 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2050 * affected processor models on the command line, hence
2051 * the need to ignore the workaround.
2052 */
2053 break;
55cd8e5a
GN		 2054 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2055 if (kvm_hv_msr_partition_wide(msr)) {
2056 int r;
2057 mutex_lock(&vcpu->kvm->lock);
2058 r = set_msr_hyperv_pw(vcpu, msr, data);
2059 mutex_unlock(&vcpu->kvm->lock);
2060 return r;
2061 } else
2062 return set_msr_hyperv(vcpu, msr, data);
2063 break;
91c9c3ed 2064 case MSR_IA32_BBL_CR_CTL3:
2065 /* Drop writes to this legacy MSR -- see rdmsr
2066 * counterpart for further detail.
2067 */
a737f256 2068 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2069 break;
2b036c6b
BO		 2070 case MSR_AMD64_OSVW_ID_LENGTH:
2071 if (!guest_cpuid_has_osvw(vcpu))
2072 return 1;
2073 vcpu->arch.osvw.length = data;
2074 break;
2075 case MSR_AMD64_OSVW_STATUS:
2076 if (!guest_cpuid_has_osvw(vcpu))
2077 return 1;
2078 vcpu->arch.osvw.status = data;
2079 break;
15c4a640 2080 default:
ffde22ac
ES		 2081 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2082 return xen_hvm_config(vcpu, data);
f5132b01
GN		 2083 if (kvm_pmu_msr(vcpu, msr))
2084 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068 2085 if (!ignore_msrs) {
a737f256
CD		 2086 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2087 msr, data);
ed85c068
AP		 2088 return 1;
2089 } else {
a737f256
CD		 2090 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2091 msr, data);
ed85c068
AP		 2092 break;
2093 }
15c4a640
CO		 2094 }
2095 return 0;
2096}
2097EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2098
2099
2100/*
2101 * Reads an msr value (of 'msr_index') into 'pdata'.
2102 * Returns 0 on success, non-0 otherwise.
2103 * Assumes vcpu_load() was already called.
2104 */
2105int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2106{
2107 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2108}
2109
9ba075a6
AK		 2110static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2111{
0bed3b56
SY		 2112 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2113
9ba075a6
AK		 2114 if (!msr_mtrr_valid(msr))
2115 return 1;
2116
0bed3b56
SY		 2117 if (msr == MSR_MTRRdefType)
2118 *pdata = vcpu->arch.mtrr_state.def_type +
2119 (vcpu->arch.mtrr_state.enabled << 10);
2120 else if (msr == MSR_MTRRfix64K_00000)
2121 *pdata = p[0];
2122 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2123 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2124 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2125 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2126 else if (msr == MSR_IA32_CR_PAT)
2127 *pdata = vcpu->arch.pat;
2128 else { /* Variable MTRRs */
2129 int idx, is_mtrr_mask;
2130 u64 *pt;
2131
2132 idx = (msr - 0x200) / 2;
2133 is_mtrr_mask = msr - 0x200 - 2 * idx;
2134 if (!is_mtrr_mask)
2135 pt =
2136 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2137 else
2138 pt =
2139 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2140 *pdata = *pt;
2141 }
2142
9ba075a6
AK		 2143 return 0;
2144}
2145
890ca9ae 2146static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2147{
2148 u64 data;
890ca9ae
HY		 2149 u64 mcg_cap = vcpu->arch.mcg_cap;
2150 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2151
2152 switch (msr) {
15c4a640
CO		 2153 case MSR_IA32_P5_MC_ADDR:
2154 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2155 data = 0;
2156 break;
15c4a640 2157 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2158 data = vcpu->arch.mcg_cap;
2159 break;
c7ac679c 2160 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2161 if (!(mcg_cap & MCG_CTL_P))
2162 return 1;
2163 data = vcpu->arch.mcg_ctl;
2164 break;
2165 case MSR_IA32_MCG_STATUS:
2166 data = vcpu->arch.mcg_status;
2167 break;
2168 default:
2169 if (msr >= MSR_IA32_MC0_CTL &&
2170 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2171 u32 offset = msr - MSR_IA32_MC0_CTL;
2172 data = vcpu->arch.mce_banks[offset];
2173 break;
2174 }
2175 return 1;
2176 }
2177 *pdata = data;
2178 return 0;
2179}
2180
55cd8e5a
GN		 2181static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2182{
2183 u64 data = 0;
2184 struct kvm *kvm = vcpu->kvm;
2185
2186 switch (msr) {
2187 case HV_X64_MSR_GUEST_OS_ID:
2188 data = kvm->arch.hv_guest_os_id;
2189 break;
2190 case HV_X64_MSR_HYPERCALL:
2191 data = kvm->arch.hv_hypercall;
2192 break;
2193 default:
a737f256 2194 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2195 return 1;
2196 }
2197
2198 *pdata = data;
2199 return 0;
2200}
2201
2202static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2203{
2204 u64 data = 0;
2205
2206 switch (msr) {
2207 case HV_X64_MSR_VP_INDEX: {
2208 int r;
2209 struct kvm_vcpu *v;
2210 kvm_for_each_vcpu(r, v, vcpu->kvm)
2211 if (v == vcpu)
2212 data = r;
2213 break;
2214 }
10388a07
GN		 2215 case HV_X64_MSR_EOI:
2216 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2217 case HV_X64_MSR_ICR:
2218 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2219 case HV_X64_MSR_TPR:
2220 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2221 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2222 data = vcpu->arch.hv_vapic;
2223 break;
55cd8e5a 2224 default:
a737f256 2225 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2226 return 1;
2227 }
2228 *pdata = data;
2229 return 0;
2230}
2231
890ca9ae
HY		 2232int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2233{
2234 u64 data;
2235
2236 switch (msr) {
890ca9ae 2237 case MSR_IA32_PLATFORM_ID:
15c4a640 2238 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2239 case MSR_IA32_DEBUGCTLMSR:
2240 case MSR_IA32_LASTBRANCHFROMIP:
2241 case MSR_IA32_LASTBRANCHTOIP:
2242 case MSR_IA32_LASTINTFROMIP:
2243 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2244 case MSR_K8_SYSCFG:
2245 case MSR_K7_HWCR:
61a6bd67 2246 case MSR_VM_HSAVE_PA:
9e699624 2247 case MSR_K7_EVNTSEL0:
1f3ee616 2248 case MSR_K7_PERFCTR0:
1fdbd48c 2249 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2250 case MSR_AMD64_NB_CFG:
f7c6d140 2251 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2252 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2253 data = 0;
2254 break;
5753785f
GN		 2255 case MSR_P6_PERFCTR0:
2256 case MSR_P6_PERFCTR1:
2257 case MSR_P6_EVNTSEL0:
2258 case MSR_P6_EVNTSEL1:
2259 if (kvm_pmu_msr(vcpu, msr))
2260 return kvm_pmu_get_msr(vcpu, msr, pdata);
2261 data = 0;
2262 break;
742bc670
MT		 2263 case MSR_IA32_UCODE_REV:
2264 data = 0x100000000ULL;
2265 break;
9ba075a6
AK		 2266 case MSR_MTRRcap:
2267 data = 0x500 | KVM_NR_VAR_MTRR;
2268 break;
2269 case 0x200 ... 0x2ff:
2270 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2271 case 0xcd: /* fsb frequency */
2272 data = 3;
2273 break;
7b914098
JS		 2274 /*
2275 * MSR_EBC_FREQUENCY_ID
2276 * Conservative value valid for even the basic CPU models.
2277 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2278 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2279 * and 266MHz for model 3, or 4. Set Core Clock
2280 * Frequency to System Bus Frequency Ratio to 1 (bits
2281 * 31:24) even though these are only valid for CPU
2282 * models > 2, however guests may end up dividing or
2283 * multiplying by zero otherwise.
2284 */
2285 case MSR_EBC_FREQUENCY_ID:
2286 data = 1 << 24;
2287 break;
15c4a640
CO		 2288 case MSR_IA32_APICBASE:
2289 data = kvm_get_apic_base(vcpu);
2290 break;
0105d1a5
GN		 2291 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2292 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2293 break;
a3e06bbe
LJ		 2294 case MSR_IA32_TSCDEADLINE:
2295 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2296 break;
ba904635
WA		 2297 case MSR_IA32_TSC_ADJUST:
2298 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2299 break;
15c4a640 2300 case MSR_IA32_MISC_ENABLE:
ad312c7c 2301 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2302 break;
847f0ad8
AG		 2303 case MSR_IA32_PERF_STATUS:
2304 /* TSC increment by tick */
2305 data = 1000ULL;
2306 /* CPU multiplier */
2307 data |= (((uint64_t)4ULL) << 40);
2308 break;
15c4a640 2309 case MSR_EFER:
f6801dff 2310 data = vcpu->arch.efer;
15c4a640 2311 break;
18068523 2312 case MSR_KVM_WALL_CLOCK:
11c6bffa 2313 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2314 data = vcpu->kvm->arch.wall_clock;
2315 break;
2316 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2317 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2318 data = vcpu->arch.time;
2319 break;
344d9588
GN		 2320 case MSR_KVM_ASYNC_PF_EN:
2321 data = vcpu->arch.apf.msr_val;
2322 break;
c9aaa895
GC		 2323 case MSR_KVM_STEAL_TIME:
2324 data = vcpu->arch.st.msr_val;
2325 break;
1d92128f
MT		 2326 case MSR_KVM_PV_EOI_EN:
2327 data = vcpu->arch.pv_eoi.msr_val;
2328 break;
890ca9ae
HY		 2329 case MSR_IA32_P5_MC_ADDR:
2330 case MSR_IA32_P5_MC_TYPE:
2331 case MSR_IA32_MCG_CAP:
2332 case MSR_IA32_MCG_CTL:
2333 case MSR_IA32_MCG_STATUS:
2334 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2335 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2336 case MSR_K7_CLK_CTL:
2337 /*
2338 * Provide expected ramp-up count for K7. All other
2339 * are set to zero, indicating minimum divisors for
2340 * every field.
2341 *
2342 * This prevents guest kernels on AMD host with CPU
2343 * type 6, model 8 and higher from exploding due to
2344 * the rdmsr failing.
2345 */
2346 data = 0x20000000;
2347 break;
55cd8e5a
GN		 2348 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2349 if (kvm_hv_msr_partition_wide(msr)) {
2350 int r;
2351 mutex_lock(&vcpu->kvm->lock);
2352 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2353 mutex_unlock(&vcpu->kvm->lock);
2354 return r;
2355 } else
2356 return get_msr_hyperv(vcpu, msr, pdata);
2357 break;
91c9c3ed 2358 case MSR_IA32_BBL_CR_CTL3:
2359 /* This legacy MSR exists but isn't fully documented in current
2360 * silicon. It is however accessed by winxp in very narrow
2361 * scenarios where it sets bit #19, itself documented as
2362 * a "reserved" bit. Best effort attempt to source coherent
2363 * read data here should the balance of the register be
2364 * interpreted by the guest:
2365 *
2366 * L2 cache control register 3: 64GB range, 256KB size,
2367 * enabled, latency 0x1, configured
2368 */
2369 data = 0xbe702111;
2370 break;
2b036c6b
BO		 2371 case MSR_AMD64_OSVW_ID_LENGTH:
2372 if (!guest_cpuid_has_osvw(vcpu))
2373 return 1;
2374 data = vcpu->arch.osvw.length;
2375 break;
2376 case MSR_AMD64_OSVW_STATUS:
2377 if (!guest_cpuid_has_osvw(vcpu))
2378 return 1;
2379 data = vcpu->arch.osvw.status;
2380 break;
15c4a640 2381 default:
f5132b01
GN		 2382 if (kvm_pmu_msr(vcpu, msr))
2383 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2384 if (!ignore_msrs) {
a737f256 2385 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2386 return 1;
2387 } else {
a737f256 2388 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2389 data = 0;
2390 }
2391 break;
15c4a640
CO		 2392 }
2393 *pdata = data;
2394 return 0;
2395}
2396EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2397
313a3dc7
CO		 2398/*
2399 * Read or write a bunch of msrs. All parameters are kernel addresses.
2400 *
2401 * @return number of msrs set successfully.
2402 */
2403static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2404 struct kvm_msr_entry *entries,
2405 int (*do_msr)(struct kvm_vcpu *vcpu,
2406 unsigned index, u64 *data))
2407{
f656ce01 2408 int i, idx;
313a3dc7 2409
f656ce01 2410 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2411 for (i = 0; i < msrs->nmsrs; ++i)
2412 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2413 break;
f656ce01 2414 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2415
313a3dc7
CO		 2416 return i;
2417}
2418
2419/*
2420 * Read or write a bunch of msrs. Parameters are user addresses.
2421 *
2422 * @return number of msrs set successfully.
2423 */
2424static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2425 int (*do_msr)(struct kvm_vcpu *vcpu,
2426 unsigned index, u64 *data),
2427 int writeback)
2428{
2429 struct kvm_msrs msrs;
2430 struct kvm_msr_entry *entries;
2431 int r, n;
2432 unsigned size;
2433
2434 r = -EFAULT;
2435 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2436 goto out;
2437
2438 r = -E2BIG;
2439 if (msrs.nmsrs >= MAX_IO_MSRS)
2440 goto out;
2441
313a3dc7 2442 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2443 entries = memdup_user(user_msrs->entries, size);
2444 if (IS_ERR(entries)) {
2445 r = PTR_ERR(entries);
313a3dc7 2446 goto out;
ff5c2c03 2447 }
313a3dc7
CO		 2448
2449 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2450 if (r < 0)
2451 goto out_free;
2452
2453 r = -EFAULT;
2454 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2455 goto out_free;
2456
2457 r = n;
2458
2459out_free:
7a73c028 2460 kfree(entries);
313a3dc7
CO		 2461out:
2462 return r;
2463}
2464
018d00d2
ZX		 2465int kvm_dev_ioctl_check_extension(long ext)
2466{
2467 int r;
2468
2469 switch (ext) {
2470 case KVM_CAP_IRQCHIP:
2471 case KVM_CAP_HLT:
2472 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2473 case KVM_CAP_SET_TSS_ADDR:
07716717 2474 case KVM_CAP_EXT_CPUID:
c8076604 2475 case KVM_CAP_CLOCKSOURCE:
7837699f 2476 case KVM_CAP_PIT:
a28e4f5a 2477 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2478 case KVM_CAP_MP_STATE:
ed848624 2479 case KVM_CAP_SYNC_MMU:
a355c85c 2480 case KVM_CAP_USER_NMI:
52d939a0 2481 case KVM_CAP_REINJECT_CONTROL:
4925663a 2482 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2483 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2484 case KVM_CAP_IRQFD:
d34e6b17 2485 case KVM_CAP_IOEVENTFD:
c5ff41ce 2486 case KVM_CAP_PIT2:
e9f42757 2487 case KVM_CAP_PIT_STATE2:
b927a3ce 2488 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2489 case KVM_CAP_XEN_HVM:
afbcf7ab 2490 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2491 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2492 case KVM_CAP_HYPERV:
10388a07 2493 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2494 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2495 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2496 case KVM_CAP_DEBUGREGS:
d2be1651 2497 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2498 case KVM_CAP_XSAVE:
344d9588 2499 case KVM_CAP_ASYNC_PF:
92a1f12d 2500 case KVM_CAP_GET_TSC_KHZ:
07700a94 2501 case KVM_CAP_PCI_2_3:
1c0b28c2 2502 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2503 case KVM_CAP_READONLY_MEM:
7a84428a 2504 case KVM_CAP_IRQFD_RESAMPLE:
018d00d2
ZX		 2505 r = 1;
2506 break;
542472b5
LV		 2507 case KVM_CAP_COALESCED_MMIO:
2508 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2509 break;
774ead3a
AK		 2510 case KVM_CAP_VAPIC:
2511 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2512 break;
f725230a 2513 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2514 r = KVM_SOFT_MAX_VCPUS;
2515 break;
2516 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2517 r = KVM_MAX_VCPUS;
2518 break;
a988b910 2519 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2520 r = KVM_USER_MEM_SLOTS;
a988b910 2521 break;
a68a6a72
MT		 2522 case KVM_CAP_PV_MMU: /* obsolete */
2523 r = 0;
2f333bcb 2524 break;
62c476c7 2525 case KVM_CAP_IOMMU:
a1b60c1c 2526 r = iommu_present(&pci_bus_type);
62c476c7 2527 break;
890ca9ae
HY		 2528 case KVM_CAP_MCE:
2529 r = KVM_MAX_MCE_BANKS;
2530 break;
2d5b5a66
SY		 2531 case KVM_CAP_XCRS:
2532 r = cpu_has_xsave;
2533 break;
92a1f12d
JR		 2534 case KVM_CAP_TSC_CONTROL:
2535 r = kvm_has_tsc_control;
2536 break;
4d25a066
JK		 2537 case KVM_CAP_TSC_DEADLINE_TIMER:
2538 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2539 break;
018d00d2
ZX		 2540 default:
2541 r = 0;
2542 break;
2543 }
2544 return r;
2545
2546}
2547
043405e1
CO		 2548long kvm_arch_dev_ioctl(struct file *filp,
2549 unsigned int ioctl, unsigned long arg)
2550{
2551 void __user *argp = (void __user *)arg;
2552 long r;
2553
2554 switch (ioctl) {
2555 case KVM_GET_MSR_INDEX_LIST: {
2556 struct kvm_msr_list __user *user_msr_list = argp;
2557 struct kvm_msr_list msr_list;
2558 unsigned n;
2559
2560 r = -EFAULT;
2561 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2562 goto out;
2563 n = msr_list.nmsrs;
2564 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2565 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2566 goto out;
2567 r = -E2BIG;
e125e7b6 2568 if (n < msr_list.nmsrs)
043405e1
CO		 2569 goto out;
2570 r = -EFAULT;
2571 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2572 num_msrs_to_save * sizeof(u32)))
2573 goto out;
e125e7b6 2574 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2575 &emulated_msrs,
2576 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2577 goto out;
2578 r = 0;
2579 break;
2580 }
674eea0f
AK		 2581 case KVM_GET_SUPPORTED_CPUID: {
2582 struct kvm_cpuid2 __user *cpuid_arg = argp;
2583 struct kvm_cpuid2 cpuid;
2584
2585 r = -EFAULT;
2586 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2587 goto out;
2588 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2589 cpuid_arg->entries);
674eea0f
AK		 2590 if (r)
2591 goto out;
2592
2593 r = -EFAULT;
2594 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2595 goto out;
2596 r = 0;
2597 break;
2598 }
890ca9ae
HY		 2599 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2600 u64 mce_cap;
2601
2602 mce_cap = KVM_MCE_CAP_SUPPORTED;
2603 r = -EFAULT;
2604 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2605 goto out;
2606 r = 0;
2607 break;
2608 }
043405e1
CO		 2609 default:
2610 r = -EINVAL;
2611 }
2612out:
2613 return r;
2614}
2615
f5f48ee1
SY		 2616static void wbinvd_ipi(void *garbage)
2617{
2618 wbinvd();
2619}
2620
2621static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2622{
2623 return vcpu->kvm->arch.iommu_domain &&
2624 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2625}
2626
313a3dc7
CO		 2627void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2628{
f5f48ee1
SY		 2629 /* Address WBINVD may be executed by guest */
2630 if (need_emulate_wbinvd(vcpu)) {
2631 if (kvm_x86_ops->has_wbinvd_exit())
2632 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2633 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2634 smp_call_function_single(vcpu->cpu,
2635 wbinvd_ipi, NULL, 1);
2636 }
2637
313a3dc7 2638 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2639
0dd6a6ed
ZA		 2640 /* Apply any externally detected TSC adjustments (due to suspend) */
2641 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2642 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2643 vcpu->arch.tsc_offset_adjustment = 0;
2644 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2645 }
8f6055cb 2646
48434c20 2647 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2648 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2649 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2650 if (tsc_delta < 0)
2651 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2652 if (check_tsc_unstable()) {
b183aa58
ZA		 2653 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2654 vcpu->arch.last_guest_tsc);
2655 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2656 vcpu->arch.tsc_catchup = 1;
c285545f 2657 }
d98d07ca
MT		 2658 /*
2659 * On a host with synchronized TSC, there is no need to update
2660 * kvmclock on vcpu->cpu migration
2661 */
2662 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2663 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2664 if (vcpu->cpu != cpu)
2665 kvm_migrate_timers(vcpu);
e48672fa 2666 vcpu->cpu = cpu;
6b7d7e76 2667 }
c9aaa895
GC		 2668
2669 accumulate_steal_time(vcpu);
2670 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2671}
2672
2673void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2674{
02daab21 2675 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2676 kvm_put_guest_fpu(vcpu);
6f526ec5 2677 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2678}
2679
313a3dc7
CO		 2680static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2681 struct kvm_lapic_state *s)
2682{
ad312c7c 2683 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2684
2685 return 0;
2686}
2687
2688static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2689 struct kvm_lapic_state *s)
2690{
64eb0620 2691 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2692 update_cr8_intercept(vcpu);
313a3dc7
CO		 2693
2694 return 0;
2695}
2696
f77bc6a4
ZX		 2697static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2698 struct kvm_interrupt *irq)
2699{
a50abc3b 2700 if (irq->irq < 0 || irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2701 return -EINVAL;
2702 if (irqchip_in_kernel(vcpu->kvm))
2703 return -ENXIO;
f77bc6a4 2704
66fd3f7f 2705 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2706 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2707
f77bc6a4
ZX		 2708 return 0;
2709}
2710
c4abb7c9
JK		 2711static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2712{
c4abb7c9 2713 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2714
2715 return 0;
2716}
2717
b209749f
AK		 2718static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2719 struct kvm_tpr_access_ctl *tac)
2720{
2721 if (tac->flags)
2722 return -EINVAL;
2723 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2724 return 0;
2725}
2726
890ca9ae
HY		 2727static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2728 u64 mcg_cap)
2729{
2730 int r;
2731 unsigned bank_num = mcg_cap & 0xff, bank;
2732
2733 r = -EINVAL;
a9e38c3e 2734 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2735 goto out;
2736 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2737 goto out;
2738 r = 0;
2739 vcpu->arch.mcg_cap = mcg_cap;
2740 /* Init IA32_MCG_CTL to all 1s */
2741 if (mcg_cap & MCG_CTL_P)
2742 vcpu->arch.mcg_ctl = ~(u64)0;
2743 /* Init IA32_MCi_CTL to all 1s */
2744 for (bank = 0; bank < bank_num; bank++)
2745 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2746out:
2747 return r;
2748}
2749
2750static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2751 struct kvm_x86_mce *mce)
2752{
2753 u64 mcg_cap = vcpu->arch.mcg_cap;
2754 unsigned bank_num = mcg_cap & 0xff;
2755 u64 *banks = vcpu->arch.mce_banks;
2756
2757 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2758 return -EINVAL;
2759 /*
2760 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2761 * reporting is disabled
2762 */
2763 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2764 vcpu->arch.mcg_ctl != ~(u64)0)
2765 return 0;
2766 banks += 4 * mce->bank;
2767 /*
2768 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2769 * reporting is disabled for the bank
2770 */
2771 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2772 return 0;
2773 if (mce->status & MCI_STATUS_UC) {
2774 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2775 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2776 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2777 return 0;
2778 }
2779 if (banks[1] & MCI_STATUS_VAL)
2780 mce->status |= MCI_STATUS_OVER;
2781 banks[2] = mce->addr;
2782 banks[3] = mce->misc;
2783 vcpu->arch.mcg_status = mce->mcg_status;
2784 banks[1] = mce->status;
2785 kvm_queue_exception(vcpu, MC_VECTOR);
2786 } else if (!(banks[1] & MCI_STATUS_VAL)
2787 || !(banks[1] & MCI_STATUS_UC)) {
2788 if (banks[1] & MCI_STATUS_VAL)
2789 mce->status |= MCI_STATUS_OVER;
2790 banks[2] = mce->addr;
2791 banks[3] = mce->misc;
2792 banks[1] = mce->status;
2793 } else
2794 banks[1] |= MCI_STATUS_OVER;
2795 return 0;
2796}
2797
3cfc3092
JK		 2798static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2799 struct kvm_vcpu_events *events)
2800{
7460fb4a 2801 process_nmi(vcpu);
03b82a30
JK		 2802 events->exception.injected =
2803 vcpu->arch.exception.pending &&
2804 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2805 events->exception.nr = vcpu->arch.exception.nr;
2806 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2807 events->exception.pad = 0;
3cfc3092
JK		 2808 events->exception.error_code = vcpu->arch.exception.error_code;
2809
03b82a30
JK		 2810 events->interrupt.injected =
2811 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2812 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2813 events->interrupt.soft = 0;
48005f64
JK		 2814 events->interrupt.shadow =
2815 kvm_x86_ops->get_interrupt_shadow(vcpu,
2816 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2817
2818 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2819 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2820 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2821 events->nmi.pad = 0;
3cfc3092
JK		 2822
2823 events->sipi_vector = vcpu->arch.sipi_vector;
2824
dab4b911 2825 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2826 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2827 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2828 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2829}
2830
2831static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2832 struct kvm_vcpu_events *events)
2833{
dab4b911 2834 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2835 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2836 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2837 return -EINVAL;
2838
7460fb4a 2839 process_nmi(vcpu);
3cfc3092
JK		 2840 vcpu->arch.exception.pending = events->exception.injected;
2841 vcpu->arch.exception.nr = events->exception.nr;
2842 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2843 vcpu->arch.exception.error_code = events->exception.error_code;
2844
2845 vcpu->arch.interrupt.pending = events->interrupt.injected;
2846 vcpu->arch.interrupt.nr = events->interrupt.nr;
2847 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2848 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2849 kvm_x86_ops->set_interrupt_shadow(vcpu,
2850 events->interrupt.shadow);
3cfc3092
JK		 2851
2852 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2853 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2854 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2855 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2856
dab4b911
JK		 2857 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2858 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2859
3842d135
AK		 2860 kvm_make_request(KVM_REQ_EVENT, vcpu);
2861
3cfc3092
JK		 2862 return 0;
2863}
2864
a1efbe77
JK		 2865static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2866 struct kvm_debugregs *dbgregs)
2867{
a1efbe77
JK		 2868 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2869 dbgregs->dr6 = vcpu->arch.dr6;
2870 dbgregs->dr7 = vcpu->arch.dr7;
2871 dbgregs->flags = 0;
97e69aa6 2872 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2873}
2874
2875static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2876 struct kvm_debugregs *dbgregs)
2877{
2878 if (dbgregs->flags)
2879 return -EINVAL;
2880
a1efbe77
JK		 2881 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2882 vcpu->arch.dr6 = dbgregs->dr6;
2883 vcpu->arch.dr7 = dbgregs->dr7;
2884
a1efbe77
JK		 2885 return 0;
2886}
2887
2d5b5a66
SY		 2888static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2889 struct kvm_xsave *guest_xsave)
2890{
2891 if (cpu_has_xsave)
2892 memcpy(guest_xsave->region,
2893 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2894 xstate_size);
2d5b5a66
SY		 2895 else {
2896 memcpy(guest_xsave->region,
2897 &vcpu->arch.guest_fpu.state->fxsave,
2898 sizeof(struct i387_fxsave_struct));
2899 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2900 XSTATE_FPSSE;
2901 }
2902}
2903
2904static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2905 struct kvm_xsave *guest_xsave)
2906{
2907 u64 xstate_bv =
2908 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2909
2910 if (cpu_has_xsave)
2911 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2912 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2913 else {
2914 if (xstate_bv & ~XSTATE_FPSSE)
2915 return -EINVAL;
2916 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2917 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2918 }
2919 return 0;
2920}
2921
2922static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2923 struct kvm_xcrs *guest_xcrs)
2924{
2925 if (!cpu_has_xsave) {
2926 guest_xcrs->nr_xcrs = 0;
2927 return;
2928 }
2929
2930 guest_xcrs->nr_xcrs = 1;
2931 guest_xcrs->flags = 0;
2932 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2933 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2934}
2935
2936static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2937 struct kvm_xcrs *guest_xcrs)
2938{
2939 int i, r = 0;
2940
2941 if (!cpu_has_xsave)
2942 return -EINVAL;
2943
2944 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2945 return -EINVAL;
2946
2947 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2948 /* Only support XCR0 currently */
2949 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2950 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2951 guest_xcrs->xcrs[0].value);
2952 break;
2953 }
2954 if (r)
2955 r = -EINVAL;
2956 return r;
2957}
2958
1c0b28c2
EM		 2959/*
2960 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2961 * stopped by the hypervisor. This function will be called from the host only.
2962 * EINVAL is returned when the host attempts to set the flag for a guest that
2963 * does not support pv clocks.
2964 */
2965static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2966{
0b79459b 2967 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 2968 return -EINVAL;
51d59c6b 2969 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 2970 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2971 return 0;
2972}
2973
313a3dc7
CO		 2974long kvm_arch_vcpu_ioctl(struct file *filp,
2975 unsigned int ioctl, unsigned long arg)
2976{
2977 struct kvm_vcpu *vcpu = filp->private_data;
2978 void __user *argp = (void __user *)arg;
2979 int r;
d1ac91d8
AK		 2980 union {
2981 struct kvm_lapic_state *lapic;
2982 struct kvm_xsave *xsave;
2983 struct kvm_xcrs *xcrs;
2984 void *buffer;
2985 } u;
2986
2987 u.buffer = NULL;
313a3dc7
CO		 2988 switch (ioctl) {
2989 case KVM_GET_LAPIC: {
2204ae3c
MT		 2990 r = -EINVAL;
2991 if (!vcpu->arch.apic)
2992 goto out;
d1ac91d8 2993 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2994
b772ff36 2995 r = -ENOMEM;
d1ac91d8 2996 if (!u.lapic)
b772ff36 2997 goto out;
d1ac91d8 2998 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2999 if (r)
3000 goto out;
3001 r = -EFAULT;
d1ac91d8 3002 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3003 goto out;
3004 r = 0;
3005 break;
3006 }
3007 case KVM_SET_LAPIC: {
2204ae3c
MT		 3008 r = -EINVAL;
3009 if (!vcpu->arch.apic)
3010 goto out;
ff5c2c03 3011 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3012 if (IS_ERR(u.lapic))
3013 return PTR_ERR(u.lapic);
ff5c2c03 3014
d1ac91d8 3015 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3016 break;
3017 }
f77bc6a4
ZX		 3018 case KVM_INTERRUPT: {
3019 struct kvm_interrupt irq;
3020
3021 r = -EFAULT;
3022 if (copy_from_user(&irq, argp, sizeof irq))
3023 goto out;
3024 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3025 break;
3026 }
c4abb7c9
JK		 3027 case KVM_NMI: {
3028 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3029 break;
3030 }
313a3dc7
CO		 3031 case KVM_SET_CPUID: {
3032 struct kvm_cpuid __user *cpuid_arg = argp;
3033 struct kvm_cpuid cpuid;
3034
3035 r = -EFAULT;
3036 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3037 goto out;
3038 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3039 break;
3040 }
07716717
DK		 3041 case KVM_SET_CPUID2: {
3042 struct kvm_cpuid2 __user *cpuid_arg = argp;
3043 struct kvm_cpuid2 cpuid;
3044
3045 r = -EFAULT;
3046 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3047 goto out;
3048 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3049 cpuid_arg->entries);
07716717
DK		 3050 break;
3051 }
3052 case KVM_GET_CPUID2: {
3053 struct kvm_cpuid2 __user *cpuid_arg = argp;
3054 struct kvm_cpuid2 cpuid;
3055
3056 r = -EFAULT;
3057 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3058 goto out;
3059 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3060 cpuid_arg->entries);
07716717
DK		 3061 if (r)
3062 goto out;
3063 r = -EFAULT;
3064 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3065 goto out;
3066 r = 0;
3067 break;
3068 }
313a3dc7
CO		 3069 case KVM_GET_MSRS:
3070 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3071 break;
3072 case KVM_SET_MSRS:
3073 r = msr_io(vcpu, argp, do_set_msr, 0);
3074 break;
b209749f
AK		 3075 case KVM_TPR_ACCESS_REPORTING: {
3076 struct kvm_tpr_access_ctl tac;
3077
3078 r = -EFAULT;
3079 if (copy_from_user(&tac, argp, sizeof tac))
3080 goto out;
3081 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3082 if (r)
3083 goto out;
3084 r = -EFAULT;
3085 if (copy_to_user(argp, &tac, sizeof tac))
3086 goto out;
3087 r = 0;
3088 break;
3089 };
b93463aa
AK		 3090 case KVM_SET_VAPIC_ADDR: {
3091 struct kvm_vapic_addr va;
3092
3093 r = -EINVAL;
3094 if (!irqchip_in_kernel(vcpu->kvm))
3095 goto out;
3096 r = -EFAULT;
3097 if (copy_from_user(&va, argp, sizeof va))
3098 goto out;
3099 r = 0;
3100 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3101 break;
3102 }
890ca9ae
HY		 3103 case KVM_X86_SETUP_MCE: {
3104 u64 mcg_cap;
3105
3106 r = -EFAULT;
3107 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3108 goto out;
3109 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3110 break;
3111 }
3112 case KVM_X86_SET_MCE: {
3113 struct kvm_x86_mce mce;
3114
3115 r = -EFAULT;
3116 if (copy_from_user(&mce, argp, sizeof mce))
3117 goto out;
3118 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3119 break;
3120 }
3cfc3092
JK		 3121 case KVM_GET_VCPU_EVENTS: {
3122 struct kvm_vcpu_events events;
3123
3124 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3125
3126 r = -EFAULT;
3127 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3128 break;
3129 r = 0;
3130 break;
3131 }
3132 case KVM_SET_VCPU_EVENTS: {
3133 struct kvm_vcpu_events events;
3134
3135 r = -EFAULT;
3136 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3137 break;
3138
3139 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3140 break;
3141 }
a1efbe77
JK		 3142 case KVM_GET_DEBUGREGS: {
3143 struct kvm_debugregs dbgregs;
3144
3145 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3146
3147 r = -EFAULT;
3148 if (copy_to_user(argp, &dbgregs,
3149 sizeof(struct kvm_debugregs)))
3150 break;
3151 r = 0;
3152 break;
3153 }
3154 case KVM_SET_DEBUGREGS: {
3155 struct kvm_debugregs dbgregs;
3156
3157 r = -EFAULT;
3158 if (copy_from_user(&dbgregs, argp,
3159 sizeof(struct kvm_debugregs)))
3160 break;
3161
3162 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3163 break;
3164 }
2d5b5a66 3165 case KVM_GET_XSAVE: {
d1ac91d8 3166 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3167 r = -ENOMEM;
d1ac91d8 3168 if (!u.xsave)
2d5b5a66
SY		 3169 break;
3170
d1ac91d8 3171 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3172
3173 r = -EFAULT;
d1ac91d8 3174 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3175 break;
3176 r = 0;
3177 break;
3178 }
3179 case KVM_SET_XSAVE: {
ff5c2c03 3180 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3181 if (IS_ERR(u.xsave))
3182 return PTR_ERR(u.xsave);
2d5b5a66 3183
d1ac91d8 3184 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3185 break;
3186 }
3187 case KVM_GET_XCRS: {
d1ac91d8 3188 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3189 r = -ENOMEM;
d1ac91d8 3190 if (!u.xcrs)
2d5b5a66
SY		 3191 break;
3192
d1ac91d8 3193 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3194
3195 r = -EFAULT;
d1ac91d8 3196 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3197 sizeof(struct kvm_xcrs)))
3198 break;
3199 r = 0;
3200 break;
3201 }
3202 case KVM_SET_XCRS: {
ff5c2c03 3203 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3204 if (IS_ERR(u.xcrs))
3205 return PTR_ERR(u.xcrs);
2d5b5a66 3206
d1ac91d8 3207 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3208 break;
3209 }
92a1f12d
JR		 3210 case KVM_SET_TSC_KHZ: {
3211 u32 user_tsc_khz;
3212
3213 r = -EINVAL;
92a1f12d
JR		 3214 user_tsc_khz = (u32)arg;
3215
3216 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3217 goto out;
3218
cc578287
ZA		 3219 if (user_tsc_khz == 0)
3220 user_tsc_khz = tsc_khz;
3221
3222 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3223
3224 r = 0;
3225 goto out;
3226 }
3227 case KVM_GET_TSC_KHZ: {
cc578287 3228 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3229 goto out;
3230 }
1c0b28c2
EM		 3231 case KVM_KVMCLOCK_CTRL: {
3232 r = kvm_set_guest_paused(vcpu);
3233 goto out;
3234 }
313a3dc7
CO		 3235 default:
3236 r = -EINVAL;
3237 }
3238out:
d1ac91d8 3239 kfree(u.buffer);
313a3dc7
CO		 3240 return r;
3241}
3242
5b1c1493
CO		 3243int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3244{
3245 return VM_FAULT_SIGBUS;
3246}
3247
1fe779f8
CO		 3248static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3249{
3250 int ret;
3251
3252 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3253 return -EINVAL;
1fe779f8
CO		 3254 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3255 return ret;
3256}
3257
b927a3ce
SY		 3258static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3259 u64 ident_addr)
3260{
3261 kvm->arch.ept_identity_map_addr = ident_addr;
3262 return 0;
3263}
3264
1fe779f8
CO		 3265static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3266 u32 kvm_nr_mmu_pages)
3267{
3268 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3269 return -EINVAL;
3270
79fac95e 3271 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3272
3273 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3274 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3275
79fac95e 3276 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3277 return 0;
3278}
3279
3280static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3281{
39de71ec 3282 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3283}
3284
1fe779f8
CO		 3285static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3286{
3287 int r;
3288
3289 r = 0;
3290 switch (chip->chip_id) {
3291 case KVM_IRQCHIP_PIC_MASTER:
3292 memcpy(&chip->chip.pic,
3293 &pic_irqchip(kvm)->pics[0],
3294 sizeof(struct kvm_pic_state));
3295 break;
3296 case KVM_IRQCHIP_PIC_SLAVE:
3297 memcpy(&chip->chip.pic,
3298 &pic_irqchip(kvm)->pics[1],
3299 sizeof(struct kvm_pic_state));
3300 break;
3301 case KVM_IRQCHIP_IOAPIC:
eba0226b 3302 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3303 break;
3304 default:
3305 r = -EINVAL;
3306 break;
3307 }
3308 return r;
3309}
3310
3311static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3312{
3313 int r;
3314
3315 r = 0;
3316 switch (chip->chip_id) {
3317 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3318 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3319 memcpy(&pic_irqchip(kvm)->pics[0],
3320 &chip->chip.pic,
3321 sizeof(struct kvm_pic_state));
f4f51050 3322 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3323 break;
3324 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3325 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3326 memcpy(&pic_irqchip(kvm)->pics[1],
3327 &chip->chip.pic,
3328 sizeof(struct kvm_pic_state));
f4f51050 3329 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3330 break;
3331 case KVM_IRQCHIP_IOAPIC:
eba0226b 3332 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3333 break;
3334 default:
3335 r = -EINVAL;
3336 break;
3337 }
3338 kvm_pic_update_irq(pic_irqchip(kvm));
3339 return r;
3340}
3341
e0f63cb9
SY		 3342static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3343{
3344 int r = 0;
3345
894a9c55 3346 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3347 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3348 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3349 return r;
3350}
3351
3352static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3353{
3354 int r = 0;
3355
894a9c55 3356 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3357 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3358 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3359 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3360 return r;
3361}
3362
3363static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3364{
3365 int r = 0;
3366
3367 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3368 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3369 sizeof(ps->channels));
3370 ps->flags = kvm->arch.vpit->pit_state.flags;
3371 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3372 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3373 return r;
3374}
3375
3376static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3377{
3378 int r = 0, start = 0;
3379 u32 prev_legacy, cur_legacy;
3380 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3381 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3382 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3383 if (!prev_legacy && cur_legacy)
3384 start = 1;
3385 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3386 sizeof(kvm->arch.vpit->pit_state.channels));
3387 kvm->arch.vpit->pit_state.flags = ps->flags;
3388 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3389 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3390 return r;
3391}
3392
52d939a0
MT		 3393static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3394 struct kvm_reinject_control *control)
3395{
3396 if (!kvm->arch.vpit)
3397 return -ENXIO;
894a9c55 3398 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3399 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3400 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3401 return 0;
3402}
3403
95d4c16c 3404/**
60c34612
TY		 3405 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3406 * @kvm: kvm instance
3407 * @log: slot id and address to which we copy the log
95d4c16c 3408 *
60c34612
TY		 3409 * We need to keep it in mind that VCPU threads can write to the bitmap
3410 * concurrently. So, to avoid losing data, we keep the following order for
3411 * each bit:
95d4c16c 3412 *
60c34612
TY		 3413 * 1. Take a snapshot of the bit and clear it if needed.
3414 * 2. Write protect the corresponding page.
3415 * 3. Flush TLB's if needed.
3416 * 4. Copy the snapshot to the userspace.
95d4c16c 3417 *
60c34612
TY		 3418 * Between 2 and 3, the guest may write to the page using the remaining TLB
3419 * entry. This is not a problem because the page will be reported dirty at
3420 * step 4 using the snapshot taken before and step 3 ensures that successive
3421 * writes will be logged for the next call.
5bb064dc 3422 */
60c34612 3423int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3424{
7850ac54 3425 int r;
5bb064dc 3426 struct kvm_memory_slot *memslot;
60c34612
TY		 3427 unsigned long n, i;
3428 unsigned long *dirty_bitmap;
3429 unsigned long *dirty_bitmap_buffer;
3430 bool is_dirty = false;
5bb064dc 3431
79fac95e 3432 mutex_lock(&kvm->slots_lock);
5bb064dc 3433
b050b015 3434 r = -EINVAL;
bbacc0c1 3435 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3436 goto out;
3437
28a37544 3438 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3439
3440 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3441 r = -ENOENT;
60c34612 3442 if (!dirty_bitmap)
b050b015
MT		 3443 goto out;
3444
87bf6e7d 3445 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3446
60c34612
TY		 3447 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3448 memset(dirty_bitmap_buffer, 0, n);
b050b015 3449
60c34612 3450 spin_lock(&kvm->mmu_lock);
b050b015 3451
60c34612
TY		 3452 for (i = 0; i < n / sizeof(long); i++) {
3453 unsigned long mask;
3454 gfn_t offset;
cdfca7b3 3455
60c34612
TY		 3456 if (!dirty_bitmap[i])
3457 continue;
b050b015 3458
60c34612 3459 is_dirty = true;
914ebccd 3460
60c34612
TY		 3461 mask = xchg(&dirty_bitmap[i], 0);
3462 dirty_bitmap_buffer[i] = mask;
edde99ce 3463
60c34612
TY		 3464 offset = i * BITS_PER_LONG;
3465 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3466 }
60c34612
TY		 3467 if (is_dirty)
3468 kvm_flush_remote_tlbs(kvm);
3469
3470 spin_unlock(&kvm->mmu_lock);
3471
3472 r = -EFAULT;
3473 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3474 goto out;
b050b015 3475
5bb064dc
ZX		 3476 r = 0;
3477out:
79fac95e 3478 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3479 return r;
3480}
3481
23d43cf9
CD		 3482int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3483{
3484 if (!irqchip_in_kernel(kvm))
3485 return -ENXIO;
3486
3487 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3488 irq_event->irq, irq_event->level);
3489 return 0;
3490}
3491
1fe779f8
CO		 3492long kvm_arch_vm_ioctl(struct file *filp,
3493 unsigned int ioctl, unsigned long arg)
3494{
3495 struct kvm *kvm = filp->private_data;
3496 void __user *argp = (void __user *)arg;
367e1319 3497 int r = -ENOTTY;
f0d66275
DH		 3498 /*
3499 * This union makes it completely explicit to gcc-3.x
3500 * that these two variables' stack usage should be
3501 * combined, not added together.
3502 */
3503 union {
3504 struct kvm_pit_state ps;
e9f42757 3505 struct kvm_pit_state2 ps2;
c5ff41ce 3506 struct kvm_pit_config pit_config;
f0d66275 3507 } u;
1fe779f8
CO		 3508
3509 switch (ioctl) {
3510 case KVM_SET_TSS_ADDR:
3511 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3512 break;
b927a3ce
SY		 3513 case KVM_SET_IDENTITY_MAP_ADDR: {
3514 u64 ident_addr;
3515
3516 r = -EFAULT;
3517 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3518 goto out;
3519 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3520 break;
3521 }
1fe779f8
CO		 3522 case KVM_SET_NR_MMU_PAGES:
3523 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3524 break;
3525 case KVM_GET_NR_MMU_PAGES:
3526 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3527 break;
3ddea128
MT		 3528 case KVM_CREATE_IRQCHIP: {
3529 struct kvm_pic *vpic;
3530
3531 mutex_lock(&kvm->lock);
3532 r = -EEXIST;
3533 if (kvm->arch.vpic)
3534 goto create_irqchip_unlock;
3e515705
AK		 3535 r = -EINVAL;
3536 if (atomic_read(&kvm->online_vcpus))
3537 goto create_irqchip_unlock;
1fe779f8 3538 r = -ENOMEM;
3ddea128
MT		 3539 vpic = kvm_create_pic(kvm);
3540 if (vpic) {
1fe779f8
CO		 3541 r = kvm_ioapic_init(kvm);
3542 if (r) {
175504cd 3543 mutex_lock(&kvm->slots_lock);
72bb2fcd 3544 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3545 &vpic->dev_master);
3546 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3547 &vpic->dev_slave);
3548 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3549 &vpic->dev_eclr);
175504cd 3550 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3551 kfree(vpic);
3552 goto create_irqchip_unlock;
1fe779f8
CO		 3553 }
3554 } else
3ddea128
MT		 3555 goto create_irqchip_unlock;
3556 smp_wmb();
3557 kvm->arch.vpic = vpic;
3558 smp_wmb();
399ec807
AK		 3559 r = kvm_setup_default_irq_routing(kvm);
3560 if (r) {
175504cd 3561 mutex_lock(&kvm->slots_lock);
3ddea128 3562 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3563 kvm_ioapic_destroy(kvm);
3564 kvm_destroy_pic(kvm);
3ddea128 3565 mutex_unlock(&kvm->irq_lock);
175504cd 3566 mutex_unlock(&kvm->slots_lock);
399ec807 3567 }
3ddea128
MT		 3568 create_irqchip_unlock:
3569 mutex_unlock(&kvm->lock);
1fe779f8 3570 break;
3ddea128 3571 }
7837699f 3572 case KVM_CREATE_PIT:
c5ff41ce
JK		 3573 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3574 goto create_pit;
3575 case KVM_CREATE_PIT2:
3576 r = -EFAULT;
3577 if (copy_from_user(&u.pit_config, argp,
3578 sizeof(struct kvm_pit_config)))
3579 goto out;
3580 create_pit:
79fac95e 3581 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3582 r = -EEXIST;
3583 if (kvm->arch.vpit)
3584 goto create_pit_unlock;
7837699f 3585 r = -ENOMEM;
c5ff41ce 3586 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3587 if (kvm->arch.vpit)
3588 r = 0;
269e05e4 3589 create_pit_unlock:
79fac95e 3590 mutex_unlock(&kvm->slots_lock);
7837699f 3591 break;
1fe779f8
CO		 3592 case KVM_GET_IRQCHIP: {
3593 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3594 struct kvm_irqchip *chip;
1fe779f8 3595
ff5c2c03
SL		 3596 chip = memdup_user(argp, sizeof(*chip));
3597 if (IS_ERR(chip)) {
3598 r = PTR_ERR(chip);
1fe779f8 3599 goto out;
ff5c2c03
SL		 3600 }
3601
1fe779f8
CO		 3602 r = -ENXIO;
3603 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3604 goto get_irqchip_out;
3605 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3606 if (r)
f0d66275 3607 goto get_irqchip_out;
1fe779f8 3608 r = -EFAULT;
f0d66275
DH		 3609 if (copy_to_user(argp, chip, sizeof *chip))
3610 goto get_irqchip_out;
1fe779f8 3611 r = 0;
f0d66275
DH		 3612 get_irqchip_out:
3613 kfree(chip);
1fe779f8
CO		 3614 break;
3615 }
3616 case KVM_SET_IRQCHIP: {
3617 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3618 struct kvm_irqchip *chip;
1fe779f8 3619
ff5c2c03
SL		 3620 chip = memdup_user(argp, sizeof(*chip));
3621 if (IS_ERR(chip)) {
3622 r = PTR_ERR(chip);
1fe779f8 3623 goto out;
ff5c2c03
SL		 3624 }
3625
1fe779f8
CO		 3626 r = -ENXIO;
3627 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3628 goto set_irqchip_out;
3629 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3630 if (r)
f0d66275 3631 goto set_irqchip_out;
1fe779f8 3632 r = 0;
f0d66275
DH		 3633 set_irqchip_out:
3634 kfree(chip);
1fe779f8
CO		 3635 break;
3636 }
e0f63cb9 3637 case KVM_GET_PIT: {
e0f63cb9 3638 r = -EFAULT;
f0d66275 3639 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3640 goto out;
3641 r = -ENXIO;
3642 if (!kvm->arch.vpit)
3643 goto out;
f0d66275 3644 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3645 if (r)
3646 goto out;
3647 r = -EFAULT;
f0d66275 3648 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3649 goto out;
3650 r = 0;
3651 break;
3652 }
3653 case KVM_SET_PIT: {
e0f63cb9 3654 r = -EFAULT;
f0d66275 3655 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3656 goto out;
3657 r = -ENXIO;
3658 if (!kvm->arch.vpit)
3659 goto out;
f0d66275 3660 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3661 break;
3662 }
e9f42757
BK		 3663 case KVM_GET_PIT2: {
3664 r = -ENXIO;
3665 if (!kvm->arch.vpit)
3666 goto out;
3667 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3668 if (r)
3669 goto out;
3670 r = -EFAULT;
3671 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3672 goto out;
3673 r = 0;
3674 break;
3675 }
3676 case KVM_SET_PIT2: {
3677 r = -EFAULT;
3678 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3679 goto out;
3680 r = -ENXIO;
3681 if (!kvm->arch.vpit)
3682 goto out;
3683 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3684 break;
3685 }
52d939a0
MT		 3686 case KVM_REINJECT_CONTROL: {
3687 struct kvm_reinject_control control;
3688 r = -EFAULT;
3689 if (copy_from_user(&control, argp, sizeof(control)))
3690 goto out;
3691 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3692 break;
3693 }
ffde22ac
ES		 3694 case KVM_XEN_HVM_CONFIG: {
3695 r = -EFAULT;
3696 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3697 sizeof(struct kvm_xen_hvm_config)))
3698 goto out;
3699 r = -EINVAL;
3700 if (kvm->arch.xen_hvm_config.flags)
3701 goto out;
3702 r = 0;
3703 break;
3704 }
afbcf7ab 3705 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3706 struct kvm_clock_data user_ns;
3707 u64 now_ns;
3708 s64 delta;
3709
3710 r = -EFAULT;
3711 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3712 goto out;
3713
3714 r = -EINVAL;
3715 if (user_ns.flags)
3716 goto out;
3717
3718 r = 0;
395c6b0a 3719 local_irq_disable();
759379dd 3720 now_ns = get_kernel_ns();
afbcf7ab 3721 delta = user_ns.clock - now_ns;
395c6b0a 3722 local_irq_enable();
afbcf7ab
GC		 3723 kvm->arch.kvmclock_offset = delta;
3724 break;
3725 }
3726 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3727 struct kvm_clock_data user_ns;
3728 u64 now_ns;
3729
395c6b0a 3730 local_irq_disable();
759379dd 3731 now_ns = get_kernel_ns();
afbcf7ab 3732 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3733 local_irq_enable();
afbcf7ab 3734 user_ns.flags = 0;
97e69aa6 3735 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3736
3737 r = -EFAULT;
3738 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3739 goto out;
3740 r = 0;
3741 break;
3742 }
3743
1fe779f8
CO		 3744 default:
3745 ;
3746 }
3747out:
3748 return r;
3749}
3750
a16b043c 3751static void kvm_init_msr_list(void)
043405e1
CO		 3752{
3753 u32 dummy[2];
3754 unsigned i, j;
3755
e3267cbb
GC		 3756 /* skip the first msrs in the list. KVM-specific */
3757 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3758 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3759 continue;
3760 if (j < i)
3761 msrs_to_save[j] = msrs_to_save[i];
3762 j++;
3763 }
3764 num_msrs_to_save = j;
3765}
3766
bda9020e
MT		 3767static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3768 const void *v)
bbd9b64e 3769{
70252a10
AK		 3770 int handled = 0;
3771 int n;
3772
3773 do {
3774 n = min(len, 8);
3775 if (!(vcpu->arch.apic &&
3776 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3777 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3778 break;
3779 handled += n;
3780 addr += n;
3781 len -= n;
3782 v += n;
3783 } while (len);
bbd9b64e 3784
70252a10 3785 return handled;
bbd9b64e
CO		 3786}
3787
bda9020e 3788static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3789{
70252a10
AK		 3790 int handled = 0;
3791 int n;
3792
3793 do {
3794 n = min(len, 8);
3795 if (!(vcpu->arch.apic &&
3796 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3797 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3798 break;
3799 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3800 handled += n;
3801 addr += n;
3802 len -= n;
3803 v += n;
3804 } while (len);
bbd9b64e 3805
70252a10 3806 return handled;
bbd9b64e
CO		 3807}
3808
2dafc6c2
GN		 3809static void kvm_set_segment(struct kvm_vcpu *vcpu,
3810 struct kvm_segment *var, int seg)
3811{
3812 kvm_x86_ops->set_segment(vcpu, var, seg);
3813}
3814
3815void kvm_get_segment(struct kvm_vcpu *vcpu,
3816 struct kvm_segment *var, int seg)
3817{
3818 kvm_x86_ops->get_segment(vcpu, var, seg);
3819}
3820
e459e322 3821gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3822{
3823 gpa_t t_gpa;
ab9ae313 3824 struct x86_exception exception;
02f59dc9
JR		 3825
3826 BUG_ON(!mmu_is_nested(vcpu));
3827
3828 /* NPT walks are always user-walks */
3829 access |= PFERR_USER_MASK;
ab9ae313 3830 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3831
3832 return t_gpa;
3833}
3834
ab9ae313
AK		 3835gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3836 struct x86_exception *exception)
1871c602
GN		 3837{
3838 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3839 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3840}
3841
ab9ae313
AK		 3842 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3843 struct x86_exception *exception)
1871c602
GN		 3844{
3845 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3846 access |= PFERR_FETCH_MASK;
ab9ae313 3847 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3848}
3849
ab9ae313
AK		 3850gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3851 struct x86_exception *exception)
1871c602
GN		 3852{
3853 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3854 access |= PFERR_WRITE_MASK;
ab9ae313 3855 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3856}
3857
3858/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3859gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3860 struct x86_exception *exception)
1871c602 3861{
ab9ae313 3862 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3863}
3864
3865static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3866 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3867 struct x86_exception *exception)
bbd9b64e
CO		 3868{
3869 void *data = val;
10589a46 3870 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3871
3872 while (bytes) {
14dfe855 3873 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3874 exception);
bbd9b64e 3875 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3876 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3877 int ret;
3878
bcc55cba 3879 if (gpa == UNMAPPED_GVA)
ab9ae313 3880 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3881 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3882 if (ret < 0) {
c3cd7ffa 3883 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3884 goto out;
3885 }
bbd9b64e 3886
77c2002e
IE		 3887 bytes -= toread;
3888 data += toread;
3889 addr += toread;
bbd9b64e 3890 }
10589a46 3891out:
10589a46 3892 return r;
bbd9b64e 3893}
77c2002e 3894
1871c602 3895/* used for instruction fetching */
0f65dd70
AK		 3896static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3897 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3898 struct x86_exception *exception)
1871c602 3899{
0f65dd70 3900 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3901 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3902
1871c602 3903 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3904 access | PFERR_FETCH_MASK,
3905 exception);
1871c602
GN		 3906}
3907
064aea77 3908int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3909 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3910 struct x86_exception *exception)
1871c602 3911{
0f65dd70 3912 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3913 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3914
1871c602 3915 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3916 exception);
1871c602 3917}
064aea77 3918EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3919
0f65dd70
AK		 3920static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3921 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3922 struct x86_exception *exception)
1871c602 3923{
0f65dd70 3924 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3925 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3926}
3927
6a4d7550 3928int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3929 gva_t addr, void *val,
2dafc6c2 3930 unsigned int bytes,
bcc55cba 3931 struct x86_exception *exception)
77c2002e 3932{
0f65dd70 3933 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3934 void *data = val;
3935 int r = X86EMUL_CONTINUE;
3936
3937 while (bytes) {
14dfe855
JR		 3938 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3939 PFERR_WRITE_MASK,
ab9ae313 3940 exception);
77c2002e
IE		 3941 unsigned offset = addr & (PAGE_SIZE-1);
3942 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3943 int ret;
3944
bcc55cba 3945 if (gpa == UNMAPPED_GVA)
ab9ae313 3946 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3947 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3948 if (ret < 0) {
c3cd7ffa 3949 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3950 goto out;
3951 }
3952
3953 bytes -= towrite;
3954 data += towrite;
3955 addr += towrite;
3956 }
3957out:
3958 return r;
3959}
6a4d7550 3960EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3961
af7cc7d1
XG		 3962static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3963 gpa_t *gpa, struct x86_exception *exception,
3964 bool write)
3965{
97d64b78
AK		 3966 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3967 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 3968
97d64b78
AK		 3969 if (vcpu_match_mmio_gva(vcpu, gva)
3970 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 3971 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3972 (gva & (PAGE_SIZE - 1));
4f022648 3973 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3974 return 1;
3975 }
3976
af7cc7d1
XG		 3977 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3978
3979 if (*gpa == UNMAPPED_GVA)
3980 return -1;
3981
3982 /* For APIC access vmexit */
3983 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3984 return 1;
3985
4f022648
XG		 3986 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3987 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3988 return 1;
4f022648 3989 }
bebb106a 3990
af7cc7d1
XG		 3991 return 0;
3992}
3993
3200f405 3994int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3995 const void *val, int bytes)
bbd9b64e
CO		 3996{
3997 int ret;
3998
3999 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4000 if (ret < 0)
bbd9b64e 4001 return 0;
f57f2ef5 4002 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4003 return 1;
4004}
4005
77d197b2
XG		 4006struct read_write_emulator_ops {
4007 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4008 int bytes);
4009 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4010 void *val, int bytes);
4011 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4012 int bytes, void *val);
4013 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4014 void *val, int bytes);
4015 bool write;
4016};
4017
4018static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4019{
4020 if (vcpu->mmio_read_completed) {
77d197b2 4021 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4022 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4023 vcpu->mmio_read_completed = 0;
4024 return 1;
4025 }
4026
4027 return 0;
4028}
4029
4030static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4031 void *val, int bytes)
4032{
4033 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4034}
4035
4036static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4037 void *val, int bytes)
4038{
4039 return emulator_write_phys(vcpu, gpa, val, bytes);
4040}
4041
4042static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4043{
4044 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4045 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4046}
4047
4048static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4049 void *val, int bytes)
4050{
4051 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4052 return X86EMUL_IO_NEEDED;
4053}
4054
4055static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4056 void *val, int bytes)
4057{
f78146b0
AK		 4058 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4059
87da7e66 4060 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4061 return X86EMUL_CONTINUE;
4062}
4063
0fbe9b0b 4064static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4065 .read_write_prepare = read_prepare,
4066 .read_write_emulate = read_emulate,
4067 .read_write_mmio = vcpu_mmio_read,
4068 .read_write_exit_mmio = read_exit_mmio,
4069};
4070
0fbe9b0b 4071static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4072 .read_write_emulate = write_emulate,
4073 .read_write_mmio = write_mmio,
4074 .read_write_exit_mmio = write_exit_mmio,
4075 .write = true,
4076};
4077
22388a3c
XG		 4078static int emulator_read_write_onepage(unsigned long addr, void *val,
4079 unsigned int bytes,
4080 struct x86_exception *exception,
4081 struct kvm_vcpu *vcpu,
0fbe9b0b 4082 const struct read_write_emulator_ops *ops)
bbd9b64e 4083{
af7cc7d1
XG		 4084 gpa_t gpa;
4085 int handled, ret;
22388a3c 4086 bool write = ops->write;
f78146b0 4087 struct kvm_mmio_fragment *frag;
10589a46 4088
22388a3c 4089 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4090
af7cc7d1 4091 if (ret < 0)
bbd9b64e 4092 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4093
4094 /* For APIC access vmexit */
af7cc7d1 4095 if (ret)
bbd9b64e
CO		 4096 goto mmio;
4097
22388a3c 4098 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4099 return X86EMUL_CONTINUE;
4100
4101mmio:
4102 /*
4103 * Is this MMIO handled locally?
4104 */
22388a3c 4105 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4106 if (handled == bytes)
bbd9b64e 4107 return X86EMUL_CONTINUE;
bbd9b64e 4108
70252a10
AK		 4109 gpa += handled;
4110 bytes -= handled;
4111 val += handled;
4112
87da7e66
XG		 4113 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4114 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4115 frag->gpa = gpa;
4116 frag->data = val;
4117 frag->len = bytes;
f78146b0 4118 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4119}
4120
22388a3c
XG		 4121int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4122 void *val, unsigned int bytes,
4123 struct x86_exception *exception,
0fbe9b0b 4124 const struct read_write_emulator_ops *ops)
bbd9b64e 4125{
0f65dd70 4126 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4127 gpa_t gpa;
4128 int rc;
4129
4130 if (ops->read_write_prepare &&
4131 ops->read_write_prepare(vcpu, val, bytes))
4132 return X86EMUL_CONTINUE;
4133
4134 vcpu->mmio_nr_fragments = 0;
0f65dd70 4135
bbd9b64e
CO		 4136 /* Crossing a page boundary? */
4137 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4138 int now;
bbd9b64e
CO		 4139
4140 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4141 rc = emulator_read_write_onepage(addr, val, now, exception,
4142 vcpu, ops);
4143
bbd9b64e
CO		 4144 if (rc != X86EMUL_CONTINUE)
4145 return rc;
4146 addr += now;
4147 val += now;
4148 bytes -= now;
4149 }
22388a3c 4150
f78146b0
AK		 4151 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4152 vcpu, ops);
4153 if (rc != X86EMUL_CONTINUE)
4154 return rc;
4155
4156 if (!vcpu->mmio_nr_fragments)
4157 return rc;
4158
4159 gpa = vcpu->mmio_fragments[0].gpa;
4160
4161 vcpu->mmio_needed = 1;
4162 vcpu->mmio_cur_fragment = 0;
4163
87da7e66 4164 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4165 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4166 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4167 vcpu->run->mmio.phys_addr = gpa;
4168
4169 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4170}
4171
4172static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4173 unsigned long addr,
4174 void *val,
4175 unsigned int bytes,
4176 struct x86_exception *exception)
4177{
4178 return emulator_read_write(ctxt, addr, val, bytes,
4179 exception, &read_emultor);
4180}
4181
4182int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4183 unsigned long addr,
4184 const void *val,
4185 unsigned int bytes,
4186 struct x86_exception *exception)
4187{
4188 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4189 exception, &write_emultor);
bbd9b64e 4190}
bbd9b64e 4191
daea3e73
AK		 4192#define CMPXCHG_TYPE(t, ptr, old, new) \
4193 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4194
4195#ifdef CONFIG_X86_64
4196# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4197#else
4198# define CMPXCHG64(ptr, old, new) \
9749a6c0 4199 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4200#endif
4201
0f65dd70
AK		 4202static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4203 unsigned long addr,
bbd9b64e
CO		 4204 const void *old,
4205 const void *new,
4206 unsigned int bytes,
0f65dd70 4207 struct x86_exception *exception)
bbd9b64e 4208{
0f65dd70 4209 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4210 gpa_t gpa;
4211 struct page *page;
4212 char *kaddr;
4213 bool exchanged;
2bacc55c 4214
daea3e73
AK		 4215 /* guests cmpxchg8b have to be emulated atomically */
4216 if (bytes > 8 || (bytes & (bytes - 1)))
4217 goto emul_write;
10589a46 4218
daea3e73 4219 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4220
daea3e73
AK		 4221 if (gpa == UNMAPPED_GVA ||
4222 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4223 goto emul_write;
2bacc55c 4224
daea3e73
AK		 4225 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4226 goto emul_write;
72dc67a6 4227
daea3e73 4228 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4229 if (is_error_page(page))
c19b8bd6 4230 goto emul_write;
72dc67a6 4231
8fd75e12 4232 kaddr = kmap_atomic(page);
daea3e73
AK		 4233 kaddr += offset_in_page(gpa);
4234 switch (bytes) {
4235 case 1:
4236 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4237 break;
4238 case 2:
4239 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4240 break;
4241 case 4:
4242 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4243 break;
4244 case 8:
4245 exchanged = CMPXCHG64(kaddr, old, new);
4246 break;
4247 default:
4248 BUG();
2bacc55c 4249 }
8fd75e12 4250 kunmap_atomic(kaddr);
daea3e73
AK		 4251 kvm_release_page_dirty(page);
4252
4253 if (!exchanged)
4254 return X86EMUL_CMPXCHG_FAILED;
4255
f57f2ef5 4256 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4257
4258 return X86EMUL_CONTINUE;
4a5f48f6 4259
3200f405 4260emul_write:
daea3e73 4261 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4262
0f65dd70 4263 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4264}
4265
cf8f70bf
GN		 4266static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4267{
4268 /* TODO: String I/O for in kernel device */
4269 int r;
4270
4271 if (vcpu->arch.pio.in)
4272 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4273 vcpu->arch.pio.size, pd);
4274 else
4275 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4276 vcpu->arch.pio.port, vcpu->arch.pio.size,
4277 pd);
4278 return r;
4279}
4280
6f6fbe98
XG		 4281static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4282 unsigned short port, void *val,
4283 unsigned int count, bool in)
cf8f70bf 4284{
6f6fbe98 4285 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4286
4287 vcpu->arch.pio.port = port;
6f6fbe98 4288 vcpu->arch.pio.in = in;
7972995b 4289 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4290 vcpu->arch.pio.size = size;
4291
4292 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4293 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4294 return 1;
4295 }
4296
4297 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4298 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4299 vcpu->run->io.size = size;
4300 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4301 vcpu->run->io.count = count;
4302 vcpu->run->io.port = port;
4303
4304 return 0;
4305}
4306
6f6fbe98
XG		 4307static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4308 int size, unsigned short port, void *val,
4309 unsigned int count)
cf8f70bf 4310{
ca1d4a9e 4311 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4312 int ret;
ca1d4a9e 4313
6f6fbe98
XG		 4314 if (vcpu->arch.pio.count)
4315 goto data_avail;
cf8f70bf 4316
6f6fbe98
XG		 4317 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4318 if (ret) {
4319data_avail:
4320 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4321 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4322 return 1;
4323 }
4324
cf8f70bf
GN		 4325 return 0;
4326}
4327
6f6fbe98
XG		 4328static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4329 int size, unsigned short port,
4330 const void *val, unsigned int count)
4331{
4332 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4333
4334 memcpy(vcpu->arch.pio_data, val, size * count);
4335 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4336}
4337
bbd9b64e
CO		 4338static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4339{
4340 return kvm_x86_ops->get_segment_base(vcpu, seg);
4341}
4342
3cb16fe7 4343static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4344{
3cb16fe7 4345 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4346}
4347
f5f48ee1
SY		 4348int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4349{
4350 if (!need_emulate_wbinvd(vcpu))
4351 return X86EMUL_CONTINUE;
4352
4353 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4354 int cpu = get_cpu();
4355
4356 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4357 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4358 wbinvd_ipi, NULL, 1);
2eec7343 4359 put_cpu();
f5f48ee1 4360 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4361 } else
4362 wbinvd();
f5f48ee1
SY		 4363 return X86EMUL_CONTINUE;
4364}
4365EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4366
bcaf5cc5
AK		 4367static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4368{
4369 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4370}
4371
717746e3 4372int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4373{
717746e3 4374 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4375}
4376
717746e3 4377int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4378{
338dbc97 4379
717746e3 4380 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4381}
4382
52a46617 4383static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4384{
52a46617 4385 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4386}
4387
717746e3 4388static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4389{
717746e3 4390 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4391 unsigned long value;
4392
4393 switch (cr) {
4394 case 0:
4395 value = kvm_read_cr0(vcpu);
4396 break;
4397 case 2:
4398 value = vcpu->arch.cr2;
4399 break;
4400 case 3:
9f8fe504 4401 value = kvm_read_cr3(vcpu);
52a46617
GN		 4402 break;
4403 case 4:
4404 value = kvm_read_cr4(vcpu);
4405 break;
4406 case 8:
4407 value = kvm_get_cr8(vcpu);
4408 break;
4409 default:
a737f256 4410 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4411 return 0;
4412 }
4413
4414 return value;
4415}
4416
717746e3 4417static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4418{
717746e3 4419 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4420 int res = 0;
4421
52a46617
GN		 4422 switch (cr) {
4423 case 0:
49a9b07e 4424 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4425 break;
4426 case 2:
4427 vcpu->arch.cr2 = val;
4428 break;
4429 case 3:
2390218b 4430 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4431 break;
4432 case 4:
a83b29c6 4433 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4434 break;
4435 case 8:
eea1cff9 4436 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4437 break;
4438 default:
a737f256 4439 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4440 res = -1;
52a46617 4441 }
0f12244f
GN		 4442
4443 return res;
52a46617
GN		 4444}
4445
4cee4798
KW		 4446static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4447{
4448 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4449}
4450
717746e3 4451static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4452{
717746e3 4453 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4454}
4455
4bff1e86 4456static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4457{
4bff1e86 4458 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4459}
4460
4bff1e86 4461static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4462{
4bff1e86 4463 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4464}
4465
1ac9d0cf
AK		 4466static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4467{
4468 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4469}
4470
4471static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4472{
4473 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4474}
4475
4bff1e86
AK		 4476static unsigned long emulator_get_cached_segment_base(
4477 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4478{
4bff1e86 4479 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4480}
4481
1aa36616
AK		 4482static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4483 struct desc_struct *desc, u32 *base3,
4484 int seg)
2dafc6c2
GN		 4485{
4486 struct kvm_segment var;
4487
4bff1e86 4488 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4489 *selector = var.selector;
2dafc6c2 4490
378a8b09
GN		 4491 if (var.unusable) {
4492 memset(desc, 0, sizeof(*desc));
2dafc6c2 4493 return false;
378a8b09 4494 }
2dafc6c2
GN		 4495
4496 if (var.g)
4497 var.limit >>= 12;
4498 set_desc_limit(desc, var.limit);
4499 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4500#ifdef CONFIG_X86_64
4501 if (base3)
4502 *base3 = var.base >> 32;
4503#endif
2dafc6c2
GN		 4504 desc->type = var.type;
4505 desc->s = var.s;
4506 desc->dpl = var.dpl;
4507 desc->p = var.present;
4508 desc->avl = var.avl;
4509 desc->l = var.l;
4510 desc->d = var.db;
4511 desc->g = var.g;
4512
4513 return true;
4514}
4515
1aa36616
AK		 4516static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4517 struct desc_struct *desc, u32 base3,
4518 int seg)
2dafc6c2 4519{
4bff1e86 4520 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4521 struct kvm_segment var;
4522
1aa36616 4523 var.selector = selector;
2dafc6c2 4524 var.base = get_desc_base(desc);
5601d05b
GN		 4525#ifdef CONFIG_X86_64
4526 var.base |= ((u64)base3) << 32;
4527#endif
2dafc6c2
GN		 4528 var.limit = get_desc_limit(desc);
4529 if (desc->g)
4530 var.limit = (var.limit << 12) | 0xfff;
4531 var.type = desc->type;
4532 var.present = desc->p;
4533 var.dpl = desc->dpl;
4534 var.db = desc->d;
4535 var.s = desc->s;
4536 var.l = desc->l;
4537 var.g = desc->g;
4538 var.avl = desc->avl;
4539 var.present = desc->p;
4540 var.unusable = !var.present;
4541 var.padding = 0;
4542
4543 kvm_set_segment(vcpu, &var, seg);
4544 return;
4545}
4546
717746e3
AK		 4547static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4548 u32 msr_index, u64 *pdata)
4549{
4550 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4551}
4552
4553static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4554 u32 msr_index, u64 data)
4555{
8fe8ab46
WA		 4556 struct msr_data msr;
4557
4558 msr.data = data;
4559 msr.index = msr_index;
4560 msr.host_initiated = false;
4561 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4562}
4563
222d21aa
AK		 4564static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4565 u32 pmc, u64 *pdata)
4566{
4567 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4568}
4569
6c3287f7
AK		 4570static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4571{
4572 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4573}
4574
5037f6f3
AK		 4575static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4576{
4577 preempt_disable();
5197b808 4578 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4579 /*
4580 * CR0.TS may reference the host fpu state, not the guest fpu state,
4581 * so it may be clear at this point.
4582 */
4583 clts();
4584}
4585
4586static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4587{
4588 preempt_enable();
4589}
4590
2953538e 4591static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4592 struct x86_instruction_info *info,
c4f035c6
AK		 4593 enum x86_intercept_stage stage)
4594{
2953538e 4595 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4596}
4597
0017f93a 4598static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4599 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4600{
0017f93a 4601 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4602}
4603
dd856efa
AK		 4604static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4605{
4606 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4607}
4608
4609static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4610{
4611 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4612}
4613
0225fb50 4614static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4615 .read_gpr = emulator_read_gpr,
4616 .write_gpr = emulator_write_gpr,
1871c602 4617 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4618 .write_std = kvm_write_guest_virt_system,
1871c602 4619 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4620 .read_emulated = emulator_read_emulated,
4621 .write_emulated = emulator_write_emulated,
4622 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4623 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4624 .pio_in_emulated = emulator_pio_in_emulated,
4625 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4626 .get_segment = emulator_get_segment,
4627 .set_segment = emulator_set_segment,
5951c442 4628 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4629 .get_gdt = emulator_get_gdt,
160ce1f1 4630 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4631 .set_gdt = emulator_set_gdt,
4632 .set_idt = emulator_set_idt,
52a46617
GN		 4633 .get_cr = emulator_get_cr,
4634 .set_cr = emulator_set_cr,
4cee4798 4635 .set_rflags = emulator_set_rflags,
9c537244 4636 .cpl = emulator_get_cpl,
35aa5375
GN		 4637 .get_dr = emulator_get_dr,
4638 .set_dr = emulator_set_dr,
717746e3
AK		 4639 .set_msr = emulator_set_msr,
4640 .get_msr = emulator_get_msr,
222d21aa 4641 .read_pmc = emulator_read_pmc,
6c3287f7 4642 .halt = emulator_halt,
bcaf5cc5 4643 .wbinvd = emulator_wbinvd,
d6aa1000 4644 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4645 .get_fpu = emulator_get_fpu,
4646 .put_fpu = emulator_put_fpu,
c4f035c6 4647 .intercept = emulator_intercept,
bdb42f5a 4648 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4649};
4650
95cb2295
GN		 4651static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4652{
4653 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4654 /*
4655 * an sti; sti; sequence only disable interrupts for the first
4656 * instruction. So, if the last instruction, be it emulated or
4657 * not, left the system with the INT_STI flag enabled, it
4658 * means that the last instruction is an sti. We should not
4659 * leave the flag on in this case. The same goes for mov ss
4660 */
4661 if (!(int_shadow & mask))
4662 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4663}
4664
54b8486f
GN		 4665static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4666{
4667 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4668 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4669 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4670 else if (ctxt->exception.error_code_valid)
4671 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4672 ctxt->exception.error_code);
54b8486f 4673 else
da9cb575 4674 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4675}
4676
dd856efa 4677static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4678{
9dac77fa 4679 memset(&ctxt->twobyte, 0,
dd856efa 4680 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4681
9dac77fa
AK		 4682 ctxt->fetch.start = 0;
4683 ctxt->fetch.end = 0;
4684 ctxt->io_read.pos = 0;
4685 ctxt->io_read.end = 0;
4686 ctxt->mem_read.pos = 0;
4687 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4688}
4689
8ec4722d
MG		 4690static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4691{
adf52235 4692 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4693 int cs_db, cs_l;
4694
8ec4722d
MG		 4695 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4696
adf52235
TY		 4697 ctxt->eflags = kvm_get_rflags(vcpu);
4698 ctxt->eip = kvm_rip_read(vcpu);
4699 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4700 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4701 cs_l ? X86EMUL_MODE_PROT64 :
4702 cs_db ? X86EMUL_MODE_PROT32 :
4703 X86EMUL_MODE_PROT16;
4704 ctxt->guest_mode = is_guest_mode(vcpu);
4705
dd856efa 4706 init_decode_cache(ctxt);
7ae441ea 4707 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4708}
4709
71f9833b 4710int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4711{
9d74191a 4712 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4713 int ret;
4714
4715 init_emulate_ctxt(vcpu);
4716
9dac77fa
AK		 4717 ctxt->op_bytes = 2;
4718 ctxt->ad_bytes = 2;
4719 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4720 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4721
4722 if (ret != X86EMUL_CONTINUE)
4723 return EMULATE_FAIL;
4724
9dac77fa 4725 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4726 kvm_rip_write(vcpu, ctxt->eip);
4727 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4728
4729 if (irq == NMI_VECTOR)
7460fb4a 4730 vcpu->arch.nmi_pending = 0;
63995653
MG		 4731 else
4732 vcpu->arch.interrupt.pending = false;
4733
4734 return EMULATE_DONE;
4735}
4736EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4737
6d77dbfc
GN		 4738static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4739{
fc3a9157
JR		 4740 int r = EMULATE_DONE;
4741
6d77dbfc
GN		 4742 ++vcpu->stat.insn_emulation_fail;
4743 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4744 if (!is_guest_mode(vcpu)) {
4745 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4746 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4747 vcpu->run->internal.ndata = 0;
4748 r = EMULATE_FAIL;
4749 }
6d77dbfc 4750 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4751
4752 return r;
6d77dbfc
GN		 4753}
4754
93c05d3e
XG		 4755static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4756 bool write_fault_to_shadow_pgtable)
a6f177ef 4757{
95b3cf69 4758 gpa_t gpa = cr2;
8e3d9d06 4759 pfn_t pfn;
a6f177ef 4760
95b3cf69
XG		 4761 if (!vcpu->arch.mmu.direct_map) {
4762 /*
4763 * Write permission should be allowed since only
4764 * write access need to be emulated.
4765 */
4766 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4767
95b3cf69
XG		 4768 /*
4769 * If the mapping is invalid in guest, let cpu retry
4770 * it to generate fault.
4771 */
4772 if (gpa == UNMAPPED_GVA)
4773 return true;
4774 }
a6f177ef 4775
8e3d9d06
XG		 4776 /*
4777 * Do not retry the unhandleable instruction if it faults on the
4778 * readonly host memory, otherwise it will goto a infinite loop:
4779 * retry instruction -> write #PF -> emulation fail -> retry
4780 * instruction -> ...
4781 */
4782 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4783
4784 /*
4785 * If the instruction failed on the error pfn, it can not be fixed,
4786 * report the error to userspace.
4787 */
4788 if (is_error_noslot_pfn(pfn))
4789 return false;
4790
4791 kvm_release_pfn_clean(pfn);
4792
4793 /* The instructions are well-emulated on direct mmu. */
4794 if (vcpu->arch.mmu.direct_map) {
4795 unsigned int indirect_shadow_pages;
4796
4797 spin_lock(&vcpu->kvm->mmu_lock);
4798 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4799 spin_unlock(&vcpu->kvm->mmu_lock);
4800
4801 if (indirect_shadow_pages)
4802 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4803
a6f177ef 4804 return true;
8e3d9d06 4805 }
a6f177ef 4806
95b3cf69
XG		 4807 /*
4808 * if emulation was due to access to shadowed page table
4809 * and it failed try to unshadow page and re-enter the
4810 * guest to let CPU execute the instruction.
4811 */
4812 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4813
4814 /*
4815 * If the access faults on its page table, it can not
4816 * be fixed by unprotecting shadow page and it should
4817 * be reported to userspace.
4818 */
4819 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4820}
4821
1cb3f3ae
XG		 4822static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4823 unsigned long cr2, int emulation_type)
4824{
4825 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4826 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4827
4828 last_retry_eip = vcpu->arch.last_retry_eip;
4829 last_retry_addr = vcpu->arch.last_retry_addr;
4830
4831 /*
4832 * If the emulation is caused by #PF and it is non-page_table
4833 * writing instruction, it means the VM-EXIT is caused by shadow
4834 * page protected, we can zap the shadow page and retry this
4835 * instruction directly.
4836 *
4837 * Note: if the guest uses a non-page-table modifying instruction
4838 * on the PDE that points to the instruction, then we will unmap
4839 * the instruction and go to an infinite loop. So, we cache the
4840 * last retried eip and the last fault address, if we meet the eip
4841 * and the address again, we can break out of the potential infinite
4842 * loop.
4843 */
4844 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4845
4846 if (!(emulation_type & EMULTYPE_RETRY))
4847 return false;
4848
4849 if (x86_page_table_writing_insn(ctxt))
4850 return false;
4851
4852 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4853 return false;
4854
4855 vcpu->arch.last_retry_eip = ctxt->eip;
4856 vcpu->arch.last_retry_addr = cr2;
4857
4858 if (!vcpu->arch.mmu.direct_map)
4859 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4860
22368028 4861 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4862
4863 return true;
4864}
4865
716d51ab
GN		 4866static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4867static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4868
51d8b661
AP		 4869int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4870 unsigned long cr2,
dc25e89e
AP		 4871 int emulation_type,
4872 void *insn,
4873 int insn_len)
bbd9b64e 4874{
95cb2295 4875 int r;
9d74191a 4876 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4877 bool writeback = true;
93c05d3e 4878 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 4879
93c05d3e
XG		 4880 /*
4881 * Clear write_fault_to_shadow_pgtable here to ensure it is
4882 * never reused.
4883 */
4884 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 4885 kvm_clear_exception_queue(vcpu);
8d7d8102 4886
571008da 4887 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4888 init_emulate_ctxt(vcpu);
9d74191a
TY		 4889 ctxt->interruptibility = 0;
4890 ctxt->have_exception = false;
4891 ctxt->perm_ok = false;
bbd9b64e 4892
9d74191a 4893 ctxt->only_vendor_specific_insn
4005996e
AK		 4894 = emulation_type & EMULTYPE_TRAP_UD;
4895
9d74191a 4896 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4897
e46479f8 4898 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4899 ++vcpu->stat.insn_emulation;
1d2887e2 4900 if (r != EMULATION_OK) {
4005996e
AK		 4901 if (emulation_type & EMULTYPE_TRAP_UD)
4902 return EMULATE_FAIL;
93c05d3e
XG		 4903 if (reexecute_instruction(vcpu, cr2,
4904 write_fault_to_spt))
bbd9b64e 4905 return EMULATE_DONE;
6d77dbfc
GN		 4906 if (emulation_type & EMULTYPE_SKIP)
4907 return EMULATE_FAIL;
4908 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4909 }
4910 }
4911
ba8afb6b 4912 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4913 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4914 return EMULATE_DONE;
4915 }
4916
1cb3f3ae
XG		 4917 if (retry_instruction(ctxt, cr2, emulation_type))
4918 return EMULATE_DONE;
4919
7ae441ea 4920 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4921 changes registers values during IO operation */
7ae441ea
GN		 4922 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4923 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 4924 emulator_invalidate_register_cache(ctxt);
7ae441ea 4925 }
4d2179e1 4926
5cd21917 4927restart:
9d74191a 4928 r = x86_emulate_insn(ctxt);
bbd9b64e 4929
775fde86
JR		 4930 if (r == EMULATION_INTERCEPTED)
4931 return EMULATE_DONE;
4932
d2ddd1c4 4933 if (r == EMULATION_FAILED) {
93c05d3e 4934 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt))
c3cd7ffa
GN		 4935 return EMULATE_DONE;
4936
6d77dbfc 4937 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4938 }
4939
9d74191a 4940 if (ctxt->have_exception) {
54b8486f 4941 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4942 r = EMULATE_DONE;
4943 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4944 if (!vcpu->arch.pio.in)
4945 vcpu->arch.pio.count = 0;
716d51ab 4946 else {
7ae441ea 4947 writeback = false;
716d51ab
GN		 4948 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4949 }
e85d28f8 4950 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4951 } else if (vcpu->mmio_needed) {
4952 if (!vcpu->mmio_is_write)
4953 writeback = false;
e85d28f8 4954 r = EMULATE_DO_MMIO;
716d51ab 4955 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 4956 } else if (r == EMULATION_RESTART)
5cd21917 4957 goto restart;
d2ddd1c4
GN		 4958 else
4959 r = EMULATE_DONE;
f850e2e6 4960
7ae441ea 4961 if (writeback) {
9d74191a
TY		 4962 toggle_interruptibility(vcpu, ctxt->interruptibility);
4963 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4964 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 4965 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4966 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4967 } else
4968 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4969
4970 return r;
de7d789a 4971}
51d8b661 4972EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4973
cf8f70bf 4974int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4975{
cf8f70bf 4976 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4977 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4978 size, port, &val, 1);
cf8f70bf 4979 /* do not return to emulator after return from userspace */
7972995b 4980 vcpu->arch.pio.count = 0;
de7d789a
CO		 4981 return ret;
4982}
cf8f70bf 4983EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4984
8cfdc000
ZA		 4985static void tsc_bad(void *info)
4986{
0a3aee0d 4987 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4988}
4989
4990static void tsc_khz_changed(void *data)
c8076604 4991{
8cfdc000
ZA		 4992 struct cpufreq_freqs *freq = data;
4993 unsigned long khz = 0;
4994
4995 if (data)
4996 khz = freq->new;
4997 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4998 khz = cpufreq_quick_get(raw_smp_processor_id());
4999 if (!khz)
5000 khz = tsc_khz;
0a3aee0d 5001 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5002}
5003
c8076604
GH		 5004static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5005 void *data)
5006{
5007 struct cpufreq_freqs *freq = data;
5008 struct kvm *kvm;
5009 struct kvm_vcpu *vcpu;
5010 int i, send_ipi = 0;
5011
8cfdc000
ZA		 5012 /*
5013 * We allow guests to temporarily run on slowing clocks,
5014 * provided we notify them after, or to run on accelerating
5015 * clocks, provided we notify them before. Thus time never
5016 * goes backwards.
5017 *
5018 * However, we have a problem. We can't atomically update
5019 * the frequency of a given CPU from this function; it is
5020 * merely a notifier, which can be called from any CPU.
5021 * Changing the TSC frequency at arbitrary points in time
5022 * requires a recomputation of local variables related to
5023 * the TSC for each VCPU. We must flag these local variables
5024 * to be updated and be sure the update takes place with the
5025 * new frequency before any guests proceed.
5026 *
5027 * Unfortunately, the combination of hotplug CPU and frequency
5028 * change creates an intractable locking scenario; the order
5029 * of when these callouts happen is undefined with respect to
5030 * CPU hotplug, and they can race with each other. As such,
5031 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5032 * undefined; you can actually have a CPU frequency change take
5033 * place in between the computation of X and the setting of the
5034 * variable. To protect against this problem, all updates of
5035 * the per_cpu tsc_khz variable are done in an interrupt
5036 * protected IPI, and all callers wishing to update the value
5037 * must wait for a synchronous IPI to complete (which is trivial
5038 * if the caller is on the CPU already). This establishes the
5039 * necessary total order on variable updates.
5040 *
5041 * Note that because a guest time update may take place
5042 * anytime after the setting of the VCPU's request bit, the
5043 * correct TSC value must be set before the request. However,
5044 * to ensure the update actually makes it to any guest which
5045 * starts running in hardware virtualization between the set
5046 * and the acquisition of the spinlock, we must also ping the
5047 * CPU after setting the request bit.
5048 *
5049 */
5050
c8076604
GH		 5051 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5052 return 0;
5053 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5054 return 0;
8cfdc000
ZA		 5055
5056 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5057
e935b837 5058 raw_spin_lock(&kvm_lock);
c8076604 5059 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5060 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5061 if (vcpu->cpu != freq->cpu)
5062 continue;
c285545f 5063 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5064 if (vcpu->cpu != smp_processor_id())
8cfdc000 5065 send_ipi = 1;
c8076604
GH		 5066 }
5067 }
e935b837 5068 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5069
5070 if (freq->old < freq->new && send_ipi) {
5071 /*
5072 * We upscale the frequency. Must make the guest
5073 * doesn't see old kvmclock values while running with
5074 * the new frequency, otherwise we risk the guest sees
5075 * time go backwards.
5076 *
5077 * In case we update the frequency for another cpu
5078 * (which might be in guest context) send an interrupt
5079 * to kick the cpu out of guest context. Next time
5080 * guest context is entered kvmclock will be updated,
5081 * so the guest will not see stale values.
5082 */
8cfdc000 5083 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5084 }
5085 return 0;
5086}
5087
5088static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5089 .notifier_call = kvmclock_cpufreq_notifier
5090};
5091
5092static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5093 unsigned long action, void *hcpu)
5094{
5095 unsigned int cpu = (unsigned long)hcpu;
5096
5097 switch (action) {
5098 case CPU_ONLINE:
5099 case CPU_DOWN_FAILED:
5100 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5101 break;
5102 case CPU_DOWN_PREPARE:
5103 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5104 break;
5105 }
5106 return NOTIFY_OK;
5107}
5108
5109static struct notifier_block kvmclock_cpu_notifier_block = {
5110 .notifier_call = kvmclock_cpu_notifier,
5111 .priority = -INT_MAX
c8076604
GH		 5112};
5113
b820cc0c
ZA		 5114static void kvm_timer_init(void)
5115{
5116 int cpu;
5117
c285545f 5118 max_tsc_khz = tsc_khz;
8cfdc000 5119 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5120 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5121#ifdef CONFIG_CPU_FREQ
5122 struct cpufreq_policy policy;
5123 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5124 cpu = get_cpu();
5125 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5126 if (policy.cpuinfo.max_freq)
5127 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5128 put_cpu();
c285545f 5129#endif
b820cc0c
ZA		 5130 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5131 CPUFREQ_TRANSITION_NOTIFIER);
5132 }
c285545f 5133 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5134 for_each_online_cpu(cpu)
5135 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5136}
5137
ff9d07a0
ZY		 5138static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5139
f5132b01 5140int kvm_is_in_guest(void)
ff9d07a0 5141{
086c9855 5142 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5143}
5144
5145static int kvm_is_user_mode(void)
5146{
5147 int user_mode = 3;
dcf46b94 5148
086c9855
AS		 5149 if (__this_cpu_read(current_vcpu))
5150 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5151
ff9d07a0
ZY		 5152 return user_mode != 0;
5153}
5154
5155static unsigned long kvm_get_guest_ip(void)
5156{
5157 unsigned long ip = 0;
dcf46b94 5158
086c9855
AS		 5159 if (__this_cpu_read(current_vcpu))
5160 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5161
ff9d07a0
ZY		 5162 return ip;
5163}
5164
5165static struct perf_guest_info_callbacks kvm_guest_cbs = {
5166 .is_in_guest = kvm_is_in_guest,
5167 .is_user_mode = kvm_is_user_mode,
5168 .get_guest_ip = kvm_get_guest_ip,
5169};
5170
5171void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5172{
086c9855 5173 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5174}
5175EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5176
5177void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5178{
086c9855 5179 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5180}
5181EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5182
ce88decf
XG		 5183static void kvm_set_mmio_spte_mask(void)
5184{
5185 u64 mask;
5186 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5187
5188 /*
5189 * Set the reserved bits and the present bit of an paging-structure
5190 * entry to generate page fault with PFER.RSV = 1.
5191 */
5192 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5193 mask |= 1ull;
5194
5195#ifdef CONFIG_X86_64
5196 /*
5197 * If reserved bit is not supported, clear the present bit to disable
5198 * mmio page fault.
5199 */
5200 if (maxphyaddr == 52)
5201 mask &= ~1ull;
5202#endif
5203
5204 kvm_mmu_set_mmio_spte_mask(mask);
5205}
5206
16e8d74d
MT		 5207#ifdef CONFIG_X86_64
5208static void pvclock_gtod_update_fn(struct work_struct *work)
5209{
d828199e
MT		 5210 struct kvm *kvm;
5211
5212 struct kvm_vcpu *vcpu;
5213 int i;
5214
5215 raw_spin_lock(&kvm_lock);
5216 list_for_each_entry(kvm, &vm_list, vm_list)
5217 kvm_for_each_vcpu(i, vcpu, kvm)
5218 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5219 atomic_set(&kvm_guest_has_master_clock, 0);
5220 raw_spin_unlock(&kvm_lock);
16e8d74d
MT		 5221}
5222
5223static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5224
5225/*
5226 * Notification about pvclock gtod data update.
5227 */
5228static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5229 void *priv)
5230{
5231 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5232 struct timekeeper *tk = priv;
5233
5234 update_pvclock_gtod(tk);
5235
5236 /* disable master clock if host does not trust, or does not
5237 * use, TSC clocksource
5238 */
5239 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5240 atomic_read(&kvm_guest_has_master_clock) != 0)
5241 queue_work(system_long_wq, &pvclock_gtod_work);
5242
5243 return 0;
5244}
5245
5246static struct notifier_block pvclock_gtod_notifier = {
5247 .notifier_call = pvclock_gtod_notify,
5248};
5249#endif
5250
f8c16bba 5251int kvm_arch_init(void *opaque)
043405e1 5252{
b820cc0c 5253 int r;
f8c16bba
ZX		 5254 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5255
f8c16bba
ZX		 5256 if (kvm_x86_ops) {
5257 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5258 r = -EEXIST;
5259 goto out;
f8c16bba
ZX		 5260 }
5261
5262 if (!ops->cpu_has_kvm_support()) {
5263 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5264 r = -EOPNOTSUPP;
5265 goto out;
f8c16bba
ZX		 5266 }
5267 if (ops->disabled_by_bios()) {
5268 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5269 r = -EOPNOTSUPP;
5270 goto out;
f8c16bba
ZX		 5271 }
5272
013f6a5d
MT		 5273 r = -ENOMEM;
5274 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5275 if (!shared_msrs) {
5276 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5277 goto out;
5278 }
5279
97db56ce
AK		 5280 r = kvm_mmu_module_init();
5281 if (r)
013f6a5d 5282 goto out_free_percpu;
97db56ce 5283
ce88decf 5284 kvm_set_mmio_spte_mask();
97db56ce
AK		 5285 kvm_init_msr_list();
5286
f8c16bba 5287 kvm_x86_ops = ops;
7b52345e 5288 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5289 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5290
b820cc0c 5291 kvm_timer_init();
c8076604 5292
ff9d07a0
ZY		 5293 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5294
2acf923e
DC		 5295 if (cpu_has_xsave)
5296 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5297
c5cc421b 5298 kvm_lapic_init();
16e8d74d
MT		 5299#ifdef CONFIG_X86_64
5300 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5301#endif
5302
f8c16bba 5303 return 0;
56c6d28a 5304
013f6a5d
MT		 5305out_free_percpu:
5306 free_percpu(shared_msrs);
56c6d28a 5307out:
56c6d28a 5308 return r;
043405e1 5309}
8776e519 5310
f8c16bba
ZX		 5311void kvm_arch_exit(void)
5312{
ff9d07a0
ZY		 5313 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5314
888d256e
JK		 5315 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5316 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5317 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5318 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5319#ifdef CONFIG_X86_64
5320 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5321#endif
f8c16bba 5322 kvm_x86_ops = NULL;
56c6d28a 5323 kvm_mmu_module_exit();
013f6a5d 5324 free_percpu(shared_msrs);
56c6d28a 5325}
f8c16bba 5326
8776e519
HB		 5327int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5328{
5329 ++vcpu->stat.halt_exits;
5330 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5331 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5332 return 1;
5333 } else {
5334 vcpu->run->exit_reason = KVM_EXIT_HLT;
5335 return 0;
5336 }
5337}
5338EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5339
55cd8e5a
GN		 5340int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5341{
5342 u64 param, ingpa, outgpa, ret;
5343 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5344 bool fast, longmode;
5345 int cs_db, cs_l;
5346
5347 /*
5348 * hypercall generates UD from non zero cpl and real mode
5349 * per HYPER-V spec
5350 */
3eeb3288 5351 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5352 kvm_queue_exception(vcpu, UD_VECTOR);
5353 return 0;
5354 }
5355
5356 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5357 longmode = is_long_mode(vcpu) && cs_l == 1;
5358
5359 if (!longmode) {
ccd46936
GN		 5360 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5361 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5362 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5363 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5364 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5365 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5366 }
5367#ifdef CONFIG_X86_64
5368 else {
5369 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5370 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5371 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5372 }
5373#endif
5374
5375 code = param & 0xffff;
5376 fast = (param >> 16) & 0x1;
5377 rep_cnt = (param >> 32) & 0xfff;
5378 rep_idx = (param >> 48) & 0xfff;
5379
5380 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5381
c25bc163
GN		 5382 switch (code) {
5383 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5384 kvm_vcpu_on_spin(vcpu);
5385 break;
5386 default:
5387 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5388 break;
5389 }
55cd8e5a
GN		 5390
5391 ret = res | (((u64)rep_done & 0xfff) << 32);
5392 if (longmode) {
5393 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5394 } else {
5395 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5396 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5397 }
5398
5399 return 1;
5400}
5401
8776e519
HB		 5402int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5403{
5404 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5405 int r = 1;
8776e519 5406
55cd8e5a
GN		 5407 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5408 return kvm_hv_hypercall(vcpu);
5409
5fdbf976
MT		 5410 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5411 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5412 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5413 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5414 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5415
229456fc 5416 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5417
8776e519
HB		 5418 if (!is_long_mode(vcpu)) {
5419 nr &= 0xFFFFFFFF;
5420 a0 &= 0xFFFFFFFF;
5421 a1 &= 0xFFFFFFFF;
5422 a2 &= 0xFFFFFFFF;
5423 a3 &= 0xFFFFFFFF;
5424 }
5425
07708c4a
JK		 5426 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5427 ret = -KVM_EPERM;
5428 goto out;
5429 }
5430
8776e519 5431 switch (nr) {
b93463aa
AK		 5432 case KVM_HC_VAPIC_POLL_IRQ:
5433 ret = 0;
5434 break;
8776e519
HB		 5435 default:
5436 ret = -KVM_ENOSYS;
5437 break;
5438 }
07708c4a 5439out:
5fdbf976 5440 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5441 ++vcpu->stat.hypercalls;
2f333bcb 5442 return r;
8776e519
HB		 5443}
5444EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5445
b6785def 5446static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5447{
d6aa1000 5448 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5449 char instruction[3];
5fdbf976 5450 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5451
8776e519
HB		 5452 /*
5453 * Blow out the MMU to ensure that no other VCPU has an active mapping
5454 * to ensure that the updated hypercall appears atomically across all
5455 * VCPUs.
5456 */
5457 kvm_mmu_zap_all(vcpu->kvm);
5458
8776e519 5459 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5460
9d74191a 5461 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5462}
5463
b6c7a5dc
HB		 5464/*
5465 * Check if userspace requested an interrupt window, and that the
5466 * interrupt window is open.
5467 *
5468 * No need to exit to userspace if we already have an interrupt queued.
5469 */
851ba692 5470static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5471{
8061823a 5472 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5473 vcpu->run->request_interrupt_window &&
5df56646 5474 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5475}
5476
851ba692 5477static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5478{
851ba692
AK		 5479 struct kvm_run *kvm_run = vcpu->run;
5480
91586a3b 5481 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5482 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5483 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5484 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5485 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5486 else
b6c7a5dc 5487 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5488 kvm_arch_interrupt_allowed(vcpu) &&
5489 !kvm_cpu_has_interrupt(vcpu) &&
5490 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5491}
5492
4484141a 5493static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5494{
5495 struct kvm_lapic *apic = vcpu->arch.apic;
5496 struct page *page;
5497
5498 if (!apic || !apic->vapic_addr)
4484141a 5499 return 0;
b93463aa
AK		 5500
5501 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5502 if (is_error_page(page))
5503 return -EFAULT;
72dc67a6
IE		 5504
5505 vcpu->arch.apic->vapic_page = page;
4484141a 5506 return 0;
b93463aa
AK		 5507}
5508
5509static void vapic_exit(struct kvm_vcpu *vcpu)
5510{
5511 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5512 int idx;
b93463aa
AK		 5513
5514 if (!apic || !apic->vapic_addr)
5515 return;
5516
f656ce01 5517 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5518 kvm_release_page_dirty(apic->vapic_page);
5519 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5520 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5521}
5522
95ba8273
GN		 5523static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5524{
5525 int max_irr, tpr;
5526
5527 if (!kvm_x86_ops->update_cr8_intercept)
5528 return;
5529
88c808fd
AK		 5530 if (!vcpu->arch.apic)
5531 return;
5532
8db3baa2
GN		 5533 if (!vcpu->arch.apic->vapic_addr)
5534 max_irr = kvm_lapic_find_highest_irr(vcpu);
5535 else
5536 max_irr = -1;
95ba8273
GN		 5537
5538 if (max_irr != -1)
5539 max_irr >>= 4;
5540
5541 tpr = kvm_lapic_get_cr8(vcpu);
5542
5543 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5544}
5545
851ba692 5546static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5547{
5548 /* try to reinject previous events if any */
b59bb7bd 5549 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5550 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5551 vcpu->arch.exception.has_error_code,
5552 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5553 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5554 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5555 vcpu->arch.exception.error_code,
5556 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5557 return;
5558 }
5559
95ba8273
GN		 5560 if (vcpu->arch.nmi_injected) {
5561 kvm_x86_ops->set_nmi(vcpu);
5562 return;
5563 }
5564
5565 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5566 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5567 return;
5568 }
5569
5570 /* try to inject new event if pending */
5571 if (vcpu->arch.nmi_pending) {
5572 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5573 --vcpu->arch.nmi_pending;
95ba8273
GN		 5574 vcpu->arch.nmi_injected = true;
5575 kvm_x86_ops->set_nmi(vcpu);
5576 }
c7c9c56c 5577 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5578 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5579 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5580 false);
5581 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5582 }
5583 }
5584}
5585
2acf923e
DC		 5586static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5587{
5588 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5589 !vcpu->guest_xcr0_loaded) {
5590 /* kvm_set_xcr() also depends on this */
5591 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5592 vcpu->guest_xcr0_loaded = 1;
5593 }
5594}
5595
5596static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5597{
5598 if (vcpu->guest_xcr0_loaded) {
5599 if (vcpu->arch.xcr0 != host_xcr0)
5600 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5601 vcpu->guest_xcr0_loaded = 0;
5602 }
5603}
5604
7460fb4a
AK		 5605static void process_nmi(struct kvm_vcpu *vcpu)
5606{
5607 unsigned limit = 2;
5608
5609 /*
5610 * x86 is limited to one NMI running, and one NMI pending after it.
5611 * If an NMI is already in progress, limit further NMIs to just one.
5612 * Otherwise, allow two (and we'll inject the first one immediately).
5613 */
5614 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5615 limit = 1;
5616
5617 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5618 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5619 kvm_make_request(KVM_REQ_EVENT, vcpu);
5620}
5621
d828199e
MT		 5622static void kvm_gen_update_masterclock(struct kvm *kvm)
5623{
5624#ifdef CONFIG_X86_64
5625 int i;
5626 struct kvm_vcpu *vcpu;
5627 struct kvm_arch *ka = &kvm->arch;
5628
5629 spin_lock(&ka->pvclock_gtod_sync_lock);
5630 kvm_make_mclock_inprogress_request(kvm);
5631 /* no guest entries from this point */
5632 pvclock_update_vm_gtod_copy(kvm);
5633
5634 kvm_for_each_vcpu(i, vcpu, kvm)
5635 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5636
5637 /* guest entries allowed */
5638 kvm_for_each_vcpu(i, vcpu, kvm)
5639 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5640
5641 spin_unlock(&ka->pvclock_gtod_sync_lock);
5642#endif
5643}
5644
c7c9c56c
YZ		 5645static void update_eoi_exitmap(struct kvm_vcpu *vcpu)
5646{
5647 u64 eoi_exit_bitmap[4];
5648
5649 memset(eoi_exit_bitmap, 0, 32);
5650
5651 kvm_ioapic_calculate_eoi_exitmap(vcpu, eoi_exit_bitmap);
5652 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5653}
5654
851ba692 5655static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5656{
5657 int r;
6a8b1d13 5658 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5659 vcpu->run->request_interrupt_window;
d6185f20 5660 bool req_immediate_exit = 0;
b6c7a5dc 5661
3e007509 5662 if (vcpu->requests) {
a8eeb04a 5663 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5664 kvm_mmu_unload(vcpu);
a8eeb04a 5665 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5666 __kvm_migrate_timers(vcpu);
d828199e
MT		 5667 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5668 kvm_gen_update_masterclock(vcpu->kvm);
34c238a1
ZA		 5669 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5670 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5671 if (unlikely(r))
5672 goto out;
5673 }
a8eeb04a 5674 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5675 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5676 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5677 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5678 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5679 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5680 r = 0;
5681 goto out;
5682 }
a8eeb04a 5683 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5684 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5685 r = 0;
5686 goto out;
5687 }
a8eeb04a 5688 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5689 vcpu->fpu_active = 0;
5690 kvm_x86_ops->fpu_deactivate(vcpu);
5691 }
af585b92
GN		 5692 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5693 /* Page is swapped out. Do synthetic halt */
5694 vcpu->arch.apf.halted = true;
5695 r = 1;
5696 goto out;
5697 }
c9aaa895
GC		 5698 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5699 record_steal_time(vcpu);
7460fb4a
AK		 5700 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5701 process_nmi(vcpu);
d6185f20
NHE		 5702 req_immediate_exit =
5703 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5704 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5705 kvm_handle_pmu_event(vcpu);
5706 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5707 kvm_deliver_pmi(vcpu);
c7c9c56c
YZ		 5708 if (kvm_check_request(KVM_REQ_EOIBITMAP, vcpu))
5709 update_eoi_exitmap(vcpu);
2f52d58c 5710 }
b93463aa 5711
b463a6f7
AK		 5712 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5713 inject_pending_event(vcpu);
5714
5715 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5716 if (vcpu->arch.nmi_pending)
b463a6f7 5717 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 5718 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
b463a6f7
AK		 5719 kvm_x86_ops->enable_irq_window(vcpu);
5720
5721 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5722 /*
5723 * Update architecture specific hints for APIC
5724 * virtual interrupt delivery.
5725 */
5726 if (kvm_x86_ops->hwapic_irr_update)
5727 kvm_x86_ops->hwapic_irr_update(vcpu,
5728 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5729 update_cr8_intercept(vcpu);
5730 kvm_lapic_sync_to_vapic(vcpu);
5731 }
5732 }
5733
d8368af8
AK		 5734 r = kvm_mmu_reload(vcpu);
5735 if (unlikely(r)) {
d905c069 5736 goto cancel_injection;
d8368af8
AK		 5737 }
5738
b6c7a5dc
HB		 5739 preempt_disable();
5740
5741 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5742 if (vcpu->fpu_active)
5743 kvm_load_guest_fpu(vcpu);
2acf923e 5744 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5745
6b7e2d09
XG		 5746 vcpu->mode = IN_GUEST_MODE;
5747
5748 /* We should set ->mode before check ->requests,
5749 * see the comment in make_all_cpus_request.
5750 */
5751 smp_mb();
b6c7a5dc 5752
d94e1dc9 5753 local_irq_disable();
32f88400 5754
6b7e2d09 5755 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5756 || need_resched() || signal_pending(current)) {
6b7e2d09 5757 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5758 smp_wmb();
6c142801
AK		 5759 local_irq_enable();
5760 preempt_enable();
5761 r = 1;
d905c069 5762 goto cancel_injection;
6c142801
AK		 5763 }
5764
f656ce01 5765 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5766
d6185f20
NHE		 5767 if (req_immediate_exit)
5768 smp_send_reschedule(vcpu->cpu);
5769
b6c7a5dc
HB		 5770 kvm_guest_enter();
5771
42dbaa5a 5772 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5773 set_debugreg(0, 7);
5774 set_debugreg(vcpu->arch.eff_db[0], 0);
5775 set_debugreg(vcpu->arch.eff_db[1], 1);
5776 set_debugreg(vcpu->arch.eff_db[2], 2);
5777 set_debugreg(vcpu->arch.eff_db[3], 3);
5778 }
b6c7a5dc 5779
229456fc 5780 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5781 kvm_x86_ops->run(vcpu);
b6c7a5dc 5782
24f1e32c
FW		 5783 /*
5784 * If the guest has used debug registers, at least dr7
5785 * will be disabled while returning to the host.
5786 * If we don't have active breakpoints in the host, we don't
5787 * care about the messed up debug address registers. But if
5788 * we have some of them active, restore the old state.
5789 */
59d8eb53 5790 if (hw_breakpoint_active())
24f1e32c 5791 hw_breakpoint_restore();
42dbaa5a 5792
886b470c
MT		 5793 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5794 native_read_tsc());
1d5f066e 5795
6b7e2d09 5796 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5797 smp_wmb();
b6c7a5dc
HB		 5798 local_irq_enable();
5799
5800 ++vcpu->stat.exits;
5801
5802 /*
5803 * We must have an instruction between local_irq_enable() and
5804 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5805 * the interrupt shadow. The stat.exits increment will do nicely.
5806 * But we need to prevent reordering, hence this barrier():
5807 */
5808 barrier();
5809
5810 kvm_guest_exit();
5811
5812 preempt_enable();
5813
f656ce01 5814 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5815
b6c7a5dc
HB		 5816 /*
5817 * Profile KVM exit RIPs:
5818 */
5819 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5820 unsigned long rip = kvm_rip_read(vcpu);
5821 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5822 }
5823
cc578287
ZA		 5824 if (unlikely(vcpu->arch.tsc_always_catchup))
5825 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5826
5cfb1d5a
MT		 5827 if (vcpu->arch.apic_attention)
5828 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5829
851ba692 5830 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5831 return r;
5832
5833cancel_injection:
5834 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5835 if (unlikely(vcpu->arch.apic_attention))
5836 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5837out:
5838 return r;
5839}
b6c7a5dc 5840
09cec754 5841
851ba692 5842static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5843{
5844 int r;
f656ce01 5845 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5846
5847 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5848 pr_debug("vcpu %d received sipi with vector # %x\n",
5849 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5850 kvm_lapic_reset(vcpu);
8b6e4547 5851 r = kvm_vcpu_reset(vcpu);
d7690175
MT		 5852 if (r)
5853 return r;
5854 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5855 }
5856
f656ce01 5857 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 5858 r = vapic_enter(vcpu);
5859 if (r) {
5860 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5861 return r;
5862 }
d7690175
MT		 5863
5864 r = 1;
5865 while (r > 0) {
af585b92
GN		 5866 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5867 !vcpu->arch.apf.halted)
851ba692 5868 r = vcpu_enter_guest(vcpu);
d7690175 5869 else {
f656ce01 5870 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5871 kvm_vcpu_block(vcpu);
f656ce01 5872 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5873 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5874 {
5875 switch(vcpu->arch.mp_state) {
5876 case KVM_MP_STATE_HALTED:
d7690175 5877 vcpu->arch.mp_state =
09cec754
GN		 5878 KVM_MP_STATE_RUNNABLE;
5879 case KVM_MP_STATE_RUNNABLE:
af585b92 5880 vcpu->arch.apf.halted = false;
09cec754
GN		 5881 break;
5882 case KVM_MP_STATE_SIPI_RECEIVED:
5883 default:
5884 r = -EINTR;
5885 break;
5886 }
5887 }
d7690175
MT		 5888 }
5889
09cec754
GN		 5890 if (r <= 0)
5891 break;
5892
5893 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5894 if (kvm_cpu_has_pending_timer(vcpu))
5895 kvm_inject_pending_timer_irqs(vcpu);
5896
851ba692 5897 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5898 r = -EINTR;
851ba692 5899 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5900 ++vcpu->stat.request_irq_exits;
5901 }
af585b92
GN		 5902
5903 kvm_check_async_pf_completion(vcpu);
5904
09cec754
GN		 5905 if (signal_pending(current)) {
5906 r = -EINTR;
851ba692 5907 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5908 ++vcpu->stat.signal_exits;
5909 }
5910 if (need_resched()) {
f656ce01 5911 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5912 kvm_resched(vcpu);
f656ce01 5913 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5914 }
b6c7a5dc
HB		 5915 }
5916
f656ce01 5917 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5918
b93463aa
AK		 5919 vapic_exit(vcpu);
5920
b6c7a5dc
HB		 5921 return r;
5922}
5923
716d51ab
GN		 5924static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5925{
5926 int r;
5927 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5928 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5929 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5930 if (r != EMULATE_DONE)
5931 return 0;
5932 return 1;
5933}
5934
5935static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5936{
5937 BUG_ON(!vcpu->arch.pio.count);
5938
5939 return complete_emulated_io(vcpu);
5940}
5941
f78146b0
AK		 5942/*
5943 * Implements the following, as a state machine:
5944 *
5945 * read:
5946 * for each fragment
87da7e66
XG		 5947 * for each mmio piece in the fragment
5948 * write gpa, len
5949 * exit
5950 * copy data
f78146b0
AK		 5951 * execute insn
5952 *
5953 * write:
5954 * for each fragment
87da7e66
XG		 5955 * for each mmio piece in the fragment
5956 * write gpa, len
5957 * copy data
5958 * exit
f78146b0 5959 */
716d51ab 5960static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 5961{
5962 struct kvm_run *run = vcpu->run;
f78146b0 5963 struct kvm_mmio_fragment *frag;
87da7e66 5964 unsigned len;
5287f194 5965
716d51ab 5966 BUG_ON(!vcpu->mmio_needed);
5287f194 5967
716d51ab 5968 /* Complete previous fragment */
87da7e66
XG		 5969 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
5970 len = min(8u, frag->len);
716d51ab 5971 if (!vcpu->mmio_is_write)
87da7e66
XG		 5972 memcpy(frag->data, run->mmio.data, len);
5973
5974 if (frag->len <= 8) {
5975 /* Switch to the next fragment. */
5976 frag++;
5977 vcpu->mmio_cur_fragment++;
5978 } else {
5979 /* Go forward to the next mmio piece. */
5980 frag->data += len;
5981 frag->gpa += len;
5982 frag->len -= len;
5983 }
5984
716d51ab
GN		 5985 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5986 vcpu->mmio_needed = 0;
cef4dea0 5987 if (vcpu->mmio_is_write)
716d51ab
GN		 5988 return 1;
5989 vcpu->mmio_read_completed = 1;
5990 return complete_emulated_io(vcpu);
5991 }
87da7e66 5992
716d51ab
GN		 5993 run->exit_reason = KVM_EXIT_MMIO;
5994 run->mmio.phys_addr = frag->gpa;
5995 if (vcpu->mmio_is_write)
87da7e66
XG		 5996 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
5997 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 5998 run->mmio.is_write = vcpu->mmio_is_write;
5999 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6000 return 0;
5287f194
AK		 6001}
6002
716d51ab 6003
b6c7a5dc
HB		 6004int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6005{
6006 int r;
6007 sigset_t sigsaved;
6008
e5c30142
AK		 6009 if (!tsk_used_math(current) && init_fpu(current))
6010 return -ENOMEM;
6011
ac9f6dc0
AK		 6012 if (vcpu->sigset_active)
6013 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6014
a4535290 6015 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6016 kvm_vcpu_block(vcpu);
d7690175 6017 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6018 r = -EAGAIN;
6019 goto out;
b6c7a5dc
HB		 6020 }
6021
b6c7a5dc 6022 /* re-sync apic's tpr */
eea1cff9
AP		 6023 if (!irqchip_in_kernel(vcpu->kvm)) {
6024 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6025 r = -EINVAL;
6026 goto out;
6027 }
6028 }
b6c7a5dc 6029
716d51ab
GN		 6030 if (unlikely(vcpu->arch.complete_userspace_io)) {
6031 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6032 vcpu->arch.complete_userspace_io = NULL;
6033 r = cui(vcpu);
6034 if (r <= 0)
6035 goto out;
6036 } else
6037 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6038
851ba692 6039 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6040
6041out:
f1d86e46 6042 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6043 if (vcpu->sigset_active)
6044 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6045
b6c7a5dc
HB		 6046 return r;
6047}
6048
6049int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6050{
7ae441ea
GN		 6051 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6052 /*
6053 * We are here if userspace calls get_regs() in the middle of
6054 * instruction emulation. Registers state needs to be copied
4a969980 6055 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6056 * that usually, but some bad designed PV devices (vmware
6057 * backdoor interface) need this to work
6058 */
dd856efa 6059 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6060 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6061 }
5fdbf976
MT		 6062 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6063 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6064 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6065 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6066 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6067 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6068 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6069 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6070#ifdef CONFIG_X86_64
5fdbf976
MT		 6071 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6072 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6073 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6074 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6075 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6076 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6077 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6078 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6079#endif
6080
5fdbf976 6081 regs->rip = kvm_rip_read(vcpu);
91586a3b 6082 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6083
b6c7a5dc
HB		 6084 return 0;
6085}
6086
6087int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6088{
7ae441ea
GN		 6089 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6090 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6091
5fdbf976
MT		 6092 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6093 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6094 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6095 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6096 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6097 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6098 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6099 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6100#ifdef CONFIG_X86_64
5fdbf976
MT		 6101 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6102 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6103 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6104 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6105 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6106 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6107 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6108 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6109#endif
6110
5fdbf976 6111 kvm_rip_write(vcpu, regs->rip);
91586a3b 6112 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6113
b4f14abd
JK		 6114 vcpu->arch.exception.pending = false;
6115
3842d135
AK		 6116 kvm_make_request(KVM_REQ_EVENT, vcpu);
6117
b6c7a5dc
HB		 6118 return 0;
6119}
6120
b6c7a5dc
HB		 6121void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6122{
6123 struct kvm_segment cs;
6124
3e6e0aab 6125 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6126 *db = cs.db;
6127 *l = cs.l;
6128}
6129EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6130
6131int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6132 struct kvm_sregs *sregs)
6133{
89a27f4d 6134 struct desc_ptr dt;
b6c7a5dc 6135
3e6e0aab
GT		 6136 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6137 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6138 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6139 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6140 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6141 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6142
3e6e0aab
GT		 6143 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6144 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6145
6146 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6147 sregs->idt.limit = dt.size;
6148 sregs->idt.base = dt.address;
b6c7a5dc 6149 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6150 sregs->gdt.limit = dt.size;
6151 sregs->gdt.base = dt.address;
b6c7a5dc 6152
4d4ec087 6153 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6154 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6155 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6156 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6157 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6158 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6159 sregs->apic_base = kvm_get_apic_base(vcpu);
6160
923c61bb 6161 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6162
36752c9b 6163 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6164 set_bit(vcpu->arch.interrupt.nr,
6165 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6166
b6c7a5dc
HB		 6167 return 0;
6168}
6169
62d9f0db
MT		 6170int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6171 struct kvm_mp_state *mp_state)
6172{
62d9f0db 6173 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6174 return 0;
6175}
6176
6177int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6178 struct kvm_mp_state *mp_state)
6179{
62d9f0db 6180 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6181 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6182 return 0;
6183}
6184
7f3d35fd
KW		 6185int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6186 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6187{
9d74191a 6188 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6189 int ret;
e01c2426 6190
8ec4722d 6191 init_emulate_ctxt(vcpu);
c697518a 6192
7f3d35fd 6193 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6194 has_error_code, error_code);
c697518a 6195
c697518a 6196 if (ret)
19d04437 6197 return EMULATE_FAIL;
37817f29 6198
9d74191a
TY		 6199 kvm_rip_write(vcpu, ctxt->eip);
6200 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6201 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6202 return EMULATE_DONE;
37817f29
IE		 6203}
6204EXPORT_SYMBOL_GPL(kvm_task_switch);
6205
b6c7a5dc
HB		 6206int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6207 struct kvm_sregs *sregs)
6208{
6209 int mmu_reset_needed = 0;
63f42e02 6210 int pending_vec, max_bits, idx;
89a27f4d 6211 struct desc_ptr dt;
b6c7a5dc 6212
6d1068b3
PM		 6213 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6214 return -EINVAL;
6215
89a27f4d
GN		 6216 dt.size = sregs->idt.limit;
6217 dt.address = sregs->idt.base;
b6c7a5dc 6218 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6219 dt.size = sregs->gdt.limit;
6220 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6221 kvm_x86_ops->set_gdt(vcpu, &dt);
6222
ad312c7c 6223 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6224 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6225 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6226 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6227
2d3ad1f4 6228 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6229
f6801dff 6230 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6231 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6232 kvm_set_apic_base(vcpu, sregs->apic_base);
6233
4d4ec087 6234 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6235 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6236 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6237
fc78f519 6238 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6239 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6240 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6241 kvm_update_cpuid(vcpu);
63f42e02
XG		 6242
6243 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6244 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6245 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6246 mmu_reset_needed = 1;
6247 }
63f42e02 6248 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6249
6250 if (mmu_reset_needed)
6251 kvm_mmu_reset_context(vcpu);
6252
a50abc3b 6253 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6254 pending_vec = find_first_bit(
6255 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6256 if (pending_vec < max_bits) {
66fd3f7f 6257 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6258 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6259 }
6260
3e6e0aab
GT		 6261 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6262 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6263 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6264 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6265 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6266 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6267
3e6e0aab
GT		 6268 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6269 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6270
5f0269f5
ME		 6271 update_cr8_intercept(vcpu);
6272
9c3e4aab 6273 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6274 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6275 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6276 !is_protmode(vcpu))
9c3e4aab
MT		 6277 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6278
3842d135
AK		 6279 kvm_make_request(KVM_REQ_EVENT, vcpu);
6280
b6c7a5dc
HB		 6281 return 0;
6282}
6283
d0bfb940
JK		 6284int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6285 struct kvm_guest_debug *dbg)
b6c7a5dc 6286{
355be0b9 6287 unsigned long rflags;
ae675ef0 6288 int i, r;
b6c7a5dc 6289
4f926bf2
JK		 6290 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6291 r = -EBUSY;
6292 if (vcpu->arch.exception.pending)
2122ff5e 6293 goto out;
4f926bf2
JK		 6294 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6295 kvm_queue_exception(vcpu, DB_VECTOR);
6296 else
6297 kvm_queue_exception(vcpu, BP_VECTOR);
6298 }
6299
91586a3b
JK		 6300 /*
6301 * Read rflags as long as potentially injected trace flags are still
6302 * filtered out.
6303 */
6304 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6305
6306 vcpu->guest_debug = dbg->control;
6307 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6308 vcpu->guest_debug = 0;
6309
6310 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6311 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6312 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6313 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6314 } else {
6315 for (i = 0; i < KVM_NR_DB_REGS; i++)
6316 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6317 }
c8639010 6318 kvm_update_dr7(vcpu);
ae675ef0 6319
f92653ee
JK		 6320 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6321 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6322 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6323
91586a3b
JK		 6324 /*
6325 * Trigger an rflags update that will inject or remove the trace
6326 * flags.
6327 */
6328 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6329
c8639010 6330 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6331
4f926bf2 6332 r = 0;
d0bfb940 6333
2122ff5e 6334out:
b6c7a5dc
HB		 6335
6336 return r;
6337}
6338
8b006791
ZX		 6339/*
6340 * Translate a guest virtual address to a guest physical address.
6341 */
6342int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6343 struct kvm_translation *tr)
6344{
6345 unsigned long vaddr = tr->linear_address;
6346 gpa_t gpa;
f656ce01 6347 int idx;
8b006791 6348
f656ce01 6349 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6350 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6351 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6352 tr->physical_address = gpa;
6353 tr->valid = gpa != UNMAPPED_GVA;
6354 tr->writeable = 1;
6355 tr->usermode = 0;
8b006791
ZX		 6356
6357 return 0;
6358}
6359
d0752060
HB		 6360int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6361{
98918833
SY		 6362 struct i387_fxsave_struct *fxsave =
6363 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6364
d0752060
HB		 6365 memcpy(fpu->fpr, fxsave->st_space, 128);
6366 fpu->fcw = fxsave->cwd;
6367 fpu->fsw = fxsave->swd;
6368 fpu->ftwx = fxsave->twd;
6369 fpu->last_opcode = fxsave->fop;
6370 fpu->last_ip = fxsave->rip;
6371 fpu->last_dp = fxsave->rdp;
6372 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6373
d0752060
HB		 6374 return 0;
6375}
6376
6377int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6378{
98918833
SY		 6379 struct i387_fxsave_struct *fxsave =
6380 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6381
d0752060
HB		 6382 memcpy(fxsave->st_space, fpu->fpr, 128);
6383 fxsave->cwd = fpu->fcw;
6384 fxsave->swd = fpu->fsw;
6385 fxsave->twd = fpu->ftwx;
6386 fxsave->fop = fpu->last_opcode;
6387 fxsave->rip = fpu->last_ip;
6388 fxsave->rdp = fpu->last_dp;
6389 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6390
d0752060
HB		 6391 return 0;
6392}
6393
10ab25cd 6394int fx_init(struct kvm_vcpu *vcpu)
d0752060 6395{
10ab25cd
JK		 6396 int err;
6397
6398 err = fpu_alloc(&vcpu->arch.guest_fpu);
6399 if (err)
6400 return err;
6401
98918833 6402 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6403
2acf923e
DC		 6404 /*
6405 * Ensure guest xcr0 is valid for loading
6406 */
6407 vcpu->arch.xcr0 = XSTATE_FP;
6408
ad312c7c 6409 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6410
6411 return 0;
d0752060
HB		 6412}
6413EXPORT_SYMBOL_GPL(fx_init);
6414
98918833
SY		 6415static void fx_free(struct kvm_vcpu *vcpu)
6416{
6417 fpu_free(&vcpu->arch.guest_fpu);
6418}
6419
d0752060
HB		 6420void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6421{
2608d7a1 6422 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6423 return;
6424
2acf923e
DC		 6425 /*
6426 * Restore all possible states in the guest,
6427 * and assume host would use all available bits.
6428 * Guest xcr0 would be loaded later.
6429 */
6430 kvm_put_guest_xcr0(vcpu);
d0752060 6431 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6432 __kernel_fpu_begin();
98918833 6433 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6434 trace_kvm_fpu(1);
d0752060 6435}
d0752060
HB		 6436
6437void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6438{
2acf923e
DC		 6439 kvm_put_guest_xcr0(vcpu);
6440
d0752060
HB		 6441 if (!vcpu->guest_fpu_loaded)
6442 return;
6443
6444 vcpu->guest_fpu_loaded = 0;
98918833 6445 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6446 __kernel_fpu_end();
f096ed85 6447 ++vcpu->stat.fpu_reload;
a8eeb04a 6448 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6449 trace_kvm_fpu(0);
d0752060 6450}
e9b11c17
ZX		 6451
6452void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6453{
12f9a48f 6454 kvmclock_reset(vcpu);
7f1ea208 6455
f5f48ee1 6456 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6457 fx_free(vcpu);
e9b11c17
ZX		 6458 kvm_x86_ops->vcpu_free(vcpu);
6459}
6460
6461struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6462 unsigned int id)
6463{
6755bae8
ZA		 6464 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6465 printk_once(KERN_WARNING
6466 "kvm: SMP vm created on host with unstable TSC; "
6467 "guest TSC will not be reliable\n");
26e5215f
AK		 6468 return kvm_x86_ops->vcpu_create(kvm, id);
6469}
e9b11c17 6470
26e5215f
AK		 6471int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6472{
6473 int r;
e9b11c17 6474
0bed3b56 6475 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6476 r = vcpu_load(vcpu);
6477 if (r)
6478 return r;
8b6e4547 6479 r = kvm_vcpu_reset(vcpu);
e9b11c17
ZX		 6480 if (r == 0)
6481 r = kvm_mmu_setup(vcpu);
6482 vcpu_put(vcpu);
e9b11c17 6483
26e5215f 6484 return r;
e9b11c17
ZX		 6485}
6486
42897d86
MT		 6487int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6488{
6489 int r;
8fe8ab46 6490 struct msr_data msr;
42897d86
MT		 6491
6492 r = vcpu_load(vcpu);
6493 if (r)
6494 return r;
8fe8ab46
WA		 6495 msr.data = 0x0;
6496 msr.index = MSR_IA32_TSC;
6497 msr.host_initiated = true;
6498 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6499 vcpu_put(vcpu);
6500
6501 return r;
6502}
6503
d40ccc62 6504void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6505{
9fc77441 6506 int r;
344d9588
GN		 6507 vcpu->arch.apf.msr_val = 0;
6508
9fc77441
MT		 6509 r = vcpu_load(vcpu);
6510 BUG_ON(r);
e9b11c17
ZX		 6511 kvm_mmu_unload(vcpu);
6512 vcpu_put(vcpu);
6513
98918833 6514 fx_free(vcpu);
e9b11c17
ZX		 6515 kvm_x86_ops->vcpu_free(vcpu);
6516}
6517
8b6e4547 6518static int kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6519{
7460fb4a
AK		 6520 atomic_set(&vcpu->arch.nmi_queued, 0);
6521 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6522 vcpu->arch.nmi_injected = false;
6523
42dbaa5a
JK		 6524 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6525 vcpu->arch.dr6 = DR6_FIXED_1;
6526 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6527 kvm_update_dr7(vcpu);
42dbaa5a 6528
3842d135 6529 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6530 vcpu->arch.apf.msr_val = 0;
c9aaa895 6531 vcpu->arch.st.msr_val = 0;
3842d135 6532
12f9a48f
GC		 6533 kvmclock_reset(vcpu);
6534
af585b92
GN		 6535 kvm_clear_async_pf_completion_queue(vcpu);
6536 kvm_async_pf_hash_reset(vcpu);
6537 vcpu->arch.apf.halted = false;
3842d135 6538
f5132b01
GN		 6539 kvm_pmu_reset(vcpu);
6540
66f7b72e
JS		 6541 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6542 vcpu->arch.regs_avail = ~0;
6543 vcpu->arch.regs_dirty = ~0;
6544
e9b11c17
ZX		 6545 return kvm_x86_ops->vcpu_reset(vcpu);
6546}
6547
10474ae8 6548int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6549{
ca84d1a2
ZA		 6550 struct kvm *kvm;
6551 struct kvm_vcpu *vcpu;
6552 int i;
0dd6a6ed
ZA		 6553 int ret;
6554 u64 local_tsc;
6555 u64 max_tsc = 0;
6556 bool stable, backwards_tsc = false;
18863bdd
AK		 6557
6558 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6559 ret = kvm_x86_ops->hardware_enable(garbage);
6560 if (ret != 0)
6561 return ret;
6562
6563 local_tsc = native_read_tsc();
6564 stable = !check_tsc_unstable();
6565 list_for_each_entry(kvm, &vm_list, vm_list) {
6566 kvm_for_each_vcpu(i, vcpu, kvm) {
6567 if (!stable && vcpu->cpu == smp_processor_id())
6568 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6569 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6570 backwards_tsc = true;
6571 if (vcpu->arch.last_host_tsc > max_tsc)
6572 max_tsc = vcpu->arch.last_host_tsc;
6573 }
6574 }
6575 }
6576
6577 /*
6578 * Sometimes, even reliable TSCs go backwards. This happens on
6579 * platforms that reset TSC during suspend or hibernate actions, but
6580 * maintain synchronization. We must compensate. Fortunately, we can
6581 * detect that condition here, which happens early in CPU bringup,
6582 * before any KVM threads can be running. Unfortunately, we can't
6583 * bring the TSCs fully up to date with real time, as we aren't yet far
6584 * enough into CPU bringup that we know how much real time has actually
6585 * elapsed; our helper function, get_kernel_ns() will be using boot
6586 * variables that haven't been updated yet.
6587 *
6588 * So we simply find the maximum observed TSC above, then record the
6589 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6590 * the adjustment will be applied. Note that we accumulate
6591 * adjustments, in case multiple suspend cycles happen before some VCPU
6592 * gets a chance to run again. In the event that no KVM threads get a
6593 * chance to run, we will miss the entire elapsed period, as we'll have
6594 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6595 * loose cycle time. This isn't too big a deal, since the loss will be
6596 * uniform across all VCPUs (not to mention the scenario is extremely
6597 * unlikely). It is possible that a second hibernate recovery happens
6598 * much faster than a first, causing the observed TSC here to be
6599 * smaller; this would require additional padding adjustment, which is
6600 * why we set last_host_tsc to the local tsc observed here.
6601 *
6602 * N.B. - this code below runs only on platforms with reliable TSC,
6603 * as that is the only way backwards_tsc is set above. Also note
6604 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6605 * have the same delta_cyc adjustment applied if backwards_tsc
6606 * is detected. Note further, this adjustment is only done once,
6607 * as we reset last_host_tsc on all VCPUs to stop this from being
6608 * called multiple times (one for each physical CPU bringup).
6609 *
4a969980 6610 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6611 * will be compensated by the logic in vcpu_load, which sets the TSC to
6612 * catchup mode. This will catchup all VCPUs to real time, but cannot
6613 * guarantee that they stay in perfect synchronization.
6614 */
6615 if (backwards_tsc) {
6616 u64 delta_cyc = max_tsc - local_tsc;
6617 list_for_each_entry(kvm, &vm_list, vm_list) {
6618 kvm_for_each_vcpu(i, vcpu, kvm) {
6619 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6620 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6621 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6622 &vcpu->requests);
0dd6a6ed
ZA		 6623 }
6624
6625 /*
6626 * We have to disable TSC offset matching.. if you were
6627 * booting a VM while issuing an S4 host suspend....
6628 * you may have some problem. Solving this issue is
6629 * left as an exercise to the reader.
6630 */
6631 kvm->arch.last_tsc_nsec = 0;
6632 kvm->arch.last_tsc_write = 0;
6633 }
6634
6635 }
6636 return 0;
e9b11c17
ZX		 6637}
6638
6639void kvm_arch_hardware_disable(void *garbage)
6640{
6641 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6642 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6643}
6644
6645int kvm_arch_hardware_setup(void)
6646{
6647 return kvm_x86_ops->hardware_setup();
6648}
6649
6650void kvm_arch_hardware_unsetup(void)
6651{
6652 kvm_x86_ops->hardware_unsetup();
6653}
6654
6655void kvm_arch_check_processor_compat(void *rtn)
6656{
6657 kvm_x86_ops->check_processor_compatibility(rtn);
6658}
6659
3e515705
AK		 6660bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6661{
6662 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6663}
6664
54e9818f
GN		 6665struct static_key kvm_no_apic_vcpu __read_mostly;
6666
e9b11c17
ZX		 6667int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6668{
6669 struct page *page;
6670 struct kvm *kvm;
6671 int r;
6672
6673 BUG_ON(vcpu->kvm == NULL);
6674 kvm = vcpu->kvm;
6675
9aabc88f 6676 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6677 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6678 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6679 else
a4535290 6680 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6681
6682 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6683 if (!page) {
6684 r = -ENOMEM;
6685 goto fail;
6686 }
ad312c7c 6687 vcpu->arch.pio_data = page_address(page);
e9b11c17 6688
cc578287 6689 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6690
e9b11c17
ZX		 6691 r = kvm_mmu_create(vcpu);
6692 if (r < 0)
6693 goto fail_free_pio_data;
6694
6695 if (irqchip_in_kernel(kvm)) {
6696 r = kvm_create_lapic(vcpu);
6697 if (r < 0)
6698 goto fail_mmu_destroy;
54e9818f
GN		 6699 } else
6700 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6701
890ca9ae
HY		 6702 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6703 GFP_KERNEL);
6704 if (!vcpu->arch.mce_banks) {
6705 r = -ENOMEM;
443c39bc 6706 goto fail_free_lapic;
890ca9ae
HY		 6707 }
6708 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6709
f5f48ee1
SY		 6710 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6711 goto fail_free_mce_banks;
6712
66f7b72e
JS		 6713 r = fx_init(vcpu);
6714 if (r)
6715 goto fail_free_wbinvd_dirty_mask;
6716
ba904635 6717 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6718 vcpu->arch.pv_time_enabled = false;
af585b92 6719 kvm_async_pf_hash_reset(vcpu);
f5132b01 6720 kvm_pmu_init(vcpu);
af585b92 6721
e9b11c17 6722 return 0;
66f7b72e
JS		 6723fail_free_wbinvd_dirty_mask:
6724 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6725fail_free_mce_banks:
6726 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6727fail_free_lapic:
6728 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6729fail_mmu_destroy:
6730 kvm_mmu_destroy(vcpu);
6731fail_free_pio_data:
ad312c7c 6732 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6733fail:
6734 return r;
6735}
6736
6737void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6738{
f656ce01
MT		 6739 int idx;
6740
f5132b01 6741 kvm_pmu_destroy(vcpu);
36cb93fd 6742 kfree(vcpu->arch.mce_banks);
e9b11c17 6743 kvm_free_lapic(vcpu);
f656ce01 6744 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6745 kvm_mmu_destroy(vcpu);
f656ce01 6746 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6747 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6748 if (!irqchip_in_kernel(vcpu->kvm))
6749 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6750}
d19a9cd2 6751
e08b9637 6752int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6753{
e08b9637
CO		 6754 if (type)
6755 return -EINVAL;
6756
f05e70ac 6757 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6758 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6759
5550af4d
SY		 6760 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6761 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6762 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6763 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6764 &kvm->arch.irq_sources_bitmap);
5550af4d 6765
038f8c11 6766 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6767 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 6768 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6769
6770 pvclock_update_vm_gtod_copy(kvm);
53f658b3 6771
d89f5eff 6772 return 0;
d19a9cd2
ZX		 6773}
6774
6775static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6776{
9fc77441
MT		 6777 int r;
6778 r = vcpu_load(vcpu);
6779 BUG_ON(r);
d19a9cd2
ZX		 6780 kvm_mmu_unload(vcpu);
6781 vcpu_put(vcpu);
6782}
6783
6784static void kvm_free_vcpus(struct kvm *kvm)
6785{
6786 unsigned int i;
988a2cae 6787 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6788
6789 /*
6790 * Unpin any mmu pages first.
6791 */
af585b92
GN		 6792 kvm_for_each_vcpu(i, vcpu, kvm) {
6793 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6794 kvm_unload_vcpu_mmu(vcpu);
af585b92 6795 }
988a2cae
GN		 6796 kvm_for_each_vcpu(i, vcpu, kvm)
6797 kvm_arch_vcpu_free(vcpu);
6798
6799 mutex_lock(&kvm->lock);
6800 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6801 kvm->vcpus[i] = NULL;
d19a9cd2 6802
988a2cae
GN		 6803 atomic_set(&kvm->online_vcpus, 0);
6804 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6805}
6806
ad8ba2cd
SY		 6807void kvm_arch_sync_events(struct kvm *kvm)
6808{
ba4cef31 6809 kvm_free_all_assigned_devices(kvm);
aea924f6 6810 kvm_free_pit(kvm);
ad8ba2cd
SY		 6811}
6812
d19a9cd2
ZX		 6813void kvm_arch_destroy_vm(struct kvm *kvm)
6814{
6eb55818 6815 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6816 kfree(kvm->arch.vpic);
6817 kfree(kvm->arch.vioapic);
d19a9cd2 6818 kvm_free_vcpus(kvm);
3d45830c
AK		 6819 if (kvm->arch.apic_access_page)
6820 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6821 if (kvm->arch.ept_identity_pagetable)
6822 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 6823 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 6824}
0de10343 6825
db3fe4eb
TY		 6826void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6827 struct kvm_memory_slot *dont)
6828{
6829 int i;
6830
d89cc617
TY		 6831 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6832 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6833 kvm_kvfree(free->arch.rmap[i]);
6834 free->arch.rmap[i] = NULL;
77d11309 6835 }
d89cc617
TY		 6836 if (i == 0)
6837 continue;
6838
6839 if (!dont || free->arch.lpage_info[i - 1] !=
6840 dont->arch.lpage_info[i - 1]) {
6841 kvm_kvfree(free->arch.lpage_info[i - 1]);
6842 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6843 }
6844 }
6845}
6846
6847int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6848{
6849 int i;
6850
d89cc617 6851 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6852 unsigned long ugfn;
6853 int lpages;
d89cc617 6854 int level = i + 1;
db3fe4eb
TY		 6855
6856 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6857 slot->base_gfn, level) + 1;
6858
d89cc617
TY		 6859 slot->arch.rmap[i] =
6860 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6861 if (!slot->arch.rmap[i])
77d11309 6862 goto out_free;
d89cc617
TY		 6863 if (i == 0)
6864 continue;
77d11309 6865
d89cc617
TY		 6866 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6867 sizeof(*slot->arch.lpage_info[i - 1]));
6868 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6869 goto out_free;
6870
6871 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6872 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6873 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6874 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6875 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6876 /*
6877 * If the gfn and userspace address are not aligned wrt each
6878 * other, or if explicitly asked to, disable large page
6879 * support for this slot
6880 */
6881 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6882 !kvm_largepages_enabled()) {
6883 unsigned long j;
6884
6885 for (j = 0; j < lpages; ++j)
d89cc617 6886 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6887 }
6888 }
6889
6890 return 0;
6891
6892out_free:
d89cc617
TY		 6893 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6894 kvm_kvfree(slot->arch.rmap[i]);
6895 slot->arch.rmap[i] = NULL;
6896 if (i == 0)
6897 continue;
6898
6899 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6900 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6901 }
6902 return -ENOMEM;
6903}
6904
f7784b8e
MT		 6905int kvm_arch_prepare_memory_region(struct kvm *kvm,
6906 struct kvm_memory_slot *memslot,
0de10343 6907 struct kvm_memory_slot old,
f7784b8e 6908 struct kvm_userspace_memory_region *mem,
f82a8cfe 6909 bool user_alloc)
0de10343 6910{
f7784b8e 6911 int npages = memslot->npages;
7ac77099 6912
7a905b14
TY		 6913 /*
6914 * Only private memory slots need to be mapped here since
6915 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 6916 */
7a905b14
TY		 6917 if ((memslot->id >= KVM_USER_MEM_SLOTS) && npages && !old.npages) {
6918 unsigned long userspace_addr;
604b38ac 6919
7a905b14
TY		 6920 /*
6921 * MAP_SHARED to prevent internal slot pages from being moved
6922 * by fork()/COW.
6923 */
6924 userspace_addr = vm_mmap(NULL, 0, npages * PAGE_SIZE,
6925 PROT_READ | PROT_WRITE,
6926 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 6927
7a905b14
TY		 6928 if (IS_ERR((void *)userspace_addr))
6929 return PTR_ERR((void *)userspace_addr);
604b38ac 6930
7a905b14 6931 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6932 }
6933
f7784b8e
MT		 6934 return 0;
6935}
6936
6937void kvm_arch_commit_memory_region(struct kvm *kvm,
6938 struct kvm_userspace_memory_region *mem,
6939 struct kvm_memory_slot old,
f82a8cfe 6940 bool user_alloc)
f7784b8e
MT		 6941{
6942
48c0e4e9 6943 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e 6944
7a905b14 6945 if ((mem->slot >= KVM_USER_MEM_SLOTS) && old.npages && !npages) {
f7784b8e
MT		 6946 int ret;
6947
bfce281c 6948 ret = vm_munmap(old.userspace_addr,
f7784b8e 6949 old.npages * PAGE_SIZE);
f7784b8e
MT		 6950 if (ret < 0)
6951 printk(KERN_WARNING
6952 "kvm_vm_ioctl_set_memory_region: "
6953 "failed to munmap memory\n");
6954 }
6955
48c0e4e9
XG		 6956 if (!kvm->arch.n_requested_mmu_pages)
6957 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6958
48c0e4e9 6959 if (nr_mmu_pages)
0de10343 6960 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 6961 /*
6962 * Write protect all pages for dirty logging.
6963 * Existing largepage mappings are destroyed here and new ones will
6964 * not be created until the end of the logging.
6965 */
9d1beefb 6966 if (npages && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 6967 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
3b4dc3a0
MT		 6968 /*
6969 * If memory slot is created, or moved, we need to clear all
6970 * mmio sptes.
6971 */
6972 if (npages && old.base_gfn != mem->guest_phys_addr >> PAGE_SHIFT) {
6973 kvm_mmu_zap_all(kvm);
6974 kvm_reload_remote_mmus(kvm);
6975 }
0de10343 6976}
1d737c8a 6977
2df72e9b 6978void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f
MT		 6979{
6980 kvm_mmu_zap_all(kvm);
8986ecc0 6981 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6982}
6983
2df72e9b
MT		 6984void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
6985 struct kvm_memory_slot *slot)
6986{
6987 kvm_arch_flush_shadow_all(kvm);
6988}
6989
1d737c8a
ZX		 6990int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6991{
af585b92
GN		 6992 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6993 !vcpu->arch.apf.halted)
6994 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6995 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6996 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6997 (kvm_arch_interrupt_allowed(vcpu) &&
6998 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6999}
5736199a 7000
b6d33834 7001int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7002{
b6d33834 7003 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7004}
78646121
GN		 7005
7006int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7007{
7008 return kvm_x86_ops->interrupt_allowed(vcpu);
7009}
229456fc 7010
f92653ee
JK		 7011bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7012{
7013 unsigned long current_rip = kvm_rip_read(vcpu) +
7014 get_segment_base(vcpu, VCPU_SREG_CS);
7015
7016 return current_rip == linear_rip;
7017}
7018EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7019
94fe45da
JK		 7020unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7021{
7022 unsigned long rflags;
7023
7024 rflags = kvm_x86_ops->get_rflags(vcpu);
7025 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7026 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7027 return rflags;
7028}
7029EXPORT_SYMBOL_GPL(kvm_get_rflags);
7030
7031void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7032{
7033 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7034 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7035 rflags |= X86_EFLAGS_TF;
94fe45da 7036 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7037 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7038}
7039EXPORT_SYMBOL_GPL(kvm_set_rflags);
7040
56028d08
GN		 7041void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7042{
7043 int r;
7044
fb67e14f 7045 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 7046 is_error_page(work->page))
56028d08
GN		 7047 return;
7048
7049 r = kvm_mmu_reload(vcpu);
7050 if (unlikely(r))
7051 return;
7052
fb67e14f
XG		 7053 if (!vcpu->arch.mmu.direct_map &&
7054 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7055 return;
7056
56028d08
GN		 7057 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7058}
7059
af585b92
GN		 7060static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7061{
7062 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7063}
7064
7065static inline u32 kvm_async_pf_next_probe(u32 key)
7066{
7067 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7068}
7069
7070static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7071{
7072 u32 key = kvm_async_pf_hash_fn(gfn);
7073
7074 while (vcpu->arch.apf.gfns[key] != ~0)
7075 key = kvm_async_pf_next_probe(key);
7076
7077 vcpu->arch.apf.gfns[key] = gfn;
7078}
7079
7080static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7081{
7082 int i;
7083 u32 key = kvm_async_pf_hash_fn(gfn);
7084
7085 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7086 (vcpu->arch.apf.gfns[key] != gfn &&
7087 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7088 key = kvm_async_pf_next_probe(key);
7089
7090 return key;
7091}
7092
7093bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7094{
7095 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7096}
7097
7098static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7099{
7100 u32 i, j, k;
7101
7102 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7103 while (true) {
7104 vcpu->arch.apf.gfns[i] = ~0;
7105 do {
7106 j = kvm_async_pf_next_probe(j);
7107 if (vcpu->arch.apf.gfns[j] == ~0)
7108 return;
7109 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7110 /*
7111 * k lies cyclically in ]i,j]
7112 * | i.k.j |
7113 * |....j i.k.| or |.k..j i...|
7114 */
7115 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7116 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7117 i = j;
7118 }
7119}
7120
7c90705b
GN		 7121static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7122{
7123
7124 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7125 sizeof(val));
7126}
7127
af585b92
GN		 7128void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7129 struct kvm_async_pf *work)
7130{
6389ee94
AK		 7131 struct x86_exception fault;
7132
7c90705b 7133 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7134 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7135
7136 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7137 (vcpu->arch.apf.send_user_only &&
7138 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7139 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7140 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7141 fault.vector = PF_VECTOR;
7142 fault.error_code_valid = true;
7143 fault.error_code = 0;
7144 fault.nested_page_fault = false;
7145 fault.address = work->arch.token;
7146 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7147 }
af585b92
GN		 7148}
7149
7150void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7151 struct kvm_async_pf *work)
7152{
6389ee94
AK		 7153 struct x86_exception fault;
7154
7c90705b
GN		 7155 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7156 if (is_error_page(work->page))
7157 work->arch.token = ~0; /* broadcast wakeup */
7158 else
7159 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7160
7161 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7162 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7163 fault.vector = PF_VECTOR;
7164 fault.error_code_valid = true;
7165 fault.error_code = 0;
7166 fault.nested_page_fault = false;
7167 fault.address = work->arch.token;
7168 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7169 }
e6d53e3b 7170 vcpu->arch.apf.halted = false;
a4fa1635 7171 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7172}
7173
7174bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7175{
7176 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7177 return true;
7178 else
7179 return !kvm_event_needs_reinjection(vcpu) &&
7180 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7181}
7182
229456fc
MT		 7183EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7184EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7185EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7186EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7187EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7188EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7189EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7190EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7191EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7192EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7193EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7194EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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