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x86/fpu: Harmonize the names of the fpstate_init() helper functions
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
0bed3b56 60#include <asm/mtrr.h>
890ca9ae 61#include <asm/mce.h>
f89e32e0 62#include <linux/kernel_stat.h>
78f7f1e5 63#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
92a1f12d
JR		 101bool kvm_has_tsc_control;
102EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103u32 kvm_max_guest_tsc_khz;
104EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
cc578287
ZA		 106/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107static u32 tsc_tolerance_ppm = 250;
108module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
d0659d94
MT		 110/* lapic timer advance (tscdeadline mode only) in nanoseconds */
111unsigned int lapic_timer_advance_ns = 0;
112module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
113
16a96021
MT		 114static bool backwards_tsc_observed = false;
115
18863bdd
AK		 116#define KVM_NR_SHARED_MSRS 16
117
118struct kvm_shared_msrs_global {
119 int nr;
2bf78fa7 120 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 121};
122
123struct kvm_shared_msrs {
124 struct user_return_notifier urn;
125 bool registered;
2bf78fa7
SY		 126 struct kvm_shared_msr_values {
127 u64 host;
128 u64 curr;
129 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 130};
131
132static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 133static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 134
417bc304 135struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 136 { "pf_fixed", VCPU_STAT(pf_fixed) },
137 { "pf_guest", VCPU_STAT(pf_guest) },
138 { "tlb_flush", VCPU_STAT(tlb_flush) },
139 { "invlpg", VCPU_STAT(invlpg) },
140 { "exits", VCPU_STAT(exits) },
141 { "io_exits", VCPU_STAT(io_exits) },
142 { "mmio_exits", VCPU_STAT(mmio_exits) },
143 { "signal_exits", VCPU_STAT(signal_exits) },
144 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 145 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 146 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 147 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 148 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 149 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 150 { "request_irq", VCPU_STAT(request_irq_exits) },
151 { "irq_exits", VCPU_STAT(irq_exits) },
152 { "host_state_reload", VCPU_STAT(host_state_reload) },
153 { "efer_reload", VCPU_STAT(efer_reload) },
154 { "fpu_reload", VCPU_STAT(fpu_reload) },
155 { "insn_emulation", VCPU_STAT(insn_emulation) },
156 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 157 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 158 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 159 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
160 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
161 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
162 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
163 { "mmu_flooded", VM_STAT(mmu_flooded) },
164 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 165 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 166 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 167 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 168 { "largepages", VM_STAT(lpages) },
417bc304
HB		 169 { NULL }
170};
171
2acf923e
DC		 172u64 __read_mostly host_xcr0;
173
b6785def 174static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 175
af585b92
GN		 176static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
177{
178 int i;
179 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
180 vcpu->arch.apf.gfns[i] = ~0;
181}
182
18863bdd
AK		 183static void kvm_on_user_return(struct user_return_notifier *urn)
184{
185 unsigned slot;
18863bdd
AK		 186 struct kvm_shared_msrs *locals
187 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 188 struct kvm_shared_msr_values *values;
18863bdd
AK		 189
190 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 191 values = &locals->values[slot];
192 if (values->host != values->curr) {
193 wrmsrl(shared_msrs_global.msrs[slot], values->host);
194 values->curr = values->host;
18863bdd
AK		 195 }
196 }
197 locals->registered = false;
198 user_return_notifier_unregister(urn);
199}
200
2bf78fa7 201static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 202{
18863bdd 203 u64 value;
013f6a5d
MT		 204 unsigned int cpu = smp_processor_id();
205 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 206
2bf78fa7
SY		 207 /* only read, and nobody should modify it at this time,
208 * so don't need lock */
209 if (slot >= shared_msrs_global.nr) {
210 printk(KERN_ERR "kvm: invalid MSR slot!");
211 return;
212 }
213 rdmsrl_safe(msr, &value);
214 smsr->values[slot].host = value;
215 smsr->values[slot].curr = value;
216}
217
218void kvm_define_shared_msr(unsigned slot, u32 msr)
219{
0123be42 220 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 221 if (slot >= shared_msrs_global.nr)
222 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 223 shared_msrs_global.msrs[slot] = msr;
224 /* we need ensured the shared_msr_global have been updated */
225 smp_wmb();
18863bdd
AK		 226}
227EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
228
229static void kvm_shared_msr_cpu_online(void)
230{
231 unsigned i;
18863bdd
AK		 232
233 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 234 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 235}
236
8b3c3104 237int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 238{
013f6a5d
MT		 239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 241 int err;
18863bdd 242
2bf78fa7 243 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 244 return 0;
2bf78fa7 245 smsr->values[slot].curr = value;
8b3c3104
AH		 246 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
247 if (err)
248 return 1;
249
18863bdd
AK		 250 if (!smsr->registered) {
251 smsr->urn.on_user_return = kvm_on_user_return;
252 user_return_notifier_register(&smsr->urn);
253 smsr->registered = true;
254 }
8b3c3104 255 return 0;
18863bdd
AK		 256}
257EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
258
13a34e06 259static void drop_user_return_notifiers(void)
3548bab5 260{
013f6a5d
MT		 261 unsigned int cpu = smp_processor_id();
262 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 263
264 if (smsr->registered)
265 kvm_on_user_return(&smsr->urn);
266}
267
6866b83e
CO		 268u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
269{
8a5a87d9 270 return vcpu->arch.apic_base;
6866b83e
CO		 271}
272EXPORT_SYMBOL_GPL(kvm_get_apic_base);
273
58cb628d
JK		 274int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
275{
276 u64 old_state = vcpu->arch.apic_base &
277 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
278 u64 new_state = msr_info->data &
279 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
280 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
281 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
282
283 if (!msr_info->host_initiated &&
284 ((msr_info->data & reserved_bits) != 0 ||
285 new_state == X2APIC_ENABLE ||
286 (new_state == MSR_IA32_APICBASE_ENABLE &&
287 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
288 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
289 old_state == 0)))
290 return 1;
291
292 kvm_lapic_set_base(vcpu, msr_info->data);
293 return 0;
6866b83e
CO		 294}
295EXPORT_SYMBOL_GPL(kvm_set_apic_base);
296
2605fc21 297asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 298{
299 /* Fault while not rebooting. We want the trace. */
300 BUG();
301}
302EXPORT_SYMBOL_GPL(kvm_spurious_fault);
303
3fd28fce
ED		 304#define EXCPT_BENIGN 0
305#define EXCPT_CONTRIBUTORY 1
306#define EXCPT_PF 2
307
308static int exception_class(int vector)
309{
310 switch (vector) {
311 case PF_VECTOR:
312 return EXCPT_PF;
313 case DE_VECTOR:
314 case TS_VECTOR:
315 case NP_VECTOR:
316 case SS_VECTOR:
317 case GP_VECTOR:
318 return EXCPT_CONTRIBUTORY;
319 default:
320 break;
321 }
322 return EXCPT_BENIGN;
323}
324
d6e8c854
NA		 325#define EXCPT_FAULT 0
326#define EXCPT_TRAP 1
327#define EXCPT_ABORT 2
328#define EXCPT_INTERRUPT 3
329
330static int exception_type(int vector)
331{
332 unsigned int mask;
333
334 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
335 return EXCPT_INTERRUPT;
336
337 mask = 1 << vector;
338
339 /* #DB is trap, as instruction watchpoints are handled elsewhere */
340 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
341 return EXCPT_TRAP;
342
343 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
344 return EXCPT_ABORT;
345
346 /* Reserved exceptions will result in fault */
347 return EXCPT_FAULT;
348}
349
3fd28fce 350static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 351 unsigned nr, bool has_error, u32 error_code,
352 bool reinject)
3fd28fce
ED		 353{
354 u32 prev_nr;
355 int class1, class2;
356
3842d135
AK		 357 kvm_make_request(KVM_REQ_EVENT, vcpu);
358
3fd28fce
ED		 359 if (!vcpu->arch.exception.pending) {
360 queue:
3ffb2468
NA		 361 if (has_error && !is_protmode(vcpu))
362 has_error = false;
3fd28fce
ED		 363 vcpu->arch.exception.pending = true;
364 vcpu->arch.exception.has_error_code = has_error;
365 vcpu->arch.exception.nr = nr;
366 vcpu->arch.exception.error_code = error_code;
3f0fd292 367 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 368 return;
369 }
370
371 /* to check exception */
372 prev_nr = vcpu->arch.exception.nr;
373 if (prev_nr == DF_VECTOR) {
374 /* triple fault -> shutdown */
a8eeb04a 375 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 376 return;
377 }
378 class1 = exception_class(prev_nr);
379 class2 = exception_class(nr);
380 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
381 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
382 /* generate double fault per SDM Table 5-5 */
383 vcpu->arch.exception.pending = true;
384 vcpu->arch.exception.has_error_code = true;
385 vcpu->arch.exception.nr = DF_VECTOR;
386 vcpu->arch.exception.error_code = 0;
387 } else
388 /* replace previous exception with a new one in a hope
389 that instruction re-execution will regenerate lost
390 exception */
391 goto queue;
392}
393
298101da
AK		 394void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
395{
ce7ddec4 396 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 397}
398EXPORT_SYMBOL_GPL(kvm_queue_exception);
399
ce7ddec4
JR		 400void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
401{
402 kvm_multiple_exception(vcpu, nr, false, 0, true);
403}
404EXPORT_SYMBOL_GPL(kvm_requeue_exception);
405
db8fcefa 406void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 407{
db8fcefa
AP		 408 if (err)
409 kvm_inject_gp(vcpu, 0);
410 else
411 kvm_x86_ops->skip_emulated_instruction(vcpu);
412}
413EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 414
6389ee94 415void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 416{
417 ++vcpu->stat.pf_guest;
6389ee94
AK		 418 vcpu->arch.cr2 = fault->address;
419 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 420}
27d6c865 421EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 422
ef54bcfe 423static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 424{
6389ee94
AK		 425 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
426 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 427 else
6389ee94 428 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 429
430 return fault->nested_page_fault;
d4f8cf66
JR		 431}
432
3419ffc8
SY		 433void kvm_inject_nmi(struct kvm_vcpu *vcpu)
434{
7460fb4a
AK		 435 atomic_inc(&vcpu->arch.nmi_queued);
436 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 437}
438EXPORT_SYMBOL_GPL(kvm_inject_nmi);
439
298101da
AK		 440void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
441{
ce7ddec4 442 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 443}
444EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
445
ce7ddec4
JR		 446void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
447{
448 kvm_multiple_exception(vcpu, nr, true, error_code, true);
449}
450EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
451
0a79b009
AK		 452/*
453 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
454 * a #GP and return false.
455 */
456bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 457{
0a79b009
AK		 458 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
459 return true;
460 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
461 return false;
298101da 462}
0a79b009 463EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 464
16f8a6f9
NA		 465bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
466{
467 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
468 return true;
469
470 kvm_queue_exception(vcpu, UD_VECTOR);
471 return false;
472}
473EXPORT_SYMBOL_GPL(kvm_require_dr);
474
ec92fe44
JR		 475/*
476 * This function will be used to read from the physical memory of the currently
477 * running guest. The difference to kvm_read_guest_page is that this function
478 * can read from guest physical or from the guest's guest physical memory.
479 */
480int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
481 gfn_t ngfn, void *data, int offset, int len,
482 u32 access)
483{
54987b7a 484 struct x86_exception exception;
ec92fe44
JR		 485 gfn_t real_gfn;
486 gpa_t ngpa;
487
488 ngpa = gfn_to_gpa(ngfn);
54987b7a 489 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 490 if (real_gfn == UNMAPPED_GVA)
491 return -EFAULT;
492
493 real_gfn = gpa_to_gfn(real_gfn);
494
495 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
496}
497EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
498
69b0049a 499static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 500 void *data, int offset, int len, u32 access)
501{
502 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
503 data, offset, len, access);
504}
505
a03490ed
CO		 506/*
507 * Load the pae pdptrs. Return true is they are all valid.
508 */
ff03a073 509int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 510{
511 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
512 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
513 int i;
514 int ret;
ff03a073 515 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 516
ff03a073
JR		 517 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
518 offset * sizeof(u64), sizeof(pdpte),
519 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 520 if (ret < 0) {
521 ret = 0;
522 goto out;
523 }
524 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 525 if (is_present_gpte(pdpte[i]) &&
20c466b5 526 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 527 ret = 0;
528 goto out;
529 }
530 }
531 ret = 1;
532
ff03a073 533 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 534 __set_bit(VCPU_EXREG_PDPTR,
535 (unsigned long *)&vcpu->arch.regs_avail);
536 __set_bit(VCPU_EXREG_PDPTR,
537 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 538out:
a03490ed
CO		 539
540 return ret;
541}
cc4b6871 542EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 543
d835dfec
AK		 544static bool pdptrs_changed(struct kvm_vcpu *vcpu)
545{
ff03a073 546 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 547 bool changed = true;
3d06b8bf
JR		 548 int offset;
549 gfn_t gfn;
d835dfec
AK		 550 int r;
551
552 if (is_long_mode(vcpu) || !is_pae(vcpu))
553 return false;
554
6de4f3ad
AK		 555 if (!test_bit(VCPU_EXREG_PDPTR,
556 (unsigned long *)&vcpu->arch.regs_avail))
557 return true;
558
9f8fe504
AK		 559 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
560 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 561 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
562 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 563 if (r < 0)
564 goto out;
ff03a073 565 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 566out:
d835dfec
AK		 567
568 return changed;
569}
570
49a9b07e 571int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 572{
aad82703
SY		 573 unsigned long old_cr0 = kvm_read_cr0(vcpu);
574 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
575 X86_CR0_CD | X86_CR0_NW;
576
f9a48e6a
AK		 577 cr0 |= X86_CR0_ET;
578
ab344828 579#ifdef CONFIG_X86_64
0f12244f
GN		 580 if (cr0 & 0xffffffff00000000UL)
581 return 1;
ab344828
GN		 582#endif
583
584 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 585
0f12244f
GN		 586 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
587 return 1;
a03490ed 588
0f12244f
GN		 589 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
590 return 1;
a03490ed
CO		 591
592 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
593#ifdef CONFIG_X86_64
f6801dff 594 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 595 int cs_db, cs_l;
596
0f12244f
GN		 597 if (!is_pae(vcpu))
598 return 1;
a03490ed 599 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 600 if (cs_l)
601 return 1;
a03490ed
CO		 602 } else
603#endif
ff03a073 604 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 605 kvm_read_cr3(vcpu)))
0f12244f 606 return 1;
a03490ed
CO		 607 }
608
ad756a16
MJ		 609 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
610 return 1;
611
a03490ed 612 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 613
d170c419 614 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 615 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 616 kvm_async_pf_hash_reset(vcpu);
617 }
e5f3f027 618
aad82703
SY		 619 if ((cr0 ^ old_cr0) & update_bits)
620 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 621 return 0;
622}
2d3ad1f4 623EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 624
2d3ad1f4 625void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 626{
49a9b07e 627 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 628}
2d3ad1f4 629EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 630
42bdf991
MT		 631static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
632{
633 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
634 !vcpu->guest_xcr0_loaded) {
635 /* kvm_set_xcr() also depends on this */
636 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
637 vcpu->guest_xcr0_loaded = 1;
638 }
639}
640
641static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
642{
643 if (vcpu->guest_xcr0_loaded) {
644 if (vcpu->arch.xcr0 != host_xcr0)
645 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
646 vcpu->guest_xcr0_loaded = 0;
647 }
648}
649
69b0049a 650static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 651{
56c103ec
LJ		 652 u64 xcr0 = xcr;
653 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 654 u64 valid_bits;
2acf923e
DC		 655
656 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
657 if (index != XCR_XFEATURE_ENABLED_MASK)
658 return 1;
2acf923e
DC		 659 if (!(xcr0 & XSTATE_FP))
660 return 1;
661 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
662 return 1;
46c34cb0
PB		 663
664 /*
665 * Do not allow the guest to set bits that we do not support
666 * saving. However, xcr0 bit 0 is always set, even if the
667 * emulated CPU does not support XSAVE (see fx_init).
668 */
669 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
670 if (xcr0 & ~valid_bits)
2acf923e 671 return 1;
46c34cb0 672
390bd528
LJ		 673 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
674 return 1;
675
612263b3
CP		 676 if (xcr0 & XSTATE_AVX512) {
677 if (!(xcr0 & XSTATE_YMM))
678 return 1;
679 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
680 return 1;
681 }
42bdf991 682 kvm_put_guest_xcr0(vcpu);
2acf923e 683 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 684
685 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
686 kvm_update_cpuid(vcpu);
2acf923e
DC		 687 return 0;
688}
689
690int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
691{
764bcbc5
Z		 692 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
693 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 694 kvm_inject_gp(vcpu, 0);
695 return 1;
696 }
697 return 0;
698}
699EXPORT_SYMBOL_GPL(kvm_set_xcr);
700
a83b29c6 701int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 702{
fc78f519 703 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 704 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
705 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 706 if (cr4 & CR4_RESERVED_BITS)
707 return 1;
a03490ed 708
2acf923e
DC		 709 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
710 return 1;
711
c68b734f
YW		 712 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
713 return 1;
714
97ec8c06
FW		 715 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
716 return 1;
717
afcbf13f 718 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 719 return 1;
720
a03490ed 721 if (is_long_mode(vcpu)) {
0f12244f
GN		 722 if (!(cr4 & X86_CR4_PAE))
723 return 1;
a2edf57f
AK		 724 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
725 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 726 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
727 kvm_read_cr3(vcpu)))
0f12244f
GN		 728 return 1;
729
ad756a16
MJ		 730 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
731 if (!guest_cpuid_has_pcid(vcpu))
732 return 1;
733
734 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
735 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
736 return 1;
737 }
738
5e1746d6 739 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 740 return 1;
a03490ed 741
ad756a16
MJ		 742 if (((cr4 ^ old_cr4) & pdptr_bits) ||
743 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 744 kvm_mmu_reset_context(vcpu);
0f12244f 745
97ec8c06
FW		 746 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
747 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
748
2acf923e 749 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 750 kvm_update_cpuid(vcpu);
2acf923e 751
0f12244f
GN		 752 return 0;
753}
2d3ad1f4 754EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 755
2390218b 756int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 757{
ac146235 758#ifdef CONFIG_X86_64
9d88fca7 759 cr3 &= ~CR3_PCID_INVD;
ac146235 760#endif
9d88fca7 761
9f8fe504 762 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 763 kvm_mmu_sync_roots(vcpu);
77c3913b 764 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 765 return 0;
d835dfec
AK		 766 }
767
a03490ed 768 if (is_long_mode(vcpu)) {
d9f89b88
JK		 769 if (cr3 & CR3_L_MODE_RESERVED_BITS)
770 return 1;
771 } else if (is_pae(vcpu) && is_paging(vcpu) &&
772 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 773 return 1;
a03490ed 774
0f12244f 775 vcpu->arch.cr3 = cr3;
aff48baa 776 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 777 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 778 return 0;
779}
2d3ad1f4 780EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 781
eea1cff9 782int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 783{
0f12244f
GN		 784 if (cr8 & CR8_RESERVED_BITS)
785 return 1;
a03490ed
CO		 786 if (irqchip_in_kernel(vcpu->kvm))
787 kvm_lapic_set_tpr(vcpu, cr8);
788 else
ad312c7c 789 vcpu->arch.cr8 = cr8;
0f12244f
GN		 790 return 0;
791}
2d3ad1f4 792EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 793
2d3ad1f4 794unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 795{
796 if (irqchip_in_kernel(vcpu->kvm))
797 return kvm_lapic_get_cr8(vcpu);
798 else
ad312c7c 799 return vcpu->arch.cr8;
a03490ed 800}
2d3ad1f4 801EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 802
ae561ede
NA		 803static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
804{
805 int i;
806
807 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
808 for (i = 0; i < KVM_NR_DB_REGS; i++)
809 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
810 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
811 }
812}
813
73aaf249
JK		 814static void kvm_update_dr6(struct kvm_vcpu *vcpu)
815{
816 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
817 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
818}
819
c8639010
JK		 820static void kvm_update_dr7(struct kvm_vcpu *vcpu)
821{
822 unsigned long dr7;
823
824 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
825 dr7 = vcpu->arch.guest_debug_dr7;
826 else
827 dr7 = vcpu->arch.dr7;
828 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 829 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
830 if (dr7 & DR7_BP_EN_MASK)
831 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 832}
833
6f43ed01
NA		 834static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
835{
836 u64 fixed = DR6_FIXED_1;
837
838 if (!guest_cpuid_has_rtm(vcpu))
839 fixed |= DR6_RTM;
840 return fixed;
841}
842
338dbc97 843static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 844{
845 switch (dr) {
846 case 0 ... 3:
847 vcpu->arch.db[dr] = val;
848 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
849 vcpu->arch.eff_db[dr] = val;
850 break;
851 case 4:
020df079
GN		 852 /* fall through */
853 case 6:
338dbc97
GN		 854 if (val & 0xffffffff00000000ULL)
855 return -1; /* #GP */
6f43ed01 856 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 857 kvm_update_dr6(vcpu);
020df079
GN		 858 break;
859 case 5:
020df079
GN		 860 /* fall through */
861 default: /* 7 */
338dbc97
GN		 862 if (val & 0xffffffff00000000ULL)
863 return -1; /* #GP */
020df079 864 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 865 kvm_update_dr7(vcpu);
020df079
GN		 866 break;
867 }
868
869 return 0;
870}
338dbc97
GN		 871
872int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
873{
16f8a6f9 874 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 875 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 876 return 1;
877 }
878 return 0;
338dbc97 879}
020df079
GN		 880EXPORT_SYMBOL_GPL(kvm_set_dr);
881
16f8a6f9 882int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 883{
884 switch (dr) {
885 case 0 ... 3:
886 *val = vcpu->arch.db[dr];
887 break;
888 case 4:
020df079
GN		 889 /* fall through */
890 case 6:
73aaf249
JK		 891 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
892 *val = vcpu->arch.dr6;
893 else
894 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 895 break;
896 case 5:
020df079
GN		 897 /* fall through */
898 default: /* 7 */
899 *val = vcpu->arch.dr7;
900 break;
901 }
338dbc97
GN		 902 return 0;
903}
020df079
GN		 904EXPORT_SYMBOL_GPL(kvm_get_dr);
905
022cd0e8
AK		 906bool kvm_rdpmc(struct kvm_vcpu *vcpu)
907{
908 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
909 u64 data;
910 int err;
911
912 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
913 if (err)
914 return err;
915 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
916 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
917 return err;
918}
919EXPORT_SYMBOL_GPL(kvm_rdpmc);
920
043405e1
CO		 921/*
922 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
923 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
924 *
925 * This list is modified at module load time to reflect the
e3267cbb
GC		 926 * capabilities of the host cpu. This capabilities test skips MSRs that are
927 * kvm-specific. Those are put in the beginning of the list.
043405e1 928 */
e3267cbb 929
e984097b 930#define KVM_SAVE_MSRS_BEGIN 12
043405e1 931static u32 msrs_to_save[] = {
e3267cbb 932 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 933 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 934 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 935 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 936 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 937 MSR_KVM_PV_EOI_EN,
043405e1 938 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 939 MSR_STAR,
043405e1
CO		 940#ifdef CONFIG_X86_64
941 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
942#endif
b3897a49 943 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 944 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 945};
946
947static unsigned num_msrs_to_save;
948
f1d24831 949static const u32 emulated_msrs[] = {
ba904635 950 MSR_IA32_TSC_ADJUST,
a3e06bbe 951 MSR_IA32_TSCDEADLINE,
043405e1 952 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 953 MSR_IA32_MCG_STATUS,
954 MSR_IA32_MCG_CTL,
043405e1
CO		 955};
956
384bb783 957bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 958{
b69e8cae 959 if (efer & efer_reserved_bits)
384bb783 960 return false;
15c4a640 961
1b2fd70c
AG		 962 if (efer & EFER_FFXSR) {
963 struct kvm_cpuid_entry2 *feat;
964
965 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 966 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 967 return false;
1b2fd70c
AG		 968 }
969
d8017474
AG		 970 if (efer & EFER_SVME) {
971 struct kvm_cpuid_entry2 *feat;
972
973 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 974 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 975 return false;
d8017474
AG		 976 }
977
384bb783
JK		 978 return true;
979}
980EXPORT_SYMBOL_GPL(kvm_valid_efer);
981
982static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
983{
984 u64 old_efer = vcpu->arch.efer;
985
986 if (!kvm_valid_efer(vcpu, efer))
987 return 1;
988
989 if (is_paging(vcpu)
990 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
991 return 1;
992
15c4a640 993 efer &= ~EFER_LMA;
f6801dff 994 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 995
a3d204e2
SY		 996 kvm_x86_ops->set_efer(vcpu, efer);
997
aad82703
SY		 998 /* Update reserved bits */
999 if ((efer ^ old_efer) & EFER_NX)
1000 kvm_mmu_reset_context(vcpu);
1001
b69e8cae 1002 return 0;
15c4a640
CO		 1003}
1004
f2b4b7dd
JR		 1005void kvm_enable_efer_bits(u64 mask)
1006{
1007 efer_reserved_bits &= ~mask;
1008}
1009EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1010
15c4a640
CO		 1011/*
1012 * Writes msr value into into the appropriate "register".
1013 * Returns 0 on success, non-0 otherwise.
1014 * Assumes vcpu_load() was already called.
1015 */
8fe8ab46 1016int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1017{
854e8bb1
NA		 1018 switch (msr->index) {
1019 case MSR_FS_BASE:
1020 case MSR_GS_BASE:
1021 case MSR_KERNEL_GS_BASE:
1022 case MSR_CSTAR:
1023 case MSR_LSTAR:
1024 if (is_noncanonical_address(msr->data))
1025 return 1;
1026 break;
1027 case MSR_IA32_SYSENTER_EIP:
1028 case MSR_IA32_SYSENTER_ESP:
1029 /*
1030 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1031 * non-canonical address is written on Intel but not on
1032 * AMD (which ignores the top 32-bits, because it does
1033 * not implement 64-bit SYSENTER).
1034 *
1035 * 64-bit code should hence be able to write a non-canonical
1036 * value on AMD. Making the address canonical ensures that
1037 * vmentry does not fail on Intel after writing a non-canonical
1038 * value, and that something deterministic happens if the guest
1039 * invokes 64-bit SYSENTER.
1040 */
1041 msr->data = get_canonical(msr->data);
1042 }
8fe8ab46 1043 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1044}
854e8bb1 1045EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1046
313a3dc7
CO		 1047/*
1048 * Adapt set_msr() to msr_io()'s calling convention
1049 */
1050static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1051{
8fe8ab46
WA		 1052 struct msr_data msr;
1053
1054 msr.data = *data;
1055 msr.index = index;
1056 msr.host_initiated = true;
1057 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1058}
1059
16e8d74d
MT		 1060#ifdef CONFIG_X86_64
1061struct pvclock_gtod_data {
1062 seqcount_t seq;
1063
1064 struct { /* extract of a clocksource struct */
1065 int vclock_mode;
1066 cycle_t cycle_last;
1067 cycle_t mask;
1068 u32 mult;
1069 u32 shift;
1070 } clock;
1071
cbcf2dd3
TG		 1072 u64 boot_ns;
1073 u64 nsec_base;
16e8d74d
MT		 1074};
1075
1076static struct pvclock_gtod_data pvclock_gtod_data;
1077
1078static void update_pvclock_gtod(struct timekeeper *tk)
1079{
1080 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1081 u64 boot_ns;
1082
876e7881 1083 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1084
1085 write_seqcount_begin(&vdata->seq);
1086
1087 /* copy pvclock gtod data */
876e7881
PZ		 1088 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1089 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1090 vdata->clock.mask = tk->tkr_mono.mask;
1091 vdata->clock.mult = tk->tkr_mono.mult;
1092 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1093
cbcf2dd3 1094 vdata->boot_ns = boot_ns;
876e7881 1095 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1096
1097 write_seqcount_end(&vdata->seq);
1098}
1099#endif
1100
bab5bb39
NK		 1101void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1102{
1103 /*
1104 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1105 * vcpu_enter_guest. This function is only called from
1106 * the physical CPU that is running vcpu.
1107 */
1108 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1109}
16e8d74d 1110
18068523
GOC		 1111static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1112{
9ed3c444
AK		 1113 int version;
1114 int r;
50d0a0f9 1115 struct pvclock_wall_clock wc;
923de3cf 1116 struct timespec boot;
18068523
GOC		 1117
1118 if (!wall_clock)
1119 return;
1120
9ed3c444
AK		 1121 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1122 if (r)
1123 return;
1124
1125 if (version & 1)
1126 ++version; /* first time write, random junk */
1127
1128 ++version;
18068523 1129
18068523
GOC		 1130 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1131
50d0a0f9
GH		 1132 /*
1133 * The guest calculates current wall clock time by adding
34c238a1 1134 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1135 * wall clock specified here. guest system time equals host
1136 * system time for us, thus we must fill in host boot time here.
1137 */
923de3cf 1138 getboottime(&boot);
50d0a0f9 1139
4b648665
BR		 1140 if (kvm->arch.kvmclock_offset) {
1141 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1142 boot = timespec_sub(boot, ts);
1143 }
50d0a0f9
GH		 1144 wc.sec = boot.tv_sec;
1145 wc.nsec = boot.tv_nsec;
1146 wc.version = version;
18068523
GOC		 1147
1148 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1149
1150 version++;
1151 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1152}
1153
50d0a0f9
GH		 1154static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1155{
1156 uint32_t quotient, remainder;
1157
1158 /* Don't try to replace with do_div(), this one calculates
1159 * "(dividend << 32) / divisor" */
1160 __asm__ ( "divl %4"
1161 : "=a" (quotient), "=d" (remainder)
1162 : "0" (0), "1" (dividend), "r" (divisor) );
1163 return quotient;
1164}
1165
5f4e3f88
ZA		 1166static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1167 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1168{
5f4e3f88 1169 uint64_t scaled64;
50d0a0f9
GH		 1170 int32_t shift = 0;
1171 uint64_t tps64;
1172 uint32_t tps32;
1173
5f4e3f88
ZA		 1174 tps64 = base_khz * 1000LL;
1175 scaled64 = scaled_khz * 1000LL;
50933623 1176 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1177 tps64 >>= 1;
1178 shift--;
1179 }
1180
1181 tps32 = (uint32_t)tps64;
50933623
JK		 1182 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1183 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1184 scaled64 >>= 1;
1185 else
1186 tps32 <<= 1;
50d0a0f9
GH		 1187 shift++;
1188 }
1189
5f4e3f88
ZA		 1190 *pshift = shift;
1191 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1192
5f4e3f88
ZA		 1193 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1194 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1195}
1196
759379dd
ZA		 1197static inline u64 get_kernel_ns(void)
1198{
bb0b5812 1199 return ktime_get_boot_ns();
50d0a0f9
GH		 1200}
1201
d828199e 1202#ifdef CONFIG_X86_64
16e8d74d 1203static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1204#endif
16e8d74d 1205
c8076604 1206static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1207static unsigned long max_tsc_khz;
c8076604 1208
cc578287 1209static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1210{
cc578287
ZA		 1211 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1212 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1213}
1214
cc578287 1215static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1216{
cc578287
ZA		 1217 u64 v = (u64)khz * (1000000 + ppm);
1218 do_div(v, 1000000);
1219 return v;
1e993611
JR		 1220}
1221
cc578287 1222static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1223{
cc578287
ZA		 1224 u32 thresh_lo, thresh_hi;
1225 int use_scaling = 0;
217fc9cf 1226
03ba32ca
MT		 1227 /* tsc_khz can be zero if TSC calibration fails */
1228 if (this_tsc_khz == 0)
1229 return;
1230
c285545f
ZA		 1231 /* Compute a scale to convert nanoseconds in TSC cycles */
1232 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1233 &vcpu->arch.virtual_tsc_shift,
1234 &vcpu->arch.virtual_tsc_mult);
1235 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1236
1237 /*
1238 * Compute the variation in TSC rate which is acceptable
1239 * within the range of tolerance and decide if the
1240 * rate being applied is within that bounds of the hardware
1241 * rate. If so, no scaling or compensation need be done.
1242 */
1243 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1244 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1245 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1246 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1247 use_scaling = 1;
1248 }
1249 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1250}
1251
1252static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1253{
e26101b1 1254 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1255 vcpu->arch.virtual_tsc_mult,
1256 vcpu->arch.virtual_tsc_shift);
e26101b1 1257 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1258 return tsc;
1259}
1260
69b0049a 1261static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1262{
1263#ifdef CONFIG_X86_64
1264 bool vcpus_matched;
b48aa97e
MT		 1265 struct kvm_arch *ka = &vcpu->kvm->arch;
1266 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1267
1268 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1269 atomic_read(&vcpu->kvm->online_vcpus));
1270
7f187922
MT		 1271 /*
1272 * Once the masterclock is enabled, always perform request in
1273 * order to update it.
1274 *
1275 * In order to enable masterclock, the host clocksource must be TSC
1276 * and the vcpus need to have matched TSCs. When that happens,
1277 * perform request to enable masterclock.
1278 */
1279 if (ka->use_master_clock ||
1280 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1281 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1282
1283 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1284 atomic_read(&vcpu->kvm->online_vcpus),
1285 ka->use_master_clock, gtod->clock.vclock_mode);
1286#endif
1287}
1288
ba904635
WA		 1289static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1290{
1291 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1292 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1293}
1294
8fe8ab46 1295void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1296{
1297 struct kvm *kvm = vcpu->kvm;
f38e098f 1298 u64 offset, ns, elapsed;
99e3e30a 1299 unsigned long flags;
02626b6a 1300 s64 usdiff;
b48aa97e 1301 bool matched;
0d3da0d2 1302 bool already_matched;
8fe8ab46 1303 u64 data = msr->data;
99e3e30a 1304
038f8c11 1305 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1306 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1307 ns = get_kernel_ns();
f38e098f 1308 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1309
03ba32ca 1310 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1311 int faulted = 0;
1312
03ba32ca
MT		 1313 /* n.b - signed multiplication and division required */
1314 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1315#ifdef CONFIG_X86_64
03ba32ca 1316 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1317#else
03ba32ca 1318 /* do_div() only does unsigned */
8915aa27
MT		 1319 asm("1: idivl %[divisor]\n"
1320 "2: xor %%edx, %%edx\n"
1321 " movl $0, %[faulted]\n"
1322 "3:\n"
1323 ".section .fixup,\"ax\"\n"
1324 "4: movl $1, %[faulted]\n"
1325 " jmp 3b\n"
1326 ".previous\n"
1327
1328 _ASM_EXTABLE(1b, 4b)
1329
1330 : "=A"(usdiff), [faulted] "=r" (faulted)
1331 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1332
5d3cb0f6 1333#endif
03ba32ca
MT		 1334 do_div(elapsed, 1000);
1335 usdiff -= elapsed;
1336 if (usdiff < 0)
1337 usdiff = -usdiff;
8915aa27
MT		 1338
1339 /* idivl overflow => difference is larger than USEC_PER_SEC */
1340 if (faulted)
1341 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1342 } else
1343 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1344
1345 /*
5d3cb0f6
ZA		 1346 * Special case: TSC write with a small delta (1 second) of virtual
1347 * cycle time against real time is interpreted as an attempt to
1348 * synchronize the CPU.
1349 *
1350 * For a reliable TSC, we can match TSC offsets, and for an unstable
1351 * TSC, we add elapsed time in this computation. We could let the
1352 * compensation code attempt to catch up if we fall behind, but
1353 * it's better to try to match offsets from the beginning.
1354 */
02626b6a 1355 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1356 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1357 if (!check_tsc_unstable()) {
e26101b1 1358 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1359 pr_debug("kvm: matched tsc offset for %llu\n", data);
1360 } else {
857e4099 1361 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1362 data += delta;
1363 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1364 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1365 }
b48aa97e 1366 matched = true;
0d3da0d2 1367 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1368 } else {
1369 /*
1370 * We split periods of matched TSC writes into generations.
1371 * For each generation, we track the original measured
1372 * nanosecond time, offset, and write, so if TSCs are in
1373 * sync, we can match exact offset, and if not, we can match
4a969980 1374 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1375 *
1376 * These values are tracked in kvm->arch.cur_xxx variables.
1377 */
1378 kvm->arch.cur_tsc_generation++;
1379 kvm->arch.cur_tsc_nsec = ns;
1380 kvm->arch.cur_tsc_write = data;
1381 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1382 matched = false;
0d3da0d2 1383 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1384 kvm->arch.cur_tsc_generation, data);
f38e098f 1385 }
e26101b1
ZA		 1386
1387 /*
1388 * We also track th most recent recorded KHZ, write and time to
1389 * allow the matching interval to be extended at each write.
1390 */
f38e098f
ZA		 1391 kvm->arch.last_tsc_nsec = ns;
1392 kvm->arch.last_tsc_write = data;
5d3cb0f6 1393 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1394
b183aa58 1395 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1396
1397 /* Keep track of which generation this VCPU has synchronized to */
1398 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1399 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1400 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1401
ba904635
WA		 1402 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1403 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1404 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1405 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1406
1407 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1408 if (!matched) {
b48aa97e 1409 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1410 } else if (!already_matched) {
1411 kvm->arch.nr_vcpus_matched_tsc++;
1412 }
b48aa97e
MT		 1413
1414 kvm_track_tsc_matching(vcpu);
1415 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1416}
e26101b1 1417
99e3e30a
ZA		 1418EXPORT_SYMBOL_GPL(kvm_write_tsc);
1419
d828199e
MT		 1420#ifdef CONFIG_X86_64
1421
1422static cycle_t read_tsc(void)
1423{
1424 cycle_t ret;
1425 u64 last;
1426
1427 /*
1428 * Empirically, a fence (of type that depends on the CPU)
1429 * before rdtsc is enough to ensure that rdtsc is ordered
1430 * with respect to loads. The various CPU manuals are unclear
1431 * as to whether rdtsc can be reordered with later loads,
1432 * but no one has ever seen it happen.
1433 */
1434 rdtsc_barrier();
1435 ret = (cycle_t)vget_cycles();
1436
1437 last = pvclock_gtod_data.clock.cycle_last;
1438
1439 if (likely(ret >= last))
1440 return ret;
1441
1442 /*
1443 * GCC likes to generate cmov here, but this branch is extremely
1444 * predictable (it's just a funciton of time and the likely is
1445 * very likely) and there's a data dependence, so force GCC
1446 * to generate a branch instead. I don't barrier() because
1447 * we don't actually need a barrier, and if this function
1448 * ever gets inlined it will generate worse code.
1449 */
1450 asm volatile ("");
1451 return last;
1452}
1453
1454static inline u64 vgettsc(cycle_t *cycle_now)
1455{
1456 long v;
1457 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1458
1459 *cycle_now = read_tsc();
1460
1461 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1462 return v * gtod->clock.mult;
1463}
1464
cbcf2dd3 1465static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1466{
cbcf2dd3 1467 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1468 unsigned long seq;
d828199e 1469 int mode;
cbcf2dd3 1470 u64 ns;
d828199e 1471
d828199e
MT		 1472 do {
1473 seq = read_seqcount_begin(&gtod->seq);
1474 mode = gtod->clock.vclock_mode;
cbcf2dd3 1475 ns = gtod->nsec_base;
d828199e
MT		 1476 ns += vgettsc(cycle_now);
1477 ns >>= gtod->clock.shift;
cbcf2dd3 1478 ns += gtod->boot_ns;
d828199e 1479 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1480 *t = ns;
d828199e
MT		 1481
1482 return mode;
1483}
1484
1485/* returns true if host is using tsc clocksource */
1486static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1487{
d828199e
MT		 1488 /* checked again under seqlock below */
1489 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1490 return false;
1491
cbcf2dd3 1492 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1493}
1494#endif
1495
1496/*
1497 *
b48aa97e
MT		 1498 * Assuming a stable TSC across physical CPUS, and a stable TSC
1499 * across virtual CPUs, the following condition is possible.
1500 * Each numbered line represents an event visible to both
d828199e
MT		 1501 * CPUs at the next numbered event.
1502 *
1503 * "timespecX" represents host monotonic time. "tscX" represents
1504 * RDTSC value.
1505 *
1506 * VCPU0 on CPU0 | VCPU1 on CPU1
1507 *
1508 * 1. read timespec0,tsc0
1509 * 2. | timespec1 = timespec0 + N
1510 * | tsc1 = tsc0 + M
1511 * 3. transition to guest | transition to guest
1512 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1513 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1514 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1515 *
1516 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1517 *
1518 * - ret0 < ret1
1519 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1520 * ...
1521 * - 0 < N - M => M < N
1522 *
1523 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1524 * always the case (the difference between two distinct xtime instances
1525 * might be smaller then the difference between corresponding TSC reads,
1526 * when updating guest vcpus pvclock areas).
1527 *
1528 * To avoid that problem, do not allow visibility of distinct
1529 * system_timestamp/tsc_timestamp values simultaneously: use a master
1530 * copy of host monotonic time values. Update that master copy
1531 * in lockstep.
1532 *
b48aa97e 1533 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1534 *
1535 */
1536
1537static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1538{
1539#ifdef CONFIG_X86_64
1540 struct kvm_arch *ka = &kvm->arch;
1541 int vclock_mode;
b48aa97e
MT		 1542 bool host_tsc_clocksource, vcpus_matched;
1543
1544 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1545 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1546
1547 /*
1548 * If the host uses TSC clock, then passthrough TSC as stable
1549 * to the guest.
1550 */
b48aa97e 1551 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1552 &ka->master_kernel_ns,
1553 &ka->master_cycle_now);
1554
16a96021 1555 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1556 && !backwards_tsc_observed
1557 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1558
d828199e
MT		 1559 if (ka->use_master_clock)
1560 atomic_set(&kvm_guest_has_master_clock, 1);
1561
1562 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1563 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1564 vcpus_matched);
d828199e
MT		 1565#endif
1566}
1567
2e762ff7
MT		 1568static void kvm_gen_update_masterclock(struct kvm *kvm)
1569{
1570#ifdef CONFIG_X86_64
1571 int i;
1572 struct kvm_vcpu *vcpu;
1573 struct kvm_arch *ka = &kvm->arch;
1574
1575 spin_lock(&ka->pvclock_gtod_sync_lock);
1576 kvm_make_mclock_inprogress_request(kvm);
1577 /* no guest entries from this point */
1578 pvclock_update_vm_gtod_copy(kvm);
1579
1580 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1581 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1582
1583 /* guest entries allowed */
1584 kvm_for_each_vcpu(i, vcpu, kvm)
1585 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1586
1587 spin_unlock(&ka->pvclock_gtod_sync_lock);
1588#endif
1589}
1590
34c238a1 1591static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1592{
d828199e 1593 unsigned long flags, this_tsc_khz;
18068523 1594 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1595 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1596 s64 kernel_ns;
d828199e 1597 u64 tsc_timestamp, host_tsc;
0b79459b 1598 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1599 u8 pvclock_flags;
d828199e
MT		 1600 bool use_master_clock;
1601
1602 kernel_ns = 0;
1603 host_tsc = 0;
18068523 1604
d828199e
MT		 1605 /*
1606 * If the host uses TSC clock, then passthrough TSC as stable
1607 * to the guest.
1608 */
1609 spin_lock(&ka->pvclock_gtod_sync_lock);
1610 use_master_clock = ka->use_master_clock;
1611 if (use_master_clock) {
1612 host_tsc = ka->master_cycle_now;
1613 kernel_ns = ka->master_kernel_ns;
1614 }
1615 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1616
1617 /* Keep irq disabled to prevent changes to the clock */
1618 local_irq_save(flags);
89cbc767 1619 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1620 if (unlikely(this_tsc_khz == 0)) {
1621 local_irq_restore(flags);
1622 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1623 return 1;
1624 }
d828199e
MT		 1625 if (!use_master_clock) {
1626 host_tsc = native_read_tsc();
1627 kernel_ns = get_kernel_ns();
1628 }
1629
1630 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1631
c285545f
ZA		 1632 /*
1633 * We may have to catch up the TSC to match elapsed wall clock
1634 * time for two reasons, even if kvmclock is used.
1635 * 1) CPU could have been running below the maximum TSC rate
1636 * 2) Broken TSC compensation resets the base at each VCPU
1637 * entry to avoid unknown leaps of TSC even when running
1638 * again on the same CPU. This may cause apparent elapsed
1639 * time to disappear, and the guest to stand still or run
1640 * very slowly.
1641 */
1642 if (vcpu->tsc_catchup) {
1643 u64 tsc = compute_guest_tsc(v, kernel_ns);
1644 if (tsc > tsc_timestamp) {
f1e2b260 1645 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1646 tsc_timestamp = tsc;
1647 }
50d0a0f9
GH		 1648 }
1649
18068523
GOC		 1650 local_irq_restore(flags);
1651
0b79459b 1652 if (!vcpu->pv_time_enabled)
c285545f 1653 return 0;
18068523 1654
e48672fa 1655 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1656 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1657 &vcpu->hv_clock.tsc_shift,
1658 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1659 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1660 }
1661
1662 /* With all the info we got, fill in the values */
1d5f066e 1663 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1664 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1665 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1666
09a0c3f1
OH		 1667 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1668 &guest_hv_clock, sizeof(guest_hv_clock))))
1669 return 0;
1670
5dca0d91
RK		 1671 /* This VCPU is paused, but it's legal for a guest to read another
1672 * VCPU's kvmclock, so we really have to follow the specification where
1673 * it says that version is odd if data is being modified, and even after
1674 * it is consistent.
1675 *
1676 * Version field updates must be kept separate. This is because
1677 * kvm_write_guest_cached might use a "rep movs" instruction, and
1678 * writes within a string instruction are weakly ordered. So there
1679 * are three writes overall.
1680 *
1681 * As a small optimization, only write the version field in the first
1682 * and third write. The vcpu->pv_time cache is still valid, because the
1683 * version field is the first in the struct.
18068523 1684 */
5dca0d91
RK		 1685 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1686
1687 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1688 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1689 &vcpu->hv_clock,
1690 sizeof(vcpu->hv_clock.version));
1691
1692 smp_wmb();
78c0337a
MT		 1693
1694 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1695 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1696
1697 if (vcpu->pvclock_set_guest_stopped_request) {
1698 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1699 vcpu->pvclock_set_guest_stopped_request = false;
1700 }
1701
d828199e
MT		 1702 /* If the host uses TSC clocksource, then it is stable */
1703 if (use_master_clock)
1704 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1705
78c0337a
MT		 1706 vcpu->hv_clock.flags = pvclock_flags;
1707
ce1a5e60
DM		 1708 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1709
0b79459b
AH		 1710 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1711 &vcpu->hv_clock,
1712 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1713
1714 smp_wmb();
1715
1716 vcpu->hv_clock.version++;
1717 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1718 &vcpu->hv_clock,
1719 sizeof(vcpu->hv_clock.version));
8cfdc000 1720 return 0;
c8076604
GH		 1721}
1722
0061d53d
MT		 1723/*
1724 * kvmclock updates which are isolated to a given vcpu, such as
1725 * vcpu->cpu migration, should not allow system_timestamp from
1726 * the rest of the vcpus to remain static. Otherwise ntp frequency
1727 * correction applies to one vcpu's system_timestamp but not
1728 * the others.
1729 *
1730 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1731 * We need to rate-limit these requests though, as they can
1732 * considerably slow guests that have a large number of vcpus.
1733 * The time for a remote vcpu to update its kvmclock is bound
1734 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1735 */
1736
7e44e449
AJ		 1737#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1738
1739static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1740{
1741 int i;
7e44e449
AJ		 1742 struct delayed_work *dwork = to_delayed_work(work);
1743 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1744 kvmclock_update_work);
1745 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1746 struct kvm_vcpu *vcpu;
1747
1748 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1749 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1750 kvm_vcpu_kick(vcpu);
1751 }
1752}
1753
7e44e449
AJ		 1754static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1755{
1756 struct kvm *kvm = v->kvm;
1757
105b21bb 1758 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1759 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1760 KVMCLOCK_UPDATE_DELAY);
1761}
1762
332967a3
AJ		 1763#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1764
1765static void kvmclock_sync_fn(struct work_struct *work)
1766{
1767 struct delayed_work *dwork = to_delayed_work(work);
1768 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1769 kvmclock_sync_work);
1770 struct kvm *kvm = container_of(ka, struct kvm, arch);
1771
1772 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1773 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1774 KVMCLOCK_SYNC_PERIOD);
1775}
1776
9ba075a6
AK		 1777static bool msr_mtrr_valid(unsigned msr)
1778{
1779 switch (msr) {
1780 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1781 case MSR_MTRRfix64K_00000:
1782 case MSR_MTRRfix16K_80000:
1783 case MSR_MTRRfix16K_A0000:
1784 case MSR_MTRRfix4K_C0000:
1785 case MSR_MTRRfix4K_C8000:
1786 case MSR_MTRRfix4K_D0000:
1787 case MSR_MTRRfix4K_D8000:
1788 case MSR_MTRRfix4K_E0000:
1789 case MSR_MTRRfix4K_E8000:
1790 case MSR_MTRRfix4K_F0000:
1791 case MSR_MTRRfix4K_F8000:
1792 case MSR_MTRRdefType:
1793 case MSR_IA32_CR_PAT:
1794 return true;
1795 case 0x2f8:
1796 return true;
1797 }
1798 return false;
1799}
1800
d6289b93
MT		 1801static bool valid_pat_type(unsigned t)
1802{
1803 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1804}
1805
1806static bool valid_mtrr_type(unsigned t)
1807{
1808 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1809}
1810
4566654b 1811bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1812{
1813 int i;
fd275235 1814 u64 mask;
d6289b93
MT		 1815
1816 if (!msr_mtrr_valid(msr))
1817 return false;
1818
1819 if (msr == MSR_IA32_CR_PAT) {
1820 for (i = 0; i < 8; i++)
1821 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1822 return false;
1823 return true;
1824 } else if (msr == MSR_MTRRdefType) {
1825 if (data & ~0xcff)
1826 return false;
1827 return valid_mtrr_type(data & 0xff);
1828 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1829 for (i = 0; i < 8 ; i++)
1830 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1831 return false;
1832 return true;
1833 }
1834
1835 /* variable MTRRs */
adfb5d27
WL		 1836 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1837
fd275235 1838 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1839 if ((msr & 1) == 0) {
adfb5d27 1840 /* MTRR base */
d7a2a246
WL		 1841 if (!valid_mtrr_type(data & 0xff))
1842 return false;
1843 mask |= 0xf00;
1844 } else
1845 /* MTRR mask */
1846 mask |= 0x7ff;
1847 if (data & mask) {
1848 kvm_inject_gp(vcpu, 0);
1849 return false;
1850 }
1851
adfb5d27 1852 return true;
d6289b93 1853}
4566654b 1854EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1855
9ba075a6
AK		 1856static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1857{
0bed3b56
SY		 1858 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1859
4566654b 1860 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1861 return 1;
1862
0bed3b56
SY		 1863 if (msr == MSR_MTRRdefType) {
1864 vcpu->arch.mtrr_state.def_type = data;
1865 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1866 } else if (msr == MSR_MTRRfix64K_00000)
1867 p[0] = data;
1868 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1869 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1870 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1871 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1872 else if (msr == MSR_IA32_CR_PAT)
1873 vcpu->arch.pat = data;
1874 else { /* Variable MTRRs */
1875 int idx, is_mtrr_mask;
1876 u64 *pt;
1877
1878 idx = (msr - 0x200) / 2;
1879 is_mtrr_mask = msr - 0x200 - 2 * idx;
1880 if (!is_mtrr_mask)
1881 pt =
1882 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1883 else
1884 pt =
1885 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1886 *pt = data;
1887 }
1888
1889 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1890 return 0;
1891}
15c4a640 1892
890ca9ae 1893static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1894{
890ca9ae
HY		 1895 u64 mcg_cap = vcpu->arch.mcg_cap;
1896 unsigned bank_num = mcg_cap & 0xff;
1897
15c4a640 1898 switch (msr) {
15c4a640 1899 case MSR_IA32_MCG_STATUS:
890ca9ae 1900 vcpu->arch.mcg_status = data;
15c4a640 1901 break;
c7ac679c 1902 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1903 if (!(mcg_cap & MCG_CTL_P))
1904 return 1;
1905 if (data != 0 && data != ~(u64)0)
1906 return -1;
1907 vcpu->arch.mcg_ctl = data;
1908 break;
1909 default:
1910 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1911 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1912 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1913 /* only 0 or all 1s can be written to IA32_MCi_CTL
1914 * some Linux kernels though clear bit 10 in bank 4 to
1915 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1916 * this to avoid an uncatched #GP in the guest
1917 */
890ca9ae 1918 if ((offset & 0x3) == 0 &&
114be429 1919 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1920 return -1;
1921 vcpu->arch.mce_banks[offset] = data;
1922 break;
1923 }
1924 return 1;
1925 }
1926 return 0;
1927}
1928
ffde22ac
ES		 1929static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1930{
1931 struct kvm *kvm = vcpu->kvm;
1932 int lm = is_long_mode(vcpu);
1933 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1934 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1935 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1936 : kvm->arch.xen_hvm_config.blob_size_32;
1937 u32 page_num = data & ~PAGE_MASK;
1938 u64 page_addr = data & PAGE_MASK;
1939 u8 *page;
1940 int r;
1941
1942 r = -E2BIG;
1943 if (page_num >= blob_size)
1944 goto out;
1945 r = -ENOMEM;
ff5c2c03
SL		 1946 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1947 if (IS_ERR(page)) {
1948 r = PTR_ERR(page);
ffde22ac 1949 goto out;
ff5c2c03 1950 }
ffde22ac
ES		 1951 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1952 goto out_free;
1953 r = 0;
1954out_free:
1955 kfree(page);
1956out:
1957 return r;
1958}
1959
55cd8e5a
GN		 1960static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1961{
1962 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1963}
1964
1965static bool kvm_hv_msr_partition_wide(u32 msr)
1966{
1967 bool r = false;
1968 switch (msr) {
1969 case HV_X64_MSR_GUEST_OS_ID:
1970 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1971 case HV_X64_MSR_REFERENCE_TSC:
1972 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1973 r = true;
1974 break;
1975 }
1976
1977 return r;
1978}
1979
1980static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1981{
1982 struct kvm *kvm = vcpu->kvm;
1983
1984 switch (msr) {
1985 case HV_X64_MSR_GUEST_OS_ID:
1986 kvm->arch.hv_guest_os_id = data;
1987 /* setting guest os id to zero disables hypercall page */
1988 if (!kvm->arch.hv_guest_os_id)
1989 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1990 break;
1991 case HV_X64_MSR_HYPERCALL: {
1992 u64 gfn;
1993 unsigned long addr;
1994 u8 instructions[4];
1995
1996 /* if guest os id is not set hypercall should remain disabled */
1997 if (!kvm->arch.hv_guest_os_id)
1998 break;
1999 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
2000 kvm->arch.hv_hypercall = data;
2001 break;
2002 }
2003 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
2004 addr = gfn_to_hva(kvm, gfn);
2005 if (kvm_is_error_hva(addr))
2006 return 1;
2007 kvm_x86_ops->patch_hypercall(vcpu, instructions);
2008 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 2009 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 2010 return 1;
2011 kvm->arch.hv_hypercall = data;
b94b64c9 2012 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 2013 break;
2014 }
e984097b
VR		 2015 case HV_X64_MSR_REFERENCE_TSC: {
2016 u64 gfn;
2017 HV_REFERENCE_TSC_PAGE tsc_ref;
2018 memset(&tsc_ref, 0, sizeof(tsc_ref));
2019 kvm->arch.hv_tsc_page = data;
2020 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
2021 break;
2022 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 2023 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 2024 &tsc_ref, sizeof(tsc_ref)))
2025 return 1;
2026 mark_page_dirty(kvm, gfn);
2027 break;
2028 }
55cd8e5a 2029 default:
a737f256
CD		 2030 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2031 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 2032 return 1;
2033 }
2034 return 0;
2035}
2036
2037static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2038{
10388a07
GN		 2039 switch (msr) {
2040 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 2041 u64 gfn;
10388a07 2042 unsigned long addr;
55cd8e5a 2043
10388a07
GN		 2044 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2045 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 2046 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2047 return 1;
10388a07
GN		 2048 break;
2049 }
b3af1e88
VR		 2050 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2051 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 2052 if (kvm_is_error_hva(addr))
2053 return 1;
8b0cedff 2054 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2055 return 1;
2056 vcpu->arch.hv_vapic = data;
b3af1e88 2057 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2058 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2059 return 1;
10388a07
GN		 2060 break;
2061 }
2062 case HV_X64_MSR_EOI:
2063 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2064 case HV_X64_MSR_ICR:
2065 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2066 case HV_X64_MSR_TPR:
2067 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2068 default:
a737f256
CD		 2069 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2070 "data 0x%llx\n", msr, data);
10388a07
GN		 2071 return 1;
2072 }
2073
2074 return 0;
55cd8e5a
GN		 2075}
2076
344d9588
GN		 2077static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2078{
2079 gpa_t gpa = data & ~0x3f;
2080
4a969980 2081 /* Bits 2:5 are reserved, Should be zero */
6adba527 2082 if (data & 0x3c)
344d9588
GN		 2083 return 1;
2084
2085 vcpu->arch.apf.msr_val = data;
2086
2087 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2088 kvm_clear_async_pf_completion_queue(vcpu);
2089 kvm_async_pf_hash_reset(vcpu);
2090 return 0;
2091 }
2092
8f964525
AH		 2093 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2094 sizeof(u32)))
344d9588
GN		 2095 return 1;
2096
6adba527 2097 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2098 kvm_async_pf_wakeup_all(vcpu);
2099 return 0;
2100}
2101
12f9a48f
GC		 2102static void kvmclock_reset(struct kvm_vcpu *vcpu)
2103{
0b79459b 2104 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2105}
2106
c9aaa895
GC		 2107static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2108{
2109 u64 delta;
2110
2111 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2112 return;
2113
2114 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2115 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2116 vcpu->arch.st.accum_steal = delta;
2117}
2118
2119static void record_steal_time(struct kvm_vcpu *vcpu)
2120{
2121 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2122 return;
2123
2124 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2125 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2126 return;
2127
2128 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2129 vcpu->arch.st.steal.version += 2;
2130 vcpu->arch.st.accum_steal = 0;
2131
2132 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2133 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2134}
2135
8fe8ab46 2136int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2137{
5753785f 2138 bool pr = false;
8fe8ab46
WA		 2139 u32 msr = msr_info->index;
2140 u64 data = msr_info->data;
5753785f 2141
15c4a640 2142 switch (msr) {
2e32b719
BP		 2143 case MSR_AMD64_NB_CFG:
2144 case MSR_IA32_UCODE_REV:
2145 case MSR_IA32_UCODE_WRITE:
2146 case MSR_VM_HSAVE_PA:
2147 case MSR_AMD64_PATCH_LOADER:
2148 case MSR_AMD64_BU_CFG2:
2149 break;
2150
15c4a640 2151 case MSR_EFER:
b69e8cae 2152 return set_efer(vcpu, data);
8f1589d9
AP		 2153 case MSR_K7_HWCR:
2154 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2155 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2156 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2157 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2158 if (data != 0) {
a737f256
CD		 2159 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2160 data);
8f1589d9
AP		 2161 return 1;
2162 }
15c4a640 2163 break;
f7c6d140
AP		 2164 case MSR_FAM10H_MMIO_CONF_BASE:
2165 if (data != 0) {
a737f256
CD		 2166 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2167 "0x%llx\n", data);
f7c6d140
AP		 2168 return 1;
2169 }
15c4a640 2170 break;
b5e2fec0
AG		 2171 case MSR_IA32_DEBUGCTLMSR:
2172 if (!data) {
2173 /* We support the non-activated case already */
2174 break;
2175 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2176 /* Values other than LBR and BTF are vendor-specific,
2177 thus reserved and should throw a #GP */
2178 return 1;
2179 }
a737f256
CD		 2180 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2181 __func__, data);
b5e2fec0 2182 break;
9ba075a6
AK		 2183 case 0x200 ... 0x2ff:
2184 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2185 case MSR_IA32_APICBASE:
58cb628d 2186 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2187 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2188 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2189 case MSR_IA32_TSCDEADLINE:
2190 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2191 break;
ba904635
WA		 2192 case MSR_IA32_TSC_ADJUST:
2193 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2194 if (!msr_info->host_initiated) {
d913b904 2195 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2196 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2197 }
2198 vcpu->arch.ia32_tsc_adjust_msr = data;
2199 }
2200 break;
15c4a640 2201 case MSR_IA32_MISC_ENABLE:
ad312c7c 2202 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2203 break;
11c6bffa 2204 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2205 case MSR_KVM_WALL_CLOCK:
2206 vcpu->kvm->arch.wall_clock = data;
2207 kvm_write_wall_clock(vcpu->kvm, data);
2208 break;
11c6bffa 2209 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2210 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2211 u64 gpa_offset;
54750f2c
MT		 2212 struct kvm_arch *ka = &vcpu->kvm->arch;
2213
12f9a48f 2214 kvmclock_reset(vcpu);
18068523 2215
54750f2c
MT		 2216 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2217 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2218
2219 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2220 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2221 &vcpu->requests);
2222
2223 ka->boot_vcpu_runs_old_kvmclock = tmp;
2224 }
2225
18068523 2226 vcpu->arch.time = data;
0061d53d 2227 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2228
2229 /* we verify if the enable bit is set... */
2230 if (!(data & 1))
2231 break;
2232
0b79459b 2233 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2234
0b79459b 2235 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2236 &vcpu->arch.pv_time, data & ~1ULL,
2237 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2238 vcpu->arch.pv_time_enabled = false;
2239 else
2240 vcpu->arch.pv_time_enabled = true;
32cad84f 2241
18068523
GOC		 2242 break;
2243 }
344d9588
GN		 2244 case MSR_KVM_ASYNC_PF_EN:
2245 if (kvm_pv_enable_async_pf(vcpu, data))
2246 return 1;
2247 break;
c9aaa895
GC		 2248 case MSR_KVM_STEAL_TIME:
2249
2250 if (unlikely(!sched_info_on()))
2251 return 1;
2252
2253 if (data & KVM_STEAL_RESERVED_MASK)
2254 return 1;
2255
2256 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2257 data & KVM_STEAL_VALID_BITS,
2258 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2259 return 1;
2260
2261 vcpu->arch.st.msr_val = data;
2262
2263 if (!(data & KVM_MSR_ENABLED))
2264 break;
2265
2266 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2267
2268 preempt_disable();
2269 accumulate_steal_time(vcpu);
2270 preempt_enable();
2271
2272 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2273
2274 break;
ae7a2a3f
MT		 2275 case MSR_KVM_PV_EOI_EN:
2276 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2277 return 1;
2278 break;
c9aaa895 2279
890ca9ae
HY		 2280 case MSR_IA32_MCG_CTL:
2281 case MSR_IA32_MCG_STATUS:
81760dcc 2282 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2283 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2284
2285 /* Performance counters are not protected by a CPUID bit,
2286 * so we should check all of them in the generic path for the sake of
2287 * cross vendor migration.
2288 * Writing a zero into the event select MSRs disables them,
2289 * which we perfectly emulate ;-). Any other value should be at least
2290 * reported, some guests depend on them.
2291 */
71db6023
AP		 2292 case MSR_K7_EVNTSEL0:
2293 case MSR_K7_EVNTSEL1:
2294 case MSR_K7_EVNTSEL2:
2295 case MSR_K7_EVNTSEL3:
2296 if (data != 0)
a737f256
CD		 2297 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2298 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2299 break;
2300 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2301 * so we ignore writes to make it happy.
2302 */
71db6023
AP		 2303 case MSR_K7_PERFCTR0:
2304 case MSR_K7_PERFCTR1:
2305 case MSR_K7_PERFCTR2:
2306 case MSR_K7_PERFCTR3:
a737f256
CD		 2307 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2308 "0x%x data 0x%llx\n", msr, data);
71db6023 2309 break;
5753785f
GN		 2310 case MSR_P6_PERFCTR0:
2311 case MSR_P6_PERFCTR1:
2312 pr = true;
2313 case MSR_P6_EVNTSEL0:
2314 case MSR_P6_EVNTSEL1:
2315 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2316 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2317
2318 if (pr || data != 0)
a737f256
CD		 2319 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2320 "0x%x data 0x%llx\n", msr, data);
5753785f 2321 break;
84e0cefa
JS		 2322 case MSR_K7_CLK_CTL:
2323 /*
2324 * Ignore all writes to this no longer documented MSR.
2325 * Writes are only relevant for old K7 processors,
2326 * all pre-dating SVM, but a recommended workaround from
4a969980 2327 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2328 * affected processor models on the command line, hence
2329 * the need to ignore the workaround.
2330 */
2331 break;
55cd8e5a
GN		 2332 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2333 if (kvm_hv_msr_partition_wide(msr)) {
2334 int r;
2335 mutex_lock(&vcpu->kvm->lock);
2336 r = set_msr_hyperv_pw(vcpu, msr, data);
2337 mutex_unlock(&vcpu->kvm->lock);
2338 return r;
2339 } else
2340 return set_msr_hyperv(vcpu, msr, data);
2341 break;
91c9c3ed 2342 case MSR_IA32_BBL_CR_CTL3:
2343 /* Drop writes to this legacy MSR -- see rdmsr
2344 * counterpart for further detail.
2345 */
a737f256 2346 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2347 break;
2b036c6b
BO		 2348 case MSR_AMD64_OSVW_ID_LENGTH:
2349 if (!guest_cpuid_has_osvw(vcpu))
2350 return 1;
2351 vcpu->arch.osvw.length = data;
2352 break;
2353 case MSR_AMD64_OSVW_STATUS:
2354 if (!guest_cpuid_has_osvw(vcpu))
2355 return 1;
2356 vcpu->arch.osvw.status = data;
2357 break;
15c4a640 2358 default:
ffde22ac
ES		 2359 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2360 return xen_hvm_config(vcpu, data);
f5132b01 2361 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2362 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2363 if (!ignore_msrs) {
a737f256
CD		 2364 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2365 msr, data);
ed85c068
AP		 2366 return 1;
2367 } else {
a737f256
CD		 2368 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2369 msr, data);
ed85c068
AP		 2370 break;
2371 }
15c4a640
CO		 2372 }
2373 return 0;
2374}
2375EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2376
2377
2378/*
2379 * Reads an msr value (of 'msr_index') into 'pdata'.
2380 * Returns 0 on success, non-0 otherwise.
2381 * Assumes vcpu_load() was already called.
2382 */
2383int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2384{
2385 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2386}
ff651cb6 2387EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2388
9ba075a6
AK		 2389static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2390{
0bed3b56
SY		 2391 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2392
9ba075a6
AK		 2393 if (!msr_mtrr_valid(msr))
2394 return 1;
2395
0bed3b56
SY		 2396 if (msr == MSR_MTRRdefType)
2397 *pdata = vcpu->arch.mtrr_state.def_type +
2398 (vcpu->arch.mtrr_state.enabled << 10);
2399 else if (msr == MSR_MTRRfix64K_00000)
2400 *pdata = p[0];
2401 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2402 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2403 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2404 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2405 else if (msr == MSR_IA32_CR_PAT)
2406 *pdata = vcpu->arch.pat;
2407 else { /* Variable MTRRs */
2408 int idx, is_mtrr_mask;
2409 u64 *pt;
2410
2411 idx = (msr - 0x200) / 2;
2412 is_mtrr_mask = msr - 0x200 - 2 * idx;
2413 if (!is_mtrr_mask)
2414 pt =
2415 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2416 else
2417 pt =
2418 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2419 *pdata = *pt;
2420 }
2421
9ba075a6
AK		 2422 return 0;
2423}
2424
890ca9ae 2425static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2426{
2427 u64 data;
890ca9ae
HY		 2428 u64 mcg_cap = vcpu->arch.mcg_cap;
2429 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2430
2431 switch (msr) {
15c4a640
CO		 2432 case MSR_IA32_P5_MC_ADDR:
2433 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2434 data = 0;
2435 break;
15c4a640 2436 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2437 data = vcpu->arch.mcg_cap;
2438 break;
c7ac679c 2439 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2440 if (!(mcg_cap & MCG_CTL_P))
2441 return 1;
2442 data = vcpu->arch.mcg_ctl;
2443 break;
2444 case MSR_IA32_MCG_STATUS:
2445 data = vcpu->arch.mcg_status;
2446 break;
2447 default:
2448 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2449 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2450 u32 offset = msr - MSR_IA32_MC0_CTL;
2451 data = vcpu->arch.mce_banks[offset];
2452 break;
2453 }
2454 return 1;
2455 }
2456 *pdata = data;
2457 return 0;
2458}
2459
55cd8e5a
GN		 2460static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2461{
2462 u64 data = 0;
2463 struct kvm *kvm = vcpu->kvm;
2464
2465 switch (msr) {
2466 case HV_X64_MSR_GUEST_OS_ID:
2467 data = kvm->arch.hv_guest_os_id;
2468 break;
2469 case HV_X64_MSR_HYPERCALL:
2470 data = kvm->arch.hv_hypercall;
2471 break;
e984097b
VR		 2472 case HV_X64_MSR_TIME_REF_COUNT: {
2473 data =
2474 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2475 break;
2476 }
2477 case HV_X64_MSR_REFERENCE_TSC:
2478 data = kvm->arch.hv_tsc_page;
2479 break;
55cd8e5a 2480 default:
a737f256 2481 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2482 return 1;
2483 }
2484
2485 *pdata = data;
2486 return 0;
2487}
2488
2489static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2490{
2491 u64 data = 0;
2492
2493 switch (msr) {
2494 case HV_X64_MSR_VP_INDEX: {
2495 int r;
2496 struct kvm_vcpu *v;
684851a1
TY		 2497 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2498 if (v == vcpu) {
55cd8e5a 2499 data = r;
684851a1
TY		 2500 break;
2501 }
2502 }
55cd8e5a
GN		 2503 break;
2504 }
10388a07
GN		 2505 case HV_X64_MSR_EOI:
2506 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2507 case HV_X64_MSR_ICR:
2508 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2509 case HV_X64_MSR_TPR:
2510 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2511 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2512 data = vcpu->arch.hv_vapic;
2513 break;
55cd8e5a 2514 default:
a737f256 2515 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2516 return 1;
2517 }
2518 *pdata = data;
2519 return 0;
2520}
2521
890ca9ae
HY		 2522int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2523{
2524 u64 data;
2525
2526 switch (msr) {
890ca9ae 2527 case MSR_IA32_PLATFORM_ID:
15c4a640 2528 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2529 case MSR_IA32_DEBUGCTLMSR:
2530 case MSR_IA32_LASTBRANCHFROMIP:
2531 case MSR_IA32_LASTBRANCHTOIP:
2532 case MSR_IA32_LASTINTFROMIP:
2533 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2534 case MSR_K8_SYSCFG:
2535 case MSR_K7_HWCR:
61a6bd67 2536 case MSR_VM_HSAVE_PA:
9e699624 2537 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2538 case MSR_K7_EVNTSEL1:
2539 case MSR_K7_EVNTSEL2:
2540 case MSR_K7_EVNTSEL3:
1f3ee616 2541 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2542 case MSR_K7_PERFCTR1:
2543 case MSR_K7_PERFCTR2:
2544 case MSR_K7_PERFCTR3:
1fdbd48c 2545 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2546 case MSR_AMD64_NB_CFG:
f7c6d140 2547 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2548 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2549 data = 0;
2550 break;
5753785f
GN		 2551 case MSR_P6_PERFCTR0:
2552 case MSR_P6_PERFCTR1:
2553 case MSR_P6_EVNTSEL0:
2554 case MSR_P6_EVNTSEL1:
2555 if (kvm_pmu_msr(vcpu, msr))
2556 return kvm_pmu_get_msr(vcpu, msr, pdata);
2557 data = 0;
2558 break;
742bc670
MT		 2559 case MSR_IA32_UCODE_REV:
2560 data = 0x100000000ULL;
2561 break;
9ba075a6
AK		 2562 case MSR_MTRRcap:
2563 data = 0x500 | KVM_NR_VAR_MTRR;
2564 break;
2565 case 0x200 ... 0x2ff:
2566 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2567 case 0xcd: /* fsb frequency */
2568 data = 3;
2569 break;
7b914098
JS		 2570 /*
2571 * MSR_EBC_FREQUENCY_ID
2572 * Conservative value valid for even the basic CPU models.
2573 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2574 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2575 * and 266MHz for model 3, or 4. Set Core Clock
2576 * Frequency to System Bus Frequency Ratio to 1 (bits
2577 * 31:24) even though these are only valid for CPU
2578 * models > 2, however guests may end up dividing or
2579 * multiplying by zero otherwise.
2580 */
2581 case MSR_EBC_FREQUENCY_ID:
2582 data = 1 << 24;
2583 break;
15c4a640
CO		 2584 case MSR_IA32_APICBASE:
2585 data = kvm_get_apic_base(vcpu);
2586 break;
0105d1a5
GN		 2587 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2588 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2589 break;
a3e06bbe
LJ		 2590 case MSR_IA32_TSCDEADLINE:
2591 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2592 break;
ba904635
WA		 2593 case MSR_IA32_TSC_ADJUST:
2594 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2595 break;
15c4a640 2596 case MSR_IA32_MISC_ENABLE:
ad312c7c 2597 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2598 break;
847f0ad8
AG		 2599 case MSR_IA32_PERF_STATUS:
2600 /* TSC increment by tick */
2601 data = 1000ULL;
2602 /* CPU multiplier */
2603 data |= (((uint64_t)4ULL) << 40);
2604 break;
15c4a640 2605 case MSR_EFER:
f6801dff 2606 data = vcpu->arch.efer;
15c4a640 2607 break;
18068523 2608 case MSR_KVM_WALL_CLOCK:
11c6bffa 2609 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2610 data = vcpu->kvm->arch.wall_clock;
2611 break;
2612 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2613 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2614 data = vcpu->arch.time;
2615 break;
344d9588
GN		 2616 case MSR_KVM_ASYNC_PF_EN:
2617 data = vcpu->arch.apf.msr_val;
2618 break;
c9aaa895
GC		 2619 case MSR_KVM_STEAL_TIME:
2620 data = vcpu->arch.st.msr_val;
2621 break;
1d92128f
MT		 2622 case MSR_KVM_PV_EOI_EN:
2623 data = vcpu->arch.pv_eoi.msr_val;
2624 break;
890ca9ae
HY		 2625 case MSR_IA32_P5_MC_ADDR:
2626 case MSR_IA32_P5_MC_TYPE:
2627 case MSR_IA32_MCG_CAP:
2628 case MSR_IA32_MCG_CTL:
2629 case MSR_IA32_MCG_STATUS:
81760dcc 2630 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2631 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2632 case MSR_K7_CLK_CTL:
2633 /*
2634 * Provide expected ramp-up count for K7. All other
2635 * are set to zero, indicating minimum divisors for
2636 * every field.
2637 *
2638 * This prevents guest kernels on AMD host with CPU
2639 * type 6, model 8 and higher from exploding due to
2640 * the rdmsr failing.
2641 */
2642 data = 0x20000000;
2643 break;
55cd8e5a
GN		 2644 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2645 if (kvm_hv_msr_partition_wide(msr)) {
2646 int r;
2647 mutex_lock(&vcpu->kvm->lock);
2648 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2649 mutex_unlock(&vcpu->kvm->lock);
2650 return r;
2651 } else
2652 return get_msr_hyperv(vcpu, msr, pdata);
2653 break;
91c9c3ed 2654 case MSR_IA32_BBL_CR_CTL3:
2655 /* This legacy MSR exists but isn't fully documented in current
2656 * silicon. It is however accessed by winxp in very narrow
2657 * scenarios where it sets bit #19, itself documented as
2658 * a "reserved" bit. Best effort attempt to source coherent
2659 * read data here should the balance of the register be
2660 * interpreted by the guest:
2661 *
2662 * L2 cache control register 3: 64GB range, 256KB size,
2663 * enabled, latency 0x1, configured
2664 */
2665 data = 0xbe702111;
2666 break;
2b036c6b
BO		 2667 case MSR_AMD64_OSVW_ID_LENGTH:
2668 if (!guest_cpuid_has_osvw(vcpu))
2669 return 1;
2670 data = vcpu->arch.osvw.length;
2671 break;
2672 case MSR_AMD64_OSVW_STATUS:
2673 if (!guest_cpuid_has_osvw(vcpu))
2674 return 1;
2675 data = vcpu->arch.osvw.status;
2676 break;
15c4a640 2677 default:
f5132b01
GN		 2678 if (kvm_pmu_msr(vcpu, msr))
2679 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2680 if (!ignore_msrs) {
a737f256 2681 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2682 return 1;
2683 } else {
a737f256 2684 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2685 data = 0;
2686 }
2687 break;
15c4a640
CO		 2688 }
2689 *pdata = data;
2690 return 0;
2691}
2692EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2693
313a3dc7
CO		 2694/*
2695 * Read or write a bunch of msrs. All parameters are kernel addresses.
2696 *
2697 * @return number of msrs set successfully.
2698 */
2699static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2700 struct kvm_msr_entry *entries,
2701 int (*do_msr)(struct kvm_vcpu *vcpu,
2702 unsigned index, u64 *data))
2703{
f656ce01 2704 int i, idx;
313a3dc7 2705
f656ce01 2706 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2707 for (i = 0; i < msrs->nmsrs; ++i)
2708 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2709 break;
f656ce01 2710 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2711
313a3dc7
CO		 2712 return i;
2713}
2714
2715/*
2716 * Read or write a bunch of msrs. Parameters are user addresses.
2717 *
2718 * @return number of msrs set successfully.
2719 */
2720static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2721 int (*do_msr)(struct kvm_vcpu *vcpu,
2722 unsigned index, u64 *data),
2723 int writeback)
2724{
2725 struct kvm_msrs msrs;
2726 struct kvm_msr_entry *entries;
2727 int r, n;
2728 unsigned size;
2729
2730 r = -EFAULT;
2731 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2732 goto out;
2733
2734 r = -E2BIG;
2735 if (msrs.nmsrs >= MAX_IO_MSRS)
2736 goto out;
2737
313a3dc7 2738 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2739 entries = memdup_user(user_msrs->entries, size);
2740 if (IS_ERR(entries)) {
2741 r = PTR_ERR(entries);
313a3dc7 2742 goto out;
ff5c2c03 2743 }
313a3dc7
CO		 2744
2745 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2746 if (r < 0)
2747 goto out_free;
2748
2749 r = -EFAULT;
2750 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2751 goto out_free;
2752
2753 r = n;
2754
2755out_free:
7a73c028 2756 kfree(entries);
313a3dc7
CO		 2757out:
2758 return r;
2759}
2760
784aa3d7 2761int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2762{
2763 int r;
2764
2765 switch (ext) {
2766 case KVM_CAP_IRQCHIP:
2767 case KVM_CAP_HLT:
2768 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2769 case KVM_CAP_SET_TSS_ADDR:
07716717 2770 case KVM_CAP_EXT_CPUID:
9c15bb1d 2771 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2772 case KVM_CAP_CLOCKSOURCE:
7837699f 2773 case KVM_CAP_PIT:
a28e4f5a 2774 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2775 case KVM_CAP_MP_STATE:
ed848624 2776 case KVM_CAP_SYNC_MMU:
a355c85c 2777 case KVM_CAP_USER_NMI:
52d939a0 2778 case KVM_CAP_REINJECT_CONTROL:
4925663a 2779 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2780 case KVM_CAP_IOEVENTFD:
f848a5a8 2781 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2782 case KVM_CAP_PIT2:
e9f42757 2783 case KVM_CAP_PIT_STATE2:
b927a3ce 2784 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2785 case KVM_CAP_XEN_HVM:
afbcf7ab 2786 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2787 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2788 case KVM_CAP_HYPERV:
10388a07 2789 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2790 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2791 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2792 case KVM_CAP_DEBUGREGS:
d2be1651 2793 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2794 case KVM_CAP_XSAVE:
344d9588 2795 case KVM_CAP_ASYNC_PF:
92a1f12d 2796 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2797 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2798 case KVM_CAP_READONLY_MEM:
5f66b620 2799 case KVM_CAP_HYPERV_TIME:
100943c5 2800 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2801 case KVM_CAP_TSC_DEADLINE_TIMER:
2a5bab10
AW		 2802#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2803 case KVM_CAP_ASSIGN_DEV_IRQ:
2804 case KVM_CAP_PCI_2_3:
2805#endif
018d00d2
ZX		 2806 r = 1;
2807 break;
542472b5
LV		 2808 case KVM_CAP_COALESCED_MMIO:
2809 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2810 break;
774ead3a
AK		 2811 case KVM_CAP_VAPIC:
2812 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2813 break;
f725230a 2814 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2815 r = KVM_SOFT_MAX_VCPUS;
2816 break;
2817 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2818 r = KVM_MAX_VCPUS;
2819 break;
a988b910 2820 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2821 r = KVM_USER_MEM_SLOTS;
a988b910 2822 break;
a68a6a72
MT		 2823 case KVM_CAP_PV_MMU: /* obsolete */
2824 r = 0;
2f333bcb 2825 break;
4cee4b72 2826#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2827 case KVM_CAP_IOMMU:
a1b60c1c 2828 r = iommu_present(&pci_bus_type);
62c476c7 2829 break;
4cee4b72 2830#endif
890ca9ae
HY		 2831 case KVM_CAP_MCE:
2832 r = KVM_MAX_MCE_BANKS;
2833 break;
2d5b5a66
SY		 2834 case KVM_CAP_XCRS:
2835 r = cpu_has_xsave;
2836 break;
92a1f12d
JR		 2837 case KVM_CAP_TSC_CONTROL:
2838 r = kvm_has_tsc_control;
2839 break;
018d00d2
ZX		 2840 default:
2841 r = 0;
2842 break;
2843 }
2844 return r;
2845
2846}
2847
043405e1
CO		 2848long kvm_arch_dev_ioctl(struct file *filp,
2849 unsigned int ioctl, unsigned long arg)
2850{
2851 void __user *argp = (void __user *)arg;
2852 long r;
2853
2854 switch (ioctl) {
2855 case KVM_GET_MSR_INDEX_LIST: {
2856 struct kvm_msr_list __user *user_msr_list = argp;
2857 struct kvm_msr_list msr_list;
2858 unsigned n;
2859
2860 r = -EFAULT;
2861 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2862 goto out;
2863 n = msr_list.nmsrs;
2864 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2865 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2866 goto out;
2867 r = -E2BIG;
e125e7b6 2868 if (n < msr_list.nmsrs)
043405e1
CO		 2869 goto out;
2870 r = -EFAULT;
2871 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2872 num_msrs_to_save * sizeof(u32)))
2873 goto out;
e125e7b6 2874 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2875 &emulated_msrs,
2876 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2877 goto out;
2878 r = 0;
2879 break;
2880 }
9c15bb1d
BP		 2881 case KVM_GET_SUPPORTED_CPUID:
2882 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2883 struct kvm_cpuid2 __user *cpuid_arg = argp;
2884 struct kvm_cpuid2 cpuid;
2885
2886 r = -EFAULT;
2887 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2888 goto out;
9c15bb1d
BP		 2889
2890 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2891 ioctl);
674eea0f
AK		 2892 if (r)
2893 goto out;
2894
2895 r = -EFAULT;
2896 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2897 goto out;
2898 r = 0;
2899 break;
2900 }
890ca9ae
HY		 2901 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2902 u64 mce_cap;
2903
2904 mce_cap = KVM_MCE_CAP_SUPPORTED;
2905 r = -EFAULT;
2906 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2907 goto out;
2908 r = 0;
2909 break;
2910 }
043405e1
CO		 2911 default:
2912 r = -EINVAL;
2913 }
2914out:
2915 return r;
2916}
2917
f5f48ee1
SY		 2918static void wbinvd_ipi(void *garbage)
2919{
2920 wbinvd();
2921}
2922
2923static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2924{
e0f0bbc5 2925 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2926}
2927
313a3dc7
CO		 2928void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2929{
f5f48ee1
SY		 2930 /* Address WBINVD may be executed by guest */
2931 if (need_emulate_wbinvd(vcpu)) {
2932 if (kvm_x86_ops->has_wbinvd_exit())
2933 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2934 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2935 smp_call_function_single(vcpu->cpu,
2936 wbinvd_ipi, NULL, 1);
2937 }
2938
313a3dc7 2939 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2940
0dd6a6ed
ZA		 2941 /* Apply any externally detected TSC adjustments (due to suspend) */
2942 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2943 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2944 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2945 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2946 }
8f6055cb 2947
48434c20 2948 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2949 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2950 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2951 if (tsc_delta < 0)
2952 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2953 if (check_tsc_unstable()) {
b183aa58
ZA		 2954 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2955 vcpu->arch.last_guest_tsc);
2956 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2957 vcpu->arch.tsc_catchup = 1;
c285545f 2958 }
d98d07ca
MT		 2959 /*
2960 * On a host with synchronized TSC, there is no need to update
2961 * kvmclock on vcpu->cpu migration
2962 */
2963 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2964 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2965 if (vcpu->cpu != cpu)
2966 kvm_migrate_timers(vcpu);
e48672fa 2967 vcpu->cpu = cpu;
6b7d7e76 2968 }
c9aaa895
GC		 2969
2970 accumulate_steal_time(vcpu);
2971 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2972}
2973
2974void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2975{
02daab21 2976 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2977 kvm_put_guest_fpu(vcpu);
6f526ec5 2978 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2979}
2980
313a3dc7
CO		 2981static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2982 struct kvm_lapic_state *s)
2983{
5a71785d 2984 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2985 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2986
2987 return 0;
2988}
2989
2990static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2991 struct kvm_lapic_state *s)
2992{
64eb0620 2993 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2994 update_cr8_intercept(vcpu);
313a3dc7
CO		 2995
2996 return 0;
2997}
2998
f77bc6a4
ZX		 2999static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3000 struct kvm_interrupt *irq)
3001{
02cdb50f 3002 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 3003 return -EINVAL;
3004 if (irqchip_in_kernel(vcpu->kvm))
3005 return -ENXIO;
f77bc6a4 3006
66fd3f7f 3007 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 3008 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 3009
f77bc6a4
ZX		 3010 return 0;
3011}
3012
c4abb7c9
JK		 3013static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3014{
c4abb7c9 3015 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3016
3017 return 0;
3018}
3019
b209749f
AK		 3020static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3021 struct kvm_tpr_access_ctl *tac)
3022{
3023 if (tac->flags)
3024 return -EINVAL;
3025 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3026 return 0;
3027}
3028
890ca9ae
HY		 3029static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3030 u64 mcg_cap)
3031{
3032 int r;
3033 unsigned bank_num = mcg_cap & 0xff, bank;
3034
3035 r = -EINVAL;
a9e38c3e 3036 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 3037 goto out;
3038 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3039 goto out;
3040 r = 0;
3041 vcpu->arch.mcg_cap = mcg_cap;
3042 /* Init IA32_MCG_CTL to all 1s */
3043 if (mcg_cap & MCG_CTL_P)
3044 vcpu->arch.mcg_ctl = ~(u64)0;
3045 /* Init IA32_MCi_CTL to all 1s */
3046 for (bank = 0; bank < bank_num; bank++)
3047 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3048out:
3049 return r;
3050}
3051
3052static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3053 struct kvm_x86_mce *mce)
3054{
3055 u64 mcg_cap = vcpu->arch.mcg_cap;
3056 unsigned bank_num = mcg_cap & 0xff;
3057 u64 *banks = vcpu->arch.mce_banks;
3058
3059 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3060 return -EINVAL;
3061 /*
3062 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3063 * reporting is disabled
3064 */
3065 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3066 vcpu->arch.mcg_ctl != ~(u64)0)
3067 return 0;
3068 banks += 4 * mce->bank;
3069 /*
3070 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3071 * reporting is disabled for the bank
3072 */
3073 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3074 return 0;
3075 if (mce->status & MCI_STATUS_UC) {
3076 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3077 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3078 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3079 return 0;
3080 }
3081 if (banks[1] & MCI_STATUS_VAL)
3082 mce->status |= MCI_STATUS_OVER;
3083 banks[2] = mce->addr;
3084 banks[3] = mce->misc;
3085 vcpu->arch.mcg_status = mce->mcg_status;
3086 banks[1] = mce->status;
3087 kvm_queue_exception(vcpu, MC_VECTOR);
3088 } else if (!(banks[1] & MCI_STATUS_VAL)
3089 || !(banks[1] & MCI_STATUS_UC)) {
3090 if (banks[1] & MCI_STATUS_VAL)
3091 mce->status |= MCI_STATUS_OVER;
3092 banks[2] = mce->addr;
3093 banks[3] = mce->misc;
3094 banks[1] = mce->status;
3095 } else
3096 banks[1] |= MCI_STATUS_OVER;
3097 return 0;
3098}
3099
3cfc3092
JK		 3100static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3101 struct kvm_vcpu_events *events)
3102{
7460fb4a 3103 process_nmi(vcpu);
03b82a30
JK		 3104 events->exception.injected =
3105 vcpu->arch.exception.pending &&
3106 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3107 events->exception.nr = vcpu->arch.exception.nr;
3108 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3109 events->exception.pad = 0;
3cfc3092
JK		 3110 events->exception.error_code = vcpu->arch.exception.error_code;
3111
03b82a30
JK		 3112 events->interrupt.injected =
3113 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3114 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3115 events->interrupt.soft = 0;
37ccdcbe 3116 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3117
3118 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3119 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3120 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3121 events->nmi.pad = 0;
3cfc3092 3122
66450a21 3123 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3124
dab4b911 3125 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3126 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3127 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3128}
3129
3130static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3131 struct kvm_vcpu_events *events)
3132{
dab4b911 3133 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3134 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3135 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3136 return -EINVAL;
3137
7460fb4a 3138 process_nmi(vcpu);
3cfc3092
JK		 3139 vcpu->arch.exception.pending = events->exception.injected;
3140 vcpu->arch.exception.nr = events->exception.nr;
3141 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3142 vcpu->arch.exception.error_code = events->exception.error_code;
3143
3144 vcpu->arch.interrupt.pending = events->interrupt.injected;
3145 vcpu->arch.interrupt.nr = events->interrupt.nr;
3146 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3147 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3148 kvm_x86_ops->set_interrupt_shadow(vcpu,
3149 events->interrupt.shadow);
3cfc3092
JK		 3150
3151 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3152 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3153 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3154 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3155
66450a21
JK		 3156 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3157 kvm_vcpu_has_lapic(vcpu))
3158 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3159
3842d135
AK		 3160 kvm_make_request(KVM_REQ_EVENT, vcpu);
3161
3cfc3092
JK		 3162 return 0;
3163}
3164
a1efbe77
JK		 3165static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3166 struct kvm_debugregs *dbgregs)
3167{
73aaf249
JK		 3168 unsigned long val;
3169
a1efbe77 3170 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3171 kvm_get_dr(vcpu, 6, &val);
73aaf249 3172 dbgregs->dr6 = val;
a1efbe77
JK		 3173 dbgregs->dr7 = vcpu->arch.dr7;
3174 dbgregs->flags = 0;
97e69aa6 3175 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3176}
3177
3178static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3179 struct kvm_debugregs *dbgregs)
3180{
3181 if (dbgregs->flags)
3182 return -EINVAL;
3183
a1efbe77 3184 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3185 kvm_update_dr0123(vcpu);
a1efbe77 3186 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3187 kvm_update_dr6(vcpu);
a1efbe77 3188 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3189 kvm_update_dr7(vcpu);
a1efbe77 3190
a1efbe77
JK		 3191 return 0;
3192}
3193
df1daba7
PB		 3194#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3195
3196static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3197{
7366ed77 3198 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3199 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3200 u64 valid;
3201
3202 /*
3203 * Copy legacy XSAVE area, to avoid complications with CPUID
3204 * leaves 0 and 1 in the loop below.
3205 */
3206 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3207
3208 /* Set XSTATE_BV */
3209 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3210
3211 /*
3212 * Copy each region from the possibly compacted offset to the
3213 * non-compacted offset.
3214 */
3215 valid = xstate_bv & ~XSTATE_FPSSE;
3216 while (valid) {
3217 u64 feature = valid & -valid;
3218 int index = fls64(feature) - 1;
3219 void *src = get_xsave_addr(xsave, feature);
3220
3221 if (src) {
3222 u32 size, offset, ecx, edx;
3223 cpuid_count(XSTATE_CPUID, index,
3224 &size, &offset, &ecx, &edx);
3225 memcpy(dest + offset, src, size);
3226 }
3227
3228 valid -= feature;
3229 }
3230}
3231
3232static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3233{
7366ed77 3234 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3235 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3236 u64 valid;
3237
3238 /*
3239 * Copy legacy XSAVE area, to avoid complications with CPUID
3240 * leaves 0 and 1 in the loop below.
3241 */
3242 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3243
3244 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3245 xsave->header.xfeatures = xstate_bv;
df1daba7 3246 if (cpu_has_xsaves)
3a54450b 3247 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3248
3249 /*
3250 * Copy each region from the non-compacted offset to the
3251 * possibly compacted offset.
3252 */
3253 valid = xstate_bv & ~XSTATE_FPSSE;
3254 while (valid) {
3255 u64 feature = valid & -valid;
3256 int index = fls64(feature) - 1;
3257 void *dest = get_xsave_addr(xsave, feature);
3258
3259 if (dest) {
3260 u32 size, offset, ecx, edx;
3261 cpuid_count(XSTATE_CPUID, index,
3262 &size, &offset, &ecx, &edx);
3263 memcpy(dest, src + offset, size);
3264 } else
3265 WARN_ON_ONCE(1);
3266
3267 valid -= feature;
3268 }
3269}
3270
2d5b5a66
SY		 3271static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3272 struct kvm_xsave *guest_xsave)
3273{
4344ee98 3274 if (cpu_has_xsave) {
df1daba7
PB		 3275 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3276 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3277 } else {
2d5b5a66 3278 memcpy(guest_xsave->region,
7366ed77 3279 &vcpu->arch.guest_fpu.state.fxsave,
2d5b5a66
SY		 3280 sizeof(struct i387_fxsave_struct));
3281 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3282 XSTATE_FPSSE;
3283 }
3284}
3285
3286static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3287 struct kvm_xsave *guest_xsave)
3288{
3289 u64 xstate_bv =
3290 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3291
d7876f1b
PB		 3292 if (cpu_has_xsave) {
3293 /*
3294 * Here we allow setting states that are not present in
3295 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3296 * with old userspace.
3297 */
4ff41732 3298 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3299 return -EINVAL;
df1daba7 3300 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3301 } else {
2d5b5a66
SY		 3302 if (xstate_bv & ~XSTATE_FPSSE)
3303 return -EINVAL;
7366ed77 3304 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
2d5b5a66
SY		 3305 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3306 }
3307 return 0;
3308}
3309
3310static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3311 struct kvm_xcrs *guest_xcrs)
3312{
3313 if (!cpu_has_xsave) {
3314 guest_xcrs->nr_xcrs = 0;
3315 return;
3316 }
3317
3318 guest_xcrs->nr_xcrs = 1;
3319 guest_xcrs->flags = 0;
3320 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3321 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3322}
3323
3324static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3325 struct kvm_xcrs *guest_xcrs)
3326{
3327 int i, r = 0;
3328
3329 if (!cpu_has_xsave)
3330 return -EINVAL;
3331
3332 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3333 return -EINVAL;
3334
3335 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3336 /* Only support XCR0 currently */
c67a04cb 3337 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3338 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3339 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3340 break;
3341 }
3342 if (r)
3343 r = -EINVAL;
3344 return r;
3345}
3346
1c0b28c2
EM		 3347/*
3348 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3349 * stopped by the hypervisor. This function will be called from the host only.
3350 * EINVAL is returned when the host attempts to set the flag for a guest that
3351 * does not support pv clocks.
3352 */
3353static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3354{
0b79459b 3355 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3356 return -EINVAL;
51d59c6b 3357 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3358 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3359 return 0;
3360}
3361
313a3dc7
CO		 3362long kvm_arch_vcpu_ioctl(struct file *filp,
3363 unsigned int ioctl, unsigned long arg)
3364{
3365 struct kvm_vcpu *vcpu = filp->private_data;
3366 void __user *argp = (void __user *)arg;
3367 int r;
d1ac91d8
AK		 3368 union {
3369 struct kvm_lapic_state *lapic;
3370 struct kvm_xsave *xsave;
3371 struct kvm_xcrs *xcrs;
3372 void *buffer;
3373 } u;
3374
3375 u.buffer = NULL;
313a3dc7
CO		 3376 switch (ioctl) {
3377 case KVM_GET_LAPIC: {
2204ae3c
MT		 3378 r = -EINVAL;
3379 if (!vcpu->arch.apic)
3380 goto out;
d1ac91d8 3381 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3382
b772ff36 3383 r = -ENOMEM;
d1ac91d8 3384 if (!u.lapic)
b772ff36 3385 goto out;
d1ac91d8 3386 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3387 if (r)
3388 goto out;
3389 r = -EFAULT;
d1ac91d8 3390 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3391 goto out;
3392 r = 0;
3393 break;
3394 }
3395 case KVM_SET_LAPIC: {
2204ae3c
MT		 3396 r = -EINVAL;
3397 if (!vcpu->arch.apic)
3398 goto out;
ff5c2c03 3399 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3400 if (IS_ERR(u.lapic))
3401 return PTR_ERR(u.lapic);
ff5c2c03 3402
d1ac91d8 3403 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3404 break;
3405 }
f77bc6a4
ZX		 3406 case KVM_INTERRUPT: {
3407 struct kvm_interrupt irq;
3408
3409 r = -EFAULT;
3410 if (copy_from_user(&irq, argp, sizeof irq))
3411 goto out;
3412 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3413 break;
3414 }
c4abb7c9
JK		 3415 case KVM_NMI: {
3416 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3417 break;
3418 }
313a3dc7
CO		 3419 case KVM_SET_CPUID: {
3420 struct kvm_cpuid __user *cpuid_arg = argp;
3421 struct kvm_cpuid cpuid;
3422
3423 r = -EFAULT;
3424 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3425 goto out;
3426 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3427 break;
3428 }
07716717
DK		 3429 case KVM_SET_CPUID2: {
3430 struct kvm_cpuid2 __user *cpuid_arg = argp;
3431 struct kvm_cpuid2 cpuid;
3432
3433 r = -EFAULT;
3434 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3435 goto out;
3436 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3437 cpuid_arg->entries);
07716717
DK		 3438 break;
3439 }
3440 case KVM_GET_CPUID2: {
3441 struct kvm_cpuid2 __user *cpuid_arg = argp;
3442 struct kvm_cpuid2 cpuid;
3443
3444 r = -EFAULT;
3445 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3446 goto out;
3447 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3448 cpuid_arg->entries);
07716717
DK		 3449 if (r)
3450 goto out;
3451 r = -EFAULT;
3452 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3453 goto out;
3454 r = 0;
3455 break;
3456 }
313a3dc7
CO		 3457 case KVM_GET_MSRS:
3458 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3459 break;
3460 case KVM_SET_MSRS:
3461 r = msr_io(vcpu, argp, do_set_msr, 0);
3462 break;
b209749f
AK		 3463 case KVM_TPR_ACCESS_REPORTING: {
3464 struct kvm_tpr_access_ctl tac;
3465
3466 r = -EFAULT;
3467 if (copy_from_user(&tac, argp, sizeof tac))
3468 goto out;
3469 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3470 if (r)
3471 goto out;
3472 r = -EFAULT;
3473 if (copy_to_user(argp, &tac, sizeof tac))
3474 goto out;
3475 r = 0;
3476 break;
3477 };
b93463aa
AK		 3478 case KVM_SET_VAPIC_ADDR: {
3479 struct kvm_vapic_addr va;
3480
3481 r = -EINVAL;
3482 if (!irqchip_in_kernel(vcpu->kvm))
3483 goto out;
3484 r = -EFAULT;
3485 if (copy_from_user(&va, argp, sizeof va))
3486 goto out;
fda4e2e8 3487 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3488 break;
3489 }
890ca9ae
HY		 3490 case KVM_X86_SETUP_MCE: {
3491 u64 mcg_cap;
3492
3493 r = -EFAULT;
3494 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3495 goto out;
3496 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3497 break;
3498 }
3499 case KVM_X86_SET_MCE: {
3500 struct kvm_x86_mce mce;
3501
3502 r = -EFAULT;
3503 if (copy_from_user(&mce, argp, sizeof mce))
3504 goto out;
3505 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3506 break;
3507 }
3cfc3092
JK		 3508 case KVM_GET_VCPU_EVENTS: {
3509 struct kvm_vcpu_events events;
3510
3511 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3512
3513 r = -EFAULT;
3514 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3515 break;
3516 r = 0;
3517 break;
3518 }
3519 case KVM_SET_VCPU_EVENTS: {
3520 struct kvm_vcpu_events events;
3521
3522 r = -EFAULT;
3523 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3524 break;
3525
3526 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3527 break;
3528 }
a1efbe77
JK		 3529 case KVM_GET_DEBUGREGS: {
3530 struct kvm_debugregs dbgregs;
3531
3532 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3533
3534 r = -EFAULT;
3535 if (copy_to_user(argp, &dbgregs,
3536 sizeof(struct kvm_debugregs)))
3537 break;
3538 r = 0;
3539 break;
3540 }
3541 case KVM_SET_DEBUGREGS: {
3542 struct kvm_debugregs dbgregs;
3543
3544 r = -EFAULT;
3545 if (copy_from_user(&dbgregs, argp,
3546 sizeof(struct kvm_debugregs)))
3547 break;
3548
3549 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3550 break;
3551 }
2d5b5a66 3552 case KVM_GET_XSAVE: {
d1ac91d8 3553 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3554 r = -ENOMEM;
d1ac91d8 3555 if (!u.xsave)
2d5b5a66
SY		 3556 break;
3557
d1ac91d8 3558 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3559
3560 r = -EFAULT;
d1ac91d8 3561 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3562 break;
3563 r = 0;
3564 break;
3565 }
3566 case KVM_SET_XSAVE: {
ff5c2c03 3567 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3568 if (IS_ERR(u.xsave))
3569 return PTR_ERR(u.xsave);
2d5b5a66 3570
d1ac91d8 3571 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3572 break;
3573 }
3574 case KVM_GET_XCRS: {
d1ac91d8 3575 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3576 r = -ENOMEM;
d1ac91d8 3577 if (!u.xcrs)
2d5b5a66
SY		 3578 break;
3579
d1ac91d8 3580 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3581
3582 r = -EFAULT;
d1ac91d8 3583 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3584 sizeof(struct kvm_xcrs)))
3585 break;
3586 r = 0;
3587 break;
3588 }
3589 case KVM_SET_XCRS: {
ff5c2c03 3590 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3591 if (IS_ERR(u.xcrs))
3592 return PTR_ERR(u.xcrs);
2d5b5a66 3593
d1ac91d8 3594 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3595 break;
3596 }
92a1f12d
JR		 3597 case KVM_SET_TSC_KHZ: {
3598 u32 user_tsc_khz;
3599
3600 r = -EINVAL;
92a1f12d
JR		 3601 user_tsc_khz = (u32)arg;
3602
3603 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3604 goto out;
3605
cc578287
ZA		 3606 if (user_tsc_khz == 0)
3607 user_tsc_khz = tsc_khz;
3608
3609 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3610
3611 r = 0;
3612 goto out;
3613 }
3614 case KVM_GET_TSC_KHZ: {
cc578287 3615 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3616 goto out;
3617 }
1c0b28c2
EM		 3618 case KVM_KVMCLOCK_CTRL: {
3619 r = kvm_set_guest_paused(vcpu);
3620 goto out;
3621 }
313a3dc7
CO		 3622 default:
3623 r = -EINVAL;
3624 }
3625out:
d1ac91d8 3626 kfree(u.buffer);
313a3dc7
CO		 3627 return r;
3628}
3629
5b1c1493
CO		 3630int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3631{
3632 return VM_FAULT_SIGBUS;
3633}
3634
1fe779f8
CO		 3635static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3636{
3637 int ret;
3638
3639 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3640 return -EINVAL;
1fe779f8
CO		 3641 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3642 return ret;
3643}
3644
b927a3ce
SY		 3645static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3646 u64 ident_addr)
3647{
3648 kvm->arch.ept_identity_map_addr = ident_addr;
3649 return 0;
3650}
3651
1fe779f8
CO		 3652static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3653 u32 kvm_nr_mmu_pages)
3654{
3655 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3656 return -EINVAL;
3657
79fac95e 3658 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3659
3660 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3661 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3662
79fac95e 3663 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3664 return 0;
3665}
3666
3667static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3668{
39de71ec 3669 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3670}
3671
1fe779f8
CO		 3672static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3673{
3674 int r;
3675
3676 r = 0;
3677 switch (chip->chip_id) {
3678 case KVM_IRQCHIP_PIC_MASTER:
3679 memcpy(&chip->chip.pic,
3680 &pic_irqchip(kvm)->pics[0],
3681 sizeof(struct kvm_pic_state));
3682 break;
3683 case KVM_IRQCHIP_PIC_SLAVE:
3684 memcpy(&chip->chip.pic,
3685 &pic_irqchip(kvm)->pics[1],
3686 sizeof(struct kvm_pic_state));
3687 break;
3688 case KVM_IRQCHIP_IOAPIC:
eba0226b 3689 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3690 break;
3691 default:
3692 r = -EINVAL;
3693 break;
3694 }
3695 return r;
3696}
3697
3698static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3699{
3700 int r;
3701
3702 r = 0;
3703 switch (chip->chip_id) {
3704 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3705 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3706 memcpy(&pic_irqchip(kvm)->pics[0],
3707 &chip->chip.pic,
3708 sizeof(struct kvm_pic_state));
f4f51050 3709 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3710 break;
3711 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3712 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3713 memcpy(&pic_irqchip(kvm)->pics[1],
3714 &chip->chip.pic,
3715 sizeof(struct kvm_pic_state));
f4f51050 3716 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3717 break;
3718 case KVM_IRQCHIP_IOAPIC:
eba0226b 3719 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3720 break;
3721 default:
3722 r = -EINVAL;
3723 break;
3724 }
3725 kvm_pic_update_irq(pic_irqchip(kvm));
3726 return r;
3727}
3728
e0f63cb9
SY		 3729static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3730{
3731 int r = 0;
3732
894a9c55 3733 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3734 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3735 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3736 return r;
3737}
3738
3739static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3740{
3741 int r = 0;
3742
894a9c55 3743 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3744 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3745 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3746 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3747 return r;
3748}
3749
3750static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3751{
3752 int r = 0;
3753
3754 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3755 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3756 sizeof(ps->channels));
3757 ps->flags = kvm->arch.vpit->pit_state.flags;
3758 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3759 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3760 return r;
3761}
3762
3763static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3764{
3765 int r = 0, start = 0;
3766 u32 prev_legacy, cur_legacy;
3767 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3768 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3769 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3770 if (!prev_legacy && cur_legacy)
3771 start = 1;
3772 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3773 sizeof(kvm->arch.vpit->pit_state.channels));
3774 kvm->arch.vpit->pit_state.flags = ps->flags;
3775 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3776 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3777 return r;
3778}
3779
52d939a0
MT		 3780static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3781 struct kvm_reinject_control *control)
3782{
3783 if (!kvm->arch.vpit)
3784 return -ENXIO;
894a9c55 3785 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3786 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3787 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3788 return 0;
3789}
3790
95d4c16c 3791/**
60c34612
TY		 3792 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3793 * @kvm: kvm instance
3794 * @log: slot id and address to which we copy the log
95d4c16c 3795 *
e108ff2f
PB		 3796 * Steps 1-4 below provide general overview of dirty page logging. See
3797 * kvm_get_dirty_log_protect() function description for additional details.
3798 *
3799 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3800 * always flush the TLB (step 4) even if previous step failed and the dirty
3801 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3802 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3803 * writes will be marked dirty for next log read.
95d4c16c 3804 *
60c34612
TY		 3805 * 1. Take a snapshot of the bit and clear it if needed.
3806 * 2. Write protect the corresponding page.
e108ff2f
PB		 3807 * 3. Copy the snapshot to the userspace.
3808 * 4. Flush TLB's if needed.
5bb064dc 3809 */
60c34612 3810int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3811{
60c34612 3812 bool is_dirty = false;
e108ff2f 3813 int r;
5bb064dc 3814
79fac95e 3815 mutex_lock(&kvm->slots_lock);
5bb064dc 3816
88178fd4
KH		 3817 /*
3818 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3819 */
3820 if (kvm_x86_ops->flush_log_dirty)
3821 kvm_x86_ops->flush_log_dirty(kvm);
3822
e108ff2f 3823 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3824
3825 /*
3826 * All the TLBs can be flushed out of mmu lock, see the comments in
3827 * kvm_mmu_slot_remove_write_access().
3828 */
e108ff2f 3829 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3830 if (is_dirty)
3831 kvm_flush_remote_tlbs(kvm);
3832
79fac95e 3833 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3834 return r;
3835}
3836
aa2fbe6d
YZ		 3837int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3838 bool line_status)
23d43cf9
CD		 3839{
3840 if (!irqchip_in_kernel(kvm))
3841 return -ENXIO;
3842
3843 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3844 irq_event->irq, irq_event->level,
3845 line_status);
23d43cf9
CD		 3846 return 0;
3847}
3848
1fe779f8
CO		 3849long kvm_arch_vm_ioctl(struct file *filp,
3850 unsigned int ioctl, unsigned long arg)
3851{
3852 struct kvm *kvm = filp->private_data;
3853 void __user *argp = (void __user *)arg;
367e1319 3854 int r = -ENOTTY;
f0d66275
DH		 3855 /*
3856 * This union makes it completely explicit to gcc-3.x
3857 * that these two variables' stack usage should be
3858 * combined, not added together.
3859 */
3860 union {
3861 struct kvm_pit_state ps;
e9f42757 3862 struct kvm_pit_state2 ps2;
c5ff41ce 3863 struct kvm_pit_config pit_config;
f0d66275 3864 } u;
1fe779f8
CO		 3865
3866 switch (ioctl) {
3867 case KVM_SET_TSS_ADDR:
3868 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3869 break;
b927a3ce
SY		 3870 case KVM_SET_IDENTITY_MAP_ADDR: {
3871 u64 ident_addr;
3872
3873 r = -EFAULT;
3874 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3875 goto out;
3876 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3877 break;
3878 }
1fe779f8
CO		 3879 case KVM_SET_NR_MMU_PAGES:
3880 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3881 break;
3882 case KVM_GET_NR_MMU_PAGES:
3883 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3884 break;
3ddea128
MT		 3885 case KVM_CREATE_IRQCHIP: {
3886 struct kvm_pic *vpic;
3887
3888 mutex_lock(&kvm->lock);
3889 r = -EEXIST;
3890 if (kvm->arch.vpic)
3891 goto create_irqchip_unlock;
3e515705
AK		 3892 r = -EINVAL;
3893 if (atomic_read(&kvm->online_vcpus))
3894 goto create_irqchip_unlock;
1fe779f8 3895 r = -ENOMEM;
3ddea128
MT		 3896 vpic = kvm_create_pic(kvm);
3897 if (vpic) {
1fe779f8
CO		 3898 r = kvm_ioapic_init(kvm);
3899 if (r) {
175504cd 3900 mutex_lock(&kvm->slots_lock);
72bb2fcd 3901 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3902 &vpic->dev_master);
3903 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3904 &vpic->dev_slave);
3905 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3906 &vpic->dev_eclr);
175504cd 3907 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3908 kfree(vpic);
3909 goto create_irqchip_unlock;
1fe779f8
CO		 3910 }
3911 } else
3ddea128
MT		 3912 goto create_irqchip_unlock;
3913 smp_wmb();
3914 kvm->arch.vpic = vpic;
3915 smp_wmb();
399ec807
AK		 3916 r = kvm_setup_default_irq_routing(kvm);
3917 if (r) {
175504cd 3918 mutex_lock(&kvm->slots_lock);
3ddea128 3919 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3920 kvm_ioapic_destroy(kvm);
3921 kvm_destroy_pic(kvm);
3ddea128 3922 mutex_unlock(&kvm->irq_lock);
175504cd 3923 mutex_unlock(&kvm->slots_lock);
399ec807 3924 }
3ddea128
MT		 3925 create_irqchip_unlock:
3926 mutex_unlock(&kvm->lock);
1fe779f8 3927 break;
3ddea128 3928 }
7837699f 3929 case KVM_CREATE_PIT:
c5ff41ce
JK		 3930 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3931 goto create_pit;
3932 case KVM_CREATE_PIT2:
3933 r = -EFAULT;
3934 if (copy_from_user(&u.pit_config, argp,
3935 sizeof(struct kvm_pit_config)))
3936 goto out;
3937 create_pit:
79fac95e 3938 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3939 r = -EEXIST;
3940 if (kvm->arch.vpit)
3941 goto create_pit_unlock;
7837699f 3942 r = -ENOMEM;
c5ff41ce 3943 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3944 if (kvm->arch.vpit)
3945 r = 0;
269e05e4 3946 create_pit_unlock:
79fac95e 3947 mutex_unlock(&kvm->slots_lock);
7837699f 3948 break;
1fe779f8
CO		 3949 case KVM_GET_IRQCHIP: {
3950 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3951 struct kvm_irqchip *chip;
1fe779f8 3952
ff5c2c03
SL		 3953 chip = memdup_user(argp, sizeof(*chip));
3954 if (IS_ERR(chip)) {
3955 r = PTR_ERR(chip);
1fe779f8 3956 goto out;
ff5c2c03
SL		 3957 }
3958
1fe779f8
CO		 3959 r = -ENXIO;
3960 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3961 goto get_irqchip_out;
3962 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3963 if (r)
f0d66275 3964 goto get_irqchip_out;
1fe779f8 3965 r = -EFAULT;
f0d66275
DH		 3966 if (copy_to_user(argp, chip, sizeof *chip))
3967 goto get_irqchip_out;
1fe779f8 3968 r = 0;
f0d66275
DH		 3969 get_irqchip_out:
3970 kfree(chip);
1fe779f8
CO		 3971 break;
3972 }
3973 case KVM_SET_IRQCHIP: {
3974 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3975 struct kvm_irqchip *chip;
1fe779f8 3976
ff5c2c03
SL		 3977 chip = memdup_user(argp, sizeof(*chip));
3978 if (IS_ERR(chip)) {
3979 r = PTR_ERR(chip);
1fe779f8 3980 goto out;
ff5c2c03
SL		 3981 }
3982
1fe779f8
CO		 3983 r = -ENXIO;
3984 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3985 goto set_irqchip_out;
3986 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3987 if (r)
f0d66275 3988 goto set_irqchip_out;
1fe779f8 3989 r = 0;
f0d66275
DH		 3990 set_irqchip_out:
3991 kfree(chip);
1fe779f8
CO		 3992 break;
3993 }
e0f63cb9 3994 case KVM_GET_PIT: {
e0f63cb9 3995 r = -EFAULT;
f0d66275 3996 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3997 goto out;
3998 r = -ENXIO;
3999 if (!kvm->arch.vpit)
4000 goto out;
f0d66275 4001 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4002 if (r)
4003 goto out;
4004 r = -EFAULT;
f0d66275 4005 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4006 goto out;
4007 r = 0;
4008 break;
4009 }
4010 case KVM_SET_PIT: {
e0f63cb9 4011 r = -EFAULT;
f0d66275 4012 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4013 goto out;
4014 r = -ENXIO;
4015 if (!kvm->arch.vpit)
4016 goto out;
f0d66275 4017 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4018 break;
4019 }
e9f42757
BK		 4020 case KVM_GET_PIT2: {
4021 r = -ENXIO;
4022 if (!kvm->arch.vpit)
4023 goto out;
4024 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4025 if (r)
4026 goto out;
4027 r = -EFAULT;
4028 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4029 goto out;
4030 r = 0;
4031 break;
4032 }
4033 case KVM_SET_PIT2: {
4034 r = -EFAULT;
4035 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4036 goto out;
4037 r = -ENXIO;
4038 if (!kvm->arch.vpit)
4039 goto out;
4040 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4041 break;
4042 }
52d939a0
MT		 4043 case KVM_REINJECT_CONTROL: {
4044 struct kvm_reinject_control control;
4045 r = -EFAULT;
4046 if (copy_from_user(&control, argp, sizeof(control)))
4047 goto out;
4048 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4049 break;
4050 }
ffde22ac
ES		 4051 case KVM_XEN_HVM_CONFIG: {
4052 r = -EFAULT;
4053 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4054 sizeof(struct kvm_xen_hvm_config)))
4055 goto out;
4056 r = -EINVAL;
4057 if (kvm->arch.xen_hvm_config.flags)
4058 goto out;
4059 r = 0;
4060 break;
4061 }
afbcf7ab 4062 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4063 struct kvm_clock_data user_ns;
4064 u64 now_ns;
4065 s64 delta;
4066
4067 r = -EFAULT;
4068 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4069 goto out;
4070
4071 r = -EINVAL;
4072 if (user_ns.flags)
4073 goto out;
4074
4075 r = 0;
395c6b0a 4076 local_irq_disable();
759379dd 4077 now_ns = get_kernel_ns();
afbcf7ab 4078 delta = user_ns.clock - now_ns;
395c6b0a 4079 local_irq_enable();
afbcf7ab 4080 kvm->arch.kvmclock_offset = delta;
2e762ff7 4081 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4082 break;
4083 }
4084 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4085 struct kvm_clock_data user_ns;
4086 u64 now_ns;
4087
395c6b0a 4088 local_irq_disable();
759379dd 4089 now_ns = get_kernel_ns();
afbcf7ab 4090 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4091 local_irq_enable();
afbcf7ab 4092 user_ns.flags = 0;
97e69aa6 4093 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4094
4095 r = -EFAULT;
4096 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4097 goto out;
4098 r = 0;
4099 break;
4100 }
4101
1fe779f8 4102 default:
c274e03a 4103 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4104 }
4105out:
4106 return r;
4107}
4108
a16b043c 4109static void kvm_init_msr_list(void)
043405e1
CO		 4110{
4111 u32 dummy[2];
4112 unsigned i, j;
4113
e3267cbb
GC		 4114 /* skip the first msrs in the list. KVM-specific */
4115 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4116 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4117 continue;
93c4adc7
PB		 4118
4119 /*
4120 * Even MSRs that are valid in the host may not be exposed
4121 * to the guests in some cases. We could work around this
4122 * in VMX with the generic MSR save/load machinery, but it
4123 * is not really worthwhile since it will really only
4124 * happen with nested virtualization.
4125 */
4126 switch (msrs_to_save[i]) {
4127 case MSR_IA32_BNDCFGS:
4128 if (!kvm_x86_ops->mpx_supported())
4129 continue;
4130 break;
4131 default:
4132 break;
4133 }
4134
043405e1
CO		 4135 if (j < i)
4136 msrs_to_save[j] = msrs_to_save[i];
4137 j++;
4138 }
4139 num_msrs_to_save = j;
4140}
4141
bda9020e
MT		 4142static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4143 const void *v)
bbd9b64e 4144{
70252a10
AK		 4145 int handled = 0;
4146 int n;
4147
4148 do {
4149 n = min(len, 8);
4150 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4151 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4152 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4153 break;
4154 handled += n;
4155 addr += n;
4156 len -= n;
4157 v += n;
4158 } while (len);
bbd9b64e 4159
70252a10 4160 return handled;
bbd9b64e
CO		 4161}
4162
bda9020e 4163static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4164{
70252a10
AK		 4165 int handled = 0;
4166 int n;
4167
4168 do {
4169 n = min(len, 8);
4170 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4171 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4172 addr, n, v))
4173 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4174 break;
4175 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4176 handled += n;
4177 addr += n;
4178 len -= n;
4179 v += n;
4180 } while (len);
bbd9b64e 4181
70252a10 4182 return handled;
bbd9b64e
CO		 4183}
4184
2dafc6c2
GN		 4185static void kvm_set_segment(struct kvm_vcpu *vcpu,
4186 struct kvm_segment *var, int seg)
4187{
4188 kvm_x86_ops->set_segment(vcpu, var, seg);
4189}
4190
4191void kvm_get_segment(struct kvm_vcpu *vcpu,
4192 struct kvm_segment *var, int seg)
4193{
4194 kvm_x86_ops->get_segment(vcpu, var, seg);
4195}
4196
54987b7a
PB		 4197gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4198 struct x86_exception *exception)
02f59dc9
JR		 4199{
4200 gpa_t t_gpa;
02f59dc9
JR		 4201
4202 BUG_ON(!mmu_is_nested(vcpu));
4203
4204 /* NPT walks are always user-walks */
4205 access |= PFERR_USER_MASK;
54987b7a 4206 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4207
4208 return t_gpa;
4209}
4210
ab9ae313
AK		 4211gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4212 struct x86_exception *exception)
1871c602
GN		 4213{
4214 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4215 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4216}
4217
ab9ae313
AK		 4218 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4219 struct x86_exception *exception)
1871c602
GN		 4220{
4221 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4222 access |= PFERR_FETCH_MASK;
ab9ae313 4223 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4224}
4225
ab9ae313
AK		 4226gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4227 struct x86_exception *exception)
1871c602
GN		 4228{
4229 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4230 access |= PFERR_WRITE_MASK;
ab9ae313 4231 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4232}
4233
4234/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4235gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4236 struct x86_exception *exception)
1871c602 4237{
ab9ae313 4238 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4239}
4240
4241static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4242 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4243 struct x86_exception *exception)
bbd9b64e
CO		 4244{
4245 void *data = val;
10589a46 4246 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4247
4248 while (bytes) {
14dfe855 4249 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4250 exception);
bbd9b64e 4251 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4252 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4253 int ret;
4254
bcc55cba 4255 if (gpa == UNMAPPED_GVA)
ab9ae313 4256 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4257 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4258 offset, toread);
10589a46 4259 if (ret < 0) {
c3cd7ffa 4260 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4261 goto out;
4262 }
bbd9b64e 4263
77c2002e
IE		 4264 bytes -= toread;
4265 data += toread;
4266 addr += toread;
bbd9b64e 4267 }
10589a46 4268out:
10589a46 4269 return r;
bbd9b64e 4270}
77c2002e 4271
1871c602 4272/* used for instruction fetching */
0f65dd70
AK		 4273static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4274 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4275 struct x86_exception *exception)
1871c602 4276{
0f65dd70 4277 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4278 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4279 unsigned offset;
4280 int ret;
0f65dd70 4281
44583cba
PB		 4282 /* Inline kvm_read_guest_virt_helper for speed. */
4283 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4284 exception);
4285 if (unlikely(gpa == UNMAPPED_GVA))
4286 return X86EMUL_PROPAGATE_FAULT;
4287
4288 offset = addr & (PAGE_SIZE-1);
4289 if (WARN_ON(offset + bytes > PAGE_SIZE))
4290 bytes = (unsigned)PAGE_SIZE - offset;
4291 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4292 offset, bytes);
4293 if (unlikely(ret < 0))
4294 return X86EMUL_IO_NEEDED;
4295
4296 return X86EMUL_CONTINUE;
1871c602
GN		 4297}
4298
064aea77 4299int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4300 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4301 struct x86_exception *exception)
1871c602 4302{
0f65dd70 4303 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4304 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4305
1871c602 4306 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4307 exception);
1871c602 4308}
064aea77 4309EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4310
0f65dd70
AK		 4311static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4312 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4313 struct x86_exception *exception)
1871c602 4314{
0f65dd70 4315 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4316 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4317}
4318
6a4d7550 4319int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4320 gva_t addr, void *val,
2dafc6c2 4321 unsigned int bytes,
bcc55cba 4322 struct x86_exception *exception)
77c2002e 4323{
0f65dd70 4324 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4325 void *data = val;
4326 int r = X86EMUL_CONTINUE;
4327
4328 while (bytes) {
14dfe855
JR		 4329 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4330 PFERR_WRITE_MASK,
ab9ae313 4331 exception);
77c2002e
IE		 4332 unsigned offset = addr & (PAGE_SIZE-1);
4333 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4334 int ret;
4335
bcc55cba 4336 if (gpa == UNMAPPED_GVA)
ab9ae313 4337 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4338 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4339 if (ret < 0) {
c3cd7ffa 4340 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4341 goto out;
4342 }
4343
4344 bytes -= towrite;
4345 data += towrite;
4346 addr += towrite;
4347 }
4348out:
4349 return r;
4350}
6a4d7550 4351EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4352
af7cc7d1
XG		 4353static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4354 gpa_t *gpa, struct x86_exception *exception,
4355 bool write)
4356{
97d64b78
AK		 4357 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4358 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4359
97d64b78 4360 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4361 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4362 vcpu->arch.access, access)) {
bebb106a
XG		 4363 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4364 (gva & (PAGE_SIZE - 1));
4f022648 4365 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4366 return 1;
4367 }
4368
af7cc7d1
XG		 4369 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4370
4371 if (*gpa == UNMAPPED_GVA)
4372 return -1;
4373
4374 /* For APIC access vmexit */
4375 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4376 return 1;
4377
4f022648
XG		 4378 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4379 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4380 return 1;
4f022648 4381 }
bebb106a 4382
af7cc7d1
XG		 4383 return 0;
4384}
4385
3200f405 4386int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4387 const void *val, int bytes)
bbd9b64e
CO		 4388{
4389 int ret;
4390
4391 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4392 if (ret < 0)
bbd9b64e 4393 return 0;
f57f2ef5 4394 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4395 return 1;
4396}
4397
77d197b2
XG		 4398struct read_write_emulator_ops {
4399 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4400 int bytes);
4401 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4402 void *val, int bytes);
4403 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4404 int bytes, void *val);
4405 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4406 void *val, int bytes);
4407 bool write;
4408};
4409
4410static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4411{
4412 if (vcpu->mmio_read_completed) {
77d197b2 4413 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4414 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4415 vcpu->mmio_read_completed = 0;
4416 return 1;
4417 }
4418
4419 return 0;
4420}
4421
4422static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4423 void *val, int bytes)
4424{
4425 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4426}
4427
4428static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4429 void *val, int bytes)
4430{
4431 return emulator_write_phys(vcpu, gpa, val, bytes);
4432}
4433
4434static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4435{
4436 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4437 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4438}
4439
4440static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4441 void *val, int bytes)
4442{
4443 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4444 return X86EMUL_IO_NEEDED;
4445}
4446
4447static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4448 void *val, int bytes)
4449{
f78146b0
AK		 4450 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4451
87da7e66 4452 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4453 return X86EMUL_CONTINUE;
4454}
4455
0fbe9b0b 4456static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4457 .read_write_prepare = read_prepare,
4458 .read_write_emulate = read_emulate,
4459 .read_write_mmio = vcpu_mmio_read,
4460 .read_write_exit_mmio = read_exit_mmio,
4461};
4462
0fbe9b0b 4463static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4464 .read_write_emulate = write_emulate,
4465 .read_write_mmio = write_mmio,
4466 .read_write_exit_mmio = write_exit_mmio,
4467 .write = true,
4468};
4469
22388a3c
XG		 4470static int emulator_read_write_onepage(unsigned long addr, void *val,
4471 unsigned int bytes,
4472 struct x86_exception *exception,
4473 struct kvm_vcpu *vcpu,
0fbe9b0b 4474 const struct read_write_emulator_ops *ops)
bbd9b64e 4475{
af7cc7d1
XG		 4476 gpa_t gpa;
4477 int handled, ret;
22388a3c 4478 bool write = ops->write;
f78146b0 4479 struct kvm_mmio_fragment *frag;
10589a46 4480
22388a3c 4481 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4482
af7cc7d1 4483 if (ret < 0)
bbd9b64e 4484 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4485
4486 /* For APIC access vmexit */
af7cc7d1 4487 if (ret)
bbd9b64e
CO		 4488 goto mmio;
4489
22388a3c 4490 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4491 return X86EMUL_CONTINUE;
4492
4493mmio:
4494 /*
4495 * Is this MMIO handled locally?
4496 */
22388a3c 4497 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4498 if (handled == bytes)
bbd9b64e 4499 return X86EMUL_CONTINUE;
bbd9b64e 4500
70252a10
AK		 4501 gpa += handled;
4502 bytes -= handled;
4503 val += handled;
4504
87da7e66
XG		 4505 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4506 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4507 frag->gpa = gpa;
4508 frag->data = val;
4509 frag->len = bytes;
f78146b0 4510 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4511}
4512
52eb5a6d
XL		 4513static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4514 unsigned long addr,
22388a3c
XG		 4515 void *val, unsigned int bytes,
4516 struct x86_exception *exception,
0fbe9b0b 4517 const struct read_write_emulator_ops *ops)
bbd9b64e 4518{
0f65dd70 4519 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4520 gpa_t gpa;
4521 int rc;
4522
4523 if (ops->read_write_prepare &&
4524 ops->read_write_prepare(vcpu, val, bytes))
4525 return X86EMUL_CONTINUE;
4526
4527 vcpu->mmio_nr_fragments = 0;
0f65dd70 4528
bbd9b64e
CO		 4529 /* Crossing a page boundary? */
4530 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4531 int now;
bbd9b64e
CO		 4532
4533 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4534 rc = emulator_read_write_onepage(addr, val, now, exception,
4535 vcpu, ops);
4536
bbd9b64e
CO		 4537 if (rc != X86EMUL_CONTINUE)
4538 return rc;
4539 addr += now;
bac15531
NA		 4540 if (ctxt->mode != X86EMUL_MODE_PROT64)
4541 addr = (u32)addr;
bbd9b64e
CO		 4542 val += now;
4543 bytes -= now;
4544 }
22388a3c 4545
f78146b0
AK		 4546 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4547 vcpu, ops);
4548 if (rc != X86EMUL_CONTINUE)
4549 return rc;
4550
4551 if (!vcpu->mmio_nr_fragments)
4552 return rc;
4553
4554 gpa = vcpu->mmio_fragments[0].gpa;
4555
4556 vcpu->mmio_needed = 1;
4557 vcpu->mmio_cur_fragment = 0;
4558
87da7e66 4559 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4560 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4561 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4562 vcpu->run->mmio.phys_addr = gpa;
4563
4564 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4565}
4566
4567static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4568 unsigned long addr,
4569 void *val,
4570 unsigned int bytes,
4571 struct x86_exception *exception)
4572{
4573 return emulator_read_write(ctxt, addr, val, bytes,
4574 exception, &read_emultor);
4575}
4576
52eb5a6d 4577static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4578 unsigned long addr,
4579 const void *val,
4580 unsigned int bytes,
4581 struct x86_exception *exception)
4582{
4583 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4584 exception, &write_emultor);
bbd9b64e 4585}
bbd9b64e 4586
daea3e73
AK		 4587#define CMPXCHG_TYPE(t, ptr, old, new) \
4588 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4589
4590#ifdef CONFIG_X86_64
4591# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4592#else
4593# define CMPXCHG64(ptr, old, new) \
9749a6c0 4594 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4595#endif
4596
0f65dd70
AK		 4597static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4598 unsigned long addr,
bbd9b64e
CO		 4599 const void *old,
4600 const void *new,
4601 unsigned int bytes,
0f65dd70 4602 struct x86_exception *exception)
bbd9b64e 4603{
0f65dd70 4604 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4605 gpa_t gpa;
4606 struct page *page;
4607 char *kaddr;
4608 bool exchanged;
2bacc55c 4609
daea3e73
AK		 4610 /* guests cmpxchg8b have to be emulated atomically */
4611 if (bytes > 8 || (bytes & (bytes - 1)))
4612 goto emul_write;
10589a46 4613
daea3e73 4614 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4615
daea3e73
AK		 4616 if (gpa == UNMAPPED_GVA ||
4617 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4618 goto emul_write;
2bacc55c 4619
daea3e73
AK		 4620 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4621 goto emul_write;
72dc67a6 4622
daea3e73 4623 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4624 if (is_error_page(page))
c19b8bd6 4625 goto emul_write;
72dc67a6 4626
8fd75e12 4627 kaddr = kmap_atomic(page);
daea3e73
AK		 4628 kaddr += offset_in_page(gpa);
4629 switch (bytes) {
4630 case 1:
4631 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4632 break;
4633 case 2:
4634 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4635 break;
4636 case 4:
4637 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4638 break;
4639 case 8:
4640 exchanged = CMPXCHG64(kaddr, old, new);
4641 break;
4642 default:
4643 BUG();
2bacc55c 4644 }
8fd75e12 4645 kunmap_atomic(kaddr);
daea3e73
AK		 4646 kvm_release_page_dirty(page);
4647
4648 if (!exchanged)
4649 return X86EMUL_CMPXCHG_FAILED;
4650
d3714010 4651 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4652 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4653
4654 return X86EMUL_CONTINUE;
4a5f48f6 4655
3200f405 4656emul_write:
daea3e73 4657 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4658
0f65dd70 4659 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4660}
4661
cf8f70bf
GN		 4662static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4663{
4664 /* TODO: String I/O for in kernel device */
4665 int r;
4666
4667 if (vcpu->arch.pio.in)
e32edf4f 4668 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4669 vcpu->arch.pio.size, pd);
4670 else
e32edf4f 4671 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4672 vcpu->arch.pio.port, vcpu->arch.pio.size,
4673 pd);
4674 return r;
4675}
4676
6f6fbe98
XG		 4677static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4678 unsigned short port, void *val,
4679 unsigned int count, bool in)
cf8f70bf 4680{
cf8f70bf 4681 vcpu->arch.pio.port = port;
6f6fbe98 4682 vcpu->arch.pio.in = in;
7972995b 4683 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4684 vcpu->arch.pio.size = size;
4685
4686 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4687 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4688 return 1;
4689 }
4690
4691 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4692 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4693 vcpu->run->io.size = size;
4694 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4695 vcpu->run->io.count = count;
4696 vcpu->run->io.port = port;
4697
4698 return 0;
4699}
4700
6f6fbe98
XG		 4701static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4702 int size, unsigned short port, void *val,
4703 unsigned int count)
cf8f70bf 4704{
ca1d4a9e 4705 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4706 int ret;
ca1d4a9e 4707
6f6fbe98
XG		 4708 if (vcpu->arch.pio.count)
4709 goto data_avail;
cf8f70bf 4710
6f6fbe98
XG		 4711 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4712 if (ret) {
4713data_avail:
4714 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4715 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4716 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4717 return 1;
4718 }
4719
cf8f70bf
GN		 4720 return 0;
4721}
4722
6f6fbe98
XG		 4723static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4724 int size, unsigned short port,
4725 const void *val, unsigned int count)
4726{
4727 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4728
4729 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4730 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4731 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4732}
4733
bbd9b64e
CO		 4734static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4735{
4736 return kvm_x86_ops->get_segment_base(vcpu, seg);
4737}
4738
3cb16fe7 4739static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4740{
3cb16fe7 4741 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4742}
4743
5cb56059 4744int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4745{
4746 if (!need_emulate_wbinvd(vcpu))
4747 return X86EMUL_CONTINUE;
4748
4749 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4750 int cpu = get_cpu();
4751
4752 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4753 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4754 wbinvd_ipi, NULL, 1);
2eec7343 4755 put_cpu();
f5f48ee1 4756 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4757 } else
4758 wbinvd();
f5f48ee1
SY		 4759 return X86EMUL_CONTINUE;
4760}
5cb56059
JS		 4761
4762int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4763{
4764 kvm_x86_ops->skip_emulated_instruction(vcpu);
4765 return kvm_emulate_wbinvd_noskip(vcpu);
4766}
f5f48ee1
SY		 4767EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4768
5cb56059
JS		 4769
4770
bcaf5cc5
AK		 4771static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4772{
5cb56059 4773 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4774}
4775
52eb5a6d
XL		 4776static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4777 unsigned long *dest)
bbd9b64e 4778{
16f8a6f9 4779 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4780}
4781
52eb5a6d
XL		 4782static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4783 unsigned long value)
bbd9b64e 4784{
338dbc97 4785
717746e3 4786 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4787}
4788
52a46617 4789static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4790{
52a46617 4791 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4792}
4793
717746e3 4794static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4795{
717746e3 4796 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4797 unsigned long value;
4798
4799 switch (cr) {
4800 case 0:
4801 value = kvm_read_cr0(vcpu);
4802 break;
4803 case 2:
4804 value = vcpu->arch.cr2;
4805 break;
4806 case 3:
9f8fe504 4807 value = kvm_read_cr3(vcpu);
52a46617
GN		 4808 break;
4809 case 4:
4810 value = kvm_read_cr4(vcpu);
4811 break;
4812 case 8:
4813 value = kvm_get_cr8(vcpu);
4814 break;
4815 default:
a737f256 4816 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4817 return 0;
4818 }
4819
4820 return value;
4821}
4822
717746e3 4823static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4824{
717746e3 4825 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4826 int res = 0;
4827
52a46617
GN		 4828 switch (cr) {
4829 case 0:
49a9b07e 4830 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4831 break;
4832 case 2:
4833 vcpu->arch.cr2 = val;
4834 break;
4835 case 3:
2390218b 4836 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4837 break;
4838 case 4:
a83b29c6 4839 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4840 break;
4841 case 8:
eea1cff9 4842 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4843 break;
4844 default:
a737f256 4845 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4846 res = -1;
52a46617 4847 }
0f12244f
GN		 4848
4849 return res;
52a46617
GN		 4850}
4851
717746e3 4852static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4853{
717746e3 4854 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4855}
4856
4bff1e86 4857static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4858{
4bff1e86 4859 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4860}
4861
4bff1e86 4862static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4863{
4bff1e86 4864 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4865}
4866
1ac9d0cf
AK		 4867static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4868{
4869 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4870}
4871
4872static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4873{
4874 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4875}
4876
4bff1e86
AK		 4877static unsigned long emulator_get_cached_segment_base(
4878 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4879{
4bff1e86 4880 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4881}
4882
1aa36616
AK		 4883static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4884 struct desc_struct *desc, u32 *base3,
4885 int seg)
2dafc6c2
GN		 4886{
4887 struct kvm_segment var;
4888
4bff1e86 4889 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4890 *selector = var.selector;
2dafc6c2 4891
378a8b09
GN		 4892 if (var.unusable) {
4893 memset(desc, 0, sizeof(*desc));
2dafc6c2 4894 return false;
378a8b09 4895 }
2dafc6c2
GN		 4896
4897 if (var.g)
4898 var.limit >>= 12;
4899 set_desc_limit(desc, var.limit);
4900 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4901#ifdef CONFIG_X86_64
4902 if (base3)
4903 *base3 = var.base >> 32;
4904#endif
2dafc6c2
GN		 4905 desc->type = var.type;
4906 desc->s = var.s;
4907 desc->dpl = var.dpl;
4908 desc->p = var.present;
4909 desc->avl = var.avl;
4910 desc->l = var.l;
4911 desc->d = var.db;
4912 desc->g = var.g;
4913
4914 return true;
4915}
4916
1aa36616
AK		 4917static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4918 struct desc_struct *desc, u32 base3,
4919 int seg)
2dafc6c2 4920{
4bff1e86 4921 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4922 struct kvm_segment var;
4923
1aa36616 4924 var.selector = selector;
2dafc6c2 4925 var.base = get_desc_base(desc);
5601d05b
GN		 4926#ifdef CONFIG_X86_64
4927 var.base |= ((u64)base3) << 32;
4928#endif
2dafc6c2
GN		 4929 var.limit = get_desc_limit(desc);
4930 if (desc->g)
4931 var.limit = (var.limit << 12) | 0xfff;
4932 var.type = desc->type;
2dafc6c2
GN		 4933 var.dpl = desc->dpl;
4934 var.db = desc->d;
4935 var.s = desc->s;
4936 var.l = desc->l;
4937 var.g = desc->g;
4938 var.avl = desc->avl;
4939 var.present = desc->p;
4940 var.unusable = !var.present;
4941 var.padding = 0;
4942
4943 kvm_set_segment(vcpu, &var, seg);
4944 return;
4945}
4946
717746e3
AK		 4947static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4948 u32 msr_index, u64 *pdata)
4949{
4950 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4951}
4952
4953static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4954 u32 msr_index, u64 data)
4955{
8fe8ab46
WA		 4956 struct msr_data msr;
4957
4958 msr.data = data;
4959 msr.index = msr_index;
4960 msr.host_initiated = false;
4961 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4962}
4963
67f4d428
NA		 4964static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4965 u32 pmc)
4966{
4967 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4968}
4969
222d21aa
AK		 4970static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4971 u32 pmc, u64 *pdata)
4972{
4973 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4974}
4975
6c3287f7
AK		 4976static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4977{
4978 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4979}
4980
5037f6f3
AK		 4981static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4982{
4983 preempt_disable();
5197b808 4984 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4985 /*
4986 * CR0.TS may reference the host fpu state, not the guest fpu state,
4987 * so it may be clear at this point.
4988 */
4989 clts();
4990}
4991
4992static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4993{
4994 preempt_enable();
4995}
4996
2953538e 4997static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4998 struct x86_instruction_info *info,
c4f035c6
AK		 4999 enum x86_intercept_stage stage)
5000{
2953538e 5001 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5002}
5003
0017f93a 5004static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5005 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5006{
0017f93a 5007 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5008}
5009
dd856efa
AK		 5010static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5011{
5012 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5013}
5014
5015static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5016{
5017 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5018}
5019
801806d9
NA		 5020static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5021{
5022 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5023}
5024
0225fb50 5025static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5026 .read_gpr = emulator_read_gpr,
5027 .write_gpr = emulator_write_gpr,
1871c602 5028 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5029 .write_std = kvm_write_guest_virt_system,
1871c602 5030 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5031 .read_emulated = emulator_read_emulated,
5032 .write_emulated = emulator_write_emulated,
5033 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5034 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5035 .pio_in_emulated = emulator_pio_in_emulated,
5036 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5037 .get_segment = emulator_get_segment,
5038 .set_segment = emulator_set_segment,
5951c442 5039 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5040 .get_gdt = emulator_get_gdt,
160ce1f1 5041 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5042 .set_gdt = emulator_set_gdt,
5043 .set_idt = emulator_set_idt,
52a46617
GN		 5044 .get_cr = emulator_get_cr,
5045 .set_cr = emulator_set_cr,
9c537244 5046 .cpl = emulator_get_cpl,
35aa5375
GN		 5047 .get_dr = emulator_get_dr,
5048 .set_dr = emulator_set_dr,
717746e3
AK		 5049 .set_msr = emulator_set_msr,
5050 .get_msr = emulator_get_msr,
67f4d428 5051 .check_pmc = emulator_check_pmc,
222d21aa 5052 .read_pmc = emulator_read_pmc,
6c3287f7 5053 .halt = emulator_halt,
bcaf5cc5 5054 .wbinvd = emulator_wbinvd,
d6aa1000 5055 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5056 .get_fpu = emulator_get_fpu,
5057 .put_fpu = emulator_put_fpu,
c4f035c6 5058 .intercept = emulator_intercept,
bdb42f5a 5059 .get_cpuid = emulator_get_cpuid,
801806d9 5060 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5061};
5062
95cb2295
GN		 5063static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5064{
37ccdcbe 5065 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5066 /*
5067 * an sti; sti; sequence only disable interrupts for the first
5068 * instruction. So, if the last instruction, be it emulated or
5069 * not, left the system with the INT_STI flag enabled, it
5070 * means that the last instruction is an sti. We should not
5071 * leave the flag on in this case. The same goes for mov ss
5072 */
37ccdcbe
PB		 5073 if (int_shadow & mask)
5074 mask = 0;
6addfc42 5075 if (unlikely(int_shadow || mask)) {
95cb2295 5076 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5077 if (!mask)
5078 kvm_make_request(KVM_REQ_EVENT, vcpu);
5079 }
95cb2295
GN		 5080}
5081
ef54bcfe 5082static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5083{
5084 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5085 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5086 return kvm_propagate_fault(vcpu, &ctxt->exception);
5087
5088 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5089 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5090 ctxt->exception.error_code);
54b8486f 5091 else
da9cb575 5092 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5093 return false;
54b8486f
GN		 5094}
5095
8ec4722d
MG		 5096static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5097{
adf52235 5098 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5099 int cs_db, cs_l;
5100
8ec4722d
MG		 5101 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5102
adf52235
TY		 5103 ctxt->eflags = kvm_get_rflags(vcpu);
5104 ctxt->eip = kvm_rip_read(vcpu);
5105 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5106 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5107 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5108 cs_db ? X86EMUL_MODE_PROT32 :
5109 X86EMUL_MODE_PROT16;
5110 ctxt->guest_mode = is_guest_mode(vcpu);
5111
dd856efa 5112 init_decode_cache(ctxt);
7ae441ea 5113 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5114}
5115
71f9833b 5116int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5117{
9d74191a 5118 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5119 int ret;
5120
5121 init_emulate_ctxt(vcpu);
5122
9dac77fa
AK		 5123 ctxt->op_bytes = 2;
5124 ctxt->ad_bytes = 2;
5125 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5126 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5127
5128 if (ret != X86EMUL_CONTINUE)
5129 return EMULATE_FAIL;
5130
9dac77fa 5131 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5132 kvm_rip_write(vcpu, ctxt->eip);
5133 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5134
5135 if (irq == NMI_VECTOR)
7460fb4a 5136 vcpu->arch.nmi_pending = 0;
63995653
MG		 5137 else
5138 vcpu->arch.interrupt.pending = false;
5139
5140 return EMULATE_DONE;
5141}
5142EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5143
6d77dbfc
GN		 5144static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5145{
fc3a9157
JR		 5146 int r = EMULATE_DONE;
5147
6d77dbfc
GN		 5148 ++vcpu->stat.insn_emulation_fail;
5149 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5150 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5151 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5152 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5153 vcpu->run->internal.ndata = 0;
5154 r = EMULATE_FAIL;
5155 }
6d77dbfc 5156 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5157
5158 return r;
6d77dbfc
GN		 5159}
5160
93c05d3e 5161static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5162 bool write_fault_to_shadow_pgtable,
5163 int emulation_type)
a6f177ef 5164{
95b3cf69 5165 gpa_t gpa = cr2;
8e3d9d06 5166 pfn_t pfn;
a6f177ef 5167
991eebf9
GN		 5168 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5169 return false;
5170
95b3cf69
XG		 5171 if (!vcpu->arch.mmu.direct_map) {
5172 /*
5173 * Write permission should be allowed since only
5174 * write access need to be emulated.
5175 */
5176 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5177
95b3cf69
XG		 5178 /*
5179 * If the mapping is invalid in guest, let cpu retry
5180 * it to generate fault.
5181 */
5182 if (gpa == UNMAPPED_GVA)
5183 return true;
5184 }
a6f177ef 5185
8e3d9d06
XG		 5186 /*
5187 * Do not retry the unhandleable instruction if it faults on the
5188 * readonly host memory, otherwise it will goto a infinite loop:
5189 * retry instruction -> write #PF -> emulation fail -> retry
5190 * instruction -> ...
5191 */
5192 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5193
5194 /*
5195 * If the instruction failed on the error pfn, it can not be fixed,
5196 * report the error to userspace.
5197 */
5198 if (is_error_noslot_pfn(pfn))
5199 return false;
5200
5201 kvm_release_pfn_clean(pfn);
5202
5203 /* The instructions are well-emulated on direct mmu. */
5204 if (vcpu->arch.mmu.direct_map) {
5205 unsigned int indirect_shadow_pages;
5206
5207 spin_lock(&vcpu->kvm->mmu_lock);
5208 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5209 spin_unlock(&vcpu->kvm->mmu_lock);
5210
5211 if (indirect_shadow_pages)
5212 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5213
a6f177ef 5214 return true;
8e3d9d06 5215 }
a6f177ef 5216
95b3cf69
XG		 5217 /*
5218 * if emulation was due to access to shadowed page table
5219 * and it failed try to unshadow page and re-enter the
5220 * guest to let CPU execute the instruction.
5221 */
5222 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5223
5224 /*
5225 * If the access faults on its page table, it can not
5226 * be fixed by unprotecting shadow page and it should
5227 * be reported to userspace.
5228 */
5229 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5230}
5231
1cb3f3ae
XG		 5232static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5233 unsigned long cr2, int emulation_type)
5234{
5235 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5236 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5237
5238 last_retry_eip = vcpu->arch.last_retry_eip;
5239 last_retry_addr = vcpu->arch.last_retry_addr;
5240
5241 /*
5242 * If the emulation is caused by #PF and it is non-page_table
5243 * writing instruction, it means the VM-EXIT is caused by shadow
5244 * page protected, we can zap the shadow page and retry this
5245 * instruction directly.
5246 *
5247 * Note: if the guest uses a non-page-table modifying instruction
5248 * on the PDE that points to the instruction, then we will unmap
5249 * the instruction and go to an infinite loop. So, we cache the
5250 * last retried eip and the last fault address, if we meet the eip
5251 * and the address again, we can break out of the potential infinite
5252 * loop.
5253 */
5254 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5255
5256 if (!(emulation_type & EMULTYPE_RETRY))
5257 return false;
5258
5259 if (x86_page_table_writing_insn(ctxt))
5260 return false;
5261
5262 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5263 return false;
5264
5265 vcpu->arch.last_retry_eip = ctxt->eip;
5266 vcpu->arch.last_retry_addr = cr2;
5267
5268 if (!vcpu->arch.mmu.direct_map)
5269 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5270
22368028 5271 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5272
5273 return true;
5274}
5275
716d51ab
GN		 5276static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5277static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5278
4a1e10d5
PB		 5279static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5280 unsigned long *db)
5281{
5282 u32 dr6 = 0;
5283 int i;
5284 u32 enable, rwlen;
5285
5286 enable = dr7;
5287 rwlen = dr7 >> 16;
5288 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5289 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5290 dr6 |= (1 << i);
5291 return dr6;
5292}
5293
6addfc42 5294static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5295{
5296 struct kvm_run *kvm_run = vcpu->run;
5297
5298 /*
6addfc42
PB		 5299 * rflags is the old, "raw" value of the flags. The new value has
5300 * not been saved yet.
663f4c61
PB		 5301 *
5302 * This is correct even for TF set by the guest, because "the
5303 * processor will not generate this exception after the instruction
5304 * that sets the TF flag".
5305 */
663f4c61
PB		 5306 if (unlikely(rflags & X86_EFLAGS_TF)) {
5307 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5308 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5309 DR6_RTM;
663f4c61
PB		 5310 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5311 kvm_run->debug.arch.exception = DB_VECTOR;
5312 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5313 *r = EMULATE_USER_EXIT;
5314 } else {
5315 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5316 /*
5317 * "Certain debug exceptions may clear bit 0-3. The
5318 * remaining contents of the DR6 register are never
5319 * cleared by the processor".
5320 */
5321 vcpu->arch.dr6 &= ~15;
6f43ed01 5322 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5323 kvm_queue_exception(vcpu, DB_VECTOR);
5324 }
5325 }
5326}
5327
4a1e10d5
PB		 5328static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5329{
4a1e10d5
PB		 5330 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5331 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5332 struct kvm_run *kvm_run = vcpu->run;
5333 unsigned long eip = kvm_get_linear_rip(vcpu);
5334 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5335 vcpu->arch.guest_debug_dr7,
5336 vcpu->arch.eff_db);
5337
5338 if (dr6 != 0) {
6f43ed01 5339 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5340 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5341 kvm_run->debug.arch.exception = DB_VECTOR;
5342 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5343 *r = EMULATE_USER_EXIT;
5344 return true;
5345 }
5346 }
5347
4161a569
NA		 5348 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5349 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5350 unsigned long eip = kvm_get_linear_rip(vcpu);
5351 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5352 vcpu->arch.dr7,
5353 vcpu->arch.db);
5354
5355 if (dr6 != 0) {
5356 vcpu->arch.dr6 &= ~15;
6f43ed01 5357 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5358 kvm_queue_exception(vcpu, DB_VECTOR);
5359 *r = EMULATE_DONE;
5360 return true;
5361 }
5362 }
5363
5364 return false;
5365}
5366
51d8b661
AP		 5367int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5368 unsigned long cr2,
dc25e89e
AP		 5369 int emulation_type,
5370 void *insn,
5371 int insn_len)
bbd9b64e 5372{
95cb2295 5373 int r;
9d74191a 5374 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5375 bool writeback = true;
93c05d3e 5376 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5377
93c05d3e
XG		 5378 /*
5379 * Clear write_fault_to_shadow_pgtable here to ensure it is
5380 * never reused.
5381 */
5382 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5383 kvm_clear_exception_queue(vcpu);
8d7d8102 5384
571008da 5385 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5386 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5387
5388 /*
5389 * We will reenter on the same instruction since
5390 * we do not set complete_userspace_io. This does not
5391 * handle watchpoints yet, those would be handled in
5392 * the emulate_ops.
5393 */
5394 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5395 return r;
5396
9d74191a
TY		 5397 ctxt->interruptibility = 0;
5398 ctxt->have_exception = false;
e0ad0b47 5399 ctxt->exception.vector = -1;
9d74191a 5400 ctxt->perm_ok = false;
bbd9b64e 5401
b51e974f 5402 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5403
9d74191a 5404 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5405
e46479f8 5406 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5407 ++vcpu->stat.insn_emulation;
1d2887e2 5408 if (r != EMULATION_OK) {
4005996e
AK		 5409 if (emulation_type & EMULTYPE_TRAP_UD)
5410 return EMULATE_FAIL;
991eebf9
GN		 5411 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5412 emulation_type))
bbd9b64e 5413 return EMULATE_DONE;
6d77dbfc
GN		 5414 if (emulation_type & EMULTYPE_SKIP)
5415 return EMULATE_FAIL;
5416 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5417 }
5418 }
5419
ba8afb6b 5420 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5421 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5422 if (ctxt->eflags & X86_EFLAGS_RF)
5423 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5424 return EMULATE_DONE;
5425 }
5426
1cb3f3ae
XG		 5427 if (retry_instruction(ctxt, cr2, emulation_type))
5428 return EMULATE_DONE;
5429
7ae441ea 5430 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5431 changes registers values during IO operation */
7ae441ea
GN		 5432 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5433 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5434 emulator_invalidate_register_cache(ctxt);
7ae441ea 5435 }
4d2179e1 5436
5cd21917 5437restart:
9d74191a 5438 r = x86_emulate_insn(ctxt);
bbd9b64e 5439
775fde86
JR		 5440 if (r == EMULATION_INTERCEPTED)
5441 return EMULATE_DONE;
5442
d2ddd1c4 5443 if (r == EMULATION_FAILED) {
991eebf9
GN		 5444 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5445 emulation_type))
c3cd7ffa
GN		 5446 return EMULATE_DONE;
5447
6d77dbfc 5448 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5449 }
5450
9d74191a 5451 if (ctxt->have_exception) {
d2ddd1c4 5452 r = EMULATE_DONE;
ef54bcfe
PB		 5453 if (inject_emulated_exception(vcpu))
5454 return r;
d2ddd1c4 5455 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5456 if (!vcpu->arch.pio.in) {
5457 /* FIXME: return into emulator if single-stepping. */
3457e419 5458 vcpu->arch.pio.count = 0;
0912c977 5459 } else {
7ae441ea 5460 writeback = false;
716d51ab
GN		 5461 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5462 }
ac0a48c3 5463 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5464 } else if (vcpu->mmio_needed) {
5465 if (!vcpu->mmio_is_write)
5466 writeback = false;
ac0a48c3 5467 r = EMULATE_USER_EXIT;
716d51ab 5468 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5469 } else if (r == EMULATION_RESTART)
5cd21917 5470 goto restart;
d2ddd1c4
GN		 5471 else
5472 r = EMULATE_DONE;
f850e2e6 5473
7ae441ea 5474 if (writeback) {
6addfc42 5475 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5476 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5477 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5478 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5479 if (r == EMULATE_DONE)
6addfc42 5480 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5481 if (!ctxt->have_exception ||
5482 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5483 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5484
5485 /*
5486 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5487 * do nothing, and it will be requested again as soon as
5488 * the shadow expires. But we still need to check here,
5489 * because POPF has no interrupt shadow.
5490 */
5491 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5492 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5493 } else
5494 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5495
5496 return r;
de7d789a 5497}
51d8b661 5498EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5499
cf8f70bf 5500int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5501{
cf8f70bf 5502 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5503 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5504 size, port, &val, 1);
cf8f70bf 5505 /* do not return to emulator after return from userspace */
7972995b 5506 vcpu->arch.pio.count = 0;
de7d789a
CO		 5507 return ret;
5508}
cf8f70bf 5509EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5510
8cfdc000
ZA		 5511static void tsc_bad(void *info)
5512{
0a3aee0d 5513 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5514}
5515
5516static void tsc_khz_changed(void *data)
c8076604 5517{
8cfdc000
ZA		 5518 struct cpufreq_freqs *freq = data;
5519 unsigned long khz = 0;
5520
5521 if (data)
5522 khz = freq->new;
5523 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5524 khz = cpufreq_quick_get(raw_smp_processor_id());
5525 if (!khz)
5526 khz = tsc_khz;
0a3aee0d 5527 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5528}
5529
c8076604
GH		 5530static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5531 void *data)
5532{
5533 struct cpufreq_freqs *freq = data;
5534 struct kvm *kvm;
5535 struct kvm_vcpu *vcpu;
5536 int i, send_ipi = 0;
5537
8cfdc000
ZA		 5538 /*
5539 * We allow guests to temporarily run on slowing clocks,
5540 * provided we notify them after, or to run on accelerating
5541 * clocks, provided we notify them before. Thus time never
5542 * goes backwards.
5543 *
5544 * However, we have a problem. We can't atomically update
5545 * the frequency of a given CPU from this function; it is
5546 * merely a notifier, which can be called from any CPU.
5547 * Changing the TSC frequency at arbitrary points in time
5548 * requires a recomputation of local variables related to
5549 * the TSC for each VCPU. We must flag these local variables
5550 * to be updated and be sure the update takes place with the
5551 * new frequency before any guests proceed.
5552 *
5553 * Unfortunately, the combination of hotplug CPU and frequency
5554 * change creates an intractable locking scenario; the order
5555 * of when these callouts happen is undefined with respect to
5556 * CPU hotplug, and they can race with each other. As such,
5557 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5558 * undefined; you can actually have a CPU frequency change take
5559 * place in between the computation of X and the setting of the
5560 * variable. To protect against this problem, all updates of
5561 * the per_cpu tsc_khz variable are done in an interrupt
5562 * protected IPI, and all callers wishing to update the value
5563 * must wait for a synchronous IPI to complete (which is trivial
5564 * if the caller is on the CPU already). This establishes the
5565 * necessary total order on variable updates.
5566 *
5567 * Note that because a guest time update may take place
5568 * anytime after the setting of the VCPU's request bit, the
5569 * correct TSC value must be set before the request. However,
5570 * to ensure the update actually makes it to any guest which
5571 * starts running in hardware virtualization between the set
5572 * and the acquisition of the spinlock, we must also ping the
5573 * CPU after setting the request bit.
5574 *
5575 */
5576
c8076604
GH		 5577 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5578 return 0;
5579 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5580 return 0;
8cfdc000
ZA		 5581
5582 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5583
2f303b74 5584 spin_lock(&kvm_lock);
c8076604 5585 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5586 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5587 if (vcpu->cpu != freq->cpu)
5588 continue;
c285545f 5589 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5590 if (vcpu->cpu != smp_processor_id())
8cfdc000 5591 send_ipi = 1;
c8076604
GH		 5592 }
5593 }
2f303b74 5594 spin_unlock(&kvm_lock);
c8076604
GH		 5595
5596 if (freq->old < freq->new && send_ipi) {
5597 /*
5598 * We upscale the frequency. Must make the guest
5599 * doesn't see old kvmclock values while running with
5600 * the new frequency, otherwise we risk the guest sees
5601 * time go backwards.
5602 *
5603 * In case we update the frequency for another cpu
5604 * (which might be in guest context) send an interrupt
5605 * to kick the cpu out of guest context. Next time
5606 * guest context is entered kvmclock will be updated,
5607 * so the guest will not see stale values.
5608 */
8cfdc000 5609 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5610 }
5611 return 0;
5612}
5613
5614static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5615 .notifier_call = kvmclock_cpufreq_notifier
5616};
5617
5618static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5619 unsigned long action, void *hcpu)
5620{
5621 unsigned int cpu = (unsigned long)hcpu;
5622
5623 switch (action) {
5624 case CPU_ONLINE:
5625 case CPU_DOWN_FAILED:
5626 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5627 break;
5628 case CPU_DOWN_PREPARE:
5629 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5630 break;
5631 }
5632 return NOTIFY_OK;
5633}
5634
5635static struct notifier_block kvmclock_cpu_notifier_block = {
5636 .notifier_call = kvmclock_cpu_notifier,
5637 .priority = -INT_MAX
c8076604
GH		 5638};
5639
b820cc0c
ZA		 5640static void kvm_timer_init(void)
5641{
5642 int cpu;
5643
c285545f 5644 max_tsc_khz = tsc_khz;
460dd42e
SB		 5645
5646 cpu_notifier_register_begin();
b820cc0c 5647 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5648#ifdef CONFIG_CPU_FREQ
5649 struct cpufreq_policy policy;
5650 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5651 cpu = get_cpu();
5652 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5653 if (policy.cpuinfo.max_freq)
5654 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5655 put_cpu();
c285545f 5656#endif
b820cc0c
ZA		 5657 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5658 CPUFREQ_TRANSITION_NOTIFIER);
5659 }
c285545f 5660 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5661 for_each_online_cpu(cpu)
5662 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5663
5664 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5665 cpu_notifier_register_done();
5666
b820cc0c
ZA		 5667}
5668
ff9d07a0
ZY		 5669static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5670
f5132b01 5671int kvm_is_in_guest(void)
ff9d07a0 5672{
086c9855 5673 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5674}
5675
5676static int kvm_is_user_mode(void)
5677{
5678 int user_mode = 3;
dcf46b94 5679
086c9855
AS		 5680 if (__this_cpu_read(current_vcpu))
5681 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5682
ff9d07a0
ZY		 5683 return user_mode != 0;
5684}
5685
5686static unsigned long kvm_get_guest_ip(void)
5687{
5688 unsigned long ip = 0;
dcf46b94 5689
086c9855
AS		 5690 if (__this_cpu_read(current_vcpu))
5691 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5692
ff9d07a0
ZY		 5693 return ip;
5694}
5695
5696static struct perf_guest_info_callbacks kvm_guest_cbs = {
5697 .is_in_guest = kvm_is_in_guest,
5698 .is_user_mode = kvm_is_user_mode,
5699 .get_guest_ip = kvm_get_guest_ip,
5700};
5701
5702void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5703{
086c9855 5704 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5705}
5706EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5707
5708void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5709{
086c9855 5710 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5711}
5712EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5713
ce88decf
XG		 5714static void kvm_set_mmio_spte_mask(void)
5715{
5716 u64 mask;
5717 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5718
5719 /*
5720 * Set the reserved bits and the present bit of an paging-structure
5721 * entry to generate page fault with PFER.RSV = 1.
5722 */
885032b9 5723 /* Mask the reserved physical address bits. */
d1431483 5724 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5725
5726 /* Bit 62 is always reserved for 32bit host. */
5727 mask |= 0x3ull << 62;
5728
5729 /* Set the present bit. */
ce88decf
XG		 5730 mask |= 1ull;
5731
5732#ifdef CONFIG_X86_64
5733 /*
5734 * If reserved bit is not supported, clear the present bit to disable
5735 * mmio page fault.
5736 */
5737 if (maxphyaddr == 52)
5738 mask &= ~1ull;
5739#endif
5740
5741 kvm_mmu_set_mmio_spte_mask(mask);
5742}
5743
16e8d74d
MT		 5744#ifdef CONFIG_X86_64
5745static void pvclock_gtod_update_fn(struct work_struct *work)
5746{
d828199e
MT		 5747 struct kvm *kvm;
5748
5749 struct kvm_vcpu *vcpu;
5750 int i;
5751
2f303b74 5752 spin_lock(&kvm_lock);
d828199e
MT		 5753 list_for_each_entry(kvm, &vm_list, vm_list)
5754 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5755 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5756 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5757 spin_unlock(&kvm_lock);
16e8d74d
MT		 5758}
5759
5760static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5761
5762/*
5763 * Notification about pvclock gtod data update.
5764 */
5765static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5766 void *priv)
5767{
5768 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5769 struct timekeeper *tk = priv;
5770
5771 update_pvclock_gtod(tk);
5772
5773 /* disable master clock if host does not trust, or does not
5774 * use, TSC clocksource
5775 */
5776 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5777 atomic_read(&kvm_guest_has_master_clock) != 0)
5778 queue_work(system_long_wq, &pvclock_gtod_work);
5779
5780 return 0;
5781}
5782
5783static struct notifier_block pvclock_gtod_notifier = {
5784 .notifier_call = pvclock_gtod_notify,
5785};
5786#endif
5787
f8c16bba 5788int kvm_arch_init(void *opaque)
043405e1 5789{
b820cc0c 5790 int r;
6b61edf7 5791 struct kvm_x86_ops *ops = opaque;
f8c16bba 5792
f8c16bba
ZX		 5793 if (kvm_x86_ops) {
5794 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5795 r = -EEXIST;
5796 goto out;
f8c16bba
ZX		 5797 }
5798
5799 if (!ops->cpu_has_kvm_support()) {
5800 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5801 r = -EOPNOTSUPP;
5802 goto out;
f8c16bba
ZX		 5803 }
5804 if (ops->disabled_by_bios()) {
5805 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5806 r = -EOPNOTSUPP;
5807 goto out;
f8c16bba
ZX		 5808 }
5809
013f6a5d
MT		 5810 r = -ENOMEM;
5811 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5812 if (!shared_msrs) {
5813 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5814 goto out;
5815 }
5816
97db56ce
AK		 5817 r = kvm_mmu_module_init();
5818 if (r)
013f6a5d 5819 goto out_free_percpu;
97db56ce 5820
ce88decf 5821 kvm_set_mmio_spte_mask();
97db56ce 5822
f8c16bba 5823 kvm_x86_ops = ops;
920c8377 5824
7b52345e 5825 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5826 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5827
b820cc0c 5828 kvm_timer_init();
c8076604 5829
ff9d07a0
ZY		 5830 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5831
2acf923e
DC		 5832 if (cpu_has_xsave)
5833 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5834
c5cc421b 5835 kvm_lapic_init();
16e8d74d
MT		 5836#ifdef CONFIG_X86_64
5837 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5838#endif
5839
f8c16bba 5840 return 0;
56c6d28a 5841
013f6a5d
MT		 5842out_free_percpu:
5843 free_percpu(shared_msrs);
56c6d28a 5844out:
56c6d28a 5845 return r;
043405e1 5846}
8776e519 5847
f8c16bba
ZX		 5848void kvm_arch_exit(void)
5849{
ff9d07a0
ZY		 5850 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5851
888d256e
JK		 5852 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5853 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5854 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5855 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5856#ifdef CONFIG_X86_64
5857 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5858#endif
f8c16bba 5859 kvm_x86_ops = NULL;
56c6d28a 5860 kvm_mmu_module_exit();
013f6a5d 5861 free_percpu(shared_msrs);
56c6d28a 5862}
f8c16bba 5863
5cb56059 5864int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5865{
5866 ++vcpu->stat.halt_exits;
5867 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5868 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5869 return 1;
5870 } else {
5871 vcpu->run->exit_reason = KVM_EXIT_HLT;
5872 return 0;
5873 }
5874}
5cb56059
JS		 5875EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5876
5877int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5878{
5879 kvm_x86_ops->skip_emulated_instruction(vcpu);
5880 return kvm_vcpu_halt(vcpu);
5881}
8776e519
HB		 5882EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5883
55cd8e5a
GN		 5884int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5885{
5886 u64 param, ingpa, outgpa, ret;
5887 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5888 bool fast, longmode;
55cd8e5a
GN		 5889
5890 /*
5891 * hypercall generates UD from non zero cpl and real mode
5892 * per HYPER-V spec
5893 */
3eeb3288 5894 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5895 kvm_queue_exception(vcpu, UD_VECTOR);
5896 return 0;
5897 }
5898
a449c7aa 5899 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5900
5901 if (!longmode) {
ccd46936
GN		 5902 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5903 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5904 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5905 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5906 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5907 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5908 }
5909#ifdef CONFIG_X86_64
5910 else {
5911 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5912 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5913 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5914 }
5915#endif
5916
5917 code = param & 0xffff;
5918 fast = (param >> 16) & 0x1;
5919 rep_cnt = (param >> 32) & 0xfff;
5920 rep_idx = (param >> 48) & 0xfff;
5921
5922 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5923
c25bc163
GN		 5924 switch (code) {
5925 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5926 kvm_vcpu_on_spin(vcpu);
5927 break;
5928 default:
5929 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5930 break;
5931 }
55cd8e5a
GN		 5932
5933 ret = res | (((u64)rep_done & 0xfff) << 32);
5934 if (longmode) {
5935 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5936 } else {
5937 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5938 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5939 }
5940
5941 return 1;
5942}
5943
6aef266c
SV		 5944/*
5945 * kvm_pv_kick_cpu_op: Kick a vcpu.
5946 *
5947 * @apicid - apicid of vcpu to be kicked.
5948 */
5949static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5950{
24d2166b 5951 struct kvm_lapic_irq lapic_irq;
6aef266c 5952
24d2166b
R		 5953 lapic_irq.shorthand = 0;
5954 lapic_irq.dest_mode = 0;
5955 lapic_irq.dest_id = apicid;
6aef266c 5956
24d2166b 5957 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5958 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5959}
5960
8776e519
HB		 5961int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5962{
5963 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5964 int op_64_bit, r = 1;
8776e519 5965
5cb56059
JS		 5966 kvm_x86_ops->skip_emulated_instruction(vcpu);
5967
55cd8e5a
GN		 5968 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5969 return kvm_hv_hypercall(vcpu);
5970
5fdbf976
MT		 5971 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5972 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5973 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5974 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5975 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5976
229456fc 5977 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5978
a449c7aa
NA		 5979 op_64_bit = is_64_bit_mode(vcpu);
5980 if (!op_64_bit) {
8776e519
HB		 5981 nr &= 0xFFFFFFFF;
5982 a0 &= 0xFFFFFFFF;
5983 a1 &= 0xFFFFFFFF;
5984 a2 &= 0xFFFFFFFF;
5985 a3 &= 0xFFFFFFFF;
5986 }
5987
07708c4a
JK		 5988 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5989 ret = -KVM_EPERM;
5990 goto out;
5991 }
5992
8776e519 5993 switch (nr) {
b93463aa
AK		 5994 case KVM_HC_VAPIC_POLL_IRQ:
5995 ret = 0;
5996 break;
6aef266c
SV		 5997 case KVM_HC_KICK_CPU:
5998 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5999 ret = 0;
6000 break;
8776e519
HB		 6001 default:
6002 ret = -KVM_ENOSYS;
6003 break;
6004 }
07708c4a 6005out:
a449c7aa
NA		 6006 if (!op_64_bit)
6007 ret = (u32)ret;
5fdbf976 6008 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6009 ++vcpu->stat.hypercalls;
2f333bcb 6010 return r;
8776e519
HB		 6011}
6012EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6013
b6785def 6014static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6015{
d6aa1000 6016 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6017 char instruction[3];
5fdbf976 6018 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6019
8776e519 6020 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6021
9d74191a 6022 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6023}
6024
b6c7a5dc
HB		 6025/*
6026 * Check if userspace requested an interrupt window, and that the
6027 * interrupt window is open.
6028 *
6029 * No need to exit to userspace if we already have an interrupt queued.
6030 */
851ba692 6031static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6032{
8061823a 6033 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 6034 vcpu->run->request_interrupt_window &&
5df56646 6035 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 6036}
6037
851ba692 6038static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6039{
851ba692
AK		 6040 struct kvm_run *kvm_run = vcpu->run;
6041
91586a3b 6042 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 6043 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6044 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 6045 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 6046 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6047 else
b6c7a5dc 6048 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6049 kvm_arch_interrupt_allowed(vcpu) &&
6050 !kvm_cpu_has_interrupt(vcpu) &&
6051 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6052}
6053
95ba8273
GN		 6054static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6055{
6056 int max_irr, tpr;
6057
6058 if (!kvm_x86_ops->update_cr8_intercept)
6059 return;
6060
88c808fd
AK		 6061 if (!vcpu->arch.apic)
6062 return;
6063
8db3baa2
GN		 6064 if (!vcpu->arch.apic->vapic_addr)
6065 max_irr = kvm_lapic_find_highest_irr(vcpu);
6066 else
6067 max_irr = -1;
95ba8273
GN		 6068
6069 if (max_irr != -1)
6070 max_irr >>= 4;
6071
6072 tpr = kvm_lapic_get_cr8(vcpu);
6073
6074 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6075}
6076
b6b8a145 6077static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6078{
b6b8a145
JK		 6079 int r;
6080
95ba8273 6081 /* try to reinject previous events if any */
b59bb7bd 6082 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6083 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6084 vcpu->arch.exception.has_error_code,
6085 vcpu->arch.exception.error_code);
d6e8c854
NA		 6086
6087 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6088 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6089 X86_EFLAGS_RF);
6090
6bdf0662
NA		 6091 if (vcpu->arch.exception.nr == DB_VECTOR &&
6092 (vcpu->arch.dr7 & DR7_GD)) {
6093 vcpu->arch.dr7 &= ~DR7_GD;
6094 kvm_update_dr7(vcpu);
6095 }
6096
b59bb7bd
GN		 6097 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6098 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6099 vcpu->arch.exception.error_code,
6100 vcpu->arch.exception.reinject);
b6b8a145 6101 return 0;
b59bb7bd
GN		 6102 }
6103
95ba8273
GN		 6104 if (vcpu->arch.nmi_injected) {
6105 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6106 return 0;
95ba8273
GN		 6107 }
6108
6109 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6110 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6111 return 0;
6112 }
6113
6114 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6115 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6116 if (r != 0)
6117 return r;
95ba8273
GN		 6118 }
6119
6120 /* try to inject new event if pending */
6121 if (vcpu->arch.nmi_pending) {
6122 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6123 --vcpu->arch.nmi_pending;
95ba8273
GN		 6124 vcpu->arch.nmi_injected = true;
6125 kvm_x86_ops->set_nmi(vcpu);
6126 }
c7c9c56c 6127 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6128 /*
6129 * Because interrupts can be injected asynchronously, we are
6130 * calling check_nested_events again here to avoid a race condition.
6131 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6132 * proposal and current concerns. Perhaps we should be setting
6133 * KVM_REQ_EVENT only on certain events and not unconditionally?
6134 */
6135 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6136 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6137 if (r != 0)
6138 return r;
6139 }
95ba8273 6140 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6141 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6142 false);
6143 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6144 }
6145 }
b6b8a145 6146 return 0;
95ba8273
GN		 6147}
6148
7460fb4a
AK		 6149static void process_nmi(struct kvm_vcpu *vcpu)
6150{
6151 unsigned limit = 2;
6152
6153 /*
6154 * x86 is limited to one NMI running, and one NMI pending after it.
6155 * If an NMI is already in progress, limit further NMIs to just one.
6156 * Otherwise, allow two (and we'll inject the first one immediately).
6157 */
6158 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6159 limit = 1;
6160
6161 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6162 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6163 kvm_make_request(KVM_REQ_EVENT, vcpu);
6164}
6165
3d81bc7e 6166static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6167{
6168 u64 eoi_exit_bitmap[4];
cf9e65b7 6169 u32 tmr[8];
c7c9c56c 6170
3d81bc7e
YZ		 6171 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6172 return;
c7c9c56c
YZ		 6173
6174 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6175 memset(tmr, 0, 32);
c7c9c56c 6176
cf9e65b7 6177 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6178 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6179 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6180}
6181
a70656b6
RK		 6182static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6183{
6184 ++vcpu->stat.tlb_flush;
6185 kvm_x86_ops->tlb_flush(vcpu);
6186}
6187
4256f43f
TC		 6188void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6189{
c24ae0dc
TC		 6190 struct page *page = NULL;
6191
f439ed27
PB		 6192 if (!irqchip_in_kernel(vcpu->kvm))
6193 return;
6194
4256f43f
TC		 6195 if (!kvm_x86_ops->set_apic_access_page_addr)
6196 return;
6197
c24ae0dc
TC		 6198 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6199 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6200
6201 /*
6202 * Do not pin apic access page in memory, the MMU notifier
6203 * will call us again if it is migrated or swapped out.
6204 */
6205 put_page(page);
4256f43f
TC		 6206}
6207EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6208
fe71557a
TC		 6209void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6210 unsigned long address)
6211{
c24ae0dc
TC		 6212 /*
6213 * The physical address of apic access page is stored in the VMCS.
6214 * Update it when it becomes invalid.
6215 */
6216 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6217 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6218}
6219
9357d939 6220/*
362c698f 6221 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6222 * exiting to the userspace. Otherwise, the value will be returned to the
6223 * userspace.
6224 */
851ba692 6225static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6226{
6227 int r;
6a8b1d13 6228 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6229 vcpu->run->request_interrupt_window;
730dca42 6230 bool req_immediate_exit = false;
b6c7a5dc 6231
3e007509 6232 if (vcpu->requests) {
a8eeb04a 6233 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6234 kvm_mmu_unload(vcpu);
a8eeb04a 6235 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6236 __kvm_migrate_timers(vcpu);
d828199e
MT		 6237 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6238 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6239 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6240 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6241 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6242 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6243 if (unlikely(r))
6244 goto out;
6245 }
a8eeb04a 6246 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6247 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6248 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6249 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6250 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6251 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6252 r = 0;
6253 goto out;
6254 }
a8eeb04a 6255 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6256 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6257 r = 0;
6258 goto out;
6259 }
a8eeb04a 6260 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6261 vcpu->fpu_active = 0;
6262 kvm_x86_ops->fpu_deactivate(vcpu);
6263 }
af585b92
GN		 6264 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6265 /* Page is swapped out. Do synthetic halt */
6266 vcpu->arch.apf.halted = true;
6267 r = 1;
6268 goto out;
6269 }
c9aaa895
GC		 6270 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6271 record_steal_time(vcpu);
7460fb4a
AK		 6272 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6273 process_nmi(vcpu);
f5132b01
GN		 6274 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6275 kvm_handle_pmu_event(vcpu);
6276 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6277 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6278 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6279 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6280 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6281 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6282 }
b93463aa 6283
b463a6f7 6284 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6285 kvm_apic_accept_events(vcpu);
6286 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6287 r = 1;
6288 goto out;
6289 }
6290
b6b8a145
JK		 6291 if (inject_pending_event(vcpu, req_int_win) != 0)
6292 req_immediate_exit = true;
b463a6f7 6293 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6294 else if (vcpu->arch.nmi_pending)
c9a7953f 6295 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6296 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6297 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6298
6299 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6300 /*
6301 * Update architecture specific hints for APIC
6302 * virtual interrupt delivery.
6303 */
6304 if (kvm_x86_ops->hwapic_irr_update)
6305 kvm_x86_ops->hwapic_irr_update(vcpu,
6306 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6307 update_cr8_intercept(vcpu);
6308 kvm_lapic_sync_to_vapic(vcpu);
6309 }
6310 }
6311
d8368af8
AK		 6312 r = kvm_mmu_reload(vcpu);
6313 if (unlikely(r)) {
d905c069 6314 goto cancel_injection;
d8368af8
AK		 6315 }
6316
b6c7a5dc
HB		 6317 preempt_disable();
6318
6319 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6320 if (vcpu->fpu_active)
6321 kvm_load_guest_fpu(vcpu);
2acf923e 6322 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6323
6b7e2d09
XG		 6324 vcpu->mode = IN_GUEST_MODE;
6325
01b71917
MT		 6326 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6327
6b7e2d09
XG		 6328 /* We should set ->mode before check ->requests,
6329 * see the comment in make_all_cpus_request.
6330 */
01b71917 6331 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6332
d94e1dc9 6333 local_irq_disable();
32f88400 6334
6b7e2d09 6335 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6336 || need_resched() || signal_pending(current)) {
6b7e2d09 6337 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6338 smp_wmb();
6c142801
AK		 6339 local_irq_enable();
6340 preempt_enable();
01b71917 6341 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6342 r = 1;
d905c069 6343 goto cancel_injection;
6c142801
AK		 6344 }
6345
d6185f20
NHE		 6346 if (req_immediate_exit)
6347 smp_send_reschedule(vcpu->cpu);
6348
b6c7a5dc
HB		 6349 kvm_guest_enter();
6350
42dbaa5a 6351 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6352 set_debugreg(0, 7);
6353 set_debugreg(vcpu->arch.eff_db[0], 0);
6354 set_debugreg(vcpu->arch.eff_db[1], 1);
6355 set_debugreg(vcpu->arch.eff_db[2], 2);
6356 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6357 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6358 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6359 }
b6c7a5dc 6360
229456fc 6361 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6362 wait_lapic_expire(vcpu);
851ba692 6363 kvm_x86_ops->run(vcpu);
b6c7a5dc 6364
c77fb5fe
PB		 6365 /*
6366 * Do this here before restoring debug registers on the host. And
6367 * since we do this before handling the vmexit, a DR access vmexit
6368 * can (a) read the correct value of the debug registers, (b) set
6369 * KVM_DEBUGREG_WONT_EXIT again.
6370 */
6371 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6372 int i;
6373
6374 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6375 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6376 for (i = 0; i < KVM_NR_DB_REGS; i++)
6377 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6378 }
6379
24f1e32c
FW		 6380 /*
6381 * If the guest has used debug registers, at least dr7
6382 * will be disabled while returning to the host.
6383 * If we don't have active breakpoints in the host, we don't
6384 * care about the messed up debug address registers. But if
6385 * we have some of them active, restore the old state.
6386 */
59d8eb53 6387 if (hw_breakpoint_active())
24f1e32c 6388 hw_breakpoint_restore();
42dbaa5a 6389
886b470c
MT		 6390 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6391 native_read_tsc());
1d5f066e 6392
6b7e2d09 6393 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6394 smp_wmb();
a547c6db
YZ		 6395
6396 /* Interrupt is enabled by handle_external_intr() */
6397 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6398
6399 ++vcpu->stat.exits;
6400
6401 /*
6402 * We must have an instruction between local_irq_enable() and
6403 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6404 * the interrupt shadow. The stat.exits increment will do nicely.
6405 * But we need to prevent reordering, hence this barrier():
6406 */
6407 barrier();
6408
6409 kvm_guest_exit();
6410
6411 preempt_enable();
6412
f656ce01 6413 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6414
b6c7a5dc
HB		 6415 /*
6416 * Profile KVM exit RIPs:
6417 */
6418 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6419 unsigned long rip = kvm_rip_read(vcpu);
6420 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6421 }
6422
cc578287
ZA		 6423 if (unlikely(vcpu->arch.tsc_always_catchup))
6424 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6425
5cfb1d5a
MT		 6426 if (vcpu->arch.apic_attention)
6427 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6428
851ba692 6429 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6430 return r;
6431
6432cancel_injection:
6433 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6434 if (unlikely(vcpu->arch.apic_attention))
6435 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6436out:
6437 return r;
6438}
b6c7a5dc 6439
362c698f
PB		 6440static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6441{
9c8fd1ba
PB		 6442 if (!kvm_arch_vcpu_runnable(vcpu)) {
6443 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6444 kvm_vcpu_block(vcpu);
6445 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6446 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6447 return 1;
6448 }
362c698f
PB		 6449
6450 kvm_apic_accept_events(vcpu);
6451 switch(vcpu->arch.mp_state) {
6452 case KVM_MP_STATE_HALTED:
6453 vcpu->arch.pv.pv_unhalted = false;
6454 vcpu->arch.mp_state =
6455 KVM_MP_STATE_RUNNABLE;
6456 case KVM_MP_STATE_RUNNABLE:
6457 vcpu->arch.apf.halted = false;
6458 break;
6459 case KVM_MP_STATE_INIT_RECEIVED:
6460 break;
6461 default:
6462 return -EINTR;
6463 break;
6464 }
6465 return 1;
6466}
09cec754 6467
362c698f 6468static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6469{
6470 int r;
f656ce01 6471 struct kvm *kvm = vcpu->kvm;
d7690175 6472
f656ce01 6473 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6474
362c698f 6475 for (;;) {
af585b92
GN		 6476 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6477 !vcpu->arch.apf.halted)
851ba692 6478 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6479 else
6480 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6481 if (r <= 0)
6482 break;
6483
6484 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6485 if (kvm_cpu_has_pending_timer(vcpu))
6486 kvm_inject_pending_timer_irqs(vcpu);
6487
851ba692 6488 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6489 r = -EINTR;
851ba692 6490 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6491 ++vcpu->stat.request_irq_exits;
362c698f 6492 break;
09cec754 6493 }
af585b92
GN		 6494
6495 kvm_check_async_pf_completion(vcpu);
6496
09cec754
GN		 6497 if (signal_pending(current)) {
6498 r = -EINTR;
851ba692 6499 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6500 ++vcpu->stat.signal_exits;
362c698f 6501 break;
09cec754
GN		 6502 }
6503 if (need_resched()) {
f656ce01 6504 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6505 cond_resched();
f656ce01 6506 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6507 }
b6c7a5dc
HB		 6508 }
6509
f656ce01 6510 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6511
6512 return r;
6513}
6514
716d51ab
GN		 6515static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6516{
6517 int r;
6518 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6519 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6520 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6521 if (r != EMULATE_DONE)
6522 return 0;
6523 return 1;
6524}
6525
6526static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6527{
6528 BUG_ON(!vcpu->arch.pio.count);
6529
6530 return complete_emulated_io(vcpu);
6531}
6532
f78146b0
AK		 6533/*
6534 * Implements the following, as a state machine:
6535 *
6536 * read:
6537 * for each fragment
87da7e66
XG		 6538 * for each mmio piece in the fragment
6539 * write gpa, len
6540 * exit
6541 * copy data
f78146b0
AK		 6542 * execute insn
6543 *
6544 * write:
6545 * for each fragment
87da7e66
XG		 6546 * for each mmio piece in the fragment
6547 * write gpa, len
6548 * copy data
6549 * exit
f78146b0 6550 */
716d51ab 6551static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6552{
6553 struct kvm_run *run = vcpu->run;
f78146b0 6554 struct kvm_mmio_fragment *frag;
87da7e66 6555 unsigned len;
5287f194 6556
716d51ab 6557 BUG_ON(!vcpu->mmio_needed);
5287f194 6558
716d51ab 6559 /* Complete previous fragment */
87da7e66
XG		 6560 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6561 len = min(8u, frag->len);
716d51ab 6562 if (!vcpu->mmio_is_write)
87da7e66
XG		 6563 memcpy(frag->data, run->mmio.data, len);
6564
6565 if (frag->len <= 8) {
6566 /* Switch to the next fragment. */
6567 frag++;
6568 vcpu->mmio_cur_fragment++;
6569 } else {
6570 /* Go forward to the next mmio piece. */
6571 frag->data += len;
6572 frag->gpa += len;
6573 frag->len -= len;
6574 }
6575
a08d3b3b 6576 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6577 vcpu->mmio_needed = 0;
0912c977
PB		 6578
6579 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6580 if (vcpu->mmio_is_write)
716d51ab
GN		 6581 return 1;
6582 vcpu->mmio_read_completed = 1;
6583 return complete_emulated_io(vcpu);
6584 }
87da7e66 6585
716d51ab
GN		 6586 run->exit_reason = KVM_EXIT_MMIO;
6587 run->mmio.phys_addr = frag->gpa;
6588 if (vcpu->mmio_is_write)
87da7e66
XG		 6589 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6590 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6591 run->mmio.is_write = vcpu->mmio_is_write;
6592 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6593 return 0;
5287f194
AK		 6594}
6595
716d51ab 6596
b6c7a5dc
HB		 6597int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6598{
c5bedc68 6599 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6600 int r;
6601 sigset_t sigsaved;
6602
c4d72e2d 6603 fpu__activate_curr(fpu);
e5c30142 6604
ac9f6dc0
AK		 6605 if (vcpu->sigset_active)
6606 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6607
a4535290 6608 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6609 kvm_vcpu_block(vcpu);
66450a21 6610 kvm_apic_accept_events(vcpu);
d7690175 6611 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6612 r = -EAGAIN;
6613 goto out;
b6c7a5dc
HB		 6614 }
6615
b6c7a5dc 6616 /* re-sync apic's tpr */
eea1cff9
AP		 6617 if (!irqchip_in_kernel(vcpu->kvm)) {
6618 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6619 r = -EINVAL;
6620 goto out;
6621 }
6622 }
b6c7a5dc 6623
716d51ab
GN		 6624 if (unlikely(vcpu->arch.complete_userspace_io)) {
6625 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6626 vcpu->arch.complete_userspace_io = NULL;
6627 r = cui(vcpu);
6628 if (r <= 0)
6629 goto out;
6630 } else
6631 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6632
362c698f 6633 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6634
6635out:
f1d86e46 6636 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6637 if (vcpu->sigset_active)
6638 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6639
b6c7a5dc
HB		 6640 return r;
6641}
6642
6643int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6644{
7ae441ea
GN		 6645 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6646 /*
6647 * We are here if userspace calls get_regs() in the middle of
6648 * instruction emulation. Registers state needs to be copied
4a969980 6649 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6650 * that usually, but some bad designed PV devices (vmware
6651 * backdoor interface) need this to work
6652 */
dd856efa 6653 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6654 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6655 }
5fdbf976
MT		 6656 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6657 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6658 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6659 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6660 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6661 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6662 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6663 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6664#ifdef CONFIG_X86_64
5fdbf976
MT		 6665 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6666 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6667 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6668 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6669 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6670 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6671 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6672 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6673#endif
6674
5fdbf976 6675 regs->rip = kvm_rip_read(vcpu);
91586a3b 6676 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6677
b6c7a5dc
HB		 6678 return 0;
6679}
6680
6681int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6682{
7ae441ea
GN		 6683 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6684 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6685
5fdbf976
MT		 6686 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6687 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6688 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6689 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6690 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6691 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6692 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6693 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6694#ifdef CONFIG_X86_64
5fdbf976
MT		 6695 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6696 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6697 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6698 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6699 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6700 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6701 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6702 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6703#endif
6704
5fdbf976 6705 kvm_rip_write(vcpu, regs->rip);
91586a3b 6706 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6707
b4f14abd
JK		 6708 vcpu->arch.exception.pending = false;
6709
3842d135
AK		 6710 kvm_make_request(KVM_REQ_EVENT, vcpu);
6711
b6c7a5dc
HB		 6712 return 0;
6713}
6714
b6c7a5dc
HB		 6715void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6716{
6717 struct kvm_segment cs;
6718
3e6e0aab 6719 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6720 *db = cs.db;
6721 *l = cs.l;
6722}
6723EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6724
6725int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6726 struct kvm_sregs *sregs)
6727{
89a27f4d 6728 struct desc_ptr dt;
b6c7a5dc 6729
3e6e0aab
GT		 6730 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6731 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6732 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6733 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6734 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6735 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6736
3e6e0aab
GT		 6737 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6738 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6739
6740 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6741 sregs->idt.limit = dt.size;
6742 sregs->idt.base = dt.address;
b6c7a5dc 6743 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6744 sregs->gdt.limit = dt.size;
6745 sregs->gdt.base = dt.address;
b6c7a5dc 6746
4d4ec087 6747 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6748 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6749 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6750 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6751 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6752 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6753 sregs->apic_base = kvm_get_apic_base(vcpu);
6754
923c61bb 6755 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6756
36752c9b 6757 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6758 set_bit(vcpu->arch.interrupt.nr,
6759 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6760
b6c7a5dc
HB		 6761 return 0;
6762}
6763
62d9f0db
MT		 6764int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6765 struct kvm_mp_state *mp_state)
6766{
66450a21 6767 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6768 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6769 vcpu->arch.pv.pv_unhalted)
6770 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6771 else
6772 mp_state->mp_state = vcpu->arch.mp_state;
6773
62d9f0db
MT		 6774 return 0;
6775}
6776
6777int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6778 struct kvm_mp_state *mp_state)
6779{
66450a21
JK		 6780 if (!kvm_vcpu_has_lapic(vcpu) &&
6781 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6782 return -EINVAL;
6783
6784 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6785 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6786 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6787 } else
6788 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6789 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6790 return 0;
6791}
6792
7f3d35fd
KW		 6793int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6794 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6795{
9d74191a 6796 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6797 int ret;
e01c2426 6798
8ec4722d 6799 init_emulate_ctxt(vcpu);
c697518a 6800
7f3d35fd 6801 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6802 has_error_code, error_code);
c697518a 6803
c697518a 6804 if (ret)
19d04437 6805 return EMULATE_FAIL;
37817f29 6806
9d74191a
TY		 6807 kvm_rip_write(vcpu, ctxt->eip);
6808 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6809 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6810 return EMULATE_DONE;
37817f29
IE		 6811}
6812EXPORT_SYMBOL_GPL(kvm_task_switch);
6813
b6c7a5dc
HB		 6814int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6815 struct kvm_sregs *sregs)
6816{
58cb628d 6817 struct msr_data apic_base_msr;
b6c7a5dc 6818 int mmu_reset_needed = 0;
63f42e02 6819 int pending_vec, max_bits, idx;
89a27f4d 6820 struct desc_ptr dt;
b6c7a5dc 6821
6d1068b3
PM		 6822 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6823 return -EINVAL;
6824
89a27f4d
GN		 6825 dt.size = sregs->idt.limit;
6826 dt.address = sregs->idt.base;
b6c7a5dc 6827 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6828 dt.size = sregs->gdt.limit;
6829 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6830 kvm_x86_ops->set_gdt(vcpu, &dt);
6831
ad312c7c 6832 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6833 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6834 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6835 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6836
2d3ad1f4 6837 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6838
f6801dff 6839 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6840 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6841 apic_base_msr.data = sregs->apic_base;
6842 apic_base_msr.host_initiated = true;
6843 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6844
4d4ec087 6845 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6846 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6847 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6848
fc78f519 6849 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6850 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6851 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6852 kvm_update_cpuid(vcpu);
63f42e02
XG		 6853
6854 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6855 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6856 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6857 mmu_reset_needed = 1;
6858 }
63f42e02 6859 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6860
6861 if (mmu_reset_needed)
6862 kvm_mmu_reset_context(vcpu);
6863
a50abc3b 6864 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6865 pending_vec = find_first_bit(
6866 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6867 if (pending_vec < max_bits) {
66fd3f7f 6868 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6869 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6870 }
6871
3e6e0aab
GT		 6872 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6873 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6874 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6875 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6876 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6877 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6878
3e6e0aab
GT		 6879 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6880 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6881
5f0269f5
ME		 6882 update_cr8_intercept(vcpu);
6883
9c3e4aab 6884 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6885 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6886 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6887 !is_protmode(vcpu))
9c3e4aab
MT		 6888 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6889
3842d135
AK		 6890 kvm_make_request(KVM_REQ_EVENT, vcpu);
6891
b6c7a5dc
HB		 6892 return 0;
6893}
6894
d0bfb940
JK		 6895int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6896 struct kvm_guest_debug *dbg)
b6c7a5dc 6897{
355be0b9 6898 unsigned long rflags;
ae675ef0 6899 int i, r;
b6c7a5dc 6900
4f926bf2
JK		 6901 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6902 r = -EBUSY;
6903 if (vcpu->arch.exception.pending)
2122ff5e 6904 goto out;
4f926bf2
JK		 6905 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6906 kvm_queue_exception(vcpu, DB_VECTOR);
6907 else
6908 kvm_queue_exception(vcpu, BP_VECTOR);
6909 }
6910
91586a3b
JK		 6911 /*
6912 * Read rflags as long as potentially injected trace flags are still
6913 * filtered out.
6914 */
6915 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6916
6917 vcpu->guest_debug = dbg->control;
6918 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6919 vcpu->guest_debug = 0;
6920
6921 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6922 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6923 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6924 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6925 } else {
6926 for (i = 0; i < KVM_NR_DB_REGS; i++)
6927 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6928 }
c8639010 6929 kvm_update_dr7(vcpu);
ae675ef0 6930
f92653ee
JK		 6931 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6932 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6933 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6934
91586a3b
JK		 6935 /*
6936 * Trigger an rflags update that will inject or remove the trace
6937 * flags.
6938 */
6939 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6940
c8639010 6941 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6942
4f926bf2 6943 r = 0;
d0bfb940 6944
2122ff5e 6945out:
b6c7a5dc
HB		 6946
6947 return r;
6948}
6949
8b006791
ZX		 6950/*
6951 * Translate a guest virtual address to a guest physical address.
6952 */
6953int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6954 struct kvm_translation *tr)
6955{
6956 unsigned long vaddr = tr->linear_address;
6957 gpa_t gpa;
f656ce01 6958 int idx;
8b006791 6959
f656ce01 6960 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6961 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6962 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6963 tr->physical_address = gpa;
6964 tr->valid = gpa != UNMAPPED_GVA;
6965 tr->writeable = 1;
6966 tr->usermode = 0;
8b006791
ZX		 6967
6968 return 0;
6969}
6970
d0752060
HB		 6971int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6972{
98918833 6973 struct i387_fxsave_struct *fxsave =
7366ed77 6974 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 6975
d0752060
HB		 6976 memcpy(fpu->fpr, fxsave->st_space, 128);
6977 fpu->fcw = fxsave->cwd;
6978 fpu->fsw = fxsave->swd;
6979 fpu->ftwx = fxsave->twd;
6980 fpu->last_opcode = fxsave->fop;
6981 fpu->last_ip = fxsave->rip;
6982 fpu->last_dp = fxsave->rdp;
6983 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6984
d0752060
HB		 6985 return 0;
6986}
6987
6988int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6989{
98918833 6990 struct i387_fxsave_struct *fxsave =
7366ed77 6991 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 6992
d0752060
HB		 6993 memcpy(fxsave->st_space, fpu->fpr, 128);
6994 fxsave->cwd = fpu->fcw;
6995 fxsave->swd = fpu->fsw;
6996 fxsave->twd = fpu->ftwx;
6997 fxsave->fop = fpu->last_opcode;
6998 fxsave->rip = fpu->last_ip;
6999 fxsave->rdp = fpu->last_dp;
7000 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7001
d0752060
HB		 7002 return 0;
7003}
7004
0ee6a517 7005static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7006{
c0ee2cf6 7007 fpstate_init(&vcpu->arch.guest_fpu);
df1daba7 7008 if (cpu_has_xsaves)
7366ed77 7009 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7010 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7011
2acf923e
DC		 7012 /*
7013 * Ensure guest xcr0 is valid for loading
7014 */
7015 vcpu->arch.xcr0 = XSTATE_FP;
7016
ad312c7c 7017 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7018}
d0752060
HB		 7019
7020void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7021{
2608d7a1 7022 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7023 return;
7024
2acf923e
DC		 7025 /*
7026 * Restore all possible states in the guest,
7027 * and assume host would use all available bits.
7028 * Guest xcr0 would be loaded later.
7029 */
7030 kvm_put_guest_xcr0(vcpu);
d0752060 7031 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7032 __kernel_fpu_begin();
0e75c54f 7033 __copy_fpstate_to_fpregs(&vcpu->arch.guest_fpu);
0c04851c 7034 trace_kvm_fpu(1);
d0752060 7035}
d0752060
HB		 7036
7037void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7038{
2acf923e
DC		 7039 kvm_put_guest_xcr0(vcpu);
7040
d0752060
HB		 7041 if (!vcpu->guest_fpu_loaded)
7042 return;
7043
7044 vcpu->guest_fpu_loaded = 0;
4f836347 7045 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7046 __kernel_fpu_end();
f096ed85 7047 ++vcpu->stat.fpu_reload;
a8eeb04a 7048 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 7049 trace_kvm_fpu(0);
d0752060 7050}
e9b11c17
ZX		 7051
7052void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7053{
12f9a48f 7054 kvmclock_reset(vcpu);
7f1ea208 7055
f5f48ee1 7056 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7057 kvm_x86_ops->vcpu_free(vcpu);
7058}
7059
7060struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7061 unsigned int id)
7062{
6755bae8
ZA		 7063 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7064 printk_once(KERN_WARNING
7065 "kvm: SMP vm created on host with unstable TSC; "
7066 "guest TSC will not be reliable\n");
26e5215f
AK		 7067 return kvm_x86_ops->vcpu_create(kvm, id);
7068}
e9b11c17 7069
26e5215f
AK		 7070int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7071{
7072 int r;
e9b11c17 7073
0bed3b56 7074 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7075 r = vcpu_load(vcpu);
7076 if (r)
7077 return r;
57f252f2 7078 kvm_vcpu_reset(vcpu);
8a3c1a33 7079 kvm_mmu_setup(vcpu);
e9b11c17 7080 vcpu_put(vcpu);
e9b11c17 7081
26e5215f 7082 return r;
e9b11c17
ZX		 7083}
7084
31928aa5 7085void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7086{
8fe8ab46 7087 struct msr_data msr;
332967a3 7088 struct kvm *kvm = vcpu->kvm;
42897d86 7089
31928aa5
DD		 7090 if (vcpu_load(vcpu))
7091 return;
8fe8ab46
WA		 7092 msr.data = 0x0;
7093 msr.index = MSR_IA32_TSC;
7094 msr.host_initiated = true;
7095 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7096 vcpu_put(vcpu);
7097
332967a3
AJ		 7098 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7099 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7100}
7101
d40ccc62 7102void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7103{
9fc77441 7104 int r;
344d9588
GN		 7105 vcpu->arch.apf.msr_val = 0;
7106
9fc77441
MT		 7107 r = vcpu_load(vcpu);
7108 BUG_ON(r);
e9b11c17
ZX		 7109 kvm_mmu_unload(vcpu);
7110 vcpu_put(vcpu);
7111
7112 kvm_x86_ops->vcpu_free(vcpu);
7113}
7114
66450a21 7115void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 7116{
7460fb4a
AK		 7117 atomic_set(&vcpu->arch.nmi_queued, 0);
7118 vcpu->arch.nmi_pending = 0;
448fa4a9 7119 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7120 kvm_clear_interrupt_queue(vcpu);
7121 kvm_clear_exception_queue(vcpu);
448fa4a9 7122
42dbaa5a 7123 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7124 kvm_update_dr0123(vcpu);
6f43ed01 7125 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7126 kvm_update_dr6(vcpu);
42dbaa5a 7127 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7128 kvm_update_dr7(vcpu);
42dbaa5a 7129
1119022c
NA		 7130 vcpu->arch.cr2 = 0;
7131
3842d135 7132 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7133 vcpu->arch.apf.msr_val = 0;
c9aaa895 7134 vcpu->arch.st.msr_val = 0;
3842d135 7135
12f9a48f
GC		 7136 kvmclock_reset(vcpu);
7137
af585b92
GN		 7138 kvm_clear_async_pf_completion_queue(vcpu);
7139 kvm_async_pf_hash_reset(vcpu);
7140 vcpu->arch.apf.halted = false;
3842d135 7141
f5132b01
GN		 7142 kvm_pmu_reset(vcpu);
7143
66f7b72e
JS		 7144 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7145 vcpu->arch.regs_avail = ~0;
7146 vcpu->arch.regs_dirty = ~0;
7147
57f252f2 7148 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 7149}
7150
2b4a273b 7151void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7152{
7153 struct kvm_segment cs;
7154
7155 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7156 cs.selector = vector << 8;
7157 cs.base = vector << 12;
7158 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7159 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7160}
7161
13a34e06 7162int kvm_arch_hardware_enable(void)
e9b11c17 7163{
ca84d1a2
ZA		 7164 struct kvm *kvm;
7165 struct kvm_vcpu *vcpu;
7166 int i;
0dd6a6ed
ZA		 7167 int ret;
7168 u64 local_tsc;
7169 u64 max_tsc = 0;
7170 bool stable, backwards_tsc = false;
18863bdd
AK		 7171
7172 kvm_shared_msr_cpu_online();
13a34e06 7173 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7174 if (ret != 0)
7175 return ret;
7176
7177 local_tsc = native_read_tsc();
7178 stable = !check_tsc_unstable();
7179 list_for_each_entry(kvm, &vm_list, vm_list) {
7180 kvm_for_each_vcpu(i, vcpu, kvm) {
7181 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7182 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7183 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7184 backwards_tsc = true;
7185 if (vcpu->arch.last_host_tsc > max_tsc)
7186 max_tsc = vcpu->arch.last_host_tsc;
7187 }
7188 }
7189 }
7190
7191 /*
7192 * Sometimes, even reliable TSCs go backwards. This happens on
7193 * platforms that reset TSC during suspend or hibernate actions, but
7194 * maintain synchronization. We must compensate. Fortunately, we can
7195 * detect that condition here, which happens early in CPU bringup,
7196 * before any KVM threads can be running. Unfortunately, we can't
7197 * bring the TSCs fully up to date with real time, as we aren't yet far
7198 * enough into CPU bringup that we know how much real time has actually
7199 * elapsed; our helper function, get_kernel_ns() will be using boot
7200 * variables that haven't been updated yet.
7201 *
7202 * So we simply find the maximum observed TSC above, then record the
7203 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7204 * the adjustment will be applied. Note that we accumulate
7205 * adjustments, in case multiple suspend cycles happen before some VCPU
7206 * gets a chance to run again. In the event that no KVM threads get a
7207 * chance to run, we will miss the entire elapsed period, as we'll have
7208 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7209 * loose cycle time. This isn't too big a deal, since the loss will be
7210 * uniform across all VCPUs (not to mention the scenario is extremely
7211 * unlikely). It is possible that a second hibernate recovery happens
7212 * much faster than a first, causing the observed TSC here to be
7213 * smaller; this would require additional padding adjustment, which is
7214 * why we set last_host_tsc to the local tsc observed here.
7215 *
7216 * N.B. - this code below runs only on platforms with reliable TSC,
7217 * as that is the only way backwards_tsc is set above. Also note
7218 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7219 * have the same delta_cyc adjustment applied if backwards_tsc
7220 * is detected. Note further, this adjustment is only done once,
7221 * as we reset last_host_tsc on all VCPUs to stop this from being
7222 * called multiple times (one for each physical CPU bringup).
7223 *
4a969980 7224 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7225 * will be compensated by the logic in vcpu_load, which sets the TSC to
7226 * catchup mode. This will catchup all VCPUs to real time, but cannot
7227 * guarantee that they stay in perfect synchronization.
7228 */
7229 if (backwards_tsc) {
7230 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7231 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7232 list_for_each_entry(kvm, &vm_list, vm_list) {
7233 kvm_for_each_vcpu(i, vcpu, kvm) {
7234 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7235 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7236 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7237 }
7238
7239 /*
7240 * We have to disable TSC offset matching.. if you were
7241 * booting a VM while issuing an S4 host suspend....
7242 * you may have some problem. Solving this issue is
7243 * left as an exercise to the reader.
7244 */
7245 kvm->arch.last_tsc_nsec = 0;
7246 kvm->arch.last_tsc_write = 0;
7247 }
7248
7249 }
7250 return 0;
e9b11c17
ZX		 7251}
7252
13a34e06 7253void kvm_arch_hardware_disable(void)
e9b11c17 7254{
13a34e06
RK		 7255 kvm_x86_ops->hardware_disable();
7256 drop_user_return_notifiers();
e9b11c17
ZX		 7257}
7258
7259int kvm_arch_hardware_setup(void)
7260{
9e9c3fe4
NA		 7261 int r;
7262
7263 r = kvm_x86_ops->hardware_setup();
7264 if (r != 0)
7265 return r;
7266
7267 kvm_init_msr_list();
7268 return 0;
e9b11c17
ZX		 7269}
7270
7271void kvm_arch_hardware_unsetup(void)
7272{
7273 kvm_x86_ops->hardware_unsetup();
7274}
7275
7276void kvm_arch_check_processor_compat(void *rtn)
7277{
7278 kvm_x86_ops->check_processor_compatibility(rtn);
7279}
7280
3e515705
AK		 7281bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7282{
7283 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7284}
7285
54e9818f
GN		 7286struct static_key kvm_no_apic_vcpu __read_mostly;
7287
e9b11c17
ZX		 7288int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7289{
7290 struct page *page;
7291 struct kvm *kvm;
7292 int r;
7293
7294 BUG_ON(vcpu->kvm == NULL);
7295 kvm = vcpu->kvm;
7296
6aef266c 7297 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7298 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7299 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7300 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7301 else
a4535290 7302 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7303
7304 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7305 if (!page) {
7306 r = -ENOMEM;
7307 goto fail;
7308 }
ad312c7c 7309 vcpu->arch.pio_data = page_address(page);
e9b11c17 7310
cc578287 7311 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7312
e9b11c17
ZX		 7313 r = kvm_mmu_create(vcpu);
7314 if (r < 0)
7315 goto fail_free_pio_data;
7316
7317 if (irqchip_in_kernel(kvm)) {
7318 r = kvm_create_lapic(vcpu);
7319 if (r < 0)
7320 goto fail_mmu_destroy;
54e9818f
GN		 7321 } else
7322 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7323
890ca9ae
HY		 7324 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7325 GFP_KERNEL);
7326 if (!vcpu->arch.mce_banks) {
7327 r = -ENOMEM;
443c39bc 7328 goto fail_free_lapic;
890ca9ae
HY		 7329 }
7330 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7331
f1797359
WY		 7332 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7333 r = -ENOMEM;
f5f48ee1 7334 goto fail_free_mce_banks;
f1797359 7335 }
f5f48ee1 7336
0ee6a517 7337 fx_init(vcpu);
66f7b72e 7338
ba904635 7339 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7340 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7341
7342 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7343 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7344
5a4f55cd
EK		 7345 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7346
af585b92 7347 kvm_async_pf_hash_reset(vcpu);
f5132b01 7348 kvm_pmu_init(vcpu);
af585b92 7349
e9b11c17 7350 return 0;
0ee6a517 7351
f5f48ee1
SY		 7352fail_free_mce_banks:
7353 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7354fail_free_lapic:
7355 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7356fail_mmu_destroy:
7357 kvm_mmu_destroy(vcpu);
7358fail_free_pio_data:
ad312c7c 7359 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7360fail:
7361 return r;
7362}
7363
7364void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7365{
f656ce01
MT		 7366 int idx;
7367
f5132b01 7368 kvm_pmu_destroy(vcpu);
36cb93fd 7369 kfree(vcpu->arch.mce_banks);
e9b11c17 7370 kvm_free_lapic(vcpu);
f656ce01 7371 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7372 kvm_mmu_destroy(vcpu);
f656ce01 7373 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7374 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7375 if (!irqchip_in_kernel(vcpu->kvm))
7376 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7377}
d19a9cd2 7378
e790d9ef
RK		 7379void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7380{
ae97a3b8 7381 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7382}
7383
e08b9637 7384int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7385{
e08b9637
CO		 7386 if (type)
7387 return -EINVAL;
7388
6ef768fa 7389 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7390 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7391 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7392 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7393 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7394
5550af4d
SY		 7395 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7396 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7397 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7398 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7399 &kvm->arch.irq_sources_bitmap);
5550af4d 7400
038f8c11 7401 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7402 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7403 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7404
7405 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7406
7e44e449 7407 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7408 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7409
d89f5eff 7410 return 0;
d19a9cd2
ZX		 7411}
7412
7413static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7414{
9fc77441
MT		 7415 int r;
7416 r = vcpu_load(vcpu);
7417 BUG_ON(r);
d19a9cd2
ZX		 7418 kvm_mmu_unload(vcpu);
7419 vcpu_put(vcpu);
7420}
7421
7422static void kvm_free_vcpus(struct kvm *kvm)
7423{
7424 unsigned int i;
988a2cae 7425 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7426
7427 /*
7428 * Unpin any mmu pages first.
7429 */
af585b92
GN		 7430 kvm_for_each_vcpu(i, vcpu, kvm) {
7431 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7432 kvm_unload_vcpu_mmu(vcpu);
af585b92 7433 }
988a2cae
GN		 7434 kvm_for_each_vcpu(i, vcpu, kvm)
7435 kvm_arch_vcpu_free(vcpu);
7436
7437 mutex_lock(&kvm->lock);
7438 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7439 kvm->vcpus[i] = NULL;
d19a9cd2 7440
988a2cae
GN		 7441 atomic_set(&kvm->online_vcpus, 0);
7442 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7443}
7444
ad8ba2cd
SY		 7445void kvm_arch_sync_events(struct kvm *kvm)
7446{
332967a3 7447 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7448 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7449 kvm_free_all_assigned_devices(kvm);
aea924f6 7450 kvm_free_pit(kvm);
ad8ba2cd
SY		 7451}
7452
d19a9cd2
ZX		 7453void kvm_arch_destroy_vm(struct kvm *kvm)
7454{
27469d29
AH		 7455 if (current->mm == kvm->mm) {
7456 /*
7457 * Free memory regions allocated on behalf of userspace,
7458 * unless the the memory map has changed due to process exit
7459 * or fd copying.
7460 */
7461 struct kvm_userspace_memory_region mem;
7462 memset(&mem, 0, sizeof(mem));
7463 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7464 kvm_set_memory_region(kvm, &mem);
7465
7466 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7467 kvm_set_memory_region(kvm, &mem);
7468
7469 mem.slot = TSS_PRIVATE_MEMSLOT;
7470 kvm_set_memory_region(kvm, &mem);
7471 }
6eb55818 7472 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7473 kfree(kvm->arch.vpic);
7474 kfree(kvm->arch.vioapic);
d19a9cd2 7475 kvm_free_vcpus(kvm);
1e08ec4a 7476 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7477}
0de10343 7478
5587027c 7479void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7480 struct kvm_memory_slot *dont)
7481{
7482 int i;
7483
d89cc617
TY		 7484 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7485 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7486 kvfree(free->arch.rmap[i]);
d89cc617 7487 free->arch.rmap[i] = NULL;
77d11309 7488 }
d89cc617
TY		 7489 if (i == 0)
7490 continue;
7491
7492 if (!dont || free->arch.lpage_info[i - 1] !=
7493 dont->arch.lpage_info[i - 1]) {
548ef284 7494 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7495 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7496 }
7497 }
7498}
7499
5587027c
AK		 7500int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7501 unsigned long npages)
db3fe4eb
TY		 7502{
7503 int i;
7504
d89cc617 7505 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7506 unsigned long ugfn;
7507 int lpages;
d89cc617 7508 int level = i + 1;
db3fe4eb
TY		 7509
7510 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7511 slot->base_gfn, level) + 1;
7512
d89cc617
TY		 7513 slot->arch.rmap[i] =
7514 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7515 if (!slot->arch.rmap[i])
77d11309 7516 goto out_free;
d89cc617
TY		 7517 if (i == 0)
7518 continue;
77d11309 7519
d89cc617
TY		 7520 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7521 sizeof(*slot->arch.lpage_info[i - 1]));
7522 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7523 goto out_free;
7524
7525 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7526 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7527 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7528 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7529 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7530 /*
7531 * If the gfn and userspace address are not aligned wrt each
7532 * other, or if explicitly asked to, disable large page
7533 * support for this slot
7534 */
7535 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7536 !kvm_largepages_enabled()) {
7537 unsigned long j;
7538
7539 for (j = 0; j < lpages; ++j)
d89cc617 7540 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7541 }
7542 }
7543
7544 return 0;
7545
7546out_free:
d89cc617 7547 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7548 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7549 slot->arch.rmap[i] = NULL;
7550 if (i == 0)
7551 continue;
7552
548ef284 7553 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7554 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7555 }
7556 return -ENOMEM;
7557}
7558
e59dbe09
TY		 7559void kvm_arch_memslots_updated(struct kvm *kvm)
7560{
e6dff7d1
TY		 7561 /*
7562 * memslots->generation has been incremented.
7563 * mmio generation may have reached its maximum value.
7564 */
7565 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7566}
7567
f7784b8e
MT		 7568int kvm_arch_prepare_memory_region(struct kvm *kvm,
7569 struct kvm_memory_slot *memslot,
f7784b8e 7570 struct kvm_userspace_memory_region *mem,
7b6195a9 7571 enum kvm_mr_change change)
0de10343 7572{
7a905b14
TY		 7573 /*
7574 * Only private memory slots need to be mapped here since
7575 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7576 */
7b6195a9 7577 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7578 unsigned long userspace_addr;
604b38ac 7579
7a905b14
TY		 7580 /*
7581 * MAP_SHARED to prevent internal slot pages from being moved
7582 * by fork()/COW.
7583 */
7b6195a9 7584 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7585 PROT_READ | PROT_WRITE,
7586 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7587
7a905b14
TY		 7588 if (IS_ERR((void *)userspace_addr))
7589 return PTR_ERR((void *)userspace_addr);
604b38ac 7590
7a905b14 7591 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7592 }
7593
f7784b8e
MT		 7594 return 0;
7595}
7596
88178fd4
KH		 7597static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7598 struct kvm_memory_slot *new)
7599{
7600 /* Still write protect RO slot */
7601 if (new->flags & KVM_MEM_READONLY) {
7602 kvm_mmu_slot_remove_write_access(kvm, new);
7603 return;
7604 }
7605
7606 /*
7607 * Call kvm_x86_ops dirty logging hooks when they are valid.
7608 *
7609 * kvm_x86_ops->slot_disable_log_dirty is called when:
7610 *
7611 * - KVM_MR_CREATE with dirty logging is disabled
7612 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7613 *
7614 * The reason is, in case of PML, we need to set D-bit for any slots
7615 * with dirty logging disabled in order to eliminate unnecessary GPA
7616 * logging in PML buffer (and potential PML buffer full VMEXT). This
7617 * guarantees leaving PML enabled during guest's lifetime won't have
7618 * any additonal overhead from PML when guest is running with dirty
7619 * logging disabled for memory slots.
7620 *
7621 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7622 * to dirty logging mode.
7623 *
7624 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7625 *
7626 * In case of write protect:
7627 *
7628 * Write protect all pages for dirty logging.
7629 *
7630 * All the sptes including the large sptes which point to this
7631 * slot are set to readonly. We can not create any new large
7632 * spte on this slot until the end of the logging.
7633 *
7634 * See the comments in fast_page_fault().
7635 */
7636 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7637 if (kvm_x86_ops->slot_enable_log_dirty)
7638 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7639 else
7640 kvm_mmu_slot_remove_write_access(kvm, new);
7641 } else {
7642 if (kvm_x86_ops->slot_disable_log_dirty)
7643 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7644 }
7645}
7646
f7784b8e
MT		 7647void kvm_arch_commit_memory_region(struct kvm *kvm,
7648 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7649 const struct kvm_memory_slot *old,
7650 enum kvm_mr_change change)
f7784b8e 7651{
1c91cad4 7652 struct kvm_memory_slot *new;
8482644a 7653 int nr_mmu_pages = 0;
f7784b8e 7654
8482644a 7655 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7656 int ret;
7657
8482644a
TY		 7658 ret = vm_munmap(old->userspace_addr,
7659 old->npages * PAGE_SIZE);
f7784b8e
MT		 7660 if (ret < 0)
7661 printk(KERN_WARNING
7662 "kvm_vm_ioctl_set_memory_region: "
7663 "failed to munmap memory\n");
7664 }
7665
48c0e4e9
XG		 7666 if (!kvm->arch.n_requested_mmu_pages)
7667 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7668
48c0e4e9 7669 if (nr_mmu_pages)
0de10343 7670 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4
KH		 7671
7672 /* It's OK to get 'new' slot here as it has already been installed */
7673 new = id_to_memslot(kvm->memslots, mem->slot);
7674
3ea3b7fa
WL		 7675 /*
7676 * Dirty logging tracks sptes in 4k granularity, meaning that large
7677 * sptes have to be split. If live migration is successful, the guest
7678 * in the source machine will be destroyed and large sptes will be
7679 * created in the destination. However, if the guest continues to run
7680 * in the source machine (for example if live migration fails), small
7681 * sptes will remain around and cause bad performance.
7682 *
7683 * Scan sptes if dirty logging has been stopped, dropping those
7684 * which can be collapsed into a single large-page spte. Later
7685 * page faults will create the large-page sptes.
7686 */
7687 if ((change != KVM_MR_DELETE) &&
7688 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7689 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7690 kvm_mmu_zap_collapsible_sptes(kvm, new);
7691
c972f3b1 7692 /*
88178fd4 7693 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7694 *
88178fd4
KH		 7695 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7696 * been zapped so no dirty logging staff is needed for old slot. For
7697 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7698 * new and it's also covered when dealing with the new slot.
c972f3b1 7699 */
88178fd4
KH		 7700 if (change != KVM_MR_DELETE)
7701 kvm_mmu_slot_apply_flags(kvm, new);
0de10343 7702}
1d737c8a 7703
2df72e9b 7704void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7705{
6ca18b69 7706 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7707}
7708
2df72e9b
MT		 7709void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7710 struct kvm_memory_slot *slot)
7711{
6ca18b69 7712 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7713}
7714
1d737c8a
ZX		 7715int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7716{
b6b8a145
JK		 7717 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7718 kvm_x86_ops->check_nested_events(vcpu, false);
7719
af585b92
GN		 7720 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7721 !vcpu->arch.apf.halted)
7722 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7723 || kvm_apic_has_events(vcpu)
6aef266c 7724 || vcpu->arch.pv.pv_unhalted
7460fb4a 7725 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7726 (kvm_arch_interrupt_allowed(vcpu) &&
7727 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7728}
5736199a 7729
b6d33834 7730int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7731{
b6d33834 7732 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7733}
78646121
GN		 7734
7735int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7736{
7737 return kvm_x86_ops->interrupt_allowed(vcpu);
7738}
229456fc 7739
82b32774 7740unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7741{
82b32774
NA		 7742 if (is_64_bit_mode(vcpu))
7743 return kvm_rip_read(vcpu);
7744 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7745 kvm_rip_read(vcpu));
7746}
7747EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7748
82b32774
NA		 7749bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7750{
7751 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7752}
7753EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7754
94fe45da
JK		 7755unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7756{
7757 unsigned long rflags;
7758
7759 rflags = kvm_x86_ops->get_rflags(vcpu);
7760 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7761 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7762 return rflags;
7763}
7764EXPORT_SYMBOL_GPL(kvm_get_rflags);
7765
6addfc42 7766static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7767{
7768 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7769 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7770 rflags |= X86_EFLAGS_TF;
94fe45da 7771 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7772}
7773
7774void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7775{
7776 __kvm_set_rflags(vcpu, rflags);
3842d135 7777 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7778}
7779EXPORT_SYMBOL_GPL(kvm_set_rflags);
7780
56028d08
GN		 7781void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7782{
7783 int r;
7784
fb67e14f 7785 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7786 work->wakeup_all)
56028d08
GN		 7787 return;
7788
7789 r = kvm_mmu_reload(vcpu);
7790 if (unlikely(r))
7791 return;
7792
fb67e14f
XG		 7793 if (!vcpu->arch.mmu.direct_map &&
7794 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7795 return;
7796
56028d08
GN		 7797 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7798}
7799
af585b92
GN		 7800static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7801{
7802 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7803}
7804
7805static inline u32 kvm_async_pf_next_probe(u32 key)
7806{
7807 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7808}
7809
7810static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7811{
7812 u32 key = kvm_async_pf_hash_fn(gfn);
7813
7814 while (vcpu->arch.apf.gfns[key] != ~0)
7815 key = kvm_async_pf_next_probe(key);
7816
7817 vcpu->arch.apf.gfns[key] = gfn;
7818}
7819
7820static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7821{
7822 int i;
7823 u32 key = kvm_async_pf_hash_fn(gfn);
7824
7825 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7826 (vcpu->arch.apf.gfns[key] != gfn &&
7827 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7828 key = kvm_async_pf_next_probe(key);
7829
7830 return key;
7831}
7832
7833bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7834{
7835 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7836}
7837
7838static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7839{
7840 u32 i, j, k;
7841
7842 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7843 while (true) {
7844 vcpu->arch.apf.gfns[i] = ~0;
7845 do {
7846 j = kvm_async_pf_next_probe(j);
7847 if (vcpu->arch.apf.gfns[j] == ~0)
7848 return;
7849 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7850 /*
7851 * k lies cyclically in ]i,j]
7852 * | i.k.j |
7853 * |....j i.k.| or |.k..j i...|
7854 */
7855 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7856 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7857 i = j;
7858 }
7859}
7860
7c90705b
GN		 7861static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7862{
7863
7864 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7865 sizeof(val));
7866}
7867
af585b92
GN		 7868void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7869 struct kvm_async_pf *work)
7870{
6389ee94
AK		 7871 struct x86_exception fault;
7872
7c90705b 7873 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7874 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7875
7876 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7877 (vcpu->arch.apf.send_user_only &&
7878 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7879 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7880 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7881 fault.vector = PF_VECTOR;
7882 fault.error_code_valid = true;
7883 fault.error_code = 0;
7884 fault.nested_page_fault = false;
7885 fault.address = work->arch.token;
7886 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7887 }
af585b92
GN		 7888}
7889
7890void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7891 struct kvm_async_pf *work)
7892{
6389ee94
AK		 7893 struct x86_exception fault;
7894
7c90705b 7895 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7896 if (work->wakeup_all)
7c90705b
GN		 7897 work->arch.token = ~0; /* broadcast wakeup */
7898 else
7899 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7900
7901 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7902 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7903 fault.vector = PF_VECTOR;
7904 fault.error_code_valid = true;
7905 fault.error_code = 0;
7906 fault.nested_page_fault = false;
7907 fault.address = work->arch.token;
7908 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7909 }
e6d53e3b 7910 vcpu->arch.apf.halted = false;
a4fa1635 7911 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7912}
7913
7914bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7915{
7916 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7917 return true;
7918 else
7919 return !kvm_event_needs_reinjection(vcpu) &&
7920 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7921}
7922
e0f0bbc5
AW		 7923void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7924{
7925 atomic_inc(&kvm->arch.noncoherent_dma_count);
7926}
7927EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7928
7929void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7930{
7931 atomic_dec(&kvm->arch.noncoherent_dma_count);
7932}
7933EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7934
7935bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7936{
7937 return atomic_read(&kvm->arch.noncoherent_dma_count);
7938}
7939EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7940
229456fc
MT		 7941EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7942EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7943EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7944EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7945EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7946EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7947EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7948EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7949EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7950EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7951EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7952EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7953EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 7954EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 7955EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
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