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KVM: x86: fix interrupt window handling in split IRQ chip case
[mirror_ubuntu-focal-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
893590c7 126static bool __read_mostly backwards_tsc_observed = false;
16a96021 127
18863bdd
AK		 128#define KVM_NR_SHARED_MSRS 16
129
130struct kvm_shared_msrs_global {
131 int nr;
2bf78fa7 132 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 133};
134
135struct kvm_shared_msrs {
136 struct user_return_notifier urn;
137 bool registered;
2bf78fa7
SY		 138 struct kvm_shared_msr_values {
139 u64 host;
140 u64 curr;
141 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 145static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 146
417bc304 147struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 148 { "pf_fixed", VCPU_STAT(pf_fixed) },
149 { "pf_guest", VCPU_STAT(pf_guest) },
150 { "tlb_flush", VCPU_STAT(tlb_flush) },
151 { "invlpg", VCPU_STAT(invlpg) },
152 { "exits", VCPU_STAT(exits) },
153 { "io_exits", VCPU_STAT(io_exits) },
154 { "mmio_exits", VCPU_STAT(mmio_exits) },
155 { "signal_exits", VCPU_STAT(signal_exits) },
156 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 157 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 158 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 159 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 160 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 161 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 162 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 163 { "request_irq", VCPU_STAT(request_irq_exits) },
164 { "irq_exits", VCPU_STAT(irq_exits) },
165 { "host_state_reload", VCPU_STAT(host_state_reload) },
166 { "efer_reload", VCPU_STAT(efer_reload) },
167 { "fpu_reload", VCPU_STAT(fpu_reload) },
168 { "insn_emulation", VCPU_STAT(insn_emulation) },
169 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 170 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 171 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 172 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
173 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
174 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
175 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
176 { "mmu_flooded", VM_STAT(mmu_flooded) },
177 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 178 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 179 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 180 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 181 { "largepages", VM_STAT(lpages) },
417bc304
HB		 182 { NULL }
183};
184
2acf923e
DC		 185u64 __read_mostly host_xcr0;
186
b6785def 187static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 188
af585b92
GN		 189static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
190{
191 int i;
192 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
193 vcpu->arch.apf.gfns[i] = ~0;
194}
195
18863bdd
AK		 196static void kvm_on_user_return(struct user_return_notifier *urn)
197{
198 unsigned slot;
18863bdd
AK		 199 struct kvm_shared_msrs *locals
200 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 201 struct kvm_shared_msr_values *values;
18863bdd
AK		 202
203 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 204 values = &locals->values[slot];
205 if (values->host != values->curr) {
206 wrmsrl(shared_msrs_global.msrs[slot], values->host);
207 values->curr = values->host;
18863bdd
AK		 208 }
209 }
210 locals->registered = false;
211 user_return_notifier_unregister(urn);
212}
213
2bf78fa7 214static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 215{
18863bdd 216 u64 value;
013f6a5d
MT		 217 unsigned int cpu = smp_processor_id();
218 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 219
2bf78fa7
SY		 220 /* only read, and nobody should modify it at this time,
221 * so don't need lock */
222 if (slot >= shared_msrs_global.nr) {
223 printk(KERN_ERR "kvm: invalid MSR slot!");
224 return;
225 }
226 rdmsrl_safe(msr, &value);
227 smsr->values[slot].host = value;
228 smsr->values[slot].curr = value;
229}
230
231void kvm_define_shared_msr(unsigned slot, u32 msr)
232{
0123be42 233 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 234 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 235 if (slot >= shared_msrs_global.nr)
236 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 237}
238EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
239
240static void kvm_shared_msr_cpu_online(void)
241{
242 unsigned i;
18863bdd
AK		 243
244 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 245 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 246}
247
8b3c3104 248int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 249{
013f6a5d
MT		 250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 252 int err;
18863bdd 253
2bf78fa7 254 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 255 return 0;
2bf78fa7 256 smsr->values[slot].curr = value;
8b3c3104
AH		 257 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
258 if (err)
259 return 1;
260
18863bdd
AK		 261 if (!smsr->registered) {
262 smsr->urn.on_user_return = kvm_on_user_return;
263 user_return_notifier_register(&smsr->urn);
264 smsr->registered = true;
265 }
8b3c3104 266 return 0;
18863bdd
AK		 267}
268EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
269
13a34e06 270static void drop_user_return_notifiers(void)
3548bab5 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 274
275 if (smsr->registered)
276 kvm_on_user_return(&smsr->urn);
277}
278
6866b83e
CO		 279u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
280{
8a5a87d9 281 return vcpu->arch.apic_base;
6866b83e
CO		 282}
283EXPORT_SYMBOL_GPL(kvm_get_apic_base);
284
58cb628d
JK		 285int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
286{
287 u64 old_state = vcpu->arch.apic_base &
288 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
289 u64 new_state = msr_info->data &
290 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
291 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
292 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
293
294 if (!msr_info->host_initiated &&
295 ((msr_info->data & reserved_bits) != 0 ||
296 new_state == X2APIC_ENABLE ||
297 (new_state == MSR_IA32_APICBASE_ENABLE &&
298 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
299 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
300 old_state == 0)))
301 return 1;
302
303 kvm_lapic_set_base(vcpu, msr_info->data);
304 return 0;
6866b83e
CO		 305}
306EXPORT_SYMBOL_GPL(kvm_set_apic_base);
307
2605fc21 308asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 309{
310 /* Fault while not rebooting. We want the trace. */
311 BUG();
312}
313EXPORT_SYMBOL_GPL(kvm_spurious_fault);
314
3fd28fce
ED		 315#define EXCPT_BENIGN 0
316#define EXCPT_CONTRIBUTORY 1
317#define EXCPT_PF 2
318
319static int exception_class(int vector)
320{
321 switch (vector) {
322 case PF_VECTOR:
323 return EXCPT_PF;
324 case DE_VECTOR:
325 case TS_VECTOR:
326 case NP_VECTOR:
327 case SS_VECTOR:
328 case GP_VECTOR:
329 return EXCPT_CONTRIBUTORY;
330 default:
331 break;
332 }
333 return EXCPT_BENIGN;
334}
335
d6e8c854
NA		 336#define EXCPT_FAULT 0
337#define EXCPT_TRAP 1
338#define EXCPT_ABORT 2
339#define EXCPT_INTERRUPT 3
340
341static int exception_type(int vector)
342{
343 unsigned int mask;
344
345 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
346 return EXCPT_INTERRUPT;
347
348 mask = 1 << vector;
349
350 /* #DB is trap, as instruction watchpoints are handled elsewhere */
351 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
352 return EXCPT_TRAP;
353
354 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
355 return EXCPT_ABORT;
356
357 /* Reserved exceptions will result in fault */
358 return EXCPT_FAULT;
359}
360
3fd28fce 361static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 362 unsigned nr, bool has_error, u32 error_code,
363 bool reinject)
3fd28fce
ED		 364{
365 u32 prev_nr;
366 int class1, class2;
367
3842d135
AK		 368 kvm_make_request(KVM_REQ_EVENT, vcpu);
369
3fd28fce
ED		 370 if (!vcpu->arch.exception.pending) {
371 queue:
3ffb2468
NA		 372 if (has_error && !is_protmode(vcpu))
373 has_error = false;
3fd28fce
ED		 374 vcpu->arch.exception.pending = true;
375 vcpu->arch.exception.has_error_code = has_error;
376 vcpu->arch.exception.nr = nr;
377 vcpu->arch.exception.error_code = error_code;
3f0fd292 378 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 379 return;
380 }
381
382 /* to check exception */
383 prev_nr = vcpu->arch.exception.nr;
384 if (prev_nr == DF_VECTOR) {
385 /* triple fault -> shutdown */
a8eeb04a 386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 387 return;
388 }
389 class1 = exception_class(prev_nr);
390 class2 = exception_class(nr);
391 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
392 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
393 /* generate double fault per SDM Table 5-5 */
394 vcpu->arch.exception.pending = true;
395 vcpu->arch.exception.has_error_code = true;
396 vcpu->arch.exception.nr = DF_VECTOR;
397 vcpu->arch.exception.error_code = 0;
398 } else
399 /* replace previous exception with a new one in a hope
400 that instruction re-execution will regenerate lost
401 exception */
402 goto queue;
403}
404
298101da
AK		 405void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
406{
ce7ddec4 407 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 408}
409EXPORT_SYMBOL_GPL(kvm_queue_exception);
410
ce7ddec4
JR		 411void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
412{
413 kvm_multiple_exception(vcpu, nr, false, 0, true);
414}
415EXPORT_SYMBOL_GPL(kvm_requeue_exception);
416
db8fcefa 417void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 418{
db8fcefa
AP		 419 if (err)
420 kvm_inject_gp(vcpu, 0);
421 else
422 kvm_x86_ops->skip_emulated_instruction(vcpu);
423}
424EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 425
6389ee94 426void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 427{
428 ++vcpu->stat.pf_guest;
6389ee94
AK		 429 vcpu->arch.cr2 = fault->address;
430 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 431}
27d6c865 432EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 433
ef54bcfe 434static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 435{
6389ee94
AK		 436 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
437 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 438 else
6389ee94 439 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 440
441 return fault->nested_page_fault;
d4f8cf66
JR		 442}
443
3419ffc8
SY		 444void kvm_inject_nmi(struct kvm_vcpu *vcpu)
445{
7460fb4a
AK		 446 atomic_inc(&vcpu->arch.nmi_queued);
447 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 448}
449EXPORT_SYMBOL_GPL(kvm_inject_nmi);
450
298101da
AK		 451void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
452{
ce7ddec4 453 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 454}
455EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
456
ce7ddec4
JR		 457void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
458{
459 kvm_multiple_exception(vcpu, nr, true, error_code, true);
460}
461EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
462
0a79b009
AK		 463/*
464 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
465 * a #GP and return false.
466 */
467bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 468{
0a79b009
AK		 469 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
470 return true;
471 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
472 return false;
298101da 473}
0a79b009 474EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 475
16f8a6f9
NA		 476bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
477{
478 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
479 return true;
480
481 kvm_queue_exception(vcpu, UD_VECTOR);
482 return false;
483}
484EXPORT_SYMBOL_GPL(kvm_require_dr);
485
ec92fe44
JR		 486/*
487 * This function will be used to read from the physical memory of the currently
54bf36aa 488 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 489 * can read from guest physical or from the guest's guest physical memory.
490 */
491int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
492 gfn_t ngfn, void *data, int offset, int len,
493 u32 access)
494{
54987b7a 495 struct x86_exception exception;
ec92fe44
JR		 496 gfn_t real_gfn;
497 gpa_t ngpa;
498
499 ngpa = gfn_to_gpa(ngfn);
54987b7a 500 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 501 if (real_gfn == UNMAPPED_GVA)
502 return -EFAULT;
503
504 real_gfn = gpa_to_gfn(real_gfn);
505
54bf36aa 506 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 507}
508EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
509
69b0049a 510static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 511 void *data, int offset, int len, u32 access)
512{
513 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
514 data, offset, len, access);
515}
516
a03490ed
CO		 517/*
518 * Load the pae pdptrs. Return true is they are all valid.
519 */
ff03a073 520int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 521{
522 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
523 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
524 int i;
525 int ret;
ff03a073 526 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 527
ff03a073
JR		 528 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
529 offset * sizeof(u64), sizeof(pdpte),
530 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 531 if (ret < 0) {
532 ret = 0;
533 goto out;
534 }
535 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 536 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 537 (pdpte[i] &
538 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 539 ret = 0;
540 goto out;
541 }
542 }
543 ret = 1;
544
ff03a073 545 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 546 __set_bit(VCPU_EXREG_PDPTR,
547 (unsigned long *)&vcpu->arch.regs_avail);
548 __set_bit(VCPU_EXREG_PDPTR,
549 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 550out:
a03490ed
CO		 551
552 return ret;
553}
cc4b6871 554EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 555
d835dfec
AK		 556static bool pdptrs_changed(struct kvm_vcpu *vcpu)
557{
ff03a073 558 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 559 bool changed = true;
3d06b8bf
JR		 560 int offset;
561 gfn_t gfn;
d835dfec
AK		 562 int r;
563
564 if (is_long_mode(vcpu) || !is_pae(vcpu))
565 return false;
566
6de4f3ad
AK		 567 if (!test_bit(VCPU_EXREG_PDPTR,
568 (unsigned long *)&vcpu->arch.regs_avail))
569 return true;
570
9f8fe504
AK		 571 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
572 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 573 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
574 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 575 if (r < 0)
576 goto out;
ff03a073 577 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 578out:
d835dfec
AK		 579
580 return changed;
581}
582
49a9b07e 583int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 584{
aad82703 585 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 586 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 587
f9a48e6a
AK		 588 cr0 |= X86_CR0_ET;
589
ab344828 590#ifdef CONFIG_X86_64
0f12244f
GN		 591 if (cr0 & 0xffffffff00000000UL)
592 return 1;
ab344828
GN		 593#endif
594
595 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 596
0f12244f
GN		 597 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
598 return 1;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
601 return 1;
a03490ed
CO		 602
603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
604#ifdef CONFIG_X86_64
f6801dff 605 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 606 int cs_db, cs_l;
607
0f12244f
GN		 608 if (!is_pae(vcpu))
609 return 1;
a03490ed 610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 611 if (cs_l)
612 return 1;
a03490ed
CO		 613 } else
614#endif
ff03a073 615 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 616 kvm_read_cr3(vcpu)))
0f12244f 617 return 1;
a03490ed
CO		 618 }
619
ad756a16
MJ		 620 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
621 return 1;
622
a03490ed 623 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 624
d170c419 625 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 626 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 627 kvm_async_pf_hash_reset(vcpu);
628 }
e5f3f027 629
aad82703
SY		 630 if ((cr0 ^ old_cr0) & update_bits)
631 kvm_mmu_reset_context(vcpu);
b18d5431 632
879ae188
LE		 633 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
634 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
635 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 636 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
637
0f12244f
GN		 638 return 0;
639}
2d3ad1f4 640EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 641
2d3ad1f4 642void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 643{
49a9b07e 644 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 645}
2d3ad1f4 646EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 647
42bdf991
MT		 648static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
649{
650 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
651 !vcpu->guest_xcr0_loaded) {
652 /* kvm_set_xcr() also depends on this */
653 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
654 vcpu->guest_xcr0_loaded = 1;
655 }
656}
657
658static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
659{
660 if (vcpu->guest_xcr0_loaded) {
661 if (vcpu->arch.xcr0 != host_xcr0)
662 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
663 vcpu->guest_xcr0_loaded = 0;
664 }
665}
666
69b0049a 667static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 668{
56c103ec
LJ		 669 u64 xcr0 = xcr;
670 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 671 u64 valid_bits;
2acf923e
DC		 672
673 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
674 if (index != XCR_XFEATURE_ENABLED_MASK)
675 return 1;
d91cab78 676 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 677 return 1;
d91cab78 678 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 679 return 1;
46c34cb0
PB		 680
681 /*
682 * Do not allow the guest to set bits that we do not support
683 * saving. However, xcr0 bit 0 is always set, even if the
684 * emulated CPU does not support XSAVE (see fx_init).
685 */
d91cab78 686 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 687 if (xcr0 & ~valid_bits)
2acf923e 688 return 1;
46c34cb0 689
d91cab78
DH		 690 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
691 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 692 return 1;
693
d91cab78
DH		 694 if (xcr0 & XFEATURE_MASK_AVX512) {
695 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 696 return 1;
d91cab78 697 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 698 return 1;
699 }
42bdf991 700 kvm_put_guest_xcr0(vcpu);
2acf923e 701 vcpu->arch.xcr0 = xcr0;
56c103ec 702
d91cab78 703 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 704 kvm_update_cpuid(vcpu);
2acf923e
DC		 705 return 0;
706}
707
708int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
709{
764bcbc5
Z		 710 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
711 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 712 kvm_inject_gp(vcpu, 0);
713 return 1;
714 }
715 return 0;
716}
717EXPORT_SYMBOL_GPL(kvm_set_xcr);
718
a83b29c6 719int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 720{
fc78f519 721 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 722 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
723 X86_CR4_SMEP | X86_CR4_SMAP;
724
0f12244f
GN		 725 if (cr4 & CR4_RESERVED_BITS)
726 return 1;
a03490ed 727
2acf923e
DC		 728 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
729 return 1;
730
c68b734f
YW		 731 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
732 return 1;
733
97ec8c06
FW		 734 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
735 return 1;
736
afcbf13f 737 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 738 return 1;
739
a03490ed 740 if (is_long_mode(vcpu)) {
0f12244f
GN		 741 if (!(cr4 & X86_CR4_PAE))
742 return 1;
a2edf57f
AK		 743 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
744 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 745 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
746 kvm_read_cr3(vcpu)))
0f12244f
GN		 747 return 1;
748
ad756a16
MJ		 749 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
750 if (!guest_cpuid_has_pcid(vcpu))
751 return 1;
752
753 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
754 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
755 return 1;
756 }
757
5e1746d6 758 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 759 return 1;
a03490ed 760
ad756a16
MJ		 761 if (((cr4 ^ old_cr4) & pdptr_bits) ||
762 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 763 kvm_mmu_reset_context(vcpu);
0f12244f 764
2acf923e 765 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 766 kvm_update_cpuid(vcpu);
2acf923e 767
0f12244f
GN		 768 return 0;
769}
2d3ad1f4 770EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 771
2390218b 772int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 773{
ac146235 774#ifdef CONFIG_X86_64
9d88fca7 775 cr3 &= ~CR3_PCID_INVD;
ac146235 776#endif
9d88fca7 777
9f8fe504 778 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 779 kvm_mmu_sync_roots(vcpu);
77c3913b 780 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 781 return 0;
d835dfec
AK		 782 }
783
a03490ed 784 if (is_long_mode(vcpu)) {
d9f89b88
JK		 785 if (cr3 & CR3_L_MODE_RESERVED_BITS)
786 return 1;
787 } else if (is_pae(vcpu) && is_paging(vcpu) &&
788 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 789 return 1;
a03490ed 790
0f12244f 791 vcpu->arch.cr3 = cr3;
aff48baa 792 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 793 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 794 return 0;
795}
2d3ad1f4 796EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 797
eea1cff9 798int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 799{
0f12244f
GN		 800 if (cr8 & CR8_RESERVED_BITS)
801 return 1;
35754c98 802 if (lapic_in_kernel(vcpu))
a03490ed
CO		 803 kvm_lapic_set_tpr(vcpu, cr8);
804 else
ad312c7c 805 vcpu->arch.cr8 = cr8;
0f12244f
GN		 806 return 0;
807}
2d3ad1f4 808EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 809
2d3ad1f4 810unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 811{
35754c98 812 if (lapic_in_kernel(vcpu))
a03490ed
CO		 813 return kvm_lapic_get_cr8(vcpu);
814 else
ad312c7c 815 return vcpu->arch.cr8;
a03490ed 816}
2d3ad1f4 817EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 818
ae561ede
NA		 819static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
820{
821 int i;
822
823 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
824 for (i = 0; i < KVM_NR_DB_REGS; i++)
825 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
826 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
827 }
828}
829
73aaf249
JK		 830static void kvm_update_dr6(struct kvm_vcpu *vcpu)
831{
832 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
833 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
834}
835
c8639010
JK		 836static void kvm_update_dr7(struct kvm_vcpu *vcpu)
837{
838 unsigned long dr7;
839
840 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
841 dr7 = vcpu->arch.guest_debug_dr7;
842 else
843 dr7 = vcpu->arch.dr7;
844 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 845 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
846 if (dr7 & DR7_BP_EN_MASK)
847 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 848}
849
6f43ed01
NA		 850static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
851{
852 u64 fixed = DR6_FIXED_1;
853
854 if (!guest_cpuid_has_rtm(vcpu))
855 fixed |= DR6_RTM;
856 return fixed;
857}
858
338dbc97 859static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 860{
861 switch (dr) {
862 case 0 ... 3:
863 vcpu->arch.db[dr] = val;
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 vcpu->arch.eff_db[dr] = val;
866 break;
867 case 4:
020df079
GN		 868 /* fall through */
869 case 6:
338dbc97
GN		 870 if (val & 0xffffffff00000000ULL)
871 return -1; /* #GP */
6f43ed01 872 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 873 kvm_update_dr6(vcpu);
020df079
GN		 874 break;
875 case 5:
020df079
GN		 876 /* fall through */
877 default: /* 7 */
338dbc97
GN		 878 if (val & 0xffffffff00000000ULL)
879 return -1; /* #GP */
020df079 880 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 881 kvm_update_dr7(vcpu);
020df079
GN		 882 break;
883 }
884
885 return 0;
886}
338dbc97
GN		 887
888int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
889{
16f8a6f9 890 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 891 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 892 return 1;
893 }
894 return 0;
338dbc97 895}
020df079
GN		 896EXPORT_SYMBOL_GPL(kvm_set_dr);
897
16f8a6f9 898int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 899{
900 switch (dr) {
901 case 0 ... 3:
902 *val = vcpu->arch.db[dr];
903 break;
904 case 4:
020df079
GN		 905 /* fall through */
906 case 6:
73aaf249
JK		 907 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
908 *val = vcpu->arch.dr6;
909 else
910 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 911 break;
912 case 5:
020df079
GN		 913 /* fall through */
914 default: /* 7 */
915 *val = vcpu->arch.dr7;
916 break;
917 }
338dbc97
GN		 918 return 0;
919}
020df079
GN		 920EXPORT_SYMBOL_GPL(kvm_get_dr);
921
022cd0e8
AK		 922bool kvm_rdpmc(struct kvm_vcpu *vcpu)
923{
924 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
925 u64 data;
926 int err;
927
c6702c9d 928 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 929 if (err)
930 return err;
931 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
932 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
933 return err;
934}
935EXPORT_SYMBOL_GPL(kvm_rdpmc);
936
043405e1
CO		 937/*
938 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
939 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
940 *
941 * This list is modified at module load time to reflect the
e3267cbb 942 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 943 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
944 * may depend on host virtualization features rather than host cpu features.
043405e1 945 */
e3267cbb 946
043405e1
CO		 947static u32 msrs_to_save[] = {
948 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 949 MSR_STAR,
043405e1
CO		 950#ifdef CONFIG_X86_64
951 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
952#endif
b3897a49 953 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 954 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 955};
956
957static unsigned num_msrs_to_save;
958
62ef68bb
PB		 959static u32 emulated_msrs[] = {
960 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
961 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
962 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
963 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 964 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
965 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 966 HV_X64_MSR_RESET,
11c4b1ca 967 HV_X64_MSR_VP_INDEX,
9eec50b8 968 HV_X64_MSR_VP_RUNTIME,
62ef68bb
PB		 969 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
970 MSR_KVM_PV_EOI_EN,
971
ba904635 972 MSR_IA32_TSC_ADJUST,
a3e06bbe 973 MSR_IA32_TSCDEADLINE,
043405e1 974 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 975 MSR_IA32_MCG_STATUS,
976 MSR_IA32_MCG_CTL,
64d60670 977 MSR_IA32_SMBASE,
043405e1
CO		 978};
979
62ef68bb
PB		 980static unsigned num_emulated_msrs;
981
384bb783 982bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 983{
b69e8cae 984 if (efer & efer_reserved_bits)
384bb783 985 return false;
15c4a640 986
1b2fd70c
AG		 987 if (efer & EFER_FFXSR) {
988 struct kvm_cpuid_entry2 *feat;
989
990 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 991 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 992 return false;
1b2fd70c
AG		 993 }
994
d8017474
AG		 995 if (efer & EFER_SVME) {
996 struct kvm_cpuid_entry2 *feat;
997
998 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 999 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1000 return false;
d8017474
AG		 1001 }
1002
384bb783
JK		 1003 return true;
1004}
1005EXPORT_SYMBOL_GPL(kvm_valid_efer);
1006
1007static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1008{
1009 u64 old_efer = vcpu->arch.efer;
1010
1011 if (!kvm_valid_efer(vcpu, efer))
1012 return 1;
1013
1014 if (is_paging(vcpu)
1015 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1016 return 1;
1017
15c4a640 1018 efer &= ~EFER_LMA;
f6801dff 1019 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1020
a3d204e2
SY		 1021 kvm_x86_ops->set_efer(vcpu, efer);
1022
aad82703
SY		 1023 /* Update reserved bits */
1024 if ((efer ^ old_efer) & EFER_NX)
1025 kvm_mmu_reset_context(vcpu);
1026
b69e8cae 1027 return 0;
15c4a640
CO		 1028}
1029
f2b4b7dd
JR		 1030void kvm_enable_efer_bits(u64 mask)
1031{
1032 efer_reserved_bits &= ~mask;
1033}
1034EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1035
15c4a640
CO		 1036/*
1037 * Writes msr value into into the appropriate "register".
1038 * Returns 0 on success, non-0 otherwise.
1039 * Assumes vcpu_load() was already called.
1040 */
8fe8ab46 1041int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1042{
854e8bb1
NA		 1043 switch (msr->index) {
1044 case MSR_FS_BASE:
1045 case MSR_GS_BASE:
1046 case MSR_KERNEL_GS_BASE:
1047 case MSR_CSTAR:
1048 case MSR_LSTAR:
1049 if (is_noncanonical_address(msr->data))
1050 return 1;
1051 break;
1052 case MSR_IA32_SYSENTER_EIP:
1053 case MSR_IA32_SYSENTER_ESP:
1054 /*
1055 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1056 * non-canonical address is written on Intel but not on
1057 * AMD (which ignores the top 32-bits, because it does
1058 * not implement 64-bit SYSENTER).
1059 *
1060 * 64-bit code should hence be able to write a non-canonical
1061 * value on AMD. Making the address canonical ensures that
1062 * vmentry does not fail on Intel after writing a non-canonical
1063 * value, and that something deterministic happens if the guest
1064 * invokes 64-bit SYSENTER.
1065 */
1066 msr->data = get_canonical(msr->data);
1067 }
8fe8ab46 1068 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1069}
854e8bb1 1070EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1071
313a3dc7
CO		 1072/*
1073 * Adapt set_msr() to msr_io()'s calling convention
1074 */
609e36d3
PB		 1075static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1076{
1077 struct msr_data msr;
1078 int r;
1079
1080 msr.index = index;
1081 msr.host_initiated = true;
1082 r = kvm_get_msr(vcpu, &msr);
1083 if (r)
1084 return r;
1085
1086 *data = msr.data;
1087 return 0;
1088}
1089
313a3dc7
CO		 1090static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1091{
8fe8ab46
WA		 1092 struct msr_data msr;
1093
1094 msr.data = *data;
1095 msr.index = index;
1096 msr.host_initiated = true;
1097 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1098}
1099
16e8d74d
MT		 1100#ifdef CONFIG_X86_64
1101struct pvclock_gtod_data {
1102 seqcount_t seq;
1103
1104 struct { /* extract of a clocksource struct */
1105 int vclock_mode;
1106 cycle_t cycle_last;
1107 cycle_t mask;
1108 u32 mult;
1109 u32 shift;
1110 } clock;
1111
cbcf2dd3
TG		 1112 u64 boot_ns;
1113 u64 nsec_base;
16e8d74d
MT		 1114};
1115
1116static struct pvclock_gtod_data pvclock_gtod_data;
1117
1118static void update_pvclock_gtod(struct timekeeper *tk)
1119{
1120 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1121 u64 boot_ns;
1122
876e7881 1123 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1124
1125 write_seqcount_begin(&vdata->seq);
1126
1127 /* copy pvclock gtod data */
876e7881
PZ		 1128 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1129 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1130 vdata->clock.mask = tk->tkr_mono.mask;
1131 vdata->clock.mult = tk->tkr_mono.mult;
1132 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1133
cbcf2dd3 1134 vdata->boot_ns = boot_ns;
876e7881 1135 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1136
1137 write_seqcount_end(&vdata->seq);
1138}
1139#endif
1140
bab5bb39
NK		 1141void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1142{
1143 /*
1144 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1145 * vcpu_enter_guest. This function is only called from
1146 * the physical CPU that is running vcpu.
1147 */
1148 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1149}
16e8d74d 1150
18068523
GOC		 1151static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1152{
9ed3c444
AK		 1153 int version;
1154 int r;
50d0a0f9 1155 struct pvclock_wall_clock wc;
923de3cf 1156 struct timespec boot;
18068523
GOC		 1157
1158 if (!wall_clock)
1159 return;
1160
9ed3c444
AK		 1161 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1162 if (r)
1163 return;
1164
1165 if (version & 1)
1166 ++version; /* first time write, random junk */
1167
1168 ++version;
18068523 1169
18068523
GOC		 1170 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1171
50d0a0f9
GH		 1172 /*
1173 * The guest calculates current wall clock time by adding
34c238a1 1174 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1175 * wall clock specified here. guest system time equals host
1176 * system time for us, thus we must fill in host boot time here.
1177 */
923de3cf 1178 getboottime(&boot);
50d0a0f9 1179
4b648665
BR		 1180 if (kvm->arch.kvmclock_offset) {
1181 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1182 boot = timespec_sub(boot, ts);
1183 }
50d0a0f9
GH		 1184 wc.sec = boot.tv_sec;
1185 wc.nsec = boot.tv_nsec;
1186 wc.version = version;
18068523
GOC		 1187
1188 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1189
1190 version++;
1191 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1192}
1193
50d0a0f9
GH		 1194static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1195{
1196 uint32_t quotient, remainder;
1197
1198 /* Don't try to replace with do_div(), this one calculates
1199 * "(dividend << 32) / divisor" */
1200 __asm__ ( "divl %4"
1201 : "=a" (quotient), "=d" (remainder)
1202 : "0" (0), "1" (dividend), "r" (divisor) );
1203 return quotient;
1204}
1205
5f4e3f88
ZA		 1206static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1207 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1208{
5f4e3f88 1209 uint64_t scaled64;
50d0a0f9
GH		 1210 int32_t shift = 0;
1211 uint64_t tps64;
1212 uint32_t tps32;
1213
5f4e3f88
ZA		 1214 tps64 = base_khz * 1000LL;
1215 scaled64 = scaled_khz * 1000LL;
50933623 1216 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1217 tps64 >>= 1;
1218 shift--;
1219 }
1220
1221 tps32 = (uint32_t)tps64;
50933623
JK		 1222 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1223 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1224 scaled64 >>= 1;
1225 else
1226 tps32 <<= 1;
50d0a0f9
GH		 1227 shift++;
1228 }
1229
5f4e3f88
ZA		 1230 *pshift = shift;
1231 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1232
5f4e3f88
ZA		 1233 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1234 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1235}
1236
d828199e 1237#ifdef CONFIG_X86_64
16e8d74d 1238static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1239#endif
16e8d74d 1240
c8076604 1241static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1242static unsigned long max_tsc_khz;
c8076604 1243
cc578287 1244static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1245{
cc578287
ZA		 1246 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1247 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1248}
1249
cc578287 1250static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1251{
cc578287
ZA		 1252 u64 v = (u64)khz * (1000000 + ppm);
1253 do_div(v, 1000000);
1254 return v;
1e993611
JR		 1255}
1256
381d585c
HZ		 1257static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1258{
1259 u64 ratio;
1260
1261 /* Guest TSC same frequency as host TSC? */
1262 if (!scale) {
1263 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1264 return 0;
1265 }
1266
1267 /* TSC scaling supported? */
1268 if (!kvm_has_tsc_control) {
1269 if (user_tsc_khz > tsc_khz) {
1270 vcpu->arch.tsc_catchup = 1;
1271 vcpu->arch.tsc_always_catchup = 1;
1272 return 0;
1273 } else {
1274 WARN(1, "user requested TSC rate below hardware speed\n");
1275 return -1;
1276 }
1277 }
1278
1279 /* TSC scaling required - calculate ratio */
1280 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1281 user_tsc_khz, tsc_khz);
1282
1283 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1284 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1285 user_tsc_khz);
1286 return -1;
1287 }
1288
1289 vcpu->arch.tsc_scaling_ratio = ratio;
1290 return 0;
1291}
1292
1293static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1294{
cc578287
ZA		 1295 u32 thresh_lo, thresh_hi;
1296 int use_scaling = 0;
217fc9cf 1297
03ba32ca 1298 /* tsc_khz can be zero if TSC calibration fails */
ad721883
HZ		 1299 if (this_tsc_khz == 0) {
1300 /* set tsc_scaling_ratio to a safe value */
1301 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1302 return -1;
ad721883 1303 }
03ba32ca 1304
c285545f
ZA		 1305 /* Compute a scale to convert nanoseconds in TSC cycles */
1306 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1307 &vcpu->arch.virtual_tsc_shift,
1308 &vcpu->arch.virtual_tsc_mult);
1309 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1310
1311 /*
1312 * Compute the variation in TSC rate which is acceptable
1313 * within the range of tolerance and decide if the
1314 * rate being applied is within that bounds of the hardware
1315 * rate. If so, no scaling or compensation need be done.
1316 */
1317 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1318 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1319 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1320 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1321 use_scaling = 1;
1322 }
381d585c 1323 return set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1324}
1325
1326static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1327{
e26101b1 1328 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1329 vcpu->arch.virtual_tsc_mult,
1330 vcpu->arch.virtual_tsc_shift);
e26101b1 1331 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1332 return tsc;
1333}
1334
69b0049a 1335static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1336{
1337#ifdef CONFIG_X86_64
1338 bool vcpus_matched;
b48aa97e
MT		 1339 struct kvm_arch *ka = &vcpu->kvm->arch;
1340 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1341
1342 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1343 atomic_read(&vcpu->kvm->online_vcpus));
1344
7f187922
MT		 1345 /*
1346 * Once the masterclock is enabled, always perform request in
1347 * order to update it.
1348 *
1349 * In order to enable masterclock, the host clocksource must be TSC
1350 * and the vcpus need to have matched TSCs. When that happens,
1351 * perform request to enable masterclock.
1352 */
1353 if (ka->use_master_clock ||
1354 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1355 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1356
1357 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1358 atomic_read(&vcpu->kvm->online_vcpus),
1359 ka->use_master_clock, gtod->clock.vclock_mode);
1360#endif
1361}
1362
ba904635
WA		 1363static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1364{
1365 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1366 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1367}
1368
35181e86
HZ		 1369/*
1370 * Multiply tsc by a fixed point number represented by ratio.
1371 *
1372 * The most significant 64-N bits (mult) of ratio represent the
1373 * integral part of the fixed point number; the remaining N bits
1374 * (frac) represent the fractional part, ie. ratio represents a fixed
1375 * point number (mult + frac * 2^(-N)).
1376 *
1377 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1378 */
1379static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1380{
1381 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1382}
1383
1384u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1385{
1386 u64 _tsc = tsc;
1387 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1388
1389 if (ratio != kvm_default_tsc_scaling_ratio)
1390 _tsc = __scale_tsc(ratio, tsc);
1391
1392 return _tsc;
1393}
1394EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1395
07c1419a
HZ		 1396static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1397{
1398 u64 tsc;
1399
1400 tsc = kvm_scale_tsc(vcpu, rdtsc());
1401
1402 return target_tsc - tsc;
1403}
1404
4ba76538
HZ		 1405u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1406{
1407 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1408}
1409EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1410
8fe8ab46 1411void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1412{
1413 struct kvm *kvm = vcpu->kvm;
f38e098f 1414 u64 offset, ns, elapsed;
99e3e30a 1415 unsigned long flags;
02626b6a 1416 s64 usdiff;
b48aa97e 1417 bool matched;
0d3da0d2 1418 bool already_matched;
8fe8ab46 1419 u64 data = msr->data;
99e3e30a 1420
038f8c11 1421 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1422 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1423 ns = get_kernel_ns();
f38e098f 1424 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1425
03ba32ca 1426 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1427 int faulted = 0;
1428
03ba32ca
MT		 1429 /* n.b - signed multiplication and division required */
1430 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1431#ifdef CONFIG_X86_64
03ba32ca 1432 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1433#else
03ba32ca 1434 /* do_div() only does unsigned */
8915aa27
MT		 1435 asm("1: idivl %[divisor]\n"
1436 "2: xor %%edx, %%edx\n"
1437 " movl $0, %[faulted]\n"
1438 "3:\n"
1439 ".section .fixup,\"ax\"\n"
1440 "4: movl $1, %[faulted]\n"
1441 " jmp 3b\n"
1442 ".previous\n"
1443
1444 _ASM_EXTABLE(1b, 4b)
1445
1446 : "=A"(usdiff), [faulted] "=r" (faulted)
1447 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1448
5d3cb0f6 1449#endif
03ba32ca
MT		 1450 do_div(elapsed, 1000);
1451 usdiff -= elapsed;
1452 if (usdiff < 0)
1453 usdiff = -usdiff;
8915aa27
MT		 1454
1455 /* idivl overflow => difference is larger than USEC_PER_SEC */
1456 if (faulted)
1457 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1458 } else
1459 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1460
1461 /*
5d3cb0f6
ZA		 1462 * Special case: TSC write with a small delta (1 second) of virtual
1463 * cycle time against real time is interpreted as an attempt to
1464 * synchronize the CPU.
1465 *
1466 * For a reliable TSC, we can match TSC offsets, and for an unstable
1467 * TSC, we add elapsed time in this computation. We could let the
1468 * compensation code attempt to catch up if we fall behind, but
1469 * it's better to try to match offsets from the beginning.
1470 */
02626b6a 1471 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1472 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1473 if (!check_tsc_unstable()) {
e26101b1 1474 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1475 pr_debug("kvm: matched tsc offset for %llu\n", data);
1476 } else {
857e4099 1477 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1478 data += delta;
07c1419a 1479 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1480 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1481 }
b48aa97e 1482 matched = true;
0d3da0d2 1483 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1484 } else {
1485 /*
1486 * We split periods of matched TSC writes into generations.
1487 * For each generation, we track the original measured
1488 * nanosecond time, offset, and write, so if TSCs are in
1489 * sync, we can match exact offset, and if not, we can match
4a969980 1490 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1491 *
1492 * These values are tracked in kvm->arch.cur_xxx variables.
1493 */
1494 kvm->arch.cur_tsc_generation++;
1495 kvm->arch.cur_tsc_nsec = ns;
1496 kvm->arch.cur_tsc_write = data;
1497 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1498 matched = false;
0d3da0d2 1499 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1500 kvm->arch.cur_tsc_generation, data);
f38e098f 1501 }
e26101b1
ZA		 1502
1503 /*
1504 * We also track th most recent recorded KHZ, write and time to
1505 * allow the matching interval to be extended at each write.
1506 */
f38e098f
ZA		 1507 kvm->arch.last_tsc_nsec = ns;
1508 kvm->arch.last_tsc_write = data;
5d3cb0f6 1509 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1510
b183aa58 1511 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1512
1513 /* Keep track of which generation this VCPU has synchronized to */
1514 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1515 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1516 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1517
ba904635
WA		 1518 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1519 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1520 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1521 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1522
1523 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1524 if (!matched) {
b48aa97e 1525 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1526 } else if (!already_matched) {
1527 kvm->arch.nr_vcpus_matched_tsc++;
1528 }
b48aa97e
MT		 1529
1530 kvm_track_tsc_matching(vcpu);
1531 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1532}
e26101b1 1533
99e3e30a
ZA		 1534EXPORT_SYMBOL_GPL(kvm_write_tsc);
1535
58ea6767
HZ		 1536static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1537 s64 adjustment)
1538{
1539 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1540}
1541
1542static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1543{
1544 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1545 WARN_ON(adjustment < 0);
1546 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1547 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1548}
1549
d828199e
MT		 1550#ifdef CONFIG_X86_64
1551
1552static cycle_t read_tsc(void)
1553{
03b9730b
AL		 1554 cycle_t ret = (cycle_t)rdtsc_ordered();
1555 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1556
1557 if (likely(ret >= last))
1558 return ret;
1559
1560 /*
1561 * GCC likes to generate cmov here, but this branch is extremely
1562 * predictable (it's just a funciton of time and the likely is
1563 * very likely) and there's a data dependence, so force GCC
1564 * to generate a branch instead. I don't barrier() because
1565 * we don't actually need a barrier, and if this function
1566 * ever gets inlined it will generate worse code.
1567 */
1568 asm volatile ("");
1569 return last;
1570}
1571
1572static inline u64 vgettsc(cycle_t *cycle_now)
1573{
1574 long v;
1575 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1576
1577 *cycle_now = read_tsc();
1578
1579 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1580 return v * gtod->clock.mult;
1581}
1582
cbcf2dd3 1583static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1584{
cbcf2dd3 1585 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1586 unsigned long seq;
d828199e 1587 int mode;
cbcf2dd3 1588 u64 ns;
d828199e 1589
d828199e
MT		 1590 do {
1591 seq = read_seqcount_begin(&gtod->seq);
1592 mode = gtod->clock.vclock_mode;
cbcf2dd3 1593 ns = gtod->nsec_base;
d828199e
MT		 1594 ns += vgettsc(cycle_now);
1595 ns >>= gtod->clock.shift;
cbcf2dd3 1596 ns += gtod->boot_ns;
d828199e 1597 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1598 *t = ns;
d828199e
MT		 1599
1600 return mode;
1601}
1602
1603/* returns true if host is using tsc clocksource */
1604static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1605{
d828199e
MT		 1606 /* checked again under seqlock below */
1607 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1608 return false;
1609
cbcf2dd3 1610 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1611}
1612#endif
1613
1614/*
1615 *
b48aa97e
MT		 1616 * Assuming a stable TSC across physical CPUS, and a stable TSC
1617 * across virtual CPUs, the following condition is possible.
1618 * Each numbered line represents an event visible to both
d828199e
MT		 1619 * CPUs at the next numbered event.
1620 *
1621 * "timespecX" represents host monotonic time. "tscX" represents
1622 * RDTSC value.
1623 *
1624 * VCPU0 on CPU0 | VCPU1 on CPU1
1625 *
1626 * 1. read timespec0,tsc0
1627 * 2. | timespec1 = timespec0 + N
1628 * | tsc1 = tsc0 + M
1629 * 3. transition to guest | transition to guest
1630 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1631 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1632 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1633 *
1634 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1635 *
1636 * - ret0 < ret1
1637 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1638 * ...
1639 * - 0 < N - M => M < N
1640 *
1641 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1642 * always the case (the difference between two distinct xtime instances
1643 * might be smaller then the difference between corresponding TSC reads,
1644 * when updating guest vcpus pvclock areas).
1645 *
1646 * To avoid that problem, do not allow visibility of distinct
1647 * system_timestamp/tsc_timestamp values simultaneously: use a master
1648 * copy of host monotonic time values. Update that master copy
1649 * in lockstep.
1650 *
b48aa97e 1651 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1652 *
1653 */
1654
1655static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1656{
1657#ifdef CONFIG_X86_64
1658 struct kvm_arch *ka = &kvm->arch;
1659 int vclock_mode;
b48aa97e
MT		 1660 bool host_tsc_clocksource, vcpus_matched;
1661
1662 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1663 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1664
1665 /*
1666 * If the host uses TSC clock, then passthrough TSC as stable
1667 * to the guest.
1668 */
b48aa97e 1669 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1670 &ka->master_kernel_ns,
1671 &ka->master_cycle_now);
1672
16a96021 1673 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1674 && !backwards_tsc_observed
1675 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1676
d828199e
MT		 1677 if (ka->use_master_clock)
1678 atomic_set(&kvm_guest_has_master_clock, 1);
1679
1680 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1681 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1682 vcpus_matched);
d828199e
MT		 1683#endif
1684}
1685
2e762ff7
MT		 1686static void kvm_gen_update_masterclock(struct kvm *kvm)
1687{
1688#ifdef CONFIG_X86_64
1689 int i;
1690 struct kvm_vcpu *vcpu;
1691 struct kvm_arch *ka = &kvm->arch;
1692
1693 spin_lock(&ka->pvclock_gtod_sync_lock);
1694 kvm_make_mclock_inprogress_request(kvm);
1695 /* no guest entries from this point */
1696 pvclock_update_vm_gtod_copy(kvm);
1697
1698 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1699 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1700
1701 /* guest entries allowed */
1702 kvm_for_each_vcpu(i, vcpu, kvm)
1703 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1704
1705 spin_unlock(&ka->pvclock_gtod_sync_lock);
1706#endif
1707}
1708
34c238a1 1709static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1710{
27cca94e 1711 unsigned long flags, this_tsc_khz, tgt_tsc_khz;
18068523 1712 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1713 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1714 s64 kernel_ns;
d828199e 1715 u64 tsc_timestamp, host_tsc;
0b79459b 1716 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1717 u8 pvclock_flags;
d828199e
MT		 1718 bool use_master_clock;
1719
1720 kernel_ns = 0;
1721 host_tsc = 0;
18068523 1722
d828199e
MT		 1723 /*
1724 * If the host uses TSC clock, then passthrough TSC as stable
1725 * to the guest.
1726 */
1727 spin_lock(&ka->pvclock_gtod_sync_lock);
1728 use_master_clock = ka->use_master_clock;
1729 if (use_master_clock) {
1730 host_tsc = ka->master_cycle_now;
1731 kernel_ns = ka->master_kernel_ns;
1732 }
1733 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1734
1735 /* Keep irq disabled to prevent changes to the clock */
1736 local_irq_save(flags);
89cbc767 1737 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1738 if (unlikely(this_tsc_khz == 0)) {
1739 local_irq_restore(flags);
1740 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1741 return 1;
1742 }
d828199e 1743 if (!use_master_clock) {
4ea1636b 1744 host_tsc = rdtsc();
d828199e
MT		 1745 kernel_ns = get_kernel_ns();
1746 }
1747
4ba76538 1748 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1749
c285545f
ZA		 1750 /*
1751 * We may have to catch up the TSC to match elapsed wall clock
1752 * time for two reasons, even if kvmclock is used.
1753 * 1) CPU could have been running below the maximum TSC rate
1754 * 2) Broken TSC compensation resets the base at each VCPU
1755 * entry to avoid unknown leaps of TSC even when running
1756 * again on the same CPU. This may cause apparent elapsed
1757 * time to disappear, and the guest to stand still or run
1758 * very slowly.
1759 */
1760 if (vcpu->tsc_catchup) {
1761 u64 tsc = compute_guest_tsc(v, kernel_ns);
1762 if (tsc > tsc_timestamp) {
f1e2b260 1763 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1764 tsc_timestamp = tsc;
1765 }
50d0a0f9
GH		 1766 }
1767
18068523
GOC		 1768 local_irq_restore(flags);
1769
0b79459b 1770 if (!vcpu->pv_time_enabled)
c285545f 1771 return 0;
18068523 1772
e48672fa 1773 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
27cca94e
HZ		 1774 tgt_tsc_khz = kvm_has_tsc_control ?
1775 vcpu->virtual_tsc_khz : this_tsc_khz;
1776 kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz,
5f4e3f88
ZA		 1777 &vcpu->hv_clock.tsc_shift,
1778 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1779 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1780 }
1781
1782 /* With all the info we got, fill in the values */
1d5f066e 1783 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1784 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1785 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1786
09a0c3f1
OH		 1787 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1788 &guest_hv_clock, sizeof(guest_hv_clock))))
1789 return 0;
1790
5dca0d91
RK		 1791 /* This VCPU is paused, but it's legal for a guest to read another
1792 * VCPU's kvmclock, so we really have to follow the specification where
1793 * it says that version is odd if data is being modified, and even after
1794 * it is consistent.
1795 *
1796 * Version field updates must be kept separate. This is because
1797 * kvm_write_guest_cached might use a "rep movs" instruction, and
1798 * writes within a string instruction are weakly ordered. So there
1799 * are three writes overall.
1800 *
1801 * As a small optimization, only write the version field in the first
1802 * and third write. The vcpu->pv_time cache is still valid, because the
1803 * version field is the first in the struct.
18068523 1804 */
5dca0d91
RK		 1805 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1806
1807 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1808 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1809 &vcpu->hv_clock,
1810 sizeof(vcpu->hv_clock.version));
1811
1812 smp_wmb();
78c0337a
MT		 1813
1814 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1815 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1816
1817 if (vcpu->pvclock_set_guest_stopped_request) {
1818 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1819 vcpu->pvclock_set_guest_stopped_request = false;
1820 }
1821
d828199e
MT		 1822 /* If the host uses TSC clocksource, then it is stable */
1823 if (use_master_clock)
1824 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1825
78c0337a
MT		 1826 vcpu->hv_clock.flags = pvclock_flags;
1827
ce1a5e60
DM		 1828 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1829
0b79459b
AH		 1830 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1831 &vcpu->hv_clock,
1832 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1833
1834 smp_wmb();
1835
1836 vcpu->hv_clock.version++;
1837 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1838 &vcpu->hv_clock,
1839 sizeof(vcpu->hv_clock.version));
8cfdc000 1840 return 0;
c8076604
GH		 1841}
1842
0061d53d
MT		 1843/*
1844 * kvmclock updates which are isolated to a given vcpu, such as
1845 * vcpu->cpu migration, should not allow system_timestamp from
1846 * the rest of the vcpus to remain static. Otherwise ntp frequency
1847 * correction applies to one vcpu's system_timestamp but not
1848 * the others.
1849 *
1850 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1851 * We need to rate-limit these requests though, as they can
1852 * considerably slow guests that have a large number of vcpus.
1853 * The time for a remote vcpu to update its kvmclock is bound
1854 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1855 */
1856
7e44e449
AJ		 1857#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1858
1859static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1860{
1861 int i;
7e44e449
AJ		 1862 struct delayed_work *dwork = to_delayed_work(work);
1863 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1864 kvmclock_update_work);
1865 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1866 struct kvm_vcpu *vcpu;
1867
1868 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1869 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1870 kvm_vcpu_kick(vcpu);
1871 }
1872}
1873
7e44e449
AJ		 1874static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1875{
1876 struct kvm *kvm = v->kvm;
1877
105b21bb 1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1879 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1880 KVMCLOCK_UPDATE_DELAY);
1881}
1882
332967a3
AJ		 1883#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1884
1885static void kvmclock_sync_fn(struct work_struct *work)
1886{
1887 struct delayed_work *dwork = to_delayed_work(work);
1888 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1889 kvmclock_sync_work);
1890 struct kvm *kvm = container_of(ka, struct kvm, arch);
1891
630994b3
MT		 1892 if (!kvmclock_periodic_sync)
1893 return;
1894
332967a3
AJ		 1895 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1896 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1897 KVMCLOCK_SYNC_PERIOD);
1898}
1899
890ca9ae 1900static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1901{
890ca9ae
HY		 1902 u64 mcg_cap = vcpu->arch.mcg_cap;
1903 unsigned bank_num = mcg_cap & 0xff;
1904
15c4a640 1905 switch (msr) {
15c4a640 1906 case MSR_IA32_MCG_STATUS:
890ca9ae 1907 vcpu->arch.mcg_status = data;
15c4a640 1908 break;
c7ac679c 1909 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1910 if (!(mcg_cap & MCG_CTL_P))
1911 return 1;
1912 if (data != 0 && data != ~(u64)0)
1913 return -1;
1914 vcpu->arch.mcg_ctl = data;
1915 break;
1916 default:
1917 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1918 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1919 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1920 /* only 0 or all 1s can be written to IA32_MCi_CTL
1921 * some Linux kernels though clear bit 10 in bank 4 to
1922 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1923 * this to avoid an uncatched #GP in the guest
1924 */
890ca9ae 1925 if ((offset & 0x3) == 0 &&
114be429 1926 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1927 return -1;
1928 vcpu->arch.mce_banks[offset] = data;
1929 break;
1930 }
1931 return 1;
1932 }
1933 return 0;
1934}
1935
ffde22ac
ES		 1936static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1937{
1938 struct kvm *kvm = vcpu->kvm;
1939 int lm = is_long_mode(vcpu);
1940 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1941 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1942 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1943 : kvm->arch.xen_hvm_config.blob_size_32;
1944 u32 page_num = data & ~PAGE_MASK;
1945 u64 page_addr = data & PAGE_MASK;
1946 u8 *page;
1947 int r;
1948
1949 r = -E2BIG;
1950 if (page_num >= blob_size)
1951 goto out;
1952 r = -ENOMEM;
ff5c2c03
SL		 1953 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1954 if (IS_ERR(page)) {
1955 r = PTR_ERR(page);
ffde22ac 1956 goto out;
ff5c2c03 1957 }
54bf36aa 1958 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1959 goto out_free;
1960 r = 0;
1961out_free:
1962 kfree(page);
1963out:
1964 return r;
1965}
1966
344d9588
GN		 1967static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1968{
1969 gpa_t gpa = data & ~0x3f;
1970
4a969980 1971 /* Bits 2:5 are reserved, Should be zero */
6adba527 1972 if (data & 0x3c)
344d9588
GN		 1973 return 1;
1974
1975 vcpu->arch.apf.msr_val = data;
1976
1977 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1978 kvm_clear_async_pf_completion_queue(vcpu);
1979 kvm_async_pf_hash_reset(vcpu);
1980 return 0;
1981 }
1982
8f964525
AH		 1983 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1984 sizeof(u32)))
344d9588
GN		 1985 return 1;
1986
6adba527 1987 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1988 kvm_async_pf_wakeup_all(vcpu);
1989 return 0;
1990}
1991
12f9a48f
GC		 1992static void kvmclock_reset(struct kvm_vcpu *vcpu)
1993{
0b79459b 1994 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1995}
1996
c9aaa895
GC		 1997static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1998{
1999 u64 delta;
2000
2001 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2002 return;
2003
2004 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2005 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2006 vcpu->arch.st.accum_steal = delta;
2007}
2008
2009static void record_steal_time(struct kvm_vcpu *vcpu)
2010{
7cae2bed
MT		 2011 accumulate_steal_time(vcpu);
2012
c9aaa895
GC		 2013 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2014 return;
2015
2016 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2017 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2018 return;
2019
2020 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2021 vcpu->arch.st.steal.version += 2;
2022 vcpu->arch.st.accum_steal = 0;
2023
2024 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2025 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2026}
2027
8fe8ab46 2028int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2029{
5753785f 2030 bool pr = false;
8fe8ab46
WA		 2031 u32 msr = msr_info->index;
2032 u64 data = msr_info->data;
5753785f 2033
15c4a640 2034 switch (msr) {
2e32b719
BP		 2035 case MSR_AMD64_NB_CFG:
2036 case MSR_IA32_UCODE_REV:
2037 case MSR_IA32_UCODE_WRITE:
2038 case MSR_VM_HSAVE_PA:
2039 case MSR_AMD64_PATCH_LOADER:
2040 case MSR_AMD64_BU_CFG2:
2041 break;
2042
15c4a640 2043 case MSR_EFER:
b69e8cae 2044 return set_efer(vcpu, data);
8f1589d9
AP		 2045 case MSR_K7_HWCR:
2046 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2047 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2048 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2049 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2050 if (data != 0) {
a737f256
CD		 2051 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2052 data);
8f1589d9
AP		 2053 return 1;
2054 }
15c4a640 2055 break;
f7c6d140
AP		 2056 case MSR_FAM10H_MMIO_CONF_BASE:
2057 if (data != 0) {
a737f256
CD		 2058 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2059 "0x%llx\n", data);
f7c6d140
AP		 2060 return 1;
2061 }
15c4a640 2062 break;
b5e2fec0
AG		 2063 case MSR_IA32_DEBUGCTLMSR:
2064 if (!data) {
2065 /* We support the non-activated case already */
2066 break;
2067 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2068 /* Values other than LBR and BTF are vendor-specific,
2069 thus reserved and should throw a #GP */
2070 return 1;
2071 }
a737f256
CD		 2072 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2073 __func__, data);
b5e2fec0 2074 break;
9ba075a6 2075 case 0x200 ... 0x2ff:
ff53604b 2076 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2077 case MSR_IA32_APICBASE:
58cb628d 2078 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2079 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2080 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2081 case MSR_IA32_TSCDEADLINE:
2082 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2083 break;
ba904635
WA		 2084 case MSR_IA32_TSC_ADJUST:
2085 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2086 if (!msr_info->host_initiated) {
d913b904 2087 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2088 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2089 }
2090 vcpu->arch.ia32_tsc_adjust_msr = data;
2091 }
2092 break;
15c4a640 2093 case MSR_IA32_MISC_ENABLE:
ad312c7c 2094 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2095 break;
64d60670
PB		 2096 case MSR_IA32_SMBASE:
2097 if (!msr_info->host_initiated)
2098 return 1;
2099 vcpu->arch.smbase = data;
2100 break;
11c6bffa 2101 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2102 case MSR_KVM_WALL_CLOCK:
2103 vcpu->kvm->arch.wall_clock = data;
2104 kvm_write_wall_clock(vcpu->kvm, data);
2105 break;
11c6bffa 2106 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2107 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2108 u64 gpa_offset;
54750f2c
MT		 2109 struct kvm_arch *ka = &vcpu->kvm->arch;
2110
12f9a48f 2111 kvmclock_reset(vcpu);
18068523 2112
54750f2c
MT		 2113 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2114 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2115
2116 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2117 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2118 &vcpu->requests);
2119
2120 ka->boot_vcpu_runs_old_kvmclock = tmp;
2121 }
2122
18068523 2123 vcpu->arch.time = data;
0061d53d 2124 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2125
2126 /* we verify if the enable bit is set... */
2127 if (!(data & 1))
2128 break;
2129
0b79459b 2130 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2131
0b79459b 2132 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2133 &vcpu->arch.pv_time, data & ~1ULL,
2134 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2135 vcpu->arch.pv_time_enabled = false;
2136 else
2137 vcpu->arch.pv_time_enabled = true;
32cad84f 2138
18068523
GOC		 2139 break;
2140 }
344d9588
GN		 2141 case MSR_KVM_ASYNC_PF_EN:
2142 if (kvm_pv_enable_async_pf(vcpu, data))
2143 return 1;
2144 break;
c9aaa895
GC		 2145 case MSR_KVM_STEAL_TIME:
2146
2147 if (unlikely(!sched_info_on()))
2148 return 1;
2149
2150 if (data & KVM_STEAL_RESERVED_MASK)
2151 return 1;
2152
2153 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2154 data & KVM_STEAL_VALID_BITS,
2155 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2156 return 1;
2157
2158 vcpu->arch.st.msr_val = data;
2159
2160 if (!(data & KVM_MSR_ENABLED))
2161 break;
2162
c9aaa895
GC		 2163 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2164
2165 break;
ae7a2a3f
MT		 2166 case MSR_KVM_PV_EOI_EN:
2167 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2168 return 1;
2169 break;
c9aaa895 2170
890ca9ae
HY		 2171 case MSR_IA32_MCG_CTL:
2172 case MSR_IA32_MCG_STATUS:
81760dcc 2173 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2174 return set_msr_mce(vcpu, msr, data);
71db6023 2175
6912ac32
WH		 2176 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2177 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2178 pr = true; /* fall through */
2179 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2180 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2181 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2182 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2183
2184 if (pr || data != 0)
a737f256
CD		 2185 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2186 "0x%x data 0x%llx\n", msr, data);
5753785f 2187 break;
84e0cefa
JS		 2188 case MSR_K7_CLK_CTL:
2189 /*
2190 * Ignore all writes to this no longer documented MSR.
2191 * Writes are only relevant for old K7 processors,
2192 * all pre-dating SVM, but a recommended workaround from
4a969980 2193 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2194 * affected processor models on the command line, hence
2195 * the need to ignore the workaround.
2196 */
2197 break;
55cd8e5a 2198 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2199 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2200 case HV_X64_MSR_CRASH_CTL:
2201 return kvm_hv_set_msr_common(vcpu, msr, data,
2202 msr_info->host_initiated);
91c9c3ed 2203 case MSR_IA32_BBL_CR_CTL3:
2204 /* Drop writes to this legacy MSR -- see rdmsr
2205 * counterpart for further detail.
2206 */
a737f256 2207 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2208 break;
2b036c6b
BO		 2209 case MSR_AMD64_OSVW_ID_LENGTH:
2210 if (!guest_cpuid_has_osvw(vcpu))
2211 return 1;
2212 vcpu->arch.osvw.length = data;
2213 break;
2214 case MSR_AMD64_OSVW_STATUS:
2215 if (!guest_cpuid_has_osvw(vcpu))
2216 return 1;
2217 vcpu->arch.osvw.status = data;
2218 break;
15c4a640 2219 default:
ffde22ac
ES		 2220 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2221 return xen_hvm_config(vcpu, data);
c6702c9d 2222 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2223 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2224 if (!ignore_msrs) {
a737f256
CD		 2225 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2226 msr, data);
ed85c068
AP		 2227 return 1;
2228 } else {
a737f256
CD		 2229 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2230 msr, data);
ed85c068
AP		 2231 break;
2232 }
15c4a640
CO		 2233 }
2234 return 0;
2235}
2236EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2237
2238
2239/*
2240 * Reads an msr value (of 'msr_index') into 'pdata'.
2241 * Returns 0 on success, non-0 otherwise.
2242 * Assumes vcpu_load() was already called.
2243 */
609e36d3 2244int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2245{
609e36d3 2246 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2247}
ff651cb6 2248EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2249
890ca9ae 2250static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2251{
2252 u64 data;
890ca9ae
HY		 2253 u64 mcg_cap = vcpu->arch.mcg_cap;
2254 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2255
2256 switch (msr) {
15c4a640
CO		 2257 case MSR_IA32_P5_MC_ADDR:
2258 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2259 data = 0;
2260 break;
15c4a640 2261 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2262 data = vcpu->arch.mcg_cap;
2263 break;
c7ac679c 2264 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2265 if (!(mcg_cap & MCG_CTL_P))
2266 return 1;
2267 data = vcpu->arch.mcg_ctl;
2268 break;
2269 case MSR_IA32_MCG_STATUS:
2270 data = vcpu->arch.mcg_status;
2271 break;
2272 default:
2273 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2274 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2275 u32 offset = msr - MSR_IA32_MC0_CTL;
2276 data = vcpu->arch.mce_banks[offset];
2277 break;
2278 }
2279 return 1;
2280 }
2281 *pdata = data;
2282 return 0;
2283}
2284
609e36d3 2285int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2286{
609e36d3 2287 switch (msr_info->index) {
890ca9ae 2288 case MSR_IA32_PLATFORM_ID:
15c4a640 2289 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2290 case MSR_IA32_DEBUGCTLMSR:
2291 case MSR_IA32_LASTBRANCHFROMIP:
2292 case MSR_IA32_LASTBRANCHTOIP:
2293 case MSR_IA32_LASTINTFROMIP:
2294 case MSR_IA32_LASTINTTOIP:
60af2ecd 2295 case MSR_K8_SYSCFG:
3afb1121
PB		 2296 case MSR_K8_TSEG_ADDR:
2297 case MSR_K8_TSEG_MASK:
60af2ecd 2298 case MSR_K7_HWCR:
61a6bd67 2299 case MSR_VM_HSAVE_PA:
1fdbd48c 2300 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2301 case MSR_AMD64_NB_CFG:
f7c6d140 2302 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2303 case MSR_AMD64_BU_CFG2:
609e36d3 2304 msr_info->data = 0;
15c4a640 2305 break;
6912ac32
WH		 2306 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2307 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2308 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2309 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2310 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2311 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2312 msr_info->data = 0;
5753785f 2313 break;
742bc670 2314 case MSR_IA32_UCODE_REV:
609e36d3 2315 msr_info->data = 0x100000000ULL;
742bc670 2316 break;
9ba075a6 2317 case MSR_MTRRcap:
9ba075a6 2318 case 0x200 ... 0x2ff:
ff53604b 2319 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2320 case 0xcd: /* fsb frequency */
609e36d3 2321 msr_info->data = 3;
15c4a640 2322 break;
7b914098
JS		 2323 /*
2324 * MSR_EBC_FREQUENCY_ID
2325 * Conservative value valid for even the basic CPU models.
2326 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2327 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2328 * and 266MHz for model 3, or 4. Set Core Clock
2329 * Frequency to System Bus Frequency Ratio to 1 (bits
2330 * 31:24) even though these are only valid for CPU
2331 * models > 2, however guests may end up dividing or
2332 * multiplying by zero otherwise.
2333 */
2334 case MSR_EBC_FREQUENCY_ID:
609e36d3 2335 msr_info->data = 1 << 24;
7b914098 2336 break;
15c4a640 2337 case MSR_IA32_APICBASE:
609e36d3 2338 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2339 break;
0105d1a5 2340 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2341 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2342 break;
a3e06bbe 2343 case MSR_IA32_TSCDEADLINE:
609e36d3 2344 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2345 break;
ba904635 2346 case MSR_IA32_TSC_ADJUST:
609e36d3 2347 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2348 break;
15c4a640 2349 case MSR_IA32_MISC_ENABLE:
609e36d3 2350 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2351 break;
64d60670
PB		 2352 case MSR_IA32_SMBASE:
2353 if (!msr_info->host_initiated)
2354 return 1;
2355 msr_info->data = vcpu->arch.smbase;
15c4a640 2356 break;
847f0ad8
AG		 2357 case MSR_IA32_PERF_STATUS:
2358 /* TSC increment by tick */
609e36d3 2359 msr_info->data = 1000ULL;
847f0ad8 2360 /* CPU multiplier */
b0996ae4 2361 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2362 break;
15c4a640 2363 case MSR_EFER:
609e36d3 2364 msr_info->data = vcpu->arch.efer;
15c4a640 2365 break;
18068523 2366 case MSR_KVM_WALL_CLOCK:
11c6bffa 2367 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2368 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2369 break;
2370 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2371 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2372 msr_info->data = vcpu->arch.time;
18068523 2373 break;
344d9588 2374 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2375 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2376 break;
c9aaa895 2377 case MSR_KVM_STEAL_TIME:
609e36d3 2378 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2379 break;
1d92128f 2380 case MSR_KVM_PV_EOI_EN:
609e36d3 2381 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2382 break;
890ca9ae
HY		 2383 case MSR_IA32_P5_MC_ADDR:
2384 case MSR_IA32_P5_MC_TYPE:
2385 case MSR_IA32_MCG_CAP:
2386 case MSR_IA32_MCG_CTL:
2387 case MSR_IA32_MCG_STATUS:
81760dcc 2388 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2389 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2390 case MSR_K7_CLK_CTL:
2391 /*
2392 * Provide expected ramp-up count for K7. All other
2393 * are set to zero, indicating minimum divisors for
2394 * every field.
2395 *
2396 * This prevents guest kernels on AMD host with CPU
2397 * type 6, model 8 and higher from exploding due to
2398 * the rdmsr failing.
2399 */
609e36d3 2400 msr_info->data = 0x20000000;
84e0cefa 2401 break;
55cd8e5a 2402 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2403 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2404 case HV_X64_MSR_CRASH_CTL:
e83d5887
AS		 2405 return kvm_hv_get_msr_common(vcpu,
2406 msr_info->index, &msr_info->data);
55cd8e5a 2407 break;
91c9c3ed 2408 case MSR_IA32_BBL_CR_CTL3:
2409 /* This legacy MSR exists but isn't fully documented in current
2410 * silicon. It is however accessed by winxp in very narrow
2411 * scenarios where it sets bit #19, itself documented as
2412 * a "reserved" bit. Best effort attempt to source coherent
2413 * read data here should the balance of the register be
2414 * interpreted by the guest:
2415 *
2416 * L2 cache control register 3: 64GB range, 256KB size,
2417 * enabled, latency 0x1, configured
2418 */
609e36d3 2419 msr_info->data = 0xbe702111;
91c9c3ed 2420 break;
2b036c6b
BO		 2421 case MSR_AMD64_OSVW_ID_LENGTH:
2422 if (!guest_cpuid_has_osvw(vcpu))
2423 return 1;
609e36d3 2424 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2425 break;
2426 case MSR_AMD64_OSVW_STATUS:
2427 if (!guest_cpuid_has_osvw(vcpu))
2428 return 1;
609e36d3 2429 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2430 break;
15c4a640 2431 default:
c6702c9d 2432 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2433 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2434 if (!ignore_msrs) {
609e36d3 2435 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2436 return 1;
2437 } else {
609e36d3
PB		 2438 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2439 msr_info->data = 0;
ed85c068
AP		 2440 }
2441 break;
15c4a640 2442 }
15c4a640
CO		 2443 return 0;
2444}
2445EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2446
313a3dc7
CO		 2447/*
2448 * Read or write a bunch of msrs. All parameters are kernel addresses.
2449 *
2450 * @return number of msrs set successfully.
2451 */
2452static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2453 struct kvm_msr_entry *entries,
2454 int (*do_msr)(struct kvm_vcpu *vcpu,
2455 unsigned index, u64 *data))
2456{
f656ce01 2457 int i, idx;
313a3dc7 2458
f656ce01 2459 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2460 for (i = 0; i < msrs->nmsrs; ++i)
2461 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2462 break;
f656ce01 2463 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2464
313a3dc7
CO		 2465 return i;
2466}
2467
2468/*
2469 * Read or write a bunch of msrs. Parameters are user addresses.
2470 *
2471 * @return number of msrs set successfully.
2472 */
2473static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2474 int (*do_msr)(struct kvm_vcpu *vcpu,
2475 unsigned index, u64 *data),
2476 int writeback)
2477{
2478 struct kvm_msrs msrs;
2479 struct kvm_msr_entry *entries;
2480 int r, n;
2481 unsigned size;
2482
2483 r = -EFAULT;
2484 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2485 goto out;
2486
2487 r = -E2BIG;
2488 if (msrs.nmsrs >= MAX_IO_MSRS)
2489 goto out;
2490
313a3dc7 2491 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2492 entries = memdup_user(user_msrs->entries, size);
2493 if (IS_ERR(entries)) {
2494 r = PTR_ERR(entries);
313a3dc7 2495 goto out;
ff5c2c03 2496 }
313a3dc7
CO		 2497
2498 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2499 if (r < 0)
2500 goto out_free;
2501
2502 r = -EFAULT;
2503 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2504 goto out_free;
2505
2506 r = n;
2507
2508out_free:
7a73c028 2509 kfree(entries);
313a3dc7
CO		 2510out:
2511 return r;
2512}
2513
784aa3d7 2514int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2515{
2516 int r;
2517
2518 switch (ext) {
2519 case KVM_CAP_IRQCHIP:
2520 case KVM_CAP_HLT:
2521 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2522 case KVM_CAP_SET_TSS_ADDR:
07716717 2523 case KVM_CAP_EXT_CPUID:
9c15bb1d 2524 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2525 case KVM_CAP_CLOCKSOURCE:
7837699f 2526 case KVM_CAP_PIT:
a28e4f5a 2527 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2528 case KVM_CAP_MP_STATE:
ed848624 2529 case KVM_CAP_SYNC_MMU:
a355c85c 2530 case KVM_CAP_USER_NMI:
52d939a0 2531 case KVM_CAP_REINJECT_CONTROL:
4925663a 2532 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2533 case KVM_CAP_IOEVENTFD:
f848a5a8 2534 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2535 case KVM_CAP_PIT2:
e9f42757 2536 case KVM_CAP_PIT_STATE2:
b927a3ce 2537 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2538 case KVM_CAP_XEN_HVM:
afbcf7ab 2539 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2540 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2541 case KVM_CAP_HYPERV:
10388a07 2542 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2543 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2544 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2545 case KVM_CAP_DEBUGREGS:
d2be1651 2546 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2547 case KVM_CAP_XSAVE:
344d9588 2548 case KVM_CAP_ASYNC_PF:
92a1f12d 2549 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2550 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2551 case KVM_CAP_READONLY_MEM:
5f66b620 2552 case KVM_CAP_HYPERV_TIME:
100943c5 2553 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2554 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2555 case KVM_CAP_ENABLE_CAP_VM:
2556 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2557 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2558 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2559#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2560 case KVM_CAP_ASSIGN_DEV_IRQ:
2561 case KVM_CAP_PCI_2_3:
2562#endif
018d00d2
ZX		 2563 r = 1;
2564 break;
6d396b55
PB		 2565 case KVM_CAP_X86_SMM:
2566 /* SMBASE is usually relocated above 1M on modern chipsets,
2567 * and SMM handlers might indeed rely on 4G segment limits,
2568 * so do not report SMM to be available if real mode is
2569 * emulated via vm86 mode. Still, do not go to great lengths
2570 * to avoid userspace's usage of the feature, because it is a
2571 * fringe case that is not enabled except via specific settings
2572 * of the module parameters.
2573 */
2574 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2575 break;
542472b5
LV		 2576 case KVM_CAP_COALESCED_MMIO:
2577 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2578 break;
774ead3a
AK		 2579 case KVM_CAP_VAPIC:
2580 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2581 break;
f725230a 2582 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2583 r = KVM_SOFT_MAX_VCPUS;
2584 break;
2585 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2586 r = KVM_MAX_VCPUS;
2587 break;
a988b910 2588 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2589 r = KVM_USER_MEM_SLOTS;
a988b910 2590 break;
a68a6a72
MT		 2591 case KVM_CAP_PV_MMU: /* obsolete */
2592 r = 0;
2f333bcb 2593 break;
4cee4b72 2594#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2595 case KVM_CAP_IOMMU:
a1b60c1c 2596 r = iommu_present(&pci_bus_type);
62c476c7 2597 break;
4cee4b72 2598#endif
890ca9ae
HY		 2599 case KVM_CAP_MCE:
2600 r = KVM_MAX_MCE_BANKS;
2601 break;
2d5b5a66
SY		 2602 case KVM_CAP_XCRS:
2603 r = cpu_has_xsave;
2604 break;
92a1f12d
JR		 2605 case KVM_CAP_TSC_CONTROL:
2606 r = kvm_has_tsc_control;
2607 break;
018d00d2
ZX		 2608 default:
2609 r = 0;
2610 break;
2611 }
2612 return r;
2613
2614}
2615
043405e1
CO		 2616long kvm_arch_dev_ioctl(struct file *filp,
2617 unsigned int ioctl, unsigned long arg)
2618{
2619 void __user *argp = (void __user *)arg;
2620 long r;
2621
2622 switch (ioctl) {
2623 case KVM_GET_MSR_INDEX_LIST: {
2624 struct kvm_msr_list __user *user_msr_list = argp;
2625 struct kvm_msr_list msr_list;
2626 unsigned n;
2627
2628 r = -EFAULT;
2629 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2630 goto out;
2631 n = msr_list.nmsrs;
62ef68bb 2632 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2633 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2634 goto out;
2635 r = -E2BIG;
e125e7b6 2636 if (n < msr_list.nmsrs)
043405e1
CO		 2637 goto out;
2638 r = -EFAULT;
2639 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2640 num_msrs_to_save * sizeof(u32)))
2641 goto out;
e125e7b6 2642 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2643 &emulated_msrs,
62ef68bb 2644 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2645 goto out;
2646 r = 0;
2647 break;
2648 }
9c15bb1d
BP		 2649 case KVM_GET_SUPPORTED_CPUID:
2650 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2651 struct kvm_cpuid2 __user *cpuid_arg = argp;
2652 struct kvm_cpuid2 cpuid;
2653
2654 r = -EFAULT;
2655 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2656 goto out;
9c15bb1d
BP		 2657
2658 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2659 ioctl);
674eea0f
AK		 2660 if (r)
2661 goto out;
2662
2663 r = -EFAULT;
2664 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2665 goto out;
2666 r = 0;
2667 break;
2668 }
890ca9ae
HY		 2669 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2670 u64 mce_cap;
2671
2672 mce_cap = KVM_MCE_CAP_SUPPORTED;
2673 r = -EFAULT;
2674 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2675 goto out;
2676 r = 0;
2677 break;
2678 }
043405e1
CO		 2679 default:
2680 r = -EINVAL;
2681 }
2682out:
2683 return r;
2684}
2685
f5f48ee1
SY		 2686static void wbinvd_ipi(void *garbage)
2687{
2688 wbinvd();
2689}
2690
2691static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2692{
e0f0bbc5 2693 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2694}
2695
313a3dc7
CO		 2696void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2697{
f5f48ee1
SY		 2698 /* Address WBINVD may be executed by guest */
2699 if (need_emulate_wbinvd(vcpu)) {
2700 if (kvm_x86_ops->has_wbinvd_exit())
2701 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2702 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2703 smp_call_function_single(vcpu->cpu,
2704 wbinvd_ipi, NULL, 1);
2705 }
2706
313a3dc7 2707 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2708
0dd6a6ed
ZA		 2709 /* Apply any externally detected TSC adjustments (due to suspend) */
2710 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2711 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2712 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2713 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2714 }
8f6055cb 2715
48434c20 2716 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2717 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2718 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2719 if (tsc_delta < 0)
2720 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2721 if (check_tsc_unstable()) {
07c1419a 2722 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2723 vcpu->arch.last_guest_tsc);
2724 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2725 vcpu->arch.tsc_catchup = 1;
c285545f 2726 }
d98d07ca
MT		 2727 /*
2728 * On a host with synchronized TSC, there is no need to update
2729 * kvmclock on vcpu->cpu migration
2730 */
2731 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2732 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2733 if (vcpu->cpu != cpu)
2734 kvm_migrate_timers(vcpu);
e48672fa 2735 vcpu->cpu = cpu;
6b7d7e76 2736 }
c9aaa895 2737
c9aaa895 2738 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2739}
2740
2741void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2742{
02daab21 2743 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2744 kvm_put_guest_fpu(vcpu);
4ea1636b 2745 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2746}
2747
313a3dc7
CO		 2748static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2749 struct kvm_lapic_state *s)
2750{
5a71785d 2751 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2752 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2753
2754 return 0;
2755}
2756
2757static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2758 struct kvm_lapic_state *s)
2759{
64eb0620 2760 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2761 update_cr8_intercept(vcpu);
313a3dc7
CO		 2762
2763 return 0;
2764}
2765
127a457a
MG		 2766static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2767{
2768 return (!lapic_in_kernel(vcpu) ||
2769 kvm_apic_accept_pic_intr(vcpu));
2770}
2771
f77bc6a4
ZX		 2772static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2773 struct kvm_interrupt *irq)
2774{
02cdb50f 2775 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2776 return -EINVAL;
1c1a9ce9
SR		 2777
2778 if (!irqchip_in_kernel(vcpu->kvm)) {
2779 kvm_queue_interrupt(vcpu, irq->irq, false);
2780 kvm_make_request(KVM_REQ_EVENT, vcpu);
2781 return 0;
2782 }
2783
2784 /*
2785 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2786 * fail for in-kernel 8259.
2787 */
2788 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2789 return -ENXIO;
f77bc6a4 2790
1c1a9ce9
SR		 2791 if (vcpu->arch.pending_external_vector != -1)
2792 return -EEXIST;
f77bc6a4 2793
1c1a9ce9 2794 vcpu->arch.pending_external_vector = irq->irq;
f77bc6a4
ZX		 2795 return 0;
2796}
2797
c4abb7c9
JK		 2798static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2799{
c4abb7c9 2800 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2801
2802 return 0;
2803}
2804
f077825a
PB		 2805static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2806{
64d60670
PB		 2807 kvm_make_request(KVM_REQ_SMI, vcpu);
2808
f077825a
PB		 2809 return 0;
2810}
2811
b209749f
AK		 2812static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2813 struct kvm_tpr_access_ctl *tac)
2814{
2815 if (tac->flags)
2816 return -EINVAL;
2817 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2818 return 0;
2819}
2820
890ca9ae
HY		 2821static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2822 u64 mcg_cap)
2823{
2824 int r;
2825 unsigned bank_num = mcg_cap & 0xff, bank;
2826
2827 r = -EINVAL;
a9e38c3e 2828 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2829 goto out;
2830 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2831 goto out;
2832 r = 0;
2833 vcpu->arch.mcg_cap = mcg_cap;
2834 /* Init IA32_MCG_CTL to all 1s */
2835 if (mcg_cap & MCG_CTL_P)
2836 vcpu->arch.mcg_ctl = ~(u64)0;
2837 /* Init IA32_MCi_CTL to all 1s */
2838 for (bank = 0; bank < bank_num; bank++)
2839 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2840out:
2841 return r;
2842}
2843
2844static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2845 struct kvm_x86_mce *mce)
2846{
2847 u64 mcg_cap = vcpu->arch.mcg_cap;
2848 unsigned bank_num = mcg_cap & 0xff;
2849 u64 *banks = vcpu->arch.mce_banks;
2850
2851 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2852 return -EINVAL;
2853 /*
2854 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2855 * reporting is disabled
2856 */
2857 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2858 vcpu->arch.mcg_ctl != ~(u64)0)
2859 return 0;
2860 banks += 4 * mce->bank;
2861 /*
2862 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2863 * reporting is disabled for the bank
2864 */
2865 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2866 return 0;
2867 if (mce->status & MCI_STATUS_UC) {
2868 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2869 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2870 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2871 return 0;
2872 }
2873 if (banks[1] & MCI_STATUS_VAL)
2874 mce->status |= MCI_STATUS_OVER;
2875 banks[2] = mce->addr;
2876 banks[3] = mce->misc;
2877 vcpu->arch.mcg_status = mce->mcg_status;
2878 banks[1] = mce->status;
2879 kvm_queue_exception(vcpu, MC_VECTOR);
2880 } else if (!(banks[1] & MCI_STATUS_VAL)
2881 || !(banks[1] & MCI_STATUS_UC)) {
2882 if (banks[1] & MCI_STATUS_VAL)
2883 mce->status |= MCI_STATUS_OVER;
2884 banks[2] = mce->addr;
2885 banks[3] = mce->misc;
2886 banks[1] = mce->status;
2887 } else
2888 banks[1] |= MCI_STATUS_OVER;
2889 return 0;
2890}
2891
3cfc3092
JK		 2892static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2893 struct kvm_vcpu_events *events)
2894{
7460fb4a 2895 process_nmi(vcpu);
03b82a30
JK		 2896 events->exception.injected =
2897 vcpu->arch.exception.pending &&
2898 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2899 events->exception.nr = vcpu->arch.exception.nr;
2900 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2901 events->exception.pad = 0;
3cfc3092
JK		 2902 events->exception.error_code = vcpu->arch.exception.error_code;
2903
03b82a30
JK		 2904 events->interrupt.injected =
2905 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2906 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2907 events->interrupt.soft = 0;
37ccdcbe 2908 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2909
2910 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2911 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2912 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2913 events->nmi.pad = 0;
3cfc3092 2914
66450a21 2915 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2916
f077825a
PB		 2917 events->smi.smm = is_smm(vcpu);
2918 events->smi.pending = vcpu->arch.smi_pending;
2919 events->smi.smm_inside_nmi =
2920 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2921 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2922
dab4b911 2923 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2924 | KVM_VCPUEVENT_VALID_SHADOW
2925 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2926 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2927}
2928
2929static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2930 struct kvm_vcpu_events *events)
2931{
dab4b911 2932 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2933 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2934 | KVM_VCPUEVENT_VALID_SHADOW
2935 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2936 return -EINVAL;
2937
7460fb4a 2938 process_nmi(vcpu);
3cfc3092
JK		 2939 vcpu->arch.exception.pending = events->exception.injected;
2940 vcpu->arch.exception.nr = events->exception.nr;
2941 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2942 vcpu->arch.exception.error_code = events->exception.error_code;
2943
2944 vcpu->arch.interrupt.pending = events->interrupt.injected;
2945 vcpu->arch.interrupt.nr = events->interrupt.nr;
2946 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2947 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2948 kvm_x86_ops->set_interrupt_shadow(vcpu,
2949 events->interrupt.shadow);
3cfc3092
JK		 2950
2951 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2952 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2953 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2954 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2955
66450a21
JK		 2956 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2957 kvm_vcpu_has_lapic(vcpu))
2958 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2959
f077825a
PB		 2960 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2961 if (events->smi.smm)
2962 vcpu->arch.hflags |= HF_SMM_MASK;
2963 else
2964 vcpu->arch.hflags &= ~HF_SMM_MASK;
2965 vcpu->arch.smi_pending = events->smi.pending;
2966 if (events->smi.smm_inside_nmi)
2967 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2968 else
2969 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2970 if (kvm_vcpu_has_lapic(vcpu)) {
2971 if (events->smi.latched_init)
2972 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2973 else
2974 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2975 }
2976 }
2977
3842d135
AK		 2978 kvm_make_request(KVM_REQ_EVENT, vcpu);
2979
3cfc3092
JK		 2980 return 0;
2981}
2982
a1efbe77
JK		 2983static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2984 struct kvm_debugregs *dbgregs)
2985{
73aaf249
JK		 2986 unsigned long val;
2987
a1efbe77 2988 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 2989 kvm_get_dr(vcpu, 6, &val);
73aaf249 2990 dbgregs->dr6 = val;
a1efbe77
JK		 2991 dbgregs->dr7 = vcpu->arch.dr7;
2992 dbgregs->flags = 0;
97e69aa6 2993 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2994}
2995
2996static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2997 struct kvm_debugregs *dbgregs)
2998{
2999 if (dbgregs->flags)
3000 return -EINVAL;
3001
a1efbe77 3002 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3003 kvm_update_dr0123(vcpu);
a1efbe77 3004 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3005 kvm_update_dr6(vcpu);
a1efbe77 3006 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3007 kvm_update_dr7(vcpu);
a1efbe77 3008
a1efbe77
JK		 3009 return 0;
3010}
3011
df1daba7
PB		 3012#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3013
3014static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3015{
c47ada30 3016 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3017 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3018 u64 valid;
3019
3020 /*
3021 * Copy legacy XSAVE area, to avoid complications with CPUID
3022 * leaves 0 and 1 in the loop below.
3023 */
3024 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3025
3026 /* Set XSTATE_BV */
3027 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3028
3029 /*
3030 * Copy each region from the possibly compacted offset to the
3031 * non-compacted offset.
3032 */
d91cab78 3033 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3034 while (valid) {
3035 u64 feature = valid & -valid;
3036 int index = fls64(feature) - 1;
3037 void *src = get_xsave_addr(xsave, feature);
3038
3039 if (src) {
3040 u32 size, offset, ecx, edx;
3041 cpuid_count(XSTATE_CPUID, index,
3042 &size, &offset, &ecx, &edx);
3043 memcpy(dest + offset, src, size);
3044 }
3045
3046 valid -= feature;
3047 }
3048}
3049
3050static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3051{
c47ada30 3052 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3053 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3054 u64 valid;
3055
3056 /*
3057 * Copy legacy XSAVE area, to avoid complications with CPUID
3058 * leaves 0 and 1 in the loop below.
3059 */
3060 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3061
3062 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3063 xsave->header.xfeatures = xstate_bv;
df1daba7 3064 if (cpu_has_xsaves)
3a54450b 3065 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3066
3067 /*
3068 * Copy each region from the non-compacted offset to the
3069 * possibly compacted offset.
3070 */
d91cab78 3071 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3072 while (valid) {
3073 u64 feature = valid & -valid;
3074 int index = fls64(feature) - 1;
3075 void *dest = get_xsave_addr(xsave, feature);
3076
3077 if (dest) {
3078 u32 size, offset, ecx, edx;
3079 cpuid_count(XSTATE_CPUID, index,
3080 &size, &offset, &ecx, &edx);
3081 memcpy(dest, src + offset, size);
ee4100da 3082 }
df1daba7
PB		 3083
3084 valid -= feature;
3085 }
3086}
3087
2d5b5a66
SY		 3088static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3089 struct kvm_xsave *guest_xsave)
3090{
4344ee98 3091 if (cpu_has_xsave) {
df1daba7
PB		 3092 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3093 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3094 } else {
2d5b5a66 3095 memcpy(guest_xsave->region,
7366ed77 3096 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3097 sizeof(struct fxregs_state));
2d5b5a66 3098 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3099 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3100 }
3101}
3102
3103static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3104 struct kvm_xsave *guest_xsave)
3105{
3106 u64 xstate_bv =
3107 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3108
d7876f1b
PB		 3109 if (cpu_has_xsave) {
3110 /*
3111 * Here we allow setting states that are not present in
3112 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3113 * with old userspace.
3114 */
4ff41732 3115 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3116 return -EINVAL;
df1daba7 3117 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3118 } else {
d91cab78 3119 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3120 return -EINVAL;
7366ed77 3121 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3122 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3123 }
3124 return 0;
3125}
3126
3127static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3128 struct kvm_xcrs *guest_xcrs)
3129{
3130 if (!cpu_has_xsave) {
3131 guest_xcrs->nr_xcrs = 0;
3132 return;
3133 }
3134
3135 guest_xcrs->nr_xcrs = 1;
3136 guest_xcrs->flags = 0;
3137 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3138 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3139}
3140
3141static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3142 struct kvm_xcrs *guest_xcrs)
3143{
3144 int i, r = 0;
3145
3146 if (!cpu_has_xsave)
3147 return -EINVAL;
3148
3149 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3150 return -EINVAL;
3151
3152 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3153 /* Only support XCR0 currently */
c67a04cb 3154 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3155 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3156 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3157 break;
3158 }
3159 if (r)
3160 r = -EINVAL;
3161 return r;
3162}
3163
1c0b28c2
EM		 3164/*
3165 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3166 * stopped by the hypervisor. This function will be called from the host only.
3167 * EINVAL is returned when the host attempts to set the flag for a guest that
3168 * does not support pv clocks.
3169 */
3170static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3171{
0b79459b 3172 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3173 return -EINVAL;
51d59c6b 3174 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3175 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3176 return 0;
3177}
3178
313a3dc7
CO		 3179long kvm_arch_vcpu_ioctl(struct file *filp,
3180 unsigned int ioctl, unsigned long arg)
3181{
3182 struct kvm_vcpu *vcpu = filp->private_data;
3183 void __user *argp = (void __user *)arg;
3184 int r;
d1ac91d8
AK		 3185 union {
3186 struct kvm_lapic_state *lapic;
3187 struct kvm_xsave *xsave;
3188 struct kvm_xcrs *xcrs;
3189 void *buffer;
3190 } u;
3191
3192 u.buffer = NULL;
313a3dc7
CO		 3193 switch (ioctl) {
3194 case KVM_GET_LAPIC: {
2204ae3c
MT		 3195 r = -EINVAL;
3196 if (!vcpu->arch.apic)
3197 goto out;
d1ac91d8 3198 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3199
b772ff36 3200 r = -ENOMEM;
d1ac91d8 3201 if (!u.lapic)
b772ff36 3202 goto out;
d1ac91d8 3203 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3204 if (r)
3205 goto out;
3206 r = -EFAULT;
d1ac91d8 3207 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3208 goto out;
3209 r = 0;
3210 break;
3211 }
3212 case KVM_SET_LAPIC: {
2204ae3c
MT		 3213 r = -EINVAL;
3214 if (!vcpu->arch.apic)
3215 goto out;
ff5c2c03 3216 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3217 if (IS_ERR(u.lapic))
3218 return PTR_ERR(u.lapic);
ff5c2c03 3219
d1ac91d8 3220 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3221 break;
3222 }
f77bc6a4
ZX		 3223 case KVM_INTERRUPT: {
3224 struct kvm_interrupt irq;
3225
3226 r = -EFAULT;
3227 if (copy_from_user(&irq, argp, sizeof irq))
3228 goto out;
3229 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3230 break;
3231 }
c4abb7c9
JK		 3232 case KVM_NMI: {
3233 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3234 break;
3235 }
f077825a
PB		 3236 case KVM_SMI: {
3237 r = kvm_vcpu_ioctl_smi(vcpu);
3238 break;
3239 }
313a3dc7
CO		 3240 case KVM_SET_CPUID: {
3241 struct kvm_cpuid __user *cpuid_arg = argp;
3242 struct kvm_cpuid cpuid;
3243
3244 r = -EFAULT;
3245 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3246 goto out;
3247 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3248 break;
3249 }
07716717
DK		 3250 case KVM_SET_CPUID2: {
3251 struct kvm_cpuid2 __user *cpuid_arg = argp;
3252 struct kvm_cpuid2 cpuid;
3253
3254 r = -EFAULT;
3255 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3256 goto out;
3257 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3258 cpuid_arg->entries);
07716717
DK		 3259 break;
3260 }
3261 case KVM_GET_CPUID2: {
3262 struct kvm_cpuid2 __user *cpuid_arg = argp;
3263 struct kvm_cpuid2 cpuid;
3264
3265 r = -EFAULT;
3266 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3267 goto out;
3268 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3269 cpuid_arg->entries);
07716717
DK		 3270 if (r)
3271 goto out;
3272 r = -EFAULT;
3273 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3274 goto out;
3275 r = 0;
3276 break;
3277 }
313a3dc7 3278 case KVM_GET_MSRS:
609e36d3 3279 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3280 break;
3281 case KVM_SET_MSRS:
3282 r = msr_io(vcpu, argp, do_set_msr, 0);
3283 break;
b209749f
AK		 3284 case KVM_TPR_ACCESS_REPORTING: {
3285 struct kvm_tpr_access_ctl tac;
3286
3287 r = -EFAULT;
3288 if (copy_from_user(&tac, argp, sizeof tac))
3289 goto out;
3290 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3291 if (r)
3292 goto out;
3293 r = -EFAULT;
3294 if (copy_to_user(argp, &tac, sizeof tac))
3295 goto out;
3296 r = 0;
3297 break;
3298 };
b93463aa
AK		 3299 case KVM_SET_VAPIC_ADDR: {
3300 struct kvm_vapic_addr va;
3301
3302 r = -EINVAL;
35754c98 3303 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3304 goto out;
3305 r = -EFAULT;
3306 if (copy_from_user(&va, argp, sizeof va))
3307 goto out;
fda4e2e8 3308 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3309 break;
3310 }
890ca9ae
HY		 3311 case KVM_X86_SETUP_MCE: {
3312 u64 mcg_cap;
3313
3314 r = -EFAULT;
3315 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3316 goto out;
3317 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3318 break;
3319 }
3320 case KVM_X86_SET_MCE: {
3321 struct kvm_x86_mce mce;
3322
3323 r = -EFAULT;
3324 if (copy_from_user(&mce, argp, sizeof mce))
3325 goto out;
3326 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3327 break;
3328 }
3cfc3092
JK		 3329 case KVM_GET_VCPU_EVENTS: {
3330 struct kvm_vcpu_events events;
3331
3332 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3333
3334 r = -EFAULT;
3335 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3336 break;
3337 r = 0;
3338 break;
3339 }
3340 case KVM_SET_VCPU_EVENTS: {
3341 struct kvm_vcpu_events events;
3342
3343 r = -EFAULT;
3344 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3345 break;
3346
3347 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3348 break;
3349 }
a1efbe77
JK		 3350 case KVM_GET_DEBUGREGS: {
3351 struct kvm_debugregs dbgregs;
3352
3353 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3354
3355 r = -EFAULT;
3356 if (copy_to_user(argp, &dbgregs,
3357 sizeof(struct kvm_debugregs)))
3358 break;
3359 r = 0;
3360 break;
3361 }
3362 case KVM_SET_DEBUGREGS: {
3363 struct kvm_debugregs dbgregs;
3364
3365 r = -EFAULT;
3366 if (copy_from_user(&dbgregs, argp,
3367 sizeof(struct kvm_debugregs)))
3368 break;
3369
3370 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3371 break;
3372 }
2d5b5a66 3373 case KVM_GET_XSAVE: {
d1ac91d8 3374 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3375 r = -ENOMEM;
d1ac91d8 3376 if (!u.xsave)
2d5b5a66
SY		 3377 break;
3378
d1ac91d8 3379 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3380
3381 r = -EFAULT;
d1ac91d8 3382 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3383 break;
3384 r = 0;
3385 break;
3386 }
3387 case KVM_SET_XSAVE: {
ff5c2c03 3388 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3389 if (IS_ERR(u.xsave))
3390 return PTR_ERR(u.xsave);
2d5b5a66 3391
d1ac91d8 3392 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3393 break;
3394 }
3395 case KVM_GET_XCRS: {
d1ac91d8 3396 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3397 r = -ENOMEM;
d1ac91d8 3398 if (!u.xcrs)
2d5b5a66
SY		 3399 break;
3400
d1ac91d8 3401 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3402
3403 r = -EFAULT;
d1ac91d8 3404 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3405 sizeof(struct kvm_xcrs)))
3406 break;
3407 r = 0;
3408 break;
3409 }
3410 case KVM_SET_XCRS: {
ff5c2c03 3411 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3412 if (IS_ERR(u.xcrs))
3413 return PTR_ERR(u.xcrs);
2d5b5a66 3414
d1ac91d8 3415 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3416 break;
3417 }
92a1f12d
JR		 3418 case KVM_SET_TSC_KHZ: {
3419 u32 user_tsc_khz;
3420
3421 r = -EINVAL;
92a1f12d
JR		 3422 user_tsc_khz = (u32)arg;
3423
3424 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3425 goto out;
3426
cc578287
ZA		 3427 if (user_tsc_khz == 0)
3428 user_tsc_khz = tsc_khz;
3429
381d585c
HZ		 3430 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3431 r = 0;
92a1f12d 3432
92a1f12d
JR		 3433 goto out;
3434 }
3435 case KVM_GET_TSC_KHZ: {
cc578287 3436 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3437 goto out;
3438 }
1c0b28c2
EM		 3439 case KVM_KVMCLOCK_CTRL: {
3440 r = kvm_set_guest_paused(vcpu);
3441 goto out;
3442 }
313a3dc7
CO		 3443 default:
3444 r = -EINVAL;
3445 }
3446out:
d1ac91d8 3447 kfree(u.buffer);
313a3dc7
CO		 3448 return r;
3449}
3450
5b1c1493
CO		 3451int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3452{
3453 return VM_FAULT_SIGBUS;
3454}
3455
1fe779f8
CO		 3456static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3457{
3458 int ret;
3459
3460 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3461 return -EINVAL;
1fe779f8
CO		 3462 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3463 return ret;
3464}
3465
b927a3ce
SY		 3466static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3467 u64 ident_addr)
3468{
3469 kvm->arch.ept_identity_map_addr = ident_addr;
3470 return 0;
3471}
3472
1fe779f8
CO		 3473static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3474 u32 kvm_nr_mmu_pages)
3475{
3476 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3477 return -EINVAL;
3478
79fac95e 3479 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3480
3481 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3482 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3483
79fac95e 3484 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3485 return 0;
3486}
3487
3488static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3489{
39de71ec 3490 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3491}
3492
1fe779f8
CO		 3493static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3494{
3495 int r;
3496
3497 r = 0;
3498 switch (chip->chip_id) {
3499 case KVM_IRQCHIP_PIC_MASTER:
3500 memcpy(&chip->chip.pic,
3501 &pic_irqchip(kvm)->pics[0],
3502 sizeof(struct kvm_pic_state));
3503 break;
3504 case KVM_IRQCHIP_PIC_SLAVE:
3505 memcpy(&chip->chip.pic,
3506 &pic_irqchip(kvm)->pics[1],
3507 sizeof(struct kvm_pic_state));
3508 break;
3509 case KVM_IRQCHIP_IOAPIC:
eba0226b 3510 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3511 break;
3512 default:
3513 r = -EINVAL;
3514 break;
3515 }
3516 return r;
3517}
3518
3519static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3520{
3521 int r;
3522
3523 r = 0;
3524 switch (chip->chip_id) {
3525 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3526 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3527 memcpy(&pic_irqchip(kvm)->pics[0],
3528 &chip->chip.pic,
3529 sizeof(struct kvm_pic_state));
f4f51050 3530 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3531 break;
3532 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3533 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3534 memcpy(&pic_irqchip(kvm)->pics[1],
3535 &chip->chip.pic,
3536 sizeof(struct kvm_pic_state));
f4f51050 3537 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3538 break;
3539 case KVM_IRQCHIP_IOAPIC:
eba0226b 3540 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3541 break;
3542 default:
3543 r = -EINVAL;
3544 break;
3545 }
3546 kvm_pic_update_irq(pic_irqchip(kvm));
3547 return r;
3548}
3549
e0f63cb9
SY		 3550static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3551{
894a9c55 3552 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3553 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3554 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3555 return 0;
e0f63cb9
SY		 3556}
3557
3558static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3559{
894a9c55 3560 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3561 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3562 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3563 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3564 return 0;
e9f42757
BK		 3565}
3566
3567static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3568{
e9f42757
BK		 3569 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3570 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3571 sizeof(ps->channels));
3572 ps->flags = kvm->arch.vpit->pit_state.flags;
3573 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3574 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3575 return 0;
e9f42757
BK		 3576}
3577
3578static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3579{
2da29bcc 3580 int start = 0;
e9f42757
BK		 3581 u32 prev_legacy, cur_legacy;
3582 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3583 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3584 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3585 if (!prev_legacy && cur_legacy)
3586 start = 1;
3587 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3588 sizeof(kvm->arch.vpit->pit_state.channels));
3589 kvm->arch.vpit->pit_state.flags = ps->flags;
3590 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3591 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3592 return 0;
e0f63cb9
SY		 3593}
3594
52d939a0
MT		 3595static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3596 struct kvm_reinject_control *control)
3597{
3598 if (!kvm->arch.vpit)
3599 return -ENXIO;
894a9c55 3600 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3601 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3602 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3603 return 0;
3604}
3605
95d4c16c 3606/**
60c34612
TY		 3607 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3608 * @kvm: kvm instance
3609 * @log: slot id and address to which we copy the log
95d4c16c 3610 *
e108ff2f
PB		 3611 * Steps 1-4 below provide general overview of dirty page logging. See
3612 * kvm_get_dirty_log_protect() function description for additional details.
3613 *
3614 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3615 * always flush the TLB (step 4) even if previous step failed and the dirty
3616 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3617 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3618 * writes will be marked dirty for next log read.
95d4c16c 3619 *
60c34612
TY		 3620 * 1. Take a snapshot of the bit and clear it if needed.
3621 * 2. Write protect the corresponding page.
e108ff2f
PB		 3622 * 3. Copy the snapshot to the userspace.
3623 * 4. Flush TLB's if needed.
5bb064dc 3624 */
60c34612 3625int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3626{
60c34612 3627 bool is_dirty = false;
e108ff2f 3628 int r;
5bb064dc 3629
79fac95e 3630 mutex_lock(&kvm->slots_lock);
5bb064dc 3631
88178fd4
KH		 3632 /*
3633 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3634 */
3635 if (kvm_x86_ops->flush_log_dirty)
3636 kvm_x86_ops->flush_log_dirty(kvm);
3637
e108ff2f 3638 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3639
3640 /*
3641 * All the TLBs can be flushed out of mmu lock, see the comments in
3642 * kvm_mmu_slot_remove_write_access().
3643 */
e108ff2f 3644 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3645 if (is_dirty)
3646 kvm_flush_remote_tlbs(kvm);
3647
79fac95e 3648 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3649 return r;
3650}
3651
aa2fbe6d
YZ		 3652int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3653 bool line_status)
23d43cf9
CD		 3654{
3655 if (!irqchip_in_kernel(kvm))
3656 return -ENXIO;
3657
3658 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3659 irq_event->irq, irq_event->level,
3660 line_status);
23d43cf9
CD		 3661 return 0;
3662}
3663
90de4a18
NA		 3664static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3665 struct kvm_enable_cap *cap)
3666{
3667 int r;
3668
3669 if (cap->flags)
3670 return -EINVAL;
3671
3672 switch (cap->cap) {
3673 case KVM_CAP_DISABLE_QUIRKS:
3674 kvm->arch.disabled_quirks = cap->args[0];
3675 r = 0;
3676 break;
49df6397
SR		 3677 case KVM_CAP_SPLIT_IRQCHIP: {
3678 mutex_lock(&kvm->lock);
b053b2ae
SR		 3679 r = -EINVAL;
3680 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3681 goto split_irqchip_unlock;
49df6397
SR		 3682 r = -EEXIST;
3683 if (irqchip_in_kernel(kvm))
3684 goto split_irqchip_unlock;
3685 if (atomic_read(&kvm->online_vcpus))
3686 goto split_irqchip_unlock;
3687 r = kvm_setup_empty_irq_routing(kvm);
3688 if (r)
3689 goto split_irqchip_unlock;
3690 /* Pairs with irqchip_in_kernel. */
3691 smp_wmb();
3692 kvm->arch.irqchip_split = true;
b053b2ae 3693 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3694 r = 0;
3695split_irqchip_unlock:
3696 mutex_unlock(&kvm->lock);
3697 break;
3698 }
90de4a18
NA		 3699 default:
3700 r = -EINVAL;
3701 break;
3702 }
3703 return r;
3704}
3705
1fe779f8
CO		 3706long kvm_arch_vm_ioctl(struct file *filp,
3707 unsigned int ioctl, unsigned long arg)
3708{
3709 struct kvm *kvm = filp->private_data;
3710 void __user *argp = (void __user *)arg;
367e1319 3711 int r = -ENOTTY;
f0d66275
DH		 3712 /*
3713 * This union makes it completely explicit to gcc-3.x
3714 * that these two variables' stack usage should be
3715 * combined, not added together.
3716 */
3717 union {
3718 struct kvm_pit_state ps;
e9f42757 3719 struct kvm_pit_state2 ps2;
c5ff41ce 3720 struct kvm_pit_config pit_config;
f0d66275 3721 } u;
1fe779f8
CO		 3722
3723 switch (ioctl) {
3724 case KVM_SET_TSS_ADDR:
3725 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3726 break;
b927a3ce
SY		 3727 case KVM_SET_IDENTITY_MAP_ADDR: {
3728 u64 ident_addr;
3729
3730 r = -EFAULT;
3731 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3732 goto out;
3733 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3734 break;
3735 }
1fe779f8
CO		 3736 case KVM_SET_NR_MMU_PAGES:
3737 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3738 break;
3739 case KVM_GET_NR_MMU_PAGES:
3740 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3741 break;
3ddea128
MT		 3742 case KVM_CREATE_IRQCHIP: {
3743 struct kvm_pic *vpic;
3744
3745 mutex_lock(&kvm->lock);
3746 r = -EEXIST;
3747 if (kvm->arch.vpic)
3748 goto create_irqchip_unlock;
3e515705
AK		 3749 r = -EINVAL;
3750 if (atomic_read(&kvm->online_vcpus))
3751 goto create_irqchip_unlock;
1fe779f8 3752 r = -ENOMEM;
3ddea128
MT		 3753 vpic = kvm_create_pic(kvm);
3754 if (vpic) {
1fe779f8
CO		 3755 r = kvm_ioapic_init(kvm);
3756 if (r) {
175504cd 3757 mutex_lock(&kvm->slots_lock);
71ba994c 3758 kvm_destroy_pic(vpic);
175504cd 3759 mutex_unlock(&kvm->slots_lock);
3ddea128 3760 goto create_irqchip_unlock;
1fe779f8
CO		 3761 }
3762 } else
3ddea128 3763 goto create_irqchip_unlock;
399ec807
AK		 3764 r = kvm_setup_default_irq_routing(kvm);
3765 if (r) {
175504cd 3766 mutex_lock(&kvm->slots_lock);
3ddea128 3767 mutex_lock(&kvm->irq_lock);
72bb2fcd 3768 kvm_ioapic_destroy(kvm);
71ba994c 3769 kvm_destroy_pic(vpic);
3ddea128 3770 mutex_unlock(&kvm->irq_lock);
175504cd 3771 mutex_unlock(&kvm->slots_lock);
71ba994c 3772 goto create_irqchip_unlock;
399ec807 3773 }
71ba994c
PB		 3774 /* Write kvm->irq_routing before kvm->arch.vpic. */
3775 smp_wmb();
3776 kvm->arch.vpic = vpic;
3ddea128
MT		 3777 create_irqchip_unlock:
3778 mutex_unlock(&kvm->lock);
1fe779f8 3779 break;
3ddea128 3780 }
7837699f 3781 case KVM_CREATE_PIT:
c5ff41ce
JK		 3782 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3783 goto create_pit;
3784 case KVM_CREATE_PIT2:
3785 r = -EFAULT;
3786 if (copy_from_user(&u.pit_config, argp,
3787 sizeof(struct kvm_pit_config)))
3788 goto out;
3789 create_pit:
79fac95e 3790 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3791 r = -EEXIST;
3792 if (kvm->arch.vpit)
3793 goto create_pit_unlock;
7837699f 3794 r = -ENOMEM;
c5ff41ce 3795 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3796 if (kvm->arch.vpit)
3797 r = 0;
269e05e4 3798 create_pit_unlock:
79fac95e 3799 mutex_unlock(&kvm->slots_lock);
7837699f 3800 break;
1fe779f8
CO		 3801 case KVM_GET_IRQCHIP: {
3802 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3803 struct kvm_irqchip *chip;
1fe779f8 3804
ff5c2c03
SL		 3805 chip = memdup_user(argp, sizeof(*chip));
3806 if (IS_ERR(chip)) {
3807 r = PTR_ERR(chip);
1fe779f8 3808 goto out;
ff5c2c03
SL		 3809 }
3810
1fe779f8 3811 r = -ENXIO;
49df6397 3812 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3813 goto get_irqchip_out;
3814 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3815 if (r)
f0d66275 3816 goto get_irqchip_out;
1fe779f8 3817 r = -EFAULT;
f0d66275
DH		 3818 if (copy_to_user(argp, chip, sizeof *chip))
3819 goto get_irqchip_out;
1fe779f8 3820 r = 0;
f0d66275
DH		 3821 get_irqchip_out:
3822 kfree(chip);
1fe779f8
CO		 3823 break;
3824 }
3825 case KVM_SET_IRQCHIP: {
3826 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3827 struct kvm_irqchip *chip;
1fe779f8 3828
ff5c2c03
SL		 3829 chip = memdup_user(argp, sizeof(*chip));
3830 if (IS_ERR(chip)) {
3831 r = PTR_ERR(chip);
1fe779f8 3832 goto out;
ff5c2c03
SL		 3833 }
3834
1fe779f8 3835 r = -ENXIO;
49df6397 3836 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3837 goto set_irqchip_out;
3838 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3839 if (r)
f0d66275 3840 goto set_irqchip_out;
1fe779f8 3841 r = 0;
f0d66275
DH		 3842 set_irqchip_out:
3843 kfree(chip);
1fe779f8
CO		 3844 break;
3845 }
e0f63cb9 3846 case KVM_GET_PIT: {
e0f63cb9 3847 r = -EFAULT;
f0d66275 3848 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3849 goto out;
3850 r = -ENXIO;
3851 if (!kvm->arch.vpit)
3852 goto out;
f0d66275 3853 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3854 if (r)
3855 goto out;
3856 r = -EFAULT;
f0d66275 3857 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3858 goto out;
3859 r = 0;
3860 break;
3861 }
3862 case KVM_SET_PIT: {
e0f63cb9 3863 r = -EFAULT;
f0d66275 3864 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3865 goto out;
3866 r = -ENXIO;
3867 if (!kvm->arch.vpit)
3868 goto out;
f0d66275 3869 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3870 break;
3871 }
e9f42757
BK		 3872 case KVM_GET_PIT2: {
3873 r = -ENXIO;
3874 if (!kvm->arch.vpit)
3875 goto out;
3876 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3877 if (r)
3878 goto out;
3879 r = -EFAULT;
3880 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3881 goto out;
3882 r = 0;
3883 break;
3884 }
3885 case KVM_SET_PIT2: {
3886 r = -EFAULT;
3887 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3888 goto out;
3889 r = -ENXIO;
3890 if (!kvm->arch.vpit)
3891 goto out;
3892 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3893 break;
3894 }
52d939a0
MT		 3895 case KVM_REINJECT_CONTROL: {
3896 struct kvm_reinject_control control;
3897 r = -EFAULT;
3898 if (copy_from_user(&control, argp, sizeof(control)))
3899 goto out;
3900 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3901 break;
3902 }
d71ba788
PB		 3903 case KVM_SET_BOOT_CPU_ID:
3904 r = 0;
3905 mutex_lock(&kvm->lock);
3906 if (atomic_read(&kvm->online_vcpus) != 0)
3907 r = -EBUSY;
3908 else
3909 kvm->arch.bsp_vcpu_id = arg;
3910 mutex_unlock(&kvm->lock);
3911 break;
ffde22ac
ES		 3912 case KVM_XEN_HVM_CONFIG: {
3913 r = -EFAULT;
3914 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3915 sizeof(struct kvm_xen_hvm_config)))
3916 goto out;
3917 r = -EINVAL;
3918 if (kvm->arch.xen_hvm_config.flags)
3919 goto out;
3920 r = 0;
3921 break;
3922 }
afbcf7ab 3923 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3924 struct kvm_clock_data user_ns;
3925 u64 now_ns;
3926 s64 delta;
3927
3928 r = -EFAULT;
3929 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3930 goto out;
3931
3932 r = -EINVAL;
3933 if (user_ns.flags)
3934 goto out;
3935
3936 r = 0;
395c6b0a 3937 local_irq_disable();
759379dd 3938 now_ns = get_kernel_ns();
afbcf7ab 3939 delta = user_ns.clock - now_ns;
395c6b0a 3940 local_irq_enable();
afbcf7ab 3941 kvm->arch.kvmclock_offset = delta;
2e762ff7 3942 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3943 break;
3944 }
3945 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3946 struct kvm_clock_data user_ns;
3947 u64 now_ns;
3948
395c6b0a 3949 local_irq_disable();
759379dd 3950 now_ns = get_kernel_ns();
afbcf7ab 3951 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3952 local_irq_enable();
afbcf7ab 3953 user_ns.flags = 0;
97e69aa6 3954 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3955
3956 r = -EFAULT;
3957 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3958 goto out;
3959 r = 0;
3960 break;
3961 }
90de4a18
NA		 3962 case KVM_ENABLE_CAP: {
3963 struct kvm_enable_cap cap;
afbcf7ab 3964
90de4a18
NA		 3965 r = -EFAULT;
3966 if (copy_from_user(&cap, argp, sizeof(cap)))
3967 goto out;
3968 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3969 break;
3970 }
1fe779f8 3971 default:
c274e03a 3972 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 3973 }
3974out:
3975 return r;
3976}
3977
a16b043c 3978static void kvm_init_msr_list(void)
043405e1
CO		 3979{
3980 u32 dummy[2];
3981 unsigned i, j;
3982
62ef68bb 3983 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3984 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3985 continue;
93c4adc7
PB		 3986
3987 /*
3988 * Even MSRs that are valid in the host may not be exposed
3989 * to the guests in some cases. We could work around this
3990 * in VMX with the generic MSR save/load machinery, but it
3991 * is not really worthwhile since it will really only
3992 * happen with nested virtualization.
3993 */
3994 switch (msrs_to_save[i]) {
3995 case MSR_IA32_BNDCFGS:
3996 if (!kvm_x86_ops->mpx_supported())
3997 continue;
3998 break;
3999 default:
4000 break;
4001 }
4002
043405e1
CO		 4003 if (j < i)
4004 msrs_to_save[j] = msrs_to_save[i];
4005 j++;
4006 }
4007 num_msrs_to_save = j;
62ef68bb
PB		 4008
4009 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4010 switch (emulated_msrs[i]) {
6d396b55
PB		 4011 case MSR_IA32_SMBASE:
4012 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4013 continue;
4014 break;
62ef68bb
PB		 4015 default:
4016 break;
4017 }
4018
4019 if (j < i)
4020 emulated_msrs[j] = emulated_msrs[i];
4021 j++;
4022 }
4023 num_emulated_msrs = j;
043405e1
CO		 4024}
4025
bda9020e
MT		 4026static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4027 const void *v)
bbd9b64e 4028{
70252a10
AK		 4029 int handled = 0;
4030 int n;
4031
4032 do {
4033 n = min(len, 8);
4034 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4035 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4036 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4037 break;
4038 handled += n;
4039 addr += n;
4040 len -= n;
4041 v += n;
4042 } while (len);
bbd9b64e 4043
70252a10 4044 return handled;
bbd9b64e
CO		 4045}
4046
bda9020e 4047static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4048{
70252a10
AK		 4049 int handled = 0;
4050 int n;
4051
4052 do {
4053 n = min(len, 8);
4054 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4055 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4056 addr, n, v))
4057 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4058 break;
4059 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4060 handled += n;
4061 addr += n;
4062 len -= n;
4063 v += n;
4064 } while (len);
bbd9b64e 4065
70252a10 4066 return handled;
bbd9b64e
CO		 4067}
4068
2dafc6c2
GN		 4069static void kvm_set_segment(struct kvm_vcpu *vcpu,
4070 struct kvm_segment *var, int seg)
4071{
4072 kvm_x86_ops->set_segment(vcpu, var, seg);
4073}
4074
4075void kvm_get_segment(struct kvm_vcpu *vcpu,
4076 struct kvm_segment *var, int seg)
4077{
4078 kvm_x86_ops->get_segment(vcpu, var, seg);
4079}
4080
54987b7a
PB		 4081gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4082 struct x86_exception *exception)
02f59dc9
JR		 4083{
4084 gpa_t t_gpa;
02f59dc9
JR		 4085
4086 BUG_ON(!mmu_is_nested(vcpu));
4087
4088 /* NPT walks are always user-walks */
4089 access |= PFERR_USER_MASK;
54987b7a 4090 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4091
4092 return t_gpa;
4093}
4094
ab9ae313
AK		 4095gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4096 struct x86_exception *exception)
1871c602
GN		 4097{
4098 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4099 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4100}
4101
ab9ae313
AK		 4102 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4103 struct x86_exception *exception)
1871c602
GN		 4104{
4105 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4106 access |= PFERR_FETCH_MASK;
ab9ae313 4107 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4108}
4109
ab9ae313
AK		 4110gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4111 struct x86_exception *exception)
1871c602
GN		 4112{
4113 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4114 access |= PFERR_WRITE_MASK;
ab9ae313 4115 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4116}
4117
4118/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4119gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4120 struct x86_exception *exception)
1871c602 4121{
ab9ae313 4122 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4123}
4124
4125static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4126 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4127 struct x86_exception *exception)
bbd9b64e
CO		 4128{
4129 void *data = val;
10589a46 4130 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4131
4132 while (bytes) {
14dfe855 4133 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4134 exception);
bbd9b64e 4135 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4136 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4137 int ret;
4138
bcc55cba 4139 if (gpa == UNMAPPED_GVA)
ab9ae313 4140 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4141 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4142 offset, toread);
10589a46 4143 if (ret < 0) {
c3cd7ffa 4144 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4145 goto out;
4146 }
bbd9b64e 4147
77c2002e
IE		 4148 bytes -= toread;
4149 data += toread;
4150 addr += toread;
bbd9b64e 4151 }
10589a46 4152out:
10589a46 4153 return r;
bbd9b64e 4154}
77c2002e 4155
1871c602 4156/* used for instruction fetching */
0f65dd70
AK		 4157static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4158 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4159 struct x86_exception *exception)
1871c602 4160{
0f65dd70 4161 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4162 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4163 unsigned offset;
4164 int ret;
0f65dd70 4165
44583cba
PB		 4166 /* Inline kvm_read_guest_virt_helper for speed. */
4167 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4168 exception);
4169 if (unlikely(gpa == UNMAPPED_GVA))
4170 return X86EMUL_PROPAGATE_FAULT;
4171
4172 offset = addr & (PAGE_SIZE-1);
4173 if (WARN_ON(offset + bytes > PAGE_SIZE))
4174 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4175 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4176 offset, bytes);
44583cba
PB		 4177 if (unlikely(ret < 0))
4178 return X86EMUL_IO_NEEDED;
4179
4180 return X86EMUL_CONTINUE;
1871c602
GN		 4181}
4182
064aea77 4183int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4184 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4185 struct x86_exception *exception)
1871c602 4186{
0f65dd70 4187 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4188 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4189
1871c602 4190 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4191 exception);
1871c602 4192}
064aea77 4193EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4194
0f65dd70
AK		 4195static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4196 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4197 struct x86_exception *exception)
1871c602 4198{
0f65dd70 4199 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4200 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4201}
4202
7a036a6f
RK		 4203static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4204 unsigned long addr, void *val, unsigned int bytes)
4205{
4206 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4207 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4208
4209 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4210}
4211
6a4d7550 4212int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4213 gva_t addr, void *val,
2dafc6c2 4214 unsigned int bytes,
bcc55cba 4215 struct x86_exception *exception)
77c2002e 4216{
0f65dd70 4217 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4218 void *data = val;
4219 int r = X86EMUL_CONTINUE;
4220
4221 while (bytes) {
14dfe855
JR		 4222 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4223 PFERR_WRITE_MASK,
ab9ae313 4224 exception);
77c2002e
IE		 4225 unsigned offset = addr & (PAGE_SIZE-1);
4226 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4227 int ret;
4228
bcc55cba 4229 if (gpa == UNMAPPED_GVA)
ab9ae313 4230 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4231 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4232 if (ret < 0) {
c3cd7ffa 4233 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4234 goto out;
4235 }
4236
4237 bytes -= towrite;
4238 data += towrite;
4239 addr += towrite;
4240 }
4241out:
4242 return r;
4243}
6a4d7550 4244EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4245
af7cc7d1
XG		 4246static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4247 gpa_t *gpa, struct x86_exception *exception,
4248 bool write)
4249{
97d64b78
AK		 4250 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4251 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4252
97d64b78 4253 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4254 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4255 vcpu->arch.access, access)) {
bebb106a
XG		 4256 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4257 (gva & (PAGE_SIZE - 1));
4f022648 4258 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4259 return 1;
4260 }
4261
af7cc7d1
XG		 4262 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4263
4264 if (*gpa == UNMAPPED_GVA)
4265 return -1;
4266
4267 /* For APIC access vmexit */
4268 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4269 return 1;
4270
4f022648
XG		 4271 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4272 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4273 return 1;
4f022648 4274 }
bebb106a 4275
af7cc7d1
XG		 4276 return 0;
4277}
4278
3200f405 4279int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4280 const void *val, int bytes)
bbd9b64e
CO		 4281{
4282 int ret;
4283
54bf36aa 4284 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4285 if (ret < 0)
bbd9b64e 4286 return 0;
f57f2ef5 4287 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4288 return 1;
4289}
4290
77d197b2
XG		 4291struct read_write_emulator_ops {
4292 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4293 int bytes);
4294 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4295 void *val, int bytes);
4296 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4297 int bytes, void *val);
4298 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4299 void *val, int bytes);
4300 bool write;
4301};
4302
4303static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4304{
4305 if (vcpu->mmio_read_completed) {
77d197b2 4306 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4307 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4308 vcpu->mmio_read_completed = 0;
4309 return 1;
4310 }
4311
4312 return 0;
4313}
4314
4315static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4316 void *val, int bytes)
4317{
54bf36aa 4318 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4319}
4320
4321static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4322 void *val, int bytes)
4323{
4324 return emulator_write_phys(vcpu, gpa, val, bytes);
4325}
4326
4327static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4328{
4329 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4330 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4331}
4332
4333static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4334 void *val, int bytes)
4335{
4336 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4337 return X86EMUL_IO_NEEDED;
4338}
4339
4340static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4341 void *val, int bytes)
4342{
f78146b0
AK		 4343 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4344
87da7e66 4345 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4346 return X86EMUL_CONTINUE;
4347}
4348
0fbe9b0b 4349static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4350 .read_write_prepare = read_prepare,
4351 .read_write_emulate = read_emulate,
4352 .read_write_mmio = vcpu_mmio_read,
4353 .read_write_exit_mmio = read_exit_mmio,
4354};
4355
0fbe9b0b 4356static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4357 .read_write_emulate = write_emulate,
4358 .read_write_mmio = write_mmio,
4359 .read_write_exit_mmio = write_exit_mmio,
4360 .write = true,
4361};
4362
22388a3c
XG		 4363static int emulator_read_write_onepage(unsigned long addr, void *val,
4364 unsigned int bytes,
4365 struct x86_exception *exception,
4366 struct kvm_vcpu *vcpu,
0fbe9b0b 4367 const struct read_write_emulator_ops *ops)
bbd9b64e 4368{
af7cc7d1
XG		 4369 gpa_t gpa;
4370 int handled, ret;
22388a3c 4371 bool write = ops->write;
f78146b0 4372 struct kvm_mmio_fragment *frag;
10589a46 4373
22388a3c 4374 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4375
af7cc7d1 4376 if (ret < 0)
bbd9b64e 4377 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4378
4379 /* For APIC access vmexit */
af7cc7d1 4380 if (ret)
bbd9b64e
CO		 4381 goto mmio;
4382
22388a3c 4383 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4384 return X86EMUL_CONTINUE;
4385
4386mmio:
4387 /*
4388 * Is this MMIO handled locally?
4389 */
22388a3c 4390 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4391 if (handled == bytes)
bbd9b64e 4392 return X86EMUL_CONTINUE;
bbd9b64e 4393
70252a10
AK		 4394 gpa += handled;
4395 bytes -= handled;
4396 val += handled;
4397
87da7e66
XG		 4398 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4399 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4400 frag->gpa = gpa;
4401 frag->data = val;
4402 frag->len = bytes;
f78146b0 4403 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4404}
4405
52eb5a6d
XL		 4406static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4407 unsigned long addr,
22388a3c
XG		 4408 void *val, unsigned int bytes,
4409 struct x86_exception *exception,
0fbe9b0b 4410 const struct read_write_emulator_ops *ops)
bbd9b64e 4411{
0f65dd70 4412 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4413 gpa_t gpa;
4414 int rc;
4415
4416 if (ops->read_write_prepare &&
4417 ops->read_write_prepare(vcpu, val, bytes))
4418 return X86EMUL_CONTINUE;
4419
4420 vcpu->mmio_nr_fragments = 0;
0f65dd70 4421
bbd9b64e
CO		 4422 /* Crossing a page boundary? */
4423 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4424 int now;
bbd9b64e
CO		 4425
4426 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4427 rc = emulator_read_write_onepage(addr, val, now, exception,
4428 vcpu, ops);
4429
bbd9b64e
CO		 4430 if (rc != X86EMUL_CONTINUE)
4431 return rc;
4432 addr += now;
bac15531
NA		 4433 if (ctxt->mode != X86EMUL_MODE_PROT64)
4434 addr = (u32)addr;
bbd9b64e
CO		 4435 val += now;
4436 bytes -= now;
4437 }
22388a3c 4438
f78146b0
AK		 4439 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4440 vcpu, ops);
4441 if (rc != X86EMUL_CONTINUE)
4442 return rc;
4443
4444 if (!vcpu->mmio_nr_fragments)
4445 return rc;
4446
4447 gpa = vcpu->mmio_fragments[0].gpa;
4448
4449 vcpu->mmio_needed = 1;
4450 vcpu->mmio_cur_fragment = 0;
4451
87da7e66 4452 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4453 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4454 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4455 vcpu->run->mmio.phys_addr = gpa;
4456
4457 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4458}
4459
4460static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4461 unsigned long addr,
4462 void *val,
4463 unsigned int bytes,
4464 struct x86_exception *exception)
4465{
4466 return emulator_read_write(ctxt, addr, val, bytes,
4467 exception, &read_emultor);
4468}
4469
52eb5a6d 4470static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4471 unsigned long addr,
4472 const void *val,
4473 unsigned int bytes,
4474 struct x86_exception *exception)
4475{
4476 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4477 exception, &write_emultor);
bbd9b64e 4478}
bbd9b64e 4479
daea3e73
AK		 4480#define CMPXCHG_TYPE(t, ptr, old, new) \
4481 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4482
4483#ifdef CONFIG_X86_64
4484# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4485#else
4486# define CMPXCHG64(ptr, old, new) \
9749a6c0 4487 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4488#endif
4489
0f65dd70
AK		 4490static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4491 unsigned long addr,
bbd9b64e
CO		 4492 const void *old,
4493 const void *new,
4494 unsigned int bytes,
0f65dd70 4495 struct x86_exception *exception)
bbd9b64e 4496{
0f65dd70 4497 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4498 gpa_t gpa;
4499 struct page *page;
4500 char *kaddr;
4501 bool exchanged;
2bacc55c 4502
daea3e73
AK		 4503 /* guests cmpxchg8b have to be emulated atomically */
4504 if (bytes > 8 || (bytes & (bytes - 1)))
4505 goto emul_write;
10589a46 4506
daea3e73 4507 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4508
daea3e73
AK		 4509 if (gpa == UNMAPPED_GVA ||
4510 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4511 goto emul_write;
2bacc55c 4512
daea3e73
AK		 4513 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4514 goto emul_write;
72dc67a6 4515
54bf36aa 4516 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4517 if (is_error_page(page))
c19b8bd6 4518 goto emul_write;
72dc67a6 4519
8fd75e12 4520 kaddr = kmap_atomic(page);
daea3e73
AK		 4521 kaddr += offset_in_page(gpa);
4522 switch (bytes) {
4523 case 1:
4524 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4525 break;
4526 case 2:
4527 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4528 break;
4529 case 4:
4530 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4531 break;
4532 case 8:
4533 exchanged = CMPXCHG64(kaddr, old, new);
4534 break;
4535 default:
4536 BUG();
2bacc55c 4537 }
8fd75e12 4538 kunmap_atomic(kaddr);
daea3e73
AK		 4539 kvm_release_page_dirty(page);
4540
4541 if (!exchanged)
4542 return X86EMUL_CMPXCHG_FAILED;
4543
54bf36aa 4544 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4545 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4546
4547 return X86EMUL_CONTINUE;
4a5f48f6 4548
3200f405 4549emul_write:
daea3e73 4550 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4551
0f65dd70 4552 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4553}
4554
cf8f70bf
GN		 4555static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4556{
4557 /* TODO: String I/O for in kernel device */
4558 int r;
4559
4560 if (vcpu->arch.pio.in)
e32edf4f 4561 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4562 vcpu->arch.pio.size, pd);
4563 else
e32edf4f 4564 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4565 vcpu->arch.pio.port, vcpu->arch.pio.size,
4566 pd);
4567 return r;
4568}
4569
6f6fbe98
XG		 4570static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4571 unsigned short port, void *val,
4572 unsigned int count, bool in)
cf8f70bf 4573{
cf8f70bf 4574 vcpu->arch.pio.port = port;
6f6fbe98 4575 vcpu->arch.pio.in = in;
7972995b 4576 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4577 vcpu->arch.pio.size = size;
4578
4579 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4580 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4581 return 1;
4582 }
4583
4584 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4585 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4586 vcpu->run->io.size = size;
4587 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4588 vcpu->run->io.count = count;
4589 vcpu->run->io.port = port;
4590
4591 return 0;
4592}
4593
6f6fbe98
XG		 4594static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4595 int size, unsigned short port, void *val,
4596 unsigned int count)
cf8f70bf 4597{
ca1d4a9e 4598 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4599 int ret;
ca1d4a9e 4600
6f6fbe98
XG		 4601 if (vcpu->arch.pio.count)
4602 goto data_avail;
cf8f70bf 4603
6f6fbe98
XG		 4604 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4605 if (ret) {
4606data_avail:
4607 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4608 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4609 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4610 return 1;
4611 }
4612
cf8f70bf
GN		 4613 return 0;
4614}
4615
6f6fbe98
XG		 4616static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4617 int size, unsigned short port,
4618 const void *val, unsigned int count)
4619{
4620 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4621
4622 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4623 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4624 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4625}
4626
bbd9b64e
CO		 4627static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4628{
4629 return kvm_x86_ops->get_segment_base(vcpu, seg);
4630}
4631
3cb16fe7 4632static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4633{
3cb16fe7 4634 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4635}
4636
5cb56059 4637int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4638{
4639 if (!need_emulate_wbinvd(vcpu))
4640 return X86EMUL_CONTINUE;
4641
4642 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4643 int cpu = get_cpu();
4644
4645 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4646 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4647 wbinvd_ipi, NULL, 1);
2eec7343 4648 put_cpu();
f5f48ee1 4649 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4650 } else
4651 wbinvd();
f5f48ee1
SY		 4652 return X86EMUL_CONTINUE;
4653}
5cb56059
JS		 4654
4655int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4656{
4657 kvm_x86_ops->skip_emulated_instruction(vcpu);
4658 return kvm_emulate_wbinvd_noskip(vcpu);
4659}
f5f48ee1
SY		 4660EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4661
5cb56059
JS		 4662
4663
bcaf5cc5
AK		 4664static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4665{
5cb56059 4666 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4667}
4668
52eb5a6d
XL		 4669static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4670 unsigned long *dest)
bbd9b64e 4671{
16f8a6f9 4672 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4673}
4674
52eb5a6d
XL		 4675static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4676 unsigned long value)
bbd9b64e 4677{
338dbc97 4678
717746e3 4679 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4680}
4681
52a46617 4682static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4683{
52a46617 4684 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4685}
4686
717746e3 4687static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4688{
717746e3 4689 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4690 unsigned long value;
4691
4692 switch (cr) {
4693 case 0:
4694 value = kvm_read_cr0(vcpu);
4695 break;
4696 case 2:
4697 value = vcpu->arch.cr2;
4698 break;
4699 case 3:
9f8fe504 4700 value = kvm_read_cr3(vcpu);
52a46617
GN		 4701 break;
4702 case 4:
4703 value = kvm_read_cr4(vcpu);
4704 break;
4705 case 8:
4706 value = kvm_get_cr8(vcpu);
4707 break;
4708 default:
a737f256 4709 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4710 return 0;
4711 }
4712
4713 return value;
4714}
4715
717746e3 4716static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4717{
717746e3 4718 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4719 int res = 0;
4720
52a46617
GN		 4721 switch (cr) {
4722 case 0:
49a9b07e 4723 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4724 break;
4725 case 2:
4726 vcpu->arch.cr2 = val;
4727 break;
4728 case 3:
2390218b 4729 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4730 break;
4731 case 4:
a83b29c6 4732 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4733 break;
4734 case 8:
eea1cff9 4735 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4736 break;
4737 default:
a737f256 4738 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4739 res = -1;
52a46617 4740 }
0f12244f
GN		 4741
4742 return res;
52a46617
GN		 4743}
4744
717746e3 4745static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4746{
717746e3 4747 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4748}
4749
4bff1e86 4750static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4751{
4bff1e86 4752 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4753}
4754
4bff1e86 4755static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4756{
4bff1e86 4757 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4758}
4759
1ac9d0cf
AK		 4760static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4761{
4762 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4763}
4764
4765static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4766{
4767 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4768}
4769
4bff1e86
AK		 4770static unsigned long emulator_get_cached_segment_base(
4771 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4772{
4bff1e86 4773 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4774}
4775
1aa36616
AK		 4776static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4777 struct desc_struct *desc, u32 *base3,
4778 int seg)
2dafc6c2
GN		 4779{
4780 struct kvm_segment var;
4781
4bff1e86 4782 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4783 *selector = var.selector;
2dafc6c2 4784
378a8b09
GN		 4785 if (var.unusable) {
4786 memset(desc, 0, sizeof(*desc));
2dafc6c2 4787 return false;
378a8b09 4788 }
2dafc6c2
GN		 4789
4790 if (var.g)
4791 var.limit >>= 12;
4792 set_desc_limit(desc, var.limit);
4793 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4794#ifdef CONFIG_X86_64
4795 if (base3)
4796 *base3 = var.base >> 32;
4797#endif
2dafc6c2
GN		 4798 desc->type = var.type;
4799 desc->s = var.s;
4800 desc->dpl = var.dpl;
4801 desc->p = var.present;
4802 desc->avl = var.avl;
4803 desc->l = var.l;
4804 desc->d = var.db;
4805 desc->g = var.g;
4806
4807 return true;
4808}
4809
1aa36616
AK		 4810static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4811 struct desc_struct *desc, u32 base3,
4812 int seg)
2dafc6c2 4813{
4bff1e86 4814 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4815 struct kvm_segment var;
4816
1aa36616 4817 var.selector = selector;
2dafc6c2 4818 var.base = get_desc_base(desc);
5601d05b
GN		 4819#ifdef CONFIG_X86_64
4820 var.base |= ((u64)base3) << 32;
4821#endif
2dafc6c2
GN		 4822 var.limit = get_desc_limit(desc);
4823 if (desc->g)
4824 var.limit = (var.limit << 12) | 0xfff;
4825 var.type = desc->type;
2dafc6c2
GN		 4826 var.dpl = desc->dpl;
4827 var.db = desc->d;
4828 var.s = desc->s;
4829 var.l = desc->l;
4830 var.g = desc->g;
4831 var.avl = desc->avl;
4832 var.present = desc->p;
4833 var.unusable = !var.present;
4834 var.padding = 0;
4835
4836 kvm_set_segment(vcpu, &var, seg);
4837 return;
4838}
4839
717746e3
AK		 4840static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4841 u32 msr_index, u64 *pdata)
4842{
609e36d3
PB		 4843 struct msr_data msr;
4844 int r;
4845
4846 msr.index = msr_index;
4847 msr.host_initiated = false;
4848 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4849 if (r)
4850 return r;
4851
4852 *pdata = msr.data;
4853 return 0;
717746e3
AK		 4854}
4855
4856static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4857 u32 msr_index, u64 data)
4858{
8fe8ab46
WA		 4859 struct msr_data msr;
4860
4861 msr.data = data;
4862 msr.index = msr_index;
4863 msr.host_initiated = false;
4864 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4865}
4866
64d60670
PB		 4867static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4868{
4869 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4870
4871 return vcpu->arch.smbase;
4872}
4873
4874static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4875{
4876 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4877
4878 vcpu->arch.smbase = smbase;
4879}
4880
67f4d428
NA		 4881static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4882 u32 pmc)
4883{
c6702c9d 4884 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4885}
4886
222d21aa
AK		 4887static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4888 u32 pmc, u64 *pdata)
4889{
c6702c9d 4890 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4891}
4892
6c3287f7
AK		 4893static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4894{
4895 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4896}
4897
5037f6f3
AK		 4898static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4899{
4900 preempt_disable();
5197b808 4901 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4902 /*
4903 * CR0.TS may reference the host fpu state, not the guest fpu state,
4904 * so it may be clear at this point.
4905 */
4906 clts();
4907}
4908
4909static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4910{
4911 preempt_enable();
4912}
4913
2953538e 4914static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4915 struct x86_instruction_info *info,
c4f035c6
AK		 4916 enum x86_intercept_stage stage)
4917{
2953538e 4918 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4919}
4920
0017f93a 4921static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4922 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4923{
0017f93a 4924 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4925}
4926
dd856efa
AK		 4927static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4928{
4929 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4930}
4931
4932static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4933{
4934 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4935}
4936
801806d9
NA		 4937static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4938{
4939 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4940}
4941
0225fb50 4942static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4943 .read_gpr = emulator_read_gpr,
4944 .write_gpr = emulator_write_gpr,
1871c602 4945 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4946 .write_std = kvm_write_guest_virt_system,
7a036a6f 4947 .read_phys = kvm_read_guest_phys_system,
1871c602 4948 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4949 .read_emulated = emulator_read_emulated,
4950 .write_emulated = emulator_write_emulated,
4951 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4952 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4953 .pio_in_emulated = emulator_pio_in_emulated,
4954 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4955 .get_segment = emulator_get_segment,
4956 .set_segment = emulator_set_segment,
5951c442 4957 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4958 .get_gdt = emulator_get_gdt,
160ce1f1 4959 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4960 .set_gdt = emulator_set_gdt,
4961 .set_idt = emulator_set_idt,
52a46617
GN		 4962 .get_cr = emulator_get_cr,
4963 .set_cr = emulator_set_cr,
9c537244 4964 .cpl = emulator_get_cpl,
35aa5375
GN		 4965 .get_dr = emulator_get_dr,
4966 .set_dr = emulator_set_dr,
64d60670
PB		 4967 .get_smbase = emulator_get_smbase,
4968 .set_smbase = emulator_set_smbase,
717746e3
AK		 4969 .set_msr = emulator_set_msr,
4970 .get_msr = emulator_get_msr,
67f4d428 4971 .check_pmc = emulator_check_pmc,
222d21aa 4972 .read_pmc = emulator_read_pmc,
6c3287f7 4973 .halt = emulator_halt,
bcaf5cc5 4974 .wbinvd = emulator_wbinvd,
d6aa1000 4975 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4976 .get_fpu = emulator_get_fpu,
4977 .put_fpu = emulator_put_fpu,
c4f035c6 4978 .intercept = emulator_intercept,
bdb42f5a 4979 .get_cpuid = emulator_get_cpuid,
801806d9 4980 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 4981};
4982
95cb2295
GN		 4983static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4984{
37ccdcbe 4985 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4986 /*
4987 * an sti; sti; sequence only disable interrupts for the first
4988 * instruction. So, if the last instruction, be it emulated or
4989 * not, left the system with the INT_STI flag enabled, it
4990 * means that the last instruction is an sti. We should not
4991 * leave the flag on in this case. The same goes for mov ss
4992 */
37ccdcbe
PB		 4993 if (int_shadow & mask)
4994 mask = 0;
6addfc42 4995 if (unlikely(int_shadow || mask)) {
95cb2295 4996 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4997 if (!mask)
4998 kvm_make_request(KVM_REQ_EVENT, vcpu);
4999 }
95cb2295
GN		 5000}
5001
ef54bcfe 5002static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5003{
5004 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5005 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5006 return kvm_propagate_fault(vcpu, &ctxt->exception);
5007
5008 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5009 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5010 ctxt->exception.error_code);
54b8486f 5011 else
da9cb575 5012 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5013 return false;
54b8486f
GN		 5014}
5015
8ec4722d
MG		 5016static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5017{
adf52235 5018 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5019 int cs_db, cs_l;
5020
8ec4722d
MG		 5021 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5022
adf52235
TY		 5023 ctxt->eflags = kvm_get_rflags(vcpu);
5024 ctxt->eip = kvm_rip_read(vcpu);
5025 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5026 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5027 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5028 cs_db ? X86EMUL_MODE_PROT32 :
5029 X86EMUL_MODE_PROT16;
a584539b 5030 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5031 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5032 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5033 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5034
dd856efa 5035 init_decode_cache(ctxt);
7ae441ea 5036 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5037}
5038
71f9833b 5039int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5040{
9d74191a 5041 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5042 int ret;
5043
5044 init_emulate_ctxt(vcpu);
5045
9dac77fa
AK		 5046 ctxt->op_bytes = 2;
5047 ctxt->ad_bytes = 2;
5048 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5049 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5050
5051 if (ret != X86EMUL_CONTINUE)
5052 return EMULATE_FAIL;
5053
9dac77fa 5054 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5055 kvm_rip_write(vcpu, ctxt->eip);
5056 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5057
5058 if (irq == NMI_VECTOR)
7460fb4a 5059 vcpu->arch.nmi_pending = 0;
63995653
MG		 5060 else
5061 vcpu->arch.interrupt.pending = false;
5062
5063 return EMULATE_DONE;
5064}
5065EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5066
6d77dbfc
GN		 5067static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5068{
fc3a9157
JR		 5069 int r = EMULATE_DONE;
5070
6d77dbfc
GN		 5071 ++vcpu->stat.insn_emulation_fail;
5072 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5073 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5074 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5075 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5076 vcpu->run->internal.ndata = 0;
5077 r = EMULATE_FAIL;
5078 }
6d77dbfc 5079 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5080
5081 return r;
6d77dbfc
GN		 5082}
5083
93c05d3e 5084static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5085 bool write_fault_to_shadow_pgtable,
5086 int emulation_type)
a6f177ef 5087{
95b3cf69 5088 gpa_t gpa = cr2;
8e3d9d06 5089 pfn_t pfn;
a6f177ef 5090
991eebf9
GN		 5091 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5092 return false;
5093
95b3cf69
XG		 5094 if (!vcpu->arch.mmu.direct_map) {
5095 /*
5096 * Write permission should be allowed since only
5097 * write access need to be emulated.
5098 */
5099 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5100
95b3cf69
XG		 5101 /*
5102 * If the mapping is invalid in guest, let cpu retry
5103 * it to generate fault.
5104 */
5105 if (gpa == UNMAPPED_GVA)
5106 return true;
5107 }
a6f177ef 5108
8e3d9d06
XG		 5109 /*
5110 * Do not retry the unhandleable instruction if it faults on the
5111 * readonly host memory, otherwise it will goto a infinite loop:
5112 * retry instruction -> write #PF -> emulation fail -> retry
5113 * instruction -> ...
5114 */
5115 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5116
5117 /*
5118 * If the instruction failed on the error pfn, it can not be fixed,
5119 * report the error to userspace.
5120 */
5121 if (is_error_noslot_pfn(pfn))
5122 return false;
5123
5124 kvm_release_pfn_clean(pfn);
5125
5126 /* The instructions are well-emulated on direct mmu. */
5127 if (vcpu->arch.mmu.direct_map) {
5128 unsigned int indirect_shadow_pages;
5129
5130 spin_lock(&vcpu->kvm->mmu_lock);
5131 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5132 spin_unlock(&vcpu->kvm->mmu_lock);
5133
5134 if (indirect_shadow_pages)
5135 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5136
a6f177ef 5137 return true;
8e3d9d06 5138 }
a6f177ef 5139
95b3cf69
XG		 5140 /*
5141 * if emulation was due to access to shadowed page table
5142 * and it failed try to unshadow page and re-enter the
5143 * guest to let CPU execute the instruction.
5144 */
5145 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5146
5147 /*
5148 * If the access faults on its page table, it can not
5149 * be fixed by unprotecting shadow page and it should
5150 * be reported to userspace.
5151 */
5152 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5153}
5154
1cb3f3ae
XG		 5155static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5156 unsigned long cr2, int emulation_type)
5157{
5158 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5159 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5160
5161 last_retry_eip = vcpu->arch.last_retry_eip;
5162 last_retry_addr = vcpu->arch.last_retry_addr;
5163
5164 /*
5165 * If the emulation is caused by #PF and it is non-page_table
5166 * writing instruction, it means the VM-EXIT is caused by shadow
5167 * page protected, we can zap the shadow page and retry this
5168 * instruction directly.
5169 *
5170 * Note: if the guest uses a non-page-table modifying instruction
5171 * on the PDE that points to the instruction, then we will unmap
5172 * the instruction and go to an infinite loop. So, we cache the
5173 * last retried eip and the last fault address, if we meet the eip
5174 * and the address again, we can break out of the potential infinite
5175 * loop.
5176 */
5177 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5178
5179 if (!(emulation_type & EMULTYPE_RETRY))
5180 return false;
5181
5182 if (x86_page_table_writing_insn(ctxt))
5183 return false;
5184
5185 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5186 return false;
5187
5188 vcpu->arch.last_retry_eip = ctxt->eip;
5189 vcpu->arch.last_retry_addr = cr2;
5190
5191 if (!vcpu->arch.mmu.direct_map)
5192 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5193
22368028 5194 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5195
5196 return true;
5197}
5198
716d51ab
GN		 5199static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5200static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5201
64d60670 5202static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5203{
64d60670 5204 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5205 /* This is a good place to trace that we are exiting SMM. */
5206 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5207
64d60670
PB		 5208 if (unlikely(vcpu->arch.smi_pending)) {
5209 kvm_make_request(KVM_REQ_SMI, vcpu);
5210 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5211 } else {
5212 /* Process a latched INIT, if any. */
5213 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5214 }
5215 }
699023e2
PB		 5216
5217 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5218}
5219
5220static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5221{
5222 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5223
a584539b 5224 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5225
5226 if (changed & HF_SMM_MASK)
5227 kvm_smm_changed(vcpu);
a584539b
PB		 5228}
5229
4a1e10d5
PB		 5230static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5231 unsigned long *db)
5232{
5233 u32 dr6 = 0;
5234 int i;
5235 u32 enable, rwlen;
5236
5237 enable = dr7;
5238 rwlen = dr7 >> 16;
5239 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5240 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5241 dr6 |= (1 << i);
5242 return dr6;
5243}
5244
6addfc42 5245static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5246{
5247 struct kvm_run *kvm_run = vcpu->run;
5248
5249 /*
6addfc42
PB		 5250 * rflags is the old, "raw" value of the flags. The new value has
5251 * not been saved yet.
663f4c61
PB		 5252 *
5253 * This is correct even for TF set by the guest, because "the
5254 * processor will not generate this exception after the instruction
5255 * that sets the TF flag".
5256 */
663f4c61
PB		 5257 if (unlikely(rflags & X86_EFLAGS_TF)) {
5258 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5259 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5260 DR6_RTM;
663f4c61
PB		 5261 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5262 kvm_run->debug.arch.exception = DB_VECTOR;
5263 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5264 *r = EMULATE_USER_EXIT;
5265 } else {
5266 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5267 /*
5268 * "Certain debug exceptions may clear bit 0-3. The
5269 * remaining contents of the DR6 register are never
5270 * cleared by the processor".
5271 */
5272 vcpu->arch.dr6 &= ~15;
6f43ed01 5273 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5274 kvm_queue_exception(vcpu, DB_VECTOR);
5275 }
5276 }
5277}
5278
4a1e10d5
PB		 5279static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5280{
4a1e10d5
PB		 5281 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5282 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5283 struct kvm_run *kvm_run = vcpu->run;
5284 unsigned long eip = kvm_get_linear_rip(vcpu);
5285 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5286 vcpu->arch.guest_debug_dr7,
5287 vcpu->arch.eff_db);
5288
5289 if (dr6 != 0) {
6f43ed01 5290 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5291 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5292 kvm_run->debug.arch.exception = DB_VECTOR;
5293 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5294 *r = EMULATE_USER_EXIT;
5295 return true;
5296 }
5297 }
5298
4161a569
NA		 5299 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5300 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5301 unsigned long eip = kvm_get_linear_rip(vcpu);
5302 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5303 vcpu->arch.dr7,
5304 vcpu->arch.db);
5305
5306 if (dr6 != 0) {
5307 vcpu->arch.dr6 &= ~15;
6f43ed01 5308 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5309 kvm_queue_exception(vcpu, DB_VECTOR);
5310 *r = EMULATE_DONE;
5311 return true;
5312 }
5313 }
5314
5315 return false;
5316}
5317
51d8b661
AP		 5318int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5319 unsigned long cr2,
dc25e89e
AP		 5320 int emulation_type,
5321 void *insn,
5322 int insn_len)
bbd9b64e 5323{
95cb2295 5324 int r;
9d74191a 5325 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5326 bool writeback = true;
93c05d3e 5327 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5328
93c05d3e
XG		 5329 /*
5330 * Clear write_fault_to_shadow_pgtable here to ensure it is
5331 * never reused.
5332 */
5333 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5334 kvm_clear_exception_queue(vcpu);
8d7d8102 5335
571008da 5336 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5337 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5338
5339 /*
5340 * We will reenter on the same instruction since
5341 * we do not set complete_userspace_io. This does not
5342 * handle watchpoints yet, those would be handled in
5343 * the emulate_ops.
5344 */
5345 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5346 return r;
5347
9d74191a
TY		 5348 ctxt->interruptibility = 0;
5349 ctxt->have_exception = false;
e0ad0b47 5350 ctxt->exception.vector = -1;
9d74191a 5351 ctxt->perm_ok = false;
bbd9b64e 5352
b51e974f 5353 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5354
9d74191a 5355 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5356
e46479f8 5357 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5358 ++vcpu->stat.insn_emulation;
1d2887e2 5359 if (r != EMULATION_OK) {
4005996e
AK		 5360 if (emulation_type & EMULTYPE_TRAP_UD)
5361 return EMULATE_FAIL;
991eebf9
GN		 5362 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5363 emulation_type))
bbd9b64e 5364 return EMULATE_DONE;
6d77dbfc
GN		 5365 if (emulation_type & EMULTYPE_SKIP)
5366 return EMULATE_FAIL;
5367 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5368 }
5369 }
5370
ba8afb6b 5371 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5372 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5373 if (ctxt->eflags & X86_EFLAGS_RF)
5374 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5375 return EMULATE_DONE;
5376 }
5377
1cb3f3ae
XG		 5378 if (retry_instruction(ctxt, cr2, emulation_type))
5379 return EMULATE_DONE;
5380
7ae441ea 5381 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5382 changes registers values during IO operation */
7ae441ea
GN		 5383 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5384 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5385 emulator_invalidate_register_cache(ctxt);
7ae441ea 5386 }
4d2179e1 5387
5cd21917 5388restart:
9d74191a 5389 r = x86_emulate_insn(ctxt);
bbd9b64e 5390
775fde86
JR		 5391 if (r == EMULATION_INTERCEPTED)
5392 return EMULATE_DONE;
5393
d2ddd1c4 5394 if (r == EMULATION_FAILED) {
991eebf9
GN		 5395 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5396 emulation_type))
c3cd7ffa
GN		 5397 return EMULATE_DONE;
5398
6d77dbfc 5399 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5400 }
5401
9d74191a 5402 if (ctxt->have_exception) {
d2ddd1c4 5403 r = EMULATE_DONE;
ef54bcfe
PB		 5404 if (inject_emulated_exception(vcpu))
5405 return r;
d2ddd1c4 5406 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5407 if (!vcpu->arch.pio.in) {
5408 /* FIXME: return into emulator if single-stepping. */
3457e419 5409 vcpu->arch.pio.count = 0;
0912c977 5410 } else {
7ae441ea 5411 writeback = false;
716d51ab
GN		 5412 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5413 }
ac0a48c3 5414 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5415 } else if (vcpu->mmio_needed) {
5416 if (!vcpu->mmio_is_write)
5417 writeback = false;
ac0a48c3 5418 r = EMULATE_USER_EXIT;
716d51ab 5419 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5420 } else if (r == EMULATION_RESTART)
5cd21917 5421 goto restart;
d2ddd1c4
GN		 5422 else
5423 r = EMULATE_DONE;
f850e2e6 5424
7ae441ea 5425 if (writeback) {
6addfc42 5426 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5427 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5428 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5429 if (vcpu->arch.hflags != ctxt->emul_flags)
5430 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5431 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5432 if (r == EMULATE_DONE)
6addfc42 5433 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5434 if (!ctxt->have_exception ||
5435 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5436 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5437
5438 /*
5439 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5440 * do nothing, and it will be requested again as soon as
5441 * the shadow expires. But we still need to check here,
5442 * because POPF has no interrupt shadow.
5443 */
5444 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5445 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5446 } else
5447 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5448
5449 return r;
de7d789a 5450}
51d8b661 5451EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5452
cf8f70bf 5453int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5454{
cf8f70bf 5455 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5456 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5457 size, port, &val, 1);
cf8f70bf 5458 /* do not return to emulator after return from userspace */
7972995b 5459 vcpu->arch.pio.count = 0;
de7d789a
CO		 5460 return ret;
5461}
cf8f70bf 5462EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5463
8cfdc000
ZA		 5464static void tsc_bad(void *info)
5465{
0a3aee0d 5466 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5467}
5468
5469static void tsc_khz_changed(void *data)
c8076604 5470{
8cfdc000
ZA		 5471 struct cpufreq_freqs *freq = data;
5472 unsigned long khz = 0;
5473
5474 if (data)
5475 khz = freq->new;
5476 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5477 khz = cpufreq_quick_get(raw_smp_processor_id());
5478 if (!khz)
5479 khz = tsc_khz;
0a3aee0d 5480 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5481}
5482
c8076604
GH		 5483static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5484 void *data)
5485{
5486 struct cpufreq_freqs *freq = data;
5487 struct kvm *kvm;
5488 struct kvm_vcpu *vcpu;
5489 int i, send_ipi = 0;
5490
8cfdc000
ZA		 5491 /*
5492 * We allow guests to temporarily run on slowing clocks,
5493 * provided we notify them after, or to run on accelerating
5494 * clocks, provided we notify them before. Thus time never
5495 * goes backwards.
5496 *
5497 * However, we have a problem. We can't atomically update
5498 * the frequency of a given CPU from this function; it is
5499 * merely a notifier, which can be called from any CPU.
5500 * Changing the TSC frequency at arbitrary points in time
5501 * requires a recomputation of local variables related to
5502 * the TSC for each VCPU. We must flag these local variables
5503 * to be updated and be sure the update takes place with the
5504 * new frequency before any guests proceed.
5505 *
5506 * Unfortunately, the combination of hotplug CPU and frequency
5507 * change creates an intractable locking scenario; the order
5508 * of when these callouts happen is undefined with respect to
5509 * CPU hotplug, and they can race with each other. As such,
5510 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5511 * undefined; you can actually have a CPU frequency change take
5512 * place in between the computation of X and the setting of the
5513 * variable. To protect against this problem, all updates of
5514 * the per_cpu tsc_khz variable are done in an interrupt
5515 * protected IPI, and all callers wishing to update the value
5516 * must wait for a synchronous IPI to complete (which is trivial
5517 * if the caller is on the CPU already). This establishes the
5518 * necessary total order on variable updates.
5519 *
5520 * Note that because a guest time update may take place
5521 * anytime after the setting of the VCPU's request bit, the
5522 * correct TSC value must be set before the request. However,
5523 * to ensure the update actually makes it to any guest which
5524 * starts running in hardware virtualization between the set
5525 * and the acquisition of the spinlock, we must also ping the
5526 * CPU after setting the request bit.
5527 *
5528 */
5529
c8076604
GH		 5530 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5531 return 0;
5532 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5533 return 0;
8cfdc000
ZA		 5534
5535 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5536
2f303b74 5537 spin_lock(&kvm_lock);
c8076604 5538 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5539 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5540 if (vcpu->cpu != freq->cpu)
5541 continue;
c285545f 5542 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5543 if (vcpu->cpu != smp_processor_id())
8cfdc000 5544 send_ipi = 1;
c8076604
GH		 5545 }
5546 }
2f303b74 5547 spin_unlock(&kvm_lock);
c8076604
GH		 5548
5549 if (freq->old < freq->new && send_ipi) {
5550 /*
5551 * We upscale the frequency. Must make the guest
5552 * doesn't see old kvmclock values while running with
5553 * the new frequency, otherwise we risk the guest sees
5554 * time go backwards.
5555 *
5556 * In case we update the frequency for another cpu
5557 * (which might be in guest context) send an interrupt
5558 * to kick the cpu out of guest context. Next time
5559 * guest context is entered kvmclock will be updated,
5560 * so the guest will not see stale values.
5561 */
8cfdc000 5562 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5563 }
5564 return 0;
5565}
5566
5567static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5568 .notifier_call = kvmclock_cpufreq_notifier
5569};
5570
5571static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5572 unsigned long action, void *hcpu)
5573{
5574 unsigned int cpu = (unsigned long)hcpu;
5575
5576 switch (action) {
5577 case CPU_ONLINE:
5578 case CPU_DOWN_FAILED:
5579 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5580 break;
5581 case CPU_DOWN_PREPARE:
5582 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5583 break;
5584 }
5585 return NOTIFY_OK;
5586}
5587
5588static struct notifier_block kvmclock_cpu_notifier_block = {
5589 .notifier_call = kvmclock_cpu_notifier,
5590 .priority = -INT_MAX
c8076604
GH		 5591};
5592
b820cc0c
ZA		 5593static void kvm_timer_init(void)
5594{
5595 int cpu;
5596
c285545f 5597 max_tsc_khz = tsc_khz;
460dd42e
SB		 5598
5599 cpu_notifier_register_begin();
b820cc0c 5600 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5601#ifdef CONFIG_CPU_FREQ
5602 struct cpufreq_policy policy;
5603 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5604 cpu = get_cpu();
5605 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5606 if (policy.cpuinfo.max_freq)
5607 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5608 put_cpu();
c285545f 5609#endif
b820cc0c
ZA		 5610 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5611 CPUFREQ_TRANSITION_NOTIFIER);
5612 }
c285545f 5613 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5614 for_each_online_cpu(cpu)
5615 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5616
5617 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5618 cpu_notifier_register_done();
5619
b820cc0c
ZA		 5620}
5621
ff9d07a0
ZY		 5622static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5623
f5132b01 5624int kvm_is_in_guest(void)
ff9d07a0 5625{
086c9855 5626 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5627}
5628
5629static int kvm_is_user_mode(void)
5630{
5631 int user_mode = 3;
dcf46b94 5632
086c9855
AS		 5633 if (__this_cpu_read(current_vcpu))
5634 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5635
ff9d07a0
ZY		 5636 return user_mode != 0;
5637}
5638
5639static unsigned long kvm_get_guest_ip(void)
5640{
5641 unsigned long ip = 0;
dcf46b94 5642
086c9855
AS		 5643 if (__this_cpu_read(current_vcpu))
5644 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5645
ff9d07a0
ZY		 5646 return ip;
5647}
5648
5649static struct perf_guest_info_callbacks kvm_guest_cbs = {
5650 .is_in_guest = kvm_is_in_guest,
5651 .is_user_mode = kvm_is_user_mode,
5652 .get_guest_ip = kvm_get_guest_ip,
5653};
5654
5655void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5656{
086c9855 5657 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5658}
5659EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5660
5661void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5662{
086c9855 5663 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5664}
5665EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5666
ce88decf
XG		 5667static void kvm_set_mmio_spte_mask(void)
5668{
5669 u64 mask;
5670 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5671
5672 /*
5673 * Set the reserved bits and the present bit of an paging-structure
5674 * entry to generate page fault with PFER.RSV = 1.
5675 */
885032b9 5676 /* Mask the reserved physical address bits. */
d1431483 5677 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5678
5679 /* Bit 62 is always reserved for 32bit host. */
5680 mask |= 0x3ull << 62;
5681
5682 /* Set the present bit. */
ce88decf
XG		 5683 mask |= 1ull;
5684
5685#ifdef CONFIG_X86_64
5686 /*
5687 * If reserved bit is not supported, clear the present bit to disable
5688 * mmio page fault.
5689 */
5690 if (maxphyaddr == 52)
5691 mask &= ~1ull;
5692#endif
5693
5694 kvm_mmu_set_mmio_spte_mask(mask);
5695}
5696
16e8d74d
MT		 5697#ifdef CONFIG_X86_64
5698static void pvclock_gtod_update_fn(struct work_struct *work)
5699{
d828199e
MT		 5700 struct kvm *kvm;
5701
5702 struct kvm_vcpu *vcpu;
5703 int i;
5704
2f303b74 5705 spin_lock(&kvm_lock);
d828199e
MT		 5706 list_for_each_entry(kvm, &vm_list, vm_list)
5707 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5708 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5709 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5710 spin_unlock(&kvm_lock);
16e8d74d
MT		 5711}
5712
5713static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5714
5715/*
5716 * Notification about pvclock gtod data update.
5717 */
5718static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5719 void *priv)
5720{
5721 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5722 struct timekeeper *tk = priv;
5723
5724 update_pvclock_gtod(tk);
5725
5726 /* disable master clock if host does not trust, or does not
5727 * use, TSC clocksource
5728 */
5729 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5730 atomic_read(&kvm_guest_has_master_clock) != 0)
5731 queue_work(system_long_wq, &pvclock_gtod_work);
5732
5733 return 0;
5734}
5735
5736static struct notifier_block pvclock_gtod_notifier = {
5737 .notifier_call = pvclock_gtod_notify,
5738};
5739#endif
5740
f8c16bba 5741int kvm_arch_init(void *opaque)
043405e1 5742{
b820cc0c 5743 int r;
6b61edf7 5744 struct kvm_x86_ops *ops = opaque;
f8c16bba 5745
f8c16bba
ZX		 5746 if (kvm_x86_ops) {
5747 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5748 r = -EEXIST;
5749 goto out;
f8c16bba
ZX		 5750 }
5751
5752 if (!ops->cpu_has_kvm_support()) {
5753 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5754 r = -EOPNOTSUPP;
5755 goto out;
f8c16bba
ZX		 5756 }
5757 if (ops->disabled_by_bios()) {
5758 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5759 r = -EOPNOTSUPP;
5760 goto out;
f8c16bba
ZX		 5761 }
5762
013f6a5d
MT		 5763 r = -ENOMEM;
5764 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5765 if (!shared_msrs) {
5766 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5767 goto out;
5768 }
5769
97db56ce
AK		 5770 r = kvm_mmu_module_init();
5771 if (r)
013f6a5d 5772 goto out_free_percpu;
97db56ce 5773
ce88decf 5774 kvm_set_mmio_spte_mask();
97db56ce 5775
f8c16bba 5776 kvm_x86_ops = ops;
920c8377 5777
7b52345e 5778 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5779 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5780
b820cc0c 5781 kvm_timer_init();
c8076604 5782
ff9d07a0
ZY		 5783 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5784
2acf923e
DC		 5785 if (cpu_has_xsave)
5786 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5787
c5cc421b 5788 kvm_lapic_init();
16e8d74d
MT		 5789#ifdef CONFIG_X86_64
5790 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5791#endif
5792
f8c16bba 5793 return 0;
56c6d28a 5794
013f6a5d
MT		 5795out_free_percpu:
5796 free_percpu(shared_msrs);
56c6d28a 5797out:
56c6d28a 5798 return r;
043405e1 5799}
8776e519 5800
f8c16bba
ZX		 5801void kvm_arch_exit(void)
5802{
ff9d07a0
ZY		 5803 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5804
888d256e
JK		 5805 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5806 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5807 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5808 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5809#ifdef CONFIG_X86_64
5810 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5811#endif
f8c16bba 5812 kvm_x86_ops = NULL;
56c6d28a 5813 kvm_mmu_module_exit();
013f6a5d 5814 free_percpu(shared_msrs);
56c6d28a 5815}
f8c16bba 5816
5cb56059 5817int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5818{
5819 ++vcpu->stat.halt_exits;
35754c98 5820 if (lapic_in_kernel(vcpu)) {
a4535290 5821 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5822 return 1;
5823 } else {
5824 vcpu->run->exit_reason = KVM_EXIT_HLT;
5825 return 0;
5826 }
5827}
5cb56059
JS		 5828EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5829
5830int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5831{
5832 kvm_x86_ops->skip_emulated_instruction(vcpu);
5833 return kvm_vcpu_halt(vcpu);
5834}
8776e519
HB		 5835EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5836
6aef266c
SV		 5837/*
5838 * kvm_pv_kick_cpu_op: Kick a vcpu.
5839 *
5840 * @apicid - apicid of vcpu to be kicked.
5841 */
5842static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5843{
24d2166b 5844 struct kvm_lapic_irq lapic_irq;
6aef266c 5845
24d2166b
R		 5846 lapic_irq.shorthand = 0;
5847 lapic_irq.dest_mode = 0;
5848 lapic_irq.dest_id = apicid;
93bbf0b8 5849 lapic_irq.msi_redir_hint = false;
6aef266c 5850
24d2166b 5851 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5852 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5853}
5854
8776e519
HB		 5855int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5856{
5857 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5858 int op_64_bit, r = 1;
8776e519 5859
5cb56059
JS		 5860 kvm_x86_ops->skip_emulated_instruction(vcpu);
5861
55cd8e5a
GN		 5862 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5863 return kvm_hv_hypercall(vcpu);
5864
5fdbf976
MT		 5865 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5866 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5867 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5868 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5869 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5870
229456fc 5871 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5872
a449c7aa
NA		 5873 op_64_bit = is_64_bit_mode(vcpu);
5874 if (!op_64_bit) {
8776e519
HB		 5875 nr &= 0xFFFFFFFF;
5876 a0 &= 0xFFFFFFFF;
5877 a1 &= 0xFFFFFFFF;
5878 a2 &= 0xFFFFFFFF;
5879 a3 &= 0xFFFFFFFF;
5880 }
5881
07708c4a
JK		 5882 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5883 ret = -KVM_EPERM;
5884 goto out;
5885 }
5886
8776e519 5887 switch (nr) {
b93463aa
AK		 5888 case KVM_HC_VAPIC_POLL_IRQ:
5889 ret = 0;
5890 break;
6aef266c
SV		 5891 case KVM_HC_KICK_CPU:
5892 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5893 ret = 0;
5894 break;
8776e519
HB		 5895 default:
5896 ret = -KVM_ENOSYS;
5897 break;
5898 }
07708c4a 5899out:
a449c7aa
NA		 5900 if (!op_64_bit)
5901 ret = (u32)ret;
5fdbf976 5902 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5903 ++vcpu->stat.hypercalls;
2f333bcb 5904 return r;
8776e519
HB		 5905}
5906EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5907
b6785def 5908static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5909{
d6aa1000 5910 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5911 char instruction[3];
5fdbf976 5912 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5913
8776e519 5914 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5915
9d74191a 5916 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5917}
5918
b6c7a5dc
HB		 5919/*
5920 * Check if userspace requested an interrupt window, and that the
5921 * interrupt window is open.
5922 *
5923 * No need to exit to userspace if we already have an interrupt queued.
5924 */
851ba692 5925static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5926{
1c1a9ce9
SR		 5927 if (!vcpu->run->request_interrupt_window || pic_in_kernel(vcpu->kvm))
5928 return false;
5929
127a457a
MG		 5930 if (!kvm_arch_interrupt_allowed(vcpu))
5931 return false;
5932
1c1a9ce9
SR		 5933 if (kvm_cpu_has_interrupt(vcpu))
5934 return false;
5935
127a457a
MG		 5936 if (kvm_event_needs_reinjection(vcpu))
5937 return false;
5938
5939 return kvm_cpu_accept_dm_intr(vcpu);
b6c7a5dc
HB		 5940}
5941
851ba692 5942static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5943{
851ba692
AK		 5944 struct kvm_run *kvm_run = vcpu->run;
5945
91586a3b 5946 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5947 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5948 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5949 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 5950 kvm_run->ready_for_interrupt_injection =
5951 pic_in_kernel(vcpu->kvm) ||
5952 (kvm_arch_interrupt_allowed(vcpu) &&
5953 !kvm_cpu_has_interrupt(vcpu) &&
5954 !kvm_event_needs_reinjection(vcpu) &&
5955 kvm_cpu_accept_dm_intr(vcpu));
b6c7a5dc
HB		 5956}
5957
95ba8273
GN		 5958static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5959{
5960 int max_irr, tpr;
5961
5962 if (!kvm_x86_ops->update_cr8_intercept)
5963 return;
5964
88c808fd
AK		 5965 if (!vcpu->arch.apic)
5966 return;
5967
8db3baa2
GN		 5968 if (!vcpu->arch.apic->vapic_addr)
5969 max_irr = kvm_lapic_find_highest_irr(vcpu);
5970 else
5971 max_irr = -1;
95ba8273
GN		 5972
5973 if (max_irr != -1)
5974 max_irr >>= 4;
5975
5976 tpr = kvm_lapic_get_cr8(vcpu);
5977
5978 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5979}
5980
b6b8a145 5981static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5982{
b6b8a145
JK		 5983 int r;
5984
95ba8273 5985 /* try to reinject previous events if any */
b59bb7bd 5986 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5987 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5988 vcpu->arch.exception.has_error_code,
5989 vcpu->arch.exception.error_code);
d6e8c854
NA		 5990
5991 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5992 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5993 X86_EFLAGS_RF);
5994
6bdf0662
NA		 5995 if (vcpu->arch.exception.nr == DB_VECTOR &&
5996 (vcpu->arch.dr7 & DR7_GD)) {
5997 vcpu->arch.dr7 &= ~DR7_GD;
5998 kvm_update_dr7(vcpu);
5999 }
6000
b59bb7bd
GN		 6001 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6002 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6003 vcpu->arch.exception.error_code,
6004 vcpu->arch.exception.reinject);
b6b8a145 6005 return 0;
b59bb7bd
GN		 6006 }
6007
95ba8273
GN		 6008 if (vcpu->arch.nmi_injected) {
6009 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6010 return 0;
95ba8273
GN		 6011 }
6012
6013 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6014 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6015 return 0;
6016 }
6017
6018 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6019 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6020 if (r != 0)
6021 return r;
95ba8273
GN		 6022 }
6023
6024 /* try to inject new event if pending */
6025 if (vcpu->arch.nmi_pending) {
6026 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6027 --vcpu->arch.nmi_pending;
95ba8273
GN		 6028 vcpu->arch.nmi_injected = true;
6029 kvm_x86_ops->set_nmi(vcpu);
6030 }
c7c9c56c 6031 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6032 /*
6033 * Because interrupts can be injected asynchronously, we are
6034 * calling check_nested_events again here to avoid a race condition.
6035 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6036 * proposal and current concerns. Perhaps we should be setting
6037 * KVM_REQ_EVENT only on certain events and not unconditionally?
6038 */
6039 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6040 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6041 if (r != 0)
6042 return r;
6043 }
95ba8273 6044 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6045 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6046 false);
6047 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6048 }
6049 }
b6b8a145 6050 return 0;
95ba8273
GN		 6051}
6052
7460fb4a
AK		 6053static void process_nmi(struct kvm_vcpu *vcpu)
6054{
6055 unsigned limit = 2;
6056
6057 /*
6058 * x86 is limited to one NMI running, and one NMI pending after it.
6059 * If an NMI is already in progress, limit further NMIs to just one.
6060 * Otherwise, allow two (and we'll inject the first one immediately).
6061 */
6062 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6063 limit = 1;
6064
6065 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6066 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6067 kvm_make_request(KVM_REQ_EVENT, vcpu);
6068}
6069
660a5d51
PB		 6070#define put_smstate(type, buf, offset, val) \
6071 *(type *)((buf) + (offset) - 0x7e00) = val
6072
6073static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6074{
6075 u32 flags = 0;
6076 flags |= seg->g << 23;
6077 flags |= seg->db << 22;
6078 flags |= seg->l << 21;
6079 flags |= seg->avl << 20;
6080 flags |= seg->present << 15;
6081 flags |= seg->dpl << 13;
6082 flags |= seg->s << 12;
6083 flags |= seg->type << 8;
6084 return flags;
6085}
6086
6087static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6088{
6089 struct kvm_segment seg;
6090 int offset;
6091
6092 kvm_get_segment(vcpu, &seg, n);
6093 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6094
6095 if (n < 3)
6096 offset = 0x7f84 + n * 12;
6097 else
6098 offset = 0x7f2c + (n - 3) * 12;
6099
6100 put_smstate(u32, buf, offset + 8, seg.base);
6101 put_smstate(u32, buf, offset + 4, seg.limit);
6102 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6103}
6104
efbb288a 6105#ifdef CONFIG_X86_64
660a5d51
PB		 6106static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6107{
6108 struct kvm_segment seg;
6109 int offset;
6110 u16 flags;
6111
6112 kvm_get_segment(vcpu, &seg, n);
6113 offset = 0x7e00 + n * 16;
6114
6115 flags = process_smi_get_segment_flags(&seg) >> 8;
6116 put_smstate(u16, buf, offset, seg.selector);
6117 put_smstate(u16, buf, offset + 2, flags);
6118 put_smstate(u32, buf, offset + 4, seg.limit);
6119 put_smstate(u64, buf, offset + 8, seg.base);
6120}
efbb288a 6121#endif
660a5d51
PB		 6122
6123static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6124{
6125 struct desc_ptr dt;
6126 struct kvm_segment seg;
6127 unsigned long val;
6128 int i;
6129
6130 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6131 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6132 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6133 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6134
6135 for (i = 0; i < 8; i++)
6136 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6137
6138 kvm_get_dr(vcpu, 6, &val);
6139 put_smstate(u32, buf, 0x7fcc, (u32)val);
6140 kvm_get_dr(vcpu, 7, &val);
6141 put_smstate(u32, buf, 0x7fc8, (u32)val);
6142
6143 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6144 put_smstate(u32, buf, 0x7fc4, seg.selector);
6145 put_smstate(u32, buf, 0x7f64, seg.base);
6146 put_smstate(u32, buf, 0x7f60, seg.limit);
6147 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6148
6149 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6150 put_smstate(u32, buf, 0x7fc0, seg.selector);
6151 put_smstate(u32, buf, 0x7f80, seg.base);
6152 put_smstate(u32, buf, 0x7f7c, seg.limit);
6153 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6154
6155 kvm_x86_ops->get_gdt(vcpu, &dt);
6156 put_smstate(u32, buf, 0x7f74, dt.address);
6157 put_smstate(u32, buf, 0x7f70, dt.size);
6158
6159 kvm_x86_ops->get_idt(vcpu, &dt);
6160 put_smstate(u32, buf, 0x7f58, dt.address);
6161 put_smstate(u32, buf, 0x7f54, dt.size);
6162
6163 for (i = 0; i < 6; i++)
6164 process_smi_save_seg_32(vcpu, buf, i);
6165
6166 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6167
6168 /* revision id */
6169 put_smstate(u32, buf, 0x7efc, 0x00020000);
6170 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6171}
6172
6173static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6174{
6175#ifdef CONFIG_X86_64
6176 struct desc_ptr dt;
6177 struct kvm_segment seg;
6178 unsigned long val;
6179 int i;
6180
6181 for (i = 0; i < 16; i++)
6182 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6183
6184 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6185 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6186
6187 kvm_get_dr(vcpu, 6, &val);
6188 put_smstate(u64, buf, 0x7f68, val);
6189 kvm_get_dr(vcpu, 7, &val);
6190 put_smstate(u64, buf, 0x7f60, val);
6191
6192 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6193 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6194 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6195
6196 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6197
6198 /* revision id */
6199 put_smstate(u32, buf, 0x7efc, 0x00020064);
6200
6201 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6202
6203 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6204 put_smstate(u16, buf, 0x7e90, seg.selector);
6205 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6206 put_smstate(u32, buf, 0x7e94, seg.limit);
6207 put_smstate(u64, buf, 0x7e98, seg.base);
6208
6209 kvm_x86_ops->get_idt(vcpu, &dt);
6210 put_smstate(u32, buf, 0x7e84, dt.size);
6211 put_smstate(u64, buf, 0x7e88, dt.address);
6212
6213 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6214 put_smstate(u16, buf, 0x7e70, seg.selector);
6215 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6216 put_smstate(u32, buf, 0x7e74, seg.limit);
6217 put_smstate(u64, buf, 0x7e78, seg.base);
6218
6219 kvm_x86_ops->get_gdt(vcpu, &dt);
6220 put_smstate(u32, buf, 0x7e64, dt.size);
6221 put_smstate(u64, buf, 0x7e68, dt.address);
6222
6223 for (i = 0; i < 6; i++)
6224 process_smi_save_seg_64(vcpu, buf, i);
6225#else
6226 WARN_ON_ONCE(1);
6227#endif
6228}
6229
64d60670
PB		 6230static void process_smi(struct kvm_vcpu *vcpu)
6231{
660a5d51 6232 struct kvm_segment cs, ds;
18c3626e 6233 struct desc_ptr dt;
660a5d51
PB		 6234 char buf[512];
6235 u32 cr0;
6236
64d60670
PB		 6237 if (is_smm(vcpu)) {
6238 vcpu->arch.smi_pending = true;
6239 return;
6240 }
6241
660a5d51
PB		 6242 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6243 vcpu->arch.hflags |= HF_SMM_MASK;
6244 memset(buf, 0, 512);
6245 if (guest_cpuid_has_longmode(vcpu))
6246 process_smi_save_state_64(vcpu, buf);
6247 else
6248 process_smi_save_state_32(vcpu, buf);
6249
54bf36aa 6250 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6251
6252 if (kvm_x86_ops->get_nmi_mask(vcpu))
6253 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6254 else
6255 kvm_x86_ops->set_nmi_mask(vcpu, true);
6256
6257 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6258 kvm_rip_write(vcpu, 0x8000);
6259
6260 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6261 kvm_x86_ops->set_cr0(vcpu, cr0);
6262 vcpu->arch.cr0 = cr0;
6263
6264 kvm_x86_ops->set_cr4(vcpu, 0);
6265
18c3626e
PB		 6266 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6267 dt.address = dt.size = 0;
6268 kvm_x86_ops->set_idt(vcpu, &dt);
6269
660a5d51
PB		 6270 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6271
6272 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6273 cs.base = vcpu->arch.smbase;
6274
6275 ds.selector = 0;
6276 ds.base = 0;
6277
6278 cs.limit = ds.limit = 0xffffffff;
6279 cs.type = ds.type = 0x3;
6280 cs.dpl = ds.dpl = 0;
6281 cs.db = ds.db = 0;
6282 cs.s = ds.s = 1;
6283 cs.l = ds.l = 0;
6284 cs.g = ds.g = 1;
6285 cs.avl = ds.avl = 0;
6286 cs.present = ds.present = 1;
6287 cs.unusable = ds.unusable = 0;
6288 cs.padding = ds.padding = 0;
6289
6290 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6291 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6292 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6293 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6294 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6295 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6296
6297 if (guest_cpuid_has_longmode(vcpu))
6298 kvm_x86_ops->set_efer(vcpu, 0);
6299
6300 kvm_update_cpuid(vcpu);
6301 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6302}
6303
3d81bc7e 6304static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6305{
3d81bc7e
YZ		 6306 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6307 return;
c7c9c56c 6308
3bb345f3 6309 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
c7c9c56c 6310
b053b2ae
SR		 6311 if (irqchip_split(vcpu->kvm))
6312 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
db2bdcbb
RK		 6313 else {
6314 kvm_x86_ops->sync_pir_to_irr(vcpu);
b053b2ae 6315 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
db2bdcbb 6316 }
3bb345f3 6317 kvm_x86_ops->load_eoi_exitmap(vcpu);
c7c9c56c
YZ		 6318}
6319
a70656b6
RK		 6320static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6321{
6322 ++vcpu->stat.tlb_flush;
6323 kvm_x86_ops->tlb_flush(vcpu);
6324}
6325
4256f43f
TC		 6326void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6327{
c24ae0dc
TC		 6328 struct page *page = NULL;
6329
35754c98 6330 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6331 return;
6332
4256f43f
TC		 6333 if (!kvm_x86_ops->set_apic_access_page_addr)
6334 return;
6335
c24ae0dc 6336 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6337 if (is_error_page(page))
6338 return;
c24ae0dc
TC		 6339 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6340
6341 /*
6342 * Do not pin apic access page in memory, the MMU notifier
6343 * will call us again if it is migrated or swapped out.
6344 */
6345 put_page(page);
4256f43f
TC		 6346}
6347EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6348
fe71557a
TC		 6349void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6350 unsigned long address)
6351{
c24ae0dc
TC		 6352 /*
6353 * The physical address of apic access page is stored in the VMCS.
6354 * Update it when it becomes invalid.
6355 */
6356 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6357 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6358}
6359
9357d939 6360/*
362c698f 6361 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6362 * exiting to the userspace. Otherwise, the value will be returned to the
6363 * userspace.
6364 */
851ba692 6365static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6366{
6367 int r;
35754c98 6368 bool req_int_win = !lapic_in_kernel(vcpu) &&
851ba692 6369 vcpu->run->request_interrupt_window;
730dca42 6370 bool req_immediate_exit = false;
b6c7a5dc 6371
3e007509 6372 if (vcpu->requests) {
a8eeb04a 6373 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6374 kvm_mmu_unload(vcpu);
a8eeb04a 6375 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6376 __kvm_migrate_timers(vcpu);
d828199e
MT		 6377 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6378 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6379 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6380 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6381 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6382 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6383 if (unlikely(r))
6384 goto out;
6385 }
a8eeb04a 6386 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6387 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6388 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6389 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6390 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6391 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6392 r = 0;
6393 goto out;
6394 }
a8eeb04a 6395 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6396 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6397 r = 0;
6398 goto out;
6399 }
a8eeb04a 6400 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6401 vcpu->fpu_active = 0;
6402 kvm_x86_ops->fpu_deactivate(vcpu);
6403 }
af585b92
GN		 6404 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6405 /* Page is swapped out. Do synthetic halt */
6406 vcpu->arch.apf.halted = true;
6407 r = 1;
6408 goto out;
6409 }
c9aaa895
GC		 6410 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6411 record_steal_time(vcpu);
64d60670
PB		 6412 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6413 process_smi(vcpu);
7460fb4a
AK		 6414 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6415 process_nmi(vcpu);
f5132b01 6416 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6417 kvm_pmu_handle_event(vcpu);
f5132b01 6418 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6419 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6420 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6421 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6422 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6423 (void *) vcpu->arch.eoi_exit_bitmap)) {
6424 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6425 vcpu->run->eoi.vector =
6426 vcpu->arch.pending_ioapic_eoi;
6427 r = 0;
6428 goto out;
6429 }
6430 }
3d81bc7e
YZ		 6431 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6432 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6433 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6434 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6435 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6436 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6437 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6438 r = 0;
6439 goto out;
6440 }
e516cebb
AS		 6441 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6442 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6443 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6444 r = 0;
6445 goto out;
6446 }
2f52d58c 6447 }
b93463aa 6448
bf9f6ac8
FW		 6449 /*
6450 * KVM_REQ_EVENT is not set when posted interrupts are set by
6451 * VT-d hardware, so we have to update RVI unconditionally.
6452 */
6453 if (kvm_lapic_enabled(vcpu)) {
6454 /*
6455 * Update architecture specific hints for APIC
6456 * virtual interrupt delivery.
6457 */
6458 if (kvm_x86_ops->hwapic_irr_update)
6459 kvm_x86_ops->hwapic_irr_update(vcpu,
6460 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6461 }
b93463aa 6462
b463a6f7 6463 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6464 kvm_apic_accept_events(vcpu);
6465 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6466 r = 1;
6467 goto out;
6468 }
6469
b6b8a145
JK		 6470 if (inject_pending_event(vcpu, req_int_win) != 0)
6471 req_immediate_exit = true;
b463a6f7 6472 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6473 else if (vcpu->arch.nmi_pending)
c9a7953f 6474 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6475 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6476 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6477
6478 if (kvm_lapic_enabled(vcpu)) {
6479 update_cr8_intercept(vcpu);
6480 kvm_lapic_sync_to_vapic(vcpu);
6481 }
6482 }
6483
d8368af8
AK		 6484 r = kvm_mmu_reload(vcpu);
6485 if (unlikely(r)) {
d905c069 6486 goto cancel_injection;
d8368af8
AK		 6487 }
6488
b6c7a5dc
HB		 6489 preempt_disable();
6490
6491 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6492 if (vcpu->fpu_active)
6493 kvm_load_guest_fpu(vcpu);
2acf923e 6494 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6495
6b7e2d09
XG		 6496 vcpu->mode = IN_GUEST_MODE;
6497
01b71917
MT		 6498 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6499
6b7e2d09
XG		 6500 /* We should set ->mode before check ->requests,
6501 * see the comment in make_all_cpus_request.
6502 */
01b71917 6503 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6504
d94e1dc9 6505 local_irq_disable();
32f88400 6506
6b7e2d09 6507 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6508 || need_resched() || signal_pending(current)) {
6b7e2d09 6509 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6510 smp_wmb();
6c142801
AK		 6511 local_irq_enable();
6512 preempt_enable();
01b71917 6513 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6514 r = 1;
d905c069 6515 goto cancel_injection;
6c142801
AK		 6516 }
6517
d6185f20
NHE		 6518 if (req_immediate_exit)
6519 smp_send_reschedule(vcpu->cpu);
6520
ccf73aaf 6521 __kvm_guest_enter();
b6c7a5dc 6522
42dbaa5a 6523 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6524 set_debugreg(0, 7);
6525 set_debugreg(vcpu->arch.eff_db[0], 0);
6526 set_debugreg(vcpu->arch.eff_db[1], 1);
6527 set_debugreg(vcpu->arch.eff_db[2], 2);
6528 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6529 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6530 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6531 }
b6c7a5dc 6532
229456fc 6533 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6534 wait_lapic_expire(vcpu);
851ba692 6535 kvm_x86_ops->run(vcpu);
b6c7a5dc 6536
c77fb5fe
PB		 6537 /*
6538 * Do this here before restoring debug registers on the host. And
6539 * since we do this before handling the vmexit, a DR access vmexit
6540 * can (a) read the correct value of the debug registers, (b) set
6541 * KVM_DEBUGREG_WONT_EXIT again.
6542 */
6543 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6544 int i;
6545
6546 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6547 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6548 for (i = 0; i < KVM_NR_DB_REGS; i++)
6549 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6550 }
6551
24f1e32c
FW		 6552 /*
6553 * If the guest has used debug registers, at least dr7
6554 * will be disabled while returning to the host.
6555 * If we don't have active breakpoints in the host, we don't
6556 * care about the messed up debug address registers. But if
6557 * we have some of them active, restore the old state.
6558 */
59d8eb53 6559 if (hw_breakpoint_active())
24f1e32c 6560 hw_breakpoint_restore();
42dbaa5a 6561
4ba76538 6562 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6563
6b7e2d09 6564 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6565 smp_wmb();
a547c6db
YZ		 6566
6567 /* Interrupt is enabled by handle_external_intr() */
6568 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6569
6570 ++vcpu->stat.exits;
6571
6572 /*
6573 * We must have an instruction between local_irq_enable() and
6574 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6575 * the interrupt shadow. The stat.exits increment will do nicely.
6576 * But we need to prevent reordering, hence this barrier():
6577 */
6578 barrier();
6579
6580 kvm_guest_exit();
6581
6582 preempt_enable();
6583
f656ce01 6584 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6585
b6c7a5dc
HB		 6586 /*
6587 * Profile KVM exit RIPs:
6588 */
6589 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6590 unsigned long rip = kvm_rip_read(vcpu);
6591 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6592 }
6593
cc578287
ZA		 6594 if (unlikely(vcpu->arch.tsc_always_catchup))
6595 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6596
5cfb1d5a
MT		 6597 if (vcpu->arch.apic_attention)
6598 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6599
851ba692 6600 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6601 return r;
6602
6603cancel_injection:
6604 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6605 if (unlikely(vcpu->arch.apic_attention))
6606 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6607out:
6608 return r;
6609}
b6c7a5dc 6610
362c698f
PB		 6611static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6612{
bf9f6ac8
FW		 6613 if (!kvm_arch_vcpu_runnable(vcpu) &&
6614 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6615 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6616 kvm_vcpu_block(vcpu);
6617 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6618
6619 if (kvm_x86_ops->post_block)
6620 kvm_x86_ops->post_block(vcpu);
6621
9c8fd1ba
PB		 6622 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6623 return 1;
6624 }
362c698f
PB		 6625
6626 kvm_apic_accept_events(vcpu);
6627 switch(vcpu->arch.mp_state) {
6628 case KVM_MP_STATE_HALTED:
6629 vcpu->arch.pv.pv_unhalted = false;
6630 vcpu->arch.mp_state =
6631 KVM_MP_STATE_RUNNABLE;
6632 case KVM_MP_STATE_RUNNABLE:
6633 vcpu->arch.apf.halted = false;
6634 break;
6635 case KVM_MP_STATE_INIT_RECEIVED:
6636 break;
6637 default:
6638 return -EINTR;
6639 break;
6640 }
6641 return 1;
6642}
09cec754 6643
5d9bc648
PB		 6644static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6645{
6646 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6647 !vcpu->arch.apf.halted);
6648}
6649
362c698f 6650static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6651{
6652 int r;
f656ce01 6653 struct kvm *kvm = vcpu->kvm;
d7690175 6654
f656ce01 6655 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6656
362c698f 6657 for (;;) {
58f800d5 6658 if (kvm_vcpu_running(vcpu)) {
851ba692 6659 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6660 } else {
362c698f 6661 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6662 }
6663
09cec754
GN		 6664 if (r <= 0)
6665 break;
6666
6667 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6668 if (kvm_cpu_has_pending_timer(vcpu))
6669 kvm_inject_pending_timer_irqs(vcpu);
6670
851ba692 6671 if (dm_request_for_irq_injection(vcpu)) {
4ca7dd8c
PB		 6672 r = 0;
6673 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6674 ++vcpu->stat.request_irq_exits;
362c698f 6675 break;
09cec754 6676 }
af585b92
GN		 6677
6678 kvm_check_async_pf_completion(vcpu);
6679
09cec754
GN		 6680 if (signal_pending(current)) {
6681 r = -EINTR;
851ba692 6682 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6683 ++vcpu->stat.signal_exits;
362c698f 6684 break;
09cec754
GN		 6685 }
6686 if (need_resched()) {
f656ce01 6687 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6688 cond_resched();
f656ce01 6689 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6690 }
b6c7a5dc
HB		 6691 }
6692
f656ce01 6693 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6694
6695 return r;
6696}
6697
716d51ab
GN		 6698static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6699{
6700 int r;
6701 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6702 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6703 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6704 if (r != EMULATE_DONE)
6705 return 0;
6706 return 1;
6707}
6708
6709static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6710{
6711 BUG_ON(!vcpu->arch.pio.count);
6712
6713 return complete_emulated_io(vcpu);
6714}
6715
f78146b0
AK		 6716/*
6717 * Implements the following, as a state machine:
6718 *
6719 * read:
6720 * for each fragment
87da7e66
XG		 6721 * for each mmio piece in the fragment
6722 * write gpa, len
6723 * exit
6724 * copy data
f78146b0
AK		 6725 * execute insn
6726 *
6727 * write:
6728 * for each fragment
87da7e66
XG		 6729 * for each mmio piece in the fragment
6730 * write gpa, len
6731 * copy data
6732 * exit
f78146b0 6733 */
716d51ab 6734static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6735{
6736 struct kvm_run *run = vcpu->run;
f78146b0 6737 struct kvm_mmio_fragment *frag;
87da7e66 6738 unsigned len;
5287f194 6739
716d51ab 6740 BUG_ON(!vcpu->mmio_needed);
5287f194 6741
716d51ab 6742 /* Complete previous fragment */
87da7e66
XG		 6743 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6744 len = min(8u, frag->len);
716d51ab 6745 if (!vcpu->mmio_is_write)
87da7e66
XG		 6746 memcpy(frag->data, run->mmio.data, len);
6747
6748 if (frag->len <= 8) {
6749 /* Switch to the next fragment. */
6750 frag++;
6751 vcpu->mmio_cur_fragment++;
6752 } else {
6753 /* Go forward to the next mmio piece. */
6754 frag->data += len;
6755 frag->gpa += len;
6756 frag->len -= len;
6757 }
6758
a08d3b3b 6759 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6760 vcpu->mmio_needed = 0;
0912c977
PB		 6761
6762 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6763 if (vcpu->mmio_is_write)
716d51ab
GN		 6764 return 1;
6765 vcpu->mmio_read_completed = 1;
6766 return complete_emulated_io(vcpu);
6767 }
87da7e66 6768
716d51ab
GN		 6769 run->exit_reason = KVM_EXIT_MMIO;
6770 run->mmio.phys_addr = frag->gpa;
6771 if (vcpu->mmio_is_write)
87da7e66
XG		 6772 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6773 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6774 run->mmio.is_write = vcpu->mmio_is_write;
6775 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6776 return 0;
5287f194
AK		 6777}
6778
716d51ab 6779
b6c7a5dc
HB		 6780int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6781{
c5bedc68 6782 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6783 int r;
6784 sigset_t sigsaved;
6785
c4d72e2d 6786 fpu__activate_curr(fpu);
e5c30142 6787
ac9f6dc0
AK		 6788 if (vcpu->sigset_active)
6789 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6790
a4535290 6791 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6792 kvm_vcpu_block(vcpu);
66450a21 6793 kvm_apic_accept_events(vcpu);
d7690175 6794 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6795 r = -EAGAIN;
6796 goto out;
b6c7a5dc
HB		 6797 }
6798
b6c7a5dc 6799 /* re-sync apic's tpr */
35754c98 6800 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6801 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6802 r = -EINVAL;
6803 goto out;
6804 }
6805 }
b6c7a5dc 6806
716d51ab
GN		 6807 if (unlikely(vcpu->arch.complete_userspace_io)) {
6808 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6809 vcpu->arch.complete_userspace_io = NULL;
6810 r = cui(vcpu);
6811 if (r <= 0)
6812 goto out;
6813 } else
6814 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6815
362c698f 6816 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6817
6818out:
f1d86e46 6819 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6820 if (vcpu->sigset_active)
6821 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6822
b6c7a5dc
HB		 6823 return r;
6824}
6825
6826int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6827{
7ae441ea
GN		 6828 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6829 /*
6830 * We are here if userspace calls get_regs() in the middle of
6831 * instruction emulation. Registers state needs to be copied
4a969980 6832 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6833 * that usually, but some bad designed PV devices (vmware
6834 * backdoor interface) need this to work
6835 */
dd856efa 6836 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6837 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6838 }
5fdbf976
MT		 6839 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6840 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6841 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6842 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6843 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6844 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6845 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6846 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6847#ifdef CONFIG_X86_64
5fdbf976
MT		 6848 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6849 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6850 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6851 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6852 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6853 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6854 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6855 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6856#endif
6857
5fdbf976 6858 regs->rip = kvm_rip_read(vcpu);
91586a3b 6859 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6860
b6c7a5dc
HB		 6861 return 0;
6862}
6863
6864int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6865{
7ae441ea
GN		 6866 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6867 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6868
5fdbf976
MT		 6869 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6870 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6871 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6872 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6873 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6874 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6875 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6876 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6877#ifdef CONFIG_X86_64
5fdbf976
MT		 6878 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6879 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6880 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6881 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6882 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6883 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6884 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6885 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6886#endif
6887
5fdbf976 6888 kvm_rip_write(vcpu, regs->rip);
91586a3b 6889 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6890
b4f14abd
JK		 6891 vcpu->arch.exception.pending = false;
6892
3842d135
AK		 6893 kvm_make_request(KVM_REQ_EVENT, vcpu);
6894
b6c7a5dc
HB		 6895 return 0;
6896}
6897
b6c7a5dc
HB		 6898void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6899{
6900 struct kvm_segment cs;
6901
3e6e0aab 6902 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6903 *db = cs.db;
6904 *l = cs.l;
6905}
6906EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6907
6908int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6909 struct kvm_sregs *sregs)
6910{
89a27f4d 6911 struct desc_ptr dt;
b6c7a5dc 6912
3e6e0aab
GT		 6913 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6914 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6915 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6916 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6917 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6918 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6919
3e6e0aab
GT		 6920 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6921 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6922
6923 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6924 sregs->idt.limit = dt.size;
6925 sregs->idt.base = dt.address;
b6c7a5dc 6926 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6927 sregs->gdt.limit = dt.size;
6928 sregs->gdt.base = dt.address;
b6c7a5dc 6929
4d4ec087 6930 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6931 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6932 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6933 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6934 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6935 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6936 sregs->apic_base = kvm_get_apic_base(vcpu);
6937
923c61bb 6938 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6939
36752c9b 6940 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6941 set_bit(vcpu->arch.interrupt.nr,
6942 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6943
b6c7a5dc
HB		 6944 return 0;
6945}
6946
62d9f0db
MT		 6947int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6948 struct kvm_mp_state *mp_state)
6949{
66450a21 6950 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6951 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6952 vcpu->arch.pv.pv_unhalted)
6953 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6954 else
6955 mp_state->mp_state = vcpu->arch.mp_state;
6956
62d9f0db
MT		 6957 return 0;
6958}
6959
6960int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6961 struct kvm_mp_state *mp_state)
6962{
66450a21
JK		 6963 if (!kvm_vcpu_has_lapic(vcpu) &&
6964 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6965 return -EINVAL;
6966
6967 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6968 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6969 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6970 } else
6971 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6972 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6973 return 0;
6974}
6975
7f3d35fd
KW		 6976int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6977 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6978{
9d74191a 6979 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6980 int ret;
e01c2426 6981
8ec4722d 6982 init_emulate_ctxt(vcpu);
c697518a 6983
7f3d35fd 6984 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6985 has_error_code, error_code);
c697518a 6986
c697518a 6987 if (ret)
19d04437 6988 return EMULATE_FAIL;
37817f29 6989
9d74191a
TY		 6990 kvm_rip_write(vcpu, ctxt->eip);
6991 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6992 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6993 return EMULATE_DONE;
37817f29
IE		 6994}
6995EXPORT_SYMBOL_GPL(kvm_task_switch);
6996
b6c7a5dc
HB		 6997int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6998 struct kvm_sregs *sregs)
6999{
58cb628d 7000 struct msr_data apic_base_msr;
b6c7a5dc 7001 int mmu_reset_needed = 0;
63f42e02 7002 int pending_vec, max_bits, idx;
89a27f4d 7003 struct desc_ptr dt;
b6c7a5dc 7004
6d1068b3
PM		 7005 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7006 return -EINVAL;
7007
89a27f4d
GN		 7008 dt.size = sregs->idt.limit;
7009 dt.address = sregs->idt.base;
b6c7a5dc 7010 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7011 dt.size = sregs->gdt.limit;
7012 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7013 kvm_x86_ops->set_gdt(vcpu, &dt);
7014
ad312c7c 7015 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7016 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7017 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7018 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7019
2d3ad1f4 7020 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7021
f6801dff 7022 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7023 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7024 apic_base_msr.data = sregs->apic_base;
7025 apic_base_msr.host_initiated = true;
7026 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7027
4d4ec087 7028 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7029 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7030 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7031
fc78f519 7032 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7033 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 7034 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 7035 kvm_update_cpuid(vcpu);
63f42e02
XG		 7036
7037 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7038 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7039 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7040 mmu_reset_needed = 1;
7041 }
63f42e02 7042 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7043
7044 if (mmu_reset_needed)
7045 kvm_mmu_reset_context(vcpu);
7046
a50abc3b 7047 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7048 pending_vec = find_first_bit(
7049 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7050 if (pending_vec < max_bits) {
66fd3f7f 7051 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7052 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7053 }
7054
3e6e0aab
GT		 7055 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7056 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7057 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7058 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7059 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7060 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7061
3e6e0aab
GT		 7062 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7063 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7064
5f0269f5
ME		 7065 update_cr8_intercept(vcpu);
7066
9c3e4aab 7067 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7068 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7069 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7070 !is_protmode(vcpu))
9c3e4aab
MT		 7071 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7072
3842d135
AK		 7073 kvm_make_request(KVM_REQ_EVENT, vcpu);
7074
b6c7a5dc
HB		 7075 return 0;
7076}
7077
d0bfb940
JK		 7078int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7079 struct kvm_guest_debug *dbg)
b6c7a5dc 7080{
355be0b9 7081 unsigned long rflags;
ae675ef0 7082 int i, r;
b6c7a5dc 7083
4f926bf2
JK		 7084 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7085 r = -EBUSY;
7086 if (vcpu->arch.exception.pending)
2122ff5e 7087 goto out;
4f926bf2
JK		 7088 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7089 kvm_queue_exception(vcpu, DB_VECTOR);
7090 else
7091 kvm_queue_exception(vcpu, BP_VECTOR);
7092 }
7093
91586a3b
JK		 7094 /*
7095 * Read rflags as long as potentially injected trace flags are still
7096 * filtered out.
7097 */
7098 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7099
7100 vcpu->guest_debug = dbg->control;
7101 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7102 vcpu->guest_debug = 0;
7103
7104 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7105 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7106 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7107 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7108 } else {
7109 for (i = 0; i < KVM_NR_DB_REGS; i++)
7110 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7111 }
c8639010 7112 kvm_update_dr7(vcpu);
ae675ef0 7113
f92653ee
JK		 7114 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7115 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7116 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7117
91586a3b
JK		 7118 /*
7119 * Trigger an rflags update that will inject or remove the trace
7120 * flags.
7121 */
7122 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7123
a96036b8 7124 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7125
4f926bf2 7126 r = 0;
d0bfb940 7127
2122ff5e 7128out:
b6c7a5dc
HB		 7129
7130 return r;
7131}
7132
8b006791
ZX		 7133/*
7134 * Translate a guest virtual address to a guest physical address.
7135 */
7136int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7137 struct kvm_translation *tr)
7138{
7139 unsigned long vaddr = tr->linear_address;
7140 gpa_t gpa;
f656ce01 7141 int idx;
8b006791 7142
f656ce01 7143 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7144 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7145 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7146 tr->physical_address = gpa;
7147 tr->valid = gpa != UNMAPPED_GVA;
7148 tr->writeable = 1;
7149 tr->usermode = 0;
8b006791
ZX		 7150
7151 return 0;
7152}
7153
d0752060
HB		 7154int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7155{
c47ada30 7156 struct fxregs_state *fxsave =
7366ed77 7157 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7158
d0752060
HB		 7159 memcpy(fpu->fpr, fxsave->st_space, 128);
7160 fpu->fcw = fxsave->cwd;
7161 fpu->fsw = fxsave->swd;
7162 fpu->ftwx = fxsave->twd;
7163 fpu->last_opcode = fxsave->fop;
7164 fpu->last_ip = fxsave->rip;
7165 fpu->last_dp = fxsave->rdp;
7166 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7167
d0752060
HB		 7168 return 0;
7169}
7170
7171int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7172{
c47ada30 7173 struct fxregs_state *fxsave =
7366ed77 7174 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7175
d0752060
HB		 7176 memcpy(fxsave->st_space, fpu->fpr, 128);
7177 fxsave->cwd = fpu->fcw;
7178 fxsave->swd = fpu->fsw;
7179 fxsave->twd = fpu->ftwx;
7180 fxsave->fop = fpu->last_opcode;
7181 fxsave->rip = fpu->last_ip;
7182 fxsave->rdp = fpu->last_dp;
7183 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7184
d0752060
HB		 7185 return 0;
7186}
7187
0ee6a517 7188static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7189{
bf935b0b 7190 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7191 if (cpu_has_xsaves)
7366ed77 7192 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7193 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7194
2acf923e
DC		 7195 /*
7196 * Ensure guest xcr0 is valid for loading
7197 */
d91cab78 7198 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7199
ad312c7c 7200 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7201}
d0752060
HB		 7202
7203void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7204{
2608d7a1 7205 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7206 return;
7207
2acf923e
DC		 7208 /*
7209 * Restore all possible states in the guest,
7210 * and assume host would use all available bits.
7211 * Guest xcr0 would be loaded later.
7212 */
7213 kvm_put_guest_xcr0(vcpu);
d0752060 7214 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7215 __kernel_fpu_begin();
003e2e8b 7216 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7217 trace_kvm_fpu(1);
d0752060 7218}
d0752060
HB		 7219
7220void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7221{
2acf923e
DC		 7222 kvm_put_guest_xcr0(vcpu);
7223
653f52c3
RR		 7224 if (!vcpu->guest_fpu_loaded) {
7225 vcpu->fpu_counter = 0;
d0752060 7226 return;
653f52c3 7227 }
d0752060
HB		 7228
7229 vcpu->guest_fpu_loaded = 0;
4f836347 7230 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7231 __kernel_fpu_end();
f096ed85 7232 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7233 /*
7234 * If using eager FPU mode, or if the guest is a frequent user
7235 * of the FPU, just leave the FPU active for next time.
7236 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7237 * the FPU in bursts will revert to loading it on demand.
7238 */
a9b4fb7e 7239 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7240 if (++vcpu->fpu_counter < 5)
7241 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7242 }
0c04851c 7243 trace_kvm_fpu(0);
d0752060 7244}
e9b11c17
ZX		 7245
7246void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7247{
12f9a48f 7248 kvmclock_reset(vcpu);
7f1ea208 7249
f5f48ee1 7250 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7251 kvm_x86_ops->vcpu_free(vcpu);
7252}
7253
7254struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7255 unsigned int id)
7256{
c447e76b
LL		 7257 struct kvm_vcpu *vcpu;
7258
6755bae8
ZA		 7259 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7260 printk_once(KERN_WARNING
7261 "kvm: SMP vm created on host with unstable TSC; "
7262 "guest TSC will not be reliable\n");
c447e76b
LL		 7263
7264 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7265
c447e76b 7266 return vcpu;
26e5215f 7267}
e9b11c17 7268
26e5215f
AK		 7269int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7270{
7271 int r;
e9b11c17 7272
19efffa2 7273 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7274 r = vcpu_load(vcpu);
7275 if (r)
7276 return r;
d28bc9dd 7277 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7278 kvm_mmu_setup(vcpu);
e9b11c17 7279 vcpu_put(vcpu);
26e5215f 7280 return r;
e9b11c17
ZX		 7281}
7282
31928aa5 7283void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7284{
8fe8ab46 7285 struct msr_data msr;
332967a3 7286 struct kvm *kvm = vcpu->kvm;
42897d86 7287
31928aa5
DD		 7288 if (vcpu_load(vcpu))
7289 return;
8fe8ab46
WA		 7290 msr.data = 0x0;
7291 msr.index = MSR_IA32_TSC;
7292 msr.host_initiated = true;
7293 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7294 vcpu_put(vcpu);
7295
630994b3
MT		 7296 if (!kvmclock_periodic_sync)
7297 return;
7298
332967a3
AJ		 7299 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7300 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7301}
7302
d40ccc62 7303void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7304{
9fc77441 7305 int r;
344d9588
GN		 7306 vcpu->arch.apf.msr_val = 0;
7307
9fc77441
MT		 7308 r = vcpu_load(vcpu);
7309 BUG_ON(r);
e9b11c17
ZX		 7310 kvm_mmu_unload(vcpu);
7311 vcpu_put(vcpu);
7312
7313 kvm_x86_ops->vcpu_free(vcpu);
7314}
7315
d28bc9dd 7316void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7317{
e69fab5d
PB		 7318 vcpu->arch.hflags = 0;
7319
7460fb4a
AK		 7320 atomic_set(&vcpu->arch.nmi_queued, 0);
7321 vcpu->arch.nmi_pending = 0;
448fa4a9 7322 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7323 kvm_clear_interrupt_queue(vcpu);
7324 kvm_clear_exception_queue(vcpu);
448fa4a9 7325
42dbaa5a 7326 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7327 kvm_update_dr0123(vcpu);
6f43ed01 7328 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7329 kvm_update_dr6(vcpu);
42dbaa5a 7330 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7331 kvm_update_dr7(vcpu);
42dbaa5a 7332
1119022c
NA		 7333 vcpu->arch.cr2 = 0;
7334
3842d135 7335 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7336 vcpu->arch.apf.msr_val = 0;
c9aaa895 7337 vcpu->arch.st.msr_val = 0;
3842d135 7338
12f9a48f
GC		 7339 kvmclock_reset(vcpu);
7340
af585b92
GN		 7341 kvm_clear_async_pf_completion_queue(vcpu);
7342 kvm_async_pf_hash_reset(vcpu);
7343 vcpu->arch.apf.halted = false;
3842d135 7344
64d60670 7345 if (!init_event) {
d28bc9dd 7346 kvm_pmu_reset(vcpu);
64d60670
PB		 7347 vcpu->arch.smbase = 0x30000;
7348 }
f5132b01 7349
66f7b72e
JS		 7350 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7351 vcpu->arch.regs_avail = ~0;
7352 vcpu->arch.regs_dirty = ~0;
7353
d28bc9dd 7354 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7355}
7356
2b4a273b 7357void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7358{
7359 struct kvm_segment cs;
7360
7361 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7362 cs.selector = vector << 8;
7363 cs.base = vector << 12;
7364 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7365 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7366}
7367
13a34e06 7368int kvm_arch_hardware_enable(void)
e9b11c17 7369{
ca84d1a2
ZA		 7370 struct kvm *kvm;
7371 struct kvm_vcpu *vcpu;
7372 int i;
0dd6a6ed
ZA		 7373 int ret;
7374 u64 local_tsc;
7375 u64 max_tsc = 0;
7376 bool stable, backwards_tsc = false;
18863bdd
AK		 7377
7378 kvm_shared_msr_cpu_online();
13a34e06 7379 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7380 if (ret != 0)
7381 return ret;
7382
4ea1636b 7383 local_tsc = rdtsc();
0dd6a6ed
ZA		 7384 stable = !check_tsc_unstable();
7385 list_for_each_entry(kvm, &vm_list, vm_list) {
7386 kvm_for_each_vcpu(i, vcpu, kvm) {
7387 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7388 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7389 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7390 backwards_tsc = true;
7391 if (vcpu->arch.last_host_tsc > max_tsc)
7392 max_tsc = vcpu->arch.last_host_tsc;
7393 }
7394 }
7395 }
7396
7397 /*
7398 * Sometimes, even reliable TSCs go backwards. This happens on
7399 * platforms that reset TSC during suspend or hibernate actions, but
7400 * maintain synchronization. We must compensate. Fortunately, we can
7401 * detect that condition here, which happens early in CPU bringup,
7402 * before any KVM threads can be running. Unfortunately, we can't
7403 * bring the TSCs fully up to date with real time, as we aren't yet far
7404 * enough into CPU bringup that we know how much real time has actually
7405 * elapsed; our helper function, get_kernel_ns() will be using boot
7406 * variables that haven't been updated yet.
7407 *
7408 * So we simply find the maximum observed TSC above, then record the
7409 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7410 * the adjustment will be applied. Note that we accumulate
7411 * adjustments, in case multiple suspend cycles happen before some VCPU
7412 * gets a chance to run again. In the event that no KVM threads get a
7413 * chance to run, we will miss the entire elapsed period, as we'll have
7414 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7415 * loose cycle time. This isn't too big a deal, since the loss will be
7416 * uniform across all VCPUs (not to mention the scenario is extremely
7417 * unlikely). It is possible that a second hibernate recovery happens
7418 * much faster than a first, causing the observed TSC here to be
7419 * smaller; this would require additional padding adjustment, which is
7420 * why we set last_host_tsc to the local tsc observed here.
7421 *
7422 * N.B. - this code below runs only on platforms with reliable TSC,
7423 * as that is the only way backwards_tsc is set above. Also note
7424 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7425 * have the same delta_cyc adjustment applied if backwards_tsc
7426 * is detected. Note further, this adjustment is only done once,
7427 * as we reset last_host_tsc on all VCPUs to stop this from being
7428 * called multiple times (one for each physical CPU bringup).
7429 *
4a969980 7430 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7431 * will be compensated by the logic in vcpu_load, which sets the TSC to
7432 * catchup mode. This will catchup all VCPUs to real time, but cannot
7433 * guarantee that they stay in perfect synchronization.
7434 */
7435 if (backwards_tsc) {
7436 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7437 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7438 list_for_each_entry(kvm, &vm_list, vm_list) {
7439 kvm_for_each_vcpu(i, vcpu, kvm) {
7440 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7441 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7442 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7443 }
7444
7445 /*
7446 * We have to disable TSC offset matching.. if you were
7447 * booting a VM while issuing an S4 host suspend....
7448 * you may have some problem. Solving this issue is
7449 * left as an exercise to the reader.
7450 */
7451 kvm->arch.last_tsc_nsec = 0;
7452 kvm->arch.last_tsc_write = 0;
7453 }
7454
7455 }
7456 return 0;
e9b11c17
ZX		 7457}
7458
13a34e06 7459void kvm_arch_hardware_disable(void)
e9b11c17 7460{
13a34e06
RK		 7461 kvm_x86_ops->hardware_disable();
7462 drop_user_return_notifiers();
e9b11c17
ZX		 7463}
7464
7465int kvm_arch_hardware_setup(void)
7466{
9e9c3fe4
NA		 7467 int r;
7468
7469 r = kvm_x86_ops->hardware_setup();
7470 if (r != 0)
7471 return r;
7472
35181e86
HZ		 7473 if (kvm_has_tsc_control) {
7474 /*
7475 * Make sure the user can only configure tsc_khz values that
7476 * fit into a signed integer.
7477 * A min value is not calculated needed because it will always
7478 * be 1 on all machines.
7479 */
7480 u64 max = min(0x7fffffffULL,
7481 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7482 kvm_max_guest_tsc_khz = max;
7483
ad721883 7484 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7485 }
ad721883 7486
9e9c3fe4
NA		 7487 kvm_init_msr_list();
7488 return 0;
e9b11c17
ZX		 7489}
7490
7491void kvm_arch_hardware_unsetup(void)
7492{
7493 kvm_x86_ops->hardware_unsetup();
7494}
7495
7496void kvm_arch_check_processor_compat(void *rtn)
7497{
7498 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7499}
7500
7501bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7502{
7503 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7504}
7505EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7506
7507bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7508{
7509 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7510}
7511
3e515705
AK		 7512bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7513{
35754c98 7514 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7515}
7516
54e9818f
GN		 7517struct static_key kvm_no_apic_vcpu __read_mostly;
7518
e9b11c17
ZX		 7519int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7520{
7521 struct page *page;
7522 struct kvm *kvm;
7523 int r;
7524
7525 BUG_ON(vcpu->kvm == NULL);
7526 kvm = vcpu->kvm;
7527
6aef266c 7528 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7529 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7530 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7531 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7532 else
a4535290 7533 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7534
7535 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7536 if (!page) {
7537 r = -ENOMEM;
7538 goto fail;
7539 }
ad312c7c 7540 vcpu->arch.pio_data = page_address(page);
e9b11c17 7541
cc578287 7542 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7543
e9b11c17
ZX		 7544 r = kvm_mmu_create(vcpu);
7545 if (r < 0)
7546 goto fail_free_pio_data;
7547
7548 if (irqchip_in_kernel(kvm)) {
7549 r = kvm_create_lapic(vcpu);
7550 if (r < 0)
7551 goto fail_mmu_destroy;
54e9818f
GN		 7552 } else
7553 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7554
890ca9ae
HY		 7555 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7556 GFP_KERNEL);
7557 if (!vcpu->arch.mce_banks) {
7558 r = -ENOMEM;
443c39bc 7559 goto fail_free_lapic;
890ca9ae
HY		 7560 }
7561 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7562
f1797359
WY		 7563 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7564 r = -ENOMEM;
f5f48ee1 7565 goto fail_free_mce_banks;
f1797359 7566 }
f5f48ee1 7567
0ee6a517 7568 fx_init(vcpu);
66f7b72e 7569
ba904635 7570 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7571 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7572
7573 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7574 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7575
5a4f55cd
EK		 7576 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7577
74545705
RK		 7578 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7579
af585b92 7580 kvm_async_pf_hash_reset(vcpu);
f5132b01 7581 kvm_pmu_init(vcpu);
af585b92 7582
1c1a9ce9
SR		 7583 vcpu->arch.pending_external_vector = -1;
7584
e9b11c17 7585 return 0;
0ee6a517 7586
f5f48ee1
SY		 7587fail_free_mce_banks:
7588 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7589fail_free_lapic:
7590 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7591fail_mmu_destroy:
7592 kvm_mmu_destroy(vcpu);
7593fail_free_pio_data:
ad312c7c 7594 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7595fail:
7596 return r;
7597}
7598
7599void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7600{
f656ce01
MT		 7601 int idx;
7602
f5132b01 7603 kvm_pmu_destroy(vcpu);
36cb93fd 7604 kfree(vcpu->arch.mce_banks);
e9b11c17 7605 kvm_free_lapic(vcpu);
f656ce01 7606 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7607 kvm_mmu_destroy(vcpu);
f656ce01 7608 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7609 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7610 if (!lapic_in_kernel(vcpu))
54e9818f 7611 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7612}
d19a9cd2 7613
e790d9ef
RK		 7614void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7615{
ae97a3b8 7616 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7617}
7618
e08b9637 7619int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7620{
e08b9637
CO		 7621 if (type)
7622 return -EINVAL;
7623
6ef768fa 7624 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7625 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7626 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7627 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7628 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7629
5550af4d
SY		 7630 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7631 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7632 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7633 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7634 &kvm->arch.irq_sources_bitmap);
5550af4d 7635
038f8c11 7636 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7637 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7638 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7639
7640 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7641
7e44e449 7642 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7643 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7644
d89f5eff 7645 return 0;
d19a9cd2
ZX		 7646}
7647
7648static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7649{
9fc77441
MT		 7650 int r;
7651 r = vcpu_load(vcpu);
7652 BUG_ON(r);
d19a9cd2
ZX		 7653 kvm_mmu_unload(vcpu);
7654 vcpu_put(vcpu);
7655}
7656
7657static void kvm_free_vcpus(struct kvm *kvm)
7658{
7659 unsigned int i;
988a2cae 7660 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7661
7662 /*
7663 * Unpin any mmu pages first.
7664 */
af585b92
GN		 7665 kvm_for_each_vcpu(i, vcpu, kvm) {
7666 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7667 kvm_unload_vcpu_mmu(vcpu);
af585b92 7668 }
988a2cae
GN		 7669 kvm_for_each_vcpu(i, vcpu, kvm)
7670 kvm_arch_vcpu_free(vcpu);
7671
7672 mutex_lock(&kvm->lock);
7673 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7674 kvm->vcpus[i] = NULL;
d19a9cd2 7675
988a2cae
GN		 7676 atomic_set(&kvm->online_vcpus, 0);
7677 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7678}
7679
ad8ba2cd
SY		 7680void kvm_arch_sync_events(struct kvm *kvm)
7681{
332967a3 7682 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7683 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7684 kvm_free_all_assigned_devices(kvm);
aea924f6 7685 kvm_free_pit(kvm);
ad8ba2cd
SY		 7686}
7687
1d8007bd 7688int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7689{
7690 int i, r;
25188b99 7691 unsigned long hva;
f0d648bd
PB		 7692 struct kvm_memslots *slots = kvm_memslots(kvm);
7693 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7694
7695 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7696 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7697 return -EINVAL;
9da0e4d5 7698
f0d648bd
PB		 7699 slot = id_to_memslot(slots, id);
7700 if (size) {
7701 if (WARN_ON(slot->npages))
7702 return -EEXIST;
7703
7704 /*
7705 * MAP_SHARED to prevent internal slot pages from being moved
7706 * by fork()/COW.
7707 */
7708 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7709 MAP_SHARED | MAP_ANONYMOUS, 0);
7710 if (IS_ERR((void *)hva))
7711 return PTR_ERR((void *)hva);
7712 } else {
7713 if (!slot->npages)
7714 return 0;
7715
7716 hva = 0;
7717 }
7718
7719 old = *slot;
9da0e4d5 7720 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7721 struct kvm_userspace_memory_region m;
9da0e4d5 7722
1d8007bd
PB		 7723 m.slot = id | (i << 16);
7724 m.flags = 0;
7725 m.guest_phys_addr = gpa;
f0d648bd 7726 m.userspace_addr = hva;
1d8007bd 7727 m.memory_size = size;
9da0e4d5
PB		 7728 r = __kvm_set_memory_region(kvm, &m);
7729 if (r < 0)
7730 return r;
7731 }
7732
f0d648bd
PB		 7733 if (!size) {
7734 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7735 WARN_ON(r < 0);
7736 }
7737
9da0e4d5
PB		 7738 return 0;
7739}
7740EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7741
1d8007bd 7742int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7743{
7744 int r;
7745
7746 mutex_lock(&kvm->slots_lock);
1d8007bd 7747 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7748 mutex_unlock(&kvm->slots_lock);
7749
7750 return r;
7751}
7752EXPORT_SYMBOL_GPL(x86_set_memory_region);
7753
d19a9cd2
ZX		 7754void kvm_arch_destroy_vm(struct kvm *kvm)
7755{
27469d29
AH		 7756 if (current->mm == kvm->mm) {
7757 /*
7758 * Free memory regions allocated on behalf of userspace,
7759 * unless the the memory map has changed due to process exit
7760 * or fd copying.
7761 */
1d8007bd
PB		 7762 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7763 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7764 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7765 }
6eb55818 7766 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7767 kfree(kvm->arch.vpic);
7768 kfree(kvm->arch.vioapic);
d19a9cd2 7769 kvm_free_vcpus(kvm);
1e08ec4a 7770 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7771}
0de10343 7772
5587027c 7773void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7774 struct kvm_memory_slot *dont)
7775{
7776 int i;
7777
d89cc617
TY		 7778 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7779 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7780 kvfree(free->arch.rmap[i]);
d89cc617 7781 free->arch.rmap[i] = NULL;
77d11309 7782 }
d89cc617
TY		 7783 if (i == 0)
7784 continue;
7785
7786 if (!dont || free->arch.lpage_info[i - 1] !=
7787 dont->arch.lpage_info[i - 1]) {
548ef284 7788 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7789 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7790 }
7791 }
7792}
7793
5587027c
AK		 7794int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7795 unsigned long npages)
db3fe4eb
TY		 7796{
7797 int i;
7798
d89cc617 7799 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7800 unsigned long ugfn;
7801 int lpages;
d89cc617 7802 int level = i + 1;
db3fe4eb
TY		 7803
7804 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7805 slot->base_gfn, level) + 1;
7806
d89cc617
TY		 7807 slot->arch.rmap[i] =
7808 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7809 if (!slot->arch.rmap[i])
77d11309 7810 goto out_free;
d89cc617
TY		 7811 if (i == 0)
7812 continue;
77d11309 7813
d89cc617
TY		 7814 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7815 sizeof(*slot->arch.lpage_info[i - 1]));
7816 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7817 goto out_free;
7818
7819 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7820 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7821 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7822 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7823 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7824 /*
7825 * If the gfn and userspace address are not aligned wrt each
7826 * other, or if explicitly asked to, disable large page
7827 * support for this slot
7828 */
7829 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7830 !kvm_largepages_enabled()) {
7831 unsigned long j;
7832
7833 for (j = 0; j < lpages; ++j)
d89cc617 7834 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7835 }
7836 }
7837
7838 return 0;
7839
7840out_free:
d89cc617 7841 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7842 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7843 slot->arch.rmap[i] = NULL;
7844 if (i == 0)
7845 continue;
7846
548ef284 7847 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7848 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7849 }
7850 return -ENOMEM;
7851}
7852
15f46015 7853void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7854{
e6dff7d1
TY		 7855 /*
7856 * memslots->generation has been incremented.
7857 * mmio generation may have reached its maximum value.
7858 */
54bf36aa 7859 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7860}
7861
f7784b8e
MT		 7862int kvm_arch_prepare_memory_region(struct kvm *kvm,
7863 struct kvm_memory_slot *memslot,
09170a49 7864 const struct kvm_userspace_memory_region *mem,
7b6195a9 7865 enum kvm_mr_change change)
0de10343 7866{
f7784b8e
MT		 7867 return 0;
7868}
7869
88178fd4
KH		 7870static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7871 struct kvm_memory_slot *new)
7872{
7873 /* Still write protect RO slot */
7874 if (new->flags & KVM_MEM_READONLY) {
7875 kvm_mmu_slot_remove_write_access(kvm, new);
7876 return;
7877 }
7878
7879 /*
7880 * Call kvm_x86_ops dirty logging hooks when they are valid.
7881 *
7882 * kvm_x86_ops->slot_disable_log_dirty is called when:
7883 *
7884 * - KVM_MR_CREATE with dirty logging is disabled
7885 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7886 *
7887 * The reason is, in case of PML, we need to set D-bit for any slots
7888 * with dirty logging disabled in order to eliminate unnecessary GPA
7889 * logging in PML buffer (and potential PML buffer full VMEXT). This
7890 * guarantees leaving PML enabled during guest's lifetime won't have
7891 * any additonal overhead from PML when guest is running with dirty
7892 * logging disabled for memory slots.
7893 *
7894 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7895 * to dirty logging mode.
7896 *
7897 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7898 *
7899 * In case of write protect:
7900 *
7901 * Write protect all pages for dirty logging.
7902 *
7903 * All the sptes including the large sptes which point to this
7904 * slot are set to readonly. We can not create any new large
7905 * spte on this slot until the end of the logging.
7906 *
7907 * See the comments in fast_page_fault().
7908 */
7909 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7910 if (kvm_x86_ops->slot_enable_log_dirty)
7911 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7912 else
7913 kvm_mmu_slot_remove_write_access(kvm, new);
7914 } else {
7915 if (kvm_x86_ops->slot_disable_log_dirty)
7916 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7917 }
7918}
7919
f7784b8e 7920void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7921 const struct kvm_userspace_memory_region *mem,
8482644a 7922 const struct kvm_memory_slot *old,
f36f3f28 7923 const struct kvm_memory_slot *new,
8482644a 7924 enum kvm_mr_change change)
f7784b8e 7925{
8482644a 7926 int nr_mmu_pages = 0;
f7784b8e 7927
48c0e4e9
XG		 7928 if (!kvm->arch.n_requested_mmu_pages)
7929 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7930
48c0e4e9 7931 if (nr_mmu_pages)
0de10343 7932 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7933
3ea3b7fa
WL		 7934 /*
7935 * Dirty logging tracks sptes in 4k granularity, meaning that large
7936 * sptes have to be split. If live migration is successful, the guest
7937 * in the source machine will be destroyed and large sptes will be
7938 * created in the destination. However, if the guest continues to run
7939 * in the source machine (for example if live migration fails), small
7940 * sptes will remain around and cause bad performance.
7941 *
7942 * Scan sptes if dirty logging has been stopped, dropping those
7943 * which can be collapsed into a single large-page spte. Later
7944 * page faults will create the large-page sptes.
7945 */
7946 if ((change != KVM_MR_DELETE) &&
7947 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7948 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7949 kvm_mmu_zap_collapsible_sptes(kvm, new);
7950
c972f3b1 7951 /*
88178fd4 7952 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7953 *
88178fd4
KH		 7954 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7955 * been zapped so no dirty logging staff is needed for old slot. For
7956 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7957 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7958 *
7959 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7960 */
88178fd4 7961 if (change != KVM_MR_DELETE)
f36f3f28 7962 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7963}
1d737c8a 7964
2df72e9b 7965void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7966{
6ca18b69 7967 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7968}
7969
2df72e9b
MT		 7970void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7971 struct kvm_memory_slot *slot)
7972{
6ca18b69 7973 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7974}
7975
5d9bc648
PB		 7976static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
7977{
7978 if (!list_empty_careful(&vcpu->async_pf.done))
7979 return true;
7980
7981 if (kvm_apic_has_events(vcpu))
7982 return true;
7983
7984 if (vcpu->arch.pv.pv_unhalted)
7985 return true;
7986
7987 if (atomic_read(&vcpu->arch.nmi_queued))
7988 return true;
7989
73917739
PB		 7990 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
7991 return true;
7992
5d9bc648
PB		 7993 if (kvm_arch_interrupt_allowed(vcpu) &&
7994 kvm_cpu_has_interrupt(vcpu))
7995 return true;
7996
7997 return false;
7998}
7999
1d737c8a
ZX		 8000int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8001{
b6b8a145
JK		 8002 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8003 kvm_x86_ops->check_nested_events(vcpu, false);
8004
5d9bc648 8005 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8006}
5736199a 8007
b6d33834 8008int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8009{
b6d33834 8010 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8011}
78646121
GN		 8012
8013int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8014{
8015 return kvm_x86_ops->interrupt_allowed(vcpu);
8016}
229456fc 8017
82b32774 8018unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8019{
82b32774
NA		 8020 if (is_64_bit_mode(vcpu))
8021 return kvm_rip_read(vcpu);
8022 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8023 kvm_rip_read(vcpu));
8024}
8025EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8026
82b32774
NA		 8027bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8028{
8029 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8030}
8031EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8032
94fe45da
JK		 8033unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8034{
8035 unsigned long rflags;
8036
8037 rflags = kvm_x86_ops->get_rflags(vcpu);
8038 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8039 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8040 return rflags;
8041}
8042EXPORT_SYMBOL_GPL(kvm_get_rflags);
8043
6addfc42 8044static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8045{
8046 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8047 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8048 rflags |= X86_EFLAGS_TF;
94fe45da 8049 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8050}
8051
8052void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8053{
8054 __kvm_set_rflags(vcpu, rflags);
3842d135 8055 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8056}
8057EXPORT_SYMBOL_GPL(kvm_set_rflags);
8058
56028d08
GN		 8059void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8060{
8061 int r;
8062
fb67e14f 8063 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8064 work->wakeup_all)
56028d08
GN		 8065 return;
8066
8067 r = kvm_mmu_reload(vcpu);
8068 if (unlikely(r))
8069 return;
8070
fb67e14f
XG		 8071 if (!vcpu->arch.mmu.direct_map &&
8072 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8073 return;
8074
56028d08
GN		 8075 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8076}
8077
af585b92
GN		 8078static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8079{
8080 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8081}
8082
8083static inline u32 kvm_async_pf_next_probe(u32 key)
8084{
8085 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8086}
8087
8088static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8089{
8090 u32 key = kvm_async_pf_hash_fn(gfn);
8091
8092 while (vcpu->arch.apf.gfns[key] != ~0)
8093 key = kvm_async_pf_next_probe(key);
8094
8095 vcpu->arch.apf.gfns[key] = gfn;
8096}
8097
8098static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8099{
8100 int i;
8101 u32 key = kvm_async_pf_hash_fn(gfn);
8102
8103 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8104 (vcpu->arch.apf.gfns[key] != gfn &&
8105 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8106 key = kvm_async_pf_next_probe(key);
8107
8108 return key;
8109}
8110
8111bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8112{
8113 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8114}
8115
8116static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8117{
8118 u32 i, j, k;
8119
8120 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8121 while (true) {
8122 vcpu->arch.apf.gfns[i] = ~0;
8123 do {
8124 j = kvm_async_pf_next_probe(j);
8125 if (vcpu->arch.apf.gfns[j] == ~0)
8126 return;
8127 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8128 /*
8129 * k lies cyclically in ]i,j]
8130 * | i.k.j |
8131 * |....j i.k.| or |.k..j i...|
8132 */
8133 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8134 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8135 i = j;
8136 }
8137}
8138
7c90705b
GN		 8139static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8140{
8141
8142 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8143 sizeof(val));
8144}
8145
af585b92
GN		 8146void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8147 struct kvm_async_pf *work)
8148{
6389ee94
AK		 8149 struct x86_exception fault;
8150
7c90705b 8151 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8152 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8153
8154 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8155 (vcpu->arch.apf.send_user_only &&
8156 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8157 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8158 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8159 fault.vector = PF_VECTOR;
8160 fault.error_code_valid = true;
8161 fault.error_code = 0;
8162 fault.nested_page_fault = false;
8163 fault.address = work->arch.token;
8164 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8165 }
af585b92
GN		 8166}
8167
8168void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8169 struct kvm_async_pf *work)
8170{
6389ee94
AK		 8171 struct x86_exception fault;
8172
7c90705b 8173 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8174 if (work->wakeup_all)
7c90705b
GN		 8175 work->arch.token = ~0; /* broadcast wakeup */
8176 else
8177 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8178
8179 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8180 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8181 fault.vector = PF_VECTOR;
8182 fault.error_code_valid = true;
8183 fault.error_code = 0;
8184 fault.nested_page_fault = false;
8185 fault.address = work->arch.token;
8186 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8187 }
e6d53e3b 8188 vcpu->arch.apf.halted = false;
a4fa1635 8189 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8190}
8191
8192bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8193{
8194 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8195 return true;
8196 else
8197 return !kvm_event_needs_reinjection(vcpu) &&
8198 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8199}
8200
5544eb9b
PB		 8201void kvm_arch_start_assignment(struct kvm *kvm)
8202{
8203 atomic_inc(&kvm->arch.assigned_device_count);
8204}
8205EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8206
8207void kvm_arch_end_assignment(struct kvm *kvm)
8208{
8209 atomic_dec(&kvm->arch.assigned_device_count);
8210}
8211EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8212
8213bool kvm_arch_has_assigned_device(struct kvm *kvm)
8214{
8215 return atomic_read(&kvm->arch.assigned_device_count);
8216}
8217EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8218
e0f0bbc5
AW		 8219void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8220{
8221 atomic_inc(&kvm->arch.noncoherent_dma_count);
8222}
8223EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8224
8225void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8226{
8227 atomic_dec(&kvm->arch.noncoherent_dma_count);
8228}
8229EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8230
8231bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8232{
8233 return atomic_read(&kvm->arch.noncoherent_dma_count);
8234}
8235EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8236
87276880
FW		 8237int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8238 struct irq_bypass_producer *prod)
8239{
8240 struct kvm_kernel_irqfd *irqfd =
8241 container_of(cons, struct kvm_kernel_irqfd, consumer);
8242
8243 if (kvm_x86_ops->update_pi_irte) {
8244 irqfd->producer = prod;
8245 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8246 prod->irq, irqfd->gsi, 1);
8247 }
8248
8249 return -EINVAL;
8250}
8251
8252void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8253 struct irq_bypass_producer *prod)
8254{
8255 int ret;
8256 struct kvm_kernel_irqfd *irqfd =
8257 container_of(cons, struct kvm_kernel_irqfd, consumer);
8258
8259 if (!kvm_x86_ops->update_pi_irte) {
8260 WARN_ON(irqfd->producer != NULL);
8261 return;
8262 }
8263
8264 WARN_ON(irqfd->producer != prod);
8265 irqfd->producer = NULL;
8266
8267 /*
8268 * When producer of consumer is unregistered, we change back to
8269 * remapped mode, so we can re-use the current implementation
8270 * when the irq is masked/disabed or the consumer side (KVM
8271 * int this case doesn't want to receive the interrupts.
8272 */
8273 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8274 if (ret)
8275 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8276 " fails: %d\n", irqfd->consumer.token, ret);
8277}
8278
8279int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8280 uint32_t guest_irq, bool set)
8281{
8282 if (!kvm_x86_ops->update_pi_irte)
8283 return -EINVAL;
8284
8285 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8286}
8287
229456fc 8288EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8289EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8290EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8291EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8292EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8293EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8294EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8295EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8296EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8297EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8298EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8299EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8300EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8301EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8302EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8303EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8304EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
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