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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
88197e6a | 21 | #include "ioapic.h" |
1d737c8a | 22 | #include "mmu.h" |
7837699f | 23 | #include "i8254.h" |
37817f29 | 24 | #include "tss.h" |
5fdbf976 | 25 | #include "kvm_cache_regs.h" |
2f728d66 | 26 | #include "kvm_emulate.h" |
26eef70c | 27 | #include "x86.h" |
00b27a3e | 28 | #include "cpuid.h" |
474a5bb9 | 29 | #include "pmu.h" |
e83d5887 | 30 | #include "hyperv.h" |
8df14af4 | 31 | #include "lapic.h" |
23200b7a | 32 | #include "xen.h" |
313a3dc7 | 33 | |
18068523 | 34 | #include <linux/clocksource.h> |
4d5c5d0f | 35 | #include <linux/interrupt.h> |
313a3dc7 CO |
36 | #include <linux/kvm.h> |
37 | #include <linux/fs.h> | |
38 | #include <linux/vmalloc.h> | |
1767e931 PG |
39 | #include <linux/export.h> |
40 | #include <linux/moduleparam.h> | |
0de10343 | 41 | #include <linux/mman.h> |
2bacc55c | 42 | #include <linux/highmem.h> |
19de40a8 | 43 | #include <linux/iommu.h> |
62c476c7 | 44 | #include <linux/intel-iommu.h> |
c8076604 | 45 | #include <linux/cpufreq.h> |
18863bdd | 46 | #include <linux/user-return-notifier.h> |
a983fb23 | 47 | #include <linux/srcu.h> |
5a0e3ad6 | 48 | #include <linux/slab.h> |
ff9d07a0 | 49 | #include <linux/perf_event.h> |
7bee342a | 50 | #include <linux/uaccess.h> |
af585b92 | 51 | #include <linux/hash.h> |
a1b60c1c | 52 | #include <linux/pci.h> |
16e8d74d MT |
53 | #include <linux/timekeeper_internal.h> |
54 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
55 | #include <linux/kvm_irqfd.h> |
56 | #include <linux/irqbypass.h> | |
3905f9ad | 57 | #include <linux/sched/stat.h> |
0c5f81da | 58 | #include <linux/sched/isolation.h> |
d0ec49d4 | 59 | #include <linux/mem_encrypt.h> |
72c3c0fe | 60 | #include <linux/entry-kvm.h> |
7d62874f | 61 | #include <linux/suspend.h> |
3905f9ad | 62 | |
aec51dc4 | 63 | #include <trace/events/kvm.h> |
2ed152af | 64 | |
24f1e32c | 65 | #include <asm/debugreg.h> |
d825ed0a | 66 | #include <asm/msr.h> |
a5f61300 | 67 | #include <asm/desc.h> |
890ca9ae | 68 | #include <asm/mce.h> |
784a4661 | 69 | #include <asm/pkru.h> |
f89e32e0 | 70 | #include <linux/kernel_stat.h> |
78f7f1e5 | 71 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 72 | #include <asm/pvclock.h> |
217fc9cf | 73 | #include <asm/div64.h> |
efc64404 | 74 | #include <asm/irq_remapping.h> |
b0c39dc6 | 75 | #include <asm/mshyperv.h> |
0092e434 | 76 | #include <asm/hypervisor.h> |
9715092f | 77 | #include <asm/tlbflush.h> |
bf8c55d8 | 78 | #include <asm/intel_pt.h> |
b3dc0695 | 79 | #include <asm/emulate_prefix.h> |
fe7e9488 | 80 | #include <asm/sgx.h> |
dd2cb348 | 81 | #include <clocksource/hyperv_timer.h> |
043405e1 | 82 | |
d1898b73 DH |
83 | #define CREATE_TRACE_POINTS |
84 | #include "trace.h" | |
85 | ||
313a3dc7 | 86 | #define MAX_IO_MSRS 256 |
890ca9ae | 87 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
88 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
89 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 90 | |
0f65dd70 | 91 | #define emul_to_vcpu(ctxt) \ |
c9b8b07c | 92 | ((struct kvm_vcpu *)(ctxt)->vcpu) |
0f65dd70 | 93 | |
50a37eb4 JR |
94 | /* EFER defaults: |
95 | * - enable syscall per default because its emulated by KVM | |
96 | * - enable LME and LMA per default on 64 bit KVM | |
97 | */ | |
98 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
99 | static |
100 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 101 | #else |
1260edbe | 102 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 103 | #endif |
313a3dc7 | 104 | |
b11306b5 SC |
105 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
106 | ||
0dbb1123 AK |
107 | #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) |
108 | ||
c519265f RK |
109 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
110 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 111 | |
cb142eb7 | 112 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 113 | static void process_nmi(struct kvm_vcpu *vcpu); |
1f7becf1 | 114 | static void process_smi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 115 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 116 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
117 | static void store_regs(struct kvm_vcpu *vcpu); |
118 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 119 | |
6dba9403 ML |
120 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); |
121 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); | |
122 | ||
afaf0b2f | 123 | struct kvm_x86_ops kvm_x86_ops __read_mostly; |
5fdbf976 | 124 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 125 | |
9af5471b JB |
126 | #define KVM_X86_OP(func) \ |
127 | DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ | |
128 | *(((struct kvm_x86_ops *)0)->func)); | |
129 | #define KVM_X86_OP_NULL KVM_X86_OP | |
130 | #include <asm/kvm-x86-ops.h> | |
131 | EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); | |
132 | EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); | |
133 | EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); | |
134 | ||
893590c7 | 135 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 136 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 137 | |
d855066f | 138 | bool __read_mostly report_ignored_msrs = true; |
fab0aa3b | 139 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); |
d855066f | 140 | EXPORT_SYMBOL_GPL(report_ignored_msrs); |
fab0aa3b | 141 | |
4c27625b | 142 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
143 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
144 | ||
630994b3 MT |
145 | static bool __read_mostly kvmclock_periodic_sync = true; |
146 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
147 | ||
893590c7 | 148 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 149 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 150 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 151 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
152 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
153 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
154 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
155 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
156 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
157 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
fe6b6bc8 CQ |
158 | bool __read_mostly kvm_has_bus_lock_exit; |
159 | EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); | |
92a1f12d | 160 | |
cc578287 | 161 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 162 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
163 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
164 | ||
c3941d9e SC |
165 | /* |
166 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
d9f6e12f | 167 | * adaptive tuning starting from default advancement of 1000ns. '0' disables |
c3941d9e | 168 | * advancement entirely. Any other value is used as-is and disables adaptive |
d9f6e12f | 169 | * tuning, i.e. allows privileged userspace to set an exact advancement time. |
c3941d9e SC |
170 | */ |
171 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 172 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 173 | |
52004014 FW |
174 | static bool __read_mostly vector_hashing = true; |
175 | module_param(vector_hashing, bool, S_IRUGO); | |
176 | ||
c4ae60e4 LA |
177 | bool __read_mostly enable_vmware_backdoor = false; |
178 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
179 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
180 | ||
6c86eedc WL |
181 | static bool __read_mostly force_emulation_prefix = false; |
182 | module_param(force_emulation_prefix, bool, S_IRUGO); | |
183 | ||
0c5f81da WL |
184 | int __read_mostly pi_inject_timer = -1; |
185 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
186 | ||
7e34fbd0 SC |
187 | /* |
188 | * Restoring the host value for MSRs that are only consumed when running in | |
189 | * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU | |
190 | * returns to userspace, i.e. the kernel can run with the guest's value. | |
191 | */ | |
192 | #define KVM_MAX_NR_USER_RETURN_MSRS 16 | |
18863bdd | 193 | |
7e34fbd0 | 194 | struct kvm_user_return_msrs { |
18863bdd AK |
195 | struct user_return_notifier urn; |
196 | bool registered; | |
7e34fbd0 | 197 | struct kvm_user_return_msr_values { |
2bf78fa7 SY |
198 | u64 host; |
199 | u64 curr; | |
7e34fbd0 | 200 | } values[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
201 | }; |
202 | ||
9cc39a5a SC |
203 | u32 __read_mostly kvm_nr_uret_msrs; |
204 | EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); | |
205 | static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; | |
7e34fbd0 | 206 | static struct kvm_user_return_msrs __percpu *user_return_msrs; |
18863bdd | 207 | |
cfc48181 SC |
208 | #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ |
209 | | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | |
210 | | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | |
211 | | XFEATURE_MASK_PKRU) | |
212 | ||
91661989 SC |
213 | u64 __read_mostly host_efer; |
214 | EXPORT_SYMBOL_GPL(host_efer); | |
215 | ||
b96e6506 | 216 | bool __read_mostly allow_smaller_maxphyaddr = 0; |
3edd6839 MG |
217 | EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); |
218 | ||
fdf513e3 VK |
219 | bool __read_mostly enable_apicv = true; |
220 | EXPORT_SYMBOL_GPL(enable_apicv); | |
221 | ||
86137773 TL |
222 | u64 __read_mostly host_xss; |
223 | EXPORT_SYMBOL_GPL(host_xss); | |
408e9a31 PB |
224 | u64 __read_mostly supported_xss; |
225 | EXPORT_SYMBOL_GPL(supported_xss); | |
139a12cf | 226 | |
fcfe1bae JZ |
227 | const struct _kvm_stats_desc kvm_vm_stats_desc[] = { |
228 | KVM_GENERIC_VM_STATS(), | |
229 | STATS_DESC_COUNTER(VM, mmu_shadow_zapped), | |
230 | STATS_DESC_COUNTER(VM, mmu_pte_write), | |
231 | STATS_DESC_COUNTER(VM, mmu_pde_zapped), | |
232 | STATS_DESC_COUNTER(VM, mmu_flooded), | |
233 | STATS_DESC_COUNTER(VM, mmu_recycled), | |
234 | STATS_DESC_COUNTER(VM, mmu_cache_miss), | |
235 | STATS_DESC_ICOUNTER(VM, mmu_unsync), | |
236 | STATS_DESC_ICOUNTER(VM, lpages), | |
237 | STATS_DESC_ICOUNTER(VM, nx_lpage_splits), | |
ec1cf69c | 238 | STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), |
bc9e9e67 | 239 | STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) |
fcfe1bae JZ |
240 | }; |
241 | static_assert(ARRAY_SIZE(kvm_vm_stats_desc) == | |
242 | sizeof(struct kvm_vm_stat) / sizeof(u64)); | |
243 | ||
244 | const struct kvm_stats_header kvm_vm_stats_header = { | |
245 | .name_size = KVM_STATS_NAME_SIZE, | |
246 | .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), | |
247 | .id_offset = sizeof(struct kvm_stats_header), | |
248 | .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, | |
249 | .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + | |
250 | sizeof(kvm_vm_stats_desc), | |
251 | }; | |
252 | ||
ce55c049 JZ |
253 | const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { |
254 | KVM_GENERIC_VCPU_STATS(), | |
255 | STATS_DESC_COUNTER(VCPU, pf_fixed), | |
256 | STATS_DESC_COUNTER(VCPU, pf_guest), | |
257 | STATS_DESC_COUNTER(VCPU, tlb_flush), | |
258 | STATS_DESC_COUNTER(VCPU, invlpg), | |
259 | STATS_DESC_COUNTER(VCPU, exits), | |
260 | STATS_DESC_COUNTER(VCPU, io_exits), | |
261 | STATS_DESC_COUNTER(VCPU, mmio_exits), | |
262 | STATS_DESC_COUNTER(VCPU, signal_exits), | |
263 | STATS_DESC_COUNTER(VCPU, irq_window_exits), | |
264 | STATS_DESC_COUNTER(VCPU, nmi_window_exits), | |
265 | STATS_DESC_COUNTER(VCPU, l1d_flush), | |
266 | STATS_DESC_COUNTER(VCPU, halt_exits), | |
267 | STATS_DESC_COUNTER(VCPU, request_irq_exits), | |
268 | STATS_DESC_COUNTER(VCPU, irq_exits), | |
269 | STATS_DESC_COUNTER(VCPU, host_state_reload), | |
270 | STATS_DESC_COUNTER(VCPU, fpu_reload), | |
271 | STATS_DESC_COUNTER(VCPU, insn_emulation), | |
272 | STATS_DESC_COUNTER(VCPU, insn_emulation_fail), | |
273 | STATS_DESC_COUNTER(VCPU, hypercalls), | |
274 | STATS_DESC_COUNTER(VCPU, irq_injections), | |
275 | STATS_DESC_COUNTER(VCPU, nmi_injections), | |
276 | STATS_DESC_COUNTER(VCPU, req_event), | |
277 | STATS_DESC_COUNTER(VCPU, nested_run), | |
278 | STATS_DESC_COUNTER(VCPU, directed_yield_attempted), | |
279 | STATS_DESC_COUNTER(VCPU, directed_yield_successful), | |
280 | STATS_DESC_ICOUNTER(VCPU, guest_mode) | |
281 | }; | |
282 | static_assert(ARRAY_SIZE(kvm_vcpu_stats_desc) == | |
283 | sizeof(struct kvm_vcpu_stat) / sizeof(u64)); | |
284 | ||
285 | const struct kvm_stats_header kvm_vcpu_stats_header = { | |
286 | .name_size = KVM_STATS_NAME_SIZE, | |
287 | .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), | |
288 | .id_offset = sizeof(struct kvm_stats_header), | |
289 | .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, | |
290 | .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + | |
291 | sizeof(kvm_vcpu_stats_desc), | |
292 | }; | |
293 | ||
2acf923e | 294 | u64 __read_mostly host_xcr0; |
cfc48181 SC |
295 | u64 __read_mostly supported_xcr0; |
296 | EXPORT_SYMBOL_GPL(supported_xcr0); | |
2acf923e | 297 | |
80fbd280 | 298 | static struct kmem_cache *x86_fpu_cache; |
b666a4b6 | 299 | |
c9b8b07c SC |
300 | static struct kmem_cache *x86_emulator_cache; |
301 | ||
6abe9c13 PX |
302 | /* |
303 | * When called, it means the previous get/set msr reached an invalid msr. | |
cc4cb017 | 304 | * Return true if we want to ignore/silent this failed msr access. |
6abe9c13 | 305 | */ |
d632826f | 306 | static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) |
6abe9c13 PX |
307 | { |
308 | const char *op = write ? "wrmsr" : "rdmsr"; | |
309 | ||
310 | if (ignore_msrs) { | |
311 | if (report_ignored_msrs) | |
d383b314 TI |
312 | kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", |
313 | op, msr, data); | |
6abe9c13 | 314 | /* Mask the error */ |
cc4cb017 | 315 | return true; |
6abe9c13 | 316 | } else { |
d383b314 TI |
317 | kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", |
318 | op, msr, data); | |
cc4cb017 | 319 | return false; |
6abe9c13 PX |
320 | } |
321 | } | |
322 | ||
c9b8b07c SC |
323 | static struct kmem_cache *kvm_alloc_emulator_cache(void) |
324 | { | |
06add254 SC |
325 | unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); |
326 | unsigned int size = sizeof(struct x86_emulate_ctxt); | |
327 | ||
328 | return kmem_cache_create_usercopy("x86_emulator", size, | |
c9b8b07c | 329 | __alignof__(struct x86_emulate_ctxt), |
06add254 SC |
330 | SLAB_ACCOUNT, useroffset, |
331 | size - useroffset, NULL); | |
c9b8b07c SC |
332 | } |
333 | ||
b6785def | 334 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 335 | |
af585b92 GN |
336 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
337 | { | |
338 | int i; | |
dd03bcaa | 339 | for (i = 0; i < ASYNC_PF_PER_VCPU; i++) |
af585b92 GN |
340 | vcpu->arch.apf.gfns[i] = ~0; |
341 | } | |
342 | ||
18863bdd AK |
343 | static void kvm_on_user_return(struct user_return_notifier *urn) |
344 | { | |
345 | unsigned slot; | |
7e34fbd0 SC |
346 | struct kvm_user_return_msrs *msrs |
347 | = container_of(urn, struct kvm_user_return_msrs, urn); | |
348 | struct kvm_user_return_msr_values *values; | |
1650b4eb IA |
349 | unsigned long flags; |
350 | ||
351 | /* | |
352 | * Disabling irqs at this point since the following code could be | |
353 | * interrupted and executed through kvm_arch_hardware_disable() | |
354 | */ | |
355 | local_irq_save(flags); | |
7e34fbd0 SC |
356 | if (msrs->registered) { |
357 | msrs->registered = false; | |
1650b4eb IA |
358 | user_return_notifier_unregister(urn); |
359 | } | |
360 | local_irq_restore(flags); | |
9cc39a5a | 361 | for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { |
7e34fbd0 | 362 | values = &msrs->values[slot]; |
2bf78fa7 | 363 | if (values->host != values->curr) { |
9cc39a5a | 364 | wrmsrl(kvm_uret_msrs_list[slot], values->host); |
2bf78fa7 | 365 | values->curr = values->host; |
18863bdd AK |
366 | } |
367 | } | |
18863bdd AK |
368 | } |
369 | ||
e5fda4bb | 370 | static int kvm_probe_user_return_msr(u32 msr) |
5104d7ff SC |
371 | { |
372 | u64 val; | |
373 | int ret; | |
374 | ||
375 | preempt_disable(); | |
376 | ret = rdmsrl_safe(msr, &val); | |
377 | if (ret) | |
378 | goto out; | |
379 | ret = wrmsrl_safe(msr, val); | |
380 | out: | |
381 | preempt_enable(); | |
382 | return ret; | |
383 | } | |
5104d7ff | 384 | |
e5fda4bb | 385 | int kvm_add_user_return_msr(u32 msr) |
2bf78fa7 | 386 | { |
e5fda4bb SC |
387 | BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); |
388 | ||
389 | if (kvm_probe_user_return_msr(msr)) | |
390 | return -1; | |
391 | ||
392 | kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; | |
393 | return kvm_nr_uret_msrs++; | |
18863bdd | 394 | } |
e5fda4bb | 395 | EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); |
18863bdd | 396 | |
8ea8b8d6 SC |
397 | int kvm_find_user_return_msr(u32 msr) |
398 | { | |
399 | int i; | |
400 | ||
9cc39a5a SC |
401 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
402 | if (kvm_uret_msrs_list[i] == msr) | |
8ea8b8d6 SC |
403 | return i; |
404 | } | |
405 | return -1; | |
406 | } | |
407 | EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); | |
408 | ||
7e34fbd0 | 409 | static void kvm_user_return_msr_cpu_online(void) |
18863bdd | 410 | { |
05c19c2f | 411 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 412 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
05c19c2f SC |
413 | u64 value; |
414 | int i; | |
18863bdd | 415 | |
9cc39a5a SC |
416 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
417 | rdmsrl_safe(kvm_uret_msrs_list[i], &value); | |
7e34fbd0 SC |
418 | msrs->values[i].host = value; |
419 | msrs->values[i].curr = value; | |
05c19c2f | 420 | } |
18863bdd AK |
421 | } |
422 | ||
7e34fbd0 | 423 | int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 424 | { |
013f6a5d | 425 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 426 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
8b3c3104 | 427 | int err; |
18863bdd | 428 | |
7e34fbd0 SC |
429 | value = (value & mask) | (msrs->values[slot].host & ~mask); |
430 | if (value == msrs->values[slot].curr) | |
8b3c3104 | 431 | return 0; |
9cc39a5a | 432 | err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); |
8b3c3104 AH |
433 | if (err) |
434 | return 1; | |
435 | ||
7e34fbd0 SC |
436 | msrs->values[slot].curr = value; |
437 | if (!msrs->registered) { | |
438 | msrs->urn.on_user_return = kvm_on_user_return; | |
439 | user_return_notifier_register(&msrs->urn); | |
440 | msrs->registered = true; | |
18863bdd | 441 | } |
8b3c3104 | 442 | return 0; |
18863bdd | 443 | } |
7e34fbd0 | 444 | EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); |
18863bdd | 445 | |
13a34e06 | 446 | static void drop_user_return_notifiers(void) |
3548bab5 | 447 | { |
013f6a5d | 448 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 449 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
3548bab5 | 450 | |
7e34fbd0 SC |
451 | if (msrs->registered) |
452 | kvm_on_user_return(&msrs->urn); | |
3548bab5 AK |
453 | } |
454 | ||
6866b83e CO |
455 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
456 | { | |
8a5a87d9 | 457 | return vcpu->arch.apic_base; |
6866b83e CO |
458 | } |
459 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
460 | ||
58871649 JM |
461 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
462 | { | |
463 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
464 | } | |
465 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
466 | ||
58cb628d JK |
467 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
468 | { | |
58871649 JM |
469 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
470 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
a8ac864a | 471 | u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | |
d6321d49 | 472 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); |
58cb628d | 473 | |
58871649 | 474 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 475 | return 1; |
58871649 JM |
476 | if (!msr_info->host_initiated) { |
477 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
478 | return 1; | |
479 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
480 | return 1; | |
481 | } | |
58cb628d JK |
482 | |
483 | kvm_lapic_set_base(vcpu, msr_info->data); | |
4abaffce | 484 | kvm_recalculate_apic_map(vcpu->kvm); |
58cb628d | 485 | return 0; |
6866b83e CO |
486 | } |
487 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
488 | ||
3ebccdf3 | 489 | asmlinkage __visible noinstr void kvm_spurious_fault(void) |
e3ba45b8 GL |
490 | { |
491 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 492 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
493 | } |
494 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
495 | ||
3fd28fce ED |
496 | #define EXCPT_BENIGN 0 |
497 | #define EXCPT_CONTRIBUTORY 1 | |
498 | #define EXCPT_PF 2 | |
499 | ||
500 | static int exception_class(int vector) | |
501 | { | |
502 | switch (vector) { | |
503 | case PF_VECTOR: | |
504 | return EXCPT_PF; | |
505 | case DE_VECTOR: | |
506 | case TS_VECTOR: | |
507 | case NP_VECTOR: | |
508 | case SS_VECTOR: | |
509 | case GP_VECTOR: | |
510 | return EXCPT_CONTRIBUTORY; | |
511 | default: | |
512 | break; | |
513 | } | |
514 | return EXCPT_BENIGN; | |
515 | } | |
516 | ||
d6e8c854 NA |
517 | #define EXCPT_FAULT 0 |
518 | #define EXCPT_TRAP 1 | |
519 | #define EXCPT_ABORT 2 | |
520 | #define EXCPT_INTERRUPT 3 | |
521 | ||
522 | static int exception_type(int vector) | |
523 | { | |
524 | unsigned int mask; | |
525 | ||
526 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
527 | return EXCPT_INTERRUPT; | |
528 | ||
529 | mask = 1 << vector; | |
530 | ||
531 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
532 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
533 | return EXCPT_TRAP; | |
534 | ||
535 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
536 | return EXCPT_ABORT; | |
537 | ||
538 | /* Reserved exceptions will result in fault */ | |
539 | return EXCPT_FAULT; | |
540 | } | |
541 | ||
da998b46 JM |
542 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
543 | { | |
544 | unsigned nr = vcpu->arch.exception.nr; | |
545 | bool has_payload = vcpu->arch.exception.has_payload; | |
546 | unsigned long payload = vcpu->arch.exception.payload; | |
547 | ||
548 | if (!has_payload) | |
549 | return; | |
550 | ||
551 | switch (nr) { | |
f10c729f JM |
552 | case DB_VECTOR: |
553 | /* | |
554 | * "Certain debug exceptions may clear bit 0-3. The | |
555 | * remaining contents of the DR6 register are never | |
556 | * cleared by the processor". | |
557 | */ | |
558 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
559 | /* | |
9a3ecd5e CQ |
560 | * In order to reflect the #DB exception payload in guest |
561 | * dr6, three components need to be considered: active low | |
562 | * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, | |
563 | * DR6_BS and DR6_BT) | |
564 | * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. | |
565 | * In the target guest dr6: | |
566 | * FIXED_1 bits should always be set. | |
567 | * Active low bits should be cleared if 1-setting in payload. | |
568 | * Active high bits should be set if 1-setting in payload. | |
569 | * | |
570 | * Note, the payload is compatible with the pending debug | |
571 | * exceptions/exit qualification under VMX, that active_low bits | |
572 | * are active high in payload. | |
573 | * So they need to be flipped for DR6. | |
f10c729f | 574 | */ |
9a3ecd5e | 575 | vcpu->arch.dr6 |= DR6_ACTIVE_LOW; |
f10c729f | 576 | vcpu->arch.dr6 |= payload; |
9a3ecd5e | 577 | vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; |
307f1cfa OU |
578 | |
579 | /* | |
580 | * The #DB payload is defined as compatible with the 'pending | |
581 | * debug exceptions' field under VMX, not DR6. While bit 12 is | |
582 | * defined in the 'pending debug exceptions' field (enabled | |
583 | * breakpoint), it is reserved and must be zero in DR6. | |
584 | */ | |
585 | vcpu->arch.dr6 &= ~BIT(12); | |
f10c729f | 586 | break; |
da998b46 JM |
587 | case PF_VECTOR: |
588 | vcpu->arch.cr2 = payload; | |
589 | break; | |
590 | } | |
591 | ||
592 | vcpu->arch.exception.has_payload = false; | |
593 | vcpu->arch.exception.payload = 0; | |
594 | } | |
595 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
596 | ||
3fd28fce | 597 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 598 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 599 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
600 | { |
601 | u32 prev_nr; | |
602 | int class1, class2; | |
603 | ||
3842d135 AK |
604 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
605 | ||
664f8e26 | 606 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 607 | queue: |
664f8e26 WL |
608 | if (reinject) { |
609 | /* | |
610 | * On vmentry, vcpu->arch.exception.pending is only | |
611 | * true if an event injection was blocked by | |
612 | * nested_run_pending. In that case, however, | |
613 | * vcpu_enter_guest requests an immediate exit, | |
614 | * and the guest shouldn't proceed far enough to | |
615 | * need reinjection. | |
616 | */ | |
617 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
618 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
619 | if (WARN_ON_ONCE(has_payload)) { |
620 | /* | |
621 | * A reinjected event has already | |
622 | * delivered its payload. | |
623 | */ | |
624 | has_payload = false; | |
625 | payload = 0; | |
626 | } | |
664f8e26 WL |
627 | } else { |
628 | vcpu->arch.exception.pending = true; | |
629 | vcpu->arch.exception.injected = false; | |
630 | } | |
3fd28fce ED |
631 | vcpu->arch.exception.has_error_code = has_error; |
632 | vcpu->arch.exception.nr = nr; | |
633 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
634 | vcpu->arch.exception.has_payload = has_payload; |
635 | vcpu->arch.exception.payload = payload; | |
a06230b6 | 636 | if (!is_guest_mode(vcpu)) |
da998b46 | 637 | kvm_deliver_exception_payload(vcpu); |
3fd28fce ED |
638 | return; |
639 | } | |
640 | ||
641 | /* to check exception */ | |
642 | prev_nr = vcpu->arch.exception.nr; | |
643 | if (prev_nr == DF_VECTOR) { | |
644 | /* triple fault -> shutdown */ | |
a8eeb04a | 645 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
646 | return; |
647 | } | |
648 | class1 = exception_class(prev_nr); | |
649 | class2 = exception_class(nr); | |
650 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
651 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
652 | /* |
653 | * Generate double fault per SDM Table 5-5. Set | |
654 | * exception.pending = true so that the double fault | |
655 | * can trigger a nested vmexit. | |
656 | */ | |
3fd28fce | 657 | vcpu->arch.exception.pending = true; |
664f8e26 | 658 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
659 | vcpu->arch.exception.has_error_code = true; |
660 | vcpu->arch.exception.nr = DF_VECTOR; | |
661 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
662 | vcpu->arch.exception.has_payload = false; |
663 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
664 | } else |
665 | /* replace previous exception with a new one in a hope | |
666 | that instruction re-execution will regenerate lost | |
667 | exception */ | |
668 | goto queue; | |
669 | } | |
670 | ||
298101da AK |
671 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
672 | { | |
91e86d22 | 673 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
674 | } |
675 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
676 | ||
ce7ddec4 JR |
677 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
678 | { | |
91e86d22 | 679 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
680 | } |
681 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
682 | ||
4d5523cf PB |
683 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
684 | unsigned long payload) | |
f10c729f JM |
685 | { |
686 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
687 | } | |
4d5523cf | 688 | EXPORT_SYMBOL_GPL(kvm_queue_exception_p); |
f10c729f | 689 | |
da998b46 JM |
690 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
691 | u32 error_code, unsigned long payload) | |
692 | { | |
693 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
694 | true, payload, false); | |
695 | } | |
696 | ||
6affcbed | 697 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 698 | { |
db8fcefa AP |
699 | if (err) |
700 | kvm_inject_gp(vcpu, 0); | |
701 | else | |
6affcbed KH |
702 | return kvm_skip_emulated_instruction(vcpu); |
703 | ||
704 | return 1; | |
db8fcefa AP |
705 | } |
706 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 707 | |
6389ee94 | 708 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
709 | { |
710 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
711 | vcpu->arch.exception.nested_apf = |
712 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 713 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 714 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
715 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
716 | } else { | |
717 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
718 | fault->address); | |
719 | } | |
c3c91fee | 720 | } |
27d6c865 | 721 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 722 | |
53b3d8e9 SC |
723 | bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
724 | struct x86_exception *fault) | |
d4f8cf66 | 725 | { |
0cd665bd | 726 | struct kvm_mmu *fault_mmu; |
53b3d8e9 SC |
727 | WARN_ON_ONCE(fault->vector != PF_VECTOR); |
728 | ||
0cd665bd PB |
729 | fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : |
730 | vcpu->arch.walk_mmu; | |
ef54bcfe | 731 | |
ee1fa209 JS |
732 | /* |
733 | * Invalidate the TLB entry for the faulting address, if it exists, | |
734 | * else the access will fault indefinitely (and to emulate hardware). | |
735 | */ | |
736 | if ((fault->error_code & PFERR_PRESENT_MASK) && | |
737 | !(fault->error_code & PFERR_RSVD_MASK)) | |
738 | kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, | |
739 | fault_mmu->root_hpa); | |
740 | ||
741 | fault_mmu->inject_page_fault(vcpu, fault); | |
ef54bcfe | 742 | return fault->nested_page_fault; |
d4f8cf66 | 743 | } |
53b3d8e9 | 744 | EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); |
d4f8cf66 | 745 | |
3419ffc8 SY |
746 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
747 | { | |
7460fb4a AK |
748 | atomic_inc(&vcpu->arch.nmi_queued); |
749 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
750 | } |
751 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
752 | ||
298101da AK |
753 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
754 | { | |
91e86d22 | 755 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
756 | } |
757 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
758 | ||
ce7ddec4 JR |
759 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
760 | { | |
91e86d22 | 761 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
762 | } |
763 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
764 | ||
0a79b009 AK |
765 | /* |
766 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
767 | * a #GP and return false. | |
768 | */ | |
769 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 770 | { |
b3646477 | 771 | if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) |
0a79b009 AK |
772 | return true; |
773 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
774 | return false; | |
298101da | 775 | } |
0a79b009 | 776 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 777 | |
16f8a6f9 NA |
778 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
779 | { | |
780 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
781 | return true; | |
782 | ||
783 | kvm_queue_exception(vcpu, UD_VECTOR); | |
784 | return false; | |
785 | } | |
786 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
787 | ||
ec92fe44 JR |
788 | /* |
789 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 790 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
791 | * can read from guest physical or from the guest's guest physical memory. |
792 | */ | |
793 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
794 | gfn_t ngfn, void *data, int offset, int len, | |
795 | u32 access) | |
796 | { | |
54987b7a | 797 | struct x86_exception exception; |
ec92fe44 JR |
798 | gfn_t real_gfn; |
799 | gpa_t ngpa; | |
800 | ||
801 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 802 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
803 | if (real_gfn == UNMAPPED_GVA) |
804 | return -EFAULT; | |
805 | ||
806 | real_gfn = gpa_to_gfn(real_gfn); | |
807 | ||
54bf36aa | 808 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
809 | } |
810 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
811 | ||
16cfacc8 SC |
812 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
813 | { | |
5b7f575c | 814 | return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); |
16cfacc8 SC |
815 | } |
816 | ||
a03490ed | 817 | /* |
16cfacc8 | 818 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 819 | */ |
ff03a073 | 820 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
821 | { |
822 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
823 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
824 | int i; | |
825 | int ret; | |
ff03a073 | 826 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 827 | |
ff03a073 JR |
828 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
829 | offset * sizeof(u64), sizeof(pdpte), | |
830 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
831 | if (ret < 0) { |
832 | ret = 0; | |
833 | goto out; | |
834 | } | |
835 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
812f30b2 | 836 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 837 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
a03490ed CO |
838 | ret = 0; |
839 | goto out; | |
840 | } | |
841 | } | |
842 | ret = 1; | |
843 | ||
ff03a073 | 844 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
cb3c1e2f | 845 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); |
158a48ec ML |
846 | vcpu->arch.pdptrs_from_userspace = false; |
847 | ||
a03490ed | 848 | out: |
a03490ed CO |
849 | |
850 | return ret; | |
851 | } | |
cc4b6871 | 852 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 853 | |
f27ad38a TL |
854 | void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) |
855 | { | |
f27ad38a TL |
856 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
857 | kvm_clear_async_pf_completion_queue(vcpu); | |
858 | kvm_async_pf_hash_reset(vcpu); | |
859 | } | |
860 | ||
20f632bd | 861 | if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) |
f27ad38a TL |
862 | kvm_mmu_reset_context(vcpu); |
863 | ||
864 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && | |
865 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
866 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
867 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); | |
868 | } | |
869 | EXPORT_SYMBOL_GPL(kvm_post_set_cr0); | |
870 | ||
49a9b07e | 871 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 872 | { |
aad82703 | 873 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d42e3fae | 874 | unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; |
aad82703 | 875 | |
f9a48e6a AK |
876 | cr0 |= X86_CR0_ET; |
877 | ||
ab344828 | 878 | #ifdef CONFIG_X86_64 |
0f12244f GN |
879 | if (cr0 & 0xffffffff00000000UL) |
880 | return 1; | |
ab344828 GN |
881 | #endif |
882 | ||
883 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 884 | |
0f12244f GN |
885 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
886 | return 1; | |
a03490ed | 887 | |
0f12244f GN |
888 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
889 | return 1; | |
a03490ed | 890 | |
a03490ed | 891 | #ifdef CONFIG_X86_64 |
05487215 SC |
892 | if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && |
893 | (cr0 & X86_CR0_PG)) { | |
894 | int cs_db, cs_l; | |
895 | ||
896 | if (!is_pae(vcpu)) | |
897 | return 1; | |
b3646477 | 898 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
05487215 | 899 | if (cs_l) |
0f12244f | 900 | return 1; |
a03490ed | 901 | } |
05487215 SC |
902 | #endif |
903 | if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && | |
904 | is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && | |
905 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) | |
906 | return 1; | |
a03490ed | 907 | |
ad756a16 MJ |
908 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
909 | return 1; | |
910 | ||
b3646477 | 911 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
a03490ed | 912 | |
f27ad38a | 913 | kvm_post_set_cr0(vcpu, old_cr0, cr0); |
b18d5431 | 914 | |
0f12244f GN |
915 | return 0; |
916 | } | |
2d3ad1f4 | 917 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 918 | |
2d3ad1f4 | 919 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 920 | { |
49a9b07e | 921 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 922 | } |
2d3ad1f4 | 923 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 924 | |
139a12cf | 925 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 926 | { |
16809ecd TL |
927 | if (vcpu->arch.guest_state_protected) |
928 | return; | |
929 | ||
139a12cf AL |
930 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
931 | ||
932 | if (vcpu->arch.xcr0 != host_xcr0) | |
933 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
934 | ||
935 | if (vcpu->arch.xsaves_enabled && | |
936 | vcpu->arch.ia32_xss != host_xss) | |
937 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
938 | } | |
37486135 BM |
939 | |
940 | if (static_cpu_has(X86_FEATURE_PKU) && | |
941 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
942 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && | |
943 | vcpu->arch.pkru != vcpu->arch.host_pkru) | |
72a6c08c | 944 | write_pkru(vcpu->arch.pkru); |
42bdf991 | 945 | } |
139a12cf | 946 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 947 | |
139a12cf | 948 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 949 | { |
16809ecd TL |
950 | if (vcpu->arch.guest_state_protected) |
951 | return; | |
952 | ||
37486135 BM |
953 | if (static_cpu_has(X86_FEATURE_PKU) && |
954 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
955 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { | |
956 | vcpu->arch.pkru = rdpkru(); | |
957 | if (vcpu->arch.pkru != vcpu->arch.host_pkru) | |
72a6c08c | 958 | write_pkru(vcpu->arch.host_pkru); |
37486135 BM |
959 | } |
960 | ||
139a12cf AL |
961 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
962 | ||
963 | if (vcpu->arch.xcr0 != host_xcr0) | |
964 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
965 | ||
966 | if (vcpu->arch.xsaves_enabled && | |
967 | vcpu->arch.ia32_xss != host_xss) | |
968 | wrmsrl(MSR_IA32_XSS, host_xss); | |
969 | } | |
970 | ||
42bdf991 | 971 | } |
139a12cf | 972 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 973 | |
69b0049a | 974 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 975 | { |
56c103ec LJ |
976 | u64 xcr0 = xcr; |
977 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 978 | u64 valid_bits; |
2acf923e DC |
979 | |
980 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
981 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
982 | return 1; | |
d91cab78 | 983 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 984 | return 1; |
d91cab78 | 985 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 986 | return 1; |
46c34cb0 PB |
987 | |
988 | /* | |
989 | * Do not allow the guest to set bits that we do not support | |
990 | * saving. However, xcr0 bit 0 is always set, even if the | |
991 | * emulated CPU does not support XSAVE (see fx_init). | |
992 | */ | |
d91cab78 | 993 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 994 | if (xcr0 & ~valid_bits) |
2acf923e | 995 | return 1; |
46c34cb0 | 996 | |
d91cab78 DH |
997 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
998 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
999 | return 1; |
1000 | ||
d91cab78 DH |
1001 | if (xcr0 & XFEATURE_MASK_AVX512) { |
1002 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 1003 | return 1; |
d91cab78 | 1004 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
1005 | return 1; |
1006 | } | |
2acf923e | 1007 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 1008 | |
d91cab78 | 1009 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
aedbaf4f | 1010 | kvm_update_cpuid_runtime(vcpu); |
2acf923e DC |
1011 | return 0; |
1012 | } | |
1013 | ||
92f9895c | 1014 | int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) |
2acf923e | 1015 | { |
92f9895c SC |
1016 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || |
1017 | __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { | |
1018 | kvm_inject_gp(vcpu, 0); | |
1019 | return 1; | |
1020 | } | |
bbefd4fc | 1021 | |
92f9895c | 1022 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e | 1023 | } |
92f9895c | 1024 | EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); |
2acf923e | 1025 | |
ee69c92b | 1026 | bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 1027 | { |
b11306b5 | 1028 | if (cr4 & cr4_reserved_bits) |
ee69c92b | 1029 | return false; |
b9baba86 | 1030 | |
b899c132 | 1031 | if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) |
ee69c92b | 1032 | return false; |
3ca94192 | 1033 | |
b3646477 | 1034 | return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); |
3ca94192 | 1035 | } |
ee69c92b | 1036 | EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); |
3ca94192 | 1037 | |
5b51cb13 TL |
1038 | void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) |
1039 | { | |
20f632bd | 1040 | if (((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) || |
5b51cb13 TL |
1041 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) |
1042 | kvm_mmu_reset_context(vcpu); | |
3ca94192 | 1043 | } |
5b51cb13 | 1044 | EXPORT_SYMBOL_GPL(kvm_post_set_cr4); |
3ca94192 WL |
1045 | |
1046 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1047 | { | |
1048 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
1049 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
cb957adb | 1050 | X86_CR4_SMEP; |
3ca94192 | 1051 | |
ee69c92b | 1052 | if (!kvm_is_valid_cr4(vcpu, cr4)) |
ae3e61e1 PB |
1053 | return 1; |
1054 | ||
a03490ed | 1055 | if (is_long_mode(vcpu)) { |
0f12244f GN |
1056 | if (!(cr4 & X86_CR4_PAE)) |
1057 | return 1; | |
d74fcfc1 SC |
1058 | if ((cr4 ^ old_cr4) & X86_CR4_LA57) |
1059 | return 1; | |
a2edf57f AK |
1060 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
1061 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
1062 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
1063 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
1064 | return 1; |
1065 | ||
ad756a16 | 1066 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 1067 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
1068 | return 1; |
1069 | ||
1070 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
1071 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
1072 | return 1; | |
1073 | } | |
1074 | ||
b3646477 | 1075 | static_call(kvm_x86_set_cr4)(vcpu, cr4); |
a03490ed | 1076 | |
5b51cb13 | 1077 | kvm_post_set_cr4(vcpu, old_cr4, cr4); |
2acf923e | 1078 | |
0f12244f GN |
1079 | return 0; |
1080 | } | |
2d3ad1f4 | 1081 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 1082 | |
21823fbd SC |
1083 | static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) |
1084 | { | |
1085 | struct kvm_mmu *mmu = vcpu->arch.mmu; | |
1086 | unsigned long roots_to_free = 0; | |
1087 | int i; | |
1088 | ||
1089 | /* | |
1090 | * If neither the current CR3 nor any of the prev_roots use the given | |
1091 | * PCID, then nothing needs to be done here because a resync will | |
1092 | * happen anyway before switching to any other CR3. | |
1093 | */ | |
1094 | if (kvm_get_active_pcid(vcpu) == pcid) { | |
e62f1aa8 | 1095 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
21823fbd SC |
1096 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
1097 | } | |
1098 | ||
1099 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
1100 | if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) | |
1101 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
1102 | ||
1103 | kvm_mmu_free_roots(vcpu, mmu, roots_to_free); | |
1104 | } | |
1105 | ||
2390218b | 1106 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 1107 | { |
ade61e28 | 1108 | bool skip_tlb_flush = false; |
21823fbd | 1109 | unsigned long pcid = 0; |
ac146235 | 1110 | #ifdef CONFIG_X86_64 |
c19986fe JS |
1111 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
1112 | ||
ade61e28 | 1113 | if (pcid_enabled) { |
208320ba JS |
1114 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
1115 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
21823fbd | 1116 | pcid = cr3 & X86_CR3_PCID_MASK; |
ade61e28 | 1117 | } |
ac146235 | 1118 | #endif |
9d88fca7 | 1119 | |
c7313155 | 1120 | /* PDPTRs are always reloaded for PAE paging. */ |
21823fbd SC |
1121 | if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) |
1122 | goto handle_tlb_flush; | |
d835dfec | 1123 | |
886bbcc7 SC |
1124 | /* |
1125 | * Do not condition the GPA check on long mode, this helper is used to | |
1126 | * stuff CR3, e.g. for RSM emulation, and there is no guarantee that | |
1127 | * the current vCPU mode is accurate. | |
1128 | */ | |
1129 | if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) | |
d1cd3ce9 | 1130 | return 1; |
886bbcc7 SC |
1131 | |
1132 | if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 1133 | return 1; |
a03490ed | 1134 | |
21823fbd | 1135 | if (cr3 != kvm_read_cr3(vcpu)) |
b5129100 | 1136 | kvm_mmu_new_pgd(vcpu, cr3); |
21823fbd | 1137 | |
0f12244f | 1138 | vcpu->arch.cr3 = cr3; |
cb3c1e2f | 1139 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
7c390d35 | 1140 | |
21823fbd SC |
1141 | handle_tlb_flush: |
1142 | /* | |
1143 | * A load of CR3 that flushes the TLB flushes only the current PCID, | |
1144 | * even if PCID is disabled, in which case PCID=0 is flushed. It's a | |
1145 | * moot point in the end because _disabling_ PCID will flush all PCIDs, | |
1146 | * and it's impossible to use a non-zero PCID when PCID is disabled, | |
1147 | * i.e. only PCID=0 can be relevant. | |
1148 | */ | |
1149 | if (!skip_tlb_flush) | |
1150 | kvm_invalidate_pcid(vcpu, pcid); | |
1151 | ||
0f12244f GN |
1152 | return 0; |
1153 | } | |
2d3ad1f4 | 1154 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1155 | |
eea1cff9 | 1156 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1157 | { |
0f12244f GN |
1158 | if (cr8 & CR8_RESERVED_BITS) |
1159 | return 1; | |
35754c98 | 1160 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1161 | kvm_lapic_set_tpr(vcpu, cr8); |
1162 | else | |
ad312c7c | 1163 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1164 | return 0; |
1165 | } | |
2d3ad1f4 | 1166 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1167 | |
2d3ad1f4 | 1168 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1169 | { |
35754c98 | 1170 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1171 | return kvm_lapic_get_cr8(vcpu); |
1172 | else | |
ad312c7c | 1173 | return vcpu->arch.cr8; |
a03490ed | 1174 | } |
2d3ad1f4 | 1175 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1176 | |
ae561ede NA |
1177 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1178 | { | |
1179 | int i; | |
1180 | ||
1181 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1182 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1183 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae561ede NA |
1184 | } |
1185 | } | |
1186 | ||
7c86663b | 1187 | void kvm_update_dr7(struct kvm_vcpu *vcpu) |
c8639010 JK |
1188 | { |
1189 | unsigned long dr7; | |
1190 | ||
1191 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1192 | dr7 = vcpu->arch.guest_debug_dr7; | |
1193 | else | |
1194 | dr7 = vcpu->arch.dr7; | |
b3646477 | 1195 | static_call(kvm_x86_set_dr7)(vcpu, dr7); |
360b948d PB |
1196 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1197 | if (dr7 & DR7_BP_EN_MASK) | |
1198 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 | 1199 | } |
7c86663b | 1200 | EXPORT_SYMBOL_GPL(kvm_update_dr7); |
c8639010 | 1201 | |
6f43ed01 NA |
1202 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1203 | { | |
1204 | u64 fixed = DR6_FIXED_1; | |
1205 | ||
d6321d49 | 1206 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 | 1207 | fixed |= DR6_RTM; |
e8ea85fb CQ |
1208 | |
1209 | if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) | |
1210 | fixed |= DR6_BUS_LOCK; | |
6f43ed01 NA |
1211 | return fixed; |
1212 | } | |
1213 | ||
996ff542 | 1214 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1215 | { |
ea740059 MP |
1216 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1217 | ||
020df079 GN |
1218 | switch (dr) { |
1219 | case 0 ... 3: | |
ea740059 | 1220 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1221 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1222 | vcpu->arch.eff_db[dr] = val; | |
1223 | break; | |
1224 | case 4: | |
020df079 | 1225 | case 6: |
f5f6145e | 1226 | if (!kvm_dr6_valid(val)) |
996ff542 | 1227 | return 1; /* #GP */ |
6f43ed01 | 1228 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
020df079 GN |
1229 | break; |
1230 | case 5: | |
020df079 | 1231 | default: /* 7 */ |
b91991bf | 1232 | if (!kvm_dr7_valid(val)) |
996ff542 | 1233 | return 1; /* #GP */ |
020df079 | 1234 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1235 | kvm_update_dr7(vcpu); |
020df079 GN |
1236 | break; |
1237 | } | |
1238 | ||
1239 | return 0; | |
1240 | } | |
1241 | EXPORT_SYMBOL_GPL(kvm_set_dr); | |
1242 | ||
29d6ca41 | 1243 | void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1244 | { |
ea740059 MP |
1245 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1246 | ||
020df079 GN |
1247 | switch (dr) { |
1248 | case 0 ... 3: | |
ea740059 | 1249 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1250 | break; |
1251 | case 4: | |
020df079 | 1252 | case 6: |
5679b803 | 1253 | *val = vcpu->arch.dr6; |
020df079 GN |
1254 | break; |
1255 | case 5: | |
020df079 GN |
1256 | default: /* 7 */ |
1257 | *val = vcpu->arch.dr7; | |
1258 | break; | |
1259 | } | |
338dbc97 | 1260 | } |
020df079 GN |
1261 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1262 | ||
c483c454 | 1263 | int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) |
022cd0e8 | 1264 | { |
de3cd117 | 1265 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 | 1266 | u64 data; |
022cd0e8 | 1267 | |
c483c454 SC |
1268 | if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { |
1269 | kvm_inject_gp(vcpu, 0); | |
1270 | return 1; | |
1271 | } | |
1272 | ||
de3cd117 SC |
1273 | kvm_rax_write(vcpu, (u32)data); |
1274 | kvm_rdx_write(vcpu, data >> 32); | |
c483c454 | 1275 | return kvm_skip_emulated_instruction(vcpu); |
022cd0e8 | 1276 | } |
c483c454 | 1277 | EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); |
022cd0e8 | 1278 | |
043405e1 CO |
1279 | /* |
1280 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1281 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1282 | * | |
7a5ee6ed CQ |
1283 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) |
1284 | * extract the supported MSRs from the related const lists. | |
1285 | * msrs_to_save is selected from the msrs_to_save_all to reflect the | |
e3267cbb | 1286 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
7a5ee6ed | 1287 | * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs |
62ef68bb | 1288 | * may depend on host virtualization features rather than host cpu features. |
043405e1 | 1289 | */ |
e3267cbb | 1290 | |
7a5ee6ed | 1291 | static const u32 msrs_to_save_all[] = { |
043405e1 | 1292 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1293 | MSR_STAR, |
043405e1 CO |
1294 | #ifdef CONFIG_X86_64 |
1295 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1296 | #endif | |
b3897a49 | 1297 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1298 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1299 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1300 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1301 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1302 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1303 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1304 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1305 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1306 | MSR_IA32_UMWAIT_CONTROL, |
1307 | ||
e2ada66e JM |
1308 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
1309 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, | |
1310 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, | |
1311 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1312 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, | |
1313 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1314 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1315 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
1316 | MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, | |
1317 | MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, | |
1318 | MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, | |
1319 | MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, | |
1320 | MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, | |
e2ada66e JM |
1321 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1322 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1323 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1324 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
1325 | MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, | |
1326 | MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, | |
1327 | MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, | |
1328 | MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, | |
1329 | MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, | |
043405e1 CO |
1330 | }; |
1331 | ||
7a5ee6ed | 1332 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; |
043405e1 CO |
1333 | static unsigned num_msrs_to_save; |
1334 | ||
7a5ee6ed | 1335 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1336 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1337 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1338 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1339 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1340 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1341 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1342 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1343 | HV_X64_MSR_RESET, |
11c4b1ca | 1344 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1345 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1346 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1347 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1348 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1349 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1350 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
f97f5a56 JD |
1351 | HV_X64_MSR_SYNDBG_OPTIONS, |
1352 | HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, | |
1353 | HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, | |
1354 | HV_X64_MSR_SYNDBG_PENDING_BUFFER, | |
a2e164e7 VK |
1355 | |
1356 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
557a961a | 1357 | MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, |
62ef68bb | 1358 | |
ba904635 | 1359 | MSR_IA32_TSC_ADJUST, |
09141ec0 | 1360 | MSR_IA32_TSC_DEADLINE, |
2bdb76c0 | 1361 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1362 | MSR_IA32_PERF_CAPABILITIES, |
043405e1 | 1363 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1364 | MSR_IA32_MCG_STATUS, |
1365 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1366 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1367 | MSR_IA32_SMBASE, |
52797bf9 | 1368 | MSR_SMI_COUNT, |
db2336a8 KH |
1369 | MSR_PLATFORM_INFO, |
1370 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1371 | MSR_AMD64_VIRT_SPEC_CTRL, |
6c6a2ab9 | 1372 | MSR_IA32_POWER_CTL, |
99634e3e | 1373 | MSR_IA32_UCODE_REV, |
191c8137 | 1374 | |
95c5c7c7 PB |
1375 | /* |
1376 | * The following list leaves out MSRs whose values are determined | |
1377 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1378 | * We always support the "true" VMX control MSRs, even if the host | |
1379 | * processor does not, so I am putting these registers here rather | |
7a5ee6ed | 1380 | * than in msrs_to_save_all. |
95c5c7c7 PB |
1381 | */ |
1382 | MSR_IA32_VMX_BASIC, | |
1383 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1384 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1385 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1386 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1387 | MSR_IA32_VMX_MISC, | |
1388 | MSR_IA32_VMX_CR0_FIXED0, | |
1389 | MSR_IA32_VMX_CR4_FIXED0, | |
1390 | MSR_IA32_VMX_VMCS_ENUM, | |
1391 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1392 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1393 | MSR_IA32_VMX_VMFUNC, | |
1394 | ||
191c8137 | 1395 | MSR_K7_HWCR, |
2d5ba19b | 1396 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1397 | }; |
1398 | ||
7a5ee6ed | 1399 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1400 | static unsigned num_emulated_msrs; |
1401 | ||
801e459a TL |
1402 | /* |
1403 | * List of msr numbers which are used to expose MSR-based features that | |
1404 | * can be used by a hypervisor to validate requested CPU features. | |
1405 | */ | |
7a5ee6ed | 1406 | static const u32 msr_based_features_all[] = { |
1389309c PB |
1407 | MSR_IA32_VMX_BASIC, |
1408 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1409 | MSR_IA32_VMX_PINBASED_CTLS, | |
1410 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1411 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1412 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1413 | MSR_IA32_VMX_EXIT_CTLS, | |
1414 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1415 | MSR_IA32_VMX_ENTRY_CTLS, | |
1416 | MSR_IA32_VMX_MISC, | |
1417 | MSR_IA32_VMX_CR0_FIXED0, | |
1418 | MSR_IA32_VMX_CR0_FIXED1, | |
1419 | MSR_IA32_VMX_CR4_FIXED0, | |
1420 | MSR_IA32_VMX_CR4_FIXED1, | |
1421 | MSR_IA32_VMX_VMCS_ENUM, | |
1422 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1423 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1424 | MSR_IA32_VMX_VMFUNC, | |
1425 | ||
d1d93fa9 | 1426 | MSR_F10H_DECFG, |
518e7b94 | 1427 | MSR_IA32_UCODE_REV, |
cd283252 | 1428 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1429 | MSR_IA32_PERF_CAPABILITIES, |
801e459a TL |
1430 | }; |
1431 | ||
7a5ee6ed | 1432 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; |
801e459a TL |
1433 | static unsigned int num_msr_based_features; |
1434 | ||
4d22c17c | 1435 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1436 | { |
4d22c17c | 1437 | u64 data = 0; |
5b76a3cf | 1438 | |
4d22c17c XL |
1439 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1440 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf | 1441 | |
b8e8c830 PB |
1442 | /* |
1443 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1444 | * the nested hypervisor runs with NX huge pages. If it is not, | |
d9f6e12f | 1445 | * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other |
b8e8c830 PB |
1446 | * L1 guests, so it need not worry about its own (L2) guests. |
1447 | */ | |
1448 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1449 | ||
5b76a3cf PB |
1450 | /* |
1451 | * If we're doing cache flushes (either "always" or "cond") | |
1452 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1453 | * If an outer hypervisor is doing the cache flush for us | |
1454 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1455 | * capability to the guest too, and if EPT is disabled we're not | |
1456 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1457 | * require a nested hypervisor to do a flush of its own. | |
1458 | */ | |
1459 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1460 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1461 | ||
0c54914d PB |
1462 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1463 | data |= ARCH_CAP_RDCL_NO; | |
1464 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1465 | data |= ARCH_CAP_SSB_NO; | |
1466 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1467 | data |= ARCH_CAP_MDS_NO; | |
1468 | ||
7131636e PB |
1469 | if (!boot_cpu_has(X86_FEATURE_RTM)) { |
1470 | /* | |
1471 | * If RTM=0 because the kernel has disabled TSX, the host might | |
1472 | * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 | |
1473 | * and therefore knows that there cannot be TAA) but keep | |
1474 | * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, | |
1475 | * and we want to allow migrating those guests to tsx=off hosts. | |
1476 | */ | |
1477 | data &= ~ARCH_CAP_TAA_NO; | |
1478 | } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { | |
cbbaa272 | 1479 | data |= ARCH_CAP_TAA_NO; |
7131636e PB |
1480 | } else { |
1481 | /* | |
1482 | * Nothing to do here; we emulate TSX_CTRL if present on the | |
1483 | * host so the guest can choose between disabling TSX or | |
1484 | * using VERW to clear CPU buffers. | |
1485 | */ | |
1486 | } | |
e1d38b63 | 1487 | |
5b76a3cf PB |
1488 | return data; |
1489 | } | |
5b76a3cf | 1490 | |
66421c1e WL |
1491 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1492 | { | |
1493 | switch (msr->index) { | |
cd283252 | 1494 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1495 | msr->data = kvm_get_arch_capabilities(); |
1496 | break; | |
1497 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1498 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1499 | break; |
66421c1e | 1500 | default: |
b3646477 | 1501 | return static_call(kvm_x86_get_msr_feature)(msr); |
66421c1e WL |
1502 | } |
1503 | return 0; | |
1504 | } | |
1505 | ||
801e459a TL |
1506 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1507 | { | |
1508 | struct kvm_msr_entry msr; | |
66421c1e | 1509 | int r; |
801e459a TL |
1510 | |
1511 | msr.index = index; | |
66421c1e | 1512 | r = kvm_get_msr_feature(&msr); |
12bc2132 PX |
1513 | |
1514 | if (r == KVM_MSR_RET_INVALID) { | |
1515 | /* Unconditionally clear the output for simplicity */ | |
1516 | *data = 0; | |
d632826f | 1517 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1518 | r = 0; |
12bc2132 PX |
1519 | } |
1520 | ||
66421c1e WL |
1521 | if (r) |
1522 | return r; | |
801e459a TL |
1523 | |
1524 | *data = msr.data; | |
1525 | ||
1526 | return 0; | |
1527 | } | |
1528 | ||
11988499 | 1529 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1530 | { |
1b4d56b8 | 1531 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1532 | return false; |
1b2fd70c | 1533 | |
1b4d56b8 | 1534 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1535 | return false; |
d8017474 | 1536 | |
0a629563 SC |
1537 | if (efer & (EFER_LME | EFER_LMA) && |
1538 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1539 | return false; | |
1540 | ||
1541 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1542 | return false; | |
d8017474 | 1543 | |
384bb783 | 1544 | return true; |
11988499 SC |
1545 | |
1546 | } | |
1547 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1548 | { | |
1549 | if (efer & efer_reserved_bits) | |
1550 | return false; | |
1551 | ||
1552 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1553 | } |
1554 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1555 | ||
11988499 | 1556 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1557 | { |
1558 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1559 | u64 efer = msr_info->data; |
72f211ec | 1560 | int r; |
384bb783 | 1561 | |
11988499 | 1562 | if (efer & efer_reserved_bits) |
66f61c92 | 1563 | return 1; |
384bb783 | 1564 | |
11988499 SC |
1565 | if (!msr_info->host_initiated) { |
1566 | if (!__kvm_valid_efer(vcpu, efer)) | |
1567 | return 1; | |
1568 | ||
1569 | if (is_paging(vcpu) && | |
1570 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1571 | return 1; | |
1572 | } | |
384bb783 | 1573 | |
15c4a640 | 1574 | efer &= ~EFER_LMA; |
f6801dff | 1575 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1576 | |
b3646477 | 1577 | r = static_call(kvm_x86_set_efer)(vcpu, efer); |
72f211ec ML |
1578 | if (r) { |
1579 | WARN_ON(r > 0); | |
1580 | return r; | |
1581 | } | |
a3d204e2 | 1582 | |
aad82703 SY |
1583 | /* Update reserved bits */ |
1584 | if ((efer ^ old_efer) & EFER_NX) | |
1585 | kvm_mmu_reset_context(vcpu); | |
1586 | ||
b69e8cae | 1587 | return 0; |
15c4a640 CO |
1588 | } |
1589 | ||
f2b4b7dd JR |
1590 | void kvm_enable_efer_bits(u64 mask) |
1591 | { | |
1592 | efer_reserved_bits &= ~mask; | |
1593 | } | |
1594 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1595 | ||
51de8151 AG |
1596 | bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) |
1597 | { | |
b318e8de SC |
1598 | struct kvm_x86_msr_filter *msr_filter; |
1599 | struct msr_bitmap_range *ranges; | |
1a155254 | 1600 | struct kvm *kvm = vcpu->kvm; |
b318e8de | 1601 | bool allowed; |
1a155254 | 1602 | int idx; |
b318e8de | 1603 | u32 i; |
1a155254 | 1604 | |
b318e8de SC |
1605 | /* x2APIC MSRs do not support filtering. */ |
1606 | if (index >= 0x800 && index <= 0x8ff) | |
1a155254 AG |
1607 | return true; |
1608 | ||
1a155254 AG |
1609 | idx = srcu_read_lock(&kvm->srcu); |
1610 | ||
b318e8de SC |
1611 | msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); |
1612 | if (!msr_filter) { | |
1613 | allowed = true; | |
1614 | goto out; | |
1615 | } | |
1616 | ||
1617 | allowed = msr_filter->default_allow; | |
1618 | ranges = msr_filter->ranges; | |
1619 | ||
1620 | for (i = 0; i < msr_filter->count; i++) { | |
1a155254 AG |
1621 | u32 start = ranges[i].base; |
1622 | u32 end = start + ranges[i].nmsrs; | |
1623 | u32 flags = ranges[i].flags; | |
1624 | unsigned long *bitmap = ranges[i].bitmap; | |
1625 | ||
1626 | if ((index >= start) && (index < end) && (flags & type)) { | |
b318e8de | 1627 | allowed = !!test_bit(index - start, bitmap); |
1a155254 AG |
1628 | break; |
1629 | } | |
1630 | } | |
1631 | ||
b318e8de | 1632 | out: |
1a155254 AG |
1633 | srcu_read_unlock(&kvm->srcu, idx); |
1634 | ||
b318e8de | 1635 | return allowed; |
51de8151 AG |
1636 | } |
1637 | EXPORT_SYMBOL_GPL(kvm_msr_allowed); | |
1638 | ||
15c4a640 | 1639 | /* |
f20935d8 SC |
1640 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1641 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1642 | * Returns 0 on success, non-0 otherwise. |
1643 | * Assumes vcpu_load() was already called. | |
1644 | */ | |
f20935d8 SC |
1645 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1646 | bool host_initiated) | |
15c4a640 | 1647 | { |
f20935d8 SC |
1648 | struct msr_data msr; |
1649 | ||
1a155254 | 1650 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) |
cc4cb017 | 1651 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1652 | |
f20935d8 | 1653 | switch (index) { |
854e8bb1 NA |
1654 | case MSR_FS_BASE: |
1655 | case MSR_GS_BASE: | |
1656 | case MSR_KERNEL_GS_BASE: | |
1657 | case MSR_CSTAR: | |
1658 | case MSR_LSTAR: | |
f20935d8 | 1659 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1660 | return 1; |
1661 | break; | |
1662 | case MSR_IA32_SYSENTER_EIP: | |
1663 | case MSR_IA32_SYSENTER_ESP: | |
1664 | /* | |
1665 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1666 | * non-canonical address is written on Intel but not on | |
1667 | * AMD (which ignores the top 32-bits, because it does | |
1668 | * not implement 64-bit SYSENTER). | |
1669 | * | |
1670 | * 64-bit code should hence be able to write a non-canonical | |
1671 | * value on AMD. Making the address canonical ensures that | |
1672 | * vmentry does not fail on Intel after writing a non-canonical | |
1673 | * value, and that something deterministic happens if the guest | |
1674 | * invokes 64-bit SYSENTER. | |
1675 | */ | |
f20935d8 | 1676 | data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); |
61a05d44 SC |
1677 | break; |
1678 | case MSR_TSC_AUX: | |
1679 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1680 | return 1; | |
1681 | ||
1682 | if (!host_initiated && | |
1683 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1684 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1685 | return 1; | |
1686 | ||
1687 | /* | |
1688 | * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has | |
1689 | * incomplete and conflicting architectural behavior. Current | |
1690 | * AMD CPUs completely ignore bits 63:32, i.e. they aren't | |
1691 | * reserved and always read as zeros. Enforce Intel's reserved | |
1692 | * bits check if and only if the guest CPU is Intel, and clear | |
1693 | * the bits in all other cases. This ensures cross-vendor | |
1694 | * migration will provide consistent behavior for the guest. | |
1695 | */ | |
1696 | if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) | |
1697 | return 1; | |
1698 | ||
1699 | data = (u32)data; | |
1700 | break; | |
854e8bb1 | 1701 | } |
f20935d8 SC |
1702 | |
1703 | msr.data = data; | |
1704 | msr.index = index; | |
1705 | msr.host_initiated = host_initiated; | |
1706 | ||
b3646477 | 1707 | return static_call(kvm_x86_set_msr)(vcpu, &msr); |
15c4a640 CO |
1708 | } |
1709 | ||
6abe9c13 PX |
1710 | static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, |
1711 | u32 index, u64 data, bool host_initiated) | |
1712 | { | |
1713 | int ret = __kvm_set_msr(vcpu, index, data, host_initiated); | |
1714 | ||
1715 | if (ret == KVM_MSR_RET_INVALID) | |
d632826f | 1716 | if (kvm_msr_ignored_check(index, data, true)) |
cc4cb017 | 1717 | ret = 0; |
6abe9c13 PX |
1718 | |
1719 | return ret; | |
1720 | } | |
1721 | ||
313a3dc7 | 1722 | /* |
f20935d8 SC |
1723 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1724 | * checks are bypassed if @host_initiated is %true. | |
1725 | * Returns 0 on success, non-0 otherwise. | |
1726 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1727 | */ |
edef5c36 PB |
1728 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1729 | bool host_initiated) | |
609e36d3 PB |
1730 | { |
1731 | struct msr_data msr; | |
f20935d8 | 1732 | int ret; |
609e36d3 | 1733 | |
1a155254 | 1734 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) |
cc4cb017 | 1735 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1736 | |
61a05d44 SC |
1737 | switch (index) { |
1738 | case MSR_TSC_AUX: | |
1739 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1740 | return 1; | |
1741 | ||
1742 | if (!host_initiated && | |
1743 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1744 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1745 | return 1; | |
1746 | break; | |
1747 | } | |
1748 | ||
609e36d3 | 1749 | msr.index = index; |
f20935d8 | 1750 | msr.host_initiated = host_initiated; |
609e36d3 | 1751 | |
b3646477 | 1752 | ret = static_call(kvm_x86_get_msr)(vcpu, &msr); |
f20935d8 SC |
1753 | if (!ret) |
1754 | *data = msr.data; | |
1755 | return ret; | |
609e36d3 PB |
1756 | } |
1757 | ||
6abe9c13 PX |
1758 | static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, |
1759 | u32 index, u64 *data, bool host_initiated) | |
1760 | { | |
1761 | int ret = __kvm_get_msr(vcpu, index, data, host_initiated); | |
1762 | ||
1763 | if (ret == KVM_MSR_RET_INVALID) { | |
1764 | /* Unconditionally clear *data for simplicity */ | |
1765 | *data = 0; | |
d632826f | 1766 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1767 | ret = 0; |
6abe9c13 PX |
1768 | } |
1769 | ||
1770 | return ret; | |
1771 | } | |
1772 | ||
f20935d8 | 1773 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1774 | { |
6abe9c13 | 1775 | return kvm_get_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1776 | } |
1777 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1778 | |
f20935d8 SC |
1779 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1780 | { | |
6abe9c13 | 1781 | return kvm_set_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1782 | } |
1783 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1784 | ||
8b474427 | 1785 | static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) |
1ae09954 | 1786 | { |
8b474427 PB |
1787 | int err = vcpu->run->msr.error; |
1788 | if (!err) { | |
1ae09954 AG |
1789 | kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); |
1790 | kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); | |
1791 | } | |
1792 | ||
b3646477 | 1793 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, err); |
1ae09954 AG |
1794 | } |
1795 | ||
1796 | static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) | |
1797 | { | |
b3646477 | 1798 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); |
1ae09954 AG |
1799 | } |
1800 | ||
1801 | static u64 kvm_msr_reason(int r) | |
1802 | { | |
1803 | switch (r) { | |
cc4cb017 | 1804 | case KVM_MSR_RET_INVALID: |
1ae09954 | 1805 | return KVM_MSR_EXIT_REASON_UNKNOWN; |
cc4cb017 | 1806 | case KVM_MSR_RET_FILTERED: |
1a155254 | 1807 | return KVM_MSR_EXIT_REASON_FILTER; |
1ae09954 AG |
1808 | default: |
1809 | return KVM_MSR_EXIT_REASON_INVAL; | |
1810 | } | |
1811 | } | |
1812 | ||
1813 | static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, | |
1814 | u32 exit_reason, u64 data, | |
1815 | int (*completion)(struct kvm_vcpu *vcpu), | |
1816 | int r) | |
1817 | { | |
1818 | u64 msr_reason = kvm_msr_reason(r); | |
1819 | ||
1820 | /* Check if the user wanted to know about this MSR fault */ | |
1821 | if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) | |
1822 | return 0; | |
1823 | ||
1824 | vcpu->run->exit_reason = exit_reason; | |
1825 | vcpu->run->msr.error = 0; | |
1826 | memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); | |
1827 | vcpu->run->msr.reason = msr_reason; | |
1828 | vcpu->run->msr.index = index; | |
1829 | vcpu->run->msr.data = data; | |
1830 | vcpu->arch.complete_userspace_io = completion; | |
1831 | ||
1832 | return 1; | |
1833 | } | |
1834 | ||
1835 | static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) | |
1836 | { | |
1837 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, | |
1838 | complete_emulated_rdmsr, r); | |
1839 | } | |
1840 | ||
1841 | static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) | |
1842 | { | |
1843 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, | |
1844 | complete_emulated_wrmsr, r); | |
1845 | } | |
1846 | ||
1edce0a9 SC |
1847 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
1848 | { | |
1849 | u32 ecx = kvm_rcx_read(vcpu); | |
1850 | u64 data; | |
1ae09954 AG |
1851 | int r; |
1852 | ||
1853 | r = kvm_get_msr(vcpu, ecx, &data); | |
1edce0a9 | 1854 | |
1ae09954 AG |
1855 | /* MSR read failed? See if we should ask user space */ |
1856 | if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { | |
1857 | /* Bounce to user space */ | |
1858 | return 0; | |
1859 | } | |
1860 | ||
8b474427 PB |
1861 | if (!r) { |
1862 | trace_kvm_msr_read(ecx, data); | |
1863 | ||
1864 | kvm_rax_write(vcpu, data & -1u); | |
1865 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
1866 | } else { | |
1edce0a9 | 1867 | trace_kvm_msr_read_ex(ecx); |
1edce0a9 SC |
1868 | } |
1869 | ||
b3646477 | 1870 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
1871 | } |
1872 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
1873 | ||
1874 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
1875 | { | |
1876 | u32 ecx = kvm_rcx_read(vcpu); | |
1877 | u64 data = kvm_read_edx_eax(vcpu); | |
1ae09954 | 1878 | int r; |
1edce0a9 | 1879 | |
1ae09954 AG |
1880 | r = kvm_set_msr(vcpu, ecx, data); |
1881 | ||
1882 | /* MSR write failed? See if we should ask user space */ | |
7dffecaf | 1883 | if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) |
1ae09954 AG |
1884 | /* Bounce to user space */ |
1885 | return 0; | |
7dffecaf ML |
1886 | |
1887 | /* Signal all other negative errors to userspace */ | |
1888 | if (r < 0) | |
1889 | return r; | |
1ae09954 | 1890 | |
8b474427 PB |
1891 | if (!r) |
1892 | trace_kvm_msr_write(ecx, data); | |
1893 | else | |
1edce0a9 | 1894 | trace_kvm_msr_write_ex(ecx, data); |
1edce0a9 | 1895 | |
b3646477 | 1896 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
1897 | } |
1898 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
1899 | ||
5ff3a351 SC |
1900 | int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) |
1901 | { | |
1902 | return kvm_skip_emulated_instruction(vcpu); | |
1903 | } | |
1904 | EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); | |
1905 | ||
1906 | int kvm_emulate_invd(struct kvm_vcpu *vcpu) | |
1907 | { | |
1908 | /* Treat an INVD instruction as a NOP and just skip it. */ | |
1909 | return kvm_emulate_as_nop(vcpu); | |
1910 | } | |
1911 | EXPORT_SYMBOL_GPL(kvm_emulate_invd); | |
1912 | ||
1913 | int kvm_emulate_mwait(struct kvm_vcpu *vcpu) | |
1914 | { | |
1915 | pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); | |
1916 | return kvm_emulate_as_nop(vcpu); | |
1917 | } | |
1918 | EXPORT_SYMBOL_GPL(kvm_emulate_mwait); | |
1919 | ||
1920 | int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) | |
1921 | { | |
1922 | kvm_queue_exception(vcpu, UD_VECTOR); | |
1923 | return 1; | |
1924 | } | |
1925 | EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); | |
1926 | ||
1927 | int kvm_emulate_monitor(struct kvm_vcpu *vcpu) | |
1928 | { | |
1929 | pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); | |
1930 | return kvm_emulate_as_nop(vcpu); | |
1931 | } | |
1932 | EXPORT_SYMBOL_GPL(kvm_emulate_monitor); | |
1933 | ||
d89d04ab | 1934 | static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) |
5a9f5443 | 1935 | { |
4ae7dc97 | 1936 | xfer_to_guest_mode_prepare(); |
5a9f5443 | 1937 | return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || |
72c3c0fe | 1938 | xfer_to_guest_mode_work_pending(); |
5a9f5443 | 1939 | } |
5a9f5443 | 1940 | |
1e9e2622 WL |
1941 | /* |
1942 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
1943 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
1944 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
1945 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
1946 | * other cases which must be called after interrupts are enabled on the host. | |
1947 | */ | |
1948 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
1949 | { | |
e1be9ac8 WL |
1950 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) |
1951 | return 1; | |
1952 | ||
1953 | if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && | |
1e9e2622 | 1954 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && |
4064a4c6 WL |
1955 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && |
1956 | ((u32)(data >> 32) != X2APIC_BROADCAST)) { | |
1e9e2622 | 1957 | |
d5361678 WL |
1958 | data &= ~(1 << 12); |
1959 | kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); | |
1e9e2622 | 1960 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); |
d5361678 WL |
1961 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); |
1962 | trace_kvm_apic_write(APIC_ICR, (u32)data); | |
1963 | return 0; | |
1e9e2622 WL |
1964 | } |
1965 | ||
1966 | return 1; | |
1967 | } | |
1968 | ||
ae95f566 WL |
1969 | static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) |
1970 | { | |
1971 | if (!kvm_can_use_hv_timer(vcpu)) | |
1972 | return 1; | |
1973 | ||
1974 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
1975 | return 0; | |
1976 | } | |
1977 | ||
404d5d7b | 1978 | fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) |
1e9e2622 WL |
1979 | { |
1980 | u32 msr = kvm_rcx_read(vcpu); | |
8a1038de | 1981 | u64 data; |
404d5d7b | 1982 | fastpath_t ret = EXIT_FASTPATH_NONE; |
1e9e2622 WL |
1983 | |
1984 | switch (msr) { | |
1985 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
8a1038de | 1986 | data = kvm_read_edx_eax(vcpu); |
404d5d7b WL |
1987 | if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { |
1988 | kvm_skip_emulated_instruction(vcpu); | |
1989 | ret = EXIT_FASTPATH_EXIT_HANDLED; | |
80bc97f2 | 1990 | } |
1e9e2622 | 1991 | break; |
09141ec0 | 1992 | case MSR_IA32_TSC_DEADLINE: |
ae95f566 WL |
1993 | data = kvm_read_edx_eax(vcpu); |
1994 | if (!handle_fastpath_set_tscdeadline(vcpu, data)) { | |
1995 | kvm_skip_emulated_instruction(vcpu); | |
1996 | ret = EXIT_FASTPATH_REENTER_GUEST; | |
1997 | } | |
1998 | break; | |
1e9e2622 | 1999 | default: |
404d5d7b | 2000 | break; |
1e9e2622 WL |
2001 | } |
2002 | ||
404d5d7b | 2003 | if (ret != EXIT_FASTPATH_NONE) |
1e9e2622 | 2004 | trace_kvm_msr_write(msr, data); |
1e9e2622 | 2005 | |
404d5d7b | 2006 | return ret; |
1e9e2622 WL |
2007 | } |
2008 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
2009 | ||
f20935d8 SC |
2010 | /* |
2011 | * Adapt set_msr() to msr_io()'s calling convention | |
2012 | */ | |
2013 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
2014 | { | |
6abe9c13 | 2015 | return kvm_get_msr_ignored_check(vcpu, index, data, true); |
f20935d8 SC |
2016 | } |
2017 | ||
2018 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
2019 | { | |
6abe9c13 | 2020 | return kvm_set_msr_ignored_check(vcpu, index, *data, true); |
313a3dc7 CO |
2021 | } |
2022 | ||
16e8d74d | 2023 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
2024 | struct pvclock_clock { |
2025 | int vclock_mode; | |
2026 | u64 cycle_last; | |
2027 | u64 mask; | |
2028 | u32 mult; | |
2029 | u32 shift; | |
917f9475 PB |
2030 | u64 base_cycles; |
2031 | u64 offset; | |
53fafdbb MT |
2032 | }; |
2033 | ||
16e8d74d MT |
2034 | struct pvclock_gtod_data { |
2035 | seqcount_t seq; | |
2036 | ||
53fafdbb MT |
2037 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
2038 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 2039 | |
917f9475 | 2040 | ktime_t offs_boot; |
55dd00a7 | 2041 | u64 wall_time_sec; |
16e8d74d MT |
2042 | }; |
2043 | ||
2044 | static struct pvclock_gtod_data pvclock_gtod_data; | |
2045 | ||
2046 | static void update_pvclock_gtod(struct timekeeper *tk) | |
2047 | { | |
2048 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
2049 | ||
2050 | write_seqcount_begin(&vdata->seq); | |
2051 | ||
2052 | /* copy pvclock gtod data */ | |
b95a8a27 | 2053 | vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; |
876e7881 PZ |
2054 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; |
2055 | vdata->clock.mask = tk->tkr_mono.mask; | |
2056 | vdata->clock.mult = tk->tkr_mono.mult; | |
2057 | vdata->clock.shift = tk->tkr_mono.shift; | |
917f9475 PB |
2058 | vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; |
2059 | vdata->clock.offset = tk->tkr_mono.base; | |
16e8d74d | 2060 | |
b95a8a27 | 2061 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; |
53fafdbb MT |
2062 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; |
2063 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
2064 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
2065 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
917f9475 PB |
2066 | vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; |
2067 | vdata->raw_clock.offset = tk->tkr_raw.base; | |
16e8d74d | 2068 | |
55dd00a7 MT |
2069 | vdata->wall_time_sec = tk->xtime_sec; |
2070 | ||
917f9475 | 2071 | vdata->offs_boot = tk->offs_boot; |
53fafdbb | 2072 | |
16e8d74d MT |
2073 | write_seqcount_end(&vdata->seq); |
2074 | } | |
8171cd68 PB |
2075 | |
2076 | static s64 get_kvmclock_base_ns(void) | |
2077 | { | |
2078 | /* Count up from boot time, but with the frequency of the raw clock. */ | |
2079 | return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); | |
2080 | } | |
2081 | #else | |
2082 | static s64 get_kvmclock_base_ns(void) | |
2083 | { | |
2084 | /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ | |
2085 | return ktime_get_boottime_ns(); | |
2086 | } | |
16e8d74d MT |
2087 | #endif |
2088 | ||
629b5348 | 2089 | void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) |
18068523 | 2090 | { |
9ed3c444 AK |
2091 | int version; |
2092 | int r; | |
50d0a0f9 | 2093 | struct pvclock_wall_clock wc; |
629b5348 | 2094 | u32 wc_sec_hi; |
8171cd68 | 2095 | u64 wall_nsec; |
18068523 GOC |
2096 | |
2097 | if (!wall_clock) | |
2098 | return; | |
2099 | ||
9ed3c444 AK |
2100 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
2101 | if (r) | |
2102 | return; | |
2103 | ||
2104 | if (version & 1) | |
2105 | ++version; /* first time write, random junk */ | |
2106 | ||
2107 | ++version; | |
18068523 | 2108 | |
1dab1345 NK |
2109 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
2110 | return; | |
18068523 | 2111 | |
50d0a0f9 GH |
2112 | /* |
2113 | * The guest calculates current wall clock time by adding | |
34c238a1 | 2114 | * system time (updated by kvm_guest_time_update below) to the |
8171cd68 | 2115 | * wall clock specified here. We do the reverse here. |
50d0a0f9 | 2116 | */ |
8171cd68 | 2117 | wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); |
50d0a0f9 | 2118 | |
8171cd68 PB |
2119 | wc.nsec = do_div(wall_nsec, 1000000000); |
2120 | wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ | |
50d0a0f9 | 2121 | wc.version = version; |
18068523 GOC |
2122 | |
2123 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
2124 | ||
629b5348 JM |
2125 | if (sec_hi_ofs) { |
2126 | wc_sec_hi = wall_nsec >> 32; | |
2127 | kvm_write_guest(kvm, wall_clock + sec_hi_ofs, | |
2128 | &wc_sec_hi, sizeof(wc_sec_hi)); | |
2129 | } | |
2130 | ||
18068523 GOC |
2131 | version++; |
2132 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
2133 | } |
2134 | ||
5b9bb0eb OU |
2135 | static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, |
2136 | bool old_msr, bool host_initiated) | |
2137 | { | |
2138 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
2139 | ||
2140 | if (vcpu->vcpu_id == 0 && !host_initiated) { | |
1e293d1a | 2141 | if (ka->boot_vcpu_runs_old_kvmclock != old_msr) |
5b9bb0eb OU |
2142 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2143 | ||
2144 | ka->boot_vcpu_runs_old_kvmclock = old_msr; | |
2145 | } | |
2146 | ||
2147 | vcpu->arch.time = system_time; | |
2148 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
2149 | ||
2150 | /* we verify if the enable bit is set... */ | |
2151 | vcpu->arch.pv_time_enabled = false; | |
2152 | if (!(system_time & 1)) | |
2153 | return; | |
2154 | ||
2155 | if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
2156 | &vcpu->arch.pv_time, system_time & ~1ULL, | |
2157 | sizeof(struct pvclock_vcpu_time_info))) | |
2158 | vcpu->arch.pv_time_enabled = true; | |
2159 | ||
2160 | return; | |
2161 | } | |
2162 | ||
50d0a0f9 GH |
2163 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
2164 | { | |
b51012de PB |
2165 | do_shl32_div32(dividend, divisor); |
2166 | return dividend; | |
50d0a0f9 GH |
2167 | } |
2168 | ||
3ae13faa | 2169 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 2170 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 2171 | { |
5f4e3f88 | 2172 | uint64_t scaled64; |
50d0a0f9 GH |
2173 | int32_t shift = 0; |
2174 | uint64_t tps64; | |
2175 | uint32_t tps32; | |
2176 | ||
3ae13faa PB |
2177 | tps64 = base_hz; |
2178 | scaled64 = scaled_hz; | |
50933623 | 2179 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
2180 | tps64 >>= 1; |
2181 | shift--; | |
2182 | } | |
2183 | ||
2184 | tps32 = (uint32_t)tps64; | |
50933623 JK |
2185 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
2186 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
2187 | scaled64 >>= 1; |
2188 | else | |
2189 | tps32 <<= 1; | |
50d0a0f9 GH |
2190 | shift++; |
2191 | } | |
2192 | ||
5f4e3f88 ZA |
2193 | *pshift = shift; |
2194 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
2195 | } |
2196 | ||
d828199e | 2197 | #ifdef CONFIG_X86_64 |
16e8d74d | 2198 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 2199 | #endif |
16e8d74d | 2200 | |
c8076604 | 2201 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 2202 | static unsigned long max_tsc_khz; |
c8076604 | 2203 | |
cc578287 | 2204 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 2205 | { |
cc578287 ZA |
2206 | u64 v = (u64)khz * (1000000 + ppm); |
2207 | do_div(v, 1000000); | |
2208 | return v; | |
1e993611 JR |
2209 | } |
2210 | ||
1ab9287a IS |
2211 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); |
2212 | ||
381d585c HZ |
2213 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
2214 | { | |
2215 | u64 ratio; | |
2216 | ||
2217 | /* Guest TSC same frequency as host TSC? */ | |
2218 | if (!scale) { | |
1ab9287a | 2219 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); |
381d585c HZ |
2220 | return 0; |
2221 | } | |
2222 | ||
2223 | /* TSC scaling supported? */ | |
2224 | if (!kvm_has_tsc_control) { | |
2225 | if (user_tsc_khz > tsc_khz) { | |
2226 | vcpu->arch.tsc_catchup = 1; | |
2227 | vcpu->arch.tsc_always_catchup = 1; | |
2228 | return 0; | |
2229 | } else { | |
3f16a5c3 | 2230 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
2231 | return -1; |
2232 | } | |
2233 | } | |
2234 | ||
2235 | /* TSC scaling required - calculate ratio */ | |
2236 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
2237 | user_tsc_khz, tsc_khz); | |
2238 | ||
2239 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
3f16a5c3 PB |
2240 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
2241 | user_tsc_khz); | |
381d585c HZ |
2242 | return -1; |
2243 | } | |
2244 | ||
1ab9287a | 2245 | kvm_vcpu_write_tsc_multiplier(vcpu, ratio); |
381d585c HZ |
2246 | return 0; |
2247 | } | |
2248 | ||
4941b8cb | 2249 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 2250 | { |
cc578287 ZA |
2251 | u32 thresh_lo, thresh_hi; |
2252 | int use_scaling = 0; | |
217fc9cf | 2253 | |
03ba32ca | 2254 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 2255 | if (user_tsc_khz == 0) { |
ad721883 | 2256 | /* set tsc_scaling_ratio to a safe value */ |
1ab9287a | 2257 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); |
381d585c | 2258 | return -1; |
ad721883 | 2259 | } |
03ba32ca | 2260 | |
c285545f | 2261 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 2262 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
2263 | &vcpu->arch.virtual_tsc_shift, |
2264 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 2265 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
2266 | |
2267 | /* | |
2268 | * Compute the variation in TSC rate which is acceptable | |
2269 | * within the range of tolerance and decide if the | |
2270 | * rate being applied is within that bounds of the hardware | |
2271 | * rate. If so, no scaling or compensation need be done. | |
2272 | */ | |
2273 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
2274 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
2275 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
2276 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
2277 | use_scaling = 1; |
2278 | } | |
4941b8cb | 2279 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
2280 | } |
2281 | ||
2282 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
2283 | { | |
e26101b1 | 2284 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
2285 | vcpu->arch.virtual_tsc_mult, |
2286 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 2287 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
2288 | return tsc; |
2289 | } | |
2290 | ||
b0c39dc6 VK |
2291 | static inline int gtod_is_based_on_tsc(int mode) |
2292 | { | |
b95a8a27 | 2293 | return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; |
b0c39dc6 VK |
2294 | } |
2295 | ||
69b0049a | 2296 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
2297 | { |
2298 | #ifdef CONFIG_X86_64 | |
2299 | bool vcpus_matched; | |
b48aa97e MT |
2300 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2301 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2302 | ||
2303 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2304 | atomic_read(&vcpu->kvm->online_vcpus)); | |
2305 | ||
7f187922 MT |
2306 | /* |
2307 | * Once the masterclock is enabled, always perform request in | |
2308 | * order to update it. | |
2309 | * | |
2310 | * In order to enable masterclock, the host clocksource must be TSC | |
2311 | * and the vcpus need to have matched TSCs. When that happens, | |
2312 | * perform request to enable masterclock. | |
2313 | */ | |
2314 | if (ka->use_master_clock || | |
b0c39dc6 | 2315 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
2316 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2317 | ||
2318 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
2319 | atomic_read(&vcpu->kvm->online_vcpus), | |
2320 | ka->use_master_clock, gtod->clock.vclock_mode); | |
2321 | #endif | |
2322 | } | |
2323 | ||
35181e86 HZ |
2324 | /* |
2325 | * Multiply tsc by a fixed point number represented by ratio. | |
2326 | * | |
2327 | * The most significant 64-N bits (mult) of ratio represent the | |
2328 | * integral part of the fixed point number; the remaining N bits | |
2329 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
2330 | * point number (mult + frac * 2^(-N)). | |
2331 | * | |
2332 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
2333 | */ | |
2334 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
2335 | { | |
2336 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
2337 | } | |
2338 | ||
fe3eb504 | 2339 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc, u64 ratio) |
35181e86 HZ |
2340 | { |
2341 | u64 _tsc = tsc; | |
35181e86 HZ |
2342 | |
2343 | if (ratio != kvm_default_tsc_scaling_ratio) | |
2344 | _tsc = __scale_tsc(ratio, tsc); | |
2345 | ||
2346 | return _tsc; | |
2347 | } | |
2348 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
2349 | ||
9b399dfd | 2350 | static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
07c1419a HZ |
2351 | { |
2352 | u64 tsc; | |
2353 | ||
fe3eb504 | 2354 | tsc = kvm_scale_tsc(vcpu, rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); |
07c1419a HZ |
2355 | |
2356 | return target_tsc - tsc; | |
2357 | } | |
2358 | ||
4ba76538 HZ |
2359 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
2360 | { | |
fe3eb504 IS |
2361 | return vcpu->arch.l1_tsc_offset + |
2362 | kvm_scale_tsc(vcpu, host_tsc, vcpu->arch.l1_tsc_scaling_ratio); | |
4ba76538 HZ |
2363 | } |
2364 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
2365 | ||
83150f29 IS |
2366 | u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) |
2367 | { | |
2368 | u64 nested_offset; | |
2369 | ||
2370 | if (l2_multiplier == kvm_default_tsc_scaling_ratio) | |
2371 | nested_offset = l1_offset; | |
2372 | else | |
2373 | nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, | |
2374 | kvm_tsc_scaling_ratio_frac_bits); | |
2375 | ||
2376 | nested_offset += l2_offset; | |
2377 | return nested_offset; | |
2378 | } | |
2379 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); | |
2380 | ||
2381 | u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) | |
2382 | { | |
2383 | if (l2_multiplier != kvm_default_tsc_scaling_ratio) | |
2384 | return mul_u64_u64_shr(l1_multiplier, l2_multiplier, | |
2385 | kvm_tsc_scaling_ratio_frac_bits); | |
2386 | ||
2387 | return l1_multiplier; | |
2388 | } | |
2389 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); | |
2390 | ||
edcfe540 | 2391 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) |
a545ab6a | 2392 | { |
edcfe540 IS |
2393 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2394 | vcpu->arch.l1_tsc_offset, | |
2395 | l1_offset); | |
2396 | ||
2397 | vcpu->arch.l1_tsc_offset = l1_offset; | |
2398 | ||
2399 | /* | |
2400 | * If we are here because L1 chose not to trap WRMSR to TSC then | |
2401 | * according to the spec this should set L1's TSC (as opposed to | |
2402 | * setting L1's offset for L2). | |
2403 | */ | |
2404 | if (is_guest_mode(vcpu)) | |
2405 | vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( | |
2406 | l1_offset, | |
2407 | static_call(kvm_x86_get_l2_tsc_offset)(vcpu), | |
2408 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2409 | else | |
2410 | vcpu->arch.tsc_offset = l1_offset; | |
2411 | ||
2412 | static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); | |
a545ab6a LC |
2413 | } |
2414 | ||
1ab9287a IS |
2415 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) |
2416 | { | |
2417 | vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; | |
2418 | ||
2419 | /* Userspace is changing the multiplier while L2 is active */ | |
2420 | if (is_guest_mode(vcpu)) | |
2421 | vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( | |
2422 | l1_multiplier, | |
2423 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2424 | else | |
2425 | vcpu->arch.tsc_scaling_ratio = l1_multiplier; | |
2426 | ||
2427 | if (kvm_has_tsc_control) | |
2428 | static_call(kvm_x86_write_tsc_multiplier)( | |
2429 | vcpu, vcpu->arch.tsc_scaling_ratio); | |
2430 | } | |
2431 | ||
b0c39dc6 VK |
2432 | static inline bool kvm_check_tsc_unstable(void) |
2433 | { | |
2434 | #ifdef CONFIG_X86_64 | |
2435 | /* | |
2436 | * TSC is marked unstable when we're running on Hyper-V, | |
2437 | * 'TSC page' clocksource is good. | |
2438 | */ | |
b95a8a27 | 2439 | if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) |
b0c39dc6 VK |
2440 | return false; |
2441 | #endif | |
2442 | return check_tsc_unstable(); | |
2443 | } | |
2444 | ||
0c899c25 | 2445 | static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) |
99e3e30a ZA |
2446 | { |
2447 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 2448 | u64 offset, ns, elapsed; |
99e3e30a | 2449 | unsigned long flags; |
b48aa97e | 2450 | bool matched; |
0d3da0d2 | 2451 | bool already_matched; |
c5e8ec8e | 2452 | bool synchronizing = false; |
99e3e30a | 2453 | |
038f8c11 | 2454 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
9b399dfd | 2455 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
8171cd68 | 2456 | ns = get_kvmclock_base_ns(); |
f38e098f | 2457 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 2458 | |
03ba32ca | 2459 | if (vcpu->arch.virtual_tsc_khz) { |
0c899c25 | 2460 | if (data == 0) { |
bd8fab39 DP |
2461 | /* |
2462 | * detection of vcpu initialization -- need to sync | |
2463 | * with other vCPUs. This particularly helps to keep | |
2464 | * kvm_clock stable after CPU hotplug | |
2465 | */ | |
2466 | synchronizing = true; | |
2467 | } else { | |
2468 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
2469 | nsec_to_cycles(vcpu, elapsed); | |
2470 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
2471 | /* | |
2472 | * Special case: TSC write with a small delta (1 second) | |
2473 | * of virtual cycle time against real time is | |
2474 | * interpreted as an attempt to synchronize the CPU. | |
2475 | */ | |
2476 | synchronizing = data < tsc_exp + tsc_hz && | |
2477 | data + tsc_hz > tsc_exp; | |
2478 | } | |
c5e8ec8e | 2479 | } |
f38e098f ZA |
2480 | |
2481 | /* | |
5d3cb0f6 ZA |
2482 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
2483 | * TSC, we add elapsed time in this computation. We could let the | |
2484 | * compensation code attempt to catch up if we fall behind, but | |
2485 | * it's better to try to match offsets from the beginning. | |
2486 | */ | |
c5e8ec8e | 2487 | if (synchronizing && |
5d3cb0f6 | 2488 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 2489 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 2490 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 2491 | } else { |
857e4099 | 2492 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 2493 | data += delta; |
9b399dfd | 2494 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
f38e098f | 2495 | } |
b48aa97e | 2496 | matched = true; |
0d3da0d2 | 2497 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
2498 | } else { |
2499 | /* | |
2500 | * We split periods of matched TSC writes into generations. | |
2501 | * For each generation, we track the original measured | |
2502 | * nanosecond time, offset, and write, so if TSCs are in | |
2503 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 2504 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
2505 | * |
2506 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2507 | */ | |
2508 | kvm->arch.cur_tsc_generation++; | |
2509 | kvm->arch.cur_tsc_nsec = ns; | |
2510 | kvm->arch.cur_tsc_write = data; | |
2511 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 2512 | matched = false; |
f38e098f | 2513 | } |
e26101b1 ZA |
2514 | |
2515 | /* | |
2516 | * We also track th most recent recorded KHZ, write and time to | |
2517 | * allow the matching interval to be extended at each write. | |
2518 | */ | |
f38e098f ZA |
2519 | kvm->arch.last_tsc_nsec = ns; |
2520 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 2521 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 2522 | |
b183aa58 | 2523 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
2524 | |
2525 | /* Keep track of which generation this VCPU has synchronized to */ | |
2526 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2527 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2528 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2529 | ||
a545ab6a | 2530 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
e26101b1 | 2531 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
b48aa97e | 2532 | |
a83829f5 | 2533 | spin_lock_irqsave(&kvm->arch.pvclock_gtod_sync_lock, flags); |
0d3da0d2 | 2534 | if (!matched) { |
b48aa97e | 2535 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
2536 | } else if (!already_matched) { |
2537 | kvm->arch.nr_vcpus_matched_tsc++; | |
2538 | } | |
b48aa97e MT |
2539 | |
2540 | kvm_track_tsc_matching(vcpu); | |
a83829f5 | 2541 | spin_unlock_irqrestore(&kvm->arch.pvclock_gtod_sync_lock, flags); |
99e3e30a | 2542 | } |
e26101b1 | 2543 | |
58ea6767 HZ |
2544 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2545 | s64 adjustment) | |
2546 | { | |
56ba77a4 | 2547 | u64 tsc_offset = vcpu->arch.l1_tsc_offset; |
326e7425 | 2548 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); |
58ea6767 HZ |
2549 | } |
2550 | ||
2551 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2552 | { | |
805d705f | 2553 | if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) |
58ea6767 | 2554 | WARN_ON(adjustment < 0); |
fe3eb504 IS |
2555 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment, |
2556 | vcpu->arch.l1_tsc_scaling_ratio); | |
ea26e4ec | 2557 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2558 | } |
2559 | ||
d828199e MT |
2560 | #ifdef CONFIG_X86_64 |
2561 | ||
a5a1d1c2 | 2562 | static u64 read_tsc(void) |
d828199e | 2563 | { |
a5a1d1c2 | 2564 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2565 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2566 | |
2567 | if (likely(ret >= last)) | |
2568 | return ret; | |
2569 | ||
2570 | /* | |
2571 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2572 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2573 | * very likely) and there's a data dependence, so force GCC |
2574 | * to generate a branch instead. I don't barrier() because | |
2575 | * we don't actually need a barrier, and if this function | |
2576 | * ever gets inlined it will generate worse code. | |
2577 | */ | |
2578 | asm volatile (""); | |
2579 | return last; | |
2580 | } | |
2581 | ||
53fafdbb MT |
2582 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2583 | int *mode) | |
d828199e MT |
2584 | { |
2585 | long v; | |
b0c39dc6 VK |
2586 | u64 tsc_pg_val; |
2587 | ||
53fafdbb | 2588 | switch (clock->vclock_mode) { |
b95a8a27 | 2589 | case VDSO_CLOCKMODE_HVCLOCK: |
b0c39dc6 VK |
2590 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), |
2591 | tsc_timestamp); | |
2592 | if (tsc_pg_val != U64_MAX) { | |
2593 | /* TSC page valid */ | |
b95a8a27 | 2594 | *mode = VDSO_CLOCKMODE_HVCLOCK; |
53fafdbb MT |
2595 | v = (tsc_pg_val - clock->cycle_last) & |
2596 | clock->mask; | |
b0c39dc6 VK |
2597 | } else { |
2598 | /* TSC page invalid */ | |
b95a8a27 | 2599 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 VK |
2600 | } |
2601 | break; | |
b95a8a27 TG |
2602 | case VDSO_CLOCKMODE_TSC: |
2603 | *mode = VDSO_CLOCKMODE_TSC; | |
b0c39dc6 | 2604 | *tsc_timestamp = read_tsc(); |
53fafdbb MT |
2605 | v = (*tsc_timestamp - clock->cycle_last) & |
2606 | clock->mask; | |
b0c39dc6 VK |
2607 | break; |
2608 | default: | |
b95a8a27 | 2609 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 | 2610 | } |
d828199e | 2611 | |
b95a8a27 | 2612 | if (*mode == VDSO_CLOCKMODE_NONE) |
b0c39dc6 | 2613 | *tsc_timestamp = v = 0; |
d828199e | 2614 | |
53fafdbb | 2615 | return v * clock->mult; |
d828199e MT |
2616 | } |
2617 | ||
53fafdbb | 2618 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2619 | { |
cbcf2dd3 | 2620 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2621 | unsigned long seq; |
d828199e | 2622 | int mode; |
cbcf2dd3 | 2623 | u64 ns; |
d828199e | 2624 | |
d828199e MT |
2625 | do { |
2626 | seq = read_seqcount_begin(>od->seq); | |
917f9475 | 2627 | ns = gtod->raw_clock.base_cycles; |
53fafdbb | 2628 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); |
917f9475 PB |
2629 | ns >>= gtod->raw_clock.shift; |
2630 | ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); | |
d828199e | 2631 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2632 | *t = ns; |
d828199e MT |
2633 | |
2634 | return mode; | |
2635 | } | |
2636 | ||
899a31f5 | 2637 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2638 | { |
2639 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2640 | unsigned long seq; | |
2641 | int mode; | |
2642 | u64 ns; | |
2643 | ||
2644 | do { | |
2645 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 | 2646 | ts->tv_sec = gtod->wall_time_sec; |
917f9475 | 2647 | ns = gtod->clock.base_cycles; |
53fafdbb | 2648 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2649 | ns >>= gtod->clock.shift; |
2650 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2651 | ||
2652 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2653 | ts->tv_nsec = ns; | |
2654 | ||
2655 | return mode; | |
2656 | } | |
2657 | ||
b0c39dc6 VK |
2658 | /* returns true if host is using TSC based clocksource */ |
2659 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2660 | { |
d828199e | 2661 | /* checked again under seqlock below */ |
b0c39dc6 | 2662 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2663 | return false; |
2664 | ||
53fafdbb | 2665 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2666 | tsc_timestamp)); |
d828199e | 2667 | } |
55dd00a7 | 2668 | |
b0c39dc6 | 2669 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2670 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2671 | u64 *tsc_timestamp) |
55dd00a7 MT |
2672 | { |
2673 | /* checked again under seqlock below */ | |
b0c39dc6 | 2674 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2675 | return false; |
2676 | ||
b0c39dc6 | 2677 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2678 | } |
d828199e MT |
2679 | #endif |
2680 | ||
2681 | /* | |
2682 | * | |
b48aa97e MT |
2683 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2684 | * across virtual CPUs, the following condition is possible. | |
2685 | * Each numbered line represents an event visible to both | |
d828199e MT |
2686 | * CPUs at the next numbered event. |
2687 | * | |
2688 | * "timespecX" represents host monotonic time. "tscX" represents | |
2689 | * RDTSC value. | |
2690 | * | |
2691 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2692 | * | |
2693 | * 1. read timespec0,tsc0 | |
2694 | * 2. | timespec1 = timespec0 + N | |
2695 | * | tsc1 = tsc0 + M | |
2696 | * 3. transition to guest | transition to guest | |
2697 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2698 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2699 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2700 | * | |
2701 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2702 | * | |
2703 | * - ret0 < ret1 | |
2704 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2705 | * ... | |
2706 | * - 0 < N - M => M < N | |
2707 | * | |
2708 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2709 | * always the case (the difference between two distinct xtime instances | |
2710 | * might be smaller then the difference between corresponding TSC reads, | |
2711 | * when updating guest vcpus pvclock areas). | |
2712 | * | |
2713 | * To avoid that problem, do not allow visibility of distinct | |
2714 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2715 | * copy of host monotonic time values. Update that master copy | |
2716 | * in lockstep. | |
2717 | * | |
b48aa97e | 2718 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2719 | * |
2720 | */ | |
2721 | ||
2722 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2723 | { | |
2724 | #ifdef CONFIG_X86_64 | |
2725 | struct kvm_arch *ka = &kvm->arch; | |
2726 | int vclock_mode; | |
b48aa97e MT |
2727 | bool host_tsc_clocksource, vcpus_matched; |
2728 | ||
2729 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2730 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2731 | |
2732 | /* | |
2733 | * If the host uses TSC clock, then passthrough TSC as stable | |
2734 | * to the guest. | |
2735 | */ | |
b48aa97e | 2736 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2737 | &ka->master_kernel_ns, |
2738 | &ka->master_cycle_now); | |
2739 | ||
16a96021 | 2740 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2741 | && !ka->backwards_tsc_observed |
54750f2c | 2742 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2743 | |
d828199e MT |
2744 | if (ka->use_master_clock) |
2745 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2746 | ||
2747 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2748 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2749 | vcpus_matched); | |
d828199e MT |
2750 | #endif |
2751 | } | |
2752 | ||
2860c4b1 PB |
2753 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2754 | { | |
2755 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2756 | } | |
2757 | ||
2e762ff7 MT |
2758 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
2759 | { | |
2760 | #ifdef CONFIG_X86_64 | |
2761 | int i; | |
2762 | struct kvm_vcpu *vcpu; | |
2763 | struct kvm_arch *ka = &kvm->arch; | |
a83829f5 | 2764 | unsigned long flags; |
2e762ff7 | 2765 | |
e880c6ea VK |
2766 | kvm_hv_invalidate_tsc_page(kvm); |
2767 | ||
2e762ff7 | 2768 | kvm_make_mclock_inprogress_request(kvm); |
c2c647f9 | 2769 | |
2e762ff7 | 2770 | /* no guest entries from this point */ |
a83829f5 | 2771 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
2e762ff7 | 2772 | pvclock_update_vm_gtod_copy(kvm); |
a83829f5 | 2773 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
2e762ff7 MT |
2774 | |
2775 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 2776 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2777 | |
2778 | /* guest entries allowed */ | |
2779 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2780 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
2781 | #endif |
2782 | } | |
2783 | ||
e891a32e | 2784 | u64 get_kvmclock_ns(struct kvm *kvm) |
108b249c | 2785 | { |
108b249c | 2786 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2787 | struct pvclock_vcpu_time_info hv_clock; |
a83829f5 | 2788 | unsigned long flags; |
e2c2206a | 2789 | u64 ret; |
108b249c | 2790 | |
a83829f5 | 2791 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
8b953440 | 2792 | if (!ka->use_master_clock) { |
a83829f5 | 2793 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
8171cd68 | 2794 | return get_kvmclock_base_ns() + ka->kvmclock_offset; |
108b249c PB |
2795 | } |
2796 | ||
8b953440 PB |
2797 | hv_clock.tsc_timestamp = ka->master_cycle_now; |
2798 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
a83829f5 | 2799 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
8b953440 | 2800 | |
e2c2206a WL |
2801 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2802 | get_cpu(); | |
2803 | ||
e70b57a6 WL |
2804 | if (__this_cpu_read(cpu_tsc_khz)) { |
2805 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, | |
2806 | &hv_clock.tsc_shift, | |
2807 | &hv_clock.tsc_to_system_mul); | |
2808 | ret = __pvclock_read_cycles(&hv_clock, rdtsc()); | |
2809 | } else | |
8171cd68 | 2810 | ret = get_kvmclock_base_ns() + ka->kvmclock_offset; |
e2c2206a WL |
2811 | |
2812 | put_cpu(); | |
2813 | ||
2814 | return ret; | |
108b249c PB |
2815 | } |
2816 | ||
aa096aa0 JM |
2817 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v, |
2818 | struct gfn_to_hva_cache *cache, | |
2819 | unsigned int offset) | |
0d6dd2ff PB |
2820 | { |
2821 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
2822 | struct pvclock_vcpu_time_info guest_hv_clock; | |
2823 | ||
aa096aa0 JM |
2824 | if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, |
2825 | &guest_hv_clock, offset, sizeof(guest_hv_clock)))) | |
0d6dd2ff PB |
2826 | return; |
2827 | ||
2828 | /* This VCPU is paused, but it's legal for a guest to read another | |
2829 | * VCPU's kvmclock, so we really have to follow the specification where | |
2830 | * it says that version is odd if data is being modified, and even after | |
2831 | * it is consistent. | |
2832 | * | |
2833 | * Version field updates must be kept separate. This is because | |
2834 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
2835 | * writes within a string instruction are weakly ordered. So there | |
2836 | * are three writes overall. | |
2837 | * | |
2838 | * As a small optimization, only write the version field in the first | |
2839 | * and third write. The vcpu->pv_time cache is still valid, because the | |
2840 | * version field is the first in the struct. | |
2841 | */ | |
2842 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
2843 | ||
51c4b8bb LA |
2844 | if (guest_hv_clock.version & 1) |
2845 | ++guest_hv_clock.version; /* first time write, random junk */ | |
2846 | ||
0d6dd2ff | 2847 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
aa096aa0 JM |
2848 | kvm_write_guest_offset_cached(v->kvm, cache, |
2849 | &vcpu->hv_clock, offset, | |
2850 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2851 | |
2852 | smp_wmb(); | |
2853 | ||
2854 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
2855 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
2856 | ||
2857 | if (vcpu->pvclock_set_guest_stopped_request) { | |
2858 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
2859 | vcpu->pvclock_set_guest_stopped_request = false; | |
2860 | } | |
2861 | ||
2862 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
2863 | ||
aa096aa0 JM |
2864 | kvm_write_guest_offset_cached(v->kvm, cache, |
2865 | &vcpu->hv_clock, offset, | |
2866 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
2867 | |
2868 | smp_wmb(); | |
2869 | ||
2870 | vcpu->hv_clock.version++; | |
aa096aa0 JM |
2871 | kvm_write_guest_offset_cached(v->kvm, cache, |
2872 | &vcpu->hv_clock, offset, | |
2873 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2874 | } |
2875 | ||
34c238a1 | 2876 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 2877 | { |
78db6a50 | 2878 | unsigned long flags, tgt_tsc_khz; |
18068523 | 2879 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 2880 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 2881 | s64 kernel_ns; |
d828199e | 2882 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 2883 | u8 pvclock_flags; |
d828199e MT |
2884 | bool use_master_clock; |
2885 | ||
2886 | kernel_ns = 0; | |
2887 | host_tsc = 0; | |
18068523 | 2888 | |
d828199e MT |
2889 | /* |
2890 | * If the host uses TSC clock, then passthrough TSC as stable | |
2891 | * to the guest. | |
2892 | */ | |
a83829f5 | 2893 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
d828199e MT |
2894 | use_master_clock = ka->use_master_clock; |
2895 | if (use_master_clock) { | |
2896 | host_tsc = ka->master_cycle_now; | |
2897 | kernel_ns = ka->master_kernel_ns; | |
2898 | } | |
a83829f5 | 2899 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
c09664bb MT |
2900 | |
2901 | /* Keep irq disabled to prevent changes to the clock */ | |
2902 | local_irq_save(flags); | |
78db6a50 PB |
2903 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2904 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2905 | local_irq_restore(flags); |
2906 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2907 | return 1; | |
2908 | } | |
d828199e | 2909 | if (!use_master_clock) { |
4ea1636b | 2910 | host_tsc = rdtsc(); |
8171cd68 | 2911 | kernel_ns = get_kvmclock_base_ns(); |
d828199e MT |
2912 | } |
2913 | ||
4ba76538 | 2914 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2915 | |
c285545f ZA |
2916 | /* |
2917 | * We may have to catch up the TSC to match elapsed wall clock | |
2918 | * time for two reasons, even if kvmclock is used. | |
2919 | * 1) CPU could have been running below the maximum TSC rate | |
2920 | * 2) Broken TSC compensation resets the base at each VCPU | |
2921 | * entry to avoid unknown leaps of TSC even when running | |
2922 | * again on the same CPU. This may cause apparent elapsed | |
2923 | * time to disappear, and the guest to stand still or run | |
2924 | * very slowly. | |
2925 | */ | |
2926 | if (vcpu->tsc_catchup) { | |
2927 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
2928 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 2929 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
2930 | tsc_timestamp = tsc; |
2931 | } | |
50d0a0f9 GH |
2932 | } |
2933 | ||
18068523 GOC |
2934 | local_irq_restore(flags); |
2935 | ||
0d6dd2ff | 2936 | /* With all the info we got, fill in the values */ |
18068523 | 2937 | |
78db6a50 | 2938 | if (kvm_has_tsc_control) |
fe3eb504 IS |
2939 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz, |
2940 | v->arch.l1_tsc_scaling_ratio); | |
78db6a50 PB |
2941 | |
2942 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 2943 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
2944 | &vcpu->hv_clock.tsc_shift, |
2945 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 2946 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
2947 | } |
2948 | ||
1d5f066e | 2949 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 2950 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 2951 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 2952 | |
d828199e | 2953 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 2954 | pvclock_flags = 0; |
d828199e MT |
2955 | if (use_master_clock) |
2956 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
2957 | ||
78c0337a MT |
2958 | vcpu->hv_clock.flags = pvclock_flags; |
2959 | ||
095cf55d | 2960 | if (vcpu->pv_time_enabled) |
aa096aa0 JM |
2961 | kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); |
2962 | if (vcpu->xen.vcpu_info_set) | |
2963 | kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, | |
2964 | offsetof(struct compat_vcpu_info, time)); | |
f2340cd9 JM |
2965 | if (vcpu->xen.vcpu_time_info_set) |
2966 | kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); | |
095cf55d PB |
2967 | if (v == kvm_get_vcpu(v->kvm, 0)) |
2968 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); | |
8cfdc000 | 2969 | return 0; |
c8076604 GH |
2970 | } |
2971 | ||
0061d53d MT |
2972 | /* |
2973 | * kvmclock updates which are isolated to a given vcpu, such as | |
2974 | * vcpu->cpu migration, should not allow system_timestamp from | |
2975 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
2976 | * correction applies to one vcpu's system_timestamp but not | |
2977 | * the others. | |
2978 | * | |
2979 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
2980 | * We need to rate-limit these requests though, as they can |
2981 | * considerably slow guests that have a large number of vcpus. | |
2982 | * The time for a remote vcpu to update its kvmclock is bound | |
2983 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
2984 | */ |
2985 | ||
7e44e449 AJ |
2986 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
2987 | ||
2988 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
2989 | { |
2990 | int i; | |
7e44e449 AJ |
2991 | struct delayed_work *dwork = to_delayed_work(work); |
2992 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2993 | kvmclock_update_work); | |
2994 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
2995 | struct kvm_vcpu *vcpu; |
2996 | ||
2997 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 2998 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
2999 | kvm_vcpu_kick(vcpu); |
3000 | } | |
3001 | } | |
3002 | ||
7e44e449 AJ |
3003 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
3004 | { | |
3005 | struct kvm *kvm = v->kvm; | |
3006 | ||
105b21bb | 3007 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
3008 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
3009 | KVMCLOCK_UPDATE_DELAY); | |
3010 | } | |
3011 | ||
332967a3 AJ |
3012 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
3013 | ||
3014 | static void kvmclock_sync_fn(struct work_struct *work) | |
3015 | { | |
3016 | struct delayed_work *dwork = to_delayed_work(work); | |
3017 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
3018 | kvmclock_sync_work); | |
3019 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
3020 | ||
630994b3 MT |
3021 | if (!kvmclock_periodic_sync) |
3022 | return; | |
3023 | ||
332967a3 AJ |
3024 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
3025 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
3026 | KVMCLOCK_SYNC_PERIOD); | |
3027 | } | |
3028 | ||
191c8137 BP |
3029 | /* |
3030 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
3031 | */ | |
3032 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
3033 | { | |
3034 | /* McStatusWrEn enabled? */ | |
23493d0a | 3035 | if (guest_cpuid_is_amd_or_hygon(vcpu)) |
191c8137 BP |
3036 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); |
3037 | ||
3038 | return false; | |
3039 | } | |
3040 | ||
9ffd986c | 3041 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3042 | { |
890ca9ae HY |
3043 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3044 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
3045 | u32 msr = msr_info->index; |
3046 | u64 data = msr_info->data; | |
890ca9ae | 3047 | |
15c4a640 | 3048 | switch (msr) { |
15c4a640 | 3049 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 3050 | vcpu->arch.mcg_status = data; |
15c4a640 | 3051 | break; |
c7ac679c | 3052 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
3053 | if (!(mcg_cap & MCG_CTL_P) && |
3054 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
3055 | return 1; |
3056 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 3057 | return 1; |
890ca9ae HY |
3058 | vcpu->arch.mcg_ctl = data; |
3059 | break; | |
3060 | default: | |
3061 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3062 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3063 | u32 offset = array_index_nospec( |
3064 | msr - MSR_IA32_MC0_CTL, | |
3065 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3066 | ||
114be429 AP |
3067 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
3068 | * some Linux kernels though clear bit 10 in bank 4 to | |
3069 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
3070 | * this to avoid an uncatched #GP in the guest | |
3071 | */ | |
890ca9ae | 3072 | if ((offset & 0x3) == 0 && |
114be429 | 3073 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 3074 | return -1; |
191c8137 BP |
3075 | |
3076 | /* MCi_STATUS */ | |
9ffd986c | 3077 | if (!msr_info->host_initiated && |
191c8137 BP |
3078 | (offset & 0x3) == 1 && data != 0) { |
3079 | if (!can_set_mci_status(vcpu)) | |
3080 | return -1; | |
3081 | } | |
3082 | ||
890ca9ae HY |
3083 | vcpu->arch.mce_banks[offset] = data; |
3084 | break; | |
3085 | } | |
3086 | return 1; | |
3087 | } | |
3088 | return 0; | |
3089 | } | |
3090 | ||
2635b5c4 VK |
3091 | static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) |
3092 | { | |
3093 | u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; | |
3094 | ||
3095 | return (vcpu->arch.apf.msr_en_val & mask) == mask; | |
3096 | } | |
3097 | ||
344d9588 GN |
3098 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
3099 | { | |
3100 | gpa_t gpa = data & ~0x3f; | |
3101 | ||
2635b5c4 VK |
3102 | /* Bits 4:5 are reserved, Should be zero */ |
3103 | if (data & 0x30) | |
344d9588 GN |
3104 | return 1; |
3105 | ||
66570e96 OU |
3106 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && |
3107 | (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) | |
3108 | return 1; | |
3109 | ||
3110 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && | |
3111 | (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) | |
3112 | return 1; | |
3113 | ||
9d3c447c | 3114 | if (!lapic_in_kernel(vcpu)) |
d831de17 | 3115 | return data ? 1 : 0; |
9d3c447c | 3116 | |
2635b5c4 | 3117 | vcpu->arch.apf.msr_en_val = data; |
344d9588 | 3118 | |
2635b5c4 | 3119 | if (!kvm_pv_async_pf_enabled(vcpu)) { |
344d9588 GN |
3120 | kvm_clear_async_pf_completion_queue(vcpu); |
3121 | kvm_async_pf_hash_reset(vcpu); | |
3122 | return 0; | |
3123 | } | |
3124 | ||
4e335d9e | 3125 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
68fd66f1 | 3126 | sizeof(u64))) |
344d9588 GN |
3127 | return 1; |
3128 | ||
6adba527 | 3129 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 3130 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
2635b5c4 | 3131 | |
344d9588 | 3132 | kvm_async_pf_wakeup_all(vcpu); |
2635b5c4 VK |
3133 | |
3134 | return 0; | |
3135 | } | |
3136 | ||
3137 | static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) | |
3138 | { | |
3139 | /* Bits 8-63 are reserved */ | |
3140 | if (data >> 8) | |
3141 | return 1; | |
3142 | ||
3143 | if (!lapic_in_kernel(vcpu)) | |
3144 | return 1; | |
3145 | ||
3146 | vcpu->arch.apf.msr_int_val = data; | |
3147 | ||
3148 | vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; | |
3149 | ||
344d9588 GN |
3150 | return 0; |
3151 | } | |
3152 | ||
12f9a48f GC |
3153 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
3154 | { | |
0b79459b | 3155 | vcpu->arch.pv_time_enabled = false; |
49dedf0d | 3156 | vcpu->arch.time = 0; |
12f9a48f GC |
3157 | } |
3158 | ||
7780938c | 3159 | static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) |
f38a7b75 WL |
3160 | { |
3161 | ++vcpu->stat.tlb_flush; | |
b3646477 | 3162 | static_call(kvm_x86_tlb_flush_all)(vcpu); |
f38a7b75 WL |
3163 | } |
3164 | ||
0baedd79 VK |
3165 | static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) |
3166 | { | |
3167 | ++vcpu->stat.tlb_flush; | |
b53e84ee LJ |
3168 | |
3169 | if (!tdp_enabled) { | |
3170 | /* | |
3171 | * A TLB flush on behalf of the guest is equivalent to | |
3172 | * INVPCID(all), toggling CR4.PGE, etc., which requires | |
3173 | * a forced sync of the shadow page tables. Unload the | |
3174 | * entire MMU here and the subsequent load will sync the | |
3175 | * shadow page tables, and also flush the TLB. | |
3176 | */ | |
3177 | kvm_mmu_unload(vcpu); | |
3178 | return; | |
3179 | } | |
3180 | ||
b3646477 | 3181 | static_call(kvm_x86_tlb_flush_guest)(vcpu); |
0baedd79 VK |
3182 | } |
3183 | ||
c9aaa895 GC |
3184 | static void record_steal_time(struct kvm_vcpu *vcpu) |
3185 | { | |
b0431382 BO |
3186 | struct kvm_host_map map; |
3187 | struct kvm_steal_time *st; | |
3188 | ||
30b5c851 DW |
3189 | if (kvm_xen_msr_enabled(vcpu->kvm)) { |
3190 | kvm_xen_runstate_set_running(vcpu); | |
3191 | return; | |
3192 | } | |
3193 | ||
c9aaa895 GC |
3194 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
3195 | return; | |
3196 | ||
b0431382 BO |
3197 | /* -EAGAIN is returned in atomic context so we can just return. */ |
3198 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, | |
3199 | &map, &vcpu->arch.st.cache, false)) | |
c9aaa895 GC |
3200 | return; |
3201 | ||
b0431382 BO |
3202 | st = map.hva + |
3203 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
3204 | ||
f38a7b75 WL |
3205 | /* |
3206 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
3207 | * expensive IPIs. | |
3208 | */ | |
66570e96 | 3209 | if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { |
af3511ff LJ |
3210 | u8 st_preempted = xchg(&st->preempted, 0); |
3211 | ||
66570e96 | 3212 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, |
af3511ff LJ |
3213 | st_preempted & KVM_VCPU_FLUSH_TLB); |
3214 | if (st_preempted & KVM_VCPU_FLUSH_TLB) | |
66570e96 | 3215 | kvm_vcpu_flush_tlb_guest(vcpu); |
1eff0ada WL |
3216 | } else { |
3217 | st->preempted = 0; | |
66570e96 | 3218 | } |
0b9f6c46 | 3219 | |
a6bd811f | 3220 | vcpu->arch.st.preempted = 0; |
35f3fae1 | 3221 | |
b0431382 BO |
3222 | if (st->version & 1) |
3223 | st->version += 1; /* first time write, random junk */ | |
35f3fae1 | 3224 | |
b0431382 | 3225 | st->version += 1; |
35f3fae1 WL |
3226 | |
3227 | smp_wmb(); | |
3228 | ||
b0431382 | 3229 | st->steal += current->sched_info.run_delay - |
c54cdf14 LC |
3230 | vcpu->arch.st.last_steal; |
3231 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
35f3fae1 | 3232 | |
35f3fae1 WL |
3233 | smp_wmb(); |
3234 | ||
b0431382 | 3235 | st->version += 1; |
c9aaa895 | 3236 | |
b0431382 | 3237 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); |
c9aaa895 GC |
3238 | } |
3239 | ||
8fe8ab46 | 3240 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3241 | { |
5753785f | 3242 | bool pr = false; |
8fe8ab46 WA |
3243 | u32 msr = msr_info->index; |
3244 | u64 data = msr_info->data; | |
5753785f | 3245 | |
1232f8e6 | 3246 | if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) |
23200b7a | 3247 | return kvm_xen_write_hypercall_page(vcpu, data); |
1232f8e6 | 3248 | |
15c4a640 | 3249 | switch (msr) { |
2e32b719 | 3250 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
3251 | case MSR_IA32_UCODE_WRITE: |
3252 | case MSR_VM_HSAVE_PA: | |
3253 | case MSR_AMD64_PATCH_LOADER: | |
3254 | case MSR_AMD64_BU_CFG2: | |
405a353a | 3255 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3256 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
3257 | break; |
3258 | ||
518e7b94 WL |
3259 | case MSR_IA32_UCODE_REV: |
3260 | if (msr_info->host_initiated) | |
3261 | vcpu->arch.microcode_version = data; | |
3262 | break; | |
0cf9135b SC |
3263 | case MSR_IA32_ARCH_CAPABILITIES: |
3264 | if (!msr_info->host_initiated) | |
3265 | return 1; | |
3266 | vcpu->arch.arch_capabilities = data; | |
3267 | break; | |
d574c539 VK |
3268 | case MSR_IA32_PERF_CAPABILITIES: { |
3269 | struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; | |
3270 | ||
3271 | if (!msr_info->host_initiated) | |
3272 | return 1; | |
3273 | if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) | |
3274 | return 1; | |
3275 | if (data & ~msr_ent.data) | |
3276 | return 1; | |
3277 | ||
3278 | vcpu->arch.perf_capabilities = data; | |
3279 | ||
3280 | return 0; | |
3281 | } | |
15c4a640 | 3282 | case MSR_EFER: |
11988499 | 3283 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
3284 | case MSR_K7_HWCR: |
3285 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 3286 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 3287 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
3288 | |
3289 | /* Handle McStatusWrEn */ | |
3290 | if (data == BIT_ULL(18)) { | |
3291 | vcpu->arch.msr_hwcr = data; | |
3292 | } else if (data != 0) { | |
a737f256 CD |
3293 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
3294 | data); | |
8f1589d9 AP |
3295 | return 1; |
3296 | } | |
15c4a640 | 3297 | break; |
f7c6d140 AP |
3298 | case MSR_FAM10H_MMIO_CONF_BASE: |
3299 | if (data != 0) { | |
a737f256 CD |
3300 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
3301 | "0x%llx\n", data); | |
f7c6d140 AP |
3302 | return 1; |
3303 | } | |
15c4a640 | 3304 | break; |
9ba075a6 | 3305 | case 0x200 ... 0x2ff: |
ff53604b | 3306 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 3307 | case MSR_IA32_APICBASE: |
58cb628d | 3308 | return kvm_set_apic_base(vcpu, msr_info); |
bf10bd0b | 3309 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
0105d1a5 | 3310 | return kvm_x2apic_msr_write(vcpu, msr, data); |
09141ec0 | 3311 | case MSR_IA32_TSC_DEADLINE: |
a3e06bbe LJ |
3312 | kvm_set_lapic_tscdeadline_msr(vcpu, data); |
3313 | break; | |
ba904635 | 3314 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 3315 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 3316 | if (!msr_info->host_initiated) { |
d913b904 | 3317 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 3318 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
3319 | } |
3320 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
3321 | } | |
3322 | break; | |
15c4a640 | 3323 | case MSR_IA32_MISC_ENABLE: |
511a8556 WL |
3324 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
3325 | ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { | |
3326 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) | |
3327 | return 1; | |
3328 | vcpu->arch.ia32_misc_enable_msr = data; | |
aedbaf4f | 3329 | kvm_update_cpuid_runtime(vcpu); |
511a8556 WL |
3330 | } else { |
3331 | vcpu->arch.ia32_misc_enable_msr = data; | |
3332 | } | |
15c4a640 | 3333 | break; |
64d60670 PB |
3334 | case MSR_IA32_SMBASE: |
3335 | if (!msr_info->host_initiated) | |
3336 | return 1; | |
3337 | vcpu->arch.smbase = data; | |
3338 | break; | |
73f624f4 PB |
3339 | case MSR_IA32_POWER_CTL: |
3340 | vcpu->arch.msr_ia32_power_ctl = data; | |
3341 | break; | |
dd259935 | 3342 | case MSR_IA32_TSC: |
0c899c25 PB |
3343 | if (msr_info->host_initiated) { |
3344 | kvm_synchronize_tsc(vcpu, data); | |
3345 | } else { | |
9b399dfd | 3346 | u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; |
0c899c25 PB |
3347 | adjust_tsc_offset_guest(vcpu, adj); |
3348 | vcpu->arch.ia32_tsc_adjust_msr += adj; | |
3349 | } | |
dd259935 | 3350 | break; |
864e2ab2 AL |
3351 | case MSR_IA32_XSS: |
3352 | if (!msr_info->host_initiated && | |
3353 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3354 | return 1; | |
3355 | /* | |
a1bead2a SC |
3356 | * KVM supports exposing PT to the guest, but does not support |
3357 | * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than | |
3358 | * XSAVES/XRSTORS to save/restore PT MSRs. | |
864e2ab2 | 3359 | */ |
408e9a31 | 3360 | if (data & ~supported_xss) |
864e2ab2 AL |
3361 | return 1; |
3362 | vcpu->arch.ia32_xss = data; | |
3363 | break; | |
52797bf9 LA |
3364 | case MSR_SMI_COUNT: |
3365 | if (!msr_info->host_initiated) | |
3366 | return 1; | |
3367 | vcpu->arch.smi_count = data; | |
3368 | break; | |
11c6bffa | 3369 | case MSR_KVM_WALL_CLOCK_NEW: |
66570e96 OU |
3370 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3371 | return 1; | |
3372 | ||
629b5348 JM |
3373 | vcpu->kvm->arch.wall_clock = data; |
3374 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
66570e96 | 3375 | break; |
18068523 | 3376 | case MSR_KVM_WALL_CLOCK: |
66570e96 OU |
3377 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3378 | return 1; | |
3379 | ||
629b5348 JM |
3380 | vcpu->kvm->arch.wall_clock = data; |
3381 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
18068523 | 3382 | break; |
11c6bffa | 3383 | case MSR_KVM_SYSTEM_TIME_NEW: |
66570e96 OU |
3384 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3385 | return 1; | |
3386 | ||
5b9bb0eb OU |
3387 | kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); |
3388 | break; | |
3389 | case MSR_KVM_SYSTEM_TIME: | |
66570e96 OU |
3390 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3391 | return 1; | |
3392 | ||
3393 | kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); | |
18068523 | 3394 | break; |
344d9588 | 3395 | case MSR_KVM_ASYNC_PF_EN: |
66570e96 OU |
3396 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3397 | return 1; | |
3398 | ||
344d9588 GN |
3399 | if (kvm_pv_enable_async_pf(vcpu, data)) |
3400 | return 1; | |
3401 | break; | |
2635b5c4 | 3402 | case MSR_KVM_ASYNC_PF_INT: |
66570e96 OU |
3403 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3404 | return 1; | |
3405 | ||
2635b5c4 VK |
3406 | if (kvm_pv_enable_async_pf_int(vcpu, data)) |
3407 | return 1; | |
3408 | break; | |
557a961a | 3409 | case MSR_KVM_ASYNC_PF_ACK: |
0a31df68 | 3410 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
66570e96 | 3411 | return 1; |
557a961a VK |
3412 | if (data & 0x1) { |
3413 | vcpu->arch.apf.pageready_pending = false; | |
3414 | kvm_check_async_pf_completion(vcpu); | |
3415 | } | |
3416 | break; | |
c9aaa895 | 3417 | case MSR_KVM_STEAL_TIME: |
66570e96 OU |
3418 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3419 | return 1; | |
c9aaa895 GC |
3420 | |
3421 | if (unlikely(!sched_info_on())) | |
3422 | return 1; | |
3423 | ||
3424 | if (data & KVM_STEAL_RESERVED_MASK) | |
3425 | return 1; | |
3426 | ||
c9aaa895 GC |
3427 | vcpu->arch.st.msr_val = data; |
3428 | ||
3429 | if (!(data & KVM_MSR_ENABLED)) | |
3430 | break; | |
3431 | ||
c9aaa895 GC |
3432 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
3433 | ||
3434 | break; | |
ae7a2a3f | 3435 | case MSR_KVM_PV_EOI_EN: |
66570e96 OU |
3436 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3437 | return 1; | |
3438 | ||
72bbf935 | 3439 | if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
3440 | return 1; |
3441 | break; | |
c9aaa895 | 3442 | |
2d5ba19b | 3443 | case MSR_KVM_POLL_CONTROL: |
66570e96 OU |
3444 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3445 | return 1; | |
3446 | ||
2d5ba19b MT |
3447 | /* only enable bit supported */ |
3448 | if (data & (-1ULL << 1)) | |
3449 | return 1; | |
3450 | ||
3451 | vcpu->arch.msr_kvm_poll_control = data; | |
3452 | break; | |
3453 | ||
890ca9ae HY |
3454 | case MSR_IA32_MCG_CTL: |
3455 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3456 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 3457 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 3458 | |
6912ac32 WH |
3459 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
3460 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
df561f66 GS |
3461 | pr = true; |
3462 | fallthrough; | |
6912ac32 WH |
3463 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3464 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3465 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3466 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
3467 | |
3468 | if (pr || data != 0) | |
a737f256 CD |
3469 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
3470 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 3471 | break; |
84e0cefa JS |
3472 | case MSR_K7_CLK_CTL: |
3473 | /* | |
3474 | * Ignore all writes to this no longer documented MSR. | |
3475 | * Writes are only relevant for old K7 processors, | |
3476 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 3477 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
3478 | * affected processor models on the command line, hence |
3479 | * the need to ignore the workaround. | |
3480 | */ | |
3481 | break; | |
55cd8e5a | 3482 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3483 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3484 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3485 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3486 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3487 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3488 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3489 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3490 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
3491 | return kvm_hv_set_msr_common(vcpu, msr, data, |
3492 | msr_info->host_initiated); | |
91c9c3ed | 3493 | case MSR_IA32_BBL_CR_CTL3: |
3494 | /* Drop writes to this legacy MSR -- see rdmsr | |
3495 | * counterpart for further detail. | |
3496 | */ | |
fab0aa3b EM |
3497 | if (report_ignored_msrs) |
3498 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
3499 | msr, data); | |
91c9c3ed | 3500 | break; |
2b036c6b | 3501 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3502 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3503 | return 1; |
3504 | vcpu->arch.osvw.length = data; | |
3505 | break; | |
3506 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3507 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3508 | return 1; |
3509 | vcpu->arch.osvw.status = data; | |
3510 | break; | |
db2336a8 KH |
3511 | case MSR_PLATFORM_INFO: |
3512 | if (!msr_info->host_initiated || | |
db2336a8 KH |
3513 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
3514 | cpuid_fault_enabled(vcpu))) | |
3515 | return 1; | |
3516 | vcpu->arch.msr_platform_info = data; | |
3517 | break; | |
3518 | case MSR_MISC_FEATURES_ENABLES: | |
3519 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
3520 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
3521 | !supports_cpuid_fault(vcpu))) | |
3522 | return 1; | |
3523 | vcpu->arch.msr_misc_features_enables = data; | |
3524 | break; | |
15c4a640 | 3525 | default: |
c6702c9d | 3526 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3527 | return kvm_pmu_set_msr(vcpu, msr_info); |
6abe9c13 | 3528 | return KVM_MSR_RET_INVALID; |
15c4a640 CO |
3529 | } |
3530 | return 0; | |
3531 | } | |
3532 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
3533 | ||
44883f01 | 3534 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
3535 | { |
3536 | u64 data; | |
890ca9ae HY |
3537 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3538 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
3539 | |
3540 | switch (msr) { | |
15c4a640 CO |
3541 | case MSR_IA32_P5_MC_ADDR: |
3542 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
3543 | data = 0; |
3544 | break; | |
15c4a640 | 3545 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
3546 | data = vcpu->arch.mcg_cap; |
3547 | break; | |
c7ac679c | 3548 | case MSR_IA32_MCG_CTL: |
44883f01 | 3549 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
3550 | return 1; |
3551 | data = vcpu->arch.mcg_ctl; | |
3552 | break; | |
3553 | case MSR_IA32_MCG_STATUS: | |
3554 | data = vcpu->arch.mcg_status; | |
3555 | break; | |
3556 | default: | |
3557 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3558 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3559 | u32 offset = array_index_nospec( |
3560 | msr - MSR_IA32_MC0_CTL, | |
3561 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3562 | ||
890ca9ae HY |
3563 | data = vcpu->arch.mce_banks[offset]; |
3564 | break; | |
3565 | } | |
3566 | return 1; | |
3567 | } | |
3568 | *pdata = data; | |
3569 | return 0; | |
3570 | } | |
3571 | ||
609e36d3 | 3572 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 3573 | { |
609e36d3 | 3574 | switch (msr_info->index) { |
890ca9ae | 3575 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 3576 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
3577 | case MSR_IA32_LASTBRANCHFROMIP: |
3578 | case MSR_IA32_LASTBRANCHTOIP: | |
3579 | case MSR_IA32_LASTINTFROMIP: | |
3580 | case MSR_IA32_LASTINTTOIP: | |
059e5c32 | 3581 | case MSR_AMD64_SYSCFG: |
3afb1121 PB |
3582 | case MSR_K8_TSEG_ADDR: |
3583 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 3584 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 3585 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 3586 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 3587 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 3588 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 3589 | case MSR_IA32_PERF_CTL: |
405a353a | 3590 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3591 | case MSR_F15H_EX_CFG: |
2ca1a06a VS |
3592 | /* |
3593 | * Intel Sandy Bridge CPUs must support the RAPL (running average power | |
3594 | * limit) MSRs. Just return 0, as we do not want to expose the host | |
3595 | * data here. Do not conditionalize this on CPUID, as KVM does not do | |
3596 | * so for existing CPU-specific MSRs. | |
3597 | */ | |
3598 | case MSR_RAPL_POWER_UNIT: | |
3599 | case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ | |
3600 | case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ | |
3601 | case MSR_PKG_ENERGY_STATUS: /* Total package */ | |
3602 | case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ | |
609e36d3 | 3603 | msr_info->data = 0; |
15c4a640 | 3604 | break; |
c51eb52b | 3605 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
c28fa560 VK |
3606 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
3607 | return kvm_pmu_get_msr(vcpu, msr_info); | |
3608 | if (!msr_info->host_initiated) | |
3609 | return 1; | |
3610 | msr_info->data = 0; | |
3611 | break; | |
6912ac32 WH |
3612 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3613 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
3614 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
3615 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3616 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3617 | return kvm_pmu_get_msr(vcpu, msr_info); |
609e36d3 | 3618 | msr_info->data = 0; |
5753785f | 3619 | break; |
742bc670 | 3620 | case MSR_IA32_UCODE_REV: |
518e7b94 | 3621 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 3622 | break; |
0cf9135b SC |
3623 | case MSR_IA32_ARCH_CAPABILITIES: |
3624 | if (!msr_info->host_initiated && | |
3625 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3626 | return 1; | |
3627 | msr_info->data = vcpu->arch.arch_capabilities; | |
3628 | break; | |
d574c539 VK |
3629 | case MSR_IA32_PERF_CAPABILITIES: |
3630 | if (!msr_info->host_initiated && | |
3631 | !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) | |
3632 | return 1; | |
3633 | msr_info->data = vcpu->arch.perf_capabilities; | |
3634 | break; | |
73f624f4 PB |
3635 | case MSR_IA32_POWER_CTL: |
3636 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
3637 | break; | |
cc5b54dd ML |
3638 | case MSR_IA32_TSC: { |
3639 | /* | |
3640 | * Intel SDM states that MSR_IA32_TSC read adds the TSC offset | |
3641 | * even when not intercepted. AMD manual doesn't explicitly | |
3642 | * state this but appears to behave the same. | |
3643 | * | |
ee6fa053 | 3644 | * On userspace reads and writes, however, we unconditionally |
c0623f5e | 3645 | * return L1's TSC value to ensure backwards-compatible |
ee6fa053 | 3646 | * behavior for migration. |
cc5b54dd | 3647 | */ |
fe3eb504 | 3648 | u64 offset, ratio; |
cc5b54dd | 3649 | |
fe3eb504 IS |
3650 | if (msr_info->host_initiated) { |
3651 | offset = vcpu->arch.l1_tsc_offset; | |
3652 | ratio = vcpu->arch.l1_tsc_scaling_ratio; | |
3653 | } else { | |
3654 | offset = vcpu->arch.tsc_offset; | |
3655 | ratio = vcpu->arch.tsc_scaling_ratio; | |
3656 | } | |
3657 | ||
3658 | msr_info->data = kvm_scale_tsc(vcpu, rdtsc(), ratio) + offset; | |
dd259935 | 3659 | break; |
cc5b54dd | 3660 | } |
9ba075a6 | 3661 | case MSR_MTRRcap: |
9ba075a6 | 3662 | case 0x200 ... 0x2ff: |
ff53604b | 3663 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 3664 | case 0xcd: /* fsb frequency */ |
609e36d3 | 3665 | msr_info->data = 3; |
15c4a640 | 3666 | break; |
7b914098 JS |
3667 | /* |
3668 | * MSR_EBC_FREQUENCY_ID | |
3669 | * Conservative value valid for even the basic CPU models. | |
3670 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
3671 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
3672 | * and 266MHz for model 3, or 4. Set Core Clock | |
3673 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
3674 | * 31:24) even though these are only valid for CPU | |
3675 | * models > 2, however guests may end up dividing or | |
3676 | * multiplying by zero otherwise. | |
3677 | */ | |
3678 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 3679 | msr_info->data = 1 << 24; |
7b914098 | 3680 | break; |
15c4a640 | 3681 | case MSR_IA32_APICBASE: |
609e36d3 | 3682 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 3683 | break; |
bf10bd0b | 3684 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
609e36d3 | 3685 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
09141ec0 | 3686 | case MSR_IA32_TSC_DEADLINE: |
609e36d3 | 3687 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 3688 | break; |
ba904635 | 3689 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 3690 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 3691 | break; |
15c4a640 | 3692 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 3693 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 3694 | break; |
64d60670 PB |
3695 | case MSR_IA32_SMBASE: |
3696 | if (!msr_info->host_initiated) | |
3697 | return 1; | |
3698 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 3699 | break; |
52797bf9 LA |
3700 | case MSR_SMI_COUNT: |
3701 | msr_info->data = vcpu->arch.smi_count; | |
3702 | break; | |
847f0ad8 AG |
3703 | case MSR_IA32_PERF_STATUS: |
3704 | /* TSC increment by tick */ | |
609e36d3 | 3705 | msr_info->data = 1000ULL; |
847f0ad8 | 3706 | /* CPU multiplier */ |
b0996ae4 | 3707 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 3708 | break; |
15c4a640 | 3709 | case MSR_EFER: |
609e36d3 | 3710 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 3711 | break; |
18068523 | 3712 | case MSR_KVM_WALL_CLOCK: |
1930e5dd OU |
3713 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3714 | return 1; | |
3715 | ||
3716 | msr_info->data = vcpu->kvm->arch.wall_clock; | |
3717 | break; | |
11c6bffa | 3718 | case MSR_KVM_WALL_CLOCK_NEW: |
1930e5dd OU |
3719 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3720 | return 1; | |
3721 | ||
609e36d3 | 3722 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
3723 | break; |
3724 | case MSR_KVM_SYSTEM_TIME: | |
1930e5dd OU |
3725 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3726 | return 1; | |
3727 | ||
3728 | msr_info->data = vcpu->arch.time; | |
3729 | break; | |
11c6bffa | 3730 | case MSR_KVM_SYSTEM_TIME_NEW: |
1930e5dd OU |
3731 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3732 | return 1; | |
3733 | ||
609e36d3 | 3734 | msr_info->data = vcpu->arch.time; |
18068523 | 3735 | break; |
344d9588 | 3736 | case MSR_KVM_ASYNC_PF_EN: |
1930e5dd OU |
3737 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3738 | return 1; | |
3739 | ||
2635b5c4 VK |
3740 | msr_info->data = vcpu->arch.apf.msr_en_val; |
3741 | break; | |
3742 | case MSR_KVM_ASYNC_PF_INT: | |
1930e5dd OU |
3743 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3744 | return 1; | |
3745 | ||
2635b5c4 | 3746 | msr_info->data = vcpu->arch.apf.msr_int_val; |
344d9588 | 3747 | break; |
557a961a | 3748 | case MSR_KVM_ASYNC_PF_ACK: |
0a31df68 | 3749 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
1930e5dd OU |
3750 | return 1; |
3751 | ||
557a961a VK |
3752 | msr_info->data = 0; |
3753 | break; | |
c9aaa895 | 3754 | case MSR_KVM_STEAL_TIME: |
1930e5dd OU |
3755 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3756 | return 1; | |
3757 | ||
609e36d3 | 3758 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 3759 | break; |
1d92128f | 3760 | case MSR_KVM_PV_EOI_EN: |
1930e5dd OU |
3761 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3762 | return 1; | |
3763 | ||
609e36d3 | 3764 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 3765 | break; |
2d5ba19b | 3766 | case MSR_KVM_POLL_CONTROL: |
1930e5dd OU |
3767 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3768 | return 1; | |
3769 | ||
2d5ba19b MT |
3770 | msr_info->data = vcpu->arch.msr_kvm_poll_control; |
3771 | break; | |
890ca9ae HY |
3772 | case MSR_IA32_P5_MC_ADDR: |
3773 | case MSR_IA32_P5_MC_TYPE: | |
3774 | case MSR_IA32_MCG_CAP: | |
3775 | case MSR_IA32_MCG_CTL: | |
3776 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3777 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
3778 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
3779 | msr_info->host_initiated); | |
864e2ab2 AL |
3780 | case MSR_IA32_XSS: |
3781 | if (!msr_info->host_initiated && | |
3782 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3783 | return 1; | |
3784 | msr_info->data = vcpu->arch.ia32_xss; | |
3785 | break; | |
84e0cefa JS |
3786 | case MSR_K7_CLK_CTL: |
3787 | /* | |
3788 | * Provide expected ramp-up count for K7. All other | |
3789 | * are set to zero, indicating minimum divisors for | |
3790 | * every field. | |
3791 | * | |
3792 | * This prevents guest kernels on AMD host with CPU | |
3793 | * type 6, model 8 and higher from exploding due to | |
3794 | * the rdmsr failing. | |
3795 | */ | |
609e36d3 | 3796 | msr_info->data = 0x20000000; |
84e0cefa | 3797 | break; |
55cd8e5a | 3798 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3799 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3800 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3801 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3802 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3803 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3804 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3805 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3806 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 3807 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
3808 | msr_info->index, &msr_info->data, |
3809 | msr_info->host_initiated); | |
91c9c3ed | 3810 | case MSR_IA32_BBL_CR_CTL3: |
3811 | /* This legacy MSR exists but isn't fully documented in current | |
3812 | * silicon. It is however accessed by winxp in very narrow | |
3813 | * scenarios where it sets bit #19, itself documented as | |
3814 | * a "reserved" bit. Best effort attempt to source coherent | |
3815 | * read data here should the balance of the register be | |
3816 | * interpreted by the guest: | |
3817 | * | |
3818 | * L2 cache control register 3: 64GB range, 256KB size, | |
3819 | * enabled, latency 0x1, configured | |
3820 | */ | |
609e36d3 | 3821 | msr_info->data = 0xbe702111; |
91c9c3ed | 3822 | break; |
2b036c6b | 3823 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3824 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3825 | return 1; |
609e36d3 | 3826 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
3827 | break; |
3828 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3829 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3830 | return 1; |
609e36d3 | 3831 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 3832 | break; |
db2336a8 | 3833 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
3834 | if (!msr_info->host_initiated && |
3835 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
3836 | return 1; | |
db2336a8 KH |
3837 | msr_info->data = vcpu->arch.msr_platform_info; |
3838 | break; | |
3839 | case MSR_MISC_FEATURES_ENABLES: | |
3840 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
3841 | break; | |
191c8137 BP |
3842 | case MSR_K7_HWCR: |
3843 | msr_info->data = vcpu->arch.msr_hwcr; | |
3844 | break; | |
15c4a640 | 3845 | default: |
c6702c9d | 3846 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3847 | return kvm_pmu_get_msr(vcpu, msr_info); |
6abe9c13 | 3848 | return KVM_MSR_RET_INVALID; |
15c4a640 | 3849 | } |
15c4a640 CO |
3850 | return 0; |
3851 | } | |
3852 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
3853 | ||
313a3dc7 CO |
3854 | /* |
3855 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
3856 | * | |
3857 | * @return number of msrs set successfully. | |
3858 | */ | |
3859 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
3860 | struct kvm_msr_entry *entries, | |
3861 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3862 | unsigned index, u64 *data)) | |
3863 | { | |
801e459a | 3864 | int i; |
313a3dc7 | 3865 | |
313a3dc7 CO |
3866 | for (i = 0; i < msrs->nmsrs; ++i) |
3867 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
3868 | break; | |
3869 | ||
313a3dc7 CO |
3870 | return i; |
3871 | } | |
3872 | ||
3873 | /* | |
3874 | * Read or write a bunch of msrs. Parameters are user addresses. | |
3875 | * | |
3876 | * @return number of msrs set successfully. | |
3877 | */ | |
3878 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
3879 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3880 | unsigned index, u64 *data), | |
3881 | int writeback) | |
3882 | { | |
3883 | struct kvm_msrs msrs; | |
3884 | struct kvm_msr_entry *entries; | |
3885 | int r, n; | |
3886 | unsigned size; | |
3887 | ||
3888 | r = -EFAULT; | |
0e96f31e | 3889 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
3890 | goto out; |
3891 | ||
3892 | r = -E2BIG; | |
3893 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
3894 | goto out; | |
3895 | ||
313a3dc7 | 3896 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
3897 | entries = memdup_user(user_msrs->entries, size); |
3898 | if (IS_ERR(entries)) { | |
3899 | r = PTR_ERR(entries); | |
313a3dc7 | 3900 | goto out; |
ff5c2c03 | 3901 | } |
313a3dc7 CO |
3902 | |
3903 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
3904 | if (r < 0) | |
3905 | goto out_free; | |
3906 | ||
3907 | r = -EFAULT; | |
3908 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
3909 | goto out_free; | |
3910 | ||
3911 | r = n; | |
3912 | ||
3913 | out_free: | |
7a73c028 | 3914 | kfree(entries); |
313a3dc7 CO |
3915 | out: |
3916 | return r; | |
3917 | } | |
3918 | ||
4d5422ce WL |
3919 | static inline bool kvm_can_mwait_in_guest(void) |
3920 | { | |
3921 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
3922 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
3923 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
3924 | } |
3925 | ||
c21d54f0 VK |
3926 | static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, |
3927 | struct kvm_cpuid2 __user *cpuid_arg) | |
3928 | { | |
3929 | struct kvm_cpuid2 cpuid; | |
3930 | int r; | |
3931 | ||
3932 | r = -EFAULT; | |
3933 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
3934 | return r; | |
3935 | ||
3936 | r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
3937 | if (r) | |
3938 | return r; | |
3939 | ||
3940 | r = -EFAULT; | |
3941 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
3942 | return r; | |
3943 | ||
3944 | return 0; | |
3945 | } | |
3946 | ||
784aa3d7 | 3947 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 3948 | { |
4d5422ce | 3949 | int r = 0; |
018d00d2 ZX |
3950 | |
3951 | switch (ext) { | |
3952 | case KVM_CAP_IRQCHIP: | |
3953 | case KVM_CAP_HLT: | |
3954 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 3955 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 3956 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 3957 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 3958 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 3959 | case KVM_CAP_PIT: |
a28e4f5a | 3960 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 3961 | case KVM_CAP_MP_STATE: |
ed848624 | 3962 | case KVM_CAP_SYNC_MMU: |
a355c85c | 3963 | case KVM_CAP_USER_NMI: |
52d939a0 | 3964 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 3965 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 3966 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 3967 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 3968 | case KVM_CAP_PIT2: |
e9f42757 | 3969 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 3970 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
3cfc3092 | 3971 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 3972 | case KVM_CAP_HYPERV: |
10388a07 | 3973 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 3974 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 3975 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 3976 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 3977 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 3978 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 3979 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 3980 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 3981 | case KVM_CAP_HYPERV_CPUID: |
644f7067 | 3982 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
c21d54f0 | 3983 | case KVM_CAP_SYS_HYPERV_CPUID: |
ab9f4ecb | 3984 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 3985 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 3986 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 3987 | case KVM_CAP_XSAVE: |
344d9588 | 3988 | case KVM_CAP_ASYNC_PF: |
72de5fa4 | 3989 | case KVM_CAP_ASYNC_PF_INT: |
92a1f12d | 3990 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 3991 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 3992 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 3993 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 3994 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 3995 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 3996 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 3997 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 3998 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 3999 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 4000 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 4001 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 4002 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 4003 | case KVM_CAP_EXCEPTION_PAYLOAD: |
b9b2782c | 4004 | case KVM_CAP_SET_GUEST_DEBUG: |
1aa561b1 | 4005 | case KVM_CAP_LAST_CPU: |
1ae09954 | 4006 | case KVM_CAP_X86_USER_SPACE_MSR: |
1a155254 | 4007 | case KVM_CAP_X86_MSR_FILTER: |
66570e96 | 4008 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
fe7e9488 SC |
4009 | #ifdef CONFIG_X86_SGX_KVM |
4010 | case KVM_CAP_SGX_ATTRIBUTE: | |
4011 | #endif | |
54526d1f | 4012 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
6dba9403 | 4013 | case KVM_CAP_SREGS2: |
19238e75 | 4014 | case KVM_CAP_EXIT_ON_EMULATION_FAILURE: |
018d00d2 ZX |
4015 | r = 1; |
4016 | break; | |
0dbb1123 AK |
4017 | case KVM_CAP_EXIT_HYPERCALL: |
4018 | r = KVM_EXIT_HYPERCALL_VALID_MASK; | |
4019 | break; | |
7e582ccb ML |
4020 | case KVM_CAP_SET_GUEST_DEBUG2: |
4021 | return KVM_GUESTDBG_VALID_MASK; | |
b59b153d | 4022 | #ifdef CONFIG_KVM_XEN |
23200b7a JM |
4023 | case KVM_CAP_XEN_HVM: |
4024 | r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | | |
8d4e7e80 DW |
4025 | KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | |
4026 | KVM_XEN_HVM_CONFIG_SHARED_INFO; | |
30b5c851 DW |
4027 | if (sched_info_on()) |
4028 | r |= KVM_XEN_HVM_CONFIG_RUNSTATE; | |
23200b7a | 4029 | break; |
b59b153d | 4030 | #endif |
01643c51 KH |
4031 | case KVM_CAP_SYNC_REGS: |
4032 | r = KVM_SYNC_X86_VALID_FIELDS; | |
4033 | break; | |
e3fd9a93 PB |
4034 | case KVM_CAP_ADJUST_CLOCK: |
4035 | r = KVM_CLOCK_TSC_STABLE; | |
4036 | break; | |
4d5422ce | 4037 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
4038 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
4039 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
4040 | if(kvm_can_mwait_in_guest()) |
4041 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 4042 | break; |
6d396b55 PB |
4043 | case KVM_CAP_X86_SMM: |
4044 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
4045 | * and SMM handlers might indeed rely on 4G segment limits, | |
4046 | * so do not report SMM to be available if real mode is | |
4047 | * emulated via vm86 mode. Still, do not go to great lengths | |
4048 | * to avoid userspace's usage of the feature, because it is a | |
4049 | * fringe case that is not enabled except via specific settings | |
4050 | * of the module parameters. | |
4051 | */ | |
b3646477 | 4052 | r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); |
6d396b55 | 4053 | break; |
774ead3a | 4054 | case KVM_CAP_VAPIC: |
b3646477 | 4055 | r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); |
774ead3a | 4056 | break; |
f725230a | 4057 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
4058 | r = KVM_SOFT_MAX_VCPUS; |
4059 | break; | |
4060 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
4061 | r = KVM_MAX_VCPUS; |
4062 | break; | |
a86cb413 TH |
4063 | case KVM_CAP_MAX_VCPU_ID: |
4064 | r = KVM_MAX_VCPU_ID; | |
4065 | break; | |
a68a6a72 MT |
4066 | case KVM_CAP_PV_MMU: /* obsolete */ |
4067 | r = 0; | |
2f333bcb | 4068 | break; |
890ca9ae HY |
4069 | case KVM_CAP_MCE: |
4070 | r = KVM_MAX_MCE_BANKS; | |
4071 | break; | |
2d5b5a66 | 4072 | case KVM_CAP_XCRS: |
d366bf7e | 4073 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 4074 | break; |
92a1f12d JR |
4075 | case KVM_CAP_TSC_CONTROL: |
4076 | r = kvm_has_tsc_control; | |
4077 | break; | |
37131313 RK |
4078 | case KVM_CAP_X2APIC_API: |
4079 | r = KVM_X2APIC_API_VALID_FLAGS; | |
4080 | break; | |
8fcc4b59 | 4081 | case KVM_CAP_NESTED_STATE: |
33b22172 PB |
4082 | r = kvm_x86_ops.nested_ops->get_state ? |
4083 | kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; | |
8fcc4b59 | 4084 | break; |
344c6c80 | 4085 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4086 | r = kvm_x86_ops.enable_direct_tlbflush != NULL; |
5a0165f6 VK |
4087 | break; |
4088 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
33b22172 | 4089 | r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; |
344c6c80 | 4090 | break; |
3edd6839 MG |
4091 | case KVM_CAP_SMALLER_MAXPHYADDR: |
4092 | r = (int) allow_smaller_maxphyaddr; | |
4093 | break; | |
004a0124 AJ |
4094 | case KVM_CAP_STEAL_TIME: |
4095 | r = sched_info_on(); | |
4096 | break; | |
fe6b6bc8 CQ |
4097 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
4098 | if (kvm_has_bus_lock_exit) | |
4099 | r = KVM_BUS_LOCK_DETECTION_OFF | | |
4100 | KVM_BUS_LOCK_DETECTION_EXIT; | |
4101 | else | |
4102 | r = 0; | |
4103 | break; | |
018d00d2 | 4104 | default: |
018d00d2 ZX |
4105 | break; |
4106 | } | |
4107 | return r; | |
4108 | ||
4109 | } | |
4110 | ||
043405e1 CO |
4111 | long kvm_arch_dev_ioctl(struct file *filp, |
4112 | unsigned int ioctl, unsigned long arg) | |
4113 | { | |
4114 | void __user *argp = (void __user *)arg; | |
4115 | long r; | |
4116 | ||
4117 | switch (ioctl) { | |
4118 | case KVM_GET_MSR_INDEX_LIST: { | |
4119 | struct kvm_msr_list __user *user_msr_list = argp; | |
4120 | struct kvm_msr_list msr_list; | |
4121 | unsigned n; | |
4122 | ||
4123 | r = -EFAULT; | |
0e96f31e | 4124 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
4125 | goto out; |
4126 | n = msr_list.nmsrs; | |
62ef68bb | 4127 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 4128 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
4129 | goto out; |
4130 | r = -E2BIG; | |
e125e7b6 | 4131 | if (n < msr_list.nmsrs) |
043405e1 CO |
4132 | goto out; |
4133 | r = -EFAULT; | |
4134 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
4135 | num_msrs_to_save * sizeof(u32))) | |
4136 | goto out; | |
e125e7b6 | 4137 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 4138 | &emulated_msrs, |
62ef68bb | 4139 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
4140 | goto out; |
4141 | r = 0; | |
4142 | break; | |
4143 | } | |
9c15bb1d BP |
4144 | case KVM_GET_SUPPORTED_CPUID: |
4145 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
4146 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
4147 | struct kvm_cpuid2 cpuid; | |
4148 | ||
4149 | r = -EFAULT; | |
0e96f31e | 4150 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 4151 | goto out; |
9c15bb1d BP |
4152 | |
4153 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
4154 | ioctl); | |
674eea0f AK |
4155 | if (r) |
4156 | goto out; | |
4157 | ||
4158 | r = -EFAULT; | |
0e96f31e | 4159 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
4160 | goto out; |
4161 | r = 0; | |
4162 | break; | |
4163 | } | |
cf6c26ec | 4164 | case KVM_X86_GET_MCE_CAP_SUPPORTED: |
890ca9ae | 4165 | r = -EFAULT; |
c45dcc71 AR |
4166 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
4167 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
4168 | goto out; |
4169 | r = 0; | |
4170 | break; | |
801e459a TL |
4171 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
4172 | struct kvm_msr_list __user *user_msr_list = argp; | |
4173 | struct kvm_msr_list msr_list; | |
4174 | unsigned int n; | |
4175 | ||
4176 | r = -EFAULT; | |
4177 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
4178 | goto out; | |
4179 | n = msr_list.nmsrs; | |
4180 | msr_list.nmsrs = num_msr_based_features; | |
4181 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
4182 | goto out; | |
4183 | r = -E2BIG; | |
4184 | if (n < msr_list.nmsrs) | |
4185 | goto out; | |
4186 | r = -EFAULT; | |
4187 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
4188 | num_msr_based_features * sizeof(u32))) | |
4189 | goto out; | |
4190 | r = 0; | |
4191 | break; | |
4192 | } | |
4193 | case KVM_GET_MSRS: | |
4194 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
4195 | break; | |
c21d54f0 VK |
4196 | case KVM_GET_SUPPORTED_HV_CPUID: |
4197 | r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); | |
4198 | break; | |
043405e1 CO |
4199 | default: |
4200 | r = -EINVAL; | |
cf6c26ec | 4201 | break; |
043405e1 CO |
4202 | } |
4203 | out: | |
4204 | return r; | |
4205 | } | |
4206 | ||
f5f48ee1 SY |
4207 | static void wbinvd_ipi(void *garbage) |
4208 | { | |
4209 | wbinvd(); | |
4210 | } | |
4211 | ||
4212 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4213 | { | |
e0f0bbc5 | 4214 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
4215 | } |
4216 | ||
313a3dc7 CO |
4217 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
4218 | { | |
f5f48ee1 SY |
4219 | /* Address WBINVD may be executed by guest */ |
4220 | if (need_emulate_wbinvd(vcpu)) { | |
b3646477 | 4221 | if (static_call(kvm_x86_has_wbinvd_exit)()) |
f5f48ee1 SY |
4222 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); |
4223 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
4224 | smp_call_function_single(vcpu->cpu, | |
4225 | wbinvd_ipi, NULL, 1); | |
4226 | } | |
4227 | ||
b3646477 | 4228 | static_call(kvm_x86_vcpu_load)(vcpu, cpu); |
8f6055cb | 4229 | |
37486135 BM |
4230 | /* Save host pkru register if supported */ |
4231 | vcpu->arch.host_pkru = read_pkru(); | |
4232 | ||
0dd6a6ed ZA |
4233 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
4234 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
4235 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
4236 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 4237 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 4238 | } |
8f6055cb | 4239 | |
b0c39dc6 | 4240 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 4241 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 4242 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
4243 | if (tsc_delta < 0) |
4244 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 4245 | |
b0c39dc6 | 4246 | if (kvm_check_tsc_unstable()) { |
9b399dfd | 4247 | u64 offset = kvm_compute_l1_tsc_offset(vcpu, |
b183aa58 | 4248 | vcpu->arch.last_guest_tsc); |
a545ab6a | 4249 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 4250 | vcpu->arch.tsc_catchup = 1; |
c285545f | 4251 | } |
a749e247 PB |
4252 | |
4253 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
4254 | kvm_lapic_restart_hv_timer(vcpu); | |
4255 | ||
d98d07ca MT |
4256 | /* |
4257 | * On a host with synchronized TSC, there is no need to update | |
4258 | * kvmclock on vcpu->cpu migration | |
4259 | */ | |
4260 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 4261 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 4262 | if (vcpu->cpu != cpu) |
1bd2009e | 4263 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 4264 | vcpu->cpu = cpu; |
6b7d7e76 | 4265 | } |
c9aaa895 | 4266 | |
c9aaa895 | 4267 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
4268 | } |
4269 | ||
0b9f6c46 PX |
4270 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
4271 | { | |
b0431382 BO |
4272 | struct kvm_host_map map; |
4273 | struct kvm_steal_time *st; | |
4274 | ||
0b9f6c46 PX |
4275 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
4276 | return; | |
4277 | ||
a6bd811f | 4278 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
4279 | return; |
4280 | ||
b0431382 BO |
4281 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, |
4282 | &vcpu->arch.st.cache, true)) | |
9c1a0744 | 4283 | return; |
b0431382 BO |
4284 | |
4285 | st = map.hva + | |
4286 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
0b9f6c46 | 4287 | |
a6bd811f | 4288 | st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; |
0b9f6c46 | 4289 | |
b0431382 | 4290 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); |
0b9f6c46 PX |
4291 | } |
4292 | ||
313a3dc7 CO |
4293 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
4294 | { | |
9c1a0744 WL |
4295 | int idx; |
4296 | ||
f1c6366e | 4297 | if (vcpu->preempted && !vcpu->arch.guest_state_protected) |
b3646477 | 4298 | vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); |
de63ad4c | 4299 | |
9c1a0744 WL |
4300 | /* |
4301 | * Take the srcu lock as memslots will be accessed to check the gfn | |
4302 | * cache generation against the memslots generation. | |
4303 | */ | |
4304 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
30b5c851 DW |
4305 | if (kvm_xen_msr_enabled(vcpu->kvm)) |
4306 | kvm_xen_runstate_set_preempted(vcpu); | |
4307 | else | |
4308 | kvm_steal_time_set_preempted(vcpu); | |
9c1a0744 | 4309 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
30b5c851 | 4310 | |
b3646477 | 4311 | static_call(kvm_x86_vcpu_put)(vcpu); |
4ea1636b | 4312 | vcpu->arch.last_host_tsc = rdtsc(); |
313a3dc7 CO |
4313 | } |
4314 | ||
313a3dc7 CO |
4315 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
4316 | struct kvm_lapic_state *s) | |
4317 | { | |
fa59cc00 | 4318 | if (vcpu->arch.apicv_active) |
b3646477 | 4319 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
d62caabb | 4320 | |
a92e2543 | 4321 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
4322 | } |
4323 | ||
4324 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
4325 | struct kvm_lapic_state *s) | |
4326 | { | |
a92e2543 RK |
4327 | int r; |
4328 | ||
4329 | r = kvm_apic_set_state(vcpu, s); | |
4330 | if (r) | |
4331 | return r; | |
cb142eb7 | 4332 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
4333 | |
4334 | return 0; | |
4335 | } | |
4336 | ||
127a457a MG |
4337 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
4338 | { | |
71cc849b PB |
4339 | /* |
4340 | * We can accept userspace's request for interrupt injection | |
4341 | * as long as we have a place to store the interrupt number. | |
4342 | * The actual injection will happen when the CPU is able to | |
4343 | * deliver the interrupt. | |
4344 | */ | |
4345 | if (kvm_cpu_has_extint(vcpu)) | |
4346 | return false; | |
4347 | ||
4348 | /* Acknowledging ExtINT does not happen if LINT0 is masked. */ | |
127a457a MG |
4349 | return (!lapic_in_kernel(vcpu) || |
4350 | kvm_apic_accept_pic_intr(vcpu)); | |
4351 | } | |
4352 | ||
782d422b MG |
4353 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) |
4354 | { | |
fa7a549d PB |
4355 | /* |
4356 | * Do not cause an interrupt window exit if an exception | |
4357 | * is pending or an event needs reinjection; userspace | |
4358 | * might want to inject the interrupt manually using KVM_SET_REGS | |
4359 | * or KVM_SET_SREGS. For that to work, we must be at an | |
4360 | * instruction boundary and with no events half-injected. | |
4361 | */ | |
4362 | return (kvm_arch_interrupt_allowed(vcpu) && | |
4363 | kvm_cpu_accept_dm_intr(vcpu) && | |
4364 | !kvm_event_needs_reinjection(vcpu) && | |
4365 | !vcpu->arch.exception.pending); | |
782d422b MG |
4366 | } |
4367 | ||
f77bc6a4 ZX |
4368 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
4369 | struct kvm_interrupt *irq) | |
4370 | { | |
02cdb50f | 4371 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 4372 | return -EINVAL; |
1c1a9ce9 SR |
4373 | |
4374 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
4375 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
4376 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4377 | return 0; | |
4378 | } | |
4379 | ||
4380 | /* | |
4381 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
4382 | * fail for in-kernel 8259. | |
4383 | */ | |
4384 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 4385 | return -ENXIO; |
f77bc6a4 | 4386 | |
1c1a9ce9 SR |
4387 | if (vcpu->arch.pending_external_vector != -1) |
4388 | return -EEXIST; | |
f77bc6a4 | 4389 | |
1c1a9ce9 | 4390 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 4391 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
4392 | return 0; |
4393 | } | |
4394 | ||
c4abb7c9 JK |
4395 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
4396 | { | |
c4abb7c9 | 4397 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
4398 | |
4399 | return 0; | |
4400 | } | |
4401 | ||
f077825a PB |
4402 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
4403 | { | |
64d60670 PB |
4404 | kvm_make_request(KVM_REQ_SMI, vcpu); |
4405 | ||
f077825a PB |
4406 | return 0; |
4407 | } | |
4408 | ||
b209749f AK |
4409 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
4410 | struct kvm_tpr_access_ctl *tac) | |
4411 | { | |
4412 | if (tac->flags) | |
4413 | return -EINVAL; | |
4414 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
4415 | return 0; | |
4416 | } | |
4417 | ||
890ca9ae HY |
4418 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
4419 | u64 mcg_cap) | |
4420 | { | |
4421 | int r; | |
4422 | unsigned bank_num = mcg_cap & 0xff, bank; | |
4423 | ||
4424 | r = -EINVAL; | |
c4e0e4ab | 4425 | if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) |
890ca9ae | 4426 | goto out; |
c45dcc71 | 4427 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
4428 | goto out; |
4429 | r = 0; | |
4430 | vcpu->arch.mcg_cap = mcg_cap; | |
4431 | /* Init IA32_MCG_CTL to all 1s */ | |
4432 | if (mcg_cap & MCG_CTL_P) | |
4433 | vcpu->arch.mcg_ctl = ~(u64)0; | |
4434 | /* Init IA32_MCi_CTL to all 1s */ | |
4435 | for (bank = 0; bank < bank_num; bank++) | |
4436 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 | 4437 | |
b3646477 | 4438 | static_call(kvm_x86_setup_mce)(vcpu); |
890ca9ae HY |
4439 | out: |
4440 | return r; | |
4441 | } | |
4442 | ||
4443 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
4444 | struct kvm_x86_mce *mce) | |
4445 | { | |
4446 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
4447 | unsigned bank_num = mcg_cap & 0xff; | |
4448 | u64 *banks = vcpu->arch.mce_banks; | |
4449 | ||
4450 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
4451 | return -EINVAL; | |
4452 | /* | |
4453 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
4454 | * reporting is disabled | |
4455 | */ | |
4456 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
4457 | vcpu->arch.mcg_ctl != ~(u64)0) | |
4458 | return 0; | |
4459 | banks += 4 * mce->bank; | |
4460 | /* | |
4461 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
4462 | * reporting is disabled for the bank | |
4463 | */ | |
4464 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
4465 | return 0; | |
4466 | if (mce->status & MCI_STATUS_UC) { | |
4467 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 4468 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 4469 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
4470 | return 0; |
4471 | } | |
4472 | if (banks[1] & MCI_STATUS_VAL) | |
4473 | mce->status |= MCI_STATUS_OVER; | |
4474 | banks[2] = mce->addr; | |
4475 | banks[3] = mce->misc; | |
4476 | vcpu->arch.mcg_status = mce->mcg_status; | |
4477 | banks[1] = mce->status; | |
4478 | kvm_queue_exception(vcpu, MC_VECTOR); | |
4479 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
4480 | || !(banks[1] & MCI_STATUS_UC)) { | |
4481 | if (banks[1] & MCI_STATUS_VAL) | |
4482 | mce->status |= MCI_STATUS_OVER; | |
4483 | banks[2] = mce->addr; | |
4484 | banks[3] = mce->misc; | |
4485 | banks[1] = mce->status; | |
4486 | } else | |
4487 | banks[1] |= MCI_STATUS_OVER; | |
4488 | return 0; | |
4489 | } | |
4490 | ||
3cfc3092 JK |
4491 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
4492 | struct kvm_vcpu_events *events) | |
4493 | { | |
7460fb4a | 4494 | process_nmi(vcpu); |
59073aaf | 4495 | |
1f7becf1 JZ |
4496 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
4497 | process_smi(vcpu); | |
4498 | ||
a06230b6 OU |
4499 | /* |
4500 | * In guest mode, payload delivery should be deferred, | |
4501 | * so that the L1 hypervisor can intercept #PF before | |
4502 | * CR2 is modified (or intercept #DB before DR6 is | |
4503 | * modified under nVMX). Unless the per-VM capability, | |
4504 | * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of | |
4505 | * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we | |
4506 | * opportunistically defer the exception payload, deliver it if the | |
4507 | * capability hasn't been requested before processing a | |
4508 | * KVM_GET_VCPU_EVENTS. | |
4509 | */ | |
4510 | if (!vcpu->kvm->arch.exception_payload_enabled && | |
4511 | vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) | |
4512 | kvm_deliver_exception_payload(vcpu); | |
4513 | ||
664f8e26 | 4514 | /* |
59073aaf JM |
4515 | * The API doesn't provide the instruction length for software |
4516 | * exceptions, so don't report them. As long as the guest RIP | |
4517 | * isn't advanced, we should expect to encounter the exception | |
4518 | * again. | |
664f8e26 | 4519 | */ |
59073aaf JM |
4520 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
4521 | events->exception.injected = 0; | |
4522 | events->exception.pending = 0; | |
4523 | } else { | |
4524 | events->exception.injected = vcpu->arch.exception.injected; | |
4525 | events->exception.pending = vcpu->arch.exception.pending; | |
4526 | /* | |
4527 | * For ABI compatibility, deliberately conflate | |
4528 | * pending and injected exceptions when | |
4529 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
4530 | */ | |
4531 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4532 | events->exception.injected |= | |
4533 | vcpu->arch.exception.pending; | |
4534 | } | |
3cfc3092 JK |
4535 | events->exception.nr = vcpu->arch.exception.nr; |
4536 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
4537 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
4538 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
4539 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 4540 | |
03b82a30 | 4541 | events->interrupt.injected = |
04140b41 | 4542 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 4543 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 4544 | events->interrupt.soft = 0; |
b3646477 | 4545 | events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
3cfc3092 JK |
4546 | |
4547 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 4548 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
b3646477 | 4549 | events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); |
97e69aa6 | 4550 | events->nmi.pad = 0; |
3cfc3092 | 4551 | |
66450a21 | 4552 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 4553 | |
f077825a PB |
4554 | events->smi.smm = is_smm(vcpu); |
4555 | events->smi.pending = vcpu->arch.smi_pending; | |
4556 | events->smi.smm_inside_nmi = | |
4557 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
4558 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
4559 | ||
dab4b911 | 4560 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
4561 | | KVM_VCPUEVENT_VALID_SHADOW |
4562 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
4563 | if (vcpu->kvm->arch.exception_payload_enabled) |
4564 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
4565 | ||
97e69aa6 | 4566 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
4567 | } |
4568 | ||
dc87275f | 4569 | static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); |
6ef4e07e | 4570 | |
3cfc3092 JK |
4571 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
4572 | struct kvm_vcpu_events *events) | |
4573 | { | |
dab4b911 | 4574 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 4575 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 4576 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf JM |
4577 | | KVM_VCPUEVENT_VALID_SMM |
4578 | | KVM_VCPUEVENT_VALID_PAYLOAD)) | |
3cfc3092 JK |
4579 | return -EINVAL; |
4580 | ||
59073aaf JM |
4581 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
4582 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4583 | return -EINVAL; | |
4584 | if (events->exception.pending) | |
4585 | events->exception.injected = 0; | |
4586 | else | |
4587 | events->exception_has_payload = 0; | |
4588 | } else { | |
4589 | events->exception.pending = 0; | |
4590 | events->exception_has_payload = 0; | |
4591 | } | |
4592 | ||
4593 | if ((events->exception.injected || events->exception.pending) && | |
4594 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
4595 | return -EINVAL; |
4596 | ||
28bf2888 DH |
4597 | /* INITs are latched while in SMM */ |
4598 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
4599 | (events->smi.smm || events->smi.pending) && | |
4600 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
4601 | return -EINVAL; | |
4602 | ||
7460fb4a | 4603 | process_nmi(vcpu); |
59073aaf JM |
4604 | vcpu->arch.exception.injected = events->exception.injected; |
4605 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
4606 | vcpu->arch.exception.nr = events->exception.nr; |
4607 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
4608 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
4609 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
4610 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 4611 | |
04140b41 | 4612 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
4613 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
4614 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 | 4615 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
b3646477 JB |
4616 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, |
4617 | events->interrupt.shadow); | |
3cfc3092 JK |
4618 | |
4619 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
4620 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
4621 | vcpu->arch.nmi_pending = events->nmi.pending; | |
b3646477 | 4622 | static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); |
3cfc3092 | 4623 | |
66450a21 | 4624 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 4625 | lapic_in_kernel(vcpu)) |
66450a21 | 4626 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 4627 | |
f077825a | 4628 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
dc87275f SC |
4629 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) |
4630 | kvm_smm_changed(vcpu, events->smi.smm); | |
6ef4e07e | 4631 | |
f077825a | 4632 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
4633 | |
4634 | if (events->smi.smm) { | |
4635 | if (events->smi.smm_inside_nmi) | |
4636 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 4637 | else |
f4ef1910 | 4638 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
4639 | } |
4640 | ||
4641 | if (lapic_in_kernel(vcpu)) { | |
4642 | if (events->smi.latched_init) | |
4643 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
4644 | else | |
4645 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
4646 | } |
4647 | } | |
4648 | ||
3842d135 AK |
4649 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
4650 | ||
3cfc3092 JK |
4651 | return 0; |
4652 | } | |
4653 | ||
a1efbe77 JK |
4654 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
4655 | struct kvm_debugregs *dbgregs) | |
4656 | { | |
73aaf249 JK |
4657 | unsigned long val; |
4658 | ||
a1efbe77 | 4659 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 4660 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 4661 | dbgregs->dr6 = val; |
a1efbe77 JK |
4662 | dbgregs->dr7 = vcpu->arch.dr7; |
4663 | dbgregs->flags = 0; | |
97e69aa6 | 4664 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
4665 | } |
4666 | ||
4667 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
4668 | struct kvm_debugregs *dbgregs) | |
4669 | { | |
4670 | if (dbgregs->flags) | |
4671 | return -EINVAL; | |
4672 | ||
fd238002 | 4673 | if (!kvm_dr6_valid(dbgregs->dr6)) |
d14bdb55 | 4674 | return -EINVAL; |
fd238002 | 4675 | if (!kvm_dr7_valid(dbgregs->dr7)) |
d14bdb55 PB |
4676 | return -EINVAL; |
4677 | ||
a1efbe77 | 4678 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 4679 | kvm_update_dr0123(vcpu); |
a1efbe77 JK |
4680 | vcpu->arch.dr6 = dbgregs->dr6; |
4681 | vcpu->arch.dr7 = dbgregs->dr7; | |
9926c9fd | 4682 | kvm_update_dr7(vcpu); |
a1efbe77 | 4683 | |
a1efbe77 JK |
4684 | return 0; |
4685 | } | |
4686 | ||
df1daba7 PB |
4687 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
4688 | ||
4689 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
4690 | { | |
b666a4b6 | 4691 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
400e4b20 | 4692 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
4693 | u64 valid; |
4694 | ||
4695 | /* | |
4696 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4697 | * leaves 0 and 1 in the loop below. | |
4698 | */ | |
4699 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
4700 | ||
4701 | /* Set XSTATE_BV */ | |
00c87e9a | 4702 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
4703 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
4704 | ||
4705 | /* | |
4706 | * Copy each region from the possibly compacted offset to the | |
4707 | * non-compacted offset. | |
4708 | */ | |
d91cab78 | 4709 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4710 | while (valid) { |
71ef4533 | 4711 | u32 size, offset, ecx, edx; |
abd16d68 SAS |
4712 | u64 xfeature_mask = valid & -valid; |
4713 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
71ef4533 DH |
4714 | void *src; |
4715 | ||
4716 | cpuid_count(XSTATE_CPUID, xfeature_nr, | |
4717 | &size, &offset, &ecx, &edx); | |
38cfd5e3 | 4718 | |
71ef4533 DH |
4719 | if (xfeature_nr == XFEATURE_PKRU) { |
4720 | memcpy(dest + offset, &vcpu->arch.pkru, | |
4721 | sizeof(vcpu->arch.pkru)); | |
4722 | } else { | |
4723 | src = get_xsave_addr(xsave, xfeature_nr); | |
4724 | if (src) | |
4725 | memcpy(dest + offset, src, size); | |
df1daba7 PB |
4726 | } |
4727 | ||
abd16d68 | 4728 | valid -= xfeature_mask; |
df1daba7 PB |
4729 | } |
4730 | } | |
4731 | ||
4732 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
4733 | { | |
b666a4b6 | 4734 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
df1daba7 PB |
4735 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
4736 | u64 valid; | |
4737 | ||
4738 | /* | |
4739 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4740 | * leaves 0 and 1 in the loop below. | |
4741 | */ | |
4742 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
4743 | ||
4744 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 4745 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 4746 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 4747 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
4748 | |
4749 | /* | |
4750 | * Copy each region from the non-compacted offset to the | |
4751 | * possibly compacted offset. | |
4752 | */ | |
d91cab78 | 4753 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4754 | while (valid) { |
71ef4533 | 4755 | u32 size, offset, ecx, edx; |
abd16d68 SAS |
4756 | u64 xfeature_mask = valid & -valid; |
4757 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
71ef4533 DH |
4758 | |
4759 | cpuid_count(XSTATE_CPUID, xfeature_nr, | |
4760 | &size, &offset, &ecx, &edx); | |
4761 | ||
4762 | if (xfeature_nr == XFEATURE_PKRU) { | |
4763 | memcpy(&vcpu->arch.pkru, src + offset, | |
4764 | sizeof(vcpu->arch.pkru)); | |
4765 | } else { | |
4766 | void *dest = get_xsave_addr(xsave, xfeature_nr); | |
4767 | ||
4768 | if (dest) | |
38cfd5e3 | 4769 | memcpy(dest, src + offset, size); |
ee4100da | 4770 | } |
df1daba7 | 4771 | |
abd16d68 | 4772 | valid -= xfeature_mask; |
df1daba7 PB |
4773 | } |
4774 | } | |
4775 | ||
2d5b5a66 SY |
4776 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
4777 | struct kvm_xsave *guest_xsave) | |
4778 | { | |
ed02b213 TL |
4779 | if (!vcpu->arch.guest_fpu) |
4780 | return; | |
4781 | ||
d366bf7e | 4782 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
4783 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
4784 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 4785 | } else { |
2d5b5a66 | 4786 | memcpy(guest_xsave->region, |
b666a4b6 | 4787 | &vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4788 | sizeof(struct fxregs_state)); |
2d5b5a66 | 4789 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 4790 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
4791 | } |
4792 | } | |
4793 | ||
a575813b WL |
4794 | #define XSAVE_MXCSR_OFFSET 24 |
4795 | ||
2d5b5a66 SY |
4796 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
4797 | struct kvm_xsave *guest_xsave) | |
4798 | { | |
ed02b213 TL |
4799 | u64 xstate_bv; |
4800 | u32 mxcsr; | |
4801 | ||
4802 | if (!vcpu->arch.guest_fpu) | |
4803 | return 0; | |
4804 | ||
4805 | xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
4806 | mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; | |
2d5b5a66 | 4807 | |
d366bf7e | 4808 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
4809 | /* |
4810 | * Here we allow setting states that are not present in | |
4811 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
4812 | * with old userspace. | |
4813 | */ | |
cfc48181 | 4814 | if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) |
d7876f1b | 4815 | return -EINVAL; |
df1daba7 | 4816 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 4817 | } else { |
a575813b WL |
4818 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
4819 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 4820 | return -EINVAL; |
b666a4b6 | 4821 | memcpy(&vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4822 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
4823 | } |
4824 | return 0; | |
4825 | } | |
4826 | ||
4827 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
4828 | struct kvm_xcrs *guest_xcrs) | |
4829 | { | |
d366bf7e | 4830 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
4831 | guest_xcrs->nr_xcrs = 0; |
4832 | return; | |
4833 | } | |
4834 | ||
4835 | guest_xcrs->nr_xcrs = 1; | |
4836 | guest_xcrs->flags = 0; | |
4837 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
4838 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
4839 | } | |
4840 | ||
4841 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
4842 | struct kvm_xcrs *guest_xcrs) | |
4843 | { | |
4844 | int i, r = 0; | |
4845 | ||
d366bf7e | 4846 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
4847 | return -EINVAL; |
4848 | ||
4849 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
4850 | return -EINVAL; | |
4851 | ||
4852 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
4853 | /* Only support XCR0 currently */ | |
c67a04cb | 4854 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 4855 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 4856 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
4857 | break; |
4858 | } | |
4859 | if (r) | |
4860 | r = -EINVAL; | |
4861 | return r; | |
4862 | } | |
4863 | ||
1c0b28c2 EM |
4864 | /* |
4865 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
4866 | * stopped by the hypervisor. This function will be called from the host only. | |
4867 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
4868 | * does not support pv clocks. | |
4869 | */ | |
4870 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
4871 | { | |
0b79459b | 4872 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 4873 | return -EINVAL; |
51d59c6b | 4874 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
4875 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
4876 | return 0; | |
4877 | } | |
4878 | ||
5c919412 AS |
4879 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
4880 | struct kvm_enable_cap *cap) | |
4881 | { | |
57b119da VK |
4882 | int r; |
4883 | uint16_t vmcs_version; | |
4884 | void __user *user_ptr; | |
4885 | ||
5c919412 AS |
4886 | if (cap->flags) |
4887 | return -EINVAL; | |
4888 | ||
4889 | switch (cap->cap) { | |
efc479e6 RK |
4890 | case KVM_CAP_HYPERV_SYNIC2: |
4891 | if (cap->args[0]) | |
4892 | return -EINVAL; | |
df561f66 | 4893 | fallthrough; |
b2869f28 | 4894 | |
5c919412 | 4895 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
4896 | if (!irqchip_in_kernel(vcpu->kvm)) |
4897 | return -EINVAL; | |
efc479e6 RK |
4898 | return kvm_hv_activate_synic(vcpu, cap->cap == |
4899 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 4900 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
33b22172 | 4901 | if (!kvm_x86_ops.nested_ops->enable_evmcs) |
5158917c | 4902 | return -ENOTTY; |
33b22172 | 4903 | r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); |
57b119da VK |
4904 | if (!r) { |
4905 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
4906 | if (copy_to_user(user_ptr, &vmcs_version, | |
4907 | sizeof(vmcs_version))) | |
4908 | r = -EFAULT; | |
4909 | } | |
4910 | return r; | |
344c6c80 | 4911 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4912 | if (!kvm_x86_ops.enable_direct_tlbflush) |
344c6c80 TL |
4913 | return -ENOTTY; |
4914 | ||
b3646477 | 4915 | return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); |
57b119da | 4916 | |
644f7067 VK |
4917 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
4918 | return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); | |
4919 | ||
66570e96 OU |
4920 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
4921 | vcpu->arch.pv_cpuid.enforce = cap->args[0]; | |
01b4f510 OU |
4922 | if (vcpu->arch.pv_cpuid.enforce) |
4923 | kvm_update_pv_runtime(vcpu); | |
66570e96 OU |
4924 | |
4925 | return 0; | |
5c919412 AS |
4926 | default: |
4927 | return -EINVAL; | |
4928 | } | |
4929 | } | |
4930 | ||
313a3dc7 CO |
4931 | long kvm_arch_vcpu_ioctl(struct file *filp, |
4932 | unsigned int ioctl, unsigned long arg) | |
4933 | { | |
4934 | struct kvm_vcpu *vcpu = filp->private_data; | |
4935 | void __user *argp = (void __user *)arg; | |
4936 | int r; | |
d1ac91d8 | 4937 | union { |
6dba9403 | 4938 | struct kvm_sregs2 *sregs2; |
d1ac91d8 AK |
4939 | struct kvm_lapic_state *lapic; |
4940 | struct kvm_xsave *xsave; | |
4941 | struct kvm_xcrs *xcrs; | |
4942 | void *buffer; | |
4943 | } u; | |
4944 | ||
9b062471 CD |
4945 | vcpu_load(vcpu); |
4946 | ||
d1ac91d8 | 4947 | u.buffer = NULL; |
313a3dc7 CO |
4948 | switch (ioctl) { |
4949 | case KVM_GET_LAPIC: { | |
2204ae3c | 4950 | r = -EINVAL; |
bce87cce | 4951 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4952 | goto out; |
254272ce BG |
4953 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
4954 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 4955 | |
b772ff36 | 4956 | r = -ENOMEM; |
d1ac91d8 | 4957 | if (!u.lapic) |
b772ff36 | 4958 | goto out; |
d1ac91d8 | 4959 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4960 | if (r) |
4961 | goto out; | |
4962 | r = -EFAULT; | |
d1ac91d8 | 4963 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
4964 | goto out; |
4965 | r = 0; | |
4966 | break; | |
4967 | } | |
4968 | case KVM_SET_LAPIC: { | |
2204ae3c | 4969 | r = -EINVAL; |
bce87cce | 4970 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4971 | goto out; |
ff5c2c03 | 4972 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
4973 | if (IS_ERR(u.lapic)) { |
4974 | r = PTR_ERR(u.lapic); | |
4975 | goto out_nofree; | |
4976 | } | |
ff5c2c03 | 4977 | |
d1ac91d8 | 4978 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4979 | break; |
4980 | } | |
f77bc6a4 ZX |
4981 | case KVM_INTERRUPT: { |
4982 | struct kvm_interrupt irq; | |
4983 | ||
4984 | r = -EFAULT; | |
0e96f31e | 4985 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
4986 | goto out; |
4987 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
4988 | break; |
4989 | } | |
c4abb7c9 JK |
4990 | case KVM_NMI: { |
4991 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
4992 | break; |
4993 | } | |
f077825a PB |
4994 | case KVM_SMI: { |
4995 | r = kvm_vcpu_ioctl_smi(vcpu); | |
4996 | break; | |
4997 | } | |
313a3dc7 CO |
4998 | case KVM_SET_CPUID: { |
4999 | struct kvm_cpuid __user *cpuid_arg = argp; | |
5000 | struct kvm_cpuid cpuid; | |
5001 | ||
5002 | r = -EFAULT; | |
0e96f31e | 5003 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
5004 | goto out; |
5005 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
5006 | break; |
5007 | } | |
07716717 DK |
5008 | case KVM_SET_CPUID2: { |
5009 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
5010 | struct kvm_cpuid2 cpuid; | |
5011 | ||
5012 | r = -EFAULT; | |
0e96f31e | 5013 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
5014 | goto out; |
5015 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 5016 | cpuid_arg->entries); |
07716717 DK |
5017 | break; |
5018 | } | |
5019 | case KVM_GET_CPUID2: { | |
5020 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
5021 | struct kvm_cpuid2 cpuid; | |
5022 | ||
5023 | r = -EFAULT; | |
0e96f31e | 5024 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
5025 | goto out; |
5026 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 5027 | cpuid_arg->entries); |
07716717 DK |
5028 | if (r) |
5029 | goto out; | |
5030 | r = -EFAULT; | |
0e96f31e | 5031 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
5032 | goto out; |
5033 | r = 0; | |
5034 | break; | |
5035 | } | |
801e459a TL |
5036 | case KVM_GET_MSRS: { |
5037 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 5038 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 5039 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 5040 | break; |
801e459a TL |
5041 | } |
5042 | case KVM_SET_MSRS: { | |
5043 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 5044 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 5045 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 5046 | break; |
801e459a | 5047 | } |
b209749f AK |
5048 | case KVM_TPR_ACCESS_REPORTING: { |
5049 | struct kvm_tpr_access_ctl tac; | |
5050 | ||
5051 | r = -EFAULT; | |
0e96f31e | 5052 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
5053 | goto out; |
5054 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
5055 | if (r) | |
5056 | goto out; | |
5057 | r = -EFAULT; | |
0e96f31e | 5058 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
5059 | goto out; |
5060 | r = 0; | |
5061 | break; | |
5062 | }; | |
b93463aa AK |
5063 | case KVM_SET_VAPIC_ADDR: { |
5064 | struct kvm_vapic_addr va; | |
7301d6ab | 5065 | int idx; |
b93463aa AK |
5066 | |
5067 | r = -EINVAL; | |
35754c98 | 5068 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
5069 | goto out; |
5070 | r = -EFAULT; | |
0e96f31e | 5071 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 5072 | goto out; |
7301d6ab | 5073 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 5074 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 5075 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
5076 | break; |
5077 | } | |
890ca9ae HY |
5078 | case KVM_X86_SETUP_MCE: { |
5079 | u64 mcg_cap; | |
5080 | ||
5081 | r = -EFAULT; | |
0e96f31e | 5082 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
5083 | goto out; |
5084 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
5085 | break; | |
5086 | } | |
5087 | case KVM_X86_SET_MCE: { | |
5088 | struct kvm_x86_mce mce; | |
5089 | ||
5090 | r = -EFAULT; | |
0e96f31e | 5091 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
5092 | goto out; |
5093 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
5094 | break; | |
5095 | } | |
3cfc3092 JK |
5096 | case KVM_GET_VCPU_EVENTS: { |
5097 | struct kvm_vcpu_events events; | |
5098 | ||
5099 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
5100 | ||
5101 | r = -EFAULT; | |
5102 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
5103 | break; | |
5104 | r = 0; | |
5105 | break; | |
5106 | } | |
5107 | case KVM_SET_VCPU_EVENTS: { | |
5108 | struct kvm_vcpu_events events; | |
5109 | ||
5110 | r = -EFAULT; | |
5111 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
5112 | break; | |
5113 | ||
5114 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
5115 | break; | |
5116 | } | |
a1efbe77 JK |
5117 | case KVM_GET_DEBUGREGS: { |
5118 | struct kvm_debugregs dbgregs; | |
5119 | ||
5120 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
5121 | ||
5122 | r = -EFAULT; | |
5123 | if (copy_to_user(argp, &dbgregs, | |
5124 | sizeof(struct kvm_debugregs))) | |
5125 | break; | |
5126 | r = 0; | |
5127 | break; | |
5128 | } | |
5129 | case KVM_SET_DEBUGREGS: { | |
5130 | struct kvm_debugregs dbgregs; | |
5131 | ||
5132 | r = -EFAULT; | |
5133 | if (copy_from_user(&dbgregs, argp, | |
5134 | sizeof(struct kvm_debugregs))) | |
5135 | break; | |
5136 | ||
5137 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
5138 | break; | |
5139 | } | |
2d5b5a66 | 5140 | case KVM_GET_XSAVE: { |
254272ce | 5141 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5142 | r = -ENOMEM; |
d1ac91d8 | 5143 | if (!u.xsave) |
2d5b5a66 SY |
5144 | break; |
5145 | ||
d1ac91d8 | 5146 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5147 | |
5148 | r = -EFAULT; | |
d1ac91d8 | 5149 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
5150 | break; |
5151 | r = 0; | |
5152 | break; | |
5153 | } | |
5154 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 5155 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
5156 | if (IS_ERR(u.xsave)) { |
5157 | r = PTR_ERR(u.xsave); | |
5158 | goto out_nofree; | |
5159 | } | |
2d5b5a66 | 5160 | |
d1ac91d8 | 5161 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5162 | break; |
5163 | } | |
5164 | case KVM_GET_XCRS: { | |
254272ce | 5165 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5166 | r = -ENOMEM; |
d1ac91d8 | 5167 | if (!u.xcrs) |
2d5b5a66 SY |
5168 | break; |
5169 | ||
d1ac91d8 | 5170 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5171 | |
5172 | r = -EFAULT; | |
d1ac91d8 | 5173 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
5174 | sizeof(struct kvm_xcrs))) |
5175 | break; | |
5176 | r = 0; | |
5177 | break; | |
5178 | } | |
5179 | case KVM_SET_XCRS: { | |
ff5c2c03 | 5180 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
5181 | if (IS_ERR(u.xcrs)) { |
5182 | r = PTR_ERR(u.xcrs); | |
5183 | goto out_nofree; | |
5184 | } | |
2d5b5a66 | 5185 | |
d1ac91d8 | 5186 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5187 | break; |
5188 | } | |
92a1f12d JR |
5189 | case KVM_SET_TSC_KHZ: { |
5190 | u32 user_tsc_khz; | |
5191 | ||
5192 | r = -EINVAL; | |
92a1f12d JR |
5193 | user_tsc_khz = (u32)arg; |
5194 | ||
26769f96 MT |
5195 | if (kvm_has_tsc_control && |
5196 | user_tsc_khz >= kvm_max_guest_tsc_khz) | |
92a1f12d JR |
5197 | goto out; |
5198 | ||
cc578287 ZA |
5199 | if (user_tsc_khz == 0) |
5200 | user_tsc_khz = tsc_khz; | |
5201 | ||
381d585c HZ |
5202 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
5203 | r = 0; | |
92a1f12d | 5204 | |
92a1f12d JR |
5205 | goto out; |
5206 | } | |
5207 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 5208 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
5209 | goto out; |
5210 | } | |
1c0b28c2 EM |
5211 | case KVM_KVMCLOCK_CTRL: { |
5212 | r = kvm_set_guest_paused(vcpu); | |
5213 | goto out; | |
5214 | } | |
5c919412 AS |
5215 | case KVM_ENABLE_CAP: { |
5216 | struct kvm_enable_cap cap; | |
5217 | ||
5218 | r = -EFAULT; | |
5219 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
5220 | goto out; | |
5221 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
5222 | break; | |
5223 | } | |
8fcc4b59 JM |
5224 | case KVM_GET_NESTED_STATE: { |
5225 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5226 | u32 user_data_size; | |
5227 | ||
5228 | r = -EINVAL; | |
33b22172 | 5229 | if (!kvm_x86_ops.nested_ops->get_state) |
8fcc4b59 JM |
5230 | break; |
5231 | ||
5232 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 5233 | r = -EFAULT; |
8fcc4b59 | 5234 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 5235 | break; |
8fcc4b59 | 5236 | |
33b22172 PB |
5237 | r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, |
5238 | user_data_size); | |
8fcc4b59 | 5239 | if (r < 0) |
26b471c7 | 5240 | break; |
8fcc4b59 JM |
5241 | |
5242 | if (r > user_data_size) { | |
5243 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
5244 | r = -EFAULT; |
5245 | else | |
5246 | r = -E2BIG; | |
5247 | break; | |
8fcc4b59 | 5248 | } |
26b471c7 | 5249 | |
8fcc4b59 JM |
5250 | r = 0; |
5251 | break; | |
5252 | } | |
5253 | case KVM_SET_NESTED_STATE: { | |
5254 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5255 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 5256 | int idx; |
8fcc4b59 JM |
5257 | |
5258 | r = -EINVAL; | |
33b22172 | 5259 | if (!kvm_x86_ops.nested_ops->set_state) |
8fcc4b59 JM |
5260 | break; |
5261 | ||
26b471c7 | 5262 | r = -EFAULT; |
8fcc4b59 | 5263 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 5264 | break; |
8fcc4b59 | 5265 | |
26b471c7 | 5266 | r = -EINVAL; |
8fcc4b59 | 5267 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 5268 | break; |
8fcc4b59 JM |
5269 | |
5270 | if (kvm_state.flags & | |
8cab6507 | 5271 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
cc440cda PB |
5272 | | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING |
5273 | | KVM_STATE_NESTED_GIF_SET)) | |
26b471c7 | 5274 | break; |
8fcc4b59 JM |
5275 | |
5276 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
5277 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
5278 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 5279 | break; |
8fcc4b59 | 5280 | |
ad5996d9 | 5281 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
33b22172 | 5282 | r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 5283 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
5284 | break; |
5285 | } | |
c21d54f0 VK |
5286 | case KVM_GET_SUPPORTED_HV_CPUID: |
5287 | r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); | |
2bc39970 | 5288 | break; |
b59b153d | 5289 | #ifdef CONFIG_KVM_XEN |
3e324615 DW |
5290 | case KVM_XEN_VCPU_GET_ATTR: { |
5291 | struct kvm_xen_vcpu_attr xva; | |
5292 | ||
5293 | r = -EFAULT; | |
5294 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
5295 | goto out; | |
5296 | r = kvm_xen_vcpu_get_attr(vcpu, &xva); | |
5297 | if (!r && copy_to_user(argp, &xva, sizeof(xva))) | |
5298 | r = -EFAULT; | |
5299 | break; | |
5300 | } | |
5301 | case KVM_XEN_VCPU_SET_ATTR: { | |
5302 | struct kvm_xen_vcpu_attr xva; | |
5303 | ||
5304 | r = -EFAULT; | |
5305 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
5306 | goto out; | |
5307 | r = kvm_xen_vcpu_set_attr(vcpu, &xva); | |
5308 | break; | |
5309 | } | |
b59b153d | 5310 | #endif |
6dba9403 ML |
5311 | case KVM_GET_SREGS2: { |
5312 | u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); | |
5313 | r = -ENOMEM; | |
5314 | if (!u.sregs2) | |
5315 | goto out; | |
5316 | __get_sregs2(vcpu, u.sregs2); | |
5317 | r = -EFAULT; | |
5318 | if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) | |
5319 | goto out; | |
5320 | r = 0; | |
5321 | break; | |
5322 | } | |
5323 | case KVM_SET_SREGS2: { | |
5324 | u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); | |
5325 | if (IS_ERR(u.sregs2)) { | |
5326 | r = PTR_ERR(u.sregs2); | |
5327 | u.sregs2 = NULL; | |
5328 | goto out; | |
5329 | } | |
5330 | r = __set_sregs2(vcpu, u.sregs2); | |
5331 | break; | |
5332 | } | |
313a3dc7 CO |
5333 | default: |
5334 | r = -EINVAL; | |
5335 | } | |
5336 | out: | |
d1ac91d8 | 5337 | kfree(u.buffer); |
9b062471 CD |
5338 | out_nofree: |
5339 | vcpu_put(vcpu); | |
313a3dc7 CO |
5340 | return r; |
5341 | } | |
5342 | ||
1499fa80 | 5343 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
5344 | { |
5345 | return VM_FAULT_SIGBUS; | |
5346 | } | |
5347 | ||
1fe779f8 CO |
5348 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
5349 | { | |
5350 | int ret; | |
5351 | ||
5352 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 5353 | return -EINVAL; |
b3646477 | 5354 | ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); |
1fe779f8 CO |
5355 | return ret; |
5356 | } | |
5357 | ||
b927a3ce SY |
5358 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
5359 | u64 ident_addr) | |
5360 | { | |
b3646477 | 5361 | return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); |
b927a3ce SY |
5362 | } |
5363 | ||
1fe779f8 | 5364 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 5365 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
5366 | { |
5367 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
5368 | return -EINVAL; | |
5369 | ||
79fac95e | 5370 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
5371 | |
5372 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 5373 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 5374 | |
79fac95e | 5375 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
5376 | return 0; |
5377 | } | |
5378 | ||
bc8a3d89 | 5379 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 5380 | { |
39de71ec | 5381 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
5382 | } |
5383 | ||
1fe779f8 CO |
5384 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
5385 | { | |
90bca052 | 5386 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5387 | int r; |
5388 | ||
5389 | r = 0; | |
5390 | switch (chip->chip_id) { | |
5391 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 5392 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
5393 | sizeof(struct kvm_pic_state)); |
5394 | break; | |
5395 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 5396 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
5397 | sizeof(struct kvm_pic_state)); |
5398 | break; | |
5399 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5400 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5401 | break; |
5402 | default: | |
5403 | r = -EINVAL; | |
5404 | break; | |
5405 | } | |
5406 | return r; | |
5407 | } | |
5408 | ||
5409 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
5410 | { | |
90bca052 | 5411 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5412 | int r; |
5413 | ||
5414 | r = 0; | |
5415 | switch (chip->chip_id) { | |
5416 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
5417 | spin_lock(&pic->lock); |
5418 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 5419 | sizeof(struct kvm_pic_state)); |
90bca052 | 5420 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5421 | break; |
5422 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
5423 | spin_lock(&pic->lock); |
5424 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 5425 | sizeof(struct kvm_pic_state)); |
90bca052 | 5426 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5427 | break; |
5428 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5429 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5430 | break; |
5431 | default: | |
5432 | r = -EINVAL; | |
5433 | break; | |
5434 | } | |
90bca052 | 5435 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
5436 | return r; |
5437 | } | |
5438 | ||
e0f63cb9 SY |
5439 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
5440 | { | |
34f3941c RK |
5441 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
5442 | ||
5443 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
5444 | ||
5445 | mutex_lock(&kps->lock); | |
5446 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
5447 | mutex_unlock(&kps->lock); | |
2da29bcc | 5448 | return 0; |
e0f63cb9 SY |
5449 | } |
5450 | ||
5451 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
5452 | { | |
0185604c | 5453 | int i; |
09edea72 RK |
5454 | struct kvm_pit *pit = kvm->arch.vpit; |
5455 | ||
5456 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 5457 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 5458 | for (i = 0; i < 3; i++) |
09edea72 RK |
5459 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
5460 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 5461 | return 0; |
e9f42757 BK |
5462 | } |
5463 | ||
5464 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5465 | { | |
e9f42757 BK |
5466 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
5467 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
5468 | sizeof(ps->channels)); | |
5469 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
5470 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 5471 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 5472 | return 0; |
e9f42757 BK |
5473 | } |
5474 | ||
5475 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5476 | { | |
2da29bcc | 5477 | int start = 0; |
0185604c | 5478 | int i; |
e9f42757 | 5479 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
5480 | struct kvm_pit *pit = kvm->arch.vpit; |
5481 | ||
5482 | mutex_lock(&pit->pit_state.lock); | |
5483 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
5484 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
5485 | if (!prev_legacy && cur_legacy) | |
5486 | start = 1; | |
09edea72 RK |
5487 | memcpy(&pit->pit_state.channels, &ps->channels, |
5488 | sizeof(pit->pit_state.channels)); | |
5489 | pit->pit_state.flags = ps->flags; | |
0185604c | 5490 | for (i = 0; i < 3; i++) |
09edea72 | 5491 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 5492 | start && i == 0); |
09edea72 | 5493 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 5494 | return 0; |
e0f63cb9 SY |
5495 | } |
5496 | ||
52d939a0 MT |
5497 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
5498 | struct kvm_reinject_control *control) | |
5499 | { | |
71474e2f RK |
5500 | struct kvm_pit *pit = kvm->arch.vpit; |
5501 | ||
71474e2f RK |
5502 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
5503 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
5504 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
5505 | */ | |
5506 | mutex_lock(&pit->pit_state.lock); | |
5507 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
5508 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 5509 | |
52d939a0 MT |
5510 | return 0; |
5511 | } | |
5512 | ||
0dff0846 | 5513 | void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) |
5bb064dc | 5514 | { |
a018eba5 | 5515 | |
88178fd4 | 5516 | /* |
a018eba5 SC |
5517 | * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called |
5518 | * before reporting dirty_bitmap to userspace. KVM flushes the buffers | |
5519 | * on all VM-Exits, thus we only need to kick running vCPUs to force a | |
5520 | * VM-Exit. | |
88178fd4 | 5521 | */ |
a018eba5 SC |
5522 | struct kvm_vcpu *vcpu; |
5523 | int i; | |
5524 | ||
5525 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5526 | kvm_vcpu_kick(vcpu); | |
5bb064dc ZX |
5527 | } |
5528 | ||
aa2fbe6d YZ |
5529 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
5530 | bool line_status) | |
23d43cf9 CD |
5531 | { |
5532 | if (!irqchip_in_kernel(kvm)) | |
5533 | return -ENXIO; | |
5534 | ||
5535 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
5536 | irq_event->irq, irq_event->level, |
5537 | line_status); | |
23d43cf9 CD |
5538 | return 0; |
5539 | } | |
5540 | ||
e5d83c74 PB |
5541 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
5542 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
5543 | { |
5544 | int r; | |
5545 | ||
5546 | if (cap->flags) | |
5547 | return -EINVAL; | |
5548 | ||
5549 | switch (cap->cap) { | |
5550 | case KVM_CAP_DISABLE_QUIRKS: | |
5551 | kvm->arch.disabled_quirks = cap->args[0]; | |
5552 | r = 0; | |
5553 | break; | |
49df6397 SR |
5554 | case KVM_CAP_SPLIT_IRQCHIP: { |
5555 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
5556 | r = -EINVAL; |
5557 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
5558 | goto split_irqchip_unlock; | |
49df6397 SR |
5559 | r = -EEXIST; |
5560 | if (irqchip_in_kernel(kvm)) | |
5561 | goto split_irqchip_unlock; | |
557abc40 | 5562 | if (kvm->created_vcpus) |
49df6397 SR |
5563 | goto split_irqchip_unlock; |
5564 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 5565 | if (r) |
49df6397 SR |
5566 | goto split_irqchip_unlock; |
5567 | /* Pairs with irqchip_in_kernel. */ | |
5568 | smp_wmb(); | |
49776faf | 5569 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 5570 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
5571 | r = 0; |
5572 | split_irqchip_unlock: | |
5573 | mutex_unlock(&kvm->lock); | |
5574 | break; | |
5575 | } | |
37131313 RK |
5576 | case KVM_CAP_X2APIC_API: |
5577 | r = -EINVAL; | |
5578 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
5579 | break; | |
5580 | ||
5581 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
5582 | kvm->arch.x2apic_format = true; | |
c519265f RK |
5583 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
5584 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
5585 | |
5586 | r = 0; | |
5587 | break; | |
4d5422ce WL |
5588 | case KVM_CAP_X86_DISABLE_EXITS: |
5589 | r = -EINVAL; | |
5590 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
5591 | break; | |
5592 | ||
5593 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
5594 | kvm_can_mwait_in_guest()) | |
5595 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 5596 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 5597 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
5598 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
5599 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
5600 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
5601 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
5602 | r = 0; |
5603 | break; | |
6fbbde9a DS |
5604 | case KVM_CAP_MSR_PLATFORM_INFO: |
5605 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
5606 | r = 0; | |
c4f55198 JM |
5607 | break; |
5608 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
5609 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
5610 | r = 0; | |
6fbbde9a | 5611 | break; |
1ae09954 AG |
5612 | case KVM_CAP_X86_USER_SPACE_MSR: |
5613 | kvm->arch.user_space_msr_mask = cap->args[0]; | |
5614 | r = 0; | |
5615 | break; | |
fe6b6bc8 CQ |
5616 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
5617 | r = -EINVAL; | |
5618 | if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) | |
5619 | break; | |
5620 | ||
5621 | if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && | |
5622 | (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) | |
5623 | break; | |
5624 | ||
5625 | if (kvm_has_bus_lock_exit && | |
5626 | cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) | |
5627 | kvm->arch.bus_lock_detection_enabled = true; | |
5628 | r = 0; | |
5629 | break; | |
fe7e9488 SC |
5630 | #ifdef CONFIG_X86_SGX_KVM |
5631 | case KVM_CAP_SGX_ATTRIBUTE: { | |
5632 | unsigned long allowed_attributes = 0; | |
5633 | ||
5634 | r = sgx_set_attribute(&allowed_attributes, cap->args[0]); | |
5635 | if (r) | |
5636 | break; | |
5637 | ||
5638 | /* KVM only supports the PROVISIONKEY privileged attribute. */ | |
5639 | if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && | |
5640 | !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) | |
5641 | kvm->arch.sgx_provisioning_allowed = true; | |
5642 | else | |
5643 | r = -EINVAL; | |
5644 | break; | |
5645 | } | |
5646 | #endif | |
54526d1f NT |
5647 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
5648 | r = -EINVAL; | |
5649 | if (kvm_x86_ops.vm_copy_enc_context_from) | |
5650 | r = kvm_x86_ops.vm_copy_enc_context_from(kvm, cap->args[0]); | |
5651 | return r; | |
0dbb1123 AK |
5652 | case KVM_CAP_EXIT_HYPERCALL: |
5653 | if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { | |
5654 | r = -EINVAL; | |
5655 | break; | |
5656 | } | |
5657 | kvm->arch.hypercall_exit_enabled = cap->args[0]; | |
5658 | r = 0; | |
5659 | break; | |
19238e75 AL |
5660 | case KVM_CAP_EXIT_ON_EMULATION_FAILURE: |
5661 | r = -EINVAL; | |
5662 | if (cap->args[0] & ~1) | |
5663 | break; | |
5664 | kvm->arch.exit_on_emulation_error = cap->args[0]; | |
5665 | r = 0; | |
5666 | break; | |
90de4a18 NA |
5667 | default: |
5668 | r = -EINVAL; | |
5669 | break; | |
5670 | } | |
5671 | return r; | |
5672 | } | |
5673 | ||
b318e8de SC |
5674 | static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) |
5675 | { | |
5676 | struct kvm_x86_msr_filter *msr_filter; | |
5677 | ||
5678 | msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); | |
5679 | if (!msr_filter) | |
5680 | return NULL; | |
5681 | ||
5682 | msr_filter->default_allow = default_allow; | |
5683 | return msr_filter; | |
5684 | } | |
5685 | ||
5686 | static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) | |
1a155254 AG |
5687 | { |
5688 | u32 i; | |
1a155254 | 5689 | |
b318e8de SC |
5690 | if (!msr_filter) |
5691 | return; | |
5692 | ||
5693 | for (i = 0; i < msr_filter->count; i++) | |
5694 | kfree(msr_filter->ranges[i].bitmap); | |
1a155254 | 5695 | |
b318e8de | 5696 | kfree(msr_filter); |
1a155254 AG |
5697 | } |
5698 | ||
b318e8de SC |
5699 | static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, |
5700 | struct kvm_msr_filter_range *user_range) | |
1a155254 | 5701 | { |
1a155254 AG |
5702 | unsigned long *bitmap = NULL; |
5703 | size_t bitmap_size; | |
1a155254 AG |
5704 | |
5705 | if (!user_range->nmsrs) | |
5706 | return 0; | |
5707 | ||
aca35288 SC |
5708 | if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) |
5709 | return -EINVAL; | |
5710 | ||
5711 | if (!user_range->flags) | |
5712 | return -EINVAL; | |
5713 | ||
1a155254 AG |
5714 | bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); |
5715 | if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) | |
5716 | return -EINVAL; | |
5717 | ||
5718 | bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); | |
5719 | if (IS_ERR(bitmap)) | |
5720 | return PTR_ERR(bitmap); | |
5721 | ||
aca35288 | 5722 | msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { |
1a155254 AG |
5723 | .flags = user_range->flags, |
5724 | .base = user_range->base, | |
5725 | .nmsrs = user_range->nmsrs, | |
5726 | .bitmap = bitmap, | |
5727 | }; | |
5728 | ||
b318e8de | 5729 | msr_filter->count++; |
1a155254 | 5730 | return 0; |
1a155254 AG |
5731 | } |
5732 | ||
5733 | static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) | |
5734 | { | |
5735 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
b318e8de | 5736 | struct kvm_x86_msr_filter *new_filter, *old_filter; |
1a155254 AG |
5737 | struct kvm_msr_filter filter; |
5738 | bool default_allow; | |
043248b3 | 5739 | bool empty = true; |
b318e8de | 5740 | int r = 0; |
1a155254 AG |
5741 | u32 i; |
5742 | ||
5743 | if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) | |
5744 | return -EFAULT; | |
5745 | ||
043248b3 PB |
5746 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) |
5747 | empty &= !filter.ranges[i].nmsrs; | |
1a155254 AG |
5748 | |
5749 | default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); | |
043248b3 PB |
5750 | if (empty && !default_allow) |
5751 | return -EINVAL; | |
5752 | ||
b318e8de SC |
5753 | new_filter = kvm_alloc_msr_filter(default_allow); |
5754 | if (!new_filter) | |
5755 | return -ENOMEM; | |
1a155254 | 5756 | |
1a155254 | 5757 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { |
b318e8de SC |
5758 | r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); |
5759 | if (r) { | |
5760 | kvm_free_msr_filter(new_filter); | |
5761 | return r; | |
5762 | } | |
1a155254 AG |
5763 | } |
5764 | ||
b318e8de SC |
5765 | mutex_lock(&kvm->lock); |
5766 | ||
5767 | /* The per-VM filter is protected by kvm->lock... */ | |
5768 | old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); | |
5769 | ||
5770 | rcu_assign_pointer(kvm->arch.msr_filter, new_filter); | |
5771 | synchronize_srcu(&kvm->srcu); | |
5772 | ||
5773 | kvm_free_msr_filter(old_filter); | |
5774 | ||
1a155254 AG |
5775 | kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); |
5776 | mutex_unlock(&kvm->lock); | |
5777 | ||
b318e8de | 5778 | return 0; |
1a155254 AG |
5779 | } |
5780 | ||
7d62874f SS |
5781 | #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER |
5782 | static int kvm_arch_suspend_notifier(struct kvm *kvm) | |
5783 | { | |
5784 | struct kvm_vcpu *vcpu; | |
5785 | int i, ret = 0; | |
5786 | ||
5787 | mutex_lock(&kvm->lock); | |
5788 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
5789 | if (!vcpu->arch.pv_time_enabled) | |
5790 | continue; | |
5791 | ||
5792 | ret = kvm_set_guest_paused(vcpu); | |
5793 | if (ret) { | |
5794 | kvm_err("Failed to pause guest VCPU%d: %d\n", | |
5795 | vcpu->vcpu_id, ret); | |
5796 | break; | |
5797 | } | |
5798 | } | |
5799 | mutex_unlock(&kvm->lock); | |
5800 | ||
5801 | return ret ? NOTIFY_BAD : NOTIFY_DONE; | |
5802 | } | |
5803 | ||
5804 | int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) | |
5805 | { | |
5806 | switch (state) { | |
5807 | case PM_HIBERNATION_PREPARE: | |
5808 | case PM_SUSPEND_PREPARE: | |
5809 | return kvm_arch_suspend_notifier(kvm); | |
5810 | } | |
5811 | ||
5812 | return NOTIFY_DONE; | |
5813 | } | |
5814 | #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ | |
5815 | ||
1fe779f8 CO |
5816 | long kvm_arch_vm_ioctl(struct file *filp, |
5817 | unsigned int ioctl, unsigned long arg) | |
5818 | { | |
5819 | struct kvm *kvm = filp->private_data; | |
5820 | void __user *argp = (void __user *)arg; | |
367e1319 | 5821 | int r = -ENOTTY; |
f0d66275 DH |
5822 | /* |
5823 | * This union makes it completely explicit to gcc-3.x | |
5824 | * that these two variables' stack usage should be | |
5825 | * combined, not added together. | |
5826 | */ | |
5827 | union { | |
5828 | struct kvm_pit_state ps; | |
e9f42757 | 5829 | struct kvm_pit_state2 ps2; |
c5ff41ce | 5830 | struct kvm_pit_config pit_config; |
f0d66275 | 5831 | } u; |
1fe779f8 CO |
5832 | |
5833 | switch (ioctl) { | |
5834 | case KVM_SET_TSS_ADDR: | |
5835 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 5836 | break; |
b927a3ce SY |
5837 | case KVM_SET_IDENTITY_MAP_ADDR: { |
5838 | u64 ident_addr; | |
5839 | ||
1af1ac91 DH |
5840 | mutex_lock(&kvm->lock); |
5841 | r = -EINVAL; | |
5842 | if (kvm->created_vcpus) | |
5843 | goto set_identity_unlock; | |
b927a3ce | 5844 | r = -EFAULT; |
0e96f31e | 5845 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 5846 | goto set_identity_unlock; |
b927a3ce | 5847 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
5848 | set_identity_unlock: |
5849 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
5850 | break; |
5851 | } | |
1fe779f8 CO |
5852 | case KVM_SET_NR_MMU_PAGES: |
5853 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
5854 | break; |
5855 | case KVM_GET_NR_MMU_PAGES: | |
5856 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
5857 | break; | |
3ddea128 | 5858 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 5859 | mutex_lock(&kvm->lock); |
09941366 | 5860 | |
3ddea128 | 5861 | r = -EEXIST; |
35e6eaa3 | 5862 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 5863 | goto create_irqchip_unlock; |
09941366 | 5864 | |
3e515705 | 5865 | r = -EINVAL; |
557abc40 | 5866 | if (kvm->created_vcpus) |
3e515705 | 5867 | goto create_irqchip_unlock; |
09941366 RK |
5868 | |
5869 | r = kvm_pic_init(kvm); | |
5870 | if (r) | |
3ddea128 | 5871 | goto create_irqchip_unlock; |
09941366 RK |
5872 | |
5873 | r = kvm_ioapic_init(kvm); | |
5874 | if (r) { | |
09941366 | 5875 | kvm_pic_destroy(kvm); |
3ddea128 | 5876 | goto create_irqchip_unlock; |
09941366 RK |
5877 | } |
5878 | ||
399ec807 AK |
5879 | r = kvm_setup_default_irq_routing(kvm); |
5880 | if (r) { | |
72bb2fcd | 5881 | kvm_ioapic_destroy(kvm); |
09941366 | 5882 | kvm_pic_destroy(kvm); |
71ba994c | 5883 | goto create_irqchip_unlock; |
399ec807 | 5884 | } |
49776faf | 5885 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 5886 | smp_wmb(); |
49776faf | 5887 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
5888 | create_irqchip_unlock: |
5889 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 5890 | break; |
3ddea128 | 5891 | } |
7837699f | 5892 | case KVM_CREATE_PIT: |
c5ff41ce JK |
5893 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
5894 | goto create_pit; | |
5895 | case KVM_CREATE_PIT2: | |
5896 | r = -EFAULT; | |
5897 | if (copy_from_user(&u.pit_config, argp, | |
5898 | sizeof(struct kvm_pit_config))) | |
5899 | goto out; | |
5900 | create_pit: | |
250715a6 | 5901 | mutex_lock(&kvm->lock); |
269e05e4 AK |
5902 | r = -EEXIST; |
5903 | if (kvm->arch.vpit) | |
5904 | goto create_pit_unlock; | |
7837699f | 5905 | r = -ENOMEM; |
c5ff41ce | 5906 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
5907 | if (kvm->arch.vpit) |
5908 | r = 0; | |
269e05e4 | 5909 | create_pit_unlock: |
250715a6 | 5910 | mutex_unlock(&kvm->lock); |
7837699f | 5911 | break; |
1fe779f8 CO |
5912 | case KVM_GET_IRQCHIP: { |
5913 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5914 | struct kvm_irqchip *chip; |
1fe779f8 | 5915 | |
ff5c2c03 SL |
5916 | chip = memdup_user(argp, sizeof(*chip)); |
5917 | if (IS_ERR(chip)) { | |
5918 | r = PTR_ERR(chip); | |
1fe779f8 | 5919 | goto out; |
ff5c2c03 SL |
5920 | } |
5921 | ||
1fe779f8 | 5922 | r = -ENXIO; |
826da321 | 5923 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5924 | goto get_irqchip_out; |
5925 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 5926 | if (r) |
f0d66275 | 5927 | goto get_irqchip_out; |
1fe779f8 | 5928 | r = -EFAULT; |
0e96f31e | 5929 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 5930 | goto get_irqchip_out; |
1fe779f8 | 5931 | r = 0; |
f0d66275 DH |
5932 | get_irqchip_out: |
5933 | kfree(chip); | |
1fe779f8 CO |
5934 | break; |
5935 | } | |
5936 | case KVM_SET_IRQCHIP: { | |
5937 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5938 | struct kvm_irqchip *chip; |
1fe779f8 | 5939 | |
ff5c2c03 SL |
5940 | chip = memdup_user(argp, sizeof(*chip)); |
5941 | if (IS_ERR(chip)) { | |
5942 | r = PTR_ERR(chip); | |
1fe779f8 | 5943 | goto out; |
ff5c2c03 SL |
5944 | } |
5945 | ||
1fe779f8 | 5946 | r = -ENXIO; |
826da321 | 5947 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5948 | goto set_irqchip_out; |
5949 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
5950 | set_irqchip_out: |
5951 | kfree(chip); | |
1fe779f8 CO |
5952 | break; |
5953 | } | |
e0f63cb9 | 5954 | case KVM_GET_PIT: { |
e0f63cb9 | 5955 | r = -EFAULT; |
f0d66275 | 5956 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5957 | goto out; |
5958 | r = -ENXIO; | |
5959 | if (!kvm->arch.vpit) | |
5960 | goto out; | |
f0d66275 | 5961 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
5962 | if (r) |
5963 | goto out; | |
5964 | r = -EFAULT; | |
f0d66275 | 5965 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5966 | goto out; |
5967 | r = 0; | |
5968 | break; | |
5969 | } | |
5970 | case KVM_SET_PIT: { | |
e0f63cb9 | 5971 | r = -EFAULT; |
0e96f31e | 5972 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 | 5973 | goto out; |
7289fdb5 | 5974 | mutex_lock(&kvm->lock); |
e0f63cb9 SY |
5975 | r = -ENXIO; |
5976 | if (!kvm->arch.vpit) | |
7289fdb5 | 5977 | goto set_pit_out; |
f0d66275 | 5978 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
7289fdb5 SR |
5979 | set_pit_out: |
5980 | mutex_unlock(&kvm->lock); | |
e0f63cb9 SY |
5981 | break; |
5982 | } | |
e9f42757 BK |
5983 | case KVM_GET_PIT2: { |
5984 | r = -ENXIO; | |
5985 | if (!kvm->arch.vpit) | |
5986 | goto out; | |
5987 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
5988 | if (r) | |
5989 | goto out; | |
5990 | r = -EFAULT; | |
5991 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
5992 | goto out; | |
5993 | r = 0; | |
5994 | break; | |
5995 | } | |
5996 | case KVM_SET_PIT2: { | |
5997 | r = -EFAULT; | |
5998 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
5999 | goto out; | |
7289fdb5 | 6000 | mutex_lock(&kvm->lock); |
e9f42757 BK |
6001 | r = -ENXIO; |
6002 | if (!kvm->arch.vpit) | |
7289fdb5 | 6003 | goto set_pit2_out; |
e9f42757 | 6004 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); |
7289fdb5 SR |
6005 | set_pit2_out: |
6006 | mutex_unlock(&kvm->lock); | |
e9f42757 BK |
6007 | break; |
6008 | } | |
52d939a0 MT |
6009 | case KVM_REINJECT_CONTROL: { |
6010 | struct kvm_reinject_control control; | |
6011 | r = -EFAULT; | |
6012 | if (copy_from_user(&control, argp, sizeof(control))) | |
6013 | goto out; | |
cad23e72 ML |
6014 | r = -ENXIO; |
6015 | if (!kvm->arch.vpit) | |
6016 | goto out; | |
52d939a0 | 6017 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
6018 | break; |
6019 | } | |
d71ba788 PB |
6020 | case KVM_SET_BOOT_CPU_ID: |
6021 | r = 0; | |
6022 | mutex_lock(&kvm->lock); | |
557abc40 | 6023 | if (kvm->created_vcpus) |
d71ba788 PB |
6024 | r = -EBUSY; |
6025 | else | |
6026 | kvm->arch.bsp_vcpu_id = arg; | |
6027 | mutex_unlock(&kvm->lock); | |
6028 | break; | |
b59b153d | 6029 | #ifdef CONFIG_KVM_XEN |
ffde22ac | 6030 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 6031 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 6032 | r = -EFAULT; |
51776043 | 6033 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac | 6034 | goto out; |
78e9878c | 6035 | r = kvm_xen_hvm_config(kvm, &xhc); |
ffde22ac ES |
6036 | break; |
6037 | } | |
a76b9641 JM |
6038 | case KVM_XEN_HVM_GET_ATTR: { |
6039 | struct kvm_xen_hvm_attr xha; | |
6040 | ||
6041 | r = -EFAULT; | |
6042 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
ffde22ac | 6043 | goto out; |
a76b9641 JM |
6044 | r = kvm_xen_hvm_get_attr(kvm, &xha); |
6045 | if (!r && copy_to_user(argp, &xha, sizeof(xha))) | |
6046 | r = -EFAULT; | |
6047 | break; | |
6048 | } | |
6049 | case KVM_XEN_HVM_SET_ATTR: { | |
6050 | struct kvm_xen_hvm_attr xha; | |
6051 | ||
6052 | r = -EFAULT; | |
6053 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
6054 | goto out; | |
6055 | r = kvm_xen_hvm_set_attr(kvm, &xha); | |
ffde22ac ES |
6056 | break; |
6057 | } | |
b59b153d | 6058 | #endif |
afbcf7ab | 6059 | case KVM_SET_CLOCK: { |
77fcbe82 | 6060 | struct kvm_arch *ka = &kvm->arch; |
afbcf7ab GC |
6061 | struct kvm_clock_data user_ns; |
6062 | u64 now_ns; | |
afbcf7ab GC |
6063 | |
6064 | r = -EFAULT; | |
6065 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
6066 | goto out; | |
6067 | ||
6068 | r = -EINVAL; | |
6069 | if (user_ns.flags) | |
6070 | goto out; | |
6071 | ||
6072 | r = 0; | |
0bc48bea RK |
6073 | /* |
6074 | * TODO: userspace has to take care of races with VCPU_RUN, so | |
6075 | * kvm_gen_update_masterclock() can be cut down to locked | |
6076 | * pvclock_update_vm_gtod_copy(). | |
6077 | */ | |
6078 | kvm_gen_update_masterclock(kvm); | |
77fcbe82 VK |
6079 | |
6080 | /* | |
6081 | * This pairs with kvm_guest_time_update(): when masterclock is | |
6082 | * in use, we use master_kernel_ns + kvmclock_offset to set | |
6083 | * unsigned 'system_time' so if we use get_kvmclock_ns() (which | |
6084 | * is slightly ahead) here we risk going negative on unsigned | |
6085 | * 'system_time' when 'user_ns.clock' is very small. | |
6086 | */ | |
6087 | spin_lock_irq(&ka->pvclock_gtod_sync_lock); | |
6088 | if (kvm->arch.use_master_clock) | |
6089 | now_ns = ka->master_kernel_ns; | |
6090 | else | |
6091 | now_ns = get_kvmclock_base_ns(); | |
6092 | ka->kvmclock_offset = user_ns.clock - now_ns; | |
6093 | spin_unlock_irq(&ka->pvclock_gtod_sync_lock); | |
6094 | ||
0bc48bea | 6095 | kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); |
afbcf7ab GC |
6096 | break; |
6097 | } | |
6098 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
6099 | struct kvm_clock_data user_ns; |
6100 | u64 now_ns; | |
6101 | ||
e891a32e | 6102 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 6103 | user_ns.clock = now_ns; |
e3fd9a93 | 6104 | user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; |
97e69aa6 | 6105 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
6106 | |
6107 | r = -EFAULT; | |
6108 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
6109 | goto out; | |
6110 | r = 0; | |
6111 | break; | |
6112 | } | |
5acc5c06 BS |
6113 | case KVM_MEMORY_ENCRYPT_OP: { |
6114 | r = -ENOTTY; | |
afaf0b2f | 6115 | if (kvm_x86_ops.mem_enc_op) |
b3646477 | 6116 | r = static_call(kvm_x86_mem_enc_op)(kvm, argp); |
5acc5c06 BS |
6117 | break; |
6118 | } | |
69eaedee BS |
6119 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
6120 | struct kvm_enc_region region; | |
6121 | ||
6122 | r = -EFAULT; | |
6123 | if (copy_from_user(®ion, argp, sizeof(region))) | |
6124 | goto out; | |
6125 | ||
6126 | r = -ENOTTY; | |
afaf0b2f | 6127 | if (kvm_x86_ops.mem_enc_reg_region) |
b3646477 | 6128 | r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); |
69eaedee BS |
6129 | break; |
6130 | } | |
6131 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
6132 | struct kvm_enc_region region; | |
6133 | ||
6134 | r = -EFAULT; | |
6135 | if (copy_from_user(®ion, argp, sizeof(region))) | |
6136 | goto out; | |
6137 | ||
6138 | r = -ENOTTY; | |
afaf0b2f | 6139 | if (kvm_x86_ops.mem_enc_unreg_region) |
b3646477 | 6140 | r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); |
69eaedee BS |
6141 | break; |
6142 | } | |
faeb7833 RK |
6143 | case KVM_HYPERV_EVENTFD: { |
6144 | struct kvm_hyperv_eventfd hvevfd; | |
6145 | ||
6146 | r = -EFAULT; | |
6147 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
6148 | goto out; | |
6149 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
6150 | break; | |
6151 | } | |
66bb8a06 EH |
6152 | case KVM_SET_PMU_EVENT_FILTER: |
6153 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
6154 | break; | |
1a155254 AG |
6155 | case KVM_X86_SET_MSR_FILTER: |
6156 | r = kvm_vm_ioctl_set_msr_filter(kvm, argp); | |
6157 | break; | |
1fe779f8 | 6158 | default: |
ad6260da | 6159 | r = -ENOTTY; |
1fe779f8 CO |
6160 | } |
6161 | out: | |
6162 | return r; | |
6163 | } | |
6164 | ||
a16b043c | 6165 | static void kvm_init_msr_list(void) |
043405e1 | 6166 | { |
24c29b7a | 6167 | struct x86_pmu_capability x86_pmu; |
043405e1 | 6168 | u32 dummy[2]; |
7a5ee6ed | 6169 | unsigned i; |
043405e1 | 6170 | |
e2ada66e | 6171 | BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, |
7a5ee6ed | 6172 | "Please update the fixed PMCs in msrs_to_saved_all[]"); |
24c29b7a PB |
6173 | |
6174 | perf_get_x86_pmu_capability(&x86_pmu); | |
e2ada66e | 6175 | |
6cbee2b9 XL |
6176 | num_msrs_to_save = 0; |
6177 | num_emulated_msrs = 0; | |
6178 | num_msr_based_features = 0; | |
6179 | ||
7a5ee6ed CQ |
6180 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { |
6181 | if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) | |
043405e1 | 6182 | continue; |
93c4adc7 PB |
6183 | |
6184 | /* | |
6185 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 6186 | * to the guests in some cases. |
93c4adc7 | 6187 | */ |
7a5ee6ed | 6188 | switch (msrs_to_save_all[i]) { |
93c4adc7 | 6189 | case MSR_IA32_BNDCFGS: |
503234b3 | 6190 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
6191 | continue; |
6192 | break; | |
9dbe6cf9 | 6193 | case MSR_TSC_AUX: |
36fa06f9 SC |
6194 | if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && |
6195 | !kvm_cpu_cap_has(X86_FEATURE_RDPID)) | |
9dbe6cf9 PB |
6196 | continue; |
6197 | break; | |
f4cfcd2d ML |
6198 | case MSR_IA32_UMWAIT_CONTROL: |
6199 | if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) | |
6200 | continue; | |
6201 | break; | |
bf8c55d8 CP |
6202 | case MSR_IA32_RTIT_CTL: |
6203 | case MSR_IA32_RTIT_STATUS: | |
7b874c26 | 6204 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) |
bf8c55d8 CP |
6205 | continue; |
6206 | break; | |
6207 | case MSR_IA32_RTIT_CR3_MATCH: | |
7b874c26 | 6208 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
6209 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) |
6210 | continue; | |
6211 | break; | |
6212 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
6213 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
7b874c26 | 6214 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
6215 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && |
6216 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
6217 | continue; | |
6218 | break; | |
7cb85fc4 | 6219 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: |
7b874c26 | 6220 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
7a5ee6ed | 6221 | msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= |
bf8c55d8 CP |
6222 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) |
6223 | continue; | |
6224 | break; | |
cf05a67b | 6225 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: |
7a5ee6ed | 6226 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= |
24c29b7a PB |
6227 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
6228 | continue; | |
6229 | break; | |
cf05a67b | 6230 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: |
7a5ee6ed | 6231 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= |
24c29b7a PB |
6232 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
6233 | continue; | |
7cb85fc4 | 6234 | break; |
93c4adc7 PB |
6235 | default: |
6236 | break; | |
6237 | } | |
6238 | ||
7a5ee6ed | 6239 | msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; |
043405e1 | 6240 | } |
62ef68bb | 6241 | |
7a5ee6ed | 6242 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
b3646477 | 6243 | if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) |
bc226f07 | 6244 | continue; |
62ef68bb | 6245 | |
7a5ee6ed | 6246 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 6247 | } |
801e459a | 6248 | |
7a5ee6ed | 6249 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { |
801e459a TL |
6250 | struct kvm_msr_entry msr; |
6251 | ||
7a5ee6ed | 6252 | msr.index = msr_based_features_all[i]; |
66421c1e | 6253 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
6254 | continue; |
6255 | ||
7a5ee6ed | 6256 | msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; |
801e459a | 6257 | } |
043405e1 CO |
6258 | } |
6259 | ||
bda9020e MT |
6260 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
6261 | const void *v) | |
bbd9b64e | 6262 | { |
70252a10 AK |
6263 | int handled = 0; |
6264 | int n; | |
6265 | ||
6266 | do { | |
6267 | n = min(len, 8); | |
bce87cce | 6268 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
6269 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
6270 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
6271 | break; |
6272 | handled += n; | |
6273 | addr += n; | |
6274 | len -= n; | |
6275 | v += n; | |
6276 | } while (len); | |
bbd9b64e | 6277 | |
70252a10 | 6278 | return handled; |
bbd9b64e CO |
6279 | } |
6280 | ||
bda9020e | 6281 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 6282 | { |
70252a10 AK |
6283 | int handled = 0; |
6284 | int n; | |
6285 | ||
6286 | do { | |
6287 | n = min(len, 8); | |
bce87cce | 6288 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
6289 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
6290 | addr, n, v)) | |
6291 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 6292 | break; |
e39d200f | 6293 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
6294 | handled += n; |
6295 | addr += n; | |
6296 | len -= n; | |
6297 | v += n; | |
6298 | } while (len); | |
bbd9b64e | 6299 | |
70252a10 | 6300 | return handled; |
bbd9b64e CO |
6301 | } |
6302 | ||
2dafc6c2 GN |
6303 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
6304 | struct kvm_segment *var, int seg) | |
6305 | { | |
b3646477 | 6306 | static_call(kvm_x86_set_segment)(vcpu, var, seg); |
2dafc6c2 GN |
6307 | } |
6308 | ||
6309 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
6310 | struct kvm_segment *var, int seg) | |
6311 | { | |
b3646477 | 6312 | static_call(kvm_x86_get_segment)(vcpu, var, seg); |
2dafc6c2 GN |
6313 | } |
6314 | ||
54987b7a PB |
6315 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
6316 | struct x86_exception *exception) | |
02f59dc9 JR |
6317 | { |
6318 | gpa_t t_gpa; | |
02f59dc9 JR |
6319 | |
6320 | BUG_ON(!mmu_is_nested(vcpu)); | |
6321 | ||
6322 | /* NPT walks are always user-walks */ | |
6323 | access |= PFERR_USER_MASK; | |
44dd3ffa | 6324 | t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
6325 | |
6326 | return t_gpa; | |
6327 | } | |
6328 | ||
ab9ae313 AK |
6329 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
6330 | struct x86_exception *exception) | |
1871c602 | 6331 | { |
b3646477 | 6332 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
ab9ae313 | 6333 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 | 6334 | } |
54f958cd | 6335 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); |
1871c602 | 6336 | |
ab9ae313 AK |
6337 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
6338 | struct x86_exception *exception) | |
1871c602 | 6339 | { |
b3646477 | 6340 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 6341 | access |= PFERR_FETCH_MASK; |
ab9ae313 | 6342 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
6343 | } |
6344 | ||
ab9ae313 AK |
6345 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
6346 | struct x86_exception *exception) | |
1871c602 | 6347 | { |
b3646477 | 6348 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 6349 | access |= PFERR_WRITE_MASK; |
ab9ae313 | 6350 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 | 6351 | } |
54f958cd | 6352 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); |
1871c602 GN |
6353 | |
6354 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
6355 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
6356 | struct x86_exception *exception) | |
1871c602 | 6357 | { |
ab9ae313 | 6358 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
6359 | } |
6360 | ||
6361 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
6362 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 6363 | struct x86_exception *exception) |
bbd9b64e CO |
6364 | { |
6365 | void *data = val; | |
10589a46 | 6366 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
6367 | |
6368 | while (bytes) { | |
14dfe855 | 6369 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 6370 | exception); |
bbd9b64e | 6371 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 6372 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
6373 | int ret; |
6374 | ||
bcc55cba | 6375 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6376 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
6377 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
6378 | offset, toread); | |
10589a46 | 6379 | if (ret < 0) { |
c3cd7ffa | 6380 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
6381 | goto out; |
6382 | } | |
bbd9b64e | 6383 | |
77c2002e IE |
6384 | bytes -= toread; |
6385 | data += toread; | |
6386 | addr += toread; | |
bbd9b64e | 6387 | } |
10589a46 | 6388 | out: |
10589a46 | 6389 | return r; |
bbd9b64e | 6390 | } |
77c2002e | 6391 | |
1871c602 | 6392 | /* used for instruction fetching */ |
0f65dd70 AK |
6393 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
6394 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 6395 | struct x86_exception *exception) |
1871c602 | 6396 | { |
0f65dd70 | 6397 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
b3646477 | 6398 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
6399 | unsigned offset; |
6400 | int ret; | |
0f65dd70 | 6401 | |
44583cba PB |
6402 | /* Inline kvm_read_guest_virt_helper for speed. */ |
6403 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
6404 | exception); | |
6405 | if (unlikely(gpa == UNMAPPED_GVA)) | |
6406 | return X86EMUL_PROPAGATE_FAULT; | |
6407 | ||
6408 | offset = addr & (PAGE_SIZE-1); | |
6409 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
6410 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
6411 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
6412 | offset, bytes); | |
44583cba PB |
6413 | if (unlikely(ret < 0)) |
6414 | return X86EMUL_IO_NEEDED; | |
6415 | ||
6416 | return X86EMUL_CONTINUE; | |
1871c602 GN |
6417 | } |
6418 | ||
ce14e868 | 6419 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 6420 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 6421 | struct x86_exception *exception) |
1871c602 | 6422 | { |
b3646477 | 6423 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 6424 | |
353c0956 PB |
6425 | /* |
6426 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
6427 | * is returned, but our callers are not ready for that and they blindly | |
6428 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
6429 | * uninitialized kernel stack memory into cr2 and error code. | |
6430 | */ | |
6431 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 6432 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 6433 | exception); |
1871c602 | 6434 | } |
064aea77 | 6435 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 6436 | |
ce14e868 PB |
6437 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
6438 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 6439 | struct x86_exception *exception, bool system) |
1871c602 | 6440 | { |
0f65dd70 | 6441 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3c9fa24c PB |
6442 | u32 access = 0; |
6443 | ||
b3646477 | 6444 | if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) |
3c9fa24c PB |
6445 | access |= PFERR_USER_MASK; |
6446 | ||
6447 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
6448 | } |
6449 | ||
7a036a6f RK |
6450 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
6451 | unsigned long addr, void *val, unsigned int bytes) | |
6452 | { | |
6453 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6454 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
6455 | ||
6456 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
6457 | } | |
6458 | ||
ce14e868 PB |
6459 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
6460 | struct kvm_vcpu *vcpu, u32 access, | |
6461 | struct x86_exception *exception) | |
77c2002e IE |
6462 | { |
6463 | void *data = val; | |
6464 | int r = X86EMUL_CONTINUE; | |
6465 | ||
6466 | while (bytes) { | |
14dfe855 | 6467 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
ce14e868 | 6468 | access, |
ab9ae313 | 6469 | exception); |
77c2002e IE |
6470 | unsigned offset = addr & (PAGE_SIZE-1); |
6471 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
6472 | int ret; | |
6473 | ||
bcc55cba | 6474 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6475 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 6476 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 6477 | if (ret < 0) { |
c3cd7ffa | 6478 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
6479 | goto out; |
6480 | } | |
6481 | ||
6482 | bytes -= towrite; | |
6483 | data += towrite; | |
6484 | addr += towrite; | |
6485 | } | |
6486 | out: | |
6487 | return r; | |
6488 | } | |
ce14e868 PB |
6489 | |
6490 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
6491 | unsigned int bytes, struct x86_exception *exception, |
6492 | bool system) | |
ce14e868 PB |
6493 | { |
6494 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
3c9fa24c PB |
6495 | u32 access = PFERR_WRITE_MASK; |
6496 | ||
b3646477 | 6497 | if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) |
3c9fa24c | 6498 | access |= PFERR_USER_MASK; |
ce14e868 PB |
6499 | |
6500 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 6501 | access, exception); |
ce14e868 PB |
6502 | } |
6503 | ||
6504 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
6505 | unsigned int bytes, struct x86_exception *exception) | |
6506 | { | |
c595ceee PB |
6507 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
6508 | vcpu->arch.l1tf_flush_l1d = true; | |
6509 | ||
ce14e868 PB |
6510 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
6511 | PFERR_WRITE_MASK, exception); | |
6512 | } | |
6a4d7550 | 6513 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 6514 | |
082d06ed WL |
6515 | int handle_ud(struct kvm_vcpu *vcpu) |
6516 | { | |
b3dc0695 | 6517 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
6c86eedc | 6518 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
6519 | char sig[5]; /* ud2; .ascii "kvm" */ |
6520 | struct x86_exception e; | |
6521 | ||
b3646477 | 6522 | if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) |
09e3e2a1 SC |
6523 | return 1; |
6524 | ||
6c86eedc | 6525 | if (force_emulation_prefix && |
3c9fa24c PB |
6526 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
6527 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 6528 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
6c86eedc | 6529 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 6530 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 6531 | } |
082d06ed | 6532 | |
60fc3d02 | 6533 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
6534 | } |
6535 | EXPORT_SYMBOL_GPL(handle_ud); | |
6536 | ||
0f89b207 TL |
6537 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6538 | gpa_t gpa, bool write) | |
6539 | { | |
6540 | /* For APIC access vmexit */ | |
6541 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6542 | return 1; | |
6543 | ||
6544 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
6545 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
6546 | return 1; | |
6547 | } | |
6548 | ||
6549 | return 0; | |
6550 | } | |
6551 | ||
af7cc7d1 XG |
6552 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6553 | gpa_t *gpa, struct x86_exception *exception, | |
6554 | bool write) | |
6555 | { | |
b3646477 | 6556 | u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) |
97d64b78 | 6557 | | (write ? PFERR_WRITE_MASK : 0); |
af7cc7d1 | 6558 | |
be94f6b7 HH |
6559 | /* |
6560 | * currently PKRU is only applied to ept enabled guest so | |
6561 | * there is no pkey in EPT page table for L1 guest or EPT | |
6562 | * shadow page table for L2 guest. | |
6563 | */ | |
908b7d43 SC |
6564 | if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || |
6565 | !permission_fault(vcpu, vcpu->arch.walk_mmu, | |
6566 | vcpu->arch.mmio_access, 0, access))) { | |
bebb106a XG |
6567 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
6568 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 6569 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
6570 | return 1; |
6571 | } | |
6572 | ||
af7cc7d1 XG |
6573 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
6574 | ||
6575 | if (*gpa == UNMAPPED_GVA) | |
6576 | return -1; | |
6577 | ||
0f89b207 | 6578 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
6579 | } |
6580 | ||
3200f405 | 6581 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 6582 | const void *val, int bytes) |
bbd9b64e CO |
6583 | { |
6584 | int ret; | |
6585 | ||
54bf36aa | 6586 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 6587 | if (ret < 0) |
bbd9b64e | 6588 | return 0; |
0eb05bf2 | 6589 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
6590 | return 1; |
6591 | } | |
6592 | ||
77d197b2 XG |
6593 | struct read_write_emulator_ops { |
6594 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
6595 | int bytes); | |
6596 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6597 | void *val, int bytes); | |
6598 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6599 | int bytes, void *val); | |
6600 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6601 | void *val, int bytes); | |
6602 | bool write; | |
6603 | }; | |
6604 | ||
6605 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
6606 | { | |
6607 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 6608 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 6609 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
6610 | vcpu->mmio_read_completed = 0; |
6611 | return 1; | |
6612 | } | |
6613 | ||
6614 | return 0; | |
6615 | } | |
6616 | ||
6617 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6618 | void *val, int bytes) | |
6619 | { | |
54bf36aa | 6620 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
6621 | } |
6622 | ||
6623 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6624 | void *val, int bytes) | |
6625 | { | |
6626 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
6627 | } | |
6628 | ||
6629 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
6630 | { | |
e39d200f | 6631 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
6632 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
6633 | } | |
6634 | ||
6635 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6636 | void *val, int bytes) | |
6637 | { | |
e39d200f | 6638 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
6639 | return X86EMUL_IO_NEEDED; |
6640 | } | |
6641 | ||
6642 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6643 | void *val, int bytes) | |
6644 | { | |
f78146b0 AK |
6645 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
6646 | ||
87da7e66 | 6647 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
6648 | return X86EMUL_CONTINUE; |
6649 | } | |
6650 | ||
0fbe9b0b | 6651 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
6652 | .read_write_prepare = read_prepare, |
6653 | .read_write_emulate = read_emulate, | |
6654 | .read_write_mmio = vcpu_mmio_read, | |
6655 | .read_write_exit_mmio = read_exit_mmio, | |
6656 | }; | |
6657 | ||
0fbe9b0b | 6658 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
6659 | .read_write_emulate = write_emulate, |
6660 | .read_write_mmio = write_mmio, | |
6661 | .read_write_exit_mmio = write_exit_mmio, | |
6662 | .write = true, | |
6663 | }; | |
6664 | ||
22388a3c XG |
6665 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
6666 | unsigned int bytes, | |
6667 | struct x86_exception *exception, | |
6668 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 6669 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6670 | { |
af7cc7d1 XG |
6671 | gpa_t gpa; |
6672 | int handled, ret; | |
22388a3c | 6673 | bool write = ops->write; |
f78146b0 | 6674 | struct kvm_mmio_fragment *frag; |
c9b8b07c | 6675 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
0f89b207 TL |
6676 | |
6677 | /* | |
6678 | * If the exit was due to a NPF we may already have a GPA. | |
6679 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
6680 | * Note, this cannot be used on string operations since string | |
6681 | * operation using rep will only have the initial GPA from the NPF | |
6682 | * occurred. | |
6683 | */ | |
744e699c SC |
6684 | if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && |
6685 | (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { | |
6686 | gpa = ctxt->gpa_val; | |
618232e2 BS |
6687 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); |
6688 | } else { | |
6689 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
6690 | if (ret < 0) | |
6691 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 6692 | } |
10589a46 | 6693 | |
618232e2 | 6694 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
6695 | return X86EMUL_CONTINUE; |
6696 | ||
bbd9b64e CO |
6697 | /* |
6698 | * Is this MMIO handled locally? | |
6699 | */ | |
22388a3c | 6700 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 6701 | if (handled == bytes) |
bbd9b64e | 6702 | return X86EMUL_CONTINUE; |
bbd9b64e | 6703 | |
70252a10 AK |
6704 | gpa += handled; |
6705 | bytes -= handled; | |
6706 | val += handled; | |
6707 | ||
87da7e66 XG |
6708 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
6709 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
6710 | frag->gpa = gpa; | |
6711 | frag->data = val; | |
6712 | frag->len = bytes; | |
f78146b0 | 6713 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
6714 | } |
6715 | ||
52eb5a6d XL |
6716 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
6717 | unsigned long addr, | |
22388a3c XG |
6718 | void *val, unsigned int bytes, |
6719 | struct x86_exception *exception, | |
0fbe9b0b | 6720 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6721 | { |
0f65dd70 | 6722 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
6723 | gpa_t gpa; |
6724 | int rc; | |
6725 | ||
6726 | if (ops->read_write_prepare && | |
6727 | ops->read_write_prepare(vcpu, val, bytes)) | |
6728 | return X86EMUL_CONTINUE; | |
6729 | ||
6730 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 6731 | |
bbd9b64e CO |
6732 | /* Crossing a page boundary? */ |
6733 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 6734 | int now; |
bbd9b64e CO |
6735 | |
6736 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
6737 | rc = emulator_read_write_onepage(addr, val, now, exception, |
6738 | vcpu, ops); | |
6739 | ||
bbd9b64e CO |
6740 | if (rc != X86EMUL_CONTINUE) |
6741 | return rc; | |
6742 | addr += now; | |
bac15531 NA |
6743 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6744 | addr = (u32)addr; | |
bbd9b64e CO |
6745 | val += now; |
6746 | bytes -= now; | |
6747 | } | |
22388a3c | 6748 | |
f78146b0 AK |
6749 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
6750 | vcpu, ops); | |
6751 | if (rc != X86EMUL_CONTINUE) | |
6752 | return rc; | |
6753 | ||
6754 | if (!vcpu->mmio_nr_fragments) | |
6755 | return rc; | |
6756 | ||
6757 | gpa = vcpu->mmio_fragments[0].gpa; | |
6758 | ||
6759 | vcpu->mmio_needed = 1; | |
6760 | vcpu->mmio_cur_fragment = 0; | |
6761 | ||
87da7e66 | 6762 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
6763 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
6764 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
6765 | vcpu->run->mmio.phys_addr = gpa; | |
6766 | ||
6767 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
6768 | } |
6769 | ||
6770 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
6771 | unsigned long addr, | |
6772 | void *val, | |
6773 | unsigned int bytes, | |
6774 | struct x86_exception *exception) | |
6775 | { | |
6776 | return emulator_read_write(ctxt, addr, val, bytes, | |
6777 | exception, &read_emultor); | |
6778 | } | |
6779 | ||
52eb5a6d | 6780 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
6781 | unsigned long addr, |
6782 | const void *val, | |
6783 | unsigned int bytes, | |
6784 | struct x86_exception *exception) | |
6785 | { | |
6786 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
6787 | exception, &write_emultor); | |
bbd9b64e | 6788 | } |
bbd9b64e | 6789 | |
daea3e73 AK |
6790 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
6791 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
6792 | ||
6793 | #ifdef CONFIG_X86_64 | |
6794 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
6795 | #else | |
6796 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 6797 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
6798 | #endif |
6799 | ||
0f65dd70 AK |
6800 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
6801 | unsigned long addr, | |
bbd9b64e CO |
6802 | const void *old, |
6803 | const void *new, | |
6804 | unsigned int bytes, | |
0f65dd70 | 6805 | struct x86_exception *exception) |
bbd9b64e | 6806 | { |
42e35f80 | 6807 | struct kvm_host_map map; |
0f65dd70 | 6808 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
9de6fe3c | 6809 | u64 page_line_mask; |
daea3e73 | 6810 | gpa_t gpa; |
daea3e73 AK |
6811 | char *kaddr; |
6812 | bool exchanged; | |
2bacc55c | 6813 | |
daea3e73 AK |
6814 | /* guests cmpxchg8b have to be emulated atomically */ |
6815 | if (bytes > 8 || (bytes & (bytes - 1))) | |
6816 | goto emul_write; | |
10589a46 | 6817 | |
daea3e73 | 6818 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 6819 | |
daea3e73 AK |
6820 | if (gpa == UNMAPPED_GVA || |
6821 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6822 | goto emul_write; | |
2bacc55c | 6823 | |
9de6fe3c XL |
6824 | /* |
6825 | * Emulate the atomic as a straight write to avoid #AC if SLD is | |
6826 | * enabled in the host and the access splits a cache line. | |
6827 | */ | |
6828 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
6829 | page_line_mask = ~(cache_line_size() - 1); | |
6830 | else | |
6831 | page_line_mask = PAGE_MASK; | |
6832 | ||
6833 | if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) | |
daea3e73 | 6834 | goto emul_write; |
72dc67a6 | 6835 | |
42e35f80 | 6836 | if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) |
c19b8bd6 | 6837 | goto emul_write; |
72dc67a6 | 6838 | |
42e35f80 KA |
6839 | kaddr = map.hva + offset_in_page(gpa); |
6840 | ||
daea3e73 AK |
6841 | switch (bytes) { |
6842 | case 1: | |
6843 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
6844 | break; | |
6845 | case 2: | |
6846 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
6847 | break; | |
6848 | case 4: | |
6849 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
6850 | break; | |
6851 | case 8: | |
6852 | exchanged = CMPXCHG64(kaddr, old, new); | |
6853 | break; | |
6854 | default: | |
6855 | BUG(); | |
2bacc55c | 6856 | } |
42e35f80 KA |
6857 | |
6858 | kvm_vcpu_unmap(vcpu, &map, true); | |
daea3e73 AK |
6859 | |
6860 | if (!exchanged) | |
6861 | return X86EMUL_CMPXCHG_FAILED; | |
6862 | ||
0eb05bf2 | 6863 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
6864 | |
6865 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 6866 | |
3200f405 | 6867 | emul_write: |
daea3e73 | 6868 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 6869 | |
0f65dd70 | 6870 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
6871 | } |
6872 | ||
cf8f70bf GN |
6873 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
6874 | { | |
cbfc6c91 | 6875 | int r = 0, i; |
cf8f70bf | 6876 | |
cbfc6c91 WL |
6877 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
6878 | if (vcpu->arch.pio.in) | |
6879 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
6880 | vcpu->arch.pio.size, pd); | |
6881 | else | |
6882 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
6883 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
6884 | pd); | |
6885 | if (r) | |
6886 | break; | |
6887 | pd += vcpu->arch.pio.size; | |
6888 | } | |
cf8f70bf GN |
6889 | return r; |
6890 | } | |
6891 | ||
6f6fbe98 XG |
6892 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
6893 | unsigned short port, void *val, | |
6894 | unsigned int count, bool in) | |
cf8f70bf | 6895 | { |
cf8f70bf | 6896 | vcpu->arch.pio.port = port; |
6f6fbe98 | 6897 | vcpu->arch.pio.in = in; |
7972995b | 6898 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
6899 | vcpu->arch.pio.size = size; |
6900 | ||
6901 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 6902 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6903 | return 1; |
6904 | } | |
6905 | ||
6906 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 6907 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
6908 | vcpu->run->io.size = size; |
6909 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
6910 | vcpu->run->io.count = count; | |
6911 | vcpu->run->io.port = port; | |
6912 | ||
6913 | return 0; | |
6914 | } | |
6915 | ||
2e3bb4d8 SC |
6916 | static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
6917 | unsigned short port, void *val, unsigned int count) | |
cf8f70bf | 6918 | { |
6f6fbe98 | 6919 | int ret; |
ca1d4a9e | 6920 | |
6f6fbe98 XG |
6921 | if (vcpu->arch.pio.count) |
6922 | goto data_avail; | |
cf8f70bf | 6923 | |
cbfc6c91 WL |
6924 | memset(vcpu->arch.pio_data, 0, size * count); |
6925 | ||
6f6fbe98 XG |
6926 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
6927 | if (ret) { | |
6928 | data_avail: | |
6929 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 6930 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 6931 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6932 | return 1; |
6933 | } | |
6934 | ||
cf8f70bf GN |
6935 | return 0; |
6936 | } | |
6937 | ||
2e3bb4d8 SC |
6938 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
6939 | int size, unsigned short port, void *val, | |
6940 | unsigned int count) | |
6f6fbe98 | 6941 | { |
2e3bb4d8 | 6942 | return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); |
6f6fbe98 | 6943 | |
2e3bb4d8 | 6944 | } |
6f6fbe98 | 6945 | |
2e3bb4d8 SC |
6946 | static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, |
6947 | unsigned short port, const void *val, | |
6948 | unsigned int count) | |
6949 | { | |
6f6fbe98 | 6950 | memcpy(vcpu->arch.pio_data, val, size * count); |
1171903d | 6951 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
6952 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
6953 | } | |
6954 | ||
2e3bb4d8 SC |
6955 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
6956 | int size, unsigned short port, | |
6957 | const void *val, unsigned int count) | |
6958 | { | |
6959 | return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); | |
6960 | } | |
6961 | ||
bbd9b64e CO |
6962 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
6963 | { | |
b3646477 | 6964 | return static_call(kvm_x86_get_segment_base)(vcpu, seg); |
bbd9b64e CO |
6965 | } |
6966 | ||
3cb16fe7 | 6967 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 6968 | { |
3cb16fe7 | 6969 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
6970 | } |
6971 | ||
ae6a2375 | 6972 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
6973 | { |
6974 | if (!need_emulate_wbinvd(vcpu)) | |
6975 | return X86EMUL_CONTINUE; | |
6976 | ||
b3646477 | 6977 | if (static_call(kvm_x86_has_wbinvd_exit)()) { |
2eec7343 JK |
6978 | int cpu = get_cpu(); |
6979 | ||
6980 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
c2162e13 | 6981 | on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, |
f5f48ee1 | 6982 | wbinvd_ipi, NULL, 1); |
2eec7343 | 6983 | put_cpu(); |
f5f48ee1 | 6984 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
6985 | } else |
6986 | wbinvd(); | |
f5f48ee1 SY |
6987 | return X86EMUL_CONTINUE; |
6988 | } | |
5cb56059 JS |
6989 | |
6990 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
6991 | { | |
6affcbed KH |
6992 | kvm_emulate_wbinvd_noskip(vcpu); |
6993 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 6994 | } |
f5f48ee1 SY |
6995 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
6996 | ||
5cb56059 JS |
6997 | |
6998 | ||
bcaf5cc5 AK |
6999 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
7000 | { | |
5cb56059 | 7001 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
7002 | } |
7003 | ||
29d6ca41 PB |
7004 | static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
7005 | unsigned long *dest) | |
bbd9b64e | 7006 | { |
29d6ca41 | 7007 | kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
7008 | } |
7009 | ||
52eb5a6d XL |
7010 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
7011 | unsigned long value) | |
bbd9b64e | 7012 | { |
338dbc97 | 7013 | |
996ff542 | 7014 | return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
7015 | } |
7016 | ||
52a46617 | 7017 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 7018 | { |
52a46617 | 7019 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
7020 | } |
7021 | ||
717746e3 | 7022 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 7023 | { |
717746e3 | 7024 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
7025 | unsigned long value; |
7026 | ||
7027 | switch (cr) { | |
7028 | case 0: | |
7029 | value = kvm_read_cr0(vcpu); | |
7030 | break; | |
7031 | case 2: | |
7032 | value = vcpu->arch.cr2; | |
7033 | break; | |
7034 | case 3: | |
9f8fe504 | 7035 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
7036 | break; |
7037 | case 4: | |
7038 | value = kvm_read_cr4(vcpu); | |
7039 | break; | |
7040 | case 8: | |
7041 | value = kvm_get_cr8(vcpu); | |
7042 | break; | |
7043 | default: | |
a737f256 | 7044 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
7045 | return 0; |
7046 | } | |
7047 | ||
7048 | return value; | |
7049 | } | |
7050 | ||
717746e3 | 7051 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 7052 | { |
717746e3 | 7053 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
7054 | int res = 0; |
7055 | ||
52a46617 GN |
7056 | switch (cr) { |
7057 | case 0: | |
49a9b07e | 7058 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
7059 | break; |
7060 | case 2: | |
7061 | vcpu->arch.cr2 = val; | |
7062 | break; | |
7063 | case 3: | |
2390218b | 7064 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
7065 | break; |
7066 | case 4: | |
a83b29c6 | 7067 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
7068 | break; |
7069 | case 8: | |
eea1cff9 | 7070 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
7071 | break; |
7072 | default: | |
a737f256 | 7073 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 7074 | res = -1; |
52a46617 | 7075 | } |
0f12244f GN |
7076 | |
7077 | return res; | |
52a46617 GN |
7078 | } |
7079 | ||
717746e3 | 7080 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 7081 | { |
b3646477 | 7082 | return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); |
9c537244 GN |
7083 | } |
7084 | ||
4bff1e86 | 7085 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 7086 | { |
b3646477 | 7087 | static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
7088 | } |
7089 | ||
4bff1e86 | 7090 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 7091 | { |
b3646477 | 7092 | static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
7093 | } |
7094 | ||
1ac9d0cf AK |
7095 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
7096 | { | |
b3646477 | 7097 | static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
7098 | } |
7099 | ||
7100 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
7101 | { | |
b3646477 | 7102 | static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
7103 | } |
7104 | ||
4bff1e86 AK |
7105 | static unsigned long emulator_get_cached_segment_base( |
7106 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 7107 | { |
4bff1e86 | 7108 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
7109 | } |
7110 | ||
1aa36616 AK |
7111 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
7112 | struct desc_struct *desc, u32 *base3, | |
7113 | int seg) | |
2dafc6c2 GN |
7114 | { |
7115 | struct kvm_segment var; | |
7116 | ||
4bff1e86 | 7117 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 7118 | *selector = var.selector; |
2dafc6c2 | 7119 | |
378a8b09 GN |
7120 | if (var.unusable) { |
7121 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
7122 | if (base3) |
7123 | *base3 = 0; | |
2dafc6c2 | 7124 | return false; |
378a8b09 | 7125 | } |
2dafc6c2 GN |
7126 | |
7127 | if (var.g) | |
7128 | var.limit >>= 12; | |
7129 | set_desc_limit(desc, var.limit); | |
7130 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
7131 | #ifdef CONFIG_X86_64 |
7132 | if (base3) | |
7133 | *base3 = var.base >> 32; | |
7134 | #endif | |
2dafc6c2 GN |
7135 | desc->type = var.type; |
7136 | desc->s = var.s; | |
7137 | desc->dpl = var.dpl; | |
7138 | desc->p = var.present; | |
7139 | desc->avl = var.avl; | |
7140 | desc->l = var.l; | |
7141 | desc->d = var.db; | |
7142 | desc->g = var.g; | |
7143 | ||
7144 | return true; | |
7145 | } | |
7146 | ||
1aa36616 AK |
7147 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
7148 | struct desc_struct *desc, u32 base3, | |
7149 | int seg) | |
2dafc6c2 | 7150 | { |
4bff1e86 | 7151 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
7152 | struct kvm_segment var; |
7153 | ||
1aa36616 | 7154 | var.selector = selector; |
2dafc6c2 | 7155 | var.base = get_desc_base(desc); |
5601d05b GN |
7156 | #ifdef CONFIG_X86_64 |
7157 | var.base |= ((u64)base3) << 32; | |
7158 | #endif | |
2dafc6c2 GN |
7159 | var.limit = get_desc_limit(desc); |
7160 | if (desc->g) | |
7161 | var.limit = (var.limit << 12) | 0xfff; | |
7162 | var.type = desc->type; | |
2dafc6c2 GN |
7163 | var.dpl = desc->dpl; |
7164 | var.db = desc->d; | |
7165 | var.s = desc->s; | |
7166 | var.l = desc->l; | |
7167 | var.g = desc->g; | |
7168 | var.avl = desc->avl; | |
7169 | var.present = desc->p; | |
7170 | var.unusable = !var.present; | |
7171 | var.padding = 0; | |
7172 | ||
7173 | kvm_set_segment(vcpu, &var, seg); | |
7174 | return; | |
7175 | } | |
7176 | ||
717746e3 AK |
7177 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
7178 | u32 msr_index, u64 *pdata) | |
7179 | { | |
1ae09954 AG |
7180 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7181 | int r; | |
7182 | ||
7183 | r = kvm_get_msr(vcpu, msr_index, pdata); | |
7184 | ||
7185 | if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { | |
7186 | /* Bounce to user space */ | |
7187 | return X86EMUL_IO_NEEDED; | |
7188 | } | |
7189 | ||
7190 | return r; | |
717746e3 AK |
7191 | } |
7192 | ||
7193 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
7194 | u32 msr_index, u64 data) | |
7195 | { | |
1ae09954 AG |
7196 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7197 | int r; | |
7198 | ||
7199 | r = kvm_set_msr(vcpu, msr_index, data); | |
7200 | ||
7201 | if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { | |
7202 | /* Bounce to user space */ | |
7203 | return X86EMUL_IO_NEEDED; | |
7204 | } | |
7205 | ||
7206 | return r; | |
717746e3 AK |
7207 | } |
7208 | ||
64d60670 PB |
7209 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
7210 | { | |
7211 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7212 | ||
7213 | return vcpu->arch.smbase; | |
7214 | } | |
7215 | ||
7216 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
7217 | { | |
7218 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7219 | ||
7220 | vcpu->arch.smbase = smbase; | |
7221 | } | |
7222 | ||
67f4d428 NA |
7223 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
7224 | u32 pmc) | |
7225 | { | |
98ff80f5 | 7226 | return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
7227 | } |
7228 | ||
222d21aa AK |
7229 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
7230 | u32 pmc, u64 *pdata) | |
7231 | { | |
c6702c9d | 7232 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
7233 | } |
7234 | ||
6c3287f7 AK |
7235 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
7236 | { | |
7237 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
7238 | } | |
7239 | ||
2953538e | 7240 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 7241 | struct x86_instruction_info *info, |
c4f035c6 AK |
7242 | enum x86_intercept_stage stage) |
7243 | { | |
b3646477 | 7244 | return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, |
21f1b8f2 | 7245 | &ctxt->exception); |
c4f035c6 AK |
7246 | } |
7247 | ||
e911eb3b | 7248 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
f91af517 SC |
7249 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, |
7250 | bool exact_only) | |
bdb42f5a | 7251 | { |
f91af517 | 7252 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); |
bdb42f5a SB |
7253 | } |
7254 | ||
5ae78e95 SC |
7255 | static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) |
7256 | { | |
7257 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); | |
7258 | } | |
7259 | ||
7260 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) | |
7261 | { | |
7262 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
7263 | } | |
7264 | ||
7265 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
7266 | { | |
7267 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
7268 | } | |
7269 | ||
dd856efa AK |
7270 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
7271 | { | |
27b4a9c4 | 7272 | return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); |
dd856efa AK |
7273 | } |
7274 | ||
7275 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
7276 | { | |
27b4a9c4 | 7277 | kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); |
dd856efa AK |
7278 | } |
7279 | ||
801806d9 NA |
7280 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
7281 | { | |
b3646477 | 7282 | static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); |
801806d9 NA |
7283 | } |
7284 | ||
6ed071f0 LP |
7285 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
7286 | { | |
7287 | return emul_to_vcpu(ctxt)->arch.hflags; | |
7288 | } | |
7289 | ||
edce4654 | 7290 | static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) |
6ed071f0 | 7291 | { |
78fcb2c9 SC |
7292 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7293 | ||
dc87275f | 7294 | kvm_smm_changed(vcpu, false); |
6ed071f0 LP |
7295 | } |
7296 | ||
ecc513e5 | 7297 | static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, |
ed19321f | 7298 | const char *smstate) |
0234bf88 | 7299 | { |
ecc513e5 | 7300 | return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
7301 | } |
7302 | ||
25b17226 SC |
7303 | static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) |
7304 | { | |
7305 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); | |
7306 | } | |
7307 | ||
02d4160f VK |
7308 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
7309 | { | |
7310 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
7311 | } | |
7312 | ||
0225fb50 | 7313 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
7314 | .read_gpr = emulator_read_gpr, |
7315 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
7316 | .read_std = emulator_read_std, |
7317 | .write_std = emulator_write_std, | |
7a036a6f | 7318 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 7319 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
7320 | .read_emulated = emulator_read_emulated, |
7321 | .write_emulated = emulator_write_emulated, | |
7322 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 7323 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
7324 | .pio_in_emulated = emulator_pio_in_emulated, |
7325 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
7326 | .get_segment = emulator_get_segment, |
7327 | .set_segment = emulator_set_segment, | |
5951c442 | 7328 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 7329 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 7330 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
7331 | .set_gdt = emulator_set_gdt, |
7332 | .set_idt = emulator_set_idt, | |
52a46617 GN |
7333 | .get_cr = emulator_get_cr, |
7334 | .set_cr = emulator_set_cr, | |
9c537244 | 7335 | .cpl = emulator_get_cpl, |
35aa5375 GN |
7336 | .get_dr = emulator_get_dr, |
7337 | .set_dr = emulator_set_dr, | |
64d60670 PB |
7338 | .get_smbase = emulator_get_smbase, |
7339 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
7340 | .set_msr = emulator_set_msr, |
7341 | .get_msr = emulator_get_msr, | |
67f4d428 | 7342 | .check_pmc = emulator_check_pmc, |
222d21aa | 7343 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 7344 | .halt = emulator_halt, |
bcaf5cc5 | 7345 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 7346 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 7347 | .intercept = emulator_intercept, |
bdb42f5a | 7348 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
7349 | .guest_has_long_mode = emulator_guest_has_long_mode, |
7350 | .guest_has_movbe = emulator_guest_has_movbe, | |
7351 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
801806d9 | 7352 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 | 7353 | .get_hflags = emulator_get_hflags, |
edce4654 | 7354 | .exiting_smm = emulator_exiting_smm, |
ecc513e5 | 7355 | .leave_smm = emulator_leave_smm, |
25b17226 | 7356 | .triple_fault = emulator_triple_fault, |
02d4160f | 7357 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
7358 | }; |
7359 | ||
95cb2295 GN |
7360 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
7361 | { | |
b3646477 | 7362 | u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
95cb2295 GN |
7363 | /* |
7364 | * an sti; sti; sequence only disable interrupts for the first | |
7365 | * instruction. So, if the last instruction, be it emulated or | |
7366 | * not, left the system with the INT_STI flag enabled, it | |
7367 | * means that the last instruction is an sti. We should not | |
7368 | * leave the flag on in this case. The same goes for mov ss | |
7369 | */ | |
37ccdcbe PB |
7370 | if (int_shadow & mask) |
7371 | mask = 0; | |
6addfc42 | 7372 | if (unlikely(int_shadow || mask)) { |
b3646477 | 7373 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); |
6addfc42 PB |
7374 | if (!mask) |
7375 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7376 | } | |
95cb2295 GN |
7377 | } |
7378 | ||
ef54bcfe | 7379 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f | 7380 | { |
c9b8b07c | 7381 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
da9cb575 | 7382 | if (ctxt->exception.vector == PF_VECTOR) |
53b3d8e9 | 7383 | return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); |
ef54bcfe PB |
7384 | |
7385 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
7386 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
7387 | ctxt->exception.error_code); | |
54b8486f | 7388 | else |
da9cb575 | 7389 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 7390 | return false; |
54b8486f GN |
7391 | } |
7392 | ||
c9b8b07c SC |
7393 | static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) |
7394 | { | |
7395 | struct x86_emulate_ctxt *ctxt; | |
7396 | ||
7397 | ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); | |
7398 | if (!ctxt) { | |
7399 | pr_err("kvm: failed to allocate vcpu's emulator\n"); | |
7400 | return NULL; | |
7401 | } | |
7402 | ||
7403 | ctxt->vcpu = vcpu; | |
7404 | ctxt->ops = &emulate_ops; | |
7405 | vcpu->arch.emulate_ctxt = ctxt; | |
7406 | ||
7407 | return ctxt; | |
7408 | } | |
7409 | ||
8ec4722d MG |
7410 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
7411 | { | |
c9b8b07c | 7412 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d MG |
7413 | int cs_db, cs_l; |
7414 | ||
b3646477 | 7415 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
8ec4722d | 7416 | |
744e699c | 7417 | ctxt->gpa_available = false; |
adf52235 | 7418 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
7419 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
7420 | ||
adf52235 TY |
7421 | ctxt->eip = kvm_rip_read(vcpu); |
7422 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
7423 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 7424 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
7425 | cs_db ? X86EMUL_MODE_PROT32 : |
7426 | X86EMUL_MODE_PROT16; | |
a584539b | 7427 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
7428 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
7429 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 7430 | |
da6393cd WL |
7431 | ctxt->interruptibility = 0; |
7432 | ctxt->have_exception = false; | |
7433 | ctxt->exception.vector = -1; | |
7434 | ctxt->perm_ok = false; | |
7435 | ||
dd856efa | 7436 | init_decode_cache(ctxt); |
7ae441ea | 7437 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
7438 | } |
7439 | ||
9497e1f2 | 7440 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 7441 | { |
c9b8b07c | 7442 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
63995653 MG |
7443 | int ret; |
7444 | ||
7445 | init_emulate_ctxt(vcpu); | |
7446 | ||
9dac77fa AK |
7447 | ctxt->op_bytes = 2; |
7448 | ctxt->ad_bytes = 2; | |
7449 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 7450 | ret = emulate_int_real(ctxt, irq); |
63995653 | 7451 | |
9497e1f2 SC |
7452 | if (ret != X86EMUL_CONTINUE) { |
7453 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
7454 | } else { | |
7455 | ctxt->eip = ctxt->_eip; | |
7456 | kvm_rip_write(vcpu, ctxt->eip); | |
7457 | kvm_set_rflags(vcpu, ctxt->eflags); | |
7458 | } | |
63995653 MG |
7459 | } |
7460 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
7461 | ||
19238e75 AL |
7462 | static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) |
7463 | { | |
7464 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; | |
7465 | u32 insn_size = ctxt->fetch.end - ctxt->fetch.data; | |
7466 | struct kvm_run *run = vcpu->run; | |
7467 | ||
7468 | run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7469 | run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7470 | run->emulation_failure.ndata = 0; | |
7471 | run->emulation_failure.flags = 0; | |
7472 | ||
7473 | if (insn_size) { | |
7474 | run->emulation_failure.ndata = 3; | |
7475 | run->emulation_failure.flags |= | |
7476 | KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; | |
7477 | run->emulation_failure.insn_size = insn_size; | |
7478 | memset(run->emulation_failure.insn_bytes, 0x90, | |
7479 | sizeof(run->emulation_failure.insn_bytes)); | |
7480 | memcpy(run->emulation_failure.insn_bytes, | |
7481 | ctxt->fetch.data, insn_size); | |
7482 | } | |
7483 | } | |
7484 | ||
e2366171 | 7485 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 7486 | { |
19238e75 AL |
7487 | struct kvm *kvm = vcpu->kvm; |
7488 | ||
6d77dbfc GN |
7489 | ++vcpu->stat.insn_emulation_fail; |
7490 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 7491 | |
42cbf068 SC |
7492 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
7493 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7494 | return 1; |
42cbf068 | 7495 | } |
e2366171 | 7496 | |
19238e75 AL |
7497 | if (kvm->arch.exit_on_emulation_error || |
7498 | (emulation_type & EMULTYPE_SKIP)) { | |
7499 | prepare_emulation_failure_exit(vcpu); | |
60fc3d02 | 7500 | return 0; |
738fece4 SC |
7501 | } |
7502 | ||
22da61c9 SC |
7503 | kvm_queue_exception(vcpu, UD_VECTOR); |
7504 | ||
b3646477 | 7505 | if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { |
fc3a9157 JR |
7506 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
7507 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7508 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7509 | return 0; |
fc3a9157 | 7510 | } |
e2366171 | 7511 | |
60fc3d02 | 7512 | return 1; |
6d77dbfc GN |
7513 | } |
7514 | ||
736c291c | 7515 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 GN |
7516 | bool write_fault_to_shadow_pgtable, |
7517 | int emulation_type) | |
a6f177ef | 7518 | { |
736c291c | 7519 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 7520 | kvm_pfn_t pfn; |
a6f177ef | 7521 | |
92daa48b | 7522 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
991eebf9 GN |
7523 | return false; |
7524 | ||
92daa48b SC |
7525 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7526 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7527 | return false; |
7528 | ||
44dd3ffa | 7529 | if (!vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7530 | /* |
7531 | * Write permission should be allowed since only | |
7532 | * write access need to be emulated. | |
7533 | */ | |
736c291c | 7534 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 7535 | |
95b3cf69 XG |
7536 | /* |
7537 | * If the mapping is invalid in guest, let cpu retry | |
7538 | * it to generate fault. | |
7539 | */ | |
7540 | if (gpa == UNMAPPED_GVA) | |
7541 | return true; | |
7542 | } | |
a6f177ef | 7543 | |
8e3d9d06 XG |
7544 | /* |
7545 | * Do not retry the unhandleable instruction if it faults on the | |
7546 | * readonly host memory, otherwise it will goto a infinite loop: | |
7547 | * retry instruction -> write #PF -> emulation fail -> retry | |
7548 | * instruction -> ... | |
7549 | */ | |
7550 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
7551 | |
7552 | /* | |
7553 | * If the instruction failed on the error pfn, it can not be fixed, | |
7554 | * report the error to userspace. | |
7555 | */ | |
7556 | if (is_error_noslot_pfn(pfn)) | |
7557 | return false; | |
7558 | ||
7559 | kvm_release_pfn_clean(pfn); | |
7560 | ||
7561 | /* The instructions are well-emulated on direct mmu. */ | |
44dd3ffa | 7562 | if (vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7563 | unsigned int indirect_shadow_pages; |
7564 | ||
531810ca | 7565 | write_lock(&vcpu->kvm->mmu_lock); |
95b3cf69 | 7566 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; |
531810ca | 7567 | write_unlock(&vcpu->kvm->mmu_lock); |
95b3cf69 XG |
7568 | |
7569 | if (indirect_shadow_pages) | |
7570 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
7571 | ||
a6f177ef | 7572 | return true; |
8e3d9d06 | 7573 | } |
a6f177ef | 7574 | |
95b3cf69 XG |
7575 | /* |
7576 | * if emulation was due to access to shadowed page table | |
7577 | * and it failed try to unshadow page and re-enter the | |
7578 | * guest to let CPU execute the instruction. | |
7579 | */ | |
7580 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
7581 | |
7582 | /* | |
7583 | * If the access faults on its page table, it can not | |
7584 | * be fixed by unprotecting shadow page and it should | |
7585 | * be reported to userspace. | |
7586 | */ | |
7587 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
7588 | } |
7589 | ||
1cb3f3ae | 7590 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 7591 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
7592 | { |
7593 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 7594 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
7595 | |
7596 | last_retry_eip = vcpu->arch.last_retry_eip; | |
7597 | last_retry_addr = vcpu->arch.last_retry_addr; | |
7598 | ||
7599 | /* | |
7600 | * If the emulation is caused by #PF and it is non-page_table | |
7601 | * writing instruction, it means the VM-EXIT is caused by shadow | |
7602 | * page protected, we can zap the shadow page and retry this | |
7603 | * instruction directly. | |
7604 | * | |
7605 | * Note: if the guest uses a non-page-table modifying instruction | |
7606 | * on the PDE that points to the instruction, then we will unmap | |
7607 | * the instruction and go to an infinite loop. So, we cache the | |
7608 | * last retried eip and the last fault address, if we meet the eip | |
7609 | * and the address again, we can break out of the potential infinite | |
7610 | * loop. | |
7611 | */ | |
7612 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
7613 | ||
92daa48b | 7614 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
1cb3f3ae XG |
7615 | return false; |
7616 | ||
92daa48b SC |
7617 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7618 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7619 | return false; |
7620 | ||
1cb3f3ae XG |
7621 | if (x86_page_table_writing_insn(ctxt)) |
7622 | return false; | |
7623 | ||
736c291c | 7624 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
7625 | return false; |
7626 | ||
7627 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 7628 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 7629 | |
44dd3ffa | 7630 | if (!vcpu->arch.mmu->direct_map) |
736c291c | 7631 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 7632 | |
22368028 | 7633 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
7634 | |
7635 | return true; | |
7636 | } | |
7637 | ||
716d51ab GN |
7638 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
7639 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
7640 | ||
dc87275f | 7641 | static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) |
a584539b | 7642 | { |
1270e647 | 7643 | trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); |
0d7ee6f4 | 7644 | |
dc87275f SC |
7645 | if (entering_smm) { |
7646 | vcpu->arch.hflags |= HF_SMM_MASK; | |
7647 | } else { | |
7648 | vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); | |
7649 | ||
c43203ca PB |
7650 | /* Process a latched INIT or SMI, if any. */ |
7651 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 | 7652 | } |
699023e2 PB |
7653 | |
7654 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
7655 | } |
7656 | ||
4a1e10d5 PB |
7657 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
7658 | unsigned long *db) | |
7659 | { | |
7660 | u32 dr6 = 0; | |
7661 | int i; | |
7662 | u32 enable, rwlen; | |
7663 | ||
7664 | enable = dr7; | |
7665 | rwlen = dr7 >> 16; | |
7666 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
7667 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
7668 | dr6 |= (1 << i); | |
7669 | return dr6; | |
7670 | } | |
7671 | ||
120c2c4f | 7672 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
7673 | { |
7674 | struct kvm_run *kvm_run = vcpu->run; | |
7675 | ||
c8401dda | 7676 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
9a3ecd5e | 7677 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; |
d5d260c5 | 7678 | kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
c8401dda PB |
7679 | kvm_run->debug.arch.exception = DB_VECTOR; |
7680 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7681 | return 0; |
663f4c61 | 7682 | } |
120c2c4f | 7683 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 7684 | return 1; |
663f4c61 PB |
7685 | } |
7686 | ||
6affcbed KH |
7687 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
7688 | { | |
b3646477 | 7689 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
f8ea7c60 | 7690 | int r; |
6affcbed | 7691 | |
b3646477 | 7692 | r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); |
60fc3d02 | 7693 | if (unlikely(!r)) |
f8ea7c60 | 7694 | return 0; |
c8401dda PB |
7695 | |
7696 | /* | |
7697 | * rflags is the old, "raw" value of the flags. The new value has | |
7698 | * not been saved yet. | |
7699 | * | |
7700 | * This is correct even for TF set by the guest, because "the | |
7701 | * processor will not generate this exception after the instruction | |
7702 | * that sets the TF flag". | |
7703 | */ | |
7704 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 7705 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 7706 | return r; |
6affcbed KH |
7707 | } |
7708 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
7709 | ||
4a1e10d5 PB |
7710 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
7711 | { | |
4a1e10d5 PB |
7712 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
7713 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
7714 | struct kvm_run *kvm_run = vcpu->run; |
7715 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
7716 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7717 | vcpu->arch.guest_debug_dr7, |
7718 | vcpu->arch.eff_db); | |
7719 | ||
7720 | if (dr6 != 0) { | |
9a3ecd5e | 7721 | kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; |
82b32774 | 7722 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
7723 | kvm_run->debug.arch.exception = DB_VECTOR; |
7724 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7725 | *r = 0; |
4a1e10d5 PB |
7726 | return true; |
7727 | } | |
7728 | } | |
7729 | ||
4161a569 NA |
7730 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
7731 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
7732 | unsigned long eip = kvm_get_linear_rip(vcpu); |
7733 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7734 | vcpu->arch.dr7, |
7735 | vcpu->arch.db); | |
7736 | ||
7737 | if (dr6 != 0) { | |
4d5523cf | 7738 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
60fc3d02 | 7739 | *r = 1; |
4a1e10d5 PB |
7740 | return true; |
7741 | } | |
7742 | } | |
7743 | ||
7744 | return false; | |
7745 | } | |
7746 | ||
04789b66 LA |
7747 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
7748 | { | |
2d7921c4 AM |
7749 | switch (ctxt->opcode_len) { |
7750 | case 1: | |
7751 | switch (ctxt->b) { | |
7752 | case 0xe4: /* IN */ | |
7753 | case 0xe5: | |
7754 | case 0xec: | |
7755 | case 0xed: | |
7756 | case 0xe6: /* OUT */ | |
7757 | case 0xe7: | |
7758 | case 0xee: | |
7759 | case 0xef: | |
7760 | case 0x6c: /* INS */ | |
7761 | case 0x6d: | |
7762 | case 0x6e: /* OUTS */ | |
7763 | case 0x6f: | |
7764 | return true; | |
7765 | } | |
7766 | break; | |
7767 | case 2: | |
7768 | switch (ctxt->b) { | |
7769 | case 0x33: /* RDPMC */ | |
7770 | return true; | |
7771 | } | |
7772 | break; | |
04789b66 LA |
7773 | } |
7774 | ||
7775 | return false; | |
7776 | } | |
7777 | ||
4aa2691d WH |
7778 | /* |
7779 | * Decode to be emulated instruction. Return EMULATION_OK if success. | |
7780 | */ | |
7781 | int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, | |
7782 | void *insn, int insn_len) | |
7783 | { | |
7784 | int r = EMULATION_OK; | |
7785 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; | |
7786 | ||
7787 | init_emulate_ctxt(vcpu); | |
7788 | ||
7789 | /* | |
7790 | * We will reenter on the same instruction since we do not set | |
7791 | * complete_userspace_io. This does not handle watchpoints yet, | |
7792 | * those would be handled in the emulate_ops. | |
7793 | */ | |
7794 | if (!(emulation_type & EMULTYPE_SKIP) && | |
7795 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
7796 | return r; | |
7797 | ||
b35491e6 | 7798 | r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); |
4aa2691d WH |
7799 | |
7800 | trace_kvm_emulate_insn_start(vcpu); | |
7801 | ++vcpu->stat.insn_emulation; | |
7802 | ||
7803 | return r; | |
7804 | } | |
7805 | EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); | |
7806 | ||
736c291c SC |
7807 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
7808 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 7809 | { |
95cb2295 | 7810 | int r; |
c9b8b07c | 7811 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
7ae441ea | 7812 | bool writeback = true; |
09e3e2a1 SC |
7813 | bool write_fault_to_spt; |
7814 | ||
b3646477 | 7815 | if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) |
09e3e2a1 | 7816 | return 1; |
bbd9b64e | 7817 | |
c595ceee PB |
7818 | vcpu->arch.l1tf_flush_l1d = true; |
7819 | ||
93c05d3e XG |
7820 | /* |
7821 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
7822 | * never reused. | |
7823 | */ | |
09e3e2a1 | 7824 | write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
93c05d3e | 7825 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
8d7d8102 | 7826 | |
571008da | 7827 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
4aa2691d | 7828 | kvm_clear_exception_queue(vcpu); |
4a1e10d5 | 7829 | |
4aa2691d WH |
7830 | r = x86_decode_emulated_instruction(vcpu, emulation_type, |
7831 | insn, insn_len); | |
1d2887e2 | 7832 | if (r != EMULATION_OK) { |
b4000606 | 7833 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
7834 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
7835 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 7836 | return 1; |
c83fad65 | 7837 | } |
736c291c SC |
7838 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
7839 | write_fault_to_spt, | |
7840 | emulation_type)) | |
60fc3d02 | 7841 | return 1; |
8530a79c | 7842 | if (ctxt->have_exception) { |
c8848cee JD |
7843 | /* |
7844 | * #UD should result in just EMULATION_FAILED, and trap-like | |
7845 | * exception should not be encountered during decode. | |
7846 | */ | |
7847 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
7848 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 7849 | inject_emulated_exception(vcpu); |
60fc3d02 | 7850 | return 1; |
8530a79c | 7851 | } |
e2366171 | 7852 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7853 | } |
7854 | } | |
7855 | ||
42cbf068 SC |
7856 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
7857 | !is_vmware_backdoor_opcode(ctxt)) { | |
7858 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7859 | return 1; |
42cbf068 | 7860 | } |
04789b66 | 7861 | |
1957aa63 SC |
7862 | /* |
7863 | * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks | |
7864 | * for kvm_skip_emulated_instruction(). The caller is responsible for | |
7865 | * updating interruptibility state and injecting single-step #DBs. | |
7866 | */ | |
ba8afb6b | 7867 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 7868 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
7869 | if (ctxt->eflags & X86_EFLAGS_RF) |
7870 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 7871 | return 1; |
ba8afb6b GN |
7872 | } |
7873 | ||
736c291c | 7874 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 7875 | return 1; |
1cb3f3ae | 7876 | |
7ae441ea | 7877 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 7878 | changes registers values during IO operation */ |
7ae441ea GN |
7879 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
7880 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 7881 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 7882 | } |
4d2179e1 | 7883 | |
5cd21917 | 7884 | restart: |
92daa48b SC |
7885 | if (emulation_type & EMULTYPE_PF) { |
7886 | /* Save the faulting GPA (cr2) in the address field */ | |
7887 | ctxt->exception.address = cr2_or_gpa; | |
7888 | ||
7889 | /* With shadow page tables, cr2 contains a GVA or nGPA. */ | |
7890 | if (vcpu->arch.mmu->direct_map) { | |
744e699c SC |
7891 | ctxt->gpa_available = true; |
7892 | ctxt->gpa_val = cr2_or_gpa; | |
92daa48b SC |
7893 | } |
7894 | } else { | |
7895 | /* Sanitize the address out of an abundance of paranoia. */ | |
7896 | ctxt->exception.address = 0; | |
7897 | } | |
0f89b207 | 7898 | |
9d74191a | 7899 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 7900 | |
775fde86 | 7901 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 7902 | return 1; |
775fde86 | 7903 | |
d2ddd1c4 | 7904 | if (r == EMULATION_FAILED) { |
736c291c | 7905 | if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, |
991eebf9 | 7906 | emulation_type)) |
60fc3d02 | 7907 | return 1; |
c3cd7ffa | 7908 | |
e2366171 | 7909 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7910 | } |
7911 | ||
9d74191a | 7912 | if (ctxt->have_exception) { |
60fc3d02 | 7913 | r = 1; |
ef54bcfe PB |
7914 | if (inject_emulated_exception(vcpu)) |
7915 | return r; | |
d2ddd1c4 | 7916 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
7917 | if (!vcpu->arch.pio.in) { |
7918 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 7919 | vcpu->arch.pio.count = 0; |
0912c977 | 7920 | } else { |
7ae441ea | 7921 | writeback = false; |
716d51ab GN |
7922 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
7923 | } | |
60fc3d02 | 7924 | r = 0; |
7ae441ea | 7925 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
7926 | ++vcpu->stat.mmio_exits; |
7927 | ||
7ae441ea GN |
7928 | if (!vcpu->mmio_is_write) |
7929 | writeback = false; | |
60fc3d02 | 7930 | r = 0; |
716d51ab | 7931 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 7932 | } else if (r == EMULATION_RESTART) |
5cd21917 | 7933 | goto restart; |
d2ddd1c4 | 7934 | else |
60fc3d02 | 7935 | r = 1; |
f850e2e6 | 7936 | |
7ae441ea | 7937 | if (writeback) { |
b3646477 | 7938 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
9d74191a | 7939 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 7940 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
38827dbd | 7941 | if (!ctxt->have_exception || |
75ee23b3 SC |
7942 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
7943 | kvm_rip_write(vcpu, ctxt->eip); | |
384dea1c | 7944 | if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) |
120c2c4f | 7945 | r = kvm_vcpu_do_singlestep(vcpu); |
afaf0b2f | 7946 | if (kvm_x86_ops.update_emulated_instruction) |
b3646477 | 7947 | static_call(kvm_x86_update_emulated_instruction)(vcpu); |
38827dbd | 7948 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 7949 | } |
6addfc42 PB |
7950 | |
7951 | /* | |
7952 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
7953 | * do nothing, and it will be requested again as soon as | |
7954 | * the shadow expires. But we still need to check here, | |
7955 | * because POPF has no interrupt shadow. | |
7956 | */ | |
7957 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
7958 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
7959 | } else |
7960 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
7961 | |
7962 | return r; | |
de7d789a | 7963 | } |
c60658d1 SC |
7964 | |
7965 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
7966 | { | |
7967 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
7968 | } | |
7969 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
7970 | ||
7971 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
7972 | void *insn, int insn_len) | |
7973 | { | |
7974 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
7975 | } | |
7976 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 7977 | |
8764ed55 SC |
7978 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
7979 | { | |
7980 | vcpu->arch.pio.count = 0; | |
7981 | return 1; | |
7982 | } | |
7983 | ||
45def77e SC |
7984 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
7985 | { | |
7986 | vcpu->arch.pio.count = 0; | |
7987 | ||
7988 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
7989 | return 1; | |
7990 | ||
7991 | return kvm_skip_emulated_instruction(vcpu); | |
7992 | } | |
7993 | ||
dca7f128 SC |
7994 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
7995 | unsigned short port) | |
de7d789a | 7996 | { |
de3cd117 | 7997 | unsigned long val = kvm_rax_read(vcpu); |
2e3bb4d8 SC |
7998 | int ret = emulator_pio_out(vcpu, size, port, &val, 1); |
7999 | ||
8764ed55 SC |
8000 | if (ret) |
8001 | return ret; | |
45def77e | 8002 | |
8764ed55 SC |
8003 | /* |
8004 | * Workaround userspace that relies on old KVM behavior of %rip being | |
8005 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
8006 | */ | |
8007 | if (port == 0x7e && | |
8008 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
8009 | vcpu->arch.complete_userspace_io = | |
8010 | complete_fast_pio_out_port_0x7e; | |
8011 | kvm_skip_emulated_instruction(vcpu); | |
8012 | } else { | |
45def77e SC |
8013 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8014 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
8015 | } | |
8764ed55 | 8016 | return 0; |
de7d789a | 8017 | } |
de7d789a | 8018 | |
8370c3d0 TL |
8019 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
8020 | { | |
8021 | unsigned long val; | |
8022 | ||
8023 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
8024 | BUG_ON(vcpu->arch.pio.count != 1); | |
8025 | ||
45def77e SC |
8026 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
8027 | vcpu->arch.pio.count = 0; | |
8028 | return 1; | |
8029 | } | |
8030 | ||
8370c3d0 | 8031 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 8032 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
8033 | |
8034 | /* | |
2e3bb4d8 | 8035 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform |
8370c3d0 TL |
8036 | * the copy and tracing |
8037 | */ | |
2e3bb4d8 | 8038 | emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); |
de3cd117 | 8039 | kvm_rax_write(vcpu, val); |
8370c3d0 | 8040 | |
45def77e | 8041 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
8042 | } |
8043 | ||
dca7f128 SC |
8044 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
8045 | unsigned short port) | |
8370c3d0 TL |
8046 | { |
8047 | unsigned long val; | |
8048 | int ret; | |
8049 | ||
8050 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 8051 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 8052 | |
2e3bb4d8 | 8053 | ret = emulator_pio_in(vcpu, size, port, &val, 1); |
8370c3d0 | 8054 | if (ret) { |
de3cd117 | 8055 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
8056 | return ret; |
8057 | } | |
8058 | ||
45def77e | 8059 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
8060 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
8061 | ||
8062 | return 0; | |
8063 | } | |
dca7f128 SC |
8064 | |
8065 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
8066 | { | |
45def77e | 8067 | int ret; |
dca7f128 | 8068 | |
dca7f128 | 8069 | if (in) |
45def77e | 8070 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 8071 | else |
45def77e SC |
8072 | ret = kvm_fast_pio_out(vcpu, size, port); |
8073 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
8074 | } |
8075 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 8076 | |
251a5fd6 | 8077 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 8078 | { |
0a3aee0d | 8079 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 8080 | return 0; |
8cfdc000 ZA |
8081 | } |
8082 | ||
8083 | static void tsc_khz_changed(void *data) | |
c8076604 | 8084 | { |
8cfdc000 ZA |
8085 | struct cpufreq_freqs *freq = data; |
8086 | unsigned long khz = 0; | |
8087 | ||
8088 | if (data) | |
8089 | khz = freq->new; | |
8090 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
8091 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
8092 | if (!khz) | |
8093 | khz = tsc_khz; | |
0a3aee0d | 8094 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
8095 | } |
8096 | ||
5fa4ec9c | 8097 | #ifdef CONFIG_X86_64 |
0092e434 VK |
8098 | static void kvm_hyperv_tsc_notifier(void) |
8099 | { | |
0092e434 VK |
8100 | struct kvm *kvm; |
8101 | struct kvm_vcpu *vcpu; | |
8102 | int cpu; | |
a83829f5 | 8103 | unsigned long flags; |
0092e434 | 8104 | |
0d9ce162 | 8105 | mutex_lock(&kvm_lock); |
0092e434 VK |
8106 | list_for_each_entry(kvm, &vm_list, vm_list) |
8107 | kvm_make_mclock_inprogress_request(kvm); | |
8108 | ||
8109 | hyperv_stop_tsc_emulation(); | |
8110 | ||
8111 | /* TSC frequency always matches when on Hyper-V */ | |
8112 | for_each_present_cpu(cpu) | |
8113 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
8114 | kvm_max_guest_tsc_khz = tsc_khz; | |
8115 | ||
8116 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
8117 | struct kvm_arch *ka = &kvm->arch; | |
8118 | ||
a83829f5 | 8119 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
0092e434 | 8120 | pvclock_update_vm_gtod_copy(kvm); |
a83829f5 | 8121 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
0092e434 VK |
8122 | |
8123 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
8124 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
8125 | ||
8126 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
8127 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); | |
0092e434 | 8128 | } |
0d9ce162 | 8129 | mutex_unlock(&kvm_lock); |
0092e434 | 8130 | } |
5fa4ec9c | 8131 | #endif |
0092e434 | 8132 | |
df24014a | 8133 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 8134 | { |
c8076604 GH |
8135 | struct kvm *kvm; |
8136 | struct kvm_vcpu *vcpu; | |
8137 | int i, send_ipi = 0; | |
8138 | ||
8cfdc000 ZA |
8139 | /* |
8140 | * We allow guests to temporarily run on slowing clocks, | |
8141 | * provided we notify them after, or to run on accelerating | |
8142 | * clocks, provided we notify them before. Thus time never | |
8143 | * goes backwards. | |
8144 | * | |
8145 | * However, we have a problem. We can't atomically update | |
8146 | * the frequency of a given CPU from this function; it is | |
8147 | * merely a notifier, which can be called from any CPU. | |
8148 | * Changing the TSC frequency at arbitrary points in time | |
8149 | * requires a recomputation of local variables related to | |
8150 | * the TSC for each VCPU. We must flag these local variables | |
8151 | * to be updated and be sure the update takes place with the | |
8152 | * new frequency before any guests proceed. | |
8153 | * | |
8154 | * Unfortunately, the combination of hotplug CPU and frequency | |
8155 | * change creates an intractable locking scenario; the order | |
8156 | * of when these callouts happen is undefined with respect to | |
8157 | * CPU hotplug, and they can race with each other. As such, | |
8158 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
8159 | * undefined; you can actually have a CPU frequency change take | |
8160 | * place in between the computation of X and the setting of the | |
8161 | * variable. To protect against this problem, all updates of | |
8162 | * the per_cpu tsc_khz variable are done in an interrupt | |
8163 | * protected IPI, and all callers wishing to update the value | |
8164 | * must wait for a synchronous IPI to complete (which is trivial | |
8165 | * if the caller is on the CPU already). This establishes the | |
8166 | * necessary total order on variable updates. | |
8167 | * | |
8168 | * Note that because a guest time update may take place | |
8169 | * anytime after the setting of the VCPU's request bit, the | |
8170 | * correct TSC value must be set before the request. However, | |
8171 | * to ensure the update actually makes it to any guest which | |
8172 | * starts running in hardware virtualization between the set | |
8173 | * and the acquisition of the spinlock, we must also ping the | |
8174 | * CPU after setting the request bit. | |
8175 | * | |
8176 | */ | |
8177 | ||
df24014a | 8178 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 8179 | |
0d9ce162 | 8180 | mutex_lock(&kvm_lock); |
c8076604 | 8181 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 8182 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 8183 | if (vcpu->cpu != cpu) |
c8076604 | 8184 | continue; |
c285545f | 8185 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 8186 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 8187 | send_ipi = 1; |
c8076604 GH |
8188 | } |
8189 | } | |
0d9ce162 | 8190 | mutex_unlock(&kvm_lock); |
c8076604 GH |
8191 | |
8192 | if (freq->old < freq->new && send_ipi) { | |
8193 | /* | |
8194 | * We upscale the frequency. Must make the guest | |
8195 | * doesn't see old kvmclock values while running with | |
8196 | * the new frequency, otherwise we risk the guest sees | |
8197 | * time go backwards. | |
8198 | * | |
8199 | * In case we update the frequency for another cpu | |
8200 | * (which might be in guest context) send an interrupt | |
8201 | * to kick the cpu out of guest context. Next time | |
8202 | * guest context is entered kvmclock will be updated, | |
8203 | * so the guest will not see stale values. | |
8204 | */ | |
df24014a | 8205 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 8206 | } |
df24014a VK |
8207 | } |
8208 | ||
8209 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
8210 | void *data) | |
8211 | { | |
8212 | struct cpufreq_freqs *freq = data; | |
8213 | int cpu; | |
8214 | ||
8215 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
8216 | return 0; | |
8217 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
8218 | return 0; | |
8219 | ||
8220 | for_each_cpu(cpu, freq->policy->cpus) | |
8221 | __kvmclock_cpufreq_notifier(freq, cpu); | |
8222 | ||
c8076604 GH |
8223 | return 0; |
8224 | } | |
8225 | ||
8226 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
8227 | .notifier_call = kvmclock_cpufreq_notifier |
8228 | }; | |
8229 | ||
251a5fd6 | 8230 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 8231 | { |
251a5fd6 SAS |
8232 | tsc_khz_changed(NULL); |
8233 | return 0; | |
8cfdc000 ZA |
8234 | } |
8235 | ||
b820cc0c ZA |
8236 | static void kvm_timer_init(void) |
8237 | { | |
c285545f | 8238 | max_tsc_khz = tsc_khz; |
460dd42e | 8239 | |
b820cc0c | 8240 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f | 8241 | #ifdef CONFIG_CPU_FREQ |
aaec7c03 | 8242 | struct cpufreq_policy *policy; |
758f588d BP |
8243 | int cpu; |
8244 | ||
3e26f230 | 8245 | cpu = get_cpu(); |
aaec7c03 | 8246 | policy = cpufreq_cpu_get(cpu); |
9a11997e WL |
8247 | if (policy) { |
8248 | if (policy->cpuinfo.max_freq) | |
8249 | max_tsc_khz = policy->cpuinfo.max_freq; | |
8250 | cpufreq_cpu_put(policy); | |
8251 | } | |
3e26f230 | 8252 | put_cpu(); |
c285545f | 8253 | #endif |
b820cc0c ZA |
8254 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
8255 | CPUFREQ_TRANSITION_NOTIFIER); | |
8256 | } | |
460dd42e | 8257 | |
73c1b41e | 8258 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 8259 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
8260 | } |
8261 | ||
dd60d217 AK |
8262 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
8263 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 8264 | |
f5132b01 | 8265 | int kvm_is_in_guest(void) |
ff9d07a0 | 8266 | { |
086c9855 | 8267 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
8268 | } |
8269 | ||
8270 | static int kvm_is_user_mode(void) | |
8271 | { | |
8272 | int user_mode = 3; | |
dcf46b94 | 8273 | |
086c9855 | 8274 | if (__this_cpu_read(current_vcpu)) |
b3646477 | 8275 | user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu)); |
dcf46b94 | 8276 | |
ff9d07a0 ZY |
8277 | return user_mode != 0; |
8278 | } | |
8279 | ||
8280 | static unsigned long kvm_get_guest_ip(void) | |
8281 | { | |
8282 | unsigned long ip = 0; | |
dcf46b94 | 8283 | |
086c9855 AS |
8284 | if (__this_cpu_read(current_vcpu)) |
8285 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 8286 | |
ff9d07a0 ZY |
8287 | return ip; |
8288 | } | |
8289 | ||
8479e04e LK |
8290 | static void kvm_handle_intel_pt_intr(void) |
8291 | { | |
8292 | struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); | |
8293 | ||
8294 | kvm_make_request(KVM_REQ_PMI, vcpu); | |
8295 | __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, | |
8296 | (unsigned long *)&vcpu->arch.pmu.global_status); | |
8297 | } | |
8298 | ||
ff9d07a0 ZY |
8299 | static struct perf_guest_info_callbacks kvm_guest_cbs = { |
8300 | .is_in_guest = kvm_is_in_guest, | |
8301 | .is_user_mode = kvm_is_user_mode, | |
8302 | .get_guest_ip = kvm_get_guest_ip, | |
8479e04e | 8303 | .handle_intel_pt_intr = kvm_handle_intel_pt_intr, |
ff9d07a0 ZY |
8304 | }; |
8305 | ||
16e8d74d MT |
8306 | #ifdef CONFIG_X86_64 |
8307 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
8308 | { | |
d828199e MT |
8309 | struct kvm *kvm; |
8310 | ||
8311 | struct kvm_vcpu *vcpu; | |
8312 | int i; | |
8313 | ||
0d9ce162 | 8314 | mutex_lock(&kvm_lock); |
d828199e MT |
8315 | list_for_each_entry(kvm, &vm_list, vm_list) |
8316 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 8317 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 8318 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 8319 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
8320 | } |
8321 | ||
8322 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
8323 | ||
3f804f6d TG |
8324 | /* |
8325 | * Indirection to move queue_work() out of the tk_core.seq write held | |
8326 | * region to prevent possible deadlocks against time accessors which | |
8327 | * are invoked with work related locks held. | |
8328 | */ | |
8329 | static void pvclock_irq_work_fn(struct irq_work *w) | |
8330 | { | |
8331 | queue_work(system_long_wq, &pvclock_gtod_work); | |
8332 | } | |
8333 | ||
8334 | static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); | |
8335 | ||
16e8d74d MT |
8336 | /* |
8337 | * Notification about pvclock gtod data update. | |
8338 | */ | |
8339 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
8340 | void *priv) | |
8341 | { | |
8342 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
8343 | struct timekeeper *tk = priv; | |
8344 | ||
8345 | update_pvclock_gtod(tk); | |
8346 | ||
3f804f6d TG |
8347 | /* |
8348 | * Disable master clock if host does not trust, or does not use, | |
8349 | * TSC based clocksource. Delegate queue_work() to irq_work as | |
8350 | * this is invoked with tk_core.seq write held. | |
16e8d74d | 8351 | */ |
b0c39dc6 | 8352 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d | 8353 | atomic_read(&kvm_guest_has_master_clock) != 0) |
3f804f6d | 8354 | irq_work_queue(&pvclock_irq_work); |
16e8d74d MT |
8355 | return 0; |
8356 | } | |
8357 | ||
8358 | static struct notifier_block pvclock_gtod_notifier = { | |
8359 | .notifier_call = pvclock_gtod_notify, | |
8360 | }; | |
8361 | #endif | |
8362 | ||
f8c16bba | 8363 | int kvm_arch_init(void *opaque) |
043405e1 | 8364 | { |
d008dfdb | 8365 | struct kvm_x86_init_ops *ops = opaque; |
b820cc0c | 8366 | int r; |
f8c16bba | 8367 | |
afaf0b2f | 8368 | if (kvm_x86_ops.hardware_enable) { |
f8c16bba | 8369 | printk(KERN_ERR "kvm: already loaded the other module\n"); |
56c6d28a ZX |
8370 | r = -EEXIST; |
8371 | goto out; | |
f8c16bba ZX |
8372 | } |
8373 | ||
8374 | if (!ops->cpu_has_kvm_support()) { | |
ef935c25 | 8375 | pr_err_ratelimited("kvm: no hardware support\n"); |
56c6d28a ZX |
8376 | r = -EOPNOTSUPP; |
8377 | goto out; | |
f8c16bba ZX |
8378 | } |
8379 | if (ops->disabled_by_bios()) { | |
ef935c25 | 8380 | pr_err_ratelimited("kvm: disabled by bios\n"); |
56c6d28a ZX |
8381 | r = -EOPNOTSUPP; |
8382 | goto out; | |
f8c16bba ZX |
8383 | } |
8384 | ||
b666a4b6 MO |
8385 | /* |
8386 | * KVM explicitly assumes that the guest has an FPU and | |
8387 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
8388 | * vCPU's FPU state as a fxregs_state struct. | |
8389 | */ | |
8390 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
8391 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
8392 | r = -EOPNOTSUPP; | |
8393 | goto out; | |
8394 | } | |
8395 | ||
013f6a5d | 8396 | r = -ENOMEM; |
ed8e4812 | 8397 | x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), |
b666a4b6 MO |
8398 | __alignof__(struct fpu), SLAB_ACCOUNT, |
8399 | NULL); | |
8400 | if (!x86_fpu_cache) { | |
8401 | printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); | |
8402 | goto out; | |
8403 | } | |
8404 | ||
c9b8b07c SC |
8405 | x86_emulator_cache = kvm_alloc_emulator_cache(); |
8406 | if (!x86_emulator_cache) { | |
8407 | pr_err("kvm: failed to allocate cache for x86 emulator\n"); | |
8408 | goto out_free_x86_fpu_cache; | |
8409 | } | |
8410 | ||
7e34fbd0 SC |
8411 | user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); |
8412 | if (!user_return_msrs) { | |
8413 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); | |
c9b8b07c | 8414 | goto out_free_x86_emulator_cache; |
013f6a5d | 8415 | } |
e5fda4bb | 8416 | kvm_nr_uret_msrs = 0; |
013f6a5d | 8417 | |
97db56ce AK |
8418 | r = kvm_mmu_module_init(); |
8419 | if (r) | |
013f6a5d | 8420 | goto out_free_percpu; |
97db56ce | 8421 | |
b820cc0c | 8422 | kvm_timer_init(); |
c8076604 | 8423 | |
ff9d07a0 ZY |
8424 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
8425 | ||
cfc48181 | 8426 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
2acf923e | 8427 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
cfc48181 SC |
8428 | supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; |
8429 | } | |
2acf923e | 8430 | |
0c5f81da WL |
8431 | if (pi_inject_timer == -1) |
8432 | pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); | |
16e8d74d MT |
8433 | #ifdef CONFIG_X86_64 |
8434 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 8435 | |
5fa4ec9c | 8436 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 8437 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
8438 | #endif |
8439 | ||
f8c16bba | 8440 | return 0; |
56c6d28a | 8441 | |
013f6a5d | 8442 | out_free_percpu: |
7e34fbd0 | 8443 | free_percpu(user_return_msrs); |
c9b8b07c SC |
8444 | out_free_x86_emulator_cache: |
8445 | kmem_cache_destroy(x86_emulator_cache); | |
b666a4b6 MO |
8446 | out_free_x86_fpu_cache: |
8447 | kmem_cache_destroy(x86_fpu_cache); | |
56c6d28a | 8448 | out: |
56c6d28a | 8449 | return r; |
043405e1 | 8450 | } |
8776e519 | 8451 | |
f8c16bba ZX |
8452 | void kvm_arch_exit(void) |
8453 | { | |
0092e434 | 8454 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 8455 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
8456 | clear_hv_tscchange_cb(); |
8457 | #endif | |
cef84c30 | 8458 | kvm_lapic_exit(); |
ff9d07a0 ZY |
8459 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
8460 | ||
888d256e JK |
8461 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
8462 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
8463 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 8464 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
8465 | #ifdef CONFIG_X86_64 |
8466 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
3f804f6d | 8467 | irq_work_sync(&pvclock_irq_work); |
594b27e6 | 8468 | cancel_work_sync(&pvclock_gtod_work); |
16e8d74d | 8469 | #endif |
afaf0b2f | 8470 | kvm_x86_ops.hardware_enable = NULL; |
56c6d28a | 8471 | kvm_mmu_module_exit(); |
7e34fbd0 | 8472 | free_percpu(user_return_msrs); |
dfdc0a71 | 8473 | kmem_cache_destroy(x86_emulator_cache); |
b666a4b6 | 8474 | kmem_cache_destroy(x86_fpu_cache); |
b59b153d | 8475 | #ifdef CONFIG_KVM_XEN |
c462f859 | 8476 | static_key_deferred_flush(&kvm_xen_enabled); |
7d6bbebb | 8477 | WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); |
b59b153d | 8478 | #endif |
56c6d28a | 8479 | } |
f8c16bba | 8480 | |
872f36eb | 8481 | static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) |
8776e519 HB |
8482 | { |
8483 | ++vcpu->stat.halt_exits; | |
35754c98 | 8484 | if (lapic_in_kernel(vcpu)) { |
647daca2 | 8485 | vcpu->arch.mp_state = state; |
8776e519 HB |
8486 | return 1; |
8487 | } else { | |
647daca2 | 8488 | vcpu->run->exit_reason = reason; |
8776e519 HB |
8489 | return 0; |
8490 | } | |
8491 | } | |
647daca2 TL |
8492 | |
8493 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) | |
8494 | { | |
8495 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); | |
8496 | } | |
5cb56059 JS |
8497 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
8498 | ||
8499 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
8500 | { | |
6affcbed KH |
8501 | int ret = kvm_skip_emulated_instruction(vcpu); |
8502 | /* | |
8503 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
8504 | * KVM_EXIT_DEBUG here. | |
8505 | */ | |
8506 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 8507 | } |
8776e519 HB |
8508 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
8509 | ||
647daca2 TL |
8510 | int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) |
8511 | { | |
8512 | int ret = kvm_skip_emulated_instruction(vcpu); | |
8513 | ||
8514 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; | |
8515 | } | |
8516 | EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); | |
8517 | ||
8ef81a9a | 8518 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8519 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
8520 | unsigned long clock_type) | |
8521 | { | |
8522 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 8523 | struct timespec64 ts; |
80fbd89c | 8524 | u64 cycle; |
55dd00a7 MT |
8525 | int ret; |
8526 | ||
8527 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
8528 | return -KVM_EOPNOTSUPP; | |
8529 | ||
7ca7f3b9 | 8530 | if (!kvm_get_walltime_and_clockread(&ts, &cycle)) |
55dd00a7 MT |
8531 | return -KVM_EOPNOTSUPP; |
8532 | ||
8533 | clock_pairing.sec = ts.tv_sec; | |
8534 | clock_pairing.nsec = ts.tv_nsec; | |
8535 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
8536 | clock_pairing.flags = 0; | |
bcbfbd8e | 8537 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
8538 | |
8539 | ret = 0; | |
8540 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
8541 | sizeof(struct kvm_clock_pairing))) | |
8542 | ret = -KVM_EFAULT; | |
8543 | ||
8544 | return ret; | |
8545 | } | |
8ef81a9a | 8546 | #endif |
55dd00a7 | 8547 | |
6aef266c SV |
8548 | /* |
8549 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
8550 | * | |
8551 | * @apicid - apicid of vcpu to be kicked. | |
8552 | */ | |
8553 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
8554 | { | |
24d2166b | 8555 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 8556 | |
150a84fe | 8557 | lapic_irq.shorthand = APIC_DEST_NOSHORT; |
c96001c5 | 8558 | lapic_irq.dest_mode = APIC_DEST_PHYSICAL; |
ebd28fcb | 8559 | lapic_irq.level = 0; |
24d2166b | 8560 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 8561 | lapic_irq.msi_redir_hint = false; |
6aef266c | 8562 | |
24d2166b | 8563 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 8564 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
8565 | } |
8566 | ||
4e19c36f SS |
8567 | bool kvm_apicv_activated(struct kvm *kvm) |
8568 | { | |
8569 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
8570 | } | |
8571 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
8572 | ||
4651fc56 | 8573 | static void kvm_apicv_init(struct kvm *kvm) |
4e19c36f | 8574 | { |
4651fc56 | 8575 | if (enable_apicv) |
4e19c36f SS |
8576 | clear_bit(APICV_INHIBIT_REASON_DISABLE, |
8577 | &kvm->arch.apicv_inhibit_reasons); | |
8578 | else | |
8579 | set_bit(APICV_INHIBIT_REASON_DISABLE, | |
8580 | &kvm->arch.apicv_inhibit_reasons); | |
8581 | } | |
4e19c36f | 8582 | |
4a7132ef | 8583 | static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) |
71506297 WL |
8584 | { |
8585 | struct kvm_vcpu *target = NULL; | |
8586 | struct kvm_apic_map *map; | |
8587 | ||
4a7132ef WL |
8588 | vcpu->stat.directed_yield_attempted++; |
8589 | ||
72b268a8 WL |
8590 | if (single_task_running()) |
8591 | goto no_yield; | |
8592 | ||
71506297 | 8593 | rcu_read_lock(); |
4a7132ef | 8594 | map = rcu_dereference(vcpu->kvm->arch.apic_map); |
71506297 WL |
8595 | |
8596 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
8597 | target = map->phys_map[dest_id]->vcpu; | |
8598 | ||
8599 | rcu_read_unlock(); | |
8600 | ||
4a7132ef WL |
8601 | if (!target || !READ_ONCE(target->ready)) |
8602 | goto no_yield; | |
8603 | ||
a1fa4cbd WL |
8604 | /* Ignore requests to yield to self */ |
8605 | if (vcpu == target) | |
8606 | goto no_yield; | |
8607 | ||
4a7132ef WL |
8608 | if (kvm_vcpu_yield_to(target) <= 0) |
8609 | goto no_yield; | |
8610 | ||
8611 | vcpu->stat.directed_yield_successful++; | |
8612 | ||
8613 | no_yield: | |
8614 | return; | |
71506297 WL |
8615 | } |
8616 | ||
0dbb1123 AK |
8617 | static int complete_hypercall_exit(struct kvm_vcpu *vcpu) |
8618 | { | |
8619 | u64 ret = vcpu->run->hypercall.ret; | |
8620 | ||
8621 | if (!is_64_bit_mode(vcpu)) | |
8622 | ret = (u32)ret; | |
8623 | kvm_rax_write(vcpu, ret); | |
8624 | ++vcpu->stat.hypercalls; | |
8625 | return kvm_skip_emulated_instruction(vcpu); | |
8626 | } | |
8627 | ||
8776e519 HB |
8628 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
8629 | { | |
8630 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 8631 | int op_64_bit; |
8776e519 | 8632 | |
23200b7a JM |
8633 | if (kvm_xen_hypercall_enabled(vcpu->kvm)) |
8634 | return kvm_xen_hypercall(vcpu); | |
8635 | ||
8f014550 | 8636 | if (kvm_hv_hypercall_enabled(vcpu)) |
696ca779 | 8637 | return kvm_hv_hypercall(vcpu); |
55cd8e5a | 8638 | |
de3cd117 SC |
8639 | nr = kvm_rax_read(vcpu); |
8640 | a0 = kvm_rbx_read(vcpu); | |
8641 | a1 = kvm_rcx_read(vcpu); | |
8642 | a2 = kvm_rdx_read(vcpu); | |
8643 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 8644 | |
229456fc | 8645 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 8646 | |
a449c7aa NA |
8647 | op_64_bit = is_64_bit_mode(vcpu); |
8648 | if (!op_64_bit) { | |
8776e519 HB |
8649 | nr &= 0xFFFFFFFF; |
8650 | a0 &= 0xFFFFFFFF; | |
8651 | a1 &= 0xFFFFFFFF; | |
8652 | a2 &= 0xFFFFFFFF; | |
8653 | a3 &= 0xFFFFFFFF; | |
8654 | } | |
8655 | ||
b3646477 | 8656 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { |
07708c4a | 8657 | ret = -KVM_EPERM; |
696ca779 | 8658 | goto out; |
07708c4a JK |
8659 | } |
8660 | ||
66570e96 OU |
8661 | ret = -KVM_ENOSYS; |
8662 | ||
8776e519 | 8663 | switch (nr) { |
b93463aa AK |
8664 | case KVM_HC_VAPIC_POLL_IRQ: |
8665 | ret = 0; | |
8666 | break; | |
6aef266c | 8667 | case KVM_HC_KICK_CPU: |
66570e96 OU |
8668 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) |
8669 | break; | |
8670 | ||
6aef266c | 8671 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); |
4a7132ef | 8672 | kvm_sched_yield(vcpu, a1); |
6aef266c SV |
8673 | ret = 0; |
8674 | break; | |
8ef81a9a | 8675 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8676 | case KVM_HC_CLOCK_PAIRING: |
8677 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
8678 | break; | |
1ed199a4 | 8679 | #endif |
4180bf1b | 8680 | case KVM_HC_SEND_IPI: |
66570e96 OU |
8681 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) |
8682 | break; | |
8683 | ||
4180bf1b WL |
8684 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); |
8685 | break; | |
71506297 | 8686 | case KVM_HC_SCHED_YIELD: |
66570e96 OU |
8687 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) |
8688 | break; | |
8689 | ||
4a7132ef | 8690 | kvm_sched_yield(vcpu, a0); |
71506297 WL |
8691 | ret = 0; |
8692 | break; | |
0dbb1123 AK |
8693 | case KVM_HC_MAP_GPA_RANGE: { |
8694 | u64 gpa = a0, npages = a1, attrs = a2; | |
8695 | ||
8696 | ret = -KVM_ENOSYS; | |
8697 | if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) | |
8698 | break; | |
8699 | ||
8700 | if (!PAGE_ALIGNED(gpa) || !npages || | |
8701 | gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { | |
8702 | ret = -KVM_EINVAL; | |
8703 | break; | |
8704 | } | |
8705 | ||
8706 | vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; | |
8707 | vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; | |
8708 | vcpu->run->hypercall.args[0] = gpa; | |
8709 | vcpu->run->hypercall.args[1] = npages; | |
8710 | vcpu->run->hypercall.args[2] = attrs; | |
8711 | vcpu->run->hypercall.longmode = op_64_bit; | |
8712 | vcpu->arch.complete_userspace_io = complete_hypercall_exit; | |
8713 | return 0; | |
8714 | } | |
8776e519 HB |
8715 | default: |
8716 | ret = -KVM_ENOSYS; | |
8717 | break; | |
8718 | } | |
696ca779 | 8719 | out: |
a449c7aa NA |
8720 | if (!op_64_bit) |
8721 | ret = (u32)ret; | |
de3cd117 | 8722 | kvm_rax_write(vcpu, ret); |
6356ee0c | 8723 | |
f11c3a8d | 8724 | ++vcpu->stat.hypercalls; |
6356ee0c | 8725 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
8726 | } |
8727 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
8728 | ||
b6785def | 8729 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 8730 | { |
d6aa1000 | 8731 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 8732 | char instruction[3]; |
5fdbf976 | 8733 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 8734 | |
b3646477 | 8735 | static_call(kvm_x86_patch_hypercall)(vcpu, instruction); |
8776e519 | 8736 | |
ce2e852e DV |
8737 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
8738 | &ctxt->exception); | |
8776e519 HB |
8739 | } |
8740 | ||
851ba692 | 8741 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8742 | { |
782d422b MG |
8743 | return vcpu->run->request_interrupt_window && |
8744 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
8745 | } |
8746 | ||
851ba692 | 8747 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8748 | { |
851ba692 AK |
8749 | struct kvm_run *kvm_run = vcpu->run; |
8750 | ||
f1c6366e TL |
8751 | /* |
8752 | * if_flag is obsolete and useless, so do not bother | |
8753 | * setting it for SEV-ES guests. Userspace can just | |
8754 | * use kvm_run->ready_for_interrupt_injection. | |
8755 | */ | |
8756 | kvm_run->if_flag = !vcpu->arch.guest_state_protected | |
8757 | && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; | |
8758 | ||
2d3ad1f4 | 8759 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 8760 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
8761 | kvm_run->ready_for_interrupt_injection = |
8762 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 8763 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
15aad3be CQ |
8764 | |
8765 | if (is_smm(vcpu)) | |
8766 | kvm_run->flags |= KVM_RUN_X86_SMM; | |
b6c7a5dc HB |
8767 | } |
8768 | ||
95ba8273 GN |
8769 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
8770 | { | |
8771 | int max_irr, tpr; | |
8772 | ||
afaf0b2f | 8773 | if (!kvm_x86_ops.update_cr8_intercept) |
95ba8273 GN |
8774 | return; |
8775 | ||
bce87cce | 8776 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
8777 | return; |
8778 | ||
d62caabb AS |
8779 | if (vcpu->arch.apicv_active) |
8780 | return; | |
8781 | ||
8db3baa2 GN |
8782 | if (!vcpu->arch.apic->vapic_addr) |
8783 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
8784 | else | |
8785 | max_irr = -1; | |
95ba8273 GN |
8786 | |
8787 | if (max_irr != -1) | |
8788 | max_irr >>= 4; | |
8789 | ||
8790 | tpr = kvm_lapic_get_cr8(vcpu); | |
8791 | ||
b3646477 | 8792 | static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); |
95ba8273 GN |
8793 | } |
8794 | ||
b97f0745 | 8795 | |
cb6a32c2 SC |
8796 | int kvm_check_nested_events(struct kvm_vcpu *vcpu) |
8797 | { | |
cb6a32c2 SC |
8798 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
8799 | kvm_x86_ops.nested_ops->triple_fault(vcpu); | |
8800 | return 1; | |
8801 | } | |
8802 | ||
8803 | return kvm_x86_ops.nested_ops->check_events(vcpu); | |
8804 | } | |
8805 | ||
b97f0745 ML |
8806 | static void kvm_inject_exception(struct kvm_vcpu *vcpu) |
8807 | { | |
8808 | if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) | |
8809 | vcpu->arch.exception.error_code = false; | |
8810 | static_call(kvm_x86_queue_exception)(vcpu); | |
8811 | } | |
8812 | ||
a5f6909a | 8813 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) |
95ba8273 | 8814 | { |
b6b8a145 | 8815 | int r; |
c6b22f59 | 8816 | bool can_inject = true; |
b6b8a145 | 8817 | |
95ba8273 | 8818 | /* try to reinject previous events if any */ |
664f8e26 | 8819 | |
c6b22f59 | 8820 | if (vcpu->arch.exception.injected) { |
b97f0745 | 8821 | kvm_inject_exception(vcpu); |
c6b22f59 PB |
8822 | can_inject = false; |
8823 | } | |
664f8e26 | 8824 | /* |
a042c26f LA |
8825 | * Do not inject an NMI or interrupt if there is a pending |
8826 | * exception. Exceptions and interrupts are recognized at | |
8827 | * instruction boundaries, i.e. the start of an instruction. | |
8828 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
8829 | * NMIs and interrupts, i.e. traps are recognized before an | |
8830 | * NMI/interrupt that's pending on the same instruction. | |
8831 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
8832 | * priority, but are only generated (pended) during instruction | |
8833 | * execution, i.e. a pending fault-like exception means the | |
8834 | * fault occurred on the *previous* instruction and must be | |
8835 | * serviced prior to recognizing any new events in order to | |
8836 | * fully complete the previous instruction. | |
664f8e26 | 8837 | */ |
1a680e35 | 8838 | else if (!vcpu->arch.exception.pending) { |
c6b22f59 | 8839 | if (vcpu->arch.nmi_injected) { |
b3646477 | 8840 | static_call(kvm_x86_set_nmi)(vcpu); |
c6b22f59 PB |
8841 | can_inject = false; |
8842 | } else if (vcpu->arch.interrupt.injected) { | |
b3646477 | 8843 | static_call(kvm_x86_set_irq)(vcpu); |
c6b22f59 PB |
8844 | can_inject = false; |
8845 | } | |
664f8e26 WL |
8846 | } |
8847 | ||
3b82b8d7 SC |
8848 | WARN_ON_ONCE(vcpu->arch.exception.injected && |
8849 | vcpu->arch.exception.pending); | |
8850 | ||
1a680e35 LA |
8851 | /* |
8852 | * Call check_nested_events() even if we reinjected a previous event | |
8853 | * in order for caller to determine if it should require immediate-exit | |
8854 | * from L2 to L1 due to pending L1 events which require exit | |
8855 | * from L2 to L1. | |
8856 | */ | |
56083bdf | 8857 | if (is_guest_mode(vcpu)) { |
cb6a32c2 | 8858 | r = kvm_check_nested_events(vcpu); |
c9d40913 | 8859 | if (r < 0) |
a5f6909a | 8860 | goto out; |
664f8e26 WL |
8861 | } |
8862 | ||
8863 | /* try to inject new event if pending */ | |
b59bb7bd | 8864 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
8865 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
8866 | vcpu->arch.exception.has_error_code, | |
8867 | vcpu->arch.exception.error_code); | |
d6e8c854 | 8868 | |
664f8e26 WL |
8869 | vcpu->arch.exception.pending = false; |
8870 | vcpu->arch.exception.injected = true; | |
8871 | ||
d6e8c854 NA |
8872 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
8873 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
8874 | X86_EFLAGS_RF); | |
8875 | ||
f10c729f | 8876 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
f10c729f JM |
8877 | kvm_deliver_exception_payload(vcpu); |
8878 | if (vcpu->arch.dr7 & DR7_GD) { | |
8879 | vcpu->arch.dr7 &= ~DR7_GD; | |
8880 | kvm_update_dr7(vcpu); | |
8881 | } | |
6bdf0662 NA |
8882 | } |
8883 | ||
b97f0745 | 8884 | kvm_inject_exception(vcpu); |
c6b22f59 | 8885 | can_inject = false; |
1a680e35 LA |
8886 | } |
8887 | ||
c9d40913 PB |
8888 | /* |
8889 | * Finally, inject interrupt events. If an event cannot be injected | |
8890 | * due to architectural conditions (e.g. IF=0) a window-open exit | |
8891 | * will re-request KVM_REQ_EVENT. Sometimes however an event is pending | |
8892 | * and can architecturally be injected, but we cannot do it right now: | |
8893 | * an interrupt could have arrived just now and we have to inject it | |
8894 | * as a vmexit, or there could already an event in the queue, which is | |
8895 | * indicated by can_inject. In that case we request an immediate exit | |
8896 | * in order to make progress and get back here for another iteration. | |
8897 | * The kvm_x86_ops hooks communicate this by returning -EBUSY. | |
8898 | */ | |
8899 | if (vcpu->arch.smi_pending) { | |
b3646477 | 8900 | r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 8901 | if (r < 0) |
a5f6909a | 8902 | goto out; |
c9d40913 PB |
8903 | if (r) { |
8904 | vcpu->arch.smi_pending = false; | |
8905 | ++vcpu->arch.smi_count; | |
8906 | enter_smm(vcpu); | |
8907 | can_inject = false; | |
8908 | } else | |
b3646477 | 8909 | static_call(kvm_x86_enable_smi_window)(vcpu); |
c9d40913 PB |
8910 | } |
8911 | ||
8912 | if (vcpu->arch.nmi_pending) { | |
b3646477 | 8913 | r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 8914 | if (r < 0) |
a5f6909a | 8915 | goto out; |
c9d40913 PB |
8916 | if (r) { |
8917 | --vcpu->arch.nmi_pending; | |
8918 | vcpu->arch.nmi_injected = true; | |
b3646477 | 8919 | static_call(kvm_x86_set_nmi)(vcpu); |
c9d40913 | 8920 | can_inject = false; |
b3646477 | 8921 | WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); |
c9d40913 PB |
8922 | } |
8923 | if (vcpu->arch.nmi_pending) | |
b3646477 | 8924 | static_call(kvm_x86_enable_nmi_window)(vcpu); |
c9d40913 | 8925 | } |
1a680e35 | 8926 | |
c9d40913 | 8927 | if (kvm_cpu_has_injectable_intr(vcpu)) { |
b3646477 | 8928 | r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 8929 | if (r < 0) |
a5f6909a | 8930 | goto out; |
c9d40913 PB |
8931 | if (r) { |
8932 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); | |
b3646477 JB |
8933 | static_call(kvm_x86_set_irq)(vcpu); |
8934 | WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); | |
c9d40913 PB |
8935 | } |
8936 | if (kvm_cpu_has_injectable_intr(vcpu)) | |
b3646477 | 8937 | static_call(kvm_x86_enable_irq_window)(vcpu); |
95ba8273 | 8938 | } |
ee2cd4b7 | 8939 | |
c9d40913 PB |
8940 | if (is_guest_mode(vcpu) && |
8941 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
8942 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
8943 | *req_immediate_exit = true; | |
8944 | ||
8945 | WARN_ON(vcpu->arch.exception.pending); | |
a5f6909a | 8946 | return 0; |
c9d40913 | 8947 | |
a5f6909a JM |
8948 | out: |
8949 | if (r == -EBUSY) { | |
8950 | *req_immediate_exit = true; | |
8951 | r = 0; | |
8952 | } | |
8953 | return r; | |
95ba8273 GN |
8954 | } |
8955 | ||
7460fb4a AK |
8956 | static void process_nmi(struct kvm_vcpu *vcpu) |
8957 | { | |
8958 | unsigned limit = 2; | |
8959 | ||
8960 | /* | |
8961 | * x86 is limited to one NMI running, and one NMI pending after it. | |
8962 | * If an NMI is already in progress, limit further NMIs to just one. | |
8963 | * Otherwise, allow two (and we'll inject the first one immediately). | |
8964 | */ | |
b3646477 | 8965 | if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) |
7460fb4a AK |
8966 | limit = 1; |
8967 | ||
8968 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
8969 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
8970 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8971 | } | |
8972 | ||
ee2cd4b7 | 8973 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
8974 | { |
8975 | u32 flags = 0; | |
8976 | flags |= seg->g << 23; | |
8977 | flags |= seg->db << 22; | |
8978 | flags |= seg->l << 21; | |
8979 | flags |= seg->avl << 20; | |
8980 | flags |= seg->present << 15; | |
8981 | flags |= seg->dpl << 13; | |
8982 | flags |= seg->s << 12; | |
8983 | flags |= seg->type << 8; | |
8984 | return flags; | |
8985 | } | |
8986 | ||
ee2cd4b7 | 8987 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
8988 | { |
8989 | struct kvm_segment seg; | |
8990 | int offset; | |
8991 | ||
8992 | kvm_get_segment(vcpu, &seg, n); | |
8993 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
8994 | ||
8995 | if (n < 3) | |
8996 | offset = 0x7f84 + n * 12; | |
8997 | else | |
8998 | offset = 0x7f2c + (n - 3) * 12; | |
8999 | ||
9000 | put_smstate(u32, buf, offset + 8, seg.base); | |
9001 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 9002 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
9003 | } |
9004 | ||
efbb288a | 9005 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 9006 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
9007 | { |
9008 | struct kvm_segment seg; | |
9009 | int offset; | |
9010 | u16 flags; | |
9011 | ||
9012 | kvm_get_segment(vcpu, &seg, n); | |
9013 | offset = 0x7e00 + n * 16; | |
9014 | ||
ee2cd4b7 | 9015 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
9016 | put_smstate(u16, buf, offset, seg.selector); |
9017 | put_smstate(u16, buf, offset + 2, flags); | |
9018 | put_smstate(u32, buf, offset + 4, seg.limit); | |
9019 | put_smstate(u64, buf, offset + 8, seg.base); | |
9020 | } | |
efbb288a | 9021 | #endif |
660a5d51 | 9022 | |
ee2cd4b7 | 9023 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
9024 | { |
9025 | struct desc_ptr dt; | |
9026 | struct kvm_segment seg; | |
9027 | unsigned long val; | |
9028 | int i; | |
9029 | ||
9030 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
9031 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
9032 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
9033 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
9034 | ||
9035 | for (i = 0; i < 8; i++) | |
27b4a9c4 | 9036 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); |
660a5d51 PB |
9037 | |
9038 | kvm_get_dr(vcpu, 6, &val); | |
9039 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
9040 | kvm_get_dr(vcpu, 7, &val); | |
9041 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
9042 | ||
9043 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
9044 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
9045 | put_smstate(u32, buf, 0x7f64, seg.base); | |
9046 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 9047 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
9048 | |
9049 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
9050 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
9051 | put_smstate(u32, buf, 0x7f80, seg.base); | |
9052 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 9053 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 | 9054 | |
b3646477 | 9055 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
660a5d51 PB |
9056 | put_smstate(u32, buf, 0x7f74, dt.address); |
9057 | put_smstate(u32, buf, 0x7f70, dt.size); | |
9058 | ||
b3646477 | 9059 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
660a5d51 PB |
9060 | put_smstate(u32, buf, 0x7f58, dt.address); |
9061 | put_smstate(u32, buf, 0x7f54, dt.size); | |
9062 | ||
9063 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 9064 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
9065 | |
9066 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
9067 | ||
9068 | /* revision id */ | |
9069 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
9070 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
9071 | } | |
9072 | ||
b68f3cc7 | 9073 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 9074 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 9075 | { |
660a5d51 PB |
9076 | struct desc_ptr dt; |
9077 | struct kvm_segment seg; | |
9078 | unsigned long val; | |
9079 | int i; | |
9080 | ||
9081 | for (i = 0; i < 16; i++) | |
27b4a9c4 | 9082 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); |
660a5d51 PB |
9083 | |
9084 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
9085 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
9086 | ||
9087 | kvm_get_dr(vcpu, 6, &val); | |
9088 | put_smstate(u64, buf, 0x7f68, val); | |
9089 | kvm_get_dr(vcpu, 7, &val); | |
9090 | put_smstate(u64, buf, 0x7f60, val); | |
9091 | ||
9092 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
9093 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
9094 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
9095 | ||
9096 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
9097 | ||
9098 | /* revision id */ | |
9099 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
9100 | ||
9101 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
9102 | ||
9103 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
9104 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 9105 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
9106 | put_smstate(u32, buf, 0x7e94, seg.limit); |
9107 | put_smstate(u64, buf, 0x7e98, seg.base); | |
9108 | ||
b3646477 | 9109 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
660a5d51 PB |
9110 | put_smstate(u32, buf, 0x7e84, dt.size); |
9111 | put_smstate(u64, buf, 0x7e88, dt.address); | |
9112 | ||
9113 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
9114 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 9115 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
9116 | put_smstate(u32, buf, 0x7e74, seg.limit); |
9117 | put_smstate(u64, buf, 0x7e78, seg.base); | |
9118 | ||
b3646477 | 9119 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
660a5d51 PB |
9120 | put_smstate(u32, buf, 0x7e64, dt.size); |
9121 | put_smstate(u64, buf, 0x7e68, dt.address); | |
9122 | ||
9123 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 9124 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 9125 | } |
b68f3cc7 | 9126 | #endif |
660a5d51 | 9127 | |
ee2cd4b7 | 9128 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 9129 | { |
660a5d51 | 9130 | struct kvm_segment cs, ds; |
18c3626e | 9131 | struct desc_ptr dt; |
dbc4739b | 9132 | unsigned long cr0; |
660a5d51 | 9133 | char buf[512]; |
660a5d51 | 9134 | |
660a5d51 | 9135 | memset(buf, 0, 512); |
b68f3cc7 | 9136 | #ifdef CONFIG_X86_64 |
d6321d49 | 9137 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 9138 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 9139 | else |
b68f3cc7 | 9140 | #endif |
ee2cd4b7 | 9141 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 9142 | |
0234bf88 | 9143 | /* |
ecc513e5 SC |
9144 | * Give enter_smm() a chance to make ISA-specific changes to the vCPU |
9145 | * state (e.g. leave guest mode) after we've saved the state into the | |
9146 | * SMM state-save area. | |
0234bf88 | 9147 | */ |
ecc513e5 | 9148 | static_call(kvm_x86_enter_smm)(vcpu, buf); |
0234bf88 | 9149 | |
dc87275f | 9150 | kvm_smm_changed(vcpu, true); |
54bf36aa | 9151 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 | 9152 | |
b3646477 | 9153 | if (static_call(kvm_x86_get_nmi_mask)(vcpu)) |
660a5d51 PB |
9154 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; |
9155 | else | |
b3646477 | 9156 | static_call(kvm_x86_set_nmi_mask)(vcpu, true); |
660a5d51 PB |
9157 | |
9158 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
9159 | kvm_rip_write(vcpu, 0x8000); | |
9160 | ||
9161 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
b3646477 | 9162 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
660a5d51 PB |
9163 | vcpu->arch.cr0 = cr0; |
9164 | ||
b3646477 | 9165 | static_call(kvm_x86_set_cr4)(vcpu, 0); |
660a5d51 | 9166 | |
18c3626e PB |
9167 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
9168 | dt.address = dt.size = 0; | |
b3646477 | 9169 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
18c3626e | 9170 | |
996ff542 | 9171 | kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
660a5d51 PB |
9172 | |
9173 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
9174 | cs.base = vcpu->arch.smbase; | |
9175 | ||
9176 | ds.selector = 0; | |
9177 | ds.base = 0; | |
9178 | ||
9179 | cs.limit = ds.limit = 0xffffffff; | |
9180 | cs.type = ds.type = 0x3; | |
9181 | cs.dpl = ds.dpl = 0; | |
9182 | cs.db = ds.db = 0; | |
9183 | cs.s = ds.s = 1; | |
9184 | cs.l = ds.l = 0; | |
9185 | cs.g = ds.g = 1; | |
9186 | cs.avl = ds.avl = 0; | |
9187 | cs.present = ds.present = 1; | |
9188 | cs.unusable = ds.unusable = 0; | |
9189 | cs.padding = ds.padding = 0; | |
9190 | ||
9191 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
9192 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
9193 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
9194 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
9195 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
9196 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
9197 | ||
b68f3cc7 | 9198 | #ifdef CONFIG_X86_64 |
d6321d49 | 9199 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
b3646477 | 9200 | static_call(kvm_x86_set_efer)(vcpu, 0); |
b68f3cc7 | 9201 | #endif |
660a5d51 | 9202 | |
aedbaf4f | 9203 | kvm_update_cpuid_runtime(vcpu); |
660a5d51 | 9204 | kvm_mmu_reset_context(vcpu); |
64d60670 PB |
9205 | } |
9206 | ||
ee2cd4b7 | 9207 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
9208 | { |
9209 | vcpu->arch.smi_pending = true; | |
9210 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9211 | } | |
9212 | ||
7ee30bc1 NNL |
9213 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
9214 | unsigned long *vcpu_bitmap) | |
9215 | { | |
9216 | cpumask_var_t cpus; | |
7ee30bc1 NNL |
9217 | |
9218 | zalloc_cpumask_var(&cpus, GFP_ATOMIC); | |
9219 | ||
db5a95ec | 9220 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, |
54163a34 | 9221 | NULL, vcpu_bitmap, cpus); |
7ee30bc1 NNL |
9222 | |
9223 | free_cpumask_var(cpus); | |
9224 | } | |
9225 | ||
2860c4b1 PB |
9226 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
9227 | { | |
9228 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
9229 | } | |
9230 | ||
8df14af4 SS |
9231 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
9232 | { | |
9233 | if (!lapic_in_kernel(vcpu)) | |
9234 | return; | |
9235 | ||
9236 | vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); | |
9237 | kvm_apic_update_apicv(vcpu); | |
b3646477 | 9238 | static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); |
bca66dbc VK |
9239 | |
9240 | /* | |
9241 | * When APICv gets disabled, we may still have injected interrupts | |
9242 | * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was | |
9243 | * still active when the interrupt got accepted. Make sure | |
9244 | * inject_pending_event() is called to check for that. | |
9245 | */ | |
9246 | if (!vcpu->arch.apicv_active) | |
9247 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8df14af4 SS |
9248 | } |
9249 | EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); | |
9250 | ||
9251 | /* | |
9252 | * NOTE: Do not hold any lock prior to calling this. | |
9253 | * | |
9254 | * In particular, kvm_request_apicv_update() expects kvm->srcu not to be | |
9255 | * locked, because it calls __x86_set_memory_region() which does | |
9256 | * synchronize_srcu(&kvm->srcu). | |
9257 | */ | |
9258 | void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) | |
9259 | { | |
8e205a6b PB |
9260 | unsigned long old, new, expected; |
9261 | ||
afaf0b2f | 9262 | if (!kvm_x86_ops.check_apicv_inhibit_reasons || |
b3646477 | 9263 | !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) |
ef8efd7a SS |
9264 | return; |
9265 | ||
8e205a6b PB |
9266 | old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); |
9267 | do { | |
9268 | expected = new = old; | |
9269 | if (activate) | |
9270 | __clear_bit(bit, &new); | |
9271 | else | |
9272 | __set_bit(bit, &new); | |
9273 | if (new == old) | |
9274 | break; | |
9275 | old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); | |
9276 | } while (old != expected); | |
9277 | ||
9278 | if (!!old == !!new) | |
9279 | return; | |
8df14af4 | 9280 | |
24bbf74c | 9281 | trace_kvm_apicv_update_request(activate, bit); |
afaf0b2f | 9282 | if (kvm_x86_ops.pre_update_apicv_exec_ctrl) |
b3646477 | 9283 | static_call(kvm_x86_pre_update_apicv_exec_ctrl)(kvm, activate); |
7d611233 | 9284 | |
df63202f | 9285 | kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); |
8df14af4 SS |
9286 | } |
9287 | EXPORT_SYMBOL_GPL(kvm_request_apicv_update); | |
9288 | ||
3d81bc7e | 9289 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 9290 | { |
dcbd3e49 | 9291 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 9292 | return; |
c7c9c56c | 9293 | |
6308630b | 9294 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 9295 | |
b053b2ae | 9296 | if (irqchip_split(vcpu->kvm)) |
6308630b | 9297 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 9298 | else { |
fa59cc00 | 9299 | if (vcpu->arch.apicv_active) |
b3646477 | 9300 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
e97f852f WL |
9301 | if (ioapic_in_kernel(vcpu->kvm)) |
9302 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 9303 | } |
e40ff1d6 LA |
9304 | |
9305 | if (is_guest_mode(vcpu)) | |
9306 | vcpu->arch.load_eoi_exitmap_pending = true; | |
9307 | else | |
9308 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
9309 | } | |
9310 | ||
9311 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
9312 | { | |
9313 | u64 eoi_exit_bitmap[4]; | |
9314 | ||
9315 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
9316 | return; | |
9317 | ||
f2bc14b6 VK |
9318 | if (to_hv_vcpu(vcpu)) |
9319 | bitmap_or((ulong *)eoi_exit_bitmap, | |
9320 | vcpu->arch.ioapic_handled_vectors, | |
9321 | to_hv_synic(vcpu)->vec_bitmap, 256); | |
9322 | ||
b3646477 | 9323 | static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); |
c7c9c56c YZ |
9324 | } |
9325 | ||
e649b3f0 ET |
9326 | void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
9327 | unsigned long start, unsigned long end) | |
b1394e74 RK |
9328 | { |
9329 | unsigned long apic_address; | |
9330 | ||
9331 | /* | |
9332 | * The physical address of apic access page is stored in the VMCS. | |
9333 | * Update it when it becomes invalid. | |
9334 | */ | |
9335 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
9336 | if (start <= apic_address && apic_address < end) | |
9337 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
9338 | } | |
9339 | ||
4256f43f TC |
9340 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
9341 | { | |
35754c98 | 9342 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
9343 | return; |
9344 | ||
afaf0b2f | 9345 | if (!kvm_x86_ops.set_apic_access_page_addr) |
4256f43f TC |
9346 | return; |
9347 | ||
b3646477 | 9348 | static_call(kvm_x86_set_apic_access_page_addr)(vcpu); |
4256f43f | 9349 | } |
4256f43f | 9350 | |
d264ee0c SC |
9351 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
9352 | { | |
9353 | smp_send_reschedule(vcpu->cpu); | |
9354 | } | |
9355 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
9356 | ||
9357d939 | 9357 | /* |
362c698f | 9358 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
9359 | * exiting to the userspace. Otherwise, the value will be returned to the |
9360 | * userspace. | |
9361 | */ | |
851ba692 | 9362 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
9363 | { |
9364 | int r; | |
62a193ed MG |
9365 | bool req_int_win = |
9366 | dm_request_for_irq_injection(vcpu) && | |
9367 | kvm_cpu_accept_dm_intr(vcpu); | |
404d5d7b | 9368 | fastpath_t exit_fastpath; |
62a193ed | 9369 | |
730dca42 | 9370 | bool req_immediate_exit = false; |
b6c7a5dc | 9371 | |
fb04a1ed PX |
9372 | /* Forbid vmenter if vcpu dirty ring is soft-full */ |
9373 | if (unlikely(vcpu->kvm->dirty_ring_size && | |
9374 | kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { | |
9375 | vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; | |
9376 | trace_kvm_dirty_ring_exit(vcpu); | |
9377 | r = 0; | |
9378 | goto out; | |
9379 | } | |
9380 | ||
2fa6e1e1 | 9381 | if (kvm_request_pending(vcpu)) { |
67369273 SC |
9382 | if (kvm_check_request(KVM_REQ_VM_BUGGED, vcpu)) { |
9383 | r = -EIO; | |
9384 | goto out; | |
9385 | } | |
729c15c2 | 9386 | if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { |
9a78e158 | 9387 | if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { |
671ddc70 JM |
9388 | r = 0; |
9389 | goto out; | |
9390 | } | |
9391 | } | |
a8eeb04a | 9392 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 9393 | kvm_mmu_unload(vcpu); |
a8eeb04a | 9394 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 9395 | __kvm_migrate_timers(vcpu); |
d828199e MT |
9396 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
9397 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
9398 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
9399 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
9400 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
9401 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
9402 | if (unlikely(r)) |
9403 | goto out; | |
9404 | } | |
a8eeb04a | 9405 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 9406 | kvm_mmu_sync_roots(vcpu); |
727a7e27 PB |
9407 | if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) |
9408 | kvm_mmu_load_pgd(vcpu); | |
eeeb4f67 | 9409 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { |
7780938c | 9410 | kvm_vcpu_flush_tlb_all(vcpu); |
eeeb4f67 SC |
9411 | |
9412 | /* Flushing all ASIDs flushes the current ASID... */ | |
9413 | kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
9414 | } | |
9415 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) | |
9416 | kvm_vcpu_flush_tlb_current(vcpu); | |
07ffaf34 | 9417 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) |
0baedd79 | 9418 | kvm_vcpu_flush_tlb_guest(vcpu); |
eeeb4f67 | 9419 | |
a8eeb04a | 9420 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 9421 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
9422 | r = 0; |
9423 | goto out; | |
9424 | } | |
a8eeb04a | 9425 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
cb6a32c2 SC |
9426 | if (is_guest_mode(vcpu)) { |
9427 | kvm_x86_ops.nested_ops->triple_fault(vcpu); | |
9428 | } else { | |
9429 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; | |
9430 | vcpu->mmio_needed = 0; | |
9431 | r = 0; | |
9432 | goto out; | |
9433 | } | |
71c4dfaf | 9434 | } |
af585b92 GN |
9435 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
9436 | /* Page is swapped out. Do synthetic halt */ | |
9437 | vcpu->arch.apf.halted = true; | |
9438 | r = 1; | |
9439 | goto out; | |
9440 | } | |
c9aaa895 GC |
9441 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
9442 | record_steal_time(vcpu); | |
64d60670 PB |
9443 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
9444 | process_smi(vcpu); | |
7460fb4a AK |
9445 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
9446 | process_nmi(vcpu); | |
f5132b01 | 9447 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 9448 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 9449 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 9450 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
9451 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
9452 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
9453 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 9454 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
9455 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
9456 | vcpu->run->eoi.vector = | |
9457 | vcpu->arch.pending_ioapic_eoi; | |
9458 | r = 0; | |
9459 | goto out; | |
9460 | } | |
9461 | } | |
3d81bc7e YZ |
9462 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
9463 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
9464 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
9465 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
9466 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
9467 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
9468 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
9469 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
9470 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
9471 | r = 0; | |
9472 | goto out; | |
9473 | } | |
e516cebb AS |
9474 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
9475 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
9476 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
9477 | r = 0; | |
9478 | goto out; | |
9479 | } | |
db397571 | 9480 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
9ff5e030 VK |
9481 | struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); |
9482 | ||
db397571 | 9483 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; |
9ff5e030 | 9484 | vcpu->run->hyperv = hv_vcpu->exit; |
db397571 AS |
9485 | r = 0; |
9486 | goto out; | |
9487 | } | |
f3b138c5 AS |
9488 | |
9489 | /* | |
9490 | * KVM_REQ_HV_STIMER has to be processed after | |
9491 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
9492 | * depend on the guest clock being up-to-date | |
9493 | */ | |
1f4b34f8 AS |
9494 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
9495 | kvm_hv_process_stimers(vcpu); | |
8df14af4 SS |
9496 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
9497 | kvm_vcpu_update_apicv(vcpu); | |
557a961a VK |
9498 | if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) |
9499 | kvm_check_async_pf_completion(vcpu); | |
1a155254 | 9500 | if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) |
b3646477 | 9501 | static_call(kvm_x86_msr_filter_changed)(vcpu); |
a85863c2 MS |
9502 | |
9503 | if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) | |
9504 | static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); | |
2f52d58c | 9505 | } |
b93463aa | 9506 | |
40da8ccd DW |
9507 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || |
9508 | kvm_xen_has_interrupt(vcpu)) { | |
0f1e261e | 9509 | ++vcpu->stat.req_event; |
4fe09bcf JM |
9510 | r = kvm_apic_accept_events(vcpu); |
9511 | if (r < 0) { | |
9512 | r = 0; | |
9513 | goto out; | |
9514 | } | |
66450a21 JK |
9515 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
9516 | r = 1; | |
9517 | goto out; | |
9518 | } | |
9519 | ||
a5f6909a JM |
9520 | r = inject_pending_event(vcpu, &req_immediate_exit); |
9521 | if (r < 0) { | |
9522 | r = 0; | |
9523 | goto out; | |
9524 | } | |
c9d40913 | 9525 | if (req_int_win) |
b3646477 | 9526 | static_call(kvm_x86_enable_irq_window)(vcpu); |
b463a6f7 AK |
9527 | |
9528 | if (kvm_lapic_enabled(vcpu)) { | |
9529 | update_cr8_intercept(vcpu); | |
9530 | kvm_lapic_sync_to_vapic(vcpu); | |
9531 | } | |
9532 | } | |
9533 | ||
d8368af8 AK |
9534 | r = kvm_mmu_reload(vcpu); |
9535 | if (unlikely(r)) { | |
d905c069 | 9536 | goto cancel_injection; |
d8368af8 AK |
9537 | } |
9538 | ||
b6c7a5dc HB |
9539 | preempt_disable(); |
9540 | ||
b3646477 | 9541 | static_call(kvm_x86_prepare_guest_switch)(vcpu); |
b95234c8 PB |
9542 | |
9543 | /* | |
9544 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
9545 | * IPI are then delayed after guest entry, which ensures that they | |
9546 | * result in virtual interrupt delivery. | |
9547 | */ | |
9548 | local_irq_disable(); | |
6b7e2d09 XG |
9549 | vcpu->mode = IN_GUEST_MODE; |
9550 | ||
01b71917 MT |
9551 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
9552 | ||
0f127d12 | 9553 | /* |
b95234c8 | 9554 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 9555 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 9556 | * |
81b01667 | 9557 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
9558 | * pairs with the memory barrier implicit in pi_test_and_set_on |
9559 | * (see vmx_deliver_posted_interrupt). | |
9560 | * | |
9561 | * 3) This also orders the write to mode from any reads to the page | |
9562 | * tables done while the VCPU is running. Please see the comment | |
9563 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 9564 | */ |
01b71917 | 9565 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 9566 | |
b95234c8 PB |
9567 | /* |
9568 | * This handles the case where a posted interrupt was | |
9569 | * notified with kvm_vcpu_kick. | |
9570 | */ | |
fa59cc00 | 9571 | if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) |
b3646477 | 9572 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
32f88400 | 9573 | |
5a9f5443 | 9574 | if (kvm_vcpu_exit_request(vcpu)) { |
6b7e2d09 | 9575 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9576 | smp_wmb(); |
6c142801 AK |
9577 | local_irq_enable(); |
9578 | preempt_enable(); | |
01b71917 | 9579 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 9580 | r = 1; |
d905c069 | 9581 | goto cancel_injection; |
6c142801 AK |
9582 | } |
9583 | ||
c43203ca PB |
9584 | if (req_immediate_exit) { |
9585 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 9586 | static_call(kvm_x86_request_immediate_exit)(vcpu); |
c43203ca | 9587 | } |
d6185f20 | 9588 | |
2620fe26 SC |
9589 | fpregs_assert_state_consistent(); |
9590 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9591 | switch_fpu_return(); | |
5f409e20 | 9592 | |
42dbaa5a | 9593 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
9594 | set_debugreg(0, 7); |
9595 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
9596 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
9597 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
9598 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
f85d4016 LJ |
9599 | } else if (unlikely(hw_breakpoint_active())) { |
9600 | set_debugreg(0, 7); | |
42dbaa5a | 9601 | } |
b6c7a5dc | 9602 | |
d89d04ab PB |
9603 | for (;;) { |
9604 | exit_fastpath = static_call(kvm_x86_run)(vcpu); | |
9605 | if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) | |
9606 | break; | |
9607 | ||
9608 | if (unlikely(kvm_vcpu_exit_request(vcpu))) { | |
9609 | exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; | |
9610 | break; | |
9611 | } | |
9612 | ||
9613 | if (vcpu->arch.apicv_active) | |
9614 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); | |
9615 | } | |
b6c7a5dc | 9616 | |
c77fb5fe PB |
9617 | /* |
9618 | * Do this here before restoring debug registers on the host. And | |
9619 | * since we do this before handling the vmexit, a DR access vmexit | |
9620 | * can (a) read the correct value of the debug registers, (b) set | |
9621 | * KVM_DEBUGREG_WONT_EXIT again. | |
9622 | */ | |
9623 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe | 9624 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
b3646477 | 9625 | static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); |
70e4da7a | 9626 | kvm_update_dr0123(vcpu); |
70e4da7a | 9627 | kvm_update_dr7(vcpu); |
c77fb5fe PB |
9628 | } |
9629 | ||
24f1e32c FW |
9630 | /* |
9631 | * If the guest has used debug registers, at least dr7 | |
9632 | * will be disabled while returning to the host. | |
9633 | * If we don't have active breakpoints in the host, we don't | |
9634 | * care about the messed up debug address registers. But if | |
9635 | * we have some of them active, restore the old state. | |
9636 | */ | |
59d8eb53 | 9637 | if (hw_breakpoint_active()) |
24f1e32c | 9638 | hw_breakpoint_restore(); |
42dbaa5a | 9639 | |
c967118d | 9640 | vcpu->arch.last_vmentry_cpu = vcpu->cpu; |
4ba76538 | 9641 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 9642 | |
6b7e2d09 | 9643 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9644 | smp_wmb(); |
a547c6db | 9645 | |
b3646477 | 9646 | static_call(kvm_x86_handle_exit_irqoff)(vcpu); |
b6c7a5dc | 9647 | |
d7a08882 SC |
9648 | /* |
9649 | * Consume any pending interrupts, including the possible source of | |
9650 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
9651 | * An instruction is required after local_irq_enable() to fully unblock | |
9652 | * interrupts on processors that implement an interrupt shadow, the | |
9653 | * stat.exits increment will do nicely. | |
9654 | */ | |
9655 | kvm_before_interrupt(vcpu); | |
9656 | local_irq_enable(); | |
b6c7a5dc | 9657 | ++vcpu->stat.exits; |
d7a08882 SC |
9658 | local_irq_disable(); |
9659 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 9660 | |
16045714 WL |
9661 | /* |
9662 | * Wait until after servicing IRQs to account guest time so that any | |
9663 | * ticks that occurred while running the guest are properly accounted | |
9664 | * to the guest. Waiting until IRQs are enabled degrades the accuracy | |
9665 | * of accounting via context tracking, but the loss of accuracy is | |
9666 | * acceptable for all known use cases. | |
9667 | */ | |
9668 | vtime_account_guest_exit(); | |
9669 | ||
ec0671d5 WL |
9670 | if (lapic_in_kernel(vcpu)) { |
9671 | s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; | |
9672 | if (delta != S64_MIN) { | |
9673 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); | |
9674 | vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; | |
9675 | } | |
9676 | } | |
b6c7a5dc | 9677 | |
f2485b3e | 9678 | local_irq_enable(); |
b6c7a5dc HB |
9679 | preempt_enable(); |
9680 | ||
f656ce01 | 9681 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 9682 | |
b6c7a5dc HB |
9683 | /* |
9684 | * Profile KVM exit RIPs: | |
9685 | */ | |
9686 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
9687 | unsigned long rip = kvm_rip_read(vcpu); |
9688 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
9689 | } |
9690 | ||
cc578287 ZA |
9691 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
9692 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 9693 | |
5cfb1d5a MT |
9694 | if (vcpu->arch.apic_attention) |
9695 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 9696 | |
b3646477 | 9697 | r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); |
d905c069 MT |
9698 | return r; |
9699 | ||
9700 | cancel_injection: | |
8081ad06 SC |
9701 | if (req_immediate_exit) |
9702 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 9703 | static_call(kvm_x86_cancel_injection)(vcpu); |
ae7a2a3f MT |
9704 | if (unlikely(vcpu->arch.apic_attention)) |
9705 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
9706 | out: |
9707 | return r; | |
9708 | } | |
b6c7a5dc | 9709 | |
362c698f PB |
9710 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
9711 | { | |
bf9f6ac8 | 9712 | if (!kvm_arch_vcpu_runnable(vcpu) && |
b3646477 | 9713 | (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { |
9c8fd1ba PB |
9714 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
9715 | kvm_vcpu_block(vcpu); | |
9716 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 | 9717 | |
afaf0b2f | 9718 | if (kvm_x86_ops.post_block) |
b3646477 | 9719 | static_call(kvm_x86_post_block)(vcpu); |
bf9f6ac8 | 9720 | |
9c8fd1ba PB |
9721 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
9722 | return 1; | |
9723 | } | |
362c698f | 9724 | |
4fe09bcf JM |
9725 | if (kvm_apic_accept_events(vcpu) < 0) |
9726 | return 0; | |
362c698f PB |
9727 | switch(vcpu->arch.mp_state) { |
9728 | case KVM_MP_STATE_HALTED: | |
647daca2 | 9729 | case KVM_MP_STATE_AP_RESET_HOLD: |
362c698f PB |
9730 | vcpu->arch.pv.pv_unhalted = false; |
9731 | vcpu->arch.mp_state = | |
9732 | KVM_MP_STATE_RUNNABLE; | |
df561f66 | 9733 | fallthrough; |
362c698f PB |
9734 | case KVM_MP_STATE_RUNNABLE: |
9735 | vcpu->arch.apf.halted = false; | |
9736 | break; | |
9737 | case KVM_MP_STATE_INIT_RECEIVED: | |
9738 | break; | |
9739 | default: | |
9740 | return -EINTR; | |
362c698f PB |
9741 | } |
9742 | return 1; | |
9743 | } | |
09cec754 | 9744 | |
5d9bc648 PB |
9745 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
9746 | { | |
56083bdf | 9747 | if (is_guest_mode(vcpu)) |
cb6a32c2 | 9748 | kvm_check_nested_events(vcpu); |
0ad3bed6 | 9749 | |
5d9bc648 PB |
9750 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
9751 | !vcpu->arch.apf.halted); | |
9752 | } | |
9753 | ||
362c698f | 9754 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
9755 | { |
9756 | int r; | |
f656ce01 | 9757 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 9758 | |
f656ce01 | 9759 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
c595ceee | 9760 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 9761 | |
362c698f | 9762 | for (;;) { |
58f800d5 | 9763 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 9764 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 9765 | } else { |
362c698f | 9766 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
9767 | } |
9768 | ||
09cec754 GN |
9769 | if (r <= 0) |
9770 | break; | |
9771 | ||
084071d5 | 9772 | kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); |
09cec754 GN |
9773 | if (kvm_cpu_has_pending_timer(vcpu)) |
9774 | kvm_inject_pending_timer_irqs(vcpu); | |
9775 | ||
782d422b MG |
9776 | if (dm_request_for_irq_injection(vcpu) && |
9777 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
9778 | r = 0; |
9779 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 9780 | ++vcpu->stat.request_irq_exits; |
362c698f | 9781 | break; |
09cec754 | 9782 | } |
af585b92 | 9783 | |
f3020b88 | 9784 | if (__xfer_to_guest_mode_work_pending()) { |
f656ce01 | 9785 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
72c3c0fe TG |
9786 | r = xfer_to_guest_mode_handle_work(vcpu); |
9787 | if (r) | |
9788 | return r; | |
f656ce01 | 9789 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 9790 | } |
b6c7a5dc HB |
9791 | } |
9792 | ||
f656ce01 | 9793 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
9794 | |
9795 | return r; | |
9796 | } | |
9797 | ||
716d51ab GN |
9798 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
9799 | { | |
9800 | int r; | |
60fc3d02 | 9801 | |
716d51ab | 9802 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
0ce97a2b | 9803 | r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab | 9804 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
60fc3d02 | 9805 | return r; |
716d51ab GN |
9806 | } |
9807 | ||
9808 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
9809 | { | |
9810 | BUG_ON(!vcpu->arch.pio.count); | |
9811 | ||
9812 | return complete_emulated_io(vcpu); | |
9813 | } | |
9814 | ||
f78146b0 AK |
9815 | /* |
9816 | * Implements the following, as a state machine: | |
9817 | * | |
9818 | * read: | |
9819 | * for each fragment | |
87da7e66 XG |
9820 | * for each mmio piece in the fragment |
9821 | * write gpa, len | |
9822 | * exit | |
9823 | * copy data | |
f78146b0 AK |
9824 | * execute insn |
9825 | * | |
9826 | * write: | |
9827 | * for each fragment | |
87da7e66 XG |
9828 | * for each mmio piece in the fragment |
9829 | * write gpa, len | |
9830 | * copy data | |
9831 | * exit | |
f78146b0 | 9832 | */ |
716d51ab | 9833 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
9834 | { |
9835 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 9836 | struct kvm_mmio_fragment *frag; |
87da7e66 | 9837 | unsigned len; |
5287f194 | 9838 | |
716d51ab | 9839 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 9840 | |
716d51ab | 9841 | /* Complete previous fragment */ |
87da7e66 XG |
9842 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
9843 | len = min(8u, frag->len); | |
716d51ab | 9844 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
9845 | memcpy(frag->data, run->mmio.data, len); |
9846 | ||
9847 | if (frag->len <= 8) { | |
9848 | /* Switch to the next fragment. */ | |
9849 | frag++; | |
9850 | vcpu->mmio_cur_fragment++; | |
9851 | } else { | |
9852 | /* Go forward to the next mmio piece. */ | |
9853 | frag->data += len; | |
9854 | frag->gpa += len; | |
9855 | frag->len -= len; | |
9856 | } | |
9857 | ||
a08d3b3b | 9858 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 9859 | vcpu->mmio_needed = 0; |
0912c977 PB |
9860 | |
9861 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 9862 | if (vcpu->mmio_is_write) |
716d51ab GN |
9863 | return 1; |
9864 | vcpu->mmio_read_completed = 1; | |
9865 | return complete_emulated_io(vcpu); | |
9866 | } | |
87da7e66 | 9867 | |
716d51ab GN |
9868 | run->exit_reason = KVM_EXIT_MMIO; |
9869 | run->mmio.phys_addr = frag->gpa; | |
9870 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
9871 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
9872 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
9873 | run->mmio.is_write = vcpu->mmio_is_write; |
9874 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
9875 | return 0; | |
5287f194 AK |
9876 | } |
9877 | ||
c9aef3b8 SC |
9878 | static void kvm_save_current_fpu(struct fpu *fpu) |
9879 | { | |
9880 | /* | |
9881 | * If the target FPU state is not resident in the CPU registers, just | |
9882 | * memcpy() from current, else save CPU state directly to the target. | |
9883 | */ | |
9884 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9885 | memcpy(&fpu->state, ¤t->thread.fpu.state, | |
9886 | fpu_kernel_xstate_size); | |
9887 | else | |
ebe7234b | 9888 | save_fpregs_to_fpstate(fpu); |
c9aef3b8 SC |
9889 | } |
9890 | ||
822f312d SAS |
9891 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
9892 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
9893 | { | |
5f409e20 RR |
9894 | fpregs_lock(); |
9895 | ||
c9aef3b8 SC |
9896 | kvm_save_current_fpu(vcpu->arch.user_fpu); |
9897 | ||
ed02b213 TL |
9898 | /* |
9899 | * Guests with protected state can't have it set by the hypervisor, | |
9900 | * so skip trying to set it. | |
9901 | */ | |
9902 | if (vcpu->arch.guest_fpu) | |
9903 | /* PKRU is separately restored in kvm_x86_ops.run. */ | |
1c61fada | 9904 | __restore_fpregs_from_fpstate(&vcpu->arch.guest_fpu->state, |
ed02b213 | 9905 | ~XFEATURE_MASK_PKRU); |
5f409e20 RR |
9906 | |
9907 | fpregs_mark_activate(); | |
9908 | fpregs_unlock(); | |
9909 | ||
822f312d SAS |
9910 | trace_kvm_fpu(1); |
9911 | } | |
9912 | ||
9913 | /* When vcpu_run ends, restore user space FPU context. */ | |
9914 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
9915 | { | |
5f409e20 RR |
9916 | fpregs_lock(); |
9917 | ||
ed02b213 TL |
9918 | /* |
9919 | * Guests with protected state can't have it read by the hypervisor, | |
9920 | * so skip trying to save it. | |
9921 | */ | |
9922 | if (vcpu->arch.guest_fpu) | |
9923 | kvm_save_current_fpu(vcpu->arch.guest_fpu); | |
c9aef3b8 | 9924 | |
1c61fada | 9925 | restore_fpregs_from_fpstate(&vcpu->arch.user_fpu->state); |
5f409e20 RR |
9926 | |
9927 | fpregs_mark_activate(); | |
9928 | fpregs_unlock(); | |
9929 | ||
822f312d SAS |
9930 | ++vcpu->stat.fpu_reload; |
9931 | trace_kvm_fpu(0); | |
9932 | } | |
9933 | ||
1b94f6f8 | 9934 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) |
b6c7a5dc | 9935 | { |
1b94f6f8 | 9936 | struct kvm_run *kvm_run = vcpu->run; |
b6c7a5dc | 9937 | int r; |
b6c7a5dc | 9938 | |
accb757d | 9939 | vcpu_load(vcpu); |
20b7035c | 9940 | kvm_sigset_activate(vcpu); |
15aad3be | 9941 | kvm_run->flags = 0; |
5663d8f9 PX |
9942 | kvm_load_guest_fpu(vcpu); |
9943 | ||
a4535290 | 9944 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
9945 | if (kvm_run->immediate_exit) { |
9946 | r = -EINTR; | |
9947 | goto out; | |
9948 | } | |
b6c7a5dc | 9949 | kvm_vcpu_block(vcpu); |
4fe09bcf JM |
9950 | if (kvm_apic_accept_events(vcpu) < 0) { |
9951 | r = 0; | |
9952 | goto out; | |
9953 | } | |
72875d8a | 9954 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 9955 | r = -EAGAIN; |
a0595000 JS |
9956 | if (signal_pending(current)) { |
9957 | r = -EINTR; | |
1b94f6f8 | 9958 | kvm_run->exit_reason = KVM_EXIT_INTR; |
a0595000 JS |
9959 | ++vcpu->stat.signal_exits; |
9960 | } | |
ac9f6dc0 | 9961 | goto out; |
b6c7a5dc HB |
9962 | } |
9963 | ||
e489a4a6 SC |
9964 | if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || |
9965 | (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { | |
01643c51 KH |
9966 | r = -EINVAL; |
9967 | goto out; | |
9968 | } | |
9969 | ||
1b94f6f8 | 9970 | if (kvm_run->kvm_dirty_regs) { |
01643c51 KH |
9971 | r = sync_regs(vcpu); |
9972 | if (r != 0) | |
9973 | goto out; | |
9974 | } | |
9975 | ||
b6c7a5dc | 9976 | /* re-sync apic's tpr */ |
35754c98 | 9977 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
9978 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
9979 | r = -EINVAL; | |
9980 | goto out; | |
9981 | } | |
9982 | } | |
b6c7a5dc | 9983 | |
716d51ab GN |
9984 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
9985 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
9986 | vcpu->arch.complete_userspace_io = NULL; | |
9987 | r = cui(vcpu); | |
9988 | if (r <= 0) | |
5663d8f9 | 9989 | goto out; |
716d51ab GN |
9990 | } else |
9991 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 9992 | |
460df4c1 PB |
9993 | if (kvm_run->immediate_exit) |
9994 | r = -EINTR; | |
9995 | else | |
9996 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
9997 | |
9998 | out: | |
5663d8f9 | 9999 | kvm_put_guest_fpu(vcpu); |
1b94f6f8 | 10000 | if (kvm_run->kvm_valid_regs) |
01643c51 | 10001 | store_regs(vcpu); |
f1d86e46 | 10002 | post_kvm_run_save(vcpu); |
20b7035c | 10003 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 10004 | |
accb757d | 10005 | vcpu_put(vcpu); |
b6c7a5dc HB |
10006 | return r; |
10007 | } | |
10008 | ||
01643c51 | 10009 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 10010 | { |
7ae441ea GN |
10011 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
10012 | /* | |
10013 | * We are here if userspace calls get_regs() in the middle of | |
10014 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 10015 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
10016 | * that usually, but some bad designed PV devices (vmware |
10017 | * backdoor interface) need this to work | |
10018 | */ | |
c9b8b07c | 10019 | emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); |
7ae441ea GN |
10020 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
10021 | } | |
de3cd117 SC |
10022 | regs->rax = kvm_rax_read(vcpu); |
10023 | regs->rbx = kvm_rbx_read(vcpu); | |
10024 | regs->rcx = kvm_rcx_read(vcpu); | |
10025 | regs->rdx = kvm_rdx_read(vcpu); | |
10026 | regs->rsi = kvm_rsi_read(vcpu); | |
10027 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 10028 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 10029 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 10030 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
10031 | regs->r8 = kvm_r8_read(vcpu); |
10032 | regs->r9 = kvm_r9_read(vcpu); | |
10033 | regs->r10 = kvm_r10_read(vcpu); | |
10034 | regs->r11 = kvm_r11_read(vcpu); | |
10035 | regs->r12 = kvm_r12_read(vcpu); | |
10036 | regs->r13 = kvm_r13_read(vcpu); | |
10037 | regs->r14 = kvm_r14_read(vcpu); | |
10038 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
10039 | #endif |
10040 | ||
5fdbf976 | 10041 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 10042 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 10043 | } |
b6c7a5dc | 10044 | |
01643c51 KH |
10045 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
10046 | { | |
10047 | vcpu_load(vcpu); | |
10048 | __get_regs(vcpu, regs); | |
1fc9b76b | 10049 | vcpu_put(vcpu); |
b6c7a5dc HB |
10050 | return 0; |
10051 | } | |
10052 | ||
01643c51 | 10053 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 10054 | { |
7ae441ea GN |
10055 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
10056 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
10057 | ||
de3cd117 SC |
10058 | kvm_rax_write(vcpu, regs->rax); |
10059 | kvm_rbx_write(vcpu, regs->rbx); | |
10060 | kvm_rcx_write(vcpu, regs->rcx); | |
10061 | kvm_rdx_write(vcpu, regs->rdx); | |
10062 | kvm_rsi_write(vcpu, regs->rsi); | |
10063 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 10064 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 10065 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 10066 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
10067 | kvm_r8_write(vcpu, regs->r8); |
10068 | kvm_r9_write(vcpu, regs->r9); | |
10069 | kvm_r10_write(vcpu, regs->r10); | |
10070 | kvm_r11_write(vcpu, regs->r11); | |
10071 | kvm_r12_write(vcpu, regs->r12); | |
10072 | kvm_r13_write(vcpu, regs->r13); | |
10073 | kvm_r14_write(vcpu, regs->r14); | |
10074 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
10075 | #endif |
10076 | ||
5fdbf976 | 10077 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 10078 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 10079 | |
b4f14abd JK |
10080 | vcpu->arch.exception.pending = false; |
10081 | ||
3842d135 | 10082 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 10083 | } |
3842d135 | 10084 | |
01643c51 KH |
10085 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
10086 | { | |
10087 | vcpu_load(vcpu); | |
10088 | __set_regs(vcpu, regs); | |
875656fe | 10089 | vcpu_put(vcpu); |
b6c7a5dc HB |
10090 | return 0; |
10091 | } | |
10092 | ||
b6c7a5dc HB |
10093 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
10094 | { | |
10095 | struct kvm_segment cs; | |
10096 | ||
3e6e0aab | 10097 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
10098 | *db = cs.db; |
10099 | *l = cs.l; | |
10100 | } | |
10101 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
10102 | ||
6dba9403 | 10103 | static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 10104 | { |
89a27f4d | 10105 | struct desc_ptr dt; |
b6c7a5dc | 10106 | |
5265713a TL |
10107 | if (vcpu->arch.guest_state_protected) |
10108 | goto skip_protected_regs; | |
10109 | ||
3e6e0aab GT |
10110 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
10111 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
10112 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
10113 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
10114 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
10115 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 10116 | |
3e6e0aab GT |
10117 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
10118 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 10119 | |
b3646477 | 10120 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
89a27f4d GN |
10121 | sregs->idt.limit = dt.size; |
10122 | sregs->idt.base = dt.address; | |
b3646477 | 10123 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
89a27f4d GN |
10124 | sregs->gdt.limit = dt.size; |
10125 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 10126 | |
ad312c7c | 10127 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 10128 | sregs->cr3 = kvm_read_cr3(vcpu); |
5265713a TL |
10129 | |
10130 | skip_protected_regs: | |
10131 | sregs->cr0 = kvm_read_cr0(vcpu); | |
fc78f519 | 10132 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 10133 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 10134 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc | 10135 | sregs->apic_base = kvm_get_apic_base(vcpu); |
6dba9403 | 10136 | } |
b6c7a5dc | 10137 | |
6dba9403 ML |
10138 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
10139 | { | |
10140 | __get_sregs_common(vcpu, sregs); | |
10141 | ||
10142 | if (vcpu->arch.guest_state_protected) | |
10143 | return; | |
b6c7a5dc | 10144 | |
04140b41 | 10145 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
10146 | set_bit(vcpu->arch.interrupt.nr, |
10147 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 10148 | } |
16d7a191 | 10149 | |
6dba9403 ML |
10150 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
10151 | { | |
10152 | int i; | |
10153 | ||
10154 | __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); | |
10155 | ||
10156 | if (vcpu->arch.guest_state_protected) | |
10157 | return; | |
10158 | ||
10159 | if (is_pae_paging(vcpu)) { | |
10160 | for (i = 0 ; i < 4 ; i++) | |
10161 | sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); | |
10162 | sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
10163 | } | |
10164 | } | |
10165 | ||
01643c51 KH |
10166 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
10167 | struct kvm_sregs *sregs) | |
10168 | { | |
10169 | vcpu_load(vcpu); | |
10170 | __get_sregs(vcpu, sregs); | |
bcdec41c | 10171 | vcpu_put(vcpu); |
b6c7a5dc HB |
10172 | return 0; |
10173 | } | |
10174 | ||
62d9f0db MT |
10175 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
10176 | struct kvm_mp_state *mp_state) | |
10177 | { | |
4fe09bcf JM |
10178 | int r; |
10179 | ||
fd232561 | 10180 | vcpu_load(vcpu); |
f958bd23 SC |
10181 | if (kvm_mpx_supported()) |
10182 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 10183 | |
4fe09bcf JM |
10184 | r = kvm_apic_accept_events(vcpu); |
10185 | if (r < 0) | |
10186 | goto out; | |
10187 | r = 0; | |
10188 | ||
647daca2 TL |
10189 | if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || |
10190 | vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && | |
10191 | vcpu->arch.pv.pv_unhalted) | |
6aef266c SV |
10192 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; |
10193 | else | |
10194 | mp_state->mp_state = vcpu->arch.mp_state; | |
10195 | ||
4fe09bcf | 10196 | out: |
f958bd23 SC |
10197 | if (kvm_mpx_supported()) |
10198 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 10199 | vcpu_put(vcpu); |
4fe09bcf | 10200 | return r; |
62d9f0db MT |
10201 | } |
10202 | ||
10203 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
10204 | struct kvm_mp_state *mp_state) | |
10205 | { | |
e83dff5e CD |
10206 | int ret = -EINVAL; |
10207 | ||
10208 | vcpu_load(vcpu); | |
10209 | ||
bce87cce | 10210 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 10211 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 10212 | goto out; |
66450a21 | 10213 | |
27cbe7d6 LA |
10214 | /* |
10215 | * KVM_MP_STATE_INIT_RECEIVED means the processor is in | |
10216 | * INIT state; latched init should be reported using | |
10217 | * KVM_SET_VCPU_EVENTS, so reject it here. | |
10218 | */ | |
10219 | if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && | |
28bf2888 DH |
10220 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
10221 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 10222 | goto out; |
28bf2888 | 10223 | |
66450a21 JK |
10224 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
10225 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
10226 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
10227 | } else | |
10228 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 10229 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
10230 | |
10231 | ret = 0; | |
10232 | out: | |
10233 | vcpu_put(vcpu); | |
10234 | return ret; | |
62d9f0db MT |
10235 | } |
10236 | ||
7f3d35fd KW |
10237 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
10238 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 10239 | { |
c9b8b07c | 10240 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d | 10241 | int ret; |
e01c2426 | 10242 | |
8ec4722d | 10243 | init_emulate_ctxt(vcpu); |
c697518a | 10244 | |
7f3d35fd | 10245 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 10246 | has_error_code, error_code); |
1051778f SC |
10247 | if (ret) { |
10248 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
10249 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
10250 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 10251 | return 0; |
1051778f | 10252 | } |
37817f29 | 10253 | |
9d74191a TY |
10254 | kvm_rip_write(vcpu, ctxt->eip); |
10255 | kvm_set_rflags(vcpu, ctxt->eflags); | |
60fc3d02 | 10256 | return 1; |
37817f29 IE |
10257 | } |
10258 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
10259 | ||
ee69c92b | 10260 | static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 10261 | { |
37b95951 | 10262 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
10263 | /* |
10264 | * When EFER.LME and CR0.PG are set, the processor is in | |
10265 | * 64-bit mode (though maybe in a 32-bit code segment). | |
10266 | * CR4.PAE and EFER.LMA must be set. | |
10267 | */ | |
ee69c92b SC |
10268 | if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) |
10269 | return false; | |
ca29e145 | 10270 | if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) |
c1c35cf7 | 10271 | return false; |
f2981033 LT |
10272 | } else { |
10273 | /* | |
10274 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
10275 | * segment cannot be 64-bit. | |
10276 | */ | |
10277 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
ee69c92b | 10278 | return false; |
f2981033 LT |
10279 | } |
10280 | ||
ee69c92b | 10281 | return kvm_is_valid_cr4(vcpu, sregs->cr4); |
f2981033 LT |
10282 | } |
10283 | ||
6dba9403 ML |
10284 | static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, |
10285 | int *mmu_reset_needed, bool update_pdptrs) | |
b6c7a5dc | 10286 | { |
58cb628d | 10287 | struct msr_data apic_base_msr; |
6dba9403 | 10288 | int idx; |
89a27f4d | 10289 | struct desc_ptr dt; |
b4ef9d4e | 10290 | |
ee69c92b | 10291 | if (!kvm_is_valid_sregs(vcpu, sregs)) |
6dba9403 | 10292 | return -EINVAL; |
f2981033 | 10293 | |
d3802286 JM |
10294 | apic_base_msr.data = sregs->apic_base; |
10295 | apic_base_msr.host_initiated = true; | |
10296 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
6dba9403 | 10297 | return -EINVAL; |
6d1068b3 | 10298 | |
5265713a | 10299 | if (vcpu->arch.guest_state_protected) |
6dba9403 | 10300 | return 0; |
5265713a | 10301 | |
89a27f4d GN |
10302 | dt.size = sregs->idt.limit; |
10303 | dt.address = sregs->idt.base; | |
b3646477 | 10304 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
89a27f4d GN |
10305 | dt.size = sregs->gdt.limit; |
10306 | dt.address = sregs->gdt.base; | |
b3646477 | 10307 | static_call(kvm_x86_set_gdt)(vcpu, &dt); |
b6c7a5dc | 10308 | |
ad312c7c | 10309 | vcpu->arch.cr2 = sregs->cr2; |
6dba9403 | 10310 | *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 10311 | vcpu->arch.cr3 = sregs->cr3; |
cb3c1e2f | 10312 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
b6c7a5dc | 10313 | |
2d3ad1f4 | 10314 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 10315 | |
6dba9403 | 10316 | *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b3646477 | 10317 | static_call(kvm_x86_set_efer)(vcpu, sregs->efer); |
b6c7a5dc | 10318 | |
6dba9403 | 10319 | *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b3646477 | 10320 | static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); |
d7306163 | 10321 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 10322 | |
6dba9403 | 10323 | *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b3646477 | 10324 | static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); |
63f42e02 | 10325 | |
6dba9403 ML |
10326 | if (update_pdptrs) { |
10327 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
10328 | if (is_pae_paging(vcpu)) { | |
10329 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); | |
10330 | *mmu_reset_needed = 1; | |
10331 | } | |
10332 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
7c93be44 | 10333 | } |
b6c7a5dc | 10334 | |
3e6e0aab GT |
10335 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
10336 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
10337 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
10338 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
10339 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
10340 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 10341 | |
3e6e0aab GT |
10342 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
10343 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 10344 | |
5f0269f5 ME |
10345 | update_cr8_intercept(vcpu); |
10346 | ||
9c3e4aab | 10347 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 10348 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 10349 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 10350 | !is_protmode(vcpu)) |
9c3e4aab MT |
10351 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
10352 | ||
6dba9403 ML |
10353 | return 0; |
10354 | } | |
10355 | ||
10356 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
10357 | { | |
10358 | int pending_vec, max_bits; | |
10359 | int mmu_reset_needed = 0; | |
10360 | int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); | |
10361 | ||
10362 | if (ret) | |
10363 | return ret; | |
10364 | ||
10365 | if (mmu_reset_needed) | |
10366 | kvm_mmu_reset_context(vcpu); | |
10367 | ||
5265713a TL |
10368 | max_bits = KVM_NR_INTERRUPTS; |
10369 | pending_vec = find_first_bit( | |
10370 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
6dba9403 | 10371 | |
5265713a TL |
10372 | if (pending_vec < max_bits) { |
10373 | kvm_queue_interrupt(vcpu, pending_vec, false); | |
10374 | pr_debug("Set back pending irq %d\n", pending_vec); | |
6dba9403 | 10375 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5265713a | 10376 | } |
6dba9403 ML |
10377 | return 0; |
10378 | } | |
5265713a | 10379 | |
6dba9403 ML |
10380 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
10381 | { | |
10382 | int mmu_reset_needed = 0; | |
10383 | bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
10384 | bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && | |
10385 | !(sregs2->efer & EFER_LMA); | |
10386 | int i, ret; | |
3842d135 | 10387 | |
6dba9403 ML |
10388 | if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) |
10389 | return -EINVAL; | |
10390 | ||
10391 | if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) | |
10392 | return -EINVAL; | |
10393 | ||
10394 | ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, | |
10395 | &mmu_reset_needed, !valid_pdptrs); | |
10396 | if (ret) | |
10397 | return ret; | |
10398 | ||
10399 | if (valid_pdptrs) { | |
10400 | for (i = 0; i < 4 ; i++) | |
10401 | kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); | |
10402 | ||
10403 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); | |
10404 | mmu_reset_needed = 1; | |
158a48ec | 10405 | vcpu->arch.pdptrs_from_userspace = true; |
6dba9403 ML |
10406 | } |
10407 | if (mmu_reset_needed) | |
10408 | kvm_mmu_reset_context(vcpu); | |
10409 | return 0; | |
01643c51 KH |
10410 | } |
10411 | ||
10412 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
10413 | struct kvm_sregs *sregs) | |
10414 | { | |
10415 | int ret; | |
10416 | ||
10417 | vcpu_load(vcpu); | |
10418 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
10419 | vcpu_put(vcpu); |
10420 | return ret; | |
b6c7a5dc HB |
10421 | } |
10422 | ||
d0bfb940 JK |
10423 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
10424 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 10425 | { |
355be0b9 | 10426 | unsigned long rflags; |
ae675ef0 | 10427 | int i, r; |
b6c7a5dc | 10428 | |
8d4846b9 TL |
10429 | if (vcpu->arch.guest_state_protected) |
10430 | return -EINVAL; | |
10431 | ||
66b56562 CD |
10432 | vcpu_load(vcpu); |
10433 | ||
4f926bf2 JK |
10434 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
10435 | r = -EBUSY; | |
10436 | if (vcpu->arch.exception.pending) | |
2122ff5e | 10437 | goto out; |
4f926bf2 JK |
10438 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
10439 | kvm_queue_exception(vcpu, DB_VECTOR); | |
10440 | else | |
10441 | kvm_queue_exception(vcpu, BP_VECTOR); | |
10442 | } | |
10443 | ||
91586a3b JK |
10444 | /* |
10445 | * Read rflags as long as potentially injected trace flags are still | |
10446 | * filtered out. | |
10447 | */ | |
10448 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
10449 | |
10450 | vcpu->guest_debug = dbg->control; | |
10451 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
10452 | vcpu->guest_debug = 0; | |
10453 | ||
10454 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
10455 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
10456 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 10457 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
10458 | } else { |
10459 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
10460 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 10461 | } |
c8639010 | 10462 | kvm_update_dr7(vcpu); |
ae675ef0 | 10463 | |
f92653ee | 10464 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
e87e46d5 | 10465 | vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); |
94fe45da | 10466 | |
91586a3b JK |
10467 | /* |
10468 | * Trigger an rflags update that will inject or remove the trace | |
10469 | * flags. | |
10470 | */ | |
10471 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 10472 | |
b3646477 | 10473 | static_call(kvm_x86_update_exception_bitmap)(vcpu); |
b6c7a5dc | 10474 | |
4f926bf2 | 10475 | r = 0; |
d0bfb940 | 10476 | |
2122ff5e | 10477 | out: |
66b56562 | 10478 | vcpu_put(vcpu); |
b6c7a5dc HB |
10479 | return r; |
10480 | } | |
10481 | ||
8b006791 ZX |
10482 | /* |
10483 | * Translate a guest virtual address to a guest physical address. | |
10484 | */ | |
10485 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
10486 | struct kvm_translation *tr) | |
10487 | { | |
10488 | unsigned long vaddr = tr->linear_address; | |
10489 | gpa_t gpa; | |
f656ce01 | 10490 | int idx; |
8b006791 | 10491 | |
1da5b61d CD |
10492 | vcpu_load(vcpu); |
10493 | ||
f656ce01 | 10494 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 10495 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 10496 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
10497 | tr->physical_address = gpa; |
10498 | tr->valid = gpa != UNMAPPED_GVA; | |
10499 | tr->writeable = 1; | |
10500 | tr->usermode = 0; | |
8b006791 | 10501 | |
1da5b61d | 10502 | vcpu_put(vcpu); |
8b006791 ZX |
10503 | return 0; |
10504 | } | |
10505 | ||
d0752060 HB |
10506 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
10507 | { | |
1393123e | 10508 | struct fxregs_state *fxsave; |
d0752060 | 10509 | |
ed02b213 TL |
10510 | if (!vcpu->arch.guest_fpu) |
10511 | return 0; | |
10512 | ||
1393123e | 10513 | vcpu_load(vcpu); |
d0752060 | 10514 | |
b666a4b6 | 10515 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 HB |
10516 | memcpy(fpu->fpr, fxsave->st_space, 128); |
10517 | fpu->fcw = fxsave->cwd; | |
10518 | fpu->fsw = fxsave->swd; | |
10519 | fpu->ftwx = fxsave->twd; | |
10520 | fpu->last_opcode = fxsave->fop; | |
10521 | fpu->last_ip = fxsave->rip; | |
10522 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 10523 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 10524 | |
1393123e | 10525 | vcpu_put(vcpu); |
d0752060 HB |
10526 | return 0; |
10527 | } | |
10528 | ||
10529 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
10530 | { | |
6a96bc7f CD |
10531 | struct fxregs_state *fxsave; |
10532 | ||
ed02b213 TL |
10533 | if (!vcpu->arch.guest_fpu) |
10534 | return 0; | |
10535 | ||
6a96bc7f CD |
10536 | vcpu_load(vcpu); |
10537 | ||
b666a4b6 | 10538 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 | 10539 | |
d0752060 HB |
10540 | memcpy(fxsave->st_space, fpu->fpr, 128); |
10541 | fxsave->cwd = fpu->fcw; | |
10542 | fxsave->swd = fpu->fsw; | |
10543 | fxsave->twd = fpu->ftwx; | |
10544 | fxsave->fop = fpu->last_opcode; | |
10545 | fxsave->rip = fpu->last_ip; | |
10546 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 10547 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 10548 | |
6a96bc7f | 10549 | vcpu_put(vcpu); |
d0752060 HB |
10550 | return 0; |
10551 | } | |
10552 | ||
01643c51 KH |
10553 | static void store_regs(struct kvm_vcpu *vcpu) |
10554 | { | |
10555 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
10556 | ||
10557 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
10558 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
10559 | ||
10560 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
10561 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
10562 | ||
10563 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
10564 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
10565 | vcpu, &vcpu->run->s.regs.events); | |
10566 | } | |
10567 | ||
10568 | static int sync_regs(struct kvm_vcpu *vcpu) | |
10569 | { | |
01643c51 KH |
10570 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { |
10571 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
10572 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
10573 | } | |
10574 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
10575 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
10576 | return -EINVAL; | |
10577 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
10578 | } | |
10579 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
10580 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
10581 | vcpu, &vcpu->run->s.regs.events)) | |
10582 | return -EINVAL; | |
10583 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
10584 | } | |
10585 | ||
10586 | return 0; | |
10587 | } | |
10588 | ||
0ee6a517 | 10589 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 10590 | { |
ed02b213 TL |
10591 | if (!vcpu->arch.guest_fpu) |
10592 | return; | |
10593 | ||
b666a4b6 | 10594 | fpstate_init(&vcpu->arch.guest_fpu->state); |
782511b0 | 10595 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
b666a4b6 | 10596 | vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = |
df1daba7 | 10597 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 10598 | |
2acf923e DC |
10599 | /* |
10600 | * Ensure guest xcr0 is valid for loading | |
10601 | */ | |
d91cab78 | 10602 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 10603 | |
ad312c7c | 10604 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 10605 | } |
d0752060 | 10606 | |
ed02b213 TL |
10607 | void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) |
10608 | { | |
10609 | if (vcpu->arch.guest_fpu) { | |
10610 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
10611 | vcpu->arch.guest_fpu = NULL; | |
10612 | } | |
10613 | } | |
10614 | EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); | |
10615 | ||
897cc38e | 10616 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 10617 | { |
897cc38e SC |
10618 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
10619 | pr_warn_once("kvm: SMP vm created on host with unstable TSC; " | |
10620 | "guest TSC will not be reliable\n"); | |
7f1ea208 | 10621 | |
897cc38e | 10622 | return 0; |
e9b11c17 ZX |
10623 | } |
10624 | ||
e529ef66 | 10625 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 10626 | { |
95a0d01e SC |
10627 | struct page *page; |
10628 | int r; | |
c447e76b | 10629 | |
63f5a190 SC |
10630 | vcpu->arch.last_vmentry_cpu = -1; |
10631 | ||
95a0d01e SC |
10632 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
10633 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
10634 | else | |
10635 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 10636 | |
95a0d01e SC |
10637 | r = kvm_mmu_create(vcpu); |
10638 | if (r < 0) | |
10639 | return r; | |
10640 | ||
10641 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
10642 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
10643 | if (r < 0) | |
10644 | goto fail_mmu_destroy; | |
4e19c36f SS |
10645 | if (kvm_apicv_activated(vcpu->kvm)) |
10646 | vcpu->arch.apicv_active = true; | |
95a0d01e | 10647 | } else |
6e4e3b4d | 10648 | static_branch_inc(&kvm_has_noapic_vcpu); |
95a0d01e SC |
10649 | |
10650 | r = -ENOMEM; | |
10651 | ||
93bb59ca | 10652 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); |
95a0d01e SC |
10653 | if (!page) |
10654 | goto fail_free_lapic; | |
10655 | vcpu->arch.pio_data = page_address(page); | |
10656 | ||
10657 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, | |
10658 | GFP_KERNEL_ACCOUNT); | |
10659 | if (!vcpu->arch.mce_banks) | |
10660 | goto fail_free_pio_data; | |
10661 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
10662 | ||
10663 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
10664 | GFP_KERNEL_ACCOUNT)) | |
10665 | goto fail_free_mce_banks; | |
10666 | ||
c9b8b07c SC |
10667 | if (!alloc_emulate_ctxt(vcpu)) |
10668 | goto free_wbinvd_dirty_mask; | |
10669 | ||
95a0d01e SC |
10670 | vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, |
10671 | GFP_KERNEL_ACCOUNT); | |
10672 | if (!vcpu->arch.user_fpu) { | |
10673 | pr_err("kvm: failed to allocate userspace's fpu\n"); | |
c9b8b07c | 10674 | goto free_emulate_ctxt; |
95a0d01e SC |
10675 | } |
10676 | ||
10677 | vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, | |
10678 | GFP_KERNEL_ACCOUNT); | |
10679 | if (!vcpu->arch.guest_fpu) { | |
10680 | pr_err("kvm: failed to allocate vcpu's fpu\n"); | |
10681 | goto free_user_fpu; | |
10682 | } | |
10683 | fx_init(vcpu); | |
10684 | ||
95a0d01e | 10685 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
a8ac864a | 10686 | vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); |
95a0d01e SC |
10687 | |
10688 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
10689 | ||
10690 | kvm_async_pf_hash_reset(vcpu); | |
10691 | kvm_pmu_init(vcpu); | |
10692 | ||
10693 | vcpu->arch.pending_external_vector = -1; | |
10694 | vcpu->arch.preempted_in_kernel = false; | |
10695 | ||
3c86c0d3 VP |
10696 | #if IS_ENABLED(CONFIG_HYPERV) |
10697 | vcpu->arch.hv_root_tdp = INVALID_PAGE; | |
10698 | #endif | |
10699 | ||
b3646477 | 10700 | r = static_call(kvm_x86_vcpu_create)(vcpu); |
95a0d01e SC |
10701 | if (r) |
10702 | goto free_guest_fpu; | |
e9b11c17 | 10703 | |
0cf9135b | 10704 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 10705 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
19efffa2 | 10706 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 10707 | vcpu_load(vcpu); |
1ab9287a | 10708 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
d28bc9dd | 10709 | kvm_vcpu_reset(vcpu, false); |
c9060662 | 10710 | kvm_init_mmu(vcpu); |
e9b11c17 | 10711 | vcpu_put(vcpu); |
ec7660cc | 10712 | return 0; |
95a0d01e SC |
10713 | |
10714 | free_guest_fpu: | |
ed02b213 | 10715 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10716 | free_user_fpu: |
10717 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
c9b8b07c SC |
10718 | free_emulate_ctxt: |
10719 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); | |
95a0d01e SC |
10720 | free_wbinvd_dirty_mask: |
10721 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
10722 | fail_free_mce_banks: | |
10723 | kfree(vcpu->arch.mce_banks); | |
10724 | fail_free_pio_data: | |
10725 | free_page((unsigned long)vcpu->arch.pio_data); | |
10726 | fail_free_lapic: | |
10727 | kvm_free_lapic(vcpu); | |
10728 | fail_mmu_destroy: | |
10729 | kvm_mmu_destroy(vcpu); | |
10730 | return r; | |
e9b11c17 ZX |
10731 | } |
10732 | ||
31928aa5 | 10733 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 10734 | { |
332967a3 | 10735 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 10736 | |
ec7660cc | 10737 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 10738 | return; |
ec7660cc | 10739 | vcpu_load(vcpu); |
0c899c25 | 10740 | kvm_synchronize_tsc(vcpu, 0); |
42897d86 | 10741 | vcpu_put(vcpu); |
2d5ba19b MT |
10742 | |
10743 | /* poll control enabled by default */ | |
10744 | vcpu->arch.msr_kvm_poll_control = 1; | |
10745 | ||
ec7660cc | 10746 | mutex_unlock(&vcpu->mutex); |
42897d86 | 10747 | |
b34de572 WL |
10748 | if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) |
10749 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
10750 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
10751 | } |
10752 | ||
d40ccc62 | 10753 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 10754 | { |
4cbc418a | 10755 | struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; |
95a0d01e | 10756 | int idx; |
344d9588 | 10757 | |
4cbc418a PB |
10758 | kvm_release_pfn(cache->pfn, cache->dirty, cache); |
10759 | ||
50b143e1 | 10760 | kvmclock_reset(vcpu); |
e9b11c17 | 10761 | |
b3646477 | 10762 | static_call(kvm_x86_vcpu_free)(vcpu); |
50b143e1 | 10763 | |
c9b8b07c | 10764 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); |
50b143e1 SC |
10765 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
10766 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
ed02b213 | 10767 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10768 | |
10769 | kvm_hv_vcpu_uninit(vcpu); | |
10770 | kvm_pmu_destroy(vcpu); | |
10771 | kfree(vcpu->arch.mce_banks); | |
10772 | kvm_free_lapic(vcpu); | |
10773 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
10774 | kvm_mmu_destroy(vcpu); | |
10775 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
10776 | free_page((unsigned long)vcpu->arch.pio_data); | |
255cbecf | 10777 | kvfree(vcpu->arch.cpuid_entries); |
95a0d01e | 10778 | if (!lapic_in_kernel(vcpu)) |
6e4e3b4d | 10779 | static_branch_dec(&kvm_has_noapic_vcpu); |
e9b11c17 ZX |
10780 | } |
10781 | ||
d28bc9dd | 10782 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 10783 | { |
0aa18375 | 10784 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
4c72ab5a | 10785 | unsigned long new_cr0; |
49d8665c | 10786 | u32 eax, dummy; |
0aa18375 | 10787 | |
b7e31be3 RK |
10788 | kvm_lapic_reset(vcpu, init_event); |
10789 | ||
e69fab5d PB |
10790 | vcpu->arch.hflags = 0; |
10791 | ||
c43203ca | 10792 | vcpu->arch.smi_pending = 0; |
52797bf9 | 10793 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
10794 | atomic_set(&vcpu->arch.nmi_queued, 0); |
10795 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 10796 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
10797 | kvm_clear_interrupt_queue(vcpu); |
10798 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 10799 | |
42dbaa5a | 10800 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 10801 | kvm_update_dr0123(vcpu); |
9a3ecd5e | 10802 | vcpu->arch.dr6 = DR6_ACTIVE_LOW; |
42dbaa5a | 10803 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 10804 | kvm_update_dr7(vcpu); |
42dbaa5a | 10805 | |
1119022c NA |
10806 | vcpu->arch.cr2 = 0; |
10807 | ||
3842d135 | 10808 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2635b5c4 VK |
10809 | vcpu->arch.apf.msr_en_val = 0; |
10810 | vcpu->arch.apf.msr_int_val = 0; | |
c9aaa895 | 10811 | vcpu->arch.st.msr_val = 0; |
3842d135 | 10812 | |
12f9a48f GC |
10813 | kvmclock_reset(vcpu); |
10814 | ||
af585b92 GN |
10815 | kvm_clear_async_pf_completion_queue(vcpu); |
10816 | kvm_async_pf_hash_reset(vcpu); | |
10817 | vcpu->arch.apf.halted = false; | |
3842d135 | 10818 | |
ed02b213 | 10819 | if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { |
a554d207 WL |
10820 | void *mpx_state_buffer; |
10821 | ||
10822 | /* | |
10823 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
10824 | * called with loaded FPU and does not let userspace fix the state. | |
10825 | */ | |
f775b13e RR |
10826 | if (init_event) |
10827 | kvm_put_guest_fpu(vcpu); | |
b666a4b6 | 10828 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10829 | XFEATURE_BNDREGS); |
a554d207 WL |
10830 | if (mpx_state_buffer) |
10831 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
b666a4b6 | 10832 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10833 | XFEATURE_BNDCSR); |
a554d207 WL |
10834 | if (mpx_state_buffer) |
10835 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
10836 | if (init_event) |
10837 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
10838 | } |
10839 | ||
64d60670 | 10840 | if (!init_event) { |
d28bc9dd | 10841 | kvm_pmu_reset(vcpu); |
64d60670 | 10842 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 10843 | |
db2336a8 | 10844 | vcpu->arch.msr_misc_features_enables = 0; |
a554d207 WL |
10845 | |
10846 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; | |
64d60670 | 10847 | } |
f5132b01 | 10848 | |
66f7b72e JS |
10849 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
10850 | vcpu->arch.regs_avail = ~0; | |
10851 | vcpu->arch.regs_dirty = ~0; | |
10852 | ||
49d8665c SC |
10853 | /* |
10854 | * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) | |
10855 | * if no CPUID match is found. Note, it's impossible to get a match at | |
10856 | * RESET since KVM emulates RESET before exposing the vCPU to userspace, | |
10857 | * i.e. it'simpossible for kvm_cpuid() to find a valid entry on RESET. | |
10858 | * But, go through the motions in case that's ever remedied. | |
10859 | */ | |
10860 | eax = 1; | |
10861 | if (!kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true)) | |
10862 | eax = 0x600; | |
10863 | kvm_rdx_write(vcpu, eax); | |
10864 | ||
a554d207 WL |
10865 | vcpu->arch.ia32_xss = 0; |
10866 | ||
b3646477 | 10867 | static_call(kvm_x86_vcpu_reset)(vcpu, init_event); |
0aa18375 | 10868 | |
f39e805e SC |
10869 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); |
10870 | kvm_rip_write(vcpu, 0xfff0); | |
10871 | ||
4c72ab5a SC |
10872 | /* |
10873 | * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions | |
10874 | * of Intel's SDM list CD/NW as being set on INIT, but they contradict | |
10875 | * (or qualify) that with a footnote stating that CD/NW are preserved. | |
10876 | */ | |
10877 | new_cr0 = X86_CR0_ET; | |
10878 | if (init_event) | |
10879 | new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); | |
10880 | else | |
10881 | new_cr0 |= X86_CR0_NW | X86_CR0_CD; | |
10882 | ||
10883 | static_call(kvm_x86_set_cr0)(vcpu, new_cr0); | |
f39e805e SC |
10884 | static_call(kvm_x86_set_cr4)(vcpu, 0); |
10885 | static_call(kvm_x86_set_efer)(vcpu, 0); | |
10886 | static_call(kvm_x86_update_exception_bitmap)(vcpu); | |
10887 | ||
0aa18375 SC |
10888 | /* |
10889 | * Reset the MMU context if paging was enabled prior to INIT (which is | |
10890 | * implied if CR0.PG=1 as CR0 will be '0' prior to RESET). Unlike the | |
10891 | * standard CR0/CR4/EFER modification paths, only CR0.PG needs to be | |
10892 | * checked because it is unconditionally cleared on INIT and all other | |
10893 | * paging related bits are ignored if paging is disabled, i.e. CR0.WP, | |
10894 | * CR4, and EFER changes are all irrelevant if CR0.PG was '0'. | |
10895 | */ | |
10896 | if (old_cr0 & X86_CR0_PG) | |
10897 | kvm_mmu_reset_context(vcpu); | |
df37ed38 SC |
10898 | |
10899 | /* | |
10900 | * Intel's SDM states that all TLB entries are flushed on INIT. AMD's | |
10901 | * APM states the TLBs are untouched by INIT, but it also states that | |
10902 | * the TLBs are flushed on "External initialization of the processor." | |
10903 | * Flush the guest TLB regardless of vendor, there is no meaningful | |
10904 | * benefit in relying on the guest to flush the TLB immediately after | |
10905 | * INIT. A spurious TLB flush is benign and likely negligible from a | |
10906 | * performance perspective. | |
10907 | */ | |
10908 | if (init_event) | |
10909 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
e9b11c17 | 10910 | } |
265e4353 | 10911 | EXPORT_SYMBOL_GPL(kvm_vcpu_reset); |
e9b11c17 | 10912 | |
2b4a273b | 10913 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
10914 | { |
10915 | struct kvm_segment cs; | |
10916 | ||
10917 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
10918 | cs.selector = vector << 8; | |
10919 | cs.base = vector << 12; | |
10920 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
10921 | kvm_rip_write(vcpu, 0); | |
e9b11c17 | 10922 | } |
647daca2 | 10923 | EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); |
e9b11c17 | 10924 | |
13a34e06 | 10925 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 10926 | { |
ca84d1a2 ZA |
10927 | struct kvm *kvm; |
10928 | struct kvm_vcpu *vcpu; | |
10929 | int i; | |
0dd6a6ed ZA |
10930 | int ret; |
10931 | u64 local_tsc; | |
10932 | u64 max_tsc = 0; | |
10933 | bool stable, backwards_tsc = false; | |
18863bdd | 10934 | |
7e34fbd0 | 10935 | kvm_user_return_msr_cpu_online(); |
b3646477 | 10936 | ret = static_call(kvm_x86_hardware_enable)(); |
0dd6a6ed ZA |
10937 | if (ret != 0) |
10938 | return ret; | |
10939 | ||
4ea1636b | 10940 | local_tsc = rdtsc(); |
b0c39dc6 | 10941 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
10942 | list_for_each_entry(kvm, &vm_list, vm_list) { |
10943 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
10944 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 10945 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10946 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
10947 | backwards_tsc = true; | |
10948 | if (vcpu->arch.last_host_tsc > max_tsc) | |
10949 | max_tsc = vcpu->arch.last_host_tsc; | |
10950 | } | |
10951 | } | |
10952 | } | |
10953 | ||
10954 | /* | |
10955 | * Sometimes, even reliable TSCs go backwards. This happens on | |
10956 | * platforms that reset TSC during suspend or hibernate actions, but | |
10957 | * maintain synchronization. We must compensate. Fortunately, we can | |
10958 | * detect that condition here, which happens early in CPU bringup, | |
10959 | * before any KVM threads can be running. Unfortunately, we can't | |
10960 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
10961 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 10962 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
10963 | * variables that haven't been updated yet. |
10964 | * | |
10965 | * So we simply find the maximum observed TSC above, then record the | |
10966 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
10967 | * the adjustment will be applied. Note that we accumulate | |
10968 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
10969 | * gets a chance to run again. In the event that no KVM threads get a | |
10970 | * chance to run, we will miss the entire elapsed period, as we'll have | |
10971 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
10972 | * loose cycle time. This isn't too big a deal, since the loss will be | |
10973 | * uniform across all VCPUs (not to mention the scenario is extremely | |
10974 | * unlikely). It is possible that a second hibernate recovery happens | |
10975 | * much faster than a first, causing the observed TSC here to be | |
10976 | * smaller; this would require additional padding adjustment, which is | |
10977 | * why we set last_host_tsc to the local tsc observed here. | |
10978 | * | |
10979 | * N.B. - this code below runs only on platforms with reliable TSC, | |
10980 | * as that is the only way backwards_tsc is set above. Also note | |
10981 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
10982 | * have the same delta_cyc adjustment applied if backwards_tsc | |
10983 | * is detected. Note further, this adjustment is only done once, | |
10984 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
10985 | * called multiple times (one for each physical CPU bringup). | |
10986 | * | |
4a969980 | 10987 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
10988 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
10989 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
10990 | * guarantee that they stay in perfect synchronization. | |
10991 | */ | |
10992 | if (backwards_tsc) { | |
10993 | u64 delta_cyc = max_tsc - local_tsc; | |
10994 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 10995 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
10996 | kvm_for_each_vcpu(i, vcpu, kvm) { |
10997 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
10998 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 10999 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
11000 | } |
11001 | ||
11002 | /* | |
11003 | * We have to disable TSC offset matching.. if you were | |
11004 | * booting a VM while issuing an S4 host suspend.... | |
11005 | * you may have some problem. Solving this issue is | |
11006 | * left as an exercise to the reader. | |
11007 | */ | |
11008 | kvm->arch.last_tsc_nsec = 0; | |
11009 | kvm->arch.last_tsc_write = 0; | |
11010 | } | |
11011 | ||
11012 | } | |
11013 | return 0; | |
e9b11c17 ZX |
11014 | } |
11015 | ||
13a34e06 | 11016 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 11017 | { |
b3646477 | 11018 | static_call(kvm_x86_hardware_disable)(); |
13a34e06 | 11019 | drop_user_return_notifiers(); |
e9b11c17 ZX |
11020 | } |
11021 | ||
b9904085 | 11022 | int kvm_arch_hardware_setup(void *opaque) |
e9b11c17 | 11023 | { |
d008dfdb | 11024 | struct kvm_x86_init_ops *ops = opaque; |
9e9c3fe4 NA |
11025 | int r; |
11026 | ||
91661989 SC |
11027 | rdmsrl_safe(MSR_EFER, &host_efer); |
11028 | ||
408e9a31 PB |
11029 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
11030 | rdmsrl(MSR_IA32_XSS, host_xss); | |
11031 | ||
d008dfdb | 11032 | r = ops->hardware_setup(); |
9e9c3fe4 NA |
11033 | if (r != 0) |
11034 | return r; | |
11035 | ||
afaf0b2f | 11036 | memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); |
b3646477 | 11037 | kvm_ops_static_call_update(); |
69c6f69a | 11038 | |
408e9a31 PB |
11039 | if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) |
11040 | supported_xss = 0; | |
11041 | ||
139f7425 PB |
11042 | #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) |
11043 | cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); | |
11044 | #undef __kvm_cpu_cap_has | |
b11306b5 | 11045 | |
35181e86 HZ |
11046 | if (kvm_has_tsc_control) { |
11047 | /* | |
11048 | * Make sure the user can only configure tsc_khz values that | |
11049 | * fit into a signed integer. | |
273ba457 | 11050 | * A min value is not calculated because it will always |
35181e86 HZ |
11051 | * be 1 on all machines. |
11052 | */ | |
11053 | u64 max = min(0x7fffffffULL, | |
11054 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
11055 | kvm_max_guest_tsc_khz = max; | |
11056 | ||
ad721883 | 11057 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 11058 | } |
ad721883 | 11059 | |
9e9c3fe4 NA |
11060 | kvm_init_msr_list(); |
11061 | return 0; | |
e9b11c17 ZX |
11062 | } |
11063 | ||
11064 | void kvm_arch_hardware_unsetup(void) | |
11065 | { | |
b3646477 | 11066 | static_call(kvm_x86_hardware_unsetup)(); |
e9b11c17 ZX |
11067 | } |
11068 | ||
b9904085 | 11069 | int kvm_arch_check_processor_compat(void *opaque) |
e9b11c17 | 11070 | { |
f1cdecf5 | 11071 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); |
d008dfdb | 11072 | struct kvm_x86_init_ops *ops = opaque; |
f1cdecf5 SC |
11073 | |
11074 | WARN_ON(!irqs_disabled()); | |
11075 | ||
139f7425 PB |
11076 | if (__cr4_reserved_bits(cpu_has, c) != |
11077 | __cr4_reserved_bits(cpu_has, &boot_cpu_data)) | |
f1cdecf5 SC |
11078 | return -EIO; |
11079 | ||
d008dfdb | 11080 | return ops->check_processor_compatibility(); |
d71ba788 PB |
11081 | } |
11082 | ||
11083 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
11084 | { | |
11085 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
11086 | } | |
11087 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
11088 | ||
11089 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
11090 | { | |
11091 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
11092 | } |
11093 | ||
6e4e3b4d CL |
11094 | __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); |
11095 | EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); | |
54e9818f | 11096 | |
e790d9ef RK |
11097 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
11098 | { | |
b35e5548 LX |
11099 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
11100 | ||
c595ceee | 11101 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
11102 | if (pmu->version && unlikely(pmu->event_count)) { |
11103 | pmu->need_cleanup = true; | |
11104 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
11105 | } | |
b3646477 | 11106 | static_call(kvm_x86_sched_in)(vcpu, cpu); |
e790d9ef RK |
11107 | } |
11108 | ||
562b6b08 SC |
11109 | void kvm_arch_free_vm(struct kvm *kvm) |
11110 | { | |
05f04ae4 | 11111 | kfree(to_kvm_hv(kvm)->hv_pa_pg); |
562b6b08 | 11112 | vfree(kvm); |
e790d9ef RK |
11113 | } |
11114 | ||
562b6b08 | 11115 | |
e08b9637 | 11116 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 11117 | { |
e08b9637 CO |
11118 | if (type) |
11119 | return -EINVAL; | |
11120 | ||
6ef768fa | 11121 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 11122 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
10605204 | 11123 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
1aa9b957 | 11124 | INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); |
4d5c5d0f | 11125 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 11126 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 11127 | |
5550af4d SY |
11128 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
11129 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
11130 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
11131 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
11132 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 11133 | |
038f8c11 | 11134 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 11135 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
11136 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
11137 | ||
8171cd68 | 11138 | kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); |
d828199e | 11139 | pvclock_update_vm_gtod_copy(kvm); |
53f658b3 | 11140 | |
6fbbde9a DS |
11141 | kvm->arch.guest_can_read_msr_platform_info = true; |
11142 | ||
3c86c0d3 VP |
11143 | #if IS_ENABLED(CONFIG_HYPERV) |
11144 | spin_lock_init(&kvm->arch.hv_root_tdp_lock); | |
11145 | kvm->arch.hv_root_tdp = INVALID_PAGE; | |
11146 | #endif | |
11147 | ||
7e44e449 | 11148 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 11149 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 11150 | |
4651fc56 | 11151 | kvm_apicv_init(kvm); |
cbc0236a | 11152 | kvm_hv_init_vm(kvm); |
0eb05bf2 | 11153 | kvm_page_track_init(kvm); |
13d268ca | 11154 | kvm_mmu_init_vm(kvm); |
319afe68 | 11155 | kvm_xen_init_vm(kvm); |
0eb05bf2 | 11156 | |
b3646477 | 11157 | return static_call(kvm_x86_vm_init)(kvm); |
d19a9cd2 ZX |
11158 | } |
11159 | ||
1aa9b957 JS |
11160 | int kvm_arch_post_init_vm(struct kvm *kvm) |
11161 | { | |
11162 | return kvm_mmu_post_init_vm(kvm); | |
11163 | } | |
11164 | ||
d19a9cd2 ZX |
11165 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
11166 | { | |
ec7660cc | 11167 | vcpu_load(vcpu); |
d19a9cd2 ZX |
11168 | kvm_mmu_unload(vcpu); |
11169 | vcpu_put(vcpu); | |
11170 | } | |
11171 | ||
11172 | static void kvm_free_vcpus(struct kvm *kvm) | |
11173 | { | |
11174 | unsigned int i; | |
988a2cae | 11175 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
11176 | |
11177 | /* | |
11178 | * Unpin any mmu pages first. | |
11179 | */ | |
af585b92 GN |
11180 | kvm_for_each_vcpu(i, vcpu, kvm) { |
11181 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 11182 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 11183 | } |
988a2cae | 11184 | kvm_for_each_vcpu(i, vcpu, kvm) |
4543bdc0 | 11185 | kvm_vcpu_destroy(vcpu); |
988a2cae GN |
11186 | |
11187 | mutex_lock(&kvm->lock); | |
11188 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
11189 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 11190 | |
988a2cae GN |
11191 | atomic_set(&kvm->online_vcpus, 0); |
11192 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
11193 | } |
11194 | ||
ad8ba2cd SY |
11195 | void kvm_arch_sync_events(struct kvm *kvm) |
11196 | { | |
332967a3 | 11197 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 11198 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 11199 | kvm_free_pit(kvm); |
ad8ba2cd SY |
11200 | } |
11201 | ||
ff5a983c PX |
11202 | #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) |
11203 | ||
11204 | /** | |
11205 | * __x86_set_memory_region: Setup KVM internal memory slot | |
11206 | * | |
11207 | * @kvm: the kvm pointer to the VM. | |
11208 | * @id: the slot ID to setup. | |
11209 | * @gpa: the GPA to install the slot (unused when @size == 0). | |
11210 | * @size: the size of the slot. Set to zero to uninstall a slot. | |
11211 | * | |
11212 | * This function helps to setup a KVM internal memory slot. Specify | |
11213 | * @size > 0 to install a new slot, while @size == 0 to uninstall a | |
11214 | * slot. The return code can be one of the following: | |
11215 | * | |
11216 | * HVA: on success (uninstall will return a bogus HVA) | |
11217 | * -errno: on error | |
11218 | * | |
11219 | * The caller should always use IS_ERR() to check the return value | |
11220 | * before use. Note, the KVM internal memory slots are guaranteed to | |
11221 | * remain valid and unchanged until the VM is destroyed, i.e., the | |
11222 | * GPA->HVA translation will not change. However, the HVA is a user | |
11223 | * address, i.e. its accessibility is not guaranteed, and must be | |
11224 | * accessed via __copy_{to,from}_user(). | |
11225 | */ | |
11226 | void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, | |
11227 | u32 size) | |
9da0e4d5 PB |
11228 | { |
11229 | int i, r; | |
3f649ab7 | 11230 | unsigned long hva, old_npages; |
f0d648bd | 11231 | struct kvm_memslots *slots = kvm_memslots(kvm); |
0577d1ab | 11232 | struct kvm_memory_slot *slot; |
9da0e4d5 PB |
11233 | |
11234 | /* Called with kvm->slots_lock held. */ | |
1d8007bd | 11235 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
ff5a983c | 11236 | return ERR_PTR_USR(-EINVAL); |
9da0e4d5 | 11237 | |
f0d648bd PB |
11238 | slot = id_to_memslot(slots, id); |
11239 | if (size) { | |
0577d1ab | 11240 | if (slot && slot->npages) |
ff5a983c | 11241 | return ERR_PTR_USR(-EEXIST); |
f0d648bd PB |
11242 | |
11243 | /* | |
11244 | * MAP_SHARED to prevent internal slot pages from being moved | |
11245 | * by fork()/COW. | |
11246 | */ | |
11247 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
11248 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
11249 | if (IS_ERR((void *)hva)) | |
ff5a983c | 11250 | return (void __user *)hva; |
f0d648bd | 11251 | } else { |
0577d1ab | 11252 | if (!slot || !slot->npages) |
46914534 | 11253 | return NULL; |
f0d648bd | 11254 | |
0577d1ab | 11255 | old_npages = slot->npages; |
b66f9bab | 11256 | hva = slot->userspace_addr; |
f0d648bd PB |
11257 | } |
11258 | ||
9da0e4d5 | 11259 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 11260 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 11261 | |
1d8007bd PB |
11262 | m.slot = id | (i << 16); |
11263 | m.flags = 0; | |
11264 | m.guest_phys_addr = gpa; | |
f0d648bd | 11265 | m.userspace_addr = hva; |
1d8007bd | 11266 | m.memory_size = size; |
9da0e4d5 PB |
11267 | r = __kvm_set_memory_region(kvm, &m); |
11268 | if (r < 0) | |
ff5a983c | 11269 | return ERR_PTR_USR(r); |
9da0e4d5 PB |
11270 | } |
11271 | ||
103c763c | 11272 | if (!size) |
0577d1ab | 11273 | vm_munmap(hva, old_npages * PAGE_SIZE); |
f0d648bd | 11274 | |
ff5a983c | 11275 | return (void __user *)hva; |
9da0e4d5 PB |
11276 | } |
11277 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
11278 | ||
1aa9b957 JS |
11279 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
11280 | { | |
11281 | kvm_mmu_pre_destroy_vm(kvm); | |
11282 | } | |
11283 | ||
d19a9cd2 ZX |
11284 | void kvm_arch_destroy_vm(struct kvm *kvm) |
11285 | { | |
27469d29 AH |
11286 | if (current->mm == kvm->mm) { |
11287 | /* | |
11288 | * Free memory regions allocated on behalf of userspace, | |
11289 | * unless the the memory map has changed due to process exit | |
11290 | * or fd copying. | |
11291 | */ | |
6a3c623b PX |
11292 | mutex_lock(&kvm->slots_lock); |
11293 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
11294 | 0, 0); | |
11295 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
11296 | 0, 0); | |
11297 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
11298 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 11299 | } |
b3646477 | 11300 | static_call_cond(kvm_x86_vm_destroy)(kvm); |
b318e8de | 11301 | kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); |
c761159c PX |
11302 | kvm_pic_destroy(kvm); |
11303 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 11304 | kvm_free_vcpus(kvm); |
af1bae54 | 11305 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 11306 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 11307 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 11308 | kvm_page_track_cleanup(kvm); |
7d6bbebb | 11309 | kvm_xen_destroy_vm(kvm); |
cbc0236a | 11310 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 11311 | } |
0de10343 | 11312 | |
c9b929b3 | 11313 | static void memslot_rmap_free(struct kvm_memory_slot *slot) |
db3fe4eb TY |
11314 | { |
11315 | int i; | |
11316 | ||
d89cc617 | 11317 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
11318 | kvfree(slot->arch.rmap[i]); |
11319 | slot->arch.rmap[i] = NULL; | |
c9b929b3 BG |
11320 | } |
11321 | } | |
e96c81ee | 11322 | |
c9b929b3 BG |
11323 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
11324 | { | |
11325 | int i; | |
11326 | ||
11327 | memslot_rmap_free(slot); | |
d89cc617 | 11328 | |
c9b929b3 | 11329 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
11330 | kvfree(slot->arch.lpage_info[i - 1]); |
11331 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb | 11332 | } |
21ebbeda | 11333 | |
e96c81ee | 11334 | kvm_page_track_free_memslot(slot); |
db3fe4eb TY |
11335 | } |
11336 | ||
56dd1019 BG |
11337 | static int memslot_rmap_alloc(struct kvm_memory_slot *slot, |
11338 | unsigned long npages) | |
11339 | { | |
11340 | const int sz = sizeof(*slot->arch.rmap[0]); | |
11341 | int i; | |
11342 | ||
11343 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { | |
11344 | int level = i + 1; | |
11345 | int lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
11346 | slot->base_gfn, level) + 1; | |
11347 | ||
d501f747 BG |
11348 | WARN_ON(slot->arch.rmap[i]); |
11349 | ||
56dd1019 BG |
11350 | slot->arch.rmap[i] = kvcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); |
11351 | if (!slot->arch.rmap[i]) { | |
11352 | memslot_rmap_free(slot); | |
11353 | return -ENOMEM; | |
11354 | } | |
11355 | } | |
11356 | ||
11357 | return 0; | |
11358 | } | |
11359 | ||
d501f747 BG |
11360 | int alloc_all_memslots_rmaps(struct kvm *kvm) |
11361 | { | |
11362 | struct kvm_memslots *slots; | |
11363 | struct kvm_memory_slot *slot; | |
11364 | int r, i; | |
11365 | ||
11366 | /* | |
11367 | * Check if memslots alreday have rmaps early before acquiring | |
11368 | * the slots_arch_lock below. | |
11369 | */ | |
11370 | if (kvm_memslots_have_rmaps(kvm)) | |
11371 | return 0; | |
11372 | ||
11373 | mutex_lock(&kvm->slots_arch_lock); | |
11374 | ||
11375 | /* | |
11376 | * Read memslots_have_rmaps again, under the slots arch lock, | |
11377 | * before allocating the rmaps | |
11378 | */ | |
11379 | if (kvm_memslots_have_rmaps(kvm)) { | |
11380 | mutex_unlock(&kvm->slots_arch_lock); | |
11381 | return 0; | |
11382 | } | |
11383 | ||
11384 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { | |
11385 | slots = __kvm_memslots(kvm, i); | |
11386 | kvm_for_each_memslot(slot, slots) { | |
11387 | r = memslot_rmap_alloc(slot, slot->npages); | |
11388 | if (r) { | |
11389 | mutex_unlock(&kvm->slots_arch_lock); | |
11390 | return r; | |
11391 | } | |
11392 | } | |
11393 | } | |
11394 | ||
11395 | /* | |
11396 | * Ensure that memslots_have_rmaps becomes true strictly after | |
11397 | * all the rmap pointers are set. | |
11398 | */ | |
11399 | smp_store_release(&kvm->arch.memslots_have_rmaps, true); | |
11400 | mutex_unlock(&kvm->slots_arch_lock); | |
11401 | return 0; | |
11402 | } | |
11403 | ||
a2557408 BG |
11404 | static int kvm_alloc_memslot_metadata(struct kvm *kvm, |
11405 | struct kvm_memory_slot *slot, | |
0dab98b7 | 11406 | unsigned long npages) |
db3fe4eb | 11407 | { |
56dd1019 | 11408 | int i, r; |
db3fe4eb | 11409 | |
edd4fa37 SC |
11410 | /* |
11411 | * Clear out the previous array pointers for the KVM_MR_MOVE case. The | |
11412 | * old arrays will be freed by __kvm_set_memory_region() if installing | |
11413 | * the new memslot is successful. | |
11414 | */ | |
11415 | memset(&slot->arch, 0, sizeof(slot->arch)); | |
11416 | ||
e2209710 | 11417 | if (kvm_memslots_have_rmaps(kvm)) { |
a2557408 BG |
11418 | r = memslot_rmap_alloc(slot, npages); |
11419 | if (r) | |
11420 | return r; | |
11421 | } | |
56dd1019 BG |
11422 | |
11423 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { | |
92f94f1e | 11424 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
11425 | unsigned long ugfn; |
11426 | int lpages; | |
d89cc617 | 11427 | int level = i + 1; |
db3fe4eb TY |
11428 | |
11429 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
11430 | slot->base_gfn, level) + 1; | |
11431 | ||
254272ce | 11432 | linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 11433 | if (!linfo) |
db3fe4eb TY |
11434 | goto out_free; |
11435 | ||
92f94f1e XG |
11436 | slot->arch.lpage_info[i - 1] = linfo; |
11437 | ||
db3fe4eb | 11438 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 11439 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 11440 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 11441 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
11442 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
11443 | /* | |
11444 | * If the gfn and userspace address are not aligned wrt each | |
600087b6 | 11445 | * other, disable large page support for this slot. |
db3fe4eb | 11446 | */ |
600087b6 | 11447 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { |
db3fe4eb TY |
11448 | unsigned long j; |
11449 | ||
11450 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 11451 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
11452 | } |
11453 | } | |
11454 | ||
21ebbeda XG |
11455 | if (kvm_page_track_create_memslot(slot, npages)) |
11456 | goto out_free; | |
11457 | ||
db3fe4eb TY |
11458 | return 0; |
11459 | ||
11460 | out_free: | |
c9b929b3 | 11461 | memslot_rmap_free(slot); |
d89cc617 | 11462 | |
c9b929b3 | 11463 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 11464 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 11465 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
11466 | } |
11467 | return -ENOMEM; | |
11468 | } | |
11469 | ||
15248258 | 11470 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 11471 | { |
91724814 BO |
11472 | struct kvm_vcpu *vcpu; |
11473 | int i; | |
11474 | ||
e6dff7d1 TY |
11475 | /* |
11476 | * memslots->generation has been incremented. | |
11477 | * mmio generation may have reached its maximum value. | |
11478 | */ | |
15248258 | 11479 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
11480 | |
11481 | /* Force re-initialization of steal_time cache */ | |
11482 | kvm_for_each_vcpu(i, vcpu, kvm) | |
11483 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
11484 | } |
11485 | ||
f7784b8e MT |
11486 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
11487 | struct kvm_memory_slot *memslot, | |
09170a49 | 11488 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 11489 | enum kvm_mr_change change) |
0de10343 | 11490 | { |
0dab98b7 | 11491 | if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) |
a2557408 | 11492 | return kvm_alloc_memslot_metadata(kvm, memslot, |
0dab98b7 | 11493 | mem->memory_size >> PAGE_SHIFT); |
f7784b8e MT |
11494 | return 0; |
11495 | } | |
11496 | ||
a85863c2 MS |
11497 | |
11498 | static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) | |
11499 | { | |
11500 | struct kvm_arch *ka = &kvm->arch; | |
11501 | ||
11502 | if (!kvm_x86_ops.cpu_dirty_log_size) | |
11503 | return; | |
11504 | ||
11505 | if ((enable && ++ka->cpu_dirty_logging_count == 1) || | |
11506 | (!enable && --ka->cpu_dirty_logging_count == 0)) | |
11507 | kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); | |
11508 | ||
11509 | WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); | |
11510 | } | |
11511 | ||
88178fd4 | 11512 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
3741679b | 11513 | struct kvm_memory_slot *old, |
269e9552 | 11514 | const struct kvm_memory_slot *new, |
3741679b | 11515 | enum kvm_mr_change change) |
88178fd4 | 11516 | { |
a85863c2 MS |
11517 | bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES; |
11518 | ||
3741679b | 11519 | /* |
a85863c2 MS |
11520 | * Update CPU dirty logging if dirty logging is being toggled. This |
11521 | * applies to all operations. | |
3741679b | 11522 | */ |
a85863c2 MS |
11523 | if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES) |
11524 | kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); | |
88178fd4 KH |
11525 | |
11526 | /* | |
a85863c2 | 11527 | * Nothing more to do for RO slots (which can't be dirtied and can't be |
b6e16ae5 | 11528 | * made writable) or CREATE/MOVE/DELETE of a slot. |
88178fd4 | 11529 | * |
b6e16ae5 | 11530 | * For a memslot with dirty logging disabled: |
3741679b AY |
11531 | * CREATE: No dirty mappings will already exist. |
11532 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
11533 | * kvm_arch_flush_shadow_memslot() | |
b6e16ae5 SC |
11534 | * |
11535 | * For a memslot with dirty logging enabled: | |
11536 | * CREATE: No shadow pages exist, thus nothing to write-protect | |
11537 | * and no dirty bits to clear. | |
11538 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
11539 | * kvm_arch_flush_shadow_memslot(). | |
3741679b | 11540 | */ |
3741679b | 11541 | if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) |
88178fd4 | 11542 | return; |
3741679b AY |
11543 | |
11544 | /* | |
52f46079 SC |
11545 | * READONLY and non-flags changes were filtered out above, and the only |
11546 | * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty | |
11547 | * logging isn't being toggled on or off. | |
88178fd4 | 11548 | */ |
52f46079 SC |
11549 | if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES))) |
11550 | return; | |
11551 | ||
b6e16ae5 SC |
11552 | if (!log_dirty_pages) { |
11553 | /* | |
11554 | * Dirty logging tracks sptes in 4k granularity, meaning that | |
11555 | * large sptes have to be split. If live migration succeeds, | |
11556 | * the guest in the source machine will be destroyed and large | |
11557 | * sptes will be created in the destination. However, if the | |
11558 | * guest continues to run in the source machine (for example if | |
11559 | * live migration fails), small sptes will remain around and | |
11560 | * cause bad performance. | |
11561 | * | |
11562 | * Scan sptes if dirty logging has been stopped, dropping those | |
11563 | * which can be collapsed into a single large-page spte. Later | |
11564 | * page faults will create the large-page sptes. | |
11565 | */ | |
3741679b | 11566 | kvm_mmu_zap_collapsible_sptes(kvm, new); |
b6e16ae5 | 11567 | } else { |
89212919 KZ |
11568 | /* |
11569 | * Initially-all-set does not require write protecting any page, | |
11570 | * because they're all assumed to be dirty. | |
11571 | */ | |
11572 | if (kvm_dirty_log_manual_protect_and_init_set(kvm)) | |
11573 | return; | |
a1419f8b | 11574 | |
a018eba5 | 11575 | if (kvm_x86_ops.cpu_dirty_log_size) { |
89212919 KZ |
11576 | kvm_mmu_slot_leaf_clear_dirty(kvm, new); |
11577 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); | |
11578 | } else { | |
11579 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); | |
3c9bd400 | 11580 | } |
88178fd4 KH |
11581 | } |
11582 | } | |
11583 | ||
f7784b8e | 11584 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 11585 | const struct kvm_userspace_memory_region *mem, |
9d4c197c | 11586 | struct kvm_memory_slot *old, |
f36f3f28 | 11587 | const struct kvm_memory_slot *new, |
8482644a | 11588 | enum kvm_mr_change change) |
f7784b8e | 11589 | { |
48c0e4e9 | 11590 | if (!kvm->arch.n_requested_mmu_pages) |
4d66623c WY |
11591 | kvm_mmu_change_mmu_pages(kvm, |
11592 | kvm_mmu_calculate_default_mmu_pages(kvm)); | |
1c91cad4 | 11593 | |
269e9552 | 11594 | kvm_mmu_slot_apply_flags(kvm, old, new, change); |
21198846 SC |
11595 | |
11596 | /* Free the arrays associated with the old memslot. */ | |
11597 | if (change == KVM_MR_MOVE) | |
e96c81ee | 11598 | kvm_arch_free_memslot(kvm, old); |
0de10343 | 11599 | } |
1d737c8a | 11600 | |
2df72e9b | 11601 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 11602 | { |
7390de1e | 11603 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
11604 | } |
11605 | ||
2df72e9b MT |
11606 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
11607 | struct kvm_memory_slot *slot) | |
11608 | { | |
ae7cd873 | 11609 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
11610 | } |
11611 | ||
e6c67d8c LA |
11612 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
11613 | { | |
11614 | return (is_guest_mode(vcpu) && | |
afaf0b2f | 11615 | kvm_x86_ops.guest_apic_has_interrupt && |
b3646477 | 11616 | static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); |
e6c67d8c LA |
11617 | } |
11618 | ||
5d9bc648 PB |
11619 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
11620 | { | |
11621 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
11622 | return true; | |
11623 | ||
11624 | if (kvm_apic_has_events(vcpu)) | |
11625 | return true; | |
11626 | ||
11627 | if (vcpu->arch.pv.pv_unhalted) | |
11628 | return true; | |
11629 | ||
a5f01f8e WL |
11630 | if (vcpu->arch.exception.pending) |
11631 | return true; | |
11632 | ||
47a66eed Z |
11633 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
11634 | (vcpu->arch.nmi_pending && | |
b3646477 | 11635 | static_call(kvm_x86_nmi_allowed)(vcpu, false))) |
5d9bc648 PB |
11636 | return true; |
11637 | ||
47a66eed | 11638 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
a9fa7cb6 | 11639 | (vcpu->arch.smi_pending && |
b3646477 | 11640 | static_call(kvm_x86_smi_allowed)(vcpu, false))) |
73917739 PB |
11641 | return true; |
11642 | ||
5d9bc648 | 11643 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
11644 | (kvm_cpu_has_interrupt(vcpu) || |
11645 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
11646 | return true; |
11647 | ||
1f4b34f8 AS |
11648 | if (kvm_hv_has_stimer_pending(vcpu)) |
11649 | return true; | |
11650 | ||
d2060bd4 SC |
11651 | if (is_guest_mode(vcpu) && |
11652 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
11653 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
11654 | return true; | |
11655 | ||
5d9bc648 PB |
11656 | return false; |
11657 | } | |
11658 | ||
1d737c8a ZX |
11659 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
11660 | { | |
5d9bc648 | 11661 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 11662 | } |
5736199a | 11663 | |
10dbdf98 | 11664 | bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) |
17e433b5 | 11665 | { |
b3646477 | 11666 | if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) |
52acd22f WL |
11667 | return true; |
11668 | ||
11669 | return false; | |
11670 | } | |
11671 | ||
17e433b5 WL |
11672 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
11673 | { | |
11674 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
11675 | return true; | |
11676 | ||
11677 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
11678 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
11679 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
11680 | return true; | |
11681 | ||
10dbdf98 | 11682 | return kvm_arch_dy_has_pending_interrupt(vcpu); |
17e433b5 WL |
11683 | } |
11684 | ||
199b5763 LM |
11685 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
11686 | { | |
b86bb11e WL |
11687 | if (vcpu->arch.guest_state_protected) |
11688 | return true; | |
11689 | ||
de63ad4c | 11690 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
11691 | } |
11692 | ||
b6d33834 | 11693 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 11694 | { |
b6d33834 | 11695 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 11696 | } |
78646121 GN |
11697 | |
11698 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
11699 | { | |
b3646477 | 11700 | return static_call(kvm_x86_interrupt_allowed)(vcpu, false); |
78646121 | 11701 | } |
229456fc | 11702 | |
82b32774 | 11703 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 11704 | { |
7ed9abfe TL |
11705 | /* Can't read the RIP when guest state is protected, just return 0 */ |
11706 | if (vcpu->arch.guest_state_protected) | |
11707 | return 0; | |
11708 | ||
82b32774 NA |
11709 | if (is_64_bit_mode(vcpu)) |
11710 | return kvm_rip_read(vcpu); | |
11711 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
11712 | kvm_rip_read(vcpu)); | |
11713 | } | |
11714 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 11715 | |
82b32774 NA |
11716 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
11717 | { | |
11718 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
11719 | } |
11720 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
11721 | ||
94fe45da JK |
11722 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
11723 | { | |
11724 | unsigned long rflags; | |
11725 | ||
b3646477 | 11726 | rflags = static_call(kvm_x86_get_rflags)(vcpu); |
94fe45da | 11727 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
c310bac5 | 11728 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
11729 | return rflags; |
11730 | } | |
11731 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
11732 | ||
6addfc42 | 11733 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
11734 | { |
11735 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 11736 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 11737 | rflags |= X86_EFLAGS_TF; |
b3646477 | 11738 | static_call(kvm_x86_set_rflags)(vcpu, rflags); |
6addfc42 PB |
11739 | } |
11740 | ||
11741 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
11742 | { | |
11743 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 11744 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
11745 | } |
11746 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
11747 | ||
56028d08 GN |
11748 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
11749 | { | |
11750 | int r; | |
11751 | ||
44dd3ffa | 11752 | if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || |
f2e10669 | 11753 | work->wakeup_all) |
56028d08 GN |
11754 | return; |
11755 | ||
11756 | r = kvm_mmu_reload(vcpu); | |
11757 | if (unlikely(r)) | |
11758 | return; | |
11759 | ||
44dd3ffa | 11760 | if (!vcpu->arch.mmu->direct_map && |
d8dd54e0 | 11761 | work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) |
fb67e14f XG |
11762 | return; |
11763 | ||
7a02674d | 11764 | kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); |
56028d08 GN |
11765 | } |
11766 | ||
af585b92 GN |
11767 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
11768 | { | |
dd03bcaa PX |
11769 | BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); |
11770 | ||
af585b92 GN |
11771 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); |
11772 | } | |
11773 | ||
11774 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
11775 | { | |
dd03bcaa | 11776 | return (key + 1) & (ASYNC_PF_PER_VCPU - 1); |
af585b92 GN |
11777 | } |
11778 | ||
11779 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11780 | { | |
11781 | u32 key = kvm_async_pf_hash_fn(gfn); | |
11782 | ||
11783 | while (vcpu->arch.apf.gfns[key] != ~0) | |
11784 | key = kvm_async_pf_next_probe(key); | |
11785 | ||
11786 | vcpu->arch.apf.gfns[key] = gfn; | |
11787 | } | |
11788 | ||
11789 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11790 | { | |
11791 | int i; | |
11792 | u32 key = kvm_async_pf_hash_fn(gfn); | |
11793 | ||
dd03bcaa | 11794 | for (i = 0; i < ASYNC_PF_PER_VCPU && |
c7d28c24 XG |
11795 | (vcpu->arch.apf.gfns[key] != gfn && |
11796 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
11797 | key = kvm_async_pf_next_probe(key); |
11798 | ||
11799 | return key; | |
11800 | } | |
11801 | ||
11802 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11803 | { | |
11804 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
11805 | } | |
11806 | ||
11807 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11808 | { | |
11809 | u32 i, j, k; | |
11810 | ||
11811 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
0fd46044 PX |
11812 | |
11813 | if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) | |
11814 | return; | |
11815 | ||
af585b92 GN |
11816 | while (true) { |
11817 | vcpu->arch.apf.gfns[i] = ~0; | |
11818 | do { | |
11819 | j = kvm_async_pf_next_probe(j); | |
11820 | if (vcpu->arch.apf.gfns[j] == ~0) | |
11821 | return; | |
11822 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
11823 | /* | |
11824 | * k lies cyclically in ]i,j] | |
11825 | * | i.k.j | | |
11826 | * |....j i.k.| or |.k..j i...| | |
11827 | */ | |
11828 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
11829 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
11830 | i = j; | |
11831 | } | |
11832 | } | |
11833 | ||
68fd66f1 | 11834 | static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) |
7c90705b | 11835 | { |
68fd66f1 VK |
11836 | u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; |
11837 | ||
11838 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, | |
11839 | sizeof(reason)); | |
11840 | } | |
11841 | ||
11842 | static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) | |
11843 | { | |
2635b5c4 | 11844 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); |
4e335d9e | 11845 | |
2635b5c4 VK |
11846 | return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, |
11847 | &token, offset, sizeof(token)); | |
11848 | } | |
11849 | ||
11850 | static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) | |
11851 | { | |
11852 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); | |
11853 | u32 val; | |
11854 | ||
11855 | if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, | |
11856 | &val, offset, sizeof(val))) | |
11857 | return false; | |
11858 | ||
11859 | return !val; | |
7c90705b GN |
11860 | } |
11861 | ||
1dfdb45e PB |
11862 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
11863 | { | |
11864 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) | |
11865 | return false; | |
11866 | ||
2635b5c4 | 11867 | if (!kvm_pv_async_pf_enabled(vcpu) || |
b3646477 | 11868 | (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) |
1dfdb45e PB |
11869 | return false; |
11870 | ||
11871 | return true; | |
11872 | } | |
11873 | ||
11874 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
11875 | { | |
11876 | if (unlikely(!lapic_in_kernel(vcpu) || | |
11877 | kvm_event_needs_reinjection(vcpu) || | |
11878 | vcpu->arch.exception.pending)) | |
11879 | return false; | |
11880 | ||
11881 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
11882 | return false; | |
11883 | ||
11884 | /* | |
11885 | * If interrupts are off we cannot even use an artificial | |
11886 | * halt state. | |
11887 | */ | |
c300ab9f | 11888 | return kvm_arch_interrupt_allowed(vcpu); |
1dfdb45e PB |
11889 | } |
11890 | ||
2a18b7e7 | 11891 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
11892 | struct kvm_async_pf *work) |
11893 | { | |
6389ee94 AK |
11894 | struct x86_exception fault; |
11895 | ||
736c291c | 11896 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 11897 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 11898 | |
1dfdb45e | 11899 | if (kvm_can_deliver_async_pf(vcpu) && |
68fd66f1 | 11900 | !apf_put_user_notpresent(vcpu)) { |
6389ee94 AK |
11901 | fault.vector = PF_VECTOR; |
11902 | fault.error_code_valid = true; | |
11903 | fault.error_code = 0; | |
11904 | fault.nested_page_fault = false; | |
11905 | fault.address = work->arch.token; | |
adfe20fb | 11906 | fault.async_page_fault = true; |
6389ee94 | 11907 | kvm_inject_page_fault(vcpu, &fault); |
2a18b7e7 | 11908 | return true; |
1dfdb45e PB |
11909 | } else { |
11910 | /* | |
11911 | * It is not possible to deliver a paravirtualized asynchronous | |
11912 | * page fault, but putting the guest in an artificial halt state | |
11913 | * can be beneficial nevertheless: if an interrupt arrives, we | |
11914 | * can deliver it timely and perhaps the guest will schedule | |
11915 | * another process. When the instruction that triggered a page | |
11916 | * fault is retried, hopefully the page will be ready in the host. | |
11917 | */ | |
11918 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2a18b7e7 | 11919 | return false; |
7c90705b | 11920 | } |
af585b92 GN |
11921 | } |
11922 | ||
11923 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
11924 | struct kvm_async_pf *work) | |
11925 | { | |
2635b5c4 VK |
11926 | struct kvm_lapic_irq irq = { |
11927 | .delivery_mode = APIC_DM_FIXED, | |
11928 | .vector = vcpu->arch.apf.vec | |
11929 | }; | |
6389ee94 | 11930 | |
f2e10669 | 11931 | if (work->wakeup_all) |
7c90705b GN |
11932 | work->arch.token = ~0; /* broadcast wakeup */ |
11933 | else | |
11934 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 11935 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 11936 | |
2a18b7e7 VK |
11937 | if ((work->wakeup_all || work->notpresent_injected) && |
11938 | kvm_pv_async_pf_enabled(vcpu) && | |
557a961a VK |
11939 | !apf_put_user_ready(vcpu, work->arch.token)) { |
11940 | vcpu->arch.apf.pageready_pending = true; | |
2635b5c4 | 11941 | kvm_apic_set_irq(vcpu, &irq, NULL); |
557a961a | 11942 | } |
2635b5c4 | 11943 | |
e6d53e3b | 11944 | vcpu->arch.apf.halted = false; |
a4fa1635 | 11945 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
11946 | } |
11947 | ||
557a961a VK |
11948 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) |
11949 | { | |
11950 | kvm_make_request(KVM_REQ_APF_READY, vcpu); | |
11951 | if (!vcpu->arch.apf.pageready_pending) | |
11952 | kvm_vcpu_kick(vcpu); | |
11953 | } | |
11954 | ||
7c0ade6c | 11955 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) |
7c90705b | 11956 | { |
2635b5c4 | 11957 | if (!kvm_pv_async_pf_enabled(vcpu)) |
7c90705b GN |
11958 | return true; |
11959 | else | |
2f15d027 | 11960 | return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); |
af585b92 GN |
11961 | } |
11962 | ||
5544eb9b PB |
11963 | void kvm_arch_start_assignment(struct kvm *kvm) |
11964 | { | |
57ab8794 MT |
11965 | if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) |
11966 | static_call_cond(kvm_x86_start_assignment)(kvm); | |
5544eb9b PB |
11967 | } |
11968 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
11969 | ||
11970 | void kvm_arch_end_assignment(struct kvm *kvm) | |
11971 | { | |
11972 | atomic_dec(&kvm->arch.assigned_device_count); | |
11973 | } | |
11974 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
11975 | ||
11976 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
11977 | { | |
11978 | return atomic_read(&kvm->arch.assigned_device_count); | |
11979 | } | |
11980 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
11981 | ||
e0f0bbc5 AW |
11982 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
11983 | { | |
11984 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
11985 | } | |
11986 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
11987 | ||
11988 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
11989 | { | |
11990 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
11991 | } | |
11992 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
11993 | ||
11994 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
11995 | { | |
11996 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
11997 | } | |
11998 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
11999 | ||
14717e20 AW |
12000 | bool kvm_arch_has_irq_bypass(void) |
12001 | { | |
92735b1b | 12002 | return true; |
14717e20 AW |
12003 | } |
12004 | ||
87276880 FW |
12005 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
12006 | struct irq_bypass_producer *prod) | |
12007 | { | |
12008 | struct kvm_kernel_irqfd *irqfd = | |
12009 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
2edd9cb7 | 12010 | int ret; |
87276880 | 12011 | |
14717e20 | 12012 | irqfd->producer = prod; |
2edd9cb7 | 12013 | kvm_arch_start_assignment(irqfd->kvm); |
b3646477 | 12014 | ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, |
2edd9cb7 ZL |
12015 | prod->irq, irqfd->gsi, 1); |
12016 | ||
12017 | if (ret) | |
12018 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 | 12019 | |
2edd9cb7 | 12020 | return ret; |
87276880 FW |
12021 | } |
12022 | ||
12023 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
12024 | struct irq_bypass_producer *prod) | |
12025 | { | |
12026 | int ret; | |
12027 | struct kvm_kernel_irqfd *irqfd = | |
12028 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
12029 | ||
87276880 FW |
12030 | WARN_ON(irqfd->producer != prod); |
12031 | irqfd->producer = NULL; | |
12032 | ||
12033 | /* | |
12034 | * When producer of consumer is unregistered, we change back to | |
12035 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 12036 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
12037 | * int this case doesn't want to receive the interrupts. |
12038 | */ | |
b3646477 | 12039 | ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); |
87276880 FW |
12040 | if (ret) |
12041 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
12042 | " fails: %d\n", irqfd->consumer.token, ret); | |
2edd9cb7 ZL |
12043 | |
12044 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 FW |
12045 | } |
12046 | ||
12047 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
12048 | uint32_t guest_irq, bool set) | |
12049 | { | |
b3646477 | 12050 | return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); |
87276880 FW |
12051 | } |
12052 | ||
52004014 FW |
12053 | bool kvm_vector_hashing_enabled(void) |
12054 | { | |
12055 | return vector_hashing; | |
12056 | } | |
52004014 | 12057 | |
2d5ba19b MT |
12058 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
12059 | { | |
12060 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
12061 | } | |
12062 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
12063 | ||
841c2be0 ML |
12064 | |
12065 | int kvm_spec_ctrl_test_value(u64 value) | |
6441fa61 | 12066 | { |
841c2be0 ML |
12067 | /* |
12068 | * test that setting IA32_SPEC_CTRL to given value | |
12069 | * is allowed by the host processor | |
12070 | */ | |
6441fa61 | 12071 | |
841c2be0 ML |
12072 | u64 saved_value; |
12073 | unsigned long flags; | |
12074 | int ret = 0; | |
6441fa61 | 12075 | |
841c2be0 | 12076 | local_irq_save(flags); |
6441fa61 | 12077 | |
841c2be0 ML |
12078 | if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) |
12079 | ret = 1; | |
12080 | else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) | |
12081 | ret = 1; | |
12082 | else | |
12083 | wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); | |
6441fa61 | 12084 | |
841c2be0 | 12085 | local_irq_restore(flags); |
6441fa61 | 12086 | |
841c2be0 | 12087 | return ret; |
6441fa61 | 12088 | } |
841c2be0 | 12089 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); |
2d5ba19b | 12090 | |
89786147 MG |
12091 | void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) |
12092 | { | |
12093 | struct x86_exception fault; | |
19cf4b7e PB |
12094 | u32 access = error_code & |
12095 | (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); | |
89786147 MG |
12096 | |
12097 | if (!(error_code & PFERR_PRESENT_MASK) || | |
19cf4b7e | 12098 | vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { |
89786147 MG |
12099 | /* |
12100 | * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page | |
12101 | * tables probably do not match the TLB. Just proceed | |
12102 | * with the error code that the processor gave. | |
12103 | */ | |
12104 | fault.vector = PF_VECTOR; | |
12105 | fault.error_code_valid = true; | |
12106 | fault.error_code = error_code; | |
12107 | fault.nested_page_fault = false; | |
12108 | fault.address = gva; | |
12109 | } | |
12110 | vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); | |
6441fa61 | 12111 | } |
89786147 | 12112 | EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); |
2d5ba19b | 12113 | |
3f3393b3 BM |
12114 | /* |
12115 | * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns | |
12116 | * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value | |
12117 | * indicates whether exit to userspace is needed. | |
12118 | */ | |
12119 | int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, | |
12120 | struct x86_exception *e) | |
12121 | { | |
12122 | if (r == X86EMUL_PROPAGATE_FAULT) { | |
12123 | kvm_inject_emulated_page_fault(vcpu, e); | |
12124 | return 1; | |
12125 | } | |
12126 | ||
12127 | /* | |
12128 | * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED | |
12129 | * while handling a VMX instruction KVM could've handled the request | |
12130 | * correctly by exiting to userspace and performing I/O but there | |
12131 | * doesn't seem to be a real use-case behind such requests, just return | |
12132 | * KVM_EXIT_INTERNAL_ERROR for now. | |
12133 | */ | |
12134 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
12135 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
12136 | vcpu->run->internal.ndata = 0; | |
12137 | ||
12138 | return 0; | |
12139 | } | |
12140 | EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); | |
12141 | ||
9715092f BM |
12142 | int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) |
12143 | { | |
12144 | bool pcid_enabled; | |
12145 | struct x86_exception e; | |
9715092f BM |
12146 | struct { |
12147 | u64 pcid; | |
12148 | u64 gla; | |
12149 | } operand; | |
12150 | int r; | |
12151 | ||
12152 | r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); | |
12153 | if (r != X86EMUL_CONTINUE) | |
12154 | return kvm_handle_memory_failure(vcpu, r, &e); | |
12155 | ||
12156 | if (operand.pcid >> 12 != 0) { | |
12157 | kvm_inject_gp(vcpu, 0); | |
12158 | return 1; | |
12159 | } | |
12160 | ||
12161 | pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); | |
12162 | ||
12163 | switch (type) { | |
12164 | case INVPCID_TYPE_INDIV_ADDR: | |
12165 | if ((!pcid_enabled && (operand.pcid != 0)) || | |
12166 | is_noncanonical_address(operand.gla, vcpu)) { | |
12167 | kvm_inject_gp(vcpu, 0); | |
12168 | return 1; | |
12169 | } | |
12170 | kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); | |
12171 | return kvm_skip_emulated_instruction(vcpu); | |
12172 | ||
12173 | case INVPCID_TYPE_SINGLE_CTXT: | |
12174 | if (!pcid_enabled && (operand.pcid != 0)) { | |
12175 | kvm_inject_gp(vcpu, 0); | |
12176 | return 1; | |
12177 | } | |
12178 | ||
21823fbd | 12179 | kvm_invalidate_pcid(vcpu, operand.pcid); |
9715092f BM |
12180 | return kvm_skip_emulated_instruction(vcpu); |
12181 | ||
12182 | case INVPCID_TYPE_ALL_NON_GLOBAL: | |
12183 | /* | |
12184 | * Currently, KVM doesn't mark global entries in the shadow | |
12185 | * page tables, so a non-global flush just degenerates to a | |
12186 | * global flush. If needed, we could optimize this later by | |
12187 | * keeping track of global entries in shadow page tables. | |
12188 | */ | |
12189 | ||
12190 | fallthrough; | |
12191 | case INVPCID_TYPE_ALL_INCL_GLOBAL: | |
28f28d45 | 12192 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); |
9715092f BM |
12193 | return kvm_skip_emulated_instruction(vcpu); |
12194 | ||
12195 | default: | |
12196 | BUG(); /* We have already checked above that type <= 3 */ | |
12197 | } | |
12198 | } | |
12199 | EXPORT_SYMBOL_GPL(kvm_handle_invpcid); | |
12200 | ||
8f423a80 TL |
12201 | static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) |
12202 | { | |
12203 | struct kvm_run *run = vcpu->run; | |
12204 | struct kvm_mmio_fragment *frag; | |
12205 | unsigned int len; | |
12206 | ||
12207 | BUG_ON(!vcpu->mmio_needed); | |
12208 | ||
12209 | /* Complete previous fragment */ | |
12210 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; | |
12211 | len = min(8u, frag->len); | |
12212 | if (!vcpu->mmio_is_write) | |
12213 | memcpy(frag->data, run->mmio.data, len); | |
12214 | ||
12215 | if (frag->len <= 8) { | |
12216 | /* Switch to the next fragment. */ | |
12217 | frag++; | |
12218 | vcpu->mmio_cur_fragment++; | |
12219 | } else { | |
12220 | /* Go forward to the next mmio piece. */ | |
12221 | frag->data += len; | |
12222 | frag->gpa += len; | |
12223 | frag->len -= len; | |
12224 | } | |
12225 | ||
12226 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { | |
12227 | vcpu->mmio_needed = 0; | |
12228 | ||
12229 | // VMG change, at this point, we're always done | |
12230 | // RIP has already been advanced | |
12231 | return 1; | |
12232 | } | |
12233 | ||
12234 | // More MMIO is needed | |
12235 | run->mmio.phys_addr = frag->gpa; | |
12236 | run->mmio.len = min(8u, frag->len); | |
12237 | run->mmio.is_write = vcpu->mmio_is_write; | |
12238 | if (run->mmio.is_write) | |
12239 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); | |
12240 | run->exit_reason = KVM_EXIT_MMIO; | |
12241 | ||
12242 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12243 | ||
12244 | return 0; | |
12245 | } | |
12246 | ||
12247 | int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
12248 | void *data) | |
12249 | { | |
12250 | int handled; | |
12251 | struct kvm_mmio_fragment *frag; | |
12252 | ||
12253 | if (!data) | |
12254 | return -EINVAL; | |
12255 | ||
12256 | handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
12257 | if (handled == bytes) | |
12258 | return 1; | |
12259 | ||
12260 | bytes -= handled; | |
12261 | gpa += handled; | |
12262 | data += handled; | |
12263 | ||
12264 | /*TODO: Check if need to increment number of frags */ | |
12265 | frag = vcpu->mmio_fragments; | |
12266 | vcpu->mmio_nr_fragments = 1; | |
12267 | frag->len = bytes; | |
12268 | frag->gpa = gpa; | |
12269 | frag->data = data; | |
12270 | ||
12271 | vcpu->mmio_needed = 1; | |
12272 | vcpu->mmio_cur_fragment = 0; | |
12273 | ||
12274 | vcpu->run->mmio.phys_addr = gpa; | |
12275 | vcpu->run->mmio.len = min(8u, frag->len); | |
12276 | vcpu->run->mmio.is_write = 1; | |
12277 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); | |
12278 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
12279 | ||
12280 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12281 | ||
12282 | return 0; | |
12283 | } | |
12284 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); | |
12285 | ||
12286 | int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
12287 | void *data) | |
12288 | { | |
12289 | int handled; | |
12290 | struct kvm_mmio_fragment *frag; | |
12291 | ||
12292 | if (!data) | |
12293 | return -EINVAL; | |
12294 | ||
12295 | handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
12296 | if (handled == bytes) | |
12297 | return 1; | |
12298 | ||
12299 | bytes -= handled; | |
12300 | gpa += handled; | |
12301 | data += handled; | |
12302 | ||
12303 | /*TODO: Check if need to increment number of frags */ | |
12304 | frag = vcpu->mmio_fragments; | |
12305 | vcpu->mmio_nr_fragments = 1; | |
12306 | frag->len = bytes; | |
12307 | frag->gpa = gpa; | |
12308 | frag->data = data; | |
12309 | ||
12310 | vcpu->mmio_needed = 1; | |
12311 | vcpu->mmio_cur_fragment = 0; | |
12312 | ||
12313 | vcpu->run->mmio.phys_addr = gpa; | |
12314 | vcpu->run->mmio.len = min(8u, frag->len); | |
12315 | vcpu->run->mmio.is_write = 0; | |
12316 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
12317 | ||
12318 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12319 | ||
12320 | return 0; | |
12321 | } | |
12322 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); | |
12323 | ||
7ed9abfe TL |
12324 | static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) |
12325 | { | |
12326 | memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data, | |
12327 | vcpu->arch.pio.count * vcpu->arch.pio.size); | |
12328 | vcpu->arch.pio.count = 0; | |
12329 | ||
12330 | return 1; | |
12331 | } | |
12332 | ||
12333 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, | |
12334 | unsigned int port, void *data, unsigned int count) | |
12335 | { | |
12336 | int ret; | |
12337 | ||
12338 | ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port, | |
12339 | data, count); | |
12340 | if (ret) | |
12341 | return ret; | |
12342 | ||
12343 | vcpu->arch.pio.count = 0; | |
12344 | ||
12345 | return 0; | |
12346 | } | |
12347 | ||
12348 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, | |
12349 | unsigned int port, void *data, unsigned int count) | |
12350 | { | |
12351 | int ret; | |
12352 | ||
12353 | ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port, | |
12354 | data, count); | |
12355 | if (ret) { | |
12356 | vcpu->arch.pio.count = 0; | |
12357 | } else { | |
12358 | vcpu->arch.guest_ins_data = data; | |
12359 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; | |
12360 | } | |
12361 | ||
12362 | return 0; | |
12363 | } | |
12364 | ||
12365 | int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, | |
12366 | unsigned int port, void *data, unsigned int count, | |
12367 | int in) | |
12368 | { | |
12369 | return in ? kvm_sev_es_ins(vcpu, size, port, data, count) | |
12370 | : kvm_sev_es_outs(vcpu, size, port, data, count); | |
12371 | } | |
12372 | EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); | |
12373 | ||
d95df951 | 12374 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); |
229456fc | 12375 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 12376 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
12377 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
12378 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
12379 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
12380 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 12381 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 12382 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 12383 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 12384 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 12385 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 12386 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 12387 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 12388 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 12389 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 12390 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 12391 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 12392 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
12393 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
12394 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
ab56f8e6 | 12395 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); |
24bbf74c | 12396 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); |
d523ab6b TL |
12397 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); |
12398 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); | |
59e38b58 TL |
12399 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); |
12400 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); |