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Commit | Line | Data |
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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Avi Kivity <avi@qumranet.com> | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
16 | ||
edf88417 | 17 | #include <linux/kvm_host.h> |
313a3dc7 | 18 | #include "irq.h" |
1d737c8a | 19 | #include "mmu.h" |
7837699f | 20 | #include "i8254.h" |
37817f29 | 21 | #include "tss.h" |
313a3dc7 | 22 | |
18068523 | 23 | #include <linux/clocksource.h> |
313a3dc7 CO |
24 | #include <linux/kvm.h> |
25 | #include <linux/fs.h> | |
26 | #include <linux/vmalloc.h> | |
5fb76f9b | 27 | #include <linux/module.h> |
0de10343 | 28 | #include <linux/mman.h> |
2bacc55c | 29 | #include <linux/highmem.h> |
043405e1 CO |
30 | |
31 | #include <asm/uaccess.h> | |
d825ed0a | 32 | #include <asm/msr.h> |
a5f61300 | 33 | #include <asm/desc.h> |
043405e1 | 34 | |
313a3dc7 | 35 | #define MAX_IO_MSRS 256 |
a03490ed CO |
36 | #define CR0_RESERVED_BITS \ |
37 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
38 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
39 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
40 | #define CR4_RESERVED_BITS \ | |
41 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
42 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
43 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
44 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) | |
45 | ||
46 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
50a37eb4 JR |
47 | /* EFER defaults: |
48 | * - enable syscall per default because its emulated by KVM | |
49 | * - enable LME and LMA per default on 64 bit KVM | |
50 | */ | |
51 | #ifdef CONFIG_X86_64 | |
52 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL; | |
53 | #else | |
54 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL; | |
55 | #endif | |
313a3dc7 | 56 | |
ba1389b7 AK |
57 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
58 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 59 | |
674eea0f AK |
60 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
61 | struct kvm_cpuid_entry2 __user *entries); | |
62 | ||
97896d04 ZX |
63 | struct kvm_x86_ops *kvm_x86_ops; |
64 | ||
417bc304 | 65 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
66 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
67 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
68 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
69 | { "invlpg", VCPU_STAT(invlpg) }, | |
70 | { "exits", VCPU_STAT(exits) }, | |
71 | { "io_exits", VCPU_STAT(io_exits) }, | |
72 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
73 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
74 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
75 | { "halt_exits", VCPU_STAT(halt_exits) }, | |
76 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 77 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
78 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
79 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
80 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
81 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
82 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
83 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
84 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
4cee5764 AK |
85 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
86 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
87 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
88 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
89 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
90 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 91 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
0f74a24c | 92 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 93 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
94 | { NULL } |
95 | }; | |
96 | ||
97 | ||
5fb76f9b CO |
98 | unsigned long segment_base(u16 selector) |
99 | { | |
100 | struct descriptor_table gdt; | |
a5f61300 | 101 | struct desc_struct *d; |
5fb76f9b CO |
102 | unsigned long table_base; |
103 | unsigned long v; | |
104 | ||
105 | if (selector == 0) | |
106 | return 0; | |
107 | ||
108 | asm("sgdt %0" : "=m"(gdt)); | |
109 | table_base = gdt.base; | |
110 | ||
111 | if (selector & 4) { /* from ldt */ | |
112 | u16 ldt_selector; | |
113 | ||
114 | asm("sldt %0" : "=g"(ldt_selector)); | |
115 | table_base = segment_base(ldt_selector); | |
116 | } | |
a5f61300 AK |
117 | d = (struct desc_struct *)(table_base + (selector & ~7)); |
118 | v = d->base0 | ((unsigned long)d->base1 << 16) | | |
119 | ((unsigned long)d->base2 << 24); | |
5fb76f9b | 120 | #ifdef CONFIG_X86_64 |
a5f61300 AK |
121 | if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) |
122 | v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; | |
5fb76f9b CO |
123 | #endif |
124 | return v; | |
125 | } | |
126 | EXPORT_SYMBOL_GPL(segment_base); | |
127 | ||
6866b83e CO |
128 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
129 | { | |
130 | if (irqchip_in_kernel(vcpu->kvm)) | |
ad312c7c | 131 | return vcpu->arch.apic_base; |
6866b83e | 132 | else |
ad312c7c | 133 | return vcpu->arch.apic_base; |
6866b83e CO |
134 | } |
135 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
136 | ||
137 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
138 | { | |
139 | /* TODO: reserve bits check */ | |
140 | if (irqchip_in_kernel(vcpu->kvm)) | |
141 | kvm_lapic_set_base(vcpu, data); | |
142 | else | |
ad312c7c | 143 | vcpu->arch.apic_base = data; |
6866b83e CO |
144 | } |
145 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
146 | ||
298101da AK |
147 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
148 | { | |
ad312c7c ZX |
149 | WARN_ON(vcpu->arch.exception.pending); |
150 | vcpu->arch.exception.pending = true; | |
151 | vcpu->arch.exception.has_error_code = false; | |
152 | vcpu->arch.exception.nr = nr; | |
298101da AK |
153 | } |
154 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
155 | ||
c3c91fee AK |
156 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr, |
157 | u32 error_code) | |
158 | { | |
159 | ++vcpu->stat.pf_guest; | |
71c4dfaf JR |
160 | if (vcpu->arch.exception.pending) { |
161 | if (vcpu->arch.exception.nr == PF_VECTOR) { | |
162 | printk(KERN_DEBUG "kvm: inject_page_fault:" | |
163 | " double fault 0x%lx\n", addr); | |
164 | vcpu->arch.exception.nr = DF_VECTOR; | |
165 | vcpu->arch.exception.error_code = 0; | |
166 | } else if (vcpu->arch.exception.nr == DF_VECTOR) { | |
167 | /* triple fault -> shutdown */ | |
168 | set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests); | |
169 | } | |
c3c91fee AK |
170 | return; |
171 | } | |
ad312c7c | 172 | vcpu->arch.cr2 = addr; |
c3c91fee AK |
173 | kvm_queue_exception_e(vcpu, PF_VECTOR, error_code); |
174 | } | |
175 | ||
298101da AK |
176 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
177 | { | |
ad312c7c ZX |
178 | WARN_ON(vcpu->arch.exception.pending); |
179 | vcpu->arch.exception.pending = true; | |
180 | vcpu->arch.exception.has_error_code = true; | |
181 | vcpu->arch.exception.nr = nr; | |
182 | vcpu->arch.exception.error_code = error_code; | |
298101da AK |
183 | } |
184 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
185 | ||
186 | static void __queue_exception(struct kvm_vcpu *vcpu) | |
187 | { | |
ad312c7c ZX |
188 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
189 | vcpu->arch.exception.has_error_code, | |
190 | vcpu->arch.exception.error_code); | |
298101da AK |
191 | } |
192 | ||
a03490ed CO |
193 | /* |
194 | * Load the pae pdptrs. Return true is they are all valid. | |
195 | */ | |
196 | int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) | |
197 | { | |
198 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
199 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
200 | int i; | |
201 | int ret; | |
ad312c7c | 202 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
a03490ed | 203 | |
72dc67a6 | 204 | down_read(&vcpu->kvm->slots_lock); |
a03490ed CO |
205 | ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte, |
206 | offset * sizeof(u64), sizeof(pdpte)); | |
207 | if (ret < 0) { | |
208 | ret = 0; | |
209 | goto out; | |
210 | } | |
211 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
212 | if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) { | |
213 | ret = 0; | |
214 | goto out; | |
215 | } | |
216 | } | |
217 | ret = 1; | |
218 | ||
ad312c7c | 219 | memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs)); |
a03490ed | 220 | out: |
72dc67a6 | 221 | up_read(&vcpu->kvm->slots_lock); |
a03490ed CO |
222 | |
223 | return ret; | |
224 | } | |
cc4b6871 | 225 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 226 | |
d835dfec AK |
227 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
228 | { | |
ad312c7c | 229 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
d835dfec AK |
230 | bool changed = true; |
231 | int r; | |
232 | ||
233 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
234 | return false; | |
235 | ||
72dc67a6 | 236 | down_read(&vcpu->kvm->slots_lock); |
ad312c7c | 237 | r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte)); |
d835dfec AK |
238 | if (r < 0) |
239 | goto out; | |
ad312c7c | 240 | changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 241 | out: |
72dc67a6 | 242 | up_read(&vcpu->kvm->slots_lock); |
d835dfec AK |
243 | |
244 | return changed; | |
245 | } | |
246 | ||
2d3ad1f4 | 247 | void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed CO |
248 | { |
249 | if (cr0 & CR0_RESERVED_BITS) { | |
250 | printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n", | |
ad312c7c | 251 | cr0, vcpu->arch.cr0); |
c1a5d4f9 | 252 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
253 | return; |
254 | } | |
255 | ||
256 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) { | |
257 | printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n"); | |
c1a5d4f9 | 258 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
259 | return; |
260 | } | |
261 | ||
262 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) { | |
263 | printk(KERN_DEBUG "set_cr0: #GP, set PG flag " | |
264 | "and a clear PE flag\n"); | |
c1a5d4f9 | 265 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
266 | return; |
267 | } | |
268 | ||
269 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
270 | #ifdef CONFIG_X86_64 | |
ad312c7c | 271 | if ((vcpu->arch.shadow_efer & EFER_LME)) { |
a03490ed CO |
272 | int cs_db, cs_l; |
273 | ||
274 | if (!is_pae(vcpu)) { | |
275 | printk(KERN_DEBUG "set_cr0: #GP, start paging " | |
276 | "in long mode while PAE is disabled\n"); | |
c1a5d4f9 | 277 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
278 | return; |
279 | } | |
280 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
281 | if (cs_l) { | |
282 | printk(KERN_DEBUG "set_cr0: #GP, start paging " | |
283 | "in long mode while CS.L == 1\n"); | |
c1a5d4f9 | 284 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
285 | return; |
286 | ||
287 | } | |
288 | } else | |
289 | #endif | |
ad312c7c | 290 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) { |
a03490ed CO |
291 | printk(KERN_DEBUG "set_cr0: #GP, pdptrs " |
292 | "reserved bits\n"); | |
c1a5d4f9 | 293 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
294 | return; |
295 | } | |
296 | ||
297 | } | |
298 | ||
299 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
ad312c7c | 300 | vcpu->arch.cr0 = cr0; |
a03490ed | 301 | |
a03490ed | 302 | kvm_mmu_reset_context(vcpu); |
a03490ed CO |
303 | return; |
304 | } | |
2d3ad1f4 | 305 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 306 | |
2d3ad1f4 | 307 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 308 | { |
2d3ad1f4 | 309 | kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)); |
a03490ed | 310 | } |
2d3ad1f4 | 311 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 312 | |
2d3ad1f4 | 313 | void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed CO |
314 | { |
315 | if (cr4 & CR4_RESERVED_BITS) { | |
316 | printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n"); | |
c1a5d4f9 | 317 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
318 | return; |
319 | } | |
320 | ||
321 | if (is_long_mode(vcpu)) { | |
322 | if (!(cr4 & X86_CR4_PAE)) { | |
323 | printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while " | |
324 | "in long mode\n"); | |
c1a5d4f9 | 325 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
326 | return; |
327 | } | |
328 | } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE) | |
ad312c7c | 329 | && !load_pdptrs(vcpu, vcpu->arch.cr3)) { |
a03490ed | 330 | printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n"); |
c1a5d4f9 | 331 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
332 | return; |
333 | } | |
334 | ||
335 | if (cr4 & X86_CR4_VMXE) { | |
336 | printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n"); | |
c1a5d4f9 | 337 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
338 | return; |
339 | } | |
340 | kvm_x86_ops->set_cr4(vcpu, cr4); | |
ad312c7c | 341 | vcpu->arch.cr4 = cr4; |
a03490ed | 342 | kvm_mmu_reset_context(vcpu); |
a03490ed | 343 | } |
2d3ad1f4 | 344 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 345 | |
2d3ad1f4 | 346 | void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 347 | { |
ad312c7c | 348 | if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) { |
d835dfec AK |
349 | kvm_mmu_flush_tlb(vcpu); |
350 | return; | |
351 | } | |
352 | ||
a03490ed CO |
353 | if (is_long_mode(vcpu)) { |
354 | if (cr3 & CR3_L_MODE_RESERVED_BITS) { | |
355 | printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n"); | |
c1a5d4f9 | 356 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
357 | return; |
358 | } | |
359 | } else { | |
360 | if (is_pae(vcpu)) { | |
361 | if (cr3 & CR3_PAE_RESERVED_BITS) { | |
362 | printk(KERN_DEBUG | |
363 | "set_cr3: #GP, reserved bits\n"); | |
c1a5d4f9 | 364 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
365 | return; |
366 | } | |
367 | if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) { | |
368 | printk(KERN_DEBUG "set_cr3: #GP, pdptrs " | |
369 | "reserved bits\n"); | |
c1a5d4f9 | 370 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
371 | return; |
372 | } | |
373 | } | |
374 | /* | |
375 | * We don't check reserved bits in nonpae mode, because | |
376 | * this isn't enforced, and VMware depends on this. | |
377 | */ | |
378 | } | |
379 | ||
72dc67a6 | 380 | down_read(&vcpu->kvm->slots_lock); |
a03490ed CO |
381 | /* |
382 | * Does the new cr3 value map to physical memory? (Note, we | |
383 | * catch an invalid cr3 even in real-mode, because it would | |
384 | * cause trouble later on when we turn on paging anyway.) | |
385 | * | |
386 | * A real CPU would silently accept an invalid cr3 and would | |
387 | * attempt to use it - with largely undefined (and often hard | |
388 | * to debug) behavior on the guest side. | |
389 | */ | |
390 | if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT))) | |
c1a5d4f9 | 391 | kvm_inject_gp(vcpu, 0); |
a03490ed | 392 | else { |
ad312c7c ZX |
393 | vcpu->arch.cr3 = cr3; |
394 | vcpu->arch.mmu.new_cr3(vcpu); | |
a03490ed | 395 | } |
72dc67a6 | 396 | up_read(&vcpu->kvm->slots_lock); |
a03490ed | 397 | } |
2d3ad1f4 | 398 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 399 | |
2d3ad1f4 | 400 | void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed CO |
401 | { |
402 | if (cr8 & CR8_RESERVED_BITS) { | |
403 | printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8); | |
c1a5d4f9 | 404 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
405 | return; |
406 | } | |
407 | if (irqchip_in_kernel(vcpu->kvm)) | |
408 | kvm_lapic_set_tpr(vcpu, cr8); | |
409 | else | |
ad312c7c | 410 | vcpu->arch.cr8 = cr8; |
a03490ed | 411 | } |
2d3ad1f4 | 412 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 413 | |
2d3ad1f4 | 414 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
415 | { |
416 | if (irqchip_in_kernel(vcpu->kvm)) | |
417 | return kvm_lapic_get_cr8(vcpu); | |
418 | else | |
ad312c7c | 419 | return vcpu->arch.cr8; |
a03490ed | 420 | } |
2d3ad1f4 | 421 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 422 | |
043405e1 CO |
423 | /* |
424 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
425 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
426 | * | |
427 | * This list is modified at module load time to reflect the | |
428 | * capabilities of the host cpu. | |
429 | */ | |
430 | static u32 msrs_to_save[] = { | |
431 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
432 | MSR_K6_STAR, | |
433 | #ifdef CONFIG_X86_64 | |
434 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
435 | #endif | |
18068523 | 436 | MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
847f0ad8 | 437 | MSR_IA32_PERF_STATUS, |
043405e1 CO |
438 | }; |
439 | ||
440 | static unsigned num_msrs_to_save; | |
441 | ||
442 | static u32 emulated_msrs[] = { | |
443 | MSR_IA32_MISC_ENABLE, | |
444 | }; | |
445 | ||
15c4a640 CO |
446 | static void set_efer(struct kvm_vcpu *vcpu, u64 efer) |
447 | { | |
f2b4b7dd | 448 | if (efer & efer_reserved_bits) { |
15c4a640 CO |
449 | printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n", |
450 | efer); | |
c1a5d4f9 | 451 | kvm_inject_gp(vcpu, 0); |
15c4a640 CO |
452 | return; |
453 | } | |
454 | ||
455 | if (is_paging(vcpu) | |
ad312c7c | 456 | && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) { |
15c4a640 | 457 | printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n"); |
c1a5d4f9 | 458 | kvm_inject_gp(vcpu, 0); |
15c4a640 CO |
459 | return; |
460 | } | |
461 | ||
462 | kvm_x86_ops->set_efer(vcpu, efer); | |
463 | ||
464 | efer &= ~EFER_LMA; | |
ad312c7c | 465 | efer |= vcpu->arch.shadow_efer & EFER_LMA; |
15c4a640 | 466 | |
ad312c7c | 467 | vcpu->arch.shadow_efer = efer; |
15c4a640 CO |
468 | } |
469 | ||
f2b4b7dd JR |
470 | void kvm_enable_efer_bits(u64 mask) |
471 | { | |
472 | efer_reserved_bits &= ~mask; | |
473 | } | |
474 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
475 | ||
476 | ||
15c4a640 CO |
477 | /* |
478 | * Writes msr value into into the appropriate "register". | |
479 | * Returns 0 on success, non-0 otherwise. | |
480 | * Assumes vcpu_load() was already called. | |
481 | */ | |
482 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
483 | { | |
484 | return kvm_x86_ops->set_msr(vcpu, msr_index, data); | |
485 | } | |
486 | ||
313a3dc7 CO |
487 | /* |
488 | * Adapt set_msr() to msr_io()'s calling convention | |
489 | */ | |
490 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
491 | { | |
492 | return kvm_set_msr(vcpu, index, *data); | |
493 | } | |
494 | ||
18068523 GOC |
495 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
496 | { | |
497 | static int version; | |
498 | struct kvm_wall_clock wc; | |
499 | struct timespec wc_ts; | |
500 | ||
501 | if (!wall_clock) | |
502 | return; | |
503 | ||
504 | version++; | |
505 | ||
506 | down_read(&kvm->slots_lock); | |
507 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
508 | ||
509 | wc_ts = current_kernel_time(); | |
510 | wc.wc_sec = wc_ts.tv_sec; | |
511 | wc.wc_nsec = wc_ts.tv_nsec; | |
512 | wc.wc_version = version; | |
513 | ||
514 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
515 | ||
516 | version++; | |
517 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
518 | up_read(&kvm->slots_lock); | |
519 | } | |
520 | ||
521 | static void kvm_write_guest_time(struct kvm_vcpu *v) | |
522 | { | |
523 | struct timespec ts; | |
524 | unsigned long flags; | |
525 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
526 | void *shared_kaddr; | |
527 | ||
528 | if ((!vcpu->time_page)) | |
529 | return; | |
530 | ||
531 | /* Keep irq disabled to prevent changes to the clock */ | |
532 | local_irq_save(flags); | |
533 | kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER, | |
534 | &vcpu->hv_clock.tsc_timestamp); | |
535 | ktime_get_ts(&ts); | |
536 | local_irq_restore(flags); | |
537 | ||
538 | /* With all the info we got, fill in the values */ | |
539 | ||
540 | vcpu->hv_clock.system_time = ts.tv_nsec + | |
541 | (NSEC_PER_SEC * (u64)ts.tv_sec); | |
542 | /* | |
543 | * The interface expects us to write an even number signaling that the | |
544 | * update is finished. Since the guest won't see the intermediate | |
545 | * state, we just write "2" at the end | |
546 | */ | |
547 | vcpu->hv_clock.version = 2; | |
548 | ||
549 | shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0); | |
550 | ||
551 | memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock, | |
552 | sizeof(vcpu->hv_clock)); | |
553 | ||
554 | kunmap_atomic(shared_kaddr, KM_USER0); | |
555 | ||
556 | mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT); | |
557 | } | |
558 | ||
15c4a640 CO |
559 | |
560 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
561 | { | |
562 | switch (msr) { | |
15c4a640 CO |
563 | case MSR_EFER: |
564 | set_efer(vcpu, data); | |
565 | break; | |
15c4a640 CO |
566 | case MSR_IA32_MC0_STATUS: |
567 | pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n", | |
b8688d51 | 568 | __func__, data); |
15c4a640 CO |
569 | break; |
570 | case MSR_IA32_MCG_STATUS: | |
571 | pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n", | |
b8688d51 | 572 | __func__, data); |
15c4a640 | 573 | break; |
c7ac679c JR |
574 | case MSR_IA32_MCG_CTL: |
575 | pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n", | |
b8688d51 | 576 | __func__, data); |
c7ac679c | 577 | break; |
15c4a640 CO |
578 | case MSR_IA32_UCODE_REV: |
579 | case MSR_IA32_UCODE_WRITE: | |
580 | case 0x200 ... 0x2ff: /* MTRRs */ | |
581 | break; | |
582 | case MSR_IA32_APICBASE: | |
583 | kvm_set_apic_base(vcpu, data); | |
584 | break; | |
585 | case MSR_IA32_MISC_ENABLE: | |
ad312c7c | 586 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 587 | break; |
18068523 GOC |
588 | case MSR_KVM_WALL_CLOCK: |
589 | vcpu->kvm->arch.wall_clock = data; | |
590 | kvm_write_wall_clock(vcpu->kvm, data); | |
591 | break; | |
592 | case MSR_KVM_SYSTEM_TIME: { | |
593 | if (vcpu->arch.time_page) { | |
594 | kvm_release_page_dirty(vcpu->arch.time_page); | |
595 | vcpu->arch.time_page = NULL; | |
596 | } | |
597 | ||
598 | vcpu->arch.time = data; | |
599 | ||
600 | /* we verify if the enable bit is set... */ | |
601 | if (!(data & 1)) | |
602 | break; | |
603 | ||
604 | /* ...but clean it before doing the actual write */ | |
605 | vcpu->arch.time_offset = data & ~(PAGE_MASK | 1); | |
606 | ||
607 | vcpu->arch.hv_clock.tsc_to_system_mul = | |
608 | clocksource_khz2mult(tsc_khz, 22); | |
609 | vcpu->arch.hv_clock.tsc_shift = 22; | |
610 | ||
611 | down_read(¤t->mm->mmap_sem); | |
612 | down_read(&vcpu->kvm->slots_lock); | |
613 | vcpu->arch.time_page = | |
614 | gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT); | |
615 | up_read(&vcpu->kvm->slots_lock); | |
616 | up_read(¤t->mm->mmap_sem); | |
617 | ||
618 | if (is_error_page(vcpu->arch.time_page)) { | |
619 | kvm_release_page_clean(vcpu->arch.time_page); | |
620 | vcpu->arch.time_page = NULL; | |
621 | } | |
622 | ||
623 | kvm_write_guest_time(vcpu); | |
624 | break; | |
625 | } | |
15c4a640 | 626 | default: |
565f1fbd | 627 | pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data); |
15c4a640 CO |
628 | return 1; |
629 | } | |
630 | return 0; | |
631 | } | |
632 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
633 | ||
634 | ||
635 | /* | |
636 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
637 | * Returns 0 on success, non-0 otherwise. | |
638 | * Assumes vcpu_load() was already called. | |
639 | */ | |
640 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
641 | { | |
642 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
643 | } | |
644 | ||
645 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
646 | { | |
647 | u64 data; | |
648 | ||
649 | switch (msr) { | |
650 | case 0xc0010010: /* SYSCFG */ | |
651 | case 0xc0010015: /* HWCR */ | |
652 | case MSR_IA32_PLATFORM_ID: | |
653 | case MSR_IA32_P5_MC_ADDR: | |
654 | case MSR_IA32_P5_MC_TYPE: | |
655 | case MSR_IA32_MC0_CTL: | |
656 | case MSR_IA32_MCG_STATUS: | |
657 | case MSR_IA32_MCG_CAP: | |
c7ac679c | 658 | case MSR_IA32_MCG_CTL: |
15c4a640 CO |
659 | case MSR_IA32_MC0_MISC: |
660 | case MSR_IA32_MC0_MISC+4: | |
661 | case MSR_IA32_MC0_MISC+8: | |
662 | case MSR_IA32_MC0_MISC+12: | |
663 | case MSR_IA32_MC0_MISC+16: | |
664 | case MSR_IA32_UCODE_REV: | |
15c4a640 CO |
665 | case MSR_IA32_EBL_CR_POWERON: |
666 | /* MTRR registers */ | |
667 | case 0xfe: | |
668 | case 0x200 ... 0x2ff: | |
669 | data = 0; | |
670 | break; | |
671 | case 0xcd: /* fsb frequency */ | |
672 | data = 3; | |
673 | break; | |
674 | case MSR_IA32_APICBASE: | |
675 | data = kvm_get_apic_base(vcpu); | |
676 | break; | |
677 | case MSR_IA32_MISC_ENABLE: | |
ad312c7c | 678 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 679 | break; |
847f0ad8 AG |
680 | case MSR_IA32_PERF_STATUS: |
681 | /* TSC increment by tick */ | |
682 | data = 1000ULL; | |
683 | /* CPU multiplier */ | |
684 | data |= (((uint64_t)4ULL) << 40); | |
685 | break; | |
15c4a640 | 686 | case MSR_EFER: |
ad312c7c | 687 | data = vcpu->arch.shadow_efer; |
15c4a640 | 688 | break; |
18068523 GOC |
689 | case MSR_KVM_WALL_CLOCK: |
690 | data = vcpu->kvm->arch.wall_clock; | |
691 | break; | |
692 | case MSR_KVM_SYSTEM_TIME: | |
693 | data = vcpu->arch.time; | |
694 | break; | |
15c4a640 CO |
695 | default: |
696 | pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); | |
697 | return 1; | |
698 | } | |
699 | *pdata = data; | |
700 | return 0; | |
701 | } | |
702 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
703 | ||
313a3dc7 CO |
704 | /* |
705 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
706 | * | |
707 | * @return number of msrs set successfully. | |
708 | */ | |
709 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
710 | struct kvm_msr_entry *entries, | |
711 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
712 | unsigned index, u64 *data)) | |
713 | { | |
714 | int i; | |
715 | ||
716 | vcpu_load(vcpu); | |
717 | ||
718 | for (i = 0; i < msrs->nmsrs; ++i) | |
719 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
720 | break; | |
721 | ||
722 | vcpu_put(vcpu); | |
723 | ||
724 | return i; | |
725 | } | |
726 | ||
727 | /* | |
728 | * Read or write a bunch of msrs. Parameters are user addresses. | |
729 | * | |
730 | * @return number of msrs set successfully. | |
731 | */ | |
732 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
733 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
734 | unsigned index, u64 *data), | |
735 | int writeback) | |
736 | { | |
737 | struct kvm_msrs msrs; | |
738 | struct kvm_msr_entry *entries; | |
739 | int r, n; | |
740 | unsigned size; | |
741 | ||
742 | r = -EFAULT; | |
743 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
744 | goto out; | |
745 | ||
746 | r = -E2BIG; | |
747 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
748 | goto out; | |
749 | ||
750 | r = -ENOMEM; | |
751 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; | |
752 | entries = vmalloc(size); | |
753 | if (!entries) | |
754 | goto out; | |
755 | ||
756 | r = -EFAULT; | |
757 | if (copy_from_user(entries, user_msrs->entries, size)) | |
758 | goto out_free; | |
759 | ||
760 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
761 | if (r < 0) | |
762 | goto out_free; | |
763 | ||
764 | r = -EFAULT; | |
765 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
766 | goto out_free; | |
767 | ||
768 | r = n; | |
769 | ||
770 | out_free: | |
771 | vfree(entries); | |
772 | out: | |
773 | return r; | |
774 | } | |
775 | ||
e9b11c17 ZX |
776 | /* |
777 | * Make sure that a cpu that is being hot-unplugged does not have any vcpus | |
778 | * cached on it. | |
779 | */ | |
780 | void decache_vcpus_on_cpu(int cpu) | |
781 | { | |
782 | struct kvm *vm; | |
783 | struct kvm_vcpu *vcpu; | |
784 | int i; | |
785 | ||
786 | spin_lock(&kvm_lock); | |
787 | list_for_each_entry(vm, &vm_list, vm_list) | |
788 | for (i = 0; i < KVM_MAX_VCPUS; ++i) { | |
789 | vcpu = vm->vcpus[i]; | |
790 | if (!vcpu) | |
791 | continue; | |
792 | /* | |
793 | * If the vcpu is locked, then it is running on some | |
794 | * other cpu and therefore it is not cached on the | |
795 | * cpu in question. | |
796 | * | |
797 | * If it's not locked, check the last cpu it executed | |
798 | * on. | |
799 | */ | |
800 | if (mutex_trylock(&vcpu->mutex)) { | |
801 | if (vcpu->cpu == cpu) { | |
802 | kvm_x86_ops->vcpu_decache(vcpu); | |
803 | vcpu->cpu = -1; | |
804 | } | |
805 | mutex_unlock(&vcpu->mutex); | |
806 | } | |
807 | } | |
808 | spin_unlock(&kvm_lock); | |
809 | } | |
810 | ||
018d00d2 ZX |
811 | int kvm_dev_ioctl_check_extension(long ext) |
812 | { | |
813 | int r; | |
814 | ||
815 | switch (ext) { | |
816 | case KVM_CAP_IRQCHIP: | |
817 | case KVM_CAP_HLT: | |
818 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
819 | case KVM_CAP_USER_MEMORY: | |
820 | case KVM_CAP_SET_TSS_ADDR: | |
07716717 | 821 | case KVM_CAP_EXT_CPUID: |
18068523 | 822 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 823 | case KVM_CAP_PIT: |
a28e4f5a | 824 | case KVM_CAP_NOP_IO_DELAY: |
018d00d2 ZX |
825 | r = 1; |
826 | break; | |
774ead3a AK |
827 | case KVM_CAP_VAPIC: |
828 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
829 | break; | |
f725230a AK |
830 | case KVM_CAP_NR_VCPUS: |
831 | r = KVM_MAX_VCPUS; | |
832 | break; | |
a988b910 AK |
833 | case KVM_CAP_NR_MEMSLOTS: |
834 | r = KVM_MEMORY_SLOTS; | |
835 | break; | |
2f333bcb MT |
836 | case KVM_CAP_PV_MMU: |
837 | r = !tdp_enabled; | |
838 | break; | |
018d00d2 ZX |
839 | default: |
840 | r = 0; | |
841 | break; | |
842 | } | |
843 | return r; | |
844 | ||
845 | } | |
846 | ||
043405e1 CO |
847 | long kvm_arch_dev_ioctl(struct file *filp, |
848 | unsigned int ioctl, unsigned long arg) | |
849 | { | |
850 | void __user *argp = (void __user *)arg; | |
851 | long r; | |
852 | ||
853 | switch (ioctl) { | |
854 | case KVM_GET_MSR_INDEX_LIST: { | |
855 | struct kvm_msr_list __user *user_msr_list = argp; | |
856 | struct kvm_msr_list msr_list; | |
857 | unsigned n; | |
858 | ||
859 | r = -EFAULT; | |
860 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
861 | goto out; | |
862 | n = msr_list.nmsrs; | |
863 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
864 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
865 | goto out; | |
866 | r = -E2BIG; | |
867 | if (n < num_msrs_to_save) | |
868 | goto out; | |
869 | r = -EFAULT; | |
870 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
871 | num_msrs_to_save * sizeof(u32))) | |
872 | goto out; | |
873 | if (copy_to_user(user_msr_list->indices | |
874 | + num_msrs_to_save * sizeof(u32), | |
875 | &emulated_msrs, | |
876 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
877 | goto out; | |
878 | r = 0; | |
879 | break; | |
880 | } | |
674eea0f AK |
881 | case KVM_GET_SUPPORTED_CPUID: { |
882 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
883 | struct kvm_cpuid2 cpuid; | |
884 | ||
885 | r = -EFAULT; | |
886 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
887 | goto out; | |
888 | r = kvm_dev_ioctl_get_supported_cpuid(&cpuid, | |
889 | cpuid_arg->entries); | |
890 | if (r) | |
891 | goto out; | |
892 | ||
893 | r = -EFAULT; | |
894 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
895 | goto out; | |
896 | r = 0; | |
897 | break; | |
898 | } | |
043405e1 CO |
899 | default: |
900 | r = -EINVAL; | |
901 | } | |
902 | out: | |
903 | return r; | |
904 | } | |
905 | ||
313a3dc7 CO |
906 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
907 | { | |
908 | kvm_x86_ops->vcpu_load(vcpu, cpu); | |
18068523 | 909 | kvm_write_guest_time(vcpu); |
313a3dc7 CO |
910 | } |
911 | ||
912 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
913 | { | |
914 | kvm_x86_ops->vcpu_put(vcpu); | |
9327fd11 | 915 | kvm_put_guest_fpu(vcpu); |
313a3dc7 CO |
916 | } |
917 | ||
07716717 | 918 | static int is_efer_nx(void) |
313a3dc7 CO |
919 | { |
920 | u64 efer; | |
313a3dc7 CO |
921 | |
922 | rdmsrl(MSR_EFER, efer); | |
07716717 DK |
923 | return efer & EFER_NX; |
924 | } | |
925 | ||
926 | static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) | |
927 | { | |
928 | int i; | |
929 | struct kvm_cpuid_entry2 *e, *entry; | |
930 | ||
313a3dc7 | 931 | entry = NULL; |
ad312c7c ZX |
932 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
933 | e = &vcpu->arch.cpuid_entries[i]; | |
313a3dc7 CO |
934 | if (e->function == 0x80000001) { |
935 | entry = e; | |
936 | break; | |
937 | } | |
938 | } | |
07716717 | 939 | if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) { |
313a3dc7 CO |
940 | entry->edx &= ~(1 << 20); |
941 | printk(KERN_INFO "kvm: guest NX capability removed\n"); | |
942 | } | |
943 | } | |
944 | ||
07716717 | 945 | /* when an old userspace process fills a new kernel module */ |
313a3dc7 CO |
946 | static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, |
947 | struct kvm_cpuid *cpuid, | |
948 | struct kvm_cpuid_entry __user *entries) | |
07716717 DK |
949 | { |
950 | int r, i; | |
951 | struct kvm_cpuid_entry *cpuid_entries; | |
952 | ||
953 | r = -E2BIG; | |
954 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
955 | goto out; | |
956 | r = -ENOMEM; | |
957 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent); | |
958 | if (!cpuid_entries) | |
959 | goto out; | |
960 | r = -EFAULT; | |
961 | if (copy_from_user(cpuid_entries, entries, | |
962 | cpuid->nent * sizeof(struct kvm_cpuid_entry))) | |
963 | goto out_free; | |
964 | for (i = 0; i < cpuid->nent; i++) { | |
ad312c7c ZX |
965 | vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; |
966 | vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; | |
967 | vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx; | |
968 | vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx; | |
969 | vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx; | |
970 | vcpu->arch.cpuid_entries[i].index = 0; | |
971 | vcpu->arch.cpuid_entries[i].flags = 0; | |
972 | vcpu->arch.cpuid_entries[i].padding[0] = 0; | |
973 | vcpu->arch.cpuid_entries[i].padding[1] = 0; | |
974 | vcpu->arch.cpuid_entries[i].padding[2] = 0; | |
975 | } | |
976 | vcpu->arch.cpuid_nent = cpuid->nent; | |
07716717 DK |
977 | cpuid_fix_nx_cap(vcpu); |
978 | r = 0; | |
979 | ||
980 | out_free: | |
981 | vfree(cpuid_entries); | |
982 | out: | |
983 | return r; | |
984 | } | |
985 | ||
986 | static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, | |
987 | struct kvm_cpuid2 *cpuid, | |
988 | struct kvm_cpuid_entry2 __user *entries) | |
313a3dc7 CO |
989 | { |
990 | int r; | |
991 | ||
992 | r = -E2BIG; | |
993 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
994 | goto out; | |
995 | r = -EFAULT; | |
ad312c7c | 996 | if (copy_from_user(&vcpu->arch.cpuid_entries, entries, |
07716717 | 997 | cpuid->nent * sizeof(struct kvm_cpuid_entry2))) |
313a3dc7 | 998 | goto out; |
ad312c7c | 999 | vcpu->arch.cpuid_nent = cpuid->nent; |
313a3dc7 CO |
1000 | return 0; |
1001 | ||
1002 | out: | |
1003 | return r; | |
1004 | } | |
1005 | ||
07716717 DK |
1006 | static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, |
1007 | struct kvm_cpuid2 *cpuid, | |
1008 | struct kvm_cpuid_entry2 __user *entries) | |
1009 | { | |
1010 | int r; | |
1011 | ||
1012 | r = -E2BIG; | |
ad312c7c | 1013 | if (cpuid->nent < vcpu->arch.cpuid_nent) |
07716717 DK |
1014 | goto out; |
1015 | r = -EFAULT; | |
ad312c7c ZX |
1016 | if (copy_to_user(entries, &vcpu->arch.cpuid_entries, |
1017 | vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) | |
07716717 DK |
1018 | goto out; |
1019 | return 0; | |
1020 | ||
1021 | out: | |
ad312c7c | 1022 | cpuid->nent = vcpu->arch.cpuid_nent; |
07716717 DK |
1023 | return r; |
1024 | } | |
1025 | ||
1026 | static inline u32 bit(int bitno) | |
1027 | { | |
1028 | return 1 << (bitno & 31); | |
1029 | } | |
1030 | ||
1031 | static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function, | |
1032 | u32 index) | |
1033 | { | |
1034 | entry->function = function; | |
1035 | entry->index = index; | |
1036 | cpuid_count(entry->function, entry->index, | |
1037 | &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); | |
1038 | entry->flags = 0; | |
1039 | } | |
1040 | ||
1041 | static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, | |
1042 | u32 index, int *nent, int maxnent) | |
1043 | { | |
1044 | const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) | | |
1045 | bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) | | |
1046 | bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) | | |
1047 | bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) | | |
1048 | bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) | | |
1049 | bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) | | |
1050 | bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) | | |
1051 | bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) | | |
1052 | bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) | | |
1053 | bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP); | |
1054 | const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) | | |
1055 | bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) | | |
1056 | bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) | | |
1057 | bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) | | |
1058 | bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) | | |
1059 | bit(X86_FEATURE_PGE) | | |
1060 | bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) | | |
1061 | bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) | | |
1062 | bit(X86_FEATURE_SYSCALL) | | |
1063 | (bit(X86_FEATURE_NX) && is_efer_nx()) | | |
1064 | #ifdef CONFIG_X86_64 | |
1065 | bit(X86_FEATURE_LM) | | |
1066 | #endif | |
1067 | bit(X86_FEATURE_MMXEXT) | | |
1068 | bit(X86_FEATURE_3DNOWEXT) | | |
1069 | bit(X86_FEATURE_3DNOW); | |
1070 | const u32 kvm_supported_word3_x86_features = | |
1071 | bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16); | |
1072 | const u32 kvm_supported_word6_x86_features = | |
1073 | bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY); | |
1074 | ||
1075 | /* all func 2 cpuid_count() should be called on the same cpu */ | |
1076 | get_cpu(); | |
1077 | do_cpuid_1_ent(entry, function, index); | |
1078 | ++*nent; | |
1079 | ||
1080 | switch (function) { | |
1081 | case 0: | |
1082 | entry->eax = min(entry->eax, (u32)0xb); | |
1083 | break; | |
1084 | case 1: | |
1085 | entry->edx &= kvm_supported_word0_x86_features; | |
1086 | entry->ecx &= kvm_supported_word3_x86_features; | |
1087 | break; | |
1088 | /* function 2 entries are STATEFUL. That is, repeated cpuid commands | |
1089 | * may return different values. This forces us to get_cpu() before | |
1090 | * issuing the first command, and also to emulate this annoying behavior | |
1091 | * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */ | |
1092 | case 2: { | |
1093 | int t, times = entry->eax & 0xff; | |
1094 | ||
1095 | entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
1096 | for (t = 1; t < times && *nent < maxnent; ++t) { | |
1097 | do_cpuid_1_ent(&entry[t], function, 0); | |
1098 | entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
1099 | ++*nent; | |
1100 | } | |
1101 | break; | |
1102 | } | |
1103 | /* function 4 and 0xb have additional index. */ | |
1104 | case 4: { | |
14af3f3c | 1105 | int i, cache_type; |
07716717 DK |
1106 | |
1107 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1108 | /* read more entries until cache_type is zero */ | |
14af3f3c HH |
1109 | for (i = 1; *nent < maxnent; ++i) { |
1110 | cache_type = entry[i - 1].eax & 0x1f; | |
07716717 DK |
1111 | if (!cache_type) |
1112 | break; | |
14af3f3c HH |
1113 | do_cpuid_1_ent(&entry[i], function, i); |
1114 | entry[i].flags |= | |
07716717 DK |
1115 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
1116 | ++*nent; | |
1117 | } | |
1118 | break; | |
1119 | } | |
1120 | case 0xb: { | |
14af3f3c | 1121 | int i, level_type; |
07716717 DK |
1122 | |
1123 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1124 | /* read more entries until level_type is zero */ | |
14af3f3c HH |
1125 | for (i = 1; *nent < maxnent; ++i) { |
1126 | level_type = entry[i - 1].ecx & 0xff; | |
07716717 DK |
1127 | if (!level_type) |
1128 | break; | |
14af3f3c HH |
1129 | do_cpuid_1_ent(&entry[i], function, i); |
1130 | entry[i].flags |= | |
07716717 DK |
1131 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
1132 | ++*nent; | |
1133 | } | |
1134 | break; | |
1135 | } | |
1136 | case 0x80000000: | |
1137 | entry->eax = min(entry->eax, 0x8000001a); | |
1138 | break; | |
1139 | case 0x80000001: | |
1140 | entry->edx &= kvm_supported_word1_x86_features; | |
1141 | entry->ecx &= kvm_supported_word6_x86_features; | |
1142 | break; | |
1143 | } | |
1144 | put_cpu(); | |
1145 | } | |
1146 | ||
674eea0f | 1147 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
07716717 DK |
1148 | struct kvm_cpuid_entry2 __user *entries) |
1149 | { | |
1150 | struct kvm_cpuid_entry2 *cpuid_entries; | |
1151 | int limit, nent = 0, r = -E2BIG; | |
1152 | u32 func; | |
1153 | ||
1154 | if (cpuid->nent < 1) | |
1155 | goto out; | |
1156 | r = -ENOMEM; | |
1157 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent); | |
1158 | if (!cpuid_entries) | |
1159 | goto out; | |
1160 | ||
1161 | do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent); | |
1162 | limit = cpuid_entries[0].eax; | |
1163 | for (func = 1; func <= limit && nent < cpuid->nent; ++func) | |
1164 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
1165 | &nent, cpuid->nent); | |
1166 | r = -E2BIG; | |
1167 | if (nent >= cpuid->nent) | |
1168 | goto out_free; | |
1169 | ||
1170 | do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent); | |
1171 | limit = cpuid_entries[nent - 1].eax; | |
1172 | for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func) | |
1173 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
1174 | &nent, cpuid->nent); | |
1175 | r = -EFAULT; | |
1176 | if (copy_to_user(entries, cpuid_entries, | |
1177 | nent * sizeof(struct kvm_cpuid_entry2))) | |
1178 | goto out_free; | |
1179 | cpuid->nent = nent; | |
1180 | r = 0; | |
1181 | ||
1182 | out_free: | |
1183 | vfree(cpuid_entries); | |
1184 | out: | |
1185 | return r; | |
1186 | } | |
1187 | ||
313a3dc7 CO |
1188 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
1189 | struct kvm_lapic_state *s) | |
1190 | { | |
1191 | vcpu_load(vcpu); | |
ad312c7c | 1192 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
1193 | vcpu_put(vcpu); |
1194 | ||
1195 | return 0; | |
1196 | } | |
1197 | ||
1198 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
1199 | struct kvm_lapic_state *s) | |
1200 | { | |
1201 | vcpu_load(vcpu); | |
ad312c7c | 1202 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); |
313a3dc7 CO |
1203 | kvm_apic_post_state_restore(vcpu); |
1204 | vcpu_put(vcpu); | |
1205 | ||
1206 | return 0; | |
1207 | } | |
1208 | ||
f77bc6a4 ZX |
1209 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
1210 | struct kvm_interrupt *irq) | |
1211 | { | |
1212 | if (irq->irq < 0 || irq->irq >= 256) | |
1213 | return -EINVAL; | |
1214 | if (irqchip_in_kernel(vcpu->kvm)) | |
1215 | return -ENXIO; | |
1216 | vcpu_load(vcpu); | |
1217 | ||
ad312c7c ZX |
1218 | set_bit(irq->irq, vcpu->arch.irq_pending); |
1219 | set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
f77bc6a4 ZX |
1220 | |
1221 | vcpu_put(vcpu); | |
1222 | ||
1223 | return 0; | |
1224 | } | |
1225 | ||
b209749f AK |
1226 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
1227 | struct kvm_tpr_access_ctl *tac) | |
1228 | { | |
1229 | if (tac->flags) | |
1230 | return -EINVAL; | |
1231 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
1232 | return 0; | |
1233 | } | |
1234 | ||
313a3dc7 CO |
1235 | long kvm_arch_vcpu_ioctl(struct file *filp, |
1236 | unsigned int ioctl, unsigned long arg) | |
1237 | { | |
1238 | struct kvm_vcpu *vcpu = filp->private_data; | |
1239 | void __user *argp = (void __user *)arg; | |
1240 | int r; | |
1241 | ||
1242 | switch (ioctl) { | |
1243 | case KVM_GET_LAPIC: { | |
1244 | struct kvm_lapic_state lapic; | |
1245 | ||
1246 | memset(&lapic, 0, sizeof lapic); | |
1247 | r = kvm_vcpu_ioctl_get_lapic(vcpu, &lapic); | |
1248 | if (r) | |
1249 | goto out; | |
1250 | r = -EFAULT; | |
1251 | if (copy_to_user(argp, &lapic, sizeof lapic)) | |
1252 | goto out; | |
1253 | r = 0; | |
1254 | break; | |
1255 | } | |
1256 | case KVM_SET_LAPIC: { | |
1257 | struct kvm_lapic_state lapic; | |
1258 | ||
1259 | r = -EFAULT; | |
1260 | if (copy_from_user(&lapic, argp, sizeof lapic)) | |
1261 | goto out; | |
1262 | r = kvm_vcpu_ioctl_set_lapic(vcpu, &lapic);; | |
1263 | if (r) | |
1264 | goto out; | |
1265 | r = 0; | |
1266 | break; | |
1267 | } | |
f77bc6a4 ZX |
1268 | case KVM_INTERRUPT: { |
1269 | struct kvm_interrupt irq; | |
1270 | ||
1271 | r = -EFAULT; | |
1272 | if (copy_from_user(&irq, argp, sizeof irq)) | |
1273 | goto out; | |
1274 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
1275 | if (r) | |
1276 | goto out; | |
1277 | r = 0; | |
1278 | break; | |
1279 | } | |
313a3dc7 CO |
1280 | case KVM_SET_CPUID: { |
1281 | struct kvm_cpuid __user *cpuid_arg = argp; | |
1282 | struct kvm_cpuid cpuid; | |
1283 | ||
1284 | r = -EFAULT; | |
1285 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1286 | goto out; | |
1287 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
1288 | if (r) | |
1289 | goto out; | |
1290 | break; | |
1291 | } | |
07716717 DK |
1292 | case KVM_SET_CPUID2: { |
1293 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
1294 | struct kvm_cpuid2 cpuid; | |
1295 | ||
1296 | r = -EFAULT; | |
1297 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1298 | goto out; | |
1299 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
1300 | cpuid_arg->entries); | |
1301 | if (r) | |
1302 | goto out; | |
1303 | break; | |
1304 | } | |
1305 | case KVM_GET_CPUID2: { | |
1306 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
1307 | struct kvm_cpuid2 cpuid; | |
1308 | ||
1309 | r = -EFAULT; | |
1310 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1311 | goto out; | |
1312 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
1313 | cpuid_arg->entries); | |
1314 | if (r) | |
1315 | goto out; | |
1316 | r = -EFAULT; | |
1317 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
1318 | goto out; | |
1319 | r = 0; | |
1320 | break; | |
1321 | } | |
313a3dc7 CO |
1322 | case KVM_GET_MSRS: |
1323 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
1324 | break; | |
1325 | case KVM_SET_MSRS: | |
1326 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
1327 | break; | |
b209749f AK |
1328 | case KVM_TPR_ACCESS_REPORTING: { |
1329 | struct kvm_tpr_access_ctl tac; | |
1330 | ||
1331 | r = -EFAULT; | |
1332 | if (copy_from_user(&tac, argp, sizeof tac)) | |
1333 | goto out; | |
1334 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
1335 | if (r) | |
1336 | goto out; | |
1337 | r = -EFAULT; | |
1338 | if (copy_to_user(argp, &tac, sizeof tac)) | |
1339 | goto out; | |
1340 | r = 0; | |
1341 | break; | |
1342 | }; | |
b93463aa AK |
1343 | case KVM_SET_VAPIC_ADDR: { |
1344 | struct kvm_vapic_addr va; | |
1345 | ||
1346 | r = -EINVAL; | |
1347 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1348 | goto out; | |
1349 | r = -EFAULT; | |
1350 | if (copy_from_user(&va, argp, sizeof va)) | |
1351 | goto out; | |
1352 | r = 0; | |
1353 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
1354 | break; | |
1355 | } | |
313a3dc7 CO |
1356 | default: |
1357 | r = -EINVAL; | |
1358 | } | |
1359 | out: | |
1360 | return r; | |
1361 | } | |
1362 | ||
1fe779f8 CO |
1363 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
1364 | { | |
1365 | int ret; | |
1366 | ||
1367 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
1368 | return -1; | |
1369 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); | |
1370 | return ret; | |
1371 | } | |
1372 | ||
1373 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, | |
1374 | u32 kvm_nr_mmu_pages) | |
1375 | { | |
1376 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
1377 | return -EINVAL; | |
1378 | ||
72dc67a6 | 1379 | down_write(&kvm->slots_lock); |
1fe779f8 CO |
1380 | |
1381 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 1382 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 1383 | |
72dc67a6 | 1384 | up_write(&kvm->slots_lock); |
1fe779f8 CO |
1385 | return 0; |
1386 | } | |
1387 | ||
1388 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
1389 | { | |
f05e70ac | 1390 | return kvm->arch.n_alloc_mmu_pages; |
1fe779f8 CO |
1391 | } |
1392 | ||
e9f85cde ZX |
1393 | gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn) |
1394 | { | |
1395 | int i; | |
1396 | struct kvm_mem_alias *alias; | |
1397 | ||
d69fb81f ZX |
1398 | for (i = 0; i < kvm->arch.naliases; ++i) { |
1399 | alias = &kvm->arch.aliases[i]; | |
e9f85cde ZX |
1400 | if (gfn >= alias->base_gfn |
1401 | && gfn < alias->base_gfn + alias->npages) | |
1402 | return alias->target_gfn + gfn - alias->base_gfn; | |
1403 | } | |
1404 | return gfn; | |
1405 | } | |
1406 | ||
1fe779f8 CO |
1407 | /* |
1408 | * Set a new alias region. Aliases map a portion of physical memory into | |
1409 | * another portion. This is useful for memory windows, for example the PC | |
1410 | * VGA region. | |
1411 | */ | |
1412 | static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm, | |
1413 | struct kvm_memory_alias *alias) | |
1414 | { | |
1415 | int r, n; | |
1416 | struct kvm_mem_alias *p; | |
1417 | ||
1418 | r = -EINVAL; | |
1419 | /* General sanity checks */ | |
1420 | if (alias->memory_size & (PAGE_SIZE - 1)) | |
1421 | goto out; | |
1422 | if (alias->guest_phys_addr & (PAGE_SIZE - 1)) | |
1423 | goto out; | |
1424 | if (alias->slot >= KVM_ALIAS_SLOTS) | |
1425 | goto out; | |
1426 | if (alias->guest_phys_addr + alias->memory_size | |
1427 | < alias->guest_phys_addr) | |
1428 | goto out; | |
1429 | if (alias->target_phys_addr + alias->memory_size | |
1430 | < alias->target_phys_addr) | |
1431 | goto out; | |
1432 | ||
72dc67a6 | 1433 | down_write(&kvm->slots_lock); |
1fe779f8 | 1434 | |
d69fb81f | 1435 | p = &kvm->arch.aliases[alias->slot]; |
1fe779f8 CO |
1436 | p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT; |
1437 | p->npages = alias->memory_size >> PAGE_SHIFT; | |
1438 | p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT; | |
1439 | ||
1440 | for (n = KVM_ALIAS_SLOTS; n > 0; --n) | |
d69fb81f | 1441 | if (kvm->arch.aliases[n - 1].npages) |
1fe779f8 | 1442 | break; |
d69fb81f | 1443 | kvm->arch.naliases = n; |
1fe779f8 CO |
1444 | |
1445 | kvm_mmu_zap_all(kvm); | |
1446 | ||
72dc67a6 | 1447 | up_write(&kvm->slots_lock); |
1fe779f8 CO |
1448 | |
1449 | return 0; | |
1450 | ||
1451 | out: | |
1452 | return r; | |
1453 | } | |
1454 | ||
1455 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
1456 | { | |
1457 | int r; | |
1458 | ||
1459 | r = 0; | |
1460 | switch (chip->chip_id) { | |
1461 | case KVM_IRQCHIP_PIC_MASTER: | |
1462 | memcpy(&chip->chip.pic, | |
1463 | &pic_irqchip(kvm)->pics[0], | |
1464 | sizeof(struct kvm_pic_state)); | |
1465 | break; | |
1466 | case KVM_IRQCHIP_PIC_SLAVE: | |
1467 | memcpy(&chip->chip.pic, | |
1468 | &pic_irqchip(kvm)->pics[1], | |
1469 | sizeof(struct kvm_pic_state)); | |
1470 | break; | |
1471 | case KVM_IRQCHIP_IOAPIC: | |
1472 | memcpy(&chip->chip.ioapic, | |
1473 | ioapic_irqchip(kvm), | |
1474 | sizeof(struct kvm_ioapic_state)); | |
1475 | break; | |
1476 | default: | |
1477 | r = -EINVAL; | |
1478 | break; | |
1479 | } | |
1480 | return r; | |
1481 | } | |
1482 | ||
1483 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
1484 | { | |
1485 | int r; | |
1486 | ||
1487 | r = 0; | |
1488 | switch (chip->chip_id) { | |
1489 | case KVM_IRQCHIP_PIC_MASTER: | |
1490 | memcpy(&pic_irqchip(kvm)->pics[0], | |
1491 | &chip->chip.pic, | |
1492 | sizeof(struct kvm_pic_state)); | |
1493 | break; | |
1494 | case KVM_IRQCHIP_PIC_SLAVE: | |
1495 | memcpy(&pic_irqchip(kvm)->pics[1], | |
1496 | &chip->chip.pic, | |
1497 | sizeof(struct kvm_pic_state)); | |
1498 | break; | |
1499 | case KVM_IRQCHIP_IOAPIC: | |
1500 | memcpy(ioapic_irqchip(kvm), | |
1501 | &chip->chip.ioapic, | |
1502 | sizeof(struct kvm_ioapic_state)); | |
1503 | break; | |
1504 | default: | |
1505 | r = -EINVAL; | |
1506 | break; | |
1507 | } | |
1508 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
1509 | return r; | |
1510 | } | |
1511 | ||
e0f63cb9 SY |
1512 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
1513 | { | |
1514 | int r = 0; | |
1515 | ||
1516 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); | |
1517 | return r; | |
1518 | } | |
1519 | ||
1520 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
1521 | { | |
1522 | int r = 0; | |
1523 | ||
1524 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); | |
1525 | kvm_pit_load_count(kvm, 0, ps->channels[0].count); | |
1526 | return r; | |
1527 | } | |
1528 | ||
5bb064dc ZX |
1529 | /* |
1530 | * Get (and clear) the dirty memory log for a memory slot. | |
1531 | */ | |
1532 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, | |
1533 | struct kvm_dirty_log *log) | |
1534 | { | |
1535 | int r; | |
1536 | int n; | |
1537 | struct kvm_memory_slot *memslot; | |
1538 | int is_dirty = 0; | |
1539 | ||
72dc67a6 | 1540 | down_write(&kvm->slots_lock); |
5bb064dc ZX |
1541 | |
1542 | r = kvm_get_dirty_log(kvm, log, &is_dirty); | |
1543 | if (r) | |
1544 | goto out; | |
1545 | ||
1546 | /* If nothing is dirty, don't bother messing with page tables. */ | |
1547 | if (is_dirty) { | |
1548 | kvm_mmu_slot_remove_write_access(kvm, log->slot); | |
1549 | kvm_flush_remote_tlbs(kvm); | |
1550 | memslot = &kvm->memslots[log->slot]; | |
1551 | n = ALIGN(memslot->npages, BITS_PER_LONG) / 8; | |
1552 | memset(memslot->dirty_bitmap, 0, n); | |
1553 | } | |
1554 | r = 0; | |
1555 | out: | |
72dc67a6 | 1556 | up_write(&kvm->slots_lock); |
5bb064dc ZX |
1557 | return r; |
1558 | } | |
1559 | ||
1fe779f8 CO |
1560 | long kvm_arch_vm_ioctl(struct file *filp, |
1561 | unsigned int ioctl, unsigned long arg) | |
1562 | { | |
1563 | struct kvm *kvm = filp->private_data; | |
1564 | void __user *argp = (void __user *)arg; | |
1565 | int r = -EINVAL; | |
1566 | ||
1567 | switch (ioctl) { | |
1568 | case KVM_SET_TSS_ADDR: | |
1569 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1570 | if (r < 0) | |
1571 | goto out; | |
1572 | break; | |
1573 | case KVM_SET_MEMORY_REGION: { | |
1574 | struct kvm_memory_region kvm_mem; | |
1575 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
1576 | ||
1577 | r = -EFAULT; | |
1578 | if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem)) | |
1579 | goto out; | |
1580 | kvm_userspace_mem.slot = kvm_mem.slot; | |
1581 | kvm_userspace_mem.flags = kvm_mem.flags; | |
1582 | kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr; | |
1583 | kvm_userspace_mem.memory_size = kvm_mem.memory_size; | |
1584 | r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
1585 | if (r) | |
1586 | goto out; | |
1587 | break; | |
1588 | } | |
1589 | case KVM_SET_NR_MMU_PAGES: | |
1590 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1591 | if (r) | |
1592 | goto out; | |
1593 | break; | |
1594 | case KVM_GET_NR_MMU_PAGES: | |
1595 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
1596 | break; | |
1597 | case KVM_SET_MEMORY_ALIAS: { | |
1598 | struct kvm_memory_alias alias; | |
1599 | ||
1600 | r = -EFAULT; | |
1601 | if (copy_from_user(&alias, argp, sizeof alias)) | |
1602 | goto out; | |
1603 | r = kvm_vm_ioctl_set_memory_alias(kvm, &alias); | |
1604 | if (r) | |
1605 | goto out; | |
1606 | break; | |
1607 | } | |
1608 | case KVM_CREATE_IRQCHIP: | |
1609 | r = -ENOMEM; | |
d7deeeb0 ZX |
1610 | kvm->arch.vpic = kvm_create_pic(kvm); |
1611 | if (kvm->arch.vpic) { | |
1fe779f8 CO |
1612 | r = kvm_ioapic_init(kvm); |
1613 | if (r) { | |
d7deeeb0 ZX |
1614 | kfree(kvm->arch.vpic); |
1615 | kvm->arch.vpic = NULL; | |
1fe779f8 CO |
1616 | goto out; |
1617 | } | |
1618 | } else | |
1619 | goto out; | |
1620 | break; | |
7837699f SY |
1621 | case KVM_CREATE_PIT: |
1622 | r = -ENOMEM; | |
1623 | kvm->arch.vpit = kvm_create_pit(kvm); | |
1624 | if (kvm->arch.vpit) | |
1625 | r = 0; | |
1626 | break; | |
1fe779f8 CO |
1627 | case KVM_IRQ_LINE: { |
1628 | struct kvm_irq_level irq_event; | |
1629 | ||
1630 | r = -EFAULT; | |
1631 | if (copy_from_user(&irq_event, argp, sizeof irq_event)) | |
1632 | goto out; | |
1633 | if (irqchip_in_kernel(kvm)) { | |
1634 | mutex_lock(&kvm->lock); | |
1635 | if (irq_event.irq < 16) | |
1636 | kvm_pic_set_irq(pic_irqchip(kvm), | |
1637 | irq_event.irq, | |
1638 | irq_event.level); | |
d7deeeb0 | 1639 | kvm_ioapic_set_irq(kvm->arch.vioapic, |
1fe779f8 CO |
1640 | irq_event.irq, |
1641 | irq_event.level); | |
1642 | mutex_unlock(&kvm->lock); | |
1643 | r = 0; | |
1644 | } | |
1645 | break; | |
1646 | } | |
1647 | case KVM_GET_IRQCHIP: { | |
1648 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
1649 | struct kvm_irqchip chip; | |
1650 | ||
1651 | r = -EFAULT; | |
1652 | if (copy_from_user(&chip, argp, sizeof chip)) | |
1653 | goto out; | |
1654 | r = -ENXIO; | |
1655 | if (!irqchip_in_kernel(kvm)) | |
1656 | goto out; | |
1657 | r = kvm_vm_ioctl_get_irqchip(kvm, &chip); | |
1658 | if (r) | |
1659 | goto out; | |
1660 | r = -EFAULT; | |
1661 | if (copy_to_user(argp, &chip, sizeof chip)) | |
1662 | goto out; | |
1663 | r = 0; | |
1664 | break; | |
1665 | } | |
1666 | case KVM_SET_IRQCHIP: { | |
1667 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
1668 | struct kvm_irqchip chip; | |
1669 | ||
1670 | r = -EFAULT; | |
1671 | if (copy_from_user(&chip, argp, sizeof chip)) | |
1672 | goto out; | |
1673 | r = -ENXIO; | |
1674 | if (!irqchip_in_kernel(kvm)) | |
1675 | goto out; | |
1676 | r = kvm_vm_ioctl_set_irqchip(kvm, &chip); | |
1677 | if (r) | |
1678 | goto out; | |
1679 | r = 0; | |
1680 | break; | |
1681 | } | |
e0f63cb9 SY |
1682 | case KVM_GET_PIT: { |
1683 | struct kvm_pit_state ps; | |
1684 | r = -EFAULT; | |
1685 | if (copy_from_user(&ps, argp, sizeof ps)) | |
1686 | goto out; | |
1687 | r = -ENXIO; | |
1688 | if (!kvm->arch.vpit) | |
1689 | goto out; | |
1690 | r = kvm_vm_ioctl_get_pit(kvm, &ps); | |
1691 | if (r) | |
1692 | goto out; | |
1693 | r = -EFAULT; | |
1694 | if (copy_to_user(argp, &ps, sizeof ps)) | |
1695 | goto out; | |
1696 | r = 0; | |
1697 | break; | |
1698 | } | |
1699 | case KVM_SET_PIT: { | |
1700 | struct kvm_pit_state ps; | |
1701 | r = -EFAULT; | |
1702 | if (copy_from_user(&ps, argp, sizeof ps)) | |
1703 | goto out; | |
1704 | r = -ENXIO; | |
1705 | if (!kvm->arch.vpit) | |
1706 | goto out; | |
1707 | r = kvm_vm_ioctl_set_pit(kvm, &ps); | |
1708 | if (r) | |
1709 | goto out; | |
1710 | r = 0; | |
1711 | break; | |
1712 | } | |
1fe779f8 CO |
1713 | default: |
1714 | ; | |
1715 | } | |
1716 | out: | |
1717 | return r; | |
1718 | } | |
1719 | ||
a16b043c | 1720 | static void kvm_init_msr_list(void) |
043405e1 CO |
1721 | { |
1722 | u32 dummy[2]; | |
1723 | unsigned i, j; | |
1724 | ||
1725 | for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { | |
1726 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) | |
1727 | continue; | |
1728 | if (j < i) | |
1729 | msrs_to_save[j] = msrs_to_save[i]; | |
1730 | j++; | |
1731 | } | |
1732 | num_msrs_to_save = j; | |
1733 | } | |
1734 | ||
bbd9b64e CO |
1735 | /* |
1736 | * Only apic need an MMIO device hook, so shortcut now.. | |
1737 | */ | |
1738 | static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu, | |
1739 | gpa_t addr) | |
1740 | { | |
1741 | struct kvm_io_device *dev; | |
1742 | ||
ad312c7c ZX |
1743 | if (vcpu->arch.apic) { |
1744 | dev = &vcpu->arch.apic->dev; | |
bbd9b64e CO |
1745 | if (dev->in_range(dev, addr)) |
1746 | return dev; | |
1747 | } | |
1748 | return NULL; | |
1749 | } | |
1750 | ||
1751 | ||
1752 | static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu, | |
1753 | gpa_t addr) | |
1754 | { | |
1755 | struct kvm_io_device *dev; | |
1756 | ||
1757 | dev = vcpu_find_pervcpu_dev(vcpu, addr); | |
1758 | if (dev == NULL) | |
1759 | dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr); | |
1760 | return dev; | |
1761 | } | |
1762 | ||
1763 | int emulator_read_std(unsigned long addr, | |
1764 | void *val, | |
1765 | unsigned int bytes, | |
1766 | struct kvm_vcpu *vcpu) | |
1767 | { | |
1768 | void *data = val; | |
10589a46 | 1769 | int r = X86EMUL_CONTINUE; |
bbd9b64e | 1770 | |
72dc67a6 | 1771 | down_read(&vcpu->kvm->slots_lock); |
bbd9b64e | 1772 | while (bytes) { |
ad312c7c | 1773 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
bbd9b64e CO |
1774 | unsigned offset = addr & (PAGE_SIZE-1); |
1775 | unsigned tocopy = min(bytes, (unsigned)PAGE_SIZE - offset); | |
1776 | int ret; | |
1777 | ||
10589a46 MT |
1778 | if (gpa == UNMAPPED_GVA) { |
1779 | r = X86EMUL_PROPAGATE_FAULT; | |
1780 | goto out; | |
1781 | } | |
bbd9b64e | 1782 | ret = kvm_read_guest(vcpu->kvm, gpa, data, tocopy); |
10589a46 MT |
1783 | if (ret < 0) { |
1784 | r = X86EMUL_UNHANDLEABLE; | |
1785 | goto out; | |
1786 | } | |
bbd9b64e CO |
1787 | |
1788 | bytes -= tocopy; | |
1789 | data += tocopy; | |
1790 | addr += tocopy; | |
1791 | } | |
10589a46 | 1792 | out: |
72dc67a6 | 1793 | up_read(&vcpu->kvm->slots_lock); |
10589a46 | 1794 | return r; |
bbd9b64e CO |
1795 | } |
1796 | EXPORT_SYMBOL_GPL(emulator_read_std); | |
1797 | ||
bbd9b64e CO |
1798 | static int emulator_read_emulated(unsigned long addr, |
1799 | void *val, | |
1800 | unsigned int bytes, | |
1801 | struct kvm_vcpu *vcpu) | |
1802 | { | |
1803 | struct kvm_io_device *mmio_dev; | |
1804 | gpa_t gpa; | |
1805 | ||
1806 | if (vcpu->mmio_read_completed) { | |
1807 | memcpy(val, vcpu->mmio_data, bytes); | |
1808 | vcpu->mmio_read_completed = 0; | |
1809 | return X86EMUL_CONTINUE; | |
1810 | } | |
1811 | ||
72dc67a6 | 1812 | down_read(&vcpu->kvm->slots_lock); |
ad312c7c | 1813 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
72dc67a6 | 1814 | up_read(&vcpu->kvm->slots_lock); |
bbd9b64e CO |
1815 | |
1816 | /* For APIC access vmexit */ | |
1817 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
1818 | goto mmio; | |
1819 | ||
1820 | if (emulator_read_std(addr, val, bytes, vcpu) | |
1821 | == X86EMUL_CONTINUE) | |
1822 | return X86EMUL_CONTINUE; | |
1823 | if (gpa == UNMAPPED_GVA) | |
1824 | return X86EMUL_PROPAGATE_FAULT; | |
1825 | ||
1826 | mmio: | |
1827 | /* | |
1828 | * Is this MMIO handled locally? | |
1829 | */ | |
10589a46 | 1830 | mutex_lock(&vcpu->kvm->lock); |
bbd9b64e CO |
1831 | mmio_dev = vcpu_find_mmio_dev(vcpu, gpa); |
1832 | if (mmio_dev) { | |
1833 | kvm_iodevice_read(mmio_dev, gpa, bytes, val); | |
10589a46 | 1834 | mutex_unlock(&vcpu->kvm->lock); |
bbd9b64e CO |
1835 | return X86EMUL_CONTINUE; |
1836 | } | |
10589a46 | 1837 | mutex_unlock(&vcpu->kvm->lock); |
bbd9b64e CO |
1838 | |
1839 | vcpu->mmio_needed = 1; | |
1840 | vcpu->mmio_phys_addr = gpa; | |
1841 | vcpu->mmio_size = bytes; | |
1842 | vcpu->mmio_is_write = 0; | |
1843 | ||
1844 | return X86EMUL_UNHANDLEABLE; | |
1845 | } | |
1846 | ||
9f811285 AK |
1847 | int __emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
1848 | const void *val, int bytes) | |
bbd9b64e CO |
1849 | { |
1850 | int ret; | |
1851 | ||
1852 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 1853 | if (ret < 0) |
bbd9b64e CO |
1854 | return 0; |
1855 | kvm_mmu_pte_write(vcpu, gpa, val, bytes); | |
1856 | return 1; | |
1857 | } | |
1858 | ||
9f811285 AK |
1859 | static int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
1860 | const void *val, int bytes) | |
1861 | { | |
1862 | int ret; | |
1863 | ||
1864 | down_read(&vcpu->kvm->slots_lock); | |
1865 | ret =__emulator_write_phys(vcpu, gpa, val, bytes); | |
1866 | up_read(&vcpu->kvm->slots_lock); | |
1867 | return ret; | |
1868 | } | |
1869 | ||
bbd9b64e CO |
1870 | static int emulator_write_emulated_onepage(unsigned long addr, |
1871 | const void *val, | |
1872 | unsigned int bytes, | |
1873 | struct kvm_vcpu *vcpu) | |
1874 | { | |
1875 | struct kvm_io_device *mmio_dev; | |
10589a46 MT |
1876 | gpa_t gpa; |
1877 | ||
72dc67a6 | 1878 | down_read(&vcpu->kvm->slots_lock); |
10589a46 | 1879 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
72dc67a6 | 1880 | up_read(&vcpu->kvm->slots_lock); |
bbd9b64e CO |
1881 | |
1882 | if (gpa == UNMAPPED_GVA) { | |
c3c91fee | 1883 | kvm_inject_page_fault(vcpu, addr, 2); |
bbd9b64e CO |
1884 | return X86EMUL_PROPAGATE_FAULT; |
1885 | } | |
1886 | ||
1887 | /* For APIC access vmexit */ | |
1888 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
1889 | goto mmio; | |
1890 | ||
1891 | if (emulator_write_phys(vcpu, gpa, val, bytes)) | |
1892 | return X86EMUL_CONTINUE; | |
1893 | ||
1894 | mmio: | |
1895 | /* | |
1896 | * Is this MMIO handled locally? | |
1897 | */ | |
10589a46 | 1898 | mutex_lock(&vcpu->kvm->lock); |
bbd9b64e CO |
1899 | mmio_dev = vcpu_find_mmio_dev(vcpu, gpa); |
1900 | if (mmio_dev) { | |
1901 | kvm_iodevice_write(mmio_dev, gpa, bytes, val); | |
10589a46 | 1902 | mutex_unlock(&vcpu->kvm->lock); |
bbd9b64e CO |
1903 | return X86EMUL_CONTINUE; |
1904 | } | |
10589a46 | 1905 | mutex_unlock(&vcpu->kvm->lock); |
bbd9b64e CO |
1906 | |
1907 | vcpu->mmio_needed = 1; | |
1908 | vcpu->mmio_phys_addr = gpa; | |
1909 | vcpu->mmio_size = bytes; | |
1910 | vcpu->mmio_is_write = 1; | |
1911 | memcpy(vcpu->mmio_data, val, bytes); | |
1912 | ||
1913 | return X86EMUL_CONTINUE; | |
1914 | } | |
1915 | ||
1916 | int emulator_write_emulated(unsigned long addr, | |
1917 | const void *val, | |
1918 | unsigned int bytes, | |
1919 | struct kvm_vcpu *vcpu) | |
1920 | { | |
1921 | /* Crossing a page boundary? */ | |
1922 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
1923 | int rc, now; | |
1924 | ||
1925 | now = -addr & ~PAGE_MASK; | |
1926 | rc = emulator_write_emulated_onepage(addr, val, now, vcpu); | |
1927 | if (rc != X86EMUL_CONTINUE) | |
1928 | return rc; | |
1929 | addr += now; | |
1930 | val += now; | |
1931 | bytes -= now; | |
1932 | } | |
1933 | return emulator_write_emulated_onepage(addr, val, bytes, vcpu); | |
1934 | } | |
1935 | EXPORT_SYMBOL_GPL(emulator_write_emulated); | |
1936 | ||
1937 | static int emulator_cmpxchg_emulated(unsigned long addr, | |
1938 | const void *old, | |
1939 | const void *new, | |
1940 | unsigned int bytes, | |
1941 | struct kvm_vcpu *vcpu) | |
1942 | { | |
1943 | static int reported; | |
1944 | ||
1945 | if (!reported) { | |
1946 | reported = 1; | |
1947 | printk(KERN_WARNING "kvm: emulating exchange as write\n"); | |
1948 | } | |
2bacc55c MT |
1949 | #ifndef CONFIG_X86_64 |
1950 | /* guests cmpxchg8b have to be emulated atomically */ | |
1951 | if (bytes == 8) { | |
10589a46 | 1952 | gpa_t gpa; |
2bacc55c | 1953 | struct page *page; |
c0b49b0d | 1954 | char *kaddr; |
2bacc55c MT |
1955 | u64 val; |
1956 | ||
72dc67a6 | 1957 | down_read(&vcpu->kvm->slots_lock); |
10589a46 MT |
1958 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
1959 | ||
2bacc55c MT |
1960 | if (gpa == UNMAPPED_GVA || |
1961 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
1962 | goto emul_write; | |
1963 | ||
1964 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) | |
1965 | goto emul_write; | |
1966 | ||
1967 | val = *(u64 *)new; | |
72dc67a6 IE |
1968 | |
1969 | down_read(¤t->mm->mmap_sem); | |
2bacc55c | 1970 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
72dc67a6 IE |
1971 | up_read(¤t->mm->mmap_sem); |
1972 | ||
c0b49b0d AM |
1973 | kaddr = kmap_atomic(page, KM_USER0); |
1974 | set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val); | |
1975 | kunmap_atomic(kaddr, KM_USER0); | |
2bacc55c | 1976 | kvm_release_page_dirty(page); |
10589a46 | 1977 | emul_write: |
72dc67a6 | 1978 | up_read(&vcpu->kvm->slots_lock); |
2bacc55c | 1979 | } |
2bacc55c MT |
1980 | #endif |
1981 | ||
bbd9b64e CO |
1982 | return emulator_write_emulated(addr, new, bytes, vcpu); |
1983 | } | |
1984 | ||
1985 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1986 | { | |
1987 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
1988 | } | |
1989 | ||
1990 | int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
1991 | { | |
1992 | return X86EMUL_CONTINUE; | |
1993 | } | |
1994 | ||
1995 | int emulate_clts(struct kvm_vcpu *vcpu) | |
1996 | { | |
ad312c7c | 1997 | kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS); |
bbd9b64e CO |
1998 | return X86EMUL_CONTINUE; |
1999 | } | |
2000 | ||
2001 | int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) | |
2002 | { | |
2003 | struct kvm_vcpu *vcpu = ctxt->vcpu; | |
2004 | ||
2005 | switch (dr) { | |
2006 | case 0 ... 3: | |
2007 | *dest = kvm_x86_ops->get_dr(vcpu, dr); | |
2008 | return X86EMUL_CONTINUE; | |
2009 | default: | |
b8688d51 | 2010 | pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr); |
bbd9b64e CO |
2011 | return X86EMUL_UNHANDLEABLE; |
2012 | } | |
2013 | } | |
2014 | ||
2015 | int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) | |
2016 | { | |
2017 | unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U; | |
2018 | int exception; | |
2019 | ||
2020 | kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception); | |
2021 | if (exception) { | |
2022 | /* FIXME: better handling */ | |
2023 | return X86EMUL_UNHANDLEABLE; | |
2024 | } | |
2025 | return X86EMUL_CONTINUE; | |
2026 | } | |
2027 | ||
2028 | void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context) | |
2029 | { | |
2030 | static int reported; | |
2031 | u8 opcodes[4]; | |
ad312c7c | 2032 | unsigned long rip = vcpu->arch.rip; |
bbd9b64e CO |
2033 | unsigned long rip_linear; |
2034 | ||
2035 | rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS); | |
2036 | ||
2037 | if (reported) | |
2038 | return; | |
2039 | ||
2040 | emulator_read_std(rip_linear, (void *)opcodes, 4, vcpu); | |
2041 | ||
2042 | printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n", | |
2043 | context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]); | |
2044 | reported = 1; | |
2045 | } | |
2046 | EXPORT_SYMBOL_GPL(kvm_report_emulation_failure); | |
2047 | ||
14af3f3c | 2048 | static struct x86_emulate_ops emulate_ops = { |
bbd9b64e | 2049 | .read_std = emulator_read_std, |
bbd9b64e CO |
2050 | .read_emulated = emulator_read_emulated, |
2051 | .write_emulated = emulator_write_emulated, | |
2052 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
2053 | }; | |
2054 | ||
2055 | int emulate_instruction(struct kvm_vcpu *vcpu, | |
2056 | struct kvm_run *run, | |
2057 | unsigned long cr2, | |
2058 | u16 error_code, | |
571008da | 2059 | int emulation_type) |
bbd9b64e CO |
2060 | { |
2061 | int r; | |
571008da | 2062 | struct decode_cache *c; |
bbd9b64e | 2063 | |
ad312c7c | 2064 | vcpu->arch.mmio_fault_cr2 = cr2; |
bbd9b64e CO |
2065 | kvm_x86_ops->cache_regs(vcpu); |
2066 | ||
2067 | vcpu->mmio_is_write = 0; | |
ad312c7c | 2068 | vcpu->arch.pio.string = 0; |
bbd9b64e | 2069 | |
571008da | 2070 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
bbd9b64e CO |
2071 | int cs_db, cs_l; |
2072 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
2073 | ||
ad312c7c ZX |
2074 | vcpu->arch.emulate_ctxt.vcpu = vcpu; |
2075 | vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu); | |
2076 | vcpu->arch.emulate_ctxt.mode = | |
2077 | (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM) | |
bbd9b64e CO |
2078 | ? X86EMUL_MODE_REAL : cs_l |
2079 | ? X86EMUL_MODE_PROT64 : cs_db | |
2080 | ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; | |
2081 | ||
ad312c7c ZX |
2082 | if (vcpu->arch.emulate_ctxt.mode == X86EMUL_MODE_PROT64) { |
2083 | vcpu->arch.emulate_ctxt.cs_base = 0; | |
2084 | vcpu->arch.emulate_ctxt.ds_base = 0; | |
2085 | vcpu->arch.emulate_ctxt.es_base = 0; | |
2086 | vcpu->arch.emulate_ctxt.ss_base = 0; | |
bbd9b64e | 2087 | } else { |
ad312c7c | 2088 | vcpu->arch.emulate_ctxt.cs_base = |
bbd9b64e | 2089 | get_segment_base(vcpu, VCPU_SREG_CS); |
ad312c7c | 2090 | vcpu->arch.emulate_ctxt.ds_base = |
bbd9b64e | 2091 | get_segment_base(vcpu, VCPU_SREG_DS); |
ad312c7c | 2092 | vcpu->arch.emulate_ctxt.es_base = |
bbd9b64e | 2093 | get_segment_base(vcpu, VCPU_SREG_ES); |
ad312c7c | 2094 | vcpu->arch.emulate_ctxt.ss_base = |
bbd9b64e CO |
2095 | get_segment_base(vcpu, VCPU_SREG_SS); |
2096 | } | |
2097 | ||
ad312c7c | 2098 | vcpu->arch.emulate_ctxt.gs_base = |
bbd9b64e | 2099 | get_segment_base(vcpu, VCPU_SREG_GS); |
ad312c7c | 2100 | vcpu->arch.emulate_ctxt.fs_base = |
bbd9b64e CO |
2101 | get_segment_base(vcpu, VCPU_SREG_FS); |
2102 | ||
ad312c7c | 2103 | r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); |
571008da SY |
2104 | |
2105 | /* Reject the instructions other than VMCALL/VMMCALL when | |
2106 | * try to emulate invalid opcode */ | |
2107 | c = &vcpu->arch.emulate_ctxt.decode; | |
2108 | if ((emulation_type & EMULTYPE_TRAP_UD) && | |
2109 | (!(c->twobyte && c->b == 0x01 && | |
2110 | (c->modrm_reg == 0 || c->modrm_reg == 3) && | |
2111 | c->modrm_mod == 3 && c->modrm_rm == 1))) | |
2112 | return EMULATE_FAIL; | |
2113 | ||
f2b5756b | 2114 | ++vcpu->stat.insn_emulation; |
bbd9b64e | 2115 | if (r) { |
f2b5756b | 2116 | ++vcpu->stat.insn_emulation_fail; |
bbd9b64e CO |
2117 | if (kvm_mmu_unprotect_page_virt(vcpu, cr2)) |
2118 | return EMULATE_DONE; | |
2119 | return EMULATE_FAIL; | |
2120 | } | |
2121 | } | |
2122 | ||
ad312c7c | 2123 | r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); |
bbd9b64e | 2124 | |
ad312c7c | 2125 | if (vcpu->arch.pio.string) |
bbd9b64e CO |
2126 | return EMULATE_DO_MMIO; |
2127 | ||
2128 | if ((r || vcpu->mmio_is_write) && run) { | |
2129 | run->exit_reason = KVM_EXIT_MMIO; | |
2130 | run->mmio.phys_addr = vcpu->mmio_phys_addr; | |
2131 | memcpy(run->mmio.data, vcpu->mmio_data, 8); | |
2132 | run->mmio.len = vcpu->mmio_size; | |
2133 | run->mmio.is_write = vcpu->mmio_is_write; | |
2134 | } | |
2135 | ||
2136 | if (r) { | |
2137 | if (kvm_mmu_unprotect_page_virt(vcpu, cr2)) | |
2138 | return EMULATE_DONE; | |
2139 | if (!vcpu->mmio_needed) { | |
2140 | kvm_report_emulation_failure(vcpu, "mmio"); | |
2141 | return EMULATE_FAIL; | |
2142 | } | |
2143 | return EMULATE_DO_MMIO; | |
2144 | } | |
2145 | ||
2146 | kvm_x86_ops->decache_regs(vcpu); | |
ad312c7c | 2147 | kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); |
bbd9b64e CO |
2148 | |
2149 | if (vcpu->mmio_is_write) { | |
2150 | vcpu->mmio_needed = 0; | |
2151 | return EMULATE_DO_MMIO; | |
2152 | } | |
2153 | ||
2154 | return EMULATE_DONE; | |
2155 | } | |
2156 | EXPORT_SYMBOL_GPL(emulate_instruction); | |
2157 | ||
de7d789a CO |
2158 | static void free_pio_guest_pages(struct kvm_vcpu *vcpu) |
2159 | { | |
2160 | int i; | |
2161 | ||
ad312c7c ZX |
2162 | for (i = 0; i < ARRAY_SIZE(vcpu->arch.pio.guest_pages); ++i) |
2163 | if (vcpu->arch.pio.guest_pages[i]) { | |
2164 | kvm_release_page_dirty(vcpu->arch.pio.guest_pages[i]); | |
2165 | vcpu->arch.pio.guest_pages[i] = NULL; | |
de7d789a CO |
2166 | } |
2167 | } | |
2168 | ||
2169 | static int pio_copy_data(struct kvm_vcpu *vcpu) | |
2170 | { | |
ad312c7c | 2171 | void *p = vcpu->arch.pio_data; |
de7d789a CO |
2172 | void *q; |
2173 | unsigned bytes; | |
ad312c7c | 2174 | int nr_pages = vcpu->arch.pio.guest_pages[1] ? 2 : 1; |
de7d789a | 2175 | |
ad312c7c | 2176 | q = vmap(vcpu->arch.pio.guest_pages, nr_pages, VM_READ|VM_WRITE, |
de7d789a CO |
2177 | PAGE_KERNEL); |
2178 | if (!q) { | |
2179 | free_pio_guest_pages(vcpu); | |
2180 | return -ENOMEM; | |
2181 | } | |
ad312c7c ZX |
2182 | q += vcpu->arch.pio.guest_page_offset; |
2183 | bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count; | |
2184 | if (vcpu->arch.pio.in) | |
de7d789a CO |
2185 | memcpy(q, p, bytes); |
2186 | else | |
2187 | memcpy(p, q, bytes); | |
ad312c7c | 2188 | q -= vcpu->arch.pio.guest_page_offset; |
de7d789a CO |
2189 | vunmap(q); |
2190 | free_pio_guest_pages(vcpu); | |
2191 | return 0; | |
2192 | } | |
2193 | ||
2194 | int complete_pio(struct kvm_vcpu *vcpu) | |
2195 | { | |
ad312c7c | 2196 | struct kvm_pio_request *io = &vcpu->arch.pio; |
de7d789a CO |
2197 | long delta; |
2198 | int r; | |
2199 | ||
2200 | kvm_x86_ops->cache_regs(vcpu); | |
2201 | ||
2202 | if (!io->string) { | |
2203 | if (io->in) | |
ad312c7c | 2204 | memcpy(&vcpu->arch.regs[VCPU_REGS_RAX], vcpu->arch.pio_data, |
de7d789a CO |
2205 | io->size); |
2206 | } else { | |
2207 | if (io->in) { | |
2208 | r = pio_copy_data(vcpu); | |
2209 | if (r) { | |
2210 | kvm_x86_ops->cache_regs(vcpu); | |
2211 | return r; | |
2212 | } | |
2213 | } | |
2214 | ||
2215 | delta = 1; | |
2216 | if (io->rep) { | |
2217 | delta *= io->cur_count; | |
2218 | /* | |
2219 | * The size of the register should really depend on | |
2220 | * current address size. | |
2221 | */ | |
ad312c7c | 2222 | vcpu->arch.regs[VCPU_REGS_RCX] -= delta; |
de7d789a CO |
2223 | } |
2224 | if (io->down) | |
2225 | delta = -delta; | |
2226 | delta *= io->size; | |
2227 | if (io->in) | |
ad312c7c | 2228 | vcpu->arch.regs[VCPU_REGS_RDI] += delta; |
de7d789a | 2229 | else |
ad312c7c | 2230 | vcpu->arch.regs[VCPU_REGS_RSI] += delta; |
de7d789a CO |
2231 | } |
2232 | ||
2233 | kvm_x86_ops->decache_regs(vcpu); | |
2234 | ||
2235 | io->count -= io->cur_count; | |
2236 | io->cur_count = 0; | |
2237 | ||
2238 | return 0; | |
2239 | } | |
2240 | ||
2241 | static void kernel_pio(struct kvm_io_device *pio_dev, | |
2242 | struct kvm_vcpu *vcpu, | |
2243 | void *pd) | |
2244 | { | |
2245 | /* TODO: String I/O for in kernel device */ | |
2246 | ||
2247 | mutex_lock(&vcpu->kvm->lock); | |
ad312c7c ZX |
2248 | if (vcpu->arch.pio.in) |
2249 | kvm_iodevice_read(pio_dev, vcpu->arch.pio.port, | |
2250 | vcpu->arch.pio.size, | |
de7d789a CO |
2251 | pd); |
2252 | else | |
ad312c7c ZX |
2253 | kvm_iodevice_write(pio_dev, vcpu->arch.pio.port, |
2254 | vcpu->arch.pio.size, | |
de7d789a CO |
2255 | pd); |
2256 | mutex_unlock(&vcpu->kvm->lock); | |
2257 | } | |
2258 | ||
2259 | static void pio_string_write(struct kvm_io_device *pio_dev, | |
2260 | struct kvm_vcpu *vcpu) | |
2261 | { | |
ad312c7c ZX |
2262 | struct kvm_pio_request *io = &vcpu->arch.pio; |
2263 | void *pd = vcpu->arch.pio_data; | |
de7d789a CO |
2264 | int i; |
2265 | ||
2266 | mutex_lock(&vcpu->kvm->lock); | |
2267 | for (i = 0; i < io->cur_count; i++) { | |
2268 | kvm_iodevice_write(pio_dev, io->port, | |
2269 | io->size, | |
2270 | pd); | |
2271 | pd += io->size; | |
2272 | } | |
2273 | mutex_unlock(&vcpu->kvm->lock); | |
2274 | } | |
2275 | ||
2276 | static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu, | |
2277 | gpa_t addr) | |
2278 | { | |
2279 | return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr); | |
2280 | } | |
2281 | ||
2282 | int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in, | |
2283 | int size, unsigned port) | |
2284 | { | |
2285 | struct kvm_io_device *pio_dev; | |
2286 | ||
2287 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
2288 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; | |
ad312c7c | 2289 | vcpu->run->io.size = vcpu->arch.pio.size = size; |
de7d789a | 2290 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; |
ad312c7c ZX |
2291 | vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1; |
2292 | vcpu->run->io.port = vcpu->arch.pio.port = port; | |
2293 | vcpu->arch.pio.in = in; | |
2294 | vcpu->arch.pio.string = 0; | |
2295 | vcpu->arch.pio.down = 0; | |
2296 | vcpu->arch.pio.guest_page_offset = 0; | |
2297 | vcpu->arch.pio.rep = 0; | |
de7d789a CO |
2298 | |
2299 | kvm_x86_ops->cache_regs(vcpu); | |
ad312c7c | 2300 | memcpy(vcpu->arch.pio_data, &vcpu->arch.regs[VCPU_REGS_RAX], 4); |
de7d789a CO |
2301 | kvm_x86_ops->decache_regs(vcpu); |
2302 | ||
2303 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
2304 | ||
2305 | pio_dev = vcpu_find_pio_dev(vcpu, port); | |
2306 | if (pio_dev) { | |
ad312c7c | 2307 | kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data); |
de7d789a CO |
2308 | complete_pio(vcpu); |
2309 | return 1; | |
2310 | } | |
2311 | return 0; | |
2312 | } | |
2313 | EXPORT_SYMBOL_GPL(kvm_emulate_pio); | |
2314 | ||
2315 | int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in, | |
2316 | int size, unsigned long count, int down, | |
2317 | gva_t address, int rep, unsigned port) | |
2318 | { | |
2319 | unsigned now, in_page; | |
2320 | int i, ret = 0; | |
2321 | int nr_pages = 1; | |
2322 | struct page *page; | |
2323 | struct kvm_io_device *pio_dev; | |
2324 | ||
2325 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
2326 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; | |
ad312c7c | 2327 | vcpu->run->io.size = vcpu->arch.pio.size = size; |
de7d789a | 2328 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; |
ad312c7c ZX |
2329 | vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count; |
2330 | vcpu->run->io.port = vcpu->arch.pio.port = port; | |
2331 | vcpu->arch.pio.in = in; | |
2332 | vcpu->arch.pio.string = 1; | |
2333 | vcpu->arch.pio.down = down; | |
2334 | vcpu->arch.pio.guest_page_offset = offset_in_page(address); | |
2335 | vcpu->arch.pio.rep = rep; | |
de7d789a CO |
2336 | |
2337 | if (!count) { | |
2338 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
2339 | return 1; | |
2340 | } | |
2341 | ||
2342 | if (!down) | |
2343 | in_page = PAGE_SIZE - offset_in_page(address); | |
2344 | else | |
2345 | in_page = offset_in_page(address) + size; | |
2346 | now = min(count, (unsigned long)in_page / size); | |
2347 | if (!now) { | |
2348 | /* | |
2349 | * String I/O straddles page boundary. Pin two guest pages | |
2350 | * so that we satisfy atomicity constraints. Do just one | |
2351 | * transaction to avoid complexity. | |
2352 | */ | |
2353 | nr_pages = 2; | |
2354 | now = 1; | |
2355 | } | |
2356 | if (down) { | |
2357 | /* | |
2358 | * String I/O in reverse. Yuck. Kill the guest, fix later. | |
2359 | */ | |
2360 | pr_unimpl(vcpu, "guest string pio down\n"); | |
c1a5d4f9 | 2361 | kvm_inject_gp(vcpu, 0); |
de7d789a CO |
2362 | return 1; |
2363 | } | |
2364 | vcpu->run->io.count = now; | |
ad312c7c | 2365 | vcpu->arch.pio.cur_count = now; |
de7d789a | 2366 | |
ad312c7c | 2367 | if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count) |
de7d789a CO |
2368 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
2369 | ||
2370 | for (i = 0; i < nr_pages; ++i) { | |
72dc67a6 | 2371 | down_read(&vcpu->kvm->slots_lock); |
de7d789a | 2372 | page = gva_to_page(vcpu, address + i * PAGE_SIZE); |
ad312c7c | 2373 | vcpu->arch.pio.guest_pages[i] = page; |
72dc67a6 | 2374 | up_read(&vcpu->kvm->slots_lock); |
de7d789a | 2375 | if (!page) { |
c1a5d4f9 | 2376 | kvm_inject_gp(vcpu, 0); |
de7d789a CO |
2377 | free_pio_guest_pages(vcpu); |
2378 | return 1; | |
2379 | } | |
2380 | } | |
2381 | ||
2382 | pio_dev = vcpu_find_pio_dev(vcpu, port); | |
ad312c7c | 2383 | if (!vcpu->arch.pio.in) { |
de7d789a CO |
2384 | /* string PIO write */ |
2385 | ret = pio_copy_data(vcpu); | |
2386 | if (ret >= 0 && pio_dev) { | |
2387 | pio_string_write(pio_dev, vcpu); | |
2388 | complete_pio(vcpu); | |
ad312c7c | 2389 | if (vcpu->arch.pio.count == 0) |
de7d789a CO |
2390 | ret = 1; |
2391 | } | |
2392 | } else if (pio_dev) | |
2393 | pr_unimpl(vcpu, "no string pio read support yet, " | |
2394 | "port %x size %d count %ld\n", | |
2395 | port, size, count); | |
2396 | ||
2397 | return ret; | |
2398 | } | |
2399 | EXPORT_SYMBOL_GPL(kvm_emulate_pio_string); | |
2400 | ||
f8c16bba | 2401 | int kvm_arch_init(void *opaque) |
043405e1 | 2402 | { |
56c6d28a | 2403 | int r; |
f8c16bba ZX |
2404 | struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque; |
2405 | ||
f8c16bba ZX |
2406 | if (kvm_x86_ops) { |
2407 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
2408 | r = -EEXIST; |
2409 | goto out; | |
f8c16bba ZX |
2410 | } |
2411 | ||
2412 | if (!ops->cpu_has_kvm_support()) { | |
2413 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
2414 | r = -EOPNOTSUPP; |
2415 | goto out; | |
f8c16bba ZX |
2416 | } |
2417 | if (ops->disabled_by_bios()) { | |
2418 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
2419 | r = -EOPNOTSUPP; |
2420 | goto out; | |
f8c16bba ZX |
2421 | } |
2422 | ||
97db56ce AK |
2423 | r = kvm_mmu_module_init(); |
2424 | if (r) | |
2425 | goto out; | |
2426 | ||
2427 | kvm_init_msr_list(); | |
2428 | ||
f8c16bba | 2429 | kvm_x86_ops = ops; |
56c6d28a | 2430 | kvm_mmu_set_nonpresent_ptes(0ull, 0ull); |
f8c16bba | 2431 | return 0; |
56c6d28a ZX |
2432 | |
2433 | out: | |
56c6d28a | 2434 | return r; |
043405e1 | 2435 | } |
8776e519 | 2436 | |
f8c16bba ZX |
2437 | void kvm_arch_exit(void) |
2438 | { | |
2439 | kvm_x86_ops = NULL; | |
56c6d28a ZX |
2440 | kvm_mmu_module_exit(); |
2441 | } | |
f8c16bba | 2442 | |
8776e519 HB |
2443 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
2444 | { | |
2445 | ++vcpu->stat.halt_exits; | |
2446 | if (irqchip_in_kernel(vcpu->kvm)) { | |
ad312c7c | 2447 | vcpu->arch.mp_state = VCPU_MP_STATE_HALTED; |
8776e519 | 2448 | kvm_vcpu_block(vcpu); |
ad312c7c | 2449 | if (vcpu->arch.mp_state != VCPU_MP_STATE_RUNNABLE) |
8776e519 HB |
2450 | return -EINTR; |
2451 | return 1; | |
2452 | } else { | |
2453 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
2454 | return 0; | |
2455 | } | |
2456 | } | |
2457 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
2458 | ||
2f333bcb MT |
2459 | static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0, |
2460 | unsigned long a1) | |
2461 | { | |
2462 | if (is_long_mode(vcpu)) | |
2463 | return a0; | |
2464 | else | |
2465 | return a0 | ((gpa_t)a1 << 32); | |
2466 | } | |
2467 | ||
8776e519 HB |
2468 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
2469 | { | |
2470 | unsigned long nr, a0, a1, a2, a3, ret; | |
2f333bcb | 2471 | int r = 1; |
8776e519 HB |
2472 | |
2473 | kvm_x86_ops->cache_regs(vcpu); | |
2474 | ||
ad312c7c ZX |
2475 | nr = vcpu->arch.regs[VCPU_REGS_RAX]; |
2476 | a0 = vcpu->arch.regs[VCPU_REGS_RBX]; | |
2477 | a1 = vcpu->arch.regs[VCPU_REGS_RCX]; | |
2478 | a2 = vcpu->arch.regs[VCPU_REGS_RDX]; | |
2479 | a3 = vcpu->arch.regs[VCPU_REGS_RSI]; | |
8776e519 HB |
2480 | |
2481 | if (!is_long_mode(vcpu)) { | |
2482 | nr &= 0xFFFFFFFF; | |
2483 | a0 &= 0xFFFFFFFF; | |
2484 | a1 &= 0xFFFFFFFF; | |
2485 | a2 &= 0xFFFFFFFF; | |
2486 | a3 &= 0xFFFFFFFF; | |
2487 | } | |
2488 | ||
2489 | switch (nr) { | |
b93463aa AK |
2490 | case KVM_HC_VAPIC_POLL_IRQ: |
2491 | ret = 0; | |
2492 | break; | |
2f333bcb MT |
2493 | case KVM_HC_MMU_OP: |
2494 | r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret); | |
2495 | break; | |
8776e519 HB |
2496 | default: |
2497 | ret = -KVM_ENOSYS; | |
2498 | break; | |
2499 | } | |
ad312c7c | 2500 | vcpu->arch.regs[VCPU_REGS_RAX] = ret; |
8776e519 | 2501 | kvm_x86_ops->decache_regs(vcpu); |
f11c3a8d | 2502 | ++vcpu->stat.hypercalls; |
2f333bcb | 2503 | return r; |
8776e519 HB |
2504 | } |
2505 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
2506 | ||
2507 | int kvm_fix_hypercall(struct kvm_vcpu *vcpu) | |
2508 | { | |
2509 | char instruction[3]; | |
2510 | int ret = 0; | |
2511 | ||
8776e519 HB |
2512 | |
2513 | /* | |
2514 | * Blow out the MMU to ensure that no other VCPU has an active mapping | |
2515 | * to ensure that the updated hypercall appears atomically across all | |
2516 | * VCPUs. | |
2517 | */ | |
2518 | kvm_mmu_zap_all(vcpu->kvm); | |
2519 | ||
2520 | kvm_x86_ops->cache_regs(vcpu); | |
2521 | kvm_x86_ops->patch_hypercall(vcpu, instruction); | |
ad312c7c | 2522 | if (emulator_write_emulated(vcpu->arch.rip, instruction, 3, vcpu) |
8776e519 HB |
2523 | != X86EMUL_CONTINUE) |
2524 | ret = -EFAULT; | |
2525 | ||
8776e519 HB |
2526 | return ret; |
2527 | } | |
2528 | ||
2529 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) | |
2530 | { | |
2531 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; | |
2532 | } | |
2533 | ||
2534 | void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
2535 | { | |
2536 | struct descriptor_table dt = { limit, base }; | |
2537 | ||
2538 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
2539 | } | |
2540 | ||
2541 | void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
2542 | { | |
2543 | struct descriptor_table dt = { limit, base }; | |
2544 | ||
2545 | kvm_x86_ops->set_idt(vcpu, &dt); | |
2546 | } | |
2547 | ||
2548 | void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw, | |
2549 | unsigned long *rflags) | |
2550 | { | |
2d3ad1f4 | 2551 | kvm_lmsw(vcpu, msw); |
8776e519 HB |
2552 | *rflags = kvm_x86_ops->get_rflags(vcpu); |
2553 | } | |
2554 | ||
2555 | unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr) | |
2556 | { | |
2557 | kvm_x86_ops->decache_cr4_guest_bits(vcpu); | |
2558 | switch (cr) { | |
2559 | case 0: | |
ad312c7c | 2560 | return vcpu->arch.cr0; |
8776e519 | 2561 | case 2: |
ad312c7c | 2562 | return vcpu->arch.cr2; |
8776e519 | 2563 | case 3: |
ad312c7c | 2564 | return vcpu->arch.cr3; |
8776e519 | 2565 | case 4: |
ad312c7c | 2566 | return vcpu->arch.cr4; |
152ff9be | 2567 | case 8: |
2d3ad1f4 | 2568 | return kvm_get_cr8(vcpu); |
8776e519 | 2569 | default: |
b8688d51 | 2570 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); |
8776e519 HB |
2571 | return 0; |
2572 | } | |
2573 | } | |
2574 | ||
2575 | void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val, | |
2576 | unsigned long *rflags) | |
2577 | { | |
2578 | switch (cr) { | |
2579 | case 0: | |
2d3ad1f4 | 2580 | kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val)); |
8776e519 HB |
2581 | *rflags = kvm_x86_ops->get_rflags(vcpu); |
2582 | break; | |
2583 | case 2: | |
ad312c7c | 2584 | vcpu->arch.cr2 = val; |
8776e519 HB |
2585 | break; |
2586 | case 3: | |
2d3ad1f4 | 2587 | kvm_set_cr3(vcpu, val); |
8776e519 HB |
2588 | break; |
2589 | case 4: | |
2d3ad1f4 | 2590 | kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val)); |
8776e519 | 2591 | break; |
152ff9be | 2592 | case 8: |
2d3ad1f4 | 2593 | kvm_set_cr8(vcpu, val & 0xfUL); |
152ff9be | 2594 | break; |
8776e519 | 2595 | default: |
b8688d51 | 2596 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); |
8776e519 HB |
2597 | } |
2598 | } | |
2599 | ||
07716717 DK |
2600 | static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i) |
2601 | { | |
ad312c7c ZX |
2602 | struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i]; |
2603 | int j, nent = vcpu->arch.cpuid_nent; | |
07716717 DK |
2604 | |
2605 | e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT; | |
2606 | /* when no next entry is found, the current entry[i] is reselected */ | |
2607 | for (j = i + 1; j == i; j = (j + 1) % nent) { | |
ad312c7c | 2608 | struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j]; |
07716717 DK |
2609 | if (ej->function == e->function) { |
2610 | ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; | |
2611 | return j; | |
2612 | } | |
2613 | } | |
2614 | return 0; /* silence gcc, even though control never reaches here */ | |
2615 | } | |
2616 | ||
2617 | /* find an entry with matching function, matching index (if needed), and that | |
2618 | * should be read next (if it's stateful) */ | |
2619 | static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e, | |
2620 | u32 function, u32 index) | |
2621 | { | |
2622 | if (e->function != function) | |
2623 | return 0; | |
2624 | if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index) | |
2625 | return 0; | |
2626 | if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) && | |
2627 | !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT)) | |
2628 | return 0; | |
2629 | return 1; | |
2630 | } | |
2631 | ||
8776e519 HB |
2632 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu) |
2633 | { | |
2634 | int i; | |
07716717 DK |
2635 | u32 function, index; |
2636 | struct kvm_cpuid_entry2 *e, *best; | |
8776e519 HB |
2637 | |
2638 | kvm_x86_ops->cache_regs(vcpu); | |
ad312c7c ZX |
2639 | function = vcpu->arch.regs[VCPU_REGS_RAX]; |
2640 | index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
2641 | vcpu->arch.regs[VCPU_REGS_RAX] = 0; | |
2642 | vcpu->arch.regs[VCPU_REGS_RBX] = 0; | |
2643 | vcpu->arch.regs[VCPU_REGS_RCX] = 0; | |
2644 | vcpu->arch.regs[VCPU_REGS_RDX] = 0; | |
8776e519 | 2645 | best = NULL; |
ad312c7c ZX |
2646 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
2647 | e = &vcpu->arch.cpuid_entries[i]; | |
07716717 DK |
2648 | if (is_matching_cpuid_entry(e, function, index)) { |
2649 | if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) | |
2650 | move_to_next_stateful_cpuid_entry(vcpu, i); | |
8776e519 HB |
2651 | best = e; |
2652 | break; | |
2653 | } | |
2654 | /* | |
2655 | * Both basic or both extended? | |
2656 | */ | |
2657 | if (((e->function ^ function) & 0x80000000) == 0) | |
2658 | if (!best || e->function > best->function) | |
2659 | best = e; | |
2660 | } | |
2661 | if (best) { | |
ad312c7c ZX |
2662 | vcpu->arch.regs[VCPU_REGS_RAX] = best->eax; |
2663 | vcpu->arch.regs[VCPU_REGS_RBX] = best->ebx; | |
2664 | vcpu->arch.regs[VCPU_REGS_RCX] = best->ecx; | |
2665 | vcpu->arch.regs[VCPU_REGS_RDX] = best->edx; | |
8776e519 HB |
2666 | } |
2667 | kvm_x86_ops->decache_regs(vcpu); | |
2668 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
2669 | } | |
2670 | EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); | |
d0752060 | 2671 | |
b6c7a5dc HB |
2672 | /* |
2673 | * Check if userspace requested an interrupt window, and that the | |
2674 | * interrupt window is open. | |
2675 | * | |
2676 | * No need to exit to userspace if we already have an interrupt queued. | |
2677 | */ | |
2678 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu, | |
2679 | struct kvm_run *kvm_run) | |
2680 | { | |
ad312c7c | 2681 | return (!vcpu->arch.irq_summary && |
b6c7a5dc | 2682 | kvm_run->request_interrupt_window && |
ad312c7c | 2683 | vcpu->arch.interrupt_window_open && |
b6c7a5dc HB |
2684 | (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF)); |
2685 | } | |
2686 | ||
2687 | static void post_kvm_run_save(struct kvm_vcpu *vcpu, | |
2688 | struct kvm_run *kvm_run) | |
2689 | { | |
2690 | kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0; | |
2d3ad1f4 | 2691 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc HB |
2692 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
2693 | if (irqchip_in_kernel(vcpu->kvm)) | |
2694 | kvm_run->ready_for_interrupt_injection = 1; | |
2695 | else | |
2696 | kvm_run->ready_for_interrupt_injection = | |
ad312c7c ZX |
2697 | (vcpu->arch.interrupt_window_open && |
2698 | vcpu->arch.irq_summary == 0); | |
b6c7a5dc HB |
2699 | } |
2700 | ||
b93463aa AK |
2701 | static void vapic_enter(struct kvm_vcpu *vcpu) |
2702 | { | |
2703 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2704 | struct page *page; | |
2705 | ||
2706 | if (!apic || !apic->vapic_addr) | |
2707 | return; | |
2708 | ||
10589a46 | 2709 | down_read(¤t->mm->mmap_sem); |
b93463aa | 2710 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); |
10589a46 | 2711 | up_read(¤t->mm->mmap_sem); |
72dc67a6 IE |
2712 | |
2713 | vcpu->arch.apic->vapic_page = page; | |
b93463aa AK |
2714 | } |
2715 | ||
2716 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
2717 | { | |
2718 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2719 | ||
2720 | if (!apic || !apic->vapic_addr) | |
2721 | return; | |
2722 | ||
2723 | kvm_release_page_dirty(apic->vapic_page); | |
2724 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
2725 | } | |
2726 | ||
b6c7a5dc HB |
2727 | static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2728 | { | |
2729 | int r; | |
2730 | ||
ad312c7c | 2731 | if (unlikely(vcpu->arch.mp_state == VCPU_MP_STATE_SIPI_RECEIVED)) { |
b6c7a5dc | 2732 | pr_debug("vcpu %d received sipi with vector # %x\n", |
ad312c7c | 2733 | vcpu->vcpu_id, vcpu->arch.sipi_vector); |
b6c7a5dc HB |
2734 | kvm_lapic_reset(vcpu); |
2735 | r = kvm_x86_ops->vcpu_reset(vcpu); | |
2736 | if (r) | |
2737 | return r; | |
ad312c7c | 2738 | vcpu->arch.mp_state = VCPU_MP_STATE_RUNNABLE; |
b6c7a5dc HB |
2739 | } |
2740 | ||
b93463aa AK |
2741 | vapic_enter(vcpu); |
2742 | ||
b6c7a5dc HB |
2743 | preempted: |
2744 | if (vcpu->guest_debug.enabled) | |
2745 | kvm_x86_ops->guest_debug_pre(vcpu); | |
2746 | ||
2747 | again: | |
2e53d63a MT |
2748 | if (vcpu->requests) |
2749 | if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests)) | |
2750 | kvm_mmu_unload(vcpu); | |
2751 | ||
b6c7a5dc HB |
2752 | r = kvm_mmu_reload(vcpu); |
2753 | if (unlikely(r)) | |
2754 | goto out; | |
2755 | ||
2f52d58c AK |
2756 | if (vcpu->requests) { |
2757 | if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests)) | |
2758 | __kvm_migrate_apic_timer(vcpu); | |
b93463aa AK |
2759 | if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS, |
2760 | &vcpu->requests)) { | |
2761 | kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS; | |
2762 | r = 0; | |
2763 | goto out; | |
2764 | } | |
71c4dfaf JR |
2765 | if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) { |
2766 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2767 | r = 0; | |
2768 | goto out; | |
2769 | } | |
2f52d58c | 2770 | } |
b93463aa | 2771 | |
b6c7a5dc HB |
2772 | kvm_inject_pending_timer_irqs(vcpu); |
2773 | ||
2774 | preempt_disable(); | |
2775 | ||
2776 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2777 | kvm_load_guest_fpu(vcpu); | |
2778 | ||
2779 | local_irq_disable(); | |
2780 | ||
6c142801 AK |
2781 | if (need_resched()) { |
2782 | local_irq_enable(); | |
2783 | preempt_enable(); | |
2784 | r = 1; | |
2785 | goto out; | |
2786 | } | |
2787 | ||
2e53d63a MT |
2788 | if (vcpu->requests) |
2789 | if (test_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests)) { | |
2790 | local_irq_enable(); | |
2791 | preempt_enable(); | |
2792 | r = 1; | |
2793 | goto out; | |
2794 | } | |
2795 | ||
b6c7a5dc HB |
2796 | if (signal_pending(current)) { |
2797 | local_irq_enable(); | |
2798 | preempt_enable(); | |
2799 | r = -EINTR; | |
2800 | kvm_run->exit_reason = KVM_EXIT_INTR; | |
2801 | ++vcpu->stat.signal_exits; | |
2802 | goto out; | |
2803 | } | |
2804 | ||
ad312c7c | 2805 | if (vcpu->arch.exception.pending) |
298101da AK |
2806 | __queue_exception(vcpu); |
2807 | else if (irqchip_in_kernel(vcpu->kvm)) | |
b6c7a5dc | 2808 | kvm_x86_ops->inject_pending_irq(vcpu); |
eb9774f0 | 2809 | else |
b6c7a5dc HB |
2810 | kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run); |
2811 | ||
b93463aa AK |
2812 | kvm_lapic_sync_to_vapic(vcpu); |
2813 | ||
b6c7a5dc HB |
2814 | vcpu->guest_mode = 1; |
2815 | kvm_guest_enter(); | |
2816 | ||
2817 | if (vcpu->requests) | |
2818 | if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests)) | |
2819 | kvm_x86_ops->tlb_flush(vcpu); | |
2820 | ||
2821 | kvm_x86_ops->run(vcpu, kvm_run); | |
2822 | ||
2823 | vcpu->guest_mode = 0; | |
2824 | local_irq_enable(); | |
2825 | ||
2826 | ++vcpu->stat.exits; | |
2827 | ||
2828 | /* | |
2829 | * We must have an instruction between local_irq_enable() and | |
2830 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
2831 | * the interrupt shadow. The stat.exits increment will do nicely. | |
2832 | * But we need to prevent reordering, hence this barrier(): | |
2833 | */ | |
2834 | barrier(); | |
2835 | ||
2836 | kvm_guest_exit(); | |
2837 | ||
2838 | preempt_enable(); | |
2839 | ||
2840 | /* | |
2841 | * Profile KVM exit RIPs: | |
2842 | */ | |
2843 | if (unlikely(prof_on == KVM_PROFILING)) { | |
2844 | kvm_x86_ops->cache_regs(vcpu); | |
ad312c7c | 2845 | profile_hit(KVM_PROFILING, (void *)vcpu->arch.rip); |
b6c7a5dc HB |
2846 | } |
2847 | ||
ad312c7c ZX |
2848 | if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu)) |
2849 | vcpu->arch.exception.pending = false; | |
298101da | 2850 | |
b93463aa AK |
2851 | kvm_lapic_sync_from_vapic(vcpu); |
2852 | ||
b6c7a5dc HB |
2853 | r = kvm_x86_ops->handle_exit(kvm_run, vcpu); |
2854 | ||
2855 | if (r > 0) { | |
2856 | if (dm_request_for_irq_injection(vcpu, kvm_run)) { | |
2857 | r = -EINTR; | |
2858 | kvm_run->exit_reason = KVM_EXIT_INTR; | |
2859 | ++vcpu->stat.request_irq_exits; | |
2860 | goto out; | |
2861 | } | |
e1beb1d3 | 2862 | if (!need_resched()) |
b6c7a5dc | 2863 | goto again; |
b6c7a5dc HB |
2864 | } |
2865 | ||
2866 | out: | |
2867 | if (r > 0) { | |
2868 | kvm_resched(vcpu); | |
2869 | goto preempted; | |
2870 | } | |
2871 | ||
2872 | post_kvm_run_save(vcpu, kvm_run); | |
2873 | ||
b93463aa AK |
2874 | vapic_exit(vcpu); |
2875 | ||
b6c7a5dc HB |
2876 | return r; |
2877 | } | |
2878 | ||
2879 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2880 | { | |
2881 | int r; | |
2882 | sigset_t sigsaved; | |
2883 | ||
2884 | vcpu_load(vcpu); | |
2885 | ||
ad312c7c | 2886 | if (unlikely(vcpu->arch.mp_state == VCPU_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc HB |
2887 | kvm_vcpu_block(vcpu); |
2888 | vcpu_put(vcpu); | |
2889 | return -EAGAIN; | |
2890 | } | |
2891 | ||
2892 | if (vcpu->sigset_active) | |
2893 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
2894 | ||
2895 | /* re-sync apic's tpr */ | |
2896 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2d3ad1f4 | 2897 | kvm_set_cr8(vcpu, kvm_run->cr8); |
b6c7a5dc | 2898 | |
ad312c7c | 2899 | if (vcpu->arch.pio.cur_count) { |
b6c7a5dc HB |
2900 | r = complete_pio(vcpu); |
2901 | if (r) | |
2902 | goto out; | |
2903 | } | |
2904 | #if CONFIG_HAS_IOMEM | |
2905 | if (vcpu->mmio_needed) { | |
2906 | memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); | |
2907 | vcpu->mmio_read_completed = 1; | |
2908 | vcpu->mmio_needed = 0; | |
2909 | r = emulate_instruction(vcpu, kvm_run, | |
571008da SY |
2910 | vcpu->arch.mmio_fault_cr2, 0, |
2911 | EMULTYPE_NO_DECODE); | |
b6c7a5dc HB |
2912 | if (r == EMULATE_DO_MMIO) { |
2913 | /* | |
2914 | * Read-modify-write. Back to userspace. | |
2915 | */ | |
2916 | r = 0; | |
2917 | goto out; | |
2918 | } | |
2919 | } | |
2920 | #endif | |
2921 | if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) { | |
2922 | kvm_x86_ops->cache_regs(vcpu); | |
ad312c7c | 2923 | vcpu->arch.regs[VCPU_REGS_RAX] = kvm_run->hypercall.ret; |
b6c7a5dc HB |
2924 | kvm_x86_ops->decache_regs(vcpu); |
2925 | } | |
2926 | ||
2927 | r = __vcpu_run(vcpu, kvm_run); | |
2928 | ||
2929 | out: | |
2930 | if (vcpu->sigset_active) | |
2931 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
2932 | ||
2933 | vcpu_put(vcpu); | |
2934 | return r; | |
2935 | } | |
2936 | ||
2937 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
2938 | { | |
2939 | vcpu_load(vcpu); | |
2940 | ||
2941 | kvm_x86_ops->cache_regs(vcpu); | |
2942 | ||
ad312c7c ZX |
2943 | regs->rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
2944 | regs->rbx = vcpu->arch.regs[VCPU_REGS_RBX]; | |
2945 | regs->rcx = vcpu->arch.regs[VCPU_REGS_RCX]; | |
2946 | regs->rdx = vcpu->arch.regs[VCPU_REGS_RDX]; | |
2947 | regs->rsi = vcpu->arch.regs[VCPU_REGS_RSI]; | |
2948 | regs->rdi = vcpu->arch.regs[VCPU_REGS_RDI]; | |
2949 | regs->rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
2950 | regs->rbp = vcpu->arch.regs[VCPU_REGS_RBP]; | |
b6c7a5dc | 2951 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
2952 | regs->r8 = vcpu->arch.regs[VCPU_REGS_R8]; |
2953 | regs->r9 = vcpu->arch.regs[VCPU_REGS_R9]; | |
2954 | regs->r10 = vcpu->arch.regs[VCPU_REGS_R10]; | |
2955 | regs->r11 = vcpu->arch.regs[VCPU_REGS_R11]; | |
2956 | regs->r12 = vcpu->arch.regs[VCPU_REGS_R12]; | |
2957 | regs->r13 = vcpu->arch.regs[VCPU_REGS_R13]; | |
2958 | regs->r14 = vcpu->arch.regs[VCPU_REGS_R14]; | |
2959 | regs->r15 = vcpu->arch.regs[VCPU_REGS_R15]; | |
b6c7a5dc HB |
2960 | #endif |
2961 | ||
ad312c7c | 2962 | regs->rip = vcpu->arch.rip; |
b6c7a5dc HB |
2963 | regs->rflags = kvm_x86_ops->get_rflags(vcpu); |
2964 | ||
2965 | /* | |
2966 | * Don't leak debug flags in case they were set for guest debugging | |
2967 | */ | |
2968 | if (vcpu->guest_debug.enabled && vcpu->guest_debug.singlestep) | |
2969 | regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
2970 | ||
2971 | vcpu_put(vcpu); | |
2972 | ||
2973 | return 0; | |
2974 | } | |
2975 | ||
2976 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
2977 | { | |
2978 | vcpu_load(vcpu); | |
2979 | ||
ad312c7c ZX |
2980 | vcpu->arch.regs[VCPU_REGS_RAX] = regs->rax; |
2981 | vcpu->arch.regs[VCPU_REGS_RBX] = regs->rbx; | |
2982 | vcpu->arch.regs[VCPU_REGS_RCX] = regs->rcx; | |
2983 | vcpu->arch.regs[VCPU_REGS_RDX] = regs->rdx; | |
2984 | vcpu->arch.regs[VCPU_REGS_RSI] = regs->rsi; | |
2985 | vcpu->arch.regs[VCPU_REGS_RDI] = regs->rdi; | |
2986 | vcpu->arch.regs[VCPU_REGS_RSP] = regs->rsp; | |
2987 | vcpu->arch.regs[VCPU_REGS_RBP] = regs->rbp; | |
b6c7a5dc | 2988 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
2989 | vcpu->arch.regs[VCPU_REGS_R8] = regs->r8; |
2990 | vcpu->arch.regs[VCPU_REGS_R9] = regs->r9; | |
2991 | vcpu->arch.regs[VCPU_REGS_R10] = regs->r10; | |
2992 | vcpu->arch.regs[VCPU_REGS_R11] = regs->r11; | |
2993 | vcpu->arch.regs[VCPU_REGS_R12] = regs->r12; | |
2994 | vcpu->arch.regs[VCPU_REGS_R13] = regs->r13; | |
2995 | vcpu->arch.regs[VCPU_REGS_R14] = regs->r14; | |
2996 | vcpu->arch.regs[VCPU_REGS_R15] = regs->r15; | |
b6c7a5dc HB |
2997 | #endif |
2998 | ||
ad312c7c | 2999 | vcpu->arch.rip = regs->rip; |
b6c7a5dc HB |
3000 | kvm_x86_ops->set_rflags(vcpu, regs->rflags); |
3001 | ||
3002 | kvm_x86_ops->decache_regs(vcpu); | |
3003 | ||
3004 | vcpu_put(vcpu); | |
3005 | ||
3006 | return 0; | |
3007 | } | |
3008 | ||
3009 | static void get_segment(struct kvm_vcpu *vcpu, | |
3010 | struct kvm_segment *var, int seg) | |
3011 | { | |
14af3f3c | 3012 | kvm_x86_ops->get_segment(vcpu, var, seg); |
b6c7a5dc HB |
3013 | } |
3014 | ||
3015 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) | |
3016 | { | |
3017 | struct kvm_segment cs; | |
3018 | ||
3019 | get_segment(vcpu, &cs, VCPU_SREG_CS); | |
3020 | *db = cs.db; | |
3021 | *l = cs.l; | |
3022 | } | |
3023 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
3024 | ||
3025 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
3026 | struct kvm_sregs *sregs) | |
3027 | { | |
3028 | struct descriptor_table dt; | |
3029 | int pending_vec; | |
3030 | ||
3031 | vcpu_load(vcpu); | |
3032 | ||
3033 | get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); | |
3034 | get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
3035 | get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
3036 | get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
3037 | get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
3038 | get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
3039 | ||
3040 | get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); | |
3041 | get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
3042 | ||
3043 | kvm_x86_ops->get_idt(vcpu, &dt); | |
3044 | sregs->idt.limit = dt.limit; | |
3045 | sregs->idt.base = dt.base; | |
3046 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
3047 | sregs->gdt.limit = dt.limit; | |
3048 | sregs->gdt.base = dt.base; | |
3049 | ||
3050 | kvm_x86_ops->decache_cr4_guest_bits(vcpu); | |
ad312c7c ZX |
3051 | sregs->cr0 = vcpu->arch.cr0; |
3052 | sregs->cr2 = vcpu->arch.cr2; | |
3053 | sregs->cr3 = vcpu->arch.cr3; | |
3054 | sregs->cr4 = vcpu->arch.cr4; | |
2d3ad1f4 | 3055 | sregs->cr8 = kvm_get_cr8(vcpu); |
ad312c7c | 3056 | sregs->efer = vcpu->arch.shadow_efer; |
b6c7a5dc HB |
3057 | sregs->apic_base = kvm_get_apic_base(vcpu); |
3058 | ||
3059 | if (irqchip_in_kernel(vcpu->kvm)) { | |
3060 | memset(sregs->interrupt_bitmap, 0, | |
3061 | sizeof sregs->interrupt_bitmap); | |
3062 | pending_vec = kvm_x86_ops->get_irq(vcpu); | |
3063 | if (pending_vec >= 0) | |
3064 | set_bit(pending_vec, | |
3065 | (unsigned long *)sregs->interrupt_bitmap); | |
3066 | } else | |
ad312c7c | 3067 | memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending, |
b6c7a5dc HB |
3068 | sizeof sregs->interrupt_bitmap); |
3069 | ||
3070 | vcpu_put(vcpu); | |
3071 | ||
3072 | return 0; | |
3073 | } | |
3074 | ||
3075 | static void set_segment(struct kvm_vcpu *vcpu, | |
3076 | struct kvm_segment *var, int seg) | |
3077 | { | |
14af3f3c | 3078 | kvm_x86_ops->set_segment(vcpu, var, seg); |
b6c7a5dc HB |
3079 | } |
3080 | ||
37817f29 IE |
3081 | static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector, |
3082 | struct kvm_segment *kvm_desct) | |
3083 | { | |
3084 | kvm_desct->base = seg_desc->base0; | |
3085 | kvm_desct->base |= seg_desc->base1 << 16; | |
3086 | kvm_desct->base |= seg_desc->base2 << 24; | |
3087 | kvm_desct->limit = seg_desc->limit0; | |
3088 | kvm_desct->limit |= seg_desc->limit << 16; | |
3089 | kvm_desct->selector = selector; | |
3090 | kvm_desct->type = seg_desc->type; | |
3091 | kvm_desct->present = seg_desc->p; | |
3092 | kvm_desct->dpl = seg_desc->dpl; | |
3093 | kvm_desct->db = seg_desc->d; | |
3094 | kvm_desct->s = seg_desc->s; | |
3095 | kvm_desct->l = seg_desc->l; | |
3096 | kvm_desct->g = seg_desc->g; | |
3097 | kvm_desct->avl = seg_desc->avl; | |
3098 | if (!selector) | |
3099 | kvm_desct->unusable = 1; | |
3100 | else | |
3101 | kvm_desct->unusable = 0; | |
3102 | kvm_desct->padding = 0; | |
3103 | } | |
3104 | ||
3105 | static void get_segment_descritptor_dtable(struct kvm_vcpu *vcpu, | |
3106 | u16 selector, | |
3107 | struct descriptor_table *dtable) | |
3108 | { | |
3109 | if (selector & 1 << 2) { | |
3110 | struct kvm_segment kvm_seg; | |
3111 | ||
3112 | get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR); | |
3113 | ||
3114 | if (kvm_seg.unusable) | |
3115 | dtable->limit = 0; | |
3116 | else | |
3117 | dtable->limit = kvm_seg.limit; | |
3118 | dtable->base = kvm_seg.base; | |
3119 | } | |
3120 | else | |
3121 | kvm_x86_ops->get_gdt(vcpu, dtable); | |
3122 | } | |
3123 | ||
3124 | /* allowed just for 8 bytes segments */ | |
3125 | static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, | |
3126 | struct desc_struct *seg_desc) | |
3127 | { | |
3128 | struct descriptor_table dtable; | |
3129 | u16 index = selector >> 3; | |
3130 | ||
3131 | get_segment_descritptor_dtable(vcpu, selector, &dtable); | |
3132 | ||
3133 | if (dtable.limit < index * 8 + 7) { | |
3134 | kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc); | |
3135 | return 1; | |
3136 | } | |
3137 | return kvm_read_guest(vcpu->kvm, dtable.base + index * 8, seg_desc, 8); | |
3138 | } | |
3139 | ||
3140 | /* allowed just for 8 bytes segments */ | |
3141 | static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, | |
3142 | struct desc_struct *seg_desc) | |
3143 | { | |
3144 | struct descriptor_table dtable; | |
3145 | u16 index = selector >> 3; | |
3146 | ||
3147 | get_segment_descritptor_dtable(vcpu, selector, &dtable); | |
3148 | ||
3149 | if (dtable.limit < index * 8 + 7) | |
3150 | return 1; | |
3151 | return kvm_write_guest(vcpu->kvm, dtable.base + index * 8, seg_desc, 8); | |
3152 | } | |
3153 | ||
3154 | static u32 get_tss_base_addr(struct kvm_vcpu *vcpu, | |
3155 | struct desc_struct *seg_desc) | |
3156 | { | |
3157 | u32 base_addr; | |
3158 | ||
3159 | base_addr = seg_desc->base0; | |
3160 | base_addr |= (seg_desc->base1 << 16); | |
3161 | base_addr |= (seg_desc->base2 << 24); | |
3162 | ||
3163 | return base_addr; | |
3164 | } | |
3165 | ||
3166 | static int load_tss_segment32(struct kvm_vcpu *vcpu, | |
3167 | struct desc_struct *seg_desc, | |
3168 | struct tss_segment_32 *tss) | |
3169 | { | |
3170 | u32 base_addr; | |
3171 | ||
3172 | base_addr = get_tss_base_addr(vcpu, seg_desc); | |
3173 | ||
3174 | return kvm_read_guest(vcpu->kvm, base_addr, tss, | |
3175 | sizeof(struct tss_segment_32)); | |
3176 | } | |
3177 | ||
3178 | static int save_tss_segment32(struct kvm_vcpu *vcpu, | |
3179 | struct desc_struct *seg_desc, | |
3180 | struct tss_segment_32 *tss) | |
3181 | { | |
3182 | u32 base_addr; | |
3183 | ||
3184 | base_addr = get_tss_base_addr(vcpu, seg_desc); | |
3185 | ||
3186 | return kvm_write_guest(vcpu->kvm, base_addr, tss, | |
3187 | sizeof(struct tss_segment_32)); | |
3188 | } | |
3189 | ||
3190 | static int load_tss_segment16(struct kvm_vcpu *vcpu, | |
3191 | struct desc_struct *seg_desc, | |
3192 | struct tss_segment_16 *tss) | |
3193 | { | |
3194 | u32 base_addr; | |
3195 | ||
3196 | base_addr = get_tss_base_addr(vcpu, seg_desc); | |
3197 | ||
3198 | return kvm_read_guest(vcpu->kvm, base_addr, tss, | |
3199 | sizeof(struct tss_segment_16)); | |
3200 | } | |
3201 | ||
3202 | static int save_tss_segment16(struct kvm_vcpu *vcpu, | |
3203 | struct desc_struct *seg_desc, | |
3204 | struct tss_segment_16 *tss) | |
3205 | { | |
3206 | u32 base_addr; | |
3207 | ||
3208 | base_addr = get_tss_base_addr(vcpu, seg_desc); | |
3209 | ||
3210 | return kvm_write_guest(vcpu->kvm, base_addr, tss, | |
3211 | sizeof(struct tss_segment_16)); | |
3212 | } | |
3213 | ||
3214 | static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg) | |
3215 | { | |
3216 | struct kvm_segment kvm_seg; | |
3217 | ||
3218 | get_segment(vcpu, &kvm_seg, seg); | |
3219 | return kvm_seg.selector; | |
3220 | } | |
3221 | ||
3222 | static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu, | |
3223 | u16 selector, | |
3224 | struct kvm_segment *kvm_seg) | |
3225 | { | |
3226 | struct desc_struct seg_desc; | |
3227 | ||
3228 | if (load_guest_segment_descriptor(vcpu, selector, &seg_desc)) | |
3229 | return 1; | |
3230 | seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg); | |
3231 | return 0; | |
3232 | } | |
3233 | ||
3234 | static int load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, | |
3235 | int type_bits, int seg) | |
3236 | { | |
3237 | struct kvm_segment kvm_seg; | |
3238 | ||
3239 | if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg)) | |
3240 | return 1; | |
3241 | kvm_seg.type |= type_bits; | |
3242 | ||
3243 | if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS && | |
3244 | seg != VCPU_SREG_LDTR) | |
3245 | if (!kvm_seg.s) | |
3246 | kvm_seg.unusable = 1; | |
3247 | ||
3248 | set_segment(vcpu, &kvm_seg, seg); | |
3249 | return 0; | |
3250 | } | |
3251 | ||
3252 | static void save_state_to_tss32(struct kvm_vcpu *vcpu, | |
3253 | struct tss_segment_32 *tss) | |
3254 | { | |
3255 | tss->cr3 = vcpu->arch.cr3; | |
3256 | tss->eip = vcpu->arch.rip; | |
3257 | tss->eflags = kvm_x86_ops->get_rflags(vcpu); | |
3258 | tss->eax = vcpu->arch.regs[VCPU_REGS_RAX]; | |
3259 | tss->ecx = vcpu->arch.regs[VCPU_REGS_RCX]; | |
3260 | tss->edx = vcpu->arch.regs[VCPU_REGS_RDX]; | |
3261 | tss->ebx = vcpu->arch.regs[VCPU_REGS_RBX]; | |
3262 | tss->esp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3263 | tss->ebp = vcpu->arch.regs[VCPU_REGS_RBP]; | |
3264 | tss->esi = vcpu->arch.regs[VCPU_REGS_RSI]; | |
3265 | tss->edi = vcpu->arch.regs[VCPU_REGS_RDI]; | |
3266 | ||
3267 | tss->es = get_segment_selector(vcpu, VCPU_SREG_ES); | |
3268 | tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS); | |
3269 | tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS); | |
3270 | tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS); | |
3271 | tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS); | |
3272 | tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS); | |
3273 | tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR); | |
3274 | tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR); | |
3275 | } | |
3276 | ||
3277 | static int load_state_from_tss32(struct kvm_vcpu *vcpu, | |
3278 | struct tss_segment_32 *tss) | |
3279 | { | |
3280 | kvm_set_cr3(vcpu, tss->cr3); | |
3281 | ||
3282 | vcpu->arch.rip = tss->eip; | |
3283 | kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2); | |
3284 | ||
3285 | vcpu->arch.regs[VCPU_REGS_RAX] = tss->eax; | |
3286 | vcpu->arch.regs[VCPU_REGS_RCX] = tss->ecx; | |
3287 | vcpu->arch.regs[VCPU_REGS_RDX] = tss->edx; | |
3288 | vcpu->arch.regs[VCPU_REGS_RBX] = tss->ebx; | |
3289 | vcpu->arch.regs[VCPU_REGS_RSP] = tss->esp; | |
3290 | vcpu->arch.regs[VCPU_REGS_RBP] = tss->ebp; | |
3291 | vcpu->arch.regs[VCPU_REGS_RSI] = tss->esi; | |
3292 | vcpu->arch.regs[VCPU_REGS_RDI] = tss->edi; | |
3293 | ||
3294 | if (load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR)) | |
3295 | return 1; | |
3296 | ||
3297 | if (load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES)) | |
3298 | return 1; | |
3299 | ||
3300 | if (load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS)) | |
3301 | return 1; | |
3302 | ||
3303 | if (load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS)) | |
3304 | return 1; | |
3305 | ||
3306 | if (load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS)) | |
3307 | return 1; | |
3308 | ||
3309 | if (load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS)) | |
3310 | return 1; | |
3311 | ||
3312 | if (load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS)) | |
3313 | return 1; | |
3314 | return 0; | |
3315 | } | |
3316 | ||
3317 | static void save_state_to_tss16(struct kvm_vcpu *vcpu, | |
3318 | struct tss_segment_16 *tss) | |
3319 | { | |
3320 | tss->ip = vcpu->arch.rip; | |
3321 | tss->flag = kvm_x86_ops->get_rflags(vcpu); | |
3322 | tss->ax = vcpu->arch.regs[VCPU_REGS_RAX]; | |
3323 | tss->cx = vcpu->arch.regs[VCPU_REGS_RCX]; | |
3324 | tss->dx = vcpu->arch.regs[VCPU_REGS_RDX]; | |
3325 | tss->bx = vcpu->arch.regs[VCPU_REGS_RBX]; | |
3326 | tss->sp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3327 | tss->bp = vcpu->arch.regs[VCPU_REGS_RBP]; | |
3328 | tss->si = vcpu->arch.regs[VCPU_REGS_RSI]; | |
3329 | tss->di = vcpu->arch.regs[VCPU_REGS_RDI]; | |
3330 | ||
3331 | tss->es = get_segment_selector(vcpu, VCPU_SREG_ES); | |
3332 | tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS); | |
3333 | tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS); | |
3334 | tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS); | |
3335 | tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR); | |
3336 | tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR); | |
3337 | } | |
3338 | ||
3339 | static int load_state_from_tss16(struct kvm_vcpu *vcpu, | |
3340 | struct tss_segment_16 *tss) | |
3341 | { | |
3342 | vcpu->arch.rip = tss->ip; | |
3343 | kvm_x86_ops->set_rflags(vcpu, tss->flag | 2); | |
3344 | vcpu->arch.regs[VCPU_REGS_RAX] = tss->ax; | |
3345 | vcpu->arch.regs[VCPU_REGS_RCX] = tss->cx; | |
3346 | vcpu->arch.regs[VCPU_REGS_RDX] = tss->dx; | |
3347 | vcpu->arch.regs[VCPU_REGS_RBX] = tss->bx; | |
3348 | vcpu->arch.regs[VCPU_REGS_RSP] = tss->sp; | |
3349 | vcpu->arch.regs[VCPU_REGS_RBP] = tss->bp; | |
3350 | vcpu->arch.regs[VCPU_REGS_RSI] = tss->si; | |
3351 | vcpu->arch.regs[VCPU_REGS_RDI] = tss->di; | |
3352 | ||
3353 | if (load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR)) | |
3354 | return 1; | |
3355 | ||
3356 | if (load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES)) | |
3357 | return 1; | |
3358 | ||
3359 | if (load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS)) | |
3360 | return 1; | |
3361 | ||
3362 | if (load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS)) | |
3363 | return 1; | |
3364 | ||
3365 | if (load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS)) | |
3366 | return 1; | |
3367 | return 0; | |
3368 | } | |
3369 | ||
3370 | int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector, | |
3371 | struct desc_struct *cseg_desc, | |
3372 | struct desc_struct *nseg_desc) | |
3373 | { | |
3374 | struct tss_segment_16 tss_segment_16; | |
3375 | int ret = 0; | |
3376 | ||
3377 | if (load_tss_segment16(vcpu, cseg_desc, &tss_segment_16)) | |
3378 | goto out; | |
3379 | ||
3380 | save_state_to_tss16(vcpu, &tss_segment_16); | |
3381 | save_tss_segment16(vcpu, cseg_desc, &tss_segment_16); | |
3382 | ||
3383 | if (load_tss_segment16(vcpu, nseg_desc, &tss_segment_16)) | |
3384 | goto out; | |
3385 | if (load_state_from_tss16(vcpu, &tss_segment_16)) | |
3386 | goto out; | |
3387 | ||
3388 | ret = 1; | |
3389 | out: | |
3390 | return ret; | |
3391 | } | |
3392 | ||
3393 | int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector, | |
3394 | struct desc_struct *cseg_desc, | |
3395 | struct desc_struct *nseg_desc) | |
3396 | { | |
3397 | struct tss_segment_32 tss_segment_32; | |
3398 | int ret = 0; | |
3399 | ||
3400 | if (load_tss_segment32(vcpu, cseg_desc, &tss_segment_32)) | |
3401 | goto out; | |
3402 | ||
3403 | save_state_to_tss32(vcpu, &tss_segment_32); | |
3404 | save_tss_segment32(vcpu, cseg_desc, &tss_segment_32); | |
3405 | ||
3406 | if (load_tss_segment32(vcpu, nseg_desc, &tss_segment_32)) | |
3407 | goto out; | |
3408 | if (load_state_from_tss32(vcpu, &tss_segment_32)) | |
3409 | goto out; | |
3410 | ||
3411 | ret = 1; | |
3412 | out: | |
3413 | return ret; | |
3414 | } | |
3415 | ||
3416 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason) | |
3417 | { | |
3418 | struct kvm_segment tr_seg; | |
3419 | struct desc_struct cseg_desc; | |
3420 | struct desc_struct nseg_desc; | |
3421 | int ret = 0; | |
3422 | ||
3423 | get_segment(vcpu, &tr_seg, VCPU_SREG_TR); | |
3424 | ||
3425 | if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc)) | |
3426 | goto out; | |
3427 | ||
3428 | if (load_guest_segment_descriptor(vcpu, tr_seg.selector, &cseg_desc)) | |
3429 | goto out; | |
3430 | ||
3431 | ||
3432 | if (reason != TASK_SWITCH_IRET) { | |
3433 | int cpl; | |
3434 | ||
3435 | cpl = kvm_x86_ops->get_cpl(vcpu); | |
3436 | if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) { | |
3437 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
3438 | return 1; | |
3439 | } | |
3440 | } | |
3441 | ||
3442 | if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) { | |
3443 | kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc); | |
3444 | return 1; | |
3445 | } | |
3446 | ||
3447 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
3448 | cseg_desc.type &= ~(1 << 8); //clear the B flag | |
3449 | save_guest_segment_descriptor(vcpu, tr_seg.selector, | |
3450 | &cseg_desc); | |
3451 | } | |
3452 | ||
3453 | if (reason == TASK_SWITCH_IRET) { | |
3454 | u32 eflags = kvm_x86_ops->get_rflags(vcpu); | |
3455 | kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT); | |
3456 | } | |
3457 | ||
3458 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
3459 | kvm_x86_ops->cache_regs(vcpu); | |
3460 | ||
3461 | if (nseg_desc.type & 8) | |
3462 | ret = kvm_task_switch_32(vcpu, tss_selector, &cseg_desc, | |
3463 | &nseg_desc); | |
3464 | else | |
3465 | ret = kvm_task_switch_16(vcpu, tss_selector, &cseg_desc, | |
3466 | &nseg_desc); | |
3467 | ||
3468 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) { | |
3469 | u32 eflags = kvm_x86_ops->get_rflags(vcpu); | |
3470 | kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT); | |
3471 | } | |
3472 | ||
3473 | if (reason != TASK_SWITCH_IRET) { | |
3474 | nseg_desc.type |= (1 << 8); | |
3475 | save_guest_segment_descriptor(vcpu, tss_selector, | |
3476 | &nseg_desc); | |
3477 | } | |
3478 | ||
3479 | kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS); | |
3480 | seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg); | |
3481 | tr_seg.type = 11; | |
3482 | set_segment(vcpu, &tr_seg, VCPU_SREG_TR); | |
3483 | out: | |
3484 | kvm_x86_ops->decache_regs(vcpu); | |
3485 | return ret; | |
3486 | } | |
3487 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
3488 | ||
b6c7a5dc HB |
3489 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
3490 | struct kvm_sregs *sregs) | |
3491 | { | |
3492 | int mmu_reset_needed = 0; | |
3493 | int i, pending_vec, max_bits; | |
3494 | struct descriptor_table dt; | |
3495 | ||
3496 | vcpu_load(vcpu); | |
3497 | ||
3498 | dt.limit = sregs->idt.limit; | |
3499 | dt.base = sregs->idt.base; | |
3500 | kvm_x86_ops->set_idt(vcpu, &dt); | |
3501 | dt.limit = sregs->gdt.limit; | |
3502 | dt.base = sregs->gdt.base; | |
3503 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
3504 | ||
ad312c7c ZX |
3505 | vcpu->arch.cr2 = sregs->cr2; |
3506 | mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3; | |
3507 | vcpu->arch.cr3 = sregs->cr3; | |
b6c7a5dc | 3508 | |
2d3ad1f4 | 3509 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 3510 | |
ad312c7c | 3511 | mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer; |
b6c7a5dc | 3512 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc HB |
3513 | kvm_set_apic_base(vcpu, sregs->apic_base); |
3514 | ||
3515 | kvm_x86_ops->decache_cr4_guest_bits(vcpu); | |
3516 | ||
ad312c7c | 3517 | mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0; |
b6c7a5dc | 3518 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 3519 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 3520 | |
ad312c7c | 3521 | mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4; |
b6c7a5dc HB |
3522 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
3523 | if (!is_long_mode(vcpu) && is_pae(vcpu)) | |
ad312c7c | 3524 | load_pdptrs(vcpu, vcpu->arch.cr3); |
b6c7a5dc HB |
3525 | |
3526 | if (mmu_reset_needed) | |
3527 | kvm_mmu_reset_context(vcpu); | |
3528 | ||
3529 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
ad312c7c ZX |
3530 | memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap, |
3531 | sizeof vcpu->arch.irq_pending); | |
3532 | vcpu->arch.irq_summary = 0; | |
3533 | for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i) | |
3534 | if (vcpu->arch.irq_pending[i]) | |
3535 | __set_bit(i, &vcpu->arch.irq_summary); | |
b6c7a5dc HB |
3536 | } else { |
3537 | max_bits = (sizeof sregs->interrupt_bitmap) << 3; | |
3538 | pending_vec = find_first_bit( | |
3539 | (const unsigned long *)sregs->interrupt_bitmap, | |
3540 | max_bits); | |
3541 | /* Only pending external irq is handled here */ | |
3542 | if (pending_vec < max_bits) { | |
3543 | kvm_x86_ops->set_irq(vcpu, pending_vec); | |
3544 | pr_debug("Set back pending irq %d\n", | |
3545 | pending_vec); | |
3546 | } | |
3547 | } | |
3548 | ||
3549 | set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); | |
3550 | set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
3551 | set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
3552 | set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
3553 | set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
3554 | set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
3555 | ||
3556 | set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); | |
3557 | set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
3558 | ||
3559 | vcpu_put(vcpu); | |
3560 | ||
3561 | return 0; | |
3562 | } | |
3563 | ||
3564 | int kvm_arch_vcpu_ioctl_debug_guest(struct kvm_vcpu *vcpu, | |
3565 | struct kvm_debug_guest *dbg) | |
3566 | { | |
3567 | int r; | |
3568 | ||
3569 | vcpu_load(vcpu); | |
3570 | ||
3571 | r = kvm_x86_ops->set_guest_debug(vcpu, dbg); | |
3572 | ||
3573 | vcpu_put(vcpu); | |
3574 | ||
3575 | return r; | |
3576 | } | |
3577 | ||
d0752060 HB |
3578 | /* |
3579 | * fxsave fpu state. Taken from x86_64/processor.h. To be killed when | |
3580 | * we have asm/x86/processor.h | |
3581 | */ | |
3582 | struct fxsave { | |
3583 | u16 cwd; | |
3584 | u16 swd; | |
3585 | u16 twd; | |
3586 | u16 fop; | |
3587 | u64 rip; | |
3588 | u64 rdp; | |
3589 | u32 mxcsr; | |
3590 | u32 mxcsr_mask; | |
3591 | u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ | |
3592 | #ifdef CONFIG_X86_64 | |
3593 | u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */ | |
3594 | #else | |
3595 | u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */ | |
3596 | #endif | |
3597 | }; | |
3598 | ||
8b006791 ZX |
3599 | /* |
3600 | * Translate a guest virtual address to a guest physical address. | |
3601 | */ | |
3602 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
3603 | struct kvm_translation *tr) | |
3604 | { | |
3605 | unsigned long vaddr = tr->linear_address; | |
3606 | gpa_t gpa; | |
3607 | ||
3608 | vcpu_load(vcpu); | |
72dc67a6 | 3609 | down_read(&vcpu->kvm->slots_lock); |
ad312c7c | 3610 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr); |
72dc67a6 | 3611 | up_read(&vcpu->kvm->slots_lock); |
8b006791 ZX |
3612 | tr->physical_address = gpa; |
3613 | tr->valid = gpa != UNMAPPED_GVA; | |
3614 | tr->writeable = 1; | |
3615 | tr->usermode = 0; | |
8b006791 ZX |
3616 | vcpu_put(vcpu); |
3617 | ||
3618 | return 0; | |
3619 | } | |
3620 | ||
d0752060 HB |
3621 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
3622 | { | |
ad312c7c | 3623 | struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image; |
d0752060 HB |
3624 | |
3625 | vcpu_load(vcpu); | |
3626 | ||
3627 | memcpy(fpu->fpr, fxsave->st_space, 128); | |
3628 | fpu->fcw = fxsave->cwd; | |
3629 | fpu->fsw = fxsave->swd; | |
3630 | fpu->ftwx = fxsave->twd; | |
3631 | fpu->last_opcode = fxsave->fop; | |
3632 | fpu->last_ip = fxsave->rip; | |
3633 | fpu->last_dp = fxsave->rdp; | |
3634 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
3635 | ||
3636 | vcpu_put(vcpu); | |
3637 | ||
3638 | return 0; | |
3639 | } | |
3640 | ||
3641 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
3642 | { | |
ad312c7c | 3643 | struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image; |
d0752060 HB |
3644 | |
3645 | vcpu_load(vcpu); | |
3646 | ||
3647 | memcpy(fxsave->st_space, fpu->fpr, 128); | |
3648 | fxsave->cwd = fpu->fcw; | |
3649 | fxsave->swd = fpu->fsw; | |
3650 | fxsave->twd = fpu->ftwx; | |
3651 | fxsave->fop = fpu->last_opcode; | |
3652 | fxsave->rip = fpu->last_ip; | |
3653 | fxsave->rdp = fpu->last_dp; | |
3654 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
3655 | ||
3656 | vcpu_put(vcpu); | |
3657 | ||
3658 | return 0; | |
3659 | } | |
3660 | ||
3661 | void fx_init(struct kvm_vcpu *vcpu) | |
3662 | { | |
3663 | unsigned after_mxcsr_mask; | |
3664 | ||
3665 | /* Initialize guest FPU by resetting ours and saving into guest's */ | |
3666 | preempt_disable(); | |
ad312c7c | 3667 | fx_save(&vcpu->arch.host_fx_image); |
d0752060 | 3668 | fpu_init(); |
ad312c7c ZX |
3669 | fx_save(&vcpu->arch.guest_fx_image); |
3670 | fx_restore(&vcpu->arch.host_fx_image); | |
d0752060 HB |
3671 | preempt_enable(); |
3672 | ||
ad312c7c | 3673 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 3674 | after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space); |
ad312c7c ZX |
3675 | vcpu->arch.guest_fx_image.mxcsr = 0x1f80; |
3676 | memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask, | |
d0752060 HB |
3677 | 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask); |
3678 | } | |
3679 | EXPORT_SYMBOL_GPL(fx_init); | |
3680 | ||
3681 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
3682 | { | |
3683 | if (!vcpu->fpu_active || vcpu->guest_fpu_loaded) | |
3684 | return; | |
3685 | ||
3686 | vcpu->guest_fpu_loaded = 1; | |
ad312c7c ZX |
3687 | fx_save(&vcpu->arch.host_fx_image); |
3688 | fx_restore(&vcpu->arch.guest_fx_image); | |
d0752060 HB |
3689 | } |
3690 | EXPORT_SYMBOL_GPL(kvm_load_guest_fpu); | |
3691 | ||
3692 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
3693 | { | |
3694 | if (!vcpu->guest_fpu_loaded) | |
3695 | return; | |
3696 | ||
3697 | vcpu->guest_fpu_loaded = 0; | |
ad312c7c ZX |
3698 | fx_save(&vcpu->arch.guest_fx_image); |
3699 | fx_restore(&vcpu->arch.host_fx_image); | |
f096ed85 | 3700 | ++vcpu->stat.fpu_reload; |
d0752060 HB |
3701 | } |
3702 | EXPORT_SYMBOL_GPL(kvm_put_guest_fpu); | |
e9b11c17 ZX |
3703 | |
3704 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
3705 | { | |
3706 | kvm_x86_ops->vcpu_free(vcpu); | |
3707 | } | |
3708 | ||
3709 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
3710 | unsigned int id) | |
3711 | { | |
26e5215f AK |
3712 | return kvm_x86_ops->vcpu_create(kvm, id); |
3713 | } | |
e9b11c17 | 3714 | |
26e5215f AK |
3715 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
3716 | { | |
3717 | int r; | |
e9b11c17 ZX |
3718 | |
3719 | /* We do fxsave: this must be aligned. */ | |
ad312c7c | 3720 | BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF); |
e9b11c17 ZX |
3721 | |
3722 | vcpu_load(vcpu); | |
3723 | r = kvm_arch_vcpu_reset(vcpu); | |
3724 | if (r == 0) | |
3725 | r = kvm_mmu_setup(vcpu); | |
3726 | vcpu_put(vcpu); | |
3727 | if (r < 0) | |
3728 | goto free_vcpu; | |
3729 | ||
26e5215f | 3730 | return 0; |
e9b11c17 ZX |
3731 | free_vcpu: |
3732 | kvm_x86_ops->vcpu_free(vcpu); | |
26e5215f | 3733 | return r; |
e9b11c17 ZX |
3734 | } |
3735 | ||
d40ccc62 | 3736 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 ZX |
3737 | { |
3738 | vcpu_load(vcpu); | |
3739 | kvm_mmu_unload(vcpu); | |
3740 | vcpu_put(vcpu); | |
3741 | ||
3742 | kvm_x86_ops->vcpu_free(vcpu); | |
3743 | } | |
3744 | ||
3745 | int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu) | |
3746 | { | |
3747 | return kvm_x86_ops->vcpu_reset(vcpu); | |
3748 | } | |
3749 | ||
3750 | void kvm_arch_hardware_enable(void *garbage) | |
3751 | { | |
3752 | kvm_x86_ops->hardware_enable(garbage); | |
3753 | } | |
3754 | ||
3755 | void kvm_arch_hardware_disable(void *garbage) | |
3756 | { | |
3757 | kvm_x86_ops->hardware_disable(garbage); | |
3758 | } | |
3759 | ||
3760 | int kvm_arch_hardware_setup(void) | |
3761 | { | |
3762 | return kvm_x86_ops->hardware_setup(); | |
3763 | } | |
3764 | ||
3765 | void kvm_arch_hardware_unsetup(void) | |
3766 | { | |
3767 | kvm_x86_ops->hardware_unsetup(); | |
3768 | } | |
3769 | ||
3770 | void kvm_arch_check_processor_compat(void *rtn) | |
3771 | { | |
3772 | kvm_x86_ops->check_processor_compatibility(rtn); | |
3773 | } | |
3774 | ||
3775 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) | |
3776 | { | |
3777 | struct page *page; | |
3778 | struct kvm *kvm; | |
3779 | int r; | |
3780 | ||
3781 | BUG_ON(vcpu->kvm == NULL); | |
3782 | kvm = vcpu->kvm; | |
3783 | ||
ad312c7c | 3784 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
e9b11c17 | 3785 | if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0) |
ad312c7c | 3786 | vcpu->arch.mp_state = VCPU_MP_STATE_RUNNABLE; |
e9b11c17 | 3787 | else |
ad312c7c | 3788 | vcpu->arch.mp_state = VCPU_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
3789 | |
3790 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
3791 | if (!page) { | |
3792 | r = -ENOMEM; | |
3793 | goto fail; | |
3794 | } | |
ad312c7c | 3795 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 ZX |
3796 | |
3797 | r = kvm_mmu_create(vcpu); | |
3798 | if (r < 0) | |
3799 | goto fail_free_pio_data; | |
3800 | ||
3801 | if (irqchip_in_kernel(kvm)) { | |
3802 | r = kvm_create_lapic(vcpu); | |
3803 | if (r < 0) | |
3804 | goto fail_mmu_destroy; | |
3805 | } | |
3806 | ||
3807 | return 0; | |
3808 | ||
3809 | fail_mmu_destroy: | |
3810 | kvm_mmu_destroy(vcpu); | |
3811 | fail_free_pio_data: | |
ad312c7c | 3812 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
3813 | fail: |
3814 | return r; | |
3815 | } | |
3816 | ||
3817 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
3818 | { | |
3819 | kvm_free_lapic(vcpu); | |
3820 | kvm_mmu_destroy(vcpu); | |
ad312c7c | 3821 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 | 3822 | } |
d19a9cd2 ZX |
3823 | |
3824 | struct kvm *kvm_arch_create_vm(void) | |
3825 | { | |
3826 | struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL); | |
3827 | ||
3828 | if (!kvm) | |
3829 | return ERR_PTR(-ENOMEM); | |
3830 | ||
f05e70ac | 3831 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
d19a9cd2 ZX |
3832 | |
3833 | return kvm; | |
3834 | } | |
3835 | ||
3836 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
3837 | { | |
3838 | vcpu_load(vcpu); | |
3839 | kvm_mmu_unload(vcpu); | |
3840 | vcpu_put(vcpu); | |
3841 | } | |
3842 | ||
3843 | static void kvm_free_vcpus(struct kvm *kvm) | |
3844 | { | |
3845 | unsigned int i; | |
3846 | ||
3847 | /* | |
3848 | * Unpin any mmu pages first. | |
3849 | */ | |
3850 | for (i = 0; i < KVM_MAX_VCPUS; ++i) | |
3851 | if (kvm->vcpus[i]) | |
3852 | kvm_unload_vcpu_mmu(kvm->vcpus[i]); | |
3853 | for (i = 0; i < KVM_MAX_VCPUS; ++i) { | |
3854 | if (kvm->vcpus[i]) { | |
3855 | kvm_arch_vcpu_free(kvm->vcpus[i]); | |
3856 | kvm->vcpus[i] = NULL; | |
3857 | } | |
3858 | } | |
3859 | ||
3860 | } | |
3861 | ||
3862 | void kvm_arch_destroy_vm(struct kvm *kvm) | |
3863 | { | |
7837699f | 3864 | kvm_free_pit(kvm); |
d7deeeb0 ZX |
3865 | kfree(kvm->arch.vpic); |
3866 | kfree(kvm->arch.vioapic); | |
d19a9cd2 ZX |
3867 | kvm_free_vcpus(kvm); |
3868 | kvm_free_physmem(kvm); | |
3869 | kfree(kvm); | |
3870 | } | |
0de10343 ZX |
3871 | |
3872 | int kvm_arch_set_memory_region(struct kvm *kvm, | |
3873 | struct kvm_userspace_memory_region *mem, | |
3874 | struct kvm_memory_slot old, | |
3875 | int user_alloc) | |
3876 | { | |
3877 | int npages = mem->memory_size >> PAGE_SHIFT; | |
3878 | struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot]; | |
3879 | ||
3880 | /*To keep backward compatibility with older userspace, | |
3881 | *x86 needs to hanlde !user_alloc case. | |
3882 | */ | |
3883 | if (!user_alloc) { | |
3884 | if (npages && !old.rmap) { | |
72dc67a6 | 3885 | down_write(¤t->mm->mmap_sem); |
0de10343 ZX |
3886 | memslot->userspace_addr = do_mmap(NULL, 0, |
3887 | npages * PAGE_SIZE, | |
3888 | PROT_READ | PROT_WRITE, | |
3889 | MAP_SHARED | MAP_ANONYMOUS, | |
3890 | 0); | |
72dc67a6 | 3891 | up_write(¤t->mm->mmap_sem); |
0de10343 ZX |
3892 | |
3893 | if (IS_ERR((void *)memslot->userspace_addr)) | |
3894 | return PTR_ERR((void *)memslot->userspace_addr); | |
3895 | } else { | |
3896 | if (!old.user_alloc && old.rmap) { | |
3897 | int ret; | |
3898 | ||
72dc67a6 | 3899 | down_write(¤t->mm->mmap_sem); |
0de10343 ZX |
3900 | ret = do_munmap(current->mm, old.userspace_addr, |
3901 | old.npages * PAGE_SIZE); | |
72dc67a6 | 3902 | up_write(¤t->mm->mmap_sem); |
0de10343 ZX |
3903 | if (ret < 0) |
3904 | printk(KERN_WARNING | |
3905 | "kvm_vm_ioctl_set_memory_region: " | |
3906 | "failed to munmap memory\n"); | |
3907 | } | |
3908 | } | |
3909 | } | |
3910 | ||
f05e70ac | 3911 | if (!kvm->arch.n_requested_mmu_pages) { |
0de10343 ZX |
3912 | unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); |
3913 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); | |
3914 | } | |
3915 | ||
3916 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); | |
3917 | kvm_flush_remote_tlbs(kvm); | |
3918 | ||
3919 | return 0; | |
3920 | } | |
1d737c8a ZX |
3921 | |
3922 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) | |
3923 | { | |
3924 | return vcpu->arch.mp_state == VCPU_MP_STATE_RUNNABLE | |
3925 | || vcpu->arch.mp_state == VCPU_MP_STATE_SIPI_RECEIVED; | |
3926 | } | |
5736199a ZX |
3927 | |
3928 | static void vcpu_kick_intr(void *info) | |
3929 | { | |
3930 | #ifdef DEBUG | |
3931 | struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info; | |
3932 | printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu); | |
3933 | #endif | |
3934 | } | |
3935 | ||
3936 | void kvm_vcpu_kick(struct kvm_vcpu *vcpu) | |
3937 | { | |
3938 | int ipi_pcpu = vcpu->cpu; | |
3939 | ||
3940 | if (waitqueue_active(&vcpu->wq)) { | |
3941 | wake_up_interruptible(&vcpu->wq); | |
3942 | ++vcpu->stat.halt_wakeup; | |
3943 | } | |
3944 | if (vcpu->guest_mode) | |
3945 | smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0, 0); | |
3946 | } |