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KVM: do not release the error page
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
1361b83a 60#include <asm/fpu-internal.h> /* Ugh! */
98918833 61#include <asm/xcr.h>
1d5f066e 62#include <asm/pvclock.h>
217fc9cf 63#include <asm/div64.h>
043405e1 64
313a3dc7 65#define MAX_IO_MSRS 256
890ca9ae 66#define KVM_MAX_MCE_BANKS 32
5854dbca 67#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 68
0f65dd70
AK		 69#define emul_to_vcpu(ctxt) \
70 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
1260edbe
LJ		 77static
78u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 79#else
1260edbe 80static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 81#endif
313a3dc7 82
ba1389b7
AK		 83#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 85
cb142eb7 86static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 87static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
476bc001
RR		 92static bool ignore_msrs = 0;
93module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 94
92a1f12d
JR		 95bool kvm_has_tsc_control;
96EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97u32 kvm_max_guest_tsc_khz;
98EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
cc578287
ZA		 100/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101static u32 tsc_tolerance_ppm = 250;
102module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
18863bdd
AK		 104#define KVM_NR_SHARED_MSRS 16
105
106struct kvm_shared_msrs_global {
107 int nr;
2bf78fa7 108 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111struct kvm_shared_msrs {
112 struct user_return_notifier urn;
113 bool registered;
2bf78fa7
SY		 114 struct kvm_shared_msr_values {
115 u64 host;
116 u64 curr;
117 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 118};
119
120static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
417bc304 123struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 124 { "pf_fixed", VCPU_STAT(pf_fixed) },
125 { "pf_guest", VCPU_STAT(pf_guest) },
126 { "tlb_flush", VCPU_STAT(tlb_flush) },
127 { "invlpg", VCPU_STAT(invlpg) },
128 { "exits", VCPU_STAT(exits) },
129 { "io_exits", VCPU_STAT(io_exits) },
130 { "mmio_exits", VCPU_STAT(mmio_exits) },
131 { "signal_exits", VCPU_STAT(signal_exits) },
132 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 133 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 134 { "halt_exits", VCPU_STAT(halt_exits) },
135 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 136 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 137 { "request_irq", VCPU_STAT(request_irq_exits) },
138 { "irq_exits", VCPU_STAT(irq_exits) },
139 { "host_state_reload", VCPU_STAT(host_state_reload) },
140 { "efer_reload", VCPU_STAT(efer_reload) },
141 { "fpu_reload", VCPU_STAT(fpu_reload) },
142 { "insn_emulation", VCPU_STAT(insn_emulation) },
143 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 144 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 145 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 146 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150 { "mmu_flooded", VM_STAT(mmu_flooded) },
151 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 152 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 153 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 154 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 155 { "largepages", VM_STAT(lpages) },
417bc304
HB		 156 { NULL }
157};
158
2acf923e
DC		 159u64 __read_mostly host_xcr0;
160
d6aa1000
AK		 161int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162
af585b92
GN		 163static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
164{
165 int i;
166 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167 vcpu->arch.apf.gfns[i] = ~0;
168}
169
18863bdd
AK		 170static void kvm_on_user_return(struct user_return_notifier *urn)
171{
172 unsigned slot;
18863bdd
AK		 173 struct kvm_shared_msrs *locals
174 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 175 struct kvm_shared_msr_values *values;
18863bdd
AK		 176
177 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 178 values = &locals->values[slot];
179 if (values->host != values->curr) {
180 wrmsrl(shared_msrs_global.msrs[slot], values->host);
181 values->curr = values->host;
18863bdd
AK		 182 }
183 }
184 locals->registered = false;
185 user_return_notifier_unregister(urn);
186}
187
2bf78fa7 188static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 189{
2bf78fa7 190 struct kvm_shared_msrs *smsr;
18863bdd
AK		 191 u64 value;
192
2bf78fa7
SY		 193 smsr = &__get_cpu_var(shared_msrs);
194 /* only read, and nobody should modify it at this time,
195 * so don't need lock */
196 if (slot >= shared_msrs_global.nr) {
197 printk(KERN_ERR "kvm: invalid MSR slot!");
198 return;
199 }
200 rdmsrl_safe(msr, &value);
201 smsr->values[slot].host = value;
202 smsr->values[slot].curr = value;
203}
204
205void kvm_define_shared_msr(unsigned slot, u32 msr)
206{
18863bdd
AK		 207 if (slot >= shared_msrs_global.nr)
208 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 209 shared_msrs_global.msrs[slot] = msr;
210 /* we need ensured the shared_msr_global have been updated */
211 smp_wmb();
18863bdd
AK		 212}
213EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214
215static void kvm_shared_msr_cpu_online(void)
216{
217 unsigned i;
18863bdd
AK		 218
219 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 220 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 221}
222
d5696725 223void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 224{
225 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
2bf78fa7 227 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 228 return;
2bf78fa7
SY		 229 smsr->values[slot].curr = value;
230 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 231 if (!smsr->registered) {
232 smsr->urn.on_user_return = kvm_on_user_return;
233 user_return_notifier_register(&smsr->urn);
234 smsr->registered = true;
235 }
236}
237EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238
3548bab5
AK		 239static void drop_user_return_notifiers(void *ignore)
240{
241 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242
243 if (smsr->registered)
244 kvm_on_user_return(&smsr->urn);
245}
246
6866b83e
CO		 247u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248{
249 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 250 return vcpu->arch.apic_base;
6866b83e 251 else
ad312c7c 252 return vcpu->arch.apic_base;
6866b83e
CO		 253}
254EXPORT_SYMBOL_GPL(kvm_get_apic_base);
255
256void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
257{
258 /* TODO: reserve bits check */
259 if (irqchip_in_kernel(vcpu->kvm))
260 kvm_lapic_set_base(vcpu, data);
261 else
ad312c7c 262 vcpu->arch.apic_base = data;
6866b83e
CO		 263}
264EXPORT_SYMBOL_GPL(kvm_set_apic_base);
265
3fd28fce
ED		 266#define EXCPT_BENIGN 0
267#define EXCPT_CONTRIBUTORY 1
268#define EXCPT_PF 2
269
270static int exception_class(int vector)
271{
272 switch (vector) {
273 case PF_VECTOR:
274 return EXCPT_PF;
275 case DE_VECTOR:
276 case TS_VECTOR:
277 case NP_VECTOR:
278 case SS_VECTOR:
279 case GP_VECTOR:
280 return EXCPT_CONTRIBUTORY;
281 default:
282 break;
283 }
284 return EXCPT_BENIGN;
285}
286
287static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 288 unsigned nr, bool has_error, u32 error_code,
289 bool reinject)
3fd28fce
ED		 290{
291 u32 prev_nr;
292 int class1, class2;
293
3842d135
AK		 294 kvm_make_request(KVM_REQ_EVENT, vcpu);
295
3fd28fce
ED		 296 if (!vcpu->arch.exception.pending) {
297 queue:
298 vcpu->arch.exception.pending = true;
299 vcpu->arch.exception.has_error_code = has_error;
300 vcpu->arch.exception.nr = nr;
301 vcpu->arch.exception.error_code = error_code;
3f0fd292 302 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 303 return;
304 }
305
306 /* to check exception */
307 prev_nr = vcpu->arch.exception.nr;
308 if (prev_nr == DF_VECTOR) {
309 /* triple fault -> shutdown */
a8eeb04a 310 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 311 return;
312 }
313 class1 = exception_class(prev_nr);
314 class2 = exception_class(nr);
315 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
316 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
317 /* generate double fault per SDM Table 5-5 */
318 vcpu->arch.exception.pending = true;
319 vcpu->arch.exception.has_error_code = true;
320 vcpu->arch.exception.nr = DF_VECTOR;
321 vcpu->arch.exception.error_code = 0;
322 } else
323 /* replace previous exception with a new one in a hope
324 that instruction re-execution will regenerate lost
325 exception */
326 goto queue;
327}
328
298101da
AK		 329void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
ce7ddec4 331 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 332}
333EXPORT_SYMBOL_GPL(kvm_queue_exception);
334
ce7ddec4
JR		 335void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
336{
337 kvm_multiple_exception(vcpu, nr, false, 0, true);
338}
339EXPORT_SYMBOL_GPL(kvm_requeue_exception);
340
db8fcefa 341void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 342{
db8fcefa
AP		 343 if (err)
344 kvm_inject_gp(vcpu, 0);
345 else
346 kvm_x86_ops->skip_emulated_instruction(vcpu);
347}
348EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 349
6389ee94 350void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 351{
352 ++vcpu->stat.pf_guest;
6389ee94
AK		 353 vcpu->arch.cr2 = fault->address;
354 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 355}
27d6c865 356EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 357
6389ee94 358void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 359{
6389ee94
AK		 360 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
361 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 362 else
6389ee94 363 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 364}
365
3419ffc8
SY		 366void kvm_inject_nmi(struct kvm_vcpu *vcpu)
367{
7460fb4a
AK		 368 atomic_inc(&vcpu->arch.nmi_queued);
369 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 370}
371EXPORT_SYMBOL_GPL(kvm_inject_nmi);
372
298101da
AK		 373void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374{
ce7ddec4 375 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 376}
377EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
378
ce7ddec4
JR		 379void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
380{
381 kvm_multiple_exception(vcpu, nr, true, error_code, true);
382}
383EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
384
0a79b009
AK		 385/*
386 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
387 * a #GP and return false.
388 */
389bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 390{
0a79b009
AK		 391 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
392 return true;
393 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
394 return false;
298101da 395}
0a79b009 396EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 397
ec92fe44
JR		 398/*
399 * This function will be used to read from the physical memory of the currently
400 * running guest. The difference to kvm_read_guest_page is that this function
401 * can read from guest physical or from the guest's guest physical memory.
402 */
403int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
404 gfn_t ngfn, void *data, int offset, int len,
405 u32 access)
406{
407 gfn_t real_gfn;
408 gpa_t ngpa;
409
410 ngpa = gfn_to_gpa(ngfn);
411 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
412 if (real_gfn == UNMAPPED_GVA)
413 return -EFAULT;
414
415 real_gfn = gpa_to_gfn(real_gfn);
416
417 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
418}
419EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
420
3d06b8bf
JR		 421int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
422 void *data, int offset, int len, u32 access)
423{
424 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
425 data, offset, len, access);
426}
427
a03490ed
CO		 428/*
429 * Load the pae pdptrs. Return true is they are all valid.
430 */
ff03a073 431int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 432{
433 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
434 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
435 int i;
436 int ret;
ff03a073 437 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 438
ff03a073
JR		 439 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
440 offset * sizeof(u64), sizeof(pdpte),
441 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 442 if (ret < 0) {
443 ret = 0;
444 goto out;
445 }
446 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 447 if (is_present_gpte(pdpte[i]) &&
20c466b5 448 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 449 ret = 0;
450 goto out;
451 }
452 }
453 ret = 1;
454
ff03a073 455 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_avail);
458 __set_bit(VCPU_EXREG_PDPTR,
459 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 460out:
a03490ed
CO		 461
462 return ret;
463}
cc4b6871 464EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 465
d835dfec
AK		 466static bool pdptrs_changed(struct kvm_vcpu *vcpu)
467{
ff03a073 468 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 469 bool changed = true;
3d06b8bf
JR		 470 int offset;
471 gfn_t gfn;
d835dfec
AK		 472 int r;
473
474 if (is_long_mode(vcpu) || !is_pae(vcpu))
475 return false;
476
6de4f3ad
AK		 477 if (!test_bit(VCPU_EXREG_PDPTR,
478 (unsigned long *)&vcpu->arch.regs_avail))
479 return true;
480
9f8fe504
AK		 481 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
482 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 483 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
484 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 485 if (r < 0)
486 goto out;
ff03a073 487 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 488out:
d835dfec
AK		 489
490 return changed;
491}
492
49a9b07e 493int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 494{
aad82703
SY		 495 unsigned long old_cr0 = kvm_read_cr0(vcpu);
496 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
497 X86_CR0_CD | X86_CR0_NW;
498
f9a48e6a
AK		 499 cr0 |= X86_CR0_ET;
500
ab344828 501#ifdef CONFIG_X86_64
0f12244f
GN		 502 if (cr0 & 0xffffffff00000000UL)
503 return 1;
ab344828
GN		 504#endif
505
506 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 507
0f12244f
GN		 508 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
509 return 1;
a03490ed 510
0f12244f
GN		 511 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
512 return 1;
a03490ed
CO		 513
514 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
515#ifdef CONFIG_X86_64
f6801dff 516 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 517 int cs_db, cs_l;
518
0f12244f
GN		 519 if (!is_pae(vcpu))
520 return 1;
a03490ed 521 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 522 if (cs_l)
523 return 1;
a03490ed
CO		 524 } else
525#endif
ff03a073 526 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 527 kvm_read_cr3(vcpu)))
0f12244f 528 return 1;
a03490ed
CO		 529 }
530
ad756a16
MJ		 531 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
532 return 1;
533
a03490ed 534 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 535
d170c419 536 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 537 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 538 kvm_async_pf_hash_reset(vcpu);
539 }
e5f3f027 540
aad82703
SY		 541 if ((cr0 ^ old_cr0) & update_bits)
542 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 543 return 0;
544}
2d3ad1f4 545EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 546
2d3ad1f4 547void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 548{
49a9b07e 549 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 550}
2d3ad1f4 551EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 552
2acf923e
DC		 553int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
554{
555 u64 xcr0;
556
557 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
558 if (index != XCR_XFEATURE_ENABLED_MASK)
559 return 1;
560 xcr0 = xcr;
561 if (kvm_x86_ops->get_cpl(vcpu) != 0)
562 return 1;
563 if (!(xcr0 & XSTATE_FP))
564 return 1;
565 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
566 return 1;
567 if (xcr0 & ~host_xcr0)
568 return 1;
569 vcpu->arch.xcr0 = xcr0;
570 vcpu->guest_xcr0_loaded = 0;
571 return 0;
572}
573
574int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
575{
576 if (__kvm_set_xcr(vcpu, index, xcr)) {
577 kvm_inject_gp(vcpu, 0);
578 return 1;
579 }
580 return 0;
581}
582EXPORT_SYMBOL_GPL(kvm_set_xcr);
583
a83b29c6 584int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 585{
fc78f519 586 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 587 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
588 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 589 if (cr4 & CR4_RESERVED_BITS)
590 return 1;
a03490ed 591
2acf923e
DC		 592 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
593 return 1;
594
c68b734f
YW		 595 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
596 return 1;
597
74dc2b4f
YW		 598 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
599 return 1;
600
a03490ed 601 if (is_long_mode(vcpu)) {
0f12244f
GN		 602 if (!(cr4 & X86_CR4_PAE))
603 return 1;
a2edf57f
AK		 604 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 606 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
607 kvm_read_cr3(vcpu)))
0f12244f
GN		 608 return 1;
609
ad756a16
MJ		 610 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
611 if (!guest_cpuid_has_pcid(vcpu))
612 return 1;
613
614 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
615 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
616 return 1;
617 }
618
5e1746d6 619 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 620 return 1;
a03490ed 621
ad756a16
MJ		 622 if (((cr4 ^ old_cr4) & pdptr_bits) ||
623 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 624 kvm_mmu_reset_context(vcpu);
0f12244f 625
2acf923e 626 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 627 kvm_update_cpuid(vcpu);
2acf923e 628
0f12244f
GN		 629 return 0;
630}
2d3ad1f4 631EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 632
2390218b 633int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 634{
9f8fe504 635 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 636 kvm_mmu_sync_roots(vcpu);
d835dfec 637 kvm_mmu_flush_tlb(vcpu);
0f12244f 638 return 0;
d835dfec
AK		 639 }
640
a03490ed 641 if (is_long_mode(vcpu)) {
ad756a16
MJ		 642 if (kvm_read_cr4(vcpu) & X86_CR4_PCIDE) {
643 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
644 return 1;
645 } else
646 if (cr3 & CR3_L_MODE_RESERVED_BITS)
647 return 1;
a03490ed
CO		 648 } else {
649 if (is_pae(vcpu)) {
0f12244f
GN		 650 if (cr3 & CR3_PAE_RESERVED_BITS)
651 return 1;
ff03a073
JR		 652 if (is_paging(vcpu) &&
653 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 654 return 1;
a03490ed
CO		 655 }
656 /*
657 * We don't check reserved bits in nonpae mode, because
658 * this isn't enforced, and VMware depends on this.
659 */
660 }
661
a03490ed
CO		 662 /*
663 * Does the new cr3 value map to physical memory? (Note, we
664 * catch an invalid cr3 even in real-mode, because it would
665 * cause trouble later on when we turn on paging anyway.)
666 *
667 * A real CPU would silently accept an invalid cr3 and would
668 * attempt to use it - with largely undefined (and often hard
669 * to debug) behavior on the guest side.
670 */
671 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 672 return 1;
673 vcpu->arch.cr3 = cr3;
aff48baa 674 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 675 vcpu->arch.mmu.new_cr3(vcpu);
676 return 0;
677}
2d3ad1f4 678EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 679
eea1cff9 680int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 681{
0f12244f
GN		 682 if (cr8 & CR8_RESERVED_BITS)
683 return 1;
a03490ed
CO		 684 if (irqchip_in_kernel(vcpu->kvm))
685 kvm_lapic_set_tpr(vcpu, cr8);
686 else
ad312c7c 687 vcpu->arch.cr8 = cr8;
0f12244f
GN		 688 return 0;
689}
2d3ad1f4 690EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 691
2d3ad1f4 692unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 693{
694 if (irqchip_in_kernel(vcpu->kvm))
695 return kvm_lapic_get_cr8(vcpu);
696 else
ad312c7c 697 return vcpu->arch.cr8;
a03490ed 698}
2d3ad1f4 699EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 700
338dbc97 701static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 702{
703 switch (dr) {
704 case 0 ... 3:
705 vcpu->arch.db[dr] = val;
706 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
707 vcpu->arch.eff_db[dr] = val;
708 break;
709 case 4:
338dbc97
GN		 710 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
711 return 1; /* #UD */
020df079
GN		 712 /* fall through */
713 case 6:
338dbc97
GN		 714 if (val & 0xffffffff00000000ULL)
715 return -1; /* #GP */
020df079
GN		 716 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
717 break;
718 case 5:
338dbc97
GN		 719 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
720 return 1; /* #UD */
020df079
GN		 721 /* fall through */
722 default: /* 7 */
338dbc97
GN		 723 if (val & 0xffffffff00000000ULL)
724 return -1; /* #GP */
020df079
GN		 725 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
726 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
727 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
728 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
729 }
730 break;
731 }
732
733 return 0;
734}
338dbc97
GN		 735
736int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
737{
738 int res;
739
740 res = __kvm_set_dr(vcpu, dr, val);
741 if (res > 0)
742 kvm_queue_exception(vcpu, UD_VECTOR);
743 else if (res < 0)
744 kvm_inject_gp(vcpu, 0);
745
746 return res;
747}
020df079
GN		 748EXPORT_SYMBOL_GPL(kvm_set_dr);
749
338dbc97 750static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 751{
752 switch (dr) {
753 case 0 ... 3:
754 *val = vcpu->arch.db[dr];
755 break;
756 case 4:
338dbc97 757 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 758 return 1;
020df079
GN		 759 /* fall through */
760 case 6:
761 *val = vcpu->arch.dr6;
762 break;
763 case 5:
338dbc97 764 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 765 return 1;
020df079
GN		 766 /* fall through */
767 default: /* 7 */
768 *val = vcpu->arch.dr7;
769 break;
770 }
771
772 return 0;
773}
338dbc97
GN		 774
775int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
776{
777 if (_kvm_get_dr(vcpu, dr, val)) {
778 kvm_queue_exception(vcpu, UD_VECTOR);
779 return 1;
780 }
781 return 0;
782}
020df079
GN		 783EXPORT_SYMBOL_GPL(kvm_get_dr);
784
022cd0e8
AK		 785bool kvm_rdpmc(struct kvm_vcpu *vcpu)
786{
787 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
788 u64 data;
789 int err;
790
791 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
792 if (err)
793 return err;
794 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
795 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
796 return err;
797}
798EXPORT_SYMBOL_GPL(kvm_rdpmc);
799
043405e1
CO		 800/*
801 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
802 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
803 *
804 * This list is modified at module load time to reflect the
e3267cbb
GC		 805 * capabilities of the host cpu. This capabilities test skips MSRs that are
806 * kvm-specific. Those are put in the beginning of the list.
043405e1 807 */
e3267cbb 808
e115676e 809#define KVM_SAVE_MSRS_BEGIN 10
043405e1 810static u32 msrs_to_save[] = {
e3267cbb 811 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 812 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 813 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 814 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 815 MSR_KVM_PV_EOI_EN,
043405e1 816 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 817 MSR_STAR,
043405e1
CO		 818#ifdef CONFIG_X86_64
819 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
820#endif
e90aa41e 821 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 822};
823
824static unsigned num_msrs_to_save;
825
826static u32 emulated_msrs[] = {
a3e06bbe 827 MSR_IA32_TSCDEADLINE,
043405e1 828 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 829 MSR_IA32_MCG_STATUS,
830 MSR_IA32_MCG_CTL,
043405e1
CO		 831};
832
b69e8cae 833static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 834{
aad82703
SY		 835 u64 old_efer = vcpu->arch.efer;
836
b69e8cae
RJ		 837 if (efer & efer_reserved_bits)
838 return 1;
15c4a640
CO		 839
840 if (is_paging(vcpu)
b69e8cae
RJ		 841 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
842 return 1;
15c4a640 843
1b2fd70c
AG		 844 if (efer & EFER_FFXSR) {
845 struct kvm_cpuid_entry2 *feat;
846
847 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 848 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
849 return 1;
1b2fd70c
AG		 850 }
851
d8017474
AG		 852 if (efer & EFER_SVME) {
853 struct kvm_cpuid_entry2 *feat;
854
855 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 856 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
857 return 1;
d8017474
AG		 858 }
859
15c4a640 860 efer &= ~EFER_LMA;
f6801dff 861 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 862
a3d204e2
SY		 863 kvm_x86_ops->set_efer(vcpu, efer);
864
9645bb56 865 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 866
aad82703
SY		 867 /* Update reserved bits */
868 if ((efer ^ old_efer) & EFER_NX)
869 kvm_mmu_reset_context(vcpu);
870
b69e8cae 871 return 0;
15c4a640
CO		 872}
873
f2b4b7dd
JR		 874void kvm_enable_efer_bits(u64 mask)
875{
876 efer_reserved_bits &= ~mask;
877}
878EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
879
880
15c4a640
CO		 881/*
882 * Writes msr value into into the appropriate "register".
883 * Returns 0 on success, non-0 otherwise.
884 * Assumes vcpu_load() was already called.
885 */
886int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
887{
888 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
889}
890
313a3dc7
CO		 891/*
892 * Adapt set_msr() to msr_io()'s calling convention
893 */
894static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
895{
896 return kvm_set_msr(vcpu, index, *data);
897}
898
18068523
GOC		 899static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
900{
9ed3c444
AK		 901 int version;
902 int r;
50d0a0f9 903 struct pvclock_wall_clock wc;
923de3cf 904 struct timespec boot;
18068523
GOC		 905
906 if (!wall_clock)
907 return;
908
9ed3c444
AK		 909 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
910 if (r)
911 return;
912
913 if (version & 1)
914 ++version; /* first time write, random junk */
915
916 ++version;
18068523 917
18068523
GOC		 918 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
919
50d0a0f9
GH		 920 /*
921 * The guest calculates current wall clock time by adding
34c238a1 922 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 923 * wall clock specified here. guest system time equals host
924 * system time for us, thus we must fill in host boot time here.
925 */
923de3cf 926 getboottime(&boot);
50d0a0f9 927
4b648665
BR		 928 if (kvm->arch.kvmclock_offset) {
929 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
930 boot = timespec_sub(boot, ts);
931 }
50d0a0f9
GH		 932 wc.sec = boot.tv_sec;
933 wc.nsec = boot.tv_nsec;
934 wc.version = version;
18068523
GOC		 935
936 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
937
938 version++;
939 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 940}
941
50d0a0f9
GH		 942static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
943{
944 uint32_t quotient, remainder;
945
946 /* Don't try to replace with do_div(), this one calculates
947 * "(dividend << 32) / divisor" */
948 __asm__ ( "divl %4"
949 : "=a" (quotient), "=d" (remainder)
950 : "0" (0), "1" (dividend), "r" (divisor) );
951 return quotient;
952}
953
5f4e3f88
ZA		 954static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
955 s8 *pshift, u32 *pmultiplier)
50d0a0f9 956{
5f4e3f88 957 uint64_t scaled64;
50d0a0f9
GH		 958 int32_t shift = 0;
959 uint64_t tps64;
960 uint32_t tps32;
961
5f4e3f88
ZA		 962 tps64 = base_khz * 1000LL;
963 scaled64 = scaled_khz * 1000LL;
50933623 964 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 965 tps64 >>= 1;
966 shift--;
967 }
968
969 tps32 = (uint32_t)tps64;
50933623
JK		 970 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
971 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 972 scaled64 >>= 1;
973 else
974 tps32 <<= 1;
50d0a0f9
GH		 975 shift++;
976 }
977
5f4e3f88
ZA		 978 *pshift = shift;
979 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 980
5f4e3f88
ZA		 981 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
982 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 983}
984
759379dd
ZA		 985static inline u64 get_kernel_ns(void)
986{
987 struct timespec ts;
988
989 WARN_ON(preemptible());
990 ktime_get_ts(&ts);
991 monotonic_to_bootbased(&ts);
992 return timespec_to_ns(&ts);
50d0a0f9
GH		 993}
994
c8076604 995static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 996unsigned long max_tsc_khz;
c8076604 997
cc578287 998static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 999{
cc578287
ZA		 1000 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1001 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1002}
1003
cc578287 1004static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1005{
cc578287
ZA		 1006 u64 v = (u64)khz * (1000000 + ppm);
1007 do_div(v, 1000000);
1008 return v;
1e993611
JR		 1009}
1010
cc578287 1011static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1012{
cc578287
ZA		 1013 u32 thresh_lo, thresh_hi;
1014 int use_scaling = 0;
217fc9cf 1015
c285545f
ZA		 1016 /* Compute a scale to convert nanoseconds in TSC cycles */
1017 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1018 &vcpu->arch.virtual_tsc_shift,
1019 &vcpu->arch.virtual_tsc_mult);
1020 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1021
1022 /*
1023 * Compute the variation in TSC rate which is acceptable
1024 * within the range of tolerance and decide if the
1025 * rate being applied is within that bounds of the hardware
1026 * rate. If so, no scaling or compensation need be done.
1027 */
1028 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1029 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1030 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1031 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1032 use_scaling = 1;
1033 }
1034 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1035}
1036
1037static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1038{
e26101b1 1039 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1040 vcpu->arch.virtual_tsc_mult,
1041 vcpu->arch.virtual_tsc_shift);
e26101b1 1042 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1043 return tsc;
1044}
1045
99e3e30a
ZA		 1046void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1047{
1048 struct kvm *kvm = vcpu->kvm;
f38e098f 1049 u64 offset, ns, elapsed;
99e3e30a 1050 unsigned long flags;
02626b6a 1051 s64 usdiff;
99e3e30a 1052
038f8c11 1053 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1054 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1055 ns = get_kernel_ns();
f38e098f 1056 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1057
1058 /* n.b - signed multiplication and division required */
02626b6a 1059 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1060#ifdef CONFIG_X86_64
02626b6a 1061 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6
ZA		 1062#else
1063 /* do_div() only does unsigned */
1064 asm("idivl %2; xor %%edx, %%edx"
02626b6a
MT		 1065 : "=A"(usdiff)
1066 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1067#endif
02626b6a
MT		 1068 do_div(elapsed, 1000);
1069 usdiff -= elapsed;
1070 if (usdiff < 0)
1071 usdiff = -usdiff;
f38e098f
ZA		 1072
1073 /*
5d3cb0f6
ZA		 1074 * Special case: TSC write with a small delta (1 second) of virtual
1075 * cycle time against real time is interpreted as an attempt to
1076 * synchronize the CPU.
1077 *
1078 * For a reliable TSC, we can match TSC offsets, and for an unstable
1079 * TSC, we add elapsed time in this computation. We could let the
1080 * compensation code attempt to catch up if we fall behind, but
1081 * it's better to try to match offsets from the beginning.
1082 */
02626b6a 1083 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1084 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1085 if (!check_tsc_unstable()) {
e26101b1 1086 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1087 pr_debug("kvm: matched tsc offset for %llu\n", data);
1088 } else {
857e4099 1089 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1090 data += delta;
1091 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1092 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1093 }
e26101b1
ZA		 1094 } else {
1095 /*
1096 * We split periods of matched TSC writes into generations.
1097 * For each generation, we track the original measured
1098 * nanosecond time, offset, and write, so if TSCs are in
1099 * sync, we can match exact offset, and if not, we can match
4a969980 1100 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1101 *
1102 * These values are tracked in kvm->arch.cur_xxx variables.
1103 */
1104 kvm->arch.cur_tsc_generation++;
1105 kvm->arch.cur_tsc_nsec = ns;
1106 kvm->arch.cur_tsc_write = data;
1107 kvm->arch.cur_tsc_offset = offset;
1108 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1109 kvm->arch.cur_tsc_generation, data);
f38e098f 1110 }
e26101b1
ZA		 1111
1112 /*
1113 * We also track th most recent recorded KHZ, write and time to
1114 * allow the matching interval to be extended at each write.
1115 */
f38e098f
ZA		 1116 kvm->arch.last_tsc_nsec = ns;
1117 kvm->arch.last_tsc_write = data;
5d3cb0f6 1118 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1119
1120 /* Reset of TSC must disable overshoot protection below */
1121 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1122 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1123
1124 /* Keep track of which generation this VCPU has synchronized to */
1125 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1126 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1127 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1128
1129 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1130 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a 1131}
e26101b1 1132
99e3e30a
ZA		 1133EXPORT_SYMBOL_GPL(kvm_write_tsc);
1134
34c238a1 1135static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1136{
18068523
GOC		 1137 unsigned long flags;
1138 struct kvm_vcpu_arch *vcpu = &v->arch;
1139 void *shared_kaddr;
463656c0 1140 unsigned long this_tsc_khz;
1d5f066e
ZA		 1141 s64 kernel_ns, max_kernel_ns;
1142 u64 tsc_timestamp;
18068523 1143
18068523
GOC		 1144 /* Keep irq disabled to prevent changes to the clock */
1145 local_irq_save(flags);
d5c1785d 1146 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1147 kernel_ns = get_kernel_ns();
cc578287 1148 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1149 if (unlikely(this_tsc_khz == 0)) {
c285545f 1150 local_irq_restore(flags);
34c238a1 1151 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1152 return 1;
1153 }
18068523 1154
c285545f
ZA		 1155 /*
1156 * We may have to catch up the TSC to match elapsed wall clock
1157 * time for two reasons, even if kvmclock is used.
1158 * 1) CPU could have been running below the maximum TSC rate
1159 * 2) Broken TSC compensation resets the base at each VCPU
1160 * entry to avoid unknown leaps of TSC even when running
1161 * again on the same CPU. This may cause apparent elapsed
1162 * time to disappear, and the guest to stand still or run
1163 * very slowly.
1164 */
1165 if (vcpu->tsc_catchup) {
1166 u64 tsc = compute_guest_tsc(v, kernel_ns);
1167 if (tsc > tsc_timestamp) {
f1e2b260 1168 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1169 tsc_timestamp = tsc;
1170 }
50d0a0f9
GH		 1171 }
1172
18068523
GOC		 1173 local_irq_restore(flags);
1174
c285545f
ZA		 1175 if (!vcpu->time_page)
1176 return 0;
18068523 1177
1d5f066e
ZA		 1178 /*
1179 * Time as measured by the TSC may go backwards when resetting the base
1180 * tsc_timestamp. The reason for this is that the TSC resolution is
1181 * higher than the resolution of the other clock scales. Thus, many
1182 * possible measurments of the TSC correspond to one measurement of any
1183 * other clock, and so a spread of values is possible. This is not a
1184 * problem for the computation of the nanosecond clock; with TSC rates
1185 * around 1GHZ, there can only be a few cycles which correspond to one
1186 * nanosecond value, and any path through this code will inevitably
1187 * take longer than that. However, with the kernel_ns value itself,
1188 * the precision may be much lower, down to HZ granularity. If the
1189 * first sampling of TSC against kernel_ns ends in the low part of the
1190 * range, and the second in the high end of the range, we can get:
1191 *
1192 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1193 *
1194 * As the sampling errors potentially range in the thousands of cycles,
1195 * it is possible such a time value has already been observed by the
1196 * guest. To protect against this, we must compute the system time as
1197 * observed by the guest and ensure the new system time is greater.
1198 */
1199 max_kernel_ns = 0;
b183aa58 1200 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1201 max_kernel_ns = vcpu->last_guest_tsc -
1202 vcpu->hv_clock.tsc_timestamp;
1203 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1204 vcpu->hv_clock.tsc_to_system_mul,
1205 vcpu->hv_clock.tsc_shift);
1206 max_kernel_ns += vcpu->last_kernel_ns;
1207 }
afbcf7ab 1208
e48672fa 1209 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1210 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1211 &vcpu->hv_clock.tsc_shift,
1212 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1213 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1214 }
1215
1d5f066e
ZA		 1216 if (max_kernel_ns > kernel_ns)
1217 kernel_ns = max_kernel_ns;
1218
8cfdc000 1219 /* With all the info we got, fill in the values */
1d5f066e 1220 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1221 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1222 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1223 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1224 vcpu->hv_clock.flags = 0;
1225
18068523
GOC		 1226 /*
1227 * The interface expects us to write an even number signaling that the
1228 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1229 * state, we just increase by 2 at the end.
18068523 1230 */
50d0a0f9 1231 vcpu->hv_clock.version += 2;
18068523 1232
8fd75e12 1233 shared_kaddr = kmap_atomic(vcpu->time_page);
18068523
GOC		 1234
1235 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1236 sizeof(vcpu->hv_clock));
18068523 1237
8fd75e12 1238 kunmap_atomic(shared_kaddr);
18068523
GOC		 1239
1240 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1241 return 0;
c8076604
GH		 1242}
1243
9ba075a6
AK		 1244static bool msr_mtrr_valid(unsigned msr)
1245{
1246 switch (msr) {
1247 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1248 case MSR_MTRRfix64K_00000:
1249 case MSR_MTRRfix16K_80000:
1250 case MSR_MTRRfix16K_A0000:
1251 case MSR_MTRRfix4K_C0000:
1252 case MSR_MTRRfix4K_C8000:
1253 case MSR_MTRRfix4K_D0000:
1254 case MSR_MTRRfix4K_D8000:
1255 case MSR_MTRRfix4K_E0000:
1256 case MSR_MTRRfix4K_E8000:
1257 case MSR_MTRRfix4K_F0000:
1258 case MSR_MTRRfix4K_F8000:
1259 case MSR_MTRRdefType:
1260 case MSR_IA32_CR_PAT:
1261 return true;
1262 case 0x2f8:
1263 return true;
1264 }
1265 return false;
1266}
1267
d6289b93
MT		 1268static bool valid_pat_type(unsigned t)
1269{
1270 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1271}
1272
1273static bool valid_mtrr_type(unsigned t)
1274{
1275 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1276}
1277
1278static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1279{
1280 int i;
1281
1282 if (!msr_mtrr_valid(msr))
1283 return false;
1284
1285 if (msr == MSR_IA32_CR_PAT) {
1286 for (i = 0; i < 8; i++)
1287 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1288 return false;
1289 return true;
1290 } else if (msr == MSR_MTRRdefType) {
1291 if (data & ~0xcff)
1292 return false;
1293 return valid_mtrr_type(data & 0xff);
1294 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1295 for (i = 0; i < 8 ; i++)
1296 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1297 return false;
1298 return true;
1299 }
1300
1301 /* variable MTRRs */
1302 return valid_mtrr_type(data & 0xff);
1303}
1304
9ba075a6
AK		 1305static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1306{
0bed3b56
SY		 1307 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1308
d6289b93 1309 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1310 return 1;
1311
0bed3b56
SY		 1312 if (msr == MSR_MTRRdefType) {
1313 vcpu->arch.mtrr_state.def_type = data;
1314 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1315 } else if (msr == MSR_MTRRfix64K_00000)
1316 p[0] = data;
1317 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1318 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1319 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1320 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1321 else if (msr == MSR_IA32_CR_PAT)
1322 vcpu->arch.pat = data;
1323 else { /* Variable MTRRs */
1324 int idx, is_mtrr_mask;
1325 u64 *pt;
1326
1327 idx = (msr - 0x200) / 2;
1328 is_mtrr_mask = msr - 0x200 - 2 * idx;
1329 if (!is_mtrr_mask)
1330 pt =
1331 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1332 else
1333 pt =
1334 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1335 *pt = data;
1336 }
1337
1338 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1339 return 0;
1340}
15c4a640 1341
890ca9ae 1342static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1343{
890ca9ae
HY		 1344 u64 mcg_cap = vcpu->arch.mcg_cap;
1345 unsigned bank_num = mcg_cap & 0xff;
1346
15c4a640 1347 switch (msr) {
15c4a640 1348 case MSR_IA32_MCG_STATUS:
890ca9ae 1349 vcpu->arch.mcg_status = data;
15c4a640 1350 break;
c7ac679c 1351 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1352 if (!(mcg_cap & MCG_CTL_P))
1353 return 1;
1354 if (data != 0 && data != ~(u64)0)
1355 return -1;
1356 vcpu->arch.mcg_ctl = data;
1357 break;
1358 default:
1359 if (msr >= MSR_IA32_MC0_CTL &&
1360 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1361 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1362 /* only 0 or all 1s can be written to IA32_MCi_CTL
1363 * some Linux kernels though clear bit 10 in bank 4 to
1364 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1365 * this to avoid an uncatched #GP in the guest
1366 */
890ca9ae 1367 if ((offset & 0x3) == 0 &&
114be429 1368 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1369 return -1;
1370 vcpu->arch.mce_banks[offset] = data;
1371 break;
1372 }
1373 return 1;
1374 }
1375 return 0;
1376}
1377
ffde22ac
ES		 1378static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1379{
1380 struct kvm *kvm = vcpu->kvm;
1381 int lm = is_long_mode(vcpu);
1382 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1383 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1384 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1385 : kvm->arch.xen_hvm_config.blob_size_32;
1386 u32 page_num = data & ~PAGE_MASK;
1387 u64 page_addr = data & PAGE_MASK;
1388 u8 *page;
1389 int r;
1390
1391 r = -E2BIG;
1392 if (page_num >= blob_size)
1393 goto out;
1394 r = -ENOMEM;
ff5c2c03
SL		 1395 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1396 if (IS_ERR(page)) {
1397 r = PTR_ERR(page);
ffde22ac 1398 goto out;
ff5c2c03 1399 }
ffde22ac
ES		 1400 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1401 goto out_free;
1402 r = 0;
1403out_free:
1404 kfree(page);
1405out:
1406 return r;
1407}
1408
55cd8e5a
GN		 1409static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1410{
1411 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1412}
1413
1414static bool kvm_hv_msr_partition_wide(u32 msr)
1415{
1416 bool r = false;
1417 switch (msr) {
1418 case HV_X64_MSR_GUEST_OS_ID:
1419 case HV_X64_MSR_HYPERCALL:
1420 r = true;
1421 break;
1422 }
1423
1424 return r;
1425}
1426
1427static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1428{
1429 struct kvm *kvm = vcpu->kvm;
1430
1431 switch (msr) {
1432 case HV_X64_MSR_GUEST_OS_ID:
1433 kvm->arch.hv_guest_os_id = data;
1434 /* setting guest os id to zero disables hypercall page */
1435 if (!kvm->arch.hv_guest_os_id)
1436 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1437 break;
1438 case HV_X64_MSR_HYPERCALL: {
1439 u64 gfn;
1440 unsigned long addr;
1441 u8 instructions[4];
1442
1443 /* if guest os id is not set hypercall should remain disabled */
1444 if (!kvm->arch.hv_guest_os_id)
1445 break;
1446 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1447 kvm->arch.hv_hypercall = data;
1448 break;
1449 }
1450 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1451 addr = gfn_to_hva(kvm, gfn);
1452 if (kvm_is_error_hva(addr))
1453 return 1;
1454 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1455 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1456 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1457 return 1;
1458 kvm->arch.hv_hypercall = data;
1459 break;
1460 }
1461 default:
a737f256
CD		 1462 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1463 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1464 return 1;
1465 }
1466 return 0;
1467}
1468
1469static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1470{
10388a07
GN		 1471 switch (msr) {
1472 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1473 unsigned long addr;
55cd8e5a 1474
10388a07
GN		 1475 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1476 vcpu->arch.hv_vapic = data;
1477 break;
1478 }
1479 addr = gfn_to_hva(vcpu->kvm, data >>
1480 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1481 if (kvm_is_error_hva(addr))
1482 return 1;
8b0cedff 1483 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1484 return 1;
1485 vcpu->arch.hv_vapic = data;
1486 break;
1487 }
1488 case HV_X64_MSR_EOI:
1489 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1490 case HV_X64_MSR_ICR:
1491 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1492 case HV_X64_MSR_TPR:
1493 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1494 default:
a737f256
CD		 1495 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1496 "data 0x%llx\n", msr, data);
10388a07
GN		 1497 return 1;
1498 }
1499
1500 return 0;
55cd8e5a
GN		 1501}
1502
344d9588
GN		 1503static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1504{
1505 gpa_t gpa = data & ~0x3f;
1506
4a969980 1507 /* Bits 2:5 are reserved, Should be zero */
6adba527 1508 if (data & 0x3c)
344d9588
GN		 1509 return 1;
1510
1511 vcpu->arch.apf.msr_val = data;
1512
1513 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1514 kvm_clear_async_pf_completion_queue(vcpu);
1515 kvm_async_pf_hash_reset(vcpu);
1516 return 0;
1517 }
1518
1519 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1520 return 1;
1521
6adba527 1522 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1523 kvm_async_pf_wakeup_all(vcpu);
1524 return 0;
1525}
1526
12f9a48f
GC		 1527static void kvmclock_reset(struct kvm_vcpu *vcpu)
1528{
1529 if (vcpu->arch.time_page) {
1530 kvm_release_page_dirty(vcpu->arch.time_page);
1531 vcpu->arch.time_page = NULL;
1532 }
1533}
1534
c9aaa895
GC		 1535static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1536{
1537 u64 delta;
1538
1539 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1540 return;
1541
1542 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1543 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1544 vcpu->arch.st.accum_steal = delta;
1545}
1546
1547static void record_steal_time(struct kvm_vcpu *vcpu)
1548{
1549 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1550 return;
1551
1552 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1553 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1554 return;
1555
1556 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1557 vcpu->arch.st.steal.version += 2;
1558 vcpu->arch.st.accum_steal = 0;
1559
1560 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1561 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1562}
1563
15c4a640
CO		 1564int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1565{
5753785f
GN		 1566 bool pr = false;
1567
15c4a640 1568 switch (msr) {
15c4a640 1569 case MSR_EFER:
b69e8cae 1570 return set_efer(vcpu, data);
8f1589d9
AP		 1571 case MSR_K7_HWCR:
1572 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1573 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1574 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1575 if (data != 0) {
a737f256
CD		 1576 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1577 data);
8f1589d9
AP		 1578 return 1;
1579 }
15c4a640 1580 break;
f7c6d140
AP		 1581 case MSR_FAM10H_MMIO_CONF_BASE:
1582 if (data != 0) {
a737f256
CD		 1583 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1584 "0x%llx\n", data);
f7c6d140
AP		 1585 return 1;
1586 }
15c4a640 1587 break;
c323c0e5 1588 case MSR_AMD64_NB_CFG:
c7ac679c 1589 break;
b5e2fec0
AG		 1590 case MSR_IA32_DEBUGCTLMSR:
1591 if (!data) {
1592 /* We support the non-activated case already */
1593 break;
1594 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1595 /* Values other than LBR and BTF are vendor-specific,
1596 thus reserved and should throw a #GP */
1597 return 1;
1598 }
a737f256
CD		 1599 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1600 __func__, data);
b5e2fec0 1601 break;
15c4a640
CO		 1602 case MSR_IA32_UCODE_REV:
1603 case MSR_IA32_UCODE_WRITE:
61a6bd67 1604 case MSR_VM_HSAVE_PA:
6098ca93 1605 case MSR_AMD64_PATCH_LOADER:
15c4a640 1606 break;
9ba075a6
AK		 1607 case 0x200 ... 0x2ff:
1608 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1609 case MSR_IA32_APICBASE:
1610 kvm_set_apic_base(vcpu, data);
1611 break;
0105d1a5
GN		 1612 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1613 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1614 case MSR_IA32_TSCDEADLINE:
1615 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1616 break;
15c4a640 1617 case MSR_IA32_MISC_ENABLE:
ad312c7c 1618 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1619 break;
11c6bffa 1620 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1621 case MSR_KVM_WALL_CLOCK:
1622 vcpu->kvm->arch.wall_clock = data;
1623 kvm_write_wall_clock(vcpu->kvm, data);
1624 break;
11c6bffa 1625 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1626 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1627 kvmclock_reset(vcpu);
18068523
GOC		 1628
1629 vcpu->arch.time = data;
c285545f 1630 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1631
1632 /* we verify if the enable bit is set... */
1633 if (!(data & 1))
1634 break;
1635
1636 /* ...but clean it before doing the actual write */
1637 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1638
18068523
GOC		 1639 vcpu->arch.time_page =
1640 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523 1641
32cad84f 1642 if (is_error_page(vcpu->arch.time_page))
18068523 1643 vcpu->arch.time_page = NULL;
32cad84f 1644
18068523
GOC		 1645 break;
1646 }
344d9588
GN		 1647 case MSR_KVM_ASYNC_PF_EN:
1648 if (kvm_pv_enable_async_pf(vcpu, data))
1649 return 1;
1650 break;
c9aaa895
GC		 1651 case MSR_KVM_STEAL_TIME:
1652
1653 if (unlikely(!sched_info_on()))
1654 return 1;
1655
1656 if (data & KVM_STEAL_RESERVED_MASK)
1657 return 1;
1658
1659 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1660 data & KVM_STEAL_VALID_BITS))
1661 return 1;
1662
1663 vcpu->arch.st.msr_val = data;
1664
1665 if (!(data & KVM_MSR_ENABLED))
1666 break;
1667
1668 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1669
1670 preempt_disable();
1671 accumulate_steal_time(vcpu);
1672 preempt_enable();
1673
1674 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1675
1676 break;
ae7a2a3f
MT		 1677 case MSR_KVM_PV_EOI_EN:
1678 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1679 return 1;
1680 break;
c9aaa895 1681
890ca9ae
HY		 1682 case MSR_IA32_MCG_CTL:
1683 case MSR_IA32_MCG_STATUS:
1684 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1685 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1686
1687 /* Performance counters are not protected by a CPUID bit,
1688 * so we should check all of them in the generic path for the sake of
1689 * cross vendor migration.
1690 * Writing a zero into the event select MSRs disables them,
1691 * which we perfectly emulate ;-). Any other value should be at least
1692 * reported, some guests depend on them.
1693 */
71db6023
AP		 1694 case MSR_K7_EVNTSEL0:
1695 case MSR_K7_EVNTSEL1:
1696 case MSR_K7_EVNTSEL2:
1697 case MSR_K7_EVNTSEL3:
1698 if (data != 0)
a737f256
CD		 1699 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1700 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 1701 break;
1702 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1703 * so we ignore writes to make it happy.
1704 */
71db6023
AP		 1705 case MSR_K7_PERFCTR0:
1706 case MSR_K7_PERFCTR1:
1707 case MSR_K7_PERFCTR2:
1708 case MSR_K7_PERFCTR3:
a737f256
CD		 1709 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1710 "0x%x data 0x%llx\n", msr, data);
71db6023 1711 break;
5753785f
GN		 1712 case MSR_P6_PERFCTR0:
1713 case MSR_P6_PERFCTR1:
1714 pr = true;
1715 case MSR_P6_EVNTSEL0:
1716 case MSR_P6_EVNTSEL1:
1717 if (kvm_pmu_msr(vcpu, msr))
1718 return kvm_pmu_set_msr(vcpu, msr, data);
1719
1720 if (pr || data != 0)
a737f256
CD		 1721 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1722 "0x%x data 0x%llx\n", msr, data);
5753785f 1723 break;
84e0cefa
JS		 1724 case MSR_K7_CLK_CTL:
1725 /*
1726 * Ignore all writes to this no longer documented MSR.
1727 * Writes are only relevant for old K7 processors,
1728 * all pre-dating SVM, but a recommended workaround from
4a969980 1729 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 1730 * affected processor models on the command line, hence
1731 * the need to ignore the workaround.
1732 */
1733 break;
55cd8e5a
GN		 1734 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1735 if (kvm_hv_msr_partition_wide(msr)) {
1736 int r;
1737 mutex_lock(&vcpu->kvm->lock);
1738 r = set_msr_hyperv_pw(vcpu, msr, data);
1739 mutex_unlock(&vcpu->kvm->lock);
1740 return r;
1741 } else
1742 return set_msr_hyperv(vcpu, msr, data);
1743 break;
91c9c3ed 1744 case MSR_IA32_BBL_CR_CTL3:
1745 /* Drop writes to this legacy MSR -- see rdmsr
1746 * counterpart for further detail.
1747 */
a737f256 1748 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 1749 break;
2b036c6b
BO		 1750 case MSR_AMD64_OSVW_ID_LENGTH:
1751 if (!guest_cpuid_has_osvw(vcpu))
1752 return 1;
1753 vcpu->arch.osvw.length = data;
1754 break;
1755 case MSR_AMD64_OSVW_STATUS:
1756 if (!guest_cpuid_has_osvw(vcpu))
1757 return 1;
1758 vcpu->arch.osvw.status = data;
1759 break;
15c4a640 1760 default:
ffde22ac
ES		 1761 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1762 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1763 if (kvm_pmu_msr(vcpu, msr))
1764 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068 1765 if (!ignore_msrs) {
a737f256
CD		 1766 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1767 msr, data);
ed85c068
AP		 1768 return 1;
1769 } else {
a737f256
CD		 1770 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1771 msr, data);
ed85c068
AP		 1772 break;
1773 }
15c4a640
CO		 1774 }
1775 return 0;
1776}
1777EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1778
1779
1780/*
1781 * Reads an msr value (of 'msr_index') into 'pdata'.
1782 * Returns 0 on success, non-0 otherwise.
1783 * Assumes vcpu_load() was already called.
1784 */
1785int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1786{
1787 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1788}
1789
9ba075a6
AK		 1790static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1791{
0bed3b56
SY		 1792 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1793
9ba075a6
AK		 1794 if (!msr_mtrr_valid(msr))
1795 return 1;
1796
0bed3b56
SY		 1797 if (msr == MSR_MTRRdefType)
1798 *pdata = vcpu->arch.mtrr_state.def_type +
1799 (vcpu->arch.mtrr_state.enabled << 10);
1800 else if (msr == MSR_MTRRfix64K_00000)
1801 *pdata = p[0];
1802 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1803 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1804 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1805 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1806 else if (msr == MSR_IA32_CR_PAT)
1807 *pdata = vcpu->arch.pat;
1808 else { /* Variable MTRRs */
1809 int idx, is_mtrr_mask;
1810 u64 *pt;
1811
1812 idx = (msr - 0x200) / 2;
1813 is_mtrr_mask = msr - 0x200 - 2 * idx;
1814 if (!is_mtrr_mask)
1815 pt =
1816 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1817 else
1818 pt =
1819 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1820 *pdata = *pt;
1821 }
1822
9ba075a6
AK		 1823 return 0;
1824}
1825
890ca9ae 1826static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1827{
1828 u64 data;
890ca9ae
HY		 1829 u64 mcg_cap = vcpu->arch.mcg_cap;
1830 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1831
1832 switch (msr) {
15c4a640
CO		 1833 case MSR_IA32_P5_MC_ADDR:
1834 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1835 data = 0;
1836 break;
15c4a640 1837 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1838 data = vcpu->arch.mcg_cap;
1839 break;
c7ac679c 1840 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1841 if (!(mcg_cap & MCG_CTL_P))
1842 return 1;
1843 data = vcpu->arch.mcg_ctl;
1844 break;
1845 case MSR_IA32_MCG_STATUS:
1846 data = vcpu->arch.mcg_status;
1847 break;
1848 default:
1849 if (msr >= MSR_IA32_MC0_CTL &&
1850 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1851 u32 offset = msr - MSR_IA32_MC0_CTL;
1852 data = vcpu->arch.mce_banks[offset];
1853 break;
1854 }
1855 return 1;
1856 }
1857 *pdata = data;
1858 return 0;
1859}
1860
55cd8e5a
GN		 1861static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1862{
1863 u64 data = 0;
1864 struct kvm *kvm = vcpu->kvm;
1865
1866 switch (msr) {
1867 case HV_X64_MSR_GUEST_OS_ID:
1868 data = kvm->arch.hv_guest_os_id;
1869 break;
1870 case HV_X64_MSR_HYPERCALL:
1871 data = kvm->arch.hv_hypercall;
1872 break;
1873 default:
a737f256 1874 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1875 return 1;
1876 }
1877
1878 *pdata = data;
1879 return 0;
1880}
1881
1882static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1883{
1884 u64 data = 0;
1885
1886 switch (msr) {
1887 case HV_X64_MSR_VP_INDEX: {
1888 int r;
1889 struct kvm_vcpu *v;
1890 kvm_for_each_vcpu(r, v, vcpu->kvm)
1891 if (v == vcpu)
1892 data = r;
1893 break;
1894 }
10388a07
GN		 1895 case HV_X64_MSR_EOI:
1896 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1897 case HV_X64_MSR_ICR:
1898 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1899 case HV_X64_MSR_TPR:
1900 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1901 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1902 data = vcpu->arch.hv_vapic;
1903 break;
55cd8e5a 1904 default:
a737f256 1905 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1906 return 1;
1907 }
1908 *pdata = data;
1909 return 0;
1910}
1911
890ca9ae
HY		 1912int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1913{
1914 u64 data;
1915
1916 switch (msr) {
890ca9ae 1917 case MSR_IA32_PLATFORM_ID:
15c4a640 1918 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1919 case MSR_IA32_DEBUGCTLMSR:
1920 case MSR_IA32_LASTBRANCHFROMIP:
1921 case MSR_IA32_LASTBRANCHTOIP:
1922 case MSR_IA32_LASTINTFROMIP:
1923 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1924 case MSR_K8_SYSCFG:
1925 case MSR_K7_HWCR:
61a6bd67 1926 case MSR_VM_HSAVE_PA:
9e699624 1927 case MSR_K7_EVNTSEL0:
1f3ee616 1928 case MSR_K7_PERFCTR0:
1fdbd48c 1929 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1930 case MSR_AMD64_NB_CFG:
f7c6d140 1931 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1932 data = 0;
1933 break;
5753785f
GN		 1934 case MSR_P6_PERFCTR0:
1935 case MSR_P6_PERFCTR1:
1936 case MSR_P6_EVNTSEL0:
1937 case MSR_P6_EVNTSEL1:
1938 if (kvm_pmu_msr(vcpu, msr))
1939 return kvm_pmu_get_msr(vcpu, msr, pdata);
1940 data = 0;
1941 break;
742bc670
MT		 1942 case MSR_IA32_UCODE_REV:
1943 data = 0x100000000ULL;
1944 break;
9ba075a6
AK		 1945 case MSR_MTRRcap:
1946 data = 0x500 | KVM_NR_VAR_MTRR;
1947 break;
1948 case 0x200 ... 0x2ff:
1949 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1950 case 0xcd: /* fsb frequency */
1951 data = 3;
1952 break;
7b914098
JS		 1953 /*
1954 * MSR_EBC_FREQUENCY_ID
1955 * Conservative value valid for even the basic CPU models.
1956 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1957 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1958 * and 266MHz for model 3, or 4. Set Core Clock
1959 * Frequency to System Bus Frequency Ratio to 1 (bits
1960 * 31:24) even though these are only valid for CPU
1961 * models > 2, however guests may end up dividing or
1962 * multiplying by zero otherwise.
1963 */
1964 case MSR_EBC_FREQUENCY_ID:
1965 data = 1 << 24;
1966 break;
15c4a640
CO		 1967 case MSR_IA32_APICBASE:
1968 data = kvm_get_apic_base(vcpu);
1969 break;
0105d1a5
GN		 1970 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1971 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1972 break;
a3e06bbe
LJ		 1973 case MSR_IA32_TSCDEADLINE:
1974 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1975 break;
15c4a640 1976 case MSR_IA32_MISC_ENABLE:
ad312c7c 1977 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1978 break;
847f0ad8
AG		 1979 case MSR_IA32_PERF_STATUS:
1980 /* TSC increment by tick */
1981 data = 1000ULL;
1982 /* CPU multiplier */
1983 data |= (((uint64_t)4ULL) << 40);
1984 break;
15c4a640 1985 case MSR_EFER:
f6801dff 1986 data = vcpu->arch.efer;
15c4a640 1987 break;
18068523 1988 case MSR_KVM_WALL_CLOCK:
11c6bffa 1989 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1990 data = vcpu->kvm->arch.wall_clock;
1991 break;
1992 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1993 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1994 data = vcpu->arch.time;
1995 break;
344d9588
GN		 1996 case MSR_KVM_ASYNC_PF_EN:
1997 data = vcpu->arch.apf.msr_val;
1998 break;
c9aaa895
GC		 1999 case MSR_KVM_STEAL_TIME:
2000 data = vcpu->arch.st.msr_val;
2001 break;
890ca9ae
HY		 2002 case MSR_IA32_P5_MC_ADDR:
2003 case MSR_IA32_P5_MC_TYPE:
2004 case MSR_IA32_MCG_CAP:
2005 case MSR_IA32_MCG_CTL:
2006 case MSR_IA32_MCG_STATUS:
2007 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2008 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2009 case MSR_K7_CLK_CTL:
2010 /*
2011 * Provide expected ramp-up count for K7. All other
2012 * are set to zero, indicating minimum divisors for
2013 * every field.
2014 *
2015 * This prevents guest kernels on AMD host with CPU
2016 * type 6, model 8 and higher from exploding due to
2017 * the rdmsr failing.
2018 */
2019 data = 0x20000000;
2020 break;
55cd8e5a
GN		 2021 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2022 if (kvm_hv_msr_partition_wide(msr)) {
2023 int r;
2024 mutex_lock(&vcpu->kvm->lock);
2025 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2026 mutex_unlock(&vcpu->kvm->lock);
2027 return r;
2028 } else
2029 return get_msr_hyperv(vcpu, msr, pdata);
2030 break;
91c9c3ed 2031 case MSR_IA32_BBL_CR_CTL3:
2032 /* This legacy MSR exists but isn't fully documented in current
2033 * silicon. It is however accessed by winxp in very narrow
2034 * scenarios where it sets bit #19, itself documented as
2035 * a "reserved" bit. Best effort attempt to source coherent
2036 * read data here should the balance of the register be
2037 * interpreted by the guest:
2038 *
2039 * L2 cache control register 3: 64GB range, 256KB size,
2040 * enabled, latency 0x1, configured
2041 */
2042 data = 0xbe702111;
2043 break;
2b036c6b
BO		 2044 case MSR_AMD64_OSVW_ID_LENGTH:
2045 if (!guest_cpuid_has_osvw(vcpu))
2046 return 1;
2047 data = vcpu->arch.osvw.length;
2048 break;
2049 case MSR_AMD64_OSVW_STATUS:
2050 if (!guest_cpuid_has_osvw(vcpu))
2051 return 1;
2052 data = vcpu->arch.osvw.status;
2053 break;
15c4a640 2054 default:
f5132b01
GN		 2055 if (kvm_pmu_msr(vcpu, msr))
2056 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2057 if (!ignore_msrs) {
a737f256 2058 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2059 return 1;
2060 } else {
a737f256 2061 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2062 data = 0;
2063 }
2064 break;
15c4a640
CO		 2065 }
2066 *pdata = data;
2067 return 0;
2068}
2069EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2070
313a3dc7
CO		 2071/*
2072 * Read or write a bunch of msrs. All parameters are kernel addresses.
2073 *
2074 * @return number of msrs set successfully.
2075 */
2076static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2077 struct kvm_msr_entry *entries,
2078 int (*do_msr)(struct kvm_vcpu *vcpu,
2079 unsigned index, u64 *data))
2080{
f656ce01 2081 int i, idx;
313a3dc7 2082
f656ce01 2083 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2084 for (i = 0; i < msrs->nmsrs; ++i)
2085 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2086 break;
f656ce01 2087 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2088
313a3dc7
CO		 2089 return i;
2090}
2091
2092/*
2093 * Read or write a bunch of msrs. Parameters are user addresses.
2094 *
2095 * @return number of msrs set successfully.
2096 */
2097static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2098 int (*do_msr)(struct kvm_vcpu *vcpu,
2099 unsigned index, u64 *data),
2100 int writeback)
2101{
2102 struct kvm_msrs msrs;
2103 struct kvm_msr_entry *entries;
2104 int r, n;
2105 unsigned size;
2106
2107 r = -EFAULT;
2108 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2109 goto out;
2110
2111 r = -E2BIG;
2112 if (msrs.nmsrs >= MAX_IO_MSRS)
2113 goto out;
2114
313a3dc7 2115 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2116 entries = memdup_user(user_msrs->entries, size);
2117 if (IS_ERR(entries)) {
2118 r = PTR_ERR(entries);
313a3dc7 2119 goto out;
ff5c2c03 2120 }
313a3dc7
CO		 2121
2122 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2123 if (r < 0)
2124 goto out_free;
2125
2126 r = -EFAULT;
2127 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2128 goto out_free;
2129
2130 r = n;
2131
2132out_free:
7a73c028 2133 kfree(entries);
313a3dc7
CO		 2134out:
2135 return r;
2136}
2137
018d00d2
ZX		 2138int kvm_dev_ioctl_check_extension(long ext)
2139{
2140 int r;
2141
2142 switch (ext) {
2143 case KVM_CAP_IRQCHIP:
2144 case KVM_CAP_HLT:
2145 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2146 case KVM_CAP_SET_TSS_ADDR:
07716717 2147 case KVM_CAP_EXT_CPUID:
c8076604 2148 case KVM_CAP_CLOCKSOURCE:
7837699f 2149 case KVM_CAP_PIT:
a28e4f5a 2150 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2151 case KVM_CAP_MP_STATE:
ed848624 2152 case KVM_CAP_SYNC_MMU:
a355c85c 2153 case KVM_CAP_USER_NMI:
52d939a0 2154 case KVM_CAP_REINJECT_CONTROL:
4925663a 2155 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2156 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2157 case KVM_CAP_IRQFD:
d34e6b17 2158 case KVM_CAP_IOEVENTFD:
c5ff41ce 2159 case KVM_CAP_PIT2:
e9f42757 2160 case KVM_CAP_PIT_STATE2:
b927a3ce 2161 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2162 case KVM_CAP_XEN_HVM:
afbcf7ab 2163 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2164 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2165 case KVM_CAP_HYPERV:
10388a07 2166 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2167 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2168 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2169 case KVM_CAP_DEBUGREGS:
d2be1651 2170 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2171 case KVM_CAP_XSAVE:
344d9588 2172 case KVM_CAP_ASYNC_PF:
92a1f12d 2173 case KVM_CAP_GET_TSC_KHZ:
07700a94 2174 case KVM_CAP_PCI_2_3:
1c0b28c2 2175 case KVM_CAP_KVMCLOCK_CTRL:
018d00d2
ZX		 2176 r = 1;
2177 break;
542472b5
LV		 2178 case KVM_CAP_COALESCED_MMIO:
2179 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2180 break;
774ead3a
AK		 2181 case KVM_CAP_VAPIC:
2182 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2183 break;
f725230a 2184 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2185 r = KVM_SOFT_MAX_VCPUS;
2186 break;
2187 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2188 r = KVM_MAX_VCPUS;
2189 break;
a988b910
AK		 2190 case KVM_CAP_NR_MEMSLOTS:
2191 r = KVM_MEMORY_SLOTS;
2192 break;
a68a6a72
MT		 2193 case KVM_CAP_PV_MMU: /* obsolete */
2194 r = 0;
2f333bcb 2195 break;
62c476c7 2196 case KVM_CAP_IOMMU:
a1b60c1c 2197 r = iommu_present(&pci_bus_type);
62c476c7 2198 break;
890ca9ae
HY		 2199 case KVM_CAP_MCE:
2200 r = KVM_MAX_MCE_BANKS;
2201 break;
2d5b5a66
SY		 2202 case KVM_CAP_XCRS:
2203 r = cpu_has_xsave;
2204 break;
92a1f12d
JR		 2205 case KVM_CAP_TSC_CONTROL:
2206 r = kvm_has_tsc_control;
2207 break;
4d25a066
JK		 2208 case KVM_CAP_TSC_DEADLINE_TIMER:
2209 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2210 break;
018d00d2
ZX		 2211 default:
2212 r = 0;
2213 break;
2214 }
2215 return r;
2216
2217}
2218
043405e1
CO		 2219long kvm_arch_dev_ioctl(struct file *filp,
2220 unsigned int ioctl, unsigned long arg)
2221{
2222 void __user *argp = (void __user *)arg;
2223 long r;
2224
2225 switch (ioctl) {
2226 case KVM_GET_MSR_INDEX_LIST: {
2227 struct kvm_msr_list __user *user_msr_list = argp;
2228 struct kvm_msr_list msr_list;
2229 unsigned n;
2230
2231 r = -EFAULT;
2232 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2233 goto out;
2234 n = msr_list.nmsrs;
2235 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2236 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2237 goto out;
2238 r = -E2BIG;
e125e7b6 2239 if (n < msr_list.nmsrs)
043405e1
CO		 2240 goto out;
2241 r = -EFAULT;
2242 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2243 num_msrs_to_save * sizeof(u32)))
2244 goto out;
e125e7b6 2245 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2246 &emulated_msrs,
2247 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2248 goto out;
2249 r = 0;
2250 break;
2251 }
674eea0f
AK		 2252 case KVM_GET_SUPPORTED_CPUID: {
2253 struct kvm_cpuid2 __user *cpuid_arg = argp;
2254 struct kvm_cpuid2 cpuid;
2255
2256 r = -EFAULT;
2257 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2258 goto out;
2259 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2260 cpuid_arg->entries);
674eea0f
AK		 2261 if (r)
2262 goto out;
2263
2264 r = -EFAULT;
2265 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2266 goto out;
2267 r = 0;
2268 break;
2269 }
890ca9ae
HY		 2270 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2271 u64 mce_cap;
2272
2273 mce_cap = KVM_MCE_CAP_SUPPORTED;
2274 r = -EFAULT;
2275 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2276 goto out;
2277 r = 0;
2278 break;
2279 }
043405e1
CO		 2280 default:
2281 r = -EINVAL;
2282 }
2283out:
2284 return r;
2285}
2286
f5f48ee1
SY		 2287static void wbinvd_ipi(void *garbage)
2288{
2289 wbinvd();
2290}
2291
2292static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2293{
2294 return vcpu->kvm->arch.iommu_domain &&
2295 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2296}
2297
313a3dc7
CO		 2298void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2299{
f5f48ee1
SY		 2300 /* Address WBINVD may be executed by guest */
2301 if (need_emulate_wbinvd(vcpu)) {
2302 if (kvm_x86_ops->has_wbinvd_exit())
2303 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2304 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2305 smp_call_function_single(vcpu->cpu,
2306 wbinvd_ipi, NULL, 1);
2307 }
2308
313a3dc7 2309 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2310
0dd6a6ed
ZA		 2311 /* Apply any externally detected TSC adjustments (due to suspend) */
2312 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2313 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2314 vcpu->arch.tsc_offset_adjustment = 0;
2315 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2316 }
8f6055cb 2317
48434c20 2318 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2319 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2320 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2321 if (tsc_delta < 0)
2322 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2323 if (check_tsc_unstable()) {
b183aa58
ZA		 2324 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2325 vcpu->arch.last_guest_tsc);
2326 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2327 vcpu->arch.tsc_catchup = 1;
c285545f 2328 }
1aa8ceef 2329 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2330 if (vcpu->cpu != cpu)
2331 kvm_migrate_timers(vcpu);
e48672fa 2332 vcpu->cpu = cpu;
6b7d7e76 2333 }
c9aaa895
GC		 2334
2335 accumulate_steal_time(vcpu);
2336 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2337}
2338
2339void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2340{
02daab21 2341 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2342 kvm_put_guest_fpu(vcpu);
6f526ec5 2343 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2344}
2345
313a3dc7
CO		 2346static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2347 struct kvm_lapic_state *s)
2348{
ad312c7c 2349 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2350
2351 return 0;
2352}
2353
2354static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2355 struct kvm_lapic_state *s)
2356{
ad312c7c 2357 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2358 kvm_apic_post_state_restore(vcpu);
cb142eb7 2359 update_cr8_intercept(vcpu);
313a3dc7
CO		 2360
2361 return 0;
2362}
2363
f77bc6a4
ZX		 2364static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2365 struct kvm_interrupt *irq)
2366{
2367 if (irq->irq < 0 || irq->irq >= 256)
2368 return -EINVAL;
2369 if (irqchip_in_kernel(vcpu->kvm))
2370 return -ENXIO;
f77bc6a4 2371
66fd3f7f 2372 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2373 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2374
f77bc6a4
ZX		 2375 return 0;
2376}
2377
c4abb7c9
JK		 2378static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2379{
c4abb7c9 2380 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2381
2382 return 0;
2383}
2384
b209749f
AK		 2385static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2386 struct kvm_tpr_access_ctl *tac)
2387{
2388 if (tac->flags)
2389 return -EINVAL;
2390 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2391 return 0;
2392}
2393
890ca9ae
HY		 2394static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2395 u64 mcg_cap)
2396{
2397 int r;
2398 unsigned bank_num = mcg_cap & 0xff, bank;
2399
2400 r = -EINVAL;
a9e38c3e 2401 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2402 goto out;
2403 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2404 goto out;
2405 r = 0;
2406 vcpu->arch.mcg_cap = mcg_cap;
2407 /* Init IA32_MCG_CTL to all 1s */
2408 if (mcg_cap & MCG_CTL_P)
2409 vcpu->arch.mcg_ctl = ~(u64)0;
2410 /* Init IA32_MCi_CTL to all 1s */
2411 for (bank = 0; bank < bank_num; bank++)
2412 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2413out:
2414 return r;
2415}
2416
2417static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2418 struct kvm_x86_mce *mce)
2419{
2420 u64 mcg_cap = vcpu->arch.mcg_cap;
2421 unsigned bank_num = mcg_cap & 0xff;
2422 u64 *banks = vcpu->arch.mce_banks;
2423
2424 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2425 return -EINVAL;
2426 /*
2427 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2428 * reporting is disabled
2429 */
2430 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2431 vcpu->arch.mcg_ctl != ~(u64)0)
2432 return 0;
2433 banks += 4 * mce->bank;
2434 /*
2435 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2436 * reporting is disabled for the bank
2437 */
2438 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2439 return 0;
2440 if (mce->status & MCI_STATUS_UC) {
2441 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2442 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2443 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2444 return 0;
2445 }
2446 if (banks[1] & MCI_STATUS_VAL)
2447 mce->status |= MCI_STATUS_OVER;
2448 banks[2] = mce->addr;
2449 banks[3] = mce->misc;
2450 vcpu->arch.mcg_status = mce->mcg_status;
2451 banks[1] = mce->status;
2452 kvm_queue_exception(vcpu, MC_VECTOR);
2453 } else if (!(banks[1] & MCI_STATUS_VAL)
2454 || !(banks[1] & MCI_STATUS_UC)) {
2455 if (banks[1] & MCI_STATUS_VAL)
2456 mce->status |= MCI_STATUS_OVER;
2457 banks[2] = mce->addr;
2458 banks[3] = mce->misc;
2459 banks[1] = mce->status;
2460 } else
2461 banks[1] |= MCI_STATUS_OVER;
2462 return 0;
2463}
2464
3cfc3092
JK		 2465static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2466 struct kvm_vcpu_events *events)
2467{
7460fb4a 2468 process_nmi(vcpu);
03b82a30
JK		 2469 events->exception.injected =
2470 vcpu->arch.exception.pending &&
2471 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2472 events->exception.nr = vcpu->arch.exception.nr;
2473 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2474 events->exception.pad = 0;
3cfc3092
JK		 2475 events->exception.error_code = vcpu->arch.exception.error_code;
2476
03b82a30
JK		 2477 events->interrupt.injected =
2478 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2479 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2480 events->interrupt.soft = 0;
48005f64
JK		 2481 events->interrupt.shadow =
2482 kvm_x86_ops->get_interrupt_shadow(vcpu,
2483 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2484
2485 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2486 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2487 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2488 events->nmi.pad = 0;
3cfc3092
JK		 2489
2490 events->sipi_vector = vcpu->arch.sipi_vector;
2491
dab4b911 2492 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2493 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2494 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2495 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2496}
2497
2498static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2499 struct kvm_vcpu_events *events)
2500{
dab4b911 2501 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2502 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2503 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2504 return -EINVAL;
2505
7460fb4a 2506 process_nmi(vcpu);
3cfc3092
JK		 2507 vcpu->arch.exception.pending = events->exception.injected;
2508 vcpu->arch.exception.nr = events->exception.nr;
2509 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2510 vcpu->arch.exception.error_code = events->exception.error_code;
2511
2512 vcpu->arch.interrupt.pending = events->interrupt.injected;
2513 vcpu->arch.interrupt.nr = events->interrupt.nr;
2514 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2515 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2516 kvm_x86_ops->set_interrupt_shadow(vcpu,
2517 events->interrupt.shadow);
3cfc3092
JK		 2518
2519 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2520 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2521 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2522 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2523
dab4b911
JK		 2524 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2525 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2526
3842d135
AK		 2527 kvm_make_request(KVM_REQ_EVENT, vcpu);
2528
3cfc3092
JK		 2529 return 0;
2530}
2531
a1efbe77
JK		 2532static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2533 struct kvm_debugregs *dbgregs)
2534{
a1efbe77
JK		 2535 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2536 dbgregs->dr6 = vcpu->arch.dr6;
2537 dbgregs->dr7 = vcpu->arch.dr7;
2538 dbgregs->flags = 0;
97e69aa6 2539 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2540}
2541
2542static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2543 struct kvm_debugregs *dbgregs)
2544{
2545 if (dbgregs->flags)
2546 return -EINVAL;
2547
a1efbe77
JK		 2548 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2549 vcpu->arch.dr6 = dbgregs->dr6;
2550 vcpu->arch.dr7 = dbgregs->dr7;
2551
a1efbe77
JK		 2552 return 0;
2553}
2554
2d5b5a66
SY		 2555static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2556 struct kvm_xsave *guest_xsave)
2557{
2558 if (cpu_has_xsave)
2559 memcpy(guest_xsave->region,
2560 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2561 xstate_size);
2d5b5a66
SY		 2562 else {
2563 memcpy(guest_xsave->region,
2564 &vcpu->arch.guest_fpu.state->fxsave,
2565 sizeof(struct i387_fxsave_struct));
2566 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2567 XSTATE_FPSSE;
2568 }
2569}
2570
2571static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2572 struct kvm_xsave *guest_xsave)
2573{
2574 u64 xstate_bv =
2575 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2576
2577 if (cpu_has_xsave)
2578 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2579 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2580 else {
2581 if (xstate_bv & ~XSTATE_FPSSE)
2582 return -EINVAL;
2583 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2584 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2585 }
2586 return 0;
2587}
2588
2589static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2590 struct kvm_xcrs *guest_xcrs)
2591{
2592 if (!cpu_has_xsave) {
2593 guest_xcrs->nr_xcrs = 0;
2594 return;
2595 }
2596
2597 guest_xcrs->nr_xcrs = 1;
2598 guest_xcrs->flags = 0;
2599 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2600 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2601}
2602
2603static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2604 struct kvm_xcrs *guest_xcrs)
2605{
2606 int i, r = 0;
2607
2608 if (!cpu_has_xsave)
2609 return -EINVAL;
2610
2611 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2612 return -EINVAL;
2613
2614 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2615 /* Only support XCR0 currently */
2616 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2617 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2618 guest_xcrs->xcrs[0].value);
2619 break;
2620 }
2621 if (r)
2622 r = -EINVAL;
2623 return r;
2624}
2625
1c0b28c2
EM		 2626/*
2627 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2628 * stopped by the hypervisor. This function will be called from the host only.
2629 * EINVAL is returned when the host attempts to set the flag for a guest that
2630 * does not support pv clocks.
2631 */
2632static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2633{
2634 struct pvclock_vcpu_time_info *src = &vcpu->arch.hv_clock;
2635 if (!vcpu->arch.time_page)
2636 return -EINVAL;
2637 src->flags |= PVCLOCK_GUEST_STOPPED;
1c0b28c2
EM		 2638 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2639 return 0;
2640}
2641
313a3dc7
CO		 2642long kvm_arch_vcpu_ioctl(struct file *filp,
2643 unsigned int ioctl, unsigned long arg)
2644{
2645 struct kvm_vcpu *vcpu = filp->private_data;
2646 void __user *argp = (void __user *)arg;
2647 int r;
d1ac91d8
AK		 2648 union {
2649 struct kvm_lapic_state *lapic;
2650 struct kvm_xsave *xsave;
2651 struct kvm_xcrs *xcrs;
2652 void *buffer;
2653 } u;
2654
2655 u.buffer = NULL;
313a3dc7
CO		 2656 switch (ioctl) {
2657 case KVM_GET_LAPIC: {
2204ae3c
MT		 2658 r = -EINVAL;
2659 if (!vcpu->arch.apic)
2660 goto out;
d1ac91d8 2661 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2662
b772ff36 2663 r = -ENOMEM;
d1ac91d8 2664 if (!u.lapic)
b772ff36 2665 goto out;
d1ac91d8 2666 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2667 if (r)
2668 goto out;
2669 r = -EFAULT;
d1ac91d8 2670 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2671 goto out;
2672 r = 0;
2673 break;
2674 }
2675 case KVM_SET_LAPIC: {
2204ae3c
MT		 2676 r = -EINVAL;
2677 if (!vcpu->arch.apic)
2678 goto out;
ff5c2c03
SL		 2679 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2680 if (IS_ERR(u.lapic)) {
2681 r = PTR_ERR(u.lapic);
313a3dc7 2682 goto out;
ff5c2c03
SL		 2683 }
2684
d1ac91d8 2685 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2686 if (r)
2687 goto out;
2688 r = 0;
2689 break;
2690 }
f77bc6a4
ZX		 2691 case KVM_INTERRUPT: {
2692 struct kvm_interrupt irq;
2693
2694 r = -EFAULT;
2695 if (copy_from_user(&irq, argp, sizeof irq))
2696 goto out;
2697 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2698 if (r)
2699 goto out;
2700 r = 0;
2701 break;
2702 }
c4abb7c9
JK		 2703 case KVM_NMI: {
2704 r = kvm_vcpu_ioctl_nmi(vcpu);
2705 if (r)
2706 goto out;
2707 r = 0;
2708 break;
2709 }
313a3dc7
CO		 2710 case KVM_SET_CPUID: {
2711 struct kvm_cpuid __user *cpuid_arg = argp;
2712 struct kvm_cpuid cpuid;
2713
2714 r = -EFAULT;
2715 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2716 goto out;
2717 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2718 if (r)
2719 goto out;
2720 break;
2721 }
07716717
DK		 2722 case KVM_SET_CPUID2: {
2723 struct kvm_cpuid2 __user *cpuid_arg = argp;
2724 struct kvm_cpuid2 cpuid;
2725
2726 r = -EFAULT;
2727 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2728 goto out;
2729 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2730 cpuid_arg->entries);
07716717
DK		 2731 if (r)
2732 goto out;
2733 break;
2734 }
2735 case KVM_GET_CPUID2: {
2736 struct kvm_cpuid2 __user *cpuid_arg = argp;
2737 struct kvm_cpuid2 cpuid;
2738
2739 r = -EFAULT;
2740 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2741 goto out;
2742 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2743 cpuid_arg->entries);
07716717
DK		 2744 if (r)
2745 goto out;
2746 r = -EFAULT;
2747 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2748 goto out;
2749 r = 0;
2750 break;
2751 }
313a3dc7
CO		 2752 case KVM_GET_MSRS:
2753 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2754 break;
2755 case KVM_SET_MSRS:
2756 r = msr_io(vcpu, argp, do_set_msr, 0);
2757 break;
b209749f
AK		 2758 case KVM_TPR_ACCESS_REPORTING: {
2759 struct kvm_tpr_access_ctl tac;
2760
2761 r = -EFAULT;
2762 if (copy_from_user(&tac, argp, sizeof tac))
2763 goto out;
2764 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2765 if (r)
2766 goto out;
2767 r = -EFAULT;
2768 if (copy_to_user(argp, &tac, sizeof tac))
2769 goto out;
2770 r = 0;
2771 break;
2772 };
b93463aa
AK		 2773 case KVM_SET_VAPIC_ADDR: {
2774 struct kvm_vapic_addr va;
2775
2776 r = -EINVAL;
2777 if (!irqchip_in_kernel(vcpu->kvm))
2778 goto out;
2779 r = -EFAULT;
2780 if (copy_from_user(&va, argp, sizeof va))
2781 goto out;
2782 r = 0;
2783 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2784 break;
2785 }
890ca9ae
HY		 2786 case KVM_X86_SETUP_MCE: {
2787 u64 mcg_cap;
2788
2789 r = -EFAULT;
2790 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2791 goto out;
2792 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2793 break;
2794 }
2795 case KVM_X86_SET_MCE: {
2796 struct kvm_x86_mce mce;
2797
2798 r = -EFAULT;
2799 if (copy_from_user(&mce, argp, sizeof mce))
2800 goto out;
2801 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2802 break;
2803 }
3cfc3092
JK		 2804 case KVM_GET_VCPU_EVENTS: {
2805 struct kvm_vcpu_events events;
2806
2807 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2808
2809 r = -EFAULT;
2810 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2811 break;
2812 r = 0;
2813 break;
2814 }
2815 case KVM_SET_VCPU_EVENTS: {
2816 struct kvm_vcpu_events events;
2817
2818 r = -EFAULT;
2819 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2820 break;
2821
2822 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2823 break;
2824 }
a1efbe77
JK		 2825 case KVM_GET_DEBUGREGS: {
2826 struct kvm_debugregs dbgregs;
2827
2828 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2829
2830 r = -EFAULT;
2831 if (copy_to_user(argp, &dbgregs,
2832 sizeof(struct kvm_debugregs)))
2833 break;
2834 r = 0;
2835 break;
2836 }
2837 case KVM_SET_DEBUGREGS: {
2838 struct kvm_debugregs dbgregs;
2839
2840 r = -EFAULT;
2841 if (copy_from_user(&dbgregs, argp,
2842 sizeof(struct kvm_debugregs)))
2843 break;
2844
2845 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2846 break;
2847 }
2d5b5a66 2848 case KVM_GET_XSAVE: {
d1ac91d8 2849 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2850 r = -ENOMEM;
d1ac91d8 2851 if (!u.xsave)
2d5b5a66
SY		 2852 break;
2853
d1ac91d8 2854 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2855
2856 r = -EFAULT;
d1ac91d8 2857 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2858 break;
2859 r = 0;
2860 break;
2861 }
2862 case KVM_SET_XSAVE: {
ff5c2c03
SL		 2863 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2864 if (IS_ERR(u.xsave)) {
2865 r = PTR_ERR(u.xsave);
2866 goto out;
2867 }
2d5b5a66 2868
d1ac91d8 2869 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2870 break;
2871 }
2872 case KVM_GET_XCRS: {
d1ac91d8 2873 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2874 r = -ENOMEM;
d1ac91d8 2875 if (!u.xcrs)
2d5b5a66
SY		 2876 break;
2877
d1ac91d8 2878 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2879
2880 r = -EFAULT;
d1ac91d8 2881 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2882 sizeof(struct kvm_xcrs)))
2883 break;
2884 r = 0;
2885 break;
2886 }
2887 case KVM_SET_XCRS: {
ff5c2c03
SL		 2888 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2889 if (IS_ERR(u.xcrs)) {
2890 r = PTR_ERR(u.xcrs);
2891 goto out;
2892 }
2d5b5a66 2893
d1ac91d8 2894 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2895 break;
2896 }
92a1f12d
JR		 2897 case KVM_SET_TSC_KHZ: {
2898 u32 user_tsc_khz;
2899
2900 r = -EINVAL;
92a1f12d
JR		 2901 user_tsc_khz = (u32)arg;
2902
2903 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2904 goto out;
2905
cc578287
ZA		 2906 if (user_tsc_khz == 0)
2907 user_tsc_khz = tsc_khz;
2908
2909 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 2910
2911 r = 0;
2912 goto out;
2913 }
2914 case KVM_GET_TSC_KHZ: {
cc578287 2915 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 2916 goto out;
2917 }
1c0b28c2
EM		 2918 case KVM_KVMCLOCK_CTRL: {
2919 r = kvm_set_guest_paused(vcpu);
2920 goto out;
2921 }
313a3dc7
CO		 2922 default:
2923 r = -EINVAL;
2924 }
2925out:
d1ac91d8 2926 kfree(u.buffer);
313a3dc7
CO		 2927 return r;
2928}
2929
5b1c1493
CO		 2930int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2931{
2932 return VM_FAULT_SIGBUS;
2933}
2934
1fe779f8
CO		 2935static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2936{
2937 int ret;
2938
2939 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2940 return -1;
2941 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2942 return ret;
2943}
2944
b927a3ce
SY		 2945static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2946 u64 ident_addr)
2947{
2948 kvm->arch.ept_identity_map_addr = ident_addr;
2949 return 0;
2950}
2951
1fe779f8
CO		 2952static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2953 u32 kvm_nr_mmu_pages)
2954{
2955 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2956 return -EINVAL;
2957
79fac95e 2958 mutex_lock(&kvm->slots_lock);
7c8a83b7 2959 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2960
2961 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2962 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2963
7c8a83b7 2964 spin_unlock(&kvm->mmu_lock);
79fac95e 2965 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2966 return 0;
2967}
2968
2969static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2970{
39de71ec 2971 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2972}
2973
1fe779f8
CO		 2974static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2975{
2976 int r;
2977
2978 r = 0;
2979 switch (chip->chip_id) {
2980 case KVM_IRQCHIP_PIC_MASTER:
2981 memcpy(&chip->chip.pic,
2982 &pic_irqchip(kvm)->pics[0],
2983 sizeof(struct kvm_pic_state));
2984 break;
2985 case KVM_IRQCHIP_PIC_SLAVE:
2986 memcpy(&chip->chip.pic,
2987 &pic_irqchip(kvm)->pics[1],
2988 sizeof(struct kvm_pic_state));
2989 break;
2990 case KVM_IRQCHIP_IOAPIC:
eba0226b 2991 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2992 break;
2993 default:
2994 r = -EINVAL;
2995 break;
2996 }
2997 return r;
2998}
2999
3000static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3001{
3002 int r;
3003
3004 r = 0;
3005 switch (chip->chip_id) {
3006 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3007 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3008 memcpy(&pic_irqchip(kvm)->pics[0],
3009 &chip->chip.pic,
3010 sizeof(struct kvm_pic_state));
f4f51050 3011 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3012 break;
3013 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3014 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3015 memcpy(&pic_irqchip(kvm)->pics[1],
3016 &chip->chip.pic,
3017 sizeof(struct kvm_pic_state));
f4f51050 3018 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3019 break;
3020 case KVM_IRQCHIP_IOAPIC:
eba0226b 3021 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3022 break;
3023 default:
3024 r = -EINVAL;
3025 break;
3026 }
3027 kvm_pic_update_irq(pic_irqchip(kvm));
3028 return r;
3029}
3030
e0f63cb9
SY		 3031static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3032{
3033 int r = 0;
3034
894a9c55 3035 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3036 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3037 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3038 return r;
3039}
3040
3041static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3042{
3043 int r = 0;
3044
894a9c55 3045 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3046 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3047 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3048 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3049 return r;
3050}
3051
3052static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3053{
3054 int r = 0;
3055
3056 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3057 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3058 sizeof(ps->channels));
3059 ps->flags = kvm->arch.vpit->pit_state.flags;
3060 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3061 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3062 return r;
3063}
3064
3065static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3066{
3067 int r = 0, start = 0;
3068 u32 prev_legacy, cur_legacy;
3069 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3070 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3071 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3072 if (!prev_legacy && cur_legacy)
3073 start = 1;
3074 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3075 sizeof(kvm->arch.vpit->pit_state.channels));
3076 kvm->arch.vpit->pit_state.flags = ps->flags;
3077 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3078 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3079 return r;
3080}
3081
52d939a0
MT		 3082static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3083 struct kvm_reinject_control *control)
3084{
3085 if (!kvm->arch.vpit)
3086 return -ENXIO;
894a9c55 3087 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3088 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3089 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3090 return 0;
3091}
3092
95d4c16c 3093/**
60c34612
TY		 3094 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3095 * @kvm: kvm instance
3096 * @log: slot id and address to which we copy the log
95d4c16c 3097 *
60c34612
TY		 3098 * We need to keep it in mind that VCPU threads can write to the bitmap
3099 * concurrently. So, to avoid losing data, we keep the following order for
3100 * each bit:
95d4c16c 3101 *
60c34612
TY		 3102 * 1. Take a snapshot of the bit and clear it if needed.
3103 * 2. Write protect the corresponding page.
3104 * 3. Flush TLB's if needed.
3105 * 4. Copy the snapshot to the userspace.
95d4c16c 3106 *
60c34612
TY		 3107 * Between 2 and 3, the guest may write to the page using the remaining TLB
3108 * entry. This is not a problem because the page will be reported dirty at
3109 * step 4 using the snapshot taken before and step 3 ensures that successive
3110 * writes will be logged for the next call.
5bb064dc 3111 */
60c34612 3112int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3113{
7850ac54 3114 int r;
5bb064dc 3115 struct kvm_memory_slot *memslot;
60c34612
TY		 3116 unsigned long n, i;
3117 unsigned long *dirty_bitmap;
3118 unsigned long *dirty_bitmap_buffer;
3119 bool is_dirty = false;
5bb064dc 3120
79fac95e 3121 mutex_lock(&kvm->slots_lock);
5bb064dc 3122
b050b015
MT		 3123 r = -EINVAL;
3124 if (log->slot >= KVM_MEMORY_SLOTS)
3125 goto out;
3126
28a37544 3127 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3128
3129 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3130 r = -ENOENT;
60c34612 3131 if (!dirty_bitmap)
b050b015
MT		 3132 goto out;
3133
87bf6e7d 3134 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3135
60c34612
TY		 3136 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3137 memset(dirty_bitmap_buffer, 0, n);
b050b015 3138
60c34612 3139 spin_lock(&kvm->mmu_lock);
b050b015 3140
60c34612
TY		 3141 for (i = 0; i < n / sizeof(long); i++) {
3142 unsigned long mask;
3143 gfn_t offset;
cdfca7b3 3144
60c34612
TY		 3145 if (!dirty_bitmap[i])
3146 continue;
b050b015 3147
60c34612 3148 is_dirty = true;
914ebccd 3149
60c34612
TY		 3150 mask = xchg(&dirty_bitmap[i], 0);
3151 dirty_bitmap_buffer[i] = mask;
edde99ce 3152
60c34612
TY		 3153 offset = i * BITS_PER_LONG;
3154 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3155 }
60c34612
TY		 3156 if (is_dirty)
3157 kvm_flush_remote_tlbs(kvm);
3158
3159 spin_unlock(&kvm->mmu_lock);
3160
3161 r = -EFAULT;
3162 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3163 goto out;
b050b015 3164
5bb064dc
ZX		 3165 r = 0;
3166out:
79fac95e 3167 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3168 return r;
3169}
3170
23d43cf9
CD		 3171int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3172{
3173 if (!irqchip_in_kernel(kvm))
3174 return -ENXIO;
3175
3176 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3177 irq_event->irq, irq_event->level);
3178 return 0;
3179}
3180
1fe779f8
CO		 3181long kvm_arch_vm_ioctl(struct file *filp,
3182 unsigned int ioctl, unsigned long arg)
3183{
3184 struct kvm *kvm = filp->private_data;
3185 void __user *argp = (void __user *)arg;
367e1319 3186 int r = -ENOTTY;
f0d66275
DH		 3187 /*
3188 * This union makes it completely explicit to gcc-3.x
3189 * that these two variables' stack usage should be
3190 * combined, not added together.
3191 */
3192 union {
3193 struct kvm_pit_state ps;
e9f42757 3194 struct kvm_pit_state2 ps2;
c5ff41ce 3195 struct kvm_pit_config pit_config;
f0d66275 3196 } u;
1fe779f8
CO		 3197
3198 switch (ioctl) {
3199 case KVM_SET_TSS_ADDR:
3200 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3201 if (r < 0)
3202 goto out;
3203 break;
b927a3ce
SY		 3204 case KVM_SET_IDENTITY_MAP_ADDR: {
3205 u64 ident_addr;
3206
3207 r = -EFAULT;
3208 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3209 goto out;
3210 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3211 if (r < 0)
3212 goto out;
3213 break;
3214 }
1fe779f8
CO		 3215 case KVM_SET_NR_MMU_PAGES:
3216 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3217 if (r)
3218 goto out;
3219 break;
3220 case KVM_GET_NR_MMU_PAGES:
3221 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3222 break;
3ddea128
MT		 3223 case KVM_CREATE_IRQCHIP: {
3224 struct kvm_pic *vpic;
3225
3226 mutex_lock(&kvm->lock);
3227 r = -EEXIST;
3228 if (kvm->arch.vpic)
3229 goto create_irqchip_unlock;
3e515705
AK		 3230 r = -EINVAL;
3231 if (atomic_read(&kvm->online_vcpus))
3232 goto create_irqchip_unlock;
1fe779f8 3233 r = -ENOMEM;
3ddea128
MT		 3234 vpic = kvm_create_pic(kvm);
3235 if (vpic) {
1fe779f8
CO		 3236 r = kvm_ioapic_init(kvm);
3237 if (r) {
175504cd 3238 mutex_lock(&kvm->slots_lock);
72bb2fcd 3239 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3240 &vpic->dev_master);
3241 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3242 &vpic->dev_slave);
3243 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3244 &vpic->dev_eclr);
175504cd 3245 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3246 kfree(vpic);
3247 goto create_irqchip_unlock;
1fe779f8
CO		 3248 }
3249 } else
3ddea128
MT		 3250 goto create_irqchip_unlock;
3251 smp_wmb();
3252 kvm->arch.vpic = vpic;
3253 smp_wmb();
399ec807
AK		 3254 r = kvm_setup_default_irq_routing(kvm);
3255 if (r) {
175504cd 3256 mutex_lock(&kvm->slots_lock);
3ddea128 3257 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3258 kvm_ioapic_destroy(kvm);
3259 kvm_destroy_pic(kvm);
3ddea128 3260 mutex_unlock(&kvm->irq_lock);
175504cd 3261 mutex_unlock(&kvm->slots_lock);
399ec807 3262 }
3ddea128
MT		 3263 create_irqchip_unlock:
3264 mutex_unlock(&kvm->lock);
1fe779f8 3265 break;
3ddea128 3266 }
7837699f 3267 case KVM_CREATE_PIT:
c5ff41ce
JK		 3268 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3269 goto create_pit;
3270 case KVM_CREATE_PIT2:
3271 r = -EFAULT;
3272 if (copy_from_user(&u.pit_config, argp,
3273 sizeof(struct kvm_pit_config)))
3274 goto out;
3275 create_pit:
79fac95e 3276 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3277 r = -EEXIST;
3278 if (kvm->arch.vpit)
3279 goto create_pit_unlock;
7837699f 3280 r = -ENOMEM;
c5ff41ce 3281 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3282 if (kvm->arch.vpit)
3283 r = 0;
269e05e4 3284 create_pit_unlock:
79fac95e 3285 mutex_unlock(&kvm->slots_lock);
7837699f 3286 break;
1fe779f8
CO		 3287 case KVM_GET_IRQCHIP: {
3288 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3289 struct kvm_irqchip *chip;
1fe779f8 3290
ff5c2c03
SL		 3291 chip = memdup_user(argp, sizeof(*chip));
3292 if (IS_ERR(chip)) {
3293 r = PTR_ERR(chip);
1fe779f8 3294 goto out;
ff5c2c03
SL		 3295 }
3296
1fe779f8
CO		 3297 r = -ENXIO;
3298 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3299 goto get_irqchip_out;
3300 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3301 if (r)
f0d66275 3302 goto get_irqchip_out;
1fe779f8 3303 r = -EFAULT;
f0d66275
DH		 3304 if (copy_to_user(argp, chip, sizeof *chip))
3305 goto get_irqchip_out;
1fe779f8 3306 r = 0;
f0d66275
DH		 3307 get_irqchip_out:
3308 kfree(chip);
3309 if (r)
3310 goto out;
1fe779f8
CO		 3311 break;
3312 }
3313 case KVM_SET_IRQCHIP: {
3314 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3315 struct kvm_irqchip *chip;
1fe779f8 3316
ff5c2c03
SL		 3317 chip = memdup_user(argp, sizeof(*chip));
3318 if (IS_ERR(chip)) {
3319 r = PTR_ERR(chip);
1fe779f8 3320 goto out;
ff5c2c03
SL		 3321 }
3322
1fe779f8
CO		 3323 r = -ENXIO;
3324 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3325 goto set_irqchip_out;
3326 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3327 if (r)
f0d66275 3328 goto set_irqchip_out;
1fe779f8 3329 r = 0;
f0d66275
DH		 3330 set_irqchip_out:
3331 kfree(chip);
3332 if (r)
3333 goto out;
1fe779f8
CO		 3334 break;
3335 }
e0f63cb9 3336 case KVM_GET_PIT: {
e0f63cb9 3337 r = -EFAULT;
f0d66275 3338 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3339 goto out;
3340 r = -ENXIO;
3341 if (!kvm->arch.vpit)
3342 goto out;
f0d66275 3343 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3344 if (r)
3345 goto out;
3346 r = -EFAULT;
f0d66275 3347 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3348 goto out;
3349 r = 0;
3350 break;
3351 }
3352 case KVM_SET_PIT: {
e0f63cb9 3353 r = -EFAULT;
f0d66275 3354 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3355 goto out;
3356 r = -ENXIO;
3357 if (!kvm->arch.vpit)
3358 goto out;
f0d66275 3359 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3360 if (r)
3361 goto out;
3362 r = 0;
3363 break;
3364 }
e9f42757
BK		 3365 case KVM_GET_PIT2: {
3366 r = -ENXIO;
3367 if (!kvm->arch.vpit)
3368 goto out;
3369 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3370 if (r)
3371 goto out;
3372 r = -EFAULT;
3373 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3374 goto out;
3375 r = 0;
3376 break;
3377 }
3378 case KVM_SET_PIT2: {
3379 r = -EFAULT;
3380 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3381 goto out;
3382 r = -ENXIO;
3383 if (!kvm->arch.vpit)
3384 goto out;
3385 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3386 if (r)
3387 goto out;
3388 r = 0;
3389 break;
3390 }
52d939a0
MT		 3391 case KVM_REINJECT_CONTROL: {
3392 struct kvm_reinject_control control;
3393 r = -EFAULT;
3394 if (copy_from_user(&control, argp, sizeof(control)))
3395 goto out;
3396 r = kvm_vm_ioctl_reinject(kvm, &control);
3397 if (r)
3398 goto out;
3399 r = 0;
3400 break;
3401 }
ffde22ac
ES		 3402 case KVM_XEN_HVM_CONFIG: {
3403 r = -EFAULT;
3404 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3405 sizeof(struct kvm_xen_hvm_config)))
3406 goto out;
3407 r = -EINVAL;
3408 if (kvm->arch.xen_hvm_config.flags)
3409 goto out;
3410 r = 0;
3411 break;
3412 }
afbcf7ab 3413 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3414 struct kvm_clock_data user_ns;
3415 u64 now_ns;
3416 s64 delta;
3417
3418 r = -EFAULT;
3419 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3420 goto out;
3421
3422 r = -EINVAL;
3423 if (user_ns.flags)
3424 goto out;
3425
3426 r = 0;
395c6b0a 3427 local_irq_disable();
759379dd 3428 now_ns = get_kernel_ns();
afbcf7ab 3429 delta = user_ns.clock - now_ns;
395c6b0a 3430 local_irq_enable();
afbcf7ab
GC		 3431 kvm->arch.kvmclock_offset = delta;
3432 break;
3433 }
3434 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3435 struct kvm_clock_data user_ns;
3436 u64 now_ns;
3437
395c6b0a 3438 local_irq_disable();
759379dd 3439 now_ns = get_kernel_ns();
afbcf7ab 3440 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3441 local_irq_enable();
afbcf7ab 3442 user_ns.flags = 0;
97e69aa6 3443 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3444
3445 r = -EFAULT;
3446 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3447 goto out;
3448 r = 0;
3449 break;
3450 }
3451
1fe779f8
CO		 3452 default:
3453 ;
3454 }
3455out:
3456 return r;
3457}
3458
a16b043c 3459static void kvm_init_msr_list(void)
043405e1
CO		 3460{
3461 u32 dummy[2];
3462 unsigned i, j;
3463
e3267cbb
GC		 3464 /* skip the first msrs in the list. KVM-specific */
3465 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3466 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3467 continue;
3468 if (j < i)
3469 msrs_to_save[j] = msrs_to_save[i];
3470 j++;
3471 }
3472 num_msrs_to_save = j;
3473}
3474
bda9020e
MT		 3475static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3476 const void *v)
bbd9b64e 3477{
70252a10
AK		 3478 int handled = 0;
3479 int n;
3480
3481 do {
3482 n = min(len, 8);
3483 if (!(vcpu->arch.apic &&
3484 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3485 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3486 break;
3487 handled += n;
3488 addr += n;
3489 len -= n;
3490 v += n;
3491 } while (len);
bbd9b64e 3492
70252a10 3493 return handled;
bbd9b64e
CO		 3494}
3495
bda9020e 3496static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3497{
70252a10
AK		 3498 int handled = 0;
3499 int n;
3500
3501 do {
3502 n = min(len, 8);
3503 if (!(vcpu->arch.apic &&
3504 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3505 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3506 break;
3507 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3508 handled += n;
3509 addr += n;
3510 len -= n;
3511 v += n;
3512 } while (len);
bbd9b64e 3513
70252a10 3514 return handled;
bbd9b64e
CO		 3515}
3516
2dafc6c2
GN		 3517static void kvm_set_segment(struct kvm_vcpu *vcpu,
3518 struct kvm_segment *var, int seg)
3519{
3520 kvm_x86_ops->set_segment(vcpu, var, seg);
3521}
3522
3523void kvm_get_segment(struct kvm_vcpu *vcpu,
3524 struct kvm_segment *var, int seg)
3525{
3526 kvm_x86_ops->get_segment(vcpu, var, seg);
3527}
3528
e459e322 3529gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3530{
3531 gpa_t t_gpa;
ab9ae313 3532 struct x86_exception exception;
02f59dc9
JR		 3533
3534 BUG_ON(!mmu_is_nested(vcpu));
3535
3536 /* NPT walks are always user-walks */
3537 access |= PFERR_USER_MASK;
ab9ae313 3538 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3539
3540 return t_gpa;
3541}
3542
ab9ae313
AK		 3543gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3544 struct x86_exception *exception)
1871c602
GN		 3545{
3546 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3547 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3548}
3549
ab9ae313
AK		 3550 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3551 struct x86_exception *exception)
1871c602
GN		 3552{
3553 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3554 access |= PFERR_FETCH_MASK;
ab9ae313 3555 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3556}
3557
ab9ae313
AK		 3558gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3559 struct x86_exception *exception)
1871c602
GN		 3560{
3561 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3562 access |= PFERR_WRITE_MASK;
ab9ae313 3563 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3564}
3565
3566/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3567gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3568 struct x86_exception *exception)
1871c602 3569{
ab9ae313 3570 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3571}
3572
3573static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3574 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3575 struct x86_exception *exception)
bbd9b64e
CO		 3576{
3577 void *data = val;
10589a46 3578 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3579
3580 while (bytes) {
14dfe855 3581 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3582 exception);
bbd9b64e 3583 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3584 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3585 int ret;
3586
bcc55cba 3587 if (gpa == UNMAPPED_GVA)
ab9ae313 3588 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3589 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3590 if (ret < 0) {
c3cd7ffa 3591 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3592 goto out;
3593 }
bbd9b64e 3594
77c2002e
IE		 3595 bytes -= toread;
3596 data += toread;
3597 addr += toread;
bbd9b64e 3598 }
10589a46 3599out:
10589a46 3600 return r;
bbd9b64e 3601}
77c2002e 3602
1871c602 3603/* used for instruction fetching */
0f65dd70
AK		 3604static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3605 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3606 struct x86_exception *exception)
1871c602 3607{
0f65dd70 3608 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3609 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3610
1871c602 3611 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3612 access | PFERR_FETCH_MASK,
3613 exception);
1871c602
GN		 3614}
3615
064aea77 3616int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3617 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3618 struct x86_exception *exception)
1871c602 3619{
0f65dd70 3620 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3621 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3622
1871c602 3623 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3624 exception);
1871c602 3625}
064aea77 3626EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3627
0f65dd70
AK		 3628static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3629 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3630 struct x86_exception *exception)
1871c602 3631{
0f65dd70 3632 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3633 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3634}
3635
6a4d7550 3636int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3637 gva_t addr, void *val,
2dafc6c2 3638 unsigned int bytes,
bcc55cba 3639 struct x86_exception *exception)
77c2002e 3640{
0f65dd70 3641 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3642 void *data = val;
3643 int r = X86EMUL_CONTINUE;
3644
3645 while (bytes) {
14dfe855
JR		 3646 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3647 PFERR_WRITE_MASK,
ab9ae313 3648 exception);
77c2002e
IE		 3649 unsigned offset = addr & (PAGE_SIZE-1);
3650 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3651 int ret;
3652
bcc55cba 3653 if (gpa == UNMAPPED_GVA)
ab9ae313 3654 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3655 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3656 if (ret < 0) {
c3cd7ffa 3657 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3658 goto out;
3659 }
3660
3661 bytes -= towrite;
3662 data += towrite;
3663 addr += towrite;
3664 }
3665out:
3666 return r;
3667}
6a4d7550 3668EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3669
af7cc7d1
XG		 3670static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3671 gpa_t *gpa, struct x86_exception *exception,
3672 bool write)
3673{
3674 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3675
bebb106a
XG		 3676 if (vcpu_match_mmio_gva(vcpu, gva) &&
3677 check_write_user_access(vcpu, write, access,
3678 vcpu->arch.access)) {
3679 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3680 (gva & (PAGE_SIZE - 1));
4f022648 3681 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3682 return 1;
3683 }
3684
af7cc7d1
XG		 3685 if (write)
3686 access |= PFERR_WRITE_MASK;
3687
3688 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3689
3690 if (*gpa == UNMAPPED_GVA)
3691 return -1;
3692
3693 /* For APIC access vmexit */
3694 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3695 return 1;
3696
4f022648
XG		 3697 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3698 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3699 return 1;
4f022648 3700 }
bebb106a 3701
af7cc7d1
XG		 3702 return 0;
3703}
3704
3200f405 3705int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3706 const void *val, int bytes)
bbd9b64e
CO		 3707{
3708 int ret;
3709
3710 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3711 if (ret < 0)
bbd9b64e 3712 return 0;
f57f2ef5 3713 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3714 return 1;
3715}
3716
77d197b2
XG		 3717struct read_write_emulator_ops {
3718 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3719 int bytes);
3720 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3721 void *val, int bytes);
3722 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3723 int bytes, void *val);
3724 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3725 void *val, int bytes);
3726 bool write;
3727};
3728
3729static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3730{
3731 if (vcpu->mmio_read_completed) {
77d197b2 3732 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 3733 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 3734 vcpu->mmio_read_completed = 0;
3735 return 1;
3736 }
3737
3738 return 0;
3739}
3740
3741static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3742 void *val, int bytes)
3743{
3744 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3745}
3746
3747static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3748 void *val, int bytes)
3749{
3750 return emulator_write_phys(vcpu, gpa, val, bytes);
3751}
3752
3753static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3754{
3755 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3756 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3757}
3758
3759static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3760 void *val, int bytes)
3761{
3762 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3763 return X86EMUL_IO_NEEDED;
3764}
3765
3766static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3767 void *val, int bytes)
3768{
f78146b0
AK		 3769 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3770
3771 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
77d197b2
XG		 3772 return X86EMUL_CONTINUE;
3773}
3774
3775static struct read_write_emulator_ops read_emultor = {
3776 .read_write_prepare = read_prepare,
3777 .read_write_emulate = read_emulate,
3778 .read_write_mmio = vcpu_mmio_read,
3779 .read_write_exit_mmio = read_exit_mmio,
3780};
3781
3782static struct read_write_emulator_ops write_emultor = {
3783 .read_write_emulate = write_emulate,
3784 .read_write_mmio = write_mmio,
3785 .read_write_exit_mmio = write_exit_mmio,
3786 .write = true,
3787};
3788
22388a3c
XG		 3789static int emulator_read_write_onepage(unsigned long addr, void *val,
3790 unsigned int bytes,
3791 struct x86_exception *exception,
3792 struct kvm_vcpu *vcpu,
3793 struct read_write_emulator_ops *ops)
bbd9b64e 3794{
af7cc7d1
XG		 3795 gpa_t gpa;
3796 int handled, ret;
22388a3c 3797 bool write = ops->write;
f78146b0 3798 struct kvm_mmio_fragment *frag;
10589a46 3799
22388a3c 3800 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3801
af7cc7d1 3802 if (ret < 0)
bbd9b64e 3803 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3804
3805 /* For APIC access vmexit */
af7cc7d1 3806 if (ret)
bbd9b64e
CO		 3807 goto mmio;
3808
22388a3c 3809 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3810 return X86EMUL_CONTINUE;
3811
3812mmio:
3813 /*
3814 * Is this MMIO handled locally?
3815 */
22388a3c 3816 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3817 if (handled == bytes)
bbd9b64e 3818 return X86EMUL_CONTINUE;
bbd9b64e 3819
70252a10
AK		 3820 gpa += handled;
3821 bytes -= handled;
3822 val += handled;
3823
f78146b0
AK		 3824 while (bytes) {
3825 unsigned now = min(bytes, 8U);
bbd9b64e 3826
f78146b0
AK		 3827 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3828 frag->gpa = gpa;
3829 frag->data = val;
3830 frag->len = now;
3831
3832 gpa += now;
3833 val += now;
3834 bytes -= now;
3835 }
3836 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3837}
3838
22388a3c
XG		 3839int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3840 void *val, unsigned int bytes,
3841 struct x86_exception *exception,
3842 struct read_write_emulator_ops *ops)
bbd9b64e 3843{
0f65dd70 3844 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 3845 gpa_t gpa;
3846 int rc;
3847
3848 if (ops->read_write_prepare &&
3849 ops->read_write_prepare(vcpu, val, bytes))
3850 return X86EMUL_CONTINUE;
3851
3852 vcpu->mmio_nr_fragments = 0;
0f65dd70 3853
bbd9b64e
CO		 3854 /* Crossing a page boundary? */
3855 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 3856 int now;
bbd9b64e
CO		 3857
3858 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3859 rc = emulator_read_write_onepage(addr, val, now, exception,
3860 vcpu, ops);
3861
bbd9b64e
CO		 3862 if (rc != X86EMUL_CONTINUE)
3863 return rc;
3864 addr += now;
3865 val += now;
3866 bytes -= now;
3867 }
22388a3c 3868
f78146b0
AK		 3869 rc = emulator_read_write_onepage(addr, val, bytes, exception,
3870 vcpu, ops);
3871 if (rc != X86EMUL_CONTINUE)
3872 return rc;
3873
3874 if (!vcpu->mmio_nr_fragments)
3875 return rc;
3876
3877 gpa = vcpu->mmio_fragments[0].gpa;
3878
3879 vcpu->mmio_needed = 1;
3880 vcpu->mmio_cur_fragment = 0;
3881
3882 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3883 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3884 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3885 vcpu->run->mmio.phys_addr = gpa;
3886
3887 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 3888}
3889
3890static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3891 unsigned long addr,
3892 void *val,
3893 unsigned int bytes,
3894 struct x86_exception *exception)
3895{
3896 return emulator_read_write(ctxt, addr, val, bytes,
3897 exception, &read_emultor);
3898}
3899
3900int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3901 unsigned long addr,
3902 const void *val,
3903 unsigned int bytes,
3904 struct x86_exception *exception)
3905{
3906 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3907 exception, &write_emultor);
bbd9b64e 3908}
bbd9b64e 3909
daea3e73
AK		 3910#define CMPXCHG_TYPE(t, ptr, old, new) \
3911 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3912
3913#ifdef CONFIG_X86_64
3914# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3915#else
3916# define CMPXCHG64(ptr, old, new) \
9749a6c0 3917 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3918#endif
3919
0f65dd70
AK		 3920static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3921 unsigned long addr,
bbd9b64e
CO		 3922 const void *old,
3923 const void *new,
3924 unsigned int bytes,
0f65dd70 3925 struct x86_exception *exception)
bbd9b64e 3926{
0f65dd70 3927 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3928 gpa_t gpa;
3929 struct page *page;
3930 char *kaddr;
3931 bool exchanged;
2bacc55c 3932
daea3e73
AK		 3933 /* guests cmpxchg8b have to be emulated atomically */
3934 if (bytes > 8 || (bytes & (bytes - 1)))
3935 goto emul_write;
10589a46 3936
daea3e73 3937 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3938
daea3e73
AK		 3939 if (gpa == UNMAPPED_GVA ||
3940 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3941 goto emul_write;
2bacc55c 3942
daea3e73
AK		 3943 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3944 goto emul_write;
72dc67a6 3945
daea3e73 3946 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 3947 if (is_error_page(page))
c19b8bd6 3948 goto emul_write;
72dc67a6 3949
8fd75e12 3950 kaddr = kmap_atomic(page);
daea3e73
AK		 3951 kaddr += offset_in_page(gpa);
3952 switch (bytes) {
3953 case 1:
3954 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3955 break;
3956 case 2:
3957 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3958 break;
3959 case 4:
3960 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3961 break;
3962 case 8:
3963 exchanged = CMPXCHG64(kaddr, old, new);
3964 break;
3965 default:
3966 BUG();
2bacc55c 3967 }
8fd75e12 3968 kunmap_atomic(kaddr);
daea3e73
AK		 3969 kvm_release_page_dirty(page);
3970
3971 if (!exchanged)
3972 return X86EMUL_CMPXCHG_FAILED;
3973
f57f2ef5 3974 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3975
3976 return X86EMUL_CONTINUE;
4a5f48f6 3977
3200f405 3978emul_write:
daea3e73 3979 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3980
0f65dd70 3981 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3982}
3983
cf8f70bf
GN		 3984static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3985{
3986 /* TODO: String I/O for in kernel device */
3987 int r;
3988
3989 if (vcpu->arch.pio.in)
3990 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3991 vcpu->arch.pio.size, pd);
3992 else
3993 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3994 vcpu->arch.pio.port, vcpu->arch.pio.size,
3995 pd);
3996 return r;
3997}
3998
6f6fbe98
XG		 3999static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4000 unsigned short port, void *val,
4001 unsigned int count, bool in)
cf8f70bf 4002{
6f6fbe98 4003 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4004
4005 vcpu->arch.pio.port = port;
6f6fbe98 4006 vcpu->arch.pio.in = in;
7972995b 4007 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4008 vcpu->arch.pio.size = size;
4009
4010 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4011 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4012 return 1;
4013 }
4014
4015 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4016 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4017 vcpu->run->io.size = size;
4018 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4019 vcpu->run->io.count = count;
4020 vcpu->run->io.port = port;
4021
4022 return 0;
4023}
4024
6f6fbe98
XG		 4025static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4026 int size, unsigned short port, void *val,
4027 unsigned int count)
cf8f70bf 4028{
ca1d4a9e 4029 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4030 int ret;
ca1d4a9e 4031
6f6fbe98
XG		 4032 if (vcpu->arch.pio.count)
4033 goto data_avail;
cf8f70bf 4034
6f6fbe98
XG		 4035 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4036 if (ret) {
4037data_avail:
4038 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4039 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4040 return 1;
4041 }
4042
cf8f70bf
GN		 4043 return 0;
4044}
4045
6f6fbe98
XG		 4046static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4047 int size, unsigned short port,
4048 const void *val, unsigned int count)
4049{
4050 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4051
4052 memcpy(vcpu->arch.pio_data, val, size * count);
4053 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4054}
4055
bbd9b64e
CO		 4056static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4057{
4058 return kvm_x86_ops->get_segment_base(vcpu, seg);
4059}
4060
3cb16fe7 4061static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4062{
3cb16fe7 4063 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4064}
4065
f5f48ee1
SY		 4066int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4067{
4068 if (!need_emulate_wbinvd(vcpu))
4069 return X86EMUL_CONTINUE;
4070
4071 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4072 int cpu = get_cpu();
4073
4074 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4075 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4076 wbinvd_ipi, NULL, 1);
2eec7343 4077 put_cpu();
f5f48ee1 4078 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4079 } else
4080 wbinvd();
f5f48ee1
SY		 4081 return X86EMUL_CONTINUE;
4082}
4083EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4084
bcaf5cc5
AK		 4085static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4086{
4087 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4088}
4089
717746e3 4090int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4091{
717746e3 4092 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4093}
4094
717746e3 4095int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4096{
338dbc97 4097
717746e3 4098 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4099}
4100
52a46617 4101static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4102{
52a46617 4103 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4104}
4105
717746e3 4106static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4107{
717746e3 4108 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4109 unsigned long value;
4110
4111 switch (cr) {
4112 case 0:
4113 value = kvm_read_cr0(vcpu);
4114 break;
4115 case 2:
4116 value = vcpu->arch.cr2;
4117 break;
4118 case 3:
9f8fe504 4119 value = kvm_read_cr3(vcpu);
52a46617
GN		 4120 break;
4121 case 4:
4122 value = kvm_read_cr4(vcpu);
4123 break;
4124 case 8:
4125 value = kvm_get_cr8(vcpu);
4126 break;
4127 default:
a737f256 4128 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4129 return 0;
4130 }
4131
4132 return value;
4133}
4134
717746e3 4135static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4136{
717746e3 4137 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4138 int res = 0;
4139
52a46617
GN		 4140 switch (cr) {
4141 case 0:
49a9b07e 4142 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4143 break;
4144 case 2:
4145 vcpu->arch.cr2 = val;
4146 break;
4147 case 3:
2390218b 4148 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4149 break;
4150 case 4:
a83b29c6 4151 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4152 break;
4153 case 8:
eea1cff9 4154 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4155 break;
4156 default:
a737f256 4157 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4158 res = -1;
52a46617 4159 }
0f12244f
GN		 4160
4161 return res;
52a46617
GN		 4162}
4163
4cee4798
KW		 4164static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4165{
4166 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4167}
4168
717746e3 4169static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4170{
717746e3 4171 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4172}
4173
4bff1e86 4174static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4175{
4bff1e86 4176 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4177}
4178
4bff1e86 4179static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4180{
4bff1e86 4181 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4182}
4183
1ac9d0cf
AK		 4184static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4185{
4186 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4187}
4188
4189static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4190{
4191 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4192}
4193
4bff1e86
AK		 4194static unsigned long emulator_get_cached_segment_base(
4195 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4196{
4bff1e86 4197 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4198}
4199
1aa36616
AK		 4200static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4201 struct desc_struct *desc, u32 *base3,
4202 int seg)
2dafc6c2
GN		 4203{
4204 struct kvm_segment var;
4205
4bff1e86 4206 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4207 *selector = var.selector;
2dafc6c2
GN		 4208
4209 if (var.unusable)
4210 return false;
4211
4212 if (var.g)
4213 var.limit >>= 12;
4214 set_desc_limit(desc, var.limit);
4215 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4216#ifdef CONFIG_X86_64
4217 if (base3)
4218 *base3 = var.base >> 32;
4219#endif
2dafc6c2
GN		 4220 desc->type = var.type;
4221 desc->s = var.s;
4222 desc->dpl = var.dpl;
4223 desc->p = var.present;
4224 desc->avl = var.avl;
4225 desc->l = var.l;
4226 desc->d = var.db;
4227 desc->g = var.g;
4228
4229 return true;
4230}
4231
1aa36616
AK		 4232static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4233 struct desc_struct *desc, u32 base3,
4234 int seg)
2dafc6c2 4235{
4bff1e86 4236 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4237 struct kvm_segment var;
4238
1aa36616 4239 var.selector = selector;
2dafc6c2 4240 var.base = get_desc_base(desc);
5601d05b
GN		 4241#ifdef CONFIG_X86_64
4242 var.base |= ((u64)base3) << 32;
4243#endif
2dafc6c2
GN		 4244 var.limit = get_desc_limit(desc);
4245 if (desc->g)
4246 var.limit = (var.limit << 12) | 0xfff;
4247 var.type = desc->type;
4248 var.present = desc->p;
4249 var.dpl = desc->dpl;
4250 var.db = desc->d;
4251 var.s = desc->s;
4252 var.l = desc->l;
4253 var.g = desc->g;
4254 var.avl = desc->avl;
4255 var.present = desc->p;
4256 var.unusable = !var.present;
4257 var.padding = 0;
4258
4259 kvm_set_segment(vcpu, &var, seg);
4260 return;
4261}
4262
717746e3
AK		 4263static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4264 u32 msr_index, u64 *pdata)
4265{
4266 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4267}
4268
4269static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4270 u32 msr_index, u64 data)
4271{
4272 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4273}
4274
222d21aa
AK		 4275static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4276 u32 pmc, u64 *pdata)
4277{
4278 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4279}
4280
6c3287f7
AK		 4281static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4282{
4283 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4284}
4285
5037f6f3
AK		 4286static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4287{
4288 preempt_disable();
5197b808 4289 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4290 /*
4291 * CR0.TS may reference the host fpu state, not the guest fpu state,
4292 * so it may be clear at this point.
4293 */
4294 clts();
4295}
4296
4297static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4298{
4299 preempt_enable();
4300}
4301
2953538e 4302static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4303 struct x86_instruction_info *info,
c4f035c6
AK		 4304 enum x86_intercept_stage stage)
4305{
2953538e 4306 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4307}
4308
0017f93a 4309static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4310 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4311{
0017f93a 4312 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4313}
4314
14af3f3c 4315static struct x86_emulate_ops emulate_ops = {
1871c602 4316 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4317 .write_std = kvm_write_guest_virt_system,
1871c602 4318 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4319 .read_emulated = emulator_read_emulated,
4320 .write_emulated = emulator_write_emulated,
4321 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4322 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4323 .pio_in_emulated = emulator_pio_in_emulated,
4324 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4325 .get_segment = emulator_get_segment,
4326 .set_segment = emulator_set_segment,
5951c442 4327 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4328 .get_gdt = emulator_get_gdt,
160ce1f1 4329 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4330 .set_gdt = emulator_set_gdt,
4331 .set_idt = emulator_set_idt,
52a46617
GN		 4332 .get_cr = emulator_get_cr,
4333 .set_cr = emulator_set_cr,
4cee4798 4334 .set_rflags = emulator_set_rflags,
9c537244 4335 .cpl = emulator_get_cpl,
35aa5375
GN		 4336 .get_dr = emulator_get_dr,
4337 .set_dr = emulator_set_dr,
717746e3
AK		 4338 .set_msr = emulator_set_msr,
4339 .get_msr = emulator_get_msr,
222d21aa 4340 .read_pmc = emulator_read_pmc,
6c3287f7 4341 .halt = emulator_halt,
bcaf5cc5 4342 .wbinvd = emulator_wbinvd,
d6aa1000 4343 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4344 .get_fpu = emulator_get_fpu,
4345 .put_fpu = emulator_put_fpu,
c4f035c6 4346 .intercept = emulator_intercept,
bdb42f5a 4347 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4348};
4349
5fdbf976
MT		 4350static void cache_all_regs(struct kvm_vcpu *vcpu)
4351{
4352 kvm_register_read(vcpu, VCPU_REGS_RAX);
4353 kvm_register_read(vcpu, VCPU_REGS_RSP);
4354 kvm_register_read(vcpu, VCPU_REGS_RIP);
4355 vcpu->arch.regs_dirty = ~0;
4356}
4357
95cb2295
GN		 4358static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4359{
4360 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4361 /*
4362 * an sti; sti; sequence only disable interrupts for the first
4363 * instruction. So, if the last instruction, be it emulated or
4364 * not, left the system with the INT_STI flag enabled, it
4365 * means that the last instruction is an sti. We should not
4366 * leave the flag on in this case. The same goes for mov ss
4367 */
4368 if (!(int_shadow & mask))
4369 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4370}
4371
54b8486f
GN		 4372static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4373{
4374 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4375 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4376 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4377 else if (ctxt->exception.error_code_valid)
4378 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4379 ctxt->exception.error_code);
54b8486f 4380 else
da9cb575 4381 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4382}
4383
9dac77fa 4384static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4385 const unsigned long *regs)
4386{
9dac77fa
AK		 4387 memset(&ctxt->twobyte, 0,
4388 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4389 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4390
9dac77fa
AK		 4391 ctxt->fetch.start = 0;
4392 ctxt->fetch.end = 0;
4393 ctxt->io_read.pos = 0;
4394 ctxt->io_read.end = 0;
4395 ctxt->mem_read.pos = 0;
4396 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4397}
4398
8ec4722d
MG		 4399static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4400{
adf52235 4401 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4402 int cs_db, cs_l;
4403
2aab2c5b
GN		 4404 /*
4405 * TODO: fix emulate.c to use guest_read/write_register
4406 * instead of direct ->regs accesses, can save hundred cycles
4407 * on Intel for instructions that don't read/change RSP, for
4408 * for example.
4409 */
8ec4722d
MG		 4410 cache_all_regs(vcpu);
4411
4412 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4413
adf52235
TY		 4414 ctxt->eflags = kvm_get_rflags(vcpu);
4415 ctxt->eip = kvm_rip_read(vcpu);
4416 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4417 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4418 cs_l ? X86EMUL_MODE_PROT64 :
4419 cs_db ? X86EMUL_MODE_PROT32 :
4420 X86EMUL_MODE_PROT16;
4421 ctxt->guest_mode = is_guest_mode(vcpu);
4422
9dac77fa 4423 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4424 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4425}
4426
71f9833b 4427int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4428{
9d74191a 4429 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4430 int ret;
4431
4432 init_emulate_ctxt(vcpu);
4433
9dac77fa
AK		 4434 ctxt->op_bytes = 2;
4435 ctxt->ad_bytes = 2;
4436 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4437 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4438
4439 if (ret != X86EMUL_CONTINUE)
4440 return EMULATE_FAIL;
4441
9dac77fa
AK		 4442 ctxt->eip = ctxt->_eip;
4443 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4444 kvm_rip_write(vcpu, ctxt->eip);
4445 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4446
4447 if (irq == NMI_VECTOR)
7460fb4a 4448 vcpu->arch.nmi_pending = 0;
63995653
MG		 4449 else
4450 vcpu->arch.interrupt.pending = false;
4451
4452 return EMULATE_DONE;
4453}
4454EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4455
6d77dbfc
GN		 4456static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4457{
fc3a9157
JR		 4458 int r = EMULATE_DONE;
4459
6d77dbfc
GN		 4460 ++vcpu->stat.insn_emulation_fail;
4461 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4462 if (!is_guest_mode(vcpu)) {
4463 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4464 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4465 vcpu->run->internal.ndata = 0;
4466 r = EMULATE_FAIL;
4467 }
6d77dbfc 4468 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4469
4470 return r;
6d77dbfc
GN		 4471}
4472
a6f177ef
GN		 4473static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4474{
4475 gpa_t gpa;
4476
68be0803
GN		 4477 if (tdp_enabled)
4478 return false;
4479
a6f177ef
GN		 4480 /*
4481 * if emulation was due to access to shadowed page table
4a969980 4482 * and it failed try to unshadow page and re-enter the
a6f177ef
GN		 4483 * guest to let CPU execute the instruction.
4484 */
4485 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4486 return true;
4487
4488 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4489
4490 if (gpa == UNMAPPED_GVA)
4491 return true; /* let cpu generate fault */
4492
4493 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4494 return true;
4495
4496 return false;
4497}
4498
1cb3f3ae
XG		 4499static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4500 unsigned long cr2, int emulation_type)
4501{
4502 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4503 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4504
4505 last_retry_eip = vcpu->arch.last_retry_eip;
4506 last_retry_addr = vcpu->arch.last_retry_addr;
4507
4508 /*
4509 * If the emulation is caused by #PF and it is non-page_table
4510 * writing instruction, it means the VM-EXIT is caused by shadow
4511 * page protected, we can zap the shadow page and retry this
4512 * instruction directly.
4513 *
4514 * Note: if the guest uses a non-page-table modifying instruction
4515 * on the PDE that points to the instruction, then we will unmap
4516 * the instruction and go to an infinite loop. So, we cache the
4517 * last retried eip and the last fault address, if we meet the eip
4518 * and the address again, we can break out of the potential infinite
4519 * loop.
4520 */
4521 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4522
4523 if (!(emulation_type & EMULTYPE_RETRY))
4524 return false;
4525
4526 if (x86_page_table_writing_insn(ctxt))
4527 return false;
4528
4529 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4530 return false;
4531
4532 vcpu->arch.last_retry_eip = ctxt->eip;
4533 vcpu->arch.last_retry_addr = cr2;
4534
4535 if (!vcpu->arch.mmu.direct_map)
4536 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4537
4538 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4539
4540 return true;
4541}
4542
51d8b661
AP		 4543int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4544 unsigned long cr2,
dc25e89e
AP		 4545 int emulation_type,
4546 void *insn,
4547 int insn_len)
bbd9b64e 4548{
95cb2295 4549 int r;
9d74191a 4550 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4551 bool writeback = true;
bbd9b64e 4552
26eef70c 4553 kvm_clear_exception_queue(vcpu);
8d7d8102 4554
571008da 4555 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4556 init_emulate_ctxt(vcpu);
9d74191a
TY		 4557 ctxt->interruptibility = 0;
4558 ctxt->have_exception = false;
4559 ctxt->perm_ok = false;
bbd9b64e 4560
9d74191a 4561 ctxt->only_vendor_specific_insn
4005996e
AK		 4562 = emulation_type & EMULTYPE_TRAP_UD;
4563
9d74191a 4564 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4565
e46479f8 4566 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4567 ++vcpu->stat.insn_emulation;
1d2887e2 4568 if (r != EMULATION_OK) {
4005996e
AK		 4569 if (emulation_type & EMULTYPE_TRAP_UD)
4570 return EMULATE_FAIL;
a6f177ef 4571 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4572 return EMULATE_DONE;
6d77dbfc
GN		 4573 if (emulation_type & EMULTYPE_SKIP)
4574 return EMULATE_FAIL;
4575 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4576 }
4577 }
4578
ba8afb6b 4579 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4580 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4581 return EMULATE_DONE;
4582 }
4583
1cb3f3ae
XG		 4584 if (retry_instruction(ctxt, cr2, emulation_type))
4585 return EMULATE_DONE;
4586
7ae441ea 4587 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4588 changes registers values during IO operation */
7ae441ea
GN		 4589 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4590 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4591 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4592 }
4d2179e1 4593
5cd21917 4594restart:
9d74191a 4595 r = x86_emulate_insn(ctxt);
bbd9b64e 4596
775fde86
JR		 4597 if (r == EMULATION_INTERCEPTED)
4598 return EMULATE_DONE;
4599
d2ddd1c4 4600 if (r == EMULATION_FAILED) {
a6f177ef 4601 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4602 return EMULATE_DONE;
4603
6d77dbfc 4604 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4605 }
4606
9d74191a 4607 if (ctxt->have_exception) {
54b8486f 4608 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4609 r = EMULATE_DONE;
4610 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4611 if (!vcpu->arch.pio.in)
4612 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4613 else
4614 writeback = false;
e85d28f8 4615 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4616 } else if (vcpu->mmio_needed) {
4617 if (!vcpu->mmio_is_write)
4618 writeback = false;
e85d28f8 4619 r = EMULATE_DO_MMIO;
7ae441ea 4620 } else if (r == EMULATION_RESTART)
5cd21917 4621 goto restart;
d2ddd1c4
GN		 4622 else
4623 r = EMULATE_DONE;
f850e2e6 4624
7ae441ea 4625 if (writeback) {
9d74191a
TY		 4626 toggle_interruptibility(vcpu, ctxt->interruptibility);
4627 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4628 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4629 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4630 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4631 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4632 } else
4633 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4634
4635 return r;
de7d789a 4636}
51d8b661 4637EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4638
cf8f70bf 4639int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4640{
cf8f70bf 4641 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4642 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4643 size, port, &val, 1);
cf8f70bf 4644 /* do not return to emulator after return from userspace */
7972995b 4645 vcpu->arch.pio.count = 0;
de7d789a
CO		 4646 return ret;
4647}
cf8f70bf 4648EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4649
8cfdc000
ZA		 4650static void tsc_bad(void *info)
4651{
0a3aee0d 4652 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4653}
4654
4655static void tsc_khz_changed(void *data)
c8076604 4656{
8cfdc000
ZA		 4657 struct cpufreq_freqs *freq = data;
4658 unsigned long khz = 0;
4659
4660 if (data)
4661 khz = freq->new;
4662 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4663 khz = cpufreq_quick_get(raw_smp_processor_id());
4664 if (!khz)
4665 khz = tsc_khz;
0a3aee0d 4666 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4667}
4668
c8076604
GH		 4669static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4670 void *data)
4671{
4672 struct cpufreq_freqs *freq = data;
4673 struct kvm *kvm;
4674 struct kvm_vcpu *vcpu;
4675 int i, send_ipi = 0;
4676
8cfdc000
ZA		 4677 /*
4678 * We allow guests to temporarily run on slowing clocks,
4679 * provided we notify them after, or to run on accelerating
4680 * clocks, provided we notify them before. Thus time never
4681 * goes backwards.
4682 *
4683 * However, we have a problem. We can't atomically update
4684 * the frequency of a given CPU from this function; it is
4685 * merely a notifier, which can be called from any CPU.
4686 * Changing the TSC frequency at arbitrary points in time
4687 * requires a recomputation of local variables related to
4688 * the TSC for each VCPU. We must flag these local variables
4689 * to be updated and be sure the update takes place with the
4690 * new frequency before any guests proceed.
4691 *
4692 * Unfortunately, the combination of hotplug CPU and frequency
4693 * change creates an intractable locking scenario; the order
4694 * of when these callouts happen is undefined with respect to
4695 * CPU hotplug, and they can race with each other. As such,
4696 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4697 * undefined; you can actually have a CPU frequency change take
4698 * place in between the computation of X and the setting of the
4699 * variable. To protect against this problem, all updates of
4700 * the per_cpu tsc_khz variable are done in an interrupt
4701 * protected IPI, and all callers wishing to update the value
4702 * must wait for a synchronous IPI to complete (which is trivial
4703 * if the caller is on the CPU already). This establishes the
4704 * necessary total order on variable updates.
4705 *
4706 * Note that because a guest time update may take place
4707 * anytime after the setting of the VCPU's request bit, the
4708 * correct TSC value must be set before the request. However,
4709 * to ensure the update actually makes it to any guest which
4710 * starts running in hardware virtualization between the set
4711 * and the acquisition of the spinlock, we must also ping the
4712 * CPU after setting the request bit.
4713 *
4714 */
4715
c8076604
GH		 4716 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4717 return 0;
4718 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4719 return 0;
8cfdc000
ZA		 4720
4721 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4722
e935b837 4723 raw_spin_lock(&kvm_lock);
c8076604 4724 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4725 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4726 if (vcpu->cpu != freq->cpu)
4727 continue;
c285545f 4728 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4729 if (vcpu->cpu != smp_processor_id())
8cfdc000 4730 send_ipi = 1;
c8076604
GH		 4731 }
4732 }
e935b837 4733 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4734
4735 if (freq->old < freq->new && send_ipi) {
4736 /*
4737 * We upscale the frequency. Must make the guest
4738 * doesn't see old kvmclock values while running with
4739 * the new frequency, otherwise we risk the guest sees
4740 * time go backwards.
4741 *
4742 * In case we update the frequency for another cpu
4743 * (which might be in guest context) send an interrupt
4744 * to kick the cpu out of guest context. Next time
4745 * guest context is entered kvmclock will be updated,
4746 * so the guest will not see stale values.
4747 */
8cfdc000 4748 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4749 }
4750 return 0;
4751}
4752
4753static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4754 .notifier_call = kvmclock_cpufreq_notifier
4755};
4756
4757static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4758 unsigned long action, void *hcpu)
4759{
4760 unsigned int cpu = (unsigned long)hcpu;
4761
4762 switch (action) {
4763 case CPU_ONLINE:
4764 case CPU_DOWN_FAILED:
4765 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4766 break;
4767 case CPU_DOWN_PREPARE:
4768 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4769 break;
4770 }
4771 return NOTIFY_OK;
4772}
4773
4774static struct notifier_block kvmclock_cpu_notifier_block = {
4775 .notifier_call = kvmclock_cpu_notifier,
4776 .priority = -INT_MAX
c8076604
GH		 4777};
4778
b820cc0c
ZA		 4779static void kvm_timer_init(void)
4780{
4781 int cpu;
4782
c285545f 4783 max_tsc_khz = tsc_khz;
8cfdc000 4784 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4785 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4786#ifdef CONFIG_CPU_FREQ
4787 struct cpufreq_policy policy;
4788 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4789 cpu = get_cpu();
4790 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4791 if (policy.cpuinfo.max_freq)
4792 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4793 put_cpu();
c285545f 4794#endif
b820cc0c
ZA		 4795 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4796 CPUFREQ_TRANSITION_NOTIFIER);
4797 }
c285545f 4798 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4799 for_each_online_cpu(cpu)
4800 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4801}
4802
ff9d07a0
ZY		 4803static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4804
f5132b01 4805int kvm_is_in_guest(void)
ff9d07a0 4806{
086c9855 4807 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4808}
4809
4810static int kvm_is_user_mode(void)
4811{
4812 int user_mode = 3;
dcf46b94 4813
086c9855
AS		 4814 if (__this_cpu_read(current_vcpu))
4815 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4816
ff9d07a0
ZY		 4817 return user_mode != 0;
4818}
4819
4820static unsigned long kvm_get_guest_ip(void)
4821{
4822 unsigned long ip = 0;
dcf46b94 4823
086c9855
AS		 4824 if (__this_cpu_read(current_vcpu))
4825 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4826
ff9d07a0
ZY		 4827 return ip;
4828}
4829
4830static struct perf_guest_info_callbacks kvm_guest_cbs = {
4831 .is_in_guest = kvm_is_in_guest,
4832 .is_user_mode = kvm_is_user_mode,
4833 .get_guest_ip = kvm_get_guest_ip,
4834};
4835
4836void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4837{
086c9855 4838 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4839}
4840EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4841
4842void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4843{
086c9855 4844 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4845}
4846EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4847
ce88decf
XG		 4848static void kvm_set_mmio_spte_mask(void)
4849{
4850 u64 mask;
4851 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4852
4853 /*
4854 * Set the reserved bits and the present bit of an paging-structure
4855 * entry to generate page fault with PFER.RSV = 1.
4856 */
4857 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4858 mask |= 1ull;
4859
4860#ifdef CONFIG_X86_64
4861 /*
4862 * If reserved bit is not supported, clear the present bit to disable
4863 * mmio page fault.
4864 */
4865 if (maxphyaddr == 52)
4866 mask &= ~1ull;
4867#endif
4868
4869 kvm_mmu_set_mmio_spte_mask(mask);
4870}
4871
f8c16bba 4872int kvm_arch_init(void *opaque)
043405e1 4873{
b820cc0c 4874 int r;
f8c16bba
ZX		 4875 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4876
f8c16bba
ZX		 4877 if (kvm_x86_ops) {
4878 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4879 r = -EEXIST;
4880 goto out;
f8c16bba
ZX		 4881 }
4882
4883 if (!ops->cpu_has_kvm_support()) {
4884 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4885 r = -EOPNOTSUPP;
4886 goto out;
f8c16bba
ZX		 4887 }
4888 if (ops->disabled_by_bios()) {
4889 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4890 r = -EOPNOTSUPP;
4891 goto out;
f8c16bba
ZX		 4892 }
4893
97db56ce
AK		 4894 r = kvm_mmu_module_init();
4895 if (r)
4896 goto out;
4897
ce88decf 4898 kvm_set_mmio_spte_mask();
97db56ce
AK		 4899 kvm_init_msr_list();
4900
f8c16bba 4901 kvm_x86_ops = ops;
7b52345e 4902 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4903 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4904
b820cc0c 4905 kvm_timer_init();
c8076604 4906
ff9d07a0
ZY		 4907 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4908
2acf923e
DC		 4909 if (cpu_has_xsave)
4910 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4911
f8c16bba 4912 return 0;
56c6d28a
ZX		 4913
4914out:
56c6d28a 4915 return r;
043405e1 4916}
8776e519 4917
f8c16bba
ZX		 4918void kvm_arch_exit(void)
4919{
ff9d07a0
ZY		 4920 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4921
888d256e
JK		 4922 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4923 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4924 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4925 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4926 kvm_x86_ops = NULL;
56c6d28a
ZX		 4927 kvm_mmu_module_exit();
4928}
f8c16bba 4929
8776e519
HB		 4930int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4931{
4932 ++vcpu->stat.halt_exits;
4933 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4934 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4935 return 1;
4936 } else {
4937 vcpu->run->exit_reason = KVM_EXIT_HLT;
4938 return 0;
4939 }
4940}
4941EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4942
55cd8e5a
GN		 4943int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4944{
4945 u64 param, ingpa, outgpa, ret;
4946 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4947 bool fast, longmode;
4948 int cs_db, cs_l;
4949
4950 /*
4951 * hypercall generates UD from non zero cpl and real mode
4952 * per HYPER-V spec
4953 */
3eeb3288 4954 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4955 kvm_queue_exception(vcpu, UD_VECTOR);
4956 return 0;
4957 }
4958
4959 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4960 longmode = is_long_mode(vcpu) && cs_l == 1;
4961
4962 if (!longmode) {
ccd46936
GN		 4963 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4964 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4965 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4966 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4967 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4968 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4969 }
4970#ifdef CONFIG_X86_64
4971 else {
4972 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4973 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4974 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4975 }
4976#endif
4977
4978 code = param & 0xffff;
4979 fast = (param >> 16) & 0x1;
4980 rep_cnt = (param >> 32) & 0xfff;
4981 rep_idx = (param >> 48) & 0xfff;
4982
4983 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4984
c25bc163
GN		 4985 switch (code) {
4986 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4987 kvm_vcpu_on_spin(vcpu);
4988 break;
4989 default:
4990 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4991 break;
4992 }
55cd8e5a
GN		 4993
4994 ret = res | (((u64)rep_done & 0xfff) << 32);
4995 if (longmode) {
4996 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4997 } else {
4998 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4999 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5000 }
5001
5002 return 1;
5003}
5004
8776e519
HB		 5005int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5006{
5007 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5008 int r = 1;
8776e519 5009
55cd8e5a
GN		 5010 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5011 return kvm_hv_hypercall(vcpu);
5012
5fdbf976
MT		 5013 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5014 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5015 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5016 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5017 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5018
229456fc 5019 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5020
8776e519
HB		 5021 if (!is_long_mode(vcpu)) {
5022 nr &= 0xFFFFFFFF;
5023 a0 &= 0xFFFFFFFF;
5024 a1 &= 0xFFFFFFFF;
5025 a2 &= 0xFFFFFFFF;
5026 a3 &= 0xFFFFFFFF;
5027 }
5028
07708c4a
JK		 5029 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5030 ret = -KVM_EPERM;
5031 goto out;
5032 }
5033
8776e519 5034 switch (nr) {
b93463aa
AK		 5035 case KVM_HC_VAPIC_POLL_IRQ:
5036 ret = 0;
5037 break;
8776e519
HB		 5038 default:
5039 ret = -KVM_ENOSYS;
5040 break;
5041 }
07708c4a 5042out:
5fdbf976 5043 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5044 ++vcpu->stat.hypercalls;
2f333bcb 5045 return r;
8776e519
HB		 5046}
5047EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5048
d6aa1000 5049int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5050{
d6aa1000 5051 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5052 char instruction[3];
5fdbf976 5053 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5054
8776e519
HB		 5055 /*
5056 * Blow out the MMU to ensure that no other VCPU has an active mapping
5057 * to ensure that the updated hypercall appears atomically across all
5058 * VCPUs.
5059 */
5060 kvm_mmu_zap_all(vcpu->kvm);
5061
8776e519 5062 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5063
9d74191a 5064 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5065}
5066
b6c7a5dc
HB		 5067/*
5068 * Check if userspace requested an interrupt window, and that the
5069 * interrupt window is open.
5070 *
5071 * No need to exit to userspace if we already have an interrupt queued.
5072 */
851ba692 5073static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5074{
8061823a 5075 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5076 vcpu->run->request_interrupt_window &&
5df56646 5077 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5078}
5079
851ba692 5080static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5081{
851ba692
AK		 5082 struct kvm_run *kvm_run = vcpu->run;
5083
91586a3b 5084 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5085 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5086 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5087 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5088 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5089 else
b6c7a5dc 5090 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5091 kvm_arch_interrupt_allowed(vcpu) &&
5092 !kvm_cpu_has_interrupt(vcpu) &&
5093 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5094}
5095
b93463aa
AK		 5096static void vapic_enter(struct kvm_vcpu *vcpu)
5097{
5098 struct kvm_lapic *apic = vcpu->arch.apic;
5099 struct page *page;
5100
5101 if (!apic || !apic->vapic_addr)
5102 return;
5103
5104 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5105
5106 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5107}
5108
5109static void vapic_exit(struct kvm_vcpu *vcpu)
5110{
5111 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5112 int idx;
b93463aa
AK		 5113
5114 if (!apic || !apic->vapic_addr)
5115 return;
5116
f656ce01 5117 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5118 kvm_release_page_dirty(apic->vapic_page);
5119 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5120 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5121}
5122
95ba8273
GN		 5123static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5124{
5125 int max_irr, tpr;
5126
5127 if (!kvm_x86_ops->update_cr8_intercept)
5128 return;
5129
88c808fd
AK		 5130 if (!vcpu->arch.apic)
5131 return;
5132
8db3baa2
GN		 5133 if (!vcpu->arch.apic->vapic_addr)
5134 max_irr = kvm_lapic_find_highest_irr(vcpu);
5135 else
5136 max_irr = -1;
95ba8273
GN		 5137
5138 if (max_irr != -1)
5139 max_irr >>= 4;
5140
5141 tpr = kvm_lapic_get_cr8(vcpu);
5142
5143 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5144}
5145
851ba692 5146static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5147{
5148 /* try to reinject previous events if any */
b59bb7bd 5149 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5150 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5151 vcpu->arch.exception.has_error_code,
5152 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5153 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5154 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5155 vcpu->arch.exception.error_code,
5156 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5157 return;
5158 }
5159
95ba8273
GN		 5160 if (vcpu->arch.nmi_injected) {
5161 kvm_x86_ops->set_nmi(vcpu);
5162 return;
5163 }
5164
5165 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5166 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5167 return;
5168 }
5169
5170 /* try to inject new event if pending */
5171 if (vcpu->arch.nmi_pending) {
5172 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5173 --vcpu->arch.nmi_pending;
95ba8273
GN		 5174 vcpu->arch.nmi_injected = true;
5175 kvm_x86_ops->set_nmi(vcpu);
5176 }
5177 } else if (kvm_cpu_has_interrupt(vcpu)) {
5178 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5179 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5180 false);
5181 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5182 }
5183 }
5184}
5185
2acf923e
DC		 5186static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5187{
5188 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5189 !vcpu->guest_xcr0_loaded) {
5190 /* kvm_set_xcr() also depends on this */
5191 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5192 vcpu->guest_xcr0_loaded = 1;
5193 }
5194}
5195
5196static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5197{
5198 if (vcpu->guest_xcr0_loaded) {
5199 if (vcpu->arch.xcr0 != host_xcr0)
5200 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5201 vcpu->guest_xcr0_loaded = 0;
5202 }
5203}
5204
7460fb4a
AK		 5205static void process_nmi(struct kvm_vcpu *vcpu)
5206{
5207 unsigned limit = 2;
5208
5209 /*
5210 * x86 is limited to one NMI running, and one NMI pending after it.
5211 * If an NMI is already in progress, limit further NMIs to just one.
5212 * Otherwise, allow two (and we'll inject the first one immediately).
5213 */
5214 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5215 limit = 1;
5216
5217 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5218 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5219 kvm_make_request(KVM_REQ_EVENT, vcpu);
5220}
5221
851ba692 5222static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5223{
5224 int r;
6a8b1d13 5225 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5226 vcpu->run->request_interrupt_window;
d6185f20 5227 bool req_immediate_exit = 0;
b6c7a5dc 5228
3e007509 5229 if (vcpu->requests) {
a8eeb04a 5230 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5231 kvm_mmu_unload(vcpu);
a8eeb04a 5232 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5233 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5234 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5235 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5236 if (unlikely(r))
5237 goto out;
5238 }
a8eeb04a 5239 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5240 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5241 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5242 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5243 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5244 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5245 r = 0;
5246 goto out;
5247 }
a8eeb04a 5248 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5249 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5250 r = 0;
5251 goto out;
5252 }
a8eeb04a 5253 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5254 vcpu->fpu_active = 0;
5255 kvm_x86_ops->fpu_deactivate(vcpu);
5256 }
af585b92
GN		 5257 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5258 /* Page is swapped out. Do synthetic halt */
5259 vcpu->arch.apf.halted = true;
5260 r = 1;
5261 goto out;
5262 }
c9aaa895
GC		 5263 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5264 record_steal_time(vcpu);
7460fb4a
AK		 5265 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5266 process_nmi(vcpu);
d6185f20
NHE		 5267 req_immediate_exit =
5268 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5269 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5270 kvm_handle_pmu_event(vcpu);
5271 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5272 kvm_deliver_pmi(vcpu);
2f52d58c 5273 }
b93463aa 5274
b463a6f7
AK		 5275 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5276 inject_pending_event(vcpu);
5277
5278 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5279 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5280 kvm_x86_ops->enable_nmi_window(vcpu);
5281 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5282 kvm_x86_ops->enable_irq_window(vcpu);
5283
5284 if (kvm_lapic_enabled(vcpu)) {
5285 update_cr8_intercept(vcpu);
5286 kvm_lapic_sync_to_vapic(vcpu);
5287 }
5288 }
5289
d8368af8
AK		 5290 r = kvm_mmu_reload(vcpu);
5291 if (unlikely(r)) {
d905c069 5292 goto cancel_injection;
d8368af8
AK		 5293 }
5294
b6c7a5dc
HB		 5295 preempt_disable();
5296
5297 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5298 if (vcpu->fpu_active)
5299 kvm_load_guest_fpu(vcpu);
2acf923e 5300 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5301
6b7e2d09
XG		 5302 vcpu->mode = IN_GUEST_MODE;
5303
5304 /* We should set ->mode before check ->requests,
5305 * see the comment in make_all_cpus_request.
5306 */
5307 smp_mb();
b6c7a5dc 5308
d94e1dc9 5309 local_irq_disable();
32f88400 5310
6b7e2d09 5311 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5312 || need_resched() || signal_pending(current)) {
6b7e2d09 5313 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5314 smp_wmb();
6c142801
AK		 5315 local_irq_enable();
5316 preempt_enable();
5317 r = 1;
d905c069 5318 goto cancel_injection;
6c142801
AK		 5319 }
5320
f656ce01 5321 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5322
d6185f20
NHE		 5323 if (req_immediate_exit)
5324 smp_send_reschedule(vcpu->cpu);
5325
b6c7a5dc
HB		 5326 kvm_guest_enter();
5327
42dbaa5a 5328 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5329 set_debugreg(0, 7);
5330 set_debugreg(vcpu->arch.eff_db[0], 0);
5331 set_debugreg(vcpu->arch.eff_db[1], 1);
5332 set_debugreg(vcpu->arch.eff_db[2], 2);
5333 set_debugreg(vcpu->arch.eff_db[3], 3);
5334 }
b6c7a5dc 5335
229456fc 5336 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5337 kvm_x86_ops->run(vcpu);
b6c7a5dc 5338
24f1e32c
FW		 5339 /*
5340 * If the guest has used debug registers, at least dr7
5341 * will be disabled while returning to the host.
5342 * If we don't have active breakpoints in the host, we don't
5343 * care about the messed up debug address registers. But if
5344 * we have some of them active, restore the old state.
5345 */
59d8eb53 5346 if (hw_breakpoint_active())
24f1e32c 5347 hw_breakpoint_restore();
42dbaa5a 5348
d5c1785d 5349 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5350
6b7e2d09 5351 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5352 smp_wmb();
b6c7a5dc
HB		 5353 local_irq_enable();
5354
5355 ++vcpu->stat.exits;
5356
5357 /*
5358 * We must have an instruction between local_irq_enable() and
5359 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5360 * the interrupt shadow. The stat.exits increment will do nicely.
5361 * But we need to prevent reordering, hence this barrier():
5362 */
5363 barrier();
5364
5365 kvm_guest_exit();
5366
5367 preempt_enable();
5368
f656ce01 5369 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5370
b6c7a5dc
HB		 5371 /*
5372 * Profile KVM exit RIPs:
5373 */
5374 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5375 unsigned long rip = kvm_rip_read(vcpu);
5376 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5377 }
5378
cc578287
ZA		 5379 if (unlikely(vcpu->arch.tsc_always_catchup))
5380 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5381
5cfb1d5a
MT		 5382 if (vcpu->arch.apic_attention)
5383 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5384
851ba692 5385 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5386 return r;
5387
5388cancel_injection:
5389 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5390 if (unlikely(vcpu->arch.apic_attention))
5391 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5392out:
5393 return r;
5394}
b6c7a5dc 5395
09cec754 5396
851ba692 5397static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5398{
5399 int r;
f656ce01 5400 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5401
5402 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5403 pr_debug("vcpu %d received sipi with vector # %x\n",
5404 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5405 kvm_lapic_reset(vcpu);
5f179287 5406 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5407 if (r)
5408 return r;
5409 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5410 }
5411
f656ce01 5412 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5413 vapic_enter(vcpu);
5414
5415 r = 1;
5416 while (r > 0) {
af585b92
GN		 5417 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5418 !vcpu->arch.apf.halted)
851ba692 5419 r = vcpu_enter_guest(vcpu);
d7690175 5420 else {
f656ce01 5421 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5422 kvm_vcpu_block(vcpu);
f656ce01 5423 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5424 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5425 {
5426 switch(vcpu->arch.mp_state) {
5427 case KVM_MP_STATE_HALTED:
d7690175 5428 vcpu->arch.mp_state =
09cec754
GN		 5429 KVM_MP_STATE_RUNNABLE;
5430 case KVM_MP_STATE_RUNNABLE:
af585b92 5431 vcpu->arch.apf.halted = false;
09cec754
GN		 5432 break;
5433 case KVM_MP_STATE_SIPI_RECEIVED:
5434 default:
5435 r = -EINTR;
5436 break;
5437 }
5438 }
d7690175
MT		 5439 }
5440
09cec754
GN		 5441 if (r <= 0)
5442 break;
5443
5444 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5445 if (kvm_cpu_has_pending_timer(vcpu))
5446 kvm_inject_pending_timer_irqs(vcpu);
5447
851ba692 5448 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5449 r = -EINTR;
851ba692 5450 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5451 ++vcpu->stat.request_irq_exits;
5452 }
af585b92
GN		 5453
5454 kvm_check_async_pf_completion(vcpu);
5455
09cec754
GN		 5456 if (signal_pending(current)) {
5457 r = -EINTR;
851ba692 5458 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5459 ++vcpu->stat.signal_exits;
5460 }
5461 if (need_resched()) {
f656ce01 5462 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5463 kvm_resched(vcpu);
f656ce01 5464 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5465 }
b6c7a5dc
HB		 5466 }
5467
f656ce01 5468 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5469
b93463aa
AK		 5470 vapic_exit(vcpu);
5471
b6c7a5dc
HB		 5472 return r;
5473}
5474
f78146b0
AK		 5475/*
5476 * Implements the following, as a state machine:
5477 *
5478 * read:
5479 * for each fragment
5480 * write gpa, len
5481 * exit
5482 * copy data
5483 * execute insn
5484 *
5485 * write:
5486 * for each fragment
5487 * write gpa, len
5488 * copy data
5489 * exit
5490 */
5287f194
AK		 5491static int complete_mmio(struct kvm_vcpu *vcpu)
5492{
5493 struct kvm_run *run = vcpu->run;
f78146b0 5494 struct kvm_mmio_fragment *frag;
5287f194
AK		 5495 int r;
5496
5497 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5498 return 1;
5499
5500 if (vcpu->mmio_needed) {
f78146b0
AK		 5501 /* Complete previous fragment */
5502 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
cef4dea0 5503 if (!vcpu->mmio_is_write)
f78146b0
AK		 5504 memcpy(frag->data, run->mmio.data, frag->len);
5505 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5506 vcpu->mmio_needed = 0;
5507 if (vcpu->mmio_is_write)
5508 return 1;
5509 vcpu->mmio_read_completed = 1;
5510 goto done;
cef4dea0 5511 }
f78146b0
AK		 5512 /* Initiate next fragment */
5513 ++frag;
5514 run->exit_reason = KVM_EXIT_MMIO;
5515 run->mmio.phys_addr = frag->gpa;
cef4dea0 5516 if (vcpu->mmio_is_write)
f78146b0
AK		 5517 memcpy(run->mmio.data, frag->data, frag->len);
5518 run->mmio.len = frag->len;
5519 run->mmio.is_write = vcpu->mmio_is_write;
5520 return 0;
5521
5287f194 5522 }
f78146b0 5523done:
5287f194
AK		 5524 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5525 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5526 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5527 if (r != EMULATE_DONE)
5528 return 0;
5529 return 1;
5530}
5531
b6c7a5dc
HB		 5532int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5533{
5534 int r;
5535 sigset_t sigsaved;
5536
e5c30142
AK		 5537 if (!tsk_used_math(current) && init_fpu(current))
5538 return -ENOMEM;
5539
ac9f6dc0
AK		 5540 if (vcpu->sigset_active)
5541 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5542
a4535290 5543 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5544 kvm_vcpu_block(vcpu);
d7690175 5545 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5546 r = -EAGAIN;
5547 goto out;
b6c7a5dc
HB		 5548 }
5549
b6c7a5dc 5550 /* re-sync apic's tpr */
eea1cff9
AP		 5551 if (!irqchip_in_kernel(vcpu->kvm)) {
5552 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5553 r = -EINVAL;
5554 goto out;
5555 }
5556 }
b6c7a5dc 5557
5287f194
AK		 5558 r = complete_mmio(vcpu);
5559 if (r <= 0)
5560 goto out;
5561
851ba692 5562 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5563
5564out:
f1d86e46 5565 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5566 if (vcpu->sigset_active)
5567 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5568
b6c7a5dc
HB		 5569 return r;
5570}
5571
5572int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5573{
7ae441ea
GN		 5574 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5575 /*
5576 * We are here if userspace calls get_regs() in the middle of
5577 * instruction emulation. Registers state needs to be copied
4a969980 5578 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 5579 * that usually, but some bad designed PV devices (vmware
5580 * backdoor interface) need this to work
5581 */
9dac77fa
AK		 5582 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5583 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5584 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5585 }
5fdbf976
MT		 5586 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5587 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5588 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5589 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5590 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5591 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5592 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5593 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5594#ifdef CONFIG_X86_64
5fdbf976
MT		 5595 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5596 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5597 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5598 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5599 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5600 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5601 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5602 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5603#endif
5604
5fdbf976 5605 regs->rip = kvm_rip_read(vcpu);
91586a3b 5606 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5607
b6c7a5dc
HB		 5608 return 0;
5609}
5610
5611int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5612{
7ae441ea
GN		 5613 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5614 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5615
5fdbf976
MT		 5616 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5617 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5618 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5619 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5620 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5621 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5622 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5623 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5624#ifdef CONFIG_X86_64
5fdbf976
MT		 5625 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5626 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5627 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5628 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5629 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5630 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5631 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5632 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5633#endif
5634
5fdbf976 5635 kvm_rip_write(vcpu, regs->rip);
91586a3b 5636 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5637
b4f14abd
JK		 5638 vcpu->arch.exception.pending = false;
5639
3842d135
AK		 5640 kvm_make_request(KVM_REQ_EVENT, vcpu);
5641
b6c7a5dc
HB		 5642 return 0;
5643}
5644
b6c7a5dc
HB		 5645void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5646{
5647 struct kvm_segment cs;
5648
3e6e0aab 5649 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5650 *db = cs.db;
5651 *l = cs.l;
5652}
5653EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5654
5655int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5656 struct kvm_sregs *sregs)
5657{
89a27f4d 5658 struct desc_ptr dt;
b6c7a5dc 5659
3e6e0aab
GT		 5660 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5661 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5662 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5663 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5664 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5665 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5666
3e6e0aab
GT		 5667 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5668 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5669
5670 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5671 sregs->idt.limit = dt.size;
5672 sregs->idt.base = dt.address;
b6c7a5dc 5673 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5674 sregs->gdt.limit = dt.size;
5675 sregs->gdt.base = dt.address;
b6c7a5dc 5676
4d4ec087 5677 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5678 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5679 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5680 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5681 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5682 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5683 sregs->apic_base = kvm_get_apic_base(vcpu);
5684
923c61bb 5685 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5686
36752c9b 5687 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5688 set_bit(vcpu->arch.interrupt.nr,
5689 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5690
b6c7a5dc
HB		 5691 return 0;
5692}
5693
62d9f0db
MT		 5694int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5695 struct kvm_mp_state *mp_state)
5696{
62d9f0db 5697 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5698 return 0;
5699}
5700
5701int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5702 struct kvm_mp_state *mp_state)
5703{
62d9f0db 5704 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5705 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5706 return 0;
5707}
5708
7f3d35fd
KW		 5709int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5710 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 5711{
9d74191a 5712 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5713 int ret;
e01c2426 5714
8ec4722d 5715 init_emulate_ctxt(vcpu);
c697518a 5716
7f3d35fd 5717 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 5718 has_error_code, error_code);
c697518a 5719
c697518a 5720 if (ret)
19d04437 5721 return EMULATE_FAIL;
37817f29 5722
9dac77fa 5723 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 5724 kvm_rip_write(vcpu, ctxt->eip);
5725 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5726 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5727 return EMULATE_DONE;
37817f29
IE		 5728}
5729EXPORT_SYMBOL_GPL(kvm_task_switch);
5730
b6c7a5dc
HB		 5731int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5732 struct kvm_sregs *sregs)
5733{
5734 int mmu_reset_needed = 0;
63f42e02 5735 int pending_vec, max_bits, idx;
89a27f4d 5736 struct desc_ptr dt;
b6c7a5dc 5737
89a27f4d
GN		 5738 dt.size = sregs->idt.limit;
5739 dt.address = sregs->idt.base;
b6c7a5dc 5740 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5741 dt.size = sregs->gdt.limit;
5742 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5743 kvm_x86_ops->set_gdt(vcpu, &dt);
5744
ad312c7c 5745 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5746 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5747 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5748 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5749
2d3ad1f4 5750 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5751
f6801dff 5752 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5753 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5754 kvm_set_apic_base(vcpu, sregs->apic_base);
5755
4d4ec087 5756 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5757 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5758 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5759
fc78f519 5760 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5761 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5762 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5763 kvm_update_cpuid(vcpu);
63f42e02
XG		 5764
5765 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5766 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5767 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5768 mmu_reset_needed = 1;
5769 }
63f42e02 5770 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5771
5772 if (mmu_reset_needed)
5773 kvm_mmu_reset_context(vcpu);
5774
923c61bb
GN		 5775 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5776 pending_vec = find_first_bit(
5777 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5778 if (pending_vec < max_bits) {
66fd3f7f 5779 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5780 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5781 }
5782
3e6e0aab
GT		 5783 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5784 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5785 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5786 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5787 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5788 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5789
3e6e0aab
GT		 5790 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5791 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5792
5f0269f5
ME		 5793 update_cr8_intercept(vcpu);
5794
9c3e4aab 5795 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5796 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5797 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5798 !is_protmode(vcpu))
9c3e4aab
MT		 5799 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5800
3842d135
AK		 5801 kvm_make_request(KVM_REQ_EVENT, vcpu);
5802
b6c7a5dc
HB		 5803 return 0;
5804}
5805
d0bfb940
JK		 5806int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5807 struct kvm_guest_debug *dbg)
b6c7a5dc 5808{
355be0b9 5809 unsigned long rflags;
ae675ef0 5810 int i, r;
b6c7a5dc 5811
4f926bf2
JK		 5812 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5813 r = -EBUSY;
5814 if (vcpu->arch.exception.pending)
2122ff5e 5815 goto out;
4f926bf2
JK		 5816 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5817 kvm_queue_exception(vcpu, DB_VECTOR);
5818 else
5819 kvm_queue_exception(vcpu, BP_VECTOR);
5820 }
5821
91586a3b
JK		 5822 /*
5823 * Read rflags as long as potentially injected trace flags are still
5824 * filtered out.
5825 */
5826 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5827
5828 vcpu->guest_debug = dbg->control;
5829 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5830 vcpu->guest_debug = 0;
5831
5832 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5833 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5834 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5835 vcpu->arch.switch_db_regs =
5836 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5837 } else {
5838 for (i = 0; i < KVM_NR_DB_REGS; i++)
5839 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5840 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5841 }
5842
f92653ee
JK		 5843 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5844 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5845 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5846
91586a3b
JK		 5847 /*
5848 * Trigger an rflags update that will inject or remove the trace
5849 * flags.
5850 */
5851 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5852
355be0b9 5853 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5854
4f926bf2 5855 r = 0;
d0bfb940 5856
2122ff5e 5857out:
b6c7a5dc
HB		 5858
5859 return r;
5860}
5861
8b006791
ZX		 5862/*
5863 * Translate a guest virtual address to a guest physical address.
5864 */
5865int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5866 struct kvm_translation *tr)
5867{
5868 unsigned long vaddr = tr->linear_address;
5869 gpa_t gpa;
f656ce01 5870 int idx;
8b006791 5871
f656ce01 5872 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5873 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5874 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5875 tr->physical_address = gpa;
5876 tr->valid = gpa != UNMAPPED_GVA;
5877 tr->writeable = 1;
5878 tr->usermode = 0;
8b006791
ZX		 5879
5880 return 0;
5881}
5882
d0752060
HB		 5883int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5884{
98918833
SY		 5885 struct i387_fxsave_struct *fxsave =
5886 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5887
d0752060
HB		 5888 memcpy(fpu->fpr, fxsave->st_space, 128);
5889 fpu->fcw = fxsave->cwd;
5890 fpu->fsw = fxsave->swd;
5891 fpu->ftwx = fxsave->twd;
5892 fpu->last_opcode = fxsave->fop;
5893 fpu->last_ip = fxsave->rip;
5894 fpu->last_dp = fxsave->rdp;
5895 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5896
d0752060
HB		 5897 return 0;
5898}
5899
5900int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5901{
98918833
SY		 5902 struct i387_fxsave_struct *fxsave =
5903 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5904
d0752060
HB		 5905 memcpy(fxsave->st_space, fpu->fpr, 128);
5906 fxsave->cwd = fpu->fcw;
5907 fxsave->swd = fpu->fsw;
5908 fxsave->twd = fpu->ftwx;
5909 fxsave->fop = fpu->last_opcode;
5910 fxsave->rip = fpu->last_ip;
5911 fxsave->rdp = fpu->last_dp;
5912 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5913
d0752060
HB		 5914 return 0;
5915}
5916
10ab25cd 5917int fx_init(struct kvm_vcpu *vcpu)
d0752060 5918{
10ab25cd
JK		 5919 int err;
5920
5921 err = fpu_alloc(&vcpu->arch.guest_fpu);
5922 if (err)
5923 return err;
5924
98918833 5925 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5926
2acf923e
DC		 5927 /*
5928 * Ensure guest xcr0 is valid for loading
5929 */
5930 vcpu->arch.xcr0 = XSTATE_FP;
5931
ad312c7c 5932 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5933
5934 return 0;
d0752060
HB		 5935}
5936EXPORT_SYMBOL_GPL(fx_init);
5937
98918833
SY		 5938static void fx_free(struct kvm_vcpu *vcpu)
5939{
5940 fpu_free(&vcpu->arch.guest_fpu);
5941}
5942
d0752060
HB		 5943void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5944{
2608d7a1 5945 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5946 return;
5947
2acf923e
DC		 5948 /*
5949 * Restore all possible states in the guest,
5950 * and assume host would use all available bits.
5951 * Guest xcr0 would be loaded later.
5952 */
5953 kvm_put_guest_xcr0(vcpu);
d0752060 5954 vcpu->guest_fpu_loaded = 1;
7cf30855 5955 unlazy_fpu(current);
98918833 5956 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5957 trace_kvm_fpu(1);
d0752060 5958}
d0752060
HB		 5959
5960void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5961{
2acf923e
DC		 5962 kvm_put_guest_xcr0(vcpu);
5963
d0752060
HB		 5964 if (!vcpu->guest_fpu_loaded)
5965 return;
5966
5967 vcpu->guest_fpu_loaded = 0;
98918833 5968 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5969 ++vcpu->stat.fpu_reload;
a8eeb04a 5970 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5971 trace_kvm_fpu(0);
d0752060 5972}
e9b11c17
ZX		 5973
5974void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5975{
12f9a48f 5976 kvmclock_reset(vcpu);
7f1ea208 5977
f5f48ee1 5978 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5979 fx_free(vcpu);
e9b11c17
ZX		 5980 kvm_x86_ops->vcpu_free(vcpu);
5981}
5982
5983struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5984 unsigned int id)
5985{
6755bae8
ZA		 5986 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5987 printk_once(KERN_WARNING
5988 "kvm: SMP vm created on host with unstable TSC; "
5989 "guest TSC will not be reliable\n");
26e5215f
AK		 5990 return kvm_x86_ops->vcpu_create(kvm, id);
5991}
e9b11c17 5992
26e5215f
AK		 5993int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5994{
5995 int r;
e9b11c17 5996
0bed3b56 5997 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5998 vcpu_load(vcpu);
5999 r = kvm_arch_vcpu_reset(vcpu);
6000 if (r == 0)
6001 r = kvm_mmu_setup(vcpu);
6002 vcpu_put(vcpu);
e9b11c17 6003
26e5215f 6004 return r;
e9b11c17
ZX		 6005}
6006
d40ccc62 6007void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6008{
344d9588
GN		 6009 vcpu->arch.apf.msr_val = 0;
6010
e9b11c17
ZX		 6011 vcpu_load(vcpu);
6012 kvm_mmu_unload(vcpu);
6013 vcpu_put(vcpu);
6014
98918833 6015 fx_free(vcpu);
e9b11c17
ZX		 6016 kvm_x86_ops->vcpu_free(vcpu);
6017}
6018
6019int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6020{
7460fb4a
AK		 6021 atomic_set(&vcpu->arch.nmi_queued, 0);
6022 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6023 vcpu->arch.nmi_injected = false;
6024
42dbaa5a
JK		 6025 vcpu->arch.switch_db_regs = 0;
6026 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6027 vcpu->arch.dr6 = DR6_FIXED_1;
6028 vcpu->arch.dr7 = DR7_FIXED_1;
6029
3842d135 6030 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6031 vcpu->arch.apf.msr_val = 0;
c9aaa895 6032 vcpu->arch.st.msr_val = 0;
3842d135 6033
12f9a48f
GC		 6034 kvmclock_reset(vcpu);
6035
af585b92
GN		 6036 kvm_clear_async_pf_completion_queue(vcpu);
6037 kvm_async_pf_hash_reset(vcpu);
6038 vcpu->arch.apf.halted = false;
3842d135 6039
f5132b01
GN		 6040 kvm_pmu_reset(vcpu);
6041
e9b11c17
ZX		 6042 return kvm_x86_ops->vcpu_reset(vcpu);
6043}
6044
10474ae8 6045int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6046{
ca84d1a2
ZA		 6047 struct kvm *kvm;
6048 struct kvm_vcpu *vcpu;
6049 int i;
0dd6a6ed
ZA		 6050 int ret;
6051 u64 local_tsc;
6052 u64 max_tsc = 0;
6053 bool stable, backwards_tsc = false;
18863bdd
AK		 6054
6055 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6056 ret = kvm_x86_ops->hardware_enable(garbage);
6057 if (ret != 0)
6058 return ret;
6059
6060 local_tsc = native_read_tsc();
6061 stable = !check_tsc_unstable();
6062 list_for_each_entry(kvm, &vm_list, vm_list) {
6063 kvm_for_each_vcpu(i, vcpu, kvm) {
6064 if (!stable && vcpu->cpu == smp_processor_id())
6065 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6066 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6067 backwards_tsc = true;
6068 if (vcpu->arch.last_host_tsc > max_tsc)
6069 max_tsc = vcpu->arch.last_host_tsc;
6070 }
6071 }
6072 }
6073
6074 /*
6075 * Sometimes, even reliable TSCs go backwards. This happens on
6076 * platforms that reset TSC during suspend or hibernate actions, but
6077 * maintain synchronization. We must compensate. Fortunately, we can
6078 * detect that condition here, which happens early in CPU bringup,
6079 * before any KVM threads can be running. Unfortunately, we can't
6080 * bring the TSCs fully up to date with real time, as we aren't yet far
6081 * enough into CPU bringup that we know how much real time has actually
6082 * elapsed; our helper function, get_kernel_ns() will be using boot
6083 * variables that haven't been updated yet.
6084 *
6085 * So we simply find the maximum observed TSC above, then record the
6086 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6087 * the adjustment will be applied. Note that we accumulate
6088 * adjustments, in case multiple suspend cycles happen before some VCPU
6089 * gets a chance to run again. In the event that no KVM threads get a
6090 * chance to run, we will miss the entire elapsed period, as we'll have
6091 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6092 * loose cycle time. This isn't too big a deal, since the loss will be
6093 * uniform across all VCPUs (not to mention the scenario is extremely
6094 * unlikely). It is possible that a second hibernate recovery happens
6095 * much faster than a first, causing the observed TSC here to be
6096 * smaller; this would require additional padding adjustment, which is
6097 * why we set last_host_tsc to the local tsc observed here.
6098 *
6099 * N.B. - this code below runs only on platforms with reliable TSC,
6100 * as that is the only way backwards_tsc is set above. Also note
6101 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6102 * have the same delta_cyc adjustment applied if backwards_tsc
6103 * is detected. Note further, this adjustment is only done once,
6104 * as we reset last_host_tsc on all VCPUs to stop this from being
6105 * called multiple times (one for each physical CPU bringup).
6106 *
4a969980 6107 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6108 * will be compensated by the logic in vcpu_load, which sets the TSC to
6109 * catchup mode. This will catchup all VCPUs to real time, but cannot
6110 * guarantee that they stay in perfect synchronization.
6111 */
6112 if (backwards_tsc) {
6113 u64 delta_cyc = max_tsc - local_tsc;
6114 list_for_each_entry(kvm, &vm_list, vm_list) {
6115 kvm_for_each_vcpu(i, vcpu, kvm) {
6116 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6117 vcpu->arch.last_host_tsc = local_tsc;
6118 }
6119
6120 /*
6121 * We have to disable TSC offset matching.. if you were
6122 * booting a VM while issuing an S4 host suspend....
6123 * you may have some problem. Solving this issue is
6124 * left as an exercise to the reader.
6125 */
6126 kvm->arch.last_tsc_nsec = 0;
6127 kvm->arch.last_tsc_write = 0;
6128 }
6129
6130 }
6131 return 0;
e9b11c17
ZX		 6132}
6133
6134void kvm_arch_hardware_disable(void *garbage)
6135{
6136 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6137 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6138}
6139
6140int kvm_arch_hardware_setup(void)
6141{
6142 return kvm_x86_ops->hardware_setup();
6143}
6144
6145void kvm_arch_hardware_unsetup(void)
6146{
6147 kvm_x86_ops->hardware_unsetup();
6148}
6149
6150void kvm_arch_check_processor_compat(void *rtn)
6151{
6152 kvm_x86_ops->check_processor_compatibility(rtn);
6153}
6154
3e515705
AK		 6155bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6156{
6157 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6158}
6159
e9b11c17
ZX		 6160int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6161{
6162 struct page *page;
6163 struct kvm *kvm;
6164 int r;
6165
6166 BUG_ON(vcpu->kvm == NULL);
6167 kvm = vcpu->kvm;
6168
9aabc88f 6169 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6170 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6171 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6172 else
a4535290 6173 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6174
6175 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6176 if (!page) {
6177 r = -ENOMEM;
6178 goto fail;
6179 }
ad312c7c 6180 vcpu->arch.pio_data = page_address(page);
e9b11c17 6181
cc578287 6182 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6183
e9b11c17
ZX		 6184 r = kvm_mmu_create(vcpu);
6185 if (r < 0)
6186 goto fail_free_pio_data;
6187
6188 if (irqchip_in_kernel(kvm)) {
6189 r = kvm_create_lapic(vcpu);
6190 if (r < 0)
6191 goto fail_mmu_destroy;
6192 }
6193
890ca9ae
HY		 6194 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6195 GFP_KERNEL);
6196 if (!vcpu->arch.mce_banks) {
6197 r = -ENOMEM;
443c39bc 6198 goto fail_free_lapic;
890ca9ae
HY		 6199 }
6200 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6201
f5f48ee1
SY		 6202 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6203 goto fail_free_mce_banks;
6204
af585b92 6205 kvm_async_pf_hash_reset(vcpu);
f5132b01 6206 kvm_pmu_init(vcpu);
af585b92 6207
e9b11c17 6208 return 0;
f5f48ee1
SY		 6209fail_free_mce_banks:
6210 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6211fail_free_lapic:
6212 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6213fail_mmu_destroy:
6214 kvm_mmu_destroy(vcpu);
6215fail_free_pio_data:
ad312c7c 6216 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6217fail:
6218 return r;
6219}
6220
6221void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6222{
f656ce01
MT		 6223 int idx;
6224
f5132b01 6225 kvm_pmu_destroy(vcpu);
36cb93fd 6226 kfree(vcpu->arch.mce_banks);
e9b11c17 6227 kvm_free_lapic(vcpu);
f656ce01 6228 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6229 kvm_mmu_destroy(vcpu);
f656ce01 6230 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6231 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6232}
d19a9cd2 6233
e08b9637 6234int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6235{
e08b9637
CO		 6236 if (type)
6237 return -EINVAL;
6238
f05e70ac 6239 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6240 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6241
5550af4d
SY		 6242 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6243 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6244
038f8c11 6245 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6246
d89f5eff 6247 return 0;
d19a9cd2
ZX		 6248}
6249
6250static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6251{
6252 vcpu_load(vcpu);
6253 kvm_mmu_unload(vcpu);
6254 vcpu_put(vcpu);
6255}
6256
6257static void kvm_free_vcpus(struct kvm *kvm)
6258{
6259 unsigned int i;
988a2cae 6260 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6261
6262 /*
6263 * Unpin any mmu pages first.
6264 */
af585b92
GN		 6265 kvm_for_each_vcpu(i, vcpu, kvm) {
6266 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6267 kvm_unload_vcpu_mmu(vcpu);
af585b92 6268 }
988a2cae
GN		 6269 kvm_for_each_vcpu(i, vcpu, kvm)
6270 kvm_arch_vcpu_free(vcpu);
6271
6272 mutex_lock(&kvm->lock);
6273 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6274 kvm->vcpus[i] = NULL;
d19a9cd2 6275
988a2cae
GN		 6276 atomic_set(&kvm->online_vcpus, 0);
6277 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6278}
6279
ad8ba2cd
SY		 6280void kvm_arch_sync_events(struct kvm *kvm)
6281{
ba4cef31 6282 kvm_free_all_assigned_devices(kvm);
aea924f6 6283 kvm_free_pit(kvm);
ad8ba2cd
SY		 6284}
6285
d19a9cd2
ZX		 6286void kvm_arch_destroy_vm(struct kvm *kvm)
6287{
6eb55818 6288 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6289 kfree(kvm->arch.vpic);
6290 kfree(kvm->arch.vioapic);
d19a9cd2 6291 kvm_free_vcpus(kvm);
3d45830c
AK		 6292 if (kvm->arch.apic_access_page)
6293 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6294 if (kvm->arch.ept_identity_pagetable)
6295 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6296}
0de10343 6297
db3fe4eb
TY		 6298void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6299 struct kvm_memory_slot *dont)
6300{
6301 int i;
6302
d89cc617
TY		 6303 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6304 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6305 kvm_kvfree(free->arch.rmap[i]);
6306 free->arch.rmap[i] = NULL;
77d11309 6307 }
d89cc617
TY		 6308 if (i == 0)
6309 continue;
6310
6311 if (!dont || free->arch.lpage_info[i - 1] !=
6312 dont->arch.lpage_info[i - 1]) {
6313 kvm_kvfree(free->arch.lpage_info[i - 1]);
6314 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6315 }
6316 }
6317}
6318
6319int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6320{
6321 int i;
6322
d89cc617 6323 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6324 unsigned long ugfn;
6325 int lpages;
d89cc617 6326 int level = i + 1;
db3fe4eb
TY		 6327
6328 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6329 slot->base_gfn, level) + 1;
6330
d89cc617
TY		 6331 slot->arch.rmap[i] =
6332 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6333 if (!slot->arch.rmap[i])
77d11309 6334 goto out_free;
d89cc617
TY		 6335 if (i == 0)
6336 continue;
77d11309 6337
d89cc617
TY		 6338 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6339 sizeof(*slot->arch.lpage_info[i - 1]));
6340 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6341 goto out_free;
6342
6343 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6344 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6345 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6346 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6347 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6348 /*
6349 * If the gfn and userspace address are not aligned wrt each
6350 * other, or if explicitly asked to, disable large page
6351 * support for this slot
6352 */
6353 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6354 !kvm_largepages_enabled()) {
6355 unsigned long j;
6356
6357 for (j = 0; j < lpages; ++j)
d89cc617 6358 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6359 }
6360 }
6361
6362 return 0;
6363
6364out_free:
d89cc617
TY		 6365 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6366 kvm_kvfree(slot->arch.rmap[i]);
6367 slot->arch.rmap[i] = NULL;
6368 if (i == 0)
6369 continue;
6370
6371 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6372 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6373 }
6374 return -ENOMEM;
6375}
6376
f7784b8e
MT		 6377int kvm_arch_prepare_memory_region(struct kvm *kvm,
6378 struct kvm_memory_slot *memslot,
0de10343 6379 struct kvm_memory_slot old,
f7784b8e 6380 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6381 int user_alloc)
6382{
f7784b8e 6383 int npages = memslot->npages;
7ac77099
AK		 6384 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6385
6386 /* Prevent internal slot pages from being moved by fork()/COW. */
6387 if (memslot->id >= KVM_MEMORY_SLOTS)
6388 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6389
6390 /*To keep backward compatibility with older userspace,
4a969980 6391 *x86 needs to handle !user_alloc case.
0de10343
ZX		 6392 */
6393 if (!user_alloc) {
aab2eb7a 6394 if (npages && !old.npages) {
604b38ac
AA		 6395 unsigned long userspace_addr;
6396
6be5ceb0 6397 userspace_addr = vm_mmap(NULL, 0,
604b38ac
AA		 6398 npages * PAGE_SIZE,
6399 PROT_READ | PROT_WRITE,
7ac77099 6400 map_flags,
604b38ac 6401 0);
0de10343 6402
604b38ac
AA		 6403 if (IS_ERR((void *)userspace_addr))
6404 return PTR_ERR((void *)userspace_addr);
6405
604b38ac 6406 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6407 }
6408 }
6409
f7784b8e
MT		 6410
6411 return 0;
6412}
6413
6414void kvm_arch_commit_memory_region(struct kvm *kvm,
6415 struct kvm_userspace_memory_region *mem,
6416 struct kvm_memory_slot old,
6417 int user_alloc)
6418{
6419
48c0e4e9 6420 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e 6421
aab2eb7a 6422 if (!user_alloc && !old.user_alloc && old.npages && !npages) {
f7784b8e
MT		 6423 int ret;
6424
bfce281c 6425 ret = vm_munmap(old.userspace_addr,
f7784b8e 6426 old.npages * PAGE_SIZE);
f7784b8e
MT		 6427 if (ret < 0)
6428 printk(KERN_WARNING
6429 "kvm_vm_ioctl_set_memory_region: "
6430 "failed to munmap memory\n");
6431 }
6432
48c0e4e9
XG		 6433 if (!kvm->arch.n_requested_mmu_pages)
6434 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6435
7c8a83b7 6436 spin_lock(&kvm->mmu_lock);
48c0e4e9 6437 if (nr_mmu_pages)
0de10343 6438 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6439 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6440 spin_unlock(&kvm->mmu_lock);
0de10343 6441}
1d737c8a 6442
34d4cb8f
MT		 6443void kvm_arch_flush_shadow(struct kvm *kvm)
6444{
6445 kvm_mmu_zap_all(kvm);
8986ecc0 6446 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6447}
6448
1d737c8a
ZX		 6449int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6450{
af585b92
GN		 6451 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6452 !vcpu->arch.apf.halted)
6453 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6454 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6455 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6456 (kvm_arch_interrupt_allowed(vcpu) &&
6457 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6458}
5736199a 6459
b6d33834 6460int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 6461{
b6d33834 6462 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 6463}
78646121
GN		 6464
6465int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6466{
6467 return kvm_x86_ops->interrupt_allowed(vcpu);
6468}
229456fc 6469
f92653ee
JK		 6470bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6471{
6472 unsigned long current_rip = kvm_rip_read(vcpu) +
6473 get_segment_base(vcpu, VCPU_SREG_CS);
6474
6475 return current_rip == linear_rip;
6476}
6477EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6478
94fe45da
JK		 6479unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6480{
6481 unsigned long rflags;
6482
6483 rflags = kvm_x86_ops->get_rflags(vcpu);
6484 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6485 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6486 return rflags;
6487}
6488EXPORT_SYMBOL_GPL(kvm_get_rflags);
6489
6490void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6491{
6492 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6493 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6494 rflags |= X86_EFLAGS_TF;
94fe45da 6495 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6496 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6497}
6498EXPORT_SYMBOL_GPL(kvm_set_rflags);
6499
56028d08
GN		 6500void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6501{
6502 int r;
6503
fb67e14f 6504 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6505 is_error_page(work->page))
56028d08
GN		 6506 return;
6507
6508 r = kvm_mmu_reload(vcpu);
6509 if (unlikely(r))
6510 return;
6511
fb67e14f
XG		 6512 if (!vcpu->arch.mmu.direct_map &&
6513 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6514 return;
6515
56028d08
GN		 6516 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6517}
6518
af585b92
GN		 6519static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6520{
6521 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6522}
6523
6524static inline u32 kvm_async_pf_next_probe(u32 key)
6525{
6526 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6527}
6528
6529static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6530{
6531 u32 key = kvm_async_pf_hash_fn(gfn);
6532
6533 while (vcpu->arch.apf.gfns[key] != ~0)
6534 key = kvm_async_pf_next_probe(key);
6535
6536 vcpu->arch.apf.gfns[key] = gfn;
6537}
6538
6539static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6540{
6541 int i;
6542 u32 key = kvm_async_pf_hash_fn(gfn);
6543
6544 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6545 (vcpu->arch.apf.gfns[key] != gfn &&
6546 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6547 key = kvm_async_pf_next_probe(key);
6548
6549 return key;
6550}
6551
6552bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6553{
6554 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6555}
6556
6557static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6558{
6559 u32 i, j, k;
6560
6561 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6562 while (true) {
6563 vcpu->arch.apf.gfns[i] = ~0;
6564 do {
6565 j = kvm_async_pf_next_probe(j);
6566 if (vcpu->arch.apf.gfns[j] == ~0)
6567 return;
6568 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6569 /*
6570 * k lies cyclically in ]i,j]
6571 * | i.k.j |
6572 * |....j i.k.| or |.k..j i...|
6573 */
6574 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6575 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6576 i = j;
6577 }
6578}
6579
7c90705b
GN		 6580static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6581{
6582
6583 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6584 sizeof(val));
6585}
6586
af585b92
GN		 6587void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6588 struct kvm_async_pf *work)
6589{
6389ee94
AK		 6590 struct x86_exception fault;
6591
7c90705b 6592 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6593 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6594
6595 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6596 (vcpu->arch.apf.send_user_only &&
6597 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6598 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6599 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6600 fault.vector = PF_VECTOR;
6601 fault.error_code_valid = true;
6602 fault.error_code = 0;
6603 fault.nested_page_fault = false;
6604 fault.address = work->arch.token;
6605 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6606 }
af585b92
GN		 6607}
6608
6609void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6610 struct kvm_async_pf *work)
6611{
6389ee94
AK		 6612 struct x86_exception fault;
6613
7c90705b
GN		 6614 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6615 if (is_error_page(work->page))
6616 work->arch.token = ~0; /* broadcast wakeup */
6617 else
6618 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6619
6620 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6621 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6622 fault.vector = PF_VECTOR;
6623 fault.error_code_valid = true;
6624 fault.error_code = 0;
6625 fault.nested_page_fault = false;
6626 fault.address = work->arch.token;
6627 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6628 }
e6d53e3b 6629 vcpu->arch.apf.halted = false;
a4fa1635 6630 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 6631}
6632
6633bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6634{
6635 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6636 return true;
6637 else
6638 return !kvm_event_needs_reinjection(vcpu) &&
6639 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6640}
6641
229456fc
MT		 6642EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6643EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6644EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6645EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6646EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6647EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6648EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6649EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6650EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6651EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6652EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6653EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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