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Merge tag 'for-4.2' of git://git.infradead.org/battery-2.6
[mirror_ubuntu-focal-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
0bed3b56 60#include <asm/mtrr.h>
890ca9ae 61#include <asm/mce.h>
f89e32e0 62#include <linux/kernel_stat.h>
78f7f1e5 63#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
92a1f12d
JR		 101bool kvm_has_tsc_control;
102EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103u32 kvm_max_guest_tsc_khz;
104EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
cc578287
ZA		 106/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107static u32 tsc_tolerance_ppm = 250;
108module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
d0659d94
MT		 110/* lapic timer advance (tscdeadline mode only) in nanoseconds */
111unsigned int lapic_timer_advance_ns = 0;
112module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
113
16a96021
MT		 114static bool backwards_tsc_observed = false;
115
18863bdd
AK		 116#define KVM_NR_SHARED_MSRS 16
117
118struct kvm_shared_msrs_global {
119 int nr;
2bf78fa7 120 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 121};
122
123struct kvm_shared_msrs {
124 struct user_return_notifier urn;
125 bool registered;
2bf78fa7
SY		 126 struct kvm_shared_msr_values {
127 u64 host;
128 u64 curr;
129 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 130};
131
132static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 133static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 134
417bc304 135struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 136 { "pf_fixed", VCPU_STAT(pf_fixed) },
137 { "pf_guest", VCPU_STAT(pf_guest) },
138 { "tlb_flush", VCPU_STAT(tlb_flush) },
139 { "invlpg", VCPU_STAT(invlpg) },
140 { "exits", VCPU_STAT(exits) },
141 { "io_exits", VCPU_STAT(io_exits) },
142 { "mmio_exits", VCPU_STAT(mmio_exits) },
143 { "signal_exits", VCPU_STAT(signal_exits) },
144 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 145 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 146 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 147 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 148 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 149 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 150 { "request_irq", VCPU_STAT(request_irq_exits) },
151 { "irq_exits", VCPU_STAT(irq_exits) },
152 { "host_state_reload", VCPU_STAT(host_state_reload) },
153 { "efer_reload", VCPU_STAT(efer_reload) },
154 { "fpu_reload", VCPU_STAT(fpu_reload) },
155 { "insn_emulation", VCPU_STAT(insn_emulation) },
156 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 157 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 158 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 159 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
160 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
161 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
162 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
163 { "mmu_flooded", VM_STAT(mmu_flooded) },
164 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 165 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 166 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 167 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 168 { "largepages", VM_STAT(lpages) },
417bc304
HB		 169 { NULL }
170};
171
2acf923e
DC		 172u64 __read_mostly host_xcr0;
173
b6785def 174static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 175
af585b92
GN		 176static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
177{
178 int i;
179 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
180 vcpu->arch.apf.gfns[i] = ~0;
181}
182
18863bdd
AK		 183static void kvm_on_user_return(struct user_return_notifier *urn)
184{
185 unsigned slot;
18863bdd
AK		 186 struct kvm_shared_msrs *locals
187 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 188 struct kvm_shared_msr_values *values;
18863bdd
AK		 189
190 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 191 values = &locals->values[slot];
192 if (values->host != values->curr) {
193 wrmsrl(shared_msrs_global.msrs[slot], values->host);
194 values->curr = values->host;
18863bdd
AK		 195 }
196 }
197 locals->registered = false;
198 user_return_notifier_unregister(urn);
199}
200
2bf78fa7 201static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 202{
18863bdd 203 u64 value;
013f6a5d
MT		 204 unsigned int cpu = smp_processor_id();
205 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 206
2bf78fa7
SY		 207 /* only read, and nobody should modify it at this time,
208 * so don't need lock */
209 if (slot >= shared_msrs_global.nr) {
210 printk(KERN_ERR "kvm: invalid MSR slot!");
211 return;
212 }
213 rdmsrl_safe(msr, &value);
214 smsr->values[slot].host = value;
215 smsr->values[slot].curr = value;
216}
217
218void kvm_define_shared_msr(unsigned slot, u32 msr)
219{
0123be42 220 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 221 if (slot >= shared_msrs_global.nr)
222 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 223 shared_msrs_global.msrs[slot] = msr;
224 /* we need ensured the shared_msr_global have been updated */
225 smp_wmb();
18863bdd
AK		 226}
227EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
228
229static void kvm_shared_msr_cpu_online(void)
230{
231 unsigned i;
18863bdd
AK		 232
233 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 234 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 235}
236
8b3c3104 237int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 238{
013f6a5d
MT		 239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 241 int err;
18863bdd 242
2bf78fa7 243 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 244 return 0;
2bf78fa7 245 smsr->values[slot].curr = value;
8b3c3104
AH		 246 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
247 if (err)
248 return 1;
249
18863bdd
AK		 250 if (!smsr->registered) {
251 smsr->urn.on_user_return = kvm_on_user_return;
252 user_return_notifier_register(&smsr->urn);
253 smsr->registered = true;
254 }
8b3c3104 255 return 0;
18863bdd
AK		 256}
257EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
258
13a34e06 259static void drop_user_return_notifiers(void)
3548bab5 260{
013f6a5d
MT		 261 unsigned int cpu = smp_processor_id();
262 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 263
264 if (smsr->registered)
265 kvm_on_user_return(&smsr->urn);
266}
267
6866b83e
CO		 268u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
269{
8a5a87d9 270 return vcpu->arch.apic_base;
6866b83e
CO		 271}
272EXPORT_SYMBOL_GPL(kvm_get_apic_base);
273
58cb628d
JK		 274int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
275{
276 u64 old_state = vcpu->arch.apic_base &
277 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
278 u64 new_state = msr_info->data &
279 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
280 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
281 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
282
283 if (!msr_info->host_initiated &&
284 ((msr_info->data & reserved_bits) != 0 ||
285 new_state == X2APIC_ENABLE ||
286 (new_state == MSR_IA32_APICBASE_ENABLE &&
287 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
288 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
289 old_state == 0)))
290 return 1;
291
292 kvm_lapic_set_base(vcpu, msr_info->data);
293 return 0;
6866b83e
CO		 294}
295EXPORT_SYMBOL_GPL(kvm_set_apic_base);
296
2605fc21 297asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 298{
299 /* Fault while not rebooting. We want the trace. */
300 BUG();
301}
302EXPORT_SYMBOL_GPL(kvm_spurious_fault);
303
3fd28fce
ED		 304#define EXCPT_BENIGN 0
305#define EXCPT_CONTRIBUTORY 1
306#define EXCPT_PF 2
307
308static int exception_class(int vector)
309{
310 switch (vector) {
311 case PF_VECTOR:
312 return EXCPT_PF;
313 case DE_VECTOR:
314 case TS_VECTOR:
315 case NP_VECTOR:
316 case SS_VECTOR:
317 case GP_VECTOR:
318 return EXCPT_CONTRIBUTORY;
319 default:
320 break;
321 }
322 return EXCPT_BENIGN;
323}
324
d6e8c854
NA		 325#define EXCPT_FAULT 0
326#define EXCPT_TRAP 1
327#define EXCPT_ABORT 2
328#define EXCPT_INTERRUPT 3
329
330static int exception_type(int vector)
331{
332 unsigned int mask;
333
334 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
335 return EXCPT_INTERRUPT;
336
337 mask = 1 << vector;
338
339 /* #DB is trap, as instruction watchpoints are handled elsewhere */
340 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
341 return EXCPT_TRAP;
342
343 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
344 return EXCPT_ABORT;
345
346 /* Reserved exceptions will result in fault */
347 return EXCPT_FAULT;
348}
349
3fd28fce 350static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 351 unsigned nr, bool has_error, u32 error_code,
352 bool reinject)
3fd28fce
ED		 353{
354 u32 prev_nr;
355 int class1, class2;
356
3842d135
AK		 357 kvm_make_request(KVM_REQ_EVENT, vcpu);
358
3fd28fce
ED		 359 if (!vcpu->arch.exception.pending) {
360 queue:
3ffb2468
NA		 361 if (has_error && !is_protmode(vcpu))
362 has_error = false;
3fd28fce
ED		 363 vcpu->arch.exception.pending = true;
364 vcpu->arch.exception.has_error_code = has_error;
365 vcpu->arch.exception.nr = nr;
366 vcpu->arch.exception.error_code = error_code;
3f0fd292 367 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 368 return;
369 }
370
371 /* to check exception */
372 prev_nr = vcpu->arch.exception.nr;
373 if (prev_nr == DF_VECTOR) {
374 /* triple fault -> shutdown */
a8eeb04a 375 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 376 return;
377 }
378 class1 = exception_class(prev_nr);
379 class2 = exception_class(nr);
380 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
381 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
382 /* generate double fault per SDM Table 5-5 */
383 vcpu->arch.exception.pending = true;
384 vcpu->arch.exception.has_error_code = true;
385 vcpu->arch.exception.nr = DF_VECTOR;
386 vcpu->arch.exception.error_code = 0;
387 } else
388 /* replace previous exception with a new one in a hope
389 that instruction re-execution will regenerate lost
390 exception */
391 goto queue;
392}
393
298101da
AK		 394void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
395{
ce7ddec4 396 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 397}
398EXPORT_SYMBOL_GPL(kvm_queue_exception);
399
ce7ddec4
JR		 400void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
401{
402 kvm_multiple_exception(vcpu, nr, false, 0, true);
403}
404EXPORT_SYMBOL_GPL(kvm_requeue_exception);
405
db8fcefa 406void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 407{
db8fcefa
AP		 408 if (err)
409 kvm_inject_gp(vcpu, 0);
410 else
411 kvm_x86_ops->skip_emulated_instruction(vcpu);
412}
413EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 414
6389ee94 415void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 416{
417 ++vcpu->stat.pf_guest;
6389ee94
AK		 418 vcpu->arch.cr2 = fault->address;
419 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 420}
27d6c865 421EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 422
ef54bcfe 423static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 424{
6389ee94
AK		 425 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
426 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 427 else
6389ee94 428 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 429
430 return fault->nested_page_fault;
d4f8cf66
JR		 431}
432
3419ffc8
SY		 433void kvm_inject_nmi(struct kvm_vcpu *vcpu)
434{
7460fb4a
AK		 435 atomic_inc(&vcpu->arch.nmi_queued);
436 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 437}
438EXPORT_SYMBOL_GPL(kvm_inject_nmi);
439
298101da
AK		 440void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
441{
ce7ddec4 442 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 443}
444EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
445
ce7ddec4
JR		 446void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
447{
448 kvm_multiple_exception(vcpu, nr, true, error_code, true);
449}
450EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
451
0a79b009
AK		 452/*
453 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
454 * a #GP and return false.
455 */
456bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 457{
0a79b009
AK		 458 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
459 return true;
460 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
461 return false;
298101da 462}
0a79b009 463EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 464
16f8a6f9
NA		 465bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
466{
467 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
468 return true;
469
470 kvm_queue_exception(vcpu, UD_VECTOR);
471 return false;
472}
473EXPORT_SYMBOL_GPL(kvm_require_dr);
474
ec92fe44
JR		 475/*
476 * This function will be used to read from the physical memory of the currently
477 * running guest. The difference to kvm_read_guest_page is that this function
478 * can read from guest physical or from the guest's guest physical memory.
479 */
480int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
481 gfn_t ngfn, void *data, int offset, int len,
482 u32 access)
483{
54987b7a 484 struct x86_exception exception;
ec92fe44
JR		 485 gfn_t real_gfn;
486 gpa_t ngpa;
487
488 ngpa = gfn_to_gpa(ngfn);
54987b7a 489 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 490 if (real_gfn == UNMAPPED_GVA)
491 return -EFAULT;
492
493 real_gfn = gpa_to_gfn(real_gfn);
494
495 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
496}
497EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
498
69b0049a 499static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 500 void *data, int offset, int len, u32 access)
501{
502 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
503 data, offset, len, access);
504}
505
a03490ed
CO		 506/*
507 * Load the pae pdptrs. Return true is they are all valid.
508 */
ff03a073 509int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 510{
511 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
512 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
513 int i;
514 int ret;
ff03a073 515 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 516
ff03a073
JR		 517 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
518 offset * sizeof(u64), sizeof(pdpte),
519 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 520 if (ret < 0) {
521 ret = 0;
522 goto out;
523 }
524 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 525 if (is_present_gpte(pdpte[i]) &&
20c466b5 526 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 527 ret = 0;
528 goto out;
529 }
530 }
531 ret = 1;
532
ff03a073 533 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 534 __set_bit(VCPU_EXREG_PDPTR,
535 (unsigned long *)&vcpu->arch.regs_avail);
536 __set_bit(VCPU_EXREG_PDPTR,
537 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 538out:
a03490ed
CO		 539
540 return ret;
541}
cc4b6871 542EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 543
d835dfec
AK		 544static bool pdptrs_changed(struct kvm_vcpu *vcpu)
545{
ff03a073 546 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 547 bool changed = true;
3d06b8bf
JR		 548 int offset;
549 gfn_t gfn;
d835dfec
AK		 550 int r;
551
552 if (is_long_mode(vcpu) || !is_pae(vcpu))
553 return false;
554
6de4f3ad
AK		 555 if (!test_bit(VCPU_EXREG_PDPTR,
556 (unsigned long *)&vcpu->arch.regs_avail))
557 return true;
558
9f8fe504
AK		 559 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
560 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 561 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
562 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 563 if (r < 0)
564 goto out;
ff03a073 565 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 566out:
d835dfec
AK		 567
568 return changed;
569}
570
49a9b07e 571int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 572{
aad82703
SY		 573 unsigned long old_cr0 = kvm_read_cr0(vcpu);
574 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
575 X86_CR0_CD | X86_CR0_NW;
576
f9a48e6a
AK		 577 cr0 |= X86_CR0_ET;
578
ab344828 579#ifdef CONFIG_X86_64
0f12244f
GN		 580 if (cr0 & 0xffffffff00000000UL)
581 return 1;
ab344828
GN		 582#endif
583
584 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 585
0f12244f
GN		 586 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
587 return 1;
a03490ed 588
0f12244f
GN		 589 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
590 return 1;
a03490ed
CO		 591
592 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
593#ifdef CONFIG_X86_64
f6801dff 594 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 595 int cs_db, cs_l;
596
0f12244f
GN		 597 if (!is_pae(vcpu))
598 return 1;
a03490ed 599 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 600 if (cs_l)
601 return 1;
a03490ed
CO		 602 } else
603#endif
ff03a073 604 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 605 kvm_read_cr3(vcpu)))
0f12244f 606 return 1;
a03490ed
CO		 607 }
608
ad756a16
MJ		 609 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
610 return 1;
611
a03490ed 612 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 613
d170c419 614 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 615 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 616 kvm_async_pf_hash_reset(vcpu);
617 }
e5f3f027 618
aad82703
SY		 619 if ((cr0 ^ old_cr0) & update_bits)
620 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 621 return 0;
622}
2d3ad1f4 623EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 624
2d3ad1f4 625void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 626{
49a9b07e 627 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 628}
2d3ad1f4 629EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 630
42bdf991
MT		 631static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
632{
633 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
634 !vcpu->guest_xcr0_loaded) {
635 /* kvm_set_xcr() also depends on this */
636 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
637 vcpu->guest_xcr0_loaded = 1;
638 }
639}
640
641static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
642{
643 if (vcpu->guest_xcr0_loaded) {
644 if (vcpu->arch.xcr0 != host_xcr0)
645 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
646 vcpu->guest_xcr0_loaded = 0;
647 }
648}
649
69b0049a 650static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 651{
56c103ec
LJ		 652 u64 xcr0 = xcr;
653 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 654 u64 valid_bits;
2acf923e
DC		 655
656 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
657 if (index != XCR_XFEATURE_ENABLED_MASK)
658 return 1;
2acf923e
DC		 659 if (!(xcr0 & XSTATE_FP))
660 return 1;
661 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
662 return 1;
46c34cb0
PB		 663
664 /*
665 * Do not allow the guest to set bits that we do not support
666 * saving. However, xcr0 bit 0 is always set, even if the
667 * emulated CPU does not support XSAVE (see fx_init).
668 */
669 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
670 if (xcr0 & ~valid_bits)
2acf923e 671 return 1;
46c34cb0 672
390bd528
LJ		 673 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
674 return 1;
675
612263b3
CP		 676 if (xcr0 & XSTATE_AVX512) {
677 if (!(xcr0 & XSTATE_YMM))
678 return 1;
679 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
680 return 1;
681 }
42bdf991 682 kvm_put_guest_xcr0(vcpu);
2acf923e 683 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 684
685 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
686 kvm_update_cpuid(vcpu);
2acf923e
DC		 687 return 0;
688}
689
690int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
691{
764bcbc5
Z		 692 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
693 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 694 kvm_inject_gp(vcpu, 0);
695 return 1;
696 }
697 return 0;
698}
699EXPORT_SYMBOL_GPL(kvm_set_xcr);
700
a83b29c6 701int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 702{
fc78f519 703 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 704 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
705 X86_CR4_SMEP | X86_CR4_SMAP;
706
0f12244f
GN		 707 if (cr4 & CR4_RESERVED_BITS)
708 return 1;
a03490ed 709
2acf923e
DC		 710 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
711 return 1;
712
c68b734f
YW		 713 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
714 return 1;
715
97ec8c06
FW		 716 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
717 return 1;
718
afcbf13f 719 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 720 return 1;
721
a03490ed 722 if (is_long_mode(vcpu)) {
0f12244f
GN		 723 if (!(cr4 & X86_CR4_PAE))
724 return 1;
a2edf57f
AK		 725 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
726 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 727 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
728 kvm_read_cr3(vcpu)))
0f12244f
GN		 729 return 1;
730
ad756a16
MJ		 731 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
732 if (!guest_cpuid_has_pcid(vcpu))
733 return 1;
734
735 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
736 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
737 return 1;
738 }
739
5e1746d6 740 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 741 return 1;
a03490ed 742
ad756a16
MJ		 743 if (((cr4 ^ old_cr4) & pdptr_bits) ||
744 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 745 kvm_mmu_reset_context(vcpu);
0f12244f 746
2acf923e 747 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 748 kvm_update_cpuid(vcpu);
2acf923e 749
0f12244f
GN		 750 return 0;
751}
2d3ad1f4 752EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 753
2390218b 754int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 755{
ac146235 756#ifdef CONFIG_X86_64
9d88fca7 757 cr3 &= ~CR3_PCID_INVD;
ac146235 758#endif
9d88fca7 759
9f8fe504 760 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 761 kvm_mmu_sync_roots(vcpu);
77c3913b 762 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 763 return 0;
d835dfec
AK		 764 }
765
a03490ed 766 if (is_long_mode(vcpu)) {
d9f89b88
JK		 767 if (cr3 & CR3_L_MODE_RESERVED_BITS)
768 return 1;
769 } else if (is_pae(vcpu) && is_paging(vcpu) &&
770 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 771 return 1;
a03490ed 772
0f12244f 773 vcpu->arch.cr3 = cr3;
aff48baa 774 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 775 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 776 return 0;
777}
2d3ad1f4 778EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 779
eea1cff9 780int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 781{
0f12244f
GN		 782 if (cr8 & CR8_RESERVED_BITS)
783 return 1;
a03490ed
CO		 784 if (irqchip_in_kernel(vcpu->kvm))
785 kvm_lapic_set_tpr(vcpu, cr8);
786 else
ad312c7c 787 vcpu->arch.cr8 = cr8;
0f12244f
GN		 788 return 0;
789}
2d3ad1f4 790EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 791
2d3ad1f4 792unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 793{
794 if (irqchip_in_kernel(vcpu->kvm))
795 return kvm_lapic_get_cr8(vcpu);
796 else
ad312c7c 797 return vcpu->arch.cr8;
a03490ed 798}
2d3ad1f4 799EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 800
ae561ede
NA		 801static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
802{
803 int i;
804
805 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
806 for (i = 0; i < KVM_NR_DB_REGS; i++)
807 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
808 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
809 }
810}
811
73aaf249
JK		 812static void kvm_update_dr6(struct kvm_vcpu *vcpu)
813{
814 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
815 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
816}
817
c8639010
JK		 818static void kvm_update_dr7(struct kvm_vcpu *vcpu)
819{
820 unsigned long dr7;
821
822 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
823 dr7 = vcpu->arch.guest_debug_dr7;
824 else
825 dr7 = vcpu->arch.dr7;
826 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 827 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
828 if (dr7 & DR7_BP_EN_MASK)
829 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 830}
831
6f43ed01
NA		 832static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
833{
834 u64 fixed = DR6_FIXED_1;
835
836 if (!guest_cpuid_has_rtm(vcpu))
837 fixed |= DR6_RTM;
838 return fixed;
839}
840
338dbc97 841static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 842{
843 switch (dr) {
844 case 0 ... 3:
845 vcpu->arch.db[dr] = val;
846 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
847 vcpu->arch.eff_db[dr] = val;
848 break;
849 case 4:
020df079
GN		 850 /* fall through */
851 case 6:
338dbc97
GN		 852 if (val & 0xffffffff00000000ULL)
853 return -1; /* #GP */
6f43ed01 854 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 855 kvm_update_dr6(vcpu);
020df079
GN		 856 break;
857 case 5:
020df079
GN		 858 /* fall through */
859 default: /* 7 */
338dbc97
GN		 860 if (val & 0xffffffff00000000ULL)
861 return -1; /* #GP */
020df079 862 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 863 kvm_update_dr7(vcpu);
020df079
GN		 864 break;
865 }
866
867 return 0;
868}
338dbc97
GN		 869
870int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
871{
16f8a6f9 872 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 873 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 874 return 1;
875 }
876 return 0;
338dbc97 877}
020df079
GN		 878EXPORT_SYMBOL_GPL(kvm_set_dr);
879
16f8a6f9 880int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 881{
882 switch (dr) {
883 case 0 ... 3:
884 *val = vcpu->arch.db[dr];
885 break;
886 case 4:
020df079
GN		 887 /* fall through */
888 case 6:
73aaf249
JK		 889 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
890 *val = vcpu->arch.dr6;
891 else
892 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 893 break;
894 case 5:
020df079
GN		 895 /* fall through */
896 default: /* 7 */
897 *val = vcpu->arch.dr7;
898 break;
899 }
338dbc97
GN		 900 return 0;
901}
020df079
GN		 902EXPORT_SYMBOL_GPL(kvm_get_dr);
903
022cd0e8
AK		 904bool kvm_rdpmc(struct kvm_vcpu *vcpu)
905{
906 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
907 u64 data;
908 int err;
909
910 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
911 if (err)
912 return err;
913 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
914 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
915 return err;
916}
917EXPORT_SYMBOL_GPL(kvm_rdpmc);
918
043405e1
CO		 919/*
920 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
921 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
922 *
923 * This list is modified at module load time to reflect the
e3267cbb
GC		 924 * capabilities of the host cpu. This capabilities test skips MSRs that are
925 * kvm-specific. Those are put in the beginning of the list.
043405e1 926 */
e3267cbb 927
e984097b 928#define KVM_SAVE_MSRS_BEGIN 12
043405e1 929static u32 msrs_to_save[] = {
e3267cbb 930 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 931 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 932 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 933 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 934 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 935 MSR_KVM_PV_EOI_EN,
043405e1 936 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 937 MSR_STAR,
043405e1
CO		 938#ifdef CONFIG_X86_64
939 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
940#endif
b3897a49 941 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 942 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 943};
944
945static unsigned num_msrs_to_save;
946
f1d24831 947static const u32 emulated_msrs[] = {
ba904635 948 MSR_IA32_TSC_ADJUST,
a3e06bbe 949 MSR_IA32_TSCDEADLINE,
043405e1 950 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 951 MSR_IA32_MCG_STATUS,
952 MSR_IA32_MCG_CTL,
043405e1
CO		 953};
954
384bb783 955bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 956{
b69e8cae 957 if (efer & efer_reserved_bits)
384bb783 958 return false;
15c4a640 959
1b2fd70c
AG		 960 if (efer & EFER_FFXSR) {
961 struct kvm_cpuid_entry2 *feat;
962
963 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 964 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 965 return false;
1b2fd70c
AG		 966 }
967
d8017474
AG		 968 if (efer & EFER_SVME) {
969 struct kvm_cpuid_entry2 *feat;
970
971 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 972 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 973 return false;
d8017474
AG		 974 }
975
384bb783
JK		 976 return true;
977}
978EXPORT_SYMBOL_GPL(kvm_valid_efer);
979
980static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
981{
982 u64 old_efer = vcpu->arch.efer;
983
984 if (!kvm_valid_efer(vcpu, efer))
985 return 1;
986
987 if (is_paging(vcpu)
988 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
989 return 1;
990
15c4a640 991 efer &= ~EFER_LMA;
f6801dff 992 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 993
a3d204e2
SY		 994 kvm_x86_ops->set_efer(vcpu, efer);
995
aad82703
SY		 996 /* Update reserved bits */
997 if ((efer ^ old_efer) & EFER_NX)
998 kvm_mmu_reset_context(vcpu);
999
b69e8cae 1000 return 0;
15c4a640
CO		 1001}
1002
f2b4b7dd
JR		 1003void kvm_enable_efer_bits(u64 mask)
1004{
1005 efer_reserved_bits &= ~mask;
1006}
1007EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1008
15c4a640
CO		 1009/*
1010 * Writes msr value into into the appropriate "register".
1011 * Returns 0 on success, non-0 otherwise.
1012 * Assumes vcpu_load() was already called.
1013 */
8fe8ab46 1014int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1015{
854e8bb1
NA		 1016 switch (msr->index) {
1017 case MSR_FS_BASE:
1018 case MSR_GS_BASE:
1019 case MSR_KERNEL_GS_BASE:
1020 case MSR_CSTAR:
1021 case MSR_LSTAR:
1022 if (is_noncanonical_address(msr->data))
1023 return 1;
1024 break;
1025 case MSR_IA32_SYSENTER_EIP:
1026 case MSR_IA32_SYSENTER_ESP:
1027 /*
1028 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1029 * non-canonical address is written on Intel but not on
1030 * AMD (which ignores the top 32-bits, because it does
1031 * not implement 64-bit SYSENTER).
1032 *
1033 * 64-bit code should hence be able to write a non-canonical
1034 * value on AMD. Making the address canonical ensures that
1035 * vmentry does not fail on Intel after writing a non-canonical
1036 * value, and that something deterministic happens if the guest
1037 * invokes 64-bit SYSENTER.
1038 */
1039 msr->data = get_canonical(msr->data);
1040 }
8fe8ab46 1041 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1042}
854e8bb1 1043EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1044
313a3dc7
CO		 1045/*
1046 * Adapt set_msr() to msr_io()'s calling convention
1047 */
1048static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1049{
8fe8ab46
WA		 1050 struct msr_data msr;
1051
1052 msr.data = *data;
1053 msr.index = index;
1054 msr.host_initiated = true;
1055 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1056}
1057
16e8d74d
MT		 1058#ifdef CONFIG_X86_64
1059struct pvclock_gtod_data {
1060 seqcount_t seq;
1061
1062 struct { /* extract of a clocksource struct */
1063 int vclock_mode;
1064 cycle_t cycle_last;
1065 cycle_t mask;
1066 u32 mult;
1067 u32 shift;
1068 } clock;
1069
cbcf2dd3
TG		 1070 u64 boot_ns;
1071 u64 nsec_base;
16e8d74d
MT		 1072};
1073
1074static struct pvclock_gtod_data pvclock_gtod_data;
1075
1076static void update_pvclock_gtod(struct timekeeper *tk)
1077{
1078 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1079 u64 boot_ns;
1080
876e7881 1081 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1082
1083 write_seqcount_begin(&vdata->seq);
1084
1085 /* copy pvclock gtod data */
876e7881
PZ		 1086 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1087 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1088 vdata->clock.mask = tk->tkr_mono.mask;
1089 vdata->clock.mult = tk->tkr_mono.mult;
1090 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1091
cbcf2dd3 1092 vdata->boot_ns = boot_ns;
876e7881 1093 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1094
1095 write_seqcount_end(&vdata->seq);
1096}
1097#endif
1098
bab5bb39
NK		 1099void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1100{
1101 /*
1102 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1103 * vcpu_enter_guest. This function is only called from
1104 * the physical CPU that is running vcpu.
1105 */
1106 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1107}
16e8d74d 1108
18068523
GOC		 1109static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1110{
9ed3c444
AK		 1111 int version;
1112 int r;
50d0a0f9 1113 struct pvclock_wall_clock wc;
923de3cf 1114 struct timespec boot;
18068523
GOC		 1115
1116 if (!wall_clock)
1117 return;
1118
9ed3c444
AK		 1119 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1120 if (r)
1121 return;
1122
1123 if (version & 1)
1124 ++version; /* first time write, random junk */
1125
1126 ++version;
18068523 1127
18068523
GOC		 1128 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1129
50d0a0f9
GH		 1130 /*
1131 * The guest calculates current wall clock time by adding
34c238a1 1132 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1133 * wall clock specified here. guest system time equals host
1134 * system time for us, thus we must fill in host boot time here.
1135 */
923de3cf 1136 getboottime(&boot);
50d0a0f9 1137
4b648665
BR		 1138 if (kvm->arch.kvmclock_offset) {
1139 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1140 boot = timespec_sub(boot, ts);
1141 }
50d0a0f9
GH		 1142 wc.sec = boot.tv_sec;
1143 wc.nsec = boot.tv_nsec;
1144 wc.version = version;
18068523
GOC		 1145
1146 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1147
1148 version++;
1149 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1150}
1151
50d0a0f9
GH		 1152static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1153{
1154 uint32_t quotient, remainder;
1155
1156 /* Don't try to replace with do_div(), this one calculates
1157 * "(dividend << 32) / divisor" */
1158 __asm__ ( "divl %4"
1159 : "=a" (quotient), "=d" (remainder)
1160 : "0" (0), "1" (dividend), "r" (divisor) );
1161 return quotient;
1162}
1163
5f4e3f88
ZA		 1164static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1165 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1166{
5f4e3f88 1167 uint64_t scaled64;
50d0a0f9
GH		 1168 int32_t shift = 0;
1169 uint64_t tps64;
1170 uint32_t tps32;
1171
5f4e3f88
ZA		 1172 tps64 = base_khz * 1000LL;
1173 scaled64 = scaled_khz * 1000LL;
50933623 1174 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1175 tps64 >>= 1;
1176 shift--;
1177 }
1178
1179 tps32 = (uint32_t)tps64;
50933623
JK		 1180 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1181 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1182 scaled64 >>= 1;
1183 else
1184 tps32 <<= 1;
50d0a0f9
GH		 1185 shift++;
1186 }
1187
5f4e3f88
ZA		 1188 *pshift = shift;
1189 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1190
5f4e3f88
ZA		 1191 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1192 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1193}
1194
759379dd
ZA		 1195static inline u64 get_kernel_ns(void)
1196{
bb0b5812 1197 return ktime_get_boot_ns();
50d0a0f9
GH		 1198}
1199
d828199e 1200#ifdef CONFIG_X86_64
16e8d74d 1201static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1202#endif
16e8d74d 1203
c8076604 1204static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1205static unsigned long max_tsc_khz;
c8076604 1206
cc578287 1207static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1208{
cc578287
ZA		 1209 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1210 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1211}
1212
cc578287 1213static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1214{
cc578287
ZA		 1215 u64 v = (u64)khz * (1000000 + ppm);
1216 do_div(v, 1000000);
1217 return v;
1e993611
JR		 1218}
1219
cc578287 1220static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1221{
cc578287
ZA		 1222 u32 thresh_lo, thresh_hi;
1223 int use_scaling = 0;
217fc9cf 1224
03ba32ca
MT		 1225 /* tsc_khz can be zero if TSC calibration fails */
1226 if (this_tsc_khz == 0)
1227 return;
1228
c285545f
ZA		 1229 /* Compute a scale to convert nanoseconds in TSC cycles */
1230 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1231 &vcpu->arch.virtual_tsc_shift,
1232 &vcpu->arch.virtual_tsc_mult);
1233 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1234
1235 /*
1236 * Compute the variation in TSC rate which is acceptable
1237 * within the range of tolerance and decide if the
1238 * rate being applied is within that bounds of the hardware
1239 * rate. If so, no scaling or compensation need be done.
1240 */
1241 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1242 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1243 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1244 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1245 use_scaling = 1;
1246 }
1247 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1248}
1249
1250static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1251{
e26101b1 1252 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1253 vcpu->arch.virtual_tsc_mult,
1254 vcpu->arch.virtual_tsc_shift);
e26101b1 1255 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1256 return tsc;
1257}
1258
69b0049a 1259static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1260{
1261#ifdef CONFIG_X86_64
1262 bool vcpus_matched;
b48aa97e
MT		 1263 struct kvm_arch *ka = &vcpu->kvm->arch;
1264 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1265
1266 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1267 atomic_read(&vcpu->kvm->online_vcpus));
1268
7f187922
MT		 1269 /*
1270 * Once the masterclock is enabled, always perform request in
1271 * order to update it.
1272 *
1273 * In order to enable masterclock, the host clocksource must be TSC
1274 * and the vcpus need to have matched TSCs. When that happens,
1275 * perform request to enable masterclock.
1276 */
1277 if (ka->use_master_clock ||
1278 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1279 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1280
1281 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1282 atomic_read(&vcpu->kvm->online_vcpus),
1283 ka->use_master_clock, gtod->clock.vclock_mode);
1284#endif
1285}
1286
ba904635
WA		 1287static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1288{
1289 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1290 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1291}
1292
8fe8ab46 1293void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1294{
1295 struct kvm *kvm = vcpu->kvm;
f38e098f 1296 u64 offset, ns, elapsed;
99e3e30a 1297 unsigned long flags;
02626b6a 1298 s64 usdiff;
b48aa97e 1299 bool matched;
0d3da0d2 1300 bool already_matched;
8fe8ab46 1301 u64 data = msr->data;
99e3e30a 1302
038f8c11 1303 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1304 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1305 ns = get_kernel_ns();
f38e098f 1306 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1307
03ba32ca 1308 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1309 int faulted = 0;
1310
03ba32ca
MT		 1311 /* n.b - signed multiplication and division required */
1312 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1313#ifdef CONFIG_X86_64
03ba32ca 1314 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1315#else
03ba32ca 1316 /* do_div() only does unsigned */
8915aa27
MT		 1317 asm("1: idivl %[divisor]\n"
1318 "2: xor %%edx, %%edx\n"
1319 " movl $0, %[faulted]\n"
1320 "3:\n"
1321 ".section .fixup,\"ax\"\n"
1322 "4: movl $1, %[faulted]\n"
1323 " jmp 3b\n"
1324 ".previous\n"
1325
1326 _ASM_EXTABLE(1b, 4b)
1327
1328 : "=A"(usdiff), [faulted] "=r" (faulted)
1329 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1330
5d3cb0f6 1331#endif
03ba32ca
MT		 1332 do_div(elapsed, 1000);
1333 usdiff -= elapsed;
1334 if (usdiff < 0)
1335 usdiff = -usdiff;
8915aa27
MT		 1336
1337 /* idivl overflow => difference is larger than USEC_PER_SEC */
1338 if (faulted)
1339 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1340 } else
1341 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1342
1343 /*
5d3cb0f6
ZA		 1344 * Special case: TSC write with a small delta (1 second) of virtual
1345 * cycle time against real time is interpreted as an attempt to
1346 * synchronize the CPU.
1347 *
1348 * For a reliable TSC, we can match TSC offsets, and for an unstable
1349 * TSC, we add elapsed time in this computation. We could let the
1350 * compensation code attempt to catch up if we fall behind, but
1351 * it's better to try to match offsets from the beginning.
1352 */
02626b6a 1353 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1354 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1355 if (!check_tsc_unstable()) {
e26101b1 1356 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1357 pr_debug("kvm: matched tsc offset for %llu\n", data);
1358 } else {
857e4099 1359 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1360 data += delta;
1361 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1362 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1363 }
b48aa97e 1364 matched = true;
0d3da0d2 1365 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1366 } else {
1367 /*
1368 * We split periods of matched TSC writes into generations.
1369 * For each generation, we track the original measured
1370 * nanosecond time, offset, and write, so if TSCs are in
1371 * sync, we can match exact offset, and if not, we can match
4a969980 1372 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1373 *
1374 * These values are tracked in kvm->arch.cur_xxx variables.
1375 */
1376 kvm->arch.cur_tsc_generation++;
1377 kvm->arch.cur_tsc_nsec = ns;
1378 kvm->arch.cur_tsc_write = data;
1379 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1380 matched = false;
0d3da0d2 1381 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1382 kvm->arch.cur_tsc_generation, data);
f38e098f 1383 }
e26101b1
ZA		 1384
1385 /*
1386 * We also track th most recent recorded KHZ, write and time to
1387 * allow the matching interval to be extended at each write.
1388 */
f38e098f
ZA		 1389 kvm->arch.last_tsc_nsec = ns;
1390 kvm->arch.last_tsc_write = data;
5d3cb0f6 1391 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1392
b183aa58 1393 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1394
1395 /* Keep track of which generation this VCPU has synchronized to */
1396 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1397 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1398 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1399
ba904635
WA		 1400 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1401 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1402 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1403 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1404
1405 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1406 if (!matched) {
b48aa97e 1407 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1408 } else if (!already_matched) {
1409 kvm->arch.nr_vcpus_matched_tsc++;
1410 }
b48aa97e
MT		 1411
1412 kvm_track_tsc_matching(vcpu);
1413 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1414}
e26101b1 1415
99e3e30a
ZA		 1416EXPORT_SYMBOL_GPL(kvm_write_tsc);
1417
d828199e
MT		 1418#ifdef CONFIG_X86_64
1419
1420static cycle_t read_tsc(void)
1421{
1422 cycle_t ret;
1423 u64 last;
1424
1425 /*
1426 * Empirically, a fence (of type that depends on the CPU)
1427 * before rdtsc is enough to ensure that rdtsc is ordered
1428 * with respect to loads. The various CPU manuals are unclear
1429 * as to whether rdtsc can be reordered with later loads,
1430 * but no one has ever seen it happen.
1431 */
1432 rdtsc_barrier();
1433 ret = (cycle_t)vget_cycles();
1434
1435 last = pvclock_gtod_data.clock.cycle_last;
1436
1437 if (likely(ret >= last))
1438 return ret;
1439
1440 /*
1441 * GCC likes to generate cmov here, but this branch is extremely
1442 * predictable (it's just a funciton of time and the likely is
1443 * very likely) and there's a data dependence, so force GCC
1444 * to generate a branch instead. I don't barrier() because
1445 * we don't actually need a barrier, and if this function
1446 * ever gets inlined it will generate worse code.
1447 */
1448 asm volatile ("");
1449 return last;
1450}
1451
1452static inline u64 vgettsc(cycle_t *cycle_now)
1453{
1454 long v;
1455 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1456
1457 *cycle_now = read_tsc();
1458
1459 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1460 return v * gtod->clock.mult;
1461}
1462
cbcf2dd3 1463static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1464{
cbcf2dd3 1465 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1466 unsigned long seq;
d828199e 1467 int mode;
cbcf2dd3 1468 u64 ns;
d828199e 1469
d828199e
MT		 1470 do {
1471 seq = read_seqcount_begin(&gtod->seq);
1472 mode = gtod->clock.vclock_mode;
cbcf2dd3 1473 ns = gtod->nsec_base;
d828199e
MT		 1474 ns += vgettsc(cycle_now);
1475 ns >>= gtod->clock.shift;
cbcf2dd3 1476 ns += gtod->boot_ns;
d828199e 1477 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1478 *t = ns;
d828199e
MT		 1479
1480 return mode;
1481}
1482
1483/* returns true if host is using tsc clocksource */
1484static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1485{
d828199e
MT		 1486 /* checked again under seqlock below */
1487 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1488 return false;
1489
cbcf2dd3 1490 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1491}
1492#endif
1493
1494/*
1495 *
b48aa97e
MT		 1496 * Assuming a stable TSC across physical CPUS, and a stable TSC
1497 * across virtual CPUs, the following condition is possible.
1498 * Each numbered line represents an event visible to both
d828199e
MT		 1499 * CPUs at the next numbered event.
1500 *
1501 * "timespecX" represents host monotonic time. "tscX" represents
1502 * RDTSC value.
1503 *
1504 * VCPU0 on CPU0 | VCPU1 on CPU1
1505 *
1506 * 1. read timespec0,tsc0
1507 * 2. | timespec1 = timespec0 + N
1508 * | tsc1 = tsc0 + M
1509 * 3. transition to guest | transition to guest
1510 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1511 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1512 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1513 *
1514 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1515 *
1516 * - ret0 < ret1
1517 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1518 * ...
1519 * - 0 < N - M => M < N
1520 *
1521 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1522 * always the case (the difference between two distinct xtime instances
1523 * might be smaller then the difference between corresponding TSC reads,
1524 * when updating guest vcpus pvclock areas).
1525 *
1526 * To avoid that problem, do not allow visibility of distinct
1527 * system_timestamp/tsc_timestamp values simultaneously: use a master
1528 * copy of host monotonic time values. Update that master copy
1529 * in lockstep.
1530 *
b48aa97e 1531 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1532 *
1533 */
1534
1535static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1536{
1537#ifdef CONFIG_X86_64
1538 struct kvm_arch *ka = &kvm->arch;
1539 int vclock_mode;
b48aa97e
MT		 1540 bool host_tsc_clocksource, vcpus_matched;
1541
1542 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1543 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1544
1545 /*
1546 * If the host uses TSC clock, then passthrough TSC as stable
1547 * to the guest.
1548 */
b48aa97e 1549 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1550 &ka->master_kernel_ns,
1551 &ka->master_cycle_now);
1552
16a96021 1553 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1554 && !backwards_tsc_observed
1555 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1556
d828199e
MT		 1557 if (ka->use_master_clock)
1558 atomic_set(&kvm_guest_has_master_clock, 1);
1559
1560 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1561 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1562 vcpus_matched);
d828199e
MT		 1563#endif
1564}
1565
2e762ff7
MT		 1566static void kvm_gen_update_masterclock(struct kvm *kvm)
1567{
1568#ifdef CONFIG_X86_64
1569 int i;
1570 struct kvm_vcpu *vcpu;
1571 struct kvm_arch *ka = &kvm->arch;
1572
1573 spin_lock(&ka->pvclock_gtod_sync_lock);
1574 kvm_make_mclock_inprogress_request(kvm);
1575 /* no guest entries from this point */
1576 pvclock_update_vm_gtod_copy(kvm);
1577
1578 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1579 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1580
1581 /* guest entries allowed */
1582 kvm_for_each_vcpu(i, vcpu, kvm)
1583 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1584
1585 spin_unlock(&ka->pvclock_gtod_sync_lock);
1586#endif
1587}
1588
34c238a1 1589static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1590{
d828199e 1591 unsigned long flags, this_tsc_khz;
18068523 1592 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1593 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1594 s64 kernel_ns;
d828199e 1595 u64 tsc_timestamp, host_tsc;
0b79459b 1596 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1597 u8 pvclock_flags;
d828199e
MT		 1598 bool use_master_clock;
1599
1600 kernel_ns = 0;
1601 host_tsc = 0;
18068523 1602
d828199e
MT		 1603 /*
1604 * If the host uses TSC clock, then passthrough TSC as stable
1605 * to the guest.
1606 */
1607 spin_lock(&ka->pvclock_gtod_sync_lock);
1608 use_master_clock = ka->use_master_clock;
1609 if (use_master_clock) {
1610 host_tsc = ka->master_cycle_now;
1611 kernel_ns = ka->master_kernel_ns;
1612 }
1613 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1614
1615 /* Keep irq disabled to prevent changes to the clock */
1616 local_irq_save(flags);
89cbc767 1617 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1618 if (unlikely(this_tsc_khz == 0)) {
1619 local_irq_restore(flags);
1620 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1621 return 1;
1622 }
d828199e
MT		 1623 if (!use_master_clock) {
1624 host_tsc = native_read_tsc();
1625 kernel_ns = get_kernel_ns();
1626 }
1627
1628 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1629
c285545f
ZA		 1630 /*
1631 * We may have to catch up the TSC to match elapsed wall clock
1632 * time for two reasons, even if kvmclock is used.
1633 * 1) CPU could have been running below the maximum TSC rate
1634 * 2) Broken TSC compensation resets the base at each VCPU
1635 * entry to avoid unknown leaps of TSC even when running
1636 * again on the same CPU. This may cause apparent elapsed
1637 * time to disappear, and the guest to stand still or run
1638 * very slowly.
1639 */
1640 if (vcpu->tsc_catchup) {
1641 u64 tsc = compute_guest_tsc(v, kernel_ns);
1642 if (tsc > tsc_timestamp) {
f1e2b260 1643 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1644 tsc_timestamp = tsc;
1645 }
50d0a0f9
GH		 1646 }
1647
18068523
GOC		 1648 local_irq_restore(flags);
1649
0b79459b 1650 if (!vcpu->pv_time_enabled)
c285545f 1651 return 0;
18068523 1652
e48672fa 1653 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1654 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1655 &vcpu->hv_clock.tsc_shift,
1656 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1657 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1658 }
1659
1660 /* With all the info we got, fill in the values */
1d5f066e 1661 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1662 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1663 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1664
09a0c3f1
OH		 1665 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1666 &guest_hv_clock, sizeof(guest_hv_clock))))
1667 return 0;
1668
5dca0d91
RK		 1669 /* This VCPU is paused, but it's legal for a guest to read another
1670 * VCPU's kvmclock, so we really have to follow the specification where
1671 * it says that version is odd if data is being modified, and even after
1672 * it is consistent.
1673 *
1674 * Version field updates must be kept separate. This is because
1675 * kvm_write_guest_cached might use a "rep movs" instruction, and
1676 * writes within a string instruction are weakly ordered. So there
1677 * are three writes overall.
1678 *
1679 * As a small optimization, only write the version field in the first
1680 * and third write. The vcpu->pv_time cache is still valid, because the
1681 * version field is the first in the struct.
18068523 1682 */
5dca0d91
RK		 1683 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1684
1685 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1686 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1687 &vcpu->hv_clock,
1688 sizeof(vcpu->hv_clock.version));
1689
1690 smp_wmb();
78c0337a
MT		 1691
1692 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1693 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1694
1695 if (vcpu->pvclock_set_guest_stopped_request) {
1696 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1697 vcpu->pvclock_set_guest_stopped_request = false;
1698 }
1699
d828199e
MT		 1700 /* If the host uses TSC clocksource, then it is stable */
1701 if (use_master_clock)
1702 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1703
78c0337a
MT		 1704 vcpu->hv_clock.flags = pvclock_flags;
1705
ce1a5e60
DM		 1706 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1707
0b79459b
AH		 1708 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1709 &vcpu->hv_clock,
1710 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1711
1712 smp_wmb();
1713
1714 vcpu->hv_clock.version++;
1715 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1716 &vcpu->hv_clock,
1717 sizeof(vcpu->hv_clock.version));
8cfdc000 1718 return 0;
c8076604
GH		 1719}
1720
0061d53d
MT		 1721/*
1722 * kvmclock updates which are isolated to a given vcpu, such as
1723 * vcpu->cpu migration, should not allow system_timestamp from
1724 * the rest of the vcpus to remain static. Otherwise ntp frequency
1725 * correction applies to one vcpu's system_timestamp but not
1726 * the others.
1727 *
1728 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1729 * We need to rate-limit these requests though, as they can
1730 * considerably slow guests that have a large number of vcpus.
1731 * The time for a remote vcpu to update its kvmclock is bound
1732 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1733 */
1734
7e44e449
AJ		 1735#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1736
1737static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1738{
1739 int i;
7e44e449
AJ		 1740 struct delayed_work *dwork = to_delayed_work(work);
1741 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1742 kvmclock_update_work);
1743 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1744 struct kvm_vcpu *vcpu;
1745
1746 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1747 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1748 kvm_vcpu_kick(vcpu);
1749 }
1750}
1751
7e44e449
AJ		 1752static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1753{
1754 struct kvm *kvm = v->kvm;
1755
105b21bb 1756 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1757 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1758 KVMCLOCK_UPDATE_DELAY);
1759}
1760
332967a3
AJ		 1761#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1762
1763static void kvmclock_sync_fn(struct work_struct *work)
1764{
1765 struct delayed_work *dwork = to_delayed_work(work);
1766 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1767 kvmclock_sync_work);
1768 struct kvm *kvm = container_of(ka, struct kvm, arch);
1769
1770 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1771 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1772 KVMCLOCK_SYNC_PERIOD);
1773}
1774
9ba075a6
AK		 1775static bool msr_mtrr_valid(unsigned msr)
1776{
1777 switch (msr) {
1778 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1779 case MSR_MTRRfix64K_00000:
1780 case MSR_MTRRfix16K_80000:
1781 case MSR_MTRRfix16K_A0000:
1782 case MSR_MTRRfix4K_C0000:
1783 case MSR_MTRRfix4K_C8000:
1784 case MSR_MTRRfix4K_D0000:
1785 case MSR_MTRRfix4K_D8000:
1786 case MSR_MTRRfix4K_E0000:
1787 case MSR_MTRRfix4K_E8000:
1788 case MSR_MTRRfix4K_F0000:
1789 case MSR_MTRRfix4K_F8000:
1790 case MSR_MTRRdefType:
1791 case MSR_IA32_CR_PAT:
1792 return true;
1793 case 0x2f8:
1794 return true;
1795 }
1796 return false;
1797}
1798
d6289b93
MT		 1799static bool valid_pat_type(unsigned t)
1800{
1801 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1802}
1803
1804static bool valid_mtrr_type(unsigned t)
1805{
1806 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1807}
1808
4566654b 1809bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1810{
1811 int i;
fd275235 1812 u64 mask;
d6289b93
MT		 1813
1814 if (!msr_mtrr_valid(msr))
1815 return false;
1816
1817 if (msr == MSR_IA32_CR_PAT) {
1818 for (i = 0; i < 8; i++)
1819 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1820 return false;
1821 return true;
1822 } else if (msr == MSR_MTRRdefType) {
1823 if (data & ~0xcff)
1824 return false;
1825 return valid_mtrr_type(data & 0xff);
1826 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1827 for (i = 0; i < 8 ; i++)
1828 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1829 return false;
1830 return true;
1831 }
1832
1833 /* variable MTRRs */
adfb5d27
WL		 1834 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1835
fd275235 1836 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1837 if ((msr & 1) == 0) {
adfb5d27 1838 /* MTRR base */
d7a2a246
WL		 1839 if (!valid_mtrr_type(data & 0xff))
1840 return false;
1841 mask |= 0xf00;
1842 } else
1843 /* MTRR mask */
1844 mask |= 0x7ff;
1845 if (data & mask) {
1846 kvm_inject_gp(vcpu, 0);
1847 return false;
1848 }
1849
adfb5d27 1850 return true;
d6289b93 1851}
4566654b 1852EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1853
9ba075a6
AK		 1854static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1855{
0bed3b56
SY		 1856 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1857
4566654b 1858 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1859 return 1;
1860
0bed3b56
SY		 1861 if (msr == MSR_MTRRdefType) {
1862 vcpu->arch.mtrr_state.def_type = data;
1863 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1864 } else if (msr == MSR_MTRRfix64K_00000)
1865 p[0] = data;
1866 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1867 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1868 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1869 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1870 else if (msr == MSR_IA32_CR_PAT)
1871 vcpu->arch.pat = data;
1872 else { /* Variable MTRRs */
1873 int idx, is_mtrr_mask;
1874 u64 *pt;
1875
1876 idx = (msr - 0x200) / 2;
1877 is_mtrr_mask = msr - 0x200 - 2 * idx;
1878 if (!is_mtrr_mask)
1879 pt =
1880 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1881 else
1882 pt =
1883 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1884 *pt = data;
1885 }
1886
1887 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1888 return 0;
1889}
15c4a640 1890
890ca9ae 1891static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1892{
890ca9ae
HY		 1893 u64 mcg_cap = vcpu->arch.mcg_cap;
1894 unsigned bank_num = mcg_cap & 0xff;
1895
15c4a640 1896 switch (msr) {
15c4a640 1897 case MSR_IA32_MCG_STATUS:
890ca9ae 1898 vcpu->arch.mcg_status = data;
15c4a640 1899 break;
c7ac679c 1900 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1901 if (!(mcg_cap & MCG_CTL_P))
1902 return 1;
1903 if (data != 0 && data != ~(u64)0)
1904 return -1;
1905 vcpu->arch.mcg_ctl = data;
1906 break;
1907 default:
1908 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1909 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1910 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1911 /* only 0 or all 1s can be written to IA32_MCi_CTL
1912 * some Linux kernels though clear bit 10 in bank 4 to
1913 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1914 * this to avoid an uncatched #GP in the guest
1915 */
890ca9ae 1916 if ((offset & 0x3) == 0 &&
114be429 1917 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1918 return -1;
1919 vcpu->arch.mce_banks[offset] = data;
1920 break;
1921 }
1922 return 1;
1923 }
1924 return 0;
1925}
1926
ffde22ac
ES		 1927static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1928{
1929 struct kvm *kvm = vcpu->kvm;
1930 int lm = is_long_mode(vcpu);
1931 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1932 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1933 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1934 : kvm->arch.xen_hvm_config.blob_size_32;
1935 u32 page_num = data & ~PAGE_MASK;
1936 u64 page_addr = data & PAGE_MASK;
1937 u8 *page;
1938 int r;
1939
1940 r = -E2BIG;
1941 if (page_num >= blob_size)
1942 goto out;
1943 r = -ENOMEM;
ff5c2c03
SL		 1944 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1945 if (IS_ERR(page)) {
1946 r = PTR_ERR(page);
ffde22ac 1947 goto out;
ff5c2c03 1948 }
ffde22ac
ES		 1949 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1950 goto out_free;
1951 r = 0;
1952out_free:
1953 kfree(page);
1954out:
1955 return r;
1956}
1957
55cd8e5a
GN		 1958static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1959{
1960 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1961}
1962
1963static bool kvm_hv_msr_partition_wide(u32 msr)
1964{
1965 bool r = false;
1966 switch (msr) {
1967 case HV_X64_MSR_GUEST_OS_ID:
1968 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1969 case HV_X64_MSR_REFERENCE_TSC:
1970 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1971 r = true;
1972 break;
1973 }
1974
1975 return r;
1976}
1977
1978static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1979{
1980 struct kvm *kvm = vcpu->kvm;
1981
1982 switch (msr) {
1983 case HV_X64_MSR_GUEST_OS_ID:
1984 kvm->arch.hv_guest_os_id = data;
1985 /* setting guest os id to zero disables hypercall page */
1986 if (!kvm->arch.hv_guest_os_id)
1987 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1988 break;
1989 case HV_X64_MSR_HYPERCALL: {
1990 u64 gfn;
1991 unsigned long addr;
1992 u8 instructions[4];
1993
1994 /* if guest os id is not set hypercall should remain disabled */
1995 if (!kvm->arch.hv_guest_os_id)
1996 break;
1997 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1998 kvm->arch.hv_hypercall = data;
1999 break;
2000 }
2001 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
2002 addr = gfn_to_hva(kvm, gfn);
2003 if (kvm_is_error_hva(addr))
2004 return 1;
2005 kvm_x86_ops->patch_hypercall(vcpu, instructions);
2006 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 2007 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 2008 return 1;
2009 kvm->arch.hv_hypercall = data;
b94b64c9 2010 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 2011 break;
2012 }
e984097b
VR		 2013 case HV_X64_MSR_REFERENCE_TSC: {
2014 u64 gfn;
2015 HV_REFERENCE_TSC_PAGE tsc_ref;
2016 memset(&tsc_ref, 0, sizeof(tsc_ref));
2017 kvm->arch.hv_tsc_page = data;
2018 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
2019 break;
2020 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 2021 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 2022 &tsc_ref, sizeof(tsc_ref)))
2023 return 1;
2024 mark_page_dirty(kvm, gfn);
2025 break;
2026 }
55cd8e5a 2027 default:
a737f256
CD		 2028 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2029 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 2030 return 1;
2031 }
2032 return 0;
2033}
2034
2035static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2036{
10388a07
GN		 2037 switch (msr) {
2038 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 2039 u64 gfn;
10388a07 2040 unsigned long addr;
55cd8e5a 2041
10388a07
GN		 2042 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2043 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 2044 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2045 return 1;
10388a07
GN		 2046 break;
2047 }
b3af1e88
VR		 2048 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2049 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 2050 if (kvm_is_error_hva(addr))
2051 return 1;
8b0cedff 2052 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2053 return 1;
2054 vcpu->arch.hv_vapic = data;
b3af1e88 2055 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2056 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2057 return 1;
10388a07
GN		 2058 break;
2059 }
2060 case HV_X64_MSR_EOI:
2061 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2062 case HV_X64_MSR_ICR:
2063 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2064 case HV_X64_MSR_TPR:
2065 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2066 default:
a737f256
CD		 2067 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2068 "data 0x%llx\n", msr, data);
10388a07
GN		 2069 return 1;
2070 }
2071
2072 return 0;
55cd8e5a
GN		 2073}
2074
344d9588
GN		 2075static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2076{
2077 gpa_t gpa = data & ~0x3f;
2078
4a969980 2079 /* Bits 2:5 are reserved, Should be zero */
6adba527 2080 if (data & 0x3c)
344d9588
GN		 2081 return 1;
2082
2083 vcpu->arch.apf.msr_val = data;
2084
2085 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2086 kvm_clear_async_pf_completion_queue(vcpu);
2087 kvm_async_pf_hash_reset(vcpu);
2088 return 0;
2089 }
2090
8f964525
AH		 2091 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2092 sizeof(u32)))
344d9588
GN		 2093 return 1;
2094
6adba527 2095 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2096 kvm_async_pf_wakeup_all(vcpu);
2097 return 0;
2098}
2099
12f9a48f
GC		 2100static void kvmclock_reset(struct kvm_vcpu *vcpu)
2101{
0b79459b 2102 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2103}
2104
c9aaa895
GC		 2105static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2106{
2107 u64 delta;
2108
2109 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2110 return;
2111
2112 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2113 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2114 vcpu->arch.st.accum_steal = delta;
2115}
2116
2117static void record_steal_time(struct kvm_vcpu *vcpu)
2118{
2119 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2120 return;
2121
2122 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2123 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2124 return;
2125
2126 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2127 vcpu->arch.st.steal.version += 2;
2128 vcpu->arch.st.accum_steal = 0;
2129
2130 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2131 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2132}
2133
8fe8ab46 2134int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2135{
5753785f 2136 bool pr = false;
8fe8ab46
WA		 2137 u32 msr = msr_info->index;
2138 u64 data = msr_info->data;
5753785f 2139
15c4a640 2140 switch (msr) {
2e32b719
BP		 2141 case MSR_AMD64_NB_CFG:
2142 case MSR_IA32_UCODE_REV:
2143 case MSR_IA32_UCODE_WRITE:
2144 case MSR_VM_HSAVE_PA:
2145 case MSR_AMD64_PATCH_LOADER:
2146 case MSR_AMD64_BU_CFG2:
2147 break;
2148
15c4a640 2149 case MSR_EFER:
b69e8cae 2150 return set_efer(vcpu, data);
8f1589d9
AP		 2151 case MSR_K7_HWCR:
2152 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2153 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2154 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2155 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2156 if (data != 0) {
a737f256
CD		 2157 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2158 data);
8f1589d9
AP		 2159 return 1;
2160 }
15c4a640 2161 break;
f7c6d140
AP		 2162 case MSR_FAM10H_MMIO_CONF_BASE:
2163 if (data != 0) {
a737f256
CD		 2164 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2165 "0x%llx\n", data);
f7c6d140
AP		 2166 return 1;
2167 }
15c4a640 2168 break;
b5e2fec0
AG		 2169 case MSR_IA32_DEBUGCTLMSR:
2170 if (!data) {
2171 /* We support the non-activated case already */
2172 break;
2173 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2174 /* Values other than LBR and BTF are vendor-specific,
2175 thus reserved and should throw a #GP */
2176 return 1;
2177 }
a737f256
CD		 2178 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2179 __func__, data);
b5e2fec0 2180 break;
9ba075a6
AK		 2181 case 0x200 ... 0x2ff:
2182 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2183 case MSR_IA32_APICBASE:
58cb628d 2184 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2185 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2186 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2187 case MSR_IA32_TSCDEADLINE:
2188 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2189 break;
ba904635
WA		 2190 case MSR_IA32_TSC_ADJUST:
2191 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2192 if (!msr_info->host_initiated) {
d913b904 2193 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2194 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2195 }
2196 vcpu->arch.ia32_tsc_adjust_msr = data;
2197 }
2198 break;
15c4a640 2199 case MSR_IA32_MISC_ENABLE:
ad312c7c 2200 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2201 break;
11c6bffa 2202 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2203 case MSR_KVM_WALL_CLOCK:
2204 vcpu->kvm->arch.wall_clock = data;
2205 kvm_write_wall_clock(vcpu->kvm, data);
2206 break;
11c6bffa 2207 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2208 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2209 u64 gpa_offset;
54750f2c
MT		 2210 struct kvm_arch *ka = &vcpu->kvm->arch;
2211
12f9a48f 2212 kvmclock_reset(vcpu);
18068523 2213
54750f2c
MT		 2214 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2215 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2216
2217 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2218 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2219 &vcpu->requests);
2220
2221 ka->boot_vcpu_runs_old_kvmclock = tmp;
2222 }
2223
18068523 2224 vcpu->arch.time = data;
0061d53d 2225 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2226
2227 /* we verify if the enable bit is set... */
2228 if (!(data & 1))
2229 break;
2230
0b79459b 2231 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2232
0b79459b 2233 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2234 &vcpu->arch.pv_time, data & ~1ULL,
2235 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2236 vcpu->arch.pv_time_enabled = false;
2237 else
2238 vcpu->arch.pv_time_enabled = true;
32cad84f 2239
18068523
GOC		 2240 break;
2241 }
344d9588
GN		 2242 case MSR_KVM_ASYNC_PF_EN:
2243 if (kvm_pv_enable_async_pf(vcpu, data))
2244 return 1;
2245 break;
c9aaa895
GC		 2246 case MSR_KVM_STEAL_TIME:
2247
2248 if (unlikely(!sched_info_on()))
2249 return 1;
2250
2251 if (data & KVM_STEAL_RESERVED_MASK)
2252 return 1;
2253
2254 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2255 data & KVM_STEAL_VALID_BITS,
2256 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2257 return 1;
2258
2259 vcpu->arch.st.msr_val = data;
2260
2261 if (!(data & KVM_MSR_ENABLED))
2262 break;
2263
2264 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2265
2266 preempt_disable();
2267 accumulate_steal_time(vcpu);
2268 preempt_enable();
2269
2270 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2271
2272 break;
ae7a2a3f
MT		 2273 case MSR_KVM_PV_EOI_EN:
2274 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2275 return 1;
2276 break;
c9aaa895 2277
890ca9ae
HY		 2278 case MSR_IA32_MCG_CTL:
2279 case MSR_IA32_MCG_STATUS:
81760dcc 2280 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2281 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2282
2283 /* Performance counters are not protected by a CPUID bit,
2284 * so we should check all of them in the generic path for the sake of
2285 * cross vendor migration.
2286 * Writing a zero into the event select MSRs disables them,
2287 * which we perfectly emulate ;-). Any other value should be at least
2288 * reported, some guests depend on them.
2289 */
71db6023
AP		 2290 case MSR_K7_EVNTSEL0:
2291 case MSR_K7_EVNTSEL1:
2292 case MSR_K7_EVNTSEL2:
2293 case MSR_K7_EVNTSEL3:
2294 if (data != 0)
a737f256
CD		 2295 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2296 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2297 break;
2298 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2299 * so we ignore writes to make it happy.
2300 */
71db6023
AP		 2301 case MSR_K7_PERFCTR0:
2302 case MSR_K7_PERFCTR1:
2303 case MSR_K7_PERFCTR2:
2304 case MSR_K7_PERFCTR3:
a737f256
CD		 2305 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2306 "0x%x data 0x%llx\n", msr, data);
71db6023 2307 break;
5753785f
GN		 2308 case MSR_P6_PERFCTR0:
2309 case MSR_P6_PERFCTR1:
2310 pr = true;
2311 case MSR_P6_EVNTSEL0:
2312 case MSR_P6_EVNTSEL1:
2313 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2314 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2315
2316 if (pr || data != 0)
a737f256
CD		 2317 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2318 "0x%x data 0x%llx\n", msr, data);
5753785f 2319 break;
84e0cefa
JS		 2320 case MSR_K7_CLK_CTL:
2321 /*
2322 * Ignore all writes to this no longer documented MSR.
2323 * Writes are only relevant for old K7 processors,
2324 * all pre-dating SVM, but a recommended workaround from
4a969980 2325 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2326 * affected processor models on the command line, hence
2327 * the need to ignore the workaround.
2328 */
2329 break;
55cd8e5a
GN		 2330 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2331 if (kvm_hv_msr_partition_wide(msr)) {
2332 int r;
2333 mutex_lock(&vcpu->kvm->lock);
2334 r = set_msr_hyperv_pw(vcpu, msr, data);
2335 mutex_unlock(&vcpu->kvm->lock);
2336 return r;
2337 } else
2338 return set_msr_hyperv(vcpu, msr, data);
2339 break;
91c9c3ed 2340 case MSR_IA32_BBL_CR_CTL3:
2341 /* Drop writes to this legacy MSR -- see rdmsr
2342 * counterpart for further detail.
2343 */
a737f256 2344 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2345 break;
2b036c6b
BO		 2346 case MSR_AMD64_OSVW_ID_LENGTH:
2347 if (!guest_cpuid_has_osvw(vcpu))
2348 return 1;
2349 vcpu->arch.osvw.length = data;
2350 break;
2351 case MSR_AMD64_OSVW_STATUS:
2352 if (!guest_cpuid_has_osvw(vcpu))
2353 return 1;
2354 vcpu->arch.osvw.status = data;
2355 break;
15c4a640 2356 default:
ffde22ac
ES		 2357 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2358 return xen_hvm_config(vcpu, data);
f5132b01 2359 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2360 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2361 if (!ignore_msrs) {
a737f256
CD		 2362 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2363 msr, data);
ed85c068
AP		 2364 return 1;
2365 } else {
a737f256
CD		 2366 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2367 msr, data);
ed85c068
AP		 2368 break;
2369 }
15c4a640
CO		 2370 }
2371 return 0;
2372}
2373EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2374
2375
2376/*
2377 * Reads an msr value (of 'msr_index') into 'pdata'.
2378 * Returns 0 on success, non-0 otherwise.
2379 * Assumes vcpu_load() was already called.
2380 */
2381int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2382{
2383 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2384}
ff651cb6 2385EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2386
9ba075a6
AK		 2387static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2388{
0bed3b56
SY		 2389 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2390
9ba075a6
AK		 2391 if (!msr_mtrr_valid(msr))
2392 return 1;
2393
0bed3b56
SY		 2394 if (msr == MSR_MTRRdefType)
2395 *pdata = vcpu->arch.mtrr_state.def_type +
2396 (vcpu->arch.mtrr_state.enabled << 10);
2397 else if (msr == MSR_MTRRfix64K_00000)
2398 *pdata = p[0];
2399 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2400 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2401 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2402 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2403 else if (msr == MSR_IA32_CR_PAT)
2404 *pdata = vcpu->arch.pat;
2405 else { /* Variable MTRRs */
2406 int idx, is_mtrr_mask;
2407 u64 *pt;
2408
2409 idx = (msr - 0x200) / 2;
2410 is_mtrr_mask = msr - 0x200 - 2 * idx;
2411 if (!is_mtrr_mask)
2412 pt =
2413 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2414 else
2415 pt =
2416 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2417 *pdata = *pt;
2418 }
2419
9ba075a6
AK		 2420 return 0;
2421}
2422
890ca9ae 2423static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2424{
2425 u64 data;
890ca9ae
HY		 2426 u64 mcg_cap = vcpu->arch.mcg_cap;
2427 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2428
2429 switch (msr) {
15c4a640
CO		 2430 case MSR_IA32_P5_MC_ADDR:
2431 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2432 data = 0;
2433 break;
15c4a640 2434 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2435 data = vcpu->arch.mcg_cap;
2436 break;
c7ac679c 2437 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2438 if (!(mcg_cap & MCG_CTL_P))
2439 return 1;
2440 data = vcpu->arch.mcg_ctl;
2441 break;
2442 case MSR_IA32_MCG_STATUS:
2443 data = vcpu->arch.mcg_status;
2444 break;
2445 default:
2446 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2447 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2448 u32 offset = msr - MSR_IA32_MC0_CTL;
2449 data = vcpu->arch.mce_banks[offset];
2450 break;
2451 }
2452 return 1;
2453 }
2454 *pdata = data;
2455 return 0;
2456}
2457
55cd8e5a
GN		 2458static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2459{
2460 u64 data = 0;
2461 struct kvm *kvm = vcpu->kvm;
2462
2463 switch (msr) {
2464 case HV_X64_MSR_GUEST_OS_ID:
2465 data = kvm->arch.hv_guest_os_id;
2466 break;
2467 case HV_X64_MSR_HYPERCALL:
2468 data = kvm->arch.hv_hypercall;
2469 break;
e984097b
VR		 2470 case HV_X64_MSR_TIME_REF_COUNT: {
2471 data =
2472 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2473 break;
2474 }
2475 case HV_X64_MSR_REFERENCE_TSC:
2476 data = kvm->arch.hv_tsc_page;
2477 break;
55cd8e5a 2478 default:
a737f256 2479 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2480 return 1;
2481 }
2482
2483 *pdata = data;
2484 return 0;
2485}
2486
2487static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2488{
2489 u64 data = 0;
2490
2491 switch (msr) {
2492 case HV_X64_MSR_VP_INDEX: {
2493 int r;
2494 struct kvm_vcpu *v;
684851a1
TY		 2495 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2496 if (v == vcpu) {
55cd8e5a 2497 data = r;
684851a1
TY		 2498 break;
2499 }
2500 }
55cd8e5a
GN		 2501 break;
2502 }
10388a07
GN		 2503 case HV_X64_MSR_EOI:
2504 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2505 case HV_X64_MSR_ICR:
2506 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2507 case HV_X64_MSR_TPR:
2508 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2509 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2510 data = vcpu->arch.hv_vapic;
2511 break;
55cd8e5a 2512 default:
a737f256 2513 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2514 return 1;
2515 }
2516 *pdata = data;
2517 return 0;
2518}
2519
890ca9ae
HY		 2520int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2521{
2522 u64 data;
2523
2524 switch (msr) {
890ca9ae 2525 case MSR_IA32_PLATFORM_ID:
15c4a640 2526 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2527 case MSR_IA32_DEBUGCTLMSR:
2528 case MSR_IA32_LASTBRANCHFROMIP:
2529 case MSR_IA32_LASTBRANCHTOIP:
2530 case MSR_IA32_LASTINTFROMIP:
2531 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2532 case MSR_K8_SYSCFG:
2533 case MSR_K7_HWCR:
61a6bd67 2534 case MSR_VM_HSAVE_PA:
9e699624 2535 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2536 case MSR_K7_EVNTSEL1:
2537 case MSR_K7_EVNTSEL2:
2538 case MSR_K7_EVNTSEL3:
1f3ee616 2539 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2540 case MSR_K7_PERFCTR1:
2541 case MSR_K7_PERFCTR2:
2542 case MSR_K7_PERFCTR3:
1fdbd48c 2543 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2544 case MSR_AMD64_NB_CFG:
f7c6d140 2545 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2546 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2547 data = 0;
2548 break;
5753785f
GN		 2549 case MSR_P6_PERFCTR0:
2550 case MSR_P6_PERFCTR1:
2551 case MSR_P6_EVNTSEL0:
2552 case MSR_P6_EVNTSEL1:
2553 if (kvm_pmu_msr(vcpu, msr))
2554 return kvm_pmu_get_msr(vcpu, msr, pdata);
2555 data = 0;
2556 break;
742bc670
MT		 2557 case MSR_IA32_UCODE_REV:
2558 data = 0x100000000ULL;
2559 break;
9ba075a6
AK		 2560 case MSR_MTRRcap:
2561 data = 0x500 | KVM_NR_VAR_MTRR;
2562 break;
2563 case 0x200 ... 0x2ff:
2564 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2565 case 0xcd: /* fsb frequency */
2566 data = 3;
2567 break;
7b914098
JS		 2568 /*
2569 * MSR_EBC_FREQUENCY_ID
2570 * Conservative value valid for even the basic CPU models.
2571 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2572 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2573 * and 266MHz for model 3, or 4. Set Core Clock
2574 * Frequency to System Bus Frequency Ratio to 1 (bits
2575 * 31:24) even though these are only valid for CPU
2576 * models > 2, however guests may end up dividing or
2577 * multiplying by zero otherwise.
2578 */
2579 case MSR_EBC_FREQUENCY_ID:
2580 data = 1 << 24;
2581 break;
15c4a640
CO		 2582 case MSR_IA32_APICBASE:
2583 data = kvm_get_apic_base(vcpu);
2584 break;
0105d1a5
GN		 2585 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2586 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2587 break;
a3e06bbe
LJ		 2588 case MSR_IA32_TSCDEADLINE:
2589 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2590 break;
ba904635
WA		 2591 case MSR_IA32_TSC_ADJUST:
2592 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2593 break;
15c4a640 2594 case MSR_IA32_MISC_ENABLE:
ad312c7c 2595 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2596 break;
847f0ad8
AG		 2597 case MSR_IA32_PERF_STATUS:
2598 /* TSC increment by tick */
2599 data = 1000ULL;
2600 /* CPU multiplier */
2601 data |= (((uint64_t)4ULL) << 40);
2602 break;
15c4a640 2603 case MSR_EFER:
f6801dff 2604 data = vcpu->arch.efer;
15c4a640 2605 break;
18068523 2606 case MSR_KVM_WALL_CLOCK:
11c6bffa 2607 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2608 data = vcpu->kvm->arch.wall_clock;
2609 break;
2610 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2611 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2612 data = vcpu->arch.time;
2613 break;
344d9588
GN		 2614 case MSR_KVM_ASYNC_PF_EN:
2615 data = vcpu->arch.apf.msr_val;
2616 break;
c9aaa895
GC		 2617 case MSR_KVM_STEAL_TIME:
2618 data = vcpu->arch.st.msr_val;
2619 break;
1d92128f
MT		 2620 case MSR_KVM_PV_EOI_EN:
2621 data = vcpu->arch.pv_eoi.msr_val;
2622 break;
890ca9ae
HY		 2623 case MSR_IA32_P5_MC_ADDR:
2624 case MSR_IA32_P5_MC_TYPE:
2625 case MSR_IA32_MCG_CAP:
2626 case MSR_IA32_MCG_CTL:
2627 case MSR_IA32_MCG_STATUS:
81760dcc 2628 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2629 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2630 case MSR_K7_CLK_CTL:
2631 /*
2632 * Provide expected ramp-up count for K7. All other
2633 * are set to zero, indicating minimum divisors for
2634 * every field.
2635 *
2636 * This prevents guest kernels on AMD host with CPU
2637 * type 6, model 8 and higher from exploding due to
2638 * the rdmsr failing.
2639 */
2640 data = 0x20000000;
2641 break;
55cd8e5a
GN		 2642 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2643 if (kvm_hv_msr_partition_wide(msr)) {
2644 int r;
2645 mutex_lock(&vcpu->kvm->lock);
2646 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2647 mutex_unlock(&vcpu->kvm->lock);
2648 return r;
2649 } else
2650 return get_msr_hyperv(vcpu, msr, pdata);
2651 break;
91c9c3ed 2652 case MSR_IA32_BBL_CR_CTL3:
2653 /* This legacy MSR exists but isn't fully documented in current
2654 * silicon. It is however accessed by winxp in very narrow
2655 * scenarios where it sets bit #19, itself documented as
2656 * a "reserved" bit. Best effort attempt to source coherent
2657 * read data here should the balance of the register be
2658 * interpreted by the guest:
2659 *
2660 * L2 cache control register 3: 64GB range, 256KB size,
2661 * enabled, latency 0x1, configured
2662 */
2663 data = 0xbe702111;
2664 break;
2b036c6b
BO		 2665 case MSR_AMD64_OSVW_ID_LENGTH:
2666 if (!guest_cpuid_has_osvw(vcpu))
2667 return 1;
2668 data = vcpu->arch.osvw.length;
2669 break;
2670 case MSR_AMD64_OSVW_STATUS:
2671 if (!guest_cpuid_has_osvw(vcpu))
2672 return 1;
2673 data = vcpu->arch.osvw.status;
2674 break;
15c4a640 2675 default:
f5132b01
GN		 2676 if (kvm_pmu_msr(vcpu, msr))
2677 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2678 if (!ignore_msrs) {
a737f256 2679 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2680 return 1;
2681 } else {
a737f256 2682 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2683 data = 0;
2684 }
2685 break;
15c4a640
CO		 2686 }
2687 *pdata = data;
2688 return 0;
2689}
2690EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2691
313a3dc7
CO		 2692/*
2693 * Read or write a bunch of msrs. All parameters are kernel addresses.
2694 *
2695 * @return number of msrs set successfully.
2696 */
2697static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2698 struct kvm_msr_entry *entries,
2699 int (*do_msr)(struct kvm_vcpu *vcpu,
2700 unsigned index, u64 *data))
2701{
f656ce01 2702 int i, idx;
313a3dc7 2703
f656ce01 2704 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2705 for (i = 0; i < msrs->nmsrs; ++i)
2706 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2707 break;
f656ce01 2708 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2709
313a3dc7
CO		 2710 return i;
2711}
2712
2713/*
2714 * Read or write a bunch of msrs. Parameters are user addresses.
2715 *
2716 * @return number of msrs set successfully.
2717 */
2718static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2719 int (*do_msr)(struct kvm_vcpu *vcpu,
2720 unsigned index, u64 *data),
2721 int writeback)
2722{
2723 struct kvm_msrs msrs;
2724 struct kvm_msr_entry *entries;
2725 int r, n;
2726 unsigned size;
2727
2728 r = -EFAULT;
2729 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2730 goto out;
2731
2732 r = -E2BIG;
2733 if (msrs.nmsrs >= MAX_IO_MSRS)
2734 goto out;
2735
313a3dc7 2736 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2737 entries = memdup_user(user_msrs->entries, size);
2738 if (IS_ERR(entries)) {
2739 r = PTR_ERR(entries);
313a3dc7 2740 goto out;
ff5c2c03 2741 }
313a3dc7
CO		 2742
2743 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2744 if (r < 0)
2745 goto out_free;
2746
2747 r = -EFAULT;
2748 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2749 goto out_free;
2750
2751 r = n;
2752
2753out_free:
7a73c028 2754 kfree(entries);
313a3dc7
CO		 2755out:
2756 return r;
2757}
2758
784aa3d7 2759int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2760{
2761 int r;
2762
2763 switch (ext) {
2764 case KVM_CAP_IRQCHIP:
2765 case KVM_CAP_HLT:
2766 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2767 case KVM_CAP_SET_TSS_ADDR:
07716717 2768 case KVM_CAP_EXT_CPUID:
9c15bb1d 2769 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2770 case KVM_CAP_CLOCKSOURCE:
7837699f 2771 case KVM_CAP_PIT:
a28e4f5a 2772 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2773 case KVM_CAP_MP_STATE:
ed848624 2774 case KVM_CAP_SYNC_MMU:
a355c85c 2775 case KVM_CAP_USER_NMI:
52d939a0 2776 case KVM_CAP_REINJECT_CONTROL:
4925663a 2777 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2778 case KVM_CAP_IOEVENTFD:
f848a5a8 2779 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2780 case KVM_CAP_PIT2:
e9f42757 2781 case KVM_CAP_PIT_STATE2:
b927a3ce 2782 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2783 case KVM_CAP_XEN_HVM:
afbcf7ab 2784 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2785 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2786 case KVM_CAP_HYPERV:
10388a07 2787 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2788 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2789 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2790 case KVM_CAP_DEBUGREGS:
d2be1651 2791 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2792 case KVM_CAP_XSAVE:
344d9588 2793 case KVM_CAP_ASYNC_PF:
92a1f12d 2794 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2795 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2796 case KVM_CAP_READONLY_MEM:
5f66b620 2797 case KVM_CAP_HYPERV_TIME:
100943c5 2798 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2799 case KVM_CAP_TSC_DEADLINE_TIMER:
2a5bab10
AW		 2800#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2801 case KVM_CAP_ASSIGN_DEV_IRQ:
2802 case KVM_CAP_PCI_2_3:
2803#endif
018d00d2
ZX		 2804 r = 1;
2805 break;
542472b5
LV		 2806 case KVM_CAP_COALESCED_MMIO:
2807 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2808 break;
774ead3a
AK		 2809 case KVM_CAP_VAPIC:
2810 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2811 break;
f725230a 2812 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2813 r = KVM_SOFT_MAX_VCPUS;
2814 break;
2815 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2816 r = KVM_MAX_VCPUS;
2817 break;
a988b910 2818 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2819 r = KVM_USER_MEM_SLOTS;
a988b910 2820 break;
a68a6a72
MT		 2821 case KVM_CAP_PV_MMU: /* obsolete */
2822 r = 0;
2f333bcb 2823 break;
4cee4b72 2824#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2825 case KVM_CAP_IOMMU:
a1b60c1c 2826 r = iommu_present(&pci_bus_type);
62c476c7 2827 break;
4cee4b72 2828#endif
890ca9ae
HY		 2829 case KVM_CAP_MCE:
2830 r = KVM_MAX_MCE_BANKS;
2831 break;
2d5b5a66
SY		 2832 case KVM_CAP_XCRS:
2833 r = cpu_has_xsave;
2834 break;
92a1f12d
JR		 2835 case KVM_CAP_TSC_CONTROL:
2836 r = kvm_has_tsc_control;
2837 break;
018d00d2
ZX		 2838 default:
2839 r = 0;
2840 break;
2841 }
2842 return r;
2843
2844}
2845
043405e1
CO		 2846long kvm_arch_dev_ioctl(struct file *filp,
2847 unsigned int ioctl, unsigned long arg)
2848{
2849 void __user *argp = (void __user *)arg;
2850 long r;
2851
2852 switch (ioctl) {
2853 case KVM_GET_MSR_INDEX_LIST: {
2854 struct kvm_msr_list __user *user_msr_list = argp;
2855 struct kvm_msr_list msr_list;
2856 unsigned n;
2857
2858 r = -EFAULT;
2859 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2860 goto out;
2861 n = msr_list.nmsrs;
2862 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2863 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2864 goto out;
2865 r = -E2BIG;
e125e7b6 2866 if (n < msr_list.nmsrs)
043405e1
CO		 2867 goto out;
2868 r = -EFAULT;
2869 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2870 num_msrs_to_save * sizeof(u32)))
2871 goto out;
e125e7b6 2872 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2873 &emulated_msrs,
2874 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2875 goto out;
2876 r = 0;
2877 break;
2878 }
9c15bb1d
BP		 2879 case KVM_GET_SUPPORTED_CPUID:
2880 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2881 struct kvm_cpuid2 __user *cpuid_arg = argp;
2882 struct kvm_cpuid2 cpuid;
2883
2884 r = -EFAULT;
2885 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2886 goto out;
9c15bb1d
BP		 2887
2888 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2889 ioctl);
674eea0f
AK		 2890 if (r)
2891 goto out;
2892
2893 r = -EFAULT;
2894 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2895 goto out;
2896 r = 0;
2897 break;
2898 }
890ca9ae
HY		 2899 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2900 u64 mce_cap;
2901
2902 mce_cap = KVM_MCE_CAP_SUPPORTED;
2903 r = -EFAULT;
2904 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2905 goto out;
2906 r = 0;
2907 break;
2908 }
043405e1
CO		 2909 default:
2910 r = -EINVAL;
2911 }
2912out:
2913 return r;
2914}
2915
f5f48ee1
SY		 2916static void wbinvd_ipi(void *garbage)
2917{
2918 wbinvd();
2919}
2920
2921static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2922{
e0f0bbc5 2923 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2924}
2925
313a3dc7
CO		 2926void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2927{
f5f48ee1
SY		 2928 /* Address WBINVD may be executed by guest */
2929 if (need_emulate_wbinvd(vcpu)) {
2930 if (kvm_x86_ops->has_wbinvd_exit())
2931 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2932 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2933 smp_call_function_single(vcpu->cpu,
2934 wbinvd_ipi, NULL, 1);
2935 }
2936
313a3dc7 2937 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2938
0dd6a6ed
ZA		 2939 /* Apply any externally detected TSC adjustments (due to suspend) */
2940 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2941 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2942 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2943 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2944 }
8f6055cb 2945
48434c20 2946 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2947 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2948 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2949 if (tsc_delta < 0)
2950 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2951 if (check_tsc_unstable()) {
b183aa58
ZA		 2952 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2953 vcpu->arch.last_guest_tsc);
2954 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2955 vcpu->arch.tsc_catchup = 1;
c285545f 2956 }
d98d07ca
MT		 2957 /*
2958 * On a host with synchronized TSC, there is no need to update
2959 * kvmclock on vcpu->cpu migration
2960 */
2961 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2962 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2963 if (vcpu->cpu != cpu)
2964 kvm_migrate_timers(vcpu);
e48672fa 2965 vcpu->cpu = cpu;
6b7d7e76 2966 }
c9aaa895
GC		 2967
2968 accumulate_steal_time(vcpu);
2969 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2970}
2971
2972void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2973{
02daab21 2974 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2975 kvm_put_guest_fpu(vcpu);
6f526ec5 2976 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2977}
2978
313a3dc7
CO		 2979static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2980 struct kvm_lapic_state *s)
2981{
5a71785d 2982 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2983 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2984
2985 return 0;
2986}
2987
2988static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2989 struct kvm_lapic_state *s)
2990{
64eb0620 2991 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2992 update_cr8_intercept(vcpu);
313a3dc7
CO		 2993
2994 return 0;
2995}
2996
f77bc6a4
ZX		 2997static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2998 struct kvm_interrupt *irq)
2999{
02cdb50f 3000 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 3001 return -EINVAL;
3002 if (irqchip_in_kernel(vcpu->kvm))
3003 return -ENXIO;
f77bc6a4 3004
66fd3f7f 3005 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 3006 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 3007
f77bc6a4
ZX		 3008 return 0;
3009}
3010
c4abb7c9
JK		 3011static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3012{
c4abb7c9 3013 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3014
3015 return 0;
3016}
3017
b209749f
AK		 3018static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3019 struct kvm_tpr_access_ctl *tac)
3020{
3021 if (tac->flags)
3022 return -EINVAL;
3023 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3024 return 0;
3025}
3026
890ca9ae
HY		 3027static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3028 u64 mcg_cap)
3029{
3030 int r;
3031 unsigned bank_num = mcg_cap & 0xff, bank;
3032
3033 r = -EINVAL;
a9e38c3e 3034 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 3035 goto out;
3036 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3037 goto out;
3038 r = 0;
3039 vcpu->arch.mcg_cap = mcg_cap;
3040 /* Init IA32_MCG_CTL to all 1s */
3041 if (mcg_cap & MCG_CTL_P)
3042 vcpu->arch.mcg_ctl = ~(u64)0;
3043 /* Init IA32_MCi_CTL to all 1s */
3044 for (bank = 0; bank < bank_num; bank++)
3045 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3046out:
3047 return r;
3048}
3049
3050static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3051 struct kvm_x86_mce *mce)
3052{
3053 u64 mcg_cap = vcpu->arch.mcg_cap;
3054 unsigned bank_num = mcg_cap & 0xff;
3055 u64 *banks = vcpu->arch.mce_banks;
3056
3057 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3058 return -EINVAL;
3059 /*
3060 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3061 * reporting is disabled
3062 */
3063 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3064 vcpu->arch.mcg_ctl != ~(u64)0)
3065 return 0;
3066 banks += 4 * mce->bank;
3067 /*
3068 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3069 * reporting is disabled for the bank
3070 */
3071 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3072 return 0;
3073 if (mce->status & MCI_STATUS_UC) {
3074 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3075 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3076 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3077 return 0;
3078 }
3079 if (banks[1] & MCI_STATUS_VAL)
3080 mce->status |= MCI_STATUS_OVER;
3081 banks[2] = mce->addr;
3082 banks[3] = mce->misc;
3083 vcpu->arch.mcg_status = mce->mcg_status;
3084 banks[1] = mce->status;
3085 kvm_queue_exception(vcpu, MC_VECTOR);
3086 } else if (!(banks[1] & MCI_STATUS_VAL)
3087 || !(banks[1] & MCI_STATUS_UC)) {
3088 if (banks[1] & MCI_STATUS_VAL)
3089 mce->status |= MCI_STATUS_OVER;
3090 banks[2] = mce->addr;
3091 banks[3] = mce->misc;
3092 banks[1] = mce->status;
3093 } else
3094 banks[1] |= MCI_STATUS_OVER;
3095 return 0;
3096}
3097
3cfc3092
JK		 3098static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3099 struct kvm_vcpu_events *events)
3100{
7460fb4a 3101 process_nmi(vcpu);
03b82a30
JK		 3102 events->exception.injected =
3103 vcpu->arch.exception.pending &&
3104 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3105 events->exception.nr = vcpu->arch.exception.nr;
3106 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3107 events->exception.pad = 0;
3cfc3092
JK		 3108 events->exception.error_code = vcpu->arch.exception.error_code;
3109
03b82a30
JK		 3110 events->interrupt.injected =
3111 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3112 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3113 events->interrupt.soft = 0;
37ccdcbe 3114 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3115
3116 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3117 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3118 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3119 events->nmi.pad = 0;
3cfc3092 3120
66450a21 3121 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3122
dab4b911 3123 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3124 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3125 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3126}
3127
3128static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3129 struct kvm_vcpu_events *events)
3130{
dab4b911 3131 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3132 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3133 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3134 return -EINVAL;
3135
7460fb4a 3136 process_nmi(vcpu);
3cfc3092
JK		 3137 vcpu->arch.exception.pending = events->exception.injected;
3138 vcpu->arch.exception.nr = events->exception.nr;
3139 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3140 vcpu->arch.exception.error_code = events->exception.error_code;
3141
3142 vcpu->arch.interrupt.pending = events->interrupt.injected;
3143 vcpu->arch.interrupt.nr = events->interrupt.nr;
3144 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3145 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3146 kvm_x86_ops->set_interrupt_shadow(vcpu,
3147 events->interrupt.shadow);
3cfc3092
JK		 3148
3149 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3150 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3151 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3152 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3153
66450a21
JK		 3154 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3155 kvm_vcpu_has_lapic(vcpu))
3156 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3157
3842d135
AK		 3158 kvm_make_request(KVM_REQ_EVENT, vcpu);
3159
3cfc3092
JK		 3160 return 0;
3161}
3162
a1efbe77
JK		 3163static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3164 struct kvm_debugregs *dbgregs)
3165{
73aaf249
JK		 3166 unsigned long val;
3167
a1efbe77 3168 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3169 kvm_get_dr(vcpu, 6, &val);
73aaf249 3170 dbgregs->dr6 = val;
a1efbe77
JK		 3171 dbgregs->dr7 = vcpu->arch.dr7;
3172 dbgregs->flags = 0;
97e69aa6 3173 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3174}
3175
3176static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3177 struct kvm_debugregs *dbgregs)
3178{
3179 if (dbgregs->flags)
3180 return -EINVAL;
3181
a1efbe77 3182 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3183 kvm_update_dr0123(vcpu);
a1efbe77 3184 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3185 kvm_update_dr6(vcpu);
a1efbe77 3186 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3187 kvm_update_dr7(vcpu);
a1efbe77 3188
a1efbe77
JK		 3189 return 0;
3190}
3191
df1daba7
PB		 3192#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3193
3194static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3195{
c47ada30 3196 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3197 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3198 u64 valid;
3199
3200 /*
3201 * Copy legacy XSAVE area, to avoid complications with CPUID
3202 * leaves 0 and 1 in the loop below.
3203 */
3204 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3205
3206 /* Set XSTATE_BV */
3207 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3208
3209 /*
3210 * Copy each region from the possibly compacted offset to the
3211 * non-compacted offset.
3212 */
3213 valid = xstate_bv & ~XSTATE_FPSSE;
3214 while (valid) {
3215 u64 feature = valid & -valid;
3216 int index = fls64(feature) - 1;
3217 void *src = get_xsave_addr(xsave, feature);
3218
3219 if (src) {
3220 u32 size, offset, ecx, edx;
3221 cpuid_count(XSTATE_CPUID, index,
3222 &size, &offset, &ecx, &edx);
3223 memcpy(dest + offset, src, size);
3224 }
3225
3226 valid -= feature;
3227 }
3228}
3229
3230static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3231{
c47ada30 3232 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3233 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3234 u64 valid;
3235
3236 /*
3237 * Copy legacy XSAVE area, to avoid complications with CPUID
3238 * leaves 0 and 1 in the loop below.
3239 */
3240 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3241
3242 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3243 xsave->header.xfeatures = xstate_bv;
df1daba7 3244 if (cpu_has_xsaves)
3a54450b 3245 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3246
3247 /*
3248 * Copy each region from the non-compacted offset to the
3249 * possibly compacted offset.
3250 */
3251 valid = xstate_bv & ~XSTATE_FPSSE;
3252 while (valid) {
3253 u64 feature = valid & -valid;
3254 int index = fls64(feature) - 1;
3255 void *dest = get_xsave_addr(xsave, feature);
3256
3257 if (dest) {
3258 u32 size, offset, ecx, edx;
3259 cpuid_count(XSTATE_CPUID, index,
3260 &size, &offset, &ecx, &edx);
3261 memcpy(dest, src + offset, size);
3262 } else
3263 WARN_ON_ONCE(1);
3264
3265 valid -= feature;
3266 }
3267}
3268
2d5b5a66
SY		 3269static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3270 struct kvm_xsave *guest_xsave)
3271{
4344ee98 3272 if (cpu_has_xsave) {
df1daba7
PB		 3273 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3274 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3275 } else {
2d5b5a66 3276 memcpy(guest_xsave->region,
7366ed77 3277 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3278 sizeof(struct fxregs_state));
2d5b5a66
SY		 3279 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3280 XSTATE_FPSSE;
3281 }
3282}
3283
3284static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3285 struct kvm_xsave *guest_xsave)
3286{
3287 u64 xstate_bv =
3288 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3289
d7876f1b
PB		 3290 if (cpu_has_xsave) {
3291 /*
3292 * Here we allow setting states that are not present in
3293 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3294 * with old userspace.
3295 */
4ff41732 3296 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3297 return -EINVAL;
df1daba7 3298 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3299 } else {
2d5b5a66
SY		 3300 if (xstate_bv & ~XSTATE_FPSSE)
3301 return -EINVAL;
7366ed77 3302 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3303 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3304 }
3305 return 0;
3306}
3307
3308static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3309 struct kvm_xcrs *guest_xcrs)
3310{
3311 if (!cpu_has_xsave) {
3312 guest_xcrs->nr_xcrs = 0;
3313 return;
3314 }
3315
3316 guest_xcrs->nr_xcrs = 1;
3317 guest_xcrs->flags = 0;
3318 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3319 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3320}
3321
3322static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3323 struct kvm_xcrs *guest_xcrs)
3324{
3325 int i, r = 0;
3326
3327 if (!cpu_has_xsave)
3328 return -EINVAL;
3329
3330 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3331 return -EINVAL;
3332
3333 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3334 /* Only support XCR0 currently */
c67a04cb 3335 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3336 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3337 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3338 break;
3339 }
3340 if (r)
3341 r = -EINVAL;
3342 return r;
3343}
3344
1c0b28c2
EM		 3345/*
3346 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3347 * stopped by the hypervisor. This function will be called from the host only.
3348 * EINVAL is returned when the host attempts to set the flag for a guest that
3349 * does not support pv clocks.
3350 */
3351static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3352{
0b79459b 3353 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3354 return -EINVAL;
51d59c6b 3355 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3356 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3357 return 0;
3358}
3359
313a3dc7
CO		 3360long kvm_arch_vcpu_ioctl(struct file *filp,
3361 unsigned int ioctl, unsigned long arg)
3362{
3363 struct kvm_vcpu *vcpu = filp->private_data;
3364 void __user *argp = (void __user *)arg;
3365 int r;
d1ac91d8
AK		 3366 union {
3367 struct kvm_lapic_state *lapic;
3368 struct kvm_xsave *xsave;
3369 struct kvm_xcrs *xcrs;
3370 void *buffer;
3371 } u;
3372
3373 u.buffer = NULL;
313a3dc7
CO		 3374 switch (ioctl) {
3375 case KVM_GET_LAPIC: {
2204ae3c
MT		 3376 r = -EINVAL;
3377 if (!vcpu->arch.apic)
3378 goto out;
d1ac91d8 3379 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3380
b772ff36 3381 r = -ENOMEM;
d1ac91d8 3382 if (!u.lapic)
b772ff36 3383 goto out;
d1ac91d8 3384 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3385 if (r)
3386 goto out;
3387 r = -EFAULT;
d1ac91d8 3388 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3389 goto out;
3390 r = 0;
3391 break;
3392 }
3393 case KVM_SET_LAPIC: {
2204ae3c
MT		 3394 r = -EINVAL;
3395 if (!vcpu->arch.apic)
3396 goto out;
ff5c2c03 3397 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3398 if (IS_ERR(u.lapic))
3399 return PTR_ERR(u.lapic);
ff5c2c03 3400
d1ac91d8 3401 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3402 break;
3403 }
f77bc6a4
ZX		 3404 case KVM_INTERRUPT: {
3405 struct kvm_interrupt irq;
3406
3407 r = -EFAULT;
3408 if (copy_from_user(&irq, argp, sizeof irq))
3409 goto out;
3410 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3411 break;
3412 }
c4abb7c9
JK		 3413 case KVM_NMI: {
3414 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3415 break;
3416 }
313a3dc7
CO		 3417 case KVM_SET_CPUID: {
3418 struct kvm_cpuid __user *cpuid_arg = argp;
3419 struct kvm_cpuid cpuid;
3420
3421 r = -EFAULT;
3422 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3423 goto out;
3424 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3425 break;
3426 }
07716717
DK		 3427 case KVM_SET_CPUID2: {
3428 struct kvm_cpuid2 __user *cpuid_arg = argp;
3429 struct kvm_cpuid2 cpuid;
3430
3431 r = -EFAULT;
3432 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3433 goto out;
3434 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3435 cpuid_arg->entries);
07716717
DK		 3436 break;
3437 }
3438 case KVM_GET_CPUID2: {
3439 struct kvm_cpuid2 __user *cpuid_arg = argp;
3440 struct kvm_cpuid2 cpuid;
3441
3442 r = -EFAULT;
3443 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3444 goto out;
3445 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3446 cpuid_arg->entries);
07716717
DK		 3447 if (r)
3448 goto out;
3449 r = -EFAULT;
3450 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3451 goto out;
3452 r = 0;
3453 break;
3454 }
313a3dc7
CO		 3455 case KVM_GET_MSRS:
3456 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3457 break;
3458 case KVM_SET_MSRS:
3459 r = msr_io(vcpu, argp, do_set_msr, 0);
3460 break;
b209749f
AK		 3461 case KVM_TPR_ACCESS_REPORTING: {
3462 struct kvm_tpr_access_ctl tac;
3463
3464 r = -EFAULT;
3465 if (copy_from_user(&tac, argp, sizeof tac))
3466 goto out;
3467 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3468 if (r)
3469 goto out;
3470 r = -EFAULT;
3471 if (copy_to_user(argp, &tac, sizeof tac))
3472 goto out;
3473 r = 0;
3474 break;
3475 };
b93463aa
AK		 3476 case KVM_SET_VAPIC_ADDR: {
3477 struct kvm_vapic_addr va;
3478
3479 r = -EINVAL;
3480 if (!irqchip_in_kernel(vcpu->kvm))
3481 goto out;
3482 r = -EFAULT;
3483 if (copy_from_user(&va, argp, sizeof va))
3484 goto out;
fda4e2e8 3485 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3486 break;
3487 }
890ca9ae
HY		 3488 case KVM_X86_SETUP_MCE: {
3489 u64 mcg_cap;
3490
3491 r = -EFAULT;
3492 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3493 goto out;
3494 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3495 break;
3496 }
3497 case KVM_X86_SET_MCE: {
3498 struct kvm_x86_mce mce;
3499
3500 r = -EFAULT;
3501 if (copy_from_user(&mce, argp, sizeof mce))
3502 goto out;
3503 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3504 break;
3505 }
3cfc3092
JK		 3506 case KVM_GET_VCPU_EVENTS: {
3507 struct kvm_vcpu_events events;
3508
3509 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3510
3511 r = -EFAULT;
3512 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3513 break;
3514 r = 0;
3515 break;
3516 }
3517 case KVM_SET_VCPU_EVENTS: {
3518 struct kvm_vcpu_events events;
3519
3520 r = -EFAULT;
3521 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3522 break;
3523
3524 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3525 break;
3526 }
a1efbe77
JK		 3527 case KVM_GET_DEBUGREGS: {
3528 struct kvm_debugregs dbgregs;
3529
3530 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3531
3532 r = -EFAULT;
3533 if (copy_to_user(argp, &dbgregs,
3534 sizeof(struct kvm_debugregs)))
3535 break;
3536 r = 0;
3537 break;
3538 }
3539 case KVM_SET_DEBUGREGS: {
3540 struct kvm_debugregs dbgregs;
3541
3542 r = -EFAULT;
3543 if (copy_from_user(&dbgregs, argp,
3544 sizeof(struct kvm_debugregs)))
3545 break;
3546
3547 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3548 break;
3549 }
2d5b5a66 3550 case KVM_GET_XSAVE: {
d1ac91d8 3551 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3552 r = -ENOMEM;
d1ac91d8 3553 if (!u.xsave)
2d5b5a66
SY		 3554 break;
3555
d1ac91d8 3556 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3557
3558 r = -EFAULT;
d1ac91d8 3559 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3560 break;
3561 r = 0;
3562 break;
3563 }
3564 case KVM_SET_XSAVE: {
ff5c2c03 3565 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3566 if (IS_ERR(u.xsave))
3567 return PTR_ERR(u.xsave);
2d5b5a66 3568
d1ac91d8 3569 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3570 break;
3571 }
3572 case KVM_GET_XCRS: {
d1ac91d8 3573 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3574 r = -ENOMEM;
d1ac91d8 3575 if (!u.xcrs)
2d5b5a66
SY		 3576 break;
3577
d1ac91d8 3578 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3579
3580 r = -EFAULT;
d1ac91d8 3581 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3582 sizeof(struct kvm_xcrs)))
3583 break;
3584 r = 0;
3585 break;
3586 }
3587 case KVM_SET_XCRS: {
ff5c2c03 3588 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3589 if (IS_ERR(u.xcrs))
3590 return PTR_ERR(u.xcrs);
2d5b5a66 3591
d1ac91d8 3592 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3593 break;
3594 }
92a1f12d
JR		 3595 case KVM_SET_TSC_KHZ: {
3596 u32 user_tsc_khz;
3597
3598 r = -EINVAL;
92a1f12d
JR		 3599 user_tsc_khz = (u32)arg;
3600
3601 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3602 goto out;
3603
cc578287
ZA		 3604 if (user_tsc_khz == 0)
3605 user_tsc_khz = tsc_khz;
3606
3607 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3608
3609 r = 0;
3610 goto out;
3611 }
3612 case KVM_GET_TSC_KHZ: {
cc578287 3613 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3614 goto out;
3615 }
1c0b28c2
EM		 3616 case KVM_KVMCLOCK_CTRL: {
3617 r = kvm_set_guest_paused(vcpu);
3618 goto out;
3619 }
313a3dc7
CO		 3620 default:
3621 r = -EINVAL;
3622 }
3623out:
d1ac91d8 3624 kfree(u.buffer);
313a3dc7
CO		 3625 return r;
3626}
3627
5b1c1493
CO		 3628int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3629{
3630 return VM_FAULT_SIGBUS;
3631}
3632
1fe779f8
CO		 3633static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3634{
3635 int ret;
3636
3637 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3638 return -EINVAL;
1fe779f8
CO		 3639 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3640 return ret;
3641}
3642
b927a3ce
SY		 3643static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3644 u64 ident_addr)
3645{
3646 kvm->arch.ept_identity_map_addr = ident_addr;
3647 return 0;
3648}
3649
1fe779f8
CO		 3650static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3651 u32 kvm_nr_mmu_pages)
3652{
3653 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3654 return -EINVAL;
3655
79fac95e 3656 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3657
3658 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3659 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3660
79fac95e 3661 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3662 return 0;
3663}
3664
3665static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3666{
39de71ec 3667 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3668}
3669
1fe779f8
CO		 3670static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3671{
3672 int r;
3673
3674 r = 0;
3675 switch (chip->chip_id) {
3676 case KVM_IRQCHIP_PIC_MASTER:
3677 memcpy(&chip->chip.pic,
3678 &pic_irqchip(kvm)->pics[0],
3679 sizeof(struct kvm_pic_state));
3680 break;
3681 case KVM_IRQCHIP_PIC_SLAVE:
3682 memcpy(&chip->chip.pic,
3683 &pic_irqchip(kvm)->pics[1],
3684 sizeof(struct kvm_pic_state));
3685 break;
3686 case KVM_IRQCHIP_IOAPIC:
eba0226b 3687 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3688 break;
3689 default:
3690 r = -EINVAL;
3691 break;
3692 }
3693 return r;
3694}
3695
3696static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3697{
3698 int r;
3699
3700 r = 0;
3701 switch (chip->chip_id) {
3702 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3703 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3704 memcpy(&pic_irqchip(kvm)->pics[0],
3705 &chip->chip.pic,
3706 sizeof(struct kvm_pic_state));
f4f51050 3707 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3708 break;
3709 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3710 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3711 memcpy(&pic_irqchip(kvm)->pics[1],
3712 &chip->chip.pic,
3713 sizeof(struct kvm_pic_state));
f4f51050 3714 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3715 break;
3716 case KVM_IRQCHIP_IOAPIC:
eba0226b 3717 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3718 break;
3719 default:
3720 r = -EINVAL;
3721 break;
3722 }
3723 kvm_pic_update_irq(pic_irqchip(kvm));
3724 return r;
3725}
3726
e0f63cb9
SY		 3727static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3728{
3729 int r = 0;
3730
894a9c55 3731 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3732 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3733 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3734 return r;
3735}
3736
3737static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3738{
3739 int r = 0;
3740
894a9c55 3741 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3742 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3743 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3744 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3745 return r;
3746}
3747
3748static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3749{
3750 int r = 0;
3751
3752 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3753 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3754 sizeof(ps->channels));
3755 ps->flags = kvm->arch.vpit->pit_state.flags;
3756 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3757 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3758 return r;
3759}
3760
3761static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3762{
3763 int r = 0, start = 0;
3764 u32 prev_legacy, cur_legacy;
3765 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3766 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3767 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3768 if (!prev_legacy && cur_legacy)
3769 start = 1;
3770 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3771 sizeof(kvm->arch.vpit->pit_state.channels));
3772 kvm->arch.vpit->pit_state.flags = ps->flags;
3773 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3774 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3775 return r;
3776}
3777
52d939a0
MT		 3778static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3779 struct kvm_reinject_control *control)
3780{
3781 if (!kvm->arch.vpit)
3782 return -ENXIO;
894a9c55 3783 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3784 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3785 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3786 return 0;
3787}
3788
95d4c16c 3789/**
60c34612
TY		 3790 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3791 * @kvm: kvm instance
3792 * @log: slot id and address to which we copy the log
95d4c16c 3793 *
e108ff2f
PB		 3794 * Steps 1-4 below provide general overview of dirty page logging. See
3795 * kvm_get_dirty_log_protect() function description for additional details.
3796 *
3797 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3798 * always flush the TLB (step 4) even if previous step failed and the dirty
3799 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3800 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3801 * writes will be marked dirty for next log read.
95d4c16c 3802 *
60c34612
TY		 3803 * 1. Take a snapshot of the bit and clear it if needed.
3804 * 2. Write protect the corresponding page.
e108ff2f
PB		 3805 * 3. Copy the snapshot to the userspace.
3806 * 4. Flush TLB's if needed.
5bb064dc 3807 */
60c34612 3808int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3809{
60c34612 3810 bool is_dirty = false;
e108ff2f 3811 int r;
5bb064dc 3812
79fac95e 3813 mutex_lock(&kvm->slots_lock);
5bb064dc 3814
88178fd4
KH		 3815 /*
3816 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3817 */
3818 if (kvm_x86_ops->flush_log_dirty)
3819 kvm_x86_ops->flush_log_dirty(kvm);
3820
e108ff2f 3821 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3822
3823 /*
3824 * All the TLBs can be flushed out of mmu lock, see the comments in
3825 * kvm_mmu_slot_remove_write_access().
3826 */
e108ff2f 3827 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3828 if (is_dirty)
3829 kvm_flush_remote_tlbs(kvm);
3830
79fac95e 3831 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3832 return r;
3833}
3834
aa2fbe6d
YZ		 3835int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3836 bool line_status)
23d43cf9
CD		 3837{
3838 if (!irqchip_in_kernel(kvm))
3839 return -ENXIO;
3840
3841 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3842 irq_event->irq, irq_event->level,
3843 line_status);
23d43cf9
CD		 3844 return 0;
3845}
3846
1fe779f8
CO		 3847long kvm_arch_vm_ioctl(struct file *filp,
3848 unsigned int ioctl, unsigned long arg)
3849{
3850 struct kvm *kvm = filp->private_data;
3851 void __user *argp = (void __user *)arg;
367e1319 3852 int r = -ENOTTY;
f0d66275
DH		 3853 /*
3854 * This union makes it completely explicit to gcc-3.x
3855 * that these two variables' stack usage should be
3856 * combined, not added together.
3857 */
3858 union {
3859 struct kvm_pit_state ps;
e9f42757 3860 struct kvm_pit_state2 ps2;
c5ff41ce 3861 struct kvm_pit_config pit_config;
f0d66275 3862 } u;
1fe779f8
CO		 3863
3864 switch (ioctl) {
3865 case KVM_SET_TSS_ADDR:
3866 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3867 break;
b927a3ce
SY		 3868 case KVM_SET_IDENTITY_MAP_ADDR: {
3869 u64 ident_addr;
3870
3871 r = -EFAULT;
3872 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3873 goto out;
3874 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3875 break;
3876 }
1fe779f8
CO		 3877 case KVM_SET_NR_MMU_PAGES:
3878 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3879 break;
3880 case KVM_GET_NR_MMU_PAGES:
3881 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3882 break;
3ddea128
MT		 3883 case KVM_CREATE_IRQCHIP: {
3884 struct kvm_pic *vpic;
3885
3886 mutex_lock(&kvm->lock);
3887 r = -EEXIST;
3888 if (kvm->arch.vpic)
3889 goto create_irqchip_unlock;
3e515705
AK		 3890 r = -EINVAL;
3891 if (atomic_read(&kvm->online_vcpus))
3892 goto create_irqchip_unlock;
1fe779f8 3893 r = -ENOMEM;
3ddea128
MT		 3894 vpic = kvm_create_pic(kvm);
3895 if (vpic) {
1fe779f8
CO		 3896 r = kvm_ioapic_init(kvm);
3897 if (r) {
175504cd 3898 mutex_lock(&kvm->slots_lock);
72bb2fcd 3899 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3900 &vpic->dev_master);
3901 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3902 &vpic->dev_slave);
3903 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3904 &vpic->dev_eclr);
175504cd 3905 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3906 kfree(vpic);
3907 goto create_irqchip_unlock;
1fe779f8
CO		 3908 }
3909 } else
3ddea128
MT		 3910 goto create_irqchip_unlock;
3911 smp_wmb();
3912 kvm->arch.vpic = vpic;
3913 smp_wmb();
399ec807
AK		 3914 r = kvm_setup_default_irq_routing(kvm);
3915 if (r) {
175504cd 3916 mutex_lock(&kvm->slots_lock);
3ddea128 3917 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3918 kvm_ioapic_destroy(kvm);
3919 kvm_destroy_pic(kvm);
3ddea128 3920 mutex_unlock(&kvm->irq_lock);
175504cd 3921 mutex_unlock(&kvm->slots_lock);
399ec807 3922 }
3ddea128
MT		 3923 create_irqchip_unlock:
3924 mutex_unlock(&kvm->lock);
1fe779f8 3925 break;
3ddea128 3926 }
7837699f 3927 case KVM_CREATE_PIT:
c5ff41ce
JK		 3928 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3929 goto create_pit;
3930 case KVM_CREATE_PIT2:
3931 r = -EFAULT;
3932 if (copy_from_user(&u.pit_config, argp,
3933 sizeof(struct kvm_pit_config)))
3934 goto out;
3935 create_pit:
79fac95e 3936 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3937 r = -EEXIST;
3938 if (kvm->arch.vpit)
3939 goto create_pit_unlock;
7837699f 3940 r = -ENOMEM;
c5ff41ce 3941 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3942 if (kvm->arch.vpit)
3943 r = 0;
269e05e4 3944 create_pit_unlock:
79fac95e 3945 mutex_unlock(&kvm->slots_lock);
7837699f 3946 break;
1fe779f8
CO		 3947 case KVM_GET_IRQCHIP: {
3948 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3949 struct kvm_irqchip *chip;
1fe779f8 3950
ff5c2c03
SL		 3951 chip = memdup_user(argp, sizeof(*chip));
3952 if (IS_ERR(chip)) {
3953 r = PTR_ERR(chip);
1fe779f8 3954 goto out;
ff5c2c03
SL		 3955 }
3956
1fe779f8
CO		 3957 r = -ENXIO;
3958 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3959 goto get_irqchip_out;
3960 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3961 if (r)
f0d66275 3962 goto get_irqchip_out;
1fe779f8 3963 r = -EFAULT;
f0d66275
DH		 3964 if (copy_to_user(argp, chip, sizeof *chip))
3965 goto get_irqchip_out;
1fe779f8 3966 r = 0;
f0d66275
DH		 3967 get_irqchip_out:
3968 kfree(chip);
1fe779f8
CO		 3969 break;
3970 }
3971 case KVM_SET_IRQCHIP: {
3972 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3973 struct kvm_irqchip *chip;
1fe779f8 3974
ff5c2c03
SL		 3975 chip = memdup_user(argp, sizeof(*chip));
3976 if (IS_ERR(chip)) {
3977 r = PTR_ERR(chip);
1fe779f8 3978 goto out;
ff5c2c03
SL		 3979 }
3980
1fe779f8
CO		 3981 r = -ENXIO;
3982 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3983 goto set_irqchip_out;
3984 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3985 if (r)
f0d66275 3986 goto set_irqchip_out;
1fe779f8 3987 r = 0;
f0d66275
DH		 3988 set_irqchip_out:
3989 kfree(chip);
1fe779f8
CO		 3990 break;
3991 }
e0f63cb9 3992 case KVM_GET_PIT: {
e0f63cb9 3993 r = -EFAULT;
f0d66275 3994 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3995 goto out;
3996 r = -ENXIO;
3997 if (!kvm->arch.vpit)
3998 goto out;
f0d66275 3999 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4000 if (r)
4001 goto out;
4002 r = -EFAULT;
f0d66275 4003 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4004 goto out;
4005 r = 0;
4006 break;
4007 }
4008 case KVM_SET_PIT: {
e0f63cb9 4009 r = -EFAULT;
f0d66275 4010 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4011 goto out;
4012 r = -ENXIO;
4013 if (!kvm->arch.vpit)
4014 goto out;
f0d66275 4015 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4016 break;
4017 }
e9f42757
BK		 4018 case KVM_GET_PIT2: {
4019 r = -ENXIO;
4020 if (!kvm->arch.vpit)
4021 goto out;
4022 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4023 if (r)
4024 goto out;
4025 r = -EFAULT;
4026 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4027 goto out;
4028 r = 0;
4029 break;
4030 }
4031 case KVM_SET_PIT2: {
4032 r = -EFAULT;
4033 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4034 goto out;
4035 r = -ENXIO;
4036 if (!kvm->arch.vpit)
4037 goto out;
4038 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4039 break;
4040 }
52d939a0
MT		 4041 case KVM_REINJECT_CONTROL: {
4042 struct kvm_reinject_control control;
4043 r = -EFAULT;
4044 if (copy_from_user(&control, argp, sizeof(control)))
4045 goto out;
4046 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4047 break;
4048 }
ffde22ac
ES		 4049 case KVM_XEN_HVM_CONFIG: {
4050 r = -EFAULT;
4051 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4052 sizeof(struct kvm_xen_hvm_config)))
4053 goto out;
4054 r = -EINVAL;
4055 if (kvm->arch.xen_hvm_config.flags)
4056 goto out;
4057 r = 0;
4058 break;
4059 }
afbcf7ab 4060 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4061 struct kvm_clock_data user_ns;
4062 u64 now_ns;
4063 s64 delta;
4064
4065 r = -EFAULT;
4066 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4067 goto out;
4068
4069 r = -EINVAL;
4070 if (user_ns.flags)
4071 goto out;
4072
4073 r = 0;
395c6b0a 4074 local_irq_disable();
759379dd 4075 now_ns = get_kernel_ns();
afbcf7ab 4076 delta = user_ns.clock - now_ns;
395c6b0a 4077 local_irq_enable();
afbcf7ab 4078 kvm->arch.kvmclock_offset = delta;
2e762ff7 4079 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4080 break;
4081 }
4082 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4083 struct kvm_clock_data user_ns;
4084 u64 now_ns;
4085
395c6b0a 4086 local_irq_disable();
759379dd 4087 now_ns = get_kernel_ns();
afbcf7ab 4088 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4089 local_irq_enable();
afbcf7ab 4090 user_ns.flags = 0;
97e69aa6 4091 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4092
4093 r = -EFAULT;
4094 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4095 goto out;
4096 r = 0;
4097 break;
4098 }
4099
1fe779f8 4100 default:
c274e03a 4101 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4102 }
4103out:
4104 return r;
4105}
4106
a16b043c 4107static void kvm_init_msr_list(void)
043405e1
CO		 4108{
4109 u32 dummy[2];
4110 unsigned i, j;
4111
e3267cbb
GC		 4112 /* skip the first msrs in the list. KVM-specific */
4113 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4114 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4115 continue;
93c4adc7
PB		 4116
4117 /*
4118 * Even MSRs that are valid in the host may not be exposed
4119 * to the guests in some cases. We could work around this
4120 * in VMX with the generic MSR save/load machinery, but it
4121 * is not really worthwhile since it will really only
4122 * happen with nested virtualization.
4123 */
4124 switch (msrs_to_save[i]) {
4125 case MSR_IA32_BNDCFGS:
4126 if (!kvm_x86_ops->mpx_supported())
4127 continue;
4128 break;
4129 default:
4130 break;
4131 }
4132
043405e1
CO		 4133 if (j < i)
4134 msrs_to_save[j] = msrs_to_save[i];
4135 j++;
4136 }
4137 num_msrs_to_save = j;
4138}
4139
bda9020e
MT		 4140static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4141 const void *v)
bbd9b64e 4142{
70252a10
AK		 4143 int handled = 0;
4144 int n;
4145
4146 do {
4147 n = min(len, 8);
4148 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4149 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4150 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4151 break;
4152 handled += n;
4153 addr += n;
4154 len -= n;
4155 v += n;
4156 } while (len);
bbd9b64e 4157
70252a10 4158 return handled;
bbd9b64e
CO		 4159}
4160
bda9020e 4161static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4162{
70252a10
AK		 4163 int handled = 0;
4164 int n;
4165
4166 do {
4167 n = min(len, 8);
4168 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4169 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4170 addr, n, v))
4171 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4172 break;
4173 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4174 handled += n;
4175 addr += n;
4176 len -= n;
4177 v += n;
4178 } while (len);
bbd9b64e 4179
70252a10 4180 return handled;
bbd9b64e
CO		 4181}
4182
2dafc6c2
GN		 4183static void kvm_set_segment(struct kvm_vcpu *vcpu,
4184 struct kvm_segment *var, int seg)
4185{
4186 kvm_x86_ops->set_segment(vcpu, var, seg);
4187}
4188
4189void kvm_get_segment(struct kvm_vcpu *vcpu,
4190 struct kvm_segment *var, int seg)
4191{
4192 kvm_x86_ops->get_segment(vcpu, var, seg);
4193}
4194
54987b7a
PB		 4195gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4196 struct x86_exception *exception)
02f59dc9
JR		 4197{
4198 gpa_t t_gpa;
02f59dc9
JR		 4199
4200 BUG_ON(!mmu_is_nested(vcpu));
4201
4202 /* NPT walks are always user-walks */
4203 access |= PFERR_USER_MASK;
54987b7a 4204 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4205
4206 return t_gpa;
4207}
4208
ab9ae313
AK		 4209gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4210 struct x86_exception *exception)
1871c602
GN		 4211{
4212 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4213 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4214}
4215
ab9ae313
AK		 4216 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4217 struct x86_exception *exception)
1871c602
GN		 4218{
4219 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4220 access |= PFERR_FETCH_MASK;
ab9ae313 4221 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4222}
4223
ab9ae313
AK		 4224gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4225 struct x86_exception *exception)
1871c602
GN		 4226{
4227 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4228 access |= PFERR_WRITE_MASK;
ab9ae313 4229 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4230}
4231
4232/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4233gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4234 struct x86_exception *exception)
1871c602 4235{
ab9ae313 4236 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4237}
4238
4239static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4240 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4241 struct x86_exception *exception)
bbd9b64e
CO		 4242{
4243 void *data = val;
10589a46 4244 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4245
4246 while (bytes) {
14dfe855 4247 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4248 exception);
bbd9b64e 4249 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4250 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4251 int ret;
4252
bcc55cba 4253 if (gpa == UNMAPPED_GVA)
ab9ae313 4254 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4255 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4256 offset, toread);
10589a46 4257 if (ret < 0) {
c3cd7ffa 4258 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4259 goto out;
4260 }
bbd9b64e 4261
77c2002e
IE		 4262 bytes -= toread;
4263 data += toread;
4264 addr += toread;
bbd9b64e 4265 }
10589a46 4266out:
10589a46 4267 return r;
bbd9b64e 4268}
77c2002e 4269
1871c602 4270/* used for instruction fetching */
0f65dd70
AK		 4271static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4272 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4273 struct x86_exception *exception)
1871c602 4274{
0f65dd70 4275 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4276 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4277 unsigned offset;
4278 int ret;
0f65dd70 4279
44583cba
PB		 4280 /* Inline kvm_read_guest_virt_helper for speed. */
4281 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4282 exception);
4283 if (unlikely(gpa == UNMAPPED_GVA))
4284 return X86EMUL_PROPAGATE_FAULT;
4285
4286 offset = addr & (PAGE_SIZE-1);
4287 if (WARN_ON(offset + bytes > PAGE_SIZE))
4288 bytes = (unsigned)PAGE_SIZE - offset;
4289 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4290 offset, bytes);
4291 if (unlikely(ret < 0))
4292 return X86EMUL_IO_NEEDED;
4293
4294 return X86EMUL_CONTINUE;
1871c602
GN		 4295}
4296
064aea77 4297int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4298 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4299 struct x86_exception *exception)
1871c602 4300{
0f65dd70 4301 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4302 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4303
1871c602 4304 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4305 exception);
1871c602 4306}
064aea77 4307EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4308
0f65dd70
AK		 4309static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4310 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4311 struct x86_exception *exception)
1871c602 4312{
0f65dd70 4313 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4314 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4315}
4316
6a4d7550 4317int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4318 gva_t addr, void *val,
2dafc6c2 4319 unsigned int bytes,
bcc55cba 4320 struct x86_exception *exception)
77c2002e 4321{
0f65dd70 4322 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4323 void *data = val;
4324 int r = X86EMUL_CONTINUE;
4325
4326 while (bytes) {
14dfe855
JR		 4327 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4328 PFERR_WRITE_MASK,
ab9ae313 4329 exception);
77c2002e
IE		 4330 unsigned offset = addr & (PAGE_SIZE-1);
4331 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4332 int ret;
4333
bcc55cba 4334 if (gpa == UNMAPPED_GVA)
ab9ae313 4335 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4336 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4337 if (ret < 0) {
c3cd7ffa 4338 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4339 goto out;
4340 }
4341
4342 bytes -= towrite;
4343 data += towrite;
4344 addr += towrite;
4345 }
4346out:
4347 return r;
4348}
6a4d7550 4349EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4350
af7cc7d1
XG		 4351static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4352 gpa_t *gpa, struct x86_exception *exception,
4353 bool write)
4354{
97d64b78
AK		 4355 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4356 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4357
97d64b78 4358 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4359 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4360 vcpu->arch.access, access)) {
bebb106a
XG		 4361 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4362 (gva & (PAGE_SIZE - 1));
4f022648 4363 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4364 return 1;
4365 }
4366
af7cc7d1
XG		 4367 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4368
4369 if (*gpa == UNMAPPED_GVA)
4370 return -1;
4371
4372 /* For APIC access vmexit */
4373 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4374 return 1;
4375
4f022648
XG		 4376 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4377 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4378 return 1;
4f022648 4379 }
bebb106a 4380
af7cc7d1
XG		 4381 return 0;
4382}
4383
3200f405 4384int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4385 const void *val, int bytes)
bbd9b64e
CO		 4386{
4387 int ret;
4388
4389 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4390 if (ret < 0)
bbd9b64e 4391 return 0;
f57f2ef5 4392 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4393 return 1;
4394}
4395
77d197b2
XG		 4396struct read_write_emulator_ops {
4397 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4398 int bytes);
4399 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4400 void *val, int bytes);
4401 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4402 int bytes, void *val);
4403 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4404 void *val, int bytes);
4405 bool write;
4406};
4407
4408static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4409{
4410 if (vcpu->mmio_read_completed) {
77d197b2 4411 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4412 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4413 vcpu->mmio_read_completed = 0;
4414 return 1;
4415 }
4416
4417 return 0;
4418}
4419
4420static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4421 void *val, int bytes)
4422{
4423 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4424}
4425
4426static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4427 void *val, int bytes)
4428{
4429 return emulator_write_phys(vcpu, gpa, val, bytes);
4430}
4431
4432static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4433{
4434 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4435 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4436}
4437
4438static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4439 void *val, int bytes)
4440{
4441 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4442 return X86EMUL_IO_NEEDED;
4443}
4444
4445static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4446 void *val, int bytes)
4447{
f78146b0
AK		 4448 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4449
87da7e66 4450 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4451 return X86EMUL_CONTINUE;
4452}
4453
0fbe9b0b 4454static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4455 .read_write_prepare = read_prepare,
4456 .read_write_emulate = read_emulate,
4457 .read_write_mmio = vcpu_mmio_read,
4458 .read_write_exit_mmio = read_exit_mmio,
4459};
4460
0fbe9b0b 4461static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4462 .read_write_emulate = write_emulate,
4463 .read_write_mmio = write_mmio,
4464 .read_write_exit_mmio = write_exit_mmio,
4465 .write = true,
4466};
4467
22388a3c
XG		 4468static int emulator_read_write_onepage(unsigned long addr, void *val,
4469 unsigned int bytes,
4470 struct x86_exception *exception,
4471 struct kvm_vcpu *vcpu,
0fbe9b0b 4472 const struct read_write_emulator_ops *ops)
bbd9b64e 4473{
af7cc7d1
XG		 4474 gpa_t gpa;
4475 int handled, ret;
22388a3c 4476 bool write = ops->write;
f78146b0 4477 struct kvm_mmio_fragment *frag;
10589a46 4478
22388a3c 4479 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4480
af7cc7d1 4481 if (ret < 0)
bbd9b64e 4482 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4483
4484 /* For APIC access vmexit */
af7cc7d1 4485 if (ret)
bbd9b64e
CO		 4486 goto mmio;
4487
22388a3c 4488 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4489 return X86EMUL_CONTINUE;
4490
4491mmio:
4492 /*
4493 * Is this MMIO handled locally?
4494 */
22388a3c 4495 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4496 if (handled == bytes)
bbd9b64e 4497 return X86EMUL_CONTINUE;
bbd9b64e 4498
70252a10
AK		 4499 gpa += handled;
4500 bytes -= handled;
4501 val += handled;
4502
87da7e66
XG		 4503 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4504 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4505 frag->gpa = gpa;
4506 frag->data = val;
4507 frag->len = bytes;
f78146b0 4508 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4509}
4510
52eb5a6d
XL		 4511static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4512 unsigned long addr,
22388a3c
XG		 4513 void *val, unsigned int bytes,
4514 struct x86_exception *exception,
0fbe9b0b 4515 const struct read_write_emulator_ops *ops)
bbd9b64e 4516{
0f65dd70 4517 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4518 gpa_t gpa;
4519 int rc;
4520
4521 if (ops->read_write_prepare &&
4522 ops->read_write_prepare(vcpu, val, bytes))
4523 return X86EMUL_CONTINUE;
4524
4525 vcpu->mmio_nr_fragments = 0;
0f65dd70 4526
bbd9b64e
CO		 4527 /* Crossing a page boundary? */
4528 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4529 int now;
bbd9b64e
CO		 4530
4531 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4532 rc = emulator_read_write_onepage(addr, val, now, exception,
4533 vcpu, ops);
4534
bbd9b64e
CO		 4535 if (rc != X86EMUL_CONTINUE)
4536 return rc;
4537 addr += now;
bac15531
NA		 4538 if (ctxt->mode != X86EMUL_MODE_PROT64)
4539 addr = (u32)addr;
bbd9b64e
CO		 4540 val += now;
4541 bytes -= now;
4542 }
22388a3c 4543
f78146b0
AK		 4544 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4545 vcpu, ops);
4546 if (rc != X86EMUL_CONTINUE)
4547 return rc;
4548
4549 if (!vcpu->mmio_nr_fragments)
4550 return rc;
4551
4552 gpa = vcpu->mmio_fragments[0].gpa;
4553
4554 vcpu->mmio_needed = 1;
4555 vcpu->mmio_cur_fragment = 0;
4556
87da7e66 4557 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4558 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4559 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4560 vcpu->run->mmio.phys_addr = gpa;
4561
4562 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4563}
4564
4565static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4566 unsigned long addr,
4567 void *val,
4568 unsigned int bytes,
4569 struct x86_exception *exception)
4570{
4571 return emulator_read_write(ctxt, addr, val, bytes,
4572 exception, &read_emultor);
4573}
4574
52eb5a6d 4575static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4576 unsigned long addr,
4577 const void *val,
4578 unsigned int bytes,
4579 struct x86_exception *exception)
4580{
4581 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4582 exception, &write_emultor);
bbd9b64e 4583}
bbd9b64e 4584
daea3e73
AK		 4585#define CMPXCHG_TYPE(t, ptr, old, new) \
4586 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4587
4588#ifdef CONFIG_X86_64
4589# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4590#else
4591# define CMPXCHG64(ptr, old, new) \
9749a6c0 4592 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4593#endif
4594
0f65dd70
AK		 4595static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4596 unsigned long addr,
bbd9b64e
CO		 4597 const void *old,
4598 const void *new,
4599 unsigned int bytes,
0f65dd70 4600 struct x86_exception *exception)
bbd9b64e 4601{
0f65dd70 4602 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4603 gpa_t gpa;
4604 struct page *page;
4605 char *kaddr;
4606 bool exchanged;
2bacc55c 4607
daea3e73
AK		 4608 /* guests cmpxchg8b have to be emulated atomically */
4609 if (bytes > 8 || (bytes & (bytes - 1)))
4610 goto emul_write;
10589a46 4611
daea3e73 4612 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4613
daea3e73
AK		 4614 if (gpa == UNMAPPED_GVA ||
4615 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4616 goto emul_write;
2bacc55c 4617
daea3e73
AK		 4618 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4619 goto emul_write;
72dc67a6 4620
daea3e73 4621 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4622 if (is_error_page(page))
c19b8bd6 4623 goto emul_write;
72dc67a6 4624
8fd75e12 4625 kaddr = kmap_atomic(page);
daea3e73
AK		 4626 kaddr += offset_in_page(gpa);
4627 switch (bytes) {
4628 case 1:
4629 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4630 break;
4631 case 2:
4632 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4633 break;
4634 case 4:
4635 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4636 break;
4637 case 8:
4638 exchanged = CMPXCHG64(kaddr, old, new);
4639 break;
4640 default:
4641 BUG();
2bacc55c 4642 }
8fd75e12 4643 kunmap_atomic(kaddr);
daea3e73
AK		 4644 kvm_release_page_dirty(page);
4645
4646 if (!exchanged)
4647 return X86EMUL_CMPXCHG_FAILED;
4648
d3714010 4649 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4650 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4651
4652 return X86EMUL_CONTINUE;
4a5f48f6 4653
3200f405 4654emul_write:
daea3e73 4655 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4656
0f65dd70 4657 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4658}
4659
cf8f70bf
GN		 4660static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4661{
4662 /* TODO: String I/O for in kernel device */
4663 int r;
4664
4665 if (vcpu->arch.pio.in)
e32edf4f 4666 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4667 vcpu->arch.pio.size, pd);
4668 else
e32edf4f 4669 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4670 vcpu->arch.pio.port, vcpu->arch.pio.size,
4671 pd);
4672 return r;
4673}
4674
6f6fbe98
XG		 4675static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4676 unsigned short port, void *val,
4677 unsigned int count, bool in)
cf8f70bf 4678{
cf8f70bf 4679 vcpu->arch.pio.port = port;
6f6fbe98 4680 vcpu->arch.pio.in = in;
7972995b 4681 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4682 vcpu->arch.pio.size = size;
4683
4684 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4685 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4686 return 1;
4687 }
4688
4689 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4690 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4691 vcpu->run->io.size = size;
4692 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4693 vcpu->run->io.count = count;
4694 vcpu->run->io.port = port;
4695
4696 return 0;
4697}
4698
6f6fbe98
XG		 4699static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4700 int size, unsigned short port, void *val,
4701 unsigned int count)
cf8f70bf 4702{
ca1d4a9e 4703 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4704 int ret;
ca1d4a9e 4705
6f6fbe98
XG		 4706 if (vcpu->arch.pio.count)
4707 goto data_avail;
cf8f70bf 4708
6f6fbe98
XG		 4709 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4710 if (ret) {
4711data_avail:
4712 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4713 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4714 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4715 return 1;
4716 }
4717
cf8f70bf
GN		 4718 return 0;
4719}
4720
6f6fbe98
XG		 4721static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4722 int size, unsigned short port,
4723 const void *val, unsigned int count)
4724{
4725 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4726
4727 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4728 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4729 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4730}
4731
bbd9b64e
CO		 4732static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4733{
4734 return kvm_x86_ops->get_segment_base(vcpu, seg);
4735}
4736
3cb16fe7 4737static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4738{
3cb16fe7 4739 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4740}
4741
5cb56059 4742int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4743{
4744 if (!need_emulate_wbinvd(vcpu))
4745 return X86EMUL_CONTINUE;
4746
4747 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4748 int cpu = get_cpu();
4749
4750 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4751 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4752 wbinvd_ipi, NULL, 1);
2eec7343 4753 put_cpu();
f5f48ee1 4754 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4755 } else
4756 wbinvd();
f5f48ee1
SY		 4757 return X86EMUL_CONTINUE;
4758}
5cb56059
JS		 4759
4760int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4761{
4762 kvm_x86_ops->skip_emulated_instruction(vcpu);
4763 return kvm_emulate_wbinvd_noskip(vcpu);
4764}
f5f48ee1
SY		 4765EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4766
5cb56059
JS		 4767
4768
bcaf5cc5
AK		 4769static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4770{
5cb56059 4771 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4772}
4773
52eb5a6d
XL		 4774static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4775 unsigned long *dest)
bbd9b64e 4776{
16f8a6f9 4777 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4778}
4779
52eb5a6d
XL		 4780static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4781 unsigned long value)
bbd9b64e 4782{
338dbc97 4783
717746e3 4784 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4785}
4786
52a46617 4787static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4788{
52a46617 4789 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4790}
4791
717746e3 4792static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4793{
717746e3 4794 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4795 unsigned long value;
4796
4797 switch (cr) {
4798 case 0:
4799 value = kvm_read_cr0(vcpu);
4800 break;
4801 case 2:
4802 value = vcpu->arch.cr2;
4803 break;
4804 case 3:
9f8fe504 4805 value = kvm_read_cr3(vcpu);
52a46617
GN		 4806 break;
4807 case 4:
4808 value = kvm_read_cr4(vcpu);
4809 break;
4810 case 8:
4811 value = kvm_get_cr8(vcpu);
4812 break;
4813 default:
a737f256 4814 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4815 return 0;
4816 }
4817
4818 return value;
4819}
4820
717746e3 4821static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4822{
717746e3 4823 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4824 int res = 0;
4825
52a46617
GN		 4826 switch (cr) {
4827 case 0:
49a9b07e 4828 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4829 break;
4830 case 2:
4831 vcpu->arch.cr2 = val;
4832 break;
4833 case 3:
2390218b 4834 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4835 break;
4836 case 4:
a83b29c6 4837 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4838 break;
4839 case 8:
eea1cff9 4840 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4841 break;
4842 default:
a737f256 4843 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4844 res = -1;
52a46617 4845 }
0f12244f
GN		 4846
4847 return res;
52a46617
GN		 4848}
4849
717746e3 4850static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4851{
717746e3 4852 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4853}
4854
4bff1e86 4855static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4856{
4bff1e86 4857 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4858}
4859
4bff1e86 4860static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4861{
4bff1e86 4862 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4863}
4864
1ac9d0cf
AK		 4865static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4866{
4867 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4868}
4869
4870static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4871{
4872 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4873}
4874
4bff1e86
AK		 4875static unsigned long emulator_get_cached_segment_base(
4876 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4877{
4bff1e86 4878 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4879}
4880
1aa36616
AK		 4881static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4882 struct desc_struct *desc, u32 *base3,
4883 int seg)
2dafc6c2
GN		 4884{
4885 struct kvm_segment var;
4886
4bff1e86 4887 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4888 *selector = var.selector;
2dafc6c2 4889
378a8b09
GN		 4890 if (var.unusable) {
4891 memset(desc, 0, sizeof(*desc));
2dafc6c2 4892 return false;
378a8b09 4893 }
2dafc6c2
GN		 4894
4895 if (var.g)
4896 var.limit >>= 12;
4897 set_desc_limit(desc, var.limit);
4898 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4899#ifdef CONFIG_X86_64
4900 if (base3)
4901 *base3 = var.base >> 32;
4902#endif
2dafc6c2
GN		 4903 desc->type = var.type;
4904 desc->s = var.s;
4905 desc->dpl = var.dpl;
4906 desc->p = var.present;
4907 desc->avl = var.avl;
4908 desc->l = var.l;
4909 desc->d = var.db;
4910 desc->g = var.g;
4911
4912 return true;
4913}
4914
1aa36616
AK		 4915static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4916 struct desc_struct *desc, u32 base3,
4917 int seg)
2dafc6c2 4918{
4bff1e86 4919 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4920 struct kvm_segment var;
4921
1aa36616 4922 var.selector = selector;
2dafc6c2 4923 var.base = get_desc_base(desc);
5601d05b
GN		 4924#ifdef CONFIG_X86_64
4925 var.base |= ((u64)base3) << 32;
4926#endif
2dafc6c2
GN		 4927 var.limit = get_desc_limit(desc);
4928 if (desc->g)
4929 var.limit = (var.limit << 12) | 0xfff;
4930 var.type = desc->type;
2dafc6c2
GN		 4931 var.dpl = desc->dpl;
4932 var.db = desc->d;
4933 var.s = desc->s;
4934 var.l = desc->l;
4935 var.g = desc->g;
4936 var.avl = desc->avl;
4937 var.present = desc->p;
4938 var.unusable = !var.present;
4939 var.padding = 0;
4940
4941 kvm_set_segment(vcpu, &var, seg);
4942 return;
4943}
4944
717746e3
AK		 4945static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4946 u32 msr_index, u64 *pdata)
4947{
4948 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4949}
4950
4951static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4952 u32 msr_index, u64 data)
4953{
8fe8ab46
WA		 4954 struct msr_data msr;
4955
4956 msr.data = data;
4957 msr.index = msr_index;
4958 msr.host_initiated = false;
4959 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4960}
4961
67f4d428
NA		 4962static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4963 u32 pmc)
4964{
4965 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4966}
4967
222d21aa
AK		 4968static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4969 u32 pmc, u64 *pdata)
4970{
4971 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4972}
4973
6c3287f7
AK		 4974static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4975{
4976 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4977}
4978
5037f6f3
AK		 4979static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4980{
4981 preempt_disable();
5197b808 4982 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4983 /*
4984 * CR0.TS may reference the host fpu state, not the guest fpu state,
4985 * so it may be clear at this point.
4986 */
4987 clts();
4988}
4989
4990static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4991{
4992 preempt_enable();
4993}
4994
2953538e 4995static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4996 struct x86_instruction_info *info,
c4f035c6
AK		 4997 enum x86_intercept_stage stage)
4998{
2953538e 4999 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5000}
5001
0017f93a 5002static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5003 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5004{
0017f93a 5005 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5006}
5007
dd856efa
AK		 5008static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5009{
5010 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5011}
5012
5013static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5014{
5015 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5016}
5017
801806d9
NA		 5018static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5019{
5020 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5021}
5022
0225fb50 5023static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5024 .read_gpr = emulator_read_gpr,
5025 .write_gpr = emulator_write_gpr,
1871c602 5026 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5027 .write_std = kvm_write_guest_virt_system,
1871c602 5028 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5029 .read_emulated = emulator_read_emulated,
5030 .write_emulated = emulator_write_emulated,
5031 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5032 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5033 .pio_in_emulated = emulator_pio_in_emulated,
5034 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5035 .get_segment = emulator_get_segment,
5036 .set_segment = emulator_set_segment,
5951c442 5037 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5038 .get_gdt = emulator_get_gdt,
160ce1f1 5039 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5040 .set_gdt = emulator_set_gdt,
5041 .set_idt = emulator_set_idt,
52a46617
GN		 5042 .get_cr = emulator_get_cr,
5043 .set_cr = emulator_set_cr,
9c537244 5044 .cpl = emulator_get_cpl,
35aa5375
GN		 5045 .get_dr = emulator_get_dr,
5046 .set_dr = emulator_set_dr,
717746e3
AK		 5047 .set_msr = emulator_set_msr,
5048 .get_msr = emulator_get_msr,
67f4d428 5049 .check_pmc = emulator_check_pmc,
222d21aa 5050 .read_pmc = emulator_read_pmc,
6c3287f7 5051 .halt = emulator_halt,
bcaf5cc5 5052 .wbinvd = emulator_wbinvd,
d6aa1000 5053 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5054 .get_fpu = emulator_get_fpu,
5055 .put_fpu = emulator_put_fpu,
c4f035c6 5056 .intercept = emulator_intercept,
bdb42f5a 5057 .get_cpuid = emulator_get_cpuid,
801806d9 5058 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5059};
5060
95cb2295
GN		 5061static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5062{
37ccdcbe 5063 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5064 /*
5065 * an sti; sti; sequence only disable interrupts for the first
5066 * instruction. So, if the last instruction, be it emulated or
5067 * not, left the system with the INT_STI flag enabled, it
5068 * means that the last instruction is an sti. We should not
5069 * leave the flag on in this case. The same goes for mov ss
5070 */
37ccdcbe
PB		 5071 if (int_shadow & mask)
5072 mask = 0;
6addfc42 5073 if (unlikely(int_shadow || mask)) {
95cb2295 5074 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5075 if (!mask)
5076 kvm_make_request(KVM_REQ_EVENT, vcpu);
5077 }
95cb2295
GN		 5078}
5079
ef54bcfe 5080static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5081{
5082 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5083 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5084 return kvm_propagate_fault(vcpu, &ctxt->exception);
5085
5086 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5087 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5088 ctxt->exception.error_code);
54b8486f 5089 else
da9cb575 5090 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5091 return false;
54b8486f
GN		 5092}
5093
8ec4722d
MG		 5094static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5095{
adf52235 5096 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5097 int cs_db, cs_l;
5098
8ec4722d
MG		 5099 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5100
adf52235
TY		 5101 ctxt->eflags = kvm_get_rflags(vcpu);
5102 ctxt->eip = kvm_rip_read(vcpu);
5103 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5104 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5105 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5106 cs_db ? X86EMUL_MODE_PROT32 :
5107 X86EMUL_MODE_PROT16;
5108 ctxt->guest_mode = is_guest_mode(vcpu);
5109
dd856efa 5110 init_decode_cache(ctxt);
7ae441ea 5111 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5112}
5113
71f9833b 5114int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5115{
9d74191a 5116 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5117 int ret;
5118
5119 init_emulate_ctxt(vcpu);
5120
9dac77fa
AK		 5121 ctxt->op_bytes = 2;
5122 ctxt->ad_bytes = 2;
5123 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5124 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5125
5126 if (ret != X86EMUL_CONTINUE)
5127 return EMULATE_FAIL;
5128
9dac77fa 5129 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5130 kvm_rip_write(vcpu, ctxt->eip);
5131 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5132
5133 if (irq == NMI_VECTOR)
7460fb4a 5134 vcpu->arch.nmi_pending = 0;
63995653
MG		 5135 else
5136 vcpu->arch.interrupt.pending = false;
5137
5138 return EMULATE_DONE;
5139}
5140EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5141
6d77dbfc
GN		 5142static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5143{
fc3a9157
JR		 5144 int r = EMULATE_DONE;
5145
6d77dbfc
GN		 5146 ++vcpu->stat.insn_emulation_fail;
5147 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5148 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5149 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5150 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5151 vcpu->run->internal.ndata = 0;
5152 r = EMULATE_FAIL;
5153 }
6d77dbfc 5154 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5155
5156 return r;
6d77dbfc
GN		 5157}
5158
93c05d3e 5159static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5160 bool write_fault_to_shadow_pgtable,
5161 int emulation_type)
a6f177ef 5162{
95b3cf69 5163 gpa_t gpa = cr2;
8e3d9d06 5164 pfn_t pfn;
a6f177ef 5165
991eebf9
GN		 5166 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5167 return false;
5168
95b3cf69
XG		 5169 if (!vcpu->arch.mmu.direct_map) {
5170 /*
5171 * Write permission should be allowed since only
5172 * write access need to be emulated.
5173 */
5174 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5175
95b3cf69
XG		 5176 /*
5177 * If the mapping is invalid in guest, let cpu retry
5178 * it to generate fault.
5179 */
5180 if (gpa == UNMAPPED_GVA)
5181 return true;
5182 }
a6f177ef 5183
8e3d9d06
XG		 5184 /*
5185 * Do not retry the unhandleable instruction if it faults on the
5186 * readonly host memory, otherwise it will goto a infinite loop:
5187 * retry instruction -> write #PF -> emulation fail -> retry
5188 * instruction -> ...
5189 */
5190 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5191
5192 /*
5193 * If the instruction failed on the error pfn, it can not be fixed,
5194 * report the error to userspace.
5195 */
5196 if (is_error_noslot_pfn(pfn))
5197 return false;
5198
5199 kvm_release_pfn_clean(pfn);
5200
5201 /* The instructions are well-emulated on direct mmu. */
5202 if (vcpu->arch.mmu.direct_map) {
5203 unsigned int indirect_shadow_pages;
5204
5205 spin_lock(&vcpu->kvm->mmu_lock);
5206 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5207 spin_unlock(&vcpu->kvm->mmu_lock);
5208
5209 if (indirect_shadow_pages)
5210 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5211
a6f177ef 5212 return true;
8e3d9d06 5213 }
a6f177ef 5214
95b3cf69
XG		 5215 /*
5216 * if emulation was due to access to shadowed page table
5217 * and it failed try to unshadow page and re-enter the
5218 * guest to let CPU execute the instruction.
5219 */
5220 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5221
5222 /*
5223 * If the access faults on its page table, it can not
5224 * be fixed by unprotecting shadow page and it should
5225 * be reported to userspace.
5226 */
5227 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5228}
5229
1cb3f3ae
XG		 5230static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5231 unsigned long cr2, int emulation_type)
5232{
5233 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5234 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5235
5236 last_retry_eip = vcpu->arch.last_retry_eip;
5237 last_retry_addr = vcpu->arch.last_retry_addr;
5238
5239 /*
5240 * If the emulation is caused by #PF and it is non-page_table
5241 * writing instruction, it means the VM-EXIT is caused by shadow
5242 * page protected, we can zap the shadow page and retry this
5243 * instruction directly.
5244 *
5245 * Note: if the guest uses a non-page-table modifying instruction
5246 * on the PDE that points to the instruction, then we will unmap
5247 * the instruction and go to an infinite loop. So, we cache the
5248 * last retried eip and the last fault address, if we meet the eip
5249 * and the address again, we can break out of the potential infinite
5250 * loop.
5251 */
5252 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5253
5254 if (!(emulation_type & EMULTYPE_RETRY))
5255 return false;
5256
5257 if (x86_page_table_writing_insn(ctxt))
5258 return false;
5259
5260 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5261 return false;
5262
5263 vcpu->arch.last_retry_eip = ctxt->eip;
5264 vcpu->arch.last_retry_addr = cr2;
5265
5266 if (!vcpu->arch.mmu.direct_map)
5267 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5268
22368028 5269 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5270
5271 return true;
5272}
5273
716d51ab
GN		 5274static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5275static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5276
4a1e10d5
PB		 5277static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5278 unsigned long *db)
5279{
5280 u32 dr6 = 0;
5281 int i;
5282 u32 enable, rwlen;
5283
5284 enable = dr7;
5285 rwlen = dr7 >> 16;
5286 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5287 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5288 dr6 |= (1 << i);
5289 return dr6;
5290}
5291
6addfc42 5292static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5293{
5294 struct kvm_run *kvm_run = vcpu->run;
5295
5296 /*
6addfc42
PB		 5297 * rflags is the old, "raw" value of the flags. The new value has
5298 * not been saved yet.
663f4c61
PB		 5299 *
5300 * This is correct even for TF set by the guest, because "the
5301 * processor will not generate this exception after the instruction
5302 * that sets the TF flag".
5303 */
663f4c61
PB		 5304 if (unlikely(rflags & X86_EFLAGS_TF)) {
5305 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5306 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5307 DR6_RTM;
663f4c61
PB		 5308 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5309 kvm_run->debug.arch.exception = DB_VECTOR;
5310 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5311 *r = EMULATE_USER_EXIT;
5312 } else {
5313 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5314 /*
5315 * "Certain debug exceptions may clear bit 0-3. The
5316 * remaining contents of the DR6 register are never
5317 * cleared by the processor".
5318 */
5319 vcpu->arch.dr6 &= ~15;
6f43ed01 5320 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5321 kvm_queue_exception(vcpu, DB_VECTOR);
5322 }
5323 }
5324}
5325
4a1e10d5
PB		 5326static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5327{
4a1e10d5
PB		 5328 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5329 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5330 struct kvm_run *kvm_run = vcpu->run;
5331 unsigned long eip = kvm_get_linear_rip(vcpu);
5332 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5333 vcpu->arch.guest_debug_dr7,
5334 vcpu->arch.eff_db);
5335
5336 if (dr6 != 0) {
6f43ed01 5337 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5338 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5339 kvm_run->debug.arch.exception = DB_VECTOR;
5340 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5341 *r = EMULATE_USER_EXIT;
5342 return true;
5343 }
5344 }
5345
4161a569
NA		 5346 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5347 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5348 unsigned long eip = kvm_get_linear_rip(vcpu);
5349 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5350 vcpu->arch.dr7,
5351 vcpu->arch.db);
5352
5353 if (dr6 != 0) {
5354 vcpu->arch.dr6 &= ~15;
6f43ed01 5355 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5356 kvm_queue_exception(vcpu, DB_VECTOR);
5357 *r = EMULATE_DONE;
5358 return true;
5359 }
5360 }
5361
5362 return false;
5363}
5364
51d8b661
AP		 5365int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5366 unsigned long cr2,
dc25e89e
AP		 5367 int emulation_type,
5368 void *insn,
5369 int insn_len)
bbd9b64e 5370{
95cb2295 5371 int r;
9d74191a 5372 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5373 bool writeback = true;
93c05d3e 5374 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5375
93c05d3e
XG		 5376 /*
5377 * Clear write_fault_to_shadow_pgtable here to ensure it is
5378 * never reused.
5379 */
5380 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5381 kvm_clear_exception_queue(vcpu);
8d7d8102 5382
571008da 5383 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5384 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5385
5386 /*
5387 * We will reenter on the same instruction since
5388 * we do not set complete_userspace_io. This does not
5389 * handle watchpoints yet, those would be handled in
5390 * the emulate_ops.
5391 */
5392 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5393 return r;
5394
9d74191a
TY		 5395 ctxt->interruptibility = 0;
5396 ctxt->have_exception = false;
e0ad0b47 5397 ctxt->exception.vector = -1;
9d74191a 5398 ctxt->perm_ok = false;
bbd9b64e 5399
b51e974f 5400 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5401
9d74191a 5402 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5403
e46479f8 5404 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5405 ++vcpu->stat.insn_emulation;
1d2887e2 5406 if (r != EMULATION_OK) {
4005996e
AK		 5407 if (emulation_type & EMULTYPE_TRAP_UD)
5408 return EMULATE_FAIL;
991eebf9
GN		 5409 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5410 emulation_type))
bbd9b64e 5411 return EMULATE_DONE;
6d77dbfc
GN		 5412 if (emulation_type & EMULTYPE_SKIP)
5413 return EMULATE_FAIL;
5414 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5415 }
5416 }
5417
ba8afb6b 5418 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5419 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5420 if (ctxt->eflags & X86_EFLAGS_RF)
5421 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5422 return EMULATE_DONE;
5423 }
5424
1cb3f3ae
XG		 5425 if (retry_instruction(ctxt, cr2, emulation_type))
5426 return EMULATE_DONE;
5427
7ae441ea 5428 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5429 changes registers values during IO operation */
7ae441ea
GN		 5430 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5431 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5432 emulator_invalidate_register_cache(ctxt);
7ae441ea 5433 }
4d2179e1 5434
5cd21917 5435restart:
9d74191a 5436 r = x86_emulate_insn(ctxt);
bbd9b64e 5437
775fde86
JR		 5438 if (r == EMULATION_INTERCEPTED)
5439 return EMULATE_DONE;
5440
d2ddd1c4 5441 if (r == EMULATION_FAILED) {
991eebf9
GN		 5442 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5443 emulation_type))
c3cd7ffa
GN		 5444 return EMULATE_DONE;
5445
6d77dbfc 5446 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5447 }
5448
9d74191a 5449 if (ctxt->have_exception) {
d2ddd1c4 5450 r = EMULATE_DONE;
ef54bcfe
PB		 5451 if (inject_emulated_exception(vcpu))
5452 return r;
d2ddd1c4 5453 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5454 if (!vcpu->arch.pio.in) {
5455 /* FIXME: return into emulator if single-stepping. */
3457e419 5456 vcpu->arch.pio.count = 0;
0912c977 5457 } else {
7ae441ea 5458 writeback = false;
716d51ab
GN		 5459 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5460 }
ac0a48c3 5461 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5462 } else if (vcpu->mmio_needed) {
5463 if (!vcpu->mmio_is_write)
5464 writeback = false;
ac0a48c3 5465 r = EMULATE_USER_EXIT;
716d51ab 5466 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5467 } else if (r == EMULATION_RESTART)
5cd21917 5468 goto restart;
d2ddd1c4
GN		 5469 else
5470 r = EMULATE_DONE;
f850e2e6 5471
7ae441ea 5472 if (writeback) {
6addfc42 5473 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5474 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5475 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5476 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5477 if (r == EMULATE_DONE)
6addfc42 5478 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5479 if (!ctxt->have_exception ||
5480 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5481 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5482
5483 /*
5484 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5485 * do nothing, and it will be requested again as soon as
5486 * the shadow expires. But we still need to check here,
5487 * because POPF has no interrupt shadow.
5488 */
5489 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5490 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5491 } else
5492 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5493
5494 return r;
de7d789a 5495}
51d8b661 5496EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5497
cf8f70bf 5498int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5499{
cf8f70bf 5500 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5501 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5502 size, port, &val, 1);
cf8f70bf 5503 /* do not return to emulator after return from userspace */
7972995b 5504 vcpu->arch.pio.count = 0;
de7d789a
CO		 5505 return ret;
5506}
cf8f70bf 5507EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5508
8cfdc000
ZA		 5509static void tsc_bad(void *info)
5510{
0a3aee0d 5511 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5512}
5513
5514static void tsc_khz_changed(void *data)
c8076604 5515{
8cfdc000
ZA		 5516 struct cpufreq_freqs *freq = data;
5517 unsigned long khz = 0;
5518
5519 if (data)
5520 khz = freq->new;
5521 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5522 khz = cpufreq_quick_get(raw_smp_processor_id());
5523 if (!khz)
5524 khz = tsc_khz;
0a3aee0d 5525 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5526}
5527
c8076604
GH		 5528static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5529 void *data)
5530{
5531 struct cpufreq_freqs *freq = data;
5532 struct kvm *kvm;
5533 struct kvm_vcpu *vcpu;
5534 int i, send_ipi = 0;
5535
8cfdc000
ZA		 5536 /*
5537 * We allow guests to temporarily run on slowing clocks,
5538 * provided we notify them after, or to run on accelerating
5539 * clocks, provided we notify them before. Thus time never
5540 * goes backwards.
5541 *
5542 * However, we have a problem. We can't atomically update
5543 * the frequency of a given CPU from this function; it is
5544 * merely a notifier, which can be called from any CPU.
5545 * Changing the TSC frequency at arbitrary points in time
5546 * requires a recomputation of local variables related to
5547 * the TSC for each VCPU. We must flag these local variables
5548 * to be updated and be sure the update takes place with the
5549 * new frequency before any guests proceed.
5550 *
5551 * Unfortunately, the combination of hotplug CPU and frequency
5552 * change creates an intractable locking scenario; the order
5553 * of when these callouts happen is undefined with respect to
5554 * CPU hotplug, and they can race with each other. As such,
5555 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5556 * undefined; you can actually have a CPU frequency change take
5557 * place in between the computation of X and the setting of the
5558 * variable. To protect against this problem, all updates of
5559 * the per_cpu tsc_khz variable are done in an interrupt
5560 * protected IPI, and all callers wishing to update the value
5561 * must wait for a synchronous IPI to complete (which is trivial
5562 * if the caller is on the CPU already). This establishes the
5563 * necessary total order on variable updates.
5564 *
5565 * Note that because a guest time update may take place
5566 * anytime after the setting of the VCPU's request bit, the
5567 * correct TSC value must be set before the request. However,
5568 * to ensure the update actually makes it to any guest which
5569 * starts running in hardware virtualization between the set
5570 * and the acquisition of the spinlock, we must also ping the
5571 * CPU after setting the request bit.
5572 *
5573 */
5574
c8076604
GH		 5575 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5576 return 0;
5577 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5578 return 0;
8cfdc000
ZA		 5579
5580 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5581
2f303b74 5582 spin_lock(&kvm_lock);
c8076604 5583 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5584 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5585 if (vcpu->cpu != freq->cpu)
5586 continue;
c285545f 5587 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5588 if (vcpu->cpu != smp_processor_id())
8cfdc000 5589 send_ipi = 1;
c8076604
GH		 5590 }
5591 }
2f303b74 5592 spin_unlock(&kvm_lock);
c8076604
GH		 5593
5594 if (freq->old < freq->new && send_ipi) {
5595 /*
5596 * We upscale the frequency. Must make the guest
5597 * doesn't see old kvmclock values while running with
5598 * the new frequency, otherwise we risk the guest sees
5599 * time go backwards.
5600 *
5601 * In case we update the frequency for another cpu
5602 * (which might be in guest context) send an interrupt
5603 * to kick the cpu out of guest context. Next time
5604 * guest context is entered kvmclock will be updated,
5605 * so the guest will not see stale values.
5606 */
8cfdc000 5607 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5608 }
5609 return 0;
5610}
5611
5612static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5613 .notifier_call = kvmclock_cpufreq_notifier
5614};
5615
5616static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5617 unsigned long action, void *hcpu)
5618{
5619 unsigned int cpu = (unsigned long)hcpu;
5620
5621 switch (action) {
5622 case CPU_ONLINE:
5623 case CPU_DOWN_FAILED:
5624 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5625 break;
5626 case CPU_DOWN_PREPARE:
5627 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5628 break;
5629 }
5630 return NOTIFY_OK;
5631}
5632
5633static struct notifier_block kvmclock_cpu_notifier_block = {
5634 .notifier_call = kvmclock_cpu_notifier,
5635 .priority = -INT_MAX
c8076604
GH		 5636};
5637
b820cc0c
ZA		 5638static void kvm_timer_init(void)
5639{
5640 int cpu;
5641
c285545f 5642 max_tsc_khz = tsc_khz;
460dd42e
SB		 5643
5644 cpu_notifier_register_begin();
b820cc0c 5645 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5646#ifdef CONFIG_CPU_FREQ
5647 struct cpufreq_policy policy;
5648 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5649 cpu = get_cpu();
5650 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5651 if (policy.cpuinfo.max_freq)
5652 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5653 put_cpu();
c285545f 5654#endif
b820cc0c
ZA		 5655 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5656 CPUFREQ_TRANSITION_NOTIFIER);
5657 }
c285545f 5658 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5659 for_each_online_cpu(cpu)
5660 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5661
5662 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5663 cpu_notifier_register_done();
5664
b820cc0c
ZA		 5665}
5666
ff9d07a0
ZY		 5667static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5668
f5132b01 5669int kvm_is_in_guest(void)
ff9d07a0 5670{
086c9855 5671 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5672}
5673
5674static int kvm_is_user_mode(void)
5675{
5676 int user_mode = 3;
dcf46b94 5677
086c9855
AS		 5678 if (__this_cpu_read(current_vcpu))
5679 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5680
ff9d07a0
ZY		 5681 return user_mode != 0;
5682}
5683
5684static unsigned long kvm_get_guest_ip(void)
5685{
5686 unsigned long ip = 0;
dcf46b94 5687
086c9855
AS		 5688 if (__this_cpu_read(current_vcpu))
5689 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5690
ff9d07a0
ZY		 5691 return ip;
5692}
5693
5694static struct perf_guest_info_callbacks kvm_guest_cbs = {
5695 .is_in_guest = kvm_is_in_guest,
5696 .is_user_mode = kvm_is_user_mode,
5697 .get_guest_ip = kvm_get_guest_ip,
5698};
5699
5700void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5701{
086c9855 5702 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5703}
5704EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5705
5706void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5707{
086c9855 5708 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5709}
5710EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5711
ce88decf
XG		 5712static void kvm_set_mmio_spte_mask(void)
5713{
5714 u64 mask;
5715 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5716
5717 /*
5718 * Set the reserved bits and the present bit of an paging-structure
5719 * entry to generate page fault with PFER.RSV = 1.
5720 */
885032b9 5721 /* Mask the reserved physical address bits. */
d1431483 5722 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5723
5724 /* Bit 62 is always reserved for 32bit host. */
5725 mask |= 0x3ull << 62;
5726
5727 /* Set the present bit. */
ce88decf
XG		 5728 mask |= 1ull;
5729
5730#ifdef CONFIG_X86_64
5731 /*
5732 * If reserved bit is not supported, clear the present bit to disable
5733 * mmio page fault.
5734 */
5735 if (maxphyaddr == 52)
5736 mask &= ~1ull;
5737#endif
5738
5739 kvm_mmu_set_mmio_spte_mask(mask);
5740}
5741
16e8d74d
MT		 5742#ifdef CONFIG_X86_64
5743static void pvclock_gtod_update_fn(struct work_struct *work)
5744{
d828199e
MT		 5745 struct kvm *kvm;
5746
5747 struct kvm_vcpu *vcpu;
5748 int i;
5749
2f303b74 5750 spin_lock(&kvm_lock);
d828199e
MT		 5751 list_for_each_entry(kvm, &vm_list, vm_list)
5752 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5753 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5754 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5755 spin_unlock(&kvm_lock);
16e8d74d
MT		 5756}
5757
5758static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5759
5760/*
5761 * Notification about pvclock gtod data update.
5762 */
5763static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5764 void *priv)
5765{
5766 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5767 struct timekeeper *tk = priv;
5768
5769 update_pvclock_gtod(tk);
5770
5771 /* disable master clock if host does not trust, or does not
5772 * use, TSC clocksource
5773 */
5774 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5775 atomic_read(&kvm_guest_has_master_clock) != 0)
5776 queue_work(system_long_wq, &pvclock_gtod_work);
5777
5778 return 0;
5779}
5780
5781static struct notifier_block pvclock_gtod_notifier = {
5782 .notifier_call = pvclock_gtod_notify,
5783};
5784#endif
5785
f8c16bba 5786int kvm_arch_init(void *opaque)
043405e1 5787{
b820cc0c 5788 int r;
6b61edf7 5789 struct kvm_x86_ops *ops = opaque;
f8c16bba 5790
f8c16bba
ZX		 5791 if (kvm_x86_ops) {
5792 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5793 r = -EEXIST;
5794 goto out;
f8c16bba
ZX		 5795 }
5796
5797 if (!ops->cpu_has_kvm_support()) {
5798 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5799 r = -EOPNOTSUPP;
5800 goto out;
f8c16bba
ZX		 5801 }
5802 if (ops->disabled_by_bios()) {
5803 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5804 r = -EOPNOTSUPP;
5805 goto out;
f8c16bba
ZX		 5806 }
5807
013f6a5d
MT		 5808 r = -ENOMEM;
5809 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5810 if (!shared_msrs) {
5811 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5812 goto out;
5813 }
5814
97db56ce
AK		 5815 r = kvm_mmu_module_init();
5816 if (r)
013f6a5d 5817 goto out_free_percpu;
97db56ce 5818
ce88decf 5819 kvm_set_mmio_spte_mask();
97db56ce 5820
f8c16bba 5821 kvm_x86_ops = ops;
920c8377 5822
7b52345e 5823 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5824 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5825
b820cc0c 5826 kvm_timer_init();
c8076604 5827
ff9d07a0
ZY		 5828 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5829
2acf923e
DC		 5830 if (cpu_has_xsave)
5831 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5832
c5cc421b 5833 kvm_lapic_init();
16e8d74d
MT		 5834#ifdef CONFIG_X86_64
5835 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5836#endif
5837
f8c16bba 5838 return 0;
56c6d28a 5839
013f6a5d
MT		 5840out_free_percpu:
5841 free_percpu(shared_msrs);
56c6d28a 5842out:
56c6d28a 5843 return r;
043405e1 5844}
8776e519 5845
f8c16bba
ZX		 5846void kvm_arch_exit(void)
5847{
ff9d07a0
ZY		 5848 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5849
888d256e
JK		 5850 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5851 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5852 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5853 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5854#ifdef CONFIG_X86_64
5855 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5856#endif
f8c16bba 5857 kvm_x86_ops = NULL;
56c6d28a 5858 kvm_mmu_module_exit();
013f6a5d 5859 free_percpu(shared_msrs);
56c6d28a 5860}
f8c16bba 5861
5cb56059 5862int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5863{
5864 ++vcpu->stat.halt_exits;
5865 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5866 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5867 return 1;
5868 } else {
5869 vcpu->run->exit_reason = KVM_EXIT_HLT;
5870 return 0;
5871 }
5872}
5cb56059
JS		 5873EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5874
5875int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5876{
5877 kvm_x86_ops->skip_emulated_instruction(vcpu);
5878 return kvm_vcpu_halt(vcpu);
5879}
8776e519
HB		 5880EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5881
55cd8e5a
GN		 5882int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5883{
5884 u64 param, ingpa, outgpa, ret;
5885 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5886 bool fast, longmode;
55cd8e5a
GN		 5887
5888 /*
5889 * hypercall generates UD from non zero cpl and real mode
5890 * per HYPER-V spec
5891 */
3eeb3288 5892 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5893 kvm_queue_exception(vcpu, UD_VECTOR);
5894 return 0;
5895 }
5896
a449c7aa 5897 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5898
5899 if (!longmode) {
ccd46936
GN		 5900 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5901 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5902 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5903 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5904 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5905 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5906 }
5907#ifdef CONFIG_X86_64
5908 else {
5909 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5910 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5911 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5912 }
5913#endif
5914
5915 code = param & 0xffff;
5916 fast = (param >> 16) & 0x1;
5917 rep_cnt = (param >> 32) & 0xfff;
5918 rep_idx = (param >> 48) & 0xfff;
5919
5920 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5921
c25bc163
GN		 5922 switch (code) {
5923 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5924 kvm_vcpu_on_spin(vcpu);
5925 break;
5926 default:
5927 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5928 break;
5929 }
55cd8e5a
GN		 5930
5931 ret = res | (((u64)rep_done & 0xfff) << 32);
5932 if (longmode) {
5933 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5934 } else {
5935 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5936 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5937 }
5938
5939 return 1;
5940}
5941
6aef266c
SV		 5942/*
5943 * kvm_pv_kick_cpu_op: Kick a vcpu.
5944 *
5945 * @apicid - apicid of vcpu to be kicked.
5946 */
5947static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5948{
24d2166b 5949 struct kvm_lapic_irq lapic_irq;
6aef266c 5950
24d2166b
R		 5951 lapic_irq.shorthand = 0;
5952 lapic_irq.dest_mode = 0;
5953 lapic_irq.dest_id = apicid;
6aef266c 5954
24d2166b 5955 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5956 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5957}
5958
8776e519
HB		 5959int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5960{
5961 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5962 int op_64_bit, r = 1;
8776e519 5963
5cb56059
JS		 5964 kvm_x86_ops->skip_emulated_instruction(vcpu);
5965
55cd8e5a
GN		 5966 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5967 return kvm_hv_hypercall(vcpu);
5968
5fdbf976
MT		 5969 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5970 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5971 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5972 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5973 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5974
229456fc 5975 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5976
a449c7aa
NA		 5977 op_64_bit = is_64_bit_mode(vcpu);
5978 if (!op_64_bit) {
8776e519
HB		 5979 nr &= 0xFFFFFFFF;
5980 a0 &= 0xFFFFFFFF;
5981 a1 &= 0xFFFFFFFF;
5982 a2 &= 0xFFFFFFFF;
5983 a3 &= 0xFFFFFFFF;
5984 }
5985
07708c4a
JK		 5986 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5987 ret = -KVM_EPERM;
5988 goto out;
5989 }
5990
8776e519 5991 switch (nr) {
b93463aa
AK		 5992 case KVM_HC_VAPIC_POLL_IRQ:
5993 ret = 0;
5994 break;
6aef266c
SV		 5995 case KVM_HC_KICK_CPU:
5996 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5997 ret = 0;
5998 break;
8776e519
HB		 5999 default:
6000 ret = -KVM_ENOSYS;
6001 break;
6002 }
07708c4a 6003out:
a449c7aa
NA		 6004 if (!op_64_bit)
6005 ret = (u32)ret;
5fdbf976 6006 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6007 ++vcpu->stat.hypercalls;
2f333bcb 6008 return r;
8776e519
HB		 6009}
6010EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6011
b6785def 6012static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6013{
d6aa1000 6014 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6015 char instruction[3];
5fdbf976 6016 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6017
8776e519 6018 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6019
9d74191a 6020 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6021}
6022
b6c7a5dc
HB		 6023/*
6024 * Check if userspace requested an interrupt window, and that the
6025 * interrupt window is open.
6026 *
6027 * No need to exit to userspace if we already have an interrupt queued.
6028 */
851ba692 6029static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6030{
8061823a 6031 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 6032 vcpu->run->request_interrupt_window &&
5df56646 6033 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 6034}
6035
851ba692 6036static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6037{
851ba692
AK		 6038 struct kvm_run *kvm_run = vcpu->run;
6039
91586a3b 6040 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 6041 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6042 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 6043 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 6044 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6045 else
b6c7a5dc 6046 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6047 kvm_arch_interrupt_allowed(vcpu) &&
6048 !kvm_cpu_has_interrupt(vcpu) &&
6049 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6050}
6051
95ba8273
GN		 6052static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6053{
6054 int max_irr, tpr;
6055
6056 if (!kvm_x86_ops->update_cr8_intercept)
6057 return;
6058
88c808fd
AK		 6059 if (!vcpu->arch.apic)
6060 return;
6061
8db3baa2
GN		 6062 if (!vcpu->arch.apic->vapic_addr)
6063 max_irr = kvm_lapic_find_highest_irr(vcpu);
6064 else
6065 max_irr = -1;
95ba8273
GN		 6066
6067 if (max_irr != -1)
6068 max_irr >>= 4;
6069
6070 tpr = kvm_lapic_get_cr8(vcpu);
6071
6072 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6073}
6074
b6b8a145 6075static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6076{
b6b8a145
JK		 6077 int r;
6078
95ba8273 6079 /* try to reinject previous events if any */
b59bb7bd 6080 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6081 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6082 vcpu->arch.exception.has_error_code,
6083 vcpu->arch.exception.error_code);
d6e8c854
NA		 6084
6085 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6086 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6087 X86_EFLAGS_RF);
6088
6bdf0662
NA		 6089 if (vcpu->arch.exception.nr == DB_VECTOR &&
6090 (vcpu->arch.dr7 & DR7_GD)) {
6091 vcpu->arch.dr7 &= ~DR7_GD;
6092 kvm_update_dr7(vcpu);
6093 }
6094
b59bb7bd
GN		 6095 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6096 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6097 vcpu->arch.exception.error_code,
6098 vcpu->arch.exception.reinject);
b6b8a145 6099 return 0;
b59bb7bd
GN		 6100 }
6101
95ba8273
GN		 6102 if (vcpu->arch.nmi_injected) {
6103 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6104 return 0;
95ba8273
GN		 6105 }
6106
6107 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6108 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6109 return 0;
6110 }
6111
6112 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6113 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6114 if (r != 0)
6115 return r;
95ba8273
GN		 6116 }
6117
6118 /* try to inject new event if pending */
6119 if (vcpu->arch.nmi_pending) {
6120 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6121 --vcpu->arch.nmi_pending;
95ba8273
GN		 6122 vcpu->arch.nmi_injected = true;
6123 kvm_x86_ops->set_nmi(vcpu);
6124 }
c7c9c56c 6125 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6126 /*
6127 * Because interrupts can be injected asynchronously, we are
6128 * calling check_nested_events again here to avoid a race condition.
6129 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6130 * proposal and current concerns. Perhaps we should be setting
6131 * KVM_REQ_EVENT only on certain events and not unconditionally?
6132 */
6133 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6134 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6135 if (r != 0)
6136 return r;
6137 }
95ba8273 6138 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6139 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6140 false);
6141 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6142 }
6143 }
b6b8a145 6144 return 0;
95ba8273
GN		 6145}
6146
7460fb4a
AK		 6147static void process_nmi(struct kvm_vcpu *vcpu)
6148{
6149 unsigned limit = 2;
6150
6151 /*
6152 * x86 is limited to one NMI running, and one NMI pending after it.
6153 * If an NMI is already in progress, limit further NMIs to just one.
6154 * Otherwise, allow two (and we'll inject the first one immediately).
6155 */
6156 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6157 limit = 1;
6158
6159 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6160 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6161 kvm_make_request(KVM_REQ_EVENT, vcpu);
6162}
6163
3d81bc7e 6164static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6165{
6166 u64 eoi_exit_bitmap[4];
cf9e65b7 6167 u32 tmr[8];
c7c9c56c 6168
3d81bc7e
YZ		 6169 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6170 return;
c7c9c56c
YZ		 6171
6172 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6173 memset(tmr, 0, 32);
c7c9c56c 6174
cf9e65b7 6175 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6176 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6177 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6178}
6179
a70656b6
RK		 6180static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6181{
6182 ++vcpu->stat.tlb_flush;
6183 kvm_x86_ops->tlb_flush(vcpu);
6184}
6185
4256f43f
TC		 6186void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6187{
c24ae0dc
TC		 6188 struct page *page = NULL;
6189
f439ed27
PB		 6190 if (!irqchip_in_kernel(vcpu->kvm))
6191 return;
6192
4256f43f
TC		 6193 if (!kvm_x86_ops->set_apic_access_page_addr)
6194 return;
6195
c24ae0dc 6196 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6197 if (is_error_page(page))
6198 return;
c24ae0dc
TC		 6199 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6200
6201 /*
6202 * Do not pin apic access page in memory, the MMU notifier
6203 * will call us again if it is migrated or swapped out.
6204 */
6205 put_page(page);
4256f43f
TC		 6206}
6207EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6208
fe71557a
TC		 6209void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6210 unsigned long address)
6211{
c24ae0dc
TC		 6212 /*
6213 * The physical address of apic access page is stored in the VMCS.
6214 * Update it when it becomes invalid.
6215 */
6216 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6217 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6218}
6219
9357d939 6220/*
362c698f 6221 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6222 * exiting to the userspace. Otherwise, the value will be returned to the
6223 * userspace.
6224 */
851ba692 6225static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6226{
6227 int r;
6a8b1d13 6228 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6229 vcpu->run->request_interrupt_window;
730dca42 6230 bool req_immediate_exit = false;
b6c7a5dc 6231
3e007509 6232 if (vcpu->requests) {
a8eeb04a 6233 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6234 kvm_mmu_unload(vcpu);
a8eeb04a 6235 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6236 __kvm_migrate_timers(vcpu);
d828199e
MT		 6237 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6238 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6239 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6240 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6241 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6242 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6243 if (unlikely(r))
6244 goto out;
6245 }
a8eeb04a 6246 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6247 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6248 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6249 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6250 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6251 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6252 r = 0;
6253 goto out;
6254 }
a8eeb04a 6255 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6256 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6257 r = 0;
6258 goto out;
6259 }
a8eeb04a 6260 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6261 vcpu->fpu_active = 0;
6262 kvm_x86_ops->fpu_deactivate(vcpu);
6263 }
af585b92
GN		 6264 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6265 /* Page is swapped out. Do synthetic halt */
6266 vcpu->arch.apf.halted = true;
6267 r = 1;
6268 goto out;
6269 }
c9aaa895
GC		 6270 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6271 record_steal_time(vcpu);
7460fb4a
AK		 6272 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6273 process_nmi(vcpu);
f5132b01
GN		 6274 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6275 kvm_handle_pmu_event(vcpu);
6276 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6277 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6278 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6279 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6280 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6281 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6282 }
b93463aa 6283
b463a6f7 6284 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6285 kvm_apic_accept_events(vcpu);
6286 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6287 r = 1;
6288 goto out;
6289 }
6290
b6b8a145
JK		 6291 if (inject_pending_event(vcpu, req_int_win) != 0)
6292 req_immediate_exit = true;
b463a6f7 6293 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6294 else if (vcpu->arch.nmi_pending)
c9a7953f 6295 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6296 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6297 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6298
6299 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6300 /*
6301 * Update architecture specific hints for APIC
6302 * virtual interrupt delivery.
6303 */
6304 if (kvm_x86_ops->hwapic_irr_update)
6305 kvm_x86_ops->hwapic_irr_update(vcpu,
6306 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6307 update_cr8_intercept(vcpu);
6308 kvm_lapic_sync_to_vapic(vcpu);
6309 }
6310 }
6311
d8368af8
AK		 6312 r = kvm_mmu_reload(vcpu);
6313 if (unlikely(r)) {
d905c069 6314 goto cancel_injection;
d8368af8
AK		 6315 }
6316
b6c7a5dc
HB		 6317 preempt_disable();
6318
6319 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6320 if (vcpu->fpu_active)
6321 kvm_load_guest_fpu(vcpu);
2acf923e 6322 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6323
6b7e2d09
XG		 6324 vcpu->mode = IN_GUEST_MODE;
6325
01b71917
MT		 6326 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6327
6b7e2d09
XG		 6328 /* We should set ->mode before check ->requests,
6329 * see the comment in make_all_cpus_request.
6330 */
01b71917 6331 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6332
d94e1dc9 6333 local_irq_disable();
32f88400 6334
6b7e2d09 6335 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6336 || need_resched() || signal_pending(current)) {
6b7e2d09 6337 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6338 smp_wmb();
6c142801
AK		 6339 local_irq_enable();
6340 preempt_enable();
01b71917 6341 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6342 r = 1;
d905c069 6343 goto cancel_injection;
6c142801
AK		 6344 }
6345
d6185f20
NHE		 6346 if (req_immediate_exit)
6347 smp_send_reschedule(vcpu->cpu);
6348
b6c7a5dc
HB		 6349 kvm_guest_enter();
6350
42dbaa5a 6351 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6352 set_debugreg(0, 7);
6353 set_debugreg(vcpu->arch.eff_db[0], 0);
6354 set_debugreg(vcpu->arch.eff_db[1], 1);
6355 set_debugreg(vcpu->arch.eff_db[2], 2);
6356 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6357 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6358 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6359 }
b6c7a5dc 6360
229456fc 6361 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6362 wait_lapic_expire(vcpu);
851ba692 6363 kvm_x86_ops->run(vcpu);
b6c7a5dc 6364
c77fb5fe
PB		 6365 /*
6366 * Do this here before restoring debug registers on the host. And
6367 * since we do this before handling the vmexit, a DR access vmexit
6368 * can (a) read the correct value of the debug registers, (b) set
6369 * KVM_DEBUGREG_WONT_EXIT again.
6370 */
6371 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6372 int i;
6373
6374 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6375 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6376 for (i = 0; i < KVM_NR_DB_REGS; i++)
6377 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6378 }
6379
24f1e32c
FW		 6380 /*
6381 * If the guest has used debug registers, at least dr7
6382 * will be disabled while returning to the host.
6383 * If we don't have active breakpoints in the host, we don't
6384 * care about the messed up debug address registers. But if
6385 * we have some of them active, restore the old state.
6386 */
59d8eb53 6387 if (hw_breakpoint_active())
24f1e32c 6388 hw_breakpoint_restore();
42dbaa5a 6389
886b470c
MT		 6390 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6391 native_read_tsc());
1d5f066e 6392
6b7e2d09 6393 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6394 smp_wmb();
a547c6db
YZ		 6395
6396 /* Interrupt is enabled by handle_external_intr() */
6397 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6398
6399 ++vcpu->stat.exits;
6400
6401 /*
6402 * We must have an instruction between local_irq_enable() and
6403 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6404 * the interrupt shadow. The stat.exits increment will do nicely.
6405 * But we need to prevent reordering, hence this barrier():
6406 */
6407 barrier();
6408
6409 kvm_guest_exit();
6410
6411 preempt_enable();
6412
f656ce01 6413 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6414
b6c7a5dc
HB		 6415 /*
6416 * Profile KVM exit RIPs:
6417 */
6418 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6419 unsigned long rip = kvm_rip_read(vcpu);
6420 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6421 }
6422
cc578287
ZA		 6423 if (unlikely(vcpu->arch.tsc_always_catchup))
6424 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6425
5cfb1d5a
MT		 6426 if (vcpu->arch.apic_attention)
6427 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6428
851ba692 6429 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6430 return r;
6431
6432cancel_injection:
6433 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6434 if (unlikely(vcpu->arch.apic_attention))
6435 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6436out:
6437 return r;
6438}
b6c7a5dc 6439
362c698f
PB		 6440static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6441{
9c8fd1ba
PB		 6442 if (!kvm_arch_vcpu_runnable(vcpu)) {
6443 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6444 kvm_vcpu_block(vcpu);
6445 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6446 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6447 return 1;
6448 }
362c698f
PB		 6449
6450 kvm_apic_accept_events(vcpu);
6451 switch(vcpu->arch.mp_state) {
6452 case KVM_MP_STATE_HALTED:
6453 vcpu->arch.pv.pv_unhalted = false;
6454 vcpu->arch.mp_state =
6455 KVM_MP_STATE_RUNNABLE;
6456 case KVM_MP_STATE_RUNNABLE:
6457 vcpu->arch.apf.halted = false;
6458 break;
6459 case KVM_MP_STATE_INIT_RECEIVED:
6460 break;
6461 default:
6462 return -EINTR;
6463 break;
6464 }
6465 return 1;
6466}
09cec754 6467
362c698f 6468static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6469{
6470 int r;
f656ce01 6471 struct kvm *kvm = vcpu->kvm;
d7690175 6472
f656ce01 6473 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6474
362c698f 6475 for (;;) {
af585b92
GN		 6476 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6477 !vcpu->arch.apf.halted)
851ba692 6478 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6479 else
6480 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6481 if (r <= 0)
6482 break;
6483
6484 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6485 if (kvm_cpu_has_pending_timer(vcpu))
6486 kvm_inject_pending_timer_irqs(vcpu);
6487
851ba692 6488 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6489 r = -EINTR;
851ba692 6490 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6491 ++vcpu->stat.request_irq_exits;
362c698f 6492 break;
09cec754 6493 }
af585b92
GN		 6494
6495 kvm_check_async_pf_completion(vcpu);
6496
09cec754
GN		 6497 if (signal_pending(current)) {
6498 r = -EINTR;
851ba692 6499 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6500 ++vcpu->stat.signal_exits;
362c698f 6501 break;
09cec754
GN		 6502 }
6503 if (need_resched()) {
f656ce01 6504 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6505 cond_resched();
f656ce01 6506 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6507 }
b6c7a5dc
HB		 6508 }
6509
f656ce01 6510 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6511
6512 return r;
6513}
6514
716d51ab
GN		 6515static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6516{
6517 int r;
6518 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6519 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6520 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6521 if (r != EMULATE_DONE)
6522 return 0;
6523 return 1;
6524}
6525
6526static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6527{
6528 BUG_ON(!vcpu->arch.pio.count);
6529
6530 return complete_emulated_io(vcpu);
6531}
6532
f78146b0
AK		 6533/*
6534 * Implements the following, as a state machine:
6535 *
6536 * read:
6537 * for each fragment
87da7e66
XG		 6538 * for each mmio piece in the fragment
6539 * write gpa, len
6540 * exit
6541 * copy data
f78146b0
AK		 6542 * execute insn
6543 *
6544 * write:
6545 * for each fragment
87da7e66
XG		 6546 * for each mmio piece in the fragment
6547 * write gpa, len
6548 * copy data
6549 * exit
f78146b0 6550 */
716d51ab 6551static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6552{
6553 struct kvm_run *run = vcpu->run;
f78146b0 6554 struct kvm_mmio_fragment *frag;
87da7e66 6555 unsigned len;
5287f194 6556
716d51ab 6557 BUG_ON(!vcpu->mmio_needed);
5287f194 6558
716d51ab 6559 /* Complete previous fragment */
87da7e66
XG		 6560 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6561 len = min(8u, frag->len);
716d51ab 6562 if (!vcpu->mmio_is_write)
87da7e66
XG		 6563 memcpy(frag->data, run->mmio.data, len);
6564
6565 if (frag->len <= 8) {
6566 /* Switch to the next fragment. */
6567 frag++;
6568 vcpu->mmio_cur_fragment++;
6569 } else {
6570 /* Go forward to the next mmio piece. */
6571 frag->data += len;
6572 frag->gpa += len;
6573 frag->len -= len;
6574 }
6575
a08d3b3b 6576 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6577 vcpu->mmio_needed = 0;
0912c977
PB		 6578
6579 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6580 if (vcpu->mmio_is_write)
716d51ab
GN		 6581 return 1;
6582 vcpu->mmio_read_completed = 1;
6583 return complete_emulated_io(vcpu);
6584 }
87da7e66 6585
716d51ab
GN		 6586 run->exit_reason = KVM_EXIT_MMIO;
6587 run->mmio.phys_addr = frag->gpa;
6588 if (vcpu->mmio_is_write)
87da7e66
XG		 6589 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6590 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6591 run->mmio.is_write = vcpu->mmio_is_write;
6592 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6593 return 0;
5287f194
AK		 6594}
6595
716d51ab 6596
b6c7a5dc
HB		 6597int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6598{
c5bedc68 6599 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6600 int r;
6601 sigset_t sigsaved;
6602
c4d72e2d 6603 fpu__activate_curr(fpu);
e5c30142 6604
ac9f6dc0
AK		 6605 if (vcpu->sigset_active)
6606 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6607
a4535290 6608 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6609 kvm_vcpu_block(vcpu);
66450a21 6610 kvm_apic_accept_events(vcpu);
d7690175 6611 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6612 r = -EAGAIN;
6613 goto out;
b6c7a5dc
HB		 6614 }
6615
b6c7a5dc 6616 /* re-sync apic's tpr */
eea1cff9
AP		 6617 if (!irqchip_in_kernel(vcpu->kvm)) {
6618 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6619 r = -EINVAL;
6620 goto out;
6621 }
6622 }
b6c7a5dc 6623
716d51ab
GN		 6624 if (unlikely(vcpu->arch.complete_userspace_io)) {
6625 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6626 vcpu->arch.complete_userspace_io = NULL;
6627 r = cui(vcpu);
6628 if (r <= 0)
6629 goto out;
6630 } else
6631 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6632
362c698f 6633 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6634
6635out:
f1d86e46 6636 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6637 if (vcpu->sigset_active)
6638 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6639
b6c7a5dc
HB		 6640 return r;
6641}
6642
6643int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6644{
7ae441ea
GN		 6645 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6646 /*
6647 * We are here if userspace calls get_regs() in the middle of
6648 * instruction emulation. Registers state needs to be copied
4a969980 6649 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6650 * that usually, but some bad designed PV devices (vmware
6651 * backdoor interface) need this to work
6652 */
dd856efa 6653 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6654 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6655 }
5fdbf976
MT		 6656 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6657 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6658 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6659 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6660 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6661 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6662 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6663 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6664#ifdef CONFIG_X86_64
5fdbf976
MT		 6665 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6666 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6667 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6668 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6669 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6670 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6671 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6672 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6673#endif
6674
5fdbf976 6675 regs->rip = kvm_rip_read(vcpu);
91586a3b 6676 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6677
b6c7a5dc
HB		 6678 return 0;
6679}
6680
6681int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6682{
7ae441ea
GN		 6683 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6684 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6685
5fdbf976
MT		 6686 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6687 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6688 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6689 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6690 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6691 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6692 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6693 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6694#ifdef CONFIG_X86_64
5fdbf976
MT		 6695 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6696 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6697 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6698 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6699 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6700 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6701 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6702 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6703#endif
6704
5fdbf976 6705 kvm_rip_write(vcpu, regs->rip);
91586a3b 6706 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6707
b4f14abd
JK		 6708 vcpu->arch.exception.pending = false;
6709
3842d135
AK		 6710 kvm_make_request(KVM_REQ_EVENT, vcpu);
6711
b6c7a5dc
HB		 6712 return 0;
6713}
6714
b6c7a5dc
HB		 6715void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6716{
6717 struct kvm_segment cs;
6718
3e6e0aab 6719 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6720 *db = cs.db;
6721 *l = cs.l;
6722}
6723EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6724
6725int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6726 struct kvm_sregs *sregs)
6727{
89a27f4d 6728 struct desc_ptr dt;
b6c7a5dc 6729
3e6e0aab
GT		 6730 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6731 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6732 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6733 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6734 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6735 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6736
3e6e0aab
GT		 6737 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6738 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6739
6740 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6741 sregs->idt.limit = dt.size;
6742 sregs->idt.base = dt.address;
b6c7a5dc 6743 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6744 sregs->gdt.limit = dt.size;
6745 sregs->gdt.base = dt.address;
b6c7a5dc 6746
4d4ec087 6747 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6748 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6749 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6750 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6751 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6752 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6753 sregs->apic_base = kvm_get_apic_base(vcpu);
6754
923c61bb 6755 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6756
36752c9b 6757 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6758 set_bit(vcpu->arch.interrupt.nr,
6759 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6760
b6c7a5dc
HB		 6761 return 0;
6762}
6763
62d9f0db
MT		 6764int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6765 struct kvm_mp_state *mp_state)
6766{
66450a21 6767 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6768 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6769 vcpu->arch.pv.pv_unhalted)
6770 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6771 else
6772 mp_state->mp_state = vcpu->arch.mp_state;
6773
62d9f0db
MT		 6774 return 0;
6775}
6776
6777int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6778 struct kvm_mp_state *mp_state)
6779{
66450a21
JK		 6780 if (!kvm_vcpu_has_lapic(vcpu) &&
6781 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6782 return -EINVAL;
6783
6784 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6785 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6786 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6787 } else
6788 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6789 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6790 return 0;
6791}
6792
7f3d35fd
KW		 6793int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6794 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6795{
9d74191a 6796 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6797 int ret;
e01c2426 6798
8ec4722d 6799 init_emulate_ctxt(vcpu);
c697518a 6800
7f3d35fd 6801 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6802 has_error_code, error_code);
c697518a 6803
c697518a 6804 if (ret)
19d04437 6805 return EMULATE_FAIL;
37817f29 6806
9d74191a
TY		 6807 kvm_rip_write(vcpu, ctxt->eip);
6808 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6809 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6810 return EMULATE_DONE;
37817f29
IE		 6811}
6812EXPORT_SYMBOL_GPL(kvm_task_switch);
6813
b6c7a5dc
HB		 6814int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6815 struct kvm_sregs *sregs)
6816{
58cb628d 6817 struct msr_data apic_base_msr;
b6c7a5dc 6818 int mmu_reset_needed = 0;
63f42e02 6819 int pending_vec, max_bits, idx;
89a27f4d 6820 struct desc_ptr dt;
b6c7a5dc 6821
6d1068b3
PM		 6822 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6823 return -EINVAL;
6824
89a27f4d
GN		 6825 dt.size = sregs->idt.limit;
6826 dt.address = sregs->idt.base;
b6c7a5dc 6827 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6828 dt.size = sregs->gdt.limit;
6829 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6830 kvm_x86_ops->set_gdt(vcpu, &dt);
6831
ad312c7c 6832 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6833 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6834 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6835 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6836
2d3ad1f4 6837 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6838
f6801dff 6839 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6840 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6841 apic_base_msr.data = sregs->apic_base;
6842 apic_base_msr.host_initiated = true;
6843 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6844
4d4ec087 6845 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6846 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6847 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6848
fc78f519 6849 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6850 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6851 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6852 kvm_update_cpuid(vcpu);
63f42e02
XG		 6853
6854 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6855 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6856 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6857 mmu_reset_needed = 1;
6858 }
63f42e02 6859 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6860
6861 if (mmu_reset_needed)
6862 kvm_mmu_reset_context(vcpu);
6863
a50abc3b 6864 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6865 pending_vec = find_first_bit(
6866 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6867 if (pending_vec < max_bits) {
66fd3f7f 6868 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6869 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6870 }
6871
3e6e0aab
GT		 6872 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6873 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6874 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6875 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6876 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6877 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6878
3e6e0aab
GT		 6879 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6880 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6881
5f0269f5
ME		 6882 update_cr8_intercept(vcpu);
6883
9c3e4aab 6884 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6885 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6886 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6887 !is_protmode(vcpu))
9c3e4aab
MT		 6888 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6889
3842d135
AK		 6890 kvm_make_request(KVM_REQ_EVENT, vcpu);
6891
b6c7a5dc
HB		 6892 return 0;
6893}
6894
d0bfb940
JK		 6895int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6896 struct kvm_guest_debug *dbg)
b6c7a5dc 6897{
355be0b9 6898 unsigned long rflags;
ae675ef0 6899 int i, r;
b6c7a5dc 6900
4f926bf2
JK		 6901 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6902 r = -EBUSY;
6903 if (vcpu->arch.exception.pending)
2122ff5e 6904 goto out;
4f926bf2
JK		 6905 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6906 kvm_queue_exception(vcpu, DB_VECTOR);
6907 else
6908 kvm_queue_exception(vcpu, BP_VECTOR);
6909 }
6910
91586a3b
JK		 6911 /*
6912 * Read rflags as long as potentially injected trace flags are still
6913 * filtered out.
6914 */
6915 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6916
6917 vcpu->guest_debug = dbg->control;
6918 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6919 vcpu->guest_debug = 0;
6920
6921 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6922 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6923 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6924 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6925 } else {
6926 for (i = 0; i < KVM_NR_DB_REGS; i++)
6927 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6928 }
c8639010 6929 kvm_update_dr7(vcpu);
ae675ef0 6930
f92653ee
JK		 6931 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6932 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6933 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6934
91586a3b
JK		 6935 /*
6936 * Trigger an rflags update that will inject or remove the trace
6937 * flags.
6938 */
6939 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6940
c8639010 6941 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6942
4f926bf2 6943 r = 0;
d0bfb940 6944
2122ff5e 6945out:
b6c7a5dc
HB		 6946
6947 return r;
6948}
6949
8b006791
ZX		 6950/*
6951 * Translate a guest virtual address to a guest physical address.
6952 */
6953int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6954 struct kvm_translation *tr)
6955{
6956 unsigned long vaddr = tr->linear_address;
6957 gpa_t gpa;
f656ce01 6958 int idx;
8b006791 6959
f656ce01 6960 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6961 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6962 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6963 tr->physical_address = gpa;
6964 tr->valid = gpa != UNMAPPED_GVA;
6965 tr->writeable = 1;
6966 tr->usermode = 0;
8b006791
ZX		 6967
6968 return 0;
6969}
6970
d0752060
HB		 6971int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6972{
c47ada30 6973 struct fxregs_state *fxsave =
7366ed77 6974 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 6975
d0752060
HB		 6976 memcpy(fpu->fpr, fxsave->st_space, 128);
6977 fpu->fcw = fxsave->cwd;
6978 fpu->fsw = fxsave->swd;
6979 fpu->ftwx = fxsave->twd;
6980 fpu->last_opcode = fxsave->fop;
6981 fpu->last_ip = fxsave->rip;
6982 fpu->last_dp = fxsave->rdp;
6983 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6984
d0752060
HB		 6985 return 0;
6986}
6987
6988int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6989{
c47ada30 6990 struct fxregs_state *fxsave =
7366ed77 6991 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 6992
d0752060
HB		 6993 memcpy(fxsave->st_space, fpu->fpr, 128);
6994 fxsave->cwd = fpu->fcw;
6995 fxsave->swd = fpu->fsw;
6996 fxsave->twd = fpu->ftwx;
6997 fxsave->fop = fpu->last_opcode;
6998 fxsave->rip = fpu->last_ip;
6999 fxsave->rdp = fpu->last_dp;
7000 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7001
d0752060
HB		 7002 return 0;
7003}
7004
0ee6a517 7005static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7006{
bf935b0b 7007 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7008 if (cpu_has_xsaves)
7366ed77 7009 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7010 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7011
2acf923e
DC		 7012 /*
7013 * Ensure guest xcr0 is valid for loading
7014 */
7015 vcpu->arch.xcr0 = XSTATE_FP;
7016
ad312c7c 7017 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7018}
d0752060
HB		 7019
7020void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7021{
2608d7a1 7022 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7023 return;
7024
2acf923e
DC		 7025 /*
7026 * Restore all possible states in the guest,
7027 * and assume host would use all available bits.
7028 * Guest xcr0 would be loaded later.
7029 */
7030 kvm_put_guest_xcr0(vcpu);
d0752060 7031 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7032 __kernel_fpu_begin();
003e2e8b 7033 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7034 trace_kvm_fpu(1);
d0752060 7035}
d0752060
HB		 7036
7037void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7038{
2acf923e
DC		 7039 kvm_put_guest_xcr0(vcpu);
7040
d0752060
HB		 7041 if (!vcpu->guest_fpu_loaded)
7042 return;
7043
7044 vcpu->guest_fpu_loaded = 0;
4f836347 7045 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7046 __kernel_fpu_end();
f096ed85 7047 ++vcpu->stat.fpu_reload;
c447e76b
LL		 7048 if (!vcpu->arch.eager_fpu)
7049 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7050
0c04851c 7051 trace_kvm_fpu(0);
d0752060 7052}
e9b11c17
ZX		 7053
7054void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7055{
12f9a48f 7056 kvmclock_reset(vcpu);
7f1ea208 7057
f5f48ee1 7058 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7059 kvm_x86_ops->vcpu_free(vcpu);
7060}
7061
7062struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7063 unsigned int id)
7064{
c447e76b
LL		 7065 struct kvm_vcpu *vcpu;
7066
6755bae8
ZA		 7067 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7068 printk_once(KERN_WARNING
7069 "kvm: SMP vm created on host with unstable TSC; "
7070 "guest TSC will not be reliable\n");
c447e76b
LL		 7071
7072 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7073
7074 /*
7075 * Activate fpu unconditionally in case the guest needs eager FPU. It will be
7076 * deactivated soon if it doesn't.
7077 */
7078 kvm_x86_ops->fpu_activate(vcpu);
7079 return vcpu;
26e5215f 7080}
e9b11c17 7081
26e5215f
AK		 7082int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7083{
7084 int r;
e9b11c17 7085
0bed3b56 7086 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7087 r = vcpu_load(vcpu);
7088 if (r)
7089 return r;
57f252f2 7090 kvm_vcpu_reset(vcpu);
8a3c1a33 7091 kvm_mmu_setup(vcpu);
e9b11c17 7092 vcpu_put(vcpu);
e9b11c17 7093
26e5215f 7094 return r;
e9b11c17
ZX		 7095}
7096
31928aa5 7097void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7098{
8fe8ab46 7099 struct msr_data msr;
332967a3 7100 struct kvm *kvm = vcpu->kvm;
42897d86 7101
31928aa5
DD		 7102 if (vcpu_load(vcpu))
7103 return;
8fe8ab46
WA		 7104 msr.data = 0x0;
7105 msr.index = MSR_IA32_TSC;
7106 msr.host_initiated = true;
7107 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7108 vcpu_put(vcpu);
7109
332967a3
AJ		 7110 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7111 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7112}
7113
d40ccc62 7114void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7115{
9fc77441 7116 int r;
344d9588
GN		 7117 vcpu->arch.apf.msr_val = 0;
7118
9fc77441
MT		 7119 r = vcpu_load(vcpu);
7120 BUG_ON(r);
e9b11c17
ZX		 7121 kvm_mmu_unload(vcpu);
7122 vcpu_put(vcpu);
7123
7124 kvm_x86_ops->vcpu_free(vcpu);
7125}
7126
66450a21 7127void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 7128{
7460fb4a
AK		 7129 atomic_set(&vcpu->arch.nmi_queued, 0);
7130 vcpu->arch.nmi_pending = 0;
448fa4a9 7131 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7132 kvm_clear_interrupt_queue(vcpu);
7133 kvm_clear_exception_queue(vcpu);
448fa4a9 7134
42dbaa5a 7135 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7136 kvm_update_dr0123(vcpu);
6f43ed01 7137 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7138 kvm_update_dr6(vcpu);
42dbaa5a 7139 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7140 kvm_update_dr7(vcpu);
42dbaa5a 7141
1119022c
NA		 7142 vcpu->arch.cr2 = 0;
7143
3842d135 7144 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7145 vcpu->arch.apf.msr_val = 0;
c9aaa895 7146 vcpu->arch.st.msr_val = 0;
3842d135 7147
12f9a48f
GC		 7148 kvmclock_reset(vcpu);
7149
af585b92
GN		 7150 kvm_clear_async_pf_completion_queue(vcpu);
7151 kvm_async_pf_hash_reset(vcpu);
7152 vcpu->arch.apf.halted = false;
3842d135 7153
f5132b01
GN		 7154 kvm_pmu_reset(vcpu);
7155
66f7b72e
JS		 7156 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7157 vcpu->arch.regs_avail = ~0;
7158 vcpu->arch.regs_dirty = ~0;
7159
57f252f2 7160 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 7161}
7162
2b4a273b 7163void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7164{
7165 struct kvm_segment cs;
7166
7167 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7168 cs.selector = vector << 8;
7169 cs.base = vector << 12;
7170 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7171 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7172}
7173
13a34e06 7174int kvm_arch_hardware_enable(void)
e9b11c17 7175{
ca84d1a2
ZA		 7176 struct kvm *kvm;
7177 struct kvm_vcpu *vcpu;
7178 int i;
0dd6a6ed
ZA		 7179 int ret;
7180 u64 local_tsc;
7181 u64 max_tsc = 0;
7182 bool stable, backwards_tsc = false;
18863bdd
AK		 7183
7184 kvm_shared_msr_cpu_online();
13a34e06 7185 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7186 if (ret != 0)
7187 return ret;
7188
7189 local_tsc = native_read_tsc();
7190 stable = !check_tsc_unstable();
7191 list_for_each_entry(kvm, &vm_list, vm_list) {
7192 kvm_for_each_vcpu(i, vcpu, kvm) {
7193 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7194 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7195 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7196 backwards_tsc = true;
7197 if (vcpu->arch.last_host_tsc > max_tsc)
7198 max_tsc = vcpu->arch.last_host_tsc;
7199 }
7200 }
7201 }
7202
7203 /*
7204 * Sometimes, even reliable TSCs go backwards. This happens on
7205 * platforms that reset TSC during suspend or hibernate actions, but
7206 * maintain synchronization. We must compensate. Fortunately, we can
7207 * detect that condition here, which happens early in CPU bringup,
7208 * before any KVM threads can be running. Unfortunately, we can't
7209 * bring the TSCs fully up to date with real time, as we aren't yet far
7210 * enough into CPU bringup that we know how much real time has actually
7211 * elapsed; our helper function, get_kernel_ns() will be using boot
7212 * variables that haven't been updated yet.
7213 *
7214 * So we simply find the maximum observed TSC above, then record the
7215 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7216 * the adjustment will be applied. Note that we accumulate
7217 * adjustments, in case multiple suspend cycles happen before some VCPU
7218 * gets a chance to run again. In the event that no KVM threads get a
7219 * chance to run, we will miss the entire elapsed period, as we'll have
7220 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7221 * loose cycle time. This isn't too big a deal, since the loss will be
7222 * uniform across all VCPUs (not to mention the scenario is extremely
7223 * unlikely). It is possible that a second hibernate recovery happens
7224 * much faster than a first, causing the observed TSC here to be
7225 * smaller; this would require additional padding adjustment, which is
7226 * why we set last_host_tsc to the local tsc observed here.
7227 *
7228 * N.B. - this code below runs only on platforms with reliable TSC,
7229 * as that is the only way backwards_tsc is set above. Also note
7230 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7231 * have the same delta_cyc adjustment applied if backwards_tsc
7232 * is detected. Note further, this adjustment is only done once,
7233 * as we reset last_host_tsc on all VCPUs to stop this from being
7234 * called multiple times (one for each physical CPU bringup).
7235 *
4a969980 7236 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7237 * will be compensated by the logic in vcpu_load, which sets the TSC to
7238 * catchup mode. This will catchup all VCPUs to real time, but cannot
7239 * guarantee that they stay in perfect synchronization.
7240 */
7241 if (backwards_tsc) {
7242 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7243 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7244 list_for_each_entry(kvm, &vm_list, vm_list) {
7245 kvm_for_each_vcpu(i, vcpu, kvm) {
7246 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7247 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7248 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7249 }
7250
7251 /*
7252 * We have to disable TSC offset matching.. if you were
7253 * booting a VM while issuing an S4 host suspend....
7254 * you may have some problem. Solving this issue is
7255 * left as an exercise to the reader.
7256 */
7257 kvm->arch.last_tsc_nsec = 0;
7258 kvm->arch.last_tsc_write = 0;
7259 }
7260
7261 }
7262 return 0;
e9b11c17
ZX		 7263}
7264
13a34e06 7265void kvm_arch_hardware_disable(void)
e9b11c17 7266{
13a34e06
RK		 7267 kvm_x86_ops->hardware_disable();
7268 drop_user_return_notifiers();
e9b11c17
ZX		 7269}
7270
7271int kvm_arch_hardware_setup(void)
7272{
9e9c3fe4
NA		 7273 int r;
7274
7275 r = kvm_x86_ops->hardware_setup();
7276 if (r != 0)
7277 return r;
7278
7279 kvm_init_msr_list();
7280 return 0;
e9b11c17
ZX		 7281}
7282
7283void kvm_arch_hardware_unsetup(void)
7284{
7285 kvm_x86_ops->hardware_unsetup();
7286}
7287
7288void kvm_arch_check_processor_compat(void *rtn)
7289{
7290 kvm_x86_ops->check_processor_compatibility(rtn);
7291}
7292
3e515705
AK		 7293bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7294{
7295 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7296}
7297
54e9818f
GN		 7298struct static_key kvm_no_apic_vcpu __read_mostly;
7299
e9b11c17
ZX		 7300int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7301{
7302 struct page *page;
7303 struct kvm *kvm;
7304 int r;
7305
7306 BUG_ON(vcpu->kvm == NULL);
7307 kvm = vcpu->kvm;
7308
6aef266c 7309 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7310 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7311 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7312 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7313 else
a4535290 7314 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7315
7316 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7317 if (!page) {
7318 r = -ENOMEM;
7319 goto fail;
7320 }
ad312c7c 7321 vcpu->arch.pio_data = page_address(page);
e9b11c17 7322
cc578287 7323 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7324
e9b11c17
ZX		 7325 r = kvm_mmu_create(vcpu);
7326 if (r < 0)
7327 goto fail_free_pio_data;
7328
7329 if (irqchip_in_kernel(kvm)) {
7330 r = kvm_create_lapic(vcpu);
7331 if (r < 0)
7332 goto fail_mmu_destroy;
54e9818f
GN		 7333 } else
7334 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7335
890ca9ae
HY		 7336 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7337 GFP_KERNEL);
7338 if (!vcpu->arch.mce_banks) {
7339 r = -ENOMEM;
443c39bc 7340 goto fail_free_lapic;
890ca9ae
HY		 7341 }
7342 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7343
f1797359
WY		 7344 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7345 r = -ENOMEM;
f5f48ee1 7346 goto fail_free_mce_banks;
f1797359 7347 }
f5f48ee1 7348
0ee6a517 7349 fx_init(vcpu);
66f7b72e 7350
ba904635 7351 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7352 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7353
7354 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7355 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7356
5a4f55cd
EK		 7357 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7358
af585b92 7359 kvm_async_pf_hash_reset(vcpu);
f5132b01 7360 kvm_pmu_init(vcpu);
af585b92 7361
e9b11c17 7362 return 0;
0ee6a517 7363
f5f48ee1
SY		 7364fail_free_mce_banks:
7365 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7366fail_free_lapic:
7367 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7368fail_mmu_destroy:
7369 kvm_mmu_destroy(vcpu);
7370fail_free_pio_data:
ad312c7c 7371 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7372fail:
7373 return r;
7374}
7375
7376void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7377{
f656ce01
MT		 7378 int idx;
7379
f5132b01 7380 kvm_pmu_destroy(vcpu);
36cb93fd 7381 kfree(vcpu->arch.mce_banks);
e9b11c17 7382 kvm_free_lapic(vcpu);
f656ce01 7383 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7384 kvm_mmu_destroy(vcpu);
f656ce01 7385 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7386 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7387 if (!irqchip_in_kernel(vcpu->kvm))
7388 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7389}
d19a9cd2 7390
e790d9ef
RK		 7391void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7392{
ae97a3b8 7393 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7394}
7395
e08b9637 7396int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7397{
e08b9637
CO		 7398 if (type)
7399 return -EINVAL;
7400
6ef768fa 7401 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7402 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7403 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7404 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7405 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7406
5550af4d
SY		 7407 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7408 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7409 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7410 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7411 &kvm->arch.irq_sources_bitmap);
5550af4d 7412
038f8c11 7413 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7414 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7415 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7416
7417 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7418
7e44e449 7419 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7420 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7421
d89f5eff 7422 return 0;
d19a9cd2
ZX		 7423}
7424
7425static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7426{
9fc77441
MT		 7427 int r;
7428 r = vcpu_load(vcpu);
7429 BUG_ON(r);
d19a9cd2
ZX		 7430 kvm_mmu_unload(vcpu);
7431 vcpu_put(vcpu);
7432}
7433
7434static void kvm_free_vcpus(struct kvm *kvm)
7435{
7436 unsigned int i;
988a2cae 7437 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7438
7439 /*
7440 * Unpin any mmu pages first.
7441 */
af585b92
GN		 7442 kvm_for_each_vcpu(i, vcpu, kvm) {
7443 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7444 kvm_unload_vcpu_mmu(vcpu);
af585b92 7445 }
988a2cae
GN		 7446 kvm_for_each_vcpu(i, vcpu, kvm)
7447 kvm_arch_vcpu_free(vcpu);
7448
7449 mutex_lock(&kvm->lock);
7450 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7451 kvm->vcpus[i] = NULL;
d19a9cd2 7452
988a2cae
GN		 7453 atomic_set(&kvm->online_vcpus, 0);
7454 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7455}
7456
ad8ba2cd
SY		 7457void kvm_arch_sync_events(struct kvm *kvm)
7458{
332967a3 7459 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7460 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7461 kvm_free_all_assigned_devices(kvm);
aea924f6 7462 kvm_free_pit(kvm);
ad8ba2cd
SY		 7463}
7464
d19a9cd2
ZX		 7465void kvm_arch_destroy_vm(struct kvm *kvm)
7466{
27469d29
AH		 7467 if (current->mm == kvm->mm) {
7468 /*
7469 * Free memory regions allocated on behalf of userspace,
7470 * unless the the memory map has changed due to process exit
7471 * or fd copying.
7472 */
7473 struct kvm_userspace_memory_region mem;
7474 memset(&mem, 0, sizeof(mem));
7475 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7476 kvm_set_memory_region(kvm, &mem);
7477
7478 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7479 kvm_set_memory_region(kvm, &mem);
7480
7481 mem.slot = TSS_PRIVATE_MEMSLOT;
7482 kvm_set_memory_region(kvm, &mem);
7483 }
6eb55818 7484 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7485 kfree(kvm->arch.vpic);
7486 kfree(kvm->arch.vioapic);
d19a9cd2 7487 kvm_free_vcpus(kvm);
1e08ec4a 7488 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7489}
0de10343 7490
5587027c 7491void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7492 struct kvm_memory_slot *dont)
7493{
7494 int i;
7495
d89cc617
TY		 7496 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7497 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7498 kvfree(free->arch.rmap[i]);
d89cc617 7499 free->arch.rmap[i] = NULL;
77d11309 7500 }
d89cc617
TY		 7501 if (i == 0)
7502 continue;
7503
7504 if (!dont || free->arch.lpage_info[i - 1] !=
7505 dont->arch.lpage_info[i - 1]) {
548ef284 7506 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7507 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7508 }
7509 }
7510}
7511
5587027c
AK		 7512int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7513 unsigned long npages)
db3fe4eb
TY		 7514{
7515 int i;
7516
d89cc617 7517 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7518 unsigned long ugfn;
7519 int lpages;
d89cc617 7520 int level = i + 1;
db3fe4eb
TY		 7521
7522 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7523 slot->base_gfn, level) + 1;
7524
d89cc617
TY		 7525 slot->arch.rmap[i] =
7526 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7527 if (!slot->arch.rmap[i])
77d11309 7528 goto out_free;
d89cc617
TY		 7529 if (i == 0)
7530 continue;
77d11309 7531
d89cc617
TY		 7532 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7533 sizeof(*slot->arch.lpage_info[i - 1]));
7534 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7535 goto out_free;
7536
7537 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7538 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7539 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7540 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7541 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7542 /*
7543 * If the gfn and userspace address are not aligned wrt each
7544 * other, or if explicitly asked to, disable large page
7545 * support for this slot
7546 */
7547 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7548 !kvm_largepages_enabled()) {
7549 unsigned long j;
7550
7551 for (j = 0; j < lpages; ++j)
d89cc617 7552 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7553 }
7554 }
7555
7556 return 0;
7557
7558out_free:
d89cc617 7559 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7560 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7561 slot->arch.rmap[i] = NULL;
7562 if (i == 0)
7563 continue;
7564
548ef284 7565 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7566 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7567 }
7568 return -ENOMEM;
7569}
7570
e59dbe09
TY		 7571void kvm_arch_memslots_updated(struct kvm *kvm)
7572{
e6dff7d1
TY		 7573 /*
7574 * memslots->generation has been incremented.
7575 * mmio generation may have reached its maximum value.
7576 */
7577 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7578}
7579
f7784b8e
MT		 7580int kvm_arch_prepare_memory_region(struct kvm *kvm,
7581 struct kvm_memory_slot *memslot,
f7784b8e 7582 struct kvm_userspace_memory_region *mem,
7b6195a9 7583 enum kvm_mr_change change)
0de10343 7584{
7a905b14
TY		 7585 /*
7586 * Only private memory slots need to be mapped here since
7587 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7588 */
7b6195a9 7589 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7590 unsigned long userspace_addr;
604b38ac 7591
7a905b14
TY		 7592 /*
7593 * MAP_SHARED to prevent internal slot pages from being moved
7594 * by fork()/COW.
7595 */
7b6195a9 7596 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7597 PROT_READ | PROT_WRITE,
7598 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7599
7a905b14
TY		 7600 if (IS_ERR((void *)userspace_addr))
7601 return PTR_ERR((void *)userspace_addr);
604b38ac 7602
7a905b14 7603 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7604 }
7605
f7784b8e
MT		 7606 return 0;
7607}
7608
88178fd4
KH		 7609static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7610 struct kvm_memory_slot *new)
7611{
7612 /* Still write protect RO slot */
7613 if (new->flags & KVM_MEM_READONLY) {
7614 kvm_mmu_slot_remove_write_access(kvm, new);
7615 return;
7616 }
7617
7618 /*
7619 * Call kvm_x86_ops dirty logging hooks when they are valid.
7620 *
7621 * kvm_x86_ops->slot_disable_log_dirty is called when:
7622 *
7623 * - KVM_MR_CREATE with dirty logging is disabled
7624 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7625 *
7626 * The reason is, in case of PML, we need to set D-bit for any slots
7627 * with dirty logging disabled in order to eliminate unnecessary GPA
7628 * logging in PML buffer (and potential PML buffer full VMEXT). This
7629 * guarantees leaving PML enabled during guest's lifetime won't have
7630 * any additonal overhead from PML when guest is running with dirty
7631 * logging disabled for memory slots.
7632 *
7633 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7634 * to dirty logging mode.
7635 *
7636 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7637 *
7638 * In case of write protect:
7639 *
7640 * Write protect all pages for dirty logging.
7641 *
7642 * All the sptes including the large sptes which point to this
7643 * slot are set to readonly. We can not create any new large
7644 * spte on this slot until the end of the logging.
7645 *
7646 * See the comments in fast_page_fault().
7647 */
7648 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7649 if (kvm_x86_ops->slot_enable_log_dirty)
7650 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7651 else
7652 kvm_mmu_slot_remove_write_access(kvm, new);
7653 } else {
7654 if (kvm_x86_ops->slot_disable_log_dirty)
7655 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7656 }
7657}
7658
f7784b8e
MT		 7659void kvm_arch_commit_memory_region(struct kvm *kvm,
7660 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7661 const struct kvm_memory_slot *old,
7662 enum kvm_mr_change change)
f7784b8e 7663{
1c91cad4 7664 struct kvm_memory_slot *new;
8482644a 7665 int nr_mmu_pages = 0;
f7784b8e 7666
8482644a 7667 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7668 int ret;
7669
8482644a
TY		 7670 ret = vm_munmap(old->userspace_addr,
7671 old->npages * PAGE_SIZE);
f7784b8e
MT		 7672 if (ret < 0)
7673 printk(KERN_WARNING
7674 "kvm_vm_ioctl_set_memory_region: "
7675 "failed to munmap memory\n");
7676 }
7677
48c0e4e9
XG		 7678 if (!kvm->arch.n_requested_mmu_pages)
7679 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7680
48c0e4e9 7681 if (nr_mmu_pages)
0de10343 7682 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4
KH		 7683
7684 /* It's OK to get 'new' slot here as it has already been installed */
7685 new = id_to_memslot(kvm->memslots, mem->slot);
7686
3ea3b7fa
WL		 7687 /*
7688 * Dirty logging tracks sptes in 4k granularity, meaning that large
7689 * sptes have to be split. If live migration is successful, the guest
7690 * in the source machine will be destroyed and large sptes will be
7691 * created in the destination. However, if the guest continues to run
7692 * in the source machine (for example if live migration fails), small
7693 * sptes will remain around and cause bad performance.
7694 *
7695 * Scan sptes if dirty logging has been stopped, dropping those
7696 * which can be collapsed into a single large-page spte. Later
7697 * page faults will create the large-page sptes.
7698 */
7699 if ((change != KVM_MR_DELETE) &&
7700 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7701 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7702 kvm_mmu_zap_collapsible_sptes(kvm, new);
7703
c972f3b1 7704 /*
88178fd4 7705 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7706 *
88178fd4
KH		 7707 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7708 * been zapped so no dirty logging staff is needed for old slot. For
7709 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7710 * new and it's also covered when dealing with the new slot.
c972f3b1 7711 */
88178fd4
KH		 7712 if (change != KVM_MR_DELETE)
7713 kvm_mmu_slot_apply_flags(kvm, new);
0de10343 7714}
1d737c8a 7715
2df72e9b 7716void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7717{
6ca18b69 7718 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7719}
7720
2df72e9b
MT		 7721void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7722 struct kvm_memory_slot *slot)
7723{
6ca18b69 7724 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7725}
7726
1d737c8a
ZX		 7727int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7728{
b6b8a145
JK		 7729 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7730 kvm_x86_ops->check_nested_events(vcpu, false);
7731
af585b92
GN		 7732 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7733 !vcpu->arch.apf.halted)
7734 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7735 || kvm_apic_has_events(vcpu)
6aef266c 7736 || vcpu->arch.pv.pv_unhalted
7460fb4a 7737 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7738 (kvm_arch_interrupt_allowed(vcpu) &&
7739 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7740}
5736199a 7741
b6d33834 7742int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7743{
b6d33834 7744 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7745}
78646121
GN		 7746
7747int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7748{
7749 return kvm_x86_ops->interrupt_allowed(vcpu);
7750}
229456fc 7751
82b32774 7752unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7753{
82b32774
NA		 7754 if (is_64_bit_mode(vcpu))
7755 return kvm_rip_read(vcpu);
7756 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7757 kvm_rip_read(vcpu));
7758}
7759EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7760
82b32774
NA		 7761bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7762{
7763 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7764}
7765EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7766
94fe45da
JK		 7767unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7768{
7769 unsigned long rflags;
7770
7771 rflags = kvm_x86_ops->get_rflags(vcpu);
7772 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7773 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7774 return rflags;
7775}
7776EXPORT_SYMBOL_GPL(kvm_get_rflags);
7777
6addfc42 7778static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7779{
7780 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7781 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7782 rflags |= X86_EFLAGS_TF;
94fe45da 7783 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7784}
7785
7786void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7787{
7788 __kvm_set_rflags(vcpu, rflags);
3842d135 7789 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7790}
7791EXPORT_SYMBOL_GPL(kvm_set_rflags);
7792
56028d08
GN		 7793void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7794{
7795 int r;
7796
fb67e14f 7797 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7798 work->wakeup_all)
56028d08
GN		 7799 return;
7800
7801 r = kvm_mmu_reload(vcpu);
7802 if (unlikely(r))
7803 return;
7804
fb67e14f
XG		 7805 if (!vcpu->arch.mmu.direct_map &&
7806 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7807 return;
7808
56028d08
GN		 7809 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7810}
7811
af585b92
GN		 7812static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7813{
7814 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7815}
7816
7817static inline u32 kvm_async_pf_next_probe(u32 key)
7818{
7819 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7820}
7821
7822static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7823{
7824 u32 key = kvm_async_pf_hash_fn(gfn);
7825
7826 while (vcpu->arch.apf.gfns[key] != ~0)
7827 key = kvm_async_pf_next_probe(key);
7828
7829 vcpu->arch.apf.gfns[key] = gfn;
7830}
7831
7832static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7833{
7834 int i;
7835 u32 key = kvm_async_pf_hash_fn(gfn);
7836
7837 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7838 (vcpu->arch.apf.gfns[key] != gfn &&
7839 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7840 key = kvm_async_pf_next_probe(key);
7841
7842 return key;
7843}
7844
7845bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7846{
7847 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7848}
7849
7850static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7851{
7852 u32 i, j, k;
7853
7854 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7855 while (true) {
7856 vcpu->arch.apf.gfns[i] = ~0;
7857 do {
7858 j = kvm_async_pf_next_probe(j);
7859 if (vcpu->arch.apf.gfns[j] == ~0)
7860 return;
7861 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7862 /*
7863 * k lies cyclically in ]i,j]
7864 * | i.k.j |
7865 * |....j i.k.| or |.k..j i...|
7866 */
7867 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7868 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7869 i = j;
7870 }
7871}
7872
7c90705b
GN		 7873static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7874{
7875
7876 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7877 sizeof(val));
7878}
7879
af585b92
GN		 7880void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7881 struct kvm_async_pf *work)
7882{
6389ee94
AK		 7883 struct x86_exception fault;
7884
7c90705b 7885 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7886 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7887
7888 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7889 (vcpu->arch.apf.send_user_only &&
7890 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7891 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7892 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7893 fault.vector = PF_VECTOR;
7894 fault.error_code_valid = true;
7895 fault.error_code = 0;
7896 fault.nested_page_fault = false;
7897 fault.address = work->arch.token;
7898 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7899 }
af585b92
GN		 7900}
7901
7902void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7903 struct kvm_async_pf *work)
7904{
6389ee94
AK		 7905 struct x86_exception fault;
7906
7c90705b 7907 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7908 if (work->wakeup_all)
7c90705b
GN		 7909 work->arch.token = ~0; /* broadcast wakeup */
7910 else
7911 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7912
7913 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7914 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7915 fault.vector = PF_VECTOR;
7916 fault.error_code_valid = true;
7917 fault.error_code = 0;
7918 fault.nested_page_fault = false;
7919 fault.address = work->arch.token;
7920 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7921 }
e6d53e3b 7922 vcpu->arch.apf.halted = false;
a4fa1635 7923 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7924}
7925
7926bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7927{
7928 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7929 return true;
7930 else
7931 return !kvm_event_needs_reinjection(vcpu) &&
7932 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7933}
7934
e0f0bbc5
AW		 7935void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7936{
7937 atomic_inc(&kvm->arch.noncoherent_dma_count);
7938}
7939EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7940
7941void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7942{
7943 atomic_dec(&kvm->arch.noncoherent_dma_count);
7944}
7945EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7946
7947bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7948{
7949 return atomic_read(&kvm->arch.noncoherent_dma_count);
7950}
7951EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7952
229456fc
MT		 7953EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7954EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7955EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7956EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7957EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7958EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7959EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7960EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7961EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7962EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7963EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7964EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7965EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 7966EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 7967EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
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