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Commit | Line | Data |
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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
00b27a3e | 29 | #include "cpuid.h" |
c9eab58f | 30 | #include "assigned-dev.h" |
474a5bb9 | 31 | #include "pmu.h" |
e83d5887 | 32 | #include "hyperv.h" |
313a3dc7 | 33 | |
18068523 | 34 | #include <linux/clocksource.h> |
4d5c5d0f | 35 | #include <linux/interrupt.h> |
313a3dc7 CO |
36 | #include <linux/kvm.h> |
37 | #include <linux/fs.h> | |
38 | #include <linux/vmalloc.h> | |
5fb76f9b | 39 | #include <linux/module.h> |
0de10343 | 40 | #include <linux/mman.h> |
2bacc55c | 41 | #include <linux/highmem.h> |
19de40a8 | 42 | #include <linux/iommu.h> |
62c476c7 | 43 | #include <linux/intel-iommu.h> |
c8076604 | 44 | #include <linux/cpufreq.h> |
18863bdd | 45 | #include <linux/user-return-notifier.h> |
a983fb23 | 46 | #include <linux/srcu.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
ff9d07a0 | 48 | #include <linux/perf_event.h> |
7bee342a | 49 | #include <linux/uaccess.h> |
af585b92 | 50 | #include <linux/hash.h> |
a1b60c1c | 51 | #include <linux/pci.h> |
16e8d74d MT |
52 | #include <linux/timekeeper_internal.h> |
53 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
54 | #include <linux/kvm_irqfd.h> |
55 | #include <linux/irqbypass.h> | |
aec51dc4 | 56 | #include <trace/events/kvm.h> |
2ed152af | 57 | |
229456fc MT |
58 | #define CREATE_TRACE_POINTS |
59 | #include "trace.h" | |
043405e1 | 60 | |
24f1e32c | 61 | #include <asm/debugreg.h> |
d825ed0a | 62 | #include <asm/msr.h> |
a5f61300 | 63 | #include <asm/desc.h> |
890ca9ae | 64 | #include <asm/mce.h> |
f89e32e0 | 65 | #include <linux/kernel_stat.h> |
78f7f1e5 | 66 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 67 | #include <asm/pvclock.h> |
217fc9cf | 68 | #include <asm/div64.h> |
efc64404 | 69 | #include <asm/irq_remapping.h> |
043405e1 | 70 | |
313a3dc7 | 71 | #define MAX_IO_MSRS 256 |
890ca9ae | 72 | #define KVM_MAX_MCE_BANKS 32 |
5854dbca | 73 | #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) |
890ca9ae | 74 | |
0f65dd70 AK |
75 | #define emul_to_vcpu(ctxt) \ |
76 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
77 | ||
50a37eb4 JR |
78 | /* EFER defaults: |
79 | * - enable syscall per default because its emulated by KVM | |
80 | * - enable LME and LMA per default on 64 bit KVM | |
81 | */ | |
82 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
83 | static |
84 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 85 | #else |
1260edbe | 86 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 87 | #endif |
313a3dc7 | 88 | |
ba1389b7 AK |
89 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
90 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 91 | |
cb142eb7 | 92 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 93 | static void process_nmi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 94 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 95 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
674eea0f | 96 | |
893590c7 | 97 | struct kvm_x86_ops *kvm_x86_ops __read_mostly; |
5fdbf976 | 98 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 99 | |
893590c7 | 100 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 101 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 102 | |
9ed96e87 MT |
103 | unsigned int min_timer_period_us = 500; |
104 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); | |
105 | ||
630994b3 MT |
106 | static bool __read_mostly kvmclock_periodic_sync = true; |
107 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
108 | ||
893590c7 | 109 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 110 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 111 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 112 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
113 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
114 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
115 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
116 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
117 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
118 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
92a1f12d | 119 | |
cc578287 | 120 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 121 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
122 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
123 | ||
d0659d94 | 124 | /* lapic timer advance (tscdeadline mode only) in nanoseconds */ |
893590c7 | 125 | unsigned int __read_mostly lapic_timer_advance_ns = 0; |
d0659d94 MT |
126 | module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); |
127 | ||
52004014 FW |
128 | static bool __read_mostly vector_hashing = true; |
129 | module_param(vector_hashing, bool, S_IRUGO); | |
130 | ||
893590c7 | 131 | static bool __read_mostly backwards_tsc_observed = false; |
16a96021 | 132 | |
18863bdd AK |
133 | #define KVM_NR_SHARED_MSRS 16 |
134 | ||
135 | struct kvm_shared_msrs_global { | |
136 | int nr; | |
2bf78fa7 | 137 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
138 | }; |
139 | ||
140 | struct kvm_shared_msrs { | |
141 | struct user_return_notifier urn; | |
142 | bool registered; | |
2bf78fa7 SY |
143 | struct kvm_shared_msr_values { |
144 | u64 host; | |
145 | u64 curr; | |
146 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
147 | }; |
148 | ||
149 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
013f6a5d | 150 | static struct kvm_shared_msrs __percpu *shared_msrs; |
18863bdd | 151 | |
417bc304 | 152 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
153 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
154 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
155 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
156 | { "invlpg", VCPU_STAT(invlpg) }, | |
157 | { "exits", VCPU_STAT(exits) }, | |
158 | { "io_exits", VCPU_STAT(io_exits) }, | |
159 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
160 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
161 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 162 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 | 163 | { "halt_exits", VCPU_STAT(halt_exits) }, |
f7819512 | 164 | { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, |
62bea5bf | 165 | { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, |
3491caf2 | 166 | { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, |
ba1389b7 | 167 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
f11c3a8d | 168 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
169 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
170 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
171 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
172 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
173 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
174 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
175 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 176 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 177 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
178 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
179 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
180 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
181 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
182 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
183 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 184 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 185 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 186 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 187 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
188 | { NULL } |
189 | }; | |
190 | ||
2acf923e DC |
191 | u64 __read_mostly host_xcr0; |
192 | ||
b6785def | 193 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 194 | |
af585b92 GN |
195 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
196 | { | |
197 | int i; | |
198 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
199 | vcpu->arch.apf.gfns[i] = ~0; | |
200 | } | |
201 | ||
18863bdd AK |
202 | static void kvm_on_user_return(struct user_return_notifier *urn) |
203 | { | |
204 | unsigned slot; | |
18863bdd AK |
205 | struct kvm_shared_msrs *locals |
206 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 207 | struct kvm_shared_msr_values *values; |
18863bdd AK |
208 | |
209 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
210 | values = &locals->values[slot]; |
211 | if (values->host != values->curr) { | |
212 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
213 | values->curr = values->host; | |
18863bdd AK |
214 | } |
215 | } | |
216 | locals->registered = false; | |
217 | user_return_notifier_unregister(urn); | |
218 | } | |
219 | ||
2bf78fa7 | 220 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 221 | { |
18863bdd | 222 | u64 value; |
013f6a5d MT |
223 | unsigned int cpu = smp_processor_id(); |
224 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
18863bdd | 225 | |
2bf78fa7 SY |
226 | /* only read, and nobody should modify it at this time, |
227 | * so don't need lock */ | |
228 | if (slot >= shared_msrs_global.nr) { | |
229 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
230 | return; | |
231 | } | |
232 | rdmsrl_safe(msr, &value); | |
233 | smsr->values[slot].host = value; | |
234 | smsr->values[slot].curr = value; | |
235 | } | |
236 | ||
237 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
238 | { | |
0123be42 | 239 | BUG_ON(slot >= KVM_NR_SHARED_MSRS); |
c847fe88 | 240 | shared_msrs_global.msrs[slot] = msr; |
18863bdd AK |
241 | if (slot >= shared_msrs_global.nr) |
242 | shared_msrs_global.nr = slot + 1; | |
18863bdd AK |
243 | } |
244 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
245 | ||
246 | static void kvm_shared_msr_cpu_online(void) | |
247 | { | |
248 | unsigned i; | |
18863bdd AK |
249 | |
250 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 251 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
252 | } |
253 | ||
8b3c3104 | 254 | int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 255 | { |
013f6a5d MT |
256 | unsigned int cpu = smp_processor_id(); |
257 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
8b3c3104 | 258 | int err; |
18863bdd | 259 | |
2bf78fa7 | 260 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
8b3c3104 | 261 | return 0; |
2bf78fa7 | 262 | smsr->values[slot].curr = value; |
8b3c3104 AH |
263 | err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); |
264 | if (err) | |
265 | return 1; | |
266 | ||
18863bdd AK |
267 | if (!smsr->registered) { |
268 | smsr->urn.on_user_return = kvm_on_user_return; | |
269 | user_return_notifier_register(&smsr->urn); | |
270 | smsr->registered = true; | |
271 | } | |
8b3c3104 | 272 | return 0; |
18863bdd AK |
273 | } |
274 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
275 | ||
13a34e06 | 276 | static void drop_user_return_notifiers(void) |
3548bab5 | 277 | { |
013f6a5d MT |
278 | unsigned int cpu = smp_processor_id(); |
279 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
3548bab5 AK |
280 | |
281 | if (smsr->registered) | |
282 | kvm_on_user_return(&smsr->urn); | |
283 | } | |
284 | ||
6866b83e CO |
285 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
286 | { | |
8a5a87d9 | 287 | return vcpu->arch.apic_base; |
6866b83e CO |
288 | } |
289 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
290 | ||
58cb628d JK |
291 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
292 | { | |
293 | u64 old_state = vcpu->arch.apic_base & | |
294 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
295 | u64 new_state = msr_info->data & | |
296 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
297 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | | |
298 | 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); | |
299 | ||
300 | if (!msr_info->host_initiated && | |
301 | ((msr_info->data & reserved_bits) != 0 || | |
302 | new_state == X2APIC_ENABLE || | |
303 | (new_state == MSR_IA32_APICBASE_ENABLE && | |
304 | old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || | |
305 | (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && | |
306 | old_state == 0))) | |
307 | return 1; | |
308 | ||
309 | kvm_lapic_set_base(vcpu, msr_info->data); | |
310 | return 0; | |
6866b83e CO |
311 | } |
312 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
313 | ||
2605fc21 | 314 | asmlinkage __visible void kvm_spurious_fault(void) |
e3ba45b8 GL |
315 | { |
316 | /* Fault while not rebooting. We want the trace. */ | |
317 | BUG(); | |
318 | } | |
319 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
320 | ||
3fd28fce ED |
321 | #define EXCPT_BENIGN 0 |
322 | #define EXCPT_CONTRIBUTORY 1 | |
323 | #define EXCPT_PF 2 | |
324 | ||
325 | static int exception_class(int vector) | |
326 | { | |
327 | switch (vector) { | |
328 | case PF_VECTOR: | |
329 | return EXCPT_PF; | |
330 | case DE_VECTOR: | |
331 | case TS_VECTOR: | |
332 | case NP_VECTOR: | |
333 | case SS_VECTOR: | |
334 | case GP_VECTOR: | |
335 | return EXCPT_CONTRIBUTORY; | |
336 | default: | |
337 | break; | |
338 | } | |
339 | return EXCPT_BENIGN; | |
340 | } | |
341 | ||
d6e8c854 NA |
342 | #define EXCPT_FAULT 0 |
343 | #define EXCPT_TRAP 1 | |
344 | #define EXCPT_ABORT 2 | |
345 | #define EXCPT_INTERRUPT 3 | |
346 | ||
347 | static int exception_type(int vector) | |
348 | { | |
349 | unsigned int mask; | |
350 | ||
351 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
352 | return EXCPT_INTERRUPT; | |
353 | ||
354 | mask = 1 << vector; | |
355 | ||
356 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
357 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
358 | return EXCPT_TRAP; | |
359 | ||
360 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
361 | return EXCPT_ABORT; | |
362 | ||
363 | /* Reserved exceptions will result in fault */ | |
364 | return EXCPT_FAULT; | |
365 | } | |
366 | ||
3fd28fce | 367 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 JR |
368 | unsigned nr, bool has_error, u32 error_code, |
369 | bool reinject) | |
3fd28fce ED |
370 | { |
371 | u32 prev_nr; | |
372 | int class1, class2; | |
373 | ||
3842d135 AK |
374 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
375 | ||
3fd28fce ED |
376 | if (!vcpu->arch.exception.pending) { |
377 | queue: | |
3ffb2468 NA |
378 | if (has_error && !is_protmode(vcpu)) |
379 | has_error = false; | |
3fd28fce ED |
380 | vcpu->arch.exception.pending = true; |
381 | vcpu->arch.exception.has_error_code = has_error; | |
382 | vcpu->arch.exception.nr = nr; | |
383 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 384 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
385 | return; |
386 | } | |
387 | ||
388 | /* to check exception */ | |
389 | prev_nr = vcpu->arch.exception.nr; | |
390 | if (prev_nr == DF_VECTOR) { | |
391 | /* triple fault -> shutdown */ | |
a8eeb04a | 392 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
393 | return; |
394 | } | |
395 | class1 = exception_class(prev_nr); | |
396 | class2 = exception_class(nr); | |
397 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
398 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
399 | /* generate double fault per SDM Table 5-5 */ | |
400 | vcpu->arch.exception.pending = true; | |
401 | vcpu->arch.exception.has_error_code = true; | |
402 | vcpu->arch.exception.nr = DF_VECTOR; | |
403 | vcpu->arch.exception.error_code = 0; | |
404 | } else | |
405 | /* replace previous exception with a new one in a hope | |
406 | that instruction re-execution will regenerate lost | |
407 | exception */ | |
408 | goto queue; | |
409 | } | |
410 | ||
298101da AK |
411 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
412 | { | |
ce7ddec4 | 413 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
414 | } |
415 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
416 | ||
ce7ddec4 JR |
417 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
418 | { | |
419 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
420 | } | |
421 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
422 | ||
db8fcefa | 423 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 424 | { |
db8fcefa AP |
425 | if (err) |
426 | kvm_inject_gp(vcpu, 0); | |
427 | else | |
428 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
429 | } | |
430 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 431 | |
6389ee94 | 432 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
433 | { |
434 | ++vcpu->stat.pf_guest; | |
6389ee94 AK |
435 | vcpu->arch.cr2 = fault->address; |
436 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); | |
c3c91fee | 437 | } |
27d6c865 | 438 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 439 | |
ef54bcfe | 440 | static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 441 | { |
6389ee94 AK |
442 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
443 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 444 | else |
6389ee94 | 445 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
ef54bcfe PB |
446 | |
447 | return fault->nested_page_fault; | |
d4f8cf66 JR |
448 | } |
449 | ||
3419ffc8 SY |
450 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
451 | { | |
7460fb4a AK |
452 | atomic_inc(&vcpu->arch.nmi_queued); |
453 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
454 | } |
455 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
456 | ||
298101da AK |
457 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
458 | { | |
ce7ddec4 | 459 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
460 | } |
461 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
462 | ||
ce7ddec4 JR |
463 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
464 | { | |
465 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
466 | } | |
467 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
468 | ||
0a79b009 AK |
469 | /* |
470 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
471 | * a #GP and return false. | |
472 | */ | |
473 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 474 | { |
0a79b009 AK |
475 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
476 | return true; | |
477 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
478 | return false; | |
298101da | 479 | } |
0a79b009 | 480 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 481 | |
16f8a6f9 NA |
482 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
483 | { | |
484 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
485 | return true; | |
486 | ||
487 | kvm_queue_exception(vcpu, UD_VECTOR); | |
488 | return false; | |
489 | } | |
490 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
491 | ||
ec92fe44 JR |
492 | /* |
493 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 494 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
495 | * can read from guest physical or from the guest's guest physical memory. |
496 | */ | |
497 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
498 | gfn_t ngfn, void *data, int offset, int len, | |
499 | u32 access) | |
500 | { | |
54987b7a | 501 | struct x86_exception exception; |
ec92fe44 JR |
502 | gfn_t real_gfn; |
503 | gpa_t ngpa; | |
504 | ||
505 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 506 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
507 | if (real_gfn == UNMAPPED_GVA) |
508 | return -EFAULT; | |
509 | ||
510 | real_gfn = gpa_to_gfn(real_gfn); | |
511 | ||
54bf36aa | 512 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
513 | } |
514 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
515 | ||
69b0049a | 516 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
517 | void *data, int offset, int len, u32 access) |
518 | { | |
519 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
520 | data, offset, len, access); | |
521 | } | |
522 | ||
a03490ed CO |
523 | /* |
524 | * Load the pae pdptrs. Return true is they are all valid. | |
525 | */ | |
ff03a073 | 526 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
527 | { |
528 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
529 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
530 | int i; | |
531 | int ret; | |
ff03a073 | 532 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 533 | |
ff03a073 JR |
534 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
535 | offset * sizeof(u64), sizeof(pdpte), | |
536 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
537 | if (ret < 0) { |
538 | ret = 0; | |
539 | goto out; | |
540 | } | |
541 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 542 | if (is_present_gpte(pdpte[i]) && |
a0a64f50 XG |
543 | (pdpte[i] & |
544 | vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { | |
a03490ed CO |
545 | ret = 0; |
546 | goto out; | |
547 | } | |
548 | } | |
549 | ret = 1; | |
550 | ||
ff03a073 | 551 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
552 | __set_bit(VCPU_EXREG_PDPTR, |
553 | (unsigned long *)&vcpu->arch.regs_avail); | |
554 | __set_bit(VCPU_EXREG_PDPTR, | |
555 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 556 | out: |
a03490ed CO |
557 | |
558 | return ret; | |
559 | } | |
cc4b6871 | 560 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 561 | |
d835dfec AK |
562 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
563 | { | |
ff03a073 | 564 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 565 | bool changed = true; |
3d06b8bf JR |
566 | int offset; |
567 | gfn_t gfn; | |
d835dfec AK |
568 | int r; |
569 | ||
570 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
571 | return false; | |
572 | ||
6de4f3ad AK |
573 | if (!test_bit(VCPU_EXREG_PDPTR, |
574 | (unsigned long *)&vcpu->arch.regs_avail)) | |
575 | return true; | |
576 | ||
9f8fe504 AK |
577 | gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; |
578 | offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
579 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
580 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
581 | if (r < 0) |
582 | goto out; | |
ff03a073 | 583 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 584 | out: |
d835dfec AK |
585 | |
586 | return changed; | |
587 | } | |
588 | ||
49a9b07e | 589 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 590 | { |
aad82703 | 591 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d81135a5 | 592 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; |
aad82703 | 593 | |
f9a48e6a AK |
594 | cr0 |= X86_CR0_ET; |
595 | ||
ab344828 | 596 | #ifdef CONFIG_X86_64 |
0f12244f GN |
597 | if (cr0 & 0xffffffff00000000UL) |
598 | return 1; | |
ab344828 GN |
599 | #endif |
600 | ||
601 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 602 | |
0f12244f GN |
603 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
604 | return 1; | |
a03490ed | 605 | |
0f12244f GN |
606 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
607 | return 1; | |
a03490ed CO |
608 | |
609 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
610 | #ifdef CONFIG_X86_64 | |
f6801dff | 611 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
612 | int cs_db, cs_l; |
613 | ||
0f12244f GN |
614 | if (!is_pae(vcpu)) |
615 | return 1; | |
a03490ed | 616 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
617 | if (cs_l) |
618 | return 1; | |
a03490ed CO |
619 | } else |
620 | #endif | |
ff03a073 | 621 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 622 | kvm_read_cr3(vcpu))) |
0f12244f | 623 | return 1; |
a03490ed CO |
624 | } |
625 | ||
ad756a16 MJ |
626 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
627 | return 1; | |
628 | ||
a03490ed | 629 | kvm_x86_ops->set_cr0(vcpu, cr0); |
a03490ed | 630 | |
d170c419 | 631 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 632 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
633 | kvm_async_pf_hash_reset(vcpu); |
634 | } | |
e5f3f027 | 635 | |
aad82703 SY |
636 | if ((cr0 ^ old_cr0) & update_bits) |
637 | kvm_mmu_reset_context(vcpu); | |
b18d5431 | 638 | |
879ae188 LE |
639 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && |
640 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
641 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
b18d5431 XG |
642 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); |
643 | ||
0f12244f GN |
644 | return 0; |
645 | } | |
2d3ad1f4 | 646 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 647 | |
2d3ad1f4 | 648 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 649 | { |
49a9b07e | 650 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 651 | } |
2d3ad1f4 | 652 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 653 | |
42bdf991 MT |
654 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
655 | { | |
656 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
657 | !vcpu->guest_xcr0_loaded) { | |
658 | /* kvm_set_xcr() also depends on this */ | |
659 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
660 | vcpu->guest_xcr0_loaded = 1; | |
661 | } | |
662 | } | |
663 | ||
664 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
665 | { | |
666 | if (vcpu->guest_xcr0_loaded) { | |
667 | if (vcpu->arch.xcr0 != host_xcr0) | |
668 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
669 | vcpu->guest_xcr0_loaded = 0; | |
670 | } | |
671 | } | |
672 | ||
69b0049a | 673 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 674 | { |
56c103ec LJ |
675 | u64 xcr0 = xcr; |
676 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 677 | u64 valid_bits; |
2acf923e DC |
678 | |
679 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
680 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
681 | return 1; | |
d91cab78 | 682 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 683 | return 1; |
d91cab78 | 684 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 685 | return 1; |
46c34cb0 PB |
686 | |
687 | /* | |
688 | * Do not allow the guest to set bits that we do not support | |
689 | * saving. However, xcr0 bit 0 is always set, even if the | |
690 | * emulated CPU does not support XSAVE (see fx_init). | |
691 | */ | |
d91cab78 | 692 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 693 | if (xcr0 & ~valid_bits) |
2acf923e | 694 | return 1; |
46c34cb0 | 695 | |
d91cab78 DH |
696 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
697 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
698 | return 1; |
699 | ||
d91cab78 DH |
700 | if (xcr0 & XFEATURE_MASK_AVX512) { |
701 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 702 | return 1; |
d91cab78 | 703 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
704 | return 1; |
705 | } | |
2acf923e | 706 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 707 | |
d91cab78 | 708 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
56c103ec | 709 | kvm_update_cpuid(vcpu); |
2acf923e DC |
710 | return 0; |
711 | } | |
712 | ||
713 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
714 | { | |
764bcbc5 Z |
715 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || |
716 | __kvm_set_xcr(vcpu, index, xcr)) { | |
2acf923e DC |
717 | kvm_inject_gp(vcpu, 0); |
718 | return 1; | |
719 | } | |
720 | return 0; | |
721 | } | |
722 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
723 | ||
a83b29c6 | 724 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 725 | { |
fc78f519 | 726 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
0be0226f | 727 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | |
b9baba86 | 728 | X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; |
0be0226f | 729 | |
0f12244f GN |
730 | if (cr4 & CR4_RESERVED_BITS) |
731 | return 1; | |
a03490ed | 732 | |
2acf923e DC |
733 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
734 | return 1; | |
735 | ||
c68b734f YW |
736 | if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) |
737 | return 1; | |
738 | ||
97ec8c06 FW |
739 | if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) |
740 | return 1; | |
741 | ||
afcbf13f | 742 | if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) |
74dc2b4f YW |
743 | return 1; |
744 | ||
b9baba86 HH |
745 | if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE)) |
746 | return 1; | |
747 | ||
a03490ed | 748 | if (is_long_mode(vcpu)) { |
0f12244f GN |
749 | if (!(cr4 & X86_CR4_PAE)) |
750 | return 1; | |
a2edf57f AK |
751 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
752 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
753 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
754 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
755 | return 1; |
756 | ||
ad756a16 MJ |
757 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
758 | if (!guest_cpuid_has_pcid(vcpu)) | |
759 | return 1; | |
760 | ||
761 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
762 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
763 | return 1; | |
764 | } | |
765 | ||
5e1746d6 | 766 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) |
0f12244f | 767 | return 1; |
a03490ed | 768 | |
ad756a16 MJ |
769 | if (((cr4 ^ old_cr4) & pdptr_bits) || |
770 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
aad82703 | 771 | kvm_mmu_reset_context(vcpu); |
0f12244f | 772 | |
b9baba86 | 773 | if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) |
00b27a3e | 774 | kvm_update_cpuid(vcpu); |
2acf923e | 775 | |
0f12244f GN |
776 | return 0; |
777 | } | |
2d3ad1f4 | 778 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 779 | |
2390218b | 780 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 781 | { |
ac146235 | 782 | #ifdef CONFIG_X86_64 |
9d88fca7 | 783 | cr3 &= ~CR3_PCID_INVD; |
ac146235 | 784 | #endif |
9d88fca7 | 785 | |
9f8fe504 | 786 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
0ba73cda | 787 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 788 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
0f12244f | 789 | return 0; |
d835dfec AK |
790 | } |
791 | ||
a03490ed | 792 | if (is_long_mode(vcpu)) { |
d9f89b88 JK |
793 | if (cr3 & CR3_L_MODE_RESERVED_BITS) |
794 | return 1; | |
795 | } else if (is_pae(vcpu) && is_paging(vcpu) && | |
796 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 797 | return 1; |
a03490ed | 798 | |
0f12244f | 799 | vcpu->arch.cr3 = cr3; |
aff48baa | 800 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
d8d173da | 801 | kvm_mmu_new_cr3(vcpu); |
0f12244f GN |
802 | return 0; |
803 | } | |
2d3ad1f4 | 804 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 805 | |
eea1cff9 | 806 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 807 | { |
0f12244f GN |
808 | if (cr8 & CR8_RESERVED_BITS) |
809 | return 1; | |
35754c98 | 810 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
811 | kvm_lapic_set_tpr(vcpu, cr8); |
812 | else | |
ad312c7c | 813 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
814 | return 0; |
815 | } | |
2d3ad1f4 | 816 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 817 | |
2d3ad1f4 | 818 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 819 | { |
35754c98 | 820 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
821 | return kvm_lapic_get_cr8(vcpu); |
822 | else | |
ad312c7c | 823 | return vcpu->arch.cr8; |
a03490ed | 824 | } |
2d3ad1f4 | 825 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 826 | |
ae561ede NA |
827 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
828 | { | |
829 | int i; | |
830 | ||
831 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
832 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
833 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
834 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
835 | } | |
836 | } | |
837 | ||
73aaf249 JK |
838 | static void kvm_update_dr6(struct kvm_vcpu *vcpu) |
839 | { | |
840 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
841 | kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); | |
842 | } | |
843 | ||
c8639010 JK |
844 | static void kvm_update_dr7(struct kvm_vcpu *vcpu) |
845 | { | |
846 | unsigned long dr7; | |
847 | ||
848 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
849 | dr7 = vcpu->arch.guest_debug_dr7; | |
850 | else | |
851 | dr7 = vcpu->arch.dr7; | |
852 | kvm_x86_ops->set_dr7(vcpu, dr7); | |
360b948d PB |
853 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
854 | if (dr7 & DR7_BP_EN_MASK) | |
855 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 JK |
856 | } |
857 | ||
6f43ed01 NA |
858 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
859 | { | |
860 | u64 fixed = DR6_FIXED_1; | |
861 | ||
862 | if (!guest_cpuid_has_rtm(vcpu)) | |
863 | fixed |= DR6_RTM; | |
864 | return fixed; | |
865 | } | |
866 | ||
338dbc97 | 867 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
868 | { |
869 | switch (dr) { | |
870 | case 0 ... 3: | |
871 | vcpu->arch.db[dr] = val; | |
872 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
873 | vcpu->arch.eff_db[dr] = val; | |
874 | break; | |
875 | case 4: | |
020df079 GN |
876 | /* fall through */ |
877 | case 6: | |
338dbc97 GN |
878 | if (val & 0xffffffff00000000ULL) |
879 | return -1; /* #GP */ | |
6f43ed01 | 880 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
73aaf249 | 881 | kvm_update_dr6(vcpu); |
020df079 GN |
882 | break; |
883 | case 5: | |
020df079 GN |
884 | /* fall through */ |
885 | default: /* 7 */ | |
338dbc97 GN |
886 | if (val & 0xffffffff00000000ULL) |
887 | return -1; /* #GP */ | |
020df079 | 888 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 889 | kvm_update_dr7(vcpu); |
020df079 GN |
890 | break; |
891 | } | |
892 | ||
893 | return 0; | |
894 | } | |
338dbc97 GN |
895 | |
896 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
897 | { | |
16f8a6f9 | 898 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 899 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
900 | return 1; |
901 | } | |
902 | return 0; | |
338dbc97 | 903 | } |
020df079 GN |
904 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
905 | ||
16f8a6f9 | 906 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
907 | { |
908 | switch (dr) { | |
909 | case 0 ... 3: | |
910 | *val = vcpu->arch.db[dr]; | |
911 | break; | |
912 | case 4: | |
020df079 GN |
913 | /* fall through */ |
914 | case 6: | |
73aaf249 JK |
915 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
916 | *val = vcpu->arch.dr6; | |
917 | else | |
918 | *val = kvm_x86_ops->get_dr6(vcpu); | |
020df079 GN |
919 | break; |
920 | case 5: | |
020df079 GN |
921 | /* fall through */ |
922 | default: /* 7 */ | |
923 | *val = vcpu->arch.dr7; | |
924 | break; | |
925 | } | |
338dbc97 GN |
926 | return 0; |
927 | } | |
020df079 GN |
928 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
929 | ||
022cd0e8 AK |
930 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
931 | { | |
932 | u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
933 | u64 data; | |
934 | int err; | |
935 | ||
c6702c9d | 936 | err = kvm_pmu_rdpmc(vcpu, ecx, &data); |
022cd0e8 AK |
937 | if (err) |
938 | return err; | |
939 | kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); | |
940 | kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); | |
941 | return err; | |
942 | } | |
943 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
944 | ||
043405e1 CO |
945 | /* |
946 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
947 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
948 | * | |
949 | * This list is modified at module load time to reflect the | |
e3267cbb | 950 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
62ef68bb PB |
951 | * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs |
952 | * may depend on host virtualization features rather than host cpu features. | |
043405e1 | 953 | */ |
e3267cbb | 954 | |
043405e1 CO |
955 | static u32 msrs_to_save[] = { |
956 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
8c06585d | 957 | MSR_STAR, |
043405e1 CO |
958 | #ifdef CONFIG_X86_64 |
959 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
960 | #endif | |
b3897a49 | 961 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
9dbe6cf9 | 962 | MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
043405e1 CO |
963 | }; |
964 | ||
965 | static unsigned num_msrs_to_save; | |
966 | ||
62ef68bb PB |
967 | static u32 emulated_msrs[] = { |
968 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, | |
969 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
970 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
971 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
e7d9513b AS |
972 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
973 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 974 | HV_X64_MSR_RESET, |
11c4b1ca | 975 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 976 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 977 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 978 | HV_X64_MSR_STIMER0_CONFIG, |
62ef68bb PB |
979 | HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, |
980 | MSR_KVM_PV_EOI_EN, | |
981 | ||
ba904635 | 982 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 983 | MSR_IA32_TSCDEADLINE, |
043405e1 | 984 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
985 | MSR_IA32_MCG_STATUS, |
986 | MSR_IA32_MCG_CTL, | |
64d60670 | 987 | MSR_IA32_SMBASE, |
043405e1 CO |
988 | }; |
989 | ||
62ef68bb PB |
990 | static unsigned num_emulated_msrs; |
991 | ||
384bb783 | 992 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 993 | { |
b69e8cae | 994 | if (efer & efer_reserved_bits) |
384bb783 | 995 | return false; |
15c4a640 | 996 | |
1b2fd70c AG |
997 | if (efer & EFER_FFXSR) { |
998 | struct kvm_cpuid_entry2 *feat; | |
999 | ||
1000 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 1001 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
384bb783 | 1002 | return false; |
1b2fd70c AG |
1003 | } |
1004 | ||
d8017474 AG |
1005 | if (efer & EFER_SVME) { |
1006 | struct kvm_cpuid_entry2 *feat; | |
1007 | ||
1008 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 1009 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
384bb783 | 1010 | return false; |
d8017474 AG |
1011 | } |
1012 | ||
384bb783 JK |
1013 | return true; |
1014 | } | |
1015 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1016 | ||
1017 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1018 | { | |
1019 | u64 old_efer = vcpu->arch.efer; | |
1020 | ||
1021 | if (!kvm_valid_efer(vcpu, efer)) | |
1022 | return 1; | |
1023 | ||
1024 | if (is_paging(vcpu) | |
1025 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1026 | return 1; | |
1027 | ||
15c4a640 | 1028 | efer &= ~EFER_LMA; |
f6801dff | 1029 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1030 | |
a3d204e2 SY |
1031 | kvm_x86_ops->set_efer(vcpu, efer); |
1032 | ||
aad82703 SY |
1033 | /* Update reserved bits */ |
1034 | if ((efer ^ old_efer) & EFER_NX) | |
1035 | kvm_mmu_reset_context(vcpu); | |
1036 | ||
b69e8cae | 1037 | return 0; |
15c4a640 CO |
1038 | } |
1039 | ||
f2b4b7dd JR |
1040 | void kvm_enable_efer_bits(u64 mask) |
1041 | { | |
1042 | efer_reserved_bits &= ~mask; | |
1043 | } | |
1044 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1045 | ||
15c4a640 CO |
1046 | /* |
1047 | * Writes msr value into into the appropriate "register". | |
1048 | * Returns 0 on success, non-0 otherwise. | |
1049 | * Assumes vcpu_load() was already called. | |
1050 | */ | |
8fe8ab46 | 1051 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 1052 | { |
854e8bb1 NA |
1053 | switch (msr->index) { |
1054 | case MSR_FS_BASE: | |
1055 | case MSR_GS_BASE: | |
1056 | case MSR_KERNEL_GS_BASE: | |
1057 | case MSR_CSTAR: | |
1058 | case MSR_LSTAR: | |
1059 | if (is_noncanonical_address(msr->data)) | |
1060 | return 1; | |
1061 | break; | |
1062 | case MSR_IA32_SYSENTER_EIP: | |
1063 | case MSR_IA32_SYSENTER_ESP: | |
1064 | /* | |
1065 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1066 | * non-canonical address is written on Intel but not on | |
1067 | * AMD (which ignores the top 32-bits, because it does | |
1068 | * not implement 64-bit SYSENTER). | |
1069 | * | |
1070 | * 64-bit code should hence be able to write a non-canonical | |
1071 | * value on AMD. Making the address canonical ensures that | |
1072 | * vmentry does not fail on Intel after writing a non-canonical | |
1073 | * value, and that something deterministic happens if the guest | |
1074 | * invokes 64-bit SYSENTER. | |
1075 | */ | |
1076 | msr->data = get_canonical(msr->data); | |
1077 | } | |
8fe8ab46 | 1078 | return kvm_x86_ops->set_msr(vcpu, msr); |
15c4a640 | 1079 | } |
854e8bb1 | 1080 | EXPORT_SYMBOL_GPL(kvm_set_msr); |
15c4a640 | 1081 | |
313a3dc7 CO |
1082 | /* |
1083 | * Adapt set_msr() to msr_io()'s calling convention | |
1084 | */ | |
609e36d3 PB |
1085 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1086 | { | |
1087 | struct msr_data msr; | |
1088 | int r; | |
1089 | ||
1090 | msr.index = index; | |
1091 | msr.host_initiated = true; | |
1092 | r = kvm_get_msr(vcpu, &msr); | |
1093 | if (r) | |
1094 | return r; | |
1095 | ||
1096 | *data = msr.data; | |
1097 | return 0; | |
1098 | } | |
1099 | ||
313a3dc7 CO |
1100 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1101 | { | |
8fe8ab46 WA |
1102 | struct msr_data msr; |
1103 | ||
1104 | msr.data = *data; | |
1105 | msr.index = index; | |
1106 | msr.host_initiated = true; | |
1107 | return kvm_set_msr(vcpu, &msr); | |
313a3dc7 CO |
1108 | } |
1109 | ||
16e8d74d MT |
1110 | #ifdef CONFIG_X86_64 |
1111 | struct pvclock_gtod_data { | |
1112 | seqcount_t seq; | |
1113 | ||
1114 | struct { /* extract of a clocksource struct */ | |
1115 | int vclock_mode; | |
1116 | cycle_t cycle_last; | |
1117 | cycle_t mask; | |
1118 | u32 mult; | |
1119 | u32 shift; | |
1120 | } clock; | |
1121 | ||
cbcf2dd3 TG |
1122 | u64 boot_ns; |
1123 | u64 nsec_base; | |
16e8d74d MT |
1124 | }; |
1125 | ||
1126 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1127 | ||
1128 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1129 | { | |
1130 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
cbcf2dd3 TG |
1131 | u64 boot_ns; |
1132 | ||
876e7881 | 1133 | boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); |
16e8d74d MT |
1134 | |
1135 | write_seqcount_begin(&vdata->seq); | |
1136 | ||
1137 | /* copy pvclock gtod data */ | |
876e7881 PZ |
1138 | vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; |
1139 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; | |
1140 | vdata->clock.mask = tk->tkr_mono.mask; | |
1141 | vdata->clock.mult = tk->tkr_mono.mult; | |
1142 | vdata->clock.shift = tk->tkr_mono.shift; | |
16e8d74d | 1143 | |
cbcf2dd3 | 1144 | vdata->boot_ns = boot_ns; |
876e7881 | 1145 | vdata->nsec_base = tk->tkr_mono.xtime_nsec; |
16e8d74d MT |
1146 | |
1147 | write_seqcount_end(&vdata->seq); | |
1148 | } | |
1149 | #endif | |
1150 | ||
bab5bb39 NK |
1151 | void kvm_set_pending_timer(struct kvm_vcpu *vcpu) |
1152 | { | |
1153 | /* | |
1154 | * Note: KVM_REQ_PENDING_TIMER is implicitly checked in | |
1155 | * vcpu_enter_guest. This function is only called from | |
1156 | * the physical CPU that is running vcpu. | |
1157 | */ | |
1158 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
1159 | } | |
16e8d74d | 1160 | |
18068523 GOC |
1161 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1162 | { | |
9ed3c444 AK |
1163 | int version; |
1164 | int r; | |
50d0a0f9 | 1165 | struct pvclock_wall_clock wc; |
923de3cf | 1166 | struct timespec boot; |
18068523 GOC |
1167 | |
1168 | if (!wall_clock) | |
1169 | return; | |
1170 | ||
9ed3c444 AK |
1171 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1172 | if (r) | |
1173 | return; | |
1174 | ||
1175 | if (version & 1) | |
1176 | ++version; /* first time write, random junk */ | |
1177 | ||
1178 | ++version; | |
18068523 | 1179 | |
1dab1345 NK |
1180 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
1181 | return; | |
18068523 | 1182 | |
50d0a0f9 GH |
1183 | /* |
1184 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1185 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
1186 | * wall clock specified here. guest system time equals host |
1187 | * system time for us, thus we must fill in host boot time here. | |
1188 | */ | |
923de3cf | 1189 | getboottime(&boot); |
50d0a0f9 | 1190 | |
4b648665 BR |
1191 | if (kvm->arch.kvmclock_offset) { |
1192 | struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); | |
1193 | boot = timespec_sub(boot, ts); | |
1194 | } | |
50d0a0f9 GH |
1195 | wc.sec = boot.tv_sec; |
1196 | wc.nsec = boot.tv_nsec; | |
1197 | wc.version = version; | |
18068523 GOC |
1198 | |
1199 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1200 | ||
1201 | version++; | |
1202 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1203 | } |
1204 | ||
50d0a0f9 GH |
1205 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
1206 | { | |
b51012de PB |
1207 | do_shl32_div32(dividend, divisor); |
1208 | return dividend; | |
50d0a0f9 GH |
1209 | } |
1210 | ||
3ae13faa | 1211 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 1212 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 1213 | { |
5f4e3f88 | 1214 | uint64_t scaled64; |
50d0a0f9 GH |
1215 | int32_t shift = 0; |
1216 | uint64_t tps64; | |
1217 | uint32_t tps32; | |
1218 | ||
3ae13faa PB |
1219 | tps64 = base_hz; |
1220 | scaled64 = scaled_hz; | |
50933623 | 1221 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
1222 | tps64 >>= 1; |
1223 | shift--; | |
1224 | } | |
1225 | ||
1226 | tps32 = (uint32_t)tps64; | |
50933623 JK |
1227 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
1228 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
1229 | scaled64 >>= 1; |
1230 | else | |
1231 | tps32 <<= 1; | |
50d0a0f9 GH |
1232 | shift++; |
1233 | } | |
1234 | ||
5f4e3f88 ZA |
1235 | *pshift = shift; |
1236 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 | 1237 | |
3ae13faa PB |
1238 | pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", |
1239 | __func__, base_hz, scaled_hz, shift, *pmultiplier); | |
50d0a0f9 GH |
1240 | } |
1241 | ||
d828199e | 1242 | #ifdef CONFIG_X86_64 |
16e8d74d | 1243 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 1244 | #endif |
16e8d74d | 1245 | |
c8076604 | 1246 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 1247 | static unsigned long max_tsc_khz; |
c8076604 | 1248 | |
cc578287 | 1249 | static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) |
8cfdc000 | 1250 | { |
cc578287 ZA |
1251 | return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, |
1252 | vcpu->arch.virtual_tsc_shift); | |
8cfdc000 ZA |
1253 | } |
1254 | ||
cc578287 | 1255 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 1256 | { |
cc578287 ZA |
1257 | u64 v = (u64)khz * (1000000 + ppm); |
1258 | do_div(v, 1000000); | |
1259 | return v; | |
1e993611 JR |
1260 | } |
1261 | ||
381d585c HZ |
1262 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
1263 | { | |
1264 | u64 ratio; | |
1265 | ||
1266 | /* Guest TSC same frequency as host TSC? */ | |
1267 | if (!scale) { | |
1268 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
1269 | return 0; | |
1270 | } | |
1271 | ||
1272 | /* TSC scaling supported? */ | |
1273 | if (!kvm_has_tsc_control) { | |
1274 | if (user_tsc_khz > tsc_khz) { | |
1275 | vcpu->arch.tsc_catchup = 1; | |
1276 | vcpu->arch.tsc_always_catchup = 1; | |
1277 | return 0; | |
1278 | } else { | |
1279 | WARN(1, "user requested TSC rate below hardware speed\n"); | |
1280 | return -1; | |
1281 | } | |
1282 | } | |
1283 | ||
1284 | /* TSC scaling required - calculate ratio */ | |
1285 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
1286 | user_tsc_khz, tsc_khz); | |
1287 | ||
1288 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
1289 | WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", | |
1290 | user_tsc_khz); | |
1291 | return -1; | |
1292 | } | |
1293 | ||
1294 | vcpu->arch.tsc_scaling_ratio = ratio; | |
1295 | return 0; | |
1296 | } | |
1297 | ||
4941b8cb | 1298 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 1299 | { |
cc578287 ZA |
1300 | u32 thresh_lo, thresh_hi; |
1301 | int use_scaling = 0; | |
217fc9cf | 1302 | |
03ba32ca | 1303 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 1304 | if (user_tsc_khz == 0) { |
ad721883 HZ |
1305 | /* set tsc_scaling_ratio to a safe value */ |
1306 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
381d585c | 1307 | return -1; |
ad721883 | 1308 | } |
03ba32ca | 1309 | |
c285545f | 1310 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 1311 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
1312 | &vcpu->arch.virtual_tsc_shift, |
1313 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 1314 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
1315 | |
1316 | /* | |
1317 | * Compute the variation in TSC rate which is acceptable | |
1318 | * within the range of tolerance and decide if the | |
1319 | * rate being applied is within that bounds of the hardware | |
1320 | * rate. If so, no scaling or compensation need be done. | |
1321 | */ | |
1322 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1323 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
1324 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
1325 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
1326 | use_scaling = 1; |
1327 | } | |
4941b8cb | 1328 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
1329 | } |
1330 | ||
1331 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1332 | { | |
e26101b1 | 1333 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1334 | vcpu->arch.virtual_tsc_mult, |
1335 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1336 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1337 | return tsc; |
1338 | } | |
1339 | ||
69b0049a | 1340 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
1341 | { |
1342 | #ifdef CONFIG_X86_64 | |
1343 | bool vcpus_matched; | |
b48aa97e MT |
1344 | struct kvm_arch *ka = &vcpu->kvm->arch; |
1345 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1346 | ||
1347 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1348 | atomic_read(&vcpu->kvm->online_vcpus)); | |
1349 | ||
7f187922 MT |
1350 | /* |
1351 | * Once the masterclock is enabled, always perform request in | |
1352 | * order to update it. | |
1353 | * | |
1354 | * In order to enable masterclock, the host clocksource must be TSC | |
1355 | * and the vcpus need to have matched TSCs. When that happens, | |
1356 | * perform request to enable masterclock. | |
1357 | */ | |
1358 | if (ka->use_master_clock || | |
1359 | (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) | |
b48aa97e MT |
1360 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1361 | ||
1362 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
1363 | atomic_read(&vcpu->kvm->online_vcpus), | |
1364 | ka->use_master_clock, gtod->clock.vclock_mode); | |
1365 | #endif | |
1366 | } | |
1367 | ||
ba904635 WA |
1368 | static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) |
1369 | { | |
1370 | u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); | |
1371 | vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; | |
1372 | } | |
1373 | ||
35181e86 HZ |
1374 | /* |
1375 | * Multiply tsc by a fixed point number represented by ratio. | |
1376 | * | |
1377 | * The most significant 64-N bits (mult) of ratio represent the | |
1378 | * integral part of the fixed point number; the remaining N bits | |
1379 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
1380 | * point number (mult + frac * 2^(-N)). | |
1381 | * | |
1382 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
1383 | */ | |
1384 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
1385 | { | |
1386 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
1387 | } | |
1388 | ||
1389 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
1390 | { | |
1391 | u64 _tsc = tsc; | |
1392 | u64 ratio = vcpu->arch.tsc_scaling_ratio; | |
1393 | ||
1394 | if (ratio != kvm_default_tsc_scaling_ratio) | |
1395 | _tsc = __scale_tsc(ratio, tsc); | |
1396 | ||
1397 | return _tsc; | |
1398 | } | |
1399 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
1400 | ||
07c1419a HZ |
1401 | static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
1402 | { | |
1403 | u64 tsc; | |
1404 | ||
1405 | tsc = kvm_scale_tsc(vcpu, rdtsc()); | |
1406 | ||
1407 | return target_tsc - tsc; | |
1408 | } | |
1409 | ||
4ba76538 HZ |
1410 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
1411 | { | |
1412 | return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc)); | |
1413 | } | |
1414 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
1415 | ||
8fe8ab46 | 1416 | void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) |
99e3e30a ZA |
1417 | { |
1418 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1419 | u64 offset, ns, elapsed; |
99e3e30a | 1420 | unsigned long flags; |
02626b6a | 1421 | s64 usdiff; |
b48aa97e | 1422 | bool matched; |
0d3da0d2 | 1423 | bool already_matched; |
8fe8ab46 | 1424 | u64 data = msr->data; |
99e3e30a | 1425 | |
038f8c11 | 1426 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
07c1419a | 1427 | offset = kvm_compute_tsc_offset(vcpu, data); |
759379dd | 1428 | ns = get_kernel_ns(); |
f38e098f | 1429 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 1430 | |
03ba32ca | 1431 | if (vcpu->arch.virtual_tsc_khz) { |
8915aa27 MT |
1432 | int faulted = 0; |
1433 | ||
03ba32ca MT |
1434 | /* n.b - signed multiplication and division required */ |
1435 | usdiff = data - kvm->arch.last_tsc_write; | |
5d3cb0f6 | 1436 | #ifdef CONFIG_X86_64 |
03ba32ca | 1437 | usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; |
5d3cb0f6 | 1438 | #else |
03ba32ca | 1439 | /* do_div() only does unsigned */ |
8915aa27 MT |
1440 | asm("1: idivl %[divisor]\n" |
1441 | "2: xor %%edx, %%edx\n" | |
1442 | " movl $0, %[faulted]\n" | |
1443 | "3:\n" | |
1444 | ".section .fixup,\"ax\"\n" | |
1445 | "4: movl $1, %[faulted]\n" | |
1446 | " jmp 3b\n" | |
1447 | ".previous\n" | |
1448 | ||
1449 | _ASM_EXTABLE(1b, 4b) | |
1450 | ||
1451 | : "=A"(usdiff), [faulted] "=r" (faulted) | |
1452 | : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); | |
1453 | ||
5d3cb0f6 | 1454 | #endif |
03ba32ca MT |
1455 | do_div(elapsed, 1000); |
1456 | usdiff -= elapsed; | |
1457 | if (usdiff < 0) | |
1458 | usdiff = -usdiff; | |
8915aa27 MT |
1459 | |
1460 | /* idivl overflow => difference is larger than USEC_PER_SEC */ | |
1461 | if (faulted) | |
1462 | usdiff = USEC_PER_SEC; | |
03ba32ca MT |
1463 | } else |
1464 | usdiff = USEC_PER_SEC; /* disable TSC match window below */ | |
f38e098f ZA |
1465 | |
1466 | /* | |
5d3cb0f6 ZA |
1467 | * Special case: TSC write with a small delta (1 second) of virtual |
1468 | * cycle time against real time is interpreted as an attempt to | |
1469 | * synchronize the CPU. | |
1470 | * | |
1471 | * For a reliable TSC, we can match TSC offsets, and for an unstable | |
1472 | * TSC, we add elapsed time in this computation. We could let the | |
1473 | * compensation code attempt to catch up if we fall behind, but | |
1474 | * it's better to try to match offsets from the beginning. | |
1475 | */ | |
02626b6a | 1476 | if (usdiff < USEC_PER_SEC && |
5d3cb0f6 | 1477 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
f38e098f | 1478 | if (!check_tsc_unstable()) { |
e26101b1 | 1479 | offset = kvm->arch.cur_tsc_offset; |
f38e098f ZA |
1480 | pr_debug("kvm: matched tsc offset for %llu\n", data); |
1481 | } else { | |
857e4099 | 1482 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 1483 | data += delta; |
07c1419a | 1484 | offset = kvm_compute_tsc_offset(vcpu, data); |
759379dd | 1485 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); |
f38e098f | 1486 | } |
b48aa97e | 1487 | matched = true; |
0d3da0d2 | 1488 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
1489 | } else { |
1490 | /* | |
1491 | * We split periods of matched TSC writes into generations. | |
1492 | * For each generation, we track the original measured | |
1493 | * nanosecond time, offset, and write, so if TSCs are in | |
1494 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 1495 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
1496 | * |
1497 | * These values are tracked in kvm->arch.cur_xxx variables. | |
1498 | */ | |
1499 | kvm->arch.cur_tsc_generation++; | |
1500 | kvm->arch.cur_tsc_nsec = ns; | |
1501 | kvm->arch.cur_tsc_write = data; | |
1502 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 1503 | matched = false; |
0d3da0d2 | 1504 | pr_debug("kvm: new tsc generation %llu, clock %llu\n", |
e26101b1 | 1505 | kvm->arch.cur_tsc_generation, data); |
f38e098f | 1506 | } |
e26101b1 ZA |
1507 | |
1508 | /* | |
1509 | * We also track th most recent recorded KHZ, write and time to | |
1510 | * allow the matching interval to be extended at each write. | |
1511 | */ | |
f38e098f ZA |
1512 | kvm->arch.last_tsc_nsec = ns; |
1513 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 1514 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 1515 | |
b183aa58 | 1516 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
1517 | |
1518 | /* Keep track of which generation this VCPU has synchronized to */ | |
1519 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
1520 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
1521 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
1522 | ||
ba904635 WA |
1523 | if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) |
1524 | update_ia32_tsc_adjust_msr(vcpu, offset); | |
e26101b1 ZA |
1525 | kvm_x86_ops->write_tsc_offset(vcpu, offset); |
1526 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
b48aa97e MT |
1527 | |
1528 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 1529 | if (!matched) { |
b48aa97e | 1530 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
1531 | } else if (!already_matched) { |
1532 | kvm->arch.nr_vcpus_matched_tsc++; | |
1533 | } | |
b48aa97e MT |
1534 | |
1535 | kvm_track_tsc_matching(vcpu); | |
1536 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 1537 | } |
e26101b1 | 1538 | |
99e3e30a ZA |
1539 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
1540 | ||
58ea6767 HZ |
1541 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
1542 | s64 adjustment) | |
1543 | { | |
1544 | kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment); | |
1545 | } | |
1546 | ||
1547 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
1548 | { | |
1549 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) | |
1550 | WARN_ON(adjustment < 0); | |
1551 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); | |
1552 | kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment); | |
1553 | } | |
1554 | ||
d828199e MT |
1555 | #ifdef CONFIG_X86_64 |
1556 | ||
1557 | static cycle_t read_tsc(void) | |
1558 | { | |
03b9730b AL |
1559 | cycle_t ret = (cycle_t)rdtsc_ordered(); |
1560 | u64 last = pvclock_gtod_data.clock.cycle_last; | |
d828199e MT |
1561 | |
1562 | if (likely(ret >= last)) | |
1563 | return ret; | |
1564 | ||
1565 | /* | |
1566 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 1567 | * predictable (it's just a function of time and the likely is |
d828199e MT |
1568 | * very likely) and there's a data dependence, so force GCC |
1569 | * to generate a branch instead. I don't barrier() because | |
1570 | * we don't actually need a barrier, and if this function | |
1571 | * ever gets inlined it will generate worse code. | |
1572 | */ | |
1573 | asm volatile (""); | |
1574 | return last; | |
1575 | } | |
1576 | ||
1577 | static inline u64 vgettsc(cycle_t *cycle_now) | |
1578 | { | |
1579 | long v; | |
1580 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1581 | ||
1582 | *cycle_now = read_tsc(); | |
1583 | ||
1584 | v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; | |
1585 | return v * gtod->clock.mult; | |
1586 | } | |
1587 | ||
cbcf2dd3 | 1588 | static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) |
d828199e | 1589 | { |
cbcf2dd3 | 1590 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 1591 | unsigned long seq; |
d828199e | 1592 | int mode; |
cbcf2dd3 | 1593 | u64 ns; |
d828199e | 1594 | |
d828199e MT |
1595 | do { |
1596 | seq = read_seqcount_begin(>od->seq); | |
1597 | mode = gtod->clock.vclock_mode; | |
cbcf2dd3 | 1598 | ns = gtod->nsec_base; |
d828199e MT |
1599 | ns += vgettsc(cycle_now); |
1600 | ns >>= gtod->clock.shift; | |
cbcf2dd3 | 1601 | ns += gtod->boot_ns; |
d828199e | 1602 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 1603 | *t = ns; |
d828199e MT |
1604 | |
1605 | return mode; | |
1606 | } | |
1607 | ||
1608 | /* returns true if host is using tsc clocksource */ | |
1609 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) | |
1610 | { | |
d828199e MT |
1611 | /* checked again under seqlock below */ |
1612 | if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) | |
1613 | return false; | |
1614 | ||
cbcf2dd3 | 1615 | return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; |
d828199e MT |
1616 | } |
1617 | #endif | |
1618 | ||
1619 | /* | |
1620 | * | |
b48aa97e MT |
1621 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
1622 | * across virtual CPUs, the following condition is possible. | |
1623 | * Each numbered line represents an event visible to both | |
d828199e MT |
1624 | * CPUs at the next numbered event. |
1625 | * | |
1626 | * "timespecX" represents host monotonic time. "tscX" represents | |
1627 | * RDTSC value. | |
1628 | * | |
1629 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
1630 | * | |
1631 | * 1. read timespec0,tsc0 | |
1632 | * 2. | timespec1 = timespec0 + N | |
1633 | * | tsc1 = tsc0 + M | |
1634 | * 3. transition to guest | transition to guest | |
1635 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
1636 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
1637 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
1638 | * | |
1639 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
1640 | * | |
1641 | * - ret0 < ret1 | |
1642 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
1643 | * ... | |
1644 | * - 0 < N - M => M < N | |
1645 | * | |
1646 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
1647 | * always the case (the difference between two distinct xtime instances | |
1648 | * might be smaller then the difference between corresponding TSC reads, | |
1649 | * when updating guest vcpus pvclock areas). | |
1650 | * | |
1651 | * To avoid that problem, do not allow visibility of distinct | |
1652 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
1653 | * copy of host monotonic time values. Update that master copy | |
1654 | * in lockstep. | |
1655 | * | |
b48aa97e | 1656 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
1657 | * |
1658 | */ | |
1659 | ||
1660 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
1661 | { | |
1662 | #ifdef CONFIG_X86_64 | |
1663 | struct kvm_arch *ka = &kvm->arch; | |
1664 | int vclock_mode; | |
b48aa97e MT |
1665 | bool host_tsc_clocksource, vcpus_matched; |
1666 | ||
1667 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1668 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
1669 | |
1670 | /* | |
1671 | * If the host uses TSC clock, then passthrough TSC as stable | |
1672 | * to the guest. | |
1673 | */ | |
b48aa97e | 1674 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
1675 | &ka->master_kernel_ns, |
1676 | &ka->master_cycle_now); | |
1677 | ||
16a96021 | 1678 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
54750f2c MT |
1679 | && !backwards_tsc_observed |
1680 | && !ka->boot_vcpu_runs_old_kvmclock; | |
b48aa97e | 1681 | |
d828199e MT |
1682 | if (ka->use_master_clock) |
1683 | atomic_set(&kvm_guest_has_master_clock, 1); | |
1684 | ||
1685 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
1686 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
1687 | vcpus_matched); | |
d828199e MT |
1688 | #endif |
1689 | } | |
1690 | ||
2860c4b1 PB |
1691 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
1692 | { | |
1693 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
1694 | } | |
1695 | ||
2e762ff7 MT |
1696 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
1697 | { | |
1698 | #ifdef CONFIG_X86_64 | |
1699 | int i; | |
1700 | struct kvm_vcpu *vcpu; | |
1701 | struct kvm_arch *ka = &kvm->arch; | |
1702 | ||
1703 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1704 | kvm_make_mclock_inprogress_request(kvm); | |
1705 | /* no guest entries from this point */ | |
1706 | pvclock_update_vm_gtod_copy(kvm); | |
1707 | ||
1708 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 1709 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
1710 | |
1711 | /* guest entries allowed */ | |
1712 | kvm_for_each_vcpu(i, vcpu, kvm) | |
1713 | clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); | |
1714 | ||
1715 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
1716 | #endif | |
1717 | } | |
1718 | ||
34c238a1 | 1719 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 1720 | { |
78db6a50 | 1721 | unsigned long flags, tgt_tsc_khz; |
18068523 | 1722 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 1723 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 1724 | s64 kernel_ns; |
d828199e | 1725 | u64 tsc_timestamp, host_tsc; |
0b79459b | 1726 | struct pvclock_vcpu_time_info guest_hv_clock; |
51d59c6b | 1727 | u8 pvclock_flags; |
d828199e MT |
1728 | bool use_master_clock; |
1729 | ||
1730 | kernel_ns = 0; | |
1731 | host_tsc = 0; | |
18068523 | 1732 | |
d828199e MT |
1733 | /* |
1734 | * If the host uses TSC clock, then passthrough TSC as stable | |
1735 | * to the guest. | |
1736 | */ | |
1737 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1738 | use_master_clock = ka->use_master_clock; | |
1739 | if (use_master_clock) { | |
1740 | host_tsc = ka->master_cycle_now; | |
1741 | kernel_ns = ka->master_kernel_ns; | |
1742 | } | |
1743 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
1744 | |
1745 | /* Keep irq disabled to prevent changes to the clock */ | |
1746 | local_irq_save(flags); | |
78db6a50 PB |
1747 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
1748 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
1749 | local_irq_restore(flags); |
1750 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
1751 | return 1; | |
1752 | } | |
d828199e | 1753 | if (!use_master_clock) { |
4ea1636b | 1754 | host_tsc = rdtsc(); |
d828199e MT |
1755 | kernel_ns = get_kernel_ns(); |
1756 | } | |
1757 | ||
4ba76538 | 1758 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 1759 | |
c285545f ZA |
1760 | /* |
1761 | * We may have to catch up the TSC to match elapsed wall clock | |
1762 | * time for two reasons, even if kvmclock is used. | |
1763 | * 1) CPU could have been running below the maximum TSC rate | |
1764 | * 2) Broken TSC compensation resets the base at each VCPU | |
1765 | * entry to avoid unknown leaps of TSC even when running | |
1766 | * again on the same CPU. This may cause apparent elapsed | |
1767 | * time to disappear, and the guest to stand still or run | |
1768 | * very slowly. | |
1769 | */ | |
1770 | if (vcpu->tsc_catchup) { | |
1771 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
1772 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 1773 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
1774 | tsc_timestamp = tsc; |
1775 | } | |
50d0a0f9 GH |
1776 | } |
1777 | ||
18068523 GOC |
1778 | local_irq_restore(flags); |
1779 | ||
0b79459b | 1780 | if (!vcpu->pv_time_enabled) |
c285545f | 1781 | return 0; |
18068523 | 1782 | |
78db6a50 PB |
1783 | if (kvm_has_tsc_control) |
1784 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); | |
1785 | ||
1786 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 1787 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
1788 | &vcpu->hv_clock.tsc_shift, |
1789 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 1790 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
1791 | } |
1792 | ||
1793 | /* With all the info we got, fill in the values */ | |
1d5f066e | 1794 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 1795 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 1796 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 1797 | |
09a0c3f1 OH |
1798 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
1799 | &guest_hv_clock, sizeof(guest_hv_clock)))) | |
1800 | return 0; | |
1801 | ||
5dca0d91 RK |
1802 | /* This VCPU is paused, but it's legal for a guest to read another |
1803 | * VCPU's kvmclock, so we really have to follow the specification where | |
1804 | * it says that version is odd if data is being modified, and even after | |
1805 | * it is consistent. | |
1806 | * | |
1807 | * Version field updates must be kept separate. This is because | |
1808 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
1809 | * writes within a string instruction are weakly ordered. So there | |
1810 | * are three writes overall. | |
1811 | * | |
1812 | * As a small optimization, only write the version field in the first | |
1813 | * and third write. The vcpu->pv_time cache is still valid, because the | |
1814 | * version field is the first in the struct. | |
18068523 | 1815 | */ |
5dca0d91 RK |
1816 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); |
1817 | ||
1818 | vcpu->hv_clock.version = guest_hv_clock.version + 1; | |
1819 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, | |
1820 | &vcpu->hv_clock, | |
1821 | sizeof(vcpu->hv_clock.version)); | |
1822 | ||
1823 | smp_wmb(); | |
78c0337a MT |
1824 | |
1825 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
0b79459b | 1826 | pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); |
78c0337a MT |
1827 | |
1828 | if (vcpu->pvclock_set_guest_stopped_request) { | |
1829 | pvclock_flags |= PVCLOCK_GUEST_STOPPED; | |
1830 | vcpu->pvclock_set_guest_stopped_request = false; | |
1831 | } | |
1832 | ||
d828199e MT |
1833 | /* If the host uses TSC clocksource, then it is stable */ |
1834 | if (use_master_clock) | |
1835 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
1836 | ||
78c0337a MT |
1837 | vcpu->hv_clock.flags = pvclock_flags; |
1838 | ||
ce1a5e60 DM |
1839 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); |
1840 | ||
0b79459b AH |
1841 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
1842 | &vcpu->hv_clock, | |
1843 | sizeof(vcpu->hv_clock)); | |
5dca0d91 RK |
1844 | |
1845 | smp_wmb(); | |
1846 | ||
1847 | vcpu->hv_clock.version++; | |
1848 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, | |
1849 | &vcpu->hv_clock, | |
1850 | sizeof(vcpu->hv_clock.version)); | |
8cfdc000 | 1851 | return 0; |
c8076604 GH |
1852 | } |
1853 | ||
0061d53d MT |
1854 | /* |
1855 | * kvmclock updates which are isolated to a given vcpu, such as | |
1856 | * vcpu->cpu migration, should not allow system_timestamp from | |
1857 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
1858 | * correction applies to one vcpu's system_timestamp but not | |
1859 | * the others. | |
1860 | * | |
1861 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
1862 | * We need to rate-limit these requests though, as they can |
1863 | * considerably slow guests that have a large number of vcpus. | |
1864 | * The time for a remote vcpu to update its kvmclock is bound | |
1865 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
1866 | */ |
1867 | ||
7e44e449 AJ |
1868 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
1869 | ||
1870 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
1871 | { |
1872 | int i; | |
7e44e449 AJ |
1873 | struct delayed_work *dwork = to_delayed_work(work); |
1874 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
1875 | kvmclock_update_work); | |
1876 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
1877 | struct kvm_vcpu *vcpu; |
1878 | ||
1879 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 1880 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
1881 | kvm_vcpu_kick(vcpu); |
1882 | } | |
1883 | } | |
1884 | ||
7e44e449 AJ |
1885 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
1886 | { | |
1887 | struct kvm *kvm = v->kvm; | |
1888 | ||
105b21bb | 1889 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
1890 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
1891 | KVMCLOCK_UPDATE_DELAY); | |
1892 | } | |
1893 | ||
332967a3 AJ |
1894 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
1895 | ||
1896 | static void kvmclock_sync_fn(struct work_struct *work) | |
1897 | { | |
1898 | struct delayed_work *dwork = to_delayed_work(work); | |
1899 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
1900 | kvmclock_sync_work); | |
1901 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
1902 | ||
630994b3 MT |
1903 | if (!kvmclock_periodic_sync) |
1904 | return; | |
1905 | ||
332967a3 AJ |
1906 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
1907 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
1908 | KVMCLOCK_SYNC_PERIOD); | |
1909 | } | |
1910 | ||
890ca9ae | 1911 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1912 | { |
890ca9ae HY |
1913 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1914 | unsigned bank_num = mcg_cap & 0xff; | |
1915 | ||
15c4a640 | 1916 | switch (msr) { |
15c4a640 | 1917 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1918 | vcpu->arch.mcg_status = data; |
15c4a640 | 1919 | break; |
c7ac679c | 1920 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1921 | if (!(mcg_cap & MCG_CTL_P)) |
1922 | return 1; | |
1923 | if (data != 0 && data != ~(u64)0) | |
1924 | return -1; | |
1925 | vcpu->arch.mcg_ctl = data; | |
1926 | break; | |
1927 | default: | |
1928 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 1929 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae | 1930 | u32 offset = msr - MSR_IA32_MC0_CTL; |
114be429 AP |
1931 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1932 | * some Linux kernels though clear bit 10 in bank 4 to | |
1933 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1934 | * this to avoid an uncatched #GP in the guest | |
1935 | */ | |
890ca9ae | 1936 | if ((offset & 0x3) == 0 && |
114be429 | 1937 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
1938 | return -1; |
1939 | vcpu->arch.mce_banks[offset] = data; | |
1940 | break; | |
1941 | } | |
1942 | return 1; | |
1943 | } | |
1944 | return 0; | |
1945 | } | |
1946 | ||
ffde22ac ES |
1947 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
1948 | { | |
1949 | struct kvm *kvm = vcpu->kvm; | |
1950 | int lm = is_long_mode(vcpu); | |
1951 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1952 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1953 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1954 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1955 | u32 page_num = data & ~PAGE_MASK; | |
1956 | u64 page_addr = data & PAGE_MASK; | |
1957 | u8 *page; | |
1958 | int r; | |
1959 | ||
1960 | r = -E2BIG; | |
1961 | if (page_num >= blob_size) | |
1962 | goto out; | |
1963 | r = -ENOMEM; | |
ff5c2c03 SL |
1964 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
1965 | if (IS_ERR(page)) { | |
1966 | r = PTR_ERR(page); | |
ffde22ac | 1967 | goto out; |
ff5c2c03 | 1968 | } |
54bf36aa | 1969 | if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) |
ffde22ac ES |
1970 | goto out_free; |
1971 | r = 0; | |
1972 | out_free: | |
1973 | kfree(page); | |
1974 | out: | |
1975 | return r; | |
1976 | } | |
1977 | ||
344d9588 GN |
1978 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
1979 | { | |
1980 | gpa_t gpa = data & ~0x3f; | |
1981 | ||
4a969980 | 1982 | /* Bits 2:5 are reserved, Should be zero */ |
6adba527 | 1983 | if (data & 0x3c) |
344d9588 GN |
1984 | return 1; |
1985 | ||
1986 | vcpu->arch.apf.msr_val = data; | |
1987 | ||
1988 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
1989 | kvm_clear_async_pf_completion_queue(vcpu); | |
1990 | kvm_async_pf_hash_reset(vcpu); | |
1991 | return 0; | |
1992 | } | |
1993 | ||
8f964525 AH |
1994 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
1995 | sizeof(u32))) | |
344d9588 GN |
1996 | return 1; |
1997 | ||
6adba527 | 1998 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
344d9588 GN |
1999 | kvm_async_pf_wakeup_all(vcpu); |
2000 | return 0; | |
2001 | } | |
2002 | ||
12f9a48f GC |
2003 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2004 | { | |
0b79459b | 2005 | vcpu->arch.pv_time_enabled = false; |
12f9a48f GC |
2006 | } |
2007 | ||
c9aaa895 GC |
2008 | static void record_steal_time(struct kvm_vcpu *vcpu) |
2009 | { | |
2010 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2011 | return; | |
2012 | ||
2013 | if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2014 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) | |
2015 | return; | |
2016 | ||
35f3fae1 WL |
2017 | if (vcpu->arch.st.steal.version & 1) |
2018 | vcpu->arch.st.steal.version += 1; /* first time write, random junk */ | |
2019 | ||
2020 | vcpu->arch.st.steal.version += 1; | |
2021 | ||
2022 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2023 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); | |
2024 | ||
2025 | smp_wmb(); | |
2026 | ||
c54cdf14 LC |
2027 | vcpu->arch.st.steal.steal += current->sched_info.run_delay - |
2028 | vcpu->arch.st.last_steal; | |
2029 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
35f3fae1 WL |
2030 | |
2031 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2032 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); | |
2033 | ||
2034 | smp_wmb(); | |
2035 | ||
2036 | vcpu->arch.st.steal.version += 1; | |
c9aaa895 GC |
2037 | |
2038 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2039 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); | |
2040 | } | |
2041 | ||
8fe8ab46 | 2042 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2043 | { |
5753785f | 2044 | bool pr = false; |
8fe8ab46 WA |
2045 | u32 msr = msr_info->index; |
2046 | u64 data = msr_info->data; | |
5753785f | 2047 | |
15c4a640 | 2048 | switch (msr) { |
2e32b719 BP |
2049 | case MSR_AMD64_NB_CFG: |
2050 | case MSR_IA32_UCODE_REV: | |
2051 | case MSR_IA32_UCODE_WRITE: | |
2052 | case MSR_VM_HSAVE_PA: | |
2053 | case MSR_AMD64_PATCH_LOADER: | |
2054 | case MSR_AMD64_BU_CFG2: | |
2055 | break; | |
2056 | ||
15c4a640 | 2057 | case MSR_EFER: |
b69e8cae | 2058 | return set_efer(vcpu, data); |
8f1589d9 AP |
2059 | case MSR_K7_HWCR: |
2060 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 2061 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 2062 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
22d48b2d | 2063 | data &= ~(u64)0x40000; /* ignore Mc status write enable */ |
8f1589d9 | 2064 | if (data != 0) { |
a737f256 CD |
2065 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
2066 | data); | |
8f1589d9 AP |
2067 | return 1; |
2068 | } | |
15c4a640 | 2069 | break; |
f7c6d140 AP |
2070 | case MSR_FAM10H_MMIO_CONF_BASE: |
2071 | if (data != 0) { | |
a737f256 CD |
2072 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
2073 | "0x%llx\n", data); | |
f7c6d140 AP |
2074 | return 1; |
2075 | } | |
15c4a640 | 2076 | break; |
b5e2fec0 AG |
2077 | case MSR_IA32_DEBUGCTLMSR: |
2078 | if (!data) { | |
2079 | /* We support the non-activated case already */ | |
2080 | break; | |
2081 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
2082 | /* Values other than LBR and BTF are vendor-specific, | |
2083 | thus reserved and should throw a #GP */ | |
2084 | return 1; | |
2085 | } | |
a737f256 CD |
2086 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
2087 | __func__, data); | |
b5e2fec0 | 2088 | break; |
9ba075a6 | 2089 | case 0x200 ... 0x2ff: |
ff53604b | 2090 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 2091 | case MSR_IA32_APICBASE: |
58cb628d | 2092 | return kvm_set_apic_base(vcpu, msr_info); |
0105d1a5 GN |
2093 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2094 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
a3e06bbe LJ |
2095 | case MSR_IA32_TSCDEADLINE: |
2096 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2097 | break; | |
ba904635 WA |
2098 | case MSR_IA32_TSC_ADJUST: |
2099 | if (guest_cpuid_has_tsc_adjust(vcpu)) { | |
2100 | if (!msr_info->host_initiated) { | |
d913b904 | 2101 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 2102 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
2103 | } |
2104 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
2105 | } | |
2106 | break; | |
15c4a640 | 2107 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 2108 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 2109 | break; |
64d60670 PB |
2110 | case MSR_IA32_SMBASE: |
2111 | if (!msr_info->host_initiated) | |
2112 | return 1; | |
2113 | vcpu->arch.smbase = data; | |
2114 | break; | |
11c6bffa | 2115 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2116 | case MSR_KVM_WALL_CLOCK: |
2117 | vcpu->kvm->arch.wall_clock = data; | |
2118 | kvm_write_wall_clock(vcpu->kvm, data); | |
2119 | break; | |
11c6bffa | 2120 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 2121 | case MSR_KVM_SYSTEM_TIME: { |
0b79459b | 2122 | u64 gpa_offset; |
54750f2c MT |
2123 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2124 | ||
12f9a48f | 2125 | kvmclock_reset(vcpu); |
18068523 | 2126 | |
54750f2c MT |
2127 | if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { |
2128 | bool tmp = (msr == MSR_KVM_SYSTEM_TIME); | |
2129 | ||
2130 | if (ka->boot_vcpu_runs_old_kvmclock != tmp) | |
2131 | set_bit(KVM_REQ_MASTERCLOCK_UPDATE, | |
2132 | &vcpu->requests); | |
2133 | ||
2134 | ka->boot_vcpu_runs_old_kvmclock = tmp; | |
2135 | } | |
2136 | ||
18068523 | 2137 | vcpu->arch.time = data; |
0061d53d | 2138 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
18068523 GOC |
2139 | |
2140 | /* we verify if the enable bit is set... */ | |
2141 | if (!(data & 1)) | |
2142 | break; | |
2143 | ||
0b79459b | 2144 | gpa_offset = data & ~(PAGE_MASK | 1); |
18068523 | 2145 | |
0b79459b | 2146 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
8f964525 AH |
2147 | &vcpu->arch.pv_time, data & ~1ULL, |
2148 | sizeof(struct pvclock_vcpu_time_info))) | |
0b79459b AH |
2149 | vcpu->arch.pv_time_enabled = false; |
2150 | else | |
2151 | vcpu->arch.pv_time_enabled = true; | |
32cad84f | 2152 | |
18068523 GOC |
2153 | break; |
2154 | } | |
344d9588 GN |
2155 | case MSR_KVM_ASYNC_PF_EN: |
2156 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
2157 | return 1; | |
2158 | break; | |
c9aaa895 GC |
2159 | case MSR_KVM_STEAL_TIME: |
2160 | ||
2161 | if (unlikely(!sched_info_on())) | |
2162 | return 1; | |
2163 | ||
2164 | if (data & KVM_STEAL_RESERVED_MASK) | |
2165 | return 1; | |
2166 | ||
2167 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, | |
8f964525 AH |
2168 | data & KVM_STEAL_VALID_BITS, |
2169 | sizeof(struct kvm_steal_time))) | |
c9aaa895 GC |
2170 | return 1; |
2171 | ||
2172 | vcpu->arch.st.msr_val = data; | |
2173 | ||
2174 | if (!(data & KVM_MSR_ENABLED)) | |
2175 | break; | |
2176 | ||
c9aaa895 GC |
2177 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
2178 | ||
2179 | break; | |
ae7a2a3f MT |
2180 | case MSR_KVM_PV_EOI_EN: |
2181 | if (kvm_lapic_enable_pv_eoi(vcpu, data)) | |
2182 | return 1; | |
2183 | break; | |
c9aaa895 | 2184 | |
890ca9ae HY |
2185 | case MSR_IA32_MCG_CTL: |
2186 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2187 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
890ca9ae | 2188 | return set_msr_mce(vcpu, msr, data); |
71db6023 | 2189 | |
6912ac32 WH |
2190 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
2191 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
2192 | pr = true; /* fall through */ | |
2193 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: | |
2194 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 2195 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 2196 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
2197 | |
2198 | if (pr || data != 0) | |
a737f256 CD |
2199 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
2200 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 2201 | break; |
84e0cefa JS |
2202 | case MSR_K7_CLK_CTL: |
2203 | /* | |
2204 | * Ignore all writes to this no longer documented MSR. | |
2205 | * Writes are only relevant for old K7 processors, | |
2206 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 2207 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
2208 | * affected processor models on the command line, hence |
2209 | * the need to ignore the workaround. | |
2210 | */ | |
2211 | break; | |
55cd8e5a | 2212 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
e7d9513b AS |
2213 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
2214 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 2215 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
e7d9513b AS |
2216 | return kvm_hv_set_msr_common(vcpu, msr, data, |
2217 | msr_info->host_initiated); | |
91c9c3ed | 2218 | case MSR_IA32_BBL_CR_CTL3: |
2219 | /* Drop writes to this legacy MSR -- see rdmsr | |
2220 | * counterpart for further detail. | |
2221 | */ | |
a737f256 | 2222 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); |
91c9c3ed | 2223 | break; |
2b036c6b BO |
2224 | case MSR_AMD64_OSVW_ID_LENGTH: |
2225 | if (!guest_cpuid_has_osvw(vcpu)) | |
2226 | return 1; | |
2227 | vcpu->arch.osvw.length = data; | |
2228 | break; | |
2229 | case MSR_AMD64_OSVW_STATUS: | |
2230 | if (!guest_cpuid_has_osvw(vcpu)) | |
2231 | return 1; | |
2232 | vcpu->arch.osvw.status = data; | |
2233 | break; | |
15c4a640 | 2234 | default: |
ffde22ac ES |
2235 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
2236 | return xen_hvm_config(vcpu, data); | |
c6702c9d | 2237 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 2238 | return kvm_pmu_set_msr(vcpu, msr_info); |
ed85c068 | 2239 | if (!ignore_msrs) { |
a737f256 CD |
2240 | vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", |
2241 | msr, data); | |
ed85c068 AP |
2242 | return 1; |
2243 | } else { | |
a737f256 CD |
2244 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", |
2245 | msr, data); | |
ed85c068 AP |
2246 | break; |
2247 | } | |
15c4a640 CO |
2248 | } |
2249 | return 0; | |
2250 | } | |
2251 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
2252 | ||
2253 | ||
2254 | /* | |
2255 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2256 | * Returns 0 on success, non-0 otherwise. | |
2257 | * Assumes vcpu_load() was already called. | |
2258 | */ | |
609e36d3 | 2259 | int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 2260 | { |
609e36d3 | 2261 | return kvm_x86_ops->get_msr(vcpu, msr); |
15c4a640 | 2262 | } |
ff651cb6 | 2263 | EXPORT_SYMBOL_GPL(kvm_get_msr); |
15c4a640 | 2264 | |
890ca9ae | 2265 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
2266 | { |
2267 | u64 data; | |
890ca9ae HY |
2268 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2269 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
2270 | |
2271 | switch (msr) { | |
15c4a640 CO |
2272 | case MSR_IA32_P5_MC_ADDR: |
2273 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
2274 | data = 0; |
2275 | break; | |
15c4a640 | 2276 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
2277 | data = vcpu->arch.mcg_cap; |
2278 | break; | |
c7ac679c | 2279 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
2280 | if (!(mcg_cap & MCG_CTL_P)) |
2281 | return 1; | |
2282 | data = vcpu->arch.mcg_ctl; | |
2283 | break; | |
2284 | case MSR_IA32_MCG_STATUS: | |
2285 | data = vcpu->arch.mcg_status; | |
2286 | break; | |
2287 | default: | |
2288 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2289 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae HY |
2290 | u32 offset = msr - MSR_IA32_MC0_CTL; |
2291 | data = vcpu->arch.mce_banks[offset]; | |
2292 | break; | |
2293 | } | |
2294 | return 1; | |
2295 | } | |
2296 | *pdata = data; | |
2297 | return 0; | |
2298 | } | |
2299 | ||
609e36d3 | 2300 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 2301 | { |
609e36d3 | 2302 | switch (msr_info->index) { |
890ca9ae | 2303 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 2304 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
2305 | case MSR_IA32_DEBUGCTLMSR: |
2306 | case MSR_IA32_LASTBRANCHFROMIP: | |
2307 | case MSR_IA32_LASTBRANCHTOIP: | |
2308 | case MSR_IA32_LASTINTFROMIP: | |
2309 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd | 2310 | case MSR_K8_SYSCFG: |
3afb1121 PB |
2311 | case MSR_K8_TSEG_ADDR: |
2312 | case MSR_K8_TSEG_MASK: | |
60af2ecd | 2313 | case MSR_K7_HWCR: |
61a6bd67 | 2314 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 2315 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 2316 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 2317 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 2318 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 2319 | case MSR_IA32_PERF_CTL: |
609e36d3 | 2320 | msr_info->data = 0; |
15c4a640 | 2321 | break; |
6912ac32 WH |
2322 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
2323 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
2324 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
2325 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 2326 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
609e36d3 PB |
2327 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); |
2328 | msr_info->data = 0; | |
5753785f | 2329 | break; |
742bc670 | 2330 | case MSR_IA32_UCODE_REV: |
609e36d3 | 2331 | msr_info->data = 0x100000000ULL; |
742bc670 | 2332 | break; |
9ba075a6 | 2333 | case MSR_MTRRcap: |
9ba075a6 | 2334 | case 0x200 ... 0x2ff: |
ff53604b | 2335 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 2336 | case 0xcd: /* fsb frequency */ |
609e36d3 | 2337 | msr_info->data = 3; |
15c4a640 | 2338 | break; |
7b914098 JS |
2339 | /* |
2340 | * MSR_EBC_FREQUENCY_ID | |
2341 | * Conservative value valid for even the basic CPU models. | |
2342 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
2343 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
2344 | * and 266MHz for model 3, or 4. Set Core Clock | |
2345 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
2346 | * 31:24) even though these are only valid for CPU | |
2347 | * models > 2, however guests may end up dividing or | |
2348 | * multiplying by zero otherwise. | |
2349 | */ | |
2350 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 2351 | msr_info->data = 1 << 24; |
7b914098 | 2352 | break; |
15c4a640 | 2353 | case MSR_IA32_APICBASE: |
609e36d3 | 2354 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 2355 | break; |
0105d1a5 | 2356 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
609e36d3 | 2357 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
0105d1a5 | 2358 | break; |
a3e06bbe | 2359 | case MSR_IA32_TSCDEADLINE: |
609e36d3 | 2360 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 2361 | break; |
ba904635 | 2362 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 2363 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 2364 | break; |
15c4a640 | 2365 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 2366 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 2367 | break; |
64d60670 PB |
2368 | case MSR_IA32_SMBASE: |
2369 | if (!msr_info->host_initiated) | |
2370 | return 1; | |
2371 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 2372 | break; |
847f0ad8 AG |
2373 | case MSR_IA32_PERF_STATUS: |
2374 | /* TSC increment by tick */ | |
609e36d3 | 2375 | msr_info->data = 1000ULL; |
847f0ad8 | 2376 | /* CPU multiplier */ |
b0996ae4 | 2377 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 2378 | break; |
15c4a640 | 2379 | case MSR_EFER: |
609e36d3 | 2380 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 2381 | break; |
18068523 | 2382 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 2383 | case MSR_KVM_WALL_CLOCK_NEW: |
609e36d3 | 2384 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
2385 | break; |
2386 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 2387 | case MSR_KVM_SYSTEM_TIME_NEW: |
609e36d3 | 2388 | msr_info->data = vcpu->arch.time; |
18068523 | 2389 | break; |
344d9588 | 2390 | case MSR_KVM_ASYNC_PF_EN: |
609e36d3 | 2391 | msr_info->data = vcpu->arch.apf.msr_val; |
344d9588 | 2392 | break; |
c9aaa895 | 2393 | case MSR_KVM_STEAL_TIME: |
609e36d3 | 2394 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 2395 | break; |
1d92128f | 2396 | case MSR_KVM_PV_EOI_EN: |
609e36d3 | 2397 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 2398 | break; |
890ca9ae HY |
2399 | case MSR_IA32_P5_MC_ADDR: |
2400 | case MSR_IA32_P5_MC_TYPE: | |
2401 | case MSR_IA32_MCG_CAP: | |
2402 | case MSR_IA32_MCG_CTL: | |
2403 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2404 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
609e36d3 | 2405 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data); |
84e0cefa JS |
2406 | case MSR_K7_CLK_CTL: |
2407 | /* | |
2408 | * Provide expected ramp-up count for K7. All other | |
2409 | * are set to zero, indicating minimum divisors for | |
2410 | * every field. | |
2411 | * | |
2412 | * This prevents guest kernels on AMD host with CPU | |
2413 | * type 6, model 8 and higher from exploding due to | |
2414 | * the rdmsr failing. | |
2415 | */ | |
609e36d3 | 2416 | msr_info->data = 0x20000000; |
84e0cefa | 2417 | break; |
55cd8e5a | 2418 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
e7d9513b AS |
2419 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
2420 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 2421 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
e83d5887 AS |
2422 | return kvm_hv_get_msr_common(vcpu, |
2423 | msr_info->index, &msr_info->data); | |
55cd8e5a | 2424 | break; |
91c9c3ed | 2425 | case MSR_IA32_BBL_CR_CTL3: |
2426 | /* This legacy MSR exists but isn't fully documented in current | |
2427 | * silicon. It is however accessed by winxp in very narrow | |
2428 | * scenarios where it sets bit #19, itself documented as | |
2429 | * a "reserved" bit. Best effort attempt to source coherent | |
2430 | * read data here should the balance of the register be | |
2431 | * interpreted by the guest: | |
2432 | * | |
2433 | * L2 cache control register 3: 64GB range, 256KB size, | |
2434 | * enabled, latency 0x1, configured | |
2435 | */ | |
609e36d3 | 2436 | msr_info->data = 0xbe702111; |
91c9c3ed | 2437 | break; |
2b036c6b BO |
2438 | case MSR_AMD64_OSVW_ID_LENGTH: |
2439 | if (!guest_cpuid_has_osvw(vcpu)) | |
2440 | return 1; | |
609e36d3 | 2441 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
2442 | break; |
2443 | case MSR_AMD64_OSVW_STATUS: | |
2444 | if (!guest_cpuid_has_osvw(vcpu)) | |
2445 | return 1; | |
609e36d3 | 2446 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 2447 | break; |
15c4a640 | 2448 | default: |
c6702c9d | 2449 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
609e36d3 | 2450 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); |
ed85c068 | 2451 | if (!ignore_msrs) { |
609e36d3 | 2452 | vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index); |
ed85c068 AP |
2453 | return 1; |
2454 | } else { | |
609e36d3 PB |
2455 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index); |
2456 | msr_info->data = 0; | |
ed85c068 AP |
2457 | } |
2458 | break; | |
15c4a640 | 2459 | } |
15c4a640 CO |
2460 | return 0; |
2461 | } | |
2462 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
2463 | ||
313a3dc7 CO |
2464 | /* |
2465 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
2466 | * | |
2467 | * @return number of msrs set successfully. | |
2468 | */ | |
2469 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
2470 | struct kvm_msr_entry *entries, | |
2471 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2472 | unsigned index, u64 *data)) | |
2473 | { | |
f656ce01 | 2474 | int i, idx; |
313a3dc7 | 2475 | |
f656ce01 | 2476 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
2477 | for (i = 0; i < msrs->nmsrs; ++i) |
2478 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
2479 | break; | |
f656ce01 | 2480 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 2481 | |
313a3dc7 CO |
2482 | return i; |
2483 | } | |
2484 | ||
2485 | /* | |
2486 | * Read or write a bunch of msrs. Parameters are user addresses. | |
2487 | * | |
2488 | * @return number of msrs set successfully. | |
2489 | */ | |
2490 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
2491 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2492 | unsigned index, u64 *data), | |
2493 | int writeback) | |
2494 | { | |
2495 | struct kvm_msrs msrs; | |
2496 | struct kvm_msr_entry *entries; | |
2497 | int r, n; | |
2498 | unsigned size; | |
2499 | ||
2500 | r = -EFAULT; | |
2501 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
2502 | goto out; | |
2503 | ||
2504 | r = -E2BIG; | |
2505 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
2506 | goto out; | |
2507 | ||
313a3dc7 | 2508 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
2509 | entries = memdup_user(user_msrs->entries, size); |
2510 | if (IS_ERR(entries)) { | |
2511 | r = PTR_ERR(entries); | |
313a3dc7 | 2512 | goto out; |
ff5c2c03 | 2513 | } |
313a3dc7 CO |
2514 | |
2515 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
2516 | if (r < 0) | |
2517 | goto out_free; | |
2518 | ||
2519 | r = -EFAULT; | |
2520 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
2521 | goto out_free; | |
2522 | ||
2523 | r = n; | |
2524 | ||
2525 | out_free: | |
7a73c028 | 2526 | kfree(entries); |
313a3dc7 CO |
2527 | out: |
2528 | return r; | |
2529 | } | |
2530 | ||
784aa3d7 | 2531 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 ZX |
2532 | { |
2533 | int r; | |
2534 | ||
2535 | switch (ext) { | |
2536 | case KVM_CAP_IRQCHIP: | |
2537 | case KVM_CAP_HLT: | |
2538 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 2539 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 2540 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 2541 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 2542 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 2543 | case KVM_CAP_PIT: |
a28e4f5a | 2544 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 2545 | case KVM_CAP_MP_STATE: |
ed848624 | 2546 | case KVM_CAP_SYNC_MMU: |
a355c85c | 2547 | case KVM_CAP_USER_NMI: |
52d939a0 | 2548 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 2549 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 2550 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 2551 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 2552 | case KVM_CAP_PIT2: |
e9f42757 | 2553 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 2554 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 2555 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 2556 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 2557 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 2558 | case KVM_CAP_HYPERV: |
10388a07 | 2559 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 2560 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 2561 | case KVM_CAP_HYPERV_SYNIC: |
ab9f4ecb | 2562 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 2563 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 2564 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 2565 | case KVM_CAP_XSAVE: |
344d9588 | 2566 | case KVM_CAP_ASYNC_PF: |
92a1f12d | 2567 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 2568 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 2569 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 2570 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 2571 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 2572 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 NA |
2573 | case KVM_CAP_ENABLE_CAP_VM: |
2574 | case KVM_CAP_DISABLE_QUIRKS: | |
d71ba788 | 2575 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 2576 | case KVM_CAP_SPLIT_IRQCHIP: |
2a5bab10 AW |
2577 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
2578 | case KVM_CAP_ASSIGN_DEV_IRQ: | |
2579 | case KVM_CAP_PCI_2_3: | |
2580 | #endif | |
018d00d2 ZX |
2581 | r = 1; |
2582 | break; | |
6d396b55 PB |
2583 | case KVM_CAP_X86_SMM: |
2584 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
2585 | * and SMM handlers might indeed rely on 4G segment limits, | |
2586 | * so do not report SMM to be available if real mode is | |
2587 | * emulated via vm86 mode. Still, do not go to great lengths | |
2588 | * to avoid userspace's usage of the feature, because it is a | |
2589 | * fringe case that is not enabled except via specific settings | |
2590 | * of the module parameters. | |
2591 | */ | |
2592 | r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); | |
2593 | break; | |
542472b5 LV |
2594 | case KVM_CAP_COALESCED_MMIO: |
2595 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
2596 | break; | |
774ead3a AK |
2597 | case KVM_CAP_VAPIC: |
2598 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
2599 | break; | |
f725230a | 2600 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
2601 | r = KVM_SOFT_MAX_VCPUS; |
2602 | break; | |
2603 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
2604 | r = KVM_MAX_VCPUS; |
2605 | break; | |
a988b910 | 2606 | case KVM_CAP_NR_MEMSLOTS: |
bbacc0c1 | 2607 | r = KVM_USER_MEM_SLOTS; |
a988b910 | 2608 | break; |
a68a6a72 MT |
2609 | case KVM_CAP_PV_MMU: /* obsolete */ |
2610 | r = 0; | |
2f333bcb | 2611 | break; |
4cee4b72 | 2612 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
62c476c7 | 2613 | case KVM_CAP_IOMMU: |
a1b60c1c | 2614 | r = iommu_present(&pci_bus_type); |
62c476c7 | 2615 | break; |
4cee4b72 | 2616 | #endif |
890ca9ae HY |
2617 | case KVM_CAP_MCE: |
2618 | r = KVM_MAX_MCE_BANKS; | |
2619 | break; | |
2d5b5a66 | 2620 | case KVM_CAP_XCRS: |
d366bf7e | 2621 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 2622 | break; |
92a1f12d JR |
2623 | case KVM_CAP_TSC_CONTROL: |
2624 | r = kvm_has_tsc_control; | |
2625 | break; | |
018d00d2 ZX |
2626 | default: |
2627 | r = 0; | |
2628 | break; | |
2629 | } | |
2630 | return r; | |
2631 | ||
2632 | } | |
2633 | ||
043405e1 CO |
2634 | long kvm_arch_dev_ioctl(struct file *filp, |
2635 | unsigned int ioctl, unsigned long arg) | |
2636 | { | |
2637 | void __user *argp = (void __user *)arg; | |
2638 | long r; | |
2639 | ||
2640 | switch (ioctl) { | |
2641 | case KVM_GET_MSR_INDEX_LIST: { | |
2642 | struct kvm_msr_list __user *user_msr_list = argp; | |
2643 | struct kvm_msr_list msr_list; | |
2644 | unsigned n; | |
2645 | ||
2646 | r = -EFAULT; | |
2647 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2648 | goto out; | |
2649 | n = msr_list.nmsrs; | |
62ef68bb | 2650 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
043405e1 CO |
2651 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) |
2652 | goto out; | |
2653 | r = -E2BIG; | |
e125e7b6 | 2654 | if (n < msr_list.nmsrs) |
043405e1 CO |
2655 | goto out; |
2656 | r = -EFAULT; | |
2657 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2658 | num_msrs_to_save * sizeof(u32))) | |
2659 | goto out; | |
e125e7b6 | 2660 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 2661 | &emulated_msrs, |
62ef68bb | 2662 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
2663 | goto out; |
2664 | r = 0; | |
2665 | break; | |
2666 | } | |
9c15bb1d BP |
2667 | case KVM_GET_SUPPORTED_CPUID: |
2668 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
2669 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
2670 | struct kvm_cpuid2 cpuid; | |
2671 | ||
2672 | r = -EFAULT; | |
2673 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2674 | goto out; | |
9c15bb1d BP |
2675 | |
2676 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
2677 | ioctl); | |
674eea0f AK |
2678 | if (r) |
2679 | goto out; | |
2680 | ||
2681 | r = -EFAULT; | |
2682 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2683 | goto out; | |
2684 | r = 0; | |
2685 | break; | |
2686 | } | |
890ca9ae HY |
2687 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
2688 | u64 mce_cap; | |
2689 | ||
2690 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
2691 | r = -EFAULT; | |
2692 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
2693 | goto out; | |
2694 | r = 0; | |
2695 | break; | |
2696 | } | |
043405e1 CO |
2697 | default: |
2698 | r = -EINVAL; | |
2699 | } | |
2700 | out: | |
2701 | return r; | |
2702 | } | |
2703 | ||
f5f48ee1 SY |
2704 | static void wbinvd_ipi(void *garbage) |
2705 | { | |
2706 | wbinvd(); | |
2707 | } | |
2708 | ||
2709 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
2710 | { | |
e0f0bbc5 | 2711 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
2712 | } |
2713 | ||
2860c4b1 PB |
2714 | static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu) |
2715 | { | |
2716 | set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests); | |
2717 | } | |
2718 | ||
313a3dc7 CO |
2719 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
2720 | { | |
f5f48ee1 SY |
2721 | /* Address WBINVD may be executed by guest */ |
2722 | if (need_emulate_wbinvd(vcpu)) { | |
2723 | if (kvm_x86_ops->has_wbinvd_exit()) | |
2724 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
2725 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
2726 | smp_call_function_single(vcpu->cpu, | |
2727 | wbinvd_ipi, NULL, 1); | |
2728 | } | |
2729 | ||
313a3dc7 | 2730 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
8f6055cb | 2731 | |
0dd6a6ed ZA |
2732 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
2733 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
2734 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
2735 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 2736 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 2737 | } |
8f6055cb | 2738 | |
48434c20 | 2739 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { |
6f526ec5 | 2740 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 2741 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
2742 | if (tsc_delta < 0) |
2743 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a YJ |
2744 | |
2745 | if (kvm_lapic_hv_timer_in_use(vcpu) && | |
2746 | kvm_x86_ops->set_hv_timer(vcpu, | |
2747 | kvm_get_lapic_tscdeadline_msr(vcpu))) | |
2748 | kvm_lapic_switch_to_sw_timer(vcpu); | |
c285545f | 2749 | if (check_tsc_unstable()) { |
07c1419a | 2750 | u64 offset = kvm_compute_tsc_offset(vcpu, |
b183aa58 ZA |
2751 | vcpu->arch.last_guest_tsc); |
2752 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
c285545f | 2753 | vcpu->arch.tsc_catchup = 1; |
c285545f | 2754 | } |
d98d07ca MT |
2755 | /* |
2756 | * On a host with synchronized TSC, there is no need to update | |
2757 | * kvmclock on vcpu->cpu migration | |
2758 | */ | |
2759 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 2760 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f ZA |
2761 | if (vcpu->cpu != cpu) |
2762 | kvm_migrate_timers(vcpu); | |
e48672fa | 2763 | vcpu->cpu = cpu; |
6b7d7e76 | 2764 | } |
c9aaa895 | 2765 | |
c9aaa895 | 2766 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
2767 | } |
2768 | ||
2769 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
2770 | { | |
02daab21 | 2771 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 2772 | kvm_put_guest_fpu(vcpu); |
4ea1636b | 2773 | vcpu->arch.last_host_tsc = rdtsc(); |
313a3dc7 CO |
2774 | } |
2775 | ||
313a3dc7 CO |
2776 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
2777 | struct kvm_lapic_state *s) | |
2778 | { | |
d62caabb AS |
2779 | if (vcpu->arch.apicv_active) |
2780 | kvm_x86_ops->sync_pir_to_irr(vcpu); | |
2781 | ||
ad312c7c | 2782 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
2783 | |
2784 | return 0; | |
2785 | } | |
2786 | ||
2787 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2788 | struct kvm_lapic_state *s) | |
2789 | { | |
64eb0620 | 2790 | kvm_apic_post_state_restore(vcpu, s); |
cb142eb7 | 2791 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2792 | |
2793 | return 0; | |
2794 | } | |
2795 | ||
127a457a MG |
2796 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
2797 | { | |
2798 | return (!lapic_in_kernel(vcpu) || | |
2799 | kvm_apic_accept_pic_intr(vcpu)); | |
2800 | } | |
2801 | ||
782d422b MG |
2802 | /* |
2803 | * if userspace requested an interrupt window, check that the | |
2804 | * interrupt window is open. | |
2805 | * | |
2806 | * No need to exit to userspace if we already have an interrupt queued. | |
2807 | */ | |
2808 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) | |
2809 | { | |
2810 | return kvm_arch_interrupt_allowed(vcpu) && | |
2811 | !kvm_cpu_has_interrupt(vcpu) && | |
2812 | !kvm_event_needs_reinjection(vcpu) && | |
2813 | kvm_cpu_accept_dm_intr(vcpu); | |
2814 | } | |
2815 | ||
f77bc6a4 ZX |
2816 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
2817 | struct kvm_interrupt *irq) | |
2818 | { | |
02cdb50f | 2819 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 2820 | return -EINVAL; |
1c1a9ce9 SR |
2821 | |
2822 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
2823 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
2824 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
2825 | return 0; | |
2826 | } | |
2827 | ||
2828 | /* | |
2829 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
2830 | * fail for in-kernel 8259. | |
2831 | */ | |
2832 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 2833 | return -ENXIO; |
f77bc6a4 | 2834 | |
1c1a9ce9 SR |
2835 | if (vcpu->arch.pending_external_vector != -1) |
2836 | return -EEXIST; | |
f77bc6a4 | 2837 | |
1c1a9ce9 | 2838 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 2839 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
2840 | return 0; |
2841 | } | |
2842 | ||
c4abb7c9 JK |
2843 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
2844 | { | |
c4abb7c9 | 2845 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
2846 | |
2847 | return 0; | |
2848 | } | |
2849 | ||
f077825a PB |
2850 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
2851 | { | |
64d60670 PB |
2852 | kvm_make_request(KVM_REQ_SMI, vcpu); |
2853 | ||
f077825a PB |
2854 | return 0; |
2855 | } | |
2856 | ||
b209749f AK |
2857 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
2858 | struct kvm_tpr_access_ctl *tac) | |
2859 | { | |
2860 | if (tac->flags) | |
2861 | return -EINVAL; | |
2862 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2863 | return 0; | |
2864 | } | |
2865 | ||
890ca9ae HY |
2866 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
2867 | u64 mcg_cap) | |
2868 | { | |
2869 | int r; | |
2870 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2871 | ||
2872 | r = -EINVAL; | |
a9e38c3e | 2873 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
2874 | goto out; |
2875 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2876 | goto out; | |
2877 | r = 0; | |
2878 | vcpu->arch.mcg_cap = mcg_cap; | |
2879 | /* Init IA32_MCG_CTL to all 1s */ | |
2880 | if (mcg_cap & MCG_CTL_P) | |
2881 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2882 | /* Init IA32_MCi_CTL to all 1s */ | |
2883 | for (bank = 0; bank < bank_num; bank++) | |
2884 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2885 | out: | |
2886 | return r; | |
2887 | } | |
2888 | ||
2889 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2890 | struct kvm_x86_mce *mce) | |
2891 | { | |
2892 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2893 | unsigned bank_num = mcg_cap & 0xff; | |
2894 | u64 *banks = vcpu->arch.mce_banks; | |
2895 | ||
2896 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
2897 | return -EINVAL; | |
2898 | /* | |
2899 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
2900 | * reporting is disabled | |
2901 | */ | |
2902 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
2903 | vcpu->arch.mcg_ctl != ~(u64)0) | |
2904 | return 0; | |
2905 | banks += 4 * mce->bank; | |
2906 | /* | |
2907 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
2908 | * reporting is disabled for the bank | |
2909 | */ | |
2910 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
2911 | return 0; | |
2912 | if (mce->status & MCI_STATUS_UC) { | |
2913 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 2914 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 2915 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
2916 | return 0; |
2917 | } | |
2918 | if (banks[1] & MCI_STATUS_VAL) | |
2919 | mce->status |= MCI_STATUS_OVER; | |
2920 | banks[2] = mce->addr; | |
2921 | banks[3] = mce->misc; | |
2922 | vcpu->arch.mcg_status = mce->mcg_status; | |
2923 | banks[1] = mce->status; | |
2924 | kvm_queue_exception(vcpu, MC_VECTOR); | |
2925 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
2926 | || !(banks[1] & MCI_STATUS_UC)) { | |
2927 | if (banks[1] & MCI_STATUS_VAL) | |
2928 | mce->status |= MCI_STATUS_OVER; | |
2929 | banks[2] = mce->addr; | |
2930 | banks[3] = mce->misc; | |
2931 | banks[1] = mce->status; | |
2932 | } else | |
2933 | banks[1] |= MCI_STATUS_OVER; | |
2934 | return 0; | |
2935 | } | |
2936 | ||
3cfc3092 JK |
2937 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
2938 | struct kvm_vcpu_events *events) | |
2939 | { | |
7460fb4a | 2940 | process_nmi(vcpu); |
03b82a30 JK |
2941 | events->exception.injected = |
2942 | vcpu->arch.exception.pending && | |
2943 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
2944 | events->exception.nr = vcpu->arch.exception.nr; |
2945 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
97e69aa6 | 2946 | events->exception.pad = 0; |
3cfc3092 JK |
2947 | events->exception.error_code = vcpu->arch.exception.error_code; |
2948 | ||
03b82a30 JK |
2949 | events->interrupt.injected = |
2950 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 2951 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 2952 | events->interrupt.soft = 0; |
37ccdcbe | 2953 | events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
3cfc3092 JK |
2954 | |
2955 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 2956 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
3cfc3092 | 2957 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); |
97e69aa6 | 2958 | events->nmi.pad = 0; |
3cfc3092 | 2959 | |
66450a21 | 2960 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 2961 | |
f077825a PB |
2962 | events->smi.smm = is_smm(vcpu); |
2963 | events->smi.pending = vcpu->arch.smi_pending; | |
2964 | events->smi.smm_inside_nmi = | |
2965 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
2966 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
2967 | ||
dab4b911 | 2968 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
2969 | | KVM_VCPUEVENT_VALID_SHADOW |
2970 | | KVM_VCPUEVENT_VALID_SMM); | |
97e69aa6 | 2971 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
2972 | } |
2973 | ||
2974 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
2975 | struct kvm_vcpu_events *events) | |
2976 | { | |
dab4b911 | 2977 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 2978 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a PB |
2979 | | KVM_VCPUEVENT_VALID_SHADOW |
2980 | | KVM_VCPUEVENT_VALID_SMM)) | |
3cfc3092 JK |
2981 | return -EINVAL; |
2982 | ||
78e546c8 PB |
2983 | if (events->exception.injected && |
2984 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
2985 | return -EINVAL; | |
2986 | ||
7460fb4a | 2987 | process_nmi(vcpu); |
3cfc3092 JK |
2988 | vcpu->arch.exception.pending = events->exception.injected; |
2989 | vcpu->arch.exception.nr = events->exception.nr; | |
2990 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
2991 | vcpu->arch.exception.error_code = events->exception.error_code; | |
2992 | ||
2993 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
2994 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
2995 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
2996 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
2997 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
2998 | events->interrupt.shadow); | |
3cfc3092 JK |
2999 | |
3000 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
3001 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
3002 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
3003 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
3004 | ||
66450a21 | 3005 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 3006 | lapic_in_kernel(vcpu)) |
66450a21 | 3007 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 3008 | |
f077825a PB |
3009 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
3010 | if (events->smi.smm) | |
3011 | vcpu->arch.hflags |= HF_SMM_MASK; | |
3012 | else | |
3013 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
3014 | vcpu->arch.smi_pending = events->smi.pending; | |
3015 | if (events->smi.smm_inside_nmi) | |
3016 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
3017 | else | |
3018 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; | |
bce87cce | 3019 | if (lapic_in_kernel(vcpu)) { |
f077825a PB |
3020 | if (events->smi.latched_init) |
3021 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
3022 | else | |
3023 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
3024 | } | |
3025 | } | |
3026 | ||
3842d135 AK |
3027 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3028 | ||
3cfc3092 JK |
3029 | return 0; |
3030 | } | |
3031 | ||
a1efbe77 JK |
3032 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
3033 | struct kvm_debugregs *dbgregs) | |
3034 | { | |
73aaf249 JK |
3035 | unsigned long val; |
3036 | ||
a1efbe77 | 3037 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 3038 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 3039 | dbgregs->dr6 = val; |
a1efbe77 JK |
3040 | dbgregs->dr7 = vcpu->arch.dr7; |
3041 | dbgregs->flags = 0; | |
97e69aa6 | 3042 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
3043 | } |
3044 | ||
3045 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
3046 | struct kvm_debugregs *dbgregs) | |
3047 | { | |
3048 | if (dbgregs->flags) | |
3049 | return -EINVAL; | |
3050 | ||
d14bdb55 PB |
3051 | if (dbgregs->dr6 & ~0xffffffffull) |
3052 | return -EINVAL; | |
3053 | if (dbgregs->dr7 & ~0xffffffffull) | |
3054 | return -EINVAL; | |
3055 | ||
a1efbe77 | 3056 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 3057 | kvm_update_dr0123(vcpu); |
a1efbe77 | 3058 | vcpu->arch.dr6 = dbgregs->dr6; |
73aaf249 | 3059 | kvm_update_dr6(vcpu); |
a1efbe77 | 3060 | vcpu->arch.dr7 = dbgregs->dr7; |
9926c9fd | 3061 | kvm_update_dr7(vcpu); |
a1efbe77 | 3062 | |
a1efbe77 JK |
3063 | return 0; |
3064 | } | |
3065 | ||
df1daba7 PB |
3066 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
3067 | ||
3068 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
3069 | { | |
c47ada30 | 3070 | struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; |
400e4b20 | 3071 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
3072 | u64 valid; |
3073 | ||
3074 | /* | |
3075 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3076 | * leaves 0 and 1 in the loop below. | |
3077 | */ | |
3078 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
3079 | ||
3080 | /* Set XSTATE_BV */ | |
3081 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; | |
3082 | ||
3083 | /* | |
3084 | * Copy each region from the possibly compacted offset to the | |
3085 | * non-compacted offset. | |
3086 | */ | |
d91cab78 | 3087 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 PB |
3088 | while (valid) { |
3089 | u64 feature = valid & -valid; | |
3090 | int index = fls64(feature) - 1; | |
3091 | void *src = get_xsave_addr(xsave, feature); | |
3092 | ||
3093 | if (src) { | |
3094 | u32 size, offset, ecx, edx; | |
3095 | cpuid_count(XSTATE_CPUID, index, | |
3096 | &size, &offset, &ecx, &edx); | |
3097 | memcpy(dest + offset, src, size); | |
3098 | } | |
3099 | ||
3100 | valid -= feature; | |
3101 | } | |
3102 | } | |
3103 | ||
3104 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
3105 | { | |
c47ada30 | 3106 | struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; |
df1daba7 PB |
3107 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
3108 | u64 valid; | |
3109 | ||
3110 | /* | |
3111 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3112 | * leaves 0 and 1 in the loop below. | |
3113 | */ | |
3114 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
3115 | ||
3116 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 3117 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 3118 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 3119 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
3120 | |
3121 | /* | |
3122 | * Copy each region from the non-compacted offset to the | |
3123 | * possibly compacted offset. | |
3124 | */ | |
d91cab78 | 3125 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 PB |
3126 | while (valid) { |
3127 | u64 feature = valid & -valid; | |
3128 | int index = fls64(feature) - 1; | |
3129 | void *dest = get_xsave_addr(xsave, feature); | |
3130 | ||
3131 | if (dest) { | |
3132 | u32 size, offset, ecx, edx; | |
3133 | cpuid_count(XSTATE_CPUID, index, | |
3134 | &size, &offset, &ecx, &edx); | |
3135 | memcpy(dest, src + offset, size); | |
ee4100da | 3136 | } |
df1daba7 PB |
3137 | |
3138 | valid -= feature; | |
3139 | } | |
3140 | } | |
3141 | ||
2d5b5a66 SY |
3142 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
3143 | struct kvm_xsave *guest_xsave) | |
3144 | { | |
d366bf7e | 3145 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
3146 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
3147 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 3148 | } else { |
2d5b5a66 | 3149 | memcpy(guest_xsave->region, |
7366ed77 | 3150 | &vcpu->arch.guest_fpu.state.fxsave, |
c47ada30 | 3151 | sizeof(struct fxregs_state)); |
2d5b5a66 | 3152 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 3153 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
3154 | } |
3155 | } | |
3156 | ||
3157 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
3158 | struct kvm_xsave *guest_xsave) | |
3159 | { | |
3160 | u64 xstate_bv = | |
3161 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
3162 | ||
d366bf7e | 3163 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
3164 | /* |
3165 | * Here we allow setting states that are not present in | |
3166 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
3167 | * with old userspace. | |
3168 | */ | |
4ff41732 | 3169 | if (xstate_bv & ~kvm_supported_xcr0()) |
d7876f1b | 3170 | return -EINVAL; |
df1daba7 | 3171 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 3172 | } else { |
d91cab78 | 3173 | if (xstate_bv & ~XFEATURE_MASK_FPSSE) |
2d5b5a66 | 3174 | return -EINVAL; |
7366ed77 | 3175 | memcpy(&vcpu->arch.guest_fpu.state.fxsave, |
c47ada30 | 3176 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
3177 | } |
3178 | return 0; | |
3179 | } | |
3180 | ||
3181 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
3182 | struct kvm_xcrs *guest_xcrs) | |
3183 | { | |
d366bf7e | 3184 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
3185 | guest_xcrs->nr_xcrs = 0; |
3186 | return; | |
3187 | } | |
3188 | ||
3189 | guest_xcrs->nr_xcrs = 1; | |
3190 | guest_xcrs->flags = 0; | |
3191 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
3192 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
3193 | } | |
3194 | ||
3195 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
3196 | struct kvm_xcrs *guest_xcrs) | |
3197 | { | |
3198 | int i, r = 0; | |
3199 | ||
d366bf7e | 3200 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
3201 | return -EINVAL; |
3202 | ||
3203 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
3204 | return -EINVAL; | |
3205 | ||
3206 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
3207 | /* Only support XCR0 currently */ | |
c67a04cb | 3208 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 3209 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 3210 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
3211 | break; |
3212 | } | |
3213 | if (r) | |
3214 | r = -EINVAL; | |
3215 | return r; | |
3216 | } | |
3217 | ||
1c0b28c2 EM |
3218 | /* |
3219 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
3220 | * stopped by the hypervisor. This function will be called from the host only. | |
3221 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
3222 | * does not support pv clocks. | |
3223 | */ | |
3224 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
3225 | { | |
0b79459b | 3226 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 3227 | return -EINVAL; |
51d59c6b | 3228 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
3229 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
3230 | return 0; | |
3231 | } | |
3232 | ||
5c919412 AS |
3233 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
3234 | struct kvm_enable_cap *cap) | |
3235 | { | |
3236 | if (cap->flags) | |
3237 | return -EINVAL; | |
3238 | ||
3239 | switch (cap->cap) { | |
3240 | case KVM_CAP_HYPERV_SYNIC: | |
3241 | return kvm_hv_activate_synic(vcpu); | |
3242 | default: | |
3243 | return -EINVAL; | |
3244 | } | |
3245 | } | |
3246 | ||
313a3dc7 CO |
3247 | long kvm_arch_vcpu_ioctl(struct file *filp, |
3248 | unsigned int ioctl, unsigned long arg) | |
3249 | { | |
3250 | struct kvm_vcpu *vcpu = filp->private_data; | |
3251 | void __user *argp = (void __user *)arg; | |
3252 | int r; | |
d1ac91d8 AK |
3253 | union { |
3254 | struct kvm_lapic_state *lapic; | |
3255 | struct kvm_xsave *xsave; | |
3256 | struct kvm_xcrs *xcrs; | |
3257 | void *buffer; | |
3258 | } u; | |
3259 | ||
3260 | u.buffer = NULL; | |
313a3dc7 CO |
3261 | switch (ioctl) { |
3262 | case KVM_GET_LAPIC: { | |
2204ae3c | 3263 | r = -EINVAL; |
bce87cce | 3264 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 3265 | goto out; |
d1ac91d8 | 3266 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 3267 | |
b772ff36 | 3268 | r = -ENOMEM; |
d1ac91d8 | 3269 | if (!u.lapic) |
b772ff36 | 3270 | goto out; |
d1ac91d8 | 3271 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3272 | if (r) |
3273 | goto out; | |
3274 | r = -EFAULT; | |
d1ac91d8 | 3275 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
3276 | goto out; |
3277 | r = 0; | |
3278 | break; | |
3279 | } | |
3280 | case KVM_SET_LAPIC: { | |
2204ae3c | 3281 | r = -EINVAL; |
bce87cce | 3282 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 3283 | goto out; |
ff5c2c03 | 3284 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
18595411 GC |
3285 | if (IS_ERR(u.lapic)) |
3286 | return PTR_ERR(u.lapic); | |
ff5c2c03 | 3287 | |
d1ac91d8 | 3288 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3289 | break; |
3290 | } | |
f77bc6a4 ZX |
3291 | case KVM_INTERRUPT: { |
3292 | struct kvm_interrupt irq; | |
3293 | ||
3294 | r = -EFAULT; | |
3295 | if (copy_from_user(&irq, argp, sizeof irq)) | |
3296 | goto out; | |
3297 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
3298 | break; |
3299 | } | |
c4abb7c9 JK |
3300 | case KVM_NMI: { |
3301 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
3302 | break; |
3303 | } | |
f077825a PB |
3304 | case KVM_SMI: { |
3305 | r = kvm_vcpu_ioctl_smi(vcpu); | |
3306 | break; | |
3307 | } | |
313a3dc7 CO |
3308 | case KVM_SET_CPUID: { |
3309 | struct kvm_cpuid __user *cpuid_arg = argp; | |
3310 | struct kvm_cpuid cpuid; | |
3311 | ||
3312 | r = -EFAULT; | |
3313 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3314 | goto out; | |
3315 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
3316 | break; |
3317 | } | |
07716717 DK |
3318 | case KVM_SET_CPUID2: { |
3319 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3320 | struct kvm_cpuid2 cpuid; | |
3321 | ||
3322 | r = -EFAULT; | |
3323 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3324 | goto out; | |
3325 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 3326 | cpuid_arg->entries); |
07716717 DK |
3327 | break; |
3328 | } | |
3329 | case KVM_GET_CPUID2: { | |
3330 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3331 | struct kvm_cpuid2 cpuid; | |
3332 | ||
3333 | r = -EFAULT; | |
3334 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3335 | goto out; | |
3336 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 3337 | cpuid_arg->entries); |
07716717 DK |
3338 | if (r) |
3339 | goto out; | |
3340 | r = -EFAULT; | |
3341 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
3342 | goto out; | |
3343 | r = 0; | |
3344 | break; | |
3345 | } | |
313a3dc7 | 3346 | case KVM_GET_MSRS: |
609e36d3 | 3347 | r = msr_io(vcpu, argp, do_get_msr, 1); |
313a3dc7 CO |
3348 | break; |
3349 | case KVM_SET_MSRS: | |
3350 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
3351 | break; | |
b209749f AK |
3352 | case KVM_TPR_ACCESS_REPORTING: { |
3353 | struct kvm_tpr_access_ctl tac; | |
3354 | ||
3355 | r = -EFAULT; | |
3356 | if (copy_from_user(&tac, argp, sizeof tac)) | |
3357 | goto out; | |
3358 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
3359 | if (r) | |
3360 | goto out; | |
3361 | r = -EFAULT; | |
3362 | if (copy_to_user(argp, &tac, sizeof tac)) | |
3363 | goto out; | |
3364 | r = 0; | |
3365 | break; | |
3366 | }; | |
b93463aa AK |
3367 | case KVM_SET_VAPIC_ADDR: { |
3368 | struct kvm_vapic_addr va; | |
3369 | ||
3370 | r = -EINVAL; | |
35754c98 | 3371 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
3372 | goto out; |
3373 | r = -EFAULT; | |
3374 | if (copy_from_user(&va, argp, sizeof va)) | |
3375 | goto out; | |
fda4e2e8 | 3376 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
b93463aa AK |
3377 | break; |
3378 | } | |
890ca9ae HY |
3379 | case KVM_X86_SETUP_MCE: { |
3380 | u64 mcg_cap; | |
3381 | ||
3382 | r = -EFAULT; | |
3383 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
3384 | goto out; | |
3385 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
3386 | break; | |
3387 | } | |
3388 | case KVM_X86_SET_MCE: { | |
3389 | struct kvm_x86_mce mce; | |
3390 | ||
3391 | r = -EFAULT; | |
3392 | if (copy_from_user(&mce, argp, sizeof mce)) | |
3393 | goto out; | |
3394 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
3395 | break; | |
3396 | } | |
3cfc3092 JK |
3397 | case KVM_GET_VCPU_EVENTS: { |
3398 | struct kvm_vcpu_events events; | |
3399 | ||
3400 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
3401 | ||
3402 | r = -EFAULT; | |
3403 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
3404 | break; | |
3405 | r = 0; | |
3406 | break; | |
3407 | } | |
3408 | case KVM_SET_VCPU_EVENTS: { | |
3409 | struct kvm_vcpu_events events; | |
3410 | ||
3411 | r = -EFAULT; | |
3412 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
3413 | break; | |
3414 | ||
3415 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
3416 | break; | |
3417 | } | |
a1efbe77 JK |
3418 | case KVM_GET_DEBUGREGS: { |
3419 | struct kvm_debugregs dbgregs; | |
3420 | ||
3421 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
3422 | ||
3423 | r = -EFAULT; | |
3424 | if (copy_to_user(argp, &dbgregs, | |
3425 | sizeof(struct kvm_debugregs))) | |
3426 | break; | |
3427 | r = 0; | |
3428 | break; | |
3429 | } | |
3430 | case KVM_SET_DEBUGREGS: { | |
3431 | struct kvm_debugregs dbgregs; | |
3432 | ||
3433 | r = -EFAULT; | |
3434 | if (copy_from_user(&dbgregs, argp, | |
3435 | sizeof(struct kvm_debugregs))) | |
3436 | break; | |
3437 | ||
3438 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
3439 | break; | |
3440 | } | |
2d5b5a66 | 3441 | case KVM_GET_XSAVE: { |
d1ac91d8 | 3442 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 3443 | r = -ENOMEM; |
d1ac91d8 | 3444 | if (!u.xsave) |
2d5b5a66 SY |
3445 | break; |
3446 | ||
d1ac91d8 | 3447 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3448 | |
3449 | r = -EFAULT; | |
d1ac91d8 | 3450 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
3451 | break; |
3452 | r = 0; | |
3453 | break; | |
3454 | } | |
3455 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 3456 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
18595411 GC |
3457 | if (IS_ERR(u.xsave)) |
3458 | return PTR_ERR(u.xsave); | |
2d5b5a66 | 3459 | |
d1ac91d8 | 3460 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3461 | break; |
3462 | } | |
3463 | case KVM_GET_XCRS: { | |
d1ac91d8 | 3464 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 3465 | r = -ENOMEM; |
d1ac91d8 | 3466 | if (!u.xcrs) |
2d5b5a66 SY |
3467 | break; |
3468 | ||
d1ac91d8 | 3469 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3470 | |
3471 | r = -EFAULT; | |
d1ac91d8 | 3472 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
3473 | sizeof(struct kvm_xcrs))) |
3474 | break; | |
3475 | r = 0; | |
3476 | break; | |
3477 | } | |
3478 | case KVM_SET_XCRS: { | |
ff5c2c03 | 3479 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
18595411 GC |
3480 | if (IS_ERR(u.xcrs)) |
3481 | return PTR_ERR(u.xcrs); | |
2d5b5a66 | 3482 | |
d1ac91d8 | 3483 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3484 | break; |
3485 | } | |
92a1f12d JR |
3486 | case KVM_SET_TSC_KHZ: { |
3487 | u32 user_tsc_khz; | |
3488 | ||
3489 | r = -EINVAL; | |
92a1f12d JR |
3490 | user_tsc_khz = (u32)arg; |
3491 | ||
3492 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
3493 | goto out; | |
3494 | ||
cc578287 ZA |
3495 | if (user_tsc_khz == 0) |
3496 | user_tsc_khz = tsc_khz; | |
3497 | ||
381d585c HZ |
3498 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
3499 | r = 0; | |
92a1f12d | 3500 | |
92a1f12d JR |
3501 | goto out; |
3502 | } | |
3503 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 3504 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
3505 | goto out; |
3506 | } | |
1c0b28c2 EM |
3507 | case KVM_KVMCLOCK_CTRL: { |
3508 | r = kvm_set_guest_paused(vcpu); | |
3509 | goto out; | |
3510 | } | |
5c919412 AS |
3511 | case KVM_ENABLE_CAP: { |
3512 | struct kvm_enable_cap cap; | |
3513 | ||
3514 | r = -EFAULT; | |
3515 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
3516 | goto out; | |
3517 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
3518 | break; | |
3519 | } | |
313a3dc7 CO |
3520 | default: |
3521 | r = -EINVAL; | |
3522 | } | |
3523 | out: | |
d1ac91d8 | 3524 | kfree(u.buffer); |
313a3dc7 CO |
3525 | return r; |
3526 | } | |
3527 | ||
5b1c1493 CO |
3528 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
3529 | { | |
3530 | return VM_FAULT_SIGBUS; | |
3531 | } | |
3532 | ||
1fe779f8 CO |
3533 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
3534 | { | |
3535 | int ret; | |
3536 | ||
3537 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 3538 | return -EINVAL; |
1fe779f8 CO |
3539 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); |
3540 | return ret; | |
3541 | } | |
3542 | ||
b927a3ce SY |
3543 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
3544 | u64 ident_addr) | |
3545 | { | |
3546 | kvm->arch.ept_identity_map_addr = ident_addr; | |
3547 | return 0; | |
3548 | } | |
3549 | ||
1fe779f8 CO |
3550 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
3551 | u32 kvm_nr_mmu_pages) | |
3552 | { | |
3553 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
3554 | return -EINVAL; | |
3555 | ||
79fac95e | 3556 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
3557 | |
3558 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 3559 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 3560 | |
79fac95e | 3561 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
3562 | return 0; |
3563 | } | |
3564 | ||
3565 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
3566 | { | |
39de71ec | 3567 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
3568 | } |
3569 | ||
1fe779f8 CO |
3570 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
3571 | { | |
3572 | int r; | |
3573 | ||
3574 | r = 0; | |
3575 | switch (chip->chip_id) { | |
3576 | case KVM_IRQCHIP_PIC_MASTER: | |
3577 | memcpy(&chip->chip.pic, | |
3578 | &pic_irqchip(kvm)->pics[0], | |
3579 | sizeof(struct kvm_pic_state)); | |
3580 | break; | |
3581 | case KVM_IRQCHIP_PIC_SLAVE: | |
3582 | memcpy(&chip->chip.pic, | |
3583 | &pic_irqchip(kvm)->pics[1], | |
3584 | sizeof(struct kvm_pic_state)); | |
3585 | break; | |
3586 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3587 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3588 | break; |
3589 | default: | |
3590 | r = -EINVAL; | |
3591 | break; | |
3592 | } | |
3593 | return r; | |
3594 | } | |
3595 | ||
3596 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
3597 | { | |
3598 | int r; | |
3599 | ||
3600 | r = 0; | |
3601 | switch (chip->chip_id) { | |
3602 | case KVM_IRQCHIP_PIC_MASTER: | |
f4f51050 | 3603 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3604 | memcpy(&pic_irqchip(kvm)->pics[0], |
3605 | &chip->chip.pic, | |
3606 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3607 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3608 | break; |
3609 | case KVM_IRQCHIP_PIC_SLAVE: | |
f4f51050 | 3610 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3611 | memcpy(&pic_irqchip(kvm)->pics[1], |
3612 | &chip->chip.pic, | |
3613 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3614 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3615 | break; |
3616 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3617 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3618 | break; |
3619 | default: | |
3620 | r = -EINVAL; | |
3621 | break; | |
3622 | } | |
3623 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
3624 | return r; | |
3625 | } | |
3626 | ||
e0f63cb9 SY |
3627 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
3628 | { | |
34f3941c RK |
3629 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
3630 | ||
3631 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
3632 | ||
3633 | mutex_lock(&kps->lock); | |
3634 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
3635 | mutex_unlock(&kps->lock); | |
2da29bcc | 3636 | return 0; |
e0f63cb9 SY |
3637 | } |
3638 | ||
3639 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3640 | { | |
0185604c | 3641 | int i; |
09edea72 RK |
3642 | struct kvm_pit *pit = kvm->arch.vpit; |
3643 | ||
3644 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 3645 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 3646 | for (i = 0; i < 3; i++) |
09edea72 RK |
3647 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
3648 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 3649 | return 0; |
e9f42757 BK |
3650 | } |
3651 | ||
3652 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3653 | { | |
e9f42757 BK |
3654 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
3655 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3656 | sizeof(ps->channels)); | |
3657 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3658 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 3659 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 3660 | return 0; |
e9f42757 BK |
3661 | } |
3662 | ||
3663 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3664 | { | |
2da29bcc | 3665 | int start = 0; |
0185604c | 3666 | int i; |
e9f42757 | 3667 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
3668 | struct kvm_pit *pit = kvm->arch.vpit; |
3669 | ||
3670 | mutex_lock(&pit->pit_state.lock); | |
3671 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
3672 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
3673 | if (!prev_legacy && cur_legacy) | |
3674 | start = 1; | |
09edea72 RK |
3675 | memcpy(&pit->pit_state.channels, &ps->channels, |
3676 | sizeof(pit->pit_state.channels)); | |
3677 | pit->pit_state.flags = ps->flags; | |
0185604c | 3678 | for (i = 0; i < 3; i++) |
09edea72 | 3679 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 3680 | start && i == 0); |
09edea72 | 3681 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 3682 | return 0; |
e0f63cb9 SY |
3683 | } |
3684 | ||
52d939a0 MT |
3685 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
3686 | struct kvm_reinject_control *control) | |
3687 | { | |
71474e2f RK |
3688 | struct kvm_pit *pit = kvm->arch.vpit; |
3689 | ||
3690 | if (!pit) | |
52d939a0 | 3691 | return -ENXIO; |
b39c90b6 | 3692 | |
71474e2f RK |
3693 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
3694 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
3695 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
3696 | */ | |
3697 | mutex_lock(&pit->pit_state.lock); | |
3698 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
3699 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 3700 | |
52d939a0 MT |
3701 | return 0; |
3702 | } | |
3703 | ||
95d4c16c | 3704 | /** |
60c34612 TY |
3705 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot |
3706 | * @kvm: kvm instance | |
3707 | * @log: slot id and address to which we copy the log | |
95d4c16c | 3708 | * |
e108ff2f PB |
3709 | * Steps 1-4 below provide general overview of dirty page logging. See |
3710 | * kvm_get_dirty_log_protect() function description for additional details. | |
3711 | * | |
3712 | * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we | |
3713 | * always flush the TLB (step 4) even if previous step failed and the dirty | |
3714 | * bitmap may be corrupt. Regardless of previous outcome the KVM logging API | |
3715 | * does not preclude user space subsequent dirty log read. Flushing TLB ensures | |
3716 | * writes will be marked dirty for next log read. | |
95d4c16c | 3717 | * |
60c34612 TY |
3718 | * 1. Take a snapshot of the bit and clear it if needed. |
3719 | * 2. Write protect the corresponding page. | |
e108ff2f PB |
3720 | * 3. Copy the snapshot to the userspace. |
3721 | * 4. Flush TLB's if needed. | |
5bb064dc | 3722 | */ |
60c34612 | 3723 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
5bb064dc | 3724 | { |
60c34612 | 3725 | bool is_dirty = false; |
e108ff2f | 3726 | int r; |
5bb064dc | 3727 | |
79fac95e | 3728 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 3729 | |
88178fd4 KH |
3730 | /* |
3731 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
3732 | */ | |
3733 | if (kvm_x86_ops->flush_log_dirty) | |
3734 | kvm_x86_ops->flush_log_dirty(kvm); | |
3735 | ||
e108ff2f | 3736 | r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); |
198c74f4 XG |
3737 | |
3738 | /* | |
3739 | * All the TLBs can be flushed out of mmu lock, see the comments in | |
3740 | * kvm_mmu_slot_remove_write_access(). | |
3741 | */ | |
e108ff2f | 3742 | lockdep_assert_held(&kvm->slots_lock); |
198c74f4 XG |
3743 | if (is_dirty) |
3744 | kvm_flush_remote_tlbs(kvm); | |
3745 | ||
79fac95e | 3746 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
3747 | return r; |
3748 | } | |
3749 | ||
aa2fbe6d YZ |
3750 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
3751 | bool line_status) | |
23d43cf9 CD |
3752 | { |
3753 | if (!irqchip_in_kernel(kvm)) | |
3754 | return -ENXIO; | |
3755 | ||
3756 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
3757 | irq_event->irq, irq_event->level, |
3758 | line_status); | |
23d43cf9 CD |
3759 | return 0; |
3760 | } | |
3761 | ||
90de4a18 NA |
3762 | static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
3763 | struct kvm_enable_cap *cap) | |
3764 | { | |
3765 | int r; | |
3766 | ||
3767 | if (cap->flags) | |
3768 | return -EINVAL; | |
3769 | ||
3770 | switch (cap->cap) { | |
3771 | case KVM_CAP_DISABLE_QUIRKS: | |
3772 | kvm->arch.disabled_quirks = cap->args[0]; | |
3773 | r = 0; | |
3774 | break; | |
49df6397 SR |
3775 | case KVM_CAP_SPLIT_IRQCHIP: { |
3776 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
3777 | r = -EINVAL; |
3778 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
3779 | goto split_irqchip_unlock; | |
49df6397 SR |
3780 | r = -EEXIST; |
3781 | if (irqchip_in_kernel(kvm)) | |
3782 | goto split_irqchip_unlock; | |
557abc40 | 3783 | if (kvm->created_vcpus) |
49df6397 SR |
3784 | goto split_irqchip_unlock; |
3785 | r = kvm_setup_empty_irq_routing(kvm); | |
3786 | if (r) | |
3787 | goto split_irqchip_unlock; | |
3788 | /* Pairs with irqchip_in_kernel. */ | |
3789 | smp_wmb(); | |
3790 | kvm->arch.irqchip_split = true; | |
b053b2ae | 3791 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
3792 | r = 0; |
3793 | split_irqchip_unlock: | |
3794 | mutex_unlock(&kvm->lock); | |
3795 | break; | |
3796 | } | |
90de4a18 NA |
3797 | default: |
3798 | r = -EINVAL; | |
3799 | break; | |
3800 | } | |
3801 | return r; | |
3802 | } | |
3803 | ||
1fe779f8 CO |
3804 | long kvm_arch_vm_ioctl(struct file *filp, |
3805 | unsigned int ioctl, unsigned long arg) | |
3806 | { | |
3807 | struct kvm *kvm = filp->private_data; | |
3808 | void __user *argp = (void __user *)arg; | |
367e1319 | 3809 | int r = -ENOTTY; |
f0d66275 DH |
3810 | /* |
3811 | * This union makes it completely explicit to gcc-3.x | |
3812 | * that these two variables' stack usage should be | |
3813 | * combined, not added together. | |
3814 | */ | |
3815 | union { | |
3816 | struct kvm_pit_state ps; | |
e9f42757 | 3817 | struct kvm_pit_state2 ps2; |
c5ff41ce | 3818 | struct kvm_pit_config pit_config; |
f0d66275 | 3819 | } u; |
1fe779f8 CO |
3820 | |
3821 | switch (ioctl) { | |
3822 | case KVM_SET_TSS_ADDR: | |
3823 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 3824 | break; |
b927a3ce SY |
3825 | case KVM_SET_IDENTITY_MAP_ADDR: { |
3826 | u64 ident_addr; | |
3827 | ||
3828 | r = -EFAULT; | |
3829 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
3830 | goto out; | |
3831 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
b927a3ce SY |
3832 | break; |
3833 | } | |
1fe779f8 CO |
3834 | case KVM_SET_NR_MMU_PAGES: |
3835 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
3836 | break; |
3837 | case KVM_GET_NR_MMU_PAGES: | |
3838 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
3839 | break; | |
3ddea128 MT |
3840 | case KVM_CREATE_IRQCHIP: { |
3841 | struct kvm_pic *vpic; | |
3842 | ||
3843 | mutex_lock(&kvm->lock); | |
3844 | r = -EEXIST; | |
3845 | if (kvm->arch.vpic) | |
3846 | goto create_irqchip_unlock; | |
3e515705 | 3847 | r = -EINVAL; |
557abc40 | 3848 | if (kvm->created_vcpus) |
3e515705 | 3849 | goto create_irqchip_unlock; |
1fe779f8 | 3850 | r = -ENOMEM; |
3ddea128 MT |
3851 | vpic = kvm_create_pic(kvm); |
3852 | if (vpic) { | |
1fe779f8 CO |
3853 | r = kvm_ioapic_init(kvm); |
3854 | if (r) { | |
175504cd | 3855 | mutex_lock(&kvm->slots_lock); |
71ba994c | 3856 | kvm_destroy_pic(vpic); |
175504cd | 3857 | mutex_unlock(&kvm->slots_lock); |
3ddea128 | 3858 | goto create_irqchip_unlock; |
1fe779f8 CO |
3859 | } |
3860 | } else | |
3ddea128 | 3861 | goto create_irqchip_unlock; |
399ec807 AK |
3862 | r = kvm_setup_default_irq_routing(kvm); |
3863 | if (r) { | |
175504cd | 3864 | mutex_lock(&kvm->slots_lock); |
3ddea128 | 3865 | mutex_lock(&kvm->irq_lock); |
72bb2fcd | 3866 | kvm_ioapic_destroy(kvm); |
71ba994c | 3867 | kvm_destroy_pic(vpic); |
3ddea128 | 3868 | mutex_unlock(&kvm->irq_lock); |
175504cd | 3869 | mutex_unlock(&kvm->slots_lock); |
71ba994c | 3870 | goto create_irqchip_unlock; |
399ec807 | 3871 | } |
71ba994c PB |
3872 | /* Write kvm->irq_routing before kvm->arch.vpic. */ |
3873 | smp_wmb(); | |
3874 | kvm->arch.vpic = vpic; | |
3ddea128 MT |
3875 | create_irqchip_unlock: |
3876 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 3877 | break; |
3ddea128 | 3878 | } |
7837699f | 3879 | case KVM_CREATE_PIT: |
c5ff41ce JK |
3880 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
3881 | goto create_pit; | |
3882 | case KVM_CREATE_PIT2: | |
3883 | r = -EFAULT; | |
3884 | if (copy_from_user(&u.pit_config, argp, | |
3885 | sizeof(struct kvm_pit_config))) | |
3886 | goto out; | |
3887 | create_pit: | |
250715a6 | 3888 | mutex_lock(&kvm->lock); |
269e05e4 AK |
3889 | r = -EEXIST; |
3890 | if (kvm->arch.vpit) | |
3891 | goto create_pit_unlock; | |
7837699f | 3892 | r = -ENOMEM; |
c5ff41ce | 3893 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
3894 | if (kvm->arch.vpit) |
3895 | r = 0; | |
269e05e4 | 3896 | create_pit_unlock: |
250715a6 | 3897 | mutex_unlock(&kvm->lock); |
7837699f | 3898 | break; |
1fe779f8 CO |
3899 | case KVM_GET_IRQCHIP: { |
3900 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3901 | struct kvm_irqchip *chip; |
1fe779f8 | 3902 | |
ff5c2c03 SL |
3903 | chip = memdup_user(argp, sizeof(*chip)); |
3904 | if (IS_ERR(chip)) { | |
3905 | r = PTR_ERR(chip); | |
1fe779f8 | 3906 | goto out; |
ff5c2c03 SL |
3907 | } |
3908 | ||
1fe779f8 | 3909 | r = -ENXIO; |
49df6397 | 3910 | if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) |
f0d66275 DH |
3911 | goto get_irqchip_out; |
3912 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 3913 | if (r) |
f0d66275 | 3914 | goto get_irqchip_out; |
1fe779f8 | 3915 | r = -EFAULT; |
f0d66275 DH |
3916 | if (copy_to_user(argp, chip, sizeof *chip)) |
3917 | goto get_irqchip_out; | |
1fe779f8 | 3918 | r = 0; |
f0d66275 DH |
3919 | get_irqchip_out: |
3920 | kfree(chip); | |
1fe779f8 CO |
3921 | break; |
3922 | } | |
3923 | case KVM_SET_IRQCHIP: { | |
3924 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3925 | struct kvm_irqchip *chip; |
1fe779f8 | 3926 | |
ff5c2c03 SL |
3927 | chip = memdup_user(argp, sizeof(*chip)); |
3928 | if (IS_ERR(chip)) { | |
3929 | r = PTR_ERR(chip); | |
1fe779f8 | 3930 | goto out; |
ff5c2c03 SL |
3931 | } |
3932 | ||
1fe779f8 | 3933 | r = -ENXIO; |
49df6397 | 3934 | if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) |
f0d66275 DH |
3935 | goto set_irqchip_out; |
3936 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 3937 | if (r) |
f0d66275 | 3938 | goto set_irqchip_out; |
1fe779f8 | 3939 | r = 0; |
f0d66275 DH |
3940 | set_irqchip_out: |
3941 | kfree(chip); | |
1fe779f8 CO |
3942 | break; |
3943 | } | |
e0f63cb9 | 3944 | case KVM_GET_PIT: { |
e0f63cb9 | 3945 | r = -EFAULT; |
f0d66275 | 3946 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3947 | goto out; |
3948 | r = -ENXIO; | |
3949 | if (!kvm->arch.vpit) | |
3950 | goto out; | |
f0d66275 | 3951 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
3952 | if (r) |
3953 | goto out; | |
3954 | r = -EFAULT; | |
f0d66275 | 3955 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3956 | goto out; |
3957 | r = 0; | |
3958 | break; | |
3959 | } | |
3960 | case KVM_SET_PIT: { | |
e0f63cb9 | 3961 | r = -EFAULT; |
f0d66275 | 3962 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
3963 | goto out; |
3964 | r = -ENXIO; | |
3965 | if (!kvm->arch.vpit) | |
3966 | goto out; | |
f0d66275 | 3967 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
3968 | break; |
3969 | } | |
e9f42757 BK |
3970 | case KVM_GET_PIT2: { |
3971 | r = -ENXIO; | |
3972 | if (!kvm->arch.vpit) | |
3973 | goto out; | |
3974 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
3975 | if (r) | |
3976 | goto out; | |
3977 | r = -EFAULT; | |
3978 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
3979 | goto out; | |
3980 | r = 0; | |
3981 | break; | |
3982 | } | |
3983 | case KVM_SET_PIT2: { | |
3984 | r = -EFAULT; | |
3985 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
3986 | goto out; | |
3987 | r = -ENXIO; | |
3988 | if (!kvm->arch.vpit) | |
3989 | goto out; | |
3990 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
e9f42757 BK |
3991 | break; |
3992 | } | |
52d939a0 MT |
3993 | case KVM_REINJECT_CONTROL: { |
3994 | struct kvm_reinject_control control; | |
3995 | r = -EFAULT; | |
3996 | if (copy_from_user(&control, argp, sizeof(control))) | |
3997 | goto out; | |
3998 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
52d939a0 MT |
3999 | break; |
4000 | } | |
d71ba788 PB |
4001 | case KVM_SET_BOOT_CPU_ID: |
4002 | r = 0; | |
4003 | mutex_lock(&kvm->lock); | |
557abc40 | 4004 | if (kvm->created_vcpus) |
d71ba788 PB |
4005 | r = -EBUSY; |
4006 | else | |
4007 | kvm->arch.bsp_vcpu_id = arg; | |
4008 | mutex_unlock(&kvm->lock); | |
4009 | break; | |
ffde22ac ES |
4010 | case KVM_XEN_HVM_CONFIG: { |
4011 | r = -EFAULT; | |
4012 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
4013 | sizeof(struct kvm_xen_hvm_config))) | |
4014 | goto out; | |
4015 | r = -EINVAL; | |
4016 | if (kvm->arch.xen_hvm_config.flags) | |
4017 | goto out; | |
4018 | r = 0; | |
4019 | break; | |
4020 | } | |
afbcf7ab | 4021 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
4022 | struct kvm_clock_data user_ns; |
4023 | u64 now_ns; | |
4024 | s64 delta; | |
4025 | ||
4026 | r = -EFAULT; | |
4027 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
4028 | goto out; | |
4029 | ||
4030 | r = -EINVAL; | |
4031 | if (user_ns.flags) | |
4032 | goto out; | |
4033 | ||
4034 | r = 0; | |
395c6b0a | 4035 | local_irq_disable(); |
759379dd | 4036 | now_ns = get_kernel_ns(); |
afbcf7ab | 4037 | delta = user_ns.clock - now_ns; |
395c6b0a | 4038 | local_irq_enable(); |
afbcf7ab | 4039 | kvm->arch.kvmclock_offset = delta; |
2e762ff7 | 4040 | kvm_gen_update_masterclock(kvm); |
afbcf7ab GC |
4041 | break; |
4042 | } | |
4043 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
4044 | struct kvm_clock_data user_ns; |
4045 | u64 now_ns; | |
4046 | ||
395c6b0a | 4047 | local_irq_disable(); |
759379dd | 4048 | now_ns = get_kernel_ns(); |
afbcf7ab | 4049 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; |
395c6b0a | 4050 | local_irq_enable(); |
afbcf7ab | 4051 | user_ns.flags = 0; |
97e69aa6 | 4052 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
4053 | |
4054 | r = -EFAULT; | |
4055 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
4056 | goto out; | |
4057 | r = 0; | |
4058 | break; | |
4059 | } | |
90de4a18 NA |
4060 | case KVM_ENABLE_CAP: { |
4061 | struct kvm_enable_cap cap; | |
afbcf7ab | 4062 | |
90de4a18 NA |
4063 | r = -EFAULT; |
4064 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
4065 | goto out; | |
4066 | r = kvm_vm_ioctl_enable_cap(kvm, &cap); | |
4067 | break; | |
4068 | } | |
1fe779f8 | 4069 | default: |
c274e03a | 4070 | r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); |
1fe779f8 CO |
4071 | } |
4072 | out: | |
4073 | return r; | |
4074 | } | |
4075 | ||
a16b043c | 4076 | static void kvm_init_msr_list(void) |
043405e1 CO |
4077 | { |
4078 | u32 dummy[2]; | |
4079 | unsigned i, j; | |
4080 | ||
62ef68bb | 4081 | for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { |
043405e1 CO |
4082 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
4083 | continue; | |
93c4adc7 PB |
4084 | |
4085 | /* | |
4086 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 4087 | * to the guests in some cases. |
93c4adc7 PB |
4088 | */ |
4089 | switch (msrs_to_save[i]) { | |
4090 | case MSR_IA32_BNDCFGS: | |
4091 | if (!kvm_x86_ops->mpx_supported()) | |
4092 | continue; | |
4093 | break; | |
9dbe6cf9 PB |
4094 | case MSR_TSC_AUX: |
4095 | if (!kvm_x86_ops->rdtscp_supported()) | |
4096 | continue; | |
4097 | break; | |
93c4adc7 PB |
4098 | default: |
4099 | break; | |
4100 | } | |
4101 | ||
043405e1 CO |
4102 | if (j < i) |
4103 | msrs_to_save[j] = msrs_to_save[i]; | |
4104 | j++; | |
4105 | } | |
4106 | num_msrs_to_save = j; | |
62ef68bb PB |
4107 | |
4108 | for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { | |
4109 | switch (emulated_msrs[i]) { | |
6d396b55 PB |
4110 | case MSR_IA32_SMBASE: |
4111 | if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) | |
4112 | continue; | |
4113 | break; | |
62ef68bb PB |
4114 | default: |
4115 | break; | |
4116 | } | |
4117 | ||
4118 | if (j < i) | |
4119 | emulated_msrs[j] = emulated_msrs[i]; | |
4120 | j++; | |
4121 | } | |
4122 | num_emulated_msrs = j; | |
043405e1 CO |
4123 | } |
4124 | ||
bda9020e MT |
4125 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
4126 | const void *v) | |
bbd9b64e | 4127 | { |
70252a10 AK |
4128 | int handled = 0; |
4129 | int n; | |
4130 | ||
4131 | do { | |
4132 | n = min(len, 8); | |
bce87cce | 4133 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
4134 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
4135 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
4136 | break; |
4137 | handled += n; | |
4138 | addr += n; | |
4139 | len -= n; | |
4140 | v += n; | |
4141 | } while (len); | |
bbd9b64e | 4142 | |
70252a10 | 4143 | return handled; |
bbd9b64e CO |
4144 | } |
4145 | ||
bda9020e | 4146 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 4147 | { |
70252a10 AK |
4148 | int handled = 0; |
4149 | int n; | |
4150 | ||
4151 | do { | |
4152 | n = min(len, 8); | |
bce87cce | 4153 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
4154 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
4155 | addr, n, v)) | |
4156 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
4157 | break; |
4158 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); | |
4159 | handled += n; | |
4160 | addr += n; | |
4161 | len -= n; | |
4162 | v += n; | |
4163 | } while (len); | |
bbd9b64e | 4164 | |
70252a10 | 4165 | return handled; |
bbd9b64e CO |
4166 | } |
4167 | ||
2dafc6c2 GN |
4168 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
4169 | struct kvm_segment *var, int seg) | |
4170 | { | |
4171 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
4172 | } | |
4173 | ||
4174 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
4175 | struct kvm_segment *var, int seg) | |
4176 | { | |
4177 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
4178 | } | |
4179 | ||
54987b7a PB |
4180 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
4181 | struct x86_exception *exception) | |
02f59dc9 JR |
4182 | { |
4183 | gpa_t t_gpa; | |
02f59dc9 JR |
4184 | |
4185 | BUG_ON(!mmu_is_nested(vcpu)); | |
4186 | ||
4187 | /* NPT walks are always user-walks */ | |
4188 | access |= PFERR_USER_MASK; | |
54987b7a | 4189 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
4190 | |
4191 | return t_gpa; | |
4192 | } | |
4193 | ||
ab9ae313 AK |
4194 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
4195 | struct x86_exception *exception) | |
1871c602 GN |
4196 | { |
4197 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 4198 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4199 | } |
4200 | ||
ab9ae313 AK |
4201 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
4202 | struct x86_exception *exception) | |
1871c602 GN |
4203 | { |
4204 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4205 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 4206 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4207 | } |
4208 | ||
ab9ae313 AK |
4209 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
4210 | struct x86_exception *exception) | |
1871c602 GN |
4211 | { |
4212 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4213 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 4214 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4215 | } |
4216 | ||
4217 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
4218 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
4219 | struct x86_exception *exception) | |
1871c602 | 4220 | { |
ab9ae313 | 4221 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
4222 | } |
4223 | ||
4224 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
4225 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 4226 | struct x86_exception *exception) |
bbd9b64e CO |
4227 | { |
4228 | void *data = val; | |
10589a46 | 4229 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
4230 | |
4231 | while (bytes) { | |
14dfe855 | 4232 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 4233 | exception); |
bbd9b64e | 4234 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 4235 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
4236 | int ret; |
4237 | ||
bcc55cba | 4238 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4239 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
4240 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
4241 | offset, toread); | |
10589a46 | 4242 | if (ret < 0) { |
c3cd7ffa | 4243 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
4244 | goto out; |
4245 | } | |
bbd9b64e | 4246 | |
77c2002e IE |
4247 | bytes -= toread; |
4248 | data += toread; | |
4249 | addr += toread; | |
bbd9b64e | 4250 | } |
10589a46 | 4251 | out: |
10589a46 | 4252 | return r; |
bbd9b64e | 4253 | } |
77c2002e | 4254 | |
1871c602 | 4255 | /* used for instruction fetching */ |
0f65dd70 AK |
4256 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
4257 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4258 | struct x86_exception *exception) |
1871c602 | 4259 | { |
0f65dd70 | 4260 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4261 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
4262 | unsigned offset; |
4263 | int ret; | |
0f65dd70 | 4264 | |
44583cba PB |
4265 | /* Inline kvm_read_guest_virt_helper for speed. */ |
4266 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
4267 | exception); | |
4268 | if (unlikely(gpa == UNMAPPED_GVA)) | |
4269 | return X86EMUL_PROPAGATE_FAULT; | |
4270 | ||
4271 | offset = addr & (PAGE_SIZE-1); | |
4272 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
4273 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
4274 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
4275 | offset, bytes); | |
44583cba PB |
4276 | if (unlikely(ret < 0)) |
4277 | return X86EMUL_IO_NEEDED; | |
4278 | ||
4279 | return X86EMUL_CONTINUE; | |
1871c602 GN |
4280 | } |
4281 | ||
064aea77 | 4282 | int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4283 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 4284 | struct x86_exception *exception) |
1871c602 | 4285 | { |
0f65dd70 | 4286 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4287 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 4288 | |
1871c602 | 4289 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 4290 | exception); |
1871c602 | 4291 | } |
064aea77 | 4292 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 4293 | |
0f65dd70 AK |
4294 | static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
4295 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4296 | struct x86_exception *exception) |
1871c602 | 4297 | { |
0f65dd70 | 4298 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
bcc55cba | 4299 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); |
1871c602 GN |
4300 | } |
4301 | ||
7a036a6f RK |
4302 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
4303 | unsigned long addr, void *val, unsigned int bytes) | |
4304 | { | |
4305 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4306 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
4307 | ||
4308 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
4309 | } | |
4310 | ||
6a4d7550 | 4311 | int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4312 | gva_t addr, void *val, |
2dafc6c2 | 4313 | unsigned int bytes, |
bcc55cba | 4314 | struct x86_exception *exception) |
77c2002e | 4315 | { |
0f65dd70 | 4316 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
77c2002e IE |
4317 | void *data = val; |
4318 | int r = X86EMUL_CONTINUE; | |
4319 | ||
4320 | while (bytes) { | |
14dfe855 JR |
4321 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
4322 | PFERR_WRITE_MASK, | |
ab9ae313 | 4323 | exception); |
77c2002e IE |
4324 | unsigned offset = addr & (PAGE_SIZE-1); |
4325 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
4326 | int ret; | |
4327 | ||
bcc55cba | 4328 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4329 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 4330 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 4331 | if (ret < 0) { |
c3cd7ffa | 4332 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
4333 | goto out; |
4334 | } | |
4335 | ||
4336 | bytes -= towrite; | |
4337 | data += towrite; | |
4338 | addr += towrite; | |
4339 | } | |
4340 | out: | |
4341 | return r; | |
4342 | } | |
6a4d7550 | 4343 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 4344 | |
af7cc7d1 XG |
4345 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
4346 | gpa_t *gpa, struct x86_exception *exception, | |
4347 | bool write) | |
4348 | { | |
97d64b78 AK |
4349 | u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
4350 | | (write ? PFERR_WRITE_MASK : 0); | |
af7cc7d1 | 4351 | |
be94f6b7 HH |
4352 | /* |
4353 | * currently PKRU is only applied to ept enabled guest so | |
4354 | * there is no pkey in EPT page table for L1 guest or EPT | |
4355 | * shadow page table for L2 guest. | |
4356 | */ | |
97d64b78 | 4357 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 | 4358 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
be94f6b7 | 4359 | vcpu->arch.access, 0, access)) { |
bebb106a XG |
4360 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
4361 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 4362 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
4363 | return 1; |
4364 | } | |
4365 | ||
af7cc7d1 XG |
4366 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
4367 | ||
4368 | if (*gpa == UNMAPPED_GVA) | |
4369 | return -1; | |
4370 | ||
4371 | /* For APIC access vmexit */ | |
4372 | if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4373 | return 1; | |
4374 | ||
4f022648 XG |
4375 | if (vcpu_match_mmio_gpa(vcpu, *gpa)) { |
4376 | trace_vcpu_match_mmio(gva, *gpa, write, true); | |
bebb106a | 4377 | return 1; |
4f022648 | 4378 | } |
bebb106a | 4379 | |
af7cc7d1 XG |
4380 | return 0; |
4381 | } | |
4382 | ||
3200f405 | 4383 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 4384 | const void *val, int bytes) |
bbd9b64e CO |
4385 | { |
4386 | int ret; | |
4387 | ||
54bf36aa | 4388 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 4389 | if (ret < 0) |
bbd9b64e | 4390 | return 0; |
0eb05bf2 | 4391 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
4392 | return 1; |
4393 | } | |
4394 | ||
77d197b2 XG |
4395 | struct read_write_emulator_ops { |
4396 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
4397 | int bytes); | |
4398 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4399 | void *val, int bytes); | |
4400 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4401 | int bytes, void *val); | |
4402 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4403 | void *val, int bytes); | |
4404 | bool write; | |
4405 | }; | |
4406 | ||
4407 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
4408 | { | |
4409 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 4410 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
f78146b0 | 4411 | vcpu->mmio_fragments[0].gpa, *(u64 *)val); |
77d197b2 XG |
4412 | vcpu->mmio_read_completed = 0; |
4413 | return 1; | |
4414 | } | |
4415 | ||
4416 | return 0; | |
4417 | } | |
4418 | ||
4419 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4420 | void *val, int bytes) | |
4421 | { | |
54bf36aa | 4422 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
4423 | } |
4424 | ||
4425 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4426 | void *val, int bytes) | |
4427 | { | |
4428 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
4429 | } | |
4430 | ||
4431 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
4432 | { | |
4433 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); | |
4434 | return vcpu_mmio_write(vcpu, gpa, bytes, val); | |
4435 | } | |
4436 | ||
4437 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4438 | void *val, int bytes) | |
4439 | { | |
4440 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
4441 | return X86EMUL_IO_NEEDED; | |
4442 | } | |
4443 | ||
4444 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4445 | void *val, int bytes) | |
4446 | { | |
f78146b0 AK |
4447 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
4448 | ||
87da7e66 | 4449 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
4450 | return X86EMUL_CONTINUE; |
4451 | } | |
4452 | ||
0fbe9b0b | 4453 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
4454 | .read_write_prepare = read_prepare, |
4455 | .read_write_emulate = read_emulate, | |
4456 | .read_write_mmio = vcpu_mmio_read, | |
4457 | .read_write_exit_mmio = read_exit_mmio, | |
4458 | }; | |
4459 | ||
0fbe9b0b | 4460 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
4461 | .read_write_emulate = write_emulate, |
4462 | .read_write_mmio = write_mmio, | |
4463 | .read_write_exit_mmio = write_exit_mmio, | |
4464 | .write = true, | |
4465 | }; | |
4466 | ||
22388a3c XG |
4467 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
4468 | unsigned int bytes, | |
4469 | struct x86_exception *exception, | |
4470 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 4471 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4472 | { |
af7cc7d1 XG |
4473 | gpa_t gpa; |
4474 | int handled, ret; | |
22388a3c | 4475 | bool write = ops->write; |
f78146b0 | 4476 | struct kvm_mmio_fragment *frag; |
10589a46 | 4477 | |
22388a3c | 4478 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); |
bbd9b64e | 4479 | |
af7cc7d1 | 4480 | if (ret < 0) |
bbd9b64e | 4481 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
4482 | |
4483 | /* For APIC access vmexit */ | |
af7cc7d1 | 4484 | if (ret) |
bbd9b64e CO |
4485 | goto mmio; |
4486 | ||
22388a3c | 4487 | if (ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
4488 | return X86EMUL_CONTINUE; |
4489 | ||
4490 | mmio: | |
4491 | /* | |
4492 | * Is this MMIO handled locally? | |
4493 | */ | |
22388a3c | 4494 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 4495 | if (handled == bytes) |
bbd9b64e | 4496 | return X86EMUL_CONTINUE; |
bbd9b64e | 4497 | |
70252a10 AK |
4498 | gpa += handled; |
4499 | bytes -= handled; | |
4500 | val += handled; | |
4501 | ||
87da7e66 XG |
4502 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
4503 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
4504 | frag->gpa = gpa; | |
4505 | frag->data = val; | |
4506 | frag->len = bytes; | |
f78146b0 | 4507 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
4508 | } |
4509 | ||
52eb5a6d XL |
4510 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
4511 | unsigned long addr, | |
22388a3c XG |
4512 | void *val, unsigned int bytes, |
4513 | struct x86_exception *exception, | |
0fbe9b0b | 4514 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4515 | { |
0f65dd70 | 4516 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
4517 | gpa_t gpa; |
4518 | int rc; | |
4519 | ||
4520 | if (ops->read_write_prepare && | |
4521 | ops->read_write_prepare(vcpu, val, bytes)) | |
4522 | return X86EMUL_CONTINUE; | |
4523 | ||
4524 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 4525 | |
bbd9b64e CO |
4526 | /* Crossing a page boundary? */ |
4527 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 4528 | int now; |
bbd9b64e CO |
4529 | |
4530 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
4531 | rc = emulator_read_write_onepage(addr, val, now, exception, |
4532 | vcpu, ops); | |
4533 | ||
bbd9b64e CO |
4534 | if (rc != X86EMUL_CONTINUE) |
4535 | return rc; | |
4536 | addr += now; | |
bac15531 NA |
4537 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
4538 | addr = (u32)addr; | |
bbd9b64e CO |
4539 | val += now; |
4540 | bytes -= now; | |
4541 | } | |
22388a3c | 4542 | |
f78146b0 AK |
4543 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
4544 | vcpu, ops); | |
4545 | if (rc != X86EMUL_CONTINUE) | |
4546 | return rc; | |
4547 | ||
4548 | if (!vcpu->mmio_nr_fragments) | |
4549 | return rc; | |
4550 | ||
4551 | gpa = vcpu->mmio_fragments[0].gpa; | |
4552 | ||
4553 | vcpu->mmio_needed = 1; | |
4554 | vcpu->mmio_cur_fragment = 0; | |
4555 | ||
87da7e66 | 4556 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
4557 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
4558 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
4559 | vcpu->run->mmio.phys_addr = gpa; | |
4560 | ||
4561 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
4562 | } |
4563 | ||
4564 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
4565 | unsigned long addr, | |
4566 | void *val, | |
4567 | unsigned int bytes, | |
4568 | struct x86_exception *exception) | |
4569 | { | |
4570 | return emulator_read_write(ctxt, addr, val, bytes, | |
4571 | exception, &read_emultor); | |
4572 | } | |
4573 | ||
52eb5a6d | 4574 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
4575 | unsigned long addr, |
4576 | const void *val, | |
4577 | unsigned int bytes, | |
4578 | struct x86_exception *exception) | |
4579 | { | |
4580 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
4581 | exception, &write_emultor); | |
bbd9b64e | 4582 | } |
bbd9b64e | 4583 | |
daea3e73 AK |
4584 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
4585 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
4586 | ||
4587 | #ifdef CONFIG_X86_64 | |
4588 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
4589 | #else | |
4590 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 4591 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
4592 | #endif |
4593 | ||
0f65dd70 AK |
4594 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
4595 | unsigned long addr, | |
bbd9b64e CO |
4596 | const void *old, |
4597 | const void *new, | |
4598 | unsigned int bytes, | |
0f65dd70 | 4599 | struct x86_exception *exception) |
bbd9b64e | 4600 | { |
0f65dd70 | 4601 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
daea3e73 AK |
4602 | gpa_t gpa; |
4603 | struct page *page; | |
4604 | char *kaddr; | |
4605 | bool exchanged; | |
2bacc55c | 4606 | |
daea3e73 AK |
4607 | /* guests cmpxchg8b have to be emulated atomically */ |
4608 | if (bytes > 8 || (bytes & (bytes - 1))) | |
4609 | goto emul_write; | |
10589a46 | 4610 | |
daea3e73 | 4611 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 4612 | |
daea3e73 AK |
4613 | if (gpa == UNMAPPED_GVA || |
4614 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4615 | goto emul_write; | |
2bacc55c | 4616 | |
daea3e73 AK |
4617 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
4618 | goto emul_write; | |
72dc67a6 | 4619 | |
54bf36aa | 4620 | page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); |
32cad84f | 4621 | if (is_error_page(page)) |
c19b8bd6 | 4622 | goto emul_write; |
72dc67a6 | 4623 | |
8fd75e12 | 4624 | kaddr = kmap_atomic(page); |
daea3e73 AK |
4625 | kaddr += offset_in_page(gpa); |
4626 | switch (bytes) { | |
4627 | case 1: | |
4628 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
4629 | break; | |
4630 | case 2: | |
4631 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
4632 | break; | |
4633 | case 4: | |
4634 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
4635 | break; | |
4636 | case 8: | |
4637 | exchanged = CMPXCHG64(kaddr, old, new); | |
4638 | break; | |
4639 | default: | |
4640 | BUG(); | |
2bacc55c | 4641 | } |
8fd75e12 | 4642 | kunmap_atomic(kaddr); |
daea3e73 AK |
4643 | kvm_release_page_dirty(page); |
4644 | ||
4645 | if (!exchanged) | |
4646 | return X86EMUL_CMPXCHG_FAILED; | |
4647 | ||
54bf36aa | 4648 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
0eb05bf2 | 4649 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
4650 | |
4651 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 4652 | |
3200f405 | 4653 | emul_write: |
daea3e73 | 4654 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 4655 | |
0f65dd70 | 4656 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
4657 | } |
4658 | ||
cf8f70bf GN |
4659 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
4660 | { | |
4661 | /* TODO: String I/O for in kernel device */ | |
4662 | int r; | |
4663 | ||
4664 | if (vcpu->arch.pio.in) | |
e32edf4f | 4665 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, |
cf8f70bf GN |
4666 | vcpu->arch.pio.size, pd); |
4667 | else | |
e32edf4f | 4668 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, |
cf8f70bf GN |
4669 | vcpu->arch.pio.port, vcpu->arch.pio.size, |
4670 | pd); | |
4671 | return r; | |
4672 | } | |
4673 | ||
6f6fbe98 XG |
4674 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
4675 | unsigned short port, void *val, | |
4676 | unsigned int count, bool in) | |
cf8f70bf | 4677 | { |
cf8f70bf | 4678 | vcpu->arch.pio.port = port; |
6f6fbe98 | 4679 | vcpu->arch.pio.in = in; |
7972995b | 4680 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
4681 | vcpu->arch.pio.size = size; |
4682 | ||
4683 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 4684 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4685 | return 1; |
4686 | } | |
4687 | ||
4688 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 4689 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
4690 | vcpu->run->io.size = size; |
4691 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
4692 | vcpu->run->io.count = count; | |
4693 | vcpu->run->io.port = port; | |
4694 | ||
4695 | return 0; | |
4696 | } | |
4697 | ||
6f6fbe98 XG |
4698 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
4699 | int size, unsigned short port, void *val, | |
4700 | unsigned int count) | |
cf8f70bf | 4701 | { |
ca1d4a9e | 4702 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6f6fbe98 | 4703 | int ret; |
ca1d4a9e | 4704 | |
6f6fbe98 XG |
4705 | if (vcpu->arch.pio.count) |
4706 | goto data_avail; | |
cf8f70bf | 4707 | |
6f6fbe98 XG |
4708 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
4709 | if (ret) { | |
4710 | data_avail: | |
4711 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 4712 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 4713 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4714 | return 1; |
4715 | } | |
4716 | ||
cf8f70bf GN |
4717 | return 0; |
4718 | } | |
4719 | ||
6f6fbe98 XG |
4720 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
4721 | int size, unsigned short port, | |
4722 | const void *val, unsigned int count) | |
4723 | { | |
4724 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4725 | ||
4726 | memcpy(vcpu->arch.pio_data, val, size * count); | |
1171903d | 4727 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
4728 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
4729 | } | |
4730 | ||
bbd9b64e CO |
4731 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4732 | { | |
4733 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
4734 | } | |
4735 | ||
3cb16fe7 | 4736 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 4737 | { |
3cb16fe7 | 4738 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
4739 | } |
4740 | ||
5cb56059 | 4741 | int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
4742 | { |
4743 | if (!need_emulate_wbinvd(vcpu)) | |
4744 | return X86EMUL_CONTINUE; | |
4745 | ||
4746 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
4747 | int cpu = get_cpu(); |
4748 | ||
4749 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
4750 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
4751 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 4752 | put_cpu(); |
f5f48ee1 | 4753 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
4754 | } else |
4755 | wbinvd(); | |
f5f48ee1 SY |
4756 | return X86EMUL_CONTINUE; |
4757 | } | |
5cb56059 JS |
4758 | |
4759 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4760 | { | |
4761 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
4762 | return kvm_emulate_wbinvd_noskip(vcpu); | |
4763 | } | |
f5f48ee1 SY |
4764 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
4765 | ||
5cb56059 JS |
4766 | |
4767 | ||
bcaf5cc5 AK |
4768 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
4769 | { | |
5cb56059 | 4770 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
4771 | } |
4772 | ||
52eb5a6d XL |
4773 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
4774 | unsigned long *dest) | |
bbd9b64e | 4775 | { |
16f8a6f9 | 4776 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
4777 | } |
4778 | ||
52eb5a6d XL |
4779 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
4780 | unsigned long value) | |
bbd9b64e | 4781 | { |
338dbc97 | 4782 | |
717746e3 | 4783 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
4784 | } |
4785 | ||
52a46617 | 4786 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 4787 | { |
52a46617 | 4788 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
4789 | } |
4790 | ||
717746e3 | 4791 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 4792 | { |
717746e3 | 4793 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
4794 | unsigned long value; |
4795 | ||
4796 | switch (cr) { | |
4797 | case 0: | |
4798 | value = kvm_read_cr0(vcpu); | |
4799 | break; | |
4800 | case 2: | |
4801 | value = vcpu->arch.cr2; | |
4802 | break; | |
4803 | case 3: | |
9f8fe504 | 4804 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
4805 | break; |
4806 | case 4: | |
4807 | value = kvm_read_cr4(vcpu); | |
4808 | break; | |
4809 | case 8: | |
4810 | value = kvm_get_cr8(vcpu); | |
4811 | break; | |
4812 | default: | |
a737f256 | 4813 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
4814 | return 0; |
4815 | } | |
4816 | ||
4817 | return value; | |
4818 | } | |
4819 | ||
717746e3 | 4820 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 4821 | { |
717746e3 | 4822 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
4823 | int res = 0; |
4824 | ||
52a46617 GN |
4825 | switch (cr) { |
4826 | case 0: | |
49a9b07e | 4827 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
4828 | break; |
4829 | case 2: | |
4830 | vcpu->arch.cr2 = val; | |
4831 | break; | |
4832 | case 3: | |
2390218b | 4833 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
4834 | break; |
4835 | case 4: | |
a83b29c6 | 4836 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
4837 | break; |
4838 | case 8: | |
eea1cff9 | 4839 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
4840 | break; |
4841 | default: | |
a737f256 | 4842 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 4843 | res = -1; |
52a46617 | 4844 | } |
0f12244f GN |
4845 | |
4846 | return res; | |
52a46617 GN |
4847 | } |
4848 | ||
717746e3 | 4849 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 4850 | { |
717746e3 | 4851 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
4852 | } |
4853 | ||
4bff1e86 | 4854 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 4855 | { |
4bff1e86 | 4856 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
4857 | } |
4858 | ||
4bff1e86 | 4859 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 4860 | { |
4bff1e86 | 4861 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
4862 | } |
4863 | ||
1ac9d0cf AK |
4864 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
4865 | { | |
4866 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
4867 | } | |
4868 | ||
4869 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
4870 | { | |
4871 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
4872 | } | |
4873 | ||
4bff1e86 AK |
4874 | static unsigned long emulator_get_cached_segment_base( |
4875 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 4876 | { |
4bff1e86 | 4877 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
4878 | } |
4879 | ||
1aa36616 AK |
4880 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
4881 | struct desc_struct *desc, u32 *base3, | |
4882 | int seg) | |
2dafc6c2 GN |
4883 | { |
4884 | struct kvm_segment var; | |
4885 | ||
4bff1e86 | 4886 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 4887 | *selector = var.selector; |
2dafc6c2 | 4888 | |
378a8b09 GN |
4889 | if (var.unusable) { |
4890 | memset(desc, 0, sizeof(*desc)); | |
2dafc6c2 | 4891 | return false; |
378a8b09 | 4892 | } |
2dafc6c2 GN |
4893 | |
4894 | if (var.g) | |
4895 | var.limit >>= 12; | |
4896 | set_desc_limit(desc, var.limit); | |
4897 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
4898 | #ifdef CONFIG_X86_64 |
4899 | if (base3) | |
4900 | *base3 = var.base >> 32; | |
4901 | #endif | |
2dafc6c2 GN |
4902 | desc->type = var.type; |
4903 | desc->s = var.s; | |
4904 | desc->dpl = var.dpl; | |
4905 | desc->p = var.present; | |
4906 | desc->avl = var.avl; | |
4907 | desc->l = var.l; | |
4908 | desc->d = var.db; | |
4909 | desc->g = var.g; | |
4910 | ||
4911 | return true; | |
4912 | } | |
4913 | ||
1aa36616 AK |
4914 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
4915 | struct desc_struct *desc, u32 base3, | |
4916 | int seg) | |
2dafc6c2 | 4917 | { |
4bff1e86 | 4918 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
4919 | struct kvm_segment var; |
4920 | ||
1aa36616 | 4921 | var.selector = selector; |
2dafc6c2 | 4922 | var.base = get_desc_base(desc); |
5601d05b GN |
4923 | #ifdef CONFIG_X86_64 |
4924 | var.base |= ((u64)base3) << 32; | |
4925 | #endif | |
2dafc6c2 GN |
4926 | var.limit = get_desc_limit(desc); |
4927 | if (desc->g) | |
4928 | var.limit = (var.limit << 12) | 0xfff; | |
4929 | var.type = desc->type; | |
2dafc6c2 GN |
4930 | var.dpl = desc->dpl; |
4931 | var.db = desc->d; | |
4932 | var.s = desc->s; | |
4933 | var.l = desc->l; | |
4934 | var.g = desc->g; | |
4935 | var.avl = desc->avl; | |
4936 | var.present = desc->p; | |
4937 | var.unusable = !var.present; | |
4938 | var.padding = 0; | |
4939 | ||
4940 | kvm_set_segment(vcpu, &var, seg); | |
4941 | return; | |
4942 | } | |
4943 | ||
717746e3 AK |
4944 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
4945 | u32 msr_index, u64 *pdata) | |
4946 | { | |
609e36d3 PB |
4947 | struct msr_data msr; |
4948 | int r; | |
4949 | ||
4950 | msr.index = msr_index; | |
4951 | msr.host_initiated = false; | |
4952 | r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); | |
4953 | if (r) | |
4954 | return r; | |
4955 | ||
4956 | *pdata = msr.data; | |
4957 | return 0; | |
717746e3 AK |
4958 | } |
4959 | ||
4960 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
4961 | u32 msr_index, u64 data) | |
4962 | { | |
8fe8ab46 WA |
4963 | struct msr_data msr; |
4964 | ||
4965 | msr.data = data; | |
4966 | msr.index = msr_index; | |
4967 | msr.host_initiated = false; | |
4968 | return kvm_set_msr(emul_to_vcpu(ctxt), &msr); | |
717746e3 AK |
4969 | } |
4970 | ||
64d60670 PB |
4971 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
4972 | { | |
4973 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4974 | ||
4975 | return vcpu->arch.smbase; | |
4976 | } | |
4977 | ||
4978 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
4979 | { | |
4980 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4981 | ||
4982 | vcpu->arch.smbase = smbase; | |
4983 | } | |
4984 | ||
67f4d428 NA |
4985 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
4986 | u32 pmc) | |
4987 | { | |
c6702c9d | 4988 | return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
4989 | } |
4990 | ||
222d21aa AK |
4991 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
4992 | u32 pmc, u64 *pdata) | |
4993 | { | |
c6702c9d | 4994 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
4995 | } |
4996 | ||
6c3287f7 AK |
4997 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
4998 | { | |
4999 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
5000 | } | |
5001 | ||
5037f6f3 AK |
5002 | static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) |
5003 | { | |
5004 | preempt_disable(); | |
5197b808 | 5005 | kvm_load_guest_fpu(emul_to_vcpu(ctxt)); |
5037f6f3 AK |
5006 | /* |
5007 | * CR0.TS may reference the host fpu state, not the guest fpu state, | |
5008 | * so it may be clear at this point. | |
5009 | */ | |
5010 | clts(); | |
5011 | } | |
5012 | ||
5013 | static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) | |
5014 | { | |
5015 | preempt_enable(); | |
5016 | } | |
5017 | ||
2953538e | 5018 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 5019 | struct x86_instruction_info *info, |
c4f035c6 AK |
5020 | enum x86_intercept_stage stage) |
5021 | { | |
2953538e | 5022 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
c4f035c6 AK |
5023 | } |
5024 | ||
0017f93a | 5025 | static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
bdb42f5a SB |
5026 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) |
5027 | { | |
0017f93a | 5028 | kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); |
bdb42f5a SB |
5029 | } |
5030 | ||
dd856efa AK |
5031 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
5032 | { | |
5033 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
5034 | } | |
5035 | ||
5036 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
5037 | { | |
5038 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
5039 | } | |
5040 | ||
801806d9 NA |
5041 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
5042 | { | |
5043 | kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); | |
5044 | } | |
5045 | ||
0225fb50 | 5046 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
5047 | .read_gpr = emulator_read_gpr, |
5048 | .write_gpr = emulator_write_gpr, | |
1871c602 | 5049 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 5050 | .write_std = kvm_write_guest_virt_system, |
7a036a6f | 5051 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 5052 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
5053 | .read_emulated = emulator_read_emulated, |
5054 | .write_emulated = emulator_write_emulated, | |
5055 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 5056 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
5057 | .pio_in_emulated = emulator_pio_in_emulated, |
5058 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
5059 | .get_segment = emulator_get_segment, |
5060 | .set_segment = emulator_set_segment, | |
5951c442 | 5061 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 5062 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 5063 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
5064 | .set_gdt = emulator_set_gdt, |
5065 | .set_idt = emulator_set_idt, | |
52a46617 GN |
5066 | .get_cr = emulator_get_cr, |
5067 | .set_cr = emulator_set_cr, | |
9c537244 | 5068 | .cpl = emulator_get_cpl, |
35aa5375 GN |
5069 | .get_dr = emulator_get_dr, |
5070 | .set_dr = emulator_set_dr, | |
64d60670 PB |
5071 | .get_smbase = emulator_get_smbase, |
5072 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
5073 | .set_msr = emulator_set_msr, |
5074 | .get_msr = emulator_get_msr, | |
67f4d428 | 5075 | .check_pmc = emulator_check_pmc, |
222d21aa | 5076 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 5077 | .halt = emulator_halt, |
bcaf5cc5 | 5078 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 5079 | .fix_hypercall = emulator_fix_hypercall, |
5037f6f3 AK |
5080 | .get_fpu = emulator_get_fpu, |
5081 | .put_fpu = emulator_put_fpu, | |
c4f035c6 | 5082 | .intercept = emulator_intercept, |
bdb42f5a | 5083 | .get_cpuid = emulator_get_cpuid, |
801806d9 | 5084 | .set_nmi_mask = emulator_set_nmi_mask, |
bbd9b64e CO |
5085 | }; |
5086 | ||
95cb2295 GN |
5087 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
5088 | { | |
37ccdcbe | 5089 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
95cb2295 GN |
5090 | /* |
5091 | * an sti; sti; sequence only disable interrupts for the first | |
5092 | * instruction. So, if the last instruction, be it emulated or | |
5093 | * not, left the system with the INT_STI flag enabled, it | |
5094 | * means that the last instruction is an sti. We should not | |
5095 | * leave the flag on in this case. The same goes for mov ss | |
5096 | */ | |
37ccdcbe PB |
5097 | if (int_shadow & mask) |
5098 | mask = 0; | |
6addfc42 | 5099 | if (unlikely(int_shadow || mask)) { |
95cb2295 | 5100 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
5101 | if (!mask) |
5102 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5103 | } | |
95cb2295 GN |
5104 | } |
5105 | ||
ef54bcfe | 5106 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f GN |
5107 | { |
5108 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 5109 | if (ctxt->exception.vector == PF_VECTOR) |
ef54bcfe PB |
5110 | return kvm_propagate_fault(vcpu, &ctxt->exception); |
5111 | ||
5112 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
5113 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
5114 | ctxt->exception.error_code); | |
54b8486f | 5115 | else |
da9cb575 | 5116 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 5117 | return false; |
54b8486f GN |
5118 | } |
5119 | ||
8ec4722d MG |
5120 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
5121 | { | |
adf52235 | 5122 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d MG |
5123 | int cs_db, cs_l; |
5124 | ||
8ec4722d MG |
5125 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
5126 | ||
adf52235 TY |
5127 | ctxt->eflags = kvm_get_rflags(vcpu); |
5128 | ctxt->eip = kvm_rip_read(vcpu); | |
5129 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
5130 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 5131 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
5132 | cs_db ? X86EMUL_MODE_PROT32 : |
5133 | X86EMUL_MODE_PROT16; | |
a584539b | 5134 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
5135 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
5136 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
a584539b | 5137 | ctxt->emul_flags = vcpu->arch.hflags; |
adf52235 | 5138 | |
dd856efa | 5139 | init_decode_cache(ctxt); |
7ae441ea | 5140 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
5141 | } |
5142 | ||
71f9833b | 5143 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 5144 | { |
9d74191a | 5145 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
63995653 MG |
5146 | int ret; |
5147 | ||
5148 | init_emulate_ctxt(vcpu); | |
5149 | ||
9dac77fa AK |
5150 | ctxt->op_bytes = 2; |
5151 | ctxt->ad_bytes = 2; | |
5152 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 5153 | ret = emulate_int_real(ctxt, irq); |
63995653 MG |
5154 | |
5155 | if (ret != X86EMUL_CONTINUE) | |
5156 | return EMULATE_FAIL; | |
5157 | ||
9dac77fa | 5158 | ctxt->eip = ctxt->_eip; |
9d74191a TY |
5159 | kvm_rip_write(vcpu, ctxt->eip); |
5160 | kvm_set_rflags(vcpu, ctxt->eflags); | |
63995653 MG |
5161 | |
5162 | if (irq == NMI_VECTOR) | |
7460fb4a | 5163 | vcpu->arch.nmi_pending = 0; |
63995653 MG |
5164 | else |
5165 | vcpu->arch.interrupt.pending = false; | |
5166 | ||
5167 | return EMULATE_DONE; | |
5168 | } | |
5169 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
5170 | ||
6d77dbfc GN |
5171 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
5172 | { | |
fc3a9157 JR |
5173 | int r = EMULATE_DONE; |
5174 | ||
6d77dbfc GN |
5175 | ++vcpu->stat.insn_emulation_fail; |
5176 | trace_kvm_emulate_insn_failed(vcpu); | |
a2b9e6c1 | 5177 | if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { |
fc3a9157 JR |
5178 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
5179 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
5180 | vcpu->run->internal.ndata = 0; | |
5181 | r = EMULATE_FAIL; | |
5182 | } | |
6d77dbfc | 5183 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
5184 | |
5185 | return r; | |
6d77dbfc GN |
5186 | } |
5187 | ||
93c05d3e | 5188 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, |
991eebf9 GN |
5189 | bool write_fault_to_shadow_pgtable, |
5190 | int emulation_type) | |
a6f177ef | 5191 | { |
95b3cf69 | 5192 | gpa_t gpa = cr2; |
ba049e93 | 5193 | kvm_pfn_t pfn; |
a6f177ef | 5194 | |
991eebf9 GN |
5195 | if (emulation_type & EMULTYPE_NO_REEXECUTE) |
5196 | return false; | |
5197 | ||
95b3cf69 XG |
5198 | if (!vcpu->arch.mmu.direct_map) { |
5199 | /* | |
5200 | * Write permission should be allowed since only | |
5201 | * write access need to be emulated. | |
5202 | */ | |
5203 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
a6f177ef | 5204 | |
95b3cf69 XG |
5205 | /* |
5206 | * If the mapping is invalid in guest, let cpu retry | |
5207 | * it to generate fault. | |
5208 | */ | |
5209 | if (gpa == UNMAPPED_GVA) | |
5210 | return true; | |
5211 | } | |
a6f177ef | 5212 | |
8e3d9d06 XG |
5213 | /* |
5214 | * Do not retry the unhandleable instruction if it faults on the | |
5215 | * readonly host memory, otherwise it will goto a infinite loop: | |
5216 | * retry instruction -> write #PF -> emulation fail -> retry | |
5217 | * instruction -> ... | |
5218 | */ | |
5219 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
5220 | |
5221 | /* | |
5222 | * If the instruction failed on the error pfn, it can not be fixed, | |
5223 | * report the error to userspace. | |
5224 | */ | |
5225 | if (is_error_noslot_pfn(pfn)) | |
5226 | return false; | |
5227 | ||
5228 | kvm_release_pfn_clean(pfn); | |
5229 | ||
5230 | /* The instructions are well-emulated on direct mmu. */ | |
5231 | if (vcpu->arch.mmu.direct_map) { | |
5232 | unsigned int indirect_shadow_pages; | |
5233 | ||
5234 | spin_lock(&vcpu->kvm->mmu_lock); | |
5235 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
5236 | spin_unlock(&vcpu->kvm->mmu_lock); | |
5237 | ||
5238 | if (indirect_shadow_pages) | |
5239 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
5240 | ||
a6f177ef | 5241 | return true; |
8e3d9d06 | 5242 | } |
a6f177ef | 5243 | |
95b3cf69 XG |
5244 | /* |
5245 | * if emulation was due to access to shadowed page table | |
5246 | * and it failed try to unshadow page and re-enter the | |
5247 | * guest to let CPU execute the instruction. | |
5248 | */ | |
5249 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
5250 | |
5251 | /* | |
5252 | * If the access faults on its page table, it can not | |
5253 | * be fixed by unprotecting shadow page and it should | |
5254 | * be reported to userspace. | |
5255 | */ | |
5256 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
5257 | } |
5258 | ||
1cb3f3ae XG |
5259 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
5260 | unsigned long cr2, int emulation_type) | |
5261 | { | |
5262 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5263 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2; | |
5264 | ||
5265 | last_retry_eip = vcpu->arch.last_retry_eip; | |
5266 | last_retry_addr = vcpu->arch.last_retry_addr; | |
5267 | ||
5268 | /* | |
5269 | * If the emulation is caused by #PF and it is non-page_table | |
5270 | * writing instruction, it means the VM-EXIT is caused by shadow | |
5271 | * page protected, we can zap the shadow page and retry this | |
5272 | * instruction directly. | |
5273 | * | |
5274 | * Note: if the guest uses a non-page-table modifying instruction | |
5275 | * on the PDE that points to the instruction, then we will unmap | |
5276 | * the instruction and go to an infinite loop. So, we cache the | |
5277 | * last retried eip and the last fault address, if we meet the eip | |
5278 | * and the address again, we can break out of the potential infinite | |
5279 | * loop. | |
5280 | */ | |
5281 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
5282 | ||
5283 | if (!(emulation_type & EMULTYPE_RETRY)) | |
5284 | return false; | |
5285 | ||
5286 | if (x86_page_table_writing_insn(ctxt)) | |
5287 | return false; | |
5288 | ||
5289 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) | |
5290 | return false; | |
5291 | ||
5292 | vcpu->arch.last_retry_eip = ctxt->eip; | |
5293 | vcpu->arch.last_retry_addr = cr2; | |
5294 | ||
5295 | if (!vcpu->arch.mmu.direct_map) | |
5296 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
5297 | ||
22368028 | 5298 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
5299 | |
5300 | return true; | |
5301 | } | |
5302 | ||
716d51ab GN |
5303 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
5304 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
5305 | ||
64d60670 | 5306 | static void kvm_smm_changed(struct kvm_vcpu *vcpu) |
a584539b | 5307 | { |
64d60670 | 5308 | if (!(vcpu->arch.hflags & HF_SMM_MASK)) { |
660a5d51 PB |
5309 | /* This is a good place to trace that we are exiting SMM. */ |
5310 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); | |
5311 | ||
c43203ca PB |
5312 | /* Process a latched INIT or SMI, if any. */ |
5313 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 | 5314 | } |
699023e2 PB |
5315 | |
5316 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
5317 | } |
5318 | ||
5319 | static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) | |
5320 | { | |
5321 | unsigned changed = vcpu->arch.hflags ^ emul_flags; | |
5322 | ||
a584539b | 5323 | vcpu->arch.hflags = emul_flags; |
64d60670 PB |
5324 | |
5325 | if (changed & HF_SMM_MASK) | |
5326 | kvm_smm_changed(vcpu); | |
a584539b PB |
5327 | } |
5328 | ||
4a1e10d5 PB |
5329 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
5330 | unsigned long *db) | |
5331 | { | |
5332 | u32 dr6 = 0; | |
5333 | int i; | |
5334 | u32 enable, rwlen; | |
5335 | ||
5336 | enable = dr7; | |
5337 | rwlen = dr7 >> 16; | |
5338 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
5339 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
5340 | dr6 |= (1 << i); | |
5341 | return dr6; | |
5342 | } | |
5343 | ||
6addfc42 | 5344 | static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) |
663f4c61 PB |
5345 | { |
5346 | struct kvm_run *kvm_run = vcpu->run; | |
5347 | ||
5348 | /* | |
6addfc42 PB |
5349 | * rflags is the old, "raw" value of the flags. The new value has |
5350 | * not been saved yet. | |
663f4c61 PB |
5351 | * |
5352 | * This is correct even for TF set by the guest, because "the | |
5353 | * processor will not generate this exception after the instruction | |
5354 | * that sets the TF flag". | |
5355 | */ | |
663f4c61 PB |
5356 | if (unlikely(rflags & X86_EFLAGS_TF)) { |
5357 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { | |
6f43ed01 NA |
5358 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | |
5359 | DR6_RTM; | |
663f4c61 PB |
5360 | kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; |
5361 | kvm_run->debug.arch.exception = DB_VECTOR; | |
5362 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5363 | *r = EMULATE_USER_EXIT; | |
5364 | } else { | |
5365 | vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; | |
5366 | /* | |
5367 | * "Certain debug exceptions may clear bit 0-3. The | |
5368 | * remaining contents of the DR6 register are never | |
5369 | * cleared by the processor". | |
5370 | */ | |
5371 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5372 | vcpu->arch.dr6 |= DR6_BS | DR6_RTM; |
663f4c61 PB |
5373 | kvm_queue_exception(vcpu, DB_VECTOR); |
5374 | } | |
5375 | } | |
5376 | } | |
5377 | ||
4a1e10d5 PB |
5378 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
5379 | { | |
4a1e10d5 PB |
5380 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
5381 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
5382 | struct kvm_run *kvm_run = vcpu->run; |
5383 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
5384 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5385 | vcpu->arch.guest_debug_dr7, |
5386 | vcpu->arch.eff_db); | |
5387 | ||
5388 | if (dr6 != 0) { | |
6f43ed01 | 5389 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 5390 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
5391 | kvm_run->debug.arch.exception = DB_VECTOR; |
5392 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5393 | *r = EMULATE_USER_EXIT; | |
5394 | return true; | |
5395 | } | |
5396 | } | |
5397 | ||
4161a569 NA |
5398 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
5399 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
5400 | unsigned long eip = kvm_get_linear_rip(vcpu); |
5401 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5402 | vcpu->arch.dr7, |
5403 | vcpu->arch.db); | |
5404 | ||
5405 | if (dr6 != 0) { | |
5406 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5407 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
4a1e10d5 PB |
5408 | kvm_queue_exception(vcpu, DB_VECTOR); |
5409 | *r = EMULATE_DONE; | |
5410 | return true; | |
5411 | } | |
5412 | } | |
5413 | ||
5414 | return false; | |
5415 | } | |
5416 | ||
51d8b661 AP |
5417 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
5418 | unsigned long cr2, | |
dc25e89e AP |
5419 | int emulation_type, |
5420 | void *insn, | |
5421 | int insn_len) | |
bbd9b64e | 5422 | { |
95cb2295 | 5423 | int r; |
9d74191a | 5424 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
7ae441ea | 5425 | bool writeback = true; |
93c05d3e | 5426 | bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
bbd9b64e | 5427 | |
93c05d3e XG |
5428 | /* |
5429 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
5430 | * never reused. | |
5431 | */ | |
5432 | vcpu->arch.write_fault_to_shadow_pgtable = false; | |
26eef70c | 5433 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 5434 | |
571008da | 5435 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 5436 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
5437 | |
5438 | /* | |
5439 | * We will reenter on the same instruction since | |
5440 | * we do not set complete_userspace_io. This does not | |
5441 | * handle watchpoints yet, those would be handled in | |
5442 | * the emulate_ops. | |
5443 | */ | |
5444 | if (kvm_vcpu_check_breakpoint(vcpu, &r)) | |
5445 | return r; | |
5446 | ||
9d74191a TY |
5447 | ctxt->interruptibility = 0; |
5448 | ctxt->have_exception = false; | |
e0ad0b47 | 5449 | ctxt->exception.vector = -1; |
9d74191a | 5450 | ctxt->perm_ok = false; |
bbd9b64e | 5451 | |
b51e974f | 5452 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 5453 | |
9d74191a | 5454 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 5455 | |
e46479f8 | 5456 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 5457 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 5458 | if (r != EMULATION_OK) { |
4005996e AK |
5459 | if (emulation_type & EMULTYPE_TRAP_UD) |
5460 | return EMULATE_FAIL; | |
991eebf9 GN |
5461 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
5462 | emulation_type)) | |
bbd9b64e | 5463 | return EMULATE_DONE; |
6d77dbfc GN |
5464 | if (emulation_type & EMULTYPE_SKIP) |
5465 | return EMULATE_FAIL; | |
5466 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
5467 | } |
5468 | } | |
5469 | ||
ba8afb6b | 5470 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 5471 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
5472 | if (ctxt->eflags & X86_EFLAGS_RF) |
5473 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
ba8afb6b GN |
5474 | return EMULATE_DONE; |
5475 | } | |
5476 | ||
1cb3f3ae XG |
5477 | if (retry_instruction(ctxt, cr2, emulation_type)) |
5478 | return EMULATE_DONE; | |
5479 | ||
7ae441ea | 5480 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 5481 | changes registers values during IO operation */ |
7ae441ea GN |
5482 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
5483 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 5484 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 5485 | } |
4d2179e1 | 5486 | |
5cd21917 | 5487 | restart: |
9d74191a | 5488 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 5489 | |
775fde86 JR |
5490 | if (r == EMULATION_INTERCEPTED) |
5491 | return EMULATE_DONE; | |
5492 | ||
d2ddd1c4 | 5493 | if (r == EMULATION_FAILED) { |
991eebf9 GN |
5494 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
5495 | emulation_type)) | |
c3cd7ffa GN |
5496 | return EMULATE_DONE; |
5497 | ||
6d77dbfc | 5498 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
5499 | } |
5500 | ||
9d74191a | 5501 | if (ctxt->have_exception) { |
d2ddd1c4 | 5502 | r = EMULATE_DONE; |
ef54bcfe PB |
5503 | if (inject_emulated_exception(vcpu)) |
5504 | return r; | |
d2ddd1c4 | 5505 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
5506 | if (!vcpu->arch.pio.in) { |
5507 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 5508 | vcpu->arch.pio.count = 0; |
0912c977 | 5509 | } else { |
7ae441ea | 5510 | writeback = false; |
716d51ab GN |
5511 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
5512 | } | |
ac0a48c3 | 5513 | r = EMULATE_USER_EXIT; |
7ae441ea GN |
5514 | } else if (vcpu->mmio_needed) { |
5515 | if (!vcpu->mmio_is_write) | |
5516 | writeback = false; | |
ac0a48c3 | 5517 | r = EMULATE_USER_EXIT; |
716d51ab | 5518 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 5519 | } else if (r == EMULATION_RESTART) |
5cd21917 | 5520 | goto restart; |
d2ddd1c4 GN |
5521 | else |
5522 | r = EMULATE_DONE; | |
f850e2e6 | 5523 | |
7ae441ea | 5524 | if (writeback) { |
6addfc42 | 5525 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); |
9d74191a | 5526 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 5527 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
a584539b PB |
5528 | if (vcpu->arch.hflags != ctxt->emul_flags) |
5529 | kvm_set_hflags(vcpu, ctxt->emul_flags); | |
9d74191a | 5530 | kvm_rip_write(vcpu, ctxt->eip); |
663f4c61 | 5531 | if (r == EMULATE_DONE) |
6addfc42 | 5532 | kvm_vcpu_check_singlestep(vcpu, rflags, &r); |
38827dbd NA |
5533 | if (!ctxt->have_exception || |
5534 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) | |
5535 | __kvm_set_rflags(vcpu, ctxt->eflags); | |
6addfc42 PB |
5536 | |
5537 | /* | |
5538 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
5539 | * do nothing, and it will be requested again as soon as | |
5540 | * the shadow expires. But we still need to check here, | |
5541 | * because POPF has no interrupt shadow. | |
5542 | */ | |
5543 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
5544 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
5545 | } else |
5546 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
5547 | |
5548 | return r; | |
de7d789a | 5549 | } |
51d8b661 | 5550 | EXPORT_SYMBOL_GPL(x86_emulate_instruction); |
de7d789a | 5551 | |
cf8f70bf | 5552 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 5553 | { |
cf8f70bf | 5554 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
ca1d4a9e AK |
5555 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, |
5556 | size, port, &val, 1); | |
cf8f70bf | 5557 | /* do not return to emulator after return from userspace */ |
7972995b | 5558 | vcpu->arch.pio.count = 0; |
de7d789a CO |
5559 | return ret; |
5560 | } | |
cf8f70bf | 5561 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 5562 | |
8cfdc000 ZA |
5563 | static void tsc_bad(void *info) |
5564 | { | |
0a3aee0d | 5565 | __this_cpu_write(cpu_tsc_khz, 0); |
8cfdc000 ZA |
5566 | } |
5567 | ||
5568 | static void tsc_khz_changed(void *data) | |
c8076604 | 5569 | { |
8cfdc000 ZA |
5570 | struct cpufreq_freqs *freq = data; |
5571 | unsigned long khz = 0; | |
5572 | ||
5573 | if (data) | |
5574 | khz = freq->new; | |
5575 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
5576 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
5577 | if (!khz) | |
5578 | khz = tsc_khz; | |
0a3aee0d | 5579 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
5580 | } |
5581 | ||
c8076604 GH |
5582 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
5583 | void *data) | |
5584 | { | |
5585 | struct cpufreq_freqs *freq = data; | |
5586 | struct kvm *kvm; | |
5587 | struct kvm_vcpu *vcpu; | |
5588 | int i, send_ipi = 0; | |
5589 | ||
8cfdc000 ZA |
5590 | /* |
5591 | * We allow guests to temporarily run on slowing clocks, | |
5592 | * provided we notify them after, or to run on accelerating | |
5593 | * clocks, provided we notify them before. Thus time never | |
5594 | * goes backwards. | |
5595 | * | |
5596 | * However, we have a problem. We can't atomically update | |
5597 | * the frequency of a given CPU from this function; it is | |
5598 | * merely a notifier, which can be called from any CPU. | |
5599 | * Changing the TSC frequency at arbitrary points in time | |
5600 | * requires a recomputation of local variables related to | |
5601 | * the TSC for each VCPU. We must flag these local variables | |
5602 | * to be updated and be sure the update takes place with the | |
5603 | * new frequency before any guests proceed. | |
5604 | * | |
5605 | * Unfortunately, the combination of hotplug CPU and frequency | |
5606 | * change creates an intractable locking scenario; the order | |
5607 | * of when these callouts happen is undefined with respect to | |
5608 | * CPU hotplug, and they can race with each other. As such, | |
5609 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
5610 | * undefined; you can actually have a CPU frequency change take | |
5611 | * place in between the computation of X and the setting of the | |
5612 | * variable. To protect against this problem, all updates of | |
5613 | * the per_cpu tsc_khz variable are done in an interrupt | |
5614 | * protected IPI, and all callers wishing to update the value | |
5615 | * must wait for a synchronous IPI to complete (which is trivial | |
5616 | * if the caller is on the CPU already). This establishes the | |
5617 | * necessary total order on variable updates. | |
5618 | * | |
5619 | * Note that because a guest time update may take place | |
5620 | * anytime after the setting of the VCPU's request bit, the | |
5621 | * correct TSC value must be set before the request. However, | |
5622 | * to ensure the update actually makes it to any guest which | |
5623 | * starts running in hardware virtualization between the set | |
5624 | * and the acquisition of the spinlock, we must also ping the | |
5625 | * CPU after setting the request bit. | |
5626 | * | |
5627 | */ | |
5628 | ||
c8076604 GH |
5629 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
5630 | return 0; | |
5631 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
5632 | return 0; | |
8cfdc000 ZA |
5633 | |
5634 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 | 5635 | |
2f303b74 | 5636 | spin_lock(&kvm_lock); |
c8076604 | 5637 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 5638 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
5639 | if (vcpu->cpu != freq->cpu) |
5640 | continue; | |
c285545f | 5641 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c8076604 | 5642 | if (vcpu->cpu != smp_processor_id()) |
8cfdc000 | 5643 | send_ipi = 1; |
c8076604 GH |
5644 | } |
5645 | } | |
2f303b74 | 5646 | spin_unlock(&kvm_lock); |
c8076604 GH |
5647 | |
5648 | if (freq->old < freq->new && send_ipi) { | |
5649 | /* | |
5650 | * We upscale the frequency. Must make the guest | |
5651 | * doesn't see old kvmclock values while running with | |
5652 | * the new frequency, otherwise we risk the guest sees | |
5653 | * time go backwards. | |
5654 | * | |
5655 | * In case we update the frequency for another cpu | |
5656 | * (which might be in guest context) send an interrupt | |
5657 | * to kick the cpu out of guest context. Next time | |
5658 | * guest context is entered kvmclock will be updated, | |
5659 | * so the guest will not see stale values. | |
5660 | */ | |
8cfdc000 | 5661 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
5662 | } |
5663 | return 0; | |
5664 | } | |
5665 | ||
5666 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
5667 | .notifier_call = kvmclock_cpufreq_notifier |
5668 | }; | |
5669 | ||
5670 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
5671 | unsigned long action, void *hcpu) | |
5672 | { | |
5673 | unsigned int cpu = (unsigned long)hcpu; | |
5674 | ||
5675 | switch (action) { | |
5676 | case CPU_ONLINE: | |
5677 | case CPU_DOWN_FAILED: | |
5678 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
5679 | break; | |
5680 | case CPU_DOWN_PREPARE: | |
5681 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
5682 | break; | |
5683 | } | |
5684 | return NOTIFY_OK; | |
5685 | } | |
5686 | ||
5687 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
5688 | .notifier_call = kvmclock_cpu_notifier, | |
5689 | .priority = -INT_MAX | |
c8076604 GH |
5690 | }; |
5691 | ||
b820cc0c ZA |
5692 | static void kvm_timer_init(void) |
5693 | { | |
5694 | int cpu; | |
5695 | ||
c285545f | 5696 | max_tsc_khz = tsc_khz; |
460dd42e SB |
5697 | |
5698 | cpu_notifier_register_begin(); | |
b820cc0c | 5699 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
5700 | #ifdef CONFIG_CPU_FREQ |
5701 | struct cpufreq_policy policy; | |
5702 | memset(&policy, 0, sizeof(policy)); | |
3e26f230 AK |
5703 | cpu = get_cpu(); |
5704 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
5705 | if (policy.cpuinfo.max_freq) |
5706 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 5707 | put_cpu(); |
c285545f | 5708 | #endif |
b820cc0c ZA |
5709 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
5710 | CPUFREQ_TRANSITION_NOTIFIER); | |
5711 | } | |
c285545f | 5712 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); |
8cfdc000 ZA |
5713 | for_each_online_cpu(cpu) |
5714 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
460dd42e SB |
5715 | |
5716 | __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); | |
5717 | cpu_notifier_register_done(); | |
5718 | ||
b820cc0c ZA |
5719 | } |
5720 | ||
ff9d07a0 ZY |
5721 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
5722 | ||
f5132b01 | 5723 | int kvm_is_in_guest(void) |
ff9d07a0 | 5724 | { |
086c9855 | 5725 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
5726 | } |
5727 | ||
5728 | static int kvm_is_user_mode(void) | |
5729 | { | |
5730 | int user_mode = 3; | |
dcf46b94 | 5731 | |
086c9855 AS |
5732 | if (__this_cpu_read(current_vcpu)) |
5733 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5734 | |
ff9d07a0 ZY |
5735 | return user_mode != 0; |
5736 | } | |
5737 | ||
5738 | static unsigned long kvm_get_guest_ip(void) | |
5739 | { | |
5740 | unsigned long ip = 0; | |
dcf46b94 | 5741 | |
086c9855 AS |
5742 | if (__this_cpu_read(current_vcpu)) |
5743 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5744 | |
ff9d07a0 ZY |
5745 | return ip; |
5746 | } | |
5747 | ||
5748 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
5749 | .is_in_guest = kvm_is_in_guest, | |
5750 | .is_user_mode = kvm_is_user_mode, | |
5751 | .get_guest_ip = kvm_get_guest_ip, | |
5752 | }; | |
5753 | ||
5754 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
5755 | { | |
086c9855 | 5756 | __this_cpu_write(current_vcpu, vcpu); |
ff9d07a0 ZY |
5757 | } |
5758 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
5759 | ||
5760 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
5761 | { | |
086c9855 | 5762 | __this_cpu_write(current_vcpu, NULL); |
ff9d07a0 ZY |
5763 | } |
5764 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
5765 | ||
ce88decf XG |
5766 | static void kvm_set_mmio_spte_mask(void) |
5767 | { | |
5768 | u64 mask; | |
5769 | int maxphyaddr = boot_cpu_data.x86_phys_bits; | |
5770 | ||
5771 | /* | |
5772 | * Set the reserved bits and the present bit of an paging-structure | |
5773 | * entry to generate page fault with PFER.RSV = 1. | |
5774 | */ | |
885032b9 | 5775 | /* Mask the reserved physical address bits. */ |
d1431483 | 5776 | mask = rsvd_bits(maxphyaddr, 51); |
885032b9 XG |
5777 | |
5778 | /* Bit 62 is always reserved for 32bit host. */ | |
5779 | mask |= 0x3ull << 62; | |
5780 | ||
5781 | /* Set the present bit. */ | |
ce88decf XG |
5782 | mask |= 1ull; |
5783 | ||
5784 | #ifdef CONFIG_X86_64 | |
5785 | /* | |
5786 | * If reserved bit is not supported, clear the present bit to disable | |
5787 | * mmio page fault. | |
5788 | */ | |
5789 | if (maxphyaddr == 52) | |
5790 | mask &= ~1ull; | |
5791 | #endif | |
5792 | ||
5793 | kvm_mmu_set_mmio_spte_mask(mask); | |
5794 | } | |
5795 | ||
16e8d74d MT |
5796 | #ifdef CONFIG_X86_64 |
5797 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
5798 | { | |
d828199e MT |
5799 | struct kvm *kvm; |
5800 | ||
5801 | struct kvm_vcpu *vcpu; | |
5802 | int i; | |
5803 | ||
2f303b74 | 5804 | spin_lock(&kvm_lock); |
d828199e MT |
5805 | list_for_each_entry(kvm, &vm_list, vm_list) |
5806 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 5807 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 5808 | atomic_set(&kvm_guest_has_master_clock, 0); |
2f303b74 | 5809 | spin_unlock(&kvm_lock); |
16e8d74d MT |
5810 | } |
5811 | ||
5812 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
5813 | ||
5814 | /* | |
5815 | * Notification about pvclock gtod data update. | |
5816 | */ | |
5817 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
5818 | void *priv) | |
5819 | { | |
5820 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
5821 | struct timekeeper *tk = priv; | |
5822 | ||
5823 | update_pvclock_gtod(tk); | |
5824 | ||
5825 | /* disable master clock if host does not trust, or does not | |
5826 | * use, TSC clocksource | |
5827 | */ | |
5828 | if (gtod->clock.vclock_mode != VCLOCK_TSC && | |
5829 | atomic_read(&kvm_guest_has_master_clock) != 0) | |
5830 | queue_work(system_long_wq, &pvclock_gtod_work); | |
5831 | ||
5832 | return 0; | |
5833 | } | |
5834 | ||
5835 | static struct notifier_block pvclock_gtod_notifier = { | |
5836 | .notifier_call = pvclock_gtod_notify, | |
5837 | }; | |
5838 | #endif | |
5839 | ||
f8c16bba | 5840 | int kvm_arch_init(void *opaque) |
043405e1 | 5841 | { |
b820cc0c | 5842 | int r; |
6b61edf7 | 5843 | struct kvm_x86_ops *ops = opaque; |
f8c16bba | 5844 | |
f8c16bba ZX |
5845 | if (kvm_x86_ops) { |
5846 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
5847 | r = -EEXIST; |
5848 | goto out; | |
f8c16bba ZX |
5849 | } |
5850 | ||
5851 | if (!ops->cpu_has_kvm_support()) { | |
5852 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
5853 | r = -EOPNOTSUPP; |
5854 | goto out; | |
f8c16bba ZX |
5855 | } |
5856 | if (ops->disabled_by_bios()) { | |
5857 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
5858 | r = -EOPNOTSUPP; |
5859 | goto out; | |
f8c16bba ZX |
5860 | } |
5861 | ||
013f6a5d MT |
5862 | r = -ENOMEM; |
5863 | shared_msrs = alloc_percpu(struct kvm_shared_msrs); | |
5864 | if (!shared_msrs) { | |
5865 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); | |
5866 | goto out; | |
5867 | } | |
5868 | ||
97db56ce AK |
5869 | r = kvm_mmu_module_init(); |
5870 | if (r) | |
013f6a5d | 5871 | goto out_free_percpu; |
97db56ce | 5872 | |
ce88decf | 5873 | kvm_set_mmio_spte_mask(); |
97db56ce | 5874 | |
f8c16bba | 5875 | kvm_x86_ops = ops; |
920c8377 | 5876 | |
7b52345e | 5877 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
4b12f0de | 5878 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 5879 | |
b820cc0c | 5880 | kvm_timer_init(); |
c8076604 | 5881 | |
ff9d07a0 ZY |
5882 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
5883 | ||
d366bf7e | 5884 | if (boot_cpu_has(X86_FEATURE_XSAVE)) |
2acf923e DC |
5885 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
5886 | ||
c5cc421b | 5887 | kvm_lapic_init(); |
16e8d74d MT |
5888 | #ifdef CONFIG_X86_64 |
5889 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
5890 | #endif | |
5891 | ||
f8c16bba | 5892 | return 0; |
56c6d28a | 5893 | |
013f6a5d MT |
5894 | out_free_percpu: |
5895 | free_percpu(shared_msrs); | |
56c6d28a | 5896 | out: |
56c6d28a | 5897 | return r; |
043405e1 | 5898 | } |
8776e519 | 5899 | |
f8c16bba ZX |
5900 | void kvm_arch_exit(void) |
5901 | { | |
ff9d07a0 ZY |
5902 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
5903 | ||
888d256e JK |
5904 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
5905 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
5906 | CPUFREQ_TRANSITION_NOTIFIER); | |
8cfdc000 | 5907 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
16e8d74d MT |
5908 | #ifdef CONFIG_X86_64 |
5909 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
5910 | #endif | |
f8c16bba | 5911 | kvm_x86_ops = NULL; |
56c6d28a | 5912 | kvm_mmu_module_exit(); |
013f6a5d | 5913 | free_percpu(shared_msrs); |
56c6d28a | 5914 | } |
f8c16bba | 5915 | |
5cb56059 | 5916 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) |
8776e519 HB |
5917 | { |
5918 | ++vcpu->stat.halt_exits; | |
35754c98 | 5919 | if (lapic_in_kernel(vcpu)) { |
a4535290 | 5920 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
5921 | return 1; |
5922 | } else { | |
5923 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
5924 | return 0; | |
5925 | } | |
5926 | } | |
5cb56059 JS |
5927 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
5928 | ||
5929 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
5930 | { | |
5931 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
5932 | return kvm_vcpu_halt(vcpu); | |
5933 | } | |
8776e519 HB |
5934 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
5935 | ||
6aef266c SV |
5936 | /* |
5937 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
5938 | * | |
5939 | * @apicid - apicid of vcpu to be kicked. | |
5940 | */ | |
5941 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
5942 | { | |
24d2166b | 5943 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 5944 | |
24d2166b R |
5945 | lapic_irq.shorthand = 0; |
5946 | lapic_irq.dest_mode = 0; | |
5947 | lapic_irq.dest_id = apicid; | |
93bbf0b8 | 5948 | lapic_irq.msi_redir_hint = false; |
6aef266c | 5949 | |
24d2166b | 5950 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 5951 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
5952 | } |
5953 | ||
d62caabb AS |
5954 | void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) |
5955 | { | |
5956 | vcpu->arch.apicv_active = false; | |
5957 | kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); | |
5958 | } | |
5959 | ||
8776e519 HB |
5960 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
5961 | { | |
5962 | unsigned long nr, a0, a1, a2, a3, ret; | |
a449c7aa | 5963 | int op_64_bit, r = 1; |
8776e519 | 5964 | |
5cb56059 JS |
5965 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
5966 | ||
55cd8e5a GN |
5967 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
5968 | return kvm_hv_hypercall(vcpu); | |
5969 | ||
5fdbf976 MT |
5970 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5971 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5972 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5973 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5974 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 5975 | |
229456fc | 5976 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 5977 | |
a449c7aa NA |
5978 | op_64_bit = is_64_bit_mode(vcpu); |
5979 | if (!op_64_bit) { | |
8776e519 HB |
5980 | nr &= 0xFFFFFFFF; |
5981 | a0 &= 0xFFFFFFFF; | |
5982 | a1 &= 0xFFFFFFFF; | |
5983 | a2 &= 0xFFFFFFFF; | |
5984 | a3 &= 0xFFFFFFFF; | |
5985 | } | |
5986 | ||
07708c4a JK |
5987 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
5988 | ret = -KVM_EPERM; | |
5989 | goto out; | |
5990 | } | |
5991 | ||
8776e519 | 5992 | switch (nr) { |
b93463aa AK |
5993 | case KVM_HC_VAPIC_POLL_IRQ: |
5994 | ret = 0; | |
5995 | break; | |
6aef266c SV |
5996 | case KVM_HC_KICK_CPU: |
5997 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); | |
5998 | ret = 0; | |
5999 | break; | |
8776e519 HB |
6000 | default: |
6001 | ret = -KVM_ENOSYS; | |
6002 | break; | |
6003 | } | |
07708c4a | 6004 | out: |
a449c7aa NA |
6005 | if (!op_64_bit) |
6006 | ret = (u32)ret; | |
5fdbf976 | 6007 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 6008 | ++vcpu->stat.hypercalls; |
2f333bcb | 6009 | return r; |
8776e519 HB |
6010 | } |
6011 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
6012 | ||
b6785def | 6013 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 6014 | { |
d6aa1000 | 6015 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 6016 | char instruction[3]; |
5fdbf976 | 6017 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 6018 | |
8776e519 | 6019 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 6020 | |
9d74191a | 6021 | return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); |
8776e519 HB |
6022 | } |
6023 | ||
851ba692 | 6024 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 6025 | { |
782d422b MG |
6026 | return vcpu->run->request_interrupt_window && |
6027 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
6028 | } |
6029 | ||
851ba692 | 6030 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 6031 | { |
851ba692 AK |
6032 | struct kvm_run *kvm_run = vcpu->run; |
6033 | ||
91586a3b | 6034 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
f077825a | 6035 | kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; |
2d3ad1f4 | 6036 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 6037 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
6038 | kvm_run->ready_for_interrupt_injection = |
6039 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 6040 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
b6c7a5dc HB |
6041 | } |
6042 | ||
95ba8273 GN |
6043 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
6044 | { | |
6045 | int max_irr, tpr; | |
6046 | ||
6047 | if (!kvm_x86_ops->update_cr8_intercept) | |
6048 | return; | |
6049 | ||
bce87cce | 6050 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
6051 | return; |
6052 | ||
d62caabb AS |
6053 | if (vcpu->arch.apicv_active) |
6054 | return; | |
6055 | ||
8db3baa2 GN |
6056 | if (!vcpu->arch.apic->vapic_addr) |
6057 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
6058 | else | |
6059 | max_irr = -1; | |
95ba8273 GN |
6060 | |
6061 | if (max_irr != -1) | |
6062 | max_irr >>= 4; | |
6063 | ||
6064 | tpr = kvm_lapic_get_cr8(vcpu); | |
6065 | ||
6066 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
6067 | } | |
6068 | ||
b6b8a145 | 6069 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) |
95ba8273 | 6070 | { |
b6b8a145 JK |
6071 | int r; |
6072 | ||
95ba8273 | 6073 | /* try to reinject previous events if any */ |
b59bb7bd | 6074 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
6075 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
6076 | vcpu->arch.exception.has_error_code, | |
6077 | vcpu->arch.exception.error_code); | |
d6e8c854 NA |
6078 | |
6079 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) | |
6080 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
6081 | X86_EFLAGS_RF); | |
6082 | ||
6bdf0662 NA |
6083 | if (vcpu->arch.exception.nr == DB_VECTOR && |
6084 | (vcpu->arch.dr7 & DR7_GD)) { | |
6085 | vcpu->arch.dr7 &= ~DR7_GD; | |
6086 | kvm_update_dr7(vcpu); | |
6087 | } | |
6088 | ||
b59bb7bd GN |
6089 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
6090 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
6091 | vcpu->arch.exception.error_code, |
6092 | vcpu->arch.exception.reinject); | |
b6b8a145 | 6093 | return 0; |
b59bb7bd GN |
6094 | } |
6095 | ||
95ba8273 GN |
6096 | if (vcpu->arch.nmi_injected) { |
6097 | kvm_x86_ops->set_nmi(vcpu); | |
b6b8a145 | 6098 | return 0; |
95ba8273 GN |
6099 | } |
6100 | ||
6101 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 6102 | kvm_x86_ops->set_irq(vcpu); |
b6b8a145 JK |
6103 | return 0; |
6104 | } | |
6105 | ||
6106 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6107 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6108 | if (r != 0) | |
6109 | return r; | |
95ba8273 GN |
6110 | } |
6111 | ||
6112 | /* try to inject new event if pending */ | |
c43203ca PB |
6113 | if (vcpu->arch.smi_pending && !is_smm(vcpu)) { |
6114 | vcpu->arch.smi_pending = false; | |
ee2cd4b7 | 6115 | enter_smm(vcpu); |
c43203ca | 6116 | } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { |
321c5658 YS |
6117 | --vcpu->arch.nmi_pending; |
6118 | vcpu->arch.nmi_injected = true; | |
6119 | kvm_x86_ops->set_nmi(vcpu); | |
c7c9c56c | 6120 | } else if (kvm_cpu_has_injectable_intr(vcpu)) { |
9242b5b6 BD |
6121 | /* |
6122 | * Because interrupts can be injected asynchronously, we are | |
6123 | * calling check_nested_events again here to avoid a race condition. | |
6124 | * See https://lkml.org/lkml/2014/7/2/60 for discussion about this | |
6125 | * proposal and current concerns. Perhaps we should be setting | |
6126 | * KVM_REQ_EVENT only on certain events and not unconditionally? | |
6127 | */ | |
6128 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6129 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6130 | if (r != 0) | |
6131 | return r; | |
6132 | } | |
95ba8273 | 6133 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { |
66fd3f7f GN |
6134 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
6135 | false); | |
6136 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
6137 | } |
6138 | } | |
ee2cd4b7 | 6139 | |
b6b8a145 | 6140 | return 0; |
95ba8273 GN |
6141 | } |
6142 | ||
7460fb4a AK |
6143 | static void process_nmi(struct kvm_vcpu *vcpu) |
6144 | { | |
6145 | unsigned limit = 2; | |
6146 | ||
6147 | /* | |
6148 | * x86 is limited to one NMI running, and one NMI pending after it. | |
6149 | * If an NMI is already in progress, limit further NMIs to just one. | |
6150 | * Otherwise, allow two (and we'll inject the first one immediately). | |
6151 | */ | |
6152 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
6153 | limit = 1; | |
6154 | ||
6155 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
6156 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
6157 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6158 | } | |
6159 | ||
660a5d51 PB |
6160 | #define put_smstate(type, buf, offset, val) \ |
6161 | *(type *)((buf) + (offset) - 0x7e00) = val | |
6162 | ||
ee2cd4b7 | 6163 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
6164 | { |
6165 | u32 flags = 0; | |
6166 | flags |= seg->g << 23; | |
6167 | flags |= seg->db << 22; | |
6168 | flags |= seg->l << 21; | |
6169 | flags |= seg->avl << 20; | |
6170 | flags |= seg->present << 15; | |
6171 | flags |= seg->dpl << 13; | |
6172 | flags |= seg->s << 12; | |
6173 | flags |= seg->type << 8; | |
6174 | return flags; | |
6175 | } | |
6176 | ||
ee2cd4b7 | 6177 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
6178 | { |
6179 | struct kvm_segment seg; | |
6180 | int offset; | |
6181 | ||
6182 | kvm_get_segment(vcpu, &seg, n); | |
6183 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
6184 | ||
6185 | if (n < 3) | |
6186 | offset = 0x7f84 + n * 12; | |
6187 | else | |
6188 | offset = 0x7f2c + (n - 3) * 12; | |
6189 | ||
6190 | put_smstate(u32, buf, offset + 8, seg.base); | |
6191 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 6192 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
6193 | } |
6194 | ||
efbb288a | 6195 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 6196 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
6197 | { |
6198 | struct kvm_segment seg; | |
6199 | int offset; | |
6200 | u16 flags; | |
6201 | ||
6202 | kvm_get_segment(vcpu, &seg, n); | |
6203 | offset = 0x7e00 + n * 16; | |
6204 | ||
ee2cd4b7 | 6205 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
6206 | put_smstate(u16, buf, offset, seg.selector); |
6207 | put_smstate(u16, buf, offset + 2, flags); | |
6208 | put_smstate(u32, buf, offset + 4, seg.limit); | |
6209 | put_smstate(u64, buf, offset + 8, seg.base); | |
6210 | } | |
efbb288a | 6211 | #endif |
660a5d51 | 6212 | |
ee2cd4b7 | 6213 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
6214 | { |
6215 | struct desc_ptr dt; | |
6216 | struct kvm_segment seg; | |
6217 | unsigned long val; | |
6218 | int i; | |
6219 | ||
6220 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
6221 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
6222 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
6223 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
6224 | ||
6225 | for (i = 0; i < 8; i++) | |
6226 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); | |
6227 | ||
6228 | kvm_get_dr(vcpu, 6, &val); | |
6229 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
6230 | kvm_get_dr(vcpu, 7, &val); | |
6231 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
6232 | ||
6233 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
6234 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
6235 | put_smstate(u32, buf, 0x7f64, seg.base); | |
6236 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 6237 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
6238 | |
6239 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
6240 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
6241 | put_smstate(u32, buf, 0x7f80, seg.base); | |
6242 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 6243 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
6244 | |
6245 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
6246 | put_smstate(u32, buf, 0x7f74, dt.address); | |
6247 | put_smstate(u32, buf, 0x7f70, dt.size); | |
6248 | ||
6249 | kvm_x86_ops->get_idt(vcpu, &dt); | |
6250 | put_smstate(u32, buf, 0x7f58, dt.address); | |
6251 | put_smstate(u32, buf, 0x7f54, dt.size); | |
6252 | ||
6253 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 6254 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
6255 | |
6256 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
6257 | ||
6258 | /* revision id */ | |
6259 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
6260 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
6261 | } | |
6262 | ||
ee2cd4b7 | 6263 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
6264 | { |
6265 | #ifdef CONFIG_X86_64 | |
6266 | struct desc_ptr dt; | |
6267 | struct kvm_segment seg; | |
6268 | unsigned long val; | |
6269 | int i; | |
6270 | ||
6271 | for (i = 0; i < 16; i++) | |
6272 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); | |
6273 | ||
6274 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
6275 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
6276 | ||
6277 | kvm_get_dr(vcpu, 6, &val); | |
6278 | put_smstate(u64, buf, 0x7f68, val); | |
6279 | kvm_get_dr(vcpu, 7, &val); | |
6280 | put_smstate(u64, buf, 0x7f60, val); | |
6281 | ||
6282 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
6283 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
6284 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
6285 | ||
6286 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
6287 | ||
6288 | /* revision id */ | |
6289 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
6290 | ||
6291 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
6292 | ||
6293 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
6294 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 6295 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
6296 | put_smstate(u32, buf, 0x7e94, seg.limit); |
6297 | put_smstate(u64, buf, 0x7e98, seg.base); | |
6298 | ||
6299 | kvm_x86_ops->get_idt(vcpu, &dt); | |
6300 | put_smstate(u32, buf, 0x7e84, dt.size); | |
6301 | put_smstate(u64, buf, 0x7e88, dt.address); | |
6302 | ||
6303 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
6304 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 6305 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
6306 | put_smstate(u32, buf, 0x7e74, seg.limit); |
6307 | put_smstate(u64, buf, 0x7e78, seg.base); | |
6308 | ||
6309 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
6310 | put_smstate(u32, buf, 0x7e64, dt.size); | |
6311 | put_smstate(u64, buf, 0x7e68, dt.address); | |
6312 | ||
6313 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 6314 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 PB |
6315 | #else |
6316 | WARN_ON_ONCE(1); | |
6317 | #endif | |
6318 | } | |
6319 | ||
ee2cd4b7 | 6320 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 6321 | { |
660a5d51 | 6322 | struct kvm_segment cs, ds; |
18c3626e | 6323 | struct desc_ptr dt; |
660a5d51 PB |
6324 | char buf[512]; |
6325 | u32 cr0; | |
6326 | ||
660a5d51 PB |
6327 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); |
6328 | vcpu->arch.hflags |= HF_SMM_MASK; | |
6329 | memset(buf, 0, 512); | |
6330 | if (guest_cpuid_has_longmode(vcpu)) | |
ee2cd4b7 | 6331 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 6332 | else |
ee2cd4b7 | 6333 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 6334 | |
54bf36aa | 6335 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 PB |
6336 | |
6337 | if (kvm_x86_ops->get_nmi_mask(vcpu)) | |
6338 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
6339 | else | |
6340 | kvm_x86_ops->set_nmi_mask(vcpu, true); | |
6341 | ||
6342 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
6343 | kvm_rip_write(vcpu, 0x8000); | |
6344 | ||
6345 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
6346 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
6347 | vcpu->arch.cr0 = cr0; | |
6348 | ||
6349 | kvm_x86_ops->set_cr4(vcpu, 0); | |
6350 | ||
18c3626e PB |
6351 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
6352 | dt.address = dt.size = 0; | |
6353 | kvm_x86_ops->set_idt(vcpu, &dt); | |
6354 | ||
660a5d51 PB |
6355 | __kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
6356 | ||
6357 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
6358 | cs.base = vcpu->arch.smbase; | |
6359 | ||
6360 | ds.selector = 0; | |
6361 | ds.base = 0; | |
6362 | ||
6363 | cs.limit = ds.limit = 0xffffffff; | |
6364 | cs.type = ds.type = 0x3; | |
6365 | cs.dpl = ds.dpl = 0; | |
6366 | cs.db = ds.db = 0; | |
6367 | cs.s = ds.s = 1; | |
6368 | cs.l = ds.l = 0; | |
6369 | cs.g = ds.g = 1; | |
6370 | cs.avl = ds.avl = 0; | |
6371 | cs.present = ds.present = 1; | |
6372 | cs.unusable = ds.unusable = 0; | |
6373 | cs.padding = ds.padding = 0; | |
6374 | ||
6375 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
6376 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
6377 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
6378 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
6379 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
6380 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
6381 | ||
6382 | if (guest_cpuid_has_longmode(vcpu)) | |
6383 | kvm_x86_ops->set_efer(vcpu, 0); | |
6384 | ||
6385 | kvm_update_cpuid(vcpu); | |
6386 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
6387 | } |
6388 | ||
ee2cd4b7 | 6389 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
6390 | { |
6391 | vcpu->arch.smi_pending = true; | |
6392 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6393 | } | |
6394 | ||
2860c4b1 PB |
6395 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
6396 | { | |
6397 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
6398 | } | |
6399 | ||
3d81bc7e | 6400 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 6401 | { |
5c919412 AS |
6402 | u64 eoi_exit_bitmap[4]; |
6403 | ||
3d81bc7e YZ |
6404 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
6405 | return; | |
c7c9c56c | 6406 | |
6308630b | 6407 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 6408 | |
b053b2ae | 6409 | if (irqchip_split(vcpu->kvm)) |
6308630b | 6410 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 6411 | else { |
d62caabb AS |
6412 | if (vcpu->arch.apicv_active) |
6413 | kvm_x86_ops->sync_pir_to_irr(vcpu); | |
6308630b | 6414 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 6415 | } |
5c919412 AS |
6416 | bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, |
6417 | vcpu_to_synic(vcpu)->vec_bitmap, 256); | |
6418 | kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); | |
c7c9c56c YZ |
6419 | } |
6420 | ||
a70656b6 RK |
6421 | static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) |
6422 | { | |
6423 | ++vcpu->stat.tlb_flush; | |
6424 | kvm_x86_ops->tlb_flush(vcpu); | |
6425 | } | |
6426 | ||
4256f43f TC |
6427 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
6428 | { | |
c24ae0dc TC |
6429 | struct page *page = NULL; |
6430 | ||
35754c98 | 6431 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
6432 | return; |
6433 | ||
4256f43f TC |
6434 | if (!kvm_x86_ops->set_apic_access_page_addr) |
6435 | return; | |
6436 | ||
c24ae0dc | 6437 | page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
e8fd5e9e AA |
6438 | if (is_error_page(page)) |
6439 | return; | |
c24ae0dc TC |
6440 | kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); |
6441 | ||
6442 | /* | |
6443 | * Do not pin apic access page in memory, the MMU notifier | |
6444 | * will call us again if it is migrated or swapped out. | |
6445 | */ | |
6446 | put_page(page); | |
4256f43f TC |
6447 | } |
6448 | EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); | |
6449 | ||
fe71557a TC |
6450 | void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, |
6451 | unsigned long address) | |
6452 | { | |
c24ae0dc TC |
6453 | /* |
6454 | * The physical address of apic access page is stored in the VMCS. | |
6455 | * Update it when it becomes invalid. | |
6456 | */ | |
6457 | if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) | |
6458 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
fe71557a TC |
6459 | } |
6460 | ||
9357d939 | 6461 | /* |
362c698f | 6462 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
6463 | * exiting to the userspace. Otherwise, the value will be returned to the |
6464 | * userspace. | |
6465 | */ | |
851ba692 | 6466 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
6467 | { |
6468 | int r; | |
62a193ed MG |
6469 | bool req_int_win = |
6470 | dm_request_for_irq_injection(vcpu) && | |
6471 | kvm_cpu_accept_dm_intr(vcpu); | |
6472 | ||
730dca42 | 6473 | bool req_immediate_exit = false; |
b6c7a5dc | 6474 | |
3e007509 | 6475 | if (vcpu->requests) { |
a8eeb04a | 6476 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 6477 | kvm_mmu_unload(vcpu); |
a8eeb04a | 6478 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 6479 | __kvm_migrate_timers(vcpu); |
d828199e MT |
6480 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
6481 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
6482 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
6483 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
6484 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
6485 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
6486 | if (unlikely(r)) |
6487 | goto out; | |
6488 | } | |
a8eeb04a | 6489 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 6490 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 6491 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
a70656b6 | 6492 | kvm_vcpu_flush_tlb(vcpu); |
a8eeb04a | 6493 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 6494 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
6495 | r = 0; |
6496 | goto out; | |
6497 | } | |
a8eeb04a | 6498 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 6499 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
6500 | r = 0; |
6501 | goto out; | |
6502 | } | |
a8eeb04a | 6503 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
6504 | vcpu->fpu_active = 0; |
6505 | kvm_x86_ops->fpu_deactivate(vcpu); | |
6506 | } | |
af585b92 GN |
6507 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
6508 | /* Page is swapped out. Do synthetic halt */ | |
6509 | vcpu->arch.apf.halted = true; | |
6510 | r = 1; | |
6511 | goto out; | |
6512 | } | |
c9aaa895 GC |
6513 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
6514 | record_steal_time(vcpu); | |
64d60670 | 6515 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
ee2cd4b7 | 6516 | process_smi(vcpu); |
7460fb4a AK |
6517 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
6518 | process_nmi(vcpu); | |
f5132b01 | 6519 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 6520 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 6521 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 6522 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
6523 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
6524 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
6525 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 6526 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
6527 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
6528 | vcpu->run->eoi.vector = | |
6529 | vcpu->arch.pending_ioapic_eoi; | |
6530 | r = 0; | |
6531 | goto out; | |
6532 | } | |
6533 | } | |
3d81bc7e YZ |
6534 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
6535 | vcpu_scan_ioapic(vcpu); | |
4256f43f TC |
6536 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
6537 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
6538 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
6539 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
6540 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
6541 | r = 0; | |
6542 | goto out; | |
6543 | } | |
e516cebb AS |
6544 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
6545 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
6546 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
6547 | r = 0; | |
6548 | goto out; | |
6549 | } | |
db397571 AS |
6550 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
6551 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; | |
6552 | vcpu->run->hyperv = vcpu->arch.hyperv.exit; | |
6553 | r = 0; | |
6554 | goto out; | |
6555 | } | |
f3b138c5 AS |
6556 | |
6557 | /* | |
6558 | * KVM_REQ_HV_STIMER has to be processed after | |
6559 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
6560 | * depend on the guest clock being up-to-date | |
6561 | */ | |
1f4b34f8 AS |
6562 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
6563 | kvm_hv_process_stimers(vcpu); | |
2f52d58c | 6564 | } |
b93463aa | 6565 | |
bf9f6ac8 FW |
6566 | /* |
6567 | * KVM_REQ_EVENT is not set when posted interrupts are set by | |
6568 | * VT-d hardware, so we have to update RVI unconditionally. | |
6569 | */ | |
6570 | if (kvm_lapic_enabled(vcpu)) { | |
6571 | /* | |
6572 | * Update architecture specific hints for APIC | |
6573 | * virtual interrupt delivery. | |
6574 | */ | |
d62caabb | 6575 | if (vcpu->arch.apicv_active) |
bf9f6ac8 FW |
6576 | kvm_x86_ops->hwapic_irr_update(vcpu, |
6577 | kvm_lapic_find_highest_irr(vcpu)); | |
2f52d58c | 6578 | } |
b93463aa | 6579 | |
b463a6f7 | 6580 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
66450a21 JK |
6581 | kvm_apic_accept_events(vcpu); |
6582 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
6583 | r = 1; | |
6584 | goto out; | |
6585 | } | |
6586 | ||
b6b8a145 JK |
6587 | if (inject_pending_event(vcpu, req_int_win) != 0) |
6588 | req_immediate_exit = true; | |
321c5658 | 6589 | else { |
c43203ca PB |
6590 | /* Enable NMI/IRQ window open exits if needed. |
6591 | * | |
6592 | * SMIs have two cases: 1) they can be nested, and | |
6593 | * then there is nothing to do here because RSM will | |
6594 | * cause a vmexit anyway; 2) or the SMI can be pending | |
6595 | * because inject_pending_event has completed the | |
6596 | * injection of an IRQ or NMI from the previous vmexit, | |
6597 | * and then we request an immediate exit to inject the SMI. | |
6598 | */ | |
6599 | if (vcpu->arch.smi_pending && !is_smm(vcpu)) | |
6600 | req_immediate_exit = true; | |
321c5658 YS |
6601 | if (vcpu->arch.nmi_pending) |
6602 | kvm_x86_ops->enable_nmi_window(vcpu); | |
6603 | if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) | |
6604 | kvm_x86_ops->enable_irq_window(vcpu); | |
6605 | } | |
b463a6f7 AK |
6606 | |
6607 | if (kvm_lapic_enabled(vcpu)) { | |
6608 | update_cr8_intercept(vcpu); | |
6609 | kvm_lapic_sync_to_vapic(vcpu); | |
6610 | } | |
6611 | } | |
6612 | ||
d8368af8 AK |
6613 | r = kvm_mmu_reload(vcpu); |
6614 | if (unlikely(r)) { | |
d905c069 | 6615 | goto cancel_injection; |
d8368af8 AK |
6616 | } |
6617 | ||
b6c7a5dc HB |
6618 | preempt_disable(); |
6619 | ||
6620 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
6621 | if (vcpu->fpu_active) |
6622 | kvm_load_guest_fpu(vcpu); | |
6b7e2d09 XG |
6623 | vcpu->mode = IN_GUEST_MODE; |
6624 | ||
01b71917 MT |
6625 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
6626 | ||
0f127d12 LT |
6627 | /* |
6628 | * We should set ->mode before check ->requests, | |
6629 | * Please see the comment in kvm_make_all_cpus_request. | |
6630 | * This also orders the write to mode from any reads | |
6631 | * to the page tables done while the VCPU is running. | |
6632 | * Please see the comment in kvm_flush_remote_tlbs. | |
6b7e2d09 | 6633 | */ |
01b71917 | 6634 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 6635 | |
d94e1dc9 | 6636 | local_irq_disable(); |
32f88400 | 6637 | |
6b7e2d09 | 6638 | if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests |
d94e1dc9 | 6639 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 6640 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 6641 | smp_wmb(); |
6c142801 AK |
6642 | local_irq_enable(); |
6643 | preempt_enable(); | |
01b71917 | 6644 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 6645 | r = 1; |
d905c069 | 6646 | goto cancel_injection; |
6c142801 AK |
6647 | } |
6648 | ||
fc5b7f3b DM |
6649 | kvm_load_guest_xcr0(vcpu); |
6650 | ||
c43203ca PB |
6651 | if (req_immediate_exit) { |
6652 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
d6185f20 | 6653 | smp_send_reschedule(vcpu->cpu); |
c43203ca | 6654 | } |
d6185f20 | 6655 | |
8b89fe1f PB |
6656 | trace_kvm_entry(vcpu->vcpu_id); |
6657 | wait_lapic_expire(vcpu); | |
ccf73aaf | 6658 | __kvm_guest_enter(); |
b6c7a5dc | 6659 | |
42dbaa5a | 6660 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
6661 | set_debugreg(0, 7); |
6662 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
6663 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
6664 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
6665 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 6666 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 6667 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 6668 | } |
b6c7a5dc | 6669 | |
851ba692 | 6670 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 6671 | |
c77fb5fe PB |
6672 | /* |
6673 | * Do this here before restoring debug registers on the host. And | |
6674 | * since we do this before handling the vmexit, a DR access vmexit | |
6675 | * can (a) read the correct value of the debug registers, (b) set | |
6676 | * KVM_DEBUGREG_WONT_EXIT again. | |
6677 | */ | |
6678 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe PB |
6679 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
6680 | kvm_x86_ops->sync_dirty_debug_regs(vcpu); | |
70e4da7a PB |
6681 | kvm_update_dr0123(vcpu); |
6682 | kvm_update_dr6(vcpu); | |
6683 | kvm_update_dr7(vcpu); | |
6684 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; | |
c77fb5fe PB |
6685 | } |
6686 | ||
24f1e32c FW |
6687 | /* |
6688 | * If the guest has used debug registers, at least dr7 | |
6689 | * will be disabled while returning to the host. | |
6690 | * If we don't have active breakpoints in the host, we don't | |
6691 | * care about the messed up debug address registers. But if | |
6692 | * we have some of them active, restore the old state. | |
6693 | */ | |
59d8eb53 | 6694 | if (hw_breakpoint_active()) |
24f1e32c | 6695 | hw_breakpoint_restore(); |
42dbaa5a | 6696 | |
4ba76538 | 6697 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 6698 | |
6b7e2d09 | 6699 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 6700 | smp_wmb(); |
a547c6db | 6701 | |
fc5b7f3b DM |
6702 | kvm_put_guest_xcr0(vcpu); |
6703 | ||
a547c6db YZ |
6704 | /* Interrupt is enabled by handle_external_intr() */ |
6705 | kvm_x86_ops->handle_external_intr(vcpu); | |
b6c7a5dc HB |
6706 | |
6707 | ++vcpu->stat.exits; | |
6708 | ||
6709 | /* | |
6710 | * We must have an instruction between local_irq_enable() and | |
6711 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
6712 | * the interrupt shadow. The stat.exits increment will do nicely. | |
6713 | * But we need to prevent reordering, hence this barrier(): | |
6714 | */ | |
6715 | barrier(); | |
6716 | ||
6717 | kvm_guest_exit(); | |
6718 | ||
6719 | preempt_enable(); | |
6720 | ||
f656ce01 | 6721 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 6722 | |
b6c7a5dc HB |
6723 | /* |
6724 | * Profile KVM exit RIPs: | |
6725 | */ | |
6726 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
6727 | unsigned long rip = kvm_rip_read(vcpu); |
6728 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
6729 | } |
6730 | ||
cc578287 ZA |
6731 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
6732 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 6733 | |
5cfb1d5a MT |
6734 | if (vcpu->arch.apic_attention) |
6735 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 6736 | |
851ba692 | 6737 | r = kvm_x86_ops->handle_exit(vcpu); |
d905c069 MT |
6738 | return r; |
6739 | ||
6740 | cancel_injection: | |
6741 | kvm_x86_ops->cancel_injection(vcpu); | |
ae7a2a3f MT |
6742 | if (unlikely(vcpu->arch.apic_attention)) |
6743 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
6744 | out: |
6745 | return r; | |
6746 | } | |
b6c7a5dc | 6747 | |
362c698f PB |
6748 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
6749 | { | |
bf9f6ac8 FW |
6750 | if (!kvm_arch_vcpu_runnable(vcpu) && |
6751 | (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { | |
9c8fd1ba PB |
6752 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
6753 | kvm_vcpu_block(vcpu); | |
6754 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 FW |
6755 | |
6756 | if (kvm_x86_ops->post_block) | |
6757 | kvm_x86_ops->post_block(vcpu); | |
6758 | ||
9c8fd1ba PB |
6759 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
6760 | return 1; | |
6761 | } | |
362c698f PB |
6762 | |
6763 | kvm_apic_accept_events(vcpu); | |
6764 | switch(vcpu->arch.mp_state) { | |
6765 | case KVM_MP_STATE_HALTED: | |
6766 | vcpu->arch.pv.pv_unhalted = false; | |
6767 | vcpu->arch.mp_state = | |
6768 | KVM_MP_STATE_RUNNABLE; | |
6769 | case KVM_MP_STATE_RUNNABLE: | |
6770 | vcpu->arch.apf.halted = false; | |
6771 | break; | |
6772 | case KVM_MP_STATE_INIT_RECEIVED: | |
6773 | break; | |
6774 | default: | |
6775 | return -EINTR; | |
6776 | break; | |
6777 | } | |
6778 | return 1; | |
6779 | } | |
09cec754 | 6780 | |
5d9bc648 PB |
6781 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
6782 | { | |
6783 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && | |
6784 | !vcpu->arch.apf.halted); | |
6785 | } | |
6786 | ||
362c698f | 6787 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
6788 | { |
6789 | int r; | |
f656ce01 | 6790 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 6791 | |
f656ce01 | 6792 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 6793 | |
362c698f | 6794 | for (;;) { |
58f800d5 | 6795 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 6796 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 6797 | } else { |
362c698f | 6798 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
6799 | } |
6800 | ||
09cec754 GN |
6801 | if (r <= 0) |
6802 | break; | |
6803 | ||
6804 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
6805 | if (kvm_cpu_has_pending_timer(vcpu)) | |
6806 | kvm_inject_pending_timer_irqs(vcpu); | |
6807 | ||
782d422b MG |
6808 | if (dm_request_for_irq_injection(vcpu) && |
6809 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
6810 | r = 0; |
6811 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 6812 | ++vcpu->stat.request_irq_exits; |
362c698f | 6813 | break; |
09cec754 | 6814 | } |
af585b92 GN |
6815 | |
6816 | kvm_check_async_pf_completion(vcpu); | |
6817 | ||
09cec754 GN |
6818 | if (signal_pending(current)) { |
6819 | r = -EINTR; | |
851ba692 | 6820 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 | 6821 | ++vcpu->stat.signal_exits; |
362c698f | 6822 | break; |
09cec754 GN |
6823 | } |
6824 | if (need_resched()) { | |
f656ce01 | 6825 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
c08ac06a | 6826 | cond_resched(); |
f656ce01 | 6827 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 6828 | } |
b6c7a5dc HB |
6829 | } |
6830 | ||
f656ce01 | 6831 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
6832 | |
6833 | return r; | |
6834 | } | |
6835 | ||
716d51ab GN |
6836 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
6837 | { | |
6838 | int r; | |
6839 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
6840 | r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); | |
6841 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
6842 | if (r != EMULATE_DONE) | |
6843 | return 0; | |
6844 | return 1; | |
6845 | } | |
6846 | ||
6847 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
6848 | { | |
6849 | BUG_ON(!vcpu->arch.pio.count); | |
6850 | ||
6851 | return complete_emulated_io(vcpu); | |
6852 | } | |
6853 | ||
f78146b0 AK |
6854 | /* |
6855 | * Implements the following, as a state machine: | |
6856 | * | |
6857 | * read: | |
6858 | * for each fragment | |
87da7e66 XG |
6859 | * for each mmio piece in the fragment |
6860 | * write gpa, len | |
6861 | * exit | |
6862 | * copy data | |
f78146b0 AK |
6863 | * execute insn |
6864 | * | |
6865 | * write: | |
6866 | * for each fragment | |
87da7e66 XG |
6867 | * for each mmio piece in the fragment |
6868 | * write gpa, len | |
6869 | * copy data | |
6870 | * exit | |
f78146b0 | 6871 | */ |
716d51ab | 6872 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
6873 | { |
6874 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 6875 | struct kvm_mmio_fragment *frag; |
87da7e66 | 6876 | unsigned len; |
5287f194 | 6877 | |
716d51ab | 6878 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 6879 | |
716d51ab | 6880 | /* Complete previous fragment */ |
87da7e66 XG |
6881 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
6882 | len = min(8u, frag->len); | |
716d51ab | 6883 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
6884 | memcpy(frag->data, run->mmio.data, len); |
6885 | ||
6886 | if (frag->len <= 8) { | |
6887 | /* Switch to the next fragment. */ | |
6888 | frag++; | |
6889 | vcpu->mmio_cur_fragment++; | |
6890 | } else { | |
6891 | /* Go forward to the next mmio piece. */ | |
6892 | frag->data += len; | |
6893 | frag->gpa += len; | |
6894 | frag->len -= len; | |
6895 | } | |
6896 | ||
a08d3b3b | 6897 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 6898 | vcpu->mmio_needed = 0; |
0912c977 PB |
6899 | |
6900 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 6901 | if (vcpu->mmio_is_write) |
716d51ab GN |
6902 | return 1; |
6903 | vcpu->mmio_read_completed = 1; | |
6904 | return complete_emulated_io(vcpu); | |
6905 | } | |
87da7e66 | 6906 | |
716d51ab GN |
6907 | run->exit_reason = KVM_EXIT_MMIO; |
6908 | run->mmio.phys_addr = frag->gpa; | |
6909 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
6910 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
6911 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
6912 | run->mmio.is_write = vcpu->mmio_is_write; |
6913 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
6914 | return 0; | |
5287f194 AK |
6915 | } |
6916 | ||
716d51ab | 6917 | |
b6c7a5dc HB |
6918 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6919 | { | |
c5bedc68 | 6920 | struct fpu *fpu = ¤t->thread.fpu; |
b6c7a5dc HB |
6921 | int r; |
6922 | sigset_t sigsaved; | |
6923 | ||
c4d72e2d | 6924 | fpu__activate_curr(fpu); |
e5c30142 | 6925 | |
ac9f6dc0 AK |
6926 | if (vcpu->sigset_active) |
6927 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
6928 | ||
a4535290 | 6929 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 6930 | kvm_vcpu_block(vcpu); |
66450a21 | 6931 | kvm_apic_accept_events(vcpu); |
d7690175 | 6932 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
6933 | r = -EAGAIN; |
6934 | goto out; | |
b6c7a5dc HB |
6935 | } |
6936 | ||
b6c7a5dc | 6937 | /* re-sync apic's tpr */ |
35754c98 | 6938 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
6939 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
6940 | r = -EINVAL; | |
6941 | goto out; | |
6942 | } | |
6943 | } | |
b6c7a5dc | 6944 | |
716d51ab GN |
6945 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
6946 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
6947 | vcpu->arch.complete_userspace_io = NULL; | |
6948 | r = cui(vcpu); | |
6949 | if (r <= 0) | |
6950 | goto out; | |
6951 | } else | |
6952 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 6953 | |
362c698f | 6954 | r = vcpu_run(vcpu); |
b6c7a5dc HB |
6955 | |
6956 | out: | |
f1d86e46 | 6957 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
6958 | if (vcpu->sigset_active) |
6959 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
6960 | ||
b6c7a5dc HB |
6961 | return r; |
6962 | } | |
6963 | ||
6964 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6965 | { | |
7ae441ea GN |
6966 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
6967 | /* | |
6968 | * We are here if userspace calls get_regs() in the middle of | |
6969 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 6970 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
6971 | * that usually, but some bad designed PV devices (vmware |
6972 | * backdoor interface) need this to work | |
6973 | */ | |
dd856efa | 6974 | emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); |
7ae441ea GN |
6975 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
6976 | } | |
5fdbf976 MT |
6977 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
6978 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
6979 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6980 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
6981 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
6982 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
6983 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
6984 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 6985 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6986 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
6987 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
6988 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
6989 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
6990 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
6991 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
6992 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
6993 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
6994 | #endif |
6995 | ||
5fdbf976 | 6996 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 6997 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 6998 | |
b6c7a5dc HB |
6999 | return 0; |
7000 | } | |
7001 | ||
7002 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
7003 | { | |
7ae441ea GN |
7004 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
7005 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
7006 | ||
5fdbf976 MT |
7007 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
7008 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
7009 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
7010 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
7011 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
7012 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
7013 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
7014 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 7015 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
7016 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
7017 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
7018 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
7019 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
7020 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
7021 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
7022 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
7023 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
7024 | #endif |
7025 | ||
5fdbf976 | 7026 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 7027 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 7028 | |
b4f14abd JK |
7029 | vcpu->arch.exception.pending = false; |
7030 | ||
3842d135 AK |
7031 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
7032 | ||
b6c7a5dc HB |
7033 | return 0; |
7034 | } | |
7035 | ||
b6c7a5dc HB |
7036 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
7037 | { | |
7038 | struct kvm_segment cs; | |
7039 | ||
3e6e0aab | 7040 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
7041 | *db = cs.db; |
7042 | *l = cs.l; | |
7043 | } | |
7044 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
7045 | ||
7046 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
7047 | struct kvm_sregs *sregs) | |
7048 | { | |
89a27f4d | 7049 | struct desc_ptr dt; |
b6c7a5dc | 7050 | |
3e6e0aab GT |
7051 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
7052 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
7053 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
7054 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
7055 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
7056 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 7057 | |
3e6e0aab GT |
7058 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
7059 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
7060 | |
7061 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
7062 | sregs->idt.limit = dt.size; |
7063 | sregs->idt.base = dt.address; | |
b6c7a5dc | 7064 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
7065 | sregs->gdt.limit = dt.size; |
7066 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 7067 | |
4d4ec087 | 7068 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 7069 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 7070 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 7071 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 7072 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 7073 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
7074 | sregs->apic_base = kvm_get_apic_base(vcpu); |
7075 | ||
923c61bb | 7076 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 7077 | |
36752c9b | 7078 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
7079 | set_bit(vcpu->arch.interrupt.nr, |
7080 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 7081 | |
b6c7a5dc HB |
7082 | return 0; |
7083 | } | |
7084 | ||
62d9f0db MT |
7085 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
7086 | struct kvm_mp_state *mp_state) | |
7087 | { | |
66450a21 | 7088 | kvm_apic_accept_events(vcpu); |
6aef266c SV |
7089 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && |
7090 | vcpu->arch.pv.pv_unhalted) | |
7091 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; | |
7092 | else | |
7093 | mp_state->mp_state = vcpu->arch.mp_state; | |
7094 | ||
62d9f0db MT |
7095 | return 0; |
7096 | } | |
7097 | ||
7098 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
7099 | struct kvm_mp_state *mp_state) | |
7100 | { | |
bce87cce | 7101 | if (!lapic_in_kernel(vcpu) && |
66450a21 JK |
7102 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
7103 | return -EINVAL; | |
7104 | ||
7105 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { | |
7106 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
7107 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
7108 | } else | |
7109 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 7110 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
62d9f0db MT |
7111 | return 0; |
7112 | } | |
7113 | ||
7f3d35fd KW |
7114 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
7115 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 7116 | { |
9d74191a | 7117 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d | 7118 | int ret; |
e01c2426 | 7119 | |
8ec4722d | 7120 | init_emulate_ctxt(vcpu); |
c697518a | 7121 | |
7f3d35fd | 7122 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 7123 | has_error_code, error_code); |
c697518a | 7124 | |
c697518a | 7125 | if (ret) |
19d04437 | 7126 | return EMULATE_FAIL; |
37817f29 | 7127 | |
9d74191a TY |
7128 | kvm_rip_write(vcpu, ctxt->eip); |
7129 | kvm_set_rflags(vcpu, ctxt->eflags); | |
3842d135 | 7130 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 7131 | return EMULATE_DONE; |
37817f29 IE |
7132 | } |
7133 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
7134 | ||
b6c7a5dc HB |
7135 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
7136 | struct kvm_sregs *sregs) | |
7137 | { | |
58cb628d | 7138 | struct msr_data apic_base_msr; |
b6c7a5dc | 7139 | int mmu_reset_needed = 0; |
63f42e02 | 7140 | int pending_vec, max_bits, idx; |
89a27f4d | 7141 | struct desc_ptr dt; |
b6c7a5dc | 7142 | |
6d1068b3 PM |
7143 | if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) |
7144 | return -EINVAL; | |
7145 | ||
89a27f4d GN |
7146 | dt.size = sregs->idt.limit; |
7147 | dt.address = sregs->idt.base; | |
b6c7a5dc | 7148 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
7149 | dt.size = sregs->gdt.limit; |
7150 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
7151 | kvm_x86_ops->set_gdt(vcpu, &dt); |
7152 | ||
ad312c7c | 7153 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 7154 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 7155 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 7156 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 7157 | |
2d3ad1f4 | 7158 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 7159 | |
f6801dff | 7160 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 7161 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
58cb628d JK |
7162 | apic_base_msr.data = sregs->apic_base; |
7163 | apic_base_msr.host_initiated = true; | |
7164 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
b6c7a5dc | 7165 | |
4d4ec087 | 7166 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 7167 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 7168 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 7169 | |
fc78f519 | 7170 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 7171 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
b9baba86 | 7172 | if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE)) |
00b27a3e | 7173 | kvm_update_cpuid(vcpu); |
63f42e02 XG |
7174 | |
7175 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
7c93be44 | 7176 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
9f8fe504 | 7177 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
7178 | mmu_reset_needed = 1; |
7179 | } | |
63f42e02 | 7180 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
7181 | |
7182 | if (mmu_reset_needed) | |
7183 | kvm_mmu_reset_context(vcpu); | |
7184 | ||
a50abc3b | 7185 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
7186 | pending_vec = find_first_bit( |
7187 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
7188 | if (pending_vec < max_bits) { | |
66fd3f7f | 7189 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 7190 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
7191 | } |
7192 | ||
3e6e0aab GT |
7193 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
7194 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
7195 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
7196 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
7197 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
7198 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 7199 | |
3e6e0aab GT |
7200 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
7201 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 7202 | |
5f0269f5 ME |
7203 | update_cr8_intercept(vcpu); |
7204 | ||
9c3e4aab | 7205 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 7206 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 7207 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 7208 | !is_protmode(vcpu)) |
9c3e4aab MT |
7209 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7210 | ||
3842d135 AK |
7211 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
7212 | ||
b6c7a5dc HB |
7213 | return 0; |
7214 | } | |
7215 | ||
d0bfb940 JK |
7216 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
7217 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 7218 | { |
355be0b9 | 7219 | unsigned long rflags; |
ae675ef0 | 7220 | int i, r; |
b6c7a5dc | 7221 | |
4f926bf2 JK |
7222 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
7223 | r = -EBUSY; | |
7224 | if (vcpu->arch.exception.pending) | |
2122ff5e | 7225 | goto out; |
4f926bf2 JK |
7226 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
7227 | kvm_queue_exception(vcpu, DB_VECTOR); | |
7228 | else | |
7229 | kvm_queue_exception(vcpu, BP_VECTOR); | |
7230 | } | |
7231 | ||
91586a3b JK |
7232 | /* |
7233 | * Read rflags as long as potentially injected trace flags are still | |
7234 | * filtered out. | |
7235 | */ | |
7236 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
7237 | |
7238 | vcpu->guest_debug = dbg->control; | |
7239 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
7240 | vcpu->guest_debug = 0; | |
7241 | ||
7242 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
7243 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
7244 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 7245 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
7246 | } else { |
7247 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
7248 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 7249 | } |
c8639010 | 7250 | kvm_update_dr7(vcpu); |
ae675ef0 | 7251 | |
f92653ee JK |
7252 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
7253 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
7254 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 7255 | |
91586a3b JK |
7256 | /* |
7257 | * Trigger an rflags update that will inject or remove the trace | |
7258 | * flags. | |
7259 | */ | |
7260 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 7261 | |
a96036b8 | 7262 | kvm_x86_ops->update_bp_intercept(vcpu); |
b6c7a5dc | 7263 | |
4f926bf2 | 7264 | r = 0; |
d0bfb940 | 7265 | |
2122ff5e | 7266 | out: |
b6c7a5dc HB |
7267 | |
7268 | return r; | |
7269 | } | |
7270 | ||
8b006791 ZX |
7271 | /* |
7272 | * Translate a guest virtual address to a guest physical address. | |
7273 | */ | |
7274 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
7275 | struct kvm_translation *tr) | |
7276 | { | |
7277 | unsigned long vaddr = tr->linear_address; | |
7278 | gpa_t gpa; | |
f656ce01 | 7279 | int idx; |
8b006791 | 7280 | |
f656ce01 | 7281 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 7282 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 7283 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
7284 | tr->physical_address = gpa; |
7285 | tr->valid = gpa != UNMAPPED_GVA; | |
7286 | tr->writeable = 1; | |
7287 | tr->usermode = 0; | |
8b006791 ZX |
7288 | |
7289 | return 0; | |
7290 | } | |
7291 | ||
d0752060 HB |
7292 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
7293 | { | |
c47ada30 | 7294 | struct fxregs_state *fxsave = |
7366ed77 | 7295 | &vcpu->arch.guest_fpu.state.fxsave; |
d0752060 | 7296 | |
d0752060 HB |
7297 | memcpy(fpu->fpr, fxsave->st_space, 128); |
7298 | fpu->fcw = fxsave->cwd; | |
7299 | fpu->fsw = fxsave->swd; | |
7300 | fpu->ftwx = fxsave->twd; | |
7301 | fpu->last_opcode = fxsave->fop; | |
7302 | fpu->last_ip = fxsave->rip; | |
7303 | fpu->last_dp = fxsave->rdp; | |
7304 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
7305 | ||
d0752060 HB |
7306 | return 0; |
7307 | } | |
7308 | ||
7309 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
7310 | { | |
c47ada30 | 7311 | struct fxregs_state *fxsave = |
7366ed77 | 7312 | &vcpu->arch.guest_fpu.state.fxsave; |
d0752060 | 7313 | |
d0752060 HB |
7314 | memcpy(fxsave->st_space, fpu->fpr, 128); |
7315 | fxsave->cwd = fpu->fcw; | |
7316 | fxsave->swd = fpu->fsw; | |
7317 | fxsave->twd = fpu->ftwx; | |
7318 | fxsave->fop = fpu->last_opcode; | |
7319 | fxsave->rip = fpu->last_ip; | |
7320 | fxsave->rdp = fpu->last_dp; | |
7321 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
7322 | ||
d0752060 HB |
7323 | return 0; |
7324 | } | |
7325 | ||
0ee6a517 | 7326 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 7327 | { |
bf935b0b | 7328 | fpstate_init(&vcpu->arch.guest_fpu.state); |
782511b0 | 7329 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
7366ed77 | 7330 | vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = |
df1daba7 | 7331 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 7332 | |
2acf923e DC |
7333 | /* |
7334 | * Ensure guest xcr0 is valid for loading | |
7335 | */ | |
d91cab78 | 7336 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 7337 | |
ad312c7c | 7338 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 7339 | } |
d0752060 HB |
7340 | |
7341 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
7342 | { | |
2608d7a1 | 7343 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
7344 | return; |
7345 | ||
2acf923e DC |
7346 | /* |
7347 | * Restore all possible states in the guest, | |
7348 | * and assume host would use all available bits. | |
7349 | * Guest xcr0 would be loaded later. | |
7350 | */ | |
d0752060 | 7351 | vcpu->guest_fpu_loaded = 1; |
b1a74bf8 | 7352 | __kernel_fpu_begin(); |
003e2e8b | 7353 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state); |
0c04851c | 7354 | trace_kvm_fpu(1); |
d0752060 | 7355 | } |
d0752060 HB |
7356 | |
7357 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
7358 | { | |
653f52c3 RR |
7359 | if (!vcpu->guest_fpu_loaded) { |
7360 | vcpu->fpu_counter = 0; | |
d0752060 | 7361 | return; |
653f52c3 | 7362 | } |
d0752060 HB |
7363 | |
7364 | vcpu->guest_fpu_loaded = 0; | |
4f836347 | 7365 | copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); |
b1a74bf8 | 7366 | __kernel_fpu_end(); |
f096ed85 | 7367 | ++vcpu->stat.fpu_reload; |
653f52c3 RR |
7368 | /* |
7369 | * If using eager FPU mode, or if the guest is a frequent user | |
7370 | * of the FPU, just leave the FPU active for next time. | |
7371 | * Every 255 times fpu_counter rolls over to 0; a guest that uses | |
7372 | * the FPU in bursts will revert to loading it on demand. | |
7373 | */ | |
5a5fbdc0 | 7374 | if (!use_eager_fpu()) { |
653f52c3 RR |
7375 | if (++vcpu->fpu_counter < 5) |
7376 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); | |
7377 | } | |
0c04851c | 7378 | trace_kvm_fpu(0); |
d0752060 | 7379 | } |
e9b11c17 ZX |
7380 | |
7381 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
7382 | { | |
12f9a48f | 7383 | kvmclock_reset(vcpu); |
7f1ea208 | 7384 | |
f5f48ee1 | 7385 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
e9b11c17 ZX |
7386 | kvm_x86_ops->vcpu_free(vcpu); |
7387 | } | |
7388 | ||
7389 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
7390 | unsigned int id) | |
7391 | { | |
c447e76b LL |
7392 | struct kvm_vcpu *vcpu; |
7393 | ||
6755bae8 ZA |
7394 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
7395 | printk_once(KERN_WARNING | |
7396 | "kvm: SMP vm created on host with unstable TSC; " | |
7397 | "guest TSC will not be reliable\n"); | |
c447e76b LL |
7398 | |
7399 | vcpu = kvm_x86_ops->vcpu_create(kvm, id); | |
7400 | ||
c447e76b | 7401 | return vcpu; |
26e5215f | 7402 | } |
e9b11c17 | 7403 | |
26e5215f AK |
7404 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
7405 | { | |
7406 | int r; | |
e9b11c17 | 7407 | |
19efffa2 | 7408 | kvm_vcpu_mtrr_init(vcpu); |
9fc77441 MT |
7409 | r = vcpu_load(vcpu); |
7410 | if (r) | |
7411 | return r; | |
d28bc9dd | 7412 | kvm_vcpu_reset(vcpu, false); |
8a3c1a33 | 7413 | kvm_mmu_setup(vcpu); |
e9b11c17 | 7414 | vcpu_put(vcpu); |
26e5215f | 7415 | return r; |
e9b11c17 ZX |
7416 | } |
7417 | ||
31928aa5 | 7418 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 7419 | { |
8fe8ab46 | 7420 | struct msr_data msr; |
332967a3 | 7421 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 7422 | |
31928aa5 DD |
7423 | if (vcpu_load(vcpu)) |
7424 | return; | |
8fe8ab46 WA |
7425 | msr.data = 0x0; |
7426 | msr.index = MSR_IA32_TSC; | |
7427 | msr.host_initiated = true; | |
7428 | kvm_write_tsc(vcpu, &msr); | |
42897d86 MT |
7429 | vcpu_put(vcpu); |
7430 | ||
630994b3 MT |
7431 | if (!kvmclock_periodic_sync) |
7432 | return; | |
7433 | ||
332967a3 AJ |
7434 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, |
7435 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
7436 | } |
7437 | ||
d40ccc62 | 7438 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 7439 | { |
9fc77441 | 7440 | int r; |
344d9588 GN |
7441 | vcpu->arch.apf.msr_val = 0; |
7442 | ||
9fc77441 MT |
7443 | r = vcpu_load(vcpu); |
7444 | BUG_ON(r); | |
e9b11c17 ZX |
7445 | kvm_mmu_unload(vcpu); |
7446 | vcpu_put(vcpu); | |
7447 | ||
7448 | kvm_x86_ops->vcpu_free(vcpu); | |
7449 | } | |
7450 | ||
d28bc9dd | 7451 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 7452 | { |
e69fab5d PB |
7453 | vcpu->arch.hflags = 0; |
7454 | ||
c43203ca | 7455 | vcpu->arch.smi_pending = 0; |
7460fb4a AK |
7456 | atomic_set(&vcpu->arch.nmi_queued, 0); |
7457 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 7458 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
7459 | kvm_clear_interrupt_queue(vcpu); |
7460 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 7461 | |
42dbaa5a | 7462 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 7463 | kvm_update_dr0123(vcpu); |
6f43ed01 | 7464 | vcpu->arch.dr6 = DR6_INIT; |
73aaf249 | 7465 | kvm_update_dr6(vcpu); |
42dbaa5a | 7466 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 7467 | kvm_update_dr7(vcpu); |
42dbaa5a | 7468 | |
1119022c NA |
7469 | vcpu->arch.cr2 = 0; |
7470 | ||
3842d135 | 7471 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 7472 | vcpu->arch.apf.msr_val = 0; |
c9aaa895 | 7473 | vcpu->arch.st.msr_val = 0; |
3842d135 | 7474 | |
12f9a48f GC |
7475 | kvmclock_reset(vcpu); |
7476 | ||
af585b92 GN |
7477 | kvm_clear_async_pf_completion_queue(vcpu); |
7478 | kvm_async_pf_hash_reset(vcpu); | |
7479 | vcpu->arch.apf.halted = false; | |
3842d135 | 7480 | |
64d60670 | 7481 | if (!init_event) { |
d28bc9dd | 7482 | kvm_pmu_reset(vcpu); |
64d60670 PB |
7483 | vcpu->arch.smbase = 0x30000; |
7484 | } | |
f5132b01 | 7485 | |
66f7b72e JS |
7486 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
7487 | vcpu->arch.regs_avail = ~0; | |
7488 | vcpu->arch.regs_dirty = ~0; | |
7489 | ||
d28bc9dd | 7490 | kvm_x86_ops->vcpu_reset(vcpu, init_event); |
e9b11c17 ZX |
7491 | } |
7492 | ||
2b4a273b | 7493 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
7494 | { |
7495 | struct kvm_segment cs; | |
7496 | ||
7497 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
7498 | cs.selector = vector << 8; | |
7499 | cs.base = vector << 12; | |
7500 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
7501 | kvm_rip_write(vcpu, 0); | |
e9b11c17 ZX |
7502 | } |
7503 | ||
13a34e06 | 7504 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 7505 | { |
ca84d1a2 ZA |
7506 | struct kvm *kvm; |
7507 | struct kvm_vcpu *vcpu; | |
7508 | int i; | |
0dd6a6ed ZA |
7509 | int ret; |
7510 | u64 local_tsc; | |
7511 | u64 max_tsc = 0; | |
7512 | bool stable, backwards_tsc = false; | |
18863bdd AK |
7513 | |
7514 | kvm_shared_msr_cpu_online(); | |
13a34e06 | 7515 | ret = kvm_x86_ops->hardware_enable(); |
0dd6a6ed ZA |
7516 | if (ret != 0) |
7517 | return ret; | |
7518 | ||
4ea1636b | 7519 | local_tsc = rdtsc(); |
0dd6a6ed ZA |
7520 | stable = !check_tsc_unstable(); |
7521 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
7522 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7523 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 7524 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
7525 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
7526 | backwards_tsc = true; | |
7527 | if (vcpu->arch.last_host_tsc > max_tsc) | |
7528 | max_tsc = vcpu->arch.last_host_tsc; | |
7529 | } | |
7530 | } | |
7531 | } | |
7532 | ||
7533 | /* | |
7534 | * Sometimes, even reliable TSCs go backwards. This happens on | |
7535 | * platforms that reset TSC during suspend or hibernate actions, but | |
7536 | * maintain synchronization. We must compensate. Fortunately, we can | |
7537 | * detect that condition here, which happens early in CPU bringup, | |
7538 | * before any KVM threads can be running. Unfortunately, we can't | |
7539 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
7540 | * enough into CPU bringup that we know how much real time has actually | |
7541 | * elapsed; our helper function, get_kernel_ns() will be using boot | |
7542 | * variables that haven't been updated yet. | |
7543 | * | |
7544 | * So we simply find the maximum observed TSC above, then record the | |
7545 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
7546 | * the adjustment will be applied. Note that we accumulate | |
7547 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
7548 | * gets a chance to run again. In the event that no KVM threads get a | |
7549 | * chance to run, we will miss the entire elapsed period, as we'll have | |
7550 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
7551 | * loose cycle time. This isn't too big a deal, since the loss will be | |
7552 | * uniform across all VCPUs (not to mention the scenario is extremely | |
7553 | * unlikely). It is possible that a second hibernate recovery happens | |
7554 | * much faster than a first, causing the observed TSC here to be | |
7555 | * smaller; this would require additional padding adjustment, which is | |
7556 | * why we set last_host_tsc to the local tsc observed here. | |
7557 | * | |
7558 | * N.B. - this code below runs only on platforms with reliable TSC, | |
7559 | * as that is the only way backwards_tsc is set above. Also note | |
7560 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
7561 | * have the same delta_cyc adjustment applied if backwards_tsc | |
7562 | * is detected. Note further, this adjustment is only done once, | |
7563 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
7564 | * called multiple times (one for each physical CPU bringup). | |
7565 | * | |
4a969980 | 7566 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
7567 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
7568 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
7569 | * guarantee that they stay in perfect synchronization. | |
7570 | */ | |
7571 | if (backwards_tsc) { | |
7572 | u64 delta_cyc = max_tsc - local_tsc; | |
16a96021 | 7573 | backwards_tsc_observed = true; |
0dd6a6ed ZA |
7574 | list_for_each_entry(kvm, &vm_list, vm_list) { |
7575 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7576 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
7577 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 7578 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
7579 | } |
7580 | ||
7581 | /* | |
7582 | * We have to disable TSC offset matching.. if you were | |
7583 | * booting a VM while issuing an S4 host suspend.... | |
7584 | * you may have some problem. Solving this issue is | |
7585 | * left as an exercise to the reader. | |
7586 | */ | |
7587 | kvm->arch.last_tsc_nsec = 0; | |
7588 | kvm->arch.last_tsc_write = 0; | |
7589 | } | |
7590 | ||
7591 | } | |
7592 | return 0; | |
e9b11c17 ZX |
7593 | } |
7594 | ||
13a34e06 | 7595 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 7596 | { |
13a34e06 RK |
7597 | kvm_x86_ops->hardware_disable(); |
7598 | drop_user_return_notifiers(); | |
e9b11c17 ZX |
7599 | } |
7600 | ||
7601 | int kvm_arch_hardware_setup(void) | |
7602 | { | |
9e9c3fe4 NA |
7603 | int r; |
7604 | ||
7605 | r = kvm_x86_ops->hardware_setup(); | |
7606 | if (r != 0) | |
7607 | return r; | |
7608 | ||
35181e86 HZ |
7609 | if (kvm_has_tsc_control) { |
7610 | /* | |
7611 | * Make sure the user can only configure tsc_khz values that | |
7612 | * fit into a signed integer. | |
7613 | * A min value is not calculated needed because it will always | |
7614 | * be 1 on all machines. | |
7615 | */ | |
7616 | u64 max = min(0x7fffffffULL, | |
7617 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
7618 | kvm_max_guest_tsc_khz = max; | |
7619 | ||
ad721883 | 7620 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 7621 | } |
ad721883 | 7622 | |
9e9c3fe4 NA |
7623 | kvm_init_msr_list(); |
7624 | return 0; | |
e9b11c17 ZX |
7625 | } |
7626 | ||
7627 | void kvm_arch_hardware_unsetup(void) | |
7628 | { | |
7629 | kvm_x86_ops->hardware_unsetup(); | |
7630 | } | |
7631 | ||
7632 | void kvm_arch_check_processor_compat(void *rtn) | |
7633 | { | |
7634 | kvm_x86_ops->check_processor_compatibility(rtn); | |
d71ba788 PB |
7635 | } |
7636 | ||
7637 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
7638 | { | |
7639 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
7640 | } | |
7641 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
7642 | ||
7643 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
7644 | { | |
7645 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
7646 | } |
7647 | ||
54e9818f | 7648 | struct static_key kvm_no_apic_vcpu __read_mostly; |
bce87cce | 7649 | EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); |
54e9818f | 7650 | |
e9b11c17 ZX |
7651 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) |
7652 | { | |
7653 | struct page *page; | |
7654 | struct kvm *kvm; | |
7655 | int r; | |
7656 | ||
7657 | BUG_ON(vcpu->kvm == NULL); | |
7658 | kvm = vcpu->kvm; | |
7659 | ||
d62caabb | 7660 | vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(); |
6aef266c | 7661 | vcpu->arch.pv.pv_unhalted = false; |
9aabc88f | 7662 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
58d269d8 | 7663 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
a4535290 | 7664 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 7665 | else |
a4535290 | 7666 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
7667 | |
7668 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
7669 | if (!page) { | |
7670 | r = -ENOMEM; | |
7671 | goto fail; | |
7672 | } | |
ad312c7c | 7673 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 7674 | |
cc578287 | 7675 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c285545f | 7676 | |
e9b11c17 ZX |
7677 | r = kvm_mmu_create(vcpu); |
7678 | if (r < 0) | |
7679 | goto fail_free_pio_data; | |
7680 | ||
7681 | if (irqchip_in_kernel(kvm)) { | |
7682 | r = kvm_create_lapic(vcpu); | |
7683 | if (r < 0) | |
7684 | goto fail_mmu_destroy; | |
54e9818f GN |
7685 | } else |
7686 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
e9b11c17 | 7687 | |
890ca9ae HY |
7688 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
7689 | GFP_KERNEL); | |
7690 | if (!vcpu->arch.mce_banks) { | |
7691 | r = -ENOMEM; | |
443c39bc | 7692 | goto fail_free_lapic; |
890ca9ae HY |
7693 | } |
7694 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
7695 | ||
f1797359 WY |
7696 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { |
7697 | r = -ENOMEM; | |
f5f48ee1 | 7698 | goto fail_free_mce_banks; |
f1797359 | 7699 | } |
f5f48ee1 | 7700 | |
0ee6a517 | 7701 | fx_init(vcpu); |
66f7b72e | 7702 | |
ba904635 | 7703 | vcpu->arch.ia32_tsc_adjust_msr = 0x0; |
0b79459b | 7704 | vcpu->arch.pv_time_enabled = false; |
d7876f1b PB |
7705 | |
7706 | vcpu->arch.guest_supported_xcr0 = 0; | |
4344ee98 | 7707 | vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; |
d7876f1b | 7708 | |
5a4f55cd EK |
7709 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
7710 | ||
74545705 RK |
7711 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; |
7712 | ||
af585b92 | 7713 | kvm_async_pf_hash_reset(vcpu); |
f5132b01 | 7714 | kvm_pmu_init(vcpu); |
af585b92 | 7715 | |
1c1a9ce9 SR |
7716 | vcpu->arch.pending_external_vector = -1; |
7717 | ||
5c919412 AS |
7718 | kvm_hv_vcpu_init(vcpu); |
7719 | ||
e9b11c17 | 7720 | return 0; |
0ee6a517 | 7721 | |
f5f48ee1 SY |
7722 | fail_free_mce_banks: |
7723 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
7724 | fail_free_lapic: |
7725 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
7726 | fail_mmu_destroy: |
7727 | kvm_mmu_destroy(vcpu); | |
7728 | fail_free_pio_data: | |
ad312c7c | 7729 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
7730 | fail: |
7731 | return r; | |
7732 | } | |
7733 | ||
7734 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
7735 | { | |
f656ce01 MT |
7736 | int idx; |
7737 | ||
1f4b34f8 | 7738 | kvm_hv_vcpu_uninit(vcpu); |
f5132b01 | 7739 | kvm_pmu_destroy(vcpu); |
36cb93fd | 7740 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 7741 | kvm_free_lapic(vcpu); |
f656ce01 | 7742 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 7743 | kvm_mmu_destroy(vcpu); |
f656ce01 | 7744 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 7745 | free_page((unsigned long)vcpu->arch.pio_data); |
35754c98 | 7746 | if (!lapic_in_kernel(vcpu)) |
54e9818f | 7747 | static_key_slow_dec(&kvm_no_apic_vcpu); |
e9b11c17 | 7748 | } |
d19a9cd2 | 7749 | |
e790d9ef RK |
7750 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
7751 | { | |
ae97a3b8 | 7752 | kvm_x86_ops->sched_in(vcpu, cpu); |
e790d9ef RK |
7753 | } |
7754 | ||
e08b9637 | 7755 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 7756 | { |
e08b9637 CO |
7757 | if (type) |
7758 | return -EINVAL; | |
7759 | ||
6ef768fa | 7760 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 7761 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
365c8868 | 7762 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
4d5c5d0f | 7763 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 7764 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 7765 | |
5550af4d SY |
7766 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
7767 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
7768 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
7769 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
7770 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 7771 | |
038f8c11 | 7772 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 7773 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
7774 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
7775 | ||
7776 | pvclock_update_vm_gtod_copy(kvm); | |
53f658b3 | 7777 | |
7e44e449 | 7778 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 7779 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 7780 | |
0eb05bf2 | 7781 | kvm_page_track_init(kvm); |
13d268ca | 7782 | kvm_mmu_init_vm(kvm); |
0eb05bf2 | 7783 | |
03543133 SS |
7784 | if (kvm_x86_ops->vm_init) |
7785 | return kvm_x86_ops->vm_init(kvm); | |
7786 | ||
d89f5eff | 7787 | return 0; |
d19a9cd2 ZX |
7788 | } |
7789 | ||
7790 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
7791 | { | |
9fc77441 MT |
7792 | int r; |
7793 | r = vcpu_load(vcpu); | |
7794 | BUG_ON(r); | |
d19a9cd2 ZX |
7795 | kvm_mmu_unload(vcpu); |
7796 | vcpu_put(vcpu); | |
7797 | } | |
7798 | ||
7799 | static void kvm_free_vcpus(struct kvm *kvm) | |
7800 | { | |
7801 | unsigned int i; | |
988a2cae | 7802 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
7803 | |
7804 | /* | |
7805 | * Unpin any mmu pages first. | |
7806 | */ | |
af585b92 GN |
7807 | kvm_for_each_vcpu(i, vcpu, kvm) { |
7808 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 7809 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 7810 | } |
988a2cae GN |
7811 | kvm_for_each_vcpu(i, vcpu, kvm) |
7812 | kvm_arch_vcpu_free(vcpu); | |
7813 | ||
7814 | mutex_lock(&kvm->lock); | |
7815 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
7816 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 7817 | |
988a2cae GN |
7818 | atomic_set(&kvm->online_vcpus, 0); |
7819 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
7820 | } |
7821 | ||
ad8ba2cd SY |
7822 | void kvm_arch_sync_events(struct kvm *kvm) |
7823 | { | |
332967a3 | 7824 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 7825 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
ba4cef31 | 7826 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 7827 | kvm_free_pit(kvm); |
ad8ba2cd SY |
7828 | } |
7829 | ||
1d8007bd | 7830 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) |
9da0e4d5 PB |
7831 | { |
7832 | int i, r; | |
25188b99 | 7833 | unsigned long hva; |
f0d648bd PB |
7834 | struct kvm_memslots *slots = kvm_memslots(kvm); |
7835 | struct kvm_memory_slot *slot, old; | |
9da0e4d5 PB |
7836 | |
7837 | /* Called with kvm->slots_lock held. */ | |
1d8007bd PB |
7838 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
7839 | return -EINVAL; | |
9da0e4d5 | 7840 | |
f0d648bd PB |
7841 | slot = id_to_memslot(slots, id); |
7842 | if (size) { | |
b21629da | 7843 | if (slot->npages) |
f0d648bd PB |
7844 | return -EEXIST; |
7845 | ||
7846 | /* | |
7847 | * MAP_SHARED to prevent internal slot pages from being moved | |
7848 | * by fork()/COW. | |
7849 | */ | |
7850 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
7851 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
7852 | if (IS_ERR((void *)hva)) | |
7853 | return PTR_ERR((void *)hva); | |
7854 | } else { | |
7855 | if (!slot->npages) | |
7856 | return 0; | |
7857 | ||
7858 | hva = 0; | |
7859 | } | |
7860 | ||
7861 | old = *slot; | |
9da0e4d5 | 7862 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 7863 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 7864 | |
1d8007bd PB |
7865 | m.slot = id | (i << 16); |
7866 | m.flags = 0; | |
7867 | m.guest_phys_addr = gpa; | |
f0d648bd | 7868 | m.userspace_addr = hva; |
1d8007bd | 7869 | m.memory_size = size; |
9da0e4d5 PB |
7870 | r = __kvm_set_memory_region(kvm, &m); |
7871 | if (r < 0) | |
7872 | return r; | |
7873 | } | |
7874 | ||
f0d648bd PB |
7875 | if (!size) { |
7876 | r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); | |
7877 | WARN_ON(r < 0); | |
7878 | } | |
7879 | ||
9da0e4d5 PB |
7880 | return 0; |
7881 | } | |
7882 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
7883 | ||
1d8007bd | 7884 | int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) |
9da0e4d5 PB |
7885 | { |
7886 | int r; | |
7887 | ||
7888 | mutex_lock(&kvm->slots_lock); | |
1d8007bd | 7889 | r = __x86_set_memory_region(kvm, id, gpa, size); |
9da0e4d5 PB |
7890 | mutex_unlock(&kvm->slots_lock); |
7891 | ||
7892 | return r; | |
7893 | } | |
7894 | EXPORT_SYMBOL_GPL(x86_set_memory_region); | |
7895 | ||
d19a9cd2 ZX |
7896 | void kvm_arch_destroy_vm(struct kvm *kvm) |
7897 | { | |
27469d29 AH |
7898 | if (current->mm == kvm->mm) { |
7899 | /* | |
7900 | * Free memory regions allocated on behalf of userspace, | |
7901 | * unless the the memory map has changed due to process exit | |
7902 | * or fd copying. | |
7903 | */ | |
1d8007bd PB |
7904 | x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); |
7905 | x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); | |
7906 | x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
27469d29 | 7907 | } |
03543133 SS |
7908 | if (kvm_x86_ops->vm_destroy) |
7909 | kvm_x86_ops->vm_destroy(kvm); | |
6eb55818 | 7910 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
7911 | kfree(kvm->arch.vpic); |
7912 | kfree(kvm->arch.vioapic); | |
d19a9cd2 | 7913 | kvm_free_vcpus(kvm); |
1e08ec4a | 7914 | kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
13d268ca | 7915 | kvm_mmu_uninit_vm(kvm); |
d19a9cd2 | 7916 | } |
0de10343 | 7917 | |
5587027c | 7918 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, |
db3fe4eb TY |
7919 | struct kvm_memory_slot *dont) |
7920 | { | |
7921 | int i; | |
7922 | ||
d89cc617 TY |
7923 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
7924 | if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { | |
548ef284 | 7925 | kvfree(free->arch.rmap[i]); |
d89cc617 | 7926 | free->arch.rmap[i] = NULL; |
77d11309 | 7927 | } |
d89cc617 TY |
7928 | if (i == 0) |
7929 | continue; | |
7930 | ||
7931 | if (!dont || free->arch.lpage_info[i - 1] != | |
7932 | dont->arch.lpage_info[i - 1]) { | |
548ef284 | 7933 | kvfree(free->arch.lpage_info[i - 1]); |
d89cc617 | 7934 | free->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
7935 | } |
7936 | } | |
21ebbeda XG |
7937 | |
7938 | kvm_page_track_free_memslot(free, dont); | |
db3fe4eb TY |
7939 | } |
7940 | ||
5587027c AK |
7941 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
7942 | unsigned long npages) | |
db3fe4eb TY |
7943 | { |
7944 | int i; | |
7945 | ||
d89cc617 | 7946 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
92f94f1e | 7947 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
7948 | unsigned long ugfn; |
7949 | int lpages; | |
d89cc617 | 7950 | int level = i + 1; |
db3fe4eb TY |
7951 | |
7952 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
7953 | slot->base_gfn, level) + 1; | |
7954 | ||
d89cc617 TY |
7955 | slot->arch.rmap[i] = |
7956 | kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); | |
7957 | if (!slot->arch.rmap[i]) | |
77d11309 | 7958 | goto out_free; |
d89cc617 TY |
7959 | if (i == 0) |
7960 | continue; | |
77d11309 | 7961 | |
92f94f1e XG |
7962 | linfo = kvm_kvzalloc(lpages * sizeof(*linfo)); |
7963 | if (!linfo) | |
db3fe4eb TY |
7964 | goto out_free; |
7965 | ||
92f94f1e XG |
7966 | slot->arch.lpage_info[i - 1] = linfo; |
7967 | ||
db3fe4eb | 7968 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 7969 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 7970 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 7971 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
7972 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
7973 | /* | |
7974 | * If the gfn and userspace address are not aligned wrt each | |
7975 | * other, or if explicitly asked to, disable large page | |
7976 | * support for this slot | |
7977 | */ | |
7978 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
7979 | !kvm_largepages_enabled()) { | |
7980 | unsigned long j; | |
7981 | ||
7982 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 7983 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
7984 | } |
7985 | } | |
7986 | ||
21ebbeda XG |
7987 | if (kvm_page_track_create_memslot(slot, npages)) |
7988 | goto out_free; | |
7989 | ||
db3fe4eb TY |
7990 | return 0; |
7991 | ||
7992 | out_free: | |
d89cc617 | 7993 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 7994 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
7995 | slot->arch.rmap[i] = NULL; |
7996 | if (i == 0) | |
7997 | continue; | |
7998 | ||
548ef284 | 7999 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 8000 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
8001 | } |
8002 | return -ENOMEM; | |
8003 | } | |
8004 | ||
15f46015 | 8005 | void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) |
e59dbe09 | 8006 | { |
e6dff7d1 TY |
8007 | /* |
8008 | * memslots->generation has been incremented. | |
8009 | * mmio generation may have reached its maximum value. | |
8010 | */ | |
54bf36aa | 8011 | kvm_mmu_invalidate_mmio_sptes(kvm, slots); |
e59dbe09 TY |
8012 | } |
8013 | ||
f7784b8e MT |
8014 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
8015 | struct kvm_memory_slot *memslot, | |
09170a49 | 8016 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 8017 | enum kvm_mr_change change) |
0de10343 | 8018 | { |
f7784b8e MT |
8019 | return 0; |
8020 | } | |
8021 | ||
88178fd4 KH |
8022 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
8023 | struct kvm_memory_slot *new) | |
8024 | { | |
8025 | /* Still write protect RO slot */ | |
8026 | if (new->flags & KVM_MEM_READONLY) { | |
8027 | kvm_mmu_slot_remove_write_access(kvm, new); | |
8028 | return; | |
8029 | } | |
8030 | ||
8031 | /* | |
8032 | * Call kvm_x86_ops dirty logging hooks when they are valid. | |
8033 | * | |
8034 | * kvm_x86_ops->slot_disable_log_dirty is called when: | |
8035 | * | |
8036 | * - KVM_MR_CREATE with dirty logging is disabled | |
8037 | * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag | |
8038 | * | |
8039 | * The reason is, in case of PML, we need to set D-bit for any slots | |
8040 | * with dirty logging disabled in order to eliminate unnecessary GPA | |
8041 | * logging in PML buffer (and potential PML buffer full VMEXT). This | |
8042 | * guarantees leaving PML enabled during guest's lifetime won't have | |
8043 | * any additonal overhead from PML when guest is running with dirty | |
8044 | * logging disabled for memory slots. | |
8045 | * | |
8046 | * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot | |
8047 | * to dirty logging mode. | |
8048 | * | |
8049 | * If kvm_x86_ops dirty logging hooks are invalid, use write protect. | |
8050 | * | |
8051 | * In case of write protect: | |
8052 | * | |
8053 | * Write protect all pages for dirty logging. | |
8054 | * | |
8055 | * All the sptes including the large sptes which point to this | |
8056 | * slot are set to readonly. We can not create any new large | |
8057 | * spte on this slot until the end of the logging. | |
8058 | * | |
8059 | * See the comments in fast_page_fault(). | |
8060 | */ | |
8061 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
8062 | if (kvm_x86_ops->slot_enable_log_dirty) | |
8063 | kvm_x86_ops->slot_enable_log_dirty(kvm, new); | |
8064 | else | |
8065 | kvm_mmu_slot_remove_write_access(kvm, new); | |
8066 | } else { | |
8067 | if (kvm_x86_ops->slot_disable_log_dirty) | |
8068 | kvm_x86_ops->slot_disable_log_dirty(kvm, new); | |
8069 | } | |
8070 | } | |
8071 | ||
f7784b8e | 8072 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 8073 | const struct kvm_userspace_memory_region *mem, |
8482644a | 8074 | const struct kvm_memory_slot *old, |
f36f3f28 | 8075 | const struct kvm_memory_slot *new, |
8482644a | 8076 | enum kvm_mr_change change) |
f7784b8e | 8077 | { |
8482644a | 8078 | int nr_mmu_pages = 0; |
f7784b8e | 8079 | |
48c0e4e9 XG |
8080 | if (!kvm->arch.n_requested_mmu_pages) |
8081 | nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); | |
8082 | ||
48c0e4e9 | 8083 | if (nr_mmu_pages) |
0de10343 | 8084 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); |
1c91cad4 | 8085 | |
3ea3b7fa WL |
8086 | /* |
8087 | * Dirty logging tracks sptes in 4k granularity, meaning that large | |
8088 | * sptes have to be split. If live migration is successful, the guest | |
8089 | * in the source machine will be destroyed and large sptes will be | |
8090 | * created in the destination. However, if the guest continues to run | |
8091 | * in the source machine (for example if live migration fails), small | |
8092 | * sptes will remain around and cause bad performance. | |
8093 | * | |
8094 | * Scan sptes if dirty logging has been stopped, dropping those | |
8095 | * which can be collapsed into a single large-page spte. Later | |
8096 | * page faults will create the large-page sptes. | |
8097 | */ | |
8098 | if ((change != KVM_MR_DELETE) && | |
8099 | (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && | |
8100 | !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
8101 | kvm_mmu_zap_collapsible_sptes(kvm, new); | |
8102 | ||
c972f3b1 | 8103 | /* |
88178fd4 | 8104 | * Set up write protection and/or dirty logging for the new slot. |
c126d94f | 8105 | * |
88178fd4 KH |
8106 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have |
8107 | * been zapped so no dirty logging staff is needed for old slot. For | |
8108 | * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the | |
8109 | * new and it's also covered when dealing with the new slot. | |
f36f3f28 PB |
8110 | * |
8111 | * FIXME: const-ify all uses of struct kvm_memory_slot. | |
c972f3b1 | 8112 | */ |
88178fd4 | 8113 | if (change != KVM_MR_DELETE) |
f36f3f28 | 8114 | kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); |
0de10343 | 8115 | } |
1d737c8a | 8116 | |
2df72e9b | 8117 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 8118 | { |
6ca18b69 | 8119 | kvm_mmu_invalidate_zap_all_pages(kvm); |
34d4cb8f MT |
8120 | } |
8121 | ||
2df72e9b MT |
8122 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
8123 | struct kvm_memory_slot *slot) | |
8124 | { | |
6ca18b69 | 8125 | kvm_mmu_invalidate_zap_all_pages(kvm); |
2df72e9b MT |
8126 | } |
8127 | ||
5d9bc648 PB |
8128 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
8129 | { | |
8130 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
8131 | return true; | |
8132 | ||
8133 | if (kvm_apic_has_events(vcpu)) | |
8134 | return true; | |
8135 | ||
8136 | if (vcpu->arch.pv.pv_unhalted) | |
8137 | return true; | |
8138 | ||
8139 | if (atomic_read(&vcpu->arch.nmi_queued)) | |
8140 | return true; | |
8141 | ||
73917739 PB |
8142 | if (test_bit(KVM_REQ_SMI, &vcpu->requests)) |
8143 | return true; | |
8144 | ||
5d9bc648 PB |
8145 | if (kvm_arch_interrupt_allowed(vcpu) && |
8146 | kvm_cpu_has_interrupt(vcpu)) | |
8147 | return true; | |
8148 | ||
1f4b34f8 AS |
8149 | if (kvm_hv_has_stimer_pending(vcpu)) |
8150 | return true; | |
8151 | ||
5d9bc648 PB |
8152 | return false; |
8153 | } | |
8154 | ||
1d737c8a ZX |
8155 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
8156 | { | |
b6b8a145 JK |
8157 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) |
8158 | kvm_x86_ops->check_nested_events(vcpu, false); | |
8159 | ||
5d9bc648 | 8160 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 8161 | } |
5736199a | 8162 | |
b6d33834 | 8163 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 8164 | { |
b6d33834 | 8165 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 8166 | } |
78646121 GN |
8167 | |
8168 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
8169 | { | |
8170 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
8171 | } | |
229456fc | 8172 | |
82b32774 | 8173 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 8174 | { |
82b32774 NA |
8175 | if (is_64_bit_mode(vcpu)) |
8176 | return kvm_rip_read(vcpu); | |
8177 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
8178 | kvm_rip_read(vcpu)); | |
8179 | } | |
8180 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 8181 | |
82b32774 NA |
8182 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
8183 | { | |
8184 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
8185 | } |
8186 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
8187 | ||
94fe45da JK |
8188 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
8189 | { | |
8190 | unsigned long rflags; | |
8191 | ||
8192 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
8193 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 8194 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
8195 | return rflags; |
8196 | } | |
8197 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
8198 | ||
6addfc42 | 8199 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
8200 | { |
8201 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 8202 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 8203 | rflags |= X86_EFLAGS_TF; |
94fe45da | 8204 | kvm_x86_ops->set_rflags(vcpu, rflags); |
6addfc42 PB |
8205 | } |
8206 | ||
8207 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
8208 | { | |
8209 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 8210 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
8211 | } |
8212 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
8213 | ||
56028d08 GN |
8214 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
8215 | { | |
8216 | int r; | |
8217 | ||
fb67e14f | 8218 | if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || |
f2e10669 | 8219 | work->wakeup_all) |
56028d08 GN |
8220 | return; |
8221 | ||
8222 | r = kvm_mmu_reload(vcpu); | |
8223 | if (unlikely(r)) | |
8224 | return; | |
8225 | ||
fb67e14f XG |
8226 | if (!vcpu->arch.mmu.direct_map && |
8227 | work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) | |
8228 | return; | |
8229 | ||
56028d08 GN |
8230 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); |
8231 | } | |
8232 | ||
af585b92 GN |
8233 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
8234 | { | |
8235 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
8236 | } | |
8237 | ||
8238 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
8239 | { | |
8240 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
8241 | } | |
8242 | ||
8243 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8244 | { | |
8245 | u32 key = kvm_async_pf_hash_fn(gfn); | |
8246 | ||
8247 | while (vcpu->arch.apf.gfns[key] != ~0) | |
8248 | key = kvm_async_pf_next_probe(key); | |
8249 | ||
8250 | vcpu->arch.apf.gfns[key] = gfn; | |
8251 | } | |
8252 | ||
8253 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8254 | { | |
8255 | int i; | |
8256 | u32 key = kvm_async_pf_hash_fn(gfn); | |
8257 | ||
8258 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
8259 | (vcpu->arch.apf.gfns[key] != gfn && |
8260 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
8261 | key = kvm_async_pf_next_probe(key); |
8262 | ||
8263 | return key; | |
8264 | } | |
8265 | ||
8266 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8267 | { | |
8268 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
8269 | } | |
8270 | ||
8271 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8272 | { | |
8273 | u32 i, j, k; | |
8274 | ||
8275 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
8276 | while (true) { | |
8277 | vcpu->arch.apf.gfns[i] = ~0; | |
8278 | do { | |
8279 | j = kvm_async_pf_next_probe(j); | |
8280 | if (vcpu->arch.apf.gfns[j] == ~0) | |
8281 | return; | |
8282 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
8283 | /* | |
8284 | * k lies cyclically in ]i,j] | |
8285 | * | i.k.j | | |
8286 | * |....j i.k.| or |.k..j i...| | |
8287 | */ | |
8288 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
8289 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
8290 | i = j; | |
8291 | } | |
8292 | } | |
8293 | ||
7c90705b GN |
8294 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
8295 | { | |
8296 | ||
8297 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
8298 | sizeof(val)); | |
8299 | } | |
8300 | ||
af585b92 GN |
8301 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
8302 | struct kvm_async_pf *work) | |
8303 | { | |
6389ee94 AK |
8304 | struct x86_exception fault; |
8305 | ||
7c90705b | 8306 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 8307 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b GN |
8308 | |
8309 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
fc5f06fa GN |
8310 | (vcpu->arch.apf.send_user_only && |
8311 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7c90705b GN |
8312 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
8313 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
8314 | fault.vector = PF_VECTOR; |
8315 | fault.error_code_valid = true; | |
8316 | fault.error_code = 0; | |
8317 | fault.nested_page_fault = false; | |
8318 | fault.address = work->arch.token; | |
8319 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 8320 | } |
af585b92 GN |
8321 | } |
8322 | ||
8323 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
8324 | struct kvm_async_pf *work) | |
8325 | { | |
6389ee94 AK |
8326 | struct x86_exception fault; |
8327 | ||
7c90705b | 8328 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
f2e10669 | 8329 | if (work->wakeup_all) |
7c90705b GN |
8330 | work->arch.token = ~0; /* broadcast wakeup */ |
8331 | else | |
8332 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
8333 | ||
8334 | if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && | |
8335 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
6389ee94 AK |
8336 | fault.vector = PF_VECTOR; |
8337 | fault.error_code_valid = true; | |
8338 | fault.error_code = 0; | |
8339 | fault.nested_page_fault = false; | |
8340 | fault.address = work->arch.token; | |
8341 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 8342 | } |
e6d53e3b | 8343 | vcpu->arch.apf.halted = false; |
a4fa1635 | 8344 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
8345 | } |
8346 | ||
8347 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
8348 | { | |
8349 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
8350 | return true; | |
8351 | else | |
8352 | return !kvm_event_needs_reinjection(vcpu) && | |
8353 | kvm_x86_ops->interrupt_allowed(vcpu); | |
af585b92 GN |
8354 | } |
8355 | ||
5544eb9b PB |
8356 | void kvm_arch_start_assignment(struct kvm *kvm) |
8357 | { | |
8358 | atomic_inc(&kvm->arch.assigned_device_count); | |
8359 | } | |
8360 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
8361 | ||
8362 | void kvm_arch_end_assignment(struct kvm *kvm) | |
8363 | { | |
8364 | atomic_dec(&kvm->arch.assigned_device_count); | |
8365 | } | |
8366 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
8367 | ||
8368 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
8369 | { | |
8370 | return atomic_read(&kvm->arch.assigned_device_count); | |
8371 | } | |
8372 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
8373 | ||
e0f0bbc5 AW |
8374 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
8375 | { | |
8376 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
8377 | } | |
8378 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
8379 | ||
8380 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
8381 | { | |
8382 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
8383 | } | |
8384 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
8385 | ||
8386 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
8387 | { | |
8388 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
8389 | } | |
8390 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
8391 | ||
14717e20 AW |
8392 | bool kvm_arch_has_irq_bypass(void) |
8393 | { | |
8394 | return kvm_x86_ops->update_pi_irte != NULL; | |
8395 | } | |
8396 | ||
87276880 FW |
8397 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
8398 | struct irq_bypass_producer *prod) | |
8399 | { | |
8400 | struct kvm_kernel_irqfd *irqfd = | |
8401 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
8402 | ||
14717e20 | 8403 | irqfd->producer = prod; |
87276880 | 8404 | |
14717e20 AW |
8405 | return kvm_x86_ops->update_pi_irte(irqfd->kvm, |
8406 | prod->irq, irqfd->gsi, 1); | |
87276880 FW |
8407 | } |
8408 | ||
8409 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
8410 | struct irq_bypass_producer *prod) | |
8411 | { | |
8412 | int ret; | |
8413 | struct kvm_kernel_irqfd *irqfd = | |
8414 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
8415 | ||
87276880 FW |
8416 | WARN_ON(irqfd->producer != prod); |
8417 | irqfd->producer = NULL; | |
8418 | ||
8419 | /* | |
8420 | * When producer of consumer is unregistered, we change back to | |
8421 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 8422 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
8423 | * int this case doesn't want to receive the interrupts. |
8424 | */ | |
8425 | ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); | |
8426 | if (ret) | |
8427 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
8428 | " fails: %d\n", irqfd->consumer.token, ret); | |
8429 | } | |
8430 | ||
8431 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
8432 | uint32_t guest_irq, bool set) | |
8433 | { | |
8434 | if (!kvm_x86_ops->update_pi_irte) | |
8435 | return -EINVAL; | |
8436 | ||
8437 | return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); | |
8438 | } | |
8439 | ||
52004014 FW |
8440 | bool kvm_vector_hashing_enabled(void) |
8441 | { | |
8442 | return vector_hashing; | |
8443 | } | |
8444 | EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); | |
8445 | ||
229456fc | 8446 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 8447 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
8448 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
8449 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
8450 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
8451 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 8452 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 8453 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 8454 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 8455 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 8456 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 8457 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 8458 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 8459 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
7b46268d | 8460 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); |
843e4330 | 8461 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 8462 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
8463 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
8464 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); |