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kvm: x86: export TSC information to user-space
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
1767e931
PG		 39#include <linux/export.h>
40#include <linux/moduleparam.h>
0de10343 41#include <linux/mman.h>
2bacc55c 42#include <linux/highmem.h>
19de40a8 43#include <linux/iommu.h>
62c476c7 44#include <linux/intel-iommu.h>
c8076604 45#include <linux/cpufreq.h>
18863bdd 46#include <linux/user-return-notifier.h>
a983fb23 47#include <linux/srcu.h>
5a0e3ad6 48#include <linux/slab.h>
ff9d07a0 49#include <linux/perf_event.h>
7bee342a 50#include <linux/uaccess.h>
af585b92 51#include <linux/hash.h>
a1b60c1c 52#include <linux/pci.h>
16e8d74d
MT		 53#include <linux/timekeeper_internal.h>
54#include <linux/pvclock_gtod.h>
87276880
FW		 55#include <linux/kvm_irqfd.h>
56#include <linux/irqbypass.h>
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
043405e1 68
d1898b73
DH		 69#define CREATE_TRACE_POINTS
70#include "trace.h"
71
313a3dc7 72#define MAX_IO_MSRS 256
890ca9ae 73#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 74u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
75EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 76
0f65dd70
AK		 77#define emul_to_vcpu(ctxt) \
78 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79
50a37eb4
JR		 80/* EFER defaults:
81 * - enable syscall per default because its emulated by KVM
82 * - enable LME and LMA per default on 64 bit KVM
83 */
84#ifdef CONFIG_X86_64
1260edbe
LJ		 85static
86u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 87#else
1260edbe 88static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 89#endif
313a3dc7 90
ba1389b7
AK		 91#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
92#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 93
c519265f
RK		 94#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
95 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 96
cb142eb7 97static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 98static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 99static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 100static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 101
893590c7 102struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 103EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 104
893590c7 105static bool __read_mostly ignore_msrs = 0;
476bc001 106module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 107
9ed96e87
MT		 108unsigned int min_timer_period_us = 500;
109module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
110
630994b3
MT		 111static bool __read_mostly kvmclock_periodic_sync = true;
112module_param(kvmclock_periodic_sync, bool, S_IRUGO);
113
893590c7 114bool __read_mostly kvm_has_tsc_control;
92a1f12d 115EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 116u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 117EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 118u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
119EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
120u64 __read_mostly kvm_max_tsc_scaling_ratio;
121EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 122u64 __read_mostly kvm_default_tsc_scaling_ratio;
123EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 124
cc578287 125/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 126static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 127module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
128
d0659d94 129/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 130unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 131module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
132
52004014
FW		 133static bool __read_mostly vector_hashing = true;
134module_param(vector_hashing, bool, S_IRUGO);
135
893590c7 136static bool __read_mostly backwards_tsc_observed = false;
16a96021 137
18863bdd
AK		 138#define KVM_NR_SHARED_MSRS 16
139
140struct kvm_shared_msrs_global {
141 int nr;
2bf78fa7 142 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 143};
144
145struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
2bf78fa7
SY		 148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 152};
153
154static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 155static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 156
417bc304 157struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 168 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 173 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 181 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 182 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 190 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 192 { "largepages", VM_STAT(lpages) },
417bc304
HB		 193 { NULL }
194};
195
2acf923e
DC		 196u64 __read_mostly host_xcr0;
197
b6785def 198static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 199
af585b92
GN		 200static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
201{
202 int i;
203 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
204 vcpu->arch.apf.gfns[i] = ~0;
205}
206
18863bdd
AK		 207static void kvm_on_user_return(struct user_return_notifier *urn)
208{
209 unsigned slot;
18863bdd
AK		 210 struct kvm_shared_msrs *locals
211 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 212 struct kvm_shared_msr_values *values;
18863bdd
AK		 213
214 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 215 values = &locals->values[slot];
216 if (values->host != values->curr) {
217 wrmsrl(shared_msrs_global.msrs[slot], values->host);
218 values->curr = values->host;
18863bdd
AK		 219 }
220 }
221 locals->registered = false;
222 user_return_notifier_unregister(urn);
223}
224
2bf78fa7 225static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 226{
18863bdd 227 u64 value;
013f6a5d
MT		 228 unsigned int cpu = smp_processor_id();
229 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 230
2bf78fa7
SY		 231 /* only read, and nobody should modify it at this time,
232 * so don't need lock */
233 if (slot >= shared_msrs_global.nr) {
234 printk(KERN_ERR "kvm: invalid MSR slot!");
235 return;
236 }
237 rdmsrl_safe(msr, &value);
238 smsr->values[slot].host = value;
239 smsr->values[slot].curr = value;
240}
241
242void kvm_define_shared_msr(unsigned slot, u32 msr)
243{
0123be42 244 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 245 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 246 if (slot >= shared_msrs_global.nr)
247 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 248}
249EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
250
251static void kvm_shared_msr_cpu_online(void)
252{
253 unsigned i;
18863bdd
AK		 254
255 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 256 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 257}
258
8b3c3104 259int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 260{
013f6a5d
MT		 261 unsigned int cpu = smp_processor_id();
262 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 263 int err;
18863bdd 264
2bf78fa7 265 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 266 return 0;
2bf78fa7 267 smsr->values[slot].curr = value;
8b3c3104
AH		 268 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
269 if (err)
270 return 1;
271
18863bdd
AK		 272 if (!smsr->registered) {
273 smsr->urn.on_user_return = kvm_on_user_return;
274 user_return_notifier_register(&smsr->urn);
275 smsr->registered = true;
276 }
8b3c3104 277 return 0;
18863bdd
AK		 278}
279EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
280
13a34e06 281static void drop_user_return_notifiers(void)
3548bab5 282{
013f6a5d
MT		 283 unsigned int cpu = smp_processor_id();
284 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 285
286 if (smsr->registered)
287 kvm_on_user_return(&smsr->urn);
288}
289
6866b83e
CO		 290u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
291{
8a5a87d9 292 return vcpu->arch.apic_base;
6866b83e
CO		 293}
294EXPORT_SYMBOL_GPL(kvm_get_apic_base);
295
58cb628d
JK		 296int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
297{
298 u64 old_state = vcpu->arch.apic_base &
299 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
300 u64 new_state = msr_info->data &
301 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
302 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
303 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
304
305 if (!msr_info->host_initiated &&
306 ((msr_info->data & reserved_bits) != 0 ||
307 new_state == X2APIC_ENABLE ||
308 (new_state == MSR_IA32_APICBASE_ENABLE &&
309 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
310 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
311 old_state == 0)))
312 return 1;
313
314 kvm_lapic_set_base(vcpu, msr_info->data);
315 return 0;
6866b83e
CO		 316}
317EXPORT_SYMBOL_GPL(kvm_set_apic_base);
318
2605fc21 319asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 320{
321 /* Fault while not rebooting. We want the trace. */
322 BUG();
323}
324EXPORT_SYMBOL_GPL(kvm_spurious_fault);
325
3fd28fce
ED		 326#define EXCPT_BENIGN 0
327#define EXCPT_CONTRIBUTORY 1
328#define EXCPT_PF 2
329
330static int exception_class(int vector)
331{
332 switch (vector) {
333 case PF_VECTOR:
334 return EXCPT_PF;
335 case DE_VECTOR:
336 case TS_VECTOR:
337 case NP_VECTOR:
338 case SS_VECTOR:
339 case GP_VECTOR:
340 return EXCPT_CONTRIBUTORY;
341 default:
342 break;
343 }
344 return EXCPT_BENIGN;
345}
346
d6e8c854
NA		 347#define EXCPT_FAULT 0
348#define EXCPT_TRAP 1
349#define EXCPT_ABORT 2
350#define EXCPT_INTERRUPT 3
351
352static int exception_type(int vector)
353{
354 unsigned int mask;
355
356 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
357 return EXCPT_INTERRUPT;
358
359 mask = 1 << vector;
360
361 /* #DB is trap, as instruction watchpoints are handled elsewhere */
362 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
363 return EXCPT_TRAP;
364
365 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
366 return EXCPT_ABORT;
367
368 /* Reserved exceptions will result in fault */
369 return EXCPT_FAULT;
370}
371
3fd28fce 372static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 373 unsigned nr, bool has_error, u32 error_code,
374 bool reinject)
3fd28fce
ED		 375{
376 u32 prev_nr;
377 int class1, class2;
378
3842d135
AK		 379 kvm_make_request(KVM_REQ_EVENT, vcpu);
380
3fd28fce
ED		 381 if (!vcpu->arch.exception.pending) {
382 queue:
3ffb2468
NA		 383 if (has_error && !is_protmode(vcpu))
384 has_error = false;
3fd28fce
ED		 385 vcpu->arch.exception.pending = true;
386 vcpu->arch.exception.has_error_code = has_error;
387 vcpu->arch.exception.nr = nr;
388 vcpu->arch.exception.error_code = error_code;
3f0fd292 389 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 390 return;
391 }
392
393 /* to check exception */
394 prev_nr = vcpu->arch.exception.nr;
395 if (prev_nr == DF_VECTOR) {
396 /* triple fault -> shutdown */
a8eeb04a 397 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 398 return;
399 }
400 class1 = exception_class(prev_nr);
401 class2 = exception_class(nr);
402 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
403 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
404 /* generate double fault per SDM Table 5-5 */
405 vcpu->arch.exception.pending = true;
406 vcpu->arch.exception.has_error_code = true;
407 vcpu->arch.exception.nr = DF_VECTOR;
408 vcpu->arch.exception.error_code = 0;
409 } else
410 /* replace previous exception with a new one in a hope
411 that instruction re-execution will regenerate lost
412 exception */
413 goto queue;
414}
415
298101da
AK		 416void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
417{
ce7ddec4 418 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 419}
420EXPORT_SYMBOL_GPL(kvm_queue_exception);
421
ce7ddec4
JR		 422void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
423{
424 kvm_multiple_exception(vcpu, nr, false, 0, true);
425}
426EXPORT_SYMBOL_GPL(kvm_requeue_exception);
427
db8fcefa 428void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 429{
db8fcefa
AP		 430 if (err)
431 kvm_inject_gp(vcpu, 0);
432 else
433 kvm_x86_ops->skip_emulated_instruction(vcpu);
434}
435EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 436
6389ee94 437void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 438{
439 ++vcpu->stat.pf_guest;
6389ee94
AK		 440 vcpu->arch.cr2 = fault->address;
441 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 442}
27d6c865 443EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 444
ef54bcfe 445static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 446{
6389ee94
AK		 447 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
448 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 449 else
6389ee94 450 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 451
452 return fault->nested_page_fault;
d4f8cf66
JR		 453}
454
3419ffc8
SY		 455void kvm_inject_nmi(struct kvm_vcpu *vcpu)
456{
7460fb4a
AK		 457 atomic_inc(&vcpu->arch.nmi_queued);
458 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 459}
460EXPORT_SYMBOL_GPL(kvm_inject_nmi);
461
298101da
AK		 462void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
463{
ce7ddec4 464 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 465}
466EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
467
ce7ddec4
JR		 468void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
469{
470 kvm_multiple_exception(vcpu, nr, true, error_code, true);
471}
472EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
473
0a79b009
AK		 474/*
475 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
476 * a #GP and return false.
477 */
478bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 479{
0a79b009
AK		 480 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
481 return true;
482 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
483 return false;
298101da 484}
0a79b009 485EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 486
16f8a6f9
NA		 487bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
488{
489 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
490 return true;
491
492 kvm_queue_exception(vcpu, UD_VECTOR);
493 return false;
494}
495EXPORT_SYMBOL_GPL(kvm_require_dr);
496
ec92fe44
JR		 497/*
498 * This function will be used to read from the physical memory of the currently
54bf36aa 499 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 500 * can read from guest physical or from the guest's guest physical memory.
501 */
502int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
503 gfn_t ngfn, void *data, int offset, int len,
504 u32 access)
505{
54987b7a 506 struct x86_exception exception;
ec92fe44
JR		 507 gfn_t real_gfn;
508 gpa_t ngpa;
509
510 ngpa = gfn_to_gpa(ngfn);
54987b7a 511 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 512 if (real_gfn == UNMAPPED_GVA)
513 return -EFAULT;
514
515 real_gfn = gpa_to_gfn(real_gfn);
516
54bf36aa 517 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 518}
519EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
520
69b0049a 521static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 522 void *data, int offset, int len, u32 access)
523{
524 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
525 data, offset, len, access);
526}
527
a03490ed
CO		 528/*
529 * Load the pae pdptrs. Return true is they are all valid.
530 */
ff03a073 531int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 532{
533 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
534 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
535 int i;
536 int ret;
ff03a073 537 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 538
ff03a073
JR		 539 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
540 offset * sizeof(u64), sizeof(pdpte),
541 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 542 if (ret < 0) {
543 ret = 0;
544 goto out;
545 }
546 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 547 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 548 (pdpte[i] &
549 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 550 ret = 0;
551 goto out;
552 }
553 }
554 ret = 1;
555
ff03a073 556 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 557 __set_bit(VCPU_EXREG_PDPTR,
558 (unsigned long *)&vcpu->arch.regs_avail);
559 __set_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 561out:
a03490ed
CO		 562
563 return ret;
564}
cc4b6871 565EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 566
d835dfec
AK		 567static bool pdptrs_changed(struct kvm_vcpu *vcpu)
568{
ff03a073 569 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 570 bool changed = true;
3d06b8bf
JR		 571 int offset;
572 gfn_t gfn;
d835dfec
AK		 573 int r;
574
575 if (is_long_mode(vcpu) || !is_pae(vcpu))
576 return false;
577
6de4f3ad
AK		 578 if (!test_bit(VCPU_EXREG_PDPTR,
579 (unsigned long *)&vcpu->arch.regs_avail))
580 return true;
581
9f8fe504
AK		 582 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
583 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 584 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
585 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 586 if (r < 0)
587 goto out;
ff03a073 588 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 589out:
d835dfec
AK		 590
591 return changed;
592}
593
49a9b07e 594int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 595{
aad82703 596 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 597 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 598
f9a48e6a
AK		 599 cr0 |= X86_CR0_ET;
600
ab344828 601#ifdef CONFIG_X86_64
0f12244f
GN		 602 if (cr0 & 0xffffffff00000000UL)
603 return 1;
ab344828
GN		 604#endif
605
606 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 607
0f12244f
GN		 608 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
609 return 1;
a03490ed 610
0f12244f
GN		 611 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
612 return 1;
a03490ed
CO		 613
614 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
615#ifdef CONFIG_X86_64
f6801dff 616 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 617 int cs_db, cs_l;
618
0f12244f
GN		 619 if (!is_pae(vcpu))
620 return 1;
a03490ed 621 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 622 if (cs_l)
623 return 1;
a03490ed
CO		 624 } else
625#endif
ff03a073 626 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 627 kvm_read_cr3(vcpu)))
0f12244f 628 return 1;
a03490ed
CO		 629 }
630
ad756a16
MJ		 631 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
632 return 1;
633
a03490ed 634 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 635
d170c419 636 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 637 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 638 kvm_async_pf_hash_reset(vcpu);
639 }
e5f3f027 640
aad82703
SY		 641 if ((cr0 ^ old_cr0) & update_bits)
642 kvm_mmu_reset_context(vcpu);
b18d5431 643
879ae188
LE		 644 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
645 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
646 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 647 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
648
0f12244f
GN		 649 return 0;
650}
2d3ad1f4 651EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 652
2d3ad1f4 653void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 654{
49a9b07e 655 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 656}
2d3ad1f4 657EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 658
42bdf991
MT		 659static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
660{
661 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
662 !vcpu->guest_xcr0_loaded) {
663 /* kvm_set_xcr() also depends on this */
664 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
665 vcpu->guest_xcr0_loaded = 1;
666 }
667}
668
669static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
670{
671 if (vcpu->guest_xcr0_loaded) {
672 if (vcpu->arch.xcr0 != host_xcr0)
673 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
674 vcpu->guest_xcr0_loaded = 0;
675 }
676}
677
69b0049a 678static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 679{
56c103ec
LJ		 680 u64 xcr0 = xcr;
681 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 682 u64 valid_bits;
2acf923e
DC		 683
684 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
685 if (index != XCR_XFEATURE_ENABLED_MASK)
686 return 1;
d91cab78 687 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 688 return 1;
d91cab78 689 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 690 return 1;
46c34cb0
PB		 691
692 /*
693 * Do not allow the guest to set bits that we do not support
694 * saving. However, xcr0 bit 0 is always set, even if the
695 * emulated CPU does not support XSAVE (see fx_init).
696 */
d91cab78 697 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 698 if (xcr0 & ~valid_bits)
2acf923e 699 return 1;
46c34cb0 700
d91cab78
DH		 701 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
702 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 703 return 1;
704
d91cab78
DH		 705 if (xcr0 & XFEATURE_MASK_AVX512) {
706 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 707 return 1;
d91cab78 708 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 709 return 1;
710 }
2acf923e 711 vcpu->arch.xcr0 = xcr0;
56c103ec 712
d91cab78 713 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 714 kvm_update_cpuid(vcpu);
2acf923e
DC		 715 return 0;
716}
717
718int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
719{
764bcbc5
Z		 720 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
721 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 722 kvm_inject_gp(vcpu, 0);
723 return 1;
724 }
725 return 0;
726}
727EXPORT_SYMBOL_GPL(kvm_set_xcr);
728
a83b29c6 729int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 730{
fc78f519 731 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 732 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 733 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 734
0f12244f
GN		 735 if (cr4 & CR4_RESERVED_BITS)
736 return 1;
a03490ed 737
2acf923e
DC		 738 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
739 return 1;
740
c68b734f
YW		 741 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
742 return 1;
743
97ec8c06
FW		 744 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
745 return 1;
746
afcbf13f 747 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 748 return 1;
749
b9baba86
HH		 750 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
751 return 1;
752
a03490ed 753 if (is_long_mode(vcpu)) {
0f12244f
GN		 754 if (!(cr4 & X86_CR4_PAE))
755 return 1;
a2edf57f
AK		 756 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
757 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 758 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
759 kvm_read_cr3(vcpu)))
0f12244f
GN		 760 return 1;
761
ad756a16
MJ		 762 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
763 if (!guest_cpuid_has_pcid(vcpu))
764 return 1;
765
766 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
767 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
768 return 1;
769 }
770
5e1746d6 771 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 772 return 1;
a03490ed 773
ad756a16
MJ		 774 if (((cr4 ^ old_cr4) & pdptr_bits) ||
775 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 776 kvm_mmu_reset_context(vcpu);
0f12244f 777
b9baba86 778 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 779 kvm_update_cpuid(vcpu);
2acf923e 780
0f12244f
GN		 781 return 0;
782}
2d3ad1f4 783EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 784
2390218b 785int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 786{
ac146235 787#ifdef CONFIG_X86_64
9d88fca7 788 cr3 &= ~CR3_PCID_INVD;
ac146235 789#endif
9d88fca7 790
9f8fe504 791 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 792 kvm_mmu_sync_roots(vcpu);
77c3913b 793 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 794 return 0;
d835dfec
AK		 795 }
796
a03490ed 797 if (is_long_mode(vcpu)) {
d9f89b88
JK		 798 if (cr3 & CR3_L_MODE_RESERVED_BITS)
799 return 1;
800 } else if (is_pae(vcpu) && is_paging(vcpu) &&
801 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 802 return 1;
a03490ed 803
0f12244f 804 vcpu->arch.cr3 = cr3;
aff48baa 805 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 806 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 807 return 0;
808}
2d3ad1f4 809EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 810
eea1cff9 811int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 812{
0f12244f
GN		 813 if (cr8 & CR8_RESERVED_BITS)
814 return 1;
35754c98 815 if (lapic_in_kernel(vcpu))
a03490ed
CO		 816 kvm_lapic_set_tpr(vcpu, cr8);
817 else
ad312c7c 818 vcpu->arch.cr8 = cr8;
0f12244f
GN		 819 return 0;
820}
2d3ad1f4 821EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 822
2d3ad1f4 823unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 824{
35754c98 825 if (lapic_in_kernel(vcpu))
a03490ed
CO		 826 return kvm_lapic_get_cr8(vcpu);
827 else
ad312c7c 828 return vcpu->arch.cr8;
a03490ed 829}
2d3ad1f4 830EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 831
ae561ede
NA		 832static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
833{
834 int i;
835
836 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
837 for (i = 0; i < KVM_NR_DB_REGS; i++)
838 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
839 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
840 }
841}
842
73aaf249
JK		 843static void kvm_update_dr6(struct kvm_vcpu *vcpu)
844{
845 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
846 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
847}
848
c8639010
JK		 849static void kvm_update_dr7(struct kvm_vcpu *vcpu)
850{
851 unsigned long dr7;
852
853 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
854 dr7 = vcpu->arch.guest_debug_dr7;
855 else
856 dr7 = vcpu->arch.dr7;
857 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 858 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
859 if (dr7 & DR7_BP_EN_MASK)
860 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 861}
862
6f43ed01
NA		 863static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
864{
865 u64 fixed = DR6_FIXED_1;
866
867 if (!guest_cpuid_has_rtm(vcpu))
868 fixed |= DR6_RTM;
869 return fixed;
870}
871
338dbc97 872static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 873{
874 switch (dr) {
875 case 0 ... 3:
876 vcpu->arch.db[dr] = val;
877 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
878 vcpu->arch.eff_db[dr] = val;
879 break;
880 case 4:
020df079
GN		 881 /* fall through */
882 case 6:
338dbc97
GN		 883 if (val & 0xffffffff00000000ULL)
884 return -1; /* #GP */
6f43ed01 885 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 886 kvm_update_dr6(vcpu);
020df079
GN		 887 break;
888 case 5:
020df079
GN		 889 /* fall through */
890 default: /* 7 */
338dbc97
GN		 891 if (val & 0xffffffff00000000ULL)
892 return -1; /* #GP */
020df079 893 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 894 kvm_update_dr7(vcpu);
020df079
GN		 895 break;
896 }
897
898 return 0;
899}
338dbc97
GN		 900
901int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
902{
16f8a6f9 903 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 904 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 905 return 1;
906 }
907 return 0;
338dbc97 908}
020df079
GN		 909EXPORT_SYMBOL_GPL(kvm_set_dr);
910
16f8a6f9 911int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 912{
913 switch (dr) {
914 case 0 ... 3:
915 *val = vcpu->arch.db[dr];
916 break;
917 case 4:
020df079
GN		 918 /* fall through */
919 case 6:
73aaf249
JK		 920 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
921 *val = vcpu->arch.dr6;
922 else
923 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 924 break;
925 case 5:
020df079
GN		 926 /* fall through */
927 default: /* 7 */
928 *val = vcpu->arch.dr7;
929 break;
930 }
338dbc97
GN		 931 return 0;
932}
020df079
GN		 933EXPORT_SYMBOL_GPL(kvm_get_dr);
934
022cd0e8
AK		 935bool kvm_rdpmc(struct kvm_vcpu *vcpu)
936{
937 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
938 u64 data;
939 int err;
940
c6702c9d 941 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 942 if (err)
943 return err;
944 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
945 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
946 return err;
947}
948EXPORT_SYMBOL_GPL(kvm_rdpmc);
949
043405e1
CO		 950/*
951 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
952 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
953 *
954 * This list is modified at module load time to reflect the
e3267cbb 955 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 956 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
957 * may depend on host virtualization features rather than host cpu features.
043405e1 958 */
e3267cbb 959
043405e1
CO		 960static u32 msrs_to_save[] = {
961 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 962 MSR_STAR,
043405e1
CO		 963#ifdef CONFIG_X86_64
964 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
965#endif
b3897a49 966 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 967 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 968};
969
970static unsigned num_msrs_to_save;
971
62ef68bb
PB		 972static u32 emulated_msrs[] = {
973 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
974 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
975 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
976 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 977 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
978 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 979 HV_X64_MSR_RESET,
11c4b1ca 980 HV_X64_MSR_VP_INDEX,
9eec50b8 981 HV_X64_MSR_VP_RUNTIME,
5c919412 982 HV_X64_MSR_SCONTROL,
1f4b34f8 983 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 984 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
985 MSR_KVM_PV_EOI_EN,
986
ba904635 987 MSR_IA32_TSC_ADJUST,
a3e06bbe 988 MSR_IA32_TSCDEADLINE,
043405e1 989 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 990 MSR_IA32_MCG_STATUS,
991 MSR_IA32_MCG_CTL,
c45dcc71 992 MSR_IA32_MCG_EXT_CTL,
64d60670 993 MSR_IA32_SMBASE,
043405e1
CO		 994};
995
62ef68bb
PB		 996static unsigned num_emulated_msrs;
997
384bb783 998bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 999{
b69e8cae 1000 if (efer & efer_reserved_bits)
384bb783 1001 return false;
15c4a640 1002
1b2fd70c
AG		 1003 if (efer & EFER_FFXSR) {
1004 struct kvm_cpuid_entry2 *feat;
1005
1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1007 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1008 return false;
1b2fd70c
AG		 1009 }
1010
d8017474
AG		 1011 if (efer & EFER_SVME) {
1012 struct kvm_cpuid_entry2 *feat;
1013
1014 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1015 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1016 return false;
d8017474
AG		 1017 }
1018
384bb783
JK		 1019 return true;
1020}
1021EXPORT_SYMBOL_GPL(kvm_valid_efer);
1022
1023static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1024{
1025 u64 old_efer = vcpu->arch.efer;
1026
1027 if (!kvm_valid_efer(vcpu, efer))
1028 return 1;
1029
1030 if (is_paging(vcpu)
1031 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1032 return 1;
1033
15c4a640 1034 efer &= ~EFER_LMA;
f6801dff 1035 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1036
a3d204e2
SY		 1037 kvm_x86_ops->set_efer(vcpu, efer);
1038
aad82703
SY		 1039 /* Update reserved bits */
1040 if ((efer ^ old_efer) & EFER_NX)
1041 kvm_mmu_reset_context(vcpu);
1042
b69e8cae 1043 return 0;
15c4a640
CO		 1044}
1045
f2b4b7dd
JR		 1046void kvm_enable_efer_bits(u64 mask)
1047{
1048 efer_reserved_bits &= ~mask;
1049}
1050EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1051
15c4a640
CO		 1052/*
1053 * Writes msr value into into the appropriate "register".
1054 * Returns 0 on success, non-0 otherwise.
1055 * Assumes vcpu_load() was already called.
1056 */
8fe8ab46 1057int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1058{
854e8bb1
NA		 1059 switch (msr->index) {
1060 case MSR_FS_BASE:
1061 case MSR_GS_BASE:
1062 case MSR_KERNEL_GS_BASE:
1063 case MSR_CSTAR:
1064 case MSR_LSTAR:
1065 if (is_noncanonical_address(msr->data))
1066 return 1;
1067 break;
1068 case MSR_IA32_SYSENTER_EIP:
1069 case MSR_IA32_SYSENTER_ESP:
1070 /*
1071 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1072 * non-canonical address is written on Intel but not on
1073 * AMD (which ignores the top 32-bits, because it does
1074 * not implement 64-bit SYSENTER).
1075 *
1076 * 64-bit code should hence be able to write a non-canonical
1077 * value on AMD. Making the address canonical ensures that
1078 * vmentry does not fail on Intel after writing a non-canonical
1079 * value, and that something deterministic happens if the guest
1080 * invokes 64-bit SYSENTER.
1081 */
1082 msr->data = get_canonical(msr->data);
1083 }
8fe8ab46 1084 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1085}
854e8bb1 1086EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1087
313a3dc7
CO		 1088/*
1089 * Adapt set_msr() to msr_io()'s calling convention
1090 */
609e36d3
PB		 1091static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1092{
1093 struct msr_data msr;
1094 int r;
1095
1096 msr.index = index;
1097 msr.host_initiated = true;
1098 r = kvm_get_msr(vcpu, &msr);
1099 if (r)
1100 return r;
1101
1102 *data = msr.data;
1103 return 0;
1104}
1105
313a3dc7
CO		 1106static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1107{
8fe8ab46
WA		 1108 struct msr_data msr;
1109
1110 msr.data = *data;
1111 msr.index = index;
1112 msr.host_initiated = true;
1113 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1114}
1115
16e8d74d
MT		 1116#ifdef CONFIG_X86_64
1117struct pvclock_gtod_data {
1118 seqcount_t seq;
1119
1120 struct { /* extract of a clocksource struct */
1121 int vclock_mode;
1122 cycle_t cycle_last;
1123 cycle_t mask;
1124 u32 mult;
1125 u32 shift;
1126 } clock;
1127
cbcf2dd3
TG		 1128 u64 boot_ns;
1129 u64 nsec_base;
16e8d74d
MT		 1130};
1131
1132static struct pvclock_gtod_data pvclock_gtod_data;
1133
1134static void update_pvclock_gtod(struct timekeeper *tk)
1135{
1136 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1137 u64 boot_ns;
1138
876e7881 1139 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1140
1141 write_seqcount_begin(&vdata->seq);
1142
1143 /* copy pvclock gtod data */
876e7881
PZ		 1144 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1145 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1146 vdata->clock.mask = tk->tkr_mono.mask;
1147 vdata->clock.mult = tk->tkr_mono.mult;
1148 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1149
cbcf2dd3 1150 vdata->boot_ns = boot_ns;
876e7881 1151 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1152
1153 write_seqcount_end(&vdata->seq);
1154}
1155#endif
1156
bab5bb39
NK		 1157void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1158{
1159 /*
1160 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1161 * vcpu_enter_guest. This function is only called from
1162 * the physical CPU that is running vcpu.
1163 */
1164 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1165}
16e8d74d 1166
18068523
GOC		 1167static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1168{
9ed3c444
AK		 1169 int version;
1170 int r;
50d0a0f9 1171 struct pvclock_wall_clock wc;
87aeb54f 1172 struct timespec64 boot;
18068523
GOC		 1173
1174 if (!wall_clock)
1175 return;
1176
9ed3c444
AK		 1177 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1178 if (r)
1179 return;
1180
1181 if (version & 1)
1182 ++version; /* first time write, random junk */
1183
1184 ++version;
18068523 1185
1dab1345
NK		 1186 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1187 return;
18068523 1188
50d0a0f9
GH		 1189 /*
1190 * The guest calculates current wall clock time by adding
34c238a1 1191 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1192 * wall clock specified here. guest system time equals host
1193 * system time for us, thus we must fill in host boot time here.
1194 */
87aeb54f 1195 getboottime64(&boot);
50d0a0f9 1196
4b648665 1197 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1198 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1199 boot = timespec64_sub(boot, ts);
4b648665 1200 }
87aeb54f 1201 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1202 wc.nsec = boot.tv_nsec;
1203 wc.version = version;
18068523
GOC		 1204
1205 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1206
1207 version++;
1208 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1209}
1210
50d0a0f9
GH		 1211static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1212{
b51012de
PB		 1213 do_shl32_div32(dividend, divisor);
1214 return dividend;
50d0a0f9
GH		 1215}
1216
3ae13faa 1217static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1218 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1219{
5f4e3f88 1220 uint64_t scaled64;
50d0a0f9
GH		 1221 int32_t shift = 0;
1222 uint64_t tps64;
1223 uint32_t tps32;
1224
3ae13faa
PB		 1225 tps64 = base_hz;
1226 scaled64 = scaled_hz;
50933623 1227 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1228 tps64 >>= 1;
1229 shift--;
1230 }
1231
1232 tps32 = (uint32_t)tps64;
50933623
JK		 1233 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1234 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1235 scaled64 >>= 1;
1236 else
1237 tps32 <<= 1;
50d0a0f9
GH		 1238 shift++;
1239 }
1240
5f4e3f88
ZA		 1241 *pshift = shift;
1242 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1243
3ae13faa
PB		 1244 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1245 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1246}
1247
d828199e 1248#ifdef CONFIG_X86_64
16e8d74d 1249static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1250#endif
16e8d74d 1251
c8076604 1252static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1253static unsigned long max_tsc_khz;
c8076604 1254
cc578287 1255static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1256{
cc578287
ZA		 1257 u64 v = (u64)khz * (1000000 + ppm);
1258 do_div(v, 1000000);
1259 return v;
1e993611
JR		 1260}
1261
381d585c
HZ		 1262static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1263{
1264 u64 ratio;
1265
1266 /* Guest TSC same frequency as host TSC? */
1267 if (!scale) {
1268 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1269 return 0;
1270 }
1271
1272 /* TSC scaling supported? */
1273 if (!kvm_has_tsc_control) {
1274 if (user_tsc_khz > tsc_khz) {
1275 vcpu->arch.tsc_catchup = 1;
1276 vcpu->arch.tsc_always_catchup = 1;
1277 return 0;
1278 } else {
1279 WARN(1, "user requested TSC rate below hardware speed\n");
1280 return -1;
1281 }
1282 }
1283
1284 /* TSC scaling required - calculate ratio */
1285 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1286 user_tsc_khz, tsc_khz);
1287
1288 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1289 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1290 user_tsc_khz);
1291 return -1;
1292 }
1293
1294 vcpu->arch.tsc_scaling_ratio = ratio;
1295 return 0;
1296}
1297
4941b8cb 1298static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1299{
cc578287
ZA		 1300 u32 thresh_lo, thresh_hi;
1301 int use_scaling = 0;
217fc9cf 1302
03ba32ca 1303 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1304 if (user_tsc_khz == 0) {
ad721883
HZ		 1305 /* set tsc_scaling_ratio to a safe value */
1306 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1307 return -1;
ad721883 1308 }
03ba32ca 1309
c285545f 1310 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1311 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1312 &vcpu->arch.virtual_tsc_shift,
1313 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1314 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1315
1316 /*
1317 * Compute the variation in TSC rate which is acceptable
1318 * within the range of tolerance and decide if the
1319 * rate being applied is within that bounds of the hardware
1320 * rate. If so, no scaling or compensation need be done.
1321 */
1322 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1323 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1324 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1325 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1326 use_scaling = 1;
1327 }
4941b8cb 1328 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1329}
1330
1331static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1332{
e26101b1 1333 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1334 vcpu->arch.virtual_tsc_mult,
1335 vcpu->arch.virtual_tsc_shift);
e26101b1 1336 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1337 return tsc;
1338}
1339
69b0049a 1340static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1341{
1342#ifdef CONFIG_X86_64
1343 bool vcpus_matched;
b48aa97e
MT		 1344 struct kvm_arch *ka = &vcpu->kvm->arch;
1345 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1346
1347 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1348 atomic_read(&vcpu->kvm->online_vcpus));
1349
7f187922
MT		 1350 /*
1351 * Once the masterclock is enabled, always perform request in
1352 * order to update it.
1353 *
1354 * In order to enable masterclock, the host clocksource must be TSC
1355 * and the vcpus need to have matched TSCs. When that happens,
1356 * perform request to enable masterclock.
1357 */
1358 if (ka->use_master_clock ||
1359 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1360 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1361
1362 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1363 atomic_read(&vcpu->kvm->online_vcpus),
1364 ka->use_master_clock, gtod->clock.vclock_mode);
1365#endif
1366}
1367
ba904635
WA		 1368static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1369{
3e3f5026 1370 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1371 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1372}
1373
35181e86
HZ		 1374/*
1375 * Multiply tsc by a fixed point number represented by ratio.
1376 *
1377 * The most significant 64-N bits (mult) of ratio represent the
1378 * integral part of the fixed point number; the remaining N bits
1379 * (frac) represent the fractional part, ie. ratio represents a fixed
1380 * point number (mult + frac * 2^(-N)).
1381 *
1382 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1383 */
1384static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1385{
1386 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1387}
1388
1389u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1390{
1391 u64 _tsc = tsc;
1392 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1393
1394 if (ratio != kvm_default_tsc_scaling_ratio)
1395 _tsc = __scale_tsc(ratio, tsc);
1396
1397 return _tsc;
1398}
1399EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1400
07c1419a
HZ		 1401static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1402{
1403 u64 tsc;
1404
1405 tsc = kvm_scale_tsc(vcpu, rdtsc());
1406
1407 return target_tsc - tsc;
1408}
1409
4ba76538
HZ		 1410u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1411{
1412 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1413}
1414EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1415
a545ab6a
LC		 1416static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1417{
1418 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1419 vcpu->arch.tsc_offset = offset;
1420}
1421
8fe8ab46 1422void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1423{
1424 struct kvm *kvm = vcpu->kvm;
f38e098f 1425 u64 offset, ns, elapsed;
99e3e30a 1426 unsigned long flags;
02626b6a 1427 s64 usdiff;
b48aa97e 1428 bool matched;
0d3da0d2 1429 bool already_matched;
8fe8ab46 1430 u64 data = msr->data;
99e3e30a 1431
038f8c11 1432 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1433 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1434 ns = get_kernel_ns();
f38e098f 1435 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1436
03ba32ca 1437 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1438 int faulted = 0;
1439
03ba32ca
MT		 1440 /* n.b - signed multiplication and division required */
1441 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1442#ifdef CONFIG_X86_64
03ba32ca 1443 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1444#else
03ba32ca 1445 /* do_div() only does unsigned */
8915aa27
MT		 1446 asm("1: idivl %[divisor]\n"
1447 "2: xor %%edx, %%edx\n"
1448 " movl $0, %[faulted]\n"
1449 "3:\n"
1450 ".section .fixup,\"ax\"\n"
1451 "4: movl $1, %[faulted]\n"
1452 " jmp 3b\n"
1453 ".previous\n"
1454
1455 _ASM_EXTABLE(1b, 4b)
1456
1457 : "=A"(usdiff), [faulted] "=r" (faulted)
1458 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1459
5d3cb0f6 1460#endif
03ba32ca
MT		 1461 do_div(elapsed, 1000);
1462 usdiff -= elapsed;
1463 if (usdiff < 0)
1464 usdiff = -usdiff;
8915aa27
MT		 1465
1466 /* idivl overflow => difference is larger than USEC_PER_SEC */
1467 if (faulted)
1468 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1469 } else
1470 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1471
1472 /*
5d3cb0f6
ZA		 1473 * Special case: TSC write with a small delta (1 second) of virtual
1474 * cycle time against real time is interpreted as an attempt to
1475 * synchronize the CPU.
1476 *
1477 * For a reliable TSC, we can match TSC offsets, and for an unstable
1478 * TSC, we add elapsed time in this computation. We could let the
1479 * compensation code attempt to catch up if we fall behind, but
1480 * it's better to try to match offsets from the beginning.
1481 */
02626b6a 1482 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1483 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1484 if (!check_tsc_unstable()) {
e26101b1 1485 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1486 pr_debug("kvm: matched tsc offset for %llu\n", data);
1487 } else {
857e4099 1488 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1489 data += delta;
07c1419a 1490 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1491 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1492 }
b48aa97e 1493 matched = true;
0d3da0d2 1494 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1495 } else {
1496 /*
1497 * We split periods of matched TSC writes into generations.
1498 * For each generation, we track the original measured
1499 * nanosecond time, offset, and write, so if TSCs are in
1500 * sync, we can match exact offset, and if not, we can match
4a969980 1501 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1502 *
1503 * These values are tracked in kvm->arch.cur_xxx variables.
1504 */
1505 kvm->arch.cur_tsc_generation++;
1506 kvm->arch.cur_tsc_nsec = ns;
1507 kvm->arch.cur_tsc_write = data;
1508 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1509 matched = false;
0d3da0d2 1510 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1511 kvm->arch.cur_tsc_generation, data);
f38e098f 1512 }
e26101b1
ZA		 1513
1514 /*
1515 * We also track th most recent recorded KHZ, write and time to
1516 * allow the matching interval to be extended at each write.
1517 */
f38e098f
ZA		 1518 kvm->arch.last_tsc_nsec = ns;
1519 kvm->arch.last_tsc_write = data;
5d3cb0f6 1520 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1521
b183aa58 1522 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1523
1524 /* Keep track of which generation this VCPU has synchronized to */
1525 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1526 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1527 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1528
ba904635
WA		 1529 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1530 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1531 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1532 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1533
1534 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1535 if (!matched) {
b48aa97e 1536 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1537 } else if (!already_matched) {
1538 kvm->arch.nr_vcpus_matched_tsc++;
1539 }
b48aa97e
MT		 1540
1541 kvm_track_tsc_matching(vcpu);
1542 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1543}
e26101b1 1544
99e3e30a
ZA		 1545EXPORT_SYMBOL_GPL(kvm_write_tsc);
1546
58ea6767
HZ		 1547static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1548 s64 adjustment)
1549{
1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1551}
1552
1553static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1554{
1555 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1556 WARN_ON(adjustment < 0);
1557 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1558 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1559}
1560
d828199e
MT		 1561#ifdef CONFIG_X86_64
1562
1563static cycle_t read_tsc(void)
1564{
03b9730b
AL		 1565 cycle_t ret = (cycle_t)rdtsc_ordered();
1566 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1567
1568 if (likely(ret >= last))
1569 return ret;
1570
1571 /*
1572 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1573 * predictable (it's just a function of time and the likely is
d828199e
MT		 1574 * very likely) and there's a data dependence, so force GCC
1575 * to generate a branch instead. I don't barrier() because
1576 * we don't actually need a barrier, and if this function
1577 * ever gets inlined it will generate worse code.
1578 */
1579 asm volatile ("");
1580 return last;
1581}
1582
1583static inline u64 vgettsc(cycle_t *cycle_now)
1584{
1585 long v;
1586 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1587
1588 *cycle_now = read_tsc();
1589
1590 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1591 return v * gtod->clock.mult;
1592}
1593
cbcf2dd3 1594static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1595{
cbcf2dd3 1596 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1597 unsigned long seq;
d828199e 1598 int mode;
cbcf2dd3 1599 u64 ns;
d828199e 1600
d828199e
MT		 1601 do {
1602 seq = read_seqcount_begin(&gtod->seq);
1603 mode = gtod->clock.vclock_mode;
cbcf2dd3 1604 ns = gtod->nsec_base;
d828199e
MT		 1605 ns += vgettsc(cycle_now);
1606 ns >>= gtod->clock.shift;
cbcf2dd3 1607 ns += gtod->boot_ns;
d828199e 1608 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1609 *t = ns;
d828199e
MT		 1610
1611 return mode;
1612}
1613
1614/* returns true if host is using tsc clocksource */
1615static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1616{
d828199e
MT		 1617 /* checked again under seqlock below */
1618 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1619 return false;
1620
cbcf2dd3 1621 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1622}
1623#endif
1624
1625/*
1626 *
b48aa97e
MT		 1627 * Assuming a stable TSC across physical CPUS, and a stable TSC
1628 * across virtual CPUs, the following condition is possible.
1629 * Each numbered line represents an event visible to both
d828199e
MT		 1630 * CPUs at the next numbered event.
1631 *
1632 * "timespecX" represents host monotonic time. "tscX" represents
1633 * RDTSC value.
1634 *
1635 * VCPU0 on CPU0 | VCPU1 on CPU1
1636 *
1637 * 1. read timespec0,tsc0
1638 * 2. | timespec1 = timespec0 + N
1639 * | tsc1 = tsc0 + M
1640 * 3. transition to guest | transition to guest
1641 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1642 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1643 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1644 *
1645 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1646 *
1647 * - ret0 < ret1
1648 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1649 * ...
1650 * - 0 < N - M => M < N
1651 *
1652 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1653 * always the case (the difference between two distinct xtime instances
1654 * might be smaller then the difference between corresponding TSC reads,
1655 * when updating guest vcpus pvclock areas).
1656 *
1657 * To avoid that problem, do not allow visibility of distinct
1658 * system_timestamp/tsc_timestamp values simultaneously: use a master
1659 * copy of host monotonic time values. Update that master copy
1660 * in lockstep.
1661 *
b48aa97e 1662 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1663 *
1664 */
1665
1666static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1667{
1668#ifdef CONFIG_X86_64
1669 struct kvm_arch *ka = &kvm->arch;
1670 int vclock_mode;
b48aa97e
MT		 1671 bool host_tsc_clocksource, vcpus_matched;
1672
1673 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1674 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1675
1676 /*
1677 * If the host uses TSC clock, then passthrough TSC as stable
1678 * to the guest.
1679 */
b48aa97e 1680 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1681 &ka->master_kernel_ns,
1682 &ka->master_cycle_now);
1683
16a96021 1684 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1685 && !backwards_tsc_observed
1686 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1687
d828199e
MT		 1688 if (ka->use_master_clock)
1689 atomic_set(&kvm_guest_has_master_clock, 1);
1690
1691 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1692 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1693 vcpus_matched);
d828199e
MT		 1694#endif
1695}
1696
2860c4b1
PB		 1697void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1698{
1699 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1700}
1701
2e762ff7
MT		 1702static void kvm_gen_update_masterclock(struct kvm *kvm)
1703{
1704#ifdef CONFIG_X86_64
1705 int i;
1706 struct kvm_vcpu *vcpu;
1707 struct kvm_arch *ka = &kvm->arch;
1708
1709 spin_lock(&ka->pvclock_gtod_sync_lock);
1710 kvm_make_mclock_inprogress_request(kvm);
1711 /* no guest entries from this point */
1712 pvclock_update_vm_gtod_copy(kvm);
1713
1714 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1715 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1716
1717 /* guest entries allowed */
1718 kvm_for_each_vcpu(i, vcpu, kvm)
1719 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1720
1721 spin_unlock(&ka->pvclock_gtod_sync_lock);
1722#endif
1723}
1724
34c238a1 1725static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1726{
78db6a50 1727 unsigned long flags, tgt_tsc_khz;
18068523 1728 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1729 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1730 s64 kernel_ns;
d828199e 1731 u64 tsc_timestamp, host_tsc;
0b79459b 1732 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1733 u8 pvclock_flags;
d828199e
MT		 1734 bool use_master_clock;
1735
1736 kernel_ns = 0;
1737 host_tsc = 0;
18068523 1738
d828199e
MT		 1739 /*
1740 * If the host uses TSC clock, then passthrough TSC as stable
1741 * to the guest.
1742 */
1743 spin_lock(&ka->pvclock_gtod_sync_lock);
1744 use_master_clock = ka->use_master_clock;
1745 if (use_master_clock) {
1746 host_tsc = ka->master_cycle_now;
1747 kernel_ns = ka->master_kernel_ns;
1748 }
1749 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1750
1751 /* Keep irq disabled to prevent changes to the clock */
1752 local_irq_save(flags);
78db6a50
PB		 1753 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1754 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1755 local_irq_restore(flags);
1756 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1757 return 1;
1758 }
d828199e 1759 if (!use_master_clock) {
4ea1636b 1760 host_tsc = rdtsc();
d828199e
MT		 1761 kernel_ns = get_kernel_ns();
1762 }
1763
4ba76538 1764 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1765
c285545f
ZA		 1766 /*
1767 * We may have to catch up the TSC to match elapsed wall clock
1768 * time for two reasons, even if kvmclock is used.
1769 * 1) CPU could have been running below the maximum TSC rate
1770 * 2) Broken TSC compensation resets the base at each VCPU
1771 * entry to avoid unknown leaps of TSC even when running
1772 * again on the same CPU. This may cause apparent elapsed
1773 * time to disappear, and the guest to stand still or run
1774 * very slowly.
1775 */
1776 if (vcpu->tsc_catchup) {
1777 u64 tsc = compute_guest_tsc(v, kernel_ns);
1778 if (tsc > tsc_timestamp) {
f1e2b260 1779 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1780 tsc_timestamp = tsc;
1781 }
50d0a0f9
GH		 1782 }
1783
18068523
GOC		 1784 local_irq_restore(flags);
1785
0b79459b 1786 if (!vcpu->pv_time_enabled)
c285545f 1787 return 0;
18068523 1788
78db6a50
PB		 1789 if (kvm_has_tsc_control)
1790 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1791
1792 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1793 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1794 &vcpu->hv_clock.tsc_shift,
1795 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1796 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1797 }
1798
1799 /* With all the info we got, fill in the values */
1d5f066e 1800 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1801 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1802 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1803
09a0c3f1
OH		 1804 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1805 &guest_hv_clock, sizeof(guest_hv_clock))))
1806 return 0;
1807
5dca0d91
RK		 1808 /* This VCPU is paused, but it's legal for a guest to read another
1809 * VCPU's kvmclock, so we really have to follow the specification where
1810 * it says that version is odd if data is being modified, and even after
1811 * it is consistent.
1812 *
1813 * Version field updates must be kept separate. This is because
1814 * kvm_write_guest_cached might use a "rep movs" instruction, and
1815 * writes within a string instruction are weakly ordered. So there
1816 * are three writes overall.
1817 *
1818 * As a small optimization, only write the version field in the first
1819 * and third write. The vcpu->pv_time cache is still valid, because the
1820 * version field is the first in the struct.
18068523 1821 */
5dca0d91
RK		 1822 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1823
1824 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1825 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1826 &vcpu->hv_clock,
1827 sizeof(vcpu->hv_clock.version));
1828
1829 smp_wmb();
78c0337a
MT		 1830
1831 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1832 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1833
1834 if (vcpu->pvclock_set_guest_stopped_request) {
1835 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1836 vcpu->pvclock_set_guest_stopped_request = false;
1837 }
1838
d828199e
MT		 1839 /* If the host uses TSC clocksource, then it is stable */
1840 if (use_master_clock)
1841 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1842
78c0337a
MT		 1843 vcpu->hv_clock.flags = pvclock_flags;
1844
ce1a5e60
DM		 1845 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1846
0b79459b
AH		 1847 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1848 &vcpu->hv_clock,
1849 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1850
1851 smp_wmb();
1852
1853 vcpu->hv_clock.version++;
1854 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1855 &vcpu->hv_clock,
1856 sizeof(vcpu->hv_clock.version));
8cfdc000 1857 return 0;
c8076604
GH		 1858}
1859
0061d53d
MT		 1860/*
1861 * kvmclock updates which are isolated to a given vcpu, such as
1862 * vcpu->cpu migration, should not allow system_timestamp from
1863 * the rest of the vcpus to remain static. Otherwise ntp frequency
1864 * correction applies to one vcpu's system_timestamp but not
1865 * the others.
1866 *
1867 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1868 * We need to rate-limit these requests though, as they can
1869 * considerably slow guests that have a large number of vcpus.
1870 * The time for a remote vcpu to update its kvmclock is bound
1871 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1872 */
1873
7e44e449
AJ		 1874#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1875
1876static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1877{
1878 int i;
7e44e449
AJ		 1879 struct delayed_work *dwork = to_delayed_work(work);
1880 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1881 kvmclock_update_work);
1882 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1883 struct kvm_vcpu *vcpu;
1884
1885 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1886 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1887 kvm_vcpu_kick(vcpu);
1888 }
1889}
1890
7e44e449
AJ		 1891static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1892{
1893 struct kvm *kvm = v->kvm;
1894
105b21bb 1895 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1896 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1897 KVMCLOCK_UPDATE_DELAY);
1898}
1899
332967a3
AJ		 1900#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1901
1902static void kvmclock_sync_fn(struct work_struct *work)
1903{
1904 struct delayed_work *dwork = to_delayed_work(work);
1905 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1906 kvmclock_sync_work);
1907 struct kvm *kvm = container_of(ka, struct kvm, arch);
1908
630994b3
MT		 1909 if (!kvmclock_periodic_sync)
1910 return;
1911
332967a3
AJ		 1912 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1913 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1914 KVMCLOCK_SYNC_PERIOD);
1915}
1916
890ca9ae 1917static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1918{
890ca9ae
HY		 1919 u64 mcg_cap = vcpu->arch.mcg_cap;
1920 unsigned bank_num = mcg_cap & 0xff;
1921
15c4a640 1922 switch (msr) {
15c4a640 1923 case MSR_IA32_MCG_STATUS:
890ca9ae 1924 vcpu->arch.mcg_status = data;
15c4a640 1925 break;
c7ac679c 1926 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1927 if (!(mcg_cap & MCG_CTL_P))
1928 return 1;
1929 if (data != 0 && data != ~(u64)0)
1930 return -1;
1931 vcpu->arch.mcg_ctl = data;
1932 break;
1933 default:
1934 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1935 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1936 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1937 /* only 0 or all 1s can be written to IA32_MCi_CTL
1938 * some Linux kernels though clear bit 10 in bank 4 to
1939 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1940 * this to avoid an uncatched #GP in the guest
1941 */
890ca9ae 1942 if ((offset & 0x3) == 0 &&
114be429 1943 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1944 return -1;
1945 vcpu->arch.mce_banks[offset] = data;
1946 break;
1947 }
1948 return 1;
1949 }
1950 return 0;
1951}
1952
ffde22ac
ES		 1953static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1954{
1955 struct kvm *kvm = vcpu->kvm;
1956 int lm = is_long_mode(vcpu);
1957 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1958 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1959 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1960 : kvm->arch.xen_hvm_config.blob_size_32;
1961 u32 page_num = data & ~PAGE_MASK;
1962 u64 page_addr = data & PAGE_MASK;
1963 u8 *page;
1964 int r;
1965
1966 r = -E2BIG;
1967 if (page_num >= blob_size)
1968 goto out;
1969 r = -ENOMEM;
ff5c2c03
SL		 1970 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1971 if (IS_ERR(page)) {
1972 r = PTR_ERR(page);
ffde22ac 1973 goto out;
ff5c2c03 1974 }
54bf36aa 1975 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1976 goto out_free;
1977 r = 0;
1978out_free:
1979 kfree(page);
1980out:
1981 return r;
1982}
1983
344d9588
GN		 1984static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1985{
1986 gpa_t gpa = data & ~0x3f;
1987
4a969980 1988 /* Bits 2:5 are reserved, Should be zero */
6adba527 1989 if (data & 0x3c)
344d9588
GN		 1990 return 1;
1991
1992 vcpu->arch.apf.msr_val = data;
1993
1994 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1995 kvm_clear_async_pf_completion_queue(vcpu);
1996 kvm_async_pf_hash_reset(vcpu);
1997 return 0;
1998 }
1999
8f964525
AH		 2000 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2001 sizeof(u32)))
344d9588
GN		 2002 return 1;
2003
6adba527 2004 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2005 kvm_async_pf_wakeup_all(vcpu);
2006 return 0;
2007}
2008
12f9a48f
GC		 2009static void kvmclock_reset(struct kvm_vcpu *vcpu)
2010{
0b79459b 2011 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2012}
2013
c9aaa895
GC		 2014static void record_steal_time(struct kvm_vcpu *vcpu)
2015{
2016 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2017 return;
2018
2019 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2020 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2021 return;
2022
35f3fae1
WL		 2023 if (vcpu->arch.st.steal.version & 1)
2024 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2025
2026 vcpu->arch.st.steal.version += 1;
2027
2028 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2029 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2030
2031 smp_wmb();
2032
c54cdf14
LC		 2033 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2034 vcpu->arch.st.last_steal;
2035 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1
WL		 2036
2037 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2038 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2039
2040 smp_wmb();
2041
2042 vcpu->arch.st.steal.version += 1;
c9aaa895
GC		 2043
2044 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2045 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2046}
2047
8fe8ab46 2048int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2049{
5753785f 2050 bool pr = false;
8fe8ab46
WA		 2051 u32 msr = msr_info->index;
2052 u64 data = msr_info->data;
5753785f 2053
15c4a640 2054 switch (msr) {
2e32b719
BP		 2055 case MSR_AMD64_NB_CFG:
2056 case MSR_IA32_UCODE_REV:
2057 case MSR_IA32_UCODE_WRITE:
2058 case MSR_VM_HSAVE_PA:
2059 case MSR_AMD64_PATCH_LOADER:
2060 case MSR_AMD64_BU_CFG2:
2061 break;
2062
15c4a640 2063 case MSR_EFER:
b69e8cae 2064 return set_efer(vcpu, data);
8f1589d9
AP		 2065 case MSR_K7_HWCR:
2066 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2067 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2068 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2069 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2070 if (data != 0) {
a737f256
CD		 2071 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2072 data);
8f1589d9
AP		 2073 return 1;
2074 }
15c4a640 2075 break;
f7c6d140
AP		 2076 case MSR_FAM10H_MMIO_CONF_BASE:
2077 if (data != 0) {
a737f256
CD		 2078 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2079 "0x%llx\n", data);
f7c6d140
AP		 2080 return 1;
2081 }
15c4a640 2082 break;
b5e2fec0
AG		 2083 case MSR_IA32_DEBUGCTLMSR:
2084 if (!data) {
2085 /* We support the non-activated case already */
2086 break;
2087 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2088 /* Values other than LBR and BTF are vendor-specific,
2089 thus reserved and should throw a #GP */
2090 return 1;
2091 }
a737f256
CD		 2092 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2093 __func__, data);
b5e2fec0 2094 break;
9ba075a6 2095 case 0x200 ... 0x2ff:
ff53604b 2096 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2097 case MSR_IA32_APICBASE:
58cb628d 2098 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2099 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2100 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2101 case MSR_IA32_TSCDEADLINE:
2102 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2103 break;
ba904635
WA		 2104 case MSR_IA32_TSC_ADJUST:
2105 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2106 if (!msr_info->host_initiated) {
d913b904 2107 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2108 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2109 }
2110 vcpu->arch.ia32_tsc_adjust_msr = data;
2111 }
2112 break;
15c4a640 2113 case MSR_IA32_MISC_ENABLE:
ad312c7c 2114 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2115 break;
64d60670
PB		 2116 case MSR_IA32_SMBASE:
2117 if (!msr_info->host_initiated)
2118 return 1;
2119 vcpu->arch.smbase = data;
2120 break;
11c6bffa 2121 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2122 case MSR_KVM_WALL_CLOCK:
2123 vcpu->kvm->arch.wall_clock = data;
2124 kvm_write_wall_clock(vcpu->kvm, data);
2125 break;
11c6bffa 2126 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2127 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2128 u64 gpa_offset;
54750f2c
MT		 2129 struct kvm_arch *ka = &vcpu->kvm->arch;
2130
12f9a48f 2131 kvmclock_reset(vcpu);
18068523 2132
54750f2c
MT		 2133 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2134 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2135
2136 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2137 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2138 &vcpu->requests);
2139
2140 ka->boot_vcpu_runs_old_kvmclock = tmp;
2141 }
2142
18068523 2143 vcpu->arch.time = data;
0061d53d 2144 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2145
2146 /* we verify if the enable bit is set... */
2147 if (!(data & 1))
2148 break;
2149
0b79459b 2150 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2151
0b79459b 2152 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2153 &vcpu->arch.pv_time, data & ~1ULL,
2154 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2155 vcpu->arch.pv_time_enabled = false;
2156 else
2157 vcpu->arch.pv_time_enabled = true;
32cad84f 2158
18068523
GOC		 2159 break;
2160 }
344d9588
GN		 2161 case MSR_KVM_ASYNC_PF_EN:
2162 if (kvm_pv_enable_async_pf(vcpu, data))
2163 return 1;
2164 break;
c9aaa895
GC		 2165 case MSR_KVM_STEAL_TIME:
2166
2167 if (unlikely(!sched_info_on()))
2168 return 1;
2169
2170 if (data & KVM_STEAL_RESERVED_MASK)
2171 return 1;
2172
2173 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2174 data & KVM_STEAL_VALID_BITS,
2175 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2176 return 1;
2177
2178 vcpu->arch.st.msr_val = data;
2179
2180 if (!(data & KVM_MSR_ENABLED))
2181 break;
2182
c9aaa895
GC		 2183 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2184
2185 break;
ae7a2a3f
MT		 2186 case MSR_KVM_PV_EOI_EN:
2187 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2188 return 1;
2189 break;
c9aaa895 2190
890ca9ae
HY		 2191 case MSR_IA32_MCG_CTL:
2192 case MSR_IA32_MCG_STATUS:
81760dcc 2193 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2194 return set_msr_mce(vcpu, msr, data);
71db6023 2195
6912ac32
WH		 2196 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2197 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2198 pr = true; /* fall through */
2199 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2200 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2201 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2202 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2203
2204 if (pr || data != 0)
a737f256
CD		 2205 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2206 "0x%x data 0x%llx\n", msr, data);
5753785f 2207 break;
84e0cefa
JS		 2208 case MSR_K7_CLK_CTL:
2209 /*
2210 * Ignore all writes to this no longer documented MSR.
2211 * Writes are only relevant for old K7 processors,
2212 * all pre-dating SVM, but a recommended workaround from
4a969980 2213 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2214 * affected processor models on the command line, hence
2215 * the need to ignore the workaround.
2216 */
2217 break;
55cd8e5a 2218 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2219 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2220 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2221 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2222 return kvm_hv_set_msr_common(vcpu, msr, data,
2223 msr_info->host_initiated);
91c9c3ed 2224 case MSR_IA32_BBL_CR_CTL3:
2225 /* Drop writes to this legacy MSR -- see rdmsr
2226 * counterpart for further detail.
2227 */
a737f256 2228 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2229 break;
2b036c6b
BO		 2230 case MSR_AMD64_OSVW_ID_LENGTH:
2231 if (!guest_cpuid_has_osvw(vcpu))
2232 return 1;
2233 vcpu->arch.osvw.length = data;
2234 break;
2235 case MSR_AMD64_OSVW_STATUS:
2236 if (!guest_cpuid_has_osvw(vcpu))
2237 return 1;
2238 vcpu->arch.osvw.status = data;
2239 break;
15c4a640 2240 default:
ffde22ac
ES		 2241 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2242 return xen_hvm_config(vcpu, data);
c6702c9d 2243 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2244 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2245 if (!ignore_msrs) {
a737f256
CD		 2246 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2247 msr, data);
ed85c068
AP		 2248 return 1;
2249 } else {
a737f256
CD		 2250 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2251 msr, data);
ed85c068
AP		 2252 break;
2253 }
15c4a640
CO		 2254 }
2255 return 0;
2256}
2257EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2258
2259
2260/*
2261 * Reads an msr value (of 'msr_index') into 'pdata'.
2262 * Returns 0 on success, non-0 otherwise.
2263 * Assumes vcpu_load() was already called.
2264 */
609e36d3 2265int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2266{
609e36d3 2267 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2268}
ff651cb6 2269EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2270
890ca9ae 2271static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2272{
2273 u64 data;
890ca9ae
HY		 2274 u64 mcg_cap = vcpu->arch.mcg_cap;
2275 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2276
2277 switch (msr) {
15c4a640
CO		 2278 case MSR_IA32_P5_MC_ADDR:
2279 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2280 data = 0;
2281 break;
15c4a640 2282 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2283 data = vcpu->arch.mcg_cap;
2284 break;
c7ac679c 2285 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2286 if (!(mcg_cap & MCG_CTL_P))
2287 return 1;
2288 data = vcpu->arch.mcg_ctl;
2289 break;
2290 case MSR_IA32_MCG_STATUS:
2291 data = vcpu->arch.mcg_status;
2292 break;
2293 default:
2294 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2295 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2296 u32 offset = msr - MSR_IA32_MC0_CTL;
2297 data = vcpu->arch.mce_banks[offset];
2298 break;
2299 }
2300 return 1;
2301 }
2302 *pdata = data;
2303 return 0;
2304}
2305
609e36d3 2306int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2307{
609e36d3 2308 switch (msr_info->index) {
890ca9ae 2309 case MSR_IA32_PLATFORM_ID:
15c4a640 2310 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2311 case MSR_IA32_DEBUGCTLMSR:
2312 case MSR_IA32_LASTBRANCHFROMIP:
2313 case MSR_IA32_LASTBRANCHTOIP:
2314 case MSR_IA32_LASTINTFROMIP:
2315 case MSR_IA32_LASTINTTOIP:
60af2ecd 2316 case MSR_K8_SYSCFG:
3afb1121
PB		 2317 case MSR_K8_TSEG_ADDR:
2318 case MSR_K8_TSEG_MASK:
60af2ecd 2319 case MSR_K7_HWCR:
61a6bd67 2320 case MSR_VM_HSAVE_PA:
1fdbd48c 2321 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2322 case MSR_AMD64_NB_CFG:
f7c6d140 2323 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2324 case MSR_AMD64_BU_CFG2:
0c2df2a1 2325 case MSR_IA32_PERF_CTL:
609e36d3 2326 msr_info->data = 0;
15c4a640 2327 break;
6912ac32
WH		 2328 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2329 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2330 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2331 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2332 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2333 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2334 msr_info->data = 0;
5753785f 2335 break;
742bc670 2336 case MSR_IA32_UCODE_REV:
609e36d3 2337 msr_info->data = 0x100000000ULL;
742bc670 2338 break;
9ba075a6 2339 case MSR_MTRRcap:
9ba075a6 2340 case 0x200 ... 0x2ff:
ff53604b 2341 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2342 case 0xcd: /* fsb frequency */
609e36d3 2343 msr_info->data = 3;
15c4a640 2344 break;
7b914098
JS		 2345 /*
2346 * MSR_EBC_FREQUENCY_ID
2347 * Conservative value valid for even the basic CPU models.
2348 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2349 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2350 * and 266MHz for model 3, or 4. Set Core Clock
2351 * Frequency to System Bus Frequency Ratio to 1 (bits
2352 * 31:24) even though these are only valid for CPU
2353 * models > 2, however guests may end up dividing or
2354 * multiplying by zero otherwise.
2355 */
2356 case MSR_EBC_FREQUENCY_ID:
609e36d3 2357 msr_info->data = 1 << 24;
7b914098 2358 break;
15c4a640 2359 case MSR_IA32_APICBASE:
609e36d3 2360 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2361 break;
0105d1a5 2362 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2363 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2364 break;
a3e06bbe 2365 case MSR_IA32_TSCDEADLINE:
609e36d3 2366 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2367 break;
ba904635 2368 case MSR_IA32_TSC_ADJUST:
609e36d3 2369 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2370 break;
15c4a640 2371 case MSR_IA32_MISC_ENABLE:
609e36d3 2372 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2373 break;
64d60670
PB		 2374 case MSR_IA32_SMBASE:
2375 if (!msr_info->host_initiated)
2376 return 1;
2377 msr_info->data = vcpu->arch.smbase;
15c4a640 2378 break;
847f0ad8
AG		 2379 case MSR_IA32_PERF_STATUS:
2380 /* TSC increment by tick */
609e36d3 2381 msr_info->data = 1000ULL;
847f0ad8 2382 /* CPU multiplier */
b0996ae4 2383 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2384 break;
15c4a640 2385 case MSR_EFER:
609e36d3 2386 msr_info->data = vcpu->arch.efer;
15c4a640 2387 break;
18068523 2388 case MSR_KVM_WALL_CLOCK:
11c6bffa 2389 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2390 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2391 break;
2392 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2393 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2394 msr_info->data = vcpu->arch.time;
18068523 2395 break;
344d9588 2396 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2397 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2398 break;
c9aaa895 2399 case MSR_KVM_STEAL_TIME:
609e36d3 2400 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2401 break;
1d92128f 2402 case MSR_KVM_PV_EOI_EN:
609e36d3 2403 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2404 break;
890ca9ae
HY		 2405 case MSR_IA32_P5_MC_ADDR:
2406 case MSR_IA32_P5_MC_TYPE:
2407 case MSR_IA32_MCG_CAP:
2408 case MSR_IA32_MCG_CTL:
2409 case MSR_IA32_MCG_STATUS:
81760dcc 2410 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2411 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2412 case MSR_K7_CLK_CTL:
2413 /*
2414 * Provide expected ramp-up count for K7. All other
2415 * are set to zero, indicating minimum divisors for
2416 * every field.
2417 *
2418 * This prevents guest kernels on AMD host with CPU
2419 * type 6, model 8 and higher from exploding due to
2420 * the rdmsr failing.
2421 */
609e36d3 2422 msr_info->data = 0x20000000;
84e0cefa 2423 break;
55cd8e5a 2424 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2425 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2426 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2427 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2428 return kvm_hv_get_msr_common(vcpu,
2429 msr_info->index, &msr_info->data);
55cd8e5a 2430 break;
91c9c3ed 2431 case MSR_IA32_BBL_CR_CTL3:
2432 /* This legacy MSR exists but isn't fully documented in current
2433 * silicon. It is however accessed by winxp in very narrow
2434 * scenarios where it sets bit #19, itself documented as
2435 * a "reserved" bit. Best effort attempt to source coherent
2436 * read data here should the balance of the register be
2437 * interpreted by the guest:
2438 *
2439 * L2 cache control register 3: 64GB range, 256KB size,
2440 * enabled, latency 0x1, configured
2441 */
609e36d3 2442 msr_info->data = 0xbe702111;
91c9c3ed 2443 break;
2b036c6b
BO		 2444 case MSR_AMD64_OSVW_ID_LENGTH:
2445 if (!guest_cpuid_has_osvw(vcpu))
2446 return 1;
609e36d3 2447 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2448 break;
2449 case MSR_AMD64_OSVW_STATUS:
2450 if (!guest_cpuid_has_osvw(vcpu))
2451 return 1;
609e36d3 2452 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2453 break;
15c4a640 2454 default:
c6702c9d 2455 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2456 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2457 if (!ignore_msrs) {
609e36d3 2458 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2459 return 1;
2460 } else {
609e36d3
PB		 2461 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2462 msr_info->data = 0;
ed85c068
AP		 2463 }
2464 break;
15c4a640 2465 }
15c4a640
CO		 2466 return 0;
2467}
2468EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2469
313a3dc7
CO		 2470/*
2471 * Read or write a bunch of msrs. All parameters are kernel addresses.
2472 *
2473 * @return number of msrs set successfully.
2474 */
2475static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2476 struct kvm_msr_entry *entries,
2477 int (*do_msr)(struct kvm_vcpu *vcpu,
2478 unsigned index, u64 *data))
2479{
f656ce01 2480 int i, idx;
313a3dc7 2481
f656ce01 2482 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2483 for (i = 0; i < msrs->nmsrs; ++i)
2484 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2485 break;
f656ce01 2486 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2487
313a3dc7
CO		 2488 return i;
2489}
2490
2491/*
2492 * Read or write a bunch of msrs. Parameters are user addresses.
2493 *
2494 * @return number of msrs set successfully.
2495 */
2496static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2497 int (*do_msr)(struct kvm_vcpu *vcpu,
2498 unsigned index, u64 *data),
2499 int writeback)
2500{
2501 struct kvm_msrs msrs;
2502 struct kvm_msr_entry *entries;
2503 int r, n;
2504 unsigned size;
2505
2506 r = -EFAULT;
2507 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2508 goto out;
2509
2510 r = -E2BIG;
2511 if (msrs.nmsrs >= MAX_IO_MSRS)
2512 goto out;
2513
313a3dc7 2514 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2515 entries = memdup_user(user_msrs->entries, size);
2516 if (IS_ERR(entries)) {
2517 r = PTR_ERR(entries);
313a3dc7 2518 goto out;
ff5c2c03 2519 }
313a3dc7
CO		 2520
2521 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2522 if (r < 0)
2523 goto out_free;
2524
2525 r = -EFAULT;
2526 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2527 goto out_free;
2528
2529 r = n;
2530
2531out_free:
7a73c028 2532 kfree(entries);
313a3dc7
CO		 2533out:
2534 return r;
2535}
2536
784aa3d7 2537int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2538{
2539 int r;
2540
2541 switch (ext) {
2542 case KVM_CAP_IRQCHIP:
2543 case KVM_CAP_HLT:
2544 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2545 case KVM_CAP_SET_TSS_ADDR:
07716717 2546 case KVM_CAP_EXT_CPUID:
9c15bb1d 2547 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2548 case KVM_CAP_CLOCKSOURCE:
7837699f 2549 case KVM_CAP_PIT:
a28e4f5a 2550 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2551 case KVM_CAP_MP_STATE:
ed848624 2552 case KVM_CAP_SYNC_MMU:
a355c85c 2553 case KVM_CAP_USER_NMI:
52d939a0 2554 case KVM_CAP_REINJECT_CONTROL:
4925663a 2555 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2556 case KVM_CAP_IOEVENTFD:
f848a5a8 2557 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2558 case KVM_CAP_PIT2:
e9f42757 2559 case KVM_CAP_PIT_STATE2:
b927a3ce 2560 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2561 case KVM_CAP_XEN_HVM:
afbcf7ab 2562 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2563 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2564 case KVM_CAP_HYPERV:
10388a07 2565 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2566 case KVM_CAP_HYPERV_SPIN:
5c919412 2567 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2568 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2569 case KVM_CAP_DEBUGREGS:
d2be1651 2570 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2571 case KVM_CAP_XSAVE:
344d9588 2572 case KVM_CAP_ASYNC_PF:
92a1f12d 2573 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2574 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2575 case KVM_CAP_READONLY_MEM:
5f66b620 2576 case KVM_CAP_HYPERV_TIME:
100943c5 2577 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2578 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2579 case KVM_CAP_ENABLE_CAP_VM:
2580 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2581 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2582 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2583#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2584 case KVM_CAP_ASSIGN_DEV_IRQ:
2585 case KVM_CAP_PCI_2_3:
2586#endif
018d00d2
ZX		 2587 r = 1;
2588 break;
6d396b55
PB		 2589 case KVM_CAP_X86_SMM:
2590 /* SMBASE is usually relocated above 1M on modern chipsets,
2591 * and SMM handlers might indeed rely on 4G segment limits,
2592 * so do not report SMM to be available if real mode is
2593 * emulated via vm86 mode. Still, do not go to great lengths
2594 * to avoid userspace's usage of the feature, because it is a
2595 * fringe case that is not enabled except via specific settings
2596 * of the module parameters.
2597 */
2598 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2599 break;
542472b5
LV		 2600 case KVM_CAP_COALESCED_MMIO:
2601 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2602 break;
774ead3a
AK		 2603 case KVM_CAP_VAPIC:
2604 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2605 break;
f725230a 2606 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2607 r = KVM_SOFT_MAX_VCPUS;
2608 break;
2609 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2610 r = KVM_MAX_VCPUS;
2611 break;
a988b910 2612 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2613 r = KVM_USER_MEM_SLOTS;
a988b910 2614 break;
a68a6a72
MT		 2615 case KVM_CAP_PV_MMU: /* obsolete */
2616 r = 0;
2f333bcb 2617 break;
4cee4b72 2618#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2619 case KVM_CAP_IOMMU:
a1b60c1c 2620 r = iommu_present(&pci_bus_type);
62c476c7 2621 break;
4cee4b72 2622#endif
890ca9ae
HY		 2623 case KVM_CAP_MCE:
2624 r = KVM_MAX_MCE_BANKS;
2625 break;
2d5b5a66 2626 case KVM_CAP_XCRS:
d366bf7e 2627 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2628 break;
92a1f12d
JR		 2629 case KVM_CAP_TSC_CONTROL:
2630 r = kvm_has_tsc_control;
2631 break;
37131313
RK		 2632 case KVM_CAP_X2APIC_API:
2633 r = KVM_X2APIC_API_VALID_FLAGS;
2634 break;
018d00d2
ZX		 2635 default:
2636 r = 0;
2637 break;
2638 }
2639 return r;
2640
2641}
2642
043405e1
CO		 2643long kvm_arch_dev_ioctl(struct file *filp,
2644 unsigned int ioctl, unsigned long arg)
2645{
2646 void __user *argp = (void __user *)arg;
2647 long r;
2648
2649 switch (ioctl) {
2650 case KVM_GET_MSR_INDEX_LIST: {
2651 struct kvm_msr_list __user *user_msr_list = argp;
2652 struct kvm_msr_list msr_list;
2653 unsigned n;
2654
2655 r = -EFAULT;
2656 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2657 goto out;
2658 n = msr_list.nmsrs;
62ef68bb 2659 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2660 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2661 goto out;
2662 r = -E2BIG;
e125e7b6 2663 if (n < msr_list.nmsrs)
043405e1
CO		 2664 goto out;
2665 r = -EFAULT;
2666 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2667 num_msrs_to_save * sizeof(u32)))
2668 goto out;
e125e7b6 2669 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2670 &emulated_msrs,
62ef68bb 2671 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2672 goto out;
2673 r = 0;
2674 break;
2675 }
9c15bb1d
BP		 2676 case KVM_GET_SUPPORTED_CPUID:
2677 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2678 struct kvm_cpuid2 __user *cpuid_arg = argp;
2679 struct kvm_cpuid2 cpuid;
2680
2681 r = -EFAULT;
2682 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2683 goto out;
9c15bb1d
BP		 2684
2685 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2686 ioctl);
674eea0f
AK		 2687 if (r)
2688 goto out;
2689
2690 r = -EFAULT;
2691 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2692 goto out;
2693 r = 0;
2694 break;
2695 }
890ca9ae 2696 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2697 r = -EFAULT;
c45dcc71
AR		 2698 if (copy_to_user(argp, &kvm_mce_cap_supported,
2699 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2700 goto out;
2701 r = 0;
2702 break;
2703 }
043405e1
CO		 2704 default:
2705 r = -EINVAL;
2706 }
2707out:
2708 return r;
2709}
2710
f5f48ee1
SY		 2711static void wbinvd_ipi(void *garbage)
2712{
2713 wbinvd();
2714}
2715
2716static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2717{
e0f0bbc5 2718 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2719}
2720
2860c4b1
PB		 2721static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2722{
2723 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2724}
2725
313a3dc7
CO		 2726void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2727{
f5f48ee1
SY		 2728 /* Address WBINVD may be executed by guest */
2729 if (need_emulate_wbinvd(vcpu)) {
2730 if (kvm_x86_ops->has_wbinvd_exit())
2731 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2732 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2733 smp_call_function_single(vcpu->cpu,
2734 wbinvd_ipi, NULL, 1);
2735 }
2736
313a3dc7 2737 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2738
0dd6a6ed
ZA		 2739 /* Apply any externally detected TSC adjustments (due to suspend) */
2740 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2741 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2742 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2743 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2744 }
8f6055cb 2745
48434c20 2746 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2747 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2748 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2749 if (tsc_delta < 0)
2750 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a
YJ		 2751
2752 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2753 kvm_x86_ops->set_hv_timer(vcpu,
2754 kvm_get_lapic_tscdeadline_msr(vcpu)))
2755 kvm_lapic_switch_to_sw_timer(vcpu);
c285545f 2756 if (check_tsc_unstable()) {
07c1419a 2757 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2758 vcpu->arch.last_guest_tsc);
a545ab6a 2759 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2760 vcpu->arch.tsc_catchup = 1;
c285545f 2761 }
d98d07ca
MT		 2762 /*
2763 * On a host with synchronized TSC, there is no need to update
2764 * kvmclock on vcpu->cpu migration
2765 */
2766 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2767 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2768 if (vcpu->cpu != cpu)
2769 kvm_migrate_timers(vcpu);
e48672fa 2770 vcpu->cpu = cpu;
6b7d7e76 2771 }
c9aaa895 2772
c9aaa895 2773 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2774}
2775
2776void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2777{
02daab21 2778 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2779 kvm_put_guest_fpu(vcpu);
4ea1636b 2780 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2781}
2782
313a3dc7
CO		 2783static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2784 struct kvm_lapic_state *s)
2785{
d62caabb
AS		 2786 if (vcpu->arch.apicv_active)
2787 kvm_x86_ops->sync_pir_to_irr(vcpu);
2788
a92e2543 2789 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2790}
2791
2792static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2793 struct kvm_lapic_state *s)
2794{
a92e2543
RK		 2795 int r;
2796
2797 r = kvm_apic_set_state(vcpu, s);
2798 if (r)
2799 return r;
cb142eb7 2800 update_cr8_intercept(vcpu);
313a3dc7
CO		 2801
2802 return 0;
2803}
2804
127a457a
MG		 2805static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2806{
2807 return (!lapic_in_kernel(vcpu) ||
2808 kvm_apic_accept_pic_intr(vcpu));
2809}
2810
782d422b
MG		 2811/*
2812 * if userspace requested an interrupt window, check that the
2813 * interrupt window is open.
2814 *
2815 * No need to exit to userspace if we already have an interrupt queued.
2816 */
2817static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2818{
2819 return kvm_arch_interrupt_allowed(vcpu) &&
2820 !kvm_cpu_has_interrupt(vcpu) &&
2821 !kvm_event_needs_reinjection(vcpu) &&
2822 kvm_cpu_accept_dm_intr(vcpu);
2823}
2824
f77bc6a4
ZX		 2825static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2826 struct kvm_interrupt *irq)
2827{
02cdb50f 2828 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2829 return -EINVAL;
1c1a9ce9
SR		 2830
2831 if (!irqchip_in_kernel(vcpu->kvm)) {
2832 kvm_queue_interrupt(vcpu, irq->irq, false);
2833 kvm_make_request(KVM_REQ_EVENT, vcpu);
2834 return 0;
2835 }
2836
2837 /*
2838 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2839 * fail for in-kernel 8259.
2840 */
2841 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2842 return -ENXIO;
f77bc6a4 2843
1c1a9ce9
SR		 2844 if (vcpu->arch.pending_external_vector != -1)
2845 return -EEXIST;
f77bc6a4 2846
1c1a9ce9 2847 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2848 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2849 return 0;
2850}
2851
c4abb7c9
JK		 2852static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2853{
c4abb7c9 2854 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2855
2856 return 0;
2857}
2858
f077825a
PB		 2859static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2860{
64d60670
PB		 2861 kvm_make_request(KVM_REQ_SMI, vcpu);
2862
f077825a
PB		 2863 return 0;
2864}
2865
b209749f
AK		 2866static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2867 struct kvm_tpr_access_ctl *tac)
2868{
2869 if (tac->flags)
2870 return -EINVAL;
2871 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2872 return 0;
2873}
2874
890ca9ae
HY		 2875static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2876 u64 mcg_cap)
2877{
2878 int r;
2879 unsigned bank_num = mcg_cap & 0xff, bank;
2880
2881 r = -EINVAL;
a9e38c3e 2882 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 2883 goto out;
c45dcc71 2884 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 2885 goto out;
2886 r = 0;
2887 vcpu->arch.mcg_cap = mcg_cap;
2888 /* Init IA32_MCG_CTL to all 1s */
2889 if (mcg_cap & MCG_CTL_P)
2890 vcpu->arch.mcg_ctl = ~(u64)0;
2891 /* Init IA32_MCi_CTL to all 1s */
2892 for (bank = 0; bank < bank_num; bank++)
2893 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 2894
2895 if (kvm_x86_ops->setup_mce)
2896 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 2897out:
2898 return r;
2899}
2900
2901static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2902 struct kvm_x86_mce *mce)
2903{
2904 u64 mcg_cap = vcpu->arch.mcg_cap;
2905 unsigned bank_num = mcg_cap & 0xff;
2906 u64 *banks = vcpu->arch.mce_banks;
2907
2908 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2909 return -EINVAL;
2910 /*
2911 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2912 * reporting is disabled
2913 */
2914 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2915 vcpu->arch.mcg_ctl != ~(u64)0)
2916 return 0;
2917 banks += 4 * mce->bank;
2918 /*
2919 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2920 * reporting is disabled for the bank
2921 */
2922 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2923 return 0;
2924 if (mce->status & MCI_STATUS_UC) {
2925 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2926 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2927 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2928 return 0;
2929 }
2930 if (banks[1] & MCI_STATUS_VAL)
2931 mce->status |= MCI_STATUS_OVER;
2932 banks[2] = mce->addr;
2933 banks[3] = mce->misc;
2934 vcpu->arch.mcg_status = mce->mcg_status;
2935 banks[1] = mce->status;
2936 kvm_queue_exception(vcpu, MC_VECTOR);
2937 } else if (!(banks[1] & MCI_STATUS_VAL)
2938 || !(banks[1] & MCI_STATUS_UC)) {
2939 if (banks[1] & MCI_STATUS_VAL)
2940 mce->status |= MCI_STATUS_OVER;
2941 banks[2] = mce->addr;
2942 banks[3] = mce->misc;
2943 banks[1] = mce->status;
2944 } else
2945 banks[1] |= MCI_STATUS_OVER;
2946 return 0;
2947}
2948
3cfc3092
JK		 2949static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2950 struct kvm_vcpu_events *events)
2951{
7460fb4a 2952 process_nmi(vcpu);
03b82a30
JK		 2953 events->exception.injected =
2954 vcpu->arch.exception.pending &&
2955 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2956 events->exception.nr = vcpu->arch.exception.nr;
2957 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2958 events->exception.pad = 0;
3cfc3092
JK		 2959 events->exception.error_code = vcpu->arch.exception.error_code;
2960
03b82a30
JK		 2961 events->interrupt.injected =
2962 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2963 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2964 events->interrupt.soft = 0;
37ccdcbe 2965 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2966
2967 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2968 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2969 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2970 events->nmi.pad = 0;
3cfc3092 2971
66450a21 2972 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2973
f077825a
PB		 2974 events->smi.smm = is_smm(vcpu);
2975 events->smi.pending = vcpu->arch.smi_pending;
2976 events->smi.smm_inside_nmi =
2977 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2978 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2979
dab4b911 2980 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2981 | KVM_VCPUEVENT_VALID_SHADOW
2982 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2983 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2984}
2985
2986static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2987 struct kvm_vcpu_events *events)
2988{
dab4b911 2989 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2990 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2991 | KVM_VCPUEVENT_VALID_SHADOW
2992 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2993 return -EINVAL;
2994
78e546c8
PB		 2995 if (events->exception.injected &&
2996 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
2997 return -EINVAL;
2998
7460fb4a 2999 process_nmi(vcpu);
3cfc3092
JK		 3000 vcpu->arch.exception.pending = events->exception.injected;
3001 vcpu->arch.exception.nr = events->exception.nr;
3002 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3003 vcpu->arch.exception.error_code = events->exception.error_code;
3004
3005 vcpu->arch.interrupt.pending = events->interrupt.injected;
3006 vcpu->arch.interrupt.nr = events->interrupt.nr;
3007 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3008 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3009 kvm_x86_ops->set_interrupt_shadow(vcpu,
3010 events->interrupt.shadow);
3cfc3092
JK		 3011
3012 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3013 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3014 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3015 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3016
66450a21 3017 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3018 lapic_in_kernel(vcpu))
66450a21 3019 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3020
f077825a
PB		 3021 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3022 if (events->smi.smm)
3023 vcpu->arch.hflags |= HF_SMM_MASK;
3024 else
3025 vcpu->arch.hflags &= ~HF_SMM_MASK;
3026 vcpu->arch.smi_pending = events->smi.pending;
3027 if (events->smi.smm_inside_nmi)
3028 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3029 else
3030 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3031 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3032 if (events->smi.latched_init)
3033 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3034 else
3035 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3036 }
3037 }
3038
3842d135
AK		 3039 kvm_make_request(KVM_REQ_EVENT, vcpu);
3040
3cfc3092
JK		 3041 return 0;
3042}
3043
a1efbe77
JK		 3044static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3045 struct kvm_debugregs *dbgregs)
3046{
73aaf249
JK		 3047 unsigned long val;
3048
a1efbe77 3049 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3050 kvm_get_dr(vcpu, 6, &val);
73aaf249 3051 dbgregs->dr6 = val;
a1efbe77
JK		 3052 dbgregs->dr7 = vcpu->arch.dr7;
3053 dbgregs->flags = 0;
97e69aa6 3054 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3055}
3056
3057static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3058 struct kvm_debugregs *dbgregs)
3059{
3060 if (dbgregs->flags)
3061 return -EINVAL;
3062
d14bdb55
PB		 3063 if (dbgregs->dr6 & ~0xffffffffull)
3064 return -EINVAL;
3065 if (dbgregs->dr7 & ~0xffffffffull)
3066 return -EINVAL;
3067
a1efbe77 3068 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3069 kvm_update_dr0123(vcpu);
a1efbe77 3070 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3071 kvm_update_dr6(vcpu);
a1efbe77 3072 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3073 kvm_update_dr7(vcpu);
a1efbe77 3074
a1efbe77
JK		 3075 return 0;
3076}
3077
df1daba7
PB		 3078#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3079
3080static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3081{
c47ada30 3082 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3083 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3084 u64 valid;
3085
3086 /*
3087 * Copy legacy XSAVE area, to avoid complications with CPUID
3088 * leaves 0 and 1 in the loop below.
3089 */
3090 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3091
3092 /* Set XSTATE_BV */
3093 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3094
3095 /*
3096 * Copy each region from the possibly compacted offset to the
3097 * non-compacted offset.
3098 */
d91cab78 3099 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3100 while (valid) {
3101 u64 feature = valid & -valid;
3102 int index = fls64(feature) - 1;
3103 void *src = get_xsave_addr(xsave, feature);
3104
3105 if (src) {
3106 u32 size, offset, ecx, edx;
3107 cpuid_count(XSTATE_CPUID, index,
3108 &size, &offset, &ecx, &edx);
3109 memcpy(dest + offset, src, size);
3110 }
3111
3112 valid -= feature;
3113 }
3114}
3115
3116static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3117{
c47ada30 3118 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3119 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3120 u64 valid;
3121
3122 /*
3123 * Copy legacy XSAVE area, to avoid complications with CPUID
3124 * leaves 0 and 1 in the loop below.
3125 */
3126 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3127
3128 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3129 xsave->header.xfeatures = xstate_bv;
782511b0 3130 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3131 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3132
3133 /*
3134 * Copy each region from the non-compacted offset to the
3135 * possibly compacted offset.
3136 */
d91cab78 3137 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3138 while (valid) {
3139 u64 feature = valid & -valid;
3140 int index = fls64(feature) - 1;
3141 void *dest = get_xsave_addr(xsave, feature);
3142
3143 if (dest) {
3144 u32 size, offset, ecx, edx;
3145 cpuid_count(XSTATE_CPUID, index,
3146 &size, &offset, &ecx, &edx);
3147 memcpy(dest, src + offset, size);
ee4100da 3148 }
df1daba7
PB		 3149
3150 valid -= feature;
3151 }
3152}
3153
2d5b5a66
SY		 3154static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3155 struct kvm_xsave *guest_xsave)
3156{
d366bf7e 3157 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3158 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3159 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3160 } else {
2d5b5a66 3161 memcpy(guest_xsave->region,
7366ed77 3162 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3163 sizeof(struct fxregs_state));
2d5b5a66 3164 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3165 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3166 }
3167}
3168
3169static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3170 struct kvm_xsave *guest_xsave)
3171{
3172 u64 xstate_bv =
3173 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3174
d366bf7e 3175 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3176 /*
3177 * Here we allow setting states that are not present in
3178 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3179 * with old userspace.
3180 */
4ff41732 3181 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3182 return -EINVAL;
df1daba7 3183 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3184 } else {
d91cab78 3185 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3186 return -EINVAL;
7366ed77 3187 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3188 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3189 }
3190 return 0;
3191}
3192
3193static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3194 struct kvm_xcrs *guest_xcrs)
3195{
d366bf7e 3196 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3197 guest_xcrs->nr_xcrs = 0;
3198 return;
3199 }
3200
3201 guest_xcrs->nr_xcrs = 1;
3202 guest_xcrs->flags = 0;
3203 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3204 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3205}
3206
3207static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3208 struct kvm_xcrs *guest_xcrs)
3209{
3210 int i, r = 0;
3211
d366bf7e 3212 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3213 return -EINVAL;
3214
3215 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3216 return -EINVAL;
3217
3218 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3219 /* Only support XCR0 currently */
c67a04cb 3220 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3221 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3222 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3223 break;
3224 }
3225 if (r)
3226 r = -EINVAL;
3227 return r;
3228}
3229
1c0b28c2
EM		 3230/*
3231 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3232 * stopped by the hypervisor. This function will be called from the host only.
3233 * EINVAL is returned when the host attempts to set the flag for a guest that
3234 * does not support pv clocks.
3235 */
3236static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3237{
0b79459b 3238 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3239 return -EINVAL;
51d59c6b 3240 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3241 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3242 return 0;
3243}
3244
5c919412
AS		 3245static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3246 struct kvm_enable_cap *cap)
3247{
3248 if (cap->flags)
3249 return -EINVAL;
3250
3251 switch (cap->cap) {
3252 case KVM_CAP_HYPERV_SYNIC:
3253 return kvm_hv_activate_synic(vcpu);
3254 default:
3255 return -EINVAL;
3256 }
3257}
3258
313a3dc7
CO		 3259long kvm_arch_vcpu_ioctl(struct file *filp,
3260 unsigned int ioctl, unsigned long arg)
3261{
3262 struct kvm_vcpu *vcpu = filp->private_data;
3263 void __user *argp = (void __user *)arg;
3264 int r;
d1ac91d8
AK		 3265 union {
3266 struct kvm_lapic_state *lapic;
3267 struct kvm_xsave *xsave;
3268 struct kvm_xcrs *xcrs;
3269 void *buffer;
3270 } u;
3271
3272 u.buffer = NULL;
313a3dc7
CO		 3273 switch (ioctl) {
3274 case KVM_GET_LAPIC: {
2204ae3c 3275 r = -EINVAL;
bce87cce 3276 if (!lapic_in_kernel(vcpu))
2204ae3c 3277 goto out;
d1ac91d8 3278 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3279
b772ff36 3280 r = -ENOMEM;
d1ac91d8 3281 if (!u.lapic)
b772ff36 3282 goto out;
d1ac91d8 3283 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3284 if (r)
3285 goto out;
3286 r = -EFAULT;
d1ac91d8 3287 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3288 goto out;
3289 r = 0;
3290 break;
3291 }
3292 case KVM_SET_LAPIC: {
2204ae3c 3293 r = -EINVAL;
bce87cce 3294 if (!lapic_in_kernel(vcpu))
2204ae3c 3295 goto out;
ff5c2c03 3296 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3297 if (IS_ERR(u.lapic))
3298 return PTR_ERR(u.lapic);
ff5c2c03 3299
d1ac91d8 3300 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3301 break;
3302 }
f77bc6a4
ZX		 3303 case KVM_INTERRUPT: {
3304 struct kvm_interrupt irq;
3305
3306 r = -EFAULT;
3307 if (copy_from_user(&irq, argp, sizeof irq))
3308 goto out;
3309 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3310 break;
3311 }
c4abb7c9
JK		 3312 case KVM_NMI: {
3313 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3314 break;
3315 }
f077825a
PB		 3316 case KVM_SMI: {
3317 r = kvm_vcpu_ioctl_smi(vcpu);
3318 break;
3319 }
313a3dc7
CO		 3320 case KVM_SET_CPUID: {
3321 struct kvm_cpuid __user *cpuid_arg = argp;
3322 struct kvm_cpuid cpuid;
3323
3324 r = -EFAULT;
3325 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3326 goto out;
3327 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3328 break;
3329 }
07716717
DK		 3330 case KVM_SET_CPUID2: {
3331 struct kvm_cpuid2 __user *cpuid_arg = argp;
3332 struct kvm_cpuid2 cpuid;
3333
3334 r = -EFAULT;
3335 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3336 goto out;
3337 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3338 cpuid_arg->entries);
07716717
DK		 3339 break;
3340 }
3341 case KVM_GET_CPUID2: {
3342 struct kvm_cpuid2 __user *cpuid_arg = argp;
3343 struct kvm_cpuid2 cpuid;
3344
3345 r = -EFAULT;
3346 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3347 goto out;
3348 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3349 cpuid_arg->entries);
07716717
DK		 3350 if (r)
3351 goto out;
3352 r = -EFAULT;
3353 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3354 goto out;
3355 r = 0;
3356 break;
3357 }
313a3dc7 3358 case KVM_GET_MSRS:
609e36d3 3359 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3360 break;
3361 case KVM_SET_MSRS:
3362 r = msr_io(vcpu, argp, do_set_msr, 0);
3363 break;
b209749f
AK		 3364 case KVM_TPR_ACCESS_REPORTING: {
3365 struct kvm_tpr_access_ctl tac;
3366
3367 r = -EFAULT;
3368 if (copy_from_user(&tac, argp, sizeof tac))
3369 goto out;
3370 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3371 if (r)
3372 goto out;
3373 r = -EFAULT;
3374 if (copy_to_user(argp, &tac, sizeof tac))
3375 goto out;
3376 r = 0;
3377 break;
3378 };
b93463aa
AK		 3379 case KVM_SET_VAPIC_ADDR: {
3380 struct kvm_vapic_addr va;
3381
3382 r = -EINVAL;
35754c98 3383 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3384 goto out;
3385 r = -EFAULT;
3386 if (copy_from_user(&va, argp, sizeof va))
3387 goto out;
fda4e2e8 3388 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3389 break;
3390 }
890ca9ae
HY		 3391 case KVM_X86_SETUP_MCE: {
3392 u64 mcg_cap;
3393
3394 r = -EFAULT;
3395 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3396 goto out;
3397 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3398 break;
3399 }
3400 case KVM_X86_SET_MCE: {
3401 struct kvm_x86_mce mce;
3402
3403 r = -EFAULT;
3404 if (copy_from_user(&mce, argp, sizeof mce))
3405 goto out;
3406 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3407 break;
3408 }
3cfc3092
JK		 3409 case KVM_GET_VCPU_EVENTS: {
3410 struct kvm_vcpu_events events;
3411
3412 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3413
3414 r = -EFAULT;
3415 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3416 break;
3417 r = 0;
3418 break;
3419 }
3420 case KVM_SET_VCPU_EVENTS: {
3421 struct kvm_vcpu_events events;
3422
3423 r = -EFAULT;
3424 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3425 break;
3426
3427 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3428 break;
3429 }
a1efbe77
JK		 3430 case KVM_GET_DEBUGREGS: {
3431 struct kvm_debugregs dbgregs;
3432
3433 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3434
3435 r = -EFAULT;
3436 if (copy_to_user(argp, &dbgregs,
3437 sizeof(struct kvm_debugregs)))
3438 break;
3439 r = 0;
3440 break;
3441 }
3442 case KVM_SET_DEBUGREGS: {
3443 struct kvm_debugregs dbgregs;
3444
3445 r = -EFAULT;
3446 if (copy_from_user(&dbgregs, argp,
3447 sizeof(struct kvm_debugregs)))
3448 break;
3449
3450 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3451 break;
3452 }
2d5b5a66 3453 case KVM_GET_XSAVE: {
d1ac91d8 3454 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3455 r = -ENOMEM;
d1ac91d8 3456 if (!u.xsave)
2d5b5a66
SY		 3457 break;
3458
d1ac91d8 3459 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3460
3461 r = -EFAULT;
d1ac91d8 3462 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3463 break;
3464 r = 0;
3465 break;
3466 }
3467 case KVM_SET_XSAVE: {
ff5c2c03 3468 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3469 if (IS_ERR(u.xsave))
3470 return PTR_ERR(u.xsave);
2d5b5a66 3471
d1ac91d8 3472 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3473 break;
3474 }
3475 case KVM_GET_XCRS: {
d1ac91d8 3476 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3477 r = -ENOMEM;
d1ac91d8 3478 if (!u.xcrs)
2d5b5a66
SY		 3479 break;
3480
d1ac91d8 3481 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3482
3483 r = -EFAULT;
d1ac91d8 3484 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3485 sizeof(struct kvm_xcrs)))
3486 break;
3487 r = 0;
3488 break;
3489 }
3490 case KVM_SET_XCRS: {
ff5c2c03 3491 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3492 if (IS_ERR(u.xcrs))
3493 return PTR_ERR(u.xcrs);
2d5b5a66 3494
d1ac91d8 3495 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3496 break;
3497 }
92a1f12d
JR		 3498 case KVM_SET_TSC_KHZ: {
3499 u32 user_tsc_khz;
3500
3501 r = -EINVAL;
92a1f12d
JR		 3502 user_tsc_khz = (u32)arg;
3503
3504 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3505 goto out;
3506
cc578287
ZA		 3507 if (user_tsc_khz == 0)
3508 user_tsc_khz = tsc_khz;
3509
381d585c
HZ		 3510 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3511 r = 0;
92a1f12d 3512
92a1f12d
JR		 3513 goto out;
3514 }
3515 case KVM_GET_TSC_KHZ: {
cc578287 3516 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3517 goto out;
3518 }
1c0b28c2
EM		 3519 case KVM_KVMCLOCK_CTRL: {
3520 r = kvm_set_guest_paused(vcpu);
3521 goto out;
3522 }
5c919412
AS		 3523 case KVM_ENABLE_CAP: {
3524 struct kvm_enable_cap cap;
3525
3526 r = -EFAULT;
3527 if (copy_from_user(&cap, argp, sizeof(cap)))
3528 goto out;
3529 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3530 break;
3531 }
313a3dc7
CO		 3532 default:
3533 r = -EINVAL;
3534 }
3535out:
d1ac91d8 3536 kfree(u.buffer);
313a3dc7
CO		 3537 return r;
3538}
3539
5b1c1493
CO		 3540int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3541{
3542 return VM_FAULT_SIGBUS;
3543}
3544
1fe779f8
CO		 3545static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3546{
3547 int ret;
3548
3549 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3550 return -EINVAL;
1fe779f8
CO		 3551 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3552 return ret;
3553}
3554
b927a3ce
SY		 3555static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3556 u64 ident_addr)
3557{
3558 kvm->arch.ept_identity_map_addr = ident_addr;
3559 return 0;
3560}
3561
1fe779f8
CO		 3562static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3563 u32 kvm_nr_mmu_pages)
3564{
3565 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3566 return -EINVAL;
3567
79fac95e 3568 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3569
3570 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3571 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3572
79fac95e 3573 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3574 return 0;
3575}
3576
3577static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3578{
39de71ec 3579 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3580}
3581
1fe779f8
CO		 3582static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3583{
3584 int r;
3585
3586 r = 0;
3587 switch (chip->chip_id) {
3588 case KVM_IRQCHIP_PIC_MASTER:
3589 memcpy(&chip->chip.pic,
3590 &pic_irqchip(kvm)->pics[0],
3591 sizeof(struct kvm_pic_state));
3592 break;
3593 case KVM_IRQCHIP_PIC_SLAVE:
3594 memcpy(&chip->chip.pic,
3595 &pic_irqchip(kvm)->pics[1],
3596 sizeof(struct kvm_pic_state));
3597 break;
3598 case KVM_IRQCHIP_IOAPIC:
eba0226b 3599 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3600 break;
3601 default:
3602 r = -EINVAL;
3603 break;
3604 }
3605 return r;
3606}
3607
3608static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3609{
3610 int r;
3611
3612 r = 0;
3613 switch (chip->chip_id) {
3614 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3615 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3616 memcpy(&pic_irqchip(kvm)->pics[0],
3617 &chip->chip.pic,
3618 sizeof(struct kvm_pic_state));
f4f51050 3619 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3620 break;
3621 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3622 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3623 memcpy(&pic_irqchip(kvm)->pics[1],
3624 &chip->chip.pic,
3625 sizeof(struct kvm_pic_state));
f4f51050 3626 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3627 break;
3628 case KVM_IRQCHIP_IOAPIC:
eba0226b 3629 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3630 break;
3631 default:
3632 r = -EINVAL;
3633 break;
3634 }
3635 kvm_pic_update_irq(pic_irqchip(kvm));
3636 return r;
3637}
3638
e0f63cb9
SY		 3639static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3640{
34f3941c
RK		 3641 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3642
3643 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3644
3645 mutex_lock(&kps->lock);
3646 memcpy(ps, &kps->channels, sizeof(*ps));
3647 mutex_unlock(&kps->lock);
2da29bcc 3648 return 0;
e0f63cb9
SY		 3649}
3650
3651static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3652{
0185604c 3653 int i;
09edea72
RK		 3654 struct kvm_pit *pit = kvm->arch.vpit;
3655
3656 mutex_lock(&pit->pit_state.lock);
34f3941c 3657 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3658 for (i = 0; i < 3; i++)
09edea72
RK		 3659 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3660 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3661 return 0;
e9f42757
BK		 3662}
3663
3664static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3665{
e9f42757
BK		 3666 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3667 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3668 sizeof(ps->channels));
3669 ps->flags = kvm->arch.vpit->pit_state.flags;
3670 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3671 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3672 return 0;
e9f42757
BK		 3673}
3674
3675static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3676{
2da29bcc 3677 int start = 0;
0185604c 3678 int i;
e9f42757 3679 u32 prev_legacy, cur_legacy;
09edea72
RK		 3680 struct kvm_pit *pit = kvm->arch.vpit;
3681
3682 mutex_lock(&pit->pit_state.lock);
3683 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3684 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3685 if (!prev_legacy && cur_legacy)
3686 start = 1;
09edea72
RK		 3687 memcpy(&pit->pit_state.channels, &ps->channels,
3688 sizeof(pit->pit_state.channels));
3689 pit->pit_state.flags = ps->flags;
0185604c 3690 for (i = 0; i < 3; i++)
09edea72 3691 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3692 start && i == 0);
09edea72 3693 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3694 return 0;
e0f63cb9
SY		 3695}
3696
52d939a0
MT		 3697static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3698 struct kvm_reinject_control *control)
3699{
71474e2f
RK		 3700 struct kvm_pit *pit = kvm->arch.vpit;
3701
3702 if (!pit)
52d939a0 3703 return -ENXIO;
b39c90b6 3704
71474e2f
RK		 3705 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3706 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3707 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3708 */
3709 mutex_lock(&pit->pit_state.lock);
3710 kvm_pit_set_reinject(pit, control->pit_reinject);
3711 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3712
52d939a0
MT		 3713 return 0;
3714}
3715
95d4c16c 3716/**
60c34612
TY		 3717 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3718 * @kvm: kvm instance
3719 * @log: slot id and address to which we copy the log
95d4c16c 3720 *
e108ff2f
PB		 3721 * Steps 1-4 below provide general overview of dirty page logging. See
3722 * kvm_get_dirty_log_protect() function description for additional details.
3723 *
3724 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3725 * always flush the TLB (step 4) even if previous step failed and the dirty
3726 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3727 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3728 * writes will be marked dirty for next log read.
95d4c16c 3729 *
60c34612
TY		 3730 * 1. Take a snapshot of the bit and clear it if needed.
3731 * 2. Write protect the corresponding page.
e108ff2f
PB		 3732 * 3. Copy the snapshot to the userspace.
3733 * 4. Flush TLB's if needed.
5bb064dc 3734 */
60c34612 3735int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3736{
60c34612 3737 bool is_dirty = false;
e108ff2f 3738 int r;
5bb064dc 3739
79fac95e 3740 mutex_lock(&kvm->slots_lock);
5bb064dc 3741
88178fd4
KH		 3742 /*
3743 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3744 */
3745 if (kvm_x86_ops->flush_log_dirty)
3746 kvm_x86_ops->flush_log_dirty(kvm);
3747
e108ff2f 3748 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3749
3750 /*
3751 * All the TLBs can be flushed out of mmu lock, see the comments in
3752 * kvm_mmu_slot_remove_write_access().
3753 */
e108ff2f 3754 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3755 if (is_dirty)
3756 kvm_flush_remote_tlbs(kvm);
3757
79fac95e 3758 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3759 return r;
3760}
3761
aa2fbe6d
YZ		 3762int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3763 bool line_status)
23d43cf9
CD		 3764{
3765 if (!irqchip_in_kernel(kvm))
3766 return -ENXIO;
3767
3768 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3769 irq_event->irq, irq_event->level,
3770 line_status);
23d43cf9
CD		 3771 return 0;
3772}
3773
90de4a18
NA		 3774static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3775 struct kvm_enable_cap *cap)
3776{
3777 int r;
3778
3779 if (cap->flags)
3780 return -EINVAL;
3781
3782 switch (cap->cap) {
3783 case KVM_CAP_DISABLE_QUIRKS:
3784 kvm->arch.disabled_quirks = cap->args[0];
3785 r = 0;
3786 break;
49df6397
SR		 3787 case KVM_CAP_SPLIT_IRQCHIP: {
3788 mutex_lock(&kvm->lock);
b053b2ae
SR		 3789 r = -EINVAL;
3790 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3791 goto split_irqchip_unlock;
49df6397
SR		 3792 r = -EEXIST;
3793 if (irqchip_in_kernel(kvm))
3794 goto split_irqchip_unlock;
557abc40 3795 if (kvm->created_vcpus)
49df6397
SR		 3796 goto split_irqchip_unlock;
3797 r = kvm_setup_empty_irq_routing(kvm);
3798 if (r)
3799 goto split_irqchip_unlock;
3800 /* Pairs with irqchip_in_kernel. */
3801 smp_wmb();
3802 kvm->arch.irqchip_split = true;
b053b2ae 3803 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3804 r = 0;
3805split_irqchip_unlock:
3806 mutex_unlock(&kvm->lock);
3807 break;
3808 }
37131313
RK		 3809 case KVM_CAP_X2APIC_API:
3810 r = -EINVAL;
3811 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3812 break;
3813
3814 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3815 kvm->arch.x2apic_format = true;
c519265f
RK		 3816 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3817 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3818
3819 r = 0;
3820 break;
90de4a18
NA		 3821 default:
3822 r = -EINVAL;
3823 break;
3824 }
3825 return r;
3826}
3827
1fe779f8
CO		 3828long kvm_arch_vm_ioctl(struct file *filp,
3829 unsigned int ioctl, unsigned long arg)
3830{
3831 struct kvm *kvm = filp->private_data;
3832 void __user *argp = (void __user *)arg;
367e1319 3833 int r = -ENOTTY;
f0d66275
DH		 3834 /*
3835 * This union makes it completely explicit to gcc-3.x
3836 * that these two variables' stack usage should be
3837 * combined, not added together.
3838 */
3839 union {
3840 struct kvm_pit_state ps;
e9f42757 3841 struct kvm_pit_state2 ps2;
c5ff41ce 3842 struct kvm_pit_config pit_config;
f0d66275 3843 } u;
1fe779f8
CO		 3844
3845 switch (ioctl) {
3846 case KVM_SET_TSS_ADDR:
3847 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3848 break;
b927a3ce
SY		 3849 case KVM_SET_IDENTITY_MAP_ADDR: {
3850 u64 ident_addr;
3851
3852 r = -EFAULT;
3853 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3854 goto out;
3855 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3856 break;
3857 }
1fe779f8
CO		 3858 case KVM_SET_NR_MMU_PAGES:
3859 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3860 break;
3861 case KVM_GET_NR_MMU_PAGES:
3862 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3863 break;
3ddea128
MT		 3864 case KVM_CREATE_IRQCHIP: {
3865 struct kvm_pic *vpic;
3866
3867 mutex_lock(&kvm->lock);
3868 r = -EEXIST;
3869 if (kvm->arch.vpic)
3870 goto create_irqchip_unlock;
3e515705 3871 r = -EINVAL;
557abc40 3872 if (kvm->created_vcpus)
3e515705 3873 goto create_irqchip_unlock;
1fe779f8 3874 r = -ENOMEM;
3ddea128
MT		 3875 vpic = kvm_create_pic(kvm);
3876 if (vpic) {
1fe779f8
CO		 3877 r = kvm_ioapic_init(kvm);
3878 if (r) {
175504cd 3879 mutex_lock(&kvm->slots_lock);
71ba994c 3880 kvm_destroy_pic(vpic);
175504cd 3881 mutex_unlock(&kvm->slots_lock);
3ddea128 3882 goto create_irqchip_unlock;
1fe779f8
CO		 3883 }
3884 } else
3ddea128 3885 goto create_irqchip_unlock;
399ec807
AK		 3886 r = kvm_setup_default_irq_routing(kvm);
3887 if (r) {
175504cd 3888 mutex_lock(&kvm->slots_lock);
3ddea128 3889 mutex_lock(&kvm->irq_lock);
72bb2fcd 3890 kvm_ioapic_destroy(kvm);
71ba994c 3891 kvm_destroy_pic(vpic);
3ddea128 3892 mutex_unlock(&kvm->irq_lock);
175504cd 3893 mutex_unlock(&kvm->slots_lock);
71ba994c 3894 goto create_irqchip_unlock;
399ec807 3895 }
71ba994c
PB		 3896 /* Write kvm->irq_routing before kvm->arch.vpic. */
3897 smp_wmb();
3898 kvm->arch.vpic = vpic;
3ddea128
MT		 3899 create_irqchip_unlock:
3900 mutex_unlock(&kvm->lock);
1fe779f8 3901 break;
3ddea128 3902 }
7837699f 3903 case KVM_CREATE_PIT:
c5ff41ce
JK		 3904 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3905 goto create_pit;
3906 case KVM_CREATE_PIT2:
3907 r = -EFAULT;
3908 if (copy_from_user(&u.pit_config, argp,
3909 sizeof(struct kvm_pit_config)))
3910 goto out;
3911 create_pit:
250715a6 3912 mutex_lock(&kvm->lock);
269e05e4
AK		 3913 r = -EEXIST;
3914 if (kvm->arch.vpit)
3915 goto create_pit_unlock;
7837699f 3916 r = -ENOMEM;
c5ff41ce 3917 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3918 if (kvm->arch.vpit)
3919 r = 0;
269e05e4 3920 create_pit_unlock:
250715a6 3921 mutex_unlock(&kvm->lock);
7837699f 3922 break;
1fe779f8
CO		 3923 case KVM_GET_IRQCHIP: {
3924 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3925 struct kvm_irqchip *chip;
1fe779f8 3926
ff5c2c03
SL		 3927 chip = memdup_user(argp, sizeof(*chip));
3928 if (IS_ERR(chip)) {
3929 r = PTR_ERR(chip);
1fe779f8 3930 goto out;
ff5c2c03
SL		 3931 }
3932
1fe779f8 3933 r = -ENXIO;
49df6397 3934 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3935 goto get_irqchip_out;
3936 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3937 if (r)
f0d66275 3938 goto get_irqchip_out;
1fe779f8 3939 r = -EFAULT;
f0d66275
DH		 3940 if (copy_to_user(argp, chip, sizeof *chip))
3941 goto get_irqchip_out;
1fe779f8 3942 r = 0;
f0d66275
DH		 3943 get_irqchip_out:
3944 kfree(chip);
1fe779f8
CO		 3945 break;
3946 }
3947 case KVM_SET_IRQCHIP: {
3948 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3949 struct kvm_irqchip *chip;
1fe779f8 3950
ff5c2c03
SL		 3951 chip = memdup_user(argp, sizeof(*chip));
3952 if (IS_ERR(chip)) {
3953 r = PTR_ERR(chip);
1fe779f8 3954 goto out;
ff5c2c03
SL		 3955 }
3956
1fe779f8 3957 r = -ENXIO;
49df6397 3958 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3959 goto set_irqchip_out;
3960 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3961 if (r)
f0d66275 3962 goto set_irqchip_out;
1fe779f8 3963 r = 0;
f0d66275
DH		 3964 set_irqchip_out:
3965 kfree(chip);
1fe779f8
CO		 3966 break;
3967 }
e0f63cb9 3968 case KVM_GET_PIT: {
e0f63cb9 3969 r = -EFAULT;
f0d66275 3970 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3971 goto out;
3972 r = -ENXIO;
3973 if (!kvm->arch.vpit)
3974 goto out;
f0d66275 3975 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3976 if (r)
3977 goto out;
3978 r = -EFAULT;
f0d66275 3979 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3980 goto out;
3981 r = 0;
3982 break;
3983 }
3984 case KVM_SET_PIT: {
e0f63cb9 3985 r = -EFAULT;
f0d66275 3986 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3987 goto out;
3988 r = -ENXIO;
3989 if (!kvm->arch.vpit)
3990 goto out;
f0d66275 3991 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3992 break;
3993 }
e9f42757
BK		 3994 case KVM_GET_PIT2: {
3995 r = -ENXIO;
3996 if (!kvm->arch.vpit)
3997 goto out;
3998 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3999 if (r)
4000 goto out;
4001 r = -EFAULT;
4002 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4003 goto out;
4004 r = 0;
4005 break;
4006 }
4007 case KVM_SET_PIT2: {
4008 r = -EFAULT;
4009 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4010 goto out;
4011 r = -ENXIO;
4012 if (!kvm->arch.vpit)
4013 goto out;
4014 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4015 break;
4016 }
52d939a0
MT		 4017 case KVM_REINJECT_CONTROL: {
4018 struct kvm_reinject_control control;
4019 r = -EFAULT;
4020 if (copy_from_user(&control, argp, sizeof(control)))
4021 goto out;
4022 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4023 break;
4024 }
d71ba788
PB		 4025 case KVM_SET_BOOT_CPU_ID:
4026 r = 0;
4027 mutex_lock(&kvm->lock);
557abc40 4028 if (kvm->created_vcpus)
d71ba788
PB		 4029 r = -EBUSY;
4030 else
4031 kvm->arch.bsp_vcpu_id = arg;
4032 mutex_unlock(&kvm->lock);
4033 break;
ffde22ac
ES		 4034 case KVM_XEN_HVM_CONFIG: {
4035 r = -EFAULT;
4036 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4037 sizeof(struct kvm_xen_hvm_config)))
4038 goto out;
4039 r = -EINVAL;
4040 if (kvm->arch.xen_hvm_config.flags)
4041 goto out;
4042 r = 0;
4043 break;
4044 }
afbcf7ab 4045 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4046 struct kvm_clock_data user_ns;
4047 u64 now_ns;
4048 s64 delta;
4049
4050 r = -EFAULT;
4051 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4052 goto out;
4053
4054 r = -EINVAL;
4055 if (user_ns.flags)
4056 goto out;
4057
4058 r = 0;
395c6b0a 4059 local_irq_disable();
759379dd 4060 now_ns = get_kernel_ns();
afbcf7ab 4061 delta = user_ns.clock - now_ns;
395c6b0a 4062 local_irq_enable();
afbcf7ab 4063 kvm->arch.kvmclock_offset = delta;
2e762ff7 4064 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4065 break;
4066 }
4067 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4068 struct kvm_clock_data user_ns;
4069 u64 now_ns;
4070
395c6b0a 4071 local_irq_disable();
759379dd 4072 now_ns = get_kernel_ns();
afbcf7ab 4073 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4074 local_irq_enable();
afbcf7ab 4075 user_ns.flags = 0;
97e69aa6 4076 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4077
4078 r = -EFAULT;
4079 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4080 goto out;
4081 r = 0;
4082 break;
4083 }
90de4a18
NA		 4084 case KVM_ENABLE_CAP: {
4085 struct kvm_enable_cap cap;
afbcf7ab 4086
90de4a18
NA		 4087 r = -EFAULT;
4088 if (copy_from_user(&cap, argp, sizeof(cap)))
4089 goto out;
4090 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4091 break;
4092 }
1fe779f8 4093 default:
c274e03a 4094 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4095 }
4096out:
4097 return r;
4098}
4099
a16b043c 4100static void kvm_init_msr_list(void)
043405e1
CO		 4101{
4102 u32 dummy[2];
4103 unsigned i, j;
4104
62ef68bb 4105 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4106 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4107 continue;
93c4adc7
PB		 4108
4109 /*
4110 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4111 * to the guests in some cases.
93c4adc7
PB		 4112 */
4113 switch (msrs_to_save[i]) {
4114 case MSR_IA32_BNDCFGS:
4115 if (!kvm_x86_ops->mpx_supported())
4116 continue;
4117 break;
9dbe6cf9
PB		 4118 case MSR_TSC_AUX:
4119 if (!kvm_x86_ops->rdtscp_supported())
4120 continue;
4121 break;
93c4adc7
PB		 4122 default:
4123 break;
4124 }
4125
043405e1
CO		 4126 if (j < i)
4127 msrs_to_save[j] = msrs_to_save[i];
4128 j++;
4129 }
4130 num_msrs_to_save = j;
62ef68bb
PB		 4131
4132 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4133 switch (emulated_msrs[i]) {
6d396b55
PB		 4134 case MSR_IA32_SMBASE:
4135 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4136 continue;
4137 break;
62ef68bb
PB		 4138 default:
4139 break;
4140 }
4141
4142 if (j < i)
4143 emulated_msrs[j] = emulated_msrs[i];
4144 j++;
4145 }
4146 num_emulated_msrs = j;
043405e1
CO		 4147}
4148
bda9020e
MT		 4149static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4150 const void *v)
bbd9b64e 4151{
70252a10
AK		 4152 int handled = 0;
4153 int n;
4154
4155 do {
4156 n = min(len, 8);
bce87cce 4157 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4158 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4159 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4160 break;
4161 handled += n;
4162 addr += n;
4163 len -= n;
4164 v += n;
4165 } while (len);
bbd9b64e 4166
70252a10 4167 return handled;
bbd9b64e
CO		 4168}
4169
bda9020e 4170static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4171{
70252a10
AK		 4172 int handled = 0;
4173 int n;
4174
4175 do {
4176 n = min(len, 8);
bce87cce 4177 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4178 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4179 addr, n, v))
4180 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4181 break;
4182 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4183 handled += n;
4184 addr += n;
4185 len -= n;
4186 v += n;
4187 } while (len);
bbd9b64e 4188
70252a10 4189 return handled;
bbd9b64e
CO		 4190}
4191
2dafc6c2
GN		 4192static void kvm_set_segment(struct kvm_vcpu *vcpu,
4193 struct kvm_segment *var, int seg)
4194{
4195 kvm_x86_ops->set_segment(vcpu, var, seg);
4196}
4197
4198void kvm_get_segment(struct kvm_vcpu *vcpu,
4199 struct kvm_segment *var, int seg)
4200{
4201 kvm_x86_ops->get_segment(vcpu, var, seg);
4202}
4203
54987b7a
PB		 4204gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4205 struct x86_exception *exception)
02f59dc9
JR		 4206{
4207 gpa_t t_gpa;
02f59dc9
JR		 4208
4209 BUG_ON(!mmu_is_nested(vcpu));
4210
4211 /* NPT walks are always user-walks */
4212 access |= PFERR_USER_MASK;
54987b7a 4213 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4214
4215 return t_gpa;
4216}
4217
ab9ae313
AK		 4218gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4219 struct x86_exception *exception)
1871c602
GN		 4220{
4221 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4222 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4223}
4224
ab9ae313
AK		 4225 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4226 struct x86_exception *exception)
1871c602
GN		 4227{
4228 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4229 access |= PFERR_FETCH_MASK;
ab9ae313 4230 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4231}
4232
ab9ae313
AK		 4233gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4234 struct x86_exception *exception)
1871c602
GN		 4235{
4236 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4237 access |= PFERR_WRITE_MASK;
ab9ae313 4238 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4239}
4240
4241/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4242gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4243 struct x86_exception *exception)
1871c602 4244{
ab9ae313 4245 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4246}
4247
4248static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4249 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4250 struct x86_exception *exception)
bbd9b64e
CO		 4251{
4252 void *data = val;
10589a46 4253 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4254
4255 while (bytes) {
14dfe855 4256 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4257 exception);
bbd9b64e 4258 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4259 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4260 int ret;
4261
bcc55cba 4262 if (gpa == UNMAPPED_GVA)
ab9ae313 4263 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4264 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4265 offset, toread);
10589a46 4266 if (ret < 0) {
c3cd7ffa 4267 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4268 goto out;
4269 }
bbd9b64e 4270
77c2002e
IE		 4271 bytes -= toread;
4272 data += toread;
4273 addr += toread;
bbd9b64e 4274 }
10589a46 4275out:
10589a46 4276 return r;
bbd9b64e 4277}
77c2002e 4278
1871c602 4279/* used for instruction fetching */
0f65dd70
AK		 4280static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4281 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4282 struct x86_exception *exception)
1871c602 4283{
0f65dd70 4284 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4285 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4286 unsigned offset;
4287 int ret;
0f65dd70 4288
44583cba
PB		 4289 /* Inline kvm_read_guest_virt_helper for speed. */
4290 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4291 exception);
4292 if (unlikely(gpa == UNMAPPED_GVA))
4293 return X86EMUL_PROPAGATE_FAULT;
4294
4295 offset = addr & (PAGE_SIZE-1);
4296 if (WARN_ON(offset + bytes > PAGE_SIZE))
4297 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4298 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4299 offset, bytes);
44583cba
PB		 4300 if (unlikely(ret < 0))
4301 return X86EMUL_IO_NEEDED;
4302
4303 return X86EMUL_CONTINUE;
1871c602
GN		 4304}
4305
064aea77 4306int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4307 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4308 struct x86_exception *exception)
1871c602 4309{
0f65dd70 4310 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4311 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4312
1871c602 4313 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4314 exception);
1871c602 4315}
064aea77 4316EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4317
0f65dd70
AK		 4318static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4319 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4320 struct x86_exception *exception)
1871c602 4321{
0f65dd70 4322 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4323 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4324}
4325
7a036a6f
RK		 4326static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4327 unsigned long addr, void *val, unsigned int bytes)
4328{
4329 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4330 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4331
4332 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4333}
4334
6a4d7550 4335int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4336 gva_t addr, void *val,
2dafc6c2 4337 unsigned int bytes,
bcc55cba 4338 struct x86_exception *exception)
77c2002e 4339{
0f65dd70 4340 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4341 void *data = val;
4342 int r = X86EMUL_CONTINUE;
4343
4344 while (bytes) {
14dfe855
JR		 4345 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4346 PFERR_WRITE_MASK,
ab9ae313 4347 exception);
77c2002e
IE		 4348 unsigned offset = addr & (PAGE_SIZE-1);
4349 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4350 int ret;
4351
bcc55cba 4352 if (gpa == UNMAPPED_GVA)
ab9ae313 4353 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4354 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4355 if (ret < 0) {
c3cd7ffa 4356 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4357 goto out;
4358 }
4359
4360 bytes -= towrite;
4361 data += towrite;
4362 addr += towrite;
4363 }
4364out:
4365 return r;
4366}
6a4d7550 4367EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4368
af7cc7d1
XG		 4369static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4370 gpa_t *gpa, struct x86_exception *exception,
4371 bool write)
4372{
97d64b78
AK		 4373 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4374 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4375
be94f6b7
HH		 4376 /*
4377 * currently PKRU is only applied to ept enabled guest so
4378 * there is no pkey in EPT page table for L1 guest or EPT
4379 * shadow page table for L2 guest.
4380 */
97d64b78 4381 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4382 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4383 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4384 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4385 (gva & (PAGE_SIZE - 1));
4f022648 4386 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4387 return 1;
4388 }
4389
af7cc7d1
XG		 4390 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4391
4392 if (*gpa == UNMAPPED_GVA)
4393 return -1;
4394
4395 /* For APIC access vmexit */
4396 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4397 return 1;
4398
4f022648
XG		 4399 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4400 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4401 return 1;
4f022648 4402 }
bebb106a 4403
af7cc7d1
XG		 4404 return 0;
4405}
4406
3200f405 4407int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4408 const void *val, int bytes)
bbd9b64e
CO		 4409{
4410 int ret;
4411
54bf36aa 4412 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4413 if (ret < 0)
bbd9b64e 4414 return 0;
0eb05bf2 4415 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4416 return 1;
4417}
4418
77d197b2
XG		 4419struct read_write_emulator_ops {
4420 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4421 int bytes);
4422 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4423 void *val, int bytes);
4424 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4425 int bytes, void *val);
4426 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4427 void *val, int bytes);
4428 bool write;
4429};
4430
4431static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4432{
4433 if (vcpu->mmio_read_completed) {
77d197b2 4434 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4435 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4436 vcpu->mmio_read_completed = 0;
4437 return 1;
4438 }
4439
4440 return 0;
4441}
4442
4443static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4444 void *val, int bytes)
4445{
54bf36aa 4446 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4447}
4448
4449static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4450 void *val, int bytes)
4451{
4452 return emulator_write_phys(vcpu, gpa, val, bytes);
4453}
4454
4455static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4456{
4457 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4458 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4459}
4460
4461static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4462 void *val, int bytes)
4463{
4464 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4465 return X86EMUL_IO_NEEDED;
4466}
4467
4468static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4469 void *val, int bytes)
4470{
f78146b0
AK		 4471 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4472
87da7e66 4473 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4474 return X86EMUL_CONTINUE;
4475}
4476
0fbe9b0b 4477static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4478 .read_write_prepare = read_prepare,
4479 .read_write_emulate = read_emulate,
4480 .read_write_mmio = vcpu_mmio_read,
4481 .read_write_exit_mmio = read_exit_mmio,
4482};
4483
0fbe9b0b 4484static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4485 .read_write_emulate = write_emulate,
4486 .read_write_mmio = write_mmio,
4487 .read_write_exit_mmio = write_exit_mmio,
4488 .write = true,
4489};
4490
22388a3c
XG		 4491static int emulator_read_write_onepage(unsigned long addr, void *val,
4492 unsigned int bytes,
4493 struct x86_exception *exception,
4494 struct kvm_vcpu *vcpu,
0fbe9b0b 4495 const struct read_write_emulator_ops *ops)
bbd9b64e 4496{
af7cc7d1
XG		 4497 gpa_t gpa;
4498 int handled, ret;
22388a3c 4499 bool write = ops->write;
f78146b0 4500 struct kvm_mmio_fragment *frag;
10589a46 4501
22388a3c 4502 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4503
af7cc7d1 4504 if (ret < 0)
bbd9b64e 4505 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4506
4507 /* For APIC access vmexit */
af7cc7d1 4508 if (ret)
bbd9b64e
CO		 4509 goto mmio;
4510
22388a3c 4511 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4512 return X86EMUL_CONTINUE;
4513
4514mmio:
4515 /*
4516 * Is this MMIO handled locally?
4517 */
22388a3c 4518 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4519 if (handled == bytes)
bbd9b64e 4520 return X86EMUL_CONTINUE;
bbd9b64e 4521
70252a10
AK		 4522 gpa += handled;
4523 bytes -= handled;
4524 val += handled;
4525
87da7e66
XG		 4526 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4527 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4528 frag->gpa = gpa;
4529 frag->data = val;
4530 frag->len = bytes;
f78146b0 4531 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4532}
4533
52eb5a6d
XL		 4534static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4535 unsigned long addr,
22388a3c
XG		 4536 void *val, unsigned int bytes,
4537 struct x86_exception *exception,
0fbe9b0b 4538 const struct read_write_emulator_ops *ops)
bbd9b64e 4539{
0f65dd70 4540 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4541 gpa_t gpa;
4542 int rc;
4543
4544 if (ops->read_write_prepare &&
4545 ops->read_write_prepare(vcpu, val, bytes))
4546 return X86EMUL_CONTINUE;
4547
4548 vcpu->mmio_nr_fragments = 0;
0f65dd70 4549
bbd9b64e
CO		 4550 /* Crossing a page boundary? */
4551 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4552 int now;
bbd9b64e
CO		 4553
4554 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4555 rc = emulator_read_write_onepage(addr, val, now, exception,
4556 vcpu, ops);
4557
bbd9b64e
CO		 4558 if (rc != X86EMUL_CONTINUE)
4559 return rc;
4560 addr += now;
bac15531
NA		 4561 if (ctxt->mode != X86EMUL_MODE_PROT64)
4562 addr = (u32)addr;
bbd9b64e
CO		 4563 val += now;
4564 bytes -= now;
4565 }
22388a3c 4566
f78146b0
AK		 4567 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4568 vcpu, ops);
4569 if (rc != X86EMUL_CONTINUE)
4570 return rc;
4571
4572 if (!vcpu->mmio_nr_fragments)
4573 return rc;
4574
4575 gpa = vcpu->mmio_fragments[0].gpa;
4576
4577 vcpu->mmio_needed = 1;
4578 vcpu->mmio_cur_fragment = 0;
4579
87da7e66 4580 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4581 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4582 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4583 vcpu->run->mmio.phys_addr = gpa;
4584
4585 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4586}
4587
4588static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4589 unsigned long addr,
4590 void *val,
4591 unsigned int bytes,
4592 struct x86_exception *exception)
4593{
4594 return emulator_read_write(ctxt, addr, val, bytes,
4595 exception, &read_emultor);
4596}
4597
52eb5a6d 4598static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4599 unsigned long addr,
4600 const void *val,
4601 unsigned int bytes,
4602 struct x86_exception *exception)
4603{
4604 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4605 exception, &write_emultor);
bbd9b64e 4606}
bbd9b64e 4607
daea3e73
AK		 4608#define CMPXCHG_TYPE(t, ptr, old, new) \
4609 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4610
4611#ifdef CONFIG_X86_64
4612# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4613#else
4614# define CMPXCHG64(ptr, old, new) \
9749a6c0 4615 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4616#endif
4617
0f65dd70
AK		 4618static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4619 unsigned long addr,
bbd9b64e
CO		 4620 const void *old,
4621 const void *new,
4622 unsigned int bytes,
0f65dd70 4623 struct x86_exception *exception)
bbd9b64e 4624{
0f65dd70 4625 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4626 gpa_t gpa;
4627 struct page *page;
4628 char *kaddr;
4629 bool exchanged;
2bacc55c 4630
daea3e73
AK		 4631 /* guests cmpxchg8b have to be emulated atomically */
4632 if (bytes > 8 || (bytes & (bytes - 1)))
4633 goto emul_write;
10589a46 4634
daea3e73 4635 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4636
daea3e73
AK		 4637 if (gpa == UNMAPPED_GVA ||
4638 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4639 goto emul_write;
2bacc55c 4640
daea3e73
AK		 4641 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4642 goto emul_write;
72dc67a6 4643
54bf36aa 4644 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4645 if (is_error_page(page))
c19b8bd6 4646 goto emul_write;
72dc67a6 4647
8fd75e12 4648 kaddr = kmap_atomic(page);
daea3e73
AK		 4649 kaddr += offset_in_page(gpa);
4650 switch (bytes) {
4651 case 1:
4652 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4653 break;
4654 case 2:
4655 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4656 break;
4657 case 4:
4658 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4659 break;
4660 case 8:
4661 exchanged = CMPXCHG64(kaddr, old, new);
4662 break;
4663 default:
4664 BUG();
2bacc55c 4665 }
8fd75e12 4666 kunmap_atomic(kaddr);
daea3e73
AK		 4667 kvm_release_page_dirty(page);
4668
4669 if (!exchanged)
4670 return X86EMUL_CMPXCHG_FAILED;
4671
54bf36aa 4672 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4673 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4674
4675 return X86EMUL_CONTINUE;
4a5f48f6 4676
3200f405 4677emul_write:
daea3e73 4678 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4679
0f65dd70 4680 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4681}
4682
cf8f70bf
GN		 4683static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4684{
4685 /* TODO: String I/O for in kernel device */
4686 int r;
4687
4688 if (vcpu->arch.pio.in)
e32edf4f 4689 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4690 vcpu->arch.pio.size, pd);
4691 else
e32edf4f 4692 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4693 vcpu->arch.pio.port, vcpu->arch.pio.size,
4694 pd);
4695 return r;
4696}
4697
6f6fbe98
XG		 4698static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4699 unsigned short port, void *val,
4700 unsigned int count, bool in)
cf8f70bf 4701{
cf8f70bf 4702 vcpu->arch.pio.port = port;
6f6fbe98 4703 vcpu->arch.pio.in = in;
7972995b 4704 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4705 vcpu->arch.pio.size = size;
4706
4707 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4708 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4709 return 1;
4710 }
4711
4712 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4713 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4714 vcpu->run->io.size = size;
4715 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4716 vcpu->run->io.count = count;
4717 vcpu->run->io.port = port;
4718
4719 return 0;
4720}
4721
6f6fbe98
XG		 4722static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4723 int size, unsigned short port, void *val,
4724 unsigned int count)
cf8f70bf 4725{
ca1d4a9e 4726 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4727 int ret;
ca1d4a9e 4728
6f6fbe98
XG		 4729 if (vcpu->arch.pio.count)
4730 goto data_avail;
cf8f70bf 4731
6f6fbe98
XG		 4732 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4733 if (ret) {
4734data_avail:
4735 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4736 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4737 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4738 return 1;
4739 }
4740
cf8f70bf
GN		 4741 return 0;
4742}
4743
6f6fbe98
XG		 4744static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4745 int size, unsigned short port,
4746 const void *val, unsigned int count)
4747{
4748 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4749
4750 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4751 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4752 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4753}
4754
bbd9b64e
CO		 4755static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4756{
4757 return kvm_x86_ops->get_segment_base(vcpu, seg);
4758}
4759
3cb16fe7 4760static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4761{
3cb16fe7 4762 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4763}
4764
5cb56059 4765int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4766{
4767 if (!need_emulate_wbinvd(vcpu))
4768 return X86EMUL_CONTINUE;
4769
4770 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4771 int cpu = get_cpu();
4772
4773 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4774 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4775 wbinvd_ipi, NULL, 1);
2eec7343 4776 put_cpu();
f5f48ee1 4777 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4778 } else
4779 wbinvd();
f5f48ee1
SY		 4780 return X86EMUL_CONTINUE;
4781}
5cb56059
JS		 4782
4783int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4784{
4785 kvm_x86_ops->skip_emulated_instruction(vcpu);
4786 return kvm_emulate_wbinvd_noskip(vcpu);
4787}
f5f48ee1
SY		 4788EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4789
5cb56059
JS		 4790
4791
bcaf5cc5
AK		 4792static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4793{
5cb56059 4794 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4795}
4796
52eb5a6d
XL		 4797static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4798 unsigned long *dest)
bbd9b64e 4799{
16f8a6f9 4800 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4801}
4802
52eb5a6d
XL		 4803static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4804 unsigned long value)
bbd9b64e 4805{
338dbc97 4806
717746e3 4807 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4808}
4809
52a46617 4810static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4811{
52a46617 4812 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4813}
4814
717746e3 4815static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4816{
717746e3 4817 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4818 unsigned long value;
4819
4820 switch (cr) {
4821 case 0:
4822 value = kvm_read_cr0(vcpu);
4823 break;
4824 case 2:
4825 value = vcpu->arch.cr2;
4826 break;
4827 case 3:
9f8fe504 4828 value = kvm_read_cr3(vcpu);
52a46617
GN		 4829 break;
4830 case 4:
4831 value = kvm_read_cr4(vcpu);
4832 break;
4833 case 8:
4834 value = kvm_get_cr8(vcpu);
4835 break;
4836 default:
a737f256 4837 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4838 return 0;
4839 }
4840
4841 return value;
4842}
4843
717746e3 4844static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4845{
717746e3 4846 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4847 int res = 0;
4848
52a46617
GN		 4849 switch (cr) {
4850 case 0:
49a9b07e 4851 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4852 break;
4853 case 2:
4854 vcpu->arch.cr2 = val;
4855 break;
4856 case 3:
2390218b 4857 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4858 break;
4859 case 4:
a83b29c6 4860 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4861 break;
4862 case 8:
eea1cff9 4863 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4864 break;
4865 default:
a737f256 4866 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4867 res = -1;
52a46617 4868 }
0f12244f
GN		 4869
4870 return res;
52a46617
GN		 4871}
4872
717746e3 4873static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4874{
717746e3 4875 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4876}
4877
4bff1e86 4878static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4879{
4bff1e86 4880 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4881}
4882
4bff1e86 4883static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4884{
4bff1e86 4885 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4886}
4887
1ac9d0cf
AK		 4888static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4889{
4890 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4891}
4892
4893static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4894{
4895 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4896}
4897
4bff1e86
AK		 4898static unsigned long emulator_get_cached_segment_base(
4899 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4900{
4bff1e86 4901 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4902}
4903
1aa36616
AK		 4904static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4905 struct desc_struct *desc, u32 *base3,
4906 int seg)
2dafc6c2
GN		 4907{
4908 struct kvm_segment var;
4909
4bff1e86 4910 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4911 *selector = var.selector;
2dafc6c2 4912
378a8b09
GN		 4913 if (var.unusable) {
4914 memset(desc, 0, sizeof(*desc));
2dafc6c2 4915 return false;
378a8b09 4916 }
2dafc6c2
GN		 4917
4918 if (var.g)
4919 var.limit >>= 12;
4920 set_desc_limit(desc, var.limit);
4921 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4922#ifdef CONFIG_X86_64
4923 if (base3)
4924 *base3 = var.base >> 32;
4925#endif
2dafc6c2
GN		 4926 desc->type = var.type;
4927 desc->s = var.s;
4928 desc->dpl = var.dpl;
4929 desc->p = var.present;
4930 desc->avl = var.avl;
4931 desc->l = var.l;
4932 desc->d = var.db;
4933 desc->g = var.g;
4934
4935 return true;
4936}
4937
1aa36616
AK		 4938static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4939 struct desc_struct *desc, u32 base3,
4940 int seg)
2dafc6c2 4941{
4bff1e86 4942 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4943 struct kvm_segment var;
4944
1aa36616 4945 var.selector = selector;
2dafc6c2 4946 var.base = get_desc_base(desc);
5601d05b
GN		 4947#ifdef CONFIG_X86_64
4948 var.base |= ((u64)base3) << 32;
4949#endif
2dafc6c2
GN		 4950 var.limit = get_desc_limit(desc);
4951 if (desc->g)
4952 var.limit = (var.limit << 12) | 0xfff;
4953 var.type = desc->type;
2dafc6c2
GN		 4954 var.dpl = desc->dpl;
4955 var.db = desc->d;
4956 var.s = desc->s;
4957 var.l = desc->l;
4958 var.g = desc->g;
4959 var.avl = desc->avl;
4960 var.present = desc->p;
4961 var.unusable = !var.present;
4962 var.padding = 0;
4963
4964 kvm_set_segment(vcpu, &var, seg);
4965 return;
4966}
4967
717746e3
AK		 4968static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4969 u32 msr_index, u64 *pdata)
4970{
609e36d3
PB		 4971 struct msr_data msr;
4972 int r;
4973
4974 msr.index = msr_index;
4975 msr.host_initiated = false;
4976 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4977 if (r)
4978 return r;
4979
4980 *pdata = msr.data;
4981 return 0;
717746e3
AK		 4982}
4983
4984static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4985 u32 msr_index, u64 data)
4986{
8fe8ab46
WA		 4987 struct msr_data msr;
4988
4989 msr.data = data;
4990 msr.index = msr_index;
4991 msr.host_initiated = false;
4992 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4993}
4994
64d60670
PB		 4995static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4996{
4997 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4998
4999 return vcpu->arch.smbase;
5000}
5001
5002static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5003{
5004 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5005
5006 vcpu->arch.smbase = smbase;
5007}
5008
67f4d428
NA		 5009static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5010 u32 pmc)
5011{
c6702c9d 5012 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5013}
5014
222d21aa
AK		 5015static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5016 u32 pmc, u64 *pdata)
5017{
c6702c9d 5018 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5019}
5020
6c3287f7
AK		 5021static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5022{
5023 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5024}
5025
5037f6f3
AK		 5026static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5027{
5028 preempt_disable();
5197b808 5029 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5030 /*
5031 * CR0.TS may reference the host fpu state, not the guest fpu state,
5032 * so it may be clear at this point.
5033 */
5034 clts();
5035}
5036
5037static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5038{
5039 preempt_enable();
5040}
5041
2953538e 5042static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5043 struct x86_instruction_info *info,
c4f035c6
AK		 5044 enum x86_intercept_stage stage)
5045{
2953538e 5046 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5047}
5048
0017f93a 5049static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5050 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5051{
0017f93a 5052 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5053}
5054
dd856efa
AK		 5055static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5056{
5057 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5058}
5059
5060static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5061{
5062 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5063}
5064
801806d9
NA		 5065static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5066{
5067 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5068}
5069
0225fb50 5070static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5071 .read_gpr = emulator_read_gpr,
5072 .write_gpr = emulator_write_gpr,
1871c602 5073 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5074 .write_std = kvm_write_guest_virt_system,
7a036a6f 5075 .read_phys = kvm_read_guest_phys_system,
1871c602 5076 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5077 .read_emulated = emulator_read_emulated,
5078 .write_emulated = emulator_write_emulated,
5079 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5080 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5081 .pio_in_emulated = emulator_pio_in_emulated,
5082 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5083 .get_segment = emulator_get_segment,
5084 .set_segment = emulator_set_segment,
5951c442 5085 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5086 .get_gdt = emulator_get_gdt,
160ce1f1 5087 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5088 .set_gdt = emulator_set_gdt,
5089 .set_idt = emulator_set_idt,
52a46617
GN		 5090 .get_cr = emulator_get_cr,
5091 .set_cr = emulator_set_cr,
9c537244 5092 .cpl = emulator_get_cpl,
35aa5375
GN		 5093 .get_dr = emulator_get_dr,
5094 .set_dr = emulator_set_dr,
64d60670
PB		 5095 .get_smbase = emulator_get_smbase,
5096 .set_smbase = emulator_set_smbase,
717746e3
AK		 5097 .set_msr = emulator_set_msr,
5098 .get_msr = emulator_get_msr,
67f4d428 5099 .check_pmc = emulator_check_pmc,
222d21aa 5100 .read_pmc = emulator_read_pmc,
6c3287f7 5101 .halt = emulator_halt,
bcaf5cc5 5102 .wbinvd = emulator_wbinvd,
d6aa1000 5103 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5104 .get_fpu = emulator_get_fpu,
5105 .put_fpu = emulator_put_fpu,
c4f035c6 5106 .intercept = emulator_intercept,
bdb42f5a 5107 .get_cpuid = emulator_get_cpuid,
801806d9 5108 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5109};
5110
95cb2295
GN		 5111static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5112{
37ccdcbe 5113 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5114 /*
5115 * an sti; sti; sequence only disable interrupts for the first
5116 * instruction. So, if the last instruction, be it emulated or
5117 * not, left the system with the INT_STI flag enabled, it
5118 * means that the last instruction is an sti. We should not
5119 * leave the flag on in this case. The same goes for mov ss
5120 */
37ccdcbe
PB		 5121 if (int_shadow & mask)
5122 mask = 0;
6addfc42 5123 if (unlikely(int_shadow || mask)) {
95cb2295 5124 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5125 if (!mask)
5126 kvm_make_request(KVM_REQ_EVENT, vcpu);
5127 }
95cb2295
GN		 5128}
5129
ef54bcfe 5130static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5131{
5132 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5133 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5134 return kvm_propagate_fault(vcpu, &ctxt->exception);
5135
5136 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5137 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5138 ctxt->exception.error_code);
54b8486f 5139 else
da9cb575 5140 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5141 return false;
54b8486f
GN		 5142}
5143
8ec4722d
MG		 5144static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5145{
adf52235 5146 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5147 int cs_db, cs_l;
5148
8ec4722d
MG		 5149 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5150
adf52235
TY		 5151 ctxt->eflags = kvm_get_rflags(vcpu);
5152 ctxt->eip = kvm_rip_read(vcpu);
5153 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5154 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5155 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5156 cs_db ? X86EMUL_MODE_PROT32 :
5157 X86EMUL_MODE_PROT16;
a584539b 5158 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5159 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5160 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5161 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5162
dd856efa 5163 init_decode_cache(ctxt);
7ae441ea 5164 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5165}
5166
71f9833b 5167int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5168{
9d74191a 5169 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5170 int ret;
5171
5172 init_emulate_ctxt(vcpu);
5173
9dac77fa
AK		 5174 ctxt->op_bytes = 2;
5175 ctxt->ad_bytes = 2;
5176 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5177 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5178
5179 if (ret != X86EMUL_CONTINUE)
5180 return EMULATE_FAIL;
5181
9dac77fa 5182 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5183 kvm_rip_write(vcpu, ctxt->eip);
5184 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5185
5186 if (irq == NMI_VECTOR)
7460fb4a 5187 vcpu->arch.nmi_pending = 0;
63995653
MG		 5188 else
5189 vcpu->arch.interrupt.pending = false;
5190
5191 return EMULATE_DONE;
5192}
5193EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5194
6d77dbfc
GN		 5195static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5196{
fc3a9157
JR		 5197 int r = EMULATE_DONE;
5198
6d77dbfc
GN		 5199 ++vcpu->stat.insn_emulation_fail;
5200 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5201 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5202 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5203 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5204 vcpu->run->internal.ndata = 0;
5205 r = EMULATE_FAIL;
5206 }
6d77dbfc 5207 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5208
5209 return r;
6d77dbfc
GN		 5210}
5211
93c05d3e 5212static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5213 bool write_fault_to_shadow_pgtable,
5214 int emulation_type)
a6f177ef 5215{
95b3cf69 5216 gpa_t gpa = cr2;
ba049e93 5217 kvm_pfn_t pfn;
a6f177ef 5218
991eebf9
GN		 5219 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5220 return false;
5221
95b3cf69
XG		 5222 if (!vcpu->arch.mmu.direct_map) {
5223 /*
5224 * Write permission should be allowed since only
5225 * write access need to be emulated.
5226 */
5227 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5228
95b3cf69
XG		 5229 /*
5230 * If the mapping is invalid in guest, let cpu retry
5231 * it to generate fault.
5232 */
5233 if (gpa == UNMAPPED_GVA)
5234 return true;
5235 }
a6f177ef 5236
8e3d9d06
XG		 5237 /*
5238 * Do not retry the unhandleable instruction if it faults on the
5239 * readonly host memory, otherwise it will goto a infinite loop:
5240 * retry instruction -> write #PF -> emulation fail -> retry
5241 * instruction -> ...
5242 */
5243 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5244
5245 /*
5246 * If the instruction failed on the error pfn, it can not be fixed,
5247 * report the error to userspace.
5248 */
5249 if (is_error_noslot_pfn(pfn))
5250 return false;
5251
5252 kvm_release_pfn_clean(pfn);
5253
5254 /* The instructions are well-emulated on direct mmu. */
5255 if (vcpu->arch.mmu.direct_map) {
5256 unsigned int indirect_shadow_pages;
5257
5258 spin_lock(&vcpu->kvm->mmu_lock);
5259 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5260 spin_unlock(&vcpu->kvm->mmu_lock);
5261
5262 if (indirect_shadow_pages)
5263 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5264
a6f177ef 5265 return true;
8e3d9d06 5266 }
a6f177ef 5267
95b3cf69
XG		 5268 /*
5269 * if emulation was due to access to shadowed page table
5270 * and it failed try to unshadow page and re-enter the
5271 * guest to let CPU execute the instruction.
5272 */
5273 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5274
5275 /*
5276 * If the access faults on its page table, it can not
5277 * be fixed by unprotecting shadow page and it should
5278 * be reported to userspace.
5279 */
5280 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5281}
5282
1cb3f3ae
XG		 5283static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5284 unsigned long cr2, int emulation_type)
5285{
5286 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5287 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5288
5289 last_retry_eip = vcpu->arch.last_retry_eip;
5290 last_retry_addr = vcpu->arch.last_retry_addr;
5291
5292 /*
5293 * If the emulation is caused by #PF and it is non-page_table
5294 * writing instruction, it means the VM-EXIT is caused by shadow
5295 * page protected, we can zap the shadow page and retry this
5296 * instruction directly.
5297 *
5298 * Note: if the guest uses a non-page-table modifying instruction
5299 * on the PDE that points to the instruction, then we will unmap
5300 * the instruction and go to an infinite loop. So, we cache the
5301 * last retried eip and the last fault address, if we meet the eip
5302 * and the address again, we can break out of the potential infinite
5303 * loop.
5304 */
5305 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5306
5307 if (!(emulation_type & EMULTYPE_RETRY))
5308 return false;
5309
5310 if (x86_page_table_writing_insn(ctxt))
5311 return false;
5312
5313 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5314 return false;
5315
5316 vcpu->arch.last_retry_eip = ctxt->eip;
5317 vcpu->arch.last_retry_addr = cr2;
5318
5319 if (!vcpu->arch.mmu.direct_map)
5320 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5321
22368028 5322 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5323
5324 return true;
5325}
5326
716d51ab
GN		 5327static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5328static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5329
64d60670 5330static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5331{
64d60670 5332 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5333 /* This is a good place to trace that we are exiting SMM. */
5334 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5335
c43203ca
PB		 5336 /* Process a latched INIT or SMI, if any. */
5337 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5338 }
699023e2
PB		 5339
5340 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5341}
5342
5343static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5344{
5345 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5346
a584539b 5347 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5348
5349 if (changed & HF_SMM_MASK)
5350 kvm_smm_changed(vcpu);
a584539b
PB		 5351}
5352
4a1e10d5
PB		 5353static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5354 unsigned long *db)
5355{
5356 u32 dr6 = 0;
5357 int i;
5358 u32 enable, rwlen;
5359
5360 enable = dr7;
5361 rwlen = dr7 >> 16;
5362 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5363 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5364 dr6 |= (1 << i);
5365 return dr6;
5366}
5367
6addfc42 5368static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5369{
5370 struct kvm_run *kvm_run = vcpu->run;
5371
5372 /*
6addfc42
PB		 5373 * rflags is the old, "raw" value of the flags. The new value has
5374 * not been saved yet.
663f4c61
PB		 5375 *
5376 * This is correct even for TF set by the guest, because "the
5377 * processor will not generate this exception after the instruction
5378 * that sets the TF flag".
5379 */
663f4c61
PB		 5380 if (unlikely(rflags & X86_EFLAGS_TF)) {
5381 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5382 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5383 DR6_RTM;
663f4c61
PB		 5384 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5385 kvm_run->debug.arch.exception = DB_VECTOR;
5386 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5387 *r = EMULATE_USER_EXIT;
5388 } else {
5389 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5390 /*
5391 * "Certain debug exceptions may clear bit 0-3. The
5392 * remaining contents of the DR6 register are never
5393 * cleared by the processor".
5394 */
5395 vcpu->arch.dr6 &= ~15;
6f43ed01 5396 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5397 kvm_queue_exception(vcpu, DB_VECTOR);
5398 }
5399 }
5400}
5401
4a1e10d5
PB		 5402static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5403{
4a1e10d5
PB		 5404 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5405 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5406 struct kvm_run *kvm_run = vcpu->run;
5407 unsigned long eip = kvm_get_linear_rip(vcpu);
5408 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5409 vcpu->arch.guest_debug_dr7,
5410 vcpu->arch.eff_db);
5411
5412 if (dr6 != 0) {
6f43ed01 5413 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5414 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5415 kvm_run->debug.arch.exception = DB_VECTOR;
5416 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5417 *r = EMULATE_USER_EXIT;
5418 return true;
5419 }
5420 }
5421
4161a569
NA		 5422 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5423 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5424 unsigned long eip = kvm_get_linear_rip(vcpu);
5425 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5426 vcpu->arch.dr7,
5427 vcpu->arch.db);
5428
5429 if (dr6 != 0) {
5430 vcpu->arch.dr6 &= ~15;
6f43ed01 5431 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5432 kvm_queue_exception(vcpu, DB_VECTOR);
5433 *r = EMULATE_DONE;
5434 return true;
5435 }
5436 }
5437
5438 return false;
5439}
5440
51d8b661
AP		 5441int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5442 unsigned long cr2,
dc25e89e
AP		 5443 int emulation_type,
5444 void *insn,
5445 int insn_len)
bbd9b64e 5446{
95cb2295 5447 int r;
9d74191a 5448 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5449 bool writeback = true;
93c05d3e 5450 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5451
93c05d3e
XG		 5452 /*
5453 * Clear write_fault_to_shadow_pgtable here to ensure it is
5454 * never reused.
5455 */
5456 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5457 kvm_clear_exception_queue(vcpu);
8d7d8102 5458
571008da 5459 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5460 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5461
5462 /*
5463 * We will reenter on the same instruction since
5464 * we do not set complete_userspace_io. This does not
5465 * handle watchpoints yet, those would be handled in
5466 * the emulate_ops.
5467 */
5468 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5469 return r;
5470
9d74191a
TY		 5471 ctxt->interruptibility = 0;
5472 ctxt->have_exception = false;
e0ad0b47 5473 ctxt->exception.vector = -1;
9d74191a 5474 ctxt->perm_ok = false;
bbd9b64e 5475
b51e974f 5476 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5477
9d74191a 5478 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5479
e46479f8 5480 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5481 ++vcpu->stat.insn_emulation;
1d2887e2 5482 if (r != EMULATION_OK) {
4005996e
AK		 5483 if (emulation_type & EMULTYPE_TRAP_UD)
5484 return EMULATE_FAIL;
991eebf9
GN		 5485 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5486 emulation_type))
bbd9b64e 5487 return EMULATE_DONE;
6d77dbfc
GN		 5488 if (emulation_type & EMULTYPE_SKIP)
5489 return EMULATE_FAIL;
5490 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5491 }
5492 }
5493
ba8afb6b 5494 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5495 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5496 if (ctxt->eflags & X86_EFLAGS_RF)
5497 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5498 return EMULATE_DONE;
5499 }
5500
1cb3f3ae
XG		 5501 if (retry_instruction(ctxt, cr2, emulation_type))
5502 return EMULATE_DONE;
5503
7ae441ea 5504 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5505 changes registers values during IO operation */
7ae441ea
GN		 5506 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5507 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5508 emulator_invalidate_register_cache(ctxt);
7ae441ea 5509 }
4d2179e1 5510
5cd21917 5511restart:
9d74191a 5512 r = x86_emulate_insn(ctxt);
bbd9b64e 5513
775fde86
JR		 5514 if (r == EMULATION_INTERCEPTED)
5515 return EMULATE_DONE;
5516
d2ddd1c4 5517 if (r == EMULATION_FAILED) {
991eebf9
GN		 5518 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5519 emulation_type))
c3cd7ffa
GN		 5520 return EMULATE_DONE;
5521
6d77dbfc 5522 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5523 }
5524
9d74191a 5525 if (ctxt->have_exception) {
d2ddd1c4 5526 r = EMULATE_DONE;
ef54bcfe
PB		 5527 if (inject_emulated_exception(vcpu))
5528 return r;
d2ddd1c4 5529 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5530 if (!vcpu->arch.pio.in) {
5531 /* FIXME: return into emulator if single-stepping. */
3457e419 5532 vcpu->arch.pio.count = 0;
0912c977 5533 } else {
7ae441ea 5534 writeback = false;
716d51ab
GN		 5535 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5536 }
ac0a48c3 5537 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5538 } else if (vcpu->mmio_needed) {
5539 if (!vcpu->mmio_is_write)
5540 writeback = false;
ac0a48c3 5541 r = EMULATE_USER_EXIT;
716d51ab 5542 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5543 } else if (r == EMULATION_RESTART)
5cd21917 5544 goto restart;
d2ddd1c4
GN		 5545 else
5546 r = EMULATE_DONE;
f850e2e6 5547
7ae441ea 5548 if (writeback) {
6addfc42 5549 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5550 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5551 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5552 if (vcpu->arch.hflags != ctxt->emul_flags)
5553 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5554 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5555 if (r == EMULATE_DONE)
6addfc42 5556 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5557 if (!ctxt->have_exception ||
5558 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5559 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5560
5561 /*
5562 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5563 * do nothing, and it will be requested again as soon as
5564 * the shadow expires. But we still need to check here,
5565 * because POPF has no interrupt shadow.
5566 */
5567 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5568 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5569 } else
5570 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5571
5572 return r;
de7d789a 5573}
51d8b661 5574EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5575
cf8f70bf 5576int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5577{
cf8f70bf 5578 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5579 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5580 size, port, &val, 1);
cf8f70bf 5581 /* do not return to emulator after return from userspace */
7972995b 5582 vcpu->arch.pio.count = 0;
de7d789a
CO		 5583 return ret;
5584}
cf8f70bf 5585EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5586
251a5fd6 5587static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5588{
0a3aee0d 5589 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5590 return 0;
8cfdc000
ZA		 5591}
5592
5593static void tsc_khz_changed(void *data)
c8076604 5594{
8cfdc000
ZA		 5595 struct cpufreq_freqs *freq = data;
5596 unsigned long khz = 0;
5597
5598 if (data)
5599 khz = freq->new;
5600 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5601 khz = cpufreq_quick_get(raw_smp_processor_id());
5602 if (!khz)
5603 khz = tsc_khz;
0a3aee0d 5604 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5605}
5606
c8076604
GH		 5607static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5608 void *data)
5609{
5610 struct cpufreq_freqs *freq = data;
5611 struct kvm *kvm;
5612 struct kvm_vcpu *vcpu;
5613 int i, send_ipi = 0;
5614
8cfdc000
ZA		 5615 /*
5616 * We allow guests to temporarily run on slowing clocks,
5617 * provided we notify them after, or to run on accelerating
5618 * clocks, provided we notify them before. Thus time never
5619 * goes backwards.
5620 *
5621 * However, we have a problem. We can't atomically update
5622 * the frequency of a given CPU from this function; it is
5623 * merely a notifier, which can be called from any CPU.
5624 * Changing the TSC frequency at arbitrary points in time
5625 * requires a recomputation of local variables related to
5626 * the TSC for each VCPU. We must flag these local variables
5627 * to be updated and be sure the update takes place with the
5628 * new frequency before any guests proceed.
5629 *
5630 * Unfortunately, the combination of hotplug CPU and frequency
5631 * change creates an intractable locking scenario; the order
5632 * of when these callouts happen is undefined with respect to
5633 * CPU hotplug, and they can race with each other. As such,
5634 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5635 * undefined; you can actually have a CPU frequency change take
5636 * place in between the computation of X and the setting of the
5637 * variable. To protect against this problem, all updates of
5638 * the per_cpu tsc_khz variable are done in an interrupt
5639 * protected IPI, and all callers wishing to update the value
5640 * must wait for a synchronous IPI to complete (which is trivial
5641 * if the caller is on the CPU already). This establishes the
5642 * necessary total order on variable updates.
5643 *
5644 * Note that because a guest time update may take place
5645 * anytime after the setting of the VCPU's request bit, the
5646 * correct TSC value must be set before the request. However,
5647 * to ensure the update actually makes it to any guest which
5648 * starts running in hardware virtualization between the set
5649 * and the acquisition of the spinlock, we must also ping the
5650 * CPU after setting the request bit.
5651 *
5652 */
5653
c8076604
GH		 5654 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5655 return 0;
5656 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5657 return 0;
8cfdc000
ZA		 5658
5659 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5660
2f303b74 5661 spin_lock(&kvm_lock);
c8076604 5662 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5663 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5664 if (vcpu->cpu != freq->cpu)
5665 continue;
c285545f 5666 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5667 if (vcpu->cpu != smp_processor_id())
8cfdc000 5668 send_ipi = 1;
c8076604
GH		 5669 }
5670 }
2f303b74 5671 spin_unlock(&kvm_lock);
c8076604
GH		 5672
5673 if (freq->old < freq->new && send_ipi) {
5674 /*
5675 * We upscale the frequency. Must make the guest
5676 * doesn't see old kvmclock values while running with
5677 * the new frequency, otherwise we risk the guest sees
5678 * time go backwards.
5679 *
5680 * In case we update the frequency for another cpu
5681 * (which might be in guest context) send an interrupt
5682 * to kick the cpu out of guest context. Next time
5683 * guest context is entered kvmclock will be updated,
5684 * so the guest will not see stale values.
5685 */
8cfdc000 5686 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5687 }
5688 return 0;
5689}
5690
5691static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5692 .notifier_call = kvmclock_cpufreq_notifier
5693};
5694
251a5fd6 5695static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5696{
251a5fd6
SAS		 5697 tsc_khz_changed(NULL);
5698 return 0;
8cfdc000
ZA		 5699}
5700
b820cc0c
ZA		 5701static void kvm_timer_init(void)
5702{
5703 int cpu;
5704
c285545f 5705 max_tsc_khz = tsc_khz;
460dd42e 5706
b820cc0c 5707 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5708#ifdef CONFIG_CPU_FREQ
5709 struct cpufreq_policy policy;
5710 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5711 cpu = get_cpu();
5712 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5713 if (policy.cpuinfo.max_freq)
5714 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5715 put_cpu();
c285545f 5716#endif
b820cc0c
ZA		 5717 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5718 CPUFREQ_TRANSITION_NOTIFIER);
5719 }
c285545f 5720 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5721
251a5fd6
SAS		 5722 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "AP_X86_KVM_CLK_ONLINE",
5723 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5724}
5725
ff9d07a0
ZY		 5726static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5727
f5132b01 5728int kvm_is_in_guest(void)
ff9d07a0 5729{
086c9855 5730 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5731}
5732
5733static int kvm_is_user_mode(void)
5734{
5735 int user_mode = 3;
dcf46b94 5736
086c9855
AS		 5737 if (__this_cpu_read(current_vcpu))
5738 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5739
ff9d07a0
ZY		 5740 return user_mode != 0;
5741}
5742
5743static unsigned long kvm_get_guest_ip(void)
5744{
5745 unsigned long ip = 0;
dcf46b94 5746
086c9855
AS		 5747 if (__this_cpu_read(current_vcpu))
5748 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5749
ff9d07a0
ZY		 5750 return ip;
5751}
5752
5753static struct perf_guest_info_callbacks kvm_guest_cbs = {
5754 .is_in_guest = kvm_is_in_guest,
5755 .is_user_mode = kvm_is_user_mode,
5756 .get_guest_ip = kvm_get_guest_ip,
5757};
5758
5759void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5760{
086c9855 5761 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5762}
5763EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5764
5765void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5766{
086c9855 5767 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5768}
5769EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5770
ce88decf
XG		 5771static void kvm_set_mmio_spte_mask(void)
5772{
5773 u64 mask;
5774 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5775
5776 /*
5777 * Set the reserved bits and the present bit of an paging-structure
5778 * entry to generate page fault with PFER.RSV = 1.
5779 */
885032b9 5780 /* Mask the reserved physical address bits. */
d1431483 5781 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5782
5783 /* Bit 62 is always reserved for 32bit host. */
5784 mask |= 0x3ull << 62;
5785
5786 /* Set the present bit. */
ce88decf
XG		 5787 mask |= 1ull;
5788
5789#ifdef CONFIG_X86_64
5790 /*
5791 * If reserved bit is not supported, clear the present bit to disable
5792 * mmio page fault.
5793 */
5794 if (maxphyaddr == 52)
5795 mask &= ~1ull;
5796#endif
5797
5798 kvm_mmu_set_mmio_spte_mask(mask);
5799}
5800
16e8d74d
MT		 5801#ifdef CONFIG_X86_64
5802static void pvclock_gtod_update_fn(struct work_struct *work)
5803{
d828199e
MT		 5804 struct kvm *kvm;
5805
5806 struct kvm_vcpu *vcpu;
5807 int i;
5808
2f303b74 5809 spin_lock(&kvm_lock);
d828199e
MT		 5810 list_for_each_entry(kvm, &vm_list, vm_list)
5811 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5812 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5813 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5814 spin_unlock(&kvm_lock);
16e8d74d
MT		 5815}
5816
5817static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5818
5819/*
5820 * Notification about pvclock gtod data update.
5821 */
5822static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5823 void *priv)
5824{
5825 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5826 struct timekeeper *tk = priv;
5827
5828 update_pvclock_gtod(tk);
5829
5830 /* disable master clock if host does not trust, or does not
5831 * use, TSC clocksource
5832 */
5833 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5834 atomic_read(&kvm_guest_has_master_clock) != 0)
5835 queue_work(system_long_wq, &pvclock_gtod_work);
5836
5837 return 0;
5838}
5839
5840static struct notifier_block pvclock_gtod_notifier = {
5841 .notifier_call = pvclock_gtod_notify,
5842};
5843#endif
5844
f8c16bba 5845int kvm_arch_init(void *opaque)
043405e1 5846{
b820cc0c 5847 int r;
6b61edf7 5848 struct kvm_x86_ops *ops = opaque;
f8c16bba 5849
f8c16bba
ZX		 5850 if (kvm_x86_ops) {
5851 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5852 r = -EEXIST;
5853 goto out;
f8c16bba
ZX		 5854 }
5855
5856 if (!ops->cpu_has_kvm_support()) {
5857 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5858 r = -EOPNOTSUPP;
5859 goto out;
f8c16bba
ZX		 5860 }
5861 if (ops->disabled_by_bios()) {
5862 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5863 r = -EOPNOTSUPP;
5864 goto out;
f8c16bba
ZX		 5865 }
5866
013f6a5d
MT		 5867 r = -ENOMEM;
5868 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5869 if (!shared_msrs) {
5870 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5871 goto out;
5872 }
5873
97db56ce
AK		 5874 r = kvm_mmu_module_init();
5875 if (r)
013f6a5d 5876 goto out_free_percpu;
97db56ce 5877
ce88decf 5878 kvm_set_mmio_spte_mask();
97db56ce 5879
f8c16bba 5880 kvm_x86_ops = ops;
920c8377 5881
7b52345e 5882 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8
BD		 5883 PT_DIRTY_MASK, PT64_NX_MASK, 0,
5884 PT_PRESENT_MASK);
b820cc0c 5885 kvm_timer_init();
c8076604 5886
ff9d07a0
ZY		 5887 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5888
d366bf7e 5889 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 5890 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5891
c5cc421b 5892 kvm_lapic_init();
16e8d74d
MT		 5893#ifdef CONFIG_X86_64
5894 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5895#endif
5896
f8c16bba 5897 return 0;
56c6d28a 5898
013f6a5d
MT		 5899out_free_percpu:
5900 free_percpu(shared_msrs);
56c6d28a 5901out:
56c6d28a 5902 return r;
043405e1 5903}
8776e519 5904
f8c16bba
ZX		 5905void kvm_arch_exit(void)
5906{
ff9d07a0
ZY		 5907 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5908
888d256e
JK		 5909 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5910 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5911 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 5912 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 5913#ifdef CONFIG_X86_64
5914 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5915#endif
f8c16bba 5916 kvm_x86_ops = NULL;
56c6d28a 5917 kvm_mmu_module_exit();
013f6a5d 5918 free_percpu(shared_msrs);
56c6d28a 5919}
f8c16bba 5920
5cb56059 5921int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5922{
5923 ++vcpu->stat.halt_exits;
35754c98 5924 if (lapic_in_kernel(vcpu)) {
a4535290 5925 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5926 return 1;
5927 } else {
5928 vcpu->run->exit_reason = KVM_EXIT_HLT;
5929 return 0;
5930 }
5931}
5cb56059
JS		 5932EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5933
5934int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5935{
5936 kvm_x86_ops->skip_emulated_instruction(vcpu);
5937 return kvm_vcpu_halt(vcpu);
5938}
8776e519
HB		 5939EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5940
6aef266c
SV		 5941/*
5942 * kvm_pv_kick_cpu_op: Kick a vcpu.
5943 *
5944 * @apicid - apicid of vcpu to be kicked.
5945 */
5946static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5947{
24d2166b 5948 struct kvm_lapic_irq lapic_irq;
6aef266c 5949
24d2166b
R		 5950 lapic_irq.shorthand = 0;
5951 lapic_irq.dest_mode = 0;
5952 lapic_irq.dest_id = apicid;
93bbf0b8 5953 lapic_irq.msi_redir_hint = false;
6aef266c 5954
24d2166b 5955 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5956 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5957}
5958
d62caabb
AS		 5959void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5960{
5961 vcpu->arch.apicv_active = false;
5962 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5963}
5964
8776e519
HB		 5965int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5966{
5967 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5968 int op_64_bit, r = 1;
8776e519 5969
5cb56059
JS		 5970 kvm_x86_ops->skip_emulated_instruction(vcpu);
5971
55cd8e5a
GN		 5972 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5973 return kvm_hv_hypercall(vcpu);
5974
5fdbf976
MT		 5975 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5976 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5977 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5978 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5979 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5980
229456fc 5981 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5982
a449c7aa
NA		 5983 op_64_bit = is_64_bit_mode(vcpu);
5984 if (!op_64_bit) {
8776e519
HB		 5985 nr &= 0xFFFFFFFF;
5986 a0 &= 0xFFFFFFFF;
5987 a1 &= 0xFFFFFFFF;
5988 a2 &= 0xFFFFFFFF;
5989 a3 &= 0xFFFFFFFF;
5990 }
5991
07708c4a
JK		 5992 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5993 ret = -KVM_EPERM;
5994 goto out;
5995 }
5996
8776e519 5997 switch (nr) {
b93463aa
AK		 5998 case KVM_HC_VAPIC_POLL_IRQ:
5999 ret = 0;
6000 break;
6aef266c
SV		 6001 case KVM_HC_KICK_CPU:
6002 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6003 ret = 0;
6004 break;
8776e519
HB		 6005 default:
6006 ret = -KVM_ENOSYS;
6007 break;
6008 }
07708c4a 6009out:
a449c7aa
NA		 6010 if (!op_64_bit)
6011 ret = (u32)ret;
5fdbf976 6012 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6013 ++vcpu->stat.hypercalls;
2f333bcb 6014 return r;
8776e519
HB		 6015}
6016EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6017
b6785def 6018static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6019{
d6aa1000 6020 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6021 char instruction[3];
5fdbf976 6022 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6023
8776e519 6024 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6025
9d74191a 6026 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6027}
6028
851ba692 6029static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6030{
782d422b
MG		 6031 return vcpu->run->request_interrupt_window &&
6032 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6033}
6034
851ba692 6035static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6036{
851ba692
AK		 6037 struct kvm_run *kvm_run = vcpu->run;
6038
91586a3b 6039 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6040 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6041 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6042 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6043 kvm_run->ready_for_interrupt_injection =
6044 pic_in_kernel(vcpu->kvm) ||
782d422b 6045 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6046}
6047
95ba8273
GN		 6048static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6049{
6050 int max_irr, tpr;
6051
6052 if (!kvm_x86_ops->update_cr8_intercept)
6053 return;
6054
bce87cce 6055 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6056 return;
6057
d62caabb
AS		 6058 if (vcpu->arch.apicv_active)
6059 return;
6060
8db3baa2
GN		 6061 if (!vcpu->arch.apic->vapic_addr)
6062 max_irr = kvm_lapic_find_highest_irr(vcpu);
6063 else
6064 max_irr = -1;
95ba8273
GN		 6065
6066 if (max_irr != -1)
6067 max_irr >>= 4;
6068
6069 tpr = kvm_lapic_get_cr8(vcpu);
6070
6071 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6072}
6073
b6b8a145 6074static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6075{
b6b8a145
JK		 6076 int r;
6077
95ba8273 6078 /* try to reinject previous events if any */
b59bb7bd 6079 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6080 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6081 vcpu->arch.exception.has_error_code,
6082 vcpu->arch.exception.error_code);
d6e8c854
NA		 6083
6084 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6085 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6086 X86_EFLAGS_RF);
6087
6bdf0662
NA		 6088 if (vcpu->arch.exception.nr == DB_VECTOR &&
6089 (vcpu->arch.dr7 & DR7_GD)) {
6090 vcpu->arch.dr7 &= ~DR7_GD;
6091 kvm_update_dr7(vcpu);
6092 }
6093
b59bb7bd
GN		 6094 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6095 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6096 vcpu->arch.exception.error_code,
6097 vcpu->arch.exception.reinject);
b6b8a145 6098 return 0;
b59bb7bd
GN		 6099 }
6100
95ba8273
GN		 6101 if (vcpu->arch.nmi_injected) {
6102 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6103 return 0;
95ba8273
GN		 6104 }
6105
6106 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6107 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6108 return 0;
6109 }
6110
6111 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6112 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6113 if (r != 0)
6114 return r;
95ba8273
GN		 6115 }
6116
6117 /* try to inject new event if pending */
c43203ca
PB		 6118 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6119 vcpu->arch.smi_pending = false;
ee2cd4b7 6120 enter_smm(vcpu);
c43203ca 6121 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6122 --vcpu->arch.nmi_pending;
6123 vcpu->arch.nmi_injected = true;
6124 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6125 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6126 /*
6127 * Because interrupts can be injected asynchronously, we are
6128 * calling check_nested_events again here to avoid a race condition.
6129 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6130 * proposal and current concerns. Perhaps we should be setting
6131 * KVM_REQ_EVENT only on certain events and not unconditionally?
6132 */
6133 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6134 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6135 if (r != 0)
6136 return r;
6137 }
95ba8273 6138 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6139 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6140 false);
6141 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6142 }
6143 }
ee2cd4b7 6144
b6b8a145 6145 return 0;
95ba8273
GN		 6146}
6147
7460fb4a
AK		 6148static void process_nmi(struct kvm_vcpu *vcpu)
6149{
6150 unsigned limit = 2;
6151
6152 /*
6153 * x86 is limited to one NMI running, and one NMI pending after it.
6154 * If an NMI is already in progress, limit further NMIs to just one.
6155 * Otherwise, allow two (and we'll inject the first one immediately).
6156 */
6157 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6158 limit = 1;
6159
6160 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6161 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6162 kvm_make_request(KVM_REQ_EVENT, vcpu);
6163}
6164
660a5d51
PB		 6165#define put_smstate(type, buf, offset, val) \
6166 *(type *)((buf) + (offset) - 0x7e00) = val
6167
ee2cd4b7 6168static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6169{
6170 u32 flags = 0;
6171 flags |= seg->g << 23;
6172 flags |= seg->db << 22;
6173 flags |= seg->l << 21;
6174 flags |= seg->avl << 20;
6175 flags |= seg->present << 15;
6176 flags |= seg->dpl << 13;
6177 flags |= seg->s << 12;
6178 flags |= seg->type << 8;
6179 return flags;
6180}
6181
ee2cd4b7 6182static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6183{
6184 struct kvm_segment seg;
6185 int offset;
6186
6187 kvm_get_segment(vcpu, &seg, n);
6188 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6189
6190 if (n < 3)
6191 offset = 0x7f84 + n * 12;
6192 else
6193 offset = 0x7f2c + (n - 3) * 12;
6194
6195 put_smstate(u32, buf, offset + 8, seg.base);
6196 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6197 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6198}
6199
efbb288a 6200#ifdef CONFIG_X86_64
ee2cd4b7 6201static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6202{
6203 struct kvm_segment seg;
6204 int offset;
6205 u16 flags;
6206
6207 kvm_get_segment(vcpu, &seg, n);
6208 offset = 0x7e00 + n * 16;
6209
ee2cd4b7 6210 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6211 put_smstate(u16, buf, offset, seg.selector);
6212 put_smstate(u16, buf, offset + 2, flags);
6213 put_smstate(u32, buf, offset + 4, seg.limit);
6214 put_smstate(u64, buf, offset + 8, seg.base);
6215}
efbb288a 6216#endif
660a5d51 6217
ee2cd4b7 6218static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6219{
6220 struct desc_ptr dt;
6221 struct kvm_segment seg;
6222 unsigned long val;
6223 int i;
6224
6225 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6226 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6227 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6228 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6229
6230 for (i = 0; i < 8; i++)
6231 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6232
6233 kvm_get_dr(vcpu, 6, &val);
6234 put_smstate(u32, buf, 0x7fcc, (u32)val);
6235 kvm_get_dr(vcpu, 7, &val);
6236 put_smstate(u32, buf, 0x7fc8, (u32)val);
6237
6238 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6239 put_smstate(u32, buf, 0x7fc4, seg.selector);
6240 put_smstate(u32, buf, 0x7f64, seg.base);
6241 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6242 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6243
6244 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6245 put_smstate(u32, buf, 0x7fc0, seg.selector);
6246 put_smstate(u32, buf, 0x7f80, seg.base);
6247 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6248 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6249
6250 kvm_x86_ops->get_gdt(vcpu, &dt);
6251 put_smstate(u32, buf, 0x7f74, dt.address);
6252 put_smstate(u32, buf, 0x7f70, dt.size);
6253
6254 kvm_x86_ops->get_idt(vcpu, &dt);
6255 put_smstate(u32, buf, 0x7f58, dt.address);
6256 put_smstate(u32, buf, 0x7f54, dt.size);
6257
6258 for (i = 0; i < 6; i++)
ee2cd4b7 6259 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6260
6261 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6262
6263 /* revision id */
6264 put_smstate(u32, buf, 0x7efc, 0x00020000);
6265 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6266}
6267
ee2cd4b7 6268static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6269{
6270#ifdef CONFIG_X86_64
6271 struct desc_ptr dt;
6272 struct kvm_segment seg;
6273 unsigned long val;
6274 int i;
6275
6276 for (i = 0; i < 16; i++)
6277 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6278
6279 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6280 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6281
6282 kvm_get_dr(vcpu, 6, &val);
6283 put_smstate(u64, buf, 0x7f68, val);
6284 kvm_get_dr(vcpu, 7, &val);
6285 put_smstate(u64, buf, 0x7f60, val);
6286
6287 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6288 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6289 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6290
6291 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6292
6293 /* revision id */
6294 put_smstate(u32, buf, 0x7efc, 0x00020064);
6295
6296 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6297
6298 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6299 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6300 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6301 put_smstate(u32, buf, 0x7e94, seg.limit);
6302 put_smstate(u64, buf, 0x7e98, seg.base);
6303
6304 kvm_x86_ops->get_idt(vcpu, &dt);
6305 put_smstate(u32, buf, 0x7e84, dt.size);
6306 put_smstate(u64, buf, 0x7e88, dt.address);
6307
6308 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6309 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6310 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6311 put_smstate(u32, buf, 0x7e74, seg.limit);
6312 put_smstate(u64, buf, 0x7e78, seg.base);
6313
6314 kvm_x86_ops->get_gdt(vcpu, &dt);
6315 put_smstate(u32, buf, 0x7e64, dt.size);
6316 put_smstate(u64, buf, 0x7e68, dt.address);
6317
6318 for (i = 0; i < 6; i++)
ee2cd4b7 6319 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6320#else
6321 WARN_ON_ONCE(1);
6322#endif
6323}
6324
ee2cd4b7 6325static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6326{
660a5d51 6327 struct kvm_segment cs, ds;
18c3626e 6328 struct desc_ptr dt;
660a5d51
PB		 6329 char buf[512];
6330 u32 cr0;
6331
660a5d51
PB		 6332 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6333 vcpu->arch.hflags |= HF_SMM_MASK;
6334 memset(buf, 0, 512);
6335 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6336 enter_smm_save_state_64(vcpu, buf);
660a5d51 6337 else
ee2cd4b7 6338 enter_smm_save_state_32(vcpu, buf);
660a5d51 6339
54bf36aa 6340 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6341
6342 if (kvm_x86_ops->get_nmi_mask(vcpu))
6343 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6344 else
6345 kvm_x86_ops->set_nmi_mask(vcpu, true);
6346
6347 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6348 kvm_rip_write(vcpu, 0x8000);
6349
6350 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6351 kvm_x86_ops->set_cr0(vcpu, cr0);
6352 vcpu->arch.cr0 = cr0;
6353
6354 kvm_x86_ops->set_cr4(vcpu, 0);
6355
18c3626e
PB		 6356 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6357 dt.address = dt.size = 0;
6358 kvm_x86_ops->set_idt(vcpu, &dt);
6359
660a5d51
PB		 6360 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6361
6362 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6363 cs.base = vcpu->arch.smbase;
6364
6365 ds.selector = 0;
6366 ds.base = 0;
6367
6368 cs.limit = ds.limit = 0xffffffff;
6369 cs.type = ds.type = 0x3;
6370 cs.dpl = ds.dpl = 0;
6371 cs.db = ds.db = 0;
6372 cs.s = ds.s = 1;
6373 cs.l = ds.l = 0;
6374 cs.g = ds.g = 1;
6375 cs.avl = ds.avl = 0;
6376 cs.present = ds.present = 1;
6377 cs.unusable = ds.unusable = 0;
6378 cs.padding = ds.padding = 0;
6379
6380 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6381 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6382 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6383 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6384 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6385 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6386
6387 if (guest_cpuid_has_longmode(vcpu))
6388 kvm_x86_ops->set_efer(vcpu, 0);
6389
6390 kvm_update_cpuid(vcpu);
6391 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6392}
6393
ee2cd4b7 6394static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6395{
6396 vcpu->arch.smi_pending = true;
6397 kvm_make_request(KVM_REQ_EVENT, vcpu);
6398}
6399
2860c4b1
PB		 6400void kvm_make_scan_ioapic_request(struct kvm *kvm)
6401{
6402 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6403}
6404
3d81bc7e 6405static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6406{
5c919412
AS		 6407 u64 eoi_exit_bitmap[4];
6408
3d81bc7e
YZ		 6409 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6410 return;
c7c9c56c 6411
6308630b 6412 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6413
b053b2ae 6414 if (irqchip_split(vcpu->kvm))
6308630b 6415 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6416 else {
d62caabb
AS		 6417 if (vcpu->arch.apicv_active)
6418 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6419 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6420 }
5c919412
AS		 6421 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6422 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6423 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6424}
6425
a70656b6
RK		 6426static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6427{
6428 ++vcpu->stat.tlb_flush;
6429 kvm_x86_ops->tlb_flush(vcpu);
6430}
6431
4256f43f
TC		 6432void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6433{
c24ae0dc
TC		 6434 struct page *page = NULL;
6435
35754c98 6436 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6437 return;
6438
4256f43f
TC		 6439 if (!kvm_x86_ops->set_apic_access_page_addr)
6440 return;
6441
c24ae0dc 6442 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6443 if (is_error_page(page))
6444 return;
c24ae0dc
TC		 6445 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6446
6447 /*
6448 * Do not pin apic access page in memory, the MMU notifier
6449 * will call us again if it is migrated or swapped out.
6450 */
6451 put_page(page);
4256f43f
TC		 6452}
6453EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6454
fe71557a
TC		 6455void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6456 unsigned long address)
6457{
c24ae0dc
TC		 6458 /*
6459 * The physical address of apic access page is stored in the VMCS.
6460 * Update it when it becomes invalid.
6461 */
6462 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6463 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6464}
6465
9357d939 6466/*
362c698f 6467 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6468 * exiting to the userspace. Otherwise, the value will be returned to the
6469 * userspace.
6470 */
851ba692 6471static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6472{
6473 int r;
62a193ed
MG		 6474 bool req_int_win =
6475 dm_request_for_irq_injection(vcpu) &&
6476 kvm_cpu_accept_dm_intr(vcpu);
6477
730dca42 6478 bool req_immediate_exit = false;
b6c7a5dc 6479
3e007509 6480 if (vcpu->requests) {
a8eeb04a 6481 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6482 kvm_mmu_unload(vcpu);
a8eeb04a 6483 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6484 __kvm_migrate_timers(vcpu);
d828199e
MT		 6485 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6486 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6487 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6488 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6489 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6490 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6491 if (unlikely(r))
6492 goto out;
6493 }
a8eeb04a 6494 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6495 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6496 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6497 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6498 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6499 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6500 r = 0;
6501 goto out;
6502 }
a8eeb04a 6503 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6504 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6505 r = 0;
6506 goto out;
6507 }
a8eeb04a 6508 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6509 vcpu->fpu_active = 0;
6510 kvm_x86_ops->fpu_deactivate(vcpu);
6511 }
af585b92
GN		 6512 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6513 /* Page is swapped out. Do synthetic halt */
6514 vcpu->arch.apf.halted = true;
6515 r = 1;
6516 goto out;
6517 }
c9aaa895
GC		 6518 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6519 record_steal_time(vcpu);
64d60670
PB		 6520 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6521 process_smi(vcpu);
7460fb4a
AK		 6522 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6523 process_nmi(vcpu);
f5132b01 6524 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6525 kvm_pmu_handle_event(vcpu);
f5132b01 6526 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6527 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6528 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6529 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6530 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6531 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6532 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6533 vcpu->run->eoi.vector =
6534 vcpu->arch.pending_ioapic_eoi;
6535 r = 0;
6536 goto out;
6537 }
6538 }
3d81bc7e
YZ		 6539 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6540 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6541 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6542 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6543 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6544 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6545 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6546 r = 0;
6547 goto out;
6548 }
e516cebb
AS		 6549 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6550 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6551 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6552 r = 0;
6553 goto out;
6554 }
db397571
AS		 6555 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6556 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6557 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6558 r = 0;
6559 goto out;
6560 }
f3b138c5
AS		 6561
6562 /*
6563 * KVM_REQ_HV_STIMER has to be processed after
6564 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6565 * depend on the guest clock being up-to-date
6566 */
1f4b34f8
AS		 6567 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6568 kvm_hv_process_stimers(vcpu);
2f52d58c 6569 }
b93463aa 6570
bf9f6ac8
FW		 6571 /*
6572 * KVM_REQ_EVENT is not set when posted interrupts are set by
6573 * VT-d hardware, so we have to update RVI unconditionally.
6574 */
6575 if (kvm_lapic_enabled(vcpu)) {
6576 /*
6577 * Update architecture specific hints for APIC
6578 * virtual interrupt delivery.
6579 */
d62caabb 6580 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6581 kvm_x86_ops->hwapic_irr_update(vcpu,
6582 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6583 }
b93463aa 6584
b463a6f7 6585 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6586 kvm_apic_accept_events(vcpu);
6587 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6588 r = 1;
6589 goto out;
6590 }
6591
b6b8a145
JK		 6592 if (inject_pending_event(vcpu, req_int_win) != 0)
6593 req_immediate_exit = true;
321c5658 6594 else {
c43203ca
PB		 6595 /* Enable NMI/IRQ window open exits if needed.
6596 *
6597 * SMIs have two cases: 1) they can be nested, and
6598 * then there is nothing to do here because RSM will
6599 * cause a vmexit anyway; 2) or the SMI can be pending
6600 * because inject_pending_event has completed the
6601 * injection of an IRQ or NMI from the previous vmexit,
6602 * and then we request an immediate exit to inject the SMI.
6603 */
6604 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6605 req_immediate_exit = true;
321c5658
YS		 6606 if (vcpu->arch.nmi_pending)
6607 kvm_x86_ops->enable_nmi_window(vcpu);
6608 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6609 kvm_x86_ops->enable_irq_window(vcpu);
6610 }
b463a6f7
AK		 6611
6612 if (kvm_lapic_enabled(vcpu)) {
6613 update_cr8_intercept(vcpu);
6614 kvm_lapic_sync_to_vapic(vcpu);
6615 }
6616 }
6617
d8368af8
AK		 6618 r = kvm_mmu_reload(vcpu);
6619 if (unlikely(r)) {
d905c069 6620 goto cancel_injection;
d8368af8
AK		 6621 }
6622
b6c7a5dc
HB		 6623 preempt_disable();
6624
6625 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6626 if (vcpu->fpu_active)
6627 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6628 vcpu->mode = IN_GUEST_MODE;
6629
01b71917
MT		 6630 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6631
0f127d12
LT		 6632 /*
6633 * We should set ->mode before check ->requests,
6634 * Please see the comment in kvm_make_all_cpus_request.
6635 * This also orders the write to mode from any reads
6636 * to the page tables done while the VCPU is running.
6637 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6638 */
01b71917 6639 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6640
d94e1dc9 6641 local_irq_disable();
32f88400 6642
6b7e2d09 6643 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6644 || need_resched() || signal_pending(current)) {
6b7e2d09 6645 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6646 smp_wmb();
6c142801
AK		 6647 local_irq_enable();
6648 preempt_enable();
01b71917 6649 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6650 r = 1;
d905c069 6651 goto cancel_injection;
6c142801
AK		 6652 }
6653
fc5b7f3b
DM		 6654 kvm_load_guest_xcr0(vcpu);
6655
c43203ca
PB		 6656 if (req_immediate_exit) {
6657 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6658 smp_send_reschedule(vcpu->cpu);
c43203ca 6659 }
d6185f20 6660
8b89fe1f
PB		 6661 trace_kvm_entry(vcpu->vcpu_id);
6662 wait_lapic_expire(vcpu);
6edaa530 6663 guest_enter_irqoff();
b6c7a5dc 6664
42dbaa5a 6665 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6666 set_debugreg(0, 7);
6667 set_debugreg(vcpu->arch.eff_db[0], 0);
6668 set_debugreg(vcpu->arch.eff_db[1], 1);
6669 set_debugreg(vcpu->arch.eff_db[2], 2);
6670 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6671 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6672 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6673 }
b6c7a5dc 6674
851ba692 6675 kvm_x86_ops->run(vcpu);
b6c7a5dc 6676
c77fb5fe
PB		 6677 /*
6678 * Do this here before restoring debug registers on the host. And
6679 * since we do this before handling the vmexit, a DR access vmexit
6680 * can (a) read the correct value of the debug registers, (b) set
6681 * KVM_DEBUGREG_WONT_EXIT again.
6682 */
6683 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6684 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6685 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6686 kvm_update_dr0123(vcpu);
6687 kvm_update_dr6(vcpu);
6688 kvm_update_dr7(vcpu);
6689 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6690 }
6691
24f1e32c
FW		 6692 /*
6693 * If the guest has used debug registers, at least dr7
6694 * will be disabled while returning to the host.
6695 * If we don't have active breakpoints in the host, we don't
6696 * care about the messed up debug address registers. But if
6697 * we have some of them active, restore the old state.
6698 */
59d8eb53 6699 if (hw_breakpoint_active())
24f1e32c 6700 hw_breakpoint_restore();
42dbaa5a 6701
4ba76538 6702 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6703
6b7e2d09 6704 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6705 smp_wmb();
a547c6db 6706
fc5b7f3b
DM		 6707 kvm_put_guest_xcr0(vcpu);
6708
a547c6db 6709 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6710
6711 ++vcpu->stat.exits;
6712
f2485b3e 6713 guest_exit_irqoff();
b6c7a5dc 6714
f2485b3e 6715 local_irq_enable();
b6c7a5dc
HB		 6716 preempt_enable();
6717
f656ce01 6718 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6719
b6c7a5dc
HB		 6720 /*
6721 * Profile KVM exit RIPs:
6722 */
6723 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6724 unsigned long rip = kvm_rip_read(vcpu);
6725 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6726 }
6727
cc578287
ZA		 6728 if (unlikely(vcpu->arch.tsc_always_catchup))
6729 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6730
5cfb1d5a
MT		 6731 if (vcpu->arch.apic_attention)
6732 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6733
851ba692 6734 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6735 return r;
6736
6737cancel_injection:
6738 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6739 if (unlikely(vcpu->arch.apic_attention))
6740 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6741out:
6742 return r;
6743}
b6c7a5dc 6744
362c698f
PB		 6745static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6746{
bf9f6ac8
FW		 6747 if (!kvm_arch_vcpu_runnable(vcpu) &&
6748 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6749 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6750 kvm_vcpu_block(vcpu);
6751 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6752
6753 if (kvm_x86_ops->post_block)
6754 kvm_x86_ops->post_block(vcpu);
6755
9c8fd1ba
PB		 6756 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6757 return 1;
6758 }
362c698f
PB		 6759
6760 kvm_apic_accept_events(vcpu);
6761 switch(vcpu->arch.mp_state) {
6762 case KVM_MP_STATE_HALTED:
6763 vcpu->arch.pv.pv_unhalted = false;
6764 vcpu->arch.mp_state =
6765 KVM_MP_STATE_RUNNABLE;
6766 case KVM_MP_STATE_RUNNABLE:
6767 vcpu->arch.apf.halted = false;
6768 break;
6769 case KVM_MP_STATE_INIT_RECEIVED:
6770 break;
6771 default:
6772 return -EINTR;
6773 break;
6774 }
6775 return 1;
6776}
09cec754 6777
5d9bc648
PB		 6778static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6779{
6780 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6781 !vcpu->arch.apf.halted);
6782}
6783
362c698f 6784static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6785{
6786 int r;
f656ce01 6787 struct kvm *kvm = vcpu->kvm;
d7690175 6788
f656ce01 6789 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6790
362c698f 6791 for (;;) {
58f800d5 6792 if (kvm_vcpu_running(vcpu)) {
851ba692 6793 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6794 } else {
362c698f 6795 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6796 }
6797
09cec754
GN		 6798 if (r <= 0)
6799 break;
6800
6801 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6802 if (kvm_cpu_has_pending_timer(vcpu))
6803 kvm_inject_pending_timer_irqs(vcpu);
6804
782d422b
MG		 6805 if (dm_request_for_irq_injection(vcpu) &&
6806 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6807 r = 0;
6808 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6809 ++vcpu->stat.request_irq_exits;
362c698f 6810 break;
09cec754 6811 }
af585b92
GN		 6812
6813 kvm_check_async_pf_completion(vcpu);
6814
09cec754
GN		 6815 if (signal_pending(current)) {
6816 r = -EINTR;
851ba692 6817 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6818 ++vcpu->stat.signal_exits;
362c698f 6819 break;
09cec754
GN		 6820 }
6821 if (need_resched()) {
f656ce01 6822 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6823 cond_resched();
f656ce01 6824 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6825 }
b6c7a5dc
HB		 6826 }
6827
f656ce01 6828 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6829
6830 return r;
6831}
6832
716d51ab
GN		 6833static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6834{
6835 int r;
6836 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6837 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6838 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6839 if (r != EMULATE_DONE)
6840 return 0;
6841 return 1;
6842}
6843
6844static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6845{
6846 BUG_ON(!vcpu->arch.pio.count);
6847
6848 return complete_emulated_io(vcpu);
6849}
6850
f78146b0
AK		 6851/*
6852 * Implements the following, as a state machine:
6853 *
6854 * read:
6855 * for each fragment
87da7e66
XG		 6856 * for each mmio piece in the fragment
6857 * write gpa, len
6858 * exit
6859 * copy data
f78146b0
AK		 6860 * execute insn
6861 *
6862 * write:
6863 * for each fragment
87da7e66
XG		 6864 * for each mmio piece in the fragment
6865 * write gpa, len
6866 * copy data
6867 * exit
f78146b0 6868 */
716d51ab 6869static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6870{
6871 struct kvm_run *run = vcpu->run;
f78146b0 6872 struct kvm_mmio_fragment *frag;
87da7e66 6873 unsigned len;
5287f194 6874
716d51ab 6875 BUG_ON(!vcpu->mmio_needed);
5287f194 6876
716d51ab 6877 /* Complete previous fragment */
87da7e66
XG		 6878 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6879 len = min(8u, frag->len);
716d51ab 6880 if (!vcpu->mmio_is_write)
87da7e66
XG		 6881 memcpy(frag->data, run->mmio.data, len);
6882
6883 if (frag->len <= 8) {
6884 /* Switch to the next fragment. */
6885 frag++;
6886 vcpu->mmio_cur_fragment++;
6887 } else {
6888 /* Go forward to the next mmio piece. */
6889 frag->data += len;
6890 frag->gpa += len;
6891 frag->len -= len;
6892 }
6893
a08d3b3b 6894 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6895 vcpu->mmio_needed = 0;
0912c977
PB		 6896
6897 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6898 if (vcpu->mmio_is_write)
716d51ab
GN		 6899 return 1;
6900 vcpu->mmio_read_completed = 1;
6901 return complete_emulated_io(vcpu);
6902 }
87da7e66 6903
716d51ab
GN		 6904 run->exit_reason = KVM_EXIT_MMIO;
6905 run->mmio.phys_addr = frag->gpa;
6906 if (vcpu->mmio_is_write)
87da7e66
XG		 6907 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6908 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6909 run->mmio.is_write = vcpu->mmio_is_write;
6910 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6911 return 0;
5287f194
AK		 6912}
6913
716d51ab 6914
b6c7a5dc
HB		 6915int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6916{
c5bedc68 6917 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6918 int r;
6919 sigset_t sigsaved;
6920
c4d72e2d 6921 fpu__activate_curr(fpu);
e5c30142 6922
ac9f6dc0
AK		 6923 if (vcpu->sigset_active)
6924 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6925
a4535290 6926 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6927 kvm_vcpu_block(vcpu);
66450a21 6928 kvm_apic_accept_events(vcpu);
d7690175 6929 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6930 r = -EAGAIN;
6931 goto out;
b6c7a5dc
HB		 6932 }
6933
b6c7a5dc 6934 /* re-sync apic's tpr */
35754c98 6935 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6936 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6937 r = -EINVAL;
6938 goto out;
6939 }
6940 }
b6c7a5dc 6941
716d51ab
GN		 6942 if (unlikely(vcpu->arch.complete_userspace_io)) {
6943 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6944 vcpu->arch.complete_userspace_io = NULL;
6945 r = cui(vcpu);
6946 if (r <= 0)
6947 goto out;
6948 } else
6949 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6950
362c698f 6951 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6952
6953out:
f1d86e46 6954 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6955 if (vcpu->sigset_active)
6956 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6957
b6c7a5dc
HB		 6958 return r;
6959}
6960
6961int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6962{
7ae441ea
GN		 6963 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6964 /*
6965 * We are here if userspace calls get_regs() in the middle of
6966 * instruction emulation. Registers state needs to be copied
4a969980 6967 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6968 * that usually, but some bad designed PV devices (vmware
6969 * backdoor interface) need this to work
6970 */
dd856efa 6971 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6972 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6973 }
5fdbf976
MT		 6974 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6975 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6976 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6977 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6978 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6979 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6980 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6981 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6982#ifdef CONFIG_X86_64
5fdbf976
MT		 6983 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6984 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6985 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6986 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6987 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6988 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6989 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6990 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6991#endif
6992
5fdbf976 6993 regs->rip = kvm_rip_read(vcpu);
91586a3b 6994 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6995
b6c7a5dc
HB		 6996 return 0;
6997}
6998
6999int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7000{
7ae441ea
GN		 7001 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7002 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7003
5fdbf976
MT		 7004 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7005 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7006 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7007 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7008 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7009 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7010 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7011 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7012#ifdef CONFIG_X86_64
5fdbf976
MT		 7013 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7014 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7015 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7016 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7017 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7018 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7019 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7020 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7021#endif
7022
5fdbf976 7023 kvm_rip_write(vcpu, regs->rip);
91586a3b 7024 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7025
b4f14abd
JK		 7026 vcpu->arch.exception.pending = false;
7027
3842d135
AK		 7028 kvm_make_request(KVM_REQ_EVENT, vcpu);
7029
b6c7a5dc
HB		 7030 return 0;
7031}
7032
b6c7a5dc
HB		 7033void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7034{
7035 struct kvm_segment cs;
7036
3e6e0aab 7037 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7038 *db = cs.db;
7039 *l = cs.l;
7040}
7041EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7042
7043int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7044 struct kvm_sregs *sregs)
7045{
89a27f4d 7046 struct desc_ptr dt;
b6c7a5dc 7047
3e6e0aab
GT		 7048 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7049 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7050 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7051 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7052 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7053 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7054
3e6e0aab
GT		 7055 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7056 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7057
7058 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7059 sregs->idt.limit = dt.size;
7060 sregs->idt.base = dt.address;
b6c7a5dc 7061 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7062 sregs->gdt.limit = dt.size;
7063 sregs->gdt.base = dt.address;
b6c7a5dc 7064
4d4ec087 7065 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7066 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7067 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7068 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7069 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7070 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7071 sregs->apic_base = kvm_get_apic_base(vcpu);
7072
923c61bb 7073 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7074
36752c9b 7075 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7076 set_bit(vcpu->arch.interrupt.nr,
7077 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7078
b6c7a5dc
HB		 7079 return 0;
7080}
7081
62d9f0db
MT		 7082int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7083 struct kvm_mp_state *mp_state)
7084{
66450a21 7085 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7086 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7087 vcpu->arch.pv.pv_unhalted)
7088 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7089 else
7090 mp_state->mp_state = vcpu->arch.mp_state;
7091
62d9f0db
MT		 7092 return 0;
7093}
7094
7095int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7096 struct kvm_mp_state *mp_state)
7097{
bce87cce 7098 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7099 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7100 return -EINVAL;
7101
7102 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7103 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7104 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7105 } else
7106 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7107 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7108 return 0;
7109}
7110
7f3d35fd
KW		 7111int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7112 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7113{
9d74191a 7114 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7115 int ret;
e01c2426 7116
8ec4722d 7117 init_emulate_ctxt(vcpu);
c697518a 7118
7f3d35fd 7119 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7120 has_error_code, error_code);
c697518a 7121
c697518a 7122 if (ret)
19d04437 7123 return EMULATE_FAIL;
37817f29 7124
9d74191a
TY		 7125 kvm_rip_write(vcpu, ctxt->eip);
7126 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7127 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7128 return EMULATE_DONE;
37817f29
IE		 7129}
7130EXPORT_SYMBOL_GPL(kvm_task_switch);
7131
b6c7a5dc
HB		 7132int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7133 struct kvm_sregs *sregs)
7134{
58cb628d 7135 struct msr_data apic_base_msr;
b6c7a5dc 7136 int mmu_reset_needed = 0;
63f42e02 7137 int pending_vec, max_bits, idx;
89a27f4d 7138 struct desc_ptr dt;
b6c7a5dc 7139
6d1068b3
PM		 7140 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7141 return -EINVAL;
7142
89a27f4d
GN		 7143 dt.size = sregs->idt.limit;
7144 dt.address = sregs->idt.base;
b6c7a5dc 7145 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7146 dt.size = sregs->gdt.limit;
7147 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7148 kvm_x86_ops->set_gdt(vcpu, &dt);
7149
ad312c7c 7150 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7151 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7152 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7153 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7154
2d3ad1f4 7155 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7156
f6801dff 7157 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7158 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7159 apic_base_msr.data = sregs->apic_base;
7160 apic_base_msr.host_initiated = true;
7161 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7162
4d4ec087 7163 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7164 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7165 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7166
fc78f519 7167 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7168 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7169 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7170 kvm_update_cpuid(vcpu);
63f42e02
XG		 7171
7172 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7173 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7174 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7175 mmu_reset_needed = 1;
7176 }
63f42e02 7177 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7178
7179 if (mmu_reset_needed)
7180 kvm_mmu_reset_context(vcpu);
7181
a50abc3b 7182 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7183 pending_vec = find_first_bit(
7184 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7185 if (pending_vec < max_bits) {
66fd3f7f 7186 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7187 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7188 }
7189
3e6e0aab
GT		 7190 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7191 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7192 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7193 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7194 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7195 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7196
3e6e0aab
GT		 7197 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7198 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7199
5f0269f5
ME		 7200 update_cr8_intercept(vcpu);
7201
9c3e4aab 7202 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7203 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7204 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7205 !is_protmode(vcpu))
9c3e4aab
MT		 7206 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7207
3842d135
AK		 7208 kvm_make_request(KVM_REQ_EVENT, vcpu);
7209
b6c7a5dc
HB		 7210 return 0;
7211}
7212
d0bfb940
JK		 7213int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7214 struct kvm_guest_debug *dbg)
b6c7a5dc 7215{
355be0b9 7216 unsigned long rflags;
ae675ef0 7217 int i, r;
b6c7a5dc 7218
4f926bf2
JK		 7219 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7220 r = -EBUSY;
7221 if (vcpu->arch.exception.pending)
2122ff5e 7222 goto out;
4f926bf2
JK		 7223 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7224 kvm_queue_exception(vcpu, DB_VECTOR);
7225 else
7226 kvm_queue_exception(vcpu, BP_VECTOR);
7227 }
7228
91586a3b
JK		 7229 /*
7230 * Read rflags as long as potentially injected trace flags are still
7231 * filtered out.
7232 */
7233 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7234
7235 vcpu->guest_debug = dbg->control;
7236 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7237 vcpu->guest_debug = 0;
7238
7239 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7240 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7241 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7242 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7243 } else {
7244 for (i = 0; i < KVM_NR_DB_REGS; i++)
7245 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7246 }
c8639010 7247 kvm_update_dr7(vcpu);
ae675ef0 7248
f92653ee
JK		 7249 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7250 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7251 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7252
91586a3b
JK		 7253 /*
7254 * Trigger an rflags update that will inject or remove the trace
7255 * flags.
7256 */
7257 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7258
a96036b8 7259 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7260
4f926bf2 7261 r = 0;
d0bfb940 7262
2122ff5e 7263out:
b6c7a5dc
HB		 7264
7265 return r;
7266}
7267
8b006791
ZX		 7268/*
7269 * Translate a guest virtual address to a guest physical address.
7270 */
7271int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7272 struct kvm_translation *tr)
7273{
7274 unsigned long vaddr = tr->linear_address;
7275 gpa_t gpa;
f656ce01 7276 int idx;
8b006791 7277
f656ce01 7278 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7279 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7280 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7281 tr->physical_address = gpa;
7282 tr->valid = gpa != UNMAPPED_GVA;
7283 tr->writeable = 1;
7284 tr->usermode = 0;
8b006791
ZX		 7285
7286 return 0;
7287}
7288
d0752060
HB		 7289int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7290{
c47ada30 7291 struct fxregs_state *fxsave =
7366ed77 7292 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7293
d0752060
HB		 7294 memcpy(fpu->fpr, fxsave->st_space, 128);
7295 fpu->fcw = fxsave->cwd;
7296 fpu->fsw = fxsave->swd;
7297 fpu->ftwx = fxsave->twd;
7298 fpu->last_opcode = fxsave->fop;
7299 fpu->last_ip = fxsave->rip;
7300 fpu->last_dp = fxsave->rdp;
7301 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7302
d0752060
HB		 7303 return 0;
7304}
7305
7306int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7307{
c47ada30 7308 struct fxregs_state *fxsave =
7366ed77 7309 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7310
d0752060
HB		 7311 memcpy(fxsave->st_space, fpu->fpr, 128);
7312 fxsave->cwd = fpu->fcw;
7313 fxsave->swd = fpu->fsw;
7314 fxsave->twd = fpu->ftwx;
7315 fxsave->fop = fpu->last_opcode;
7316 fxsave->rip = fpu->last_ip;
7317 fxsave->rdp = fpu->last_dp;
7318 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7319
d0752060
HB		 7320 return 0;
7321}
7322
0ee6a517 7323static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7324{
bf935b0b 7325 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7326 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7327 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7328 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7329
2acf923e
DC		 7330 /*
7331 * Ensure guest xcr0 is valid for loading
7332 */
d91cab78 7333 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7334
ad312c7c 7335 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7336}
d0752060
HB		 7337
7338void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7339{
2608d7a1 7340 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7341 return;
7342
2acf923e
DC		 7343 /*
7344 * Restore all possible states in the guest,
7345 * and assume host would use all available bits.
7346 * Guest xcr0 would be loaded later.
7347 */
d0752060 7348 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7349 __kernel_fpu_begin();
003e2e8b 7350 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7351 trace_kvm_fpu(1);
d0752060 7352}
d0752060
HB		 7353
7354void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7355{
653f52c3
RR		 7356 if (!vcpu->guest_fpu_loaded) {
7357 vcpu->fpu_counter = 0;
d0752060 7358 return;
653f52c3 7359 }
d0752060
HB		 7360
7361 vcpu->guest_fpu_loaded = 0;
4f836347 7362 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7363 __kernel_fpu_end();
f096ed85 7364 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7365 /*
7366 * If using eager FPU mode, or if the guest is a frequent user
7367 * of the FPU, just leave the FPU active for next time.
7368 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7369 * the FPU in bursts will revert to loading it on demand.
7370 */
5a5fbdc0 7371 if (!use_eager_fpu()) {
653f52c3
RR		 7372 if (++vcpu->fpu_counter < 5)
7373 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7374 }
0c04851c 7375 trace_kvm_fpu(0);
d0752060 7376}
e9b11c17
ZX		 7377
7378void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7379{
12f9a48f 7380 kvmclock_reset(vcpu);
7f1ea208 7381
f5f48ee1 7382 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7383 kvm_x86_ops->vcpu_free(vcpu);
7384}
7385
7386struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7387 unsigned int id)
7388{
c447e76b
LL		 7389 struct kvm_vcpu *vcpu;
7390
6755bae8
ZA		 7391 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7392 printk_once(KERN_WARNING
7393 "kvm: SMP vm created on host with unstable TSC; "
7394 "guest TSC will not be reliable\n");
c447e76b
LL		 7395
7396 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7397
c447e76b 7398 return vcpu;
26e5215f 7399}
e9b11c17 7400
26e5215f
AK		 7401int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7402{
7403 int r;
e9b11c17 7404
19efffa2 7405 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7406 r = vcpu_load(vcpu);
7407 if (r)
7408 return r;
d28bc9dd 7409 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7410 kvm_mmu_setup(vcpu);
e9b11c17 7411 vcpu_put(vcpu);
26e5215f 7412 return r;
e9b11c17
ZX		 7413}
7414
31928aa5 7415void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7416{
8fe8ab46 7417 struct msr_data msr;
332967a3 7418 struct kvm *kvm = vcpu->kvm;
42897d86 7419
31928aa5
DD		 7420 if (vcpu_load(vcpu))
7421 return;
8fe8ab46
WA		 7422 msr.data = 0x0;
7423 msr.index = MSR_IA32_TSC;
7424 msr.host_initiated = true;
7425 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7426 vcpu_put(vcpu);
7427
630994b3
MT		 7428 if (!kvmclock_periodic_sync)
7429 return;
7430
332967a3
AJ		 7431 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7432 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7433}
7434
d40ccc62 7435void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7436{
9fc77441 7437 int r;
344d9588
GN		 7438 vcpu->arch.apf.msr_val = 0;
7439
9fc77441
MT		 7440 r = vcpu_load(vcpu);
7441 BUG_ON(r);
e9b11c17
ZX		 7442 kvm_mmu_unload(vcpu);
7443 vcpu_put(vcpu);
7444
7445 kvm_x86_ops->vcpu_free(vcpu);
7446}
7447
d28bc9dd 7448void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7449{
e69fab5d
PB		 7450 vcpu->arch.hflags = 0;
7451
c43203ca 7452 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7453 atomic_set(&vcpu->arch.nmi_queued, 0);
7454 vcpu->arch.nmi_pending = 0;
448fa4a9 7455 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7456 kvm_clear_interrupt_queue(vcpu);
7457 kvm_clear_exception_queue(vcpu);
448fa4a9 7458
42dbaa5a 7459 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7460 kvm_update_dr0123(vcpu);
6f43ed01 7461 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7462 kvm_update_dr6(vcpu);
42dbaa5a 7463 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7464 kvm_update_dr7(vcpu);
42dbaa5a 7465
1119022c
NA		 7466 vcpu->arch.cr2 = 0;
7467
3842d135 7468 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7469 vcpu->arch.apf.msr_val = 0;
c9aaa895 7470 vcpu->arch.st.msr_val = 0;
3842d135 7471
12f9a48f
GC		 7472 kvmclock_reset(vcpu);
7473
af585b92
GN		 7474 kvm_clear_async_pf_completion_queue(vcpu);
7475 kvm_async_pf_hash_reset(vcpu);
7476 vcpu->arch.apf.halted = false;
3842d135 7477
64d60670 7478 if (!init_event) {
d28bc9dd 7479 kvm_pmu_reset(vcpu);
64d60670
PB		 7480 vcpu->arch.smbase = 0x30000;
7481 }
f5132b01 7482
66f7b72e
JS		 7483 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7484 vcpu->arch.regs_avail = ~0;
7485 vcpu->arch.regs_dirty = ~0;
7486
d28bc9dd 7487 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7488}
7489
2b4a273b 7490void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7491{
7492 struct kvm_segment cs;
7493
7494 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7495 cs.selector = vector << 8;
7496 cs.base = vector << 12;
7497 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7498 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7499}
7500
13a34e06 7501int kvm_arch_hardware_enable(void)
e9b11c17 7502{
ca84d1a2
ZA		 7503 struct kvm *kvm;
7504 struct kvm_vcpu *vcpu;
7505 int i;
0dd6a6ed
ZA		 7506 int ret;
7507 u64 local_tsc;
7508 u64 max_tsc = 0;
7509 bool stable, backwards_tsc = false;
18863bdd
AK		 7510
7511 kvm_shared_msr_cpu_online();
13a34e06 7512 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7513 if (ret != 0)
7514 return ret;
7515
4ea1636b 7516 local_tsc = rdtsc();
0dd6a6ed
ZA		 7517 stable = !check_tsc_unstable();
7518 list_for_each_entry(kvm, &vm_list, vm_list) {
7519 kvm_for_each_vcpu(i, vcpu, kvm) {
7520 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7521 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7522 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7523 backwards_tsc = true;
7524 if (vcpu->arch.last_host_tsc > max_tsc)
7525 max_tsc = vcpu->arch.last_host_tsc;
7526 }
7527 }
7528 }
7529
7530 /*
7531 * Sometimes, even reliable TSCs go backwards. This happens on
7532 * platforms that reset TSC during suspend or hibernate actions, but
7533 * maintain synchronization. We must compensate. Fortunately, we can
7534 * detect that condition here, which happens early in CPU bringup,
7535 * before any KVM threads can be running. Unfortunately, we can't
7536 * bring the TSCs fully up to date with real time, as we aren't yet far
7537 * enough into CPU bringup that we know how much real time has actually
7538 * elapsed; our helper function, get_kernel_ns() will be using boot
7539 * variables that haven't been updated yet.
7540 *
7541 * So we simply find the maximum observed TSC above, then record the
7542 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7543 * the adjustment will be applied. Note that we accumulate
7544 * adjustments, in case multiple suspend cycles happen before some VCPU
7545 * gets a chance to run again. In the event that no KVM threads get a
7546 * chance to run, we will miss the entire elapsed period, as we'll have
7547 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7548 * loose cycle time. This isn't too big a deal, since the loss will be
7549 * uniform across all VCPUs (not to mention the scenario is extremely
7550 * unlikely). It is possible that a second hibernate recovery happens
7551 * much faster than a first, causing the observed TSC here to be
7552 * smaller; this would require additional padding adjustment, which is
7553 * why we set last_host_tsc to the local tsc observed here.
7554 *
7555 * N.B. - this code below runs only on platforms with reliable TSC,
7556 * as that is the only way backwards_tsc is set above. Also note
7557 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7558 * have the same delta_cyc adjustment applied if backwards_tsc
7559 * is detected. Note further, this adjustment is only done once,
7560 * as we reset last_host_tsc on all VCPUs to stop this from being
7561 * called multiple times (one for each physical CPU bringup).
7562 *
4a969980 7563 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7564 * will be compensated by the logic in vcpu_load, which sets the TSC to
7565 * catchup mode. This will catchup all VCPUs to real time, but cannot
7566 * guarantee that they stay in perfect synchronization.
7567 */
7568 if (backwards_tsc) {
7569 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7570 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7571 list_for_each_entry(kvm, &vm_list, vm_list) {
7572 kvm_for_each_vcpu(i, vcpu, kvm) {
7573 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7574 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7575 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7576 }
7577
7578 /*
7579 * We have to disable TSC offset matching.. if you were
7580 * booting a VM while issuing an S4 host suspend....
7581 * you may have some problem. Solving this issue is
7582 * left as an exercise to the reader.
7583 */
7584 kvm->arch.last_tsc_nsec = 0;
7585 kvm->arch.last_tsc_write = 0;
7586 }
7587
7588 }
7589 return 0;
e9b11c17
ZX		 7590}
7591
13a34e06 7592void kvm_arch_hardware_disable(void)
e9b11c17 7593{
13a34e06
RK		 7594 kvm_x86_ops->hardware_disable();
7595 drop_user_return_notifiers();
e9b11c17
ZX		 7596}
7597
7598int kvm_arch_hardware_setup(void)
7599{
9e9c3fe4
NA		 7600 int r;
7601
7602 r = kvm_x86_ops->hardware_setup();
7603 if (r != 0)
7604 return r;
7605
35181e86
HZ		 7606 if (kvm_has_tsc_control) {
7607 /*
7608 * Make sure the user can only configure tsc_khz values that
7609 * fit into a signed integer.
7610 * A min value is not calculated needed because it will always
7611 * be 1 on all machines.
7612 */
7613 u64 max = min(0x7fffffffULL,
7614 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7615 kvm_max_guest_tsc_khz = max;
7616
ad721883 7617 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7618 }
ad721883 7619
9e9c3fe4
NA		 7620 kvm_init_msr_list();
7621 return 0;
e9b11c17
ZX		 7622}
7623
7624void kvm_arch_hardware_unsetup(void)
7625{
7626 kvm_x86_ops->hardware_unsetup();
7627}
7628
7629void kvm_arch_check_processor_compat(void *rtn)
7630{
7631 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7632}
7633
7634bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7635{
7636 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7637}
7638EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7639
7640bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7641{
7642 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7643}
7644
54e9818f 7645struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7646EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7647
e9b11c17
ZX		 7648int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7649{
7650 struct page *page;
7651 struct kvm *kvm;
7652 int r;
7653
7654 BUG_ON(vcpu->kvm == NULL);
7655 kvm = vcpu->kvm;
7656
d62caabb 7657 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7658 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7659 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7660 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7661 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7662 else
a4535290 7663 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7664
7665 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7666 if (!page) {
7667 r = -ENOMEM;
7668 goto fail;
7669 }
ad312c7c 7670 vcpu->arch.pio_data = page_address(page);
e9b11c17 7671
cc578287 7672 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7673
e9b11c17
ZX		 7674 r = kvm_mmu_create(vcpu);
7675 if (r < 0)
7676 goto fail_free_pio_data;
7677
7678 if (irqchip_in_kernel(kvm)) {
7679 r = kvm_create_lapic(vcpu);
7680 if (r < 0)
7681 goto fail_mmu_destroy;
54e9818f
GN		 7682 } else
7683 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7684
890ca9ae
HY		 7685 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7686 GFP_KERNEL);
7687 if (!vcpu->arch.mce_banks) {
7688 r = -ENOMEM;
443c39bc 7689 goto fail_free_lapic;
890ca9ae
HY		 7690 }
7691 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7692
f1797359
WY		 7693 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7694 r = -ENOMEM;
f5f48ee1 7695 goto fail_free_mce_banks;
f1797359 7696 }
f5f48ee1 7697
0ee6a517 7698 fx_init(vcpu);
66f7b72e 7699
ba904635 7700 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7701 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7702
7703 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7704 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7705
5a4f55cd
EK		 7706 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7707
74545705
RK		 7708 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7709
af585b92 7710 kvm_async_pf_hash_reset(vcpu);
f5132b01 7711 kvm_pmu_init(vcpu);
af585b92 7712
1c1a9ce9
SR		 7713 vcpu->arch.pending_external_vector = -1;
7714
5c919412
AS		 7715 kvm_hv_vcpu_init(vcpu);
7716
e9b11c17 7717 return 0;
0ee6a517 7718
f5f48ee1
SY		 7719fail_free_mce_banks:
7720 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7721fail_free_lapic:
7722 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7723fail_mmu_destroy:
7724 kvm_mmu_destroy(vcpu);
7725fail_free_pio_data:
ad312c7c 7726 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7727fail:
7728 return r;
7729}
7730
7731void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7732{
f656ce01
MT		 7733 int idx;
7734
1f4b34f8 7735 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7736 kvm_pmu_destroy(vcpu);
36cb93fd 7737 kfree(vcpu->arch.mce_banks);
e9b11c17 7738 kvm_free_lapic(vcpu);
f656ce01 7739 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7740 kvm_mmu_destroy(vcpu);
f656ce01 7741 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7742 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7743 if (!lapic_in_kernel(vcpu))
54e9818f 7744 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7745}
d19a9cd2 7746
e790d9ef
RK		 7747void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7748{
ae97a3b8 7749 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7750}
7751
e08b9637 7752int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7753{
e08b9637
CO		 7754 if (type)
7755 return -EINVAL;
7756
6ef768fa 7757 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7758 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7759 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7760 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7761 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7762
5550af4d
SY		 7763 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7764 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7765 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7766 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7767 &kvm->arch.irq_sources_bitmap);
5550af4d 7768
038f8c11 7769 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7770 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7771 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7772
7773 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7774
7e44e449 7775 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7776 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7777
0eb05bf2 7778 kvm_page_track_init(kvm);
13d268ca 7779 kvm_mmu_init_vm(kvm);
0eb05bf2 7780
03543133
SS		 7781 if (kvm_x86_ops->vm_init)
7782 return kvm_x86_ops->vm_init(kvm);
7783
d89f5eff 7784 return 0;
d19a9cd2
ZX		 7785}
7786
7787static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7788{
9fc77441
MT		 7789 int r;
7790 r = vcpu_load(vcpu);
7791 BUG_ON(r);
d19a9cd2
ZX		 7792 kvm_mmu_unload(vcpu);
7793 vcpu_put(vcpu);
7794}
7795
7796static void kvm_free_vcpus(struct kvm *kvm)
7797{
7798 unsigned int i;
988a2cae 7799 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7800
7801 /*
7802 * Unpin any mmu pages first.
7803 */
af585b92
GN		 7804 kvm_for_each_vcpu(i, vcpu, kvm) {
7805 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7806 kvm_unload_vcpu_mmu(vcpu);
af585b92 7807 }
988a2cae
GN		 7808 kvm_for_each_vcpu(i, vcpu, kvm)
7809 kvm_arch_vcpu_free(vcpu);
7810
7811 mutex_lock(&kvm->lock);
7812 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7813 kvm->vcpus[i] = NULL;
d19a9cd2 7814
988a2cae
GN		 7815 atomic_set(&kvm->online_vcpus, 0);
7816 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7817}
7818
ad8ba2cd
SY		 7819void kvm_arch_sync_events(struct kvm *kvm)
7820{
332967a3 7821 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7822 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7823 kvm_free_all_assigned_devices(kvm);
aea924f6 7824 kvm_free_pit(kvm);
ad8ba2cd
SY		 7825}
7826
1d8007bd 7827int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7828{
7829 int i, r;
25188b99 7830 unsigned long hva;
f0d648bd
PB		 7831 struct kvm_memslots *slots = kvm_memslots(kvm);
7832 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7833
7834 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7835 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7836 return -EINVAL;
9da0e4d5 7837
f0d648bd
PB		 7838 slot = id_to_memslot(slots, id);
7839 if (size) {
b21629da 7840 if (slot->npages)
f0d648bd
PB		 7841 return -EEXIST;
7842
7843 /*
7844 * MAP_SHARED to prevent internal slot pages from being moved
7845 * by fork()/COW.
7846 */
7847 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7848 MAP_SHARED | MAP_ANONYMOUS, 0);
7849 if (IS_ERR((void *)hva))
7850 return PTR_ERR((void *)hva);
7851 } else {
7852 if (!slot->npages)
7853 return 0;
7854
7855 hva = 0;
7856 }
7857
7858 old = *slot;
9da0e4d5 7859 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7860 struct kvm_userspace_memory_region m;
9da0e4d5 7861
1d8007bd
PB		 7862 m.slot = id | (i << 16);
7863 m.flags = 0;
7864 m.guest_phys_addr = gpa;
f0d648bd 7865 m.userspace_addr = hva;
1d8007bd 7866 m.memory_size = size;
9da0e4d5
PB		 7867 r = __kvm_set_memory_region(kvm, &m);
7868 if (r < 0)
7869 return r;
7870 }
7871
f0d648bd
PB		 7872 if (!size) {
7873 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7874 WARN_ON(r < 0);
7875 }
7876
9da0e4d5
PB		 7877 return 0;
7878}
7879EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7880
1d8007bd 7881int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7882{
7883 int r;
7884
7885 mutex_lock(&kvm->slots_lock);
1d8007bd 7886 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7887 mutex_unlock(&kvm->slots_lock);
7888
7889 return r;
7890}
7891EXPORT_SYMBOL_GPL(x86_set_memory_region);
7892
d19a9cd2
ZX		 7893void kvm_arch_destroy_vm(struct kvm *kvm)
7894{
27469d29
AH		 7895 if (current->mm == kvm->mm) {
7896 /*
7897 * Free memory regions allocated on behalf of userspace,
7898 * unless the the memory map has changed due to process exit
7899 * or fd copying.
7900 */
1d8007bd
PB		 7901 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7902 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7903 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7904 }
03543133
SS		 7905 if (kvm_x86_ops->vm_destroy)
7906 kvm_x86_ops->vm_destroy(kvm);
6eb55818 7907 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7908 kfree(kvm->arch.vpic);
7909 kfree(kvm->arch.vioapic);
d19a9cd2 7910 kvm_free_vcpus(kvm);
af1bae54 7911 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7912 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7913}
0de10343 7914
5587027c 7915void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7916 struct kvm_memory_slot *dont)
7917{
7918 int i;
7919
d89cc617
TY		 7920 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7921 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7922 kvfree(free->arch.rmap[i]);
d89cc617 7923 free->arch.rmap[i] = NULL;
77d11309 7924 }
d89cc617
TY		 7925 if (i == 0)
7926 continue;
7927
7928 if (!dont || free->arch.lpage_info[i - 1] !=
7929 dont->arch.lpage_info[i - 1]) {
548ef284 7930 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7931 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7932 }
7933 }
21ebbeda
XG		 7934
7935 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7936}
7937
5587027c
AK		 7938int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7939 unsigned long npages)
db3fe4eb
TY		 7940{
7941 int i;
7942
d89cc617 7943 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7944 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7945 unsigned long ugfn;
7946 int lpages;
d89cc617 7947 int level = i + 1;
db3fe4eb
TY		 7948
7949 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7950 slot->base_gfn, level) + 1;
7951
d89cc617
TY		 7952 slot->arch.rmap[i] =
7953 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7954 if (!slot->arch.rmap[i])
77d11309 7955 goto out_free;
d89cc617
TY		 7956 if (i == 0)
7957 continue;
77d11309 7958
92f94f1e
XG		 7959 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7960 if (!linfo)
db3fe4eb
TY		 7961 goto out_free;
7962
92f94f1e
XG		 7963 slot->arch.lpage_info[i - 1] = linfo;
7964
db3fe4eb 7965 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7966 linfo[0].disallow_lpage = 1;
db3fe4eb 7967 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7968 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 7969 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7970 /*
7971 * If the gfn and userspace address are not aligned wrt each
7972 * other, or if explicitly asked to, disable large page
7973 * support for this slot
7974 */
7975 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7976 !kvm_largepages_enabled()) {
7977 unsigned long j;
7978
7979 for (j = 0; j < lpages; ++j)
92f94f1e 7980 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 7981 }
7982 }
7983
21ebbeda
XG		 7984 if (kvm_page_track_create_memslot(slot, npages))
7985 goto out_free;
7986
db3fe4eb
TY		 7987 return 0;
7988
7989out_free:
d89cc617 7990 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7991 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7992 slot->arch.rmap[i] = NULL;
7993 if (i == 0)
7994 continue;
7995
548ef284 7996 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7997 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7998 }
7999 return -ENOMEM;
8000}
8001
15f46015 8002void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8003{
e6dff7d1
TY		 8004 /*
8005 * memslots->generation has been incremented.
8006 * mmio generation may have reached its maximum value.
8007 */
54bf36aa 8008 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8009}
8010
f7784b8e
MT		 8011int kvm_arch_prepare_memory_region(struct kvm *kvm,
8012 struct kvm_memory_slot *memslot,
09170a49 8013 const struct kvm_userspace_memory_region *mem,
7b6195a9 8014 enum kvm_mr_change change)
0de10343 8015{
f7784b8e
MT		 8016 return 0;
8017}
8018
88178fd4
KH		 8019static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8020 struct kvm_memory_slot *new)
8021{
8022 /* Still write protect RO slot */
8023 if (new->flags & KVM_MEM_READONLY) {
8024 kvm_mmu_slot_remove_write_access(kvm, new);
8025 return;
8026 }
8027
8028 /*
8029 * Call kvm_x86_ops dirty logging hooks when they are valid.
8030 *
8031 * kvm_x86_ops->slot_disable_log_dirty is called when:
8032 *
8033 * - KVM_MR_CREATE with dirty logging is disabled
8034 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8035 *
8036 * The reason is, in case of PML, we need to set D-bit for any slots
8037 * with dirty logging disabled in order to eliminate unnecessary GPA
8038 * logging in PML buffer (and potential PML buffer full VMEXT). This
8039 * guarantees leaving PML enabled during guest's lifetime won't have
8040 * any additonal overhead from PML when guest is running with dirty
8041 * logging disabled for memory slots.
8042 *
8043 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8044 * to dirty logging mode.
8045 *
8046 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8047 *
8048 * In case of write protect:
8049 *
8050 * Write protect all pages for dirty logging.
8051 *
8052 * All the sptes including the large sptes which point to this
8053 * slot are set to readonly. We can not create any new large
8054 * spte on this slot until the end of the logging.
8055 *
8056 * See the comments in fast_page_fault().
8057 */
8058 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8059 if (kvm_x86_ops->slot_enable_log_dirty)
8060 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8061 else
8062 kvm_mmu_slot_remove_write_access(kvm, new);
8063 } else {
8064 if (kvm_x86_ops->slot_disable_log_dirty)
8065 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8066 }
8067}
8068
f7784b8e 8069void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8070 const struct kvm_userspace_memory_region *mem,
8482644a 8071 const struct kvm_memory_slot *old,
f36f3f28 8072 const struct kvm_memory_slot *new,
8482644a 8073 enum kvm_mr_change change)
f7784b8e 8074{
8482644a 8075 int nr_mmu_pages = 0;
f7784b8e 8076
48c0e4e9
XG		 8077 if (!kvm->arch.n_requested_mmu_pages)
8078 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8079
48c0e4e9 8080 if (nr_mmu_pages)
0de10343 8081 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8082
3ea3b7fa
WL		 8083 /*
8084 * Dirty logging tracks sptes in 4k granularity, meaning that large
8085 * sptes have to be split. If live migration is successful, the guest
8086 * in the source machine will be destroyed and large sptes will be
8087 * created in the destination. However, if the guest continues to run
8088 * in the source machine (for example if live migration fails), small
8089 * sptes will remain around and cause bad performance.
8090 *
8091 * Scan sptes if dirty logging has been stopped, dropping those
8092 * which can be collapsed into a single large-page spte. Later
8093 * page faults will create the large-page sptes.
8094 */
8095 if ((change != KVM_MR_DELETE) &&
8096 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8097 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8098 kvm_mmu_zap_collapsible_sptes(kvm, new);
8099
c972f3b1 8100 /*
88178fd4 8101 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8102 *
88178fd4
KH		 8103 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8104 * been zapped so no dirty logging staff is needed for old slot. For
8105 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8106 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8107 *
8108 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8109 */
88178fd4 8110 if (change != KVM_MR_DELETE)
f36f3f28 8111 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8112}
1d737c8a 8113
2df72e9b 8114void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8115{
6ca18b69 8116 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8117}
8118
2df72e9b
MT		 8119void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8120 struct kvm_memory_slot *slot)
8121{
6ca18b69 8122 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8123}
8124
5d9bc648
PB		 8125static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8126{
8127 if (!list_empty_careful(&vcpu->async_pf.done))
8128 return true;
8129
8130 if (kvm_apic_has_events(vcpu))
8131 return true;
8132
8133 if (vcpu->arch.pv.pv_unhalted)
8134 return true;
8135
8136 if (atomic_read(&vcpu->arch.nmi_queued))
8137 return true;
8138
73917739
PB		 8139 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8140 return true;
8141
5d9bc648
PB		 8142 if (kvm_arch_interrupt_allowed(vcpu) &&
8143 kvm_cpu_has_interrupt(vcpu))
8144 return true;
8145
1f4b34f8
AS		 8146 if (kvm_hv_has_stimer_pending(vcpu))
8147 return true;
8148
5d9bc648
PB		 8149 return false;
8150}
8151
1d737c8a
ZX		 8152int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8153{
b6b8a145
JK		 8154 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8155 kvm_x86_ops->check_nested_events(vcpu, false);
8156
5d9bc648 8157 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8158}
5736199a 8159
b6d33834 8160int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8161{
b6d33834 8162 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8163}
78646121
GN		 8164
8165int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8166{
8167 return kvm_x86_ops->interrupt_allowed(vcpu);
8168}
229456fc 8169
82b32774 8170unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8171{
82b32774
NA		 8172 if (is_64_bit_mode(vcpu))
8173 return kvm_rip_read(vcpu);
8174 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8175 kvm_rip_read(vcpu));
8176}
8177EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8178
82b32774
NA		 8179bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8180{
8181 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8182}
8183EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8184
94fe45da
JK		 8185unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8186{
8187 unsigned long rflags;
8188
8189 rflags = kvm_x86_ops->get_rflags(vcpu);
8190 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8191 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8192 return rflags;
8193}
8194EXPORT_SYMBOL_GPL(kvm_get_rflags);
8195
6addfc42 8196static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8197{
8198 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8199 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8200 rflags |= X86_EFLAGS_TF;
94fe45da 8201 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8202}
8203
8204void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8205{
8206 __kvm_set_rflags(vcpu, rflags);
3842d135 8207 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8208}
8209EXPORT_SYMBOL_GPL(kvm_set_rflags);
8210
56028d08
GN		 8211void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8212{
8213 int r;
8214
fb67e14f 8215 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8216 work->wakeup_all)
56028d08
GN		 8217 return;
8218
8219 r = kvm_mmu_reload(vcpu);
8220 if (unlikely(r))
8221 return;
8222
fb67e14f
XG		 8223 if (!vcpu->arch.mmu.direct_map &&
8224 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8225 return;
8226
56028d08
GN		 8227 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8228}
8229
af585b92
GN		 8230static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8231{
8232 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8233}
8234
8235static inline u32 kvm_async_pf_next_probe(u32 key)
8236{
8237 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8238}
8239
8240static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8241{
8242 u32 key = kvm_async_pf_hash_fn(gfn);
8243
8244 while (vcpu->arch.apf.gfns[key] != ~0)
8245 key = kvm_async_pf_next_probe(key);
8246
8247 vcpu->arch.apf.gfns[key] = gfn;
8248}
8249
8250static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8251{
8252 int i;
8253 u32 key = kvm_async_pf_hash_fn(gfn);
8254
8255 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8256 (vcpu->arch.apf.gfns[key] != gfn &&
8257 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8258 key = kvm_async_pf_next_probe(key);
8259
8260 return key;
8261}
8262
8263bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8264{
8265 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8266}
8267
8268static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8269{
8270 u32 i, j, k;
8271
8272 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8273 while (true) {
8274 vcpu->arch.apf.gfns[i] = ~0;
8275 do {
8276 j = kvm_async_pf_next_probe(j);
8277 if (vcpu->arch.apf.gfns[j] == ~0)
8278 return;
8279 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8280 /*
8281 * k lies cyclically in ]i,j]
8282 * | i.k.j |
8283 * |....j i.k.| or |.k..j i...|
8284 */
8285 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8286 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8287 i = j;
8288 }
8289}
8290
7c90705b
GN		 8291static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8292{
8293
8294 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8295 sizeof(val));
8296}
8297
af585b92
GN		 8298void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8299 struct kvm_async_pf *work)
8300{
6389ee94
AK		 8301 struct x86_exception fault;
8302
7c90705b 8303 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8304 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8305
8306 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8307 (vcpu->arch.apf.send_user_only &&
8308 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8309 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8310 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8311 fault.vector = PF_VECTOR;
8312 fault.error_code_valid = true;
8313 fault.error_code = 0;
8314 fault.nested_page_fault = false;
8315 fault.address = work->arch.token;
8316 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8317 }
af585b92
GN		 8318}
8319
8320void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8321 struct kvm_async_pf *work)
8322{
6389ee94
AK		 8323 struct x86_exception fault;
8324
7c90705b 8325 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8326 if (work->wakeup_all)
7c90705b
GN		 8327 work->arch.token = ~0; /* broadcast wakeup */
8328 else
8329 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8330
8331 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8332 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8333 fault.vector = PF_VECTOR;
8334 fault.error_code_valid = true;
8335 fault.error_code = 0;
8336 fault.nested_page_fault = false;
8337 fault.address = work->arch.token;
8338 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8339 }
e6d53e3b 8340 vcpu->arch.apf.halted = false;
a4fa1635 8341 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8342}
8343
8344bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8345{
8346 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8347 return true;
8348 else
8349 return !kvm_event_needs_reinjection(vcpu) &&
8350 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8351}
8352
5544eb9b
PB		 8353void kvm_arch_start_assignment(struct kvm *kvm)
8354{
8355 atomic_inc(&kvm->arch.assigned_device_count);
8356}
8357EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8358
8359void kvm_arch_end_assignment(struct kvm *kvm)
8360{
8361 atomic_dec(&kvm->arch.assigned_device_count);
8362}
8363EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8364
8365bool kvm_arch_has_assigned_device(struct kvm *kvm)
8366{
8367 return atomic_read(&kvm->arch.assigned_device_count);
8368}
8369EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8370
e0f0bbc5
AW		 8371void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8372{
8373 atomic_inc(&kvm->arch.noncoherent_dma_count);
8374}
8375EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8376
8377void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8378{
8379 atomic_dec(&kvm->arch.noncoherent_dma_count);
8380}
8381EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8382
8383bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8384{
8385 return atomic_read(&kvm->arch.noncoherent_dma_count);
8386}
8387EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8388
14717e20
AW		 8389bool kvm_arch_has_irq_bypass(void)
8390{
8391 return kvm_x86_ops->update_pi_irte != NULL;
8392}
8393
87276880
FW		 8394int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8395 struct irq_bypass_producer *prod)
8396{
8397 struct kvm_kernel_irqfd *irqfd =
8398 container_of(cons, struct kvm_kernel_irqfd, consumer);
8399
14717e20 8400 irqfd->producer = prod;
87276880 8401
14717e20
AW		 8402 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8403 prod->irq, irqfd->gsi, 1);
87276880
FW		 8404}
8405
8406void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8407 struct irq_bypass_producer *prod)
8408{
8409 int ret;
8410 struct kvm_kernel_irqfd *irqfd =
8411 container_of(cons, struct kvm_kernel_irqfd, consumer);
8412
87276880
FW		 8413 WARN_ON(irqfd->producer != prod);
8414 irqfd->producer = NULL;
8415
8416 /*
8417 * When producer of consumer is unregistered, we change back to
8418 * remapped mode, so we can re-use the current implementation
bb3541f1 8419 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8420 * int this case doesn't want to receive the interrupts.
8421 */
8422 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8423 if (ret)
8424 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8425 " fails: %d\n", irqfd->consumer.token, ret);
8426}
8427
8428int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8429 uint32_t guest_irq, bool set)
8430{
8431 if (!kvm_x86_ops->update_pi_irte)
8432 return -EINVAL;
8433
8434 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8435}
8436
52004014
FW		 8437bool kvm_vector_hashing_enabled(void)
8438{
8439 return vector_hashing;
8440}
8441EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8442
229456fc 8443EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8444EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8445EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8446EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8447EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8448EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8449EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8450EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8451EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8452EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8453EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8454EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8455EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8456EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8457EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8458EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8459EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8460EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8461EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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