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KVM: MMU: add "oos_shadow" parameter to disable oos
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
4d5c5d0f 33#include <linux/pci.h>
313a3dc7 34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
62c476c7 38#include <linux/intel-iommu.h>
043405e1
CO		 39
40#include <asm/uaccess.h>
d825ed0a 41#include <asm/msr.h>
a5f61300 42#include <asm/desc.h>
043405e1 43
313a3dc7 44#define MAX_IO_MSRS 256
a03490ed
CO		 45#define CR0_RESERVED_BITS \
46 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
47 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
48 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
49#define CR4_RESERVED_BITS \
50 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
51 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
52 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
53 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
54
55#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 56/* EFER defaults:
57 * - enable syscall per default because its emulated by KVM
58 * - enable LME and LMA per default on 64 bit KVM
59 */
60#ifdef CONFIG_X86_64
61static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
62#else
63static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
64#endif
313a3dc7 65
ba1389b7
AK		 66#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
67#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 68
674eea0f
AK		 69static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
70 struct kvm_cpuid_entry2 __user *entries);
71
97896d04 72struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 73EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 74
417bc304 75struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 76 { "pf_fixed", VCPU_STAT(pf_fixed) },
77 { "pf_guest", VCPU_STAT(pf_guest) },
78 { "tlb_flush", VCPU_STAT(tlb_flush) },
79 { "invlpg", VCPU_STAT(invlpg) },
80 { "exits", VCPU_STAT(exits) },
81 { "io_exits", VCPU_STAT(io_exits) },
82 { "mmio_exits", VCPU_STAT(mmio_exits) },
83 { "signal_exits", VCPU_STAT(signal_exits) },
84 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 85 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 86 { "halt_exits", VCPU_STAT(halt_exits) },
87 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 88 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 89 { "request_irq", VCPU_STAT(request_irq_exits) },
90 { "irq_exits", VCPU_STAT(irq_exits) },
91 { "host_state_reload", VCPU_STAT(host_state_reload) },
92 { "efer_reload", VCPU_STAT(efer_reload) },
93 { "fpu_reload", VCPU_STAT(fpu_reload) },
94 { "insn_emulation", VCPU_STAT(insn_emulation) },
95 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 96 { "irq_injections", VCPU_STAT(irq_injections) },
4cee5764
AK		 97 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
98 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
99 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
100 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
101 { "mmu_flooded", VM_STAT(mmu_flooded) },
102 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 103 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 104 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 105 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 106 { "largepages", VM_STAT(lpages) },
417bc304
HB		 107 { NULL }
108};
109
ee032c99 110static struct kvm_assigned_dev_kernel *kvm_find_assigned_dev(struct list_head *head,
4d5c5d0f
BAY		 111 int assigned_dev_id)
112{
113 struct list_head *ptr;
114 struct kvm_assigned_dev_kernel *match;
115
116 list_for_each(ptr, head) {
117 match = list_entry(ptr, struct kvm_assigned_dev_kernel, list);
118 if (match->assigned_dev_id == assigned_dev_id)
119 return match;
120 }
121 return NULL;
122}
123
124static void kvm_assigned_dev_interrupt_work_handler(struct work_struct *work)
125{
126 struct kvm_assigned_dev_kernel *assigned_dev;
127
128 assigned_dev = container_of(work, struct kvm_assigned_dev_kernel,
129 interrupt_work);
130
131 /* This is taken to safely inject irq inside the guest. When
132 * the interrupt injection (or the ioapic code) uses a
133 * finer-grained lock, update this
134 */
135 mutex_lock(&assigned_dev->kvm->lock);
136 kvm_set_irq(assigned_dev->kvm,
137 assigned_dev->guest_irq, 1);
138 mutex_unlock(&assigned_dev->kvm->lock);
139 kvm_put_kvm(assigned_dev->kvm);
140}
141
142/* FIXME: Implement the OR logic needed to make shared interrupts on
143 * this line behave properly
144 */
145static irqreturn_t kvm_assigned_dev_intr(int irq, void *dev_id)
146{
147 struct kvm_assigned_dev_kernel *assigned_dev =
148 (struct kvm_assigned_dev_kernel *) dev_id;
149
150 kvm_get_kvm(assigned_dev->kvm);
151 schedule_work(&assigned_dev->interrupt_work);
152 disable_irq_nosync(irq);
153 return IRQ_HANDLED;
154}
155
156/* Ack the irq line for an assigned device */
157static void kvm_assigned_dev_ack_irq(struct kvm_irq_ack_notifier *kian)
158{
159 struct kvm_assigned_dev_kernel *dev;
160
161 if (kian->gsi == -1)
162 return;
163
164 dev = container_of(kian, struct kvm_assigned_dev_kernel,
165 ack_notifier);
166 kvm_set_irq(dev->kvm, dev->guest_irq, 0);
167 enable_irq(dev->host_irq);
168}
169
bfadaded
AS		 170static void kvm_free_assigned_device(struct kvm *kvm,
171 struct kvm_assigned_dev_kernel
172 *assigned_dev)
173{
174 if (irqchip_in_kernel(kvm) && assigned_dev->irq_requested)
175 free_irq(assigned_dev->host_irq, (void *)assigned_dev);
176
177 kvm_unregister_irq_ack_notifier(kvm, &assigned_dev->ack_notifier);
178
179 if (cancel_work_sync(&assigned_dev->interrupt_work))
180 /* We had pending work. That means we will have to take
181 * care of kvm_put_kvm.
182 */
183 kvm_put_kvm(kvm);
184
185 pci_release_regions(assigned_dev->dev);
186 pci_disable_device(assigned_dev->dev);
187 pci_dev_put(assigned_dev->dev);
188
189 list_del(&assigned_dev->list);
190 kfree(assigned_dev);
191}
192
193static void kvm_free_all_assigned_devices(struct kvm *kvm)
194{
195 struct list_head *ptr, *ptr2;
196 struct kvm_assigned_dev_kernel *assigned_dev;
197
198 list_for_each_safe(ptr, ptr2, &kvm->arch.assigned_dev_head) {
199 assigned_dev = list_entry(ptr,
200 struct kvm_assigned_dev_kernel,
201 list);
202
203 kvm_free_assigned_device(kvm, assigned_dev);
204 }
205}
206
4d5c5d0f
BAY		 207static int kvm_vm_ioctl_assign_irq(struct kvm *kvm,
208 struct kvm_assigned_irq
209 *assigned_irq)
210{
211 int r = 0;
212 struct kvm_assigned_dev_kernel *match;
213
214 mutex_lock(&kvm->lock);
215
216 match = kvm_find_assigned_dev(&kvm->arch.assigned_dev_head,
217 assigned_irq->assigned_dev_id);
218 if (!match) {
219 mutex_unlock(&kvm->lock);
220 return -EINVAL;
221 }
222
223 if (match->irq_requested) {
224 match->guest_irq = assigned_irq->guest_irq;
225 match->ack_notifier.gsi = assigned_irq->guest_irq;
226 mutex_unlock(&kvm->lock);
227 return 0;
228 }
229
230 INIT_WORK(&match->interrupt_work,
231 kvm_assigned_dev_interrupt_work_handler);
232
233 if (irqchip_in_kernel(kvm)) {
6762b729 234 if (!capable(CAP_SYS_RAWIO)) {
bfadaded
AS		 235 r = -EPERM;
236 goto out_release;
6762b729
AS		 237 }
238
4d5c5d0f
BAY		 239 if (assigned_irq->host_irq)
240 match->host_irq = assigned_irq->host_irq;
241 else
242 match->host_irq = match->dev->irq;
243 match->guest_irq = assigned_irq->guest_irq;
244 match->ack_notifier.gsi = assigned_irq->guest_irq;
245 match->ack_notifier.irq_acked = kvm_assigned_dev_ack_irq;
246 kvm_register_irq_ack_notifier(kvm, &match->ack_notifier);
247
248 /* Even though this is PCI, we don't want to use shared
249 * interrupts. Sharing host devices with guest-assigned devices
250 * on the same interrupt line is not a happy situation: there
251 * are going to be long delays in accepting, acking, etc.
252 */
253 if (request_irq(match->host_irq, kvm_assigned_dev_intr, 0,
254 "kvm_assigned_device", (void *)match)) {
4d5c5d0f 255 r = -EIO;
bfadaded 256 goto out_release;
4d5c5d0f
BAY		 257 }
258 }
259
260 match->irq_requested = true;
4d5c5d0f
BAY		 261 mutex_unlock(&kvm->lock);
262 return r;
bfadaded
AS		 263out_release:
264 mutex_unlock(&kvm->lock);
265 kvm_free_assigned_device(kvm, match);
266 return r;
4d5c5d0f
BAY		 267}
268
269static int kvm_vm_ioctl_assign_device(struct kvm *kvm,
270 struct kvm_assigned_pci_dev *assigned_dev)
271{
272 int r = 0;
273 struct kvm_assigned_dev_kernel *match;
274 struct pci_dev *dev;
275
276 mutex_lock(&kvm->lock);
277
278 match = kvm_find_assigned_dev(&kvm->arch.assigned_dev_head,
279 assigned_dev->assigned_dev_id);
280 if (match) {
281 /* device already assigned */
282 r = -EINVAL;
283 goto out;
284 }
285
286 match = kzalloc(sizeof(struct kvm_assigned_dev_kernel), GFP_KERNEL);
287 if (match == NULL) {
288 printk(KERN_INFO "%s: Couldn't allocate memory\n",
289 __func__);
290 r = -ENOMEM;
291 goto out;
292 }
293 dev = pci_get_bus_and_slot(assigned_dev->busnr,
294 assigned_dev->devfn);
295 if (!dev) {
296 printk(KERN_INFO "%s: host device not found\n", __func__);
297 r = -EINVAL;
298 goto out_free;
299 }
300 if (pci_enable_device(dev)) {
301 printk(KERN_INFO "%s: Could not enable PCI device\n", __func__);
302 r = -EBUSY;
303 goto out_put;
304 }
305 r = pci_request_regions(dev, "kvm_assigned_device");
306 if (r) {
307 printk(KERN_INFO "%s: Could not get access to device regions\n",
308 __func__);
309 goto out_disable;
310 }
311 match->assigned_dev_id = assigned_dev->assigned_dev_id;
312 match->host_busnr = assigned_dev->busnr;
313 match->host_devfn = assigned_dev->devfn;
314 match->dev = dev;
315
316 match->kvm = kvm;
317
318 list_add(&match->list, &kvm->arch.assigned_dev_head);
319
62c476c7
BAY		 320 if (assigned_dev->flags & KVM_DEV_ASSIGN_ENABLE_IOMMU) {
321 r = kvm_iommu_map_guest(kvm, match);
322 if (r)
323 goto out_list_del;
324 }
325
4d5c5d0f
BAY		 326out:
327 mutex_unlock(&kvm->lock);
328 return r;
62c476c7
BAY		 329out_list_del:
330 list_del(&match->list);
331 pci_release_regions(dev);
4d5c5d0f
BAY		 332out_disable:
333 pci_disable_device(dev);
334out_put:
335 pci_dev_put(dev);
336out_free:
337 kfree(match);
338 mutex_unlock(&kvm->lock);
339 return r;
340}
341
5fb76f9b
CO		 342unsigned long segment_base(u16 selector)
343{
344 struct descriptor_table gdt;
a5f61300 345 struct desc_struct *d;
5fb76f9b
CO		 346 unsigned long table_base;
347 unsigned long v;
348
349 if (selector == 0)
350 return 0;
351
352 asm("sgdt %0" : "=m"(gdt));
353 table_base = gdt.base;
354
355 if (selector & 4) { /* from ldt */
356 u16 ldt_selector;
357
358 asm("sldt %0" : "=g"(ldt_selector));
359 table_base = segment_base(ldt_selector);
360 }
a5f61300
AK		 361 d = (struct desc_struct *)(table_base + (selector & ~7));
362 v = d->base0 | ((unsigned long)d->base1 << 16) |
363 ((unsigned long)d->base2 << 24);
5fb76f9b 364#ifdef CONFIG_X86_64
a5f61300
AK		 365 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
366 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 367#endif
368 return v;
369}
370EXPORT_SYMBOL_GPL(segment_base);
371
6866b83e
CO		 372u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
373{
374 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 375 return vcpu->arch.apic_base;
6866b83e 376 else
ad312c7c 377 return vcpu->arch.apic_base;
6866b83e
CO		 378}
379EXPORT_SYMBOL_GPL(kvm_get_apic_base);
380
381void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
382{
383 /* TODO: reserve bits check */
384 if (irqchip_in_kernel(vcpu->kvm))
385 kvm_lapic_set_base(vcpu, data);
386 else
ad312c7c 387 vcpu->arch.apic_base = data;
6866b83e
CO		 388}
389EXPORT_SYMBOL_GPL(kvm_set_apic_base);
390
298101da
AK		 391void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
392{
ad312c7c
ZX		 393 WARN_ON(vcpu->arch.exception.pending);
394 vcpu->arch.exception.pending = true;
395 vcpu->arch.exception.has_error_code = false;
396 vcpu->arch.exception.nr = nr;
298101da
AK		 397}
398EXPORT_SYMBOL_GPL(kvm_queue_exception);
399
c3c91fee
AK		 400void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
401 u32 error_code)
402{
403 ++vcpu->stat.pf_guest;
71c4dfaf
JR		 404 if (vcpu->arch.exception.pending) {
405 if (vcpu->arch.exception.nr == PF_VECTOR) {
406 printk(KERN_DEBUG "kvm: inject_page_fault:"
407 " double fault 0x%lx\n", addr);
408 vcpu->arch.exception.nr = DF_VECTOR;
409 vcpu->arch.exception.error_code = 0;
410 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
411 /* triple fault -> shutdown */
412 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
413 }
c3c91fee
AK		 414 return;
415 }
ad312c7c 416 vcpu->arch.cr2 = addr;
c3c91fee
AK		 417 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
418}
419
3419ffc8
SY		 420void kvm_inject_nmi(struct kvm_vcpu *vcpu)
421{
422 vcpu->arch.nmi_pending = 1;
423}
424EXPORT_SYMBOL_GPL(kvm_inject_nmi);
425
298101da
AK		 426void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
427{
ad312c7c
ZX		 428 WARN_ON(vcpu->arch.exception.pending);
429 vcpu->arch.exception.pending = true;
430 vcpu->arch.exception.has_error_code = true;
431 vcpu->arch.exception.nr = nr;
432 vcpu->arch.exception.error_code = error_code;
298101da
AK		 433}
434EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
435
436static void __queue_exception(struct kvm_vcpu *vcpu)
437{
ad312c7c
ZX		 438 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
439 vcpu->arch.exception.has_error_code,
440 vcpu->arch.exception.error_code);
298101da
AK		 441}
442
a03490ed
CO		 443/*
444 * Load the pae pdptrs. Return true is they are all valid.
445 */
446int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
447{
448 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
449 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
450 int i;
451 int ret;
ad312c7c 452 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 453
a03490ed
CO		 454 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
455 offset * sizeof(u64), sizeof(pdpte));
456 if (ret < 0) {
457 ret = 0;
458 goto out;
459 }
460 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
461 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
462 ret = 0;
463 goto out;
464 }
465 }
466 ret = 1;
467
ad312c7c 468 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 469out:
a03490ed
CO		 470
471 return ret;
472}
cc4b6871 473EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 474
d835dfec
AK		 475static bool pdptrs_changed(struct kvm_vcpu *vcpu)
476{
ad312c7c 477 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 478 bool changed = true;
479 int r;
480
481 if (is_long_mode(vcpu) || !is_pae(vcpu))
482 return false;
483
ad312c7c 484 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 485 if (r < 0)
486 goto out;
ad312c7c 487 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 488out:
d835dfec
AK		 489
490 return changed;
491}
492
2d3ad1f4 493void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 494{
495 if (cr0 & CR0_RESERVED_BITS) {
496 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 497 cr0, vcpu->arch.cr0);
c1a5d4f9 498 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 499 return;
500 }
501
502 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
503 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 504 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 505 return;
506 }
507
508 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
509 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
510 "and a clear PE flag\n");
c1a5d4f9 511 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 512 return;
513 }
514
515 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
516#ifdef CONFIG_X86_64
ad312c7c 517 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 518 int cs_db, cs_l;
519
520 if (!is_pae(vcpu)) {
521 printk(KERN_DEBUG "set_cr0: #GP, start paging "
522 "in long mode while PAE is disabled\n");
c1a5d4f9 523 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 524 return;
525 }
526 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
527 if (cs_l) {
528 printk(KERN_DEBUG "set_cr0: #GP, start paging "
529 "in long mode while CS.L == 1\n");
c1a5d4f9 530 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 531 return;
532
533 }
534 } else
535#endif
ad312c7c 536 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 537 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
538 "reserved bits\n");
c1a5d4f9 539 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 540 return;
541 }
542
543 }
544
545 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 546 vcpu->arch.cr0 = cr0;
a03490ed 547
a03490ed 548 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 549 return;
550}
2d3ad1f4 551EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 552
2d3ad1f4 553void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 554{
2d3ad1f4 555 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 556 KVMTRACE_1D(LMSW, vcpu,
557 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
558 handler);
a03490ed 559}
2d3ad1f4 560EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 561
2d3ad1f4 562void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 563{
564 if (cr4 & CR4_RESERVED_BITS) {
565 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 566 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 567 return;
568 }
569
570 if (is_long_mode(vcpu)) {
571 if (!(cr4 & X86_CR4_PAE)) {
572 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
573 "in long mode\n");
c1a5d4f9 574 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 575 return;
576 }
577 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 578 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 579 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 580 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 581 return;
582 }
583
584 if (cr4 & X86_CR4_VMXE) {
585 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 586 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 587 return;
588 }
589 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 590 vcpu->arch.cr4 = cr4;
a03490ed 591 kvm_mmu_reset_context(vcpu);
a03490ed 592}
2d3ad1f4 593EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 594
2d3ad1f4 595void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 596{
ad312c7c 597 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 598 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 599 kvm_mmu_flush_tlb(vcpu);
600 return;
601 }
602
a03490ed
CO		 603 if (is_long_mode(vcpu)) {
604 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
605 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 606 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 607 return;
608 }
609 } else {
610 if (is_pae(vcpu)) {
611 if (cr3 & CR3_PAE_RESERVED_BITS) {
612 printk(KERN_DEBUG
613 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 614 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 615 return;
616 }
617 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
618 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
619 "reserved bits\n");
c1a5d4f9 620 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 621 return;
622 }
623 }
624 /*
625 * We don't check reserved bits in nonpae mode, because
626 * this isn't enforced, and VMware depends on this.
627 */
628 }
629
a03490ed
CO		 630 /*
631 * Does the new cr3 value map to physical memory? (Note, we
632 * catch an invalid cr3 even in real-mode, because it would
633 * cause trouble later on when we turn on paging anyway.)
634 *
635 * A real CPU would silently accept an invalid cr3 and would
636 * attempt to use it - with largely undefined (and often hard
637 * to debug) behavior on the guest side.
638 */
639 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 640 kvm_inject_gp(vcpu, 0);
a03490ed 641 else {
ad312c7c
ZX		 642 vcpu->arch.cr3 = cr3;
643 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 644 }
a03490ed 645}
2d3ad1f4 646EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 647
2d3ad1f4 648void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 649{
650 if (cr8 & CR8_RESERVED_BITS) {
651 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 652 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 653 return;
654 }
655 if (irqchip_in_kernel(vcpu->kvm))
656 kvm_lapic_set_tpr(vcpu, cr8);
657 else
ad312c7c 658 vcpu->arch.cr8 = cr8;
a03490ed 659}
2d3ad1f4 660EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 661
2d3ad1f4 662unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 663{
664 if (irqchip_in_kernel(vcpu->kvm))
665 return kvm_lapic_get_cr8(vcpu);
666 else
ad312c7c 667 return vcpu->arch.cr8;
a03490ed 668}
2d3ad1f4 669EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 670
043405e1
CO		 671/*
672 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
673 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
674 *
675 * This list is modified at module load time to reflect the
676 * capabilities of the host cpu.
677 */
678static u32 msrs_to_save[] = {
679 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
680 MSR_K6_STAR,
681#ifdef CONFIG_X86_64
682 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
683#endif
18068523 684 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
847f0ad8 685 MSR_IA32_PERF_STATUS,
043405e1
CO		 686};
687
688static unsigned num_msrs_to_save;
689
690static u32 emulated_msrs[] = {
691 MSR_IA32_MISC_ENABLE,
692};
693
15c4a640
CO		 694static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
695{
f2b4b7dd 696 if (efer & efer_reserved_bits) {
15c4a640
CO		 697 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
698 efer);
c1a5d4f9 699 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 700 return;
701 }
702
703 if (is_paging(vcpu)
ad312c7c 704 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 705 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 706 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 707 return;
708 }
709
710 kvm_x86_ops->set_efer(vcpu, efer);
711
712 efer &= ~EFER_LMA;
ad312c7c 713 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 714
ad312c7c 715 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 716}
717
f2b4b7dd
JR		 718void kvm_enable_efer_bits(u64 mask)
719{
720 efer_reserved_bits &= ~mask;
721}
722EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
723
724
15c4a640
CO		 725/*
726 * Writes msr value into into the appropriate "register".
727 * Returns 0 on success, non-0 otherwise.
728 * Assumes vcpu_load() was already called.
729 */
730int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
731{
732 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
733}
734
313a3dc7
CO		 735/*
736 * Adapt set_msr() to msr_io()'s calling convention
737 */
738static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
739{
740 return kvm_set_msr(vcpu, index, *data);
741}
742
18068523
GOC		 743static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
744{
745 static int version;
50d0a0f9
GH		 746 struct pvclock_wall_clock wc;
747 struct timespec now, sys, boot;
18068523
GOC		 748
749 if (!wall_clock)
750 return;
751
752 version++;
753
18068523
GOC		 754 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
755
50d0a0f9
GH		 756 /*
757 * The guest calculates current wall clock time by adding
758 * system time (updated by kvm_write_guest_time below) to the
759 * wall clock specified here. guest system time equals host
760 * system time for us, thus we must fill in host boot time here.
761 */
762 now = current_kernel_time();
763 ktime_get_ts(&sys);
764 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
765
766 wc.sec = boot.tv_sec;
767 wc.nsec = boot.tv_nsec;
768 wc.version = version;
18068523
GOC		 769
770 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
771
772 version++;
773 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 774}
775
50d0a0f9
GH		 776static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
777{
778 uint32_t quotient, remainder;
779
780 /* Don't try to replace with do_div(), this one calculates
781 * "(dividend << 32) / divisor" */
782 __asm__ ( "divl %4"
783 : "=a" (quotient), "=d" (remainder)
784 : "0" (0), "1" (dividend), "r" (divisor) );
785 return quotient;
786}
787
788static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
789{
790 uint64_t nsecs = 1000000000LL;
791 int32_t shift = 0;
792 uint64_t tps64;
793 uint32_t tps32;
794
795 tps64 = tsc_khz * 1000LL;
796 while (tps64 > nsecs*2) {
797 tps64 >>= 1;
798 shift--;
799 }
800
801 tps32 = (uint32_t)tps64;
802 while (tps32 <= (uint32_t)nsecs) {
803 tps32 <<= 1;
804 shift++;
805 }
806
807 hv_clock->tsc_shift = shift;
808 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
809
810 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
811 __FUNCTION__, tsc_khz, hv_clock->tsc_shift,
812 hv_clock->tsc_to_system_mul);
813}
814
18068523
GOC		 815static void kvm_write_guest_time(struct kvm_vcpu *v)
816{
817 struct timespec ts;
818 unsigned long flags;
819 struct kvm_vcpu_arch *vcpu = &v->arch;
820 void *shared_kaddr;
821
822 if ((!vcpu->time_page))
823 return;
824
50d0a0f9
GH		 825 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
826 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
827 vcpu->hv_clock_tsc_khz = tsc_khz;
828 }
829
18068523
GOC		 830 /* Keep irq disabled to prevent changes to the clock */
831 local_irq_save(flags);
832 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
833 &vcpu->hv_clock.tsc_timestamp);
834 ktime_get_ts(&ts);
835 local_irq_restore(flags);
836
837 /* With all the info we got, fill in the values */
838
839 vcpu->hv_clock.system_time = ts.tv_nsec +
840 (NSEC_PER_SEC * (u64)ts.tv_sec);
841 /*
842 * The interface expects us to write an even number signaling that the
843 * update is finished. Since the guest won't see the intermediate
50d0a0f9 844 * state, we just increase by 2 at the end.
18068523 845 */
50d0a0f9 846 vcpu->hv_clock.version += 2;
18068523
GOC		 847
848 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
849
850 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 851 sizeof(vcpu->hv_clock));
18068523
GOC		 852
853 kunmap_atomic(shared_kaddr, KM_USER0);
854
855 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
856}
857
9ba075a6
AK		 858static bool msr_mtrr_valid(unsigned msr)
859{
860 switch (msr) {
861 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
862 case MSR_MTRRfix64K_00000:
863 case MSR_MTRRfix16K_80000:
864 case MSR_MTRRfix16K_A0000:
865 case MSR_MTRRfix4K_C0000:
866 case MSR_MTRRfix4K_C8000:
867 case MSR_MTRRfix4K_D0000:
868 case MSR_MTRRfix4K_D8000:
869 case MSR_MTRRfix4K_E0000:
870 case MSR_MTRRfix4K_E8000:
871 case MSR_MTRRfix4K_F0000:
872 case MSR_MTRRfix4K_F8000:
873 case MSR_MTRRdefType:
874 case MSR_IA32_CR_PAT:
875 return true;
876 case 0x2f8:
877 return true;
878 }
879 return false;
880}
881
882static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
883{
884 if (!msr_mtrr_valid(msr))
885 return 1;
886
887 vcpu->arch.mtrr[msr - 0x200] = data;
888 return 0;
889}
15c4a640
CO		 890
891int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
892{
893 switch (msr) {
15c4a640
CO		 894 case MSR_EFER:
895 set_efer(vcpu, data);
896 break;
15c4a640
CO		 897 case MSR_IA32_MC0_STATUS:
898 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 899 __func__, data);
15c4a640
CO		 900 break;
901 case MSR_IA32_MCG_STATUS:
902 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 903 __func__, data);
15c4a640 904 break;
c7ac679c
JR		 905 case MSR_IA32_MCG_CTL:
906 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 907 __func__, data);
c7ac679c 908 break;
b5e2fec0
AG		 909 case MSR_IA32_DEBUGCTLMSR:
910 if (!data) {
911 /* We support the non-activated case already */
912 break;
913 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
914 /* Values other than LBR and BTF are vendor-specific,
915 thus reserved and should throw a #GP */
916 return 1;
917 }
918 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
919 __func__, data);
920 break;
15c4a640
CO		 921 case MSR_IA32_UCODE_REV:
922 case MSR_IA32_UCODE_WRITE:
15c4a640 923 break;
9ba075a6
AK		 924 case 0x200 ... 0x2ff:
925 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 926 case MSR_IA32_APICBASE:
927 kvm_set_apic_base(vcpu, data);
928 break;
929 case MSR_IA32_MISC_ENABLE:
ad312c7c 930 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 931 break;
18068523
GOC		 932 case MSR_KVM_WALL_CLOCK:
933 vcpu->kvm->arch.wall_clock = data;
934 kvm_write_wall_clock(vcpu->kvm, data);
935 break;
936 case MSR_KVM_SYSTEM_TIME: {
937 if (vcpu->arch.time_page) {
938 kvm_release_page_dirty(vcpu->arch.time_page);
939 vcpu->arch.time_page = NULL;
940 }
941
942 vcpu->arch.time = data;
943
944 /* we verify if the enable bit is set... */
945 if (!(data & 1))
946 break;
947
948 /* ...but clean it before doing the actual write */
949 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
950
18068523
GOC		 951 vcpu->arch.time_page =
952 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 953
954 if (is_error_page(vcpu->arch.time_page)) {
955 kvm_release_page_clean(vcpu->arch.time_page);
956 vcpu->arch.time_page = NULL;
957 }
958
959 kvm_write_guest_time(vcpu);
960 break;
961 }
15c4a640 962 default:
565f1fbd 963 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 964 return 1;
965 }
966 return 0;
967}
968EXPORT_SYMBOL_GPL(kvm_set_msr_common);
969
970
971/*
972 * Reads an msr value (of 'msr_index') into 'pdata'.
973 * Returns 0 on success, non-0 otherwise.
974 * Assumes vcpu_load() was already called.
975 */
976int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
977{
978 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
979}
980
9ba075a6
AK		 981static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
982{
983 if (!msr_mtrr_valid(msr))
984 return 1;
985
986 *pdata = vcpu->arch.mtrr[msr - 0x200];
987 return 0;
988}
989
15c4a640
CO		 990int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
991{
992 u64 data;
993
994 switch (msr) {
995 case 0xc0010010: /* SYSCFG */
996 case 0xc0010015: /* HWCR */
997 case MSR_IA32_PLATFORM_ID:
998 case MSR_IA32_P5_MC_ADDR:
999 case MSR_IA32_P5_MC_TYPE:
1000 case MSR_IA32_MC0_CTL:
1001 case MSR_IA32_MCG_STATUS:
1002 case MSR_IA32_MCG_CAP:
c7ac679c 1003 case MSR_IA32_MCG_CTL:
15c4a640
CO		 1004 case MSR_IA32_MC0_MISC:
1005 case MSR_IA32_MC0_MISC+4:
1006 case MSR_IA32_MC0_MISC+8:
1007 case MSR_IA32_MC0_MISC+12:
1008 case MSR_IA32_MC0_MISC+16:
a89c1ad2 1009 case MSR_IA32_MC0_MISC+20:
15c4a640 1010 case MSR_IA32_UCODE_REV:
15c4a640 1011 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1012 case MSR_IA32_DEBUGCTLMSR:
1013 case MSR_IA32_LASTBRANCHFROMIP:
1014 case MSR_IA32_LASTBRANCHTOIP:
1015 case MSR_IA32_LASTINTFROMIP:
1016 case MSR_IA32_LASTINTTOIP:
15c4a640
CO		 1017 data = 0;
1018 break;
9ba075a6
AK		 1019 case MSR_MTRRcap:
1020 data = 0x500 | KVM_NR_VAR_MTRR;
1021 break;
1022 case 0x200 ... 0x2ff:
1023 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1024 case 0xcd: /* fsb frequency */
1025 data = 3;
1026 break;
1027 case MSR_IA32_APICBASE:
1028 data = kvm_get_apic_base(vcpu);
1029 break;
1030 case MSR_IA32_MISC_ENABLE:
ad312c7c 1031 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1032 break;
847f0ad8
AG		 1033 case MSR_IA32_PERF_STATUS:
1034 /* TSC increment by tick */
1035 data = 1000ULL;
1036 /* CPU multiplier */
1037 data |= (((uint64_t)4ULL) << 40);
1038 break;
15c4a640 1039 case MSR_EFER:
ad312c7c 1040 data = vcpu->arch.shadow_efer;
15c4a640 1041 break;
18068523
GOC		 1042 case MSR_KVM_WALL_CLOCK:
1043 data = vcpu->kvm->arch.wall_clock;
1044 break;
1045 case MSR_KVM_SYSTEM_TIME:
1046 data = vcpu->arch.time;
1047 break;
15c4a640
CO		 1048 default:
1049 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1050 return 1;
1051 }
1052 *pdata = data;
1053 return 0;
1054}
1055EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1056
313a3dc7
CO		 1057/*
1058 * Read or write a bunch of msrs. All parameters are kernel addresses.
1059 *
1060 * @return number of msrs set successfully.
1061 */
1062static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1063 struct kvm_msr_entry *entries,
1064 int (*do_msr)(struct kvm_vcpu *vcpu,
1065 unsigned index, u64 *data))
1066{
1067 int i;
1068
1069 vcpu_load(vcpu);
1070
3200f405 1071 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1072 for (i = 0; i < msrs->nmsrs; ++i)
1073 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1074 break;
3200f405 1075 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1076
1077 vcpu_put(vcpu);
1078
1079 return i;
1080}
1081
1082/*
1083 * Read or write a bunch of msrs. Parameters are user addresses.
1084 *
1085 * @return number of msrs set successfully.
1086 */
1087static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1088 int (*do_msr)(struct kvm_vcpu *vcpu,
1089 unsigned index, u64 *data),
1090 int writeback)
1091{
1092 struct kvm_msrs msrs;
1093 struct kvm_msr_entry *entries;
1094 int r, n;
1095 unsigned size;
1096
1097 r = -EFAULT;
1098 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1099 goto out;
1100
1101 r = -E2BIG;
1102 if (msrs.nmsrs >= MAX_IO_MSRS)
1103 goto out;
1104
1105 r = -ENOMEM;
1106 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1107 entries = vmalloc(size);
1108 if (!entries)
1109 goto out;
1110
1111 r = -EFAULT;
1112 if (copy_from_user(entries, user_msrs->entries, size))
1113 goto out_free;
1114
1115 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1116 if (r < 0)
1117 goto out_free;
1118
1119 r = -EFAULT;
1120 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1121 goto out_free;
1122
1123 r = n;
1124
1125out_free:
1126 vfree(entries);
1127out:
1128 return r;
1129}
1130
018d00d2
ZX		 1131int kvm_dev_ioctl_check_extension(long ext)
1132{
1133 int r;
1134
1135 switch (ext) {
1136 case KVM_CAP_IRQCHIP:
1137 case KVM_CAP_HLT:
1138 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
1139 case KVM_CAP_USER_MEMORY:
1140 case KVM_CAP_SET_TSS_ADDR:
07716717 1141 case KVM_CAP_EXT_CPUID:
18068523 1142 case KVM_CAP_CLOCKSOURCE:
7837699f 1143 case KVM_CAP_PIT:
a28e4f5a 1144 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1145 case KVM_CAP_MP_STATE:
ed848624 1146 case KVM_CAP_SYNC_MMU:
018d00d2
ZX		 1147 r = 1;
1148 break;
542472b5
LV		 1149 case KVM_CAP_COALESCED_MMIO:
1150 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1151 break;
774ead3a
AK		 1152 case KVM_CAP_VAPIC:
1153 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1154 break;
f725230a
AK		 1155 case KVM_CAP_NR_VCPUS:
1156 r = KVM_MAX_VCPUS;
1157 break;
a988b910
AK		 1158 case KVM_CAP_NR_MEMSLOTS:
1159 r = KVM_MEMORY_SLOTS;
1160 break;
2f333bcb
MT		 1161 case KVM_CAP_PV_MMU:
1162 r = !tdp_enabled;
1163 break;
62c476c7
BAY		 1164 case KVM_CAP_IOMMU:
1165 r = intel_iommu_found();
1166 break;
018d00d2
ZX		 1167 default:
1168 r = 0;
1169 break;
1170 }
1171 return r;
1172
1173}
1174
043405e1
CO		 1175long kvm_arch_dev_ioctl(struct file *filp,
1176 unsigned int ioctl, unsigned long arg)
1177{
1178 void __user *argp = (void __user *)arg;
1179 long r;
1180
1181 switch (ioctl) {
1182 case KVM_GET_MSR_INDEX_LIST: {
1183 struct kvm_msr_list __user *user_msr_list = argp;
1184 struct kvm_msr_list msr_list;
1185 unsigned n;
1186
1187 r = -EFAULT;
1188 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1189 goto out;
1190 n = msr_list.nmsrs;
1191 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1192 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1193 goto out;
1194 r = -E2BIG;
1195 if (n < num_msrs_to_save)
1196 goto out;
1197 r = -EFAULT;
1198 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1199 num_msrs_to_save * sizeof(u32)))
1200 goto out;
1201 if (copy_to_user(user_msr_list->indices
1202 + num_msrs_to_save * sizeof(u32),
1203 &emulated_msrs,
1204 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1205 goto out;
1206 r = 0;
1207 break;
1208 }
674eea0f
AK		 1209 case KVM_GET_SUPPORTED_CPUID: {
1210 struct kvm_cpuid2 __user *cpuid_arg = argp;
1211 struct kvm_cpuid2 cpuid;
1212
1213 r = -EFAULT;
1214 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1215 goto out;
1216 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1217 cpuid_arg->entries);
1218 if (r)
1219 goto out;
1220
1221 r = -EFAULT;
1222 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1223 goto out;
1224 r = 0;
1225 break;
1226 }
043405e1
CO		 1227 default:
1228 r = -EINVAL;
1229 }
1230out:
1231 return r;
1232}
1233
313a3dc7
CO		 1234void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1235{
1236 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 1237 kvm_write_guest_time(vcpu);
313a3dc7
CO		 1238}
1239
1240void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1241{
1242 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1243 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1244}
1245
07716717 1246static int is_efer_nx(void)
313a3dc7
CO		 1247{
1248 u64 efer;
313a3dc7
CO		 1249
1250 rdmsrl(MSR_EFER, efer);
07716717
DK		 1251 return efer & EFER_NX;
1252}
1253
1254static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1255{
1256 int i;
1257 struct kvm_cpuid_entry2 *e, *entry;
1258
313a3dc7 1259 entry = NULL;
ad312c7c
ZX		 1260 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1261 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1262 if (e->function == 0x80000001) {
1263 entry = e;
1264 break;
1265 }
1266 }
07716717 1267 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1268 entry->edx &= ~(1 << 20);
1269 printk(KERN_INFO "kvm: guest NX capability removed\n");
1270 }
1271}
1272
07716717 1273/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1274static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1275 struct kvm_cpuid *cpuid,
1276 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1277{
1278 int r, i;
1279 struct kvm_cpuid_entry *cpuid_entries;
1280
1281 r = -E2BIG;
1282 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1283 goto out;
1284 r = -ENOMEM;
1285 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1286 if (!cpuid_entries)
1287 goto out;
1288 r = -EFAULT;
1289 if (copy_from_user(cpuid_entries, entries,
1290 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1291 goto out_free;
1292 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1293 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1294 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1295 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1296 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1297 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1298 vcpu->arch.cpuid_entries[i].index = 0;
1299 vcpu->arch.cpuid_entries[i].flags = 0;
1300 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1301 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1302 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1303 }
1304 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1305 cpuid_fix_nx_cap(vcpu);
1306 r = 0;
1307
1308out_free:
1309 vfree(cpuid_entries);
1310out:
1311 return r;
1312}
1313
1314static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1315 struct kvm_cpuid2 *cpuid,
1316 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1317{
1318 int r;
1319
1320 r = -E2BIG;
1321 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1322 goto out;
1323 r = -EFAULT;
ad312c7c 1324 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1325 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1326 goto out;
ad312c7c 1327 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1328 return 0;
1329
1330out:
1331 return r;
1332}
1333
07716717
DK		 1334static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1335 struct kvm_cpuid2 *cpuid,
1336 struct kvm_cpuid_entry2 __user *entries)
1337{
1338 int r;
1339
1340 r = -E2BIG;
ad312c7c 1341 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1342 goto out;
1343 r = -EFAULT;
ad312c7c
ZX		 1344 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1345 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1346 goto out;
1347 return 0;
1348
1349out:
ad312c7c 1350 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1351 return r;
1352}
1353
1354static inline u32 bit(int bitno)
1355{
1356 return 1 << (bitno & 31);
1357}
1358
1359static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1360 u32 index)
1361{
1362 entry->function = function;
1363 entry->index = index;
1364 cpuid_count(entry->function, entry->index,
1365 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1366 entry->flags = 0;
1367}
1368
1369static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1370 u32 index, int *nent, int maxnent)
1371{
1372 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1373 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1374 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1375 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1376 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1377 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1378 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1379 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1380 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1381 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1382 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1383 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1384 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1385 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1386 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1387 bit(X86_FEATURE_PGE) |
1388 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1389 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1390 bit(X86_FEATURE_SYSCALL) |
1391 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1392#ifdef CONFIG_X86_64
1393 bit(X86_FEATURE_LM) |
1394#endif
1395 bit(X86_FEATURE_MMXEXT) |
1396 bit(X86_FEATURE_3DNOWEXT) |
1397 bit(X86_FEATURE_3DNOW);
1398 const u32 kvm_supported_word3_x86_features =
1399 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1400 const u32 kvm_supported_word6_x86_features =
1401 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY);
1402
1403 /* all func 2 cpuid_count() should be called on the same cpu */
1404 get_cpu();
1405 do_cpuid_1_ent(entry, function, index);
1406 ++*nent;
1407
1408 switch (function) {
1409 case 0:
1410 entry->eax = min(entry->eax, (u32)0xb);
1411 break;
1412 case 1:
1413 entry->edx &= kvm_supported_word0_x86_features;
1414 entry->ecx &= kvm_supported_word3_x86_features;
1415 break;
1416 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1417 * may return different values. This forces us to get_cpu() before
1418 * issuing the first command, and also to emulate this annoying behavior
1419 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1420 case 2: {
1421 int t, times = entry->eax & 0xff;
1422
1423 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1424 for (t = 1; t < times && *nent < maxnent; ++t) {
1425 do_cpuid_1_ent(&entry[t], function, 0);
1426 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1427 ++*nent;
1428 }
1429 break;
1430 }
1431 /* function 4 and 0xb have additional index. */
1432 case 4: {
14af3f3c 1433 int i, cache_type;
07716717
DK		 1434
1435 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1436 /* read more entries until cache_type is zero */
14af3f3c
HH		 1437 for (i = 1; *nent < maxnent; ++i) {
1438 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1439 if (!cache_type)
1440 break;
14af3f3c
HH		 1441 do_cpuid_1_ent(&entry[i], function, i);
1442 entry[i].flags |=
07716717
DK		 1443 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1444 ++*nent;
1445 }
1446 break;
1447 }
1448 case 0xb: {
14af3f3c 1449 int i, level_type;
07716717
DK		 1450
1451 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1452 /* read more entries until level_type is zero */
14af3f3c
HH		 1453 for (i = 1; *nent < maxnent; ++i) {
1454 level_type = entry[i - 1].ecx & 0xff;
07716717
DK		 1455 if (!level_type)
1456 break;
14af3f3c
HH		 1457 do_cpuid_1_ent(&entry[i], function, i);
1458 entry[i].flags |=
07716717
DK		 1459 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1460 ++*nent;
1461 }
1462 break;
1463 }
1464 case 0x80000000:
1465 entry->eax = min(entry->eax, 0x8000001a);
1466 break;
1467 case 0x80000001:
1468 entry->edx &= kvm_supported_word1_x86_features;
1469 entry->ecx &= kvm_supported_word6_x86_features;
1470 break;
1471 }
1472 put_cpu();
1473}
1474
674eea0f 1475static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1476 struct kvm_cpuid_entry2 __user *entries)
1477{
1478 struct kvm_cpuid_entry2 *cpuid_entries;
1479 int limit, nent = 0, r = -E2BIG;
1480 u32 func;
1481
1482 if (cpuid->nent < 1)
1483 goto out;
1484 r = -ENOMEM;
1485 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1486 if (!cpuid_entries)
1487 goto out;
1488
1489 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1490 limit = cpuid_entries[0].eax;
1491 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1492 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1493 &nent, cpuid->nent);
1494 r = -E2BIG;
1495 if (nent >= cpuid->nent)
1496 goto out_free;
1497
1498 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1499 limit = cpuid_entries[nent - 1].eax;
1500 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1501 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1502 &nent, cpuid->nent);
1503 r = -EFAULT;
1504 if (copy_to_user(entries, cpuid_entries,
1505 nent * sizeof(struct kvm_cpuid_entry2)))
1506 goto out_free;
1507 cpuid->nent = nent;
1508 r = 0;
1509
1510out_free:
1511 vfree(cpuid_entries);
1512out:
1513 return r;
1514}
1515
313a3dc7
CO		 1516static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1517 struct kvm_lapic_state *s)
1518{
1519 vcpu_load(vcpu);
ad312c7c 1520 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1521 vcpu_put(vcpu);
1522
1523 return 0;
1524}
1525
1526static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1527 struct kvm_lapic_state *s)
1528{
1529 vcpu_load(vcpu);
ad312c7c 1530 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1531 kvm_apic_post_state_restore(vcpu);
1532 vcpu_put(vcpu);
1533
1534 return 0;
1535}
1536
f77bc6a4
ZX		 1537static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1538 struct kvm_interrupt *irq)
1539{
1540 if (irq->irq < 0 || irq->irq >= 256)
1541 return -EINVAL;
1542 if (irqchip_in_kernel(vcpu->kvm))
1543 return -ENXIO;
1544 vcpu_load(vcpu);
1545
ad312c7c
ZX		 1546 set_bit(irq->irq, vcpu->arch.irq_pending);
1547 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1548
1549 vcpu_put(vcpu);
1550
1551 return 0;
1552}
1553
b209749f
AK		 1554static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1555 struct kvm_tpr_access_ctl *tac)
1556{
1557 if (tac->flags)
1558 return -EINVAL;
1559 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1560 return 0;
1561}
1562
313a3dc7
CO		 1563long kvm_arch_vcpu_ioctl(struct file *filp,
1564 unsigned int ioctl, unsigned long arg)
1565{
1566 struct kvm_vcpu *vcpu = filp->private_data;
1567 void __user *argp = (void __user *)arg;
1568 int r;
b772ff36 1569 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1570
1571 switch (ioctl) {
1572 case KVM_GET_LAPIC: {
b772ff36 1573 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1574
b772ff36
DH		 1575 r = -ENOMEM;
1576 if (!lapic)
1577 goto out;
1578 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1579 if (r)
1580 goto out;
1581 r = -EFAULT;
b772ff36 1582 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1583 goto out;
1584 r = 0;
1585 break;
1586 }
1587 case KVM_SET_LAPIC: {
b772ff36
DH		 1588 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1589 r = -ENOMEM;
1590 if (!lapic)
1591 goto out;
313a3dc7 1592 r = -EFAULT;
b772ff36 1593 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1594 goto out;
b772ff36 1595 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1596 if (r)
1597 goto out;
1598 r = 0;
1599 break;
1600 }
f77bc6a4
ZX		 1601 case KVM_INTERRUPT: {
1602 struct kvm_interrupt irq;
1603
1604 r = -EFAULT;
1605 if (copy_from_user(&irq, argp, sizeof irq))
1606 goto out;
1607 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1608 if (r)
1609 goto out;
1610 r = 0;
1611 break;
1612 }
313a3dc7
CO		 1613 case KVM_SET_CPUID: {
1614 struct kvm_cpuid __user *cpuid_arg = argp;
1615 struct kvm_cpuid cpuid;
1616
1617 r = -EFAULT;
1618 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1619 goto out;
1620 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1621 if (r)
1622 goto out;
1623 break;
1624 }
07716717
DK		 1625 case KVM_SET_CPUID2: {
1626 struct kvm_cpuid2 __user *cpuid_arg = argp;
1627 struct kvm_cpuid2 cpuid;
1628
1629 r = -EFAULT;
1630 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1631 goto out;
1632 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1633 cpuid_arg->entries);
1634 if (r)
1635 goto out;
1636 break;
1637 }
1638 case KVM_GET_CPUID2: {
1639 struct kvm_cpuid2 __user *cpuid_arg = argp;
1640 struct kvm_cpuid2 cpuid;
1641
1642 r = -EFAULT;
1643 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1644 goto out;
1645 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1646 cpuid_arg->entries);
1647 if (r)
1648 goto out;
1649 r = -EFAULT;
1650 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1651 goto out;
1652 r = 0;
1653 break;
1654 }
313a3dc7
CO		 1655 case KVM_GET_MSRS:
1656 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1657 break;
1658 case KVM_SET_MSRS:
1659 r = msr_io(vcpu, argp, do_set_msr, 0);
1660 break;
b209749f
AK		 1661 case KVM_TPR_ACCESS_REPORTING: {
1662 struct kvm_tpr_access_ctl tac;
1663
1664 r = -EFAULT;
1665 if (copy_from_user(&tac, argp, sizeof tac))
1666 goto out;
1667 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1668 if (r)
1669 goto out;
1670 r = -EFAULT;
1671 if (copy_to_user(argp, &tac, sizeof tac))
1672 goto out;
1673 r = 0;
1674 break;
1675 };
b93463aa
AK		 1676 case KVM_SET_VAPIC_ADDR: {
1677 struct kvm_vapic_addr va;
1678
1679 r = -EINVAL;
1680 if (!irqchip_in_kernel(vcpu->kvm))
1681 goto out;
1682 r = -EFAULT;
1683 if (copy_from_user(&va, argp, sizeof va))
1684 goto out;
1685 r = 0;
1686 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1687 break;
1688 }
313a3dc7
CO		 1689 default:
1690 r = -EINVAL;
1691 }
1692out:
b772ff36
DH		 1693 if (lapic)
1694 kfree(lapic);
313a3dc7
CO		 1695 return r;
1696}
1697
1fe779f8
CO		 1698static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1699{
1700 int ret;
1701
1702 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1703 return -1;
1704 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1705 return ret;
1706}
1707
1708static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1709 u32 kvm_nr_mmu_pages)
1710{
1711 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1712 return -EINVAL;
1713
72dc67a6 1714 down_write(&kvm->slots_lock);
1fe779f8
CO		 1715
1716 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1717 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1718
72dc67a6 1719 up_write(&kvm->slots_lock);
1fe779f8
CO		 1720 return 0;
1721}
1722
1723static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1724{
f05e70ac 1725 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1726}
1727
e9f85cde
ZX		 1728gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1729{
1730 int i;
1731 struct kvm_mem_alias *alias;
1732
d69fb81f
ZX		 1733 for (i = 0; i < kvm->arch.naliases; ++i) {
1734 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1735 if (gfn >= alias->base_gfn
1736 && gfn < alias->base_gfn + alias->npages)
1737 return alias->target_gfn + gfn - alias->base_gfn;
1738 }
1739 return gfn;
1740}
1741
1fe779f8
CO		 1742/*
1743 * Set a new alias region. Aliases map a portion of physical memory into
1744 * another portion. This is useful for memory windows, for example the PC
1745 * VGA region.
1746 */
1747static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1748 struct kvm_memory_alias *alias)
1749{
1750 int r, n;
1751 struct kvm_mem_alias *p;
1752
1753 r = -EINVAL;
1754 /* General sanity checks */
1755 if (alias->memory_size & (PAGE_SIZE - 1))
1756 goto out;
1757 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1758 goto out;
1759 if (alias->slot >= KVM_ALIAS_SLOTS)
1760 goto out;
1761 if (alias->guest_phys_addr + alias->memory_size
1762 < alias->guest_phys_addr)
1763 goto out;
1764 if (alias->target_phys_addr + alias->memory_size
1765 < alias->target_phys_addr)
1766 goto out;
1767
72dc67a6 1768 down_write(&kvm->slots_lock);
a1708ce8 1769 spin_lock(&kvm->mmu_lock);
1fe779f8 1770
d69fb81f 1771 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1772 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1773 p->npages = alias->memory_size >> PAGE_SHIFT;
1774 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1775
1776 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1777 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1778 break;
d69fb81f 1779 kvm->arch.naliases = n;
1fe779f8 1780
a1708ce8 1781 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1782 kvm_mmu_zap_all(kvm);
1783
72dc67a6 1784 up_write(&kvm->slots_lock);
1fe779f8
CO		 1785
1786 return 0;
1787
1788out:
1789 return r;
1790}
1791
1792static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1793{
1794 int r;
1795
1796 r = 0;
1797 switch (chip->chip_id) {
1798 case KVM_IRQCHIP_PIC_MASTER:
1799 memcpy(&chip->chip.pic,
1800 &pic_irqchip(kvm)->pics[0],
1801 sizeof(struct kvm_pic_state));
1802 break;
1803 case KVM_IRQCHIP_PIC_SLAVE:
1804 memcpy(&chip->chip.pic,
1805 &pic_irqchip(kvm)->pics[1],
1806 sizeof(struct kvm_pic_state));
1807 break;
1808 case KVM_IRQCHIP_IOAPIC:
1809 memcpy(&chip->chip.ioapic,
1810 ioapic_irqchip(kvm),
1811 sizeof(struct kvm_ioapic_state));
1812 break;
1813 default:
1814 r = -EINVAL;
1815 break;
1816 }
1817 return r;
1818}
1819
1820static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1821{
1822 int r;
1823
1824 r = 0;
1825 switch (chip->chip_id) {
1826 case KVM_IRQCHIP_PIC_MASTER:
1827 memcpy(&pic_irqchip(kvm)->pics[0],
1828 &chip->chip.pic,
1829 sizeof(struct kvm_pic_state));
1830 break;
1831 case KVM_IRQCHIP_PIC_SLAVE:
1832 memcpy(&pic_irqchip(kvm)->pics[1],
1833 &chip->chip.pic,
1834 sizeof(struct kvm_pic_state));
1835 break;
1836 case KVM_IRQCHIP_IOAPIC:
1837 memcpy(ioapic_irqchip(kvm),
1838 &chip->chip.ioapic,
1839 sizeof(struct kvm_ioapic_state));
1840 break;
1841 default:
1842 r = -EINVAL;
1843 break;
1844 }
1845 kvm_pic_update_irq(pic_irqchip(kvm));
1846 return r;
1847}
1848
e0f63cb9
SY		 1849static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1850{
1851 int r = 0;
1852
1853 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1854 return r;
1855}
1856
1857static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1858{
1859 int r = 0;
1860
1861 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1862 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1863 return r;
1864}
1865
5bb064dc
ZX		 1866/*
1867 * Get (and clear) the dirty memory log for a memory slot.
1868 */
1869int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1870 struct kvm_dirty_log *log)
1871{
1872 int r;
1873 int n;
1874 struct kvm_memory_slot *memslot;
1875 int is_dirty = 0;
1876
72dc67a6 1877 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1878
1879 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1880 if (r)
1881 goto out;
1882
1883 /* If nothing is dirty, don't bother messing with page tables. */
1884 if (is_dirty) {
1885 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1886 kvm_flush_remote_tlbs(kvm);
1887 memslot = &kvm->memslots[log->slot];
1888 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1889 memset(memslot->dirty_bitmap, 0, n);
1890 }
1891 r = 0;
1892out:
72dc67a6 1893 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1894 return r;
1895}
1896
1fe779f8
CO		 1897long kvm_arch_vm_ioctl(struct file *filp,
1898 unsigned int ioctl, unsigned long arg)
1899{
1900 struct kvm *kvm = filp->private_data;
1901 void __user *argp = (void __user *)arg;
1902 int r = -EINVAL;
f0d66275
DH		 1903 /*
1904 * This union makes it completely explicit to gcc-3.x
1905 * that these two variables' stack usage should be
1906 * combined, not added together.
1907 */
1908 union {
1909 struct kvm_pit_state ps;
1910 struct kvm_memory_alias alias;
1911 } u;
1fe779f8
CO		 1912
1913 switch (ioctl) {
1914 case KVM_SET_TSS_ADDR:
1915 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1916 if (r < 0)
1917 goto out;
1918 break;
1919 case KVM_SET_MEMORY_REGION: {
1920 struct kvm_memory_region kvm_mem;
1921 struct kvm_userspace_memory_region kvm_userspace_mem;
1922
1923 r = -EFAULT;
1924 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1925 goto out;
1926 kvm_userspace_mem.slot = kvm_mem.slot;
1927 kvm_userspace_mem.flags = kvm_mem.flags;
1928 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1929 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1930 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1931 if (r)
1932 goto out;
1933 break;
1934 }
1935 case KVM_SET_NR_MMU_PAGES:
1936 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1937 if (r)
1938 goto out;
1939 break;
1940 case KVM_GET_NR_MMU_PAGES:
1941 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1942 break;
f0d66275 1943 case KVM_SET_MEMORY_ALIAS:
1fe779f8 1944 r = -EFAULT;
f0d66275 1945 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 1946 goto out;
f0d66275 1947 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 1948 if (r)
1949 goto out;
1950 break;
1fe779f8
CO		 1951 case KVM_CREATE_IRQCHIP:
1952 r = -ENOMEM;
d7deeeb0
ZX		 1953 kvm->arch.vpic = kvm_create_pic(kvm);
1954 if (kvm->arch.vpic) {
1fe779f8
CO		 1955 r = kvm_ioapic_init(kvm);
1956 if (r) {
d7deeeb0
ZX		 1957 kfree(kvm->arch.vpic);
1958 kvm->arch.vpic = NULL;
1fe779f8
CO		 1959 goto out;
1960 }
1961 } else
1962 goto out;
1963 break;
7837699f
SY		 1964 case KVM_CREATE_PIT:
1965 r = -ENOMEM;
1966 kvm->arch.vpit = kvm_create_pit(kvm);
1967 if (kvm->arch.vpit)
1968 r = 0;
1969 break;
1fe779f8
CO		 1970 case KVM_IRQ_LINE: {
1971 struct kvm_irq_level irq_event;
1972
1973 r = -EFAULT;
1974 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1975 goto out;
1976 if (irqchip_in_kernel(kvm)) {
1977 mutex_lock(&kvm->lock);
29c8fa32 1978 kvm_set_irq(kvm, irq_event.irq, irq_event.level);
1fe779f8
CO		 1979 mutex_unlock(&kvm->lock);
1980 r = 0;
1981 }
1982 break;
1983 }
1984 case KVM_GET_IRQCHIP: {
1985 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1986 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1987
f0d66275
DH		 1988 r = -ENOMEM;
1989 if (!chip)
1fe779f8 1990 goto out;
f0d66275
DH		 1991 r = -EFAULT;
1992 if (copy_from_user(chip, argp, sizeof *chip))
1993 goto get_irqchip_out;
1fe779f8
CO		 1994 r = -ENXIO;
1995 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1996 goto get_irqchip_out;
1997 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 1998 if (r)
f0d66275 1999 goto get_irqchip_out;
1fe779f8 2000 r = -EFAULT;
f0d66275
DH		 2001 if (copy_to_user(argp, chip, sizeof *chip))
2002 goto get_irqchip_out;
1fe779f8 2003 r = 0;
f0d66275
DH		 2004 get_irqchip_out:
2005 kfree(chip);
2006 if (r)
2007 goto out;
1fe779f8
CO		 2008 break;
2009 }
2010 case KVM_SET_IRQCHIP: {
2011 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2012 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2013
f0d66275
DH		 2014 r = -ENOMEM;
2015 if (!chip)
1fe779f8 2016 goto out;
f0d66275
DH		 2017 r = -EFAULT;
2018 if (copy_from_user(chip, argp, sizeof *chip))
2019 goto set_irqchip_out;
1fe779f8
CO		 2020 r = -ENXIO;
2021 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2022 goto set_irqchip_out;
2023 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2024 if (r)
f0d66275 2025 goto set_irqchip_out;
1fe779f8 2026 r = 0;
f0d66275
DH		 2027 set_irqchip_out:
2028 kfree(chip);
2029 if (r)
2030 goto out;
1fe779f8
CO		 2031 break;
2032 }
4d5c5d0f
BAY		 2033 case KVM_ASSIGN_PCI_DEVICE: {
2034 struct kvm_assigned_pci_dev assigned_dev;
2035
2036 r = -EFAULT;
2037 if (copy_from_user(&assigned_dev, argp, sizeof assigned_dev))
2038 goto out;
2039 r = kvm_vm_ioctl_assign_device(kvm, &assigned_dev);
2040 if (r)
2041 goto out;
2042 break;
2043 }
2044 case KVM_ASSIGN_IRQ: {
2045 struct kvm_assigned_irq assigned_irq;
2046
2047 r = -EFAULT;
2048 if (copy_from_user(&assigned_irq, argp, sizeof assigned_irq))
2049 goto out;
2050 r = kvm_vm_ioctl_assign_irq(kvm, &assigned_irq);
2051 if (r)
2052 goto out;
2053 break;
2054 }
e0f63cb9 2055 case KVM_GET_PIT: {
e0f63cb9 2056 r = -EFAULT;
f0d66275 2057 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2058 goto out;
2059 r = -ENXIO;
2060 if (!kvm->arch.vpit)
2061 goto out;
f0d66275 2062 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2063 if (r)
2064 goto out;
2065 r = -EFAULT;
f0d66275 2066 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2067 goto out;
2068 r = 0;
2069 break;
2070 }
2071 case KVM_SET_PIT: {
e0f63cb9 2072 r = -EFAULT;
f0d66275 2073 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2074 goto out;
2075 r = -ENXIO;
2076 if (!kvm->arch.vpit)
2077 goto out;
f0d66275 2078 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2079 if (r)
2080 goto out;
2081 r = 0;
2082 break;
2083 }
1fe779f8
CO		 2084 default:
2085 ;
2086 }
2087out:
2088 return r;
2089}
2090
a16b043c 2091static void kvm_init_msr_list(void)
043405e1
CO		 2092{
2093 u32 dummy[2];
2094 unsigned i, j;
2095
2096 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2097 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2098 continue;
2099 if (j < i)
2100 msrs_to_save[j] = msrs_to_save[i];
2101 j++;
2102 }
2103 num_msrs_to_save = j;
2104}
2105
bbd9b64e
CO		 2106/*
2107 * Only apic need an MMIO device hook, so shortcut now..
2108 */
2109static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2110 gpa_t addr, int len,
2111 int is_write)
bbd9b64e
CO		 2112{
2113 struct kvm_io_device *dev;
2114
ad312c7c
ZX		 2115 if (vcpu->arch.apic) {
2116 dev = &vcpu->arch.apic->dev;
92760499 2117 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 2118 return dev;
2119 }
2120 return NULL;
2121}
2122
2123
2124static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2125 gpa_t addr, int len,
2126 int is_write)
bbd9b64e
CO		 2127{
2128 struct kvm_io_device *dev;
2129
92760499 2130 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 2131 if (dev == NULL)
92760499
LV		 2132 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
2133 is_write);
bbd9b64e
CO		 2134 return dev;
2135}
2136
2137int emulator_read_std(unsigned long addr,
2138 void *val,
2139 unsigned int bytes,
2140 struct kvm_vcpu *vcpu)
2141{
2142 void *data = val;
10589a46 2143 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2144
2145 while (bytes) {
ad312c7c 2146 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2147 unsigned offset = addr & (PAGE_SIZE-1);
2148 unsigned tocopy = min(bytes, (unsigned)PAGE_SIZE - offset);
2149 int ret;
2150
10589a46
MT		 2151 if (gpa == UNMAPPED_GVA) {
2152 r = X86EMUL_PROPAGATE_FAULT;
2153 goto out;
2154 }
bbd9b64e 2155 ret = kvm_read_guest(vcpu->kvm, gpa, data, tocopy);
10589a46
MT		 2156 if (ret < 0) {
2157 r = X86EMUL_UNHANDLEABLE;
2158 goto out;
2159 }
bbd9b64e
CO		 2160
2161 bytes -= tocopy;
2162 data += tocopy;
2163 addr += tocopy;
2164 }
10589a46 2165out:
10589a46 2166 return r;
bbd9b64e
CO		 2167}
2168EXPORT_SYMBOL_GPL(emulator_read_std);
2169
bbd9b64e
CO		 2170static int emulator_read_emulated(unsigned long addr,
2171 void *val,
2172 unsigned int bytes,
2173 struct kvm_vcpu *vcpu)
2174{
2175 struct kvm_io_device *mmio_dev;
2176 gpa_t gpa;
2177
2178 if (vcpu->mmio_read_completed) {
2179 memcpy(val, vcpu->mmio_data, bytes);
2180 vcpu->mmio_read_completed = 0;
2181 return X86EMUL_CONTINUE;
2182 }
2183
ad312c7c 2184 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2185
2186 /* For APIC access vmexit */
2187 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2188 goto mmio;
2189
2190 if (emulator_read_std(addr, val, bytes, vcpu)
2191 == X86EMUL_CONTINUE)
2192 return X86EMUL_CONTINUE;
2193 if (gpa == UNMAPPED_GVA)
2194 return X86EMUL_PROPAGATE_FAULT;
2195
2196mmio:
2197 /*
2198 * Is this MMIO handled locally?
2199 */
10589a46 2200 mutex_lock(&vcpu->kvm->lock);
92760499 2201 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 2202 if (mmio_dev) {
2203 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 2204 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2205 return X86EMUL_CONTINUE;
2206 }
10589a46 2207 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2208
2209 vcpu->mmio_needed = 1;
2210 vcpu->mmio_phys_addr = gpa;
2211 vcpu->mmio_size = bytes;
2212 vcpu->mmio_is_write = 0;
2213
2214 return X86EMUL_UNHANDLEABLE;
2215}
2216
3200f405 2217int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2218 const void *val, int bytes)
bbd9b64e
CO		 2219{
2220 int ret;
2221
2222 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2223 if (ret < 0)
bbd9b64e
CO		 2224 return 0;
2225 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
2226 return 1;
2227}
2228
2229static int emulator_write_emulated_onepage(unsigned long addr,
2230 const void *val,
2231 unsigned int bytes,
2232 struct kvm_vcpu *vcpu)
2233{
2234 struct kvm_io_device *mmio_dev;
10589a46
MT		 2235 gpa_t gpa;
2236
10589a46 2237 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2238
2239 if (gpa == UNMAPPED_GVA) {
c3c91fee 2240 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2241 return X86EMUL_PROPAGATE_FAULT;
2242 }
2243
2244 /* For APIC access vmexit */
2245 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2246 goto mmio;
2247
2248 if (emulator_write_phys(vcpu, gpa, val, bytes))
2249 return X86EMUL_CONTINUE;
2250
2251mmio:
2252 /*
2253 * Is this MMIO handled locally?
2254 */
10589a46 2255 mutex_lock(&vcpu->kvm->lock);
92760499 2256 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 2257 if (mmio_dev) {
2258 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 2259 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2260 return X86EMUL_CONTINUE;
2261 }
10589a46 2262 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2263
2264 vcpu->mmio_needed = 1;
2265 vcpu->mmio_phys_addr = gpa;
2266 vcpu->mmio_size = bytes;
2267 vcpu->mmio_is_write = 1;
2268 memcpy(vcpu->mmio_data, val, bytes);
2269
2270 return X86EMUL_CONTINUE;
2271}
2272
2273int emulator_write_emulated(unsigned long addr,
2274 const void *val,
2275 unsigned int bytes,
2276 struct kvm_vcpu *vcpu)
2277{
2278 /* Crossing a page boundary? */
2279 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2280 int rc, now;
2281
2282 now = -addr & ~PAGE_MASK;
2283 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2284 if (rc != X86EMUL_CONTINUE)
2285 return rc;
2286 addr += now;
2287 val += now;
2288 bytes -= now;
2289 }
2290 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2291}
2292EXPORT_SYMBOL_GPL(emulator_write_emulated);
2293
2294static int emulator_cmpxchg_emulated(unsigned long addr,
2295 const void *old,
2296 const void *new,
2297 unsigned int bytes,
2298 struct kvm_vcpu *vcpu)
2299{
2300 static int reported;
2301
2302 if (!reported) {
2303 reported = 1;
2304 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2305 }
2bacc55c
MT		 2306#ifndef CONFIG_X86_64
2307 /* guests cmpxchg8b have to be emulated atomically */
2308 if (bytes == 8) {
10589a46 2309 gpa_t gpa;
2bacc55c 2310 struct page *page;
c0b49b0d 2311 char *kaddr;
2bacc55c
MT		 2312 u64 val;
2313
10589a46
MT		 2314 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2315
2bacc55c
MT		 2316 if (gpa == UNMAPPED_GVA ||
2317 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2318 goto emul_write;
2319
2320 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2321 goto emul_write;
2322
2323 val = *(u64 *)new;
72dc67a6 2324
2bacc55c 2325 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2326
c0b49b0d
AM		 2327 kaddr = kmap_atomic(page, KM_USER0);
2328 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2329 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2330 kvm_release_page_dirty(page);
2331 }
3200f405 2332emul_write:
2bacc55c
MT		 2333#endif
2334
bbd9b64e
CO		 2335 return emulator_write_emulated(addr, new, bytes, vcpu);
2336}
2337
2338static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2339{
2340 return kvm_x86_ops->get_segment_base(vcpu, seg);
2341}
2342
2343int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2344{
a7052897 2345 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2346 return X86EMUL_CONTINUE;
2347}
2348
2349int emulate_clts(struct kvm_vcpu *vcpu)
2350{
54e445ca 2351 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2352 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2353 return X86EMUL_CONTINUE;
2354}
2355
2356int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2357{
2358 struct kvm_vcpu *vcpu = ctxt->vcpu;
2359
2360 switch (dr) {
2361 case 0 ... 3:
2362 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2363 return X86EMUL_CONTINUE;
2364 default:
b8688d51 2365 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2366 return X86EMUL_UNHANDLEABLE;
2367 }
2368}
2369
2370int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2371{
2372 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2373 int exception;
2374
2375 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2376 if (exception) {
2377 /* FIXME: better handling */
2378 return X86EMUL_UNHANDLEABLE;
2379 }
2380 return X86EMUL_CONTINUE;
2381}
2382
2383void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2384{
bbd9b64e 2385 u8 opcodes[4];
5fdbf976 2386 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2387 unsigned long rip_linear;
2388
f76c710d 2389 if (!printk_ratelimit())
bbd9b64e
CO		 2390 return;
2391
25be4608
GC		 2392 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2393
bbd9b64e
CO		 2394 emulator_read_std(rip_linear, (void *)opcodes, 4, vcpu);
2395
2396 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2397 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2398}
2399EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2400
14af3f3c 2401static struct x86_emulate_ops emulate_ops = {
bbd9b64e 2402 .read_std = emulator_read_std,
bbd9b64e
CO		 2403 .read_emulated = emulator_read_emulated,
2404 .write_emulated = emulator_write_emulated,
2405 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2406};
2407
5fdbf976
MT		 2408static void cache_all_regs(struct kvm_vcpu *vcpu)
2409{
2410 kvm_register_read(vcpu, VCPU_REGS_RAX);
2411 kvm_register_read(vcpu, VCPU_REGS_RSP);
2412 kvm_register_read(vcpu, VCPU_REGS_RIP);
2413 vcpu->arch.regs_dirty = ~0;
2414}
2415
bbd9b64e
CO		 2416int emulate_instruction(struct kvm_vcpu *vcpu,
2417 struct kvm_run *run,
2418 unsigned long cr2,
2419 u16 error_code,
571008da 2420 int emulation_type)
bbd9b64e
CO		 2421{
2422 int r;
571008da 2423 struct decode_cache *c;
bbd9b64e 2424
26eef70c 2425 kvm_clear_exception_queue(vcpu);
ad312c7c 2426 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2427 /*
2428 * TODO: fix x86_emulate.c to use guest_read/write_register
2429 * instead of direct ->regs accesses, can save hundred cycles
2430 * on Intel for instructions that don't read/change RSP, for
2431 * for example.
2432 */
2433 cache_all_regs(vcpu);
bbd9b64e
CO		 2434
2435 vcpu->mmio_is_write = 0;
ad312c7c 2436 vcpu->arch.pio.string = 0;
bbd9b64e 2437
571008da 2438 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2439 int cs_db, cs_l;
2440 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2441
ad312c7c
ZX		 2442 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2443 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2444 vcpu->arch.emulate_ctxt.mode =
2445 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2446 ? X86EMUL_MODE_REAL : cs_l
2447 ? X86EMUL_MODE_PROT64 : cs_db
2448 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2449
ad312c7c 2450 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2451
2452 /* Reject the instructions other than VMCALL/VMMCALL when
2453 * try to emulate invalid opcode */
2454 c = &vcpu->arch.emulate_ctxt.decode;
2455 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2456 (!(c->twobyte && c->b == 0x01 &&
2457 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2458 c->modrm_mod == 3 && c->modrm_rm == 1)))
2459 return EMULATE_FAIL;
2460
f2b5756b 2461 ++vcpu->stat.insn_emulation;
bbd9b64e 2462 if (r) {
f2b5756b 2463 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2464 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2465 return EMULATE_DONE;
2466 return EMULATE_FAIL;
2467 }
2468 }
2469
ad312c7c 2470 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2471
ad312c7c 2472 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2473 return EMULATE_DO_MMIO;
2474
2475 if ((r || vcpu->mmio_is_write) && run) {
2476 run->exit_reason = KVM_EXIT_MMIO;
2477 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2478 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2479 run->mmio.len = vcpu->mmio_size;
2480 run->mmio.is_write = vcpu->mmio_is_write;
2481 }
2482
2483 if (r) {
2484 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2485 return EMULATE_DONE;
2486 if (!vcpu->mmio_needed) {
2487 kvm_report_emulation_failure(vcpu, "mmio");
2488 return EMULATE_FAIL;
2489 }
2490 return EMULATE_DO_MMIO;
2491 }
2492
ad312c7c 2493 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2494
2495 if (vcpu->mmio_is_write) {
2496 vcpu->mmio_needed = 0;
2497 return EMULATE_DO_MMIO;
2498 }
2499
2500 return EMULATE_DONE;
2501}
2502EXPORT_SYMBOL_GPL(emulate_instruction);
2503
de7d789a
CO		 2504static void free_pio_guest_pages(struct kvm_vcpu *vcpu)
2505{
2506 int i;
2507
ad312c7c
ZX		 2508 for (i = 0; i < ARRAY_SIZE(vcpu->arch.pio.guest_pages); ++i)
2509 if (vcpu->arch.pio.guest_pages[i]) {
2510 kvm_release_page_dirty(vcpu->arch.pio.guest_pages[i]);
2511 vcpu->arch.pio.guest_pages[i] = NULL;
de7d789a
CO		 2512 }
2513}
2514
2515static int pio_copy_data(struct kvm_vcpu *vcpu)
2516{
ad312c7c 2517 void *p = vcpu->arch.pio_data;
de7d789a
CO		 2518 void *q;
2519 unsigned bytes;
ad312c7c 2520 int nr_pages = vcpu->arch.pio.guest_pages[1] ? 2 : 1;
de7d789a 2521
ad312c7c 2522 q = vmap(vcpu->arch.pio.guest_pages, nr_pages, VM_READ|VM_WRITE,
de7d789a
CO		 2523 PAGE_KERNEL);
2524 if (!q) {
2525 free_pio_guest_pages(vcpu);
2526 return -ENOMEM;
2527 }
ad312c7c
ZX		 2528 q += vcpu->arch.pio.guest_page_offset;
2529 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2530 if (vcpu->arch.pio.in)
de7d789a
CO		 2531 memcpy(q, p, bytes);
2532 else
2533 memcpy(p, q, bytes);
ad312c7c 2534 q -= vcpu->arch.pio.guest_page_offset;
de7d789a
CO		 2535 vunmap(q);
2536 free_pio_guest_pages(vcpu);
2537 return 0;
2538}
2539
2540int complete_pio(struct kvm_vcpu *vcpu)
2541{
ad312c7c 2542 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2543 long delta;
2544 int r;
5fdbf976 2545 unsigned long val;
de7d789a
CO		 2546
2547 if (!io->string) {
5fdbf976
MT		 2548 if (io->in) {
2549 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2550 memcpy(&val, vcpu->arch.pio_data, io->size);
2551 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2552 }
de7d789a
CO		 2553 } else {
2554 if (io->in) {
2555 r = pio_copy_data(vcpu);
5fdbf976 2556 if (r)
de7d789a 2557 return r;
de7d789a
CO		 2558 }
2559
2560 delta = 1;
2561 if (io->rep) {
2562 delta *= io->cur_count;
2563 /*
2564 * The size of the register should really depend on
2565 * current address size.
2566 */
5fdbf976
MT		 2567 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2568 val -= delta;
2569 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2570 }
2571 if (io->down)
2572 delta = -delta;
2573 delta *= io->size;
5fdbf976
MT		 2574 if (io->in) {
2575 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2576 val += delta;
2577 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2578 } else {
2579 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2580 val += delta;
2581 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2582 }
de7d789a
CO		 2583 }
2584
de7d789a
CO		 2585 io->count -= io->cur_count;
2586 io->cur_count = 0;
2587
2588 return 0;
2589}
2590
2591static void kernel_pio(struct kvm_io_device *pio_dev,
2592 struct kvm_vcpu *vcpu,
2593 void *pd)
2594{
2595 /* TODO: String I/O for in kernel device */
2596
2597 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2598 if (vcpu->arch.pio.in)
2599 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2600 vcpu->arch.pio.size,
de7d789a
CO		 2601 pd);
2602 else
ad312c7c
ZX		 2603 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2604 vcpu->arch.pio.size,
de7d789a
CO		 2605 pd);
2606 mutex_unlock(&vcpu->kvm->lock);
2607}
2608
2609static void pio_string_write(struct kvm_io_device *pio_dev,
2610 struct kvm_vcpu *vcpu)
2611{
ad312c7c
ZX		 2612 struct kvm_pio_request *io = &vcpu->arch.pio;
2613 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2614 int i;
2615
2616 mutex_lock(&vcpu->kvm->lock);
2617 for (i = 0; i < io->cur_count; i++) {
2618 kvm_iodevice_write(pio_dev, io->port,
2619 io->size,
2620 pd);
2621 pd += io->size;
2622 }
2623 mutex_unlock(&vcpu->kvm->lock);
2624}
2625
2626static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2627 gpa_t addr, int len,
2628 int is_write)
de7d789a 2629{
92760499 2630 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2631}
2632
2633int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2634 int size, unsigned port)
2635{
2636 struct kvm_io_device *pio_dev;
5fdbf976 2637 unsigned long val;
de7d789a
CO		 2638
2639 vcpu->run->exit_reason = KVM_EXIT_IO;
2640 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2641 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2642 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2643 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2644 vcpu->run->io.port = vcpu->arch.pio.port = port;
2645 vcpu->arch.pio.in = in;
2646 vcpu->arch.pio.string = 0;
2647 vcpu->arch.pio.down = 0;
2648 vcpu->arch.pio.guest_page_offset = 0;
2649 vcpu->arch.pio.rep = 0;
de7d789a 2650
2714d1d3
FEL		 2651 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2652 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2653 handler);
2654 else
2655 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2656 handler);
2657
5fdbf976
MT		 2658 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2659 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a
CO		 2660
2661 kvm_x86_ops->skip_emulated_instruction(vcpu);
2662
92760499 2663 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2664 if (pio_dev) {
ad312c7c 2665 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2666 complete_pio(vcpu);
2667 return 1;
2668 }
2669 return 0;
2670}
2671EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2672
2673int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2674 int size, unsigned long count, int down,
2675 gva_t address, int rep, unsigned port)
2676{
2677 unsigned now, in_page;
2678 int i, ret = 0;
2679 int nr_pages = 1;
2680 struct page *page;
2681 struct kvm_io_device *pio_dev;
2682
2683 vcpu->run->exit_reason = KVM_EXIT_IO;
2684 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2685 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2686 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2687 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2688 vcpu->run->io.port = vcpu->arch.pio.port = port;
2689 vcpu->arch.pio.in = in;
2690 vcpu->arch.pio.string = 1;
2691 vcpu->arch.pio.down = down;
2692 vcpu->arch.pio.guest_page_offset = offset_in_page(address);
2693 vcpu->arch.pio.rep = rep;
de7d789a 2694
2714d1d3
FEL		 2695 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2696 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2697 handler);
2698 else
2699 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2700 handler);
2701
de7d789a
CO		 2702 if (!count) {
2703 kvm_x86_ops->skip_emulated_instruction(vcpu);
2704 return 1;
2705 }
2706
2707 if (!down)
2708 in_page = PAGE_SIZE - offset_in_page(address);
2709 else
2710 in_page = offset_in_page(address) + size;
2711 now = min(count, (unsigned long)in_page / size);
2712 if (!now) {
2713 /*
2714 * String I/O straddles page boundary. Pin two guest pages
2715 * so that we satisfy atomicity constraints. Do just one
2716 * transaction to avoid complexity.
2717 */
2718 nr_pages = 2;
2719 now = 1;
2720 }
2721 if (down) {
2722 /*
2723 * String I/O in reverse. Yuck. Kill the guest, fix later.
2724 */
2725 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2726 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2727 return 1;
2728 }
2729 vcpu->run->io.count = now;
ad312c7c 2730 vcpu->arch.pio.cur_count = now;
de7d789a 2731
ad312c7c 2732 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2733 kvm_x86_ops->skip_emulated_instruction(vcpu);
2734
2735 for (i = 0; i < nr_pages; ++i) {
de7d789a 2736 page = gva_to_page(vcpu, address + i * PAGE_SIZE);
ad312c7c 2737 vcpu->arch.pio.guest_pages[i] = page;
de7d789a 2738 if (!page) {
c1a5d4f9 2739 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2740 free_pio_guest_pages(vcpu);
2741 return 1;
2742 }
2743 }
2744
92760499
LV		 2745 pio_dev = vcpu_find_pio_dev(vcpu, port,
2746 vcpu->arch.pio.cur_count,
2747 !vcpu->arch.pio.in);
ad312c7c 2748 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2749 /* string PIO write */
2750 ret = pio_copy_data(vcpu);
2751 if (ret >= 0 && pio_dev) {
2752 pio_string_write(pio_dev, vcpu);
2753 complete_pio(vcpu);
ad312c7c 2754 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2755 ret = 1;
2756 }
2757 } else if (pio_dev)
2758 pr_unimpl(vcpu, "no string pio read support yet, "
2759 "port %x size %d count %ld\n",
2760 port, size, count);
2761
2762 return ret;
2763}
2764EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2765
f8c16bba 2766int kvm_arch_init(void *opaque)
043405e1 2767{
56c6d28a 2768 int r;
f8c16bba
ZX		 2769 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2770
f8c16bba
ZX		 2771 if (kvm_x86_ops) {
2772 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2773 r = -EEXIST;
2774 goto out;
f8c16bba
ZX		 2775 }
2776
2777 if (!ops->cpu_has_kvm_support()) {
2778 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2779 r = -EOPNOTSUPP;
2780 goto out;
f8c16bba
ZX		 2781 }
2782 if (ops->disabled_by_bios()) {
2783 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2784 r = -EOPNOTSUPP;
2785 goto out;
f8c16bba
ZX		 2786 }
2787
97db56ce
AK		 2788 r = kvm_mmu_module_init();
2789 if (r)
2790 goto out;
2791
2792 kvm_init_msr_list();
2793
f8c16bba 2794 kvm_x86_ops = ops;
56c6d28a 2795 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2796 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2797 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
2798 PT_DIRTY_MASK, PT64_NX_MASK, 0);
f8c16bba 2799 return 0;
56c6d28a
ZX		 2800
2801out:
56c6d28a 2802 return r;
043405e1 2803}
8776e519 2804
f8c16bba
ZX		 2805void kvm_arch_exit(void)
2806{
2807 kvm_x86_ops = NULL;
56c6d28a
ZX		 2808 kvm_mmu_module_exit();
2809}
f8c16bba 2810
8776e519
HB		 2811int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2812{
2813 ++vcpu->stat.halt_exits;
2714d1d3 2814 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2815 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2816 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 2817 return 1;
2818 } else {
2819 vcpu->run->exit_reason = KVM_EXIT_HLT;
2820 return 0;
2821 }
2822}
2823EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2824
2f333bcb
MT		 2825static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2826 unsigned long a1)
2827{
2828 if (is_long_mode(vcpu))
2829 return a0;
2830 else
2831 return a0 | ((gpa_t)a1 << 32);
2832}
2833
8776e519
HB		 2834int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2835{
2836 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2837 int r = 1;
8776e519 2838
5fdbf976
MT		 2839 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2840 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2841 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2842 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2843 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2844
2714d1d3
FEL		 2845 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2846
8776e519
HB		 2847 if (!is_long_mode(vcpu)) {
2848 nr &= 0xFFFFFFFF;
2849 a0 &= 0xFFFFFFFF;
2850 a1 &= 0xFFFFFFFF;
2851 a2 &= 0xFFFFFFFF;
2852 a3 &= 0xFFFFFFFF;
2853 }
2854
2855 switch (nr) {
b93463aa
AK		 2856 case KVM_HC_VAPIC_POLL_IRQ:
2857 ret = 0;
2858 break;
2f333bcb
MT		 2859 case KVM_HC_MMU_OP:
2860 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2861 break;
8776e519
HB		 2862 default:
2863 ret = -KVM_ENOSYS;
2864 break;
2865 }
5fdbf976 2866 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2867 ++vcpu->stat.hypercalls;
2f333bcb 2868 return r;
8776e519
HB		 2869}
2870EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2871
2872int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2873{
2874 char instruction[3];
2875 int ret = 0;
5fdbf976 2876 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2877
8776e519
HB		 2878
2879 /*
2880 * Blow out the MMU to ensure that no other VCPU has an active mapping
2881 * to ensure that the updated hypercall appears atomically across all
2882 * VCPUs.
2883 */
2884 kvm_mmu_zap_all(vcpu->kvm);
2885
8776e519 2886 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2887 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2888 != X86EMUL_CONTINUE)
2889 ret = -EFAULT;
2890
8776e519
HB		 2891 return ret;
2892}
2893
2894static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2895{
2896 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2897}
2898
2899void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2900{
2901 struct descriptor_table dt = { limit, base };
2902
2903 kvm_x86_ops->set_gdt(vcpu, &dt);
2904}
2905
2906void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2907{
2908 struct descriptor_table dt = { limit, base };
2909
2910 kvm_x86_ops->set_idt(vcpu, &dt);
2911}
2912
2913void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2914 unsigned long *rflags)
2915{
2d3ad1f4 2916 kvm_lmsw(vcpu, msw);
8776e519
HB		 2917 *rflags = kvm_x86_ops->get_rflags(vcpu);
2918}
2919
2920unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2921{
54e445ca
JR		 2922 unsigned long value;
2923
8776e519
HB		 2924 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2925 switch (cr) {
2926 case 0:
54e445ca
JR		 2927 value = vcpu->arch.cr0;
2928 break;
8776e519 2929 case 2:
54e445ca
JR		 2930 value = vcpu->arch.cr2;
2931 break;
8776e519 2932 case 3:
54e445ca
JR		 2933 value = vcpu->arch.cr3;
2934 break;
8776e519 2935 case 4:
54e445ca
JR		 2936 value = vcpu->arch.cr4;
2937 break;
152ff9be 2938 case 8:
54e445ca
JR		 2939 value = kvm_get_cr8(vcpu);
2940 break;
8776e519 2941 default:
b8688d51 2942 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2943 return 0;
2944 }
54e445ca
JR		 2945 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2946 (u32)((u64)value >> 32), handler);
2947
2948 return value;
8776e519
HB		 2949}
2950
2951void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2952 unsigned long *rflags)
2953{
54e445ca
JR		 2954 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2955 (u32)((u64)val >> 32), handler);
2956
8776e519
HB		 2957 switch (cr) {
2958 case 0:
2d3ad1f4 2959 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2960 *rflags = kvm_x86_ops->get_rflags(vcpu);
2961 break;
2962 case 2:
ad312c7c 2963 vcpu->arch.cr2 = val;
8776e519
HB		 2964 break;
2965 case 3:
2d3ad1f4 2966 kvm_set_cr3(vcpu, val);
8776e519
HB		 2967 break;
2968 case 4:
2d3ad1f4 2969 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2970 break;
152ff9be 2971 case 8:
2d3ad1f4 2972 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2973 break;
8776e519 2974 default:
b8688d51 2975 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2976 }
2977}
2978
07716717
DK		 2979static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2980{
ad312c7c
ZX		 2981 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2982 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2983
2984 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2985 /* when no next entry is found, the current entry[i] is reselected */
2986 for (j = i + 1; j == i; j = (j + 1) % nent) {
ad312c7c 2987 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2988 if (ej->function == e->function) {
2989 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2990 return j;
2991 }
2992 }
2993 return 0; /* silence gcc, even though control never reaches here */
2994}
2995
2996/* find an entry with matching function, matching index (if needed), and that
2997 * should be read next (if it's stateful) */
2998static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2999 u32 function, u32 index)
3000{
3001 if (e->function != function)
3002 return 0;
3003 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3004 return 0;
3005 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
3006 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
3007 return 0;
3008 return 1;
3009}
3010
8776e519
HB		 3011void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3012{
3013 int i;
07716717
DK		 3014 u32 function, index;
3015 struct kvm_cpuid_entry2 *e, *best;
8776e519 3016
5fdbf976
MT		 3017 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3018 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3019 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3020 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3021 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3022 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
8776e519 3023 best = NULL;
ad312c7c
ZX		 3024 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
3025 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3026 if (is_matching_cpuid_entry(e, function, index)) {
3027 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3028 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3029 best = e;
3030 break;
3031 }
3032 /*
3033 * Both basic or both extended?
3034 */
3035 if (((e->function ^ function) & 0x80000000) == 0)
3036 if (!best || e->function > best->function)
3037 best = e;
3038 }
3039 if (best) {
5fdbf976
MT		 3040 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3041 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3042 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3043 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3044 }
8776e519 3045 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 3046 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 3047 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
3048 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
3049 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
3050 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 3051}
3052EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3053
b6c7a5dc
HB		 3054/*
3055 * Check if userspace requested an interrupt window, and that the
3056 * interrupt window is open.
3057 *
3058 * No need to exit to userspace if we already have an interrupt queued.
3059 */
3060static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3061 struct kvm_run *kvm_run)
3062{
ad312c7c 3063 return (!vcpu->arch.irq_summary &&
b6c7a5dc 3064 kvm_run->request_interrupt_window &&
ad312c7c 3065 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 3066 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
3067}
3068
3069static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3070 struct kvm_run *kvm_run)
3071{
3072 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3073 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc
HB		 3074 kvm_run->apic_base = kvm_get_apic_base(vcpu);
3075 if (irqchip_in_kernel(vcpu->kvm))
3076 kvm_run->ready_for_interrupt_injection = 1;
3077 else
3078 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 3079 (vcpu->arch.interrupt_window_open &&
3080 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 3081}
3082
b93463aa
AK		 3083static void vapic_enter(struct kvm_vcpu *vcpu)
3084{
3085 struct kvm_lapic *apic = vcpu->arch.apic;
3086 struct page *page;
3087
3088 if (!apic || !apic->vapic_addr)
3089 return;
3090
3091 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3092
3093 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3094}
3095
3096static void vapic_exit(struct kvm_vcpu *vcpu)
3097{
3098 struct kvm_lapic *apic = vcpu->arch.apic;
3099
3100 if (!apic || !apic->vapic_addr)
3101 return;
3102
f8b78fa3 3103 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3104 kvm_release_page_dirty(apic->vapic_page);
3105 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3106 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3107}
3108
d7690175 3109static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3110{
3111 int r;
3112
2e53d63a
MT		 3113 if (vcpu->requests)
3114 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3115 kvm_mmu_unload(vcpu);
3116
b6c7a5dc
HB		 3117 r = kvm_mmu_reload(vcpu);
3118 if (unlikely(r))
3119 goto out;
3120
2f52d58c
AK		 3121 if (vcpu->requests) {
3122 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3123 __kvm_migrate_timers(vcpu);
4731d4c7
MT		 3124 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3125 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3126 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3127 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3128 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3129 &vcpu->requests)) {
3130 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3131 r = 0;
3132 goto out;
3133 }
71c4dfaf
JR		 3134 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3135 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3136 r = 0;
3137 goto out;
3138 }
2f52d58c 3139 }
b93463aa 3140
06e05645 3141 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 3142 kvm_inject_pending_timer_irqs(vcpu);
3143
3144 preempt_disable();
3145
3146 kvm_x86_ops->prepare_guest_switch(vcpu);
3147 kvm_load_guest_fpu(vcpu);
3148
3149 local_irq_disable();
3150
d7690175 3151 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3152 local_irq_enable();
3153 preempt_enable();
3154 r = 1;
3155 goto out;
3156 }
3157
29415c37
MT		 3158 if (vcpu->guest_debug.enabled)
3159 kvm_x86_ops->guest_debug_pre(vcpu);
3160
e9571ed5
MT		 3161 vcpu->guest_mode = 1;
3162 /*
3163 * Make sure that guest_mode assignment won't happen after
3164 * testing the pending IRQ vector bitmap.
3165 */
3166 smp_wmb();
3167
ad312c7c 3168 if (vcpu->arch.exception.pending)
298101da
AK		 3169 __queue_exception(vcpu);
3170 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3171 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 3172 else
b6c7a5dc
HB		 3173 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
3174
b93463aa
AK		 3175 kvm_lapic_sync_to_vapic(vcpu);
3176
3200f405
MT		 3177 up_read(&vcpu->kvm->slots_lock);
3178
b6c7a5dc
HB		 3179 kvm_guest_enter();
3180
b6c7a5dc 3181
2714d1d3 3182 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3183 kvm_x86_ops->run(vcpu, kvm_run);
3184
3185 vcpu->guest_mode = 0;
3186 local_irq_enable();
3187
3188 ++vcpu->stat.exits;
3189
3190 /*
3191 * We must have an instruction between local_irq_enable() and
3192 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3193 * the interrupt shadow. The stat.exits increment will do nicely.
3194 * But we need to prevent reordering, hence this barrier():
3195 */
3196 barrier();
3197
3198 kvm_guest_exit();
3199
3200 preempt_enable();
3201
3200f405
MT		 3202 down_read(&vcpu->kvm->slots_lock);
3203
b6c7a5dc
HB		 3204 /*
3205 * Profile KVM exit RIPs:
3206 */
3207 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3208 unsigned long rip = kvm_rip_read(vcpu);
3209 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3210 }
3211
ad312c7c
ZX		 3212 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
3213 vcpu->arch.exception.pending = false;
298101da 3214
b93463aa
AK		 3215 kvm_lapic_sync_from_vapic(vcpu);
3216
b6c7a5dc 3217 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3218out:
3219 return r;
3220}
b6c7a5dc 3221
d7690175
MT		 3222static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3223{
3224 int r;
3225
3226 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
3227 printk("vcpu %d received sipi with vector # %x\n",
3228 vcpu->vcpu_id, vcpu->arch.sipi_vector);
3229 kvm_lapic_reset(vcpu);
3230 r = kvm_x86_ops->vcpu_reset(vcpu);
3231 if (r)
3232 return r;
3233 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3234 }
3235
d7690175
MT		 3236 down_read(&vcpu->kvm->slots_lock);
3237 vapic_enter(vcpu);
3238
3239 r = 1;
3240 while (r > 0) {
af2152f5 3241 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3242 r = vcpu_enter_guest(vcpu, kvm_run);
3243 else {
3244 up_read(&vcpu->kvm->slots_lock);
3245 kvm_vcpu_block(vcpu);
3246 down_read(&vcpu->kvm->slots_lock);
3247 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3248 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
3249 vcpu->arch.mp_state =
3250 KVM_MP_STATE_RUNNABLE;
3251 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
3252 r = -EINTR;
3253 }
3254
3255 if (r > 0) {
3256 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3257 r = -EINTR;
3258 kvm_run->exit_reason = KVM_EXIT_INTR;
3259 ++vcpu->stat.request_irq_exits;
3260 }
3261 if (signal_pending(current)) {
3262 r = -EINTR;
3263 kvm_run->exit_reason = KVM_EXIT_INTR;
3264 ++vcpu->stat.signal_exits;
3265 }
3266 if (need_resched()) {
3267 up_read(&vcpu->kvm->slots_lock);
3268 kvm_resched(vcpu);
3269 down_read(&vcpu->kvm->slots_lock);
3270 }
3271 }
b6c7a5dc
HB		 3272 }
3273
d7690175 3274 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3275 post_kvm_run_save(vcpu, kvm_run);
3276
b93463aa
AK		 3277 vapic_exit(vcpu);
3278
b6c7a5dc
HB		 3279 return r;
3280}
3281
3282int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3283{
3284 int r;
3285 sigset_t sigsaved;
3286
3287 vcpu_load(vcpu);
3288
ac9f6dc0
AK		 3289 if (vcpu->sigset_active)
3290 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3291
a4535290 3292 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3293 kvm_vcpu_block(vcpu);
d7690175 3294 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3295 r = -EAGAIN;
3296 goto out;
b6c7a5dc
HB		 3297 }
3298
b6c7a5dc
HB		 3299 /* re-sync apic's tpr */
3300 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3301 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3302
ad312c7c 3303 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3304 r = complete_pio(vcpu);
3305 if (r)
3306 goto out;
3307 }
3308#if CONFIG_HAS_IOMEM
3309 if (vcpu->mmio_needed) {
3310 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3311 vcpu->mmio_read_completed = 1;
3312 vcpu->mmio_needed = 0;
3200f405
MT		 3313
3314 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3315 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3316 vcpu->arch.mmio_fault_cr2, 0,
3317 EMULTYPE_NO_DECODE);
3200f405 3318 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3319 if (r == EMULATE_DO_MMIO) {
3320 /*
3321 * Read-modify-write. Back to userspace.
3322 */
3323 r = 0;
3324 goto out;
3325 }
3326 }
3327#endif
5fdbf976
MT		 3328 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3329 kvm_register_write(vcpu, VCPU_REGS_RAX,
3330 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3331
3332 r = __vcpu_run(vcpu, kvm_run);
3333
3334out:
3335 if (vcpu->sigset_active)
3336 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3337
3338 vcpu_put(vcpu);
3339 return r;
3340}
3341
3342int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3343{
3344 vcpu_load(vcpu);
3345
5fdbf976
MT		 3346 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3347 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3348 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3349 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3350 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3351 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3352 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3353 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3354#ifdef CONFIG_X86_64
5fdbf976
MT		 3355 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3356 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3357 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3358 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3359 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3360 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3361 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3362 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3363#endif
3364
5fdbf976 3365 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3366 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3367
3368 /*
3369 * Don't leak debug flags in case they were set for guest debugging
3370 */
3371 if (vcpu->guest_debug.enabled && vcpu->guest_debug.singlestep)
3372 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3373
3374 vcpu_put(vcpu);
3375
3376 return 0;
3377}
3378
3379int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3380{
3381 vcpu_load(vcpu);
3382
5fdbf976
MT		 3383 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3384 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3385 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3386 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3387 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3388 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3389 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3390 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3391#ifdef CONFIG_X86_64
5fdbf976
MT		 3392 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3393 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3394 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3395 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3396 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3397 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3398 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3399 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3400
b6c7a5dc
HB		 3401#endif
3402
5fdbf976 3403 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3404 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3405
b6c7a5dc 3406
b4f14abd
JK		 3407 vcpu->arch.exception.pending = false;
3408
b6c7a5dc
HB		 3409 vcpu_put(vcpu);
3410
3411 return 0;
3412}
3413
3e6e0aab
GT		 3414void kvm_get_segment(struct kvm_vcpu *vcpu,
3415 struct kvm_segment *var, int seg)
b6c7a5dc 3416{
14af3f3c 3417 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3418}
3419
3420void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3421{
3422 struct kvm_segment cs;
3423
3e6e0aab 3424 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3425 *db = cs.db;
3426 *l = cs.l;
3427}
3428EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3429
3430int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3431 struct kvm_sregs *sregs)
3432{
3433 struct descriptor_table dt;
3434 int pending_vec;
3435
3436 vcpu_load(vcpu);
3437
3e6e0aab
GT		 3438 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3439 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3440 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3441 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3442 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3443 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3444
3e6e0aab
GT		 3445 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3446 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3447
3448 kvm_x86_ops->get_idt(vcpu, &dt);
3449 sregs->idt.limit = dt.limit;
3450 sregs->idt.base = dt.base;
3451 kvm_x86_ops->get_gdt(vcpu, &dt);
3452 sregs->gdt.limit = dt.limit;
3453 sregs->gdt.base = dt.base;
3454
3455 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3456 sregs->cr0 = vcpu->arch.cr0;
3457 sregs->cr2 = vcpu->arch.cr2;
3458 sregs->cr3 = vcpu->arch.cr3;
3459 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3460 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3461 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3462 sregs->apic_base = kvm_get_apic_base(vcpu);
3463
3464 if (irqchip_in_kernel(vcpu->kvm)) {
3465 memset(sregs->interrupt_bitmap, 0,
3466 sizeof sregs->interrupt_bitmap);
3467 pending_vec = kvm_x86_ops->get_irq(vcpu);
3468 if (pending_vec >= 0)
3469 set_bit(pending_vec,
3470 (unsigned long *)sregs->interrupt_bitmap);
3471 } else
ad312c7c 3472 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3473 sizeof sregs->interrupt_bitmap);
3474
3475 vcpu_put(vcpu);
3476
3477 return 0;
3478}
3479
62d9f0db
MT		 3480int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3481 struct kvm_mp_state *mp_state)
3482{
3483 vcpu_load(vcpu);
3484 mp_state->mp_state = vcpu->arch.mp_state;
3485 vcpu_put(vcpu);
3486 return 0;
3487}
3488
3489int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3490 struct kvm_mp_state *mp_state)
3491{
3492 vcpu_load(vcpu);
3493 vcpu->arch.mp_state = mp_state->mp_state;
3494 vcpu_put(vcpu);
3495 return 0;
3496}
3497
3e6e0aab 3498static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3499 struct kvm_segment *var, int seg)
3500{
14af3f3c 3501 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3502}
3503
37817f29
IE		 3504static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3505 struct kvm_segment *kvm_desct)
3506{
3507 kvm_desct->base = seg_desc->base0;
3508 kvm_desct->base |= seg_desc->base1 << 16;
3509 kvm_desct->base |= seg_desc->base2 << 24;
3510 kvm_desct->limit = seg_desc->limit0;
3511 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3512 if (seg_desc->g) {
3513 kvm_desct->limit <<= 12;
3514 kvm_desct->limit |= 0xfff;
3515 }
37817f29
IE		 3516 kvm_desct->selector = selector;
3517 kvm_desct->type = seg_desc->type;
3518 kvm_desct->present = seg_desc->p;
3519 kvm_desct->dpl = seg_desc->dpl;
3520 kvm_desct->db = seg_desc->d;
3521 kvm_desct->s = seg_desc->s;
3522 kvm_desct->l = seg_desc->l;
3523 kvm_desct->g = seg_desc->g;
3524 kvm_desct->avl = seg_desc->avl;
3525 if (!selector)
3526 kvm_desct->unusable = 1;
3527 else
3528 kvm_desct->unusable = 0;
3529 kvm_desct->padding = 0;
3530}
3531
3532static void get_segment_descritptor_dtable(struct kvm_vcpu *vcpu,
3533 u16 selector,
3534 struct descriptor_table *dtable)
3535{
3536 if (selector & 1 << 2) {
3537 struct kvm_segment kvm_seg;
3538
3e6e0aab 3539 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3540
3541 if (kvm_seg.unusable)
3542 dtable->limit = 0;
3543 else
3544 dtable->limit = kvm_seg.limit;
3545 dtable->base = kvm_seg.base;
3546 }
3547 else
3548 kvm_x86_ops->get_gdt(vcpu, dtable);
3549}
3550
3551/* allowed just for 8 bytes segments */
3552static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3553 struct desc_struct *seg_desc)
3554{
98899aa0 3555 gpa_t gpa;
37817f29
IE		 3556 struct descriptor_table dtable;
3557 u16 index = selector >> 3;
3558
3559 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3560
3561 if (dtable.limit < index * 8 + 7) {
3562 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3563 return 1;
3564 }
98899aa0
MT		 3565 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3566 gpa += index * 8;
3567 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3568}
3569
3570/* allowed just for 8 bytes segments */
3571static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3572 struct desc_struct *seg_desc)
3573{
98899aa0 3574 gpa_t gpa;
37817f29
IE		 3575 struct descriptor_table dtable;
3576 u16 index = selector >> 3;
3577
3578 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3579
3580 if (dtable.limit < index * 8 + 7)
3581 return 1;
98899aa0
MT		 3582 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3583 gpa += index * 8;
3584 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3585}
3586
3587static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3588 struct desc_struct *seg_desc)
3589{
3590 u32 base_addr;
3591
3592 base_addr = seg_desc->base0;
3593 base_addr |= (seg_desc->base1 << 16);
3594 base_addr |= (seg_desc->base2 << 24);
3595
98899aa0 3596 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3597}
3598
37817f29
IE		 3599static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3600{
3601 struct kvm_segment kvm_seg;
3602
3e6e0aab 3603 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3604 return kvm_seg.selector;
3605}
3606
3607static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3608 u16 selector,
3609 struct kvm_segment *kvm_seg)
3610{
3611 struct desc_struct seg_desc;
3612
3613 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3614 return 1;
3615 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3616 return 0;
3617}
3618
2259e3a7 3619static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3620{
3621 struct kvm_segment segvar = {
3622 .base = selector << 4,
3623 .limit = 0xffff,
3624 .selector = selector,
3625 .type = 3,
3626 .present = 1,
3627 .dpl = 3,
3628 .db = 0,
3629 .s = 1,
3630 .l = 0,
3631 .g = 0,
3632 .avl = 0,
3633 .unusable = 0,
3634 };
3635 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3636 return 0;
3637}
3638
3e6e0aab
GT		 3639int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3640 int type_bits, int seg)
37817f29
IE		 3641{
3642 struct kvm_segment kvm_seg;
3643
f4bbd9aa
AK		 3644 if (!(vcpu->arch.cr0 & X86_CR0_PE))
3645 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 3646 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3647 return 1;
3648 kvm_seg.type |= type_bits;
3649
3650 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3651 seg != VCPU_SREG_LDTR)
3652 if (!kvm_seg.s)
3653 kvm_seg.unusable = 1;
3654
3e6e0aab 3655 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3656 return 0;
3657}
3658
3659static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3660 struct tss_segment_32 *tss)
3661{
3662 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3663 tss->eip = kvm_rip_read(vcpu);
37817f29 3664 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3665 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3666 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3667 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3668 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3669 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3670 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3671 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3672 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3673 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3674 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3675 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3676 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3677 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3678 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3679 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3680 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3681}
3682
3683static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3684 struct tss_segment_32 *tss)
3685{
3686 kvm_set_cr3(vcpu, tss->cr3);
3687
5fdbf976 3688 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3689 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3690
5fdbf976
MT		 3691 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3692 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3693 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3694 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3695 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3696 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3697 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3698 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3699
3e6e0aab 3700 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3701 return 1;
3702
3e6e0aab 3703 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3704 return 1;
3705
3e6e0aab 3706 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3707 return 1;
3708
3e6e0aab 3709 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3710 return 1;
3711
3e6e0aab 3712 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3713 return 1;
3714
3e6e0aab 3715 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3716 return 1;
3717
3e6e0aab 3718 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3719 return 1;
3720 return 0;
3721}
3722
3723static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3724 struct tss_segment_16 *tss)
3725{
5fdbf976 3726 tss->ip = kvm_rip_read(vcpu);
37817f29 3727 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3728 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3729 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3730 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3731 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3732 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3733 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3734 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3735 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3736
3737 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3738 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3739 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3740 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3741 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3742 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3743}
3744
3745static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3746 struct tss_segment_16 *tss)
3747{
5fdbf976 3748 kvm_rip_write(vcpu, tss->ip);
37817f29 3749 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3750 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3751 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3752 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3753 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3754 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3755 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3756 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3757 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3758
3e6e0aab 3759 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3760 return 1;
3761
3e6e0aab 3762 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3763 return 1;
3764
3e6e0aab 3765 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3766 return 1;
3767
3e6e0aab 3768 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3769 return 1;
3770
3e6e0aab 3771 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3772 return 1;
3773 return 0;
3774}
3775
8b2cf73c 3776static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3777 u32 old_tss_base,
37817f29
IE		 3778 struct desc_struct *nseg_desc)
3779{
3780 struct tss_segment_16 tss_segment_16;
3781 int ret = 0;
3782
34198bf8
MT		 3783 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3784 sizeof tss_segment_16))
37817f29
IE		 3785 goto out;
3786
3787 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3788
34198bf8
MT		 3789 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3790 sizeof tss_segment_16))
37817f29 3791 goto out;
34198bf8
MT		 3792
3793 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3794 &tss_segment_16, sizeof tss_segment_16))
3795 goto out;
3796
37817f29
IE		 3797 if (load_state_from_tss16(vcpu, &tss_segment_16))
3798 goto out;
3799
3800 ret = 1;
3801out:
3802 return ret;
3803}
3804
8b2cf73c 3805static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3806 u32 old_tss_base,
37817f29
IE		 3807 struct desc_struct *nseg_desc)
3808{
3809 struct tss_segment_32 tss_segment_32;
3810 int ret = 0;
3811
34198bf8
MT		 3812 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3813 sizeof tss_segment_32))
37817f29
IE		 3814 goto out;
3815
3816 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3817
34198bf8
MT		 3818 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3819 sizeof tss_segment_32))
3820 goto out;
3821
3822 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3823 &tss_segment_32, sizeof tss_segment_32))
37817f29 3824 goto out;
34198bf8 3825
37817f29
IE		 3826 if (load_state_from_tss32(vcpu, &tss_segment_32))
3827 goto out;
3828
3829 ret = 1;
3830out:
3831 return ret;
3832}
3833
3834int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3835{
3836 struct kvm_segment tr_seg;
3837 struct desc_struct cseg_desc;
3838 struct desc_struct nseg_desc;
3839 int ret = 0;
34198bf8
MT		 3840 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3841 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3842
34198bf8 3843 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3844
34198bf8
MT		 3845 /* FIXME: Handle errors. Failure to read either TSS or their
3846 * descriptors should generate a pagefault.
3847 */
37817f29
IE		 3848 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3849 goto out;
3850
34198bf8 3851 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3852 goto out;
3853
37817f29
IE		 3854 if (reason != TASK_SWITCH_IRET) {
3855 int cpl;
3856
3857 cpl = kvm_x86_ops->get_cpl(vcpu);
3858 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3859 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3860 return 1;
3861 }
3862 }
3863
3864 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3865 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3866 return 1;
3867 }
3868
3869 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3870 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3871 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3872 }
3873
3874 if (reason == TASK_SWITCH_IRET) {
3875 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3876 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3877 }
3878
3879 kvm_x86_ops->skip_emulated_instruction(vcpu);
37817f29
IE		 3880
3881 if (nseg_desc.type & 8)
34198bf8 3882 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3883 &nseg_desc);
3884 else
34198bf8 3885 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3886 &nseg_desc);
3887
3888 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3889 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3890 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3891 }
3892
3893 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3894 nseg_desc.type |= (1 << 1);
37817f29
IE		 3895 save_guest_segment_descriptor(vcpu, tss_selector,
3896 &nseg_desc);
3897 }
3898
3899 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3900 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3901 tr_seg.type = 11;
3e6e0aab 3902 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 3903out:
37817f29
IE		 3904 return ret;
3905}
3906EXPORT_SYMBOL_GPL(kvm_task_switch);
3907
b6c7a5dc
HB		 3908int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3909 struct kvm_sregs *sregs)
3910{
3911 int mmu_reset_needed = 0;
3912 int i, pending_vec, max_bits;
3913 struct descriptor_table dt;
3914
3915 vcpu_load(vcpu);
3916
3917 dt.limit = sregs->idt.limit;
3918 dt.base = sregs->idt.base;
3919 kvm_x86_ops->set_idt(vcpu, &dt);
3920 dt.limit = sregs->gdt.limit;
3921 dt.base = sregs->gdt.base;
3922 kvm_x86_ops->set_gdt(vcpu, &dt);
3923
ad312c7c
ZX		 3924 vcpu->arch.cr2 = sregs->cr2;
3925 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3926 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3927
2d3ad1f4 3928 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3929
ad312c7c 3930 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3931 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3932 kvm_set_apic_base(vcpu, sregs->apic_base);
3933
3934 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3935
ad312c7c 3936 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3937 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3938 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3939
ad312c7c 3940 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3941 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3942 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3943 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3944
3945 if (mmu_reset_needed)
3946 kvm_mmu_reset_context(vcpu);
3947
3948 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3949 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3950 sizeof vcpu->arch.irq_pending);
3951 vcpu->arch.irq_summary = 0;
3952 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3953 if (vcpu->arch.irq_pending[i])
3954 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3955 } else {
3956 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3957 pending_vec = find_first_bit(
3958 (const unsigned long *)sregs->interrupt_bitmap,
3959 max_bits);
3960 /* Only pending external irq is handled here */
3961 if (pending_vec < max_bits) {
3962 kvm_x86_ops->set_irq(vcpu, pending_vec);
3963 pr_debug("Set back pending irq %d\n",
3964 pending_vec);
3965 }
3966 }
3967
3e6e0aab
GT		 3968 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3969 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3970 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3971 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3972 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3973 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3974
3e6e0aab
GT		 3975 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3976 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 3977
9c3e4aab
MT		 3978 /* Older userspace won't unhalt the vcpu on reset. */
3979 if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
3980 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3981 !(vcpu->arch.cr0 & X86_CR0_PE))
3982 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3983
b6c7a5dc
HB		 3984 vcpu_put(vcpu);
3985
3986 return 0;
3987}
3988
3989int kvm_arch_vcpu_ioctl_debug_guest(struct kvm_vcpu *vcpu,
3990 struct kvm_debug_guest *dbg)
3991{
3992 int r;
3993
3994 vcpu_load(vcpu);
3995
3996 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3997
3998 vcpu_put(vcpu);
3999
4000 return r;
4001}
4002
d0752060
HB		 4003/*
4004 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4005 * we have asm/x86/processor.h
4006 */
4007struct fxsave {
4008 u16 cwd;
4009 u16 swd;
4010 u16 twd;
4011 u16 fop;
4012 u64 rip;
4013 u64 rdp;
4014 u32 mxcsr;
4015 u32 mxcsr_mask;
4016 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4017#ifdef CONFIG_X86_64
4018 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4019#else
4020 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4021#endif
4022};
4023
8b006791
ZX		 4024/*
4025 * Translate a guest virtual address to a guest physical address.
4026 */
4027int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4028 struct kvm_translation *tr)
4029{
4030 unsigned long vaddr = tr->linear_address;
4031 gpa_t gpa;
4032
4033 vcpu_load(vcpu);
72dc67a6 4034 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4035 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4036 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4037 tr->physical_address = gpa;
4038 tr->valid = gpa != UNMAPPED_GVA;
4039 tr->writeable = 1;
4040 tr->usermode = 0;
8b006791
ZX		 4041 vcpu_put(vcpu);
4042
4043 return 0;
4044}
4045
d0752060
HB		 4046int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4047{
ad312c7c 4048 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4049
4050 vcpu_load(vcpu);
4051
4052 memcpy(fpu->fpr, fxsave->st_space, 128);
4053 fpu->fcw = fxsave->cwd;
4054 fpu->fsw = fxsave->swd;
4055 fpu->ftwx = fxsave->twd;
4056 fpu->last_opcode = fxsave->fop;
4057 fpu->last_ip = fxsave->rip;
4058 fpu->last_dp = fxsave->rdp;
4059 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4060
4061 vcpu_put(vcpu);
4062
4063 return 0;
4064}
4065
4066int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4067{
ad312c7c 4068 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4069
4070 vcpu_load(vcpu);
4071
4072 memcpy(fxsave->st_space, fpu->fpr, 128);
4073 fxsave->cwd = fpu->fcw;
4074 fxsave->swd = fpu->fsw;
4075 fxsave->twd = fpu->ftwx;
4076 fxsave->fop = fpu->last_opcode;
4077 fxsave->rip = fpu->last_ip;
4078 fxsave->rdp = fpu->last_dp;
4079 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4080
4081 vcpu_put(vcpu);
4082
4083 return 0;
4084}
4085
4086void fx_init(struct kvm_vcpu *vcpu)
4087{
4088 unsigned after_mxcsr_mask;
4089
bc1a34f1
AA		 4090 /*
4091 * Touch the fpu the first time in non atomic context as if
4092 * this is the first fpu instruction the exception handler
4093 * will fire before the instruction returns and it'll have to
4094 * allocate ram with GFP_KERNEL.
4095 */
4096 if (!used_math())
d6e88aec 4097 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4098
d0752060
HB		 4099 /* Initialize guest FPU by resetting ours and saving into guest's */
4100 preempt_disable();
d6e88aec
AK		 4101 kvm_fx_save(&vcpu->arch.host_fx_image);
4102 kvm_fx_finit();
4103 kvm_fx_save(&vcpu->arch.guest_fx_image);
4104 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4105 preempt_enable();
4106
ad312c7c 4107 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4108 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4109 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4110 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4111 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4112}
4113EXPORT_SYMBOL_GPL(fx_init);
4114
4115void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4116{
4117 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4118 return;
4119
4120 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4121 kvm_fx_save(&vcpu->arch.host_fx_image);
4122 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4123}
4124EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4125
4126void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4127{
4128 if (!vcpu->guest_fpu_loaded)
4129 return;
4130
4131 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4132 kvm_fx_save(&vcpu->arch.guest_fx_image);
4133 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4134 ++vcpu->stat.fpu_reload;
d0752060
HB		 4135}
4136EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4137
4138void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4139{
4140 kvm_x86_ops->vcpu_free(vcpu);
4141}
4142
4143struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4144 unsigned int id)
4145{
26e5215f
AK		 4146 return kvm_x86_ops->vcpu_create(kvm, id);
4147}
e9b11c17 4148
26e5215f
AK		 4149int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4150{
4151 int r;
e9b11c17
ZX		 4152
4153 /* We do fxsave: this must be aligned. */
ad312c7c 4154 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17
ZX		 4155
4156 vcpu_load(vcpu);
4157 r = kvm_arch_vcpu_reset(vcpu);
4158 if (r == 0)
4159 r = kvm_mmu_setup(vcpu);
4160 vcpu_put(vcpu);
4161 if (r < 0)
4162 goto free_vcpu;
4163
26e5215f 4164 return 0;
e9b11c17
ZX		 4165free_vcpu:
4166 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4167 return r;
e9b11c17
ZX		 4168}
4169
d40ccc62 4170void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4171{
4172 vcpu_load(vcpu);
4173 kvm_mmu_unload(vcpu);
4174 vcpu_put(vcpu);
4175
4176 kvm_x86_ops->vcpu_free(vcpu);
4177}
4178
4179int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4180{
4181 return kvm_x86_ops->vcpu_reset(vcpu);
4182}
4183
4184void kvm_arch_hardware_enable(void *garbage)
4185{
4186 kvm_x86_ops->hardware_enable(garbage);
4187}
4188
4189void kvm_arch_hardware_disable(void *garbage)
4190{
4191 kvm_x86_ops->hardware_disable(garbage);
4192}
4193
4194int kvm_arch_hardware_setup(void)
4195{
4196 return kvm_x86_ops->hardware_setup();
4197}
4198
4199void kvm_arch_hardware_unsetup(void)
4200{
4201 kvm_x86_ops->hardware_unsetup();
4202}
4203
4204void kvm_arch_check_processor_compat(void *rtn)
4205{
4206 kvm_x86_ops->check_processor_compatibility(rtn);
4207}
4208
4209int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4210{
4211 struct page *page;
4212 struct kvm *kvm;
4213 int r;
4214
4215 BUG_ON(vcpu->kvm == NULL);
4216 kvm = vcpu->kvm;
4217
ad312c7c 4218 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 4219 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 4220 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4221 else
a4535290 4222 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4223
4224 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4225 if (!page) {
4226 r = -ENOMEM;
4227 goto fail;
4228 }
ad312c7c 4229 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4230
4231 r = kvm_mmu_create(vcpu);
4232 if (r < 0)
4233 goto fail_free_pio_data;
4234
4235 if (irqchip_in_kernel(kvm)) {
4236 r = kvm_create_lapic(vcpu);
4237 if (r < 0)
4238 goto fail_mmu_destroy;
4239 }
4240
4241 return 0;
4242
4243fail_mmu_destroy:
4244 kvm_mmu_destroy(vcpu);
4245fail_free_pio_data:
ad312c7c 4246 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4247fail:
4248 return r;
4249}
4250
4251void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4252{
4253 kvm_free_lapic(vcpu);
3200f405 4254 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4255 kvm_mmu_destroy(vcpu);
3200f405 4256 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4257 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4258}
d19a9cd2
ZX		 4259
4260struct kvm *kvm_arch_create_vm(void)
4261{
4262 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4263
4264 if (!kvm)
4265 return ERR_PTR(-ENOMEM);
4266
f05e70ac 4267 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4268 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2
ZX		 4269
4270 return kvm;
4271}
4272
4273static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4274{
4275 vcpu_load(vcpu);
4276 kvm_mmu_unload(vcpu);
4277 vcpu_put(vcpu);
4278}
4279
4280static void kvm_free_vcpus(struct kvm *kvm)
4281{
4282 unsigned int i;
4283
4284 /*
4285 * Unpin any mmu pages first.
4286 */
4287 for (i = 0; i < KVM_MAX_VCPUS; ++i)
4288 if (kvm->vcpus[i])
4289 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
4290 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
4291 if (kvm->vcpus[i]) {
4292 kvm_arch_vcpu_free(kvm->vcpus[i]);
4293 kvm->vcpus[i] = NULL;
4294 }
4295 }
4296
4297}
4298
4299void kvm_arch_destroy_vm(struct kvm *kvm)
4300{
62c476c7 4301 kvm_iommu_unmap_guest(kvm);
bfadaded 4302 kvm_free_all_assigned_devices(kvm);
7837699f 4303 kvm_free_pit(kvm);
d7deeeb0
ZX		 4304 kfree(kvm->arch.vpic);
4305 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4306 kvm_free_vcpus(kvm);
4307 kvm_free_physmem(kvm);
3d45830c
AK		 4308 if (kvm->arch.apic_access_page)
4309 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4310 if (kvm->arch.ept_identity_pagetable)
4311 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4312 kfree(kvm);
4313}
0de10343
ZX		 4314
4315int kvm_arch_set_memory_region(struct kvm *kvm,
4316 struct kvm_userspace_memory_region *mem,
4317 struct kvm_memory_slot old,
4318 int user_alloc)
4319{
4320 int npages = mem->memory_size >> PAGE_SHIFT;
4321 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4322
4323 /*To keep backward compatibility with older userspace,
4324 *x86 needs to hanlde !user_alloc case.
4325 */
4326 if (!user_alloc) {
4327 if (npages && !old.rmap) {
604b38ac
AA		 4328 unsigned long userspace_addr;
4329
72dc67a6 4330 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4331 userspace_addr = do_mmap(NULL, 0,
4332 npages * PAGE_SIZE,
4333 PROT_READ | PROT_WRITE,
acee3c04 4334 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4335 0);
72dc67a6 4336 up_write(&current->mm->mmap_sem);
0de10343 4337
604b38ac
AA		 4338 if (IS_ERR((void *)userspace_addr))
4339 return PTR_ERR((void *)userspace_addr);
4340
4341 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4342 spin_lock(&kvm->mmu_lock);
4343 memslot->userspace_addr = userspace_addr;
4344 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4345 } else {
4346 if (!old.user_alloc && old.rmap) {
4347 int ret;
4348
72dc67a6 4349 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4350 ret = do_munmap(current->mm, old.userspace_addr,
4351 old.npages * PAGE_SIZE);
72dc67a6 4352 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4353 if (ret < 0)
4354 printk(KERN_WARNING
4355 "kvm_vm_ioctl_set_memory_region: "
4356 "failed to munmap memory\n");
4357 }
4358 }
4359 }
4360
f05e70ac 4361 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4362 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4363 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4364 }
4365
4366 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4367 kvm_flush_remote_tlbs(kvm);
4368
4369 return 0;
4370}
1d737c8a 4371
34d4cb8f
MT		 4372void kvm_arch_flush_shadow(struct kvm *kvm)
4373{
4374 kvm_mmu_zap_all(kvm);
4375}
4376
1d737c8a
ZX		 4377int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4378{
a4535290
AK		 4379 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
4380 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED;
1d737c8a 4381}
5736199a
ZX		 4382
4383static void vcpu_kick_intr(void *info)
4384{
4385#ifdef DEBUG
4386 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4387 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4388#endif
4389}
4390
4391void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4392{
4393 int ipi_pcpu = vcpu->cpu;
e9571ed5 4394 int cpu = get_cpu();
5736199a
ZX		 4395
4396 if (waitqueue_active(&vcpu->wq)) {
4397 wake_up_interruptible(&vcpu->wq);
4398 ++vcpu->stat.halt_wakeup;
4399 }
e9571ed5
MT		 4400 /*
4401 * We may be called synchronously with irqs disabled in guest mode,
4402 * So need not to call smp_call_function_single() in that case.
4403 */
4404 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4405 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4406 put_cpu();
5736199a 4407}
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