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kvm: x86: Add exception payload fields to kvm_vcpu_events
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
3b8a5df6 139unsigned int __read_mostly lapic_timer_advance_ns = 1000;
d0659d94 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 141EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 142
52004014
FW		 143static bool __read_mostly vector_hashing = true;
144module_param(vector_hashing, bool, S_IRUGO);
145
c4ae60e4
LA		 146bool __read_mostly enable_vmware_backdoor = false;
147module_param(enable_vmware_backdoor, bool, S_IRUGO);
148EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149
6c86eedc
WL		 150static bool __read_mostly force_emulation_prefix = false;
151module_param(force_emulation_prefix, bool, S_IRUGO);
152
18863bdd
AK		 153#define KVM_NR_SHARED_MSRS 16
154
155struct kvm_shared_msrs_global {
156 int nr;
2bf78fa7 157 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 158};
159
160struct kvm_shared_msrs {
161 struct user_return_notifier urn;
162 bool registered;
2bf78fa7
SY		 163 struct kvm_shared_msr_values {
164 u64 host;
165 u64 curr;
166 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 167};
168
169static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 170static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 171
417bc304 172struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 183 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 188 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 195 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 196 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 197 { "req_event", VCPU_STAT(req_event) },
c595ceee 198 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 199 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
200 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
201 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
202 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
203 { "mmu_flooded", VM_STAT(mmu_flooded) },
204 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 205 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 206 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 207 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 208 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 209 { "max_mmu_page_hash_collisions",
210 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 211 { NULL }
212};
213
2acf923e
DC		 214u64 __read_mostly host_xcr0;
215
b6785def 216static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 217
af585b92
GN		 218static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
219{
220 int i;
221 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
222 vcpu->arch.apf.gfns[i] = ~0;
223}
224
18863bdd
AK		 225static void kvm_on_user_return(struct user_return_notifier *urn)
226{
227 unsigned slot;
18863bdd
AK		 228 struct kvm_shared_msrs *locals
229 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 230 struct kvm_shared_msr_values *values;
1650b4eb
IA		 231 unsigned long flags;
232
233 /*
234 * Disabling irqs at this point since the following code could be
235 * interrupted and executed through kvm_arch_hardware_disable()
236 */
237 local_irq_save(flags);
238 if (locals->registered) {
239 locals->registered = false;
240 user_return_notifier_unregister(urn);
241 }
242 local_irq_restore(flags);
18863bdd 243 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 244 values = &locals->values[slot];
245 if (values->host != values->curr) {
246 wrmsrl(shared_msrs_global.msrs[slot], values->host);
247 values->curr = values->host;
18863bdd
AK		 248 }
249 }
18863bdd
AK		 250}
251
2bf78fa7 252static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 253{
18863bdd 254 u64 value;
013f6a5d
MT		 255 unsigned int cpu = smp_processor_id();
256 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 257
2bf78fa7
SY		 258 /* only read, and nobody should modify it at this time,
259 * so don't need lock */
260 if (slot >= shared_msrs_global.nr) {
261 printk(KERN_ERR "kvm: invalid MSR slot!");
262 return;
263 }
264 rdmsrl_safe(msr, &value);
265 smsr->values[slot].host = value;
266 smsr->values[slot].curr = value;
267}
268
269void kvm_define_shared_msr(unsigned slot, u32 msr)
270{
0123be42 271 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 272 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 273 if (slot >= shared_msrs_global.nr)
274 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 275}
276EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
277
278static void kvm_shared_msr_cpu_online(void)
279{
280 unsigned i;
18863bdd
AK		 281
282 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 283 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 284}
285
8b3c3104 286int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 287{
013f6a5d
MT		 288 unsigned int cpu = smp_processor_id();
289 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 290 int err;
18863bdd 291
2bf78fa7 292 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 293 return 0;
2bf78fa7 294 smsr->values[slot].curr = value;
8b3c3104
AH		 295 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
296 if (err)
297 return 1;
298
18863bdd
AK		 299 if (!smsr->registered) {
300 smsr->urn.on_user_return = kvm_on_user_return;
301 user_return_notifier_register(&smsr->urn);
302 smsr->registered = true;
303 }
8b3c3104 304 return 0;
18863bdd
AK		 305}
306EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
307
13a34e06 308static void drop_user_return_notifiers(void)
3548bab5 309{
013f6a5d
MT		 310 unsigned int cpu = smp_processor_id();
311 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 312
313 if (smsr->registered)
314 kvm_on_user_return(&smsr->urn);
315}
316
6866b83e
CO		 317u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
318{
8a5a87d9 319 return vcpu->arch.apic_base;
6866b83e
CO		 320}
321EXPORT_SYMBOL_GPL(kvm_get_apic_base);
322
58871649
JM		 323enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
324{
325 return kvm_apic_mode(kvm_get_apic_base(vcpu));
326}
327EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
328
58cb628d
JK		 329int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
330{
58871649
JM		 331 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
332 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 333 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
334 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 335
58871649 336 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 337 return 1;
58871649
JM		 338 if (!msr_info->host_initiated) {
339 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
340 return 1;
341 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
342 return 1;
343 }
58cb628d
JK		 344
345 kvm_lapic_set_base(vcpu, msr_info->data);
346 return 0;
6866b83e
CO		 347}
348EXPORT_SYMBOL_GPL(kvm_set_apic_base);
349
2605fc21 350asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 351{
352 /* Fault while not rebooting. We want the trace. */
353 BUG();
354}
355EXPORT_SYMBOL_GPL(kvm_spurious_fault);
356
3fd28fce
ED		 357#define EXCPT_BENIGN 0
358#define EXCPT_CONTRIBUTORY 1
359#define EXCPT_PF 2
360
361static int exception_class(int vector)
362{
363 switch (vector) {
364 case PF_VECTOR:
365 return EXCPT_PF;
366 case DE_VECTOR:
367 case TS_VECTOR:
368 case NP_VECTOR:
369 case SS_VECTOR:
370 case GP_VECTOR:
371 return EXCPT_CONTRIBUTORY;
372 default:
373 break;
374 }
375 return EXCPT_BENIGN;
376}
377
d6e8c854
NA		 378#define EXCPT_FAULT 0
379#define EXCPT_TRAP 1
380#define EXCPT_ABORT 2
381#define EXCPT_INTERRUPT 3
382
383static int exception_type(int vector)
384{
385 unsigned int mask;
386
387 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
388 return EXCPT_INTERRUPT;
389
390 mask = 1 << vector;
391
392 /* #DB is trap, as instruction watchpoints are handled elsewhere */
393 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
394 return EXCPT_TRAP;
395
396 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
397 return EXCPT_ABORT;
398
399 /* Reserved exceptions will result in fault */
400 return EXCPT_FAULT;
401}
402
3fd28fce 403static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 404 unsigned nr, bool has_error, u32 error_code,
405 bool reinject)
3fd28fce
ED		 406{
407 u32 prev_nr;
408 int class1, class2;
409
3842d135
AK		 410 kvm_make_request(KVM_REQ_EVENT, vcpu);
411
664f8e26 412 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 413 queue:
3ffb2468
NA		 414 if (has_error && !is_protmode(vcpu))
415 has_error = false;
664f8e26
WL		 416 if (reinject) {
417 /*
418 * On vmentry, vcpu->arch.exception.pending is only
419 * true if an event injection was blocked by
420 * nested_run_pending. In that case, however,
421 * vcpu_enter_guest requests an immediate exit,
422 * and the guest shouldn't proceed far enough to
423 * need reinjection.
424 */
425 WARN_ON_ONCE(vcpu->arch.exception.pending);
426 vcpu->arch.exception.injected = true;
427 } else {
428 vcpu->arch.exception.pending = true;
429 vcpu->arch.exception.injected = false;
430 }
3fd28fce
ED		 431 vcpu->arch.exception.has_error_code = has_error;
432 vcpu->arch.exception.nr = nr;
433 vcpu->arch.exception.error_code = error_code;
c851436a
JM		 434 vcpu->arch.exception.has_payload = false;
435 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 436 return;
437 }
438
439 /* to check exception */
440 prev_nr = vcpu->arch.exception.nr;
441 if (prev_nr == DF_VECTOR) {
442 /* triple fault -> shutdown */
a8eeb04a 443 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 444 return;
445 }
446 class1 = exception_class(prev_nr);
447 class2 = exception_class(nr);
448 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
449 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 450 /*
451 * Generate double fault per SDM Table 5-5. Set
452 * exception.pending = true so that the double fault
453 * can trigger a nested vmexit.
454 */
3fd28fce 455 vcpu->arch.exception.pending = true;
664f8e26 456 vcpu->arch.exception.injected = false;
3fd28fce
ED		 457 vcpu->arch.exception.has_error_code = true;
458 vcpu->arch.exception.nr = DF_VECTOR;
459 vcpu->arch.exception.error_code = 0;
c851436a
JM		 460 vcpu->arch.exception.has_payload = false;
461 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 462 } else
463 /* replace previous exception with a new one in a hope
464 that instruction re-execution will regenerate lost
465 exception */
466 goto queue;
467}
468
298101da
AK		 469void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
470{
ce7ddec4 471 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 472}
473EXPORT_SYMBOL_GPL(kvm_queue_exception);
474
ce7ddec4
JR		 475void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
476{
477 kvm_multiple_exception(vcpu, nr, false, 0, true);
478}
479EXPORT_SYMBOL_GPL(kvm_requeue_exception);
480
6affcbed 481int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 482{
db8fcefa
AP		 483 if (err)
484 kvm_inject_gp(vcpu, 0);
485 else
6affcbed
KH		 486 return kvm_skip_emulated_instruction(vcpu);
487
488 return 1;
db8fcefa
AP		 489}
490EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 491
6389ee94 492void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 493{
494 ++vcpu->stat.pf_guest;
adfe20fb
WL		 495 vcpu->arch.exception.nested_apf =
496 is_guest_mode(vcpu) && fault->async_page_fault;
497 if (vcpu->arch.exception.nested_apf)
498 vcpu->arch.apf.nested_apf_token = fault->address;
499 else
500 vcpu->arch.cr2 = fault->address;
6389ee94 501 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 502}
27d6c865 503EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 504
ef54bcfe 505static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 506{
6389ee94
AK		 507 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
508 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 509 else
44dd3ffa 510 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 511
512 return fault->nested_page_fault;
d4f8cf66
JR		 513}
514
3419ffc8
SY		 515void kvm_inject_nmi(struct kvm_vcpu *vcpu)
516{
7460fb4a
AK		 517 atomic_inc(&vcpu->arch.nmi_queued);
518 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 519}
520EXPORT_SYMBOL_GPL(kvm_inject_nmi);
521
298101da
AK		 522void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
523{
ce7ddec4 524 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 525}
526EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
527
ce7ddec4
JR		 528void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
529{
530 kvm_multiple_exception(vcpu, nr, true, error_code, true);
531}
532EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
533
0a79b009
AK		 534/*
535 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
536 * a #GP and return false.
537 */
538bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 539{
0a79b009
AK		 540 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
541 return true;
542 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
543 return false;
298101da 544}
0a79b009 545EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 546
16f8a6f9
NA		 547bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
548{
549 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
550 return true;
551
552 kvm_queue_exception(vcpu, UD_VECTOR);
553 return false;
554}
555EXPORT_SYMBOL_GPL(kvm_require_dr);
556
ec92fe44
JR		 557/*
558 * This function will be used to read from the physical memory of the currently
54bf36aa 559 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 560 * can read from guest physical or from the guest's guest physical memory.
561 */
562int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
563 gfn_t ngfn, void *data, int offset, int len,
564 u32 access)
565{
54987b7a 566 struct x86_exception exception;
ec92fe44
JR		 567 gfn_t real_gfn;
568 gpa_t ngpa;
569
570 ngpa = gfn_to_gpa(ngfn);
54987b7a 571 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 572 if (real_gfn == UNMAPPED_GVA)
573 return -EFAULT;
574
575 real_gfn = gpa_to_gfn(real_gfn);
576
54bf36aa 577 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 578}
579EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
580
69b0049a 581static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 582 void *data, int offset, int len, u32 access)
583{
584 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
585 data, offset, len, access);
586}
587
a03490ed
CO		 588/*
589 * Load the pae pdptrs. Return true is they are all valid.
590 */
ff03a073 591int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 592{
593 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
594 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
595 int i;
596 int ret;
ff03a073 597 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 598
ff03a073
JR		 599 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
600 offset * sizeof(u64), sizeof(pdpte),
601 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 602 if (ret < 0) {
603 ret = 0;
604 goto out;
605 }
606 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 607 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 608 (pdpte[i] &
44dd3ffa 609 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 610 ret = 0;
611 goto out;
612 }
613 }
614 ret = 1;
615
ff03a073 616 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 617 __set_bit(VCPU_EXREG_PDPTR,
618 (unsigned long *)&vcpu->arch.regs_avail);
619 __set_bit(VCPU_EXREG_PDPTR,
620 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 621out:
a03490ed
CO		 622
623 return ret;
624}
cc4b6871 625EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 626
9ed38ffa 627bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 628{
ff03a073 629 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 630 bool changed = true;
3d06b8bf
JR		 631 int offset;
632 gfn_t gfn;
d835dfec
AK		 633 int r;
634
d35b34a9 635 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
d835dfec
AK		 636 return false;
637
6de4f3ad
AK		 638 if (!test_bit(VCPU_EXREG_PDPTR,
639 (unsigned long *)&vcpu->arch.regs_avail))
640 return true;
641
a512177e
PB		 642 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
643 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 644 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
645 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 646 if (r < 0)
647 goto out;
ff03a073 648 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 649out:
d835dfec
AK		 650
651 return changed;
652}
9ed38ffa 653EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 654
49a9b07e 655int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 656{
aad82703 657 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 658 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 659
f9a48e6a
AK		 660 cr0 |= X86_CR0_ET;
661
ab344828 662#ifdef CONFIG_X86_64
0f12244f
GN		 663 if (cr0 & 0xffffffff00000000UL)
664 return 1;
ab344828
GN		 665#endif
666
667 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 668
0f12244f
GN		 669 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
670 return 1;
a03490ed 671
0f12244f
GN		 672 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
673 return 1;
a03490ed
CO		 674
675 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
676#ifdef CONFIG_X86_64
f6801dff 677 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 678 int cs_db, cs_l;
679
0f12244f
GN		 680 if (!is_pae(vcpu))
681 return 1;
a03490ed 682 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 683 if (cs_l)
684 return 1;
a03490ed
CO		 685 } else
686#endif
ff03a073 687 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 688 kvm_read_cr3(vcpu)))
0f12244f 689 return 1;
a03490ed
CO		 690 }
691
ad756a16
MJ		 692 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
693 return 1;
694
a03490ed 695 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 696
d170c419 697 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 698 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 699 kvm_async_pf_hash_reset(vcpu);
700 }
e5f3f027 701
aad82703
SY		 702 if ((cr0 ^ old_cr0) & update_bits)
703 kvm_mmu_reset_context(vcpu);
b18d5431 704
879ae188
LE		 705 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
706 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
707 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 708 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
709
0f12244f
GN		 710 return 0;
711}
2d3ad1f4 712EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 713
2d3ad1f4 714void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 715{
49a9b07e 716 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 717}
2d3ad1f4 718EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 719
42bdf991
MT		 720static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
721{
722 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
723 !vcpu->guest_xcr0_loaded) {
724 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 725 if (vcpu->arch.xcr0 != host_xcr0)
726 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 727 vcpu->guest_xcr0_loaded = 1;
728 }
729}
730
731static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
732{
733 if (vcpu->guest_xcr0_loaded) {
734 if (vcpu->arch.xcr0 != host_xcr0)
735 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
736 vcpu->guest_xcr0_loaded = 0;
737 }
738}
739
69b0049a 740static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 741{
56c103ec
LJ		 742 u64 xcr0 = xcr;
743 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 744 u64 valid_bits;
2acf923e
DC		 745
746 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
747 if (index != XCR_XFEATURE_ENABLED_MASK)
748 return 1;
d91cab78 749 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 750 return 1;
d91cab78 751 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 752 return 1;
46c34cb0
PB		 753
754 /*
755 * Do not allow the guest to set bits that we do not support
756 * saving. However, xcr0 bit 0 is always set, even if the
757 * emulated CPU does not support XSAVE (see fx_init).
758 */
d91cab78 759 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 760 if (xcr0 & ~valid_bits)
2acf923e 761 return 1;
46c34cb0 762
d91cab78
DH		 763 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
764 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 765 return 1;
766
d91cab78
DH		 767 if (xcr0 & XFEATURE_MASK_AVX512) {
768 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 769 return 1;
d91cab78 770 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 771 return 1;
772 }
2acf923e 773 vcpu->arch.xcr0 = xcr0;
56c103ec 774
d91cab78 775 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 776 kvm_update_cpuid(vcpu);
2acf923e
DC		 777 return 0;
778}
779
780int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
781{
764bcbc5
Z		 782 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
783 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 784 kvm_inject_gp(vcpu, 0);
785 return 1;
786 }
787 return 0;
788}
789EXPORT_SYMBOL_GPL(kvm_set_xcr);
790
a83b29c6 791int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 792{
fc78f519 793 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 794 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 795 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 796
0f12244f
GN		 797 if (cr4 & CR4_RESERVED_BITS)
798 return 1;
a03490ed 799
d6321d49 800 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 801 return 1;
802
d6321d49 803 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 804 return 1;
805
d6321d49 806 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 807 return 1;
808
d6321d49 809 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 810 return 1;
811
d6321d49 812 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 813 return 1;
814
fd8cb433 815 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 816 return 1;
817
ae3e61e1
PB		 818 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
819 return 1;
820
a03490ed 821 if (is_long_mode(vcpu)) {
0f12244f
GN		 822 if (!(cr4 & X86_CR4_PAE))
823 return 1;
a2edf57f
AK		 824 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
825 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 826 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
827 kvm_read_cr3(vcpu)))
0f12244f
GN		 828 return 1;
829
ad756a16 830 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 831 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 832 return 1;
833
834 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
835 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
836 return 1;
837 }
838
5e1746d6 839 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 840 return 1;
a03490ed 841
ad756a16
MJ		 842 if (((cr4 ^ old_cr4) & pdptr_bits) ||
843 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 844 kvm_mmu_reset_context(vcpu);
0f12244f 845
b9baba86 846 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 847 kvm_update_cpuid(vcpu);
2acf923e 848
0f12244f
GN		 849 return 0;
850}
2d3ad1f4 851EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 852
2390218b 853int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 854{
ade61e28 855 bool skip_tlb_flush = false;
ac146235 856#ifdef CONFIG_X86_64
c19986fe
JS		 857 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
858
ade61e28 859 if (pcid_enabled) {
208320ba
JS		 860 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
861 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 862 }
ac146235 863#endif
9d88fca7 864
9f8fe504 865 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 866 if (!skip_tlb_flush) {
867 kvm_mmu_sync_roots(vcpu);
ade61e28 868 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 869 }
0f12244f 870 return 0;
d835dfec
AK		 871 }
872
d1cd3ce9 873 if (is_long_mode(vcpu) &&
a780a3ea 874 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 875 return 1;
876 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 877 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 878 return 1;
a03490ed 879
ade61e28 880 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 881 vcpu->arch.cr3 = cr3;
aff48baa 882 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 883
0f12244f
GN		 884 return 0;
885}
2d3ad1f4 886EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 887
eea1cff9 888int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 889{
0f12244f
GN		 890 if (cr8 & CR8_RESERVED_BITS)
891 return 1;
35754c98 892 if (lapic_in_kernel(vcpu))
a03490ed
CO		 893 kvm_lapic_set_tpr(vcpu, cr8);
894 else
ad312c7c 895 vcpu->arch.cr8 = cr8;
0f12244f
GN		 896 return 0;
897}
2d3ad1f4 898EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 899
2d3ad1f4 900unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 901{
35754c98 902 if (lapic_in_kernel(vcpu))
a03490ed
CO		 903 return kvm_lapic_get_cr8(vcpu);
904 else
ad312c7c 905 return vcpu->arch.cr8;
a03490ed 906}
2d3ad1f4 907EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 908
ae561ede
NA		 909static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
910{
911 int i;
912
913 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
914 for (i = 0; i < KVM_NR_DB_REGS; i++)
915 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
916 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
917 }
918}
919
73aaf249
JK		 920static void kvm_update_dr6(struct kvm_vcpu *vcpu)
921{
922 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
923 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
924}
925
c8639010
JK		 926static void kvm_update_dr7(struct kvm_vcpu *vcpu)
927{
928 unsigned long dr7;
929
930 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
931 dr7 = vcpu->arch.guest_debug_dr7;
932 else
933 dr7 = vcpu->arch.dr7;
934 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 935 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
936 if (dr7 & DR7_BP_EN_MASK)
937 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 938}
939
6f43ed01
NA		 940static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
941{
942 u64 fixed = DR6_FIXED_1;
943
d6321d49 944 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 945 fixed |= DR6_RTM;
946 return fixed;
947}
948
338dbc97 949static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 950{
951 switch (dr) {
952 case 0 ... 3:
953 vcpu->arch.db[dr] = val;
954 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
955 vcpu->arch.eff_db[dr] = val;
956 break;
957 case 4:
020df079
GN		 958 /* fall through */
959 case 6:
338dbc97
GN		 960 if (val & 0xffffffff00000000ULL)
961 return -1; /* #GP */
6f43ed01 962 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 963 kvm_update_dr6(vcpu);
020df079
GN		 964 break;
965 case 5:
020df079
GN		 966 /* fall through */
967 default: /* 7 */
338dbc97
GN		 968 if (val & 0xffffffff00000000ULL)
969 return -1; /* #GP */
020df079 970 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 971 kvm_update_dr7(vcpu);
020df079
GN		 972 break;
973 }
974
975 return 0;
976}
338dbc97
GN		 977
978int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
979{
16f8a6f9 980 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 981 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 982 return 1;
983 }
984 return 0;
338dbc97 985}
020df079
GN		 986EXPORT_SYMBOL_GPL(kvm_set_dr);
987
16f8a6f9 988int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 989{
990 switch (dr) {
991 case 0 ... 3:
992 *val = vcpu->arch.db[dr];
993 break;
994 case 4:
020df079
GN		 995 /* fall through */
996 case 6:
73aaf249
JK		 997 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
998 *val = vcpu->arch.dr6;
999 else
1000 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1001 break;
1002 case 5:
020df079
GN		 1003 /* fall through */
1004 default: /* 7 */
1005 *val = vcpu->arch.dr7;
1006 break;
1007 }
338dbc97
GN		 1008 return 0;
1009}
020df079
GN		 1010EXPORT_SYMBOL_GPL(kvm_get_dr);
1011
022cd0e8
AK		 1012bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1013{
1014 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1015 u64 data;
1016 int err;
1017
c6702c9d 1018 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1019 if (err)
1020 return err;
1021 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1022 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1023 return err;
1024}
1025EXPORT_SYMBOL_GPL(kvm_rdpmc);
1026
043405e1
CO		 1027/*
1028 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1029 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1030 *
1031 * This list is modified at module load time to reflect the
e3267cbb 1032 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1033 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1034 * may depend on host virtualization features rather than host cpu features.
043405e1 1035 */
e3267cbb 1036
043405e1
CO		 1037static u32 msrs_to_save[] = {
1038 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1039 MSR_STAR,
043405e1
CO		 1040#ifdef CONFIG_X86_64
1041 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1042#endif
b3897a49 1043 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1044 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1045 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1046};
1047
1048static unsigned num_msrs_to_save;
1049
62ef68bb
PB		 1050static u32 emulated_msrs[] = {
1051 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1052 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1053 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1054 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1055 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1056 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1057 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1058 HV_X64_MSR_RESET,
11c4b1ca 1059 HV_X64_MSR_VP_INDEX,
9eec50b8 1060 HV_X64_MSR_VP_RUNTIME,
5c919412 1061 HV_X64_MSR_SCONTROL,
1f4b34f8 1062 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1063 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1064 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1065 HV_X64_MSR_TSC_EMULATION_STATUS,
1066
1067 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1068 MSR_KVM_PV_EOI_EN,
1069
ba904635 1070 MSR_IA32_TSC_ADJUST,
a3e06bbe 1071 MSR_IA32_TSCDEADLINE,
043405e1 1072 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1073 MSR_IA32_MCG_STATUS,
1074 MSR_IA32_MCG_CTL,
c45dcc71 1075 MSR_IA32_MCG_EXT_CTL,
64d60670 1076 MSR_IA32_SMBASE,
52797bf9 1077 MSR_SMI_COUNT,
db2336a8
KH		 1078 MSR_PLATFORM_INFO,
1079 MSR_MISC_FEATURES_ENABLES,
bc226f07 1080 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1081};
1082
62ef68bb
PB		 1083static unsigned num_emulated_msrs;
1084
801e459a
TL		 1085/*
1086 * List of msr numbers which are used to expose MSR-based features that
1087 * can be used by a hypervisor to validate requested CPU features.
1088 */
1089static u32 msr_based_features[] = {
1389309c
PB		 1090 MSR_IA32_VMX_BASIC,
1091 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1092 MSR_IA32_VMX_PINBASED_CTLS,
1093 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1094 MSR_IA32_VMX_PROCBASED_CTLS,
1095 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1096 MSR_IA32_VMX_EXIT_CTLS,
1097 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1098 MSR_IA32_VMX_ENTRY_CTLS,
1099 MSR_IA32_VMX_MISC,
1100 MSR_IA32_VMX_CR0_FIXED0,
1101 MSR_IA32_VMX_CR0_FIXED1,
1102 MSR_IA32_VMX_CR4_FIXED0,
1103 MSR_IA32_VMX_CR4_FIXED1,
1104 MSR_IA32_VMX_VMCS_ENUM,
1105 MSR_IA32_VMX_PROCBASED_CTLS2,
1106 MSR_IA32_VMX_EPT_VPID_CAP,
1107 MSR_IA32_VMX_VMFUNC,
1108
d1d93fa9 1109 MSR_F10H_DECFG,
518e7b94 1110 MSR_IA32_UCODE_REV,
cd283252 1111 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1112};
1113
1114static unsigned int num_msr_based_features;
1115
5b76a3cf
PB		 1116u64 kvm_get_arch_capabilities(void)
1117{
1118 u64 data;
1119
1120 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1121
1122 /*
1123 * If we're doing cache flushes (either "always" or "cond")
1124 * we will do one whenever the guest does a vmlaunch/vmresume.
1125 * If an outer hypervisor is doing the cache flush for us
1126 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1127 * capability to the guest too, and if EPT is disabled we're not
1128 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1129 * require a nested hypervisor to do a flush of its own.
1130 */
1131 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1132 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1133
1134 return data;
1135}
1136EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1137
66421c1e
WL		 1138static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1139{
1140 switch (msr->index) {
cd283252 1141 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1142 msr->data = kvm_get_arch_capabilities();
1143 break;
1144 case MSR_IA32_UCODE_REV:
cd283252 1145 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1146 break;
66421c1e
WL		 1147 default:
1148 if (kvm_x86_ops->get_msr_feature(msr))
1149 return 1;
1150 }
1151 return 0;
1152}
1153
801e459a
TL		 1154static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1155{
1156 struct kvm_msr_entry msr;
66421c1e 1157 int r;
801e459a
TL		 1158
1159 msr.index = index;
66421c1e
WL		 1160 r = kvm_get_msr_feature(&msr);
1161 if (r)
1162 return r;
801e459a
TL		 1163
1164 *data = msr.data;
1165
1166 return 0;
1167}
1168
384bb783 1169bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1170{
b69e8cae 1171 if (efer & efer_reserved_bits)
384bb783 1172 return false;
15c4a640 1173
1b4d56b8 1174 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1175 return false;
1b2fd70c 1176
1b4d56b8 1177 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1178 return false;
d8017474 1179
384bb783
JK		 1180 return true;
1181}
1182EXPORT_SYMBOL_GPL(kvm_valid_efer);
1183
1184static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1185{
1186 u64 old_efer = vcpu->arch.efer;
1187
1188 if (!kvm_valid_efer(vcpu, efer))
1189 return 1;
1190
1191 if (is_paging(vcpu)
1192 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1193 return 1;
1194
15c4a640 1195 efer &= ~EFER_LMA;
f6801dff 1196 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1197
a3d204e2
SY		 1198 kvm_x86_ops->set_efer(vcpu, efer);
1199
aad82703
SY		 1200 /* Update reserved bits */
1201 if ((efer ^ old_efer) & EFER_NX)
1202 kvm_mmu_reset_context(vcpu);
1203
b69e8cae 1204 return 0;
15c4a640
CO		 1205}
1206
f2b4b7dd
JR		 1207void kvm_enable_efer_bits(u64 mask)
1208{
1209 efer_reserved_bits &= ~mask;
1210}
1211EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1212
15c4a640
CO		 1213/*
1214 * Writes msr value into into the appropriate "register".
1215 * Returns 0 on success, non-0 otherwise.
1216 * Assumes vcpu_load() was already called.
1217 */
8fe8ab46 1218int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1219{
854e8bb1
NA		 1220 switch (msr->index) {
1221 case MSR_FS_BASE:
1222 case MSR_GS_BASE:
1223 case MSR_KERNEL_GS_BASE:
1224 case MSR_CSTAR:
1225 case MSR_LSTAR:
fd8cb433 1226 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1227 return 1;
1228 break;
1229 case MSR_IA32_SYSENTER_EIP:
1230 case MSR_IA32_SYSENTER_ESP:
1231 /*
1232 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1233 * non-canonical address is written on Intel but not on
1234 * AMD (which ignores the top 32-bits, because it does
1235 * not implement 64-bit SYSENTER).
1236 *
1237 * 64-bit code should hence be able to write a non-canonical
1238 * value on AMD. Making the address canonical ensures that
1239 * vmentry does not fail on Intel after writing a non-canonical
1240 * value, and that something deterministic happens if the guest
1241 * invokes 64-bit SYSENTER.
1242 */
fd8cb433 1243 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1244 }
8fe8ab46 1245 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1246}
854e8bb1 1247EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1248
313a3dc7
CO		 1249/*
1250 * Adapt set_msr() to msr_io()'s calling convention
1251 */
609e36d3
PB		 1252static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1253{
1254 struct msr_data msr;
1255 int r;
1256
1257 msr.index = index;
1258 msr.host_initiated = true;
1259 r = kvm_get_msr(vcpu, &msr);
1260 if (r)
1261 return r;
1262
1263 *data = msr.data;
1264 return 0;
1265}
1266
313a3dc7
CO		 1267static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1268{
8fe8ab46
WA		 1269 struct msr_data msr;
1270
1271 msr.data = *data;
1272 msr.index = index;
1273 msr.host_initiated = true;
1274 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1275}
1276
16e8d74d
MT		 1277#ifdef CONFIG_X86_64
1278struct pvclock_gtod_data {
1279 seqcount_t seq;
1280
1281 struct { /* extract of a clocksource struct */
1282 int vclock_mode;
a5a1d1c2
TG		 1283 u64 cycle_last;
1284 u64 mask;
16e8d74d
MT		 1285 u32 mult;
1286 u32 shift;
1287 } clock;
1288
cbcf2dd3
TG		 1289 u64 boot_ns;
1290 u64 nsec_base;
55dd00a7 1291 u64 wall_time_sec;
16e8d74d
MT		 1292};
1293
1294static struct pvclock_gtod_data pvclock_gtod_data;
1295
1296static void update_pvclock_gtod(struct timekeeper *tk)
1297{
1298 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1299 u64 boot_ns;
1300
876e7881 1301 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1302
1303 write_seqcount_begin(&vdata->seq);
1304
1305 /* copy pvclock gtod data */
876e7881
PZ		 1306 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1307 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1308 vdata->clock.mask = tk->tkr_mono.mask;
1309 vdata->clock.mult = tk->tkr_mono.mult;
1310 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1311
cbcf2dd3 1312 vdata->boot_ns = boot_ns;
876e7881 1313 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1314
55dd00a7
MT		 1315 vdata->wall_time_sec = tk->xtime_sec;
1316
16e8d74d
MT		 1317 write_seqcount_end(&vdata->seq);
1318}
1319#endif
1320
bab5bb39
NK		 1321void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1322{
1323 /*
1324 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1325 * vcpu_enter_guest. This function is only called from
1326 * the physical CPU that is running vcpu.
1327 */
1328 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1329}
16e8d74d 1330
18068523
GOC		 1331static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1332{
9ed3c444
AK		 1333 int version;
1334 int r;
50d0a0f9 1335 struct pvclock_wall_clock wc;
87aeb54f 1336 struct timespec64 boot;
18068523
GOC		 1337
1338 if (!wall_clock)
1339 return;
1340
9ed3c444
AK		 1341 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1342 if (r)
1343 return;
1344
1345 if (version & 1)
1346 ++version; /* first time write, random junk */
1347
1348 ++version;
18068523 1349
1dab1345
NK		 1350 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1351 return;
18068523 1352
50d0a0f9
GH		 1353 /*
1354 * The guest calculates current wall clock time by adding
34c238a1 1355 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1356 * wall clock specified here. guest system time equals host
1357 * system time for us, thus we must fill in host boot time here.
1358 */
87aeb54f 1359 getboottime64(&boot);
50d0a0f9 1360
4b648665 1361 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1362 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1363 boot = timespec64_sub(boot, ts);
4b648665 1364 }
87aeb54f 1365 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1366 wc.nsec = boot.tv_nsec;
1367 wc.version = version;
18068523
GOC		 1368
1369 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1370
1371 version++;
1372 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1373}
1374
50d0a0f9
GH		 1375static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1376{
b51012de
PB		 1377 do_shl32_div32(dividend, divisor);
1378 return dividend;
50d0a0f9
GH		 1379}
1380
3ae13faa 1381static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1382 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1383{
5f4e3f88 1384 uint64_t scaled64;
50d0a0f9
GH		 1385 int32_t shift = 0;
1386 uint64_t tps64;
1387 uint32_t tps32;
1388
3ae13faa
PB		 1389 tps64 = base_hz;
1390 scaled64 = scaled_hz;
50933623 1391 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1392 tps64 >>= 1;
1393 shift--;
1394 }
1395
1396 tps32 = (uint32_t)tps64;
50933623
JK		 1397 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1398 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1399 scaled64 >>= 1;
1400 else
1401 tps32 <<= 1;
50d0a0f9
GH		 1402 shift++;
1403 }
1404
5f4e3f88
ZA		 1405 *pshift = shift;
1406 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1407
3ae13faa
PB		 1408 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1409 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1410}
1411
d828199e 1412#ifdef CONFIG_X86_64
16e8d74d 1413static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1414#endif
16e8d74d 1415
c8076604 1416static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1417static unsigned long max_tsc_khz;
c8076604 1418
cc578287 1419static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1420{
cc578287
ZA		 1421 u64 v = (u64)khz * (1000000 + ppm);
1422 do_div(v, 1000000);
1423 return v;
1e993611
JR		 1424}
1425
381d585c
HZ		 1426static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1427{
1428 u64 ratio;
1429
1430 /* Guest TSC same frequency as host TSC? */
1431 if (!scale) {
1432 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1433 return 0;
1434 }
1435
1436 /* TSC scaling supported? */
1437 if (!kvm_has_tsc_control) {
1438 if (user_tsc_khz > tsc_khz) {
1439 vcpu->arch.tsc_catchup = 1;
1440 vcpu->arch.tsc_always_catchup = 1;
1441 return 0;
1442 } else {
1443 WARN(1, "user requested TSC rate below hardware speed\n");
1444 return -1;
1445 }
1446 }
1447
1448 /* TSC scaling required - calculate ratio */
1449 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1450 user_tsc_khz, tsc_khz);
1451
1452 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1453 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1454 user_tsc_khz);
1455 return -1;
1456 }
1457
1458 vcpu->arch.tsc_scaling_ratio = ratio;
1459 return 0;
1460}
1461
4941b8cb 1462static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1463{
cc578287
ZA		 1464 u32 thresh_lo, thresh_hi;
1465 int use_scaling = 0;
217fc9cf 1466
03ba32ca 1467 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1468 if (user_tsc_khz == 0) {
ad721883
HZ		 1469 /* set tsc_scaling_ratio to a safe value */
1470 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1471 return -1;
ad721883 1472 }
03ba32ca 1473
c285545f 1474 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1475 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1476 &vcpu->arch.virtual_tsc_shift,
1477 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1478 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1479
1480 /*
1481 * Compute the variation in TSC rate which is acceptable
1482 * within the range of tolerance and decide if the
1483 * rate being applied is within that bounds of the hardware
1484 * rate. If so, no scaling or compensation need be done.
1485 */
1486 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1487 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1488 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1489 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1490 use_scaling = 1;
1491 }
4941b8cb 1492 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1493}
1494
1495static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1496{
e26101b1 1497 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1498 vcpu->arch.virtual_tsc_mult,
1499 vcpu->arch.virtual_tsc_shift);
e26101b1 1500 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1501 return tsc;
1502}
1503
b0c39dc6
VK		 1504static inline int gtod_is_based_on_tsc(int mode)
1505{
1506 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1507}
1508
69b0049a 1509static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1510{
1511#ifdef CONFIG_X86_64
1512 bool vcpus_matched;
b48aa97e
MT		 1513 struct kvm_arch *ka = &vcpu->kvm->arch;
1514 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1515
1516 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1517 atomic_read(&vcpu->kvm->online_vcpus));
1518
7f187922
MT		 1519 /*
1520 * Once the masterclock is enabled, always perform request in
1521 * order to update it.
1522 *
1523 * In order to enable masterclock, the host clocksource must be TSC
1524 * and the vcpus need to have matched TSCs. When that happens,
1525 * perform request to enable masterclock.
1526 */
1527 if (ka->use_master_clock ||
b0c39dc6 1528 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1529 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1530
1531 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1532 atomic_read(&vcpu->kvm->online_vcpus),
1533 ka->use_master_clock, gtod->clock.vclock_mode);
1534#endif
1535}
1536
ba904635
WA		 1537static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1538{
e79f245d 1539 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1540 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1541}
1542
35181e86
HZ		 1543/*
1544 * Multiply tsc by a fixed point number represented by ratio.
1545 *
1546 * The most significant 64-N bits (mult) of ratio represent the
1547 * integral part of the fixed point number; the remaining N bits
1548 * (frac) represent the fractional part, ie. ratio represents a fixed
1549 * point number (mult + frac * 2^(-N)).
1550 *
1551 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1552 */
1553static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1554{
1555 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1556}
1557
1558u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1559{
1560 u64 _tsc = tsc;
1561 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1562
1563 if (ratio != kvm_default_tsc_scaling_ratio)
1564 _tsc = __scale_tsc(ratio, tsc);
1565
1566 return _tsc;
1567}
1568EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1569
07c1419a
HZ		 1570static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1571{
1572 u64 tsc;
1573
1574 tsc = kvm_scale_tsc(vcpu, rdtsc());
1575
1576 return target_tsc - tsc;
1577}
1578
4ba76538
HZ		 1579u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1580{
e79f245d
KA		 1581 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1582
1583 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1584}
1585EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1586
a545ab6a
LC		 1587static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1588{
1589 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1590 vcpu->arch.tsc_offset = offset;
1591}
1592
b0c39dc6
VK		 1593static inline bool kvm_check_tsc_unstable(void)
1594{
1595#ifdef CONFIG_X86_64
1596 /*
1597 * TSC is marked unstable when we're running on Hyper-V,
1598 * 'TSC page' clocksource is good.
1599 */
1600 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1601 return false;
1602#endif
1603 return check_tsc_unstable();
1604}
1605
8fe8ab46 1606void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1607{
1608 struct kvm *kvm = vcpu->kvm;
f38e098f 1609 u64 offset, ns, elapsed;
99e3e30a 1610 unsigned long flags;
b48aa97e 1611 bool matched;
0d3da0d2 1612 bool already_matched;
8fe8ab46 1613 u64 data = msr->data;
c5e8ec8e 1614 bool synchronizing = false;
99e3e30a 1615
038f8c11 1616 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1617 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1618 ns = ktime_get_boot_ns();
f38e098f 1619 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1620
03ba32ca 1621 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1622 if (data == 0 && msr->host_initiated) {
1623 /*
1624 * detection of vcpu initialization -- need to sync
1625 * with other vCPUs. This particularly helps to keep
1626 * kvm_clock stable after CPU hotplug
1627 */
1628 synchronizing = true;
1629 } else {
1630 u64 tsc_exp = kvm->arch.last_tsc_write +
1631 nsec_to_cycles(vcpu, elapsed);
1632 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1633 /*
1634 * Special case: TSC write with a small delta (1 second)
1635 * of virtual cycle time against real time is
1636 * interpreted as an attempt to synchronize the CPU.
1637 */
1638 synchronizing = data < tsc_exp + tsc_hz &&
1639 data + tsc_hz > tsc_exp;
1640 }
c5e8ec8e 1641 }
f38e098f
ZA		 1642
1643 /*
5d3cb0f6
ZA		 1644 * For a reliable TSC, we can match TSC offsets, and for an unstable
1645 * TSC, we add elapsed time in this computation. We could let the
1646 * compensation code attempt to catch up if we fall behind, but
1647 * it's better to try to match offsets from the beginning.
1648 */
c5e8ec8e 1649 if (synchronizing &&
5d3cb0f6 1650 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1651 if (!kvm_check_tsc_unstable()) {
e26101b1 1652 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1653 pr_debug("kvm: matched tsc offset for %llu\n", data);
1654 } else {
857e4099 1655 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1656 data += delta;
07c1419a 1657 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1658 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1659 }
b48aa97e 1660 matched = true;
0d3da0d2 1661 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1662 } else {
1663 /*
1664 * We split periods of matched TSC writes into generations.
1665 * For each generation, we track the original measured
1666 * nanosecond time, offset, and write, so if TSCs are in
1667 * sync, we can match exact offset, and if not, we can match
4a969980 1668 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1669 *
1670 * These values are tracked in kvm->arch.cur_xxx variables.
1671 */
1672 kvm->arch.cur_tsc_generation++;
1673 kvm->arch.cur_tsc_nsec = ns;
1674 kvm->arch.cur_tsc_write = data;
1675 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1676 matched = false;
0d3da0d2 1677 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1678 kvm->arch.cur_tsc_generation, data);
f38e098f 1679 }
e26101b1
ZA		 1680
1681 /*
1682 * We also track th most recent recorded KHZ, write and time to
1683 * allow the matching interval to be extended at each write.
1684 */
f38e098f
ZA		 1685 kvm->arch.last_tsc_nsec = ns;
1686 kvm->arch.last_tsc_write = data;
5d3cb0f6 1687 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1688
b183aa58 1689 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1690
1691 /* Keep track of which generation this VCPU has synchronized to */
1692 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1693 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1694 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1695
d6321d49 1696 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1697 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1698
a545ab6a 1699 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1700 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1701
1702 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1703 if (!matched) {
b48aa97e 1704 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1705 } else if (!already_matched) {
1706 kvm->arch.nr_vcpus_matched_tsc++;
1707 }
b48aa97e
MT		 1708
1709 kvm_track_tsc_matching(vcpu);
1710 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1711}
e26101b1 1712
99e3e30a
ZA		 1713EXPORT_SYMBOL_GPL(kvm_write_tsc);
1714
58ea6767
HZ		 1715static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1716 s64 adjustment)
1717{
ea26e4ec 1718 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1719}
1720
1721static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1722{
1723 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1724 WARN_ON(adjustment < 0);
1725 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1726 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1727}
1728
d828199e
MT		 1729#ifdef CONFIG_X86_64
1730
a5a1d1c2 1731static u64 read_tsc(void)
d828199e 1732{
a5a1d1c2 1733 u64 ret = (u64)rdtsc_ordered();
03b9730b 1734 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1735
1736 if (likely(ret >= last))
1737 return ret;
1738
1739 /*
1740 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1741 * predictable (it's just a function of time and the likely is
d828199e
MT		 1742 * very likely) and there's a data dependence, so force GCC
1743 * to generate a branch instead. I don't barrier() because
1744 * we don't actually need a barrier, and if this function
1745 * ever gets inlined it will generate worse code.
1746 */
1747 asm volatile ("");
1748 return last;
1749}
1750
b0c39dc6 1751static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1752{
1753 long v;
1754 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1755 u64 tsc_pg_val;
1756
1757 switch (gtod->clock.vclock_mode) {
1758 case VCLOCK_HVCLOCK:
1759 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1760 tsc_timestamp);
1761 if (tsc_pg_val != U64_MAX) {
1762 /* TSC page valid */
1763 *mode = VCLOCK_HVCLOCK;
1764 v = (tsc_pg_val - gtod->clock.cycle_last) &
1765 gtod->clock.mask;
1766 } else {
1767 /* TSC page invalid */
1768 *mode = VCLOCK_NONE;
1769 }
1770 break;
1771 case VCLOCK_TSC:
1772 *mode = VCLOCK_TSC;
1773 *tsc_timestamp = read_tsc();
1774 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1775 gtod->clock.mask;
1776 break;
1777 default:
1778 *mode = VCLOCK_NONE;
1779 }
d828199e 1780
b0c39dc6
VK		 1781 if (*mode == VCLOCK_NONE)
1782 *tsc_timestamp = v = 0;
d828199e 1783
d828199e
MT		 1784 return v * gtod->clock.mult;
1785}
1786
b0c39dc6 1787static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1788{
cbcf2dd3 1789 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1790 unsigned long seq;
d828199e 1791 int mode;
cbcf2dd3 1792 u64 ns;
d828199e 1793
d828199e
MT		 1794 do {
1795 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1796 ns = gtod->nsec_base;
b0c39dc6 1797 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1798 ns >>= gtod->clock.shift;
cbcf2dd3 1799 ns += gtod->boot_ns;
d828199e 1800 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1801 *t = ns;
d828199e
MT		 1802
1803 return mode;
1804}
1805
899a31f5 1806static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1807{
1808 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1809 unsigned long seq;
1810 int mode;
1811 u64 ns;
1812
1813 do {
1814 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1815 ts->tv_sec = gtod->wall_time_sec;
1816 ns = gtod->nsec_base;
b0c39dc6 1817 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1818 ns >>= gtod->clock.shift;
1819 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1820
1821 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1822 ts->tv_nsec = ns;
1823
1824 return mode;
1825}
1826
b0c39dc6
VK		 1827/* returns true if host is using TSC based clocksource */
1828static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1829{
d828199e 1830 /* checked again under seqlock below */
b0c39dc6 1831 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1832 return false;
1833
b0c39dc6
VK		 1834 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1835 tsc_timestamp));
d828199e 1836}
55dd00a7 1837
b0c39dc6 1838/* returns true if host is using TSC based clocksource */
899a31f5 1839static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1840 u64 *tsc_timestamp)
55dd00a7
MT		 1841{
1842 /* checked again under seqlock below */
b0c39dc6 1843 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1844 return false;
1845
b0c39dc6 1846 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1847}
d828199e
MT		 1848#endif
1849
1850/*
1851 *
b48aa97e
MT		 1852 * Assuming a stable TSC across physical CPUS, and a stable TSC
1853 * across virtual CPUs, the following condition is possible.
1854 * Each numbered line represents an event visible to both
d828199e
MT		 1855 * CPUs at the next numbered event.
1856 *
1857 * "timespecX" represents host monotonic time. "tscX" represents
1858 * RDTSC value.
1859 *
1860 * VCPU0 on CPU0 | VCPU1 on CPU1
1861 *
1862 * 1. read timespec0,tsc0
1863 * 2. | timespec1 = timespec0 + N
1864 * | tsc1 = tsc0 + M
1865 * 3. transition to guest | transition to guest
1866 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1867 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1868 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1869 *
1870 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1871 *
1872 * - ret0 < ret1
1873 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1874 * ...
1875 * - 0 < N - M => M < N
1876 *
1877 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1878 * always the case (the difference between two distinct xtime instances
1879 * might be smaller then the difference between corresponding TSC reads,
1880 * when updating guest vcpus pvclock areas).
1881 *
1882 * To avoid that problem, do not allow visibility of distinct
1883 * system_timestamp/tsc_timestamp values simultaneously: use a master
1884 * copy of host monotonic time values. Update that master copy
1885 * in lockstep.
1886 *
b48aa97e 1887 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1888 *
1889 */
1890
1891static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1892{
1893#ifdef CONFIG_X86_64
1894 struct kvm_arch *ka = &kvm->arch;
1895 int vclock_mode;
b48aa97e
MT		 1896 bool host_tsc_clocksource, vcpus_matched;
1897
1898 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1899 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1900
1901 /*
1902 * If the host uses TSC clock, then passthrough TSC as stable
1903 * to the guest.
1904 */
b48aa97e 1905 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1906 &ka->master_kernel_ns,
1907 &ka->master_cycle_now);
1908
16a96021 1909 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1910 && !ka->backwards_tsc_observed
54750f2c 1911 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1912
d828199e
MT		 1913 if (ka->use_master_clock)
1914 atomic_set(&kvm_guest_has_master_clock, 1);
1915
1916 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1917 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1918 vcpus_matched);
d828199e
MT		 1919#endif
1920}
1921
2860c4b1
PB		 1922void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1923{
1924 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1925}
1926
2e762ff7
MT		 1927static void kvm_gen_update_masterclock(struct kvm *kvm)
1928{
1929#ifdef CONFIG_X86_64
1930 int i;
1931 struct kvm_vcpu *vcpu;
1932 struct kvm_arch *ka = &kvm->arch;
1933
1934 spin_lock(&ka->pvclock_gtod_sync_lock);
1935 kvm_make_mclock_inprogress_request(kvm);
1936 /* no guest entries from this point */
1937 pvclock_update_vm_gtod_copy(kvm);
1938
1939 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1940 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1941
1942 /* guest entries allowed */
1943 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1944 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1945
1946 spin_unlock(&ka->pvclock_gtod_sync_lock);
1947#endif
1948}
1949
e891a32e 1950u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1951{
108b249c 1952 struct kvm_arch *ka = &kvm->arch;
8b953440 1953 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1954 u64 ret;
108b249c 1955
8b953440
PB		 1956 spin_lock(&ka->pvclock_gtod_sync_lock);
1957 if (!ka->use_master_clock) {
1958 spin_unlock(&ka->pvclock_gtod_sync_lock);
1959 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1960 }
1961
8b953440
PB		 1962 hv_clock.tsc_timestamp = ka->master_cycle_now;
1963 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1964 spin_unlock(&ka->pvclock_gtod_sync_lock);
1965
e2c2206a
WL		 1966 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1967 get_cpu();
1968
e70b57a6
WL		 1969 if (__this_cpu_read(cpu_tsc_khz)) {
1970 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1971 &hv_clock.tsc_shift,
1972 &hv_clock.tsc_to_system_mul);
1973 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1974 } else
1975 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1976
1977 put_cpu();
1978
1979 return ret;
108b249c
PB		 1980}
1981
0d6dd2ff
PB		 1982static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1983{
1984 struct kvm_vcpu_arch *vcpu = &v->arch;
1985 struct pvclock_vcpu_time_info guest_hv_clock;
1986
4e335d9e 1987 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1988 &guest_hv_clock, sizeof(guest_hv_clock))))
1989 return;
1990
1991 /* This VCPU is paused, but it's legal for a guest to read another
1992 * VCPU's kvmclock, so we really have to follow the specification where
1993 * it says that version is odd if data is being modified, and even after
1994 * it is consistent.
1995 *
1996 * Version field updates must be kept separate. This is because
1997 * kvm_write_guest_cached might use a "rep movs" instruction, and
1998 * writes within a string instruction are weakly ordered. So there
1999 * are three writes overall.
2000 *
2001 * As a small optimization, only write the version field in the first
2002 * and third write. The vcpu->pv_time cache is still valid, because the
2003 * version field is the first in the struct.
2004 */
2005 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2006
51c4b8bb
LA		 2007 if (guest_hv_clock.version & 1)
2008 ++guest_hv_clock.version; /* first time write, random junk */
2009
0d6dd2ff 2010 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2011 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2012 &vcpu->hv_clock,
2013 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2014
2015 smp_wmb();
2016
2017 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2018 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2019
2020 if (vcpu->pvclock_set_guest_stopped_request) {
2021 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2022 vcpu->pvclock_set_guest_stopped_request = false;
2023 }
2024
2025 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2026
4e335d9e
PB		 2027 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2028 &vcpu->hv_clock,
2029 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2030
2031 smp_wmb();
2032
2033 vcpu->hv_clock.version++;
4e335d9e
PB		 2034 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2035 &vcpu->hv_clock,
2036 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2037}
2038
34c238a1 2039static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2040{
78db6a50 2041 unsigned long flags, tgt_tsc_khz;
18068523 2042 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2043 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2044 s64 kernel_ns;
d828199e 2045 u64 tsc_timestamp, host_tsc;
51d59c6b 2046 u8 pvclock_flags;
d828199e
MT		 2047 bool use_master_clock;
2048
2049 kernel_ns = 0;
2050 host_tsc = 0;
18068523 2051
d828199e
MT		 2052 /*
2053 * If the host uses TSC clock, then passthrough TSC as stable
2054 * to the guest.
2055 */
2056 spin_lock(&ka->pvclock_gtod_sync_lock);
2057 use_master_clock = ka->use_master_clock;
2058 if (use_master_clock) {
2059 host_tsc = ka->master_cycle_now;
2060 kernel_ns = ka->master_kernel_ns;
2061 }
2062 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2063
2064 /* Keep irq disabled to prevent changes to the clock */
2065 local_irq_save(flags);
78db6a50
PB		 2066 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2067 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2068 local_irq_restore(flags);
2069 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2070 return 1;
2071 }
d828199e 2072 if (!use_master_clock) {
4ea1636b 2073 host_tsc = rdtsc();
108b249c 2074 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2075 }
2076
4ba76538 2077 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2078
c285545f
ZA		 2079 /*
2080 * We may have to catch up the TSC to match elapsed wall clock
2081 * time for two reasons, even if kvmclock is used.
2082 * 1) CPU could have been running below the maximum TSC rate
2083 * 2) Broken TSC compensation resets the base at each VCPU
2084 * entry to avoid unknown leaps of TSC even when running
2085 * again on the same CPU. This may cause apparent elapsed
2086 * time to disappear, and the guest to stand still or run
2087 * very slowly.
2088 */
2089 if (vcpu->tsc_catchup) {
2090 u64 tsc = compute_guest_tsc(v, kernel_ns);
2091 if (tsc > tsc_timestamp) {
f1e2b260 2092 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2093 tsc_timestamp = tsc;
2094 }
50d0a0f9
GH		 2095 }
2096
18068523
GOC		 2097 local_irq_restore(flags);
2098
0d6dd2ff 2099 /* With all the info we got, fill in the values */
18068523 2100
78db6a50
PB		 2101 if (kvm_has_tsc_control)
2102 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2103
2104 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2105 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2106 &vcpu->hv_clock.tsc_shift,
2107 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2108 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2109 }
2110
1d5f066e 2111 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2112 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2113 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2114
d828199e 2115 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2116 pvclock_flags = 0;
d828199e
MT		 2117 if (use_master_clock)
2118 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2119
78c0337a
MT		 2120 vcpu->hv_clock.flags = pvclock_flags;
2121
095cf55d
PB		 2122 if (vcpu->pv_time_enabled)
2123 kvm_setup_pvclock_page(v);
2124 if (v == kvm_get_vcpu(v->kvm, 0))
2125 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2126 return 0;
c8076604
GH		 2127}
2128
0061d53d
MT		 2129/*
2130 * kvmclock updates which are isolated to a given vcpu, such as
2131 * vcpu->cpu migration, should not allow system_timestamp from
2132 * the rest of the vcpus to remain static. Otherwise ntp frequency
2133 * correction applies to one vcpu's system_timestamp but not
2134 * the others.
2135 *
2136 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2137 * We need to rate-limit these requests though, as they can
2138 * considerably slow guests that have a large number of vcpus.
2139 * The time for a remote vcpu to update its kvmclock is bound
2140 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2141 */
2142
7e44e449
AJ		 2143#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2144
2145static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2146{
2147 int i;
7e44e449
AJ		 2148 struct delayed_work *dwork = to_delayed_work(work);
2149 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2150 kvmclock_update_work);
2151 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2152 struct kvm_vcpu *vcpu;
2153
2154 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2155 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2156 kvm_vcpu_kick(vcpu);
2157 }
2158}
2159
7e44e449
AJ		 2160static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2161{
2162 struct kvm *kvm = v->kvm;
2163
105b21bb 2164 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2165 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2166 KVMCLOCK_UPDATE_DELAY);
2167}
2168
332967a3
AJ		 2169#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2170
2171static void kvmclock_sync_fn(struct work_struct *work)
2172{
2173 struct delayed_work *dwork = to_delayed_work(work);
2174 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2175 kvmclock_sync_work);
2176 struct kvm *kvm = container_of(ka, struct kvm, arch);
2177
630994b3
MT		 2178 if (!kvmclock_periodic_sync)
2179 return;
2180
332967a3
AJ		 2181 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2182 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2183 KVMCLOCK_SYNC_PERIOD);
2184}
2185
9ffd986c 2186static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2187{
890ca9ae
HY		 2188 u64 mcg_cap = vcpu->arch.mcg_cap;
2189 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2190 u32 msr = msr_info->index;
2191 u64 data = msr_info->data;
890ca9ae 2192
15c4a640 2193 switch (msr) {
15c4a640 2194 case MSR_IA32_MCG_STATUS:
890ca9ae 2195 vcpu->arch.mcg_status = data;
15c4a640 2196 break;
c7ac679c 2197 case MSR_IA32_MCG_CTL:
44883f01
PB		 2198 if (!(mcg_cap & MCG_CTL_P) &&
2199 (data || !msr_info->host_initiated))
890ca9ae
HY		 2200 return 1;
2201 if (data != 0 && data != ~(u64)0)
44883f01 2202 return 1;
890ca9ae
HY		 2203 vcpu->arch.mcg_ctl = data;
2204 break;
2205 default:
2206 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2207 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2208 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2209 /* only 0 or all 1s can be written to IA32_MCi_CTL
2210 * some Linux kernels though clear bit 10 in bank 4 to
2211 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2212 * this to avoid an uncatched #GP in the guest
2213 */
890ca9ae 2214 if ((offset & 0x3) == 0 &&
114be429 2215 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2216 return -1;
9ffd986c
WL		 2217 if (!msr_info->host_initiated &&
2218 (offset & 0x3) == 1 && data != 0)
2219 return -1;
890ca9ae
HY		 2220 vcpu->arch.mce_banks[offset] = data;
2221 break;
2222 }
2223 return 1;
2224 }
2225 return 0;
2226}
2227
ffde22ac
ES		 2228static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2229{
2230 struct kvm *kvm = vcpu->kvm;
2231 int lm = is_long_mode(vcpu);
2232 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2233 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2234 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2235 : kvm->arch.xen_hvm_config.blob_size_32;
2236 u32 page_num = data & ~PAGE_MASK;
2237 u64 page_addr = data & PAGE_MASK;
2238 u8 *page;
2239 int r;
2240
2241 r = -E2BIG;
2242 if (page_num >= blob_size)
2243 goto out;
2244 r = -ENOMEM;
ff5c2c03
SL		 2245 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2246 if (IS_ERR(page)) {
2247 r = PTR_ERR(page);
ffde22ac 2248 goto out;
ff5c2c03 2249 }
54bf36aa 2250 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2251 goto out_free;
2252 r = 0;
2253out_free:
2254 kfree(page);
2255out:
2256 return r;
2257}
2258
344d9588
GN		 2259static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2260{
2261 gpa_t gpa = data & ~0x3f;
2262
52a5c155
WL		 2263 /* Bits 3:5 are reserved, Should be zero */
2264 if (data & 0x38)
344d9588
GN		 2265 return 1;
2266
2267 vcpu->arch.apf.msr_val = data;
2268
2269 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2270 kvm_clear_async_pf_completion_queue(vcpu);
2271 kvm_async_pf_hash_reset(vcpu);
2272 return 0;
2273 }
2274
4e335d9e 2275 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2276 sizeof(u32)))
344d9588
GN		 2277 return 1;
2278
6adba527 2279 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2280 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2281 kvm_async_pf_wakeup_all(vcpu);
2282 return 0;
2283}
2284
12f9a48f
GC		 2285static void kvmclock_reset(struct kvm_vcpu *vcpu)
2286{
0b79459b 2287 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2288}
2289
f38a7b75
WL		 2290static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2291{
2292 ++vcpu->stat.tlb_flush;
2293 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2294}
2295
c9aaa895
GC		 2296static void record_steal_time(struct kvm_vcpu *vcpu)
2297{
2298 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2299 return;
2300
4e335d9e 2301 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2302 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2303 return;
2304
f38a7b75
WL		 2305 /*
2306 * Doing a TLB flush here, on the guest's behalf, can avoid
2307 * expensive IPIs.
2308 */
2309 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2310 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2311
35f3fae1
WL		 2312 if (vcpu->arch.st.steal.version & 1)
2313 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2314
2315 vcpu->arch.st.steal.version += 1;
2316
4e335d9e 2317 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2318 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2319
2320 smp_wmb();
2321
c54cdf14
LC		 2322 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2323 vcpu->arch.st.last_steal;
2324 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2325
4e335d9e 2326 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2327 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2328
2329 smp_wmb();
2330
2331 vcpu->arch.st.steal.version += 1;
c9aaa895 2332
4e335d9e 2333 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2334 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2335}
2336
8fe8ab46 2337int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2338{
5753785f 2339 bool pr = false;
8fe8ab46
WA		 2340 u32 msr = msr_info->index;
2341 u64 data = msr_info->data;
5753785f 2342
15c4a640 2343 switch (msr) {
2e32b719 2344 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2345 case MSR_IA32_UCODE_WRITE:
2346 case MSR_VM_HSAVE_PA:
2347 case MSR_AMD64_PATCH_LOADER:
2348 case MSR_AMD64_BU_CFG2:
405a353a 2349 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2350 break;
2351
518e7b94
WL		 2352 case MSR_IA32_UCODE_REV:
2353 if (msr_info->host_initiated)
2354 vcpu->arch.microcode_version = data;
2355 break;
15c4a640 2356 case MSR_EFER:
b69e8cae 2357 return set_efer(vcpu, data);
8f1589d9
AP		 2358 case MSR_K7_HWCR:
2359 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2360 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2361 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2362 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2363 if (data != 0) {
a737f256
CD		 2364 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2365 data);
8f1589d9
AP		 2366 return 1;
2367 }
15c4a640 2368 break;
f7c6d140
AP		 2369 case MSR_FAM10H_MMIO_CONF_BASE:
2370 if (data != 0) {
a737f256
CD		 2371 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2372 "0x%llx\n", data);
f7c6d140
AP		 2373 return 1;
2374 }
15c4a640 2375 break;
b5e2fec0
AG		 2376 case MSR_IA32_DEBUGCTLMSR:
2377 if (!data) {
2378 /* We support the non-activated case already */
2379 break;
2380 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2381 /* Values other than LBR and BTF are vendor-specific,
2382 thus reserved and should throw a #GP */
2383 return 1;
2384 }
a737f256
CD		 2385 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2386 __func__, data);
b5e2fec0 2387 break;
9ba075a6 2388 case 0x200 ... 0x2ff:
ff53604b 2389 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2390 case MSR_IA32_APICBASE:
58cb628d 2391 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2392 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2393 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2394 case MSR_IA32_TSCDEADLINE:
2395 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2396 break;
ba904635 2397 case MSR_IA32_TSC_ADJUST:
d6321d49 2398 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2399 if (!msr_info->host_initiated) {
d913b904 2400 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2401 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2402 }
2403 vcpu->arch.ia32_tsc_adjust_msr = data;
2404 }
2405 break;
15c4a640 2406 case MSR_IA32_MISC_ENABLE:
ad312c7c 2407 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2408 break;
64d60670
PB		 2409 case MSR_IA32_SMBASE:
2410 if (!msr_info->host_initiated)
2411 return 1;
2412 vcpu->arch.smbase = data;
2413 break;
dd259935
PB		 2414 case MSR_IA32_TSC:
2415 kvm_write_tsc(vcpu, msr_info);
2416 break;
52797bf9
LA		 2417 case MSR_SMI_COUNT:
2418 if (!msr_info->host_initiated)
2419 return 1;
2420 vcpu->arch.smi_count = data;
2421 break;
11c6bffa 2422 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2423 case MSR_KVM_WALL_CLOCK:
2424 vcpu->kvm->arch.wall_clock = data;
2425 kvm_write_wall_clock(vcpu->kvm, data);
2426 break;
11c6bffa 2427 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2428 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2429 struct kvm_arch *ka = &vcpu->kvm->arch;
2430
12f9a48f 2431 kvmclock_reset(vcpu);
18068523 2432
54750f2c
MT		 2433 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2434 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2435
2436 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2437 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2438
2439 ka->boot_vcpu_runs_old_kvmclock = tmp;
2440 }
2441
18068523 2442 vcpu->arch.time = data;
0061d53d 2443 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2444
2445 /* we verify if the enable bit is set... */
2446 if (!(data & 1))
2447 break;
2448
4e335d9e 2449 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2450 &vcpu->arch.pv_time, data & ~1ULL,
2451 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2452 vcpu->arch.pv_time_enabled = false;
2453 else
2454 vcpu->arch.pv_time_enabled = true;
32cad84f 2455
18068523
GOC		 2456 break;
2457 }
344d9588
GN		 2458 case MSR_KVM_ASYNC_PF_EN:
2459 if (kvm_pv_enable_async_pf(vcpu, data))
2460 return 1;
2461 break;
c9aaa895
GC		 2462 case MSR_KVM_STEAL_TIME:
2463
2464 if (unlikely(!sched_info_on()))
2465 return 1;
2466
2467 if (data & KVM_STEAL_RESERVED_MASK)
2468 return 1;
2469
4e335d9e 2470 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2471 data & KVM_STEAL_VALID_BITS,
2472 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2473 return 1;
2474
2475 vcpu->arch.st.msr_val = data;
2476
2477 if (!(data & KVM_MSR_ENABLED))
2478 break;
2479
c9aaa895
GC		 2480 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2481
2482 break;
ae7a2a3f 2483 case MSR_KVM_PV_EOI_EN:
72bbf935 2484 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2485 return 1;
2486 break;
c9aaa895 2487
890ca9ae
HY		 2488 case MSR_IA32_MCG_CTL:
2489 case MSR_IA32_MCG_STATUS:
81760dcc 2490 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2491 return set_msr_mce(vcpu, msr_info);
71db6023 2492
6912ac32
WH		 2493 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2494 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2495 pr = true; /* fall through */
2496 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2497 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2498 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2499 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2500
2501 if (pr || data != 0)
a737f256
CD		 2502 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2503 "0x%x data 0x%llx\n", msr, data);
5753785f 2504 break;
84e0cefa
JS		 2505 case MSR_K7_CLK_CTL:
2506 /*
2507 * Ignore all writes to this no longer documented MSR.
2508 * Writes are only relevant for old K7 processors,
2509 * all pre-dating SVM, but a recommended workaround from
4a969980 2510 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2511 * affected processor models on the command line, hence
2512 * the need to ignore the workaround.
2513 */
2514 break;
55cd8e5a 2515 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2516 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2517 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2518 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2519 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2520 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2521 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2522 return kvm_hv_set_msr_common(vcpu, msr, data,
2523 msr_info->host_initiated);
91c9c3ed 2524 case MSR_IA32_BBL_CR_CTL3:
2525 /* Drop writes to this legacy MSR -- see rdmsr
2526 * counterpart for further detail.
2527 */
fab0aa3b
EM		 2528 if (report_ignored_msrs)
2529 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2530 msr, data);
91c9c3ed 2531 break;
2b036c6b 2532 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2533 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2534 return 1;
2535 vcpu->arch.osvw.length = data;
2536 break;
2537 case MSR_AMD64_OSVW_STATUS:
d6321d49 2538 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2539 return 1;
2540 vcpu->arch.osvw.status = data;
2541 break;
db2336a8
KH		 2542 case MSR_PLATFORM_INFO:
2543 if (!msr_info->host_initiated ||
db2336a8
KH		 2544 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2545 cpuid_fault_enabled(vcpu)))
2546 return 1;
2547 vcpu->arch.msr_platform_info = data;
2548 break;
2549 case MSR_MISC_FEATURES_ENABLES:
2550 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2551 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2552 !supports_cpuid_fault(vcpu)))
2553 return 1;
2554 vcpu->arch.msr_misc_features_enables = data;
2555 break;
15c4a640 2556 default:
ffde22ac
ES		 2557 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2558 return xen_hvm_config(vcpu, data);
c6702c9d 2559 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2560 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2561 if (!ignore_msrs) {
ae0f5499 2562 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2563 msr, data);
ed85c068
AP		 2564 return 1;
2565 } else {
fab0aa3b
EM		 2566 if (report_ignored_msrs)
2567 vcpu_unimpl(vcpu,
2568 "ignored wrmsr: 0x%x data 0x%llx\n",
2569 msr, data);
ed85c068
AP		 2570 break;
2571 }
15c4a640
CO		 2572 }
2573 return 0;
2574}
2575EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2576
2577
2578/*
2579 * Reads an msr value (of 'msr_index') into 'pdata'.
2580 * Returns 0 on success, non-0 otherwise.
2581 * Assumes vcpu_load() was already called.
2582 */
609e36d3 2583int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2584{
609e36d3 2585 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2586}
ff651cb6 2587EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2588
44883f01 2589static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2590{
2591 u64 data;
890ca9ae
HY		 2592 u64 mcg_cap = vcpu->arch.mcg_cap;
2593 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2594
2595 switch (msr) {
15c4a640
CO		 2596 case MSR_IA32_P5_MC_ADDR:
2597 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2598 data = 0;
2599 break;
15c4a640 2600 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2601 data = vcpu->arch.mcg_cap;
2602 break;
c7ac679c 2603 case MSR_IA32_MCG_CTL:
44883f01 2604 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2605 return 1;
2606 data = vcpu->arch.mcg_ctl;
2607 break;
2608 case MSR_IA32_MCG_STATUS:
2609 data = vcpu->arch.mcg_status;
2610 break;
2611 default:
2612 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2613 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2614 u32 offset = msr - MSR_IA32_MC0_CTL;
2615 data = vcpu->arch.mce_banks[offset];
2616 break;
2617 }
2618 return 1;
2619 }
2620 *pdata = data;
2621 return 0;
2622}
2623
609e36d3 2624int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2625{
609e36d3 2626 switch (msr_info->index) {
890ca9ae 2627 case MSR_IA32_PLATFORM_ID:
15c4a640 2628 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2629 case MSR_IA32_DEBUGCTLMSR:
2630 case MSR_IA32_LASTBRANCHFROMIP:
2631 case MSR_IA32_LASTBRANCHTOIP:
2632 case MSR_IA32_LASTINTFROMIP:
2633 case MSR_IA32_LASTINTTOIP:
60af2ecd 2634 case MSR_K8_SYSCFG:
3afb1121
PB		 2635 case MSR_K8_TSEG_ADDR:
2636 case MSR_K8_TSEG_MASK:
60af2ecd 2637 case MSR_K7_HWCR:
61a6bd67 2638 case MSR_VM_HSAVE_PA:
1fdbd48c 2639 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2640 case MSR_AMD64_NB_CFG:
f7c6d140 2641 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2642 case MSR_AMD64_BU_CFG2:
0c2df2a1 2643 case MSR_IA32_PERF_CTL:
405a353a 2644 case MSR_AMD64_DC_CFG:
609e36d3 2645 msr_info->data = 0;
15c4a640 2646 break;
c51eb52b 2647 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2648 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2649 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2650 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2651 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2652 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2653 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2654 msr_info->data = 0;
5753785f 2655 break;
742bc670 2656 case MSR_IA32_UCODE_REV:
518e7b94 2657 msr_info->data = vcpu->arch.microcode_version;
742bc670 2658 break;
dd259935
PB		 2659 case MSR_IA32_TSC:
2660 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2661 break;
9ba075a6 2662 case MSR_MTRRcap:
9ba075a6 2663 case 0x200 ... 0x2ff:
ff53604b 2664 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2665 case 0xcd: /* fsb frequency */
609e36d3 2666 msr_info->data = 3;
15c4a640 2667 break;
7b914098
JS		 2668 /*
2669 * MSR_EBC_FREQUENCY_ID
2670 * Conservative value valid for even the basic CPU models.
2671 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2672 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2673 * and 266MHz for model 3, or 4. Set Core Clock
2674 * Frequency to System Bus Frequency Ratio to 1 (bits
2675 * 31:24) even though these are only valid for CPU
2676 * models > 2, however guests may end up dividing or
2677 * multiplying by zero otherwise.
2678 */
2679 case MSR_EBC_FREQUENCY_ID:
609e36d3 2680 msr_info->data = 1 << 24;
7b914098 2681 break;
15c4a640 2682 case MSR_IA32_APICBASE:
609e36d3 2683 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2684 break;
0105d1a5 2685 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2686 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2687 break;
a3e06bbe 2688 case MSR_IA32_TSCDEADLINE:
609e36d3 2689 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2690 break;
ba904635 2691 case MSR_IA32_TSC_ADJUST:
609e36d3 2692 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2693 break;
15c4a640 2694 case MSR_IA32_MISC_ENABLE:
609e36d3 2695 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2696 break;
64d60670
PB		 2697 case MSR_IA32_SMBASE:
2698 if (!msr_info->host_initiated)
2699 return 1;
2700 msr_info->data = vcpu->arch.smbase;
15c4a640 2701 break;
52797bf9
LA		 2702 case MSR_SMI_COUNT:
2703 msr_info->data = vcpu->arch.smi_count;
2704 break;
847f0ad8
AG		 2705 case MSR_IA32_PERF_STATUS:
2706 /* TSC increment by tick */
609e36d3 2707 msr_info->data = 1000ULL;
847f0ad8 2708 /* CPU multiplier */
b0996ae4 2709 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2710 break;
15c4a640 2711 case MSR_EFER:
609e36d3 2712 msr_info->data = vcpu->arch.efer;
15c4a640 2713 break;
18068523 2714 case MSR_KVM_WALL_CLOCK:
11c6bffa 2715 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2716 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2717 break;
2718 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2719 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2720 msr_info->data = vcpu->arch.time;
18068523 2721 break;
344d9588 2722 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2723 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2724 break;
c9aaa895 2725 case MSR_KVM_STEAL_TIME:
609e36d3 2726 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2727 break;
1d92128f 2728 case MSR_KVM_PV_EOI_EN:
609e36d3 2729 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2730 break;
890ca9ae
HY		 2731 case MSR_IA32_P5_MC_ADDR:
2732 case MSR_IA32_P5_MC_TYPE:
2733 case MSR_IA32_MCG_CAP:
2734 case MSR_IA32_MCG_CTL:
2735 case MSR_IA32_MCG_STATUS:
81760dcc 2736 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2737 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2738 msr_info->host_initiated);
84e0cefa
JS		 2739 case MSR_K7_CLK_CTL:
2740 /*
2741 * Provide expected ramp-up count for K7. All other
2742 * are set to zero, indicating minimum divisors for
2743 * every field.
2744 *
2745 * This prevents guest kernels on AMD host with CPU
2746 * type 6, model 8 and higher from exploding due to
2747 * the rdmsr failing.
2748 */
609e36d3 2749 msr_info->data = 0x20000000;
84e0cefa 2750 break;
55cd8e5a 2751 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2752 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2753 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2754 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2755 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2756 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2757 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2758 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2759 msr_info->index, &msr_info->data,
2760 msr_info->host_initiated);
55cd8e5a 2761 break;
91c9c3ed 2762 case MSR_IA32_BBL_CR_CTL3:
2763 /* This legacy MSR exists but isn't fully documented in current
2764 * silicon. It is however accessed by winxp in very narrow
2765 * scenarios where it sets bit #19, itself documented as
2766 * a "reserved" bit. Best effort attempt to source coherent
2767 * read data here should the balance of the register be
2768 * interpreted by the guest:
2769 *
2770 * L2 cache control register 3: 64GB range, 256KB size,
2771 * enabled, latency 0x1, configured
2772 */
609e36d3 2773 msr_info->data = 0xbe702111;
91c9c3ed 2774 break;
2b036c6b 2775 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2776 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2777 return 1;
609e36d3 2778 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2779 break;
2780 case MSR_AMD64_OSVW_STATUS:
d6321d49 2781 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2782 return 1;
609e36d3 2783 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2784 break;
db2336a8 2785 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2786 if (!msr_info->host_initiated &&
2787 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2788 return 1;
db2336a8
KH		 2789 msr_info->data = vcpu->arch.msr_platform_info;
2790 break;
2791 case MSR_MISC_FEATURES_ENABLES:
2792 msr_info->data = vcpu->arch.msr_misc_features_enables;
2793 break;
15c4a640 2794 default:
c6702c9d 2795 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2796 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2797 if (!ignore_msrs) {
ae0f5499
BD		 2798 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2799 msr_info->index);
ed85c068
AP		 2800 return 1;
2801 } else {
fab0aa3b
EM		 2802 if (report_ignored_msrs)
2803 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2804 msr_info->index);
609e36d3 2805 msr_info->data = 0;
ed85c068
AP		 2806 }
2807 break;
15c4a640 2808 }
15c4a640
CO		 2809 return 0;
2810}
2811EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2812
313a3dc7
CO		 2813/*
2814 * Read or write a bunch of msrs. All parameters are kernel addresses.
2815 *
2816 * @return number of msrs set successfully.
2817 */
2818static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2819 struct kvm_msr_entry *entries,
2820 int (*do_msr)(struct kvm_vcpu *vcpu,
2821 unsigned index, u64 *data))
2822{
801e459a 2823 int i;
313a3dc7 2824
313a3dc7
CO		 2825 for (i = 0; i < msrs->nmsrs; ++i)
2826 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2827 break;
2828
313a3dc7
CO		 2829 return i;
2830}
2831
2832/*
2833 * Read or write a bunch of msrs. Parameters are user addresses.
2834 *
2835 * @return number of msrs set successfully.
2836 */
2837static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2838 int (*do_msr)(struct kvm_vcpu *vcpu,
2839 unsigned index, u64 *data),
2840 int writeback)
2841{
2842 struct kvm_msrs msrs;
2843 struct kvm_msr_entry *entries;
2844 int r, n;
2845 unsigned size;
2846
2847 r = -EFAULT;
2848 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2849 goto out;
2850
2851 r = -E2BIG;
2852 if (msrs.nmsrs >= MAX_IO_MSRS)
2853 goto out;
2854
313a3dc7 2855 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2856 entries = memdup_user(user_msrs->entries, size);
2857 if (IS_ERR(entries)) {
2858 r = PTR_ERR(entries);
313a3dc7 2859 goto out;
ff5c2c03 2860 }
313a3dc7
CO		 2861
2862 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2863 if (r < 0)
2864 goto out_free;
2865
2866 r = -EFAULT;
2867 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2868 goto out_free;
2869
2870 r = n;
2871
2872out_free:
7a73c028 2873 kfree(entries);
313a3dc7
CO		 2874out:
2875 return r;
2876}
2877
4d5422ce
WL		 2878static inline bool kvm_can_mwait_in_guest(void)
2879{
2880 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2881 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2882 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2883}
2884
784aa3d7 2885int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2886{
4d5422ce 2887 int r = 0;
018d00d2
ZX		 2888
2889 switch (ext) {
2890 case KVM_CAP_IRQCHIP:
2891 case KVM_CAP_HLT:
2892 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2893 case KVM_CAP_SET_TSS_ADDR:
07716717 2894 case KVM_CAP_EXT_CPUID:
9c15bb1d 2895 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2896 case KVM_CAP_CLOCKSOURCE:
7837699f 2897 case KVM_CAP_PIT:
a28e4f5a 2898 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2899 case KVM_CAP_MP_STATE:
ed848624 2900 case KVM_CAP_SYNC_MMU:
a355c85c 2901 case KVM_CAP_USER_NMI:
52d939a0 2902 case KVM_CAP_REINJECT_CONTROL:
4925663a 2903 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2904 case KVM_CAP_IOEVENTFD:
f848a5a8 2905 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2906 case KVM_CAP_PIT2:
e9f42757 2907 case KVM_CAP_PIT_STATE2:
b927a3ce 2908 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2909 case KVM_CAP_XEN_HVM:
3cfc3092 2910 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2911 case KVM_CAP_HYPERV:
10388a07 2912 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2913 case KVM_CAP_HYPERV_SPIN:
5c919412 2914 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2915 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2916 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2917 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 2918 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 2919 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 2920 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
ab9f4ecb 2921 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2922 case KVM_CAP_DEBUGREGS:
d2be1651 2923 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2924 case KVM_CAP_XSAVE:
344d9588 2925 case KVM_CAP_ASYNC_PF:
92a1f12d 2926 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2927 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2928 case KVM_CAP_READONLY_MEM:
5f66b620 2929 case KVM_CAP_HYPERV_TIME:
100943c5 2930 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2931 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2932 case KVM_CAP_ENABLE_CAP_VM:
2933 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2934 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2935 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2936 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2937 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 2938 case KVM_CAP_MSR_PLATFORM_INFO:
018d00d2
ZX		 2939 r = 1;
2940 break;
01643c51
KH		 2941 case KVM_CAP_SYNC_REGS:
2942 r = KVM_SYNC_X86_VALID_FIELDS;
2943 break;
e3fd9a93
PB		 2944 case KVM_CAP_ADJUST_CLOCK:
2945 r = KVM_CLOCK_TSC_STABLE;
2946 break;
4d5422ce 2947 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 2948 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2949 if(kvm_can_mwait_in_guest())
2950 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2951 break;
6d396b55
PB		 2952 case KVM_CAP_X86_SMM:
2953 /* SMBASE is usually relocated above 1M on modern chipsets,
2954 * and SMM handlers might indeed rely on 4G segment limits,
2955 * so do not report SMM to be available if real mode is
2956 * emulated via vm86 mode. Still, do not go to great lengths
2957 * to avoid userspace's usage of the feature, because it is a
2958 * fringe case that is not enabled except via specific settings
2959 * of the module parameters.
2960 */
bc226f07 2961 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 2962 break;
774ead3a
AK		 2963 case KVM_CAP_VAPIC:
2964 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2965 break;
f725230a 2966 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2967 r = KVM_SOFT_MAX_VCPUS;
2968 break;
2969 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2970 r = KVM_MAX_VCPUS;
2971 break;
a988b910 2972 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2973 r = KVM_USER_MEM_SLOTS;
a988b910 2974 break;
a68a6a72
MT		 2975 case KVM_CAP_PV_MMU: /* obsolete */
2976 r = 0;
2f333bcb 2977 break;
890ca9ae
HY		 2978 case KVM_CAP_MCE:
2979 r = KVM_MAX_MCE_BANKS;
2980 break;
2d5b5a66 2981 case KVM_CAP_XCRS:
d366bf7e 2982 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2983 break;
92a1f12d
JR		 2984 case KVM_CAP_TSC_CONTROL:
2985 r = kvm_has_tsc_control;
2986 break;
37131313
RK		 2987 case KVM_CAP_X2APIC_API:
2988 r = KVM_X2APIC_API_VALID_FLAGS;
2989 break;
8fcc4b59
JM		 2990 case KVM_CAP_NESTED_STATE:
2991 r = kvm_x86_ops->get_nested_state ?
2992 kvm_x86_ops->get_nested_state(NULL, 0, 0) : 0;
2993 break;
018d00d2 2994 default:
018d00d2
ZX		 2995 break;
2996 }
2997 return r;
2998
2999}
3000
043405e1
CO		 3001long kvm_arch_dev_ioctl(struct file *filp,
3002 unsigned int ioctl, unsigned long arg)
3003{
3004 void __user *argp = (void __user *)arg;
3005 long r;
3006
3007 switch (ioctl) {
3008 case KVM_GET_MSR_INDEX_LIST: {
3009 struct kvm_msr_list __user *user_msr_list = argp;
3010 struct kvm_msr_list msr_list;
3011 unsigned n;
3012
3013 r = -EFAULT;
3014 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
3015 goto out;
3016 n = msr_list.nmsrs;
62ef68bb 3017 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 3018 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
3019 goto out;
3020 r = -E2BIG;
e125e7b6 3021 if (n < msr_list.nmsrs)
043405e1
CO		 3022 goto out;
3023 r = -EFAULT;
3024 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3025 num_msrs_to_save * sizeof(u32)))
3026 goto out;
e125e7b6 3027 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3028 &emulated_msrs,
62ef68bb 3029 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3030 goto out;
3031 r = 0;
3032 break;
3033 }
9c15bb1d
BP		 3034 case KVM_GET_SUPPORTED_CPUID:
3035 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3036 struct kvm_cpuid2 __user *cpuid_arg = argp;
3037 struct kvm_cpuid2 cpuid;
3038
3039 r = -EFAULT;
3040 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3041 goto out;
9c15bb1d
BP		 3042
3043 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3044 ioctl);
674eea0f
AK		 3045 if (r)
3046 goto out;
3047
3048 r = -EFAULT;
3049 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3050 goto out;
3051 r = 0;
3052 break;
3053 }
890ca9ae 3054 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3055 r = -EFAULT;
c45dcc71
AR		 3056 if (copy_to_user(argp, &kvm_mce_cap_supported,
3057 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3058 goto out;
3059 r = 0;
3060 break;
801e459a
TL		 3061 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3062 struct kvm_msr_list __user *user_msr_list = argp;
3063 struct kvm_msr_list msr_list;
3064 unsigned int n;
3065
3066 r = -EFAULT;
3067 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3068 goto out;
3069 n = msr_list.nmsrs;
3070 msr_list.nmsrs = num_msr_based_features;
3071 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3072 goto out;
3073 r = -E2BIG;
3074 if (n < msr_list.nmsrs)
3075 goto out;
3076 r = -EFAULT;
3077 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3078 num_msr_based_features * sizeof(u32)))
3079 goto out;
3080 r = 0;
3081 break;
3082 }
3083 case KVM_GET_MSRS:
3084 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3085 break;
890ca9ae 3086 }
043405e1
CO		 3087 default:
3088 r = -EINVAL;
3089 }
3090out:
3091 return r;
3092}
3093
f5f48ee1
SY		 3094static void wbinvd_ipi(void *garbage)
3095{
3096 wbinvd();
3097}
3098
3099static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3100{
e0f0bbc5 3101 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3102}
3103
313a3dc7
CO		 3104void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3105{
f5f48ee1
SY		 3106 /* Address WBINVD may be executed by guest */
3107 if (need_emulate_wbinvd(vcpu)) {
3108 if (kvm_x86_ops->has_wbinvd_exit())
3109 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3110 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3111 smp_call_function_single(vcpu->cpu,
3112 wbinvd_ipi, NULL, 1);
3113 }
3114
313a3dc7 3115 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3116
0dd6a6ed
ZA		 3117 /* Apply any externally detected TSC adjustments (due to suspend) */
3118 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3119 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3120 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3121 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3122 }
8f6055cb 3123
b0c39dc6 3124 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3125 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3126 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3127 if (tsc_delta < 0)
3128 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3129
b0c39dc6 3130 if (kvm_check_tsc_unstable()) {
07c1419a 3131 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3132 vcpu->arch.last_guest_tsc);
a545ab6a 3133 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3134 vcpu->arch.tsc_catchup = 1;
c285545f 3135 }
a749e247
PB		 3136
3137 if (kvm_lapic_hv_timer_in_use(vcpu))
3138 kvm_lapic_restart_hv_timer(vcpu);
3139
d98d07ca
MT		 3140 /*
3141 * On a host with synchronized TSC, there is no need to update
3142 * kvmclock on vcpu->cpu migration
3143 */
3144 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3145 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3146 if (vcpu->cpu != cpu)
1bd2009e 3147 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3148 vcpu->cpu = cpu;
6b7d7e76 3149 }
c9aaa895 3150
c9aaa895 3151 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3152}
3153
0b9f6c46
PX		 3154static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3155{
3156 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3157 return;
3158
fa55eedd 3159 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3160
4e335d9e 3161 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3162 &vcpu->arch.st.steal.preempted,
3163 offsetof(struct kvm_steal_time, preempted),
3164 sizeof(vcpu->arch.st.steal.preempted));
3165}
3166
313a3dc7
CO		 3167void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3168{
cc0d907c 3169 int idx;
de63ad4c
LM		 3170
3171 if (vcpu->preempted)
3172 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3173
931f261b
AA		 3174 /*
3175 * Disable page faults because we're in atomic context here.
3176 * kvm_write_guest_offset_cached() would call might_fault()
3177 * that relies on pagefault_disable() to tell if there's a
3178 * bug. NOTE: the write to guest memory may not go through if
3179 * during postcopy live migration or if there's heavy guest
3180 * paging.
3181 */
3182 pagefault_disable();
cc0d907c
AA		 3183 /*
3184 * kvm_memslots() will be called by
3185 * kvm_write_guest_offset_cached() so take the srcu lock.
3186 */
3187 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3188 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3189 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3190 pagefault_enable();
02daab21 3191 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3192 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3193 /*
0e0a53c5
PB		 3194 * Here dr6 is either zero or, if the guest has run and userspace
3195 * has not set any breakpoints or watchpoints, it can be set to
3196 * the guest dr6 (stored in vcpu->arch.dr6). do_debug expects dr6
3197 * to be cleared after it runs, so clear the host register. However,
3198 * MOV to DR can be expensive when running nested, omit it if
3199 * vcpu->arch.dr6 is already zero: in that case, the host dr6 cannot
3200 * currently be nonzero.
efdab992 3201 */
0e0a53c5
PB		 3202 if (vcpu->arch.dr6)
3203 set_debugreg(0, 6);
313a3dc7
CO		 3204}
3205
313a3dc7
CO		 3206static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3207 struct kvm_lapic_state *s)
3208{
fa59cc00 3209 if (vcpu->arch.apicv_active)
d62caabb
AS		 3210 kvm_x86_ops->sync_pir_to_irr(vcpu);
3211
a92e2543 3212 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3213}
3214
3215static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3216 struct kvm_lapic_state *s)
3217{
a92e2543
RK		 3218 int r;
3219
3220 r = kvm_apic_set_state(vcpu, s);
3221 if (r)
3222 return r;
cb142eb7 3223 update_cr8_intercept(vcpu);
313a3dc7
CO		 3224
3225 return 0;
3226}
3227
127a457a
MG		 3228static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3229{
3230 return (!lapic_in_kernel(vcpu) ||
3231 kvm_apic_accept_pic_intr(vcpu));
3232}
3233
782d422b
MG		 3234/*
3235 * if userspace requested an interrupt window, check that the
3236 * interrupt window is open.
3237 *
3238 * No need to exit to userspace if we already have an interrupt queued.
3239 */
3240static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3241{
3242 return kvm_arch_interrupt_allowed(vcpu) &&
3243 !kvm_cpu_has_interrupt(vcpu) &&
3244 !kvm_event_needs_reinjection(vcpu) &&
3245 kvm_cpu_accept_dm_intr(vcpu);
3246}
3247
f77bc6a4
ZX		 3248static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3249 struct kvm_interrupt *irq)
3250{
02cdb50f 3251 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3252 return -EINVAL;
1c1a9ce9
SR		 3253
3254 if (!irqchip_in_kernel(vcpu->kvm)) {
3255 kvm_queue_interrupt(vcpu, irq->irq, false);
3256 kvm_make_request(KVM_REQ_EVENT, vcpu);
3257 return 0;
3258 }
3259
3260 /*
3261 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3262 * fail for in-kernel 8259.
3263 */
3264 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3265 return -ENXIO;
f77bc6a4 3266
1c1a9ce9
SR		 3267 if (vcpu->arch.pending_external_vector != -1)
3268 return -EEXIST;
f77bc6a4 3269
1c1a9ce9 3270 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3271 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3272 return 0;
3273}
3274
c4abb7c9
JK		 3275static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3276{
c4abb7c9 3277 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3278
3279 return 0;
3280}
3281
f077825a
PB		 3282static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3283{
64d60670
PB		 3284 kvm_make_request(KVM_REQ_SMI, vcpu);
3285
f077825a
PB		 3286 return 0;
3287}
3288
b209749f
AK		 3289static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3290 struct kvm_tpr_access_ctl *tac)
3291{
3292 if (tac->flags)
3293 return -EINVAL;
3294 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3295 return 0;
3296}
3297
890ca9ae
HY		 3298static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3299 u64 mcg_cap)
3300{
3301 int r;
3302 unsigned bank_num = mcg_cap & 0xff, bank;
3303
3304 r = -EINVAL;
a9e38c3e 3305 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3306 goto out;
c45dcc71 3307 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3308 goto out;
3309 r = 0;
3310 vcpu->arch.mcg_cap = mcg_cap;
3311 /* Init IA32_MCG_CTL to all 1s */
3312 if (mcg_cap & MCG_CTL_P)
3313 vcpu->arch.mcg_ctl = ~(u64)0;
3314 /* Init IA32_MCi_CTL to all 1s */
3315 for (bank = 0; bank < bank_num; bank++)
3316 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3317
3318 if (kvm_x86_ops->setup_mce)
3319 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3320out:
3321 return r;
3322}
3323
3324static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3325 struct kvm_x86_mce *mce)
3326{
3327 u64 mcg_cap = vcpu->arch.mcg_cap;
3328 unsigned bank_num = mcg_cap & 0xff;
3329 u64 *banks = vcpu->arch.mce_banks;
3330
3331 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3332 return -EINVAL;
3333 /*
3334 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3335 * reporting is disabled
3336 */
3337 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3338 vcpu->arch.mcg_ctl != ~(u64)0)
3339 return 0;
3340 banks += 4 * mce->bank;
3341 /*
3342 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3343 * reporting is disabled for the bank
3344 */
3345 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3346 return 0;
3347 if (mce->status & MCI_STATUS_UC) {
3348 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3349 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3350 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3351 return 0;
3352 }
3353 if (banks[1] & MCI_STATUS_VAL)
3354 mce->status |= MCI_STATUS_OVER;
3355 banks[2] = mce->addr;
3356 banks[3] = mce->misc;
3357 vcpu->arch.mcg_status = mce->mcg_status;
3358 banks[1] = mce->status;
3359 kvm_queue_exception(vcpu, MC_VECTOR);
3360 } else if (!(banks[1] & MCI_STATUS_VAL)
3361 || !(banks[1] & MCI_STATUS_UC)) {
3362 if (banks[1] & MCI_STATUS_VAL)
3363 mce->status |= MCI_STATUS_OVER;
3364 banks[2] = mce->addr;
3365 banks[3] = mce->misc;
3366 banks[1] = mce->status;
3367 } else
3368 banks[1] |= MCI_STATUS_OVER;
3369 return 0;
3370}
3371
3cfc3092
JK		 3372static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3373 struct kvm_vcpu_events *events)
3374{
7460fb4a 3375 process_nmi(vcpu);
59073aaf 3376
664f8e26 3377 /*
59073aaf
JM		 3378 * The API doesn't provide the instruction length for software
3379 * exceptions, so don't report them. As long as the guest RIP
3380 * isn't advanced, we should expect to encounter the exception
3381 * again.
664f8e26 3382 */
59073aaf
JM		 3383 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3384 events->exception.injected = 0;
3385 events->exception.pending = 0;
3386 } else {
3387 events->exception.injected = vcpu->arch.exception.injected;
3388 events->exception.pending = vcpu->arch.exception.pending;
3389 /*
3390 * For ABI compatibility, deliberately conflate
3391 * pending and injected exceptions when
3392 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3393 */
3394 if (!vcpu->kvm->arch.exception_payload_enabled)
3395 events->exception.injected |=
3396 vcpu->arch.exception.pending;
3397 }
3cfc3092
JK		 3398 events->exception.nr = vcpu->arch.exception.nr;
3399 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3400 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3401 events->exception_has_payload = vcpu->arch.exception.has_payload;
3402 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3403
03b82a30 3404 events->interrupt.injected =
04140b41 3405 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3406 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3407 events->interrupt.soft = 0;
37ccdcbe 3408 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3409
3410 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3411 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3412 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3413 events->nmi.pad = 0;
3cfc3092 3414
66450a21 3415 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3416
f077825a
PB		 3417 events->smi.smm = is_smm(vcpu);
3418 events->smi.pending = vcpu->arch.smi_pending;
3419 events->smi.smm_inside_nmi =
3420 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3421 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3422
dab4b911 3423 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3424 | KVM_VCPUEVENT_VALID_SHADOW
3425 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3426 if (vcpu->kvm->arch.exception_payload_enabled)
3427 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3428
97e69aa6 3429 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3430}
3431
6ef4e07e
XG		 3432static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3433
3cfc3092
JK		 3434static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3435 struct kvm_vcpu_events *events)
3436{
dab4b911 3437 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3438 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3439 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3440 | KVM_VCPUEVENT_VALID_SMM
3441 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3442 return -EINVAL;
3443
59073aaf
JM		 3444 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3445 if (!vcpu->kvm->arch.exception_payload_enabled)
3446 return -EINVAL;
3447 if (events->exception.pending)
3448 events->exception.injected = 0;
3449 else
3450 events->exception_has_payload = 0;
3451 } else {
3452 events->exception.pending = 0;
3453 events->exception_has_payload = 0;
3454 }
3455
3456 if ((events->exception.injected || events->exception.pending) &&
3457 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3458 return -EINVAL;
3459
28bf2888
DH		 3460 /* INITs are latched while in SMM */
3461 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3462 (events->smi.smm || events->smi.pending) &&
3463 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3464 return -EINVAL;
3465
7460fb4a 3466 process_nmi(vcpu);
59073aaf
JM		 3467 vcpu->arch.exception.injected = events->exception.injected;
3468 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3469 vcpu->arch.exception.nr = events->exception.nr;
3470 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3471 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3472 vcpu->arch.exception.has_payload = events->exception_has_payload;
3473 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3474
04140b41 3475 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3476 vcpu->arch.interrupt.nr = events->interrupt.nr;
3477 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3478 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3479 kvm_x86_ops->set_interrupt_shadow(vcpu,
3480 events->interrupt.shadow);
3cfc3092
JK		 3481
3482 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3483 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3484 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3485 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3486
66450a21 3487 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3488 lapic_in_kernel(vcpu))
66450a21 3489 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3490
f077825a 3491 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3492 u32 hflags = vcpu->arch.hflags;
f077825a 3493 if (events->smi.smm)
6ef4e07e 3494 hflags |= HF_SMM_MASK;
f077825a 3495 else
6ef4e07e
XG		 3496 hflags &= ~HF_SMM_MASK;
3497 kvm_set_hflags(vcpu, hflags);
3498
f077825a 3499 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3500
3501 if (events->smi.smm) {
3502 if (events->smi.smm_inside_nmi)
3503 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3504 else
f4ef1910
WL		 3505 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3506 if (lapic_in_kernel(vcpu)) {
3507 if (events->smi.latched_init)
3508 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3509 else
3510 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3511 }
f077825a
PB		 3512 }
3513 }
3514
3842d135
AK		 3515 kvm_make_request(KVM_REQ_EVENT, vcpu);
3516
3cfc3092
JK		 3517 return 0;
3518}
3519
a1efbe77
JK		 3520static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3521 struct kvm_debugregs *dbgregs)
3522{
73aaf249
JK		 3523 unsigned long val;
3524
a1efbe77 3525 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3526 kvm_get_dr(vcpu, 6, &val);
73aaf249 3527 dbgregs->dr6 = val;
a1efbe77
JK		 3528 dbgregs->dr7 = vcpu->arch.dr7;
3529 dbgregs->flags = 0;
97e69aa6 3530 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3531}
3532
3533static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3534 struct kvm_debugregs *dbgregs)
3535{
3536 if (dbgregs->flags)
3537 return -EINVAL;
3538
d14bdb55
PB		 3539 if (dbgregs->dr6 & ~0xffffffffull)
3540 return -EINVAL;
3541 if (dbgregs->dr7 & ~0xffffffffull)
3542 return -EINVAL;
3543
a1efbe77 3544 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3545 kvm_update_dr0123(vcpu);
a1efbe77 3546 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3547 kvm_update_dr6(vcpu);
a1efbe77 3548 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3549 kvm_update_dr7(vcpu);
a1efbe77 3550
a1efbe77
JK		 3551 return 0;
3552}
3553
df1daba7
PB		 3554#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3555
3556static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3557{
c47ada30 3558 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3559 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3560 u64 valid;
3561
3562 /*
3563 * Copy legacy XSAVE area, to avoid complications with CPUID
3564 * leaves 0 and 1 in the loop below.
3565 */
3566 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3567
3568 /* Set XSTATE_BV */
00c87e9a 3569 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3570 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3571
3572 /*
3573 * Copy each region from the possibly compacted offset to the
3574 * non-compacted offset.
3575 */
d91cab78 3576 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3577 while (valid) {
3578 u64 feature = valid & -valid;
3579 int index = fls64(feature) - 1;
3580 void *src = get_xsave_addr(xsave, feature);
3581
3582 if (src) {
3583 u32 size, offset, ecx, edx;
3584 cpuid_count(XSTATE_CPUID, index,
3585 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3586 if (feature == XFEATURE_MASK_PKRU)
3587 memcpy(dest + offset, &vcpu->arch.pkru,
3588 sizeof(vcpu->arch.pkru));
3589 else
3590 memcpy(dest + offset, src, size);
3591
df1daba7
PB		 3592 }
3593
3594 valid -= feature;
3595 }
3596}
3597
3598static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3599{
c47ada30 3600 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3601 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3602 u64 valid;
3603
3604 /*
3605 * Copy legacy XSAVE area, to avoid complications with CPUID
3606 * leaves 0 and 1 in the loop below.
3607 */
3608 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3609
3610 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3611 xsave->header.xfeatures = xstate_bv;
782511b0 3612 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3613 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3614
3615 /*
3616 * Copy each region from the non-compacted offset to the
3617 * possibly compacted offset.
3618 */
d91cab78 3619 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3620 while (valid) {
3621 u64 feature = valid & -valid;
3622 int index = fls64(feature) - 1;
3623 void *dest = get_xsave_addr(xsave, feature);
3624
3625 if (dest) {
3626 u32 size, offset, ecx, edx;
3627 cpuid_count(XSTATE_CPUID, index,
3628 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3629 if (feature == XFEATURE_MASK_PKRU)
3630 memcpy(&vcpu->arch.pkru, src + offset,
3631 sizeof(vcpu->arch.pkru));
3632 else
3633 memcpy(dest, src + offset, size);
ee4100da 3634 }
df1daba7
PB		 3635
3636 valid -= feature;
3637 }
3638}
3639
2d5b5a66
SY		 3640static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3641 struct kvm_xsave *guest_xsave)
3642{
d366bf7e 3643 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3644 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3645 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3646 } else {
2d5b5a66 3647 memcpy(guest_xsave->region,
7366ed77 3648 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3649 sizeof(struct fxregs_state));
2d5b5a66 3650 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3651 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3652 }
3653}
3654
a575813b
WL		 3655#define XSAVE_MXCSR_OFFSET 24
3656
2d5b5a66
SY		 3657static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3658 struct kvm_xsave *guest_xsave)
3659{
3660 u64 xstate_bv =
3661 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3662 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3663
d366bf7e 3664 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3665 /*
3666 * Here we allow setting states that are not present in
3667 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3668 * with old userspace.
3669 */
a575813b
WL		 3670 if (xstate_bv & ~kvm_supported_xcr0() ||
3671 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3672 return -EINVAL;
df1daba7 3673 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3674 } else {
a575813b
WL		 3675 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3676 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3677 return -EINVAL;
7366ed77 3678 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3679 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3680 }
3681 return 0;
3682}
3683
3684static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3685 struct kvm_xcrs *guest_xcrs)
3686{
d366bf7e 3687 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3688 guest_xcrs->nr_xcrs = 0;
3689 return;
3690 }
3691
3692 guest_xcrs->nr_xcrs = 1;
3693 guest_xcrs->flags = 0;
3694 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3695 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3696}
3697
3698static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3699 struct kvm_xcrs *guest_xcrs)
3700{
3701 int i, r = 0;
3702
d366bf7e 3703 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3704 return -EINVAL;
3705
3706 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3707 return -EINVAL;
3708
3709 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3710 /* Only support XCR0 currently */
c67a04cb 3711 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3712 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3713 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3714 break;
3715 }
3716 if (r)
3717 r = -EINVAL;
3718 return r;
3719}
3720
1c0b28c2
EM		 3721/*
3722 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3723 * stopped by the hypervisor. This function will be called from the host only.
3724 * EINVAL is returned when the host attempts to set the flag for a guest that
3725 * does not support pv clocks.
3726 */
3727static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3728{
0b79459b 3729 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3730 return -EINVAL;
51d59c6b 3731 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3732 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3733 return 0;
3734}
3735
5c919412
AS		 3736static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3737 struct kvm_enable_cap *cap)
3738{
57b119da
VK		 3739 int r;
3740 uint16_t vmcs_version;
3741 void __user *user_ptr;
3742
5c919412
AS		 3743 if (cap->flags)
3744 return -EINVAL;
3745
3746 switch (cap->cap) {
efc479e6
RK		 3747 case KVM_CAP_HYPERV_SYNIC2:
3748 if (cap->args[0])
3749 return -EINVAL;
5c919412 3750 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3751 if (!irqchip_in_kernel(vcpu->kvm))
3752 return -EINVAL;
efc479e6
RK		 3753 return kvm_hv_activate_synic(vcpu, cap->cap ==
3754 KVM_CAP_HYPERV_SYNIC2);
57b119da
VK		 3755 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3756 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3757 if (!r) {
3758 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3759 if (copy_to_user(user_ptr, &vmcs_version,
3760 sizeof(vmcs_version)))
3761 r = -EFAULT;
3762 }
3763 return r;
3764
5c919412
AS		 3765 default:
3766 return -EINVAL;
3767 }
3768}
3769
313a3dc7
CO		 3770long kvm_arch_vcpu_ioctl(struct file *filp,
3771 unsigned int ioctl, unsigned long arg)
3772{
3773 struct kvm_vcpu *vcpu = filp->private_data;
3774 void __user *argp = (void __user *)arg;
3775 int r;
d1ac91d8
AK		 3776 union {
3777 struct kvm_lapic_state *lapic;
3778 struct kvm_xsave *xsave;
3779 struct kvm_xcrs *xcrs;
3780 void *buffer;
3781 } u;
3782
9b062471
CD		 3783 vcpu_load(vcpu);
3784
d1ac91d8 3785 u.buffer = NULL;
313a3dc7
CO		 3786 switch (ioctl) {
3787 case KVM_GET_LAPIC: {
2204ae3c 3788 r = -EINVAL;
bce87cce 3789 if (!lapic_in_kernel(vcpu))
2204ae3c 3790 goto out;
d1ac91d8 3791 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3792
b772ff36 3793 r = -ENOMEM;
d1ac91d8 3794 if (!u.lapic)
b772ff36 3795 goto out;
d1ac91d8 3796 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3797 if (r)
3798 goto out;
3799 r = -EFAULT;
d1ac91d8 3800 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3801 goto out;
3802 r = 0;
3803 break;
3804 }
3805 case KVM_SET_LAPIC: {
2204ae3c 3806 r = -EINVAL;
bce87cce 3807 if (!lapic_in_kernel(vcpu))
2204ae3c 3808 goto out;
ff5c2c03 3809 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3810 if (IS_ERR(u.lapic)) {
3811 r = PTR_ERR(u.lapic);
3812 goto out_nofree;
3813 }
ff5c2c03 3814
d1ac91d8 3815 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3816 break;
3817 }
f77bc6a4
ZX		 3818 case KVM_INTERRUPT: {
3819 struct kvm_interrupt irq;
3820
3821 r = -EFAULT;
3822 if (copy_from_user(&irq, argp, sizeof irq))
3823 goto out;
3824 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3825 break;
3826 }
c4abb7c9
JK		 3827 case KVM_NMI: {
3828 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3829 break;
3830 }
f077825a
PB		 3831 case KVM_SMI: {
3832 r = kvm_vcpu_ioctl_smi(vcpu);
3833 break;
3834 }
313a3dc7
CO		 3835 case KVM_SET_CPUID: {
3836 struct kvm_cpuid __user *cpuid_arg = argp;
3837 struct kvm_cpuid cpuid;
3838
3839 r = -EFAULT;
3840 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3841 goto out;
3842 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3843 break;
3844 }
07716717
DK		 3845 case KVM_SET_CPUID2: {
3846 struct kvm_cpuid2 __user *cpuid_arg = argp;
3847 struct kvm_cpuid2 cpuid;
3848
3849 r = -EFAULT;
3850 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3851 goto out;
3852 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3853 cpuid_arg->entries);
07716717
DK		 3854 break;
3855 }
3856 case KVM_GET_CPUID2: {
3857 struct kvm_cpuid2 __user *cpuid_arg = argp;
3858 struct kvm_cpuid2 cpuid;
3859
3860 r = -EFAULT;
3861 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3862 goto out;
3863 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3864 cpuid_arg->entries);
07716717
DK		 3865 if (r)
3866 goto out;
3867 r = -EFAULT;
3868 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3869 goto out;
3870 r = 0;
3871 break;
3872 }
801e459a
TL		 3873 case KVM_GET_MSRS: {
3874 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3875 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3876 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3877 break;
801e459a
TL		 3878 }
3879 case KVM_SET_MSRS: {
3880 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3881 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3882 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3883 break;
801e459a 3884 }
b209749f
AK		 3885 case KVM_TPR_ACCESS_REPORTING: {
3886 struct kvm_tpr_access_ctl tac;
3887
3888 r = -EFAULT;
3889 if (copy_from_user(&tac, argp, sizeof tac))
3890 goto out;
3891 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3892 if (r)
3893 goto out;
3894 r = -EFAULT;
3895 if (copy_to_user(argp, &tac, sizeof tac))
3896 goto out;
3897 r = 0;
3898 break;
3899 };
b93463aa
AK		 3900 case KVM_SET_VAPIC_ADDR: {
3901 struct kvm_vapic_addr va;
7301d6ab 3902 int idx;
b93463aa
AK		 3903
3904 r = -EINVAL;
35754c98 3905 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3906 goto out;
3907 r = -EFAULT;
3908 if (copy_from_user(&va, argp, sizeof va))
3909 goto out;
7301d6ab 3910 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3911 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3912 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3913 break;
3914 }
890ca9ae
HY		 3915 case KVM_X86_SETUP_MCE: {
3916 u64 mcg_cap;
3917
3918 r = -EFAULT;
3919 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3920 goto out;
3921 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3922 break;
3923 }
3924 case KVM_X86_SET_MCE: {
3925 struct kvm_x86_mce mce;
3926
3927 r = -EFAULT;
3928 if (copy_from_user(&mce, argp, sizeof mce))
3929 goto out;
3930 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3931 break;
3932 }
3cfc3092
JK		 3933 case KVM_GET_VCPU_EVENTS: {
3934 struct kvm_vcpu_events events;
3935
3936 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3937
3938 r = -EFAULT;
3939 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3940 break;
3941 r = 0;
3942 break;
3943 }
3944 case KVM_SET_VCPU_EVENTS: {
3945 struct kvm_vcpu_events events;
3946
3947 r = -EFAULT;
3948 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3949 break;
3950
3951 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3952 break;
3953 }
a1efbe77
JK		 3954 case KVM_GET_DEBUGREGS: {
3955 struct kvm_debugregs dbgregs;
3956
3957 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3958
3959 r = -EFAULT;
3960 if (copy_to_user(argp, &dbgregs,
3961 sizeof(struct kvm_debugregs)))
3962 break;
3963 r = 0;
3964 break;
3965 }
3966 case KVM_SET_DEBUGREGS: {
3967 struct kvm_debugregs dbgregs;
3968
3969 r = -EFAULT;
3970 if (copy_from_user(&dbgregs, argp,
3971 sizeof(struct kvm_debugregs)))
3972 break;
3973
3974 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3975 break;
3976 }
2d5b5a66 3977 case KVM_GET_XSAVE: {
d1ac91d8 3978 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3979 r = -ENOMEM;
d1ac91d8 3980 if (!u.xsave)
2d5b5a66
SY		 3981 break;
3982
d1ac91d8 3983 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3984
3985 r = -EFAULT;
d1ac91d8 3986 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3987 break;
3988 r = 0;
3989 break;
3990 }
3991 case KVM_SET_XSAVE: {
ff5c2c03 3992 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3993 if (IS_ERR(u.xsave)) {
3994 r = PTR_ERR(u.xsave);
3995 goto out_nofree;
3996 }
2d5b5a66 3997
d1ac91d8 3998 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3999 break;
4000 }
4001 case KVM_GET_XCRS: {
d1ac91d8 4002 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 4003 r = -ENOMEM;
d1ac91d8 4004 if (!u.xcrs)
2d5b5a66
SY		 4005 break;
4006
d1ac91d8 4007 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4008
4009 r = -EFAULT;
d1ac91d8 4010 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4011 sizeof(struct kvm_xcrs)))
4012 break;
4013 r = 0;
4014 break;
4015 }
4016 case KVM_SET_XCRS: {
ff5c2c03 4017 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4018 if (IS_ERR(u.xcrs)) {
4019 r = PTR_ERR(u.xcrs);
4020 goto out_nofree;
4021 }
2d5b5a66 4022
d1ac91d8 4023 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4024 break;
4025 }
92a1f12d
JR		 4026 case KVM_SET_TSC_KHZ: {
4027 u32 user_tsc_khz;
4028
4029 r = -EINVAL;
92a1f12d
JR		 4030 user_tsc_khz = (u32)arg;
4031
4032 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4033 goto out;
4034
cc578287
ZA		 4035 if (user_tsc_khz == 0)
4036 user_tsc_khz = tsc_khz;
4037
381d585c
HZ		 4038 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4039 r = 0;
92a1f12d 4040
92a1f12d
JR		 4041 goto out;
4042 }
4043 case KVM_GET_TSC_KHZ: {
cc578287 4044 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4045 goto out;
4046 }
1c0b28c2
EM		 4047 case KVM_KVMCLOCK_CTRL: {
4048 r = kvm_set_guest_paused(vcpu);
4049 goto out;
4050 }
5c919412
AS		 4051 case KVM_ENABLE_CAP: {
4052 struct kvm_enable_cap cap;
4053
4054 r = -EFAULT;
4055 if (copy_from_user(&cap, argp, sizeof(cap)))
4056 goto out;
4057 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4058 break;
4059 }
8fcc4b59
JM		 4060 case KVM_GET_NESTED_STATE: {
4061 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4062 u32 user_data_size;
4063
4064 r = -EINVAL;
4065 if (!kvm_x86_ops->get_nested_state)
4066 break;
4067
4068 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4069 r = -EFAULT;
8fcc4b59 4070 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4071 break;
8fcc4b59
JM		 4072
4073 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4074 user_data_size);
4075 if (r < 0)
26b471c7 4076 break;
8fcc4b59
JM		 4077
4078 if (r > user_data_size) {
4079 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4080 r = -EFAULT;
4081 else
4082 r = -E2BIG;
4083 break;
8fcc4b59 4084 }
26b471c7 4085
8fcc4b59
JM		 4086 r = 0;
4087 break;
4088 }
4089 case KVM_SET_NESTED_STATE: {
4090 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4091 struct kvm_nested_state kvm_state;
4092
4093 r = -EINVAL;
4094 if (!kvm_x86_ops->set_nested_state)
4095 break;
4096
26b471c7 4097 r = -EFAULT;
8fcc4b59 4098 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4099 break;
8fcc4b59 4100
26b471c7 4101 r = -EINVAL;
8fcc4b59 4102 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4103 break;
8fcc4b59
JM		 4104
4105 if (kvm_state.flags &
8cab6507
VK		 4106 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4107 | KVM_STATE_NESTED_EVMCS))
26b471c7 4108 break;
8fcc4b59
JM		 4109
4110 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4111 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4112 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4113 break;
8fcc4b59
JM		 4114
4115 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4116 break;
4117 }
313a3dc7
CO		 4118 default:
4119 r = -EINVAL;
4120 }
4121out:
d1ac91d8 4122 kfree(u.buffer);
9b062471
CD		 4123out_nofree:
4124 vcpu_put(vcpu);
313a3dc7
CO		 4125 return r;
4126}
4127
1499fa80 4128vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4129{
4130 return VM_FAULT_SIGBUS;
4131}
4132
1fe779f8
CO		 4133static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4134{
4135 int ret;
4136
4137 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4138 return -EINVAL;
1fe779f8
CO		 4139 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4140 return ret;
4141}
4142
b927a3ce
SY		 4143static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4144 u64 ident_addr)
4145{
2ac52ab8 4146 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4147}
4148
1fe779f8
CO		 4149static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4150 u32 kvm_nr_mmu_pages)
4151{
4152 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4153 return -EINVAL;
4154
79fac95e 4155 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4156
4157 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4158 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4159
79fac95e 4160 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4161 return 0;
4162}
4163
4164static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4165{
39de71ec 4166 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4167}
4168
1fe779f8
CO		 4169static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4170{
90bca052 4171 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4172 int r;
4173
4174 r = 0;
4175 switch (chip->chip_id) {
4176 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4177 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4178 sizeof(struct kvm_pic_state));
4179 break;
4180 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4181 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4182 sizeof(struct kvm_pic_state));
4183 break;
4184 case KVM_IRQCHIP_IOAPIC:
33392b49 4185 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4186 break;
4187 default:
4188 r = -EINVAL;
4189 break;
4190 }
4191 return r;
4192}
4193
4194static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4195{
90bca052 4196 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4197 int r;
4198
4199 r = 0;
4200 switch (chip->chip_id) {
4201 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4202 spin_lock(&pic->lock);
4203 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4204 sizeof(struct kvm_pic_state));
90bca052 4205 spin_unlock(&pic->lock);
1fe779f8
CO		 4206 break;
4207 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4208 spin_lock(&pic->lock);
4209 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4210 sizeof(struct kvm_pic_state));
90bca052 4211 spin_unlock(&pic->lock);
1fe779f8
CO		 4212 break;
4213 case KVM_IRQCHIP_IOAPIC:
33392b49 4214 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4215 break;
4216 default:
4217 r = -EINVAL;
4218 break;
4219 }
90bca052 4220 kvm_pic_update_irq(pic);
1fe779f8
CO		 4221 return r;
4222}
4223
e0f63cb9
SY		 4224static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4225{
34f3941c
RK		 4226 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4227
4228 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4229
4230 mutex_lock(&kps->lock);
4231 memcpy(ps, &kps->channels, sizeof(*ps));
4232 mutex_unlock(&kps->lock);
2da29bcc 4233 return 0;
e0f63cb9
SY		 4234}
4235
4236static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4237{
0185604c 4238 int i;
09edea72
RK		 4239 struct kvm_pit *pit = kvm->arch.vpit;
4240
4241 mutex_lock(&pit->pit_state.lock);
34f3941c 4242 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4243 for (i = 0; i < 3; i++)
09edea72
RK		 4244 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4245 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4246 return 0;
e9f42757
BK		 4247}
4248
4249static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4250{
e9f42757
BK		 4251 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4252 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4253 sizeof(ps->channels));
4254 ps->flags = kvm->arch.vpit->pit_state.flags;
4255 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4256 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4257 return 0;
e9f42757
BK		 4258}
4259
4260static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4261{
2da29bcc 4262 int start = 0;
0185604c 4263 int i;
e9f42757 4264 u32 prev_legacy, cur_legacy;
09edea72
RK		 4265 struct kvm_pit *pit = kvm->arch.vpit;
4266
4267 mutex_lock(&pit->pit_state.lock);
4268 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4269 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4270 if (!prev_legacy && cur_legacy)
4271 start = 1;
09edea72
RK		 4272 memcpy(&pit->pit_state.channels, &ps->channels,
4273 sizeof(pit->pit_state.channels));
4274 pit->pit_state.flags = ps->flags;
0185604c 4275 for (i = 0; i < 3; i++)
09edea72 4276 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4277 start && i == 0);
09edea72 4278 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4279 return 0;
e0f63cb9
SY		 4280}
4281
52d939a0
MT		 4282static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4283 struct kvm_reinject_control *control)
4284{
71474e2f
RK		 4285 struct kvm_pit *pit = kvm->arch.vpit;
4286
4287 if (!pit)
52d939a0 4288 return -ENXIO;
b39c90b6 4289
71474e2f
RK		 4290 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4291 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4292 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4293 */
4294 mutex_lock(&pit->pit_state.lock);
4295 kvm_pit_set_reinject(pit, control->pit_reinject);
4296 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4297
52d939a0
MT		 4298 return 0;
4299}
4300
95d4c16c 4301/**
60c34612
TY		 4302 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4303 * @kvm: kvm instance
4304 * @log: slot id and address to which we copy the log
95d4c16c 4305 *
e108ff2f
PB		 4306 * Steps 1-4 below provide general overview of dirty page logging. See
4307 * kvm_get_dirty_log_protect() function description for additional details.
4308 *
4309 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4310 * always flush the TLB (step 4) even if previous step failed and the dirty
4311 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4312 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4313 * writes will be marked dirty for next log read.
95d4c16c 4314 *
60c34612
TY		 4315 * 1. Take a snapshot of the bit and clear it if needed.
4316 * 2. Write protect the corresponding page.
e108ff2f
PB		 4317 * 3. Copy the snapshot to the userspace.
4318 * 4. Flush TLB's if needed.
5bb064dc 4319 */
60c34612 4320int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4321{
60c34612 4322 bool is_dirty = false;
e108ff2f 4323 int r;
5bb064dc 4324
79fac95e 4325 mutex_lock(&kvm->slots_lock);
5bb064dc 4326
88178fd4
KH		 4327 /*
4328 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4329 */
4330 if (kvm_x86_ops->flush_log_dirty)
4331 kvm_x86_ops->flush_log_dirty(kvm);
4332
e108ff2f 4333 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4334
4335 /*
4336 * All the TLBs can be flushed out of mmu lock, see the comments in
4337 * kvm_mmu_slot_remove_write_access().
4338 */
e108ff2f 4339 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4340 if (is_dirty)
4341 kvm_flush_remote_tlbs(kvm);
4342
79fac95e 4343 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4344 return r;
4345}
4346
aa2fbe6d
YZ		 4347int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4348 bool line_status)
23d43cf9
CD		 4349{
4350 if (!irqchip_in_kernel(kvm))
4351 return -ENXIO;
4352
4353 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4354 irq_event->irq, irq_event->level,
4355 line_status);
23d43cf9
CD		 4356 return 0;
4357}
4358
90de4a18
NA		 4359static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4360 struct kvm_enable_cap *cap)
4361{
4362 int r;
4363
4364 if (cap->flags)
4365 return -EINVAL;
4366
4367 switch (cap->cap) {
4368 case KVM_CAP_DISABLE_QUIRKS:
4369 kvm->arch.disabled_quirks = cap->args[0];
4370 r = 0;
4371 break;
49df6397
SR		 4372 case KVM_CAP_SPLIT_IRQCHIP: {
4373 mutex_lock(&kvm->lock);
b053b2ae
SR		 4374 r = -EINVAL;
4375 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4376 goto split_irqchip_unlock;
49df6397
SR		 4377 r = -EEXIST;
4378 if (irqchip_in_kernel(kvm))
4379 goto split_irqchip_unlock;
557abc40 4380 if (kvm->created_vcpus)
49df6397
SR		 4381 goto split_irqchip_unlock;
4382 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4383 if (r)
49df6397
SR		 4384 goto split_irqchip_unlock;
4385 /* Pairs with irqchip_in_kernel. */
4386 smp_wmb();
49776faf 4387 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4388 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4389 r = 0;
4390split_irqchip_unlock:
4391 mutex_unlock(&kvm->lock);
4392 break;
4393 }
37131313
RK		 4394 case KVM_CAP_X2APIC_API:
4395 r = -EINVAL;
4396 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4397 break;
4398
4399 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4400 kvm->arch.x2apic_format = true;
c519265f
RK		 4401 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4402 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4403
4404 r = 0;
4405 break;
4d5422ce
WL		 4406 case KVM_CAP_X86_DISABLE_EXITS:
4407 r = -EINVAL;
4408 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4409 break;
4410
4411 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4412 kvm_can_mwait_in_guest())
4413 kvm->arch.mwait_in_guest = true;
766d3571 4414 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4415 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4416 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4417 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4418 r = 0;
4419 break;
6fbbde9a
DS		 4420 case KVM_CAP_MSR_PLATFORM_INFO:
4421 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4422 r = 0;
4423 break;
90de4a18
NA		 4424 default:
4425 r = -EINVAL;
4426 break;
4427 }
4428 return r;
4429}
4430
1fe779f8
CO		 4431long kvm_arch_vm_ioctl(struct file *filp,
4432 unsigned int ioctl, unsigned long arg)
4433{
4434 struct kvm *kvm = filp->private_data;
4435 void __user *argp = (void __user *)arg;
367e1319 4436 int r = -ENOTTY;
f0d66275
DH		 4437 /*
4438 * This union makes it completely explicit to gcc-3.x
4439 * that these two variables' stack usage should be
4440 * combined, not added together.
4441 */
4442 union {
4443 struct kvm_pit_state ps;
e9f42757 4444 struct kvm_pit_state2 ps2;
c5ff41ce 4445 struct kvm_pit_config pit_config;
f0d66275 4446 } u;
1fe779f8
CO		 4447
4448 switch (ioctl) {
4449 case KVM_SET_TSS_ADDR:
4450 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4451 break;
b927a3ce
SY		 4452 case KVM_SET_IDENTITY_MAP_ADDR: {
4453 u64 ident_addr;
4454
1af1ac91
DH		 4455 mutex_lock(&kvm->lock);
4456 r = -EINVAL;
4457 if (kvm->created_vcpus)
4458 goto set_identity_unlock;
b927a3ce
SY		 4459 r = -EFAULT;
4460 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4461 goto set_identity_unlock;
b927a3ce 4462 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4463set_identity_unlock:
4464 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4465 break;
4466 }
1fe779f8
CO		 4467 case KVM_SET_NR_MMU_PAGES:
4468 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4469 break;
4470 case KVM_GET_NR_MMU_PAGES:
4471 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4472 break;
3ddea128 4473 case KVM_CREATE_IRQCHIP: {
3ddea128 4474 mutex_lock(&kvm->lock);
09941366 4475
3ddea128 4476 r = -EEXIST;
35e6eaa3 4477 if (irqchip_in_kernel(kvm))
3ddea128 4478 goto create_irqchip_unlock;
09941366 4479
3e515705 4480 r = -EINVAL;
557abc40 4481 if (kvm->created_vcpus)
3e515705 4482 goto create_irqchip_unlock;
09941366
RK		 4483
4484 r = kvm_pic_init(kvm);
4485 if (r)
3ddea128 4486 goto create_irqchip_unlock;
09941366
RK		 4487
4488 r = kvm_ioapic_init(kvm);
4489 if (r) {
09941366 4490 kvm_pic_destroy(kvm);
3ddea128 4491 goto create_irqchip_unlock;
09941366
RK		 4492 }
4493
399ec807
AK		 4494 r = kvm_setup_default_irq_routing(kvm);
4495 if (r) {
72bb2fcd 4496 kvm_ioapic_destroy(kvm);
09941366 4497 kvm_pic_destroy(kvm);
71ba994c 4498 goto create_irqchip_unlock;
399ec807 4499 }
49776faf 4500 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4501 smp_wmb();
49776faf 4502 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4503 create_irqchip_unlock:
4504 mutex_unlock(&kvm->lock);
1fe779f8 4505 break;
3ddea128 4506 }
7837699f 4507 case KVM_CREATE_PIT:
c5ff41ce
JK		 4508 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4509 goto create_pit;
4510 case KVM_CREATE_PIT2:
4511 r = -EFAULT;
4512 if (copy_from_user(&u.pit_config, argp,
4513 sizeof(struct kvm_pit_config)))
4514 goto out;
4515 create_pit:
250715a6 4516 mutex_lock(&kvm->lock);
269e05e4
AK		 4517 r = -EEXIST;
4518 if (kvm->arch.vpit)
4519 goto create_pit_unlock;
7837699f 4520 r = -ENOMEM;
c5ff41ce 4521 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4522 if (kvm->arch.vpit)
4523 r = 0;
269e05e4 4524 create_pit_unlock:
250715a6 4525 mutex_unlock(&kvm->lock);
7837699f 4526 break;
1fe779f8
CO		 4527 case KVM_GET_IRQCHIP: {
4528 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4529 struct kvm_irqchip *chip;
1fe779f8 4530
ff5c2c03
SL		 4531 chip = memdup_user(argp, sizeof(*chip));
4532 if (IS_ERR(chip)) {
4533 r = PTR_ERR(chip);
1fe779f8 4534 goto out;
ff5c2c03
SL		 4535 }
4536
1fe779f8 4537 r = -ENXIO;
826da321 4538 if (!irqchip_kernel(kvm))
f0d66275
DH		 4539 goto get_irqchip_out;
4540 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4541 if (r)
f0d66275 4542 goto get_irqchip_out;
1fe779f8 4543 r = -EFAULT;
f0d66275
DH		 4544 if (copy_to_user(argp, chip, sizeof *chip))
4545 goto get_irqchip_out;
1fe779f8 4546 r = 0;
f0d66275
DH		 4547 get_irqchip_out:
4548 kfree(chip);
1fe779f8
CO		 4549 break;
4550 }
4551 case KVM_SET_IRQCHIP: {
4552 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4553 struct kvm_irqchip *chip;
1fe779f8 4554
ff5c2c03
SL		 4555 chip = memdup_user(argp, sizeof(*chip));
4556 if (IS_ERR(chip)) {
4557 r = PTR_ERR(chip);
1fe779f8 4558 goto out;
ff5c2c03
SL		 4559 }
4560
1fe779f8 4561 r = -ENXIO;
826da321 4562 if (!irqchip_kernel(kvm))
f0d66275
DH		 4563 goto set_irqchip_out;
4564 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4565 if (r)
f0d66275 4566 goto set_irqchip_out;
1fe779f8 4567 r = 0;
f0d66275
DH		 4568 set_irqchip_out:
4569 kfree(chip);
1fe779f8
CO		 4570 break;
4571 }
e0f63cb9 4572 case KVM_GET_PIT: {
e0f63cb9 4573 r = -EFAULT;
f0d66275 4574 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4575 goto out;
4576 r = -ENXIO;
4577 if (!kvm->arch.vpit)
4578 goto out;
f0d66275 4579 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4580 if (r)
4581 goto out;
4582 r = -EFAULT;
f0d66275 4583 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4584 goto out;
4585 r = 0;
4586 break;
4587 }
4588 case KVM_SET_PIT: {
e0f63cb9 4589 r = -EFAULT;
f0d66275 4590 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4591 goto out;
4592 r = -ENXIO;
4593 if (!kvm->arch.vpit)
4594 goto out;
f0d66275 4595 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4596 break;
4597 }
e9f42757
BK		 4598 case KVM_GET_PIT2: {
4599 r = -ENXIO;
4600 if (!kvm->arch.vpit)
4601 goto out;
4602 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4603 if (r)
4604 goto out;
4605 r = -EFAULT;
4606 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4607 goto out;
4608 r = 0;
4609 break;
4610 }
4611 case KVM_SET_PIT2: {
4612 r = -EFAULT;
4613 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4614 goto out;
4615 r = -ENXIO;
4616 if (!kvm->arch.vpit)
4617 goto out;
4618 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4619 break;
4620 }
52d939a0
MT		 4621 case KVM_REINJECT_CONTROL: {
4622 struct kvm_reinject_control control;
4623 r = -EFAULT;
4624 if (copy_from_user(&control, argp, sizeof(control)))
4625 goto out;
4626 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4627 break;
4628 }
d71ba788
PB		 4629 case KVM_SET_BOOT_CPU_ID:
4630 r = 0;
4631 mutex_lock(&kvm->lock);
557abc40 4632 if (kvm->created_vcpus)
d71ba788
PB		 4633 r = -EBUSY;
4634 else
4635 kvm->arch.bsp_vcpu_id = arg;
4636 mutex_unlock(&kvm->lock);
4637 break;
ffde22ac 4638 case KVM_XEN_HVM_CONFIG: {
51776043 4639 struct kvm_xen_hvm_config xhc;
ffde22ac 4640 r = -EFAULT;
51776043 4641 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4642 goto out;
4643 r = -EINVAL;
51776043 4644 if (xhc.flags)
ffde22ac 4645 goto out;
51776043 4646 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4647 r = 0;
4648 break;
4649 }
afbcf7ab 4650 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4651 struct kvm_clock_data user_ns;
4652 u64 now_ns;
afbcf7ab
GC		 4653
4654 r = -EFAULT;
4655 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4656 goto out;
4657
4658 r = -EINVAL;
4659 if (user_ns.flags)
4660 goto out;
4661
4662 r = 0;
0bc48bea
RK		 4663 /*
4664 * TODO: userspace has to take care of races with VCPU_RUN, so
4665 * kvm_gen_update_masterclock() can be cut down to locked
4666 * pvclock_update_vm_gtod_copy().
4667 */
4668 kvm_gen_update_masterclock(kvm);
e891a32e 4669 now_ns = get_kvmclock_ns(kvm);
108b249c 4670 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4671 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4672 break;
4673 }
4674 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4675 struct kvm_clock_data user_ns;
4676 u64 now_ns;
4677
e891a32e 4678 now_ns = get_kvmclock_ns(kvm);
108b249c 4679 user_ns.clock = now_ns;
e3fd9a93 4680 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4681 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4682
4683 r = -EFAULT;
4684 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4685 goto out;
4686 r = 0;
4687 break;
4688 }
90de4a18
NA		 4689 case KVM_ENABLE_CAP: {
4690 struct kvm_enable_cap cap;
afbcf7ab 4691
90de4a18
NA		 4692 r = -EFAULT;
4693 if (copy_from_user(&cap, argp, sizeof(cap)))
4694 goto out;
4695 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4696 break;
4697 }
5acc5c06
BS		 4698 case KVM_MEMORY_ENCRYPT_OP: {
4699 r = -ENOTTY;
4700 if (kvm_x86_ops->mem_enc_op)
4701 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4702 break;
4703 }
69eaedee
BS		 4704 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4705 struct kvm_enc_region region;
4706
4707 r = -EFAULT;
4708 if (copy_from_user(&region, argp, sizeof(region)))
4709 goto out;
4710
4711 r = -ENOTTY;
4712 if (kvm_x86_ops->mem_enc_reg_region)
4713 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4714 break;
4715 }
4716 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4717 struct kvm_enc_region region;
4718
4719 r = -EFAULT;
4720 if (copy_from_user(&region, argp, sizeof(region)))
4721 goto out;
4722
4723 r = -ENOTTY;
4724 if (kvm_x86_ops->mem_enc_unreg_region)
4725 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4726 break;
4727 }
faeb7833
RK		 4728 case KVM_HYPERV_EVENTFD: {
4729 struct kvm_hyperv_eventfd hvevfd;
4730
4731 r = -EFAULT;
4732 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4733 goto out;
4734 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4735 break;
4736 }
1fe779f8 4737 default:
ad6260da 4738 r = -ENOTTY;
1fe779f8
CO		 4739 }
4740out:
4741 return r;
4742}
4743
a16b043c 4744static void kvm_init_msr_list(void)
043405e1
CO		 4745{
4746 u32 dummy[2];
4747 unsigned i, j;
4748
62ef68bb 4749 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4750 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4751 continue;
93c4adc7
PB		 4752
4753 /*
4754 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4755 * to the guests in some cases.
93c4adc7
PB		 4756 */
4757 switch (msrs_to_save[i]) {
4758 case MSR_IA32_BNDCFGS:
503234b3 4759 if (!kvm_mpx_supported())
93c4adc7
PB		 4760 continue;
4761 break;
9dbe6cf9
PB		 4762 case MSR_TSC_AUX:
4763 if (!kvm_x86_ops->rdtscp_supported())
4764 continue;
4765 break;
93c4adc7
PB		 4766 default:
4767 break;
4768 }
4769
043405e1
CO		 4770 if (j < i)
4771 msrs_to_save[j] = msrs_to_save[i];
4772 j++;
4773 }
4774 num_msrs_to_save = j;
62ef68bb
PB		 4775
4776 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4777 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4778 continue;
62ef68bb
PB		 4779
4780 if (j < i)
4781 emulated_msrs[j] = emulated_msrs[i];
4782 j++;
4783 }
4784 num_emulated_msrs = j;
801e459a
TL		 4785
4786 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4787 struct kvm_msr_entry msr;
4788
4789 msr.index = msr_based_features[i];
66421c1e 4790 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4791 continue;
4792
4793 if (j < i)
4794 msr_based_features[j] = msr_based_features[i];
4795 j++;
4796 }
4797 num_msr_based_features = j;
043405e1
CO		 4798}
4799
bda9020e
MT		 4800static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4801 const void *v)
bbd9b64e 4802{
70252a10
AK		 4803 int handled = 0;
4804 int n;
4805
4806 do {
4807 n = min(len, 8);
bce87cce 4808 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4809 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4810 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4811 break;
4812 handled += n;
4813 addr += n;
4814 len -= n;
4815 v += n;
4816 } while (len);
bbd9b64e 4817
70252a10 4818 return handled;
bbd9b64e
CO		 4819}
4820
bda9020e 4821static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4822{
70252a10
AK		 4823 int handled = 0;
4824 int n;
4825
4826 do {
4827 n = min(len, 8);
bce87cce 4828 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4829 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4830 addr, n, v))
4831 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4832 break;
e39d200f 4833 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4834 handled += n;
4835 addr += n;
4836 len -= n;
4837 v += n;
4838 } while (len);
bbd9b64e 4839
70252a10 4840 return handled;
bbd9b64e
CO		 4841}
4842
2dafc6c2
GN		 4843static void kvm_set_segment(struct kvm_vcpu *vcpu,
4844 struct kvm_segment *var, int seg)
4845{
4846 kvm_x86_ops->set_segment(vcpu, var, seg);
4847}
4848
4849void kvm_get_segment(struct kvm_vcpu *vcpu,
4850 struct kvm_segment *var, int seg)
4851{
4852 kvm_x86_ops->get_segment(vcpu, var, seg);
4853}
4854
54987b7a
PB		 4855gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4856 struct x86_exception *exception)
02f59dc9
JR		 4857{
4858 gpa_t t_gpa;
02f59dc9
JR		 4859
4860 BUG_ON(!mmu_is_nested(vcpu));
4861
4862 /* NPT walks are always user-walks */
4863 access |= PFERR_USER_MASK;
44dd3ffa 4864 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4865
4866 return t_gpa;
4867}
4868
ab9ae313
AK		 4869gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4870 struct x86_exception *exception)
1871c602
GN		 4871{
4872 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4873 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4874}
4875
ab9ae313
AK		 4876 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4877 struct x86_exception *exception)
1871c602
GN		 4878{
4879 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4880 access |= PFERR_FETCH_MASK;
ab9ae313 4881 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4882}
4883
ab9ae313
AK		 4884gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4885 struct x86_exception *exception)
1871c602
GN		 4886{
4887 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4888 access |= PFERR_WRITE_MASK;
ab9ae313 4889 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4890}
4891
4892/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4893gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4894 struct x86_exception *exception)
1871c602 4895{
ab9ae313 4896 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4897}
4898
4899static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4900 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4901 struct x86_exception *exception)
bbd9b64e
CO		 4902{
4903 void *data = val;
10589a46 4904 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4905
4906 while (bytes) {
14dfe855 4907 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4908 exception);
bbd9b64e 4909 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4910 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4911 int ret;
4912
bcc55cba 4913 if (gpa == UNMAPPED_GVA)
ab9ae313 4914 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4915 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4916 offset, toread);
10589a46 4917 if (ret < 0) {
c3cd7ffa 4918 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4919 goto out;
4920 }
bbd9b64e 4921
77c2002e
IE		 4922 bytes -= toread;
4923 data += toread;
4924 addr += toread;
bbd9b64e 4925 }
10589a46 4926out:
10589a46 4927 return r;
bbd9b64e 4928}
77c2002e 4929
1871c602 4930/* used for instruction fetching */
0f65dd70
AK		 4931static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4932 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4933 struct x86_exception *exception)
1871c602 4934{
0f65dd70 4935 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4936 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4937 unsigned offset;
4938 int ret;
0f65dd70 4939
44583cba
PB		 4940 /* Inline kvm_read_guest_virt_helper for speed. */
4941 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4942 exception);
4943 if (unlikely(gpa == UNMAPPED_GVA))
4944 return X86EMUL_PROPAGATE_FAULT;
4945
4946 offset = addr & (PAGE_SIZE-1);
4947 if (WARN_ON(offset + bytes > PAGE_SIZE))
4948 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4949 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4950 offset, bytes);
44583cba
PB		 4951 if (unlikely(ret < 0))
4952 return X86EMUL_IO_NEEDED;
4953
4954 return X86EMUL_CONTINUE;
1871c602
GN		 4955}
4956
ce14e868 4957int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 4958 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4959 struct x86_exception *exception)
1871c602
GN		 4960{
4961 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4962
1871c602 4963 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4964 exception);
1871c602 4965}
064aea77 4966EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4967
ce14e868
PB		 4968static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
4969 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 4970 struct x86_exception *exception, bool system)
1871c602 4971{
0f65dd70 4972 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 4973 u32 access = 0;
4974
4975 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4976 access |= PFERR_USER_MASK;
4977
4978 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 4979}
4980
7a036a6f
RK		 4981static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4982 unsigned long addr, void *val, unsigned int bytes)
4983{
4984 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4985 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4986
4987 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4988}
4989
ce14e868
PB		 4990static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4991 struct kvm_vcpu *vcpu, u32 access,
4992 struct x86_exception *exception)
77c2002e
IE		 4993{
4994 void *data = val;
4995 int r = X86EMUL_CONTINUE;
4996
4997 while (bytes) {
14dfe855 4998 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 4999 access,
ab9ae313 5000 exception);
77c2002e
IE		 5001 unsigned offset = addr & (PAGE_SIZE-1);
5002 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5003 int ret;
5004
bcc55cba 5005 if (gpa == UNMAPPED_GVA)
ab9ae313 5006 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5007 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5008 if (ret < 0) {
c3cd7ffa 5009 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5010 goto out;
5011 }
5012
5013 bytes -= towrite;
5014 data += towrite;
5015 addr += towrite;
5016 }
5017out:
5018 return r;
5019}
ce14e868
PB		 5020
5021static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5022 unsigned int bytes, struct x86_exception *exception,
5023 bool system)
ce14e868
PB		 5024{
5025 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5026 u32 access = PFERR_WRITE_MASK;
5027
5028 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5029 access |= PFERR_USER_MASK;
ce14e868
PB		 5030
5031 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5032 access, exception);
ce14e868
PB		 5033}
5034
5035int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5036 unsigned int bytes, struct x86_exception *exception)
5037{
c595ceee
PB		 5038 /* kvm_write_guest_virt_system can pull in tons of pages. */
5039 vcpu->arch.l1tf_flush_l1d = true;
5040
ce14e868
PB		 5041 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5042 PFERR_WRITE_MASK, exception);
5043}
6a4d7550 5044EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5045
082d06ed
WL		 5046int handle_ud(struct kvm_vcpu *vcpu)
5047{
6c86eedc 5048 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5049 enum emulation_result er;
6c86eedc
WL		 5050 char sig[5]; /* ud2; .ascii "kvm" */
5051 struct x86_exception e;
5052
5053 if (force_emulation_prefix &&
3c9fa24c
PB		 5054 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5055 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5056 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5057 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5058 emul_type = 0;
5059 }
082d06ed 5060
0ce97a2b 5061 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5062 if (er == EMULATE_USER_EXIT)
5063 return 0;
5064 if (er != EMULATE_DONE)
5065 kvm_queue_exception(vcpu, UD_VECTOR);
5066 return 1;
5067}
5068EXPORT_SYMBOL_GPL(handle_ud);
5069
0f89b207
TL		 5070static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5071 gpa_t gpa, bool write)
5072{
5073 /* For APIC access vmexit */
5074 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5075 return 1;
5076
5077 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5078 trace_vcpu_match_mmio(gva, gpa, write, true);
5079 return 1;
5080 }
5081
5082 return 0;
5083}
5084
af7cc7d1
XG		 5085static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5086 gpa_t *gpa, struct x86_exception *exception,
5087 bool write)
5088{
97d64b78
AK		 5089 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5090 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5091
be94f6b7
HH		 5092 /*
5093 * currently PKRU is only applied to ept enabled guest so
5094 * there is no pkey in EPT page table for L1 guest or EPT
5095 * shadow page table for L2 guest.
5096 */
97d64b78 5097 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5098 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5099 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5100 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5101 (gva & (PAGE_SIZE - 1));
4f022648 5102 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5103 return 1;
5104 }
5105
af7cc7d1
XG		 5106 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5107
5108 if (*gpa == UNMAPPED_GVA)
5109 return -1;
5110
0f89b207 5111 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5112}
5113
3200f405 5114int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5115 const void *val, int bytes)
bbd9b64e
CO		 5116{
5117 int ret;
5118
54bf36aa 5119 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5120 if (ret < 0)
bbd9b64e 5121 return 0;
0eb05bf2 5122 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5123 return 1;
5124}
5125
77d197b2
XG		 5126struct read_write_emulator_ops {
5127 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5128 int bytes);
5129 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5130 void *val, int bytes);
5131 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5132 int bytes, void *val);
5133 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5134 void *val, int bytes);
5135 bool write;
5136};
5137
5138static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5139{
5140 if (vcpu->mmio_read_completed) {
77d197b2 5141 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5142 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5143 vcpu->mmio_read_completed = 0;
5144 return 1;
5145 }
5146
5147 return 0;
5148}
5149
5150static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5151 void *val, int bytes)
5152{
54bf36aa 5153 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5154}
5155
5156static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5157 void *val, int bytes)
5158{
5159 return emulator_write_phys(vcpu, gpa, val, bytes);
5160}
5161
5162static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5163{
e39d200f 5164 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5165 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5166}
5167
5168static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5169 void *val, int bytes)
5170{
e39d200f 5171 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5172 return X86EMUL_IO_NEEDED;
5173}
5174
5175static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5176 void *val, int bytes)
5177{
f78146b0
AK		 5178 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5179
87da7e66 5180 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5181 return X86EMUL_CONTINUE;
5182}
5183
0fbe9b0b 5184static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5185 .read_write_prepare = read_prepare,
5186 .read_write_emulate = read_emulate,
5187 .read_write_mmio = vcpu_mmio_read,
5188 .read_write_exit_mmio = read_exit_mmio,
5189};
5190
0fbe9b0b 5191static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5192 .read_write_emulate = write_emulate,
5193 .read_write_mmio = write_mmio,
5194 .read_write_exit_mmio = write_exit_mmio,
5195 .write = true,
5196};
5197
22388a3c
XG		 5198static int emulator_read_write_onepage(unsigned long addr, void *val,
5199 unsigned int bytes,
5200 struct x86_exception *exception,
5201 struct kvm_vcpu *vcpu,
0fbe9b0b 5202 const struct read_write_emulator_ops *ops)
bbd9b64e 5203{
af7cc7d1
XG		 5204 gpa_t gpa;
5205 int handled, ret;
22388a3c 5206 bool write = ops->write;
f78146b0 5207 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5208 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5209
5210 /*
5211 * If the exit was due to a NPF we may already have a GPA.
5212 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5213 * Note, this cannot be used on string operations since string
5214 * operation using rep will only have the initial GPA from the NPF
5215 * occurred.
5216 */
5217 if (vcpu->arch.gpa_available &&
5218 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5219 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5220 gpa = vcpu->arch.gpa_val;
5221 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5222 } else {
5223 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5224 if (ret < 0)
5225 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5226 }
10589a46 5227
618232e2 5228 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5229 return X86EMUL_CONTINUE;
5230
bbd9b64e
CO		 5231 /*
5232 * Is this MMIO handled locally?
5233 */
22388a3c 5234 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5235 if (handled == bytes)
bbd9b64e 5236 return X86EMUL_CONTINUE;
bbd9b64e 5237
70252a10
AK		 5238 gpa += handled;
5239 bytes -= handled;
5240 val += handled;
5241
87da7e66
XG		 5242 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5243 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5244 frag->gpa = gpa;
5245 frag->data = val;
5246 frag->len = bytes;
f78146b0 5247 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5248}
5249
52eb5a6d
XL		 5250static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5251 unsigned long addr,
22388a3c
XG		 5252 void *val, unsigned int bytes,
5253 struct x86_exception *exception,
0fbe9b0b 5254 const struct read_write_emulator_ops *ops)
bbd9b64e 5255{
0f65dd70 5256 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5257 gpa_t gpa;
5258 int rc;
5259
5260 if (ops->read_write_prepare &&
5261 ops->read_write_prepare(vcpu, val, bytes))
5262 return X86EMUL_CONTINUE;
5263
5264 vcpu->mmio_nr_fragments = 0;
0f65dd70 5265
bbd9b64e
CO		 5266 /* Crossing a page boundary? */
5267 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5268 int now;
bbd9b64e
CO		 5269
5270 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5271 rc = emulator_read_write_onepage(addr, val, now, exception,
5272 vcpu, ops);
5273
bbd9b64e
CO		 5274 if (rc != X86EMUL_CONTINUE)
5275 return rc;
5276 addr += now;
bac15531
NA		 5277 if (ctxt->mode != X86EMUL_MODE_PROT64)
5278 addr = (u32)addr;
bbd9b64e
CO		 5279 val += now;
5280 bytes -= now;
5281 }
22388a3c 5282
f78146b0
AK		 5283 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5284 vcpu, ops);
5285 if (rc != X86EMUL_CONTINUE)
5286 return rc;
5287
5288 if (!vcpu->mmio_nr_fragments)
5289 return rc;
5290
5291 gpa = vcpu->mmio_fragments[0].gpa;
5292
5293 vcpu->mmio_needed = 1;
5294 vcpu->mmio_cur_fragment = 0;
5295
87da7e66 5296 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5297 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5298 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5299 vcpu->run->mmio.phys_addr = gpa;
5300
5301 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5302}
5303
5304static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5305 unsigned long addr,
5306 void *val,
5307 unsigned int bytes,
5308 struct x86_exception *exception)
5309{
5310 return emulator_read_write(ctxt, addr, val, bytes,
5311 exception, &read_emultor);
5312}
5313
52eb5a6d 5314static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5315 unsigned long addr,
5316 const void *val,
5317 unsigned int bytes,
5318 struct x86_exception *exception)
5319{
5320 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5321 exception, &write_emultor);
bbd9b64e 5322}
bbd9b64e 5323
daea3e73
AK		 5324#define CMPXCHG_TYPE(t, ptr, old, new) \
5325 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5326
5327#ifdef CONFIG_X86_64
5328# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5329#else
5330# define CMPXCHG64(ptr, old, new) \
9749a6c0 5331 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5332#endif
5333
0f65dd70
AK		 5334static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5335 unsigned long addr,
bbd9b64e
CO		 5336 const void *old,
5337 const void *new,
5338 unsigned int bytes,
0f65dd70 5339 struct x86_exception *exception)
bbd9b64e 5340{
0f65dd70 5341 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5342 gpa_t gpa;
5343 struct page *page;
5344 char *kaddr;
5345 bool exchanged;
2bacc55c 5346
daea3e73
AK		 5347 /* guests cmpxchg8b have to be emulated atomically */
5348 if (bytes > 8 || (bytes & (bytes - 1)))
5349 goto emul_write;
10589a46 5350
daea3e73 5351 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5352
daea3e73
AK		 5353 if (gpa == UNMAPPED_GVA ||
5354 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5355 goto emul_write;
2bacc55c 5356
daea3e73
AK		 5357 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5358 goto emul_write;
72dc67a6 5359
54bf36aa 5360 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5361 if (is_error_page(page))
c19b8bd6 5362 goto emul_write;
72dc67a6 5363
8fd75e12 5364 kaddr = kmap_atomic(page);
daea3e73
AK		 5365 kaddr += offset_in_page(gpa);
5366 switch (bytes) {
5367 case 1:
5368 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5369 break;
5370 case 2:
5371 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5372 break;
5373 case 4:
5374 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5375 break;
5376 case 8:
5377 exchanged = CMPXCHG64(kaddr, old, new);
5378 break;
5379 default:
5380 BUG();
2bacc55c 5381 }
8fd75e12 5382 kunmap_atomic(kaddr);
daea3e73
AK		 5383 kvm_release_page_dirty(page);
5384
5385 if (!exchanged)
5386 return X86EMUL_CMPXCHG_FAILED;
5387
54bf36aa 5388 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5389 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5390
5391 return X86EMUL_CONTINUE;
4a5f48f6 5392
3200f405 5393emul_write:
daea3e73 5394 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5395
0f65dd70 5396 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5397}
5398
cf8f70bf
GN		 5399static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5400{
cbfc6c91 5401 int r = 0, i;
cf8f70bf 5402
cbfc6c91
WL		 5403 for (i = 0; i < vcpu->arch.pio.count; i++) {
5404 if (vcpu->arch.pio.in)
5405 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5406 vcpu->arch.pio.size, pd);
5407 else
5408 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5409 vcpu->arch.pio.port, vcpu->arch.pio.size,
5410 pd);
5411 if (r)
5412 break;
5413 pd += vcpu->arch.pio.size;
5414 }
cf8f70bf
GN		 5415 return r;
5416}
5417
6f6fbe98
XG		 5418static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5419 unsigned short port, void *val,
5420 unsigned int count, bool in)
cf8f70bf 5421{
cf8f70bf 5422 vcpu->arch.pio.port = port;
6f6fbe98 5423 vcpu->arch.pio.in = in;
7972995b 5424 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5425 vcpu->arch.pio.size = size;
5426
5427 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5428 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5429 return 1;
5430 }
5431
5432 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5433 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5434 vcpu->run->io.size = size;
5435 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5436 vcpu->run->io.count = count;
5437 vcpu->run->io.port = port;
5438
5439 return 0;
5440}
5441
6f6fbe98
XG		 5442static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5443 int size, unsigned short port, void *val,
5444 unsigned int count)
cf8f70bf 5445{
ca1d4a9e 5446 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5447 int ret;
ca1d4a9e 5448
6f6fbe98
XG		 5449 if (vcpu->arch.pio.count)
5450 goto data_avail;
cf8f70bf 5451
cbfc6c91
WL		 5452 memset(vcpu->arch.pio_data, 0, size * count);
5453
6f6fbe98
XG		 5454 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5455 if (ret) {
5456data_avail:
5457 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5458 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5459 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5460 return 1;
5461 }
5462
cf8f70bf
GN		 5463 return 0;
5464}
5465
6f6fbe98
XG		 5466static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5467 int size, unsigned short port,
5468 const void *val, unsigned int count)
5469{
5470 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5471
5472 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5473 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5474 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5475}
5476
bbd9b64e
CO		 5477static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5478{
5479 return kvm_x86_ops->get_segment_base(vcpu, seg);
5480}
5481
3cb16fe7 5482static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5483{
3cb16fe7 5484 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5485}
5486
ae6a2375 5487static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5488{
5489 if (!need_emulate_wbinvd(vcpu))
5490 return X86EMUL_CONTINUE;
5491
5492 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5493 int cpu = get_cpu();
5494
5495 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5496 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5497 wbinvd_ipi, NULL, 1);
2eec7343 5498 put_cpu();
f5f48ee1 5499 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5500 } else
5501 wbinvd();
f5f48ee1
SY		 5502 return X86EMUL_CONTINUE;
5503}
5cb56059
JS		 5504
5505int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5506{
6affcbed
KH		 5507 kvm_emulate_wbinvd_noskip(vcpu);
5508 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5509}
f5f48ee1
SY		 5510EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5511
5cb56059
JS		 5512
5513
bcaf5cc5
AK		 5514static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5515{
5cb56059 5516 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5517}
5518
52eb5a6d
XL		 5519static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5520 unsigned long *dest)
bbd9b64e 5521{
16f8a6f9 5522 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5523}
5524
52eb5a6d
XL		 5525static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5526 unsigned long value)
bbd9b64e 5527{
338dbc97 5528
717746e3 5529 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5530}
5531
52a46617 5532static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5533{
52a46617 5534 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5535}
5536
717746e3 5537static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5538{
717746e3 5539 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5540 unsigned long value;
5541
5542 switch (cr) {
5543 case 0:
5544 value = kvm_read_cr0(vcpu);
5545 break;
5546 case 2:
5547 value = vcpu->arch.cr2;
5548 break;
5549 case 3:
9f8fe504 5550 value = kvm_read_cr3(vcpu);
52a46617
GN		 5551 break;
5552 case 4:
5553 value = kvm_read_cr4(vcpu);
5554 break;
5555 case 8:
5556 value = kvm_get_cr8(vcpu);
5557 break;
5558 default:
a737f256 5559 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5560 return 0;
5561 }
5562
5563 return value;
5564}
5565
717746e3 5566static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5567{
717746e3 5568 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5569 int res = 0;
5570
52a46617
GN		 5571 switch (cr) {
5572 case 0:
49a9b07e 5573 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5574 break;
5575 case 2:
5576 vcpu->arch.cr2 = val;
5577 break;
5578 case 3:
2390218b 5579 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5580 break;
5581 case 4:
a83b29c6 5582 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5583 break;
5584 case 8:
eea1cff9 5585 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5586 break;
5587 default:
a737f256 5588 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5589 res = -1;
52a46617 5590 }
0f12244f
GN		 5591
5592 return res;
52a46617
GN		 5593}
5594
717746e3 5595static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5596{
717746e3 5597 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5598}
5599
4bff1e86 5600static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5601{
4bff1e86 5602 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5603}
5604
4bff1e86 5605static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5606{
4bff1e86 5607 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5608}
5609
1ac9d0cf
AK		 5610static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5611{
5612 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5613}
5614
5615static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5616{
5617 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5618}
5619
4bff1e86
AK		 5620static unsigned long emulator_get_cached_segment_base(
5621 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5622{
4bff1e86 5623 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5624}
5625
1aa36616
AK		 5626static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5627 struct desc_struct *desc, u32 *base3,
5628 int seg)
2dafc6c2
GN		 5629{
5630 struct kvm_segment var;
5631
4bff1e86 5632 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5633 *selector = var.selector;
2dafc6c2 5634
378a8b09
GN		 5635 if (var.unusable) {
5636 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5637 if (base3)
5638 *base3 = 0;
2dafc6c2 5639 return false;
378a8b09 5640 }
2dafc6c2
GN		 5641
5642 if (var.g)
5643 var.limit >>= 12;
5644 set_desc_limit(desc, var.limit);
5645 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5646#ifdef CONFIG_X86_64
5647 if (base3)
5648 *base3 = var.base >> 32;
5649#endif
2dafc6c2
GN		 5650 desc->type = var.type;
5651 desc->s = var.s;
5652 desc->dpl = var.dpl;
5653 desc->p = var.present;
5654 desc->avl = var.avl;
5655 desc->l = var.l;
5656 desc->d = var.db;
5657 desc->g = var.g;
5658
5659 return true;
5660}
5661
1aa36616
AK		 5662static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5663 struct desc_struct *desc, u32 base3,
5664 int seg)
2dafc6c2 5665{
4bff1e86 5666 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5667 struct kvm_segment var;
5668
1aa36616 5669 var.selector = selector;
2dafc6c2 5670 var.base = get_desc_base(desc);
5601d05b
GN		 5671#ifdef CONFIG_X86_64
5672 var.base |= ((u64)base3) << 32;
5673#endif
2dafc6c2
GN		 5674 var.limit = get_desc_limit(desc);
5675 if (desc->g)
5676 var.limit = (var.limit << 12) | 0xfff;
5677 var.type = desc->type;
2dafc6c2
GN		 5678 var.dpl = desc->dpl;
5679 var.db = desc->d;
5680 var.s = desc->s;
5681 var.l = desc->l;
5682 var.g = desc->g;
5683 var.avl = desc->avl;
5684 var.present = desc->p;
5685 var.unusable = !var.present;
5686 var.padding = 0;
5687
5688 kvm_set_segment(vcpu, &var, seg);
5689 return;
5690}
5691
717746e3
AK		 5692static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5693 u32 msr_index, u64 *pdata)
5694{
609e36d3
PB		 5695 struct msr_data msr;
5696 int r;
5697
5698 msr.index = msr_index;
5699 msr.host_initiated = false;
5700 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5701 if (r)
5702 return r;
5703
5704 *pdata = msr.data;
5705 return 0;
717746e3
AK		 5706}
5707
5708static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5709 u32 msr_index, u64 data)
5710{
8fe8ab46
WA		 5711 struct msr_data msr;
5712
5713 msr.data = data;
5714 msr.index = msr_index;
5715 msr.host_initiated = false;
5716 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5717}
5718
64d60670
PB		 5719static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5720{
5721 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5722
5723 return vcpu->arch.smbase;
5724}
5725
5726static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5727{
5728 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5729
5730 vcpu->arch.smbase = smbase;
5731}
5732
67f4d428
NA		 5733static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5734 u32 pmc)
5735{
c6702c9d 5736 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5737}
5738
222d21aa
AK		 5739static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5740 u32 pmc, u64 *pdata)
5741{
c6702c9d 5742 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5743}
5744
6c3287f7
AK		 5745static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5746{
5747 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5748}
5749
2953538e 5750static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5751 struct x86_instruction_info *info,
c4f035c6
AK		 5752 enum x86_intercept_stage stage)
5753{
2953538e 5754 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5755}
5756
e911eb3b
YZ		 5757static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5758 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5759{
e911eb3b 5760 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5761}
5762
dd856efa
AK		 5763static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5764{
5765 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5766}
5767
5768static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5769{
5770 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5771}
5772
801806d9
NA		 5773static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5774{
5775 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5776}
5777
6ed071f0
LP		 5778static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5779{
5780 return emul_to_vcpu(ctxt)->arch.hflags;
5781}
5782
5783static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5784{
5785 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5786}
5787
0234bf88
LP		 5788static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5789{
5790 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5791}
5792
0225fb50 5793static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5794 .read_gpr = emulator_read_gpr,
5795 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5796 .read_std = emulator_read_std,
5797 .write_std = emulator_write_std,
7a036a6f 5798 .read_phys = kvm_read_guest_phys_system,
1871c602 5799 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5800 .read_emulated = emulator_read_emulated,
5801 .write_emulated = emulator_write_emulated,
5802 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5803 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5804 .pio_in_emulated = emulator_pio_in_emulated,
5805 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5806 .get_segment = emulator_get_segment,
5807 .set_segment = emulator_set_segment,
5951c442 5808 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5809 .get_gdt = emulator_get_gdt,
160ce1f1 5810 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5811 .set_gdt = emulator_set_gdt,
5812 .set_idt = emulator_set_idt,
52a46617
GN		 5813 .get_cr = emulator_get_cr,
5814 .set_cr = emulator_set_cr,
9c537244 5815 .cpl = emulator_get_cpl,
35aa5375
GN		 5816 .get_dr = emulator_get_dr,
5817 .set_dr = emulator_set_dr,
64d60670
PB		 5818 .get_smbase = emulator_get_smbase,
5819 .set_smbase = emulator_set_smbase,
717746e3
AK		 5820 .set_msr = emulator_set_msr,
5821 .get_msr = emulator_get_msr,
67f4d428 5822 .check_pmc = emulator_check_pmc,
222d21aa 5823 .read_pmc = emulator_read_pmc,
6c3287f7 5824 .halt = emulator_halt,
bcaf5cc5 5825 .wbinvd = emulator_wbinvd,
d6aa1000 5826 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5827 .intercept = emulator_intercept,
bdb42f5a 5828 .get_cpuid = emulator_get_cpuid,
801806d9 5829 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5830 .get_hflags = emulator_get_hflags,
5831 .set_hflags = emulator_set_hflags,
0234bf88 5832 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5833};
5834
95cb2295
GN		 5835static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5836{
37ccdcbe 5837 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5838 /*
5839 * an sti; sti; sequence only disable interrupts for the first
5840 * instruction. So, if the last instruction, be it emulated or
5841 * not, left the system with the INT_STI flag enabled, it
5842 * means that the last instruction is an sti. We should not
5843 * leave the flag on in this case. The same goes for mov ss
5844 */
37ccdcbe
PB		 5845 if (int_shadow & mask)
5846 mask = 0;
6addfc42 5847 if (unlikely(int_shadow || mask)) {
95cb2295 5848 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5849 if (!mask)
5850 kvm_make_request(KVM_REQ_EVENT, vcpu);
5851 }
95cb2295
GN		 5852}
5853
ef54bcfe 5854static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5855{
5856 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5857 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5858 return kvm_propagate_fault(vcpu, &ctxt->exception);
5859
5860 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5861 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5862 ctxt->exception.error_code);
54b8486f 5863 else
da9cb575 5864 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5865 return false;
54b8486f
GN		 5866}
5867
8ec4722d
MG		 5868static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5869{
adf52235 5870 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5871 int cs_db, cs_l;
5872
8ec4722d
MG		 5873 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5874
adf52235 5875 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5876 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5877
adf52235
TY		 5878 ctxt->eip = kvm_rip_read(vcpu);
5879 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5880 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5881 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5882 cs_db ? X86EMUL_MODE_PROT32 :
5883 X86EMUL_MODE_PROT16;
a584539b 5884 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5885 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5886 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5887
dd856efa 5888 init_decode_cache(ctxt);
7ae441ea 5889 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5890}
5891
71f9833b 5892int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5893{
9d74191a 5894 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5895 int ret;
5896
5897 init_emulate_ctxt(vcpu);
5898
9dac77fa
AK		 5899 ctxt->op_bytes = 2;
5900 ctxt->ad_bytes = 2;
5901 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5902 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5903
5904 if (ret != X86EMUL_CONTINUE)
5905 return EMULATE_FAIL;
5906
9dac77fa 5907 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5908 kvm_rip_write(vcpu, ctxt->eip);
5909 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5910
63995653
MG		 5911 return EMULATE_DONE;
5912}
5913EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5914
e2366171 5915static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5916{
fc3a9157
JR		 5917 int r = EMULATE_DONE;
5918
6d77dbfc
GN		 5919 ++vcpu->stat.insn_emulation_fail;
5920 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5921
5922 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5923 return EMULATE_FAIL;
5924
a2b9e6c1 5925 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5926 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5927 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5928 vcpu->run->internal.ndata = 0;
1f4dcb3b 5929 r = EMULATE_USER_EXIT;
fc3a9157 5930 }
e2366171 5931
6d77dbfc 5932 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5933
5934 return r;
6d77dbfc
GN		 5935}
5936
93c05d3e 5937static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5938 bool write_fault_to_shadow_pgtable,
5939 int emulation_type)
a6f177ef 5940{
95b3cf69 5941 gpa_t gpa = cr2;
ba049e93 5942 kvm_pfn_t pfn;
a6f177ef 5943
384bf221 5944 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 5945 return false;
5946
6c3dfeb6
SC		 5947 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
5948 return false;
5949
44dd3ffa 5950 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 5951 /*
5952 * Write permission should be allowed since only
5953 * write access need to be emulated.
5954 */
5955 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5956
95b3cf69
XG		 5957 /*
5958 * If the mapping is invalid in guest, let cpu retry
5959 * it to generate fault.
5960 */
5961 if (gpa == UNMAPPED_GVA)
5962 return true;
5963 }
a6f177ef 5964
8e3d9d06
XG		 5965 /*
5966 * Do not retry the unhandleable instruction if it faults on the
5967 * readonly host memory, otherwise it will goto a infinite loop:
5968 * retry instruction -> write #PF -> emulation fail -> retry
5969 * instruction -> ...
5970 */
5971 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5972
5973 /*
5974 * If the instruction failed on the error pfn, it can not be fixed,
5975 * report the error to userspace.
5976 */
5977 if (is_error_noslot_pfn(pfn))
5978 return false;
5979
5980 kvm_release_pfn_clean(pfn);
5981
5982 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 5983 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 5984 unsigned int indirect_shadow_pages;
5985
5986 spin_lock(&vcpu->kvm->mmu_lock);
5987 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5988 spin_unlock(&vcpu->kvm->mmu_lock);
5989
5990 if (indirect_shadow_pages)
5991 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5992
a6f177ef 5993 return true;
8e3d9d06 5994 }
a6f177ef 5995
95b3cf69
XG		 5996 /*
5997 * if emulation was due to access to shadowed page table
5998 * and it failed try to unshadow page and re-enter the
5999 * guest to let CPU execute the instruction.
6000 */
6001 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6002
6003 /*
6004 * If the access faults on its page table, it can not
6005 * be fixed by unprotecting shadow page and it should
6006 * be reported to userspace.
6007 */
6008 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6009}
6010
1cb3f3ae
XG		 6011static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6012 unsigned long cr2, int emulation_type)
6013{
6014 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6015 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6016
6017 last_retry_eip = vcpu->arch.last_retry_eip;
6018 last_retry_addr = vcpu->arch.last_retry_addr;
6019
6020 /*
6021 * If the emulation is caused by #PF and it is non-page_table
6022 * writing instruction, it means the VM-EXIT is caused by shadow
6023 * page protected, we can zap the shadow page and retry this
6024 * instruction directly.
6025 *
6026 * Note: if the guest uses a non-page-table modifying instruction
6027 * on the PDE that points to the instruction, then we will unmap
6028 * the instruction and go to an infinite loop. So, we cache the
6029 * last retried eip and the last fault address, if we meet the eip
6030 * and the address again, we can break out of the potential infinite
6031 * loop.
6032 */
6033 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6034
384bf221 6035 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6036 return false;
6037
6c3dfeb6
SC		 6038 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6039 return false;
6040
1cb3f3ae
XG		 6041 if (x86_page_table_writing_insn(ctxt))
6042 return false;
6043
6044 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6045 return false;
6046
6047 vcpu->arch.last_retry_eip = ctxt->eip;
6048 vcpu->arch.last_retry_addr = cr2;
6049
44dd3ffa 6050 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6051 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6052
22368028 6053 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6054
6055 return true;
6056}
6057
716d51ab
GN		 6058static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6059static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6060
64d60670 6061static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6062{
64d60670 6063 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6064 /* This is a good place to trace that we are exiting SMM. */
6065 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6066
c43203ca
PB		 6067 /* Process a latched INIT or SMI, if any. */
6068 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6069 }
699023e2
PB		 6070
6071 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6072}
6073
6074static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
6075{
6076 unsigned changed = vcpu->arch.hflags ^ emul_flags;
6077
a584539b 6078 vcpu->arch.hflags = emul_flags;
64d60670
PB		 6079
6080 if (changed & HF_SMM_MASK)
6081 kvm_smm_changed(vcpu);
a584539b
PB		 6082}
6083
4a1e10d5
PB		 6084static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6085 unsigned long *db)
6086{
6087 u32 dr6 = 0;
6088 int i;
6089 u32 enable, rwlen;
6090
6091 enable = dr7;
6092 rwlen = dr7 >> 16;
6093 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6094 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6095 dr6 |= (1 << i);
6096 return dr6;
6097}
6098
c8401dda 6099static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6100{
6101 struct kvm_run *kvm_run = vcpu->run;
6102
c8401dda
PB		 6103 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6104 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6105 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6106 kvm_run->debug.arch.exception = DB_VECTOR;
6107 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6108 *r = EMULATE_USER_EXIT;
6109 } else {
6110 /*
6111 * "Certain debug exceptions may clear bit 0-3. The
6112 * remaining contents of the DR6 register are never
6113 * cleared by the processor".
6114 */
6115 vcpu->arch.dr6 &= ~15;
6116 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
6117 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 6118 }
6119}
6120
6affcbed
KH		 6121int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6122{
6123 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6124 int r = EMULATE_DONE;
6125
6126 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6127
6128 /*
6129 * rflags is the old, "raw" value of the flags. The new value has
6130 * not been saved yet.
6131 *
6132 * This is correct even for TF set by the guest, because "the
6133 * processor will not generate this exception after the instruction
6134 * that sets the TF flag".
6135 */
6136 if (unlikely(rflags & X86_EFLAGS_TF))
6137 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6138 return r == EMULATE_DONE;
6139}
6140EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6141
4a1e10d5
PB		 6142static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6143{
4a1e10d5
PB		 6144 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6145 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6146 struct kvm_run *kvm_run = vcpu->run;
6147 unsigned long eip = kvm_get_linear_rip(vcpu);
6148 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6149 vcpu->arch.guest_debug_dr7,
6150 vcpu->arch.eff_db);
6151
6152 if (dr6 != 0) {
6f43ed01 6153 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6154 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6155 kvm_run->debug.arch.exception = DB_VECTOR;
6156 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6157 *r = EMULATE_USER_EXIT;
6158 return true;
6159 }
6160 }
6161
4161a569
NA		 6162 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6163 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6164 unsigned long eip = kvm_get_linear_rip(vcpu);
6165 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6166 vcpu->arch.dr7,
6167 vcpu->arch.db);
6168
6169 if (dr6 != 0) {
6170 vcpu->arch.dr6 &= ~15;
6f43ed01 6171 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6172 kvm_queue_exception(vcpu, DB_VECTOR);
6173 *r = EMULATE_DONE;
6174 return true;
6175 }
6176 }
6177
6178 return false;
6179}
6180
04789b66
LA		 6181static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6182{
2d7921c4
AM		 6183 switch (ctxt->opcode_len) {
6184 case 1:
6185 switch (ctxt->b) {
6186 case 0xe4: /* IN */
6187 case 0xe5:
6188 case 0xec:
6189 case 0xed:
6190 case 0xe6: /* OUT */
6191 case 0xe7:
6192 case 0xee:
6193 case 0xef:
6194 case 0x6c: /* INS */
6195 case 0x6d:
6196 case 0x6e: /* OUTS */
6197 case 0x6f:
6198 return true;
6199 }
6200 break;
6201 case 2:
6202 switch (ctxt->b) {
6203 case 0x33: /* RDPMC */
6204 return true;
6205 }
6206 break;
04789b66
LA		 6207 }
6208
6209 return false;
6210}
6211
51d8b661
AP		 6212int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6213 unsigned long cr2,
dc25e89e
AP		 6214 int emulation_type,
6215 void *insn,
6216 int insn_len)
bbd9b64e 6217{
95cb2295 6218 int r;
9d74191a 6219 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6220 bool writeback = true;
93c05d3e 6221 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6222
c595ceee
PB		 6223 vcpu->arch.l1tf_flush_l1d = true;
6224
93c05d3e
XG		 6225 /*
6226 * Clear write_fault_to_shadow_pgtable here to ensure it is
6227 * never reused.
6228 */
6229 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6230 kvm_clear_exception_queue(vcpu);
8d7d8102 6231
571008da 6232 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6233 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6234
6235 /*
6236 * We will reenter on the same instruction since
6237 * we do not set complete_userspace_io. This does not
6238 * handle watchpoints yet, those would be handled in
6239 * the emulate_ops.
6240 */
d391f120
VK		 6241 if (!(emulation_type & EMULTYPE_SKIP) &&
6242 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6243 return r;
6244
9d74191a
TY		 6245 ctxt->interruptibility = 0;
6246 ctxt->have_exception = false;
e0ad0b47 6247 ctxt->exception.vector = -1;
9d74191a 6248 ctxt->perm_ok = false;
bbd9b64e 6249
b51e974f 6250 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6251
9d74191a 6252 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6253
e46479f8 6254 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6255 ++vcpu->stat.insn_emulation;
1d2887e2 6256 if (r != EMULATION_OK) {
4005996e
AK		 6257 if (emulation_type & EMULTYPE_TRAP_UD)
6258 return EMULATE_FAIL;
991eebf9
GN		 6259 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6260 emulation_type))
bbd9b64e 6261 return EMULATE_DONE;
6ea6e843
PB		 6262 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6263 return EMULATE_DONE;
6d77dbfc
GN		 6264 if (emulation_type & EMULTYPE_SKIP)
6265 return EMULATE_FAIL;
e2366171 6266 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6267 }
6268 }
6269
04789b66
LA		 6270 if ((emulation_type & EMULTYPE_VMWARE) &&
6271 !is_vmware_backdoor_opcode(ctxt))
6272 return EMULATE_FAIL;
6273
ba8afb6b 6274 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6275 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6276 if (ctxt->eflags & X86_EFLAGS_RF)
6277 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6278 return EMULATE_DONE;
6279 }
6280
1cb3f3ae
XG		 6281 if (retry_instruction(ctxt, cr2, emulation_type))
6282 return EMULATE_DONE;
6283
7ae441ea 6284 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6285 changes registers values during IO operation */
7ae441ea
GN		 6286 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6287 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6288 emulator_invalidate_register_cache(ctxt);
7ae441ea 6289 }
4d2179e1 6290
5cd21917 6291restart:
0f89b207
TL		 6292 /* Save the faulting GPA (cr2) in the address field */
6293 ctxt->exception.address = cr2;
6294
9d74191a 6295 r = x86_emulate_insn(ctxt);
bbd9b64e 6296
775fde86
JR		 6297 if (r == EMULATION_INTERCEPTED)
6298 return EMULATE_DONE;
6299
d2ddd1c4 6300 if (r == EMULATION_FAILED) {
991eebf9
GN		 6301 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6302 emulation_type))
c3cd7ffa
GN		 6303 return EMULATE_DONE;
6304
e2366171 6305 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6306 }
6307
9d74191a 6308 if (ctxt->have_exception) {
d2ddd1c4 6309 r = EMULATE_DONE;
ef54bcfe
PB		 6310 if (inject_emulated_exception(vcpu))
6311 return r;
d2ddd1c4 6312 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6313 if (!vcpu->arch.pio.in) {
6314 /* FIXME: return into emulator if single-stepping. */
3457e419 6315 vcpu->arch.pio.count = 0;
0912c977 6316 } else {
7ae441ea 6317 writeback = false;
716d51ab
GN		 6318 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6319 }
ac0a48c3 6320 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6321 } else if (vcpu->mmio_needed) {
6322 if (!vcpu->mmio_is_write)
6323 writeback = false;
ac0a48c3 6324 r = EMULATE_USER_EXIT;
716d51ab 6325 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6326 } else if (r == EMULATION_RESTART)
5cd21917 6327 goto restart;
d2ddd1c4
GN		 6328 else
6329 r = EMULATE_DONE;
f850e2e6 6330
7ae441ea 6331 if (writeback) {
6addfc42 6332 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6333 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6334 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6335 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6336 if (r == EMULATE_DONE &&
6337 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6338 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6339 if (!ctxt->have_exception ||
6340 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6341 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6342
6343 /*
6344 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6345 * do nothing, and it will be requested again as soon as
6346 * the shadow expires. But we still need to check here,
6347 * because POPF has no interrupt shadow.
6348 */
6349 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6350 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6351 } else
6352 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6353
6354 return r;
de7d789a 6355}
c60658d1
SC		 6356
6357int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6358{
6359 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6360}
6361EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6362
6363int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6364 void *insn, int insn_len)
6365{
6366 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6367}
6368EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6369
dca7f128
SC		 6370static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6371 unsigned short port)
de7d789a 6372{
cf8f70bf 6373 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6374 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6375 size, port, &val, 1);
cf8f70bf 6376 /* do not return to emulator after return from userspace */
7972995b 6377 vcpu->arch.pio.count = 0;
de7d789a
CO		 6378 return ret;
6379}
de7d789a 6380
8370c3d0
TL		 6381static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6382{
6383 unsigned long val;
6384
6385 /* We should only ever be called with arch.pio.count equal to 1 */
6386 BUG_ON(vcpu->arch.pio.count != 1);
6387
6388 /* For size less than 4 we merge, else we zero extend */
6389 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6390 : 0;
6391
6392 /*
6393 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6394 * the copy and tracing
6395 */
6396 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6397 vcpu->arch.pio.port, &val, 1);
6398 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6399
6400 return 1;
6401}
6402
dca7f128
SC		 6403static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6404 unsigned short port)
8370c3d0
TL		 6405{
6406 unsigned long val;
6407 int ret;
6408
6409 /* For size less than 4 we merge, else we zero extend */
6410 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6411
6412 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6413 &val, 1);
6414 if (ret) {
6415 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6416 return ret;
6417 }
6418
6419 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6420
6421 return 0;
6422}
dca7f128
SC		 6423
6424int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6425{
6426 int ret = kvm_skip_emulated_instruction(vcpu);
6427
6428 /*
6429 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6430 * KVM_EXIT_DEBUG here.
6431 */
6432 if (in)
6433 return kvm_fast_pio_in(vcpu, size, port) && ret;
6434 else
6435 return kvm_fast_pio_out(vcpu, size, port) && ret;
6436}
6437EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6438
251a5fd6 6439static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6440{
0a3aee0d 6441 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6442 return 0;
8cfdc000
ZA		 6443}
6444
6445static void tsc_khz_changed(void *data)
c8076604 6446{
8cfdc000
ZA		 6447 struct cpufreq_freqs *freq = data;
6448 unsigned long khz = 0;
6449
6450 if (data)
6451 khz = freq->new;
6452 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6453 khz = cpufreq_quick_get(raw_smp_processor_id());
6454 if (!khz)
6455 khz = tsc_khz;
0a3aee0d 6456 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6457}
6458
5fa4ec9c 6459#ifdef CONFIG_X86_64
0092e434
VK		 6460static void kvm_hyperv_tsc_notifier(void)
6461{
0092e434
VK		 6462 struct kvm *kvm;
6463 struct kvm_vcpu *vcpu;
6464 int cpu;
6465
6466 spin_lock(&kvm_lock);
6467 list_for_each_entry(kvm, &vm_list, vm_list)
6468 kvm_make_mclock_inprogress_request(kvm);
6469
6470 hyperv_stop_tsc_emulation();
6471
6472 /* TSC frequency always matches when on Hyper-V */
6473 for_each_present_cpu(cpu)
6474 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6475 kvm_max_guest_tsc_khz = tsc_khz;
6476
6477 list_for_each_entry(kvm, &vm_list, vm_list) {
6478 struct kvm_arch *ka = &kvm->arch;
6479
6480 spin_lock(&ka->pvclock_gtod_sync_lock);
6481
6482 pvclock_update_vm_gtod_copy(kvm);
6483
6484 kvm_for_each_vcpu(cpu, vcpu, kvm)
6485 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6486
6487 kvm_for_each_vcpu(cpu, vcpu, kvm)
6488 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6489
6490 spin_unlock(&ka->pvclock_gtod_sync_lock);
6491 }
6492 spin_unlock(&kvm_lock);
0092e434 6493}
5fa4ec9c 6494#endif
0092e434 6495
c8076604
GH		 6496static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6497 void *data)
6498{
6499 struct cpufreq_freqs *freq = data;
6500 struct kvm *kvm;
6501 struct kvm_vcpu *vcpu;
6502 int i, send_ipi = 0;
6503
8cfdc000
ZA		 6504 /*
6505 * We allow guests to temporarily run on slowing clocks,
6506 * provided we notify them after, or to run on accelerating
6507 * clocks, provided we notify them before. Thus time never
6508 * goes backwards.
6509 *
6510 * However, we have a problem. We can't atomically update
6511 * the frequency of a given CPU from this function; it is
6512 * merely a notifier, which can be called from any CPU.
6513 * Changing the TSC frequency at arbitrary points in time
6514 * requires a recomputation of local variables related to
6515 * the TSC for each VCPU. We must flag these local variables
6516 * to be updated and be sure the update takes place with the
6517 * new frequency before any guests proceed.
6518 *
6519 * Unfortunately, the combination of hotplug CPU and frequency
6520 * change creates an intractable locking scenario; the order
6521 * of when these callouts happen is undefined with respect to
6522 * CPU hotplug, and they can race with each other. As such,
6523 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6524 * undefined; you can actually have a CPU frequency change take
6525 * place in between the computation of X and the setting of the
6526 * variable. To protect against this problem, all updates of
6527 * the per_cpu tsc_khz variable are done in an interrupt
6528 * protected IPI, and all callers wishing to update the value
6529 * must wait for a synchronous IPI to complete (which is trivial
6530 * if the caller is on the CPU already). This establishes the
6531 * necessary total order on variable updates.
6532 *
6533 * Note that because a guest time update may take place
6534 * anytime after the setting of the VCPU's request bit, the
6535 * correct TSC value must be set before the request. However,
6536 * to ensure the update actually makes it to any guest which
6537 * starts running in hardware virtualization between the set
6538 * and the acquisition of the spinlock, we must also ping the
6539 * CPU after setting the request bit.
6540 *
6541 */
6542
c8076604
GH		 6543 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6544 return 0;
6545 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6546 return 0;
8cfdc000
ZA		 6547
6548 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6549
2f303b74 6550 spin_lock(&kvm_lock);
c8076604 6551 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6552 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6553 if (vcpu->cpu != freq->cpu)
6554 continue;
c285545f 6555 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6556 if (vcpu->cpu != smp_processor_id())
8cfdc000 6557 send_ipi = 1;
c8076604
GH		 6558 }
6559 }
2f303b74 6560 spin_unlock(&kvm_lock);
c8076604
GH		 6561
6562 if (freq->old < freq->new && send_ipi) {
6563 /*
6564 * We upscale the frequency. Must make the guest
6565 * doesn't see old kvmclock values while running with
6566 * the new frequency, otherwise we risk the guest sees
6567 * time go backwards.
6568 *
6569 * In case we update the frequency for another cpu
6570 * (which might be in guest context) send an interrupt
6571 * to kick the cpu out of guest context. Next time
6572 * guest context is entered kvmclock will be updated,
6573 * so the guest will not see stale values.
6574 */
8cfdc000 6575 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6576 }
6577 return 0;
6578}
6579
6580static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6581 .notifier_call = kvmclock_cpufreq_notifier
6582};
6583
251a5fd6 6584static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6585{
251a5fd6
SAS		 6586 tsc_khz_changed(NULL);
6587 return 0;
8cfdc000
ZA		 6588}
6589
b820cc0c
ZA		 6590static void kvm_timer_init(void)
6591{
c285545f 6592 max_tsc_khz = tsc_khz;
460dd42e 6593
b820cc0c 6594 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6595#ifdef CONFIG_CPU_FREQ
6596 struct cpufreq_policy policy;
758f588d
BP		 6597 int cpu;
6598
c285545f 6599 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6600 cpu = get_cpu();
6601 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6602 if (policy.cpuinfo.max_freq)
6603 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6604 put_cpu();
c285545f 6605#endif
b820cc0c
ZA		 6606 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6607 CPUFREQ_TRANSITION_NOTIFIER);
6608 }
c285545f 6609 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6610
73c1b41e 6611 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6612 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6613}
6614
dd60d217
AK		 6615DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6616EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6617
f5132b01 6618int kvm_is_in_guest(void)
ff9d07a0 6619{
086c9855 6620 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6621}
6622
6623static int kvm_is_user_mode(void)
6624{
6625 int user_mode = 3;
dcf46b94 6626
086c9855
AS		 6627 if (__this_cpu_read(current_vcpu))
6628 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6629
ff9d07a0
ZY		 6630 return user_mode != 0;
6631}
6632
6633static unsigned long kvm_get_guest_ip(void)
6634{
6635 unsigned long ip = 0;
dcf46b94 6636
086c9855
AS		 6637 if (__this_cpu_read(current_vcpu))
6638 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6639
ff9d07a0
ZY		 6640 return ip;
6641}
6642
6643static struct perf_guest_info_callbacks kvm_guest_cbs = {
6644 .is_in_guest = kvm_is_in_guest,
6645 .is_user_mode = kvm_is_user_mode,
6646 .get_guest_ip = kvm_get_guest_ip,
6647};
6648
ce88decf
XG		 6649static void kvm_set_mmio_spte_mask(void)
6650{
6651 u64 mask;
6652 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6653
6654 /*
6655 * Set the reserved bits and the present bit of an paging-structure
6656 * entry to generate page fault with PFER.RSV = 1.
6657 */
28a1f3ac
JS		 6658
6659 /*
6660 * Mask the uppermost physical address bit, which would be reserved as
6661 * long as the supported physical address width is less than 52.
6662 */
6663 mask = 1ull << 51;
885032b9 6664
885032b9 6665 /* Set the present bit. */
ce88decf
XG		 6666 mask |= 1ull;
6667
ce88decf
XG		 6668 /*
6669 * If reserved bit is not supported, clear the present bit to disable
6670 * mmio page fault.
6671 */
7288bde1 6672 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
ce88decf 6673 mask &= ~1ull;
ce88decf 6674
dcdca5fe 6675 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6676}
6677
16e8d74d
MT		 6678#ifdef CONFIG_X86_64
6679static void pvclock_gtod_update_fn(struct work_struct *work)
6680{
d828199e
MT		 6681 struct kvm *kvm;
6682
6683 struct kvm_vcpu *vcpu;
6684 int i;
6685
2f303b74 6686 spin_lock(&kvm_lock);
d828199e
MT		 6687 list_for_each_entry(kvm, &vm_list, vm_list)
6688 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6689 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6690 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6691 spin_unlock(&kvm_lock);
16e8d74d
MT		 6692}
6693
6694static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6695
6696/*
6697 * Notification about pvclock gtod data update.
6698 */
6699static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6700 void *priv)
6701{
6702 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6703 struct timekeeper *tk = priv;
6704
6705 update_pvclock_gtod(tk);
6706
6707 /* disable master clock if host does not trust, or does not
b0c39dc6 6708 * use, TSC based clocksource.
16e8d74d 6709 */
b0c39dc6 6710 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6711 atomic_read(&kvm_guest_has_master_clock) != 0)
6712 queue_work(system_long_wq, &pvclock_gtod_work);
6713
6714 return 0;
6715}
6716
6717static struct notifier_block pvclock_gtod_notifier = {
6718 .notifier_call = pvclock_gtod_notify,
6719};
6720#endif
6721
f8c16bba 6722int kvm_arch_init(void *opaque)
043405e1 6723{
b820cc0c 6724 int r;
6b61edf7 6725 struct kvm_x86_ops *ops = opaque;
f8c16bba 6726
f8c16bba
ZX		 6727 if (kvm_x86_ops) {
6728 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6729 r = -EEXIST;
6730 goto out;
f8c16bba
ZX		 6731 }
6732
6733 if (!ops->cpu_has_kvm_support()) {
6734 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6735 r = -EOPNOTSUPP;
6736 goto out;
f8c16bba
ZX		 6737 }
6738 if (ops->disabled_by_bios()) {
6739 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6740 r = -EOPNOTSUPP;
6741 goto out;
f8c16bba
ZX		 6742 }
6743
013f6a5d
MT		 6744 r = -ENOMEM;
6745 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6746 if (!shared_msrs) {
6747 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6748 goto out;
6749 }
6750
97db56ce
AK		 6751 r = kvm_mmu_module_init();
6752 if (r)
013f6a5d 6753 goto out_free_percpu;
97db56ce 6754
ce88decf 6755 kvm_set_mmio_spte_mask();
97db56ce 6756
f8c16bba 6757 kvm_x86_ops = ops;
920c8377 6758
7b52345e 6759 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6760 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6761 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6762 kvm_timer_init();
c8076604 6763
ff9d07a0
ZY		 6764 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6765
d366bf7e 6766 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6767 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6768
c5cc421b 6769 kvm_lapic_init();
16e8d74d
MT		 6770#ifdef CONFIG_X86_64
6771 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6772
5fa4ec9c 6773 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6774 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6775#endif
6776
f8c16bba 6777 return 0;
56c6d28a 6778
013f6a5d
MT		 6779out_free_percpu:
6780 free_percpu(shared_msrs);
56c6d28a 6781out:
56c6d28a 6782 return r;
043405e1 6783}
8776e519 6784
f8c16bba
ZX		 6785void kvm_arch_exit(void)
6786{
0092e434 6787#ifdef CONFIG_X86_64
5fa4ec9c 6788 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6789 clear_hv_tscchange_cb();
6790#endif
cef84c30 6791 kvm_lapic_exit();
ff9d07a0
ZY		 6792 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6793
888d256e
JK		 6794 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6795 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6796 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6797 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6798#ifdef CONFIG_X86_64
6799 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6800#endif
f8c16bba 6801 kvm_x86_ops = NULL;
56c6d28a 6802 kvm_mmu_module_exit();
013f6a5d 6803 free_percpu(shared_msrs);
56c6d28a 6804}
f8c16bba 6805
5cb56059 6806int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6807{
6808 ++vcpu->stat.halt_exits;
35754c98 6809 if (lapic_in_kernel(vcpu)) {
a4535290 6810 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6811 return 1;
6812 } else {
6813 vcpu->run->exit_reason = KVM_EXIT_HLT;
6814 return 0;
6815 }
6816}
5cb56059
JS		 6817EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6818
6819int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6820{
6affcbed
KH		 6821 int ret = kvm_skip_emulated_instruction(vcpu);
6822 /*
6823 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6824 * KVM_EXIT_DEBUG here.
6825 */
6826 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6827}
8776e519
HB		 6828EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6829
8ef81a9a 6830#ifdef CONFIG_X86_64
55dd00a7
MT		 6831static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6832 unsigned long clock_type)
6833{
6834 struct kvm_clock_pairing clock_pairing;
899a31f5 6835 struct timespec64 ts;
80fbd89c 6836 u64 cycle;
55dd00a7
MT		 6837 int ret;
6838
6839 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6840 return -KVM_EOPNOTSUPP;
6841
6842 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6843 return -KVM_EOPNOTSUPP;
6844
6845 clock_pairing.sec = ts.tv_sec;
6846 clock_pairing.nsec = ts.tv_nsec;
6847 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6848 clock_pairing.flags = 0;
6849
6850 ret = 0;
6851 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6852 sizeof(struct kvm_clock_pairing)))
6853 ret = -KVM_EFAULT;
6854
6855 return ret;
6856}
8ef81a9a 6857#endif
55dd00a7 6858
6aef266c
SV		 6859/*
6860 * kvm_pv_kick_cpu_op: Kick a vcpu.
6861 *
6862 * @apicid - apicid of vcpu to be kicked.
6863 */
6864static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6865{
24d2166b 6866 struct kvm_lapic_irq lapic_irq;
6aef266c 6867
24d2166b
R		 6868 lapic_irq.shorthand = 0;
6869 lapic_irq.dest_mode = 0;
ebd28fcb 6870 lapic_irq.level = 0;
24d2166b 6871 lapic_irq.dest_id = apicid;
93bbf0b8 6872 lapic_irq.msi_redir_hint = false;
6aef266c 6873
24d2166b 6874 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6875 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6876}
6877
d62caabb
AS		 6878void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6879{
6880 vcpu->arch.apicv_active = false;
6881 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6882}
6883
8776e519
HB		 6884int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6885{
6886 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6887 int op_64_bit;
8776e519 6888
696ca779
RK		 6889 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6890 return kvm_hv_hypercall(vcpu);
55cd8e5a 6891
5fdbf976
MT		 6892 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6893 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6894 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6895 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6896 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6897
229456fc 6898 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6899
a449c7aa
NA		 6900 op_64_bit = is_64_bit_mode(vcpu);
6901 if (!op_64_bit) {
8776e519
HB		 6902 nr &= 0xFFFFFFFF;
6903 a0 &= 0xFFFFFFFF;
6904 a1 &= 0xFFFFFFFF;
6905 a2 &= 0xFFFFFFFF;
6906 a3 &= 0xFFFFFFFF;
6907 }
6908
07708c4a
JK		 6909 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6910 ret = -KVM_EPERM;
696ca779 6911 goto out;
07708c4a
JK		 6912 }
6913
8776e519 6914 switch (nr) {
b93463aa
AK		 6915 case KVM_HC_VAPIC_POLL_IRQ:
6916 ret = 0;
6917 break;
6aef266c
SV		 6918 case KVM_HC_KICK_CPU:
6919 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6920 ret = 0;
6921 break;
8ef81a9a 6922#ifdef CONFIG_X86_64
55dd00a7
MT		 6923 case KVM_HC_CLOCK_PAIRING:
6924 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6925 break;
4180bf1b
WL		 6926 case KVM_HC_SEND_IPI:
6927 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
6928 break;
8ef81a9a 6929#endif
8776e519
HB		 6930 default:
6931 ret = -KVM_ENOSYS;
6932 break;
6933 }
696ca779 6934out:
a449c7aa
NA		 6935 if (!op_64_bit)
6936 ret = (u32)ret;
5fdbf976 6937 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 6938
f11c3a8d 6939 ++vcpu->stat.hypercalls;
6356ee0c 6940 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6941}
6942EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6943
b6785def 6944static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6945{
d6aa1000 6946 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6947 char instruction[3];
5fdbf976 6948 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6949
8776e519 6950 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6951
ce2e852e
DV		 6952 return emulator_write_emulated(ctxt, rip, instruction, 3,
6953 &ctxt->exception);
8776e519
HB		 6954}
6955
851ba692 6956static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6957{
782d422b
MG		 6958 return vcpu->run->request_interrupt_window &&
6959 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6960}
6961
851ba692 6962static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6963{
851ba692
AK		 6964 struct kvm_run *kvm_run = vcpu->run;
6965
91586a3b 6966 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6967 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6968 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6969 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6970 kvm_run->ready_for_interrupt_injection =
6971 pic_in_kernel(vcpu->kvm) ||
782d422b 6972 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6973}
6974
95ba8273
GN		 6975static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6976{
6977 int max_irr, tpr;
6978
6979 if (!kvm_x86_ops->update_cr8_intercept)
6980 return;
6981
bce87cce 6982 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6983 return;
6984
d62caabb
AS		 6985 if (vcpu->arch.apicv_active)
6986 return;
6987
8db3baa2
GN		 6988 if (!vcpu->arch.apic->vapic_addr)
6989 max_irr = kvm_lapic_find_highest_irr(vcpu);
6990 else
6991 max_irr = -1;
95ba8273
GN		 6992
6993 if (max_irr != -1)
6994 max_irr >>= 4;
6995
6996 tpr = kvm_lapic_get_cr8(vcpu);
6997
6998 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6999}
7000
b6b8a145 7001static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7002{
b6b8a145
JK		 7003 int r;
7004
95ba8273 7005 /* try to reinject previous events if any */
664f8e26 7006
1a680e35
LA		 7007 if (vcpu->arch.exception.injected)
7008 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7009 /*
a042c26f
LA		 7010 * Do not inject an NMI or interrupt if there is a pending
7011 * exception. Exceptions and interrupts are recognized at
7012 * instruction boundaries, i.e. the start of an instruction.
7013 * Trap-like exceptions, e.g. #DB, have higher priority than
7014 * NMIs and interrupts, i.e. traps are recognized before an
7015 * NMI/interrupt that's pending on the same instruction.
7016 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7017 * priority, but are only generated (pended) during instruction
7018 * execution, i.e. a pending fault-like exception means the
7019 * fault occurred on the *previous* instruction and must be
7020 * serviced prior to recognizing any new events in order to
7021 * fully complete the previous instruction.
664f8e26 7022 */
1a680e35
LA		 7023 else if (!vcpu->arch.exception.pending) {
7024 if (vcpu->arch.nmi_injected)
664f8e26 7025 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7026 else if (vcpu->arch.interrupt.injected)
664f8e26 7027 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7028 }
7029
1a680e35
LA		 7030 /*
7031 * Call check_nested_events() even if we reinjected a previous event
7032 * in order for caller to determine if it should require immediate-exit
7033 * from L2 to L1 due to pending L1 events which require exit
7034 * from L2 to L1.
7035 */
664f8e26
WL		 7036 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7037 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7038 if (r != 0)
7039 return r;
7040 }
7041
7042 /* try to inject new event if pending */
b59bb7bd 7043 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7044 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7045 vcpu->arch.exception.has_error_code,
7046 vcpu->arch.exception.error_code);
d6e8c854 7047
1a680e35 7048 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7049 vcpu->arch.exception.pending = false;
7050 vcpu->arch.exception.injected = true;
7051
d6e8c854
NA		 7052 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7053 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7054 X86_EFLAGS_RF);
7055
6bdf0662
NA		 7056 if (vcpu->arch.exception.nr == DB_VECTOR &&
7057 (vcpu->arch.dr7 & DR7_GD)) {
7058 vcpu->arch.dr7 &= ~DR7_GD;
7059 kvm_update_dr7(vcpu);
7060 }
7061
cfcd20e5 7062 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7063 }
7064
7065 /* Don't consider new event if we re-injected an event */
7066 if (kvm_event_needs_reinjection(vcpu))
7067 return 0;
7068
7069 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7070 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7071 vcpu->arch.smi_pending = false;
52797bf9 7072 ++vcpu->arch.smi_count;
ee2cd4b7 7073 enter_smm(vcpu);
c43203ca 7074 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7075 --vcpu->arch.nmi_pending;
7076 vcpu->arch.nmi_injected = true;
7077 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7078 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7079 /*
7080 * Because interrupts can be injected asynchronously, we are
7081 * calling check_nested_events again here to avoid a race condition.
7082 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7083 * proposal and current concerns. Perhaps we should be setting
7084 * KVM_REQ_EVENT only on certain events and not unconditionally?
7085 */
7086 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7087 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7088 if (r != 0)
7089 return r;
7090 }
95ba8273 7091 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7092 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7093 false);
7094 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7095 }
7096 }
ee2cd4b7 7097
b6b8a145 7098 return 0;
95ba8273
GN		 7099}
7100
7460fb4a
AK		 7101static void process_nmi(struct kvm_vcpu *vcpu)
7102{
7103 unsigned limit = 2;
7104
7105 /*
7106 * x86 is limited to one NMI running, and one NMI pending after it.
7107 * If an NMI is already in progress, limit further NMIs to just one.
7108 * Otherwise, allow two (and we'll inject the first one immediately).
7109 */
7110 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7111 limit = 1;
7112
7113 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7114 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7115 kvm_make_request(KVM_REQ_EVENT, vcpu);
7116}
7117
ee2cd4b7 7118static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7119{
7120 u32 flags = 0;
7121 flags |= seg->g << 23;
7122 flags |= seg->db << 22;
7123 flags |= seg->l << 21;
7124 flags |= seg->avl << 20;
7125 flags |= seg->present << 15;
7126 flags |= seg->dpl << 13;
7127 flags |= seg->s << 12;
7128 flags |= seg->type << 8;
7129 return flags;
7130}
7131
ee2cd4b7 7132static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7133{
7134 struct kvm_segment seg;
7135 int offset;
7136
7137 kvm_get_segment(vcpu, &seg, n);
7138 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7139
7140 if (n < 3)
7141 offset = 0x7f84 + n * 12;
7142 else
7143 offset = 0x7f2c + (n - 3) * 12;
7144
7145 put_smstate(u32, buf, offset + 8, seg.base);
7146 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7147 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7148}
7149
efbb288a 7150#ifdef CONFIG_X86_64
ee2cd4b7 7151static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7152{
7153 struct kvm_segment seg;
7154 int offset;
7155 u16 flags;
7156
7157 kvm_get_segment(vcpu, &seg, n);
7158 offset = 0x7e00 + n * 16;
7159
ee2cd4b7 7160 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7161 put_smstate(u16, buf, offset, seg.selector);
7162 put_smstate(u16, buf, offset + 2, flags);
7163 put_smstate(u32, buf, offset + 4, seg.limit);
7164 put_smstate(u64, buf, offset + 8, seg.base);
7165}
efbb288a 7166#endif
660a5d51 7167
ee2cd4b7 7168static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7169{
7170 struct desc_ptr dt;
7171 struct kvm_segment seg;
7172 unsigned long val;
7173 int i;
7174
7175 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7176 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7177 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7178 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7179
7180 for (i = 0; i < 8; i++)
7181 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7182
7183 kvm_get_dr(vcpu, 6, &val);
7184 put_smstate(u32, buf, 0x7fcc, (u32)val);
7185 kvm_get_dr(vcpu, 7, &val);
7186 put_smstate(u32, buf, 0x7fc8, (u32)val);
7187
7188 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7189 put_smstate(u32, buf, 0x7fc4, seg.selector);
7190 put_smstate(u32, buf, 0x7f64, seg.base);
7191 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7192 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7193
7194 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7195 put_smstate(u32, buf, 0x7fc0, seg.selector);
7196 put_smstate(u32, buf, 0x7f80, seg.base);
7197 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7198 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7199
7200 kvm_x86_ops->get_gdt(vcpu, &dt);
7201 put_smstate(u32, buf, 0x7f74, dt.address);
7202 put_smstate(u32, buf, 0x7f70, dt.size);
7203
7204 kvm_x86_ops->get_idt(vcpu, &dt);
7205 put_smstate(u32, buf, 0x7f58, dt.address);
7206 put_smstate(u32, buf, 0x7f54, dt.size);
7207
7208 for (i = 0; i < 6; i++)
ee2cd4b7 7209 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7210
7211 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7212
7213 /* revision id */
7214 put_smstate(u32, buf, 0x7efc, 0x00020000);
7215 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7216}
7217
ee2cd4b7 7218static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7219{
7220#ifdef CONFIG_X86_64
7221 struct desc_ptr dt;
7222 struct kvm_segment seg;
7223 unsigned long val;
7224 int i;
7225
7226 for (i = 0; i < 16; i++)
7227 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7228
7229 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7230 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7231
7232 kvm_get_dr(vcpu, 6, &val);
7233 put_smstate(u64, buf, 0x7f68, val);
7234 kvm_get_dr(vcpu, 7, &val);
7235 put_smstate(u64, buf, 0x7f60, val);
7236
7237 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7238 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7239 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7240
7241 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7242
7243 /* revision id */
7244 put_smstate(u32, buf, 0x7efc, 0x00020064);
7245
7246 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7247
7248 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7249 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7250 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7251 put_smstate(u32, buf, 0x7e94, seg.limit);
7252 put_smstate(u64, buf, 0x7e98, seg.base);
7253
7254 kvm_x86_ops->get_idt(vcpu, &dt);
7255 put_smstate(u32, buf, 0x7e84, dt.size);
7256 put_smstate(u64, buf, 0x7e88, dt.address);
7257
7258 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7259 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7260 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7261 put_smstate(u32, buf, 0x7e74, seg.limit);
7262 put_smstate(u64, buf, 0x7e78, seg.base);
7263
7264 kvm_x86_ops->get_gdt(vcpu, &dt);
7265 put_smstate(u32, buf, 0x7e64, dt.size);
7266 put_smstate(u64, buf, 0x7e68, dt.address);
7267
7268 for (i = 0; i < 6; i++)
ee2cd4b7 7269 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7270#else
7271 WARN_ON_ONCE(1);
7272#endif
7273}
7274
ee2cd4b7 7275static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7276{
660a5d51 7277 struct kvm_segment cs, ds;
18c3626e 7278 struct desc_ptr dt;
660a5d51
PB		 7279 char buf[512];
7280 u32 cr0;
7281
660a5d51 7282 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7283 memset(buf, 0, 512);
d6321d49 7284 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7285 enter_smm_save_state_64(vcpu, buf);
660a5d51 7286 else
ee2cd4b7 7287 enter_smm_save_state_32(vcpu, buf);
660a5d51 7288
0234bf88
LP		 7289 /*
7290 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7291 * vCPU state (e.g. leave guest mode) after we've saved the state into
7292 * the SMM state-save area.
7293 */
7294 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7295
7296 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7297 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7298
7299 if (kvm_x86_ops->get_nmi_mask(vcpu))
7300 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7301 else
7302 kvm_x86_ops->set_nmi_mask(vcpu, true);
7303
7304 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7305 kvm_rip_write(vcpu, 0x8000);
7306
7307 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7308 kvm_x86_ops->set_cr0(vcpu, cr0);
7309 vcpu->arch.cr0 = cr0;
7310
7311 kvm_x86_ops->set_cr4(vcpu, 0);
7312
18c3626e
PB		 7313 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7314 dt.address = dt.size = 0;
7315 kvm_x86_ops->set_idt(vcpu, &dt);
7316
660a5d51
PB		 7317 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7318
7319 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7320 cs.base = vcpu->arch.smbase;
7321
7322 ds.selector = 0;
7323 ds.base = 0;
7324
7325 cs.limit = ds.limit = 0xffffffff;
7326 cs.type = ds.type = 0x3;
7327 cs.dpl = ds.dpl = 0;
7328 cs.db = ds.db = 0;
7329 cs.s = ds.s = 1;
7330 cs.l = ds.l = 0;
7331 cs.g = ds.g = 1;
7332 cs.avl = ds.avl = 0;
7333 cs.present = ds.present = 1;
7334 cs.unusable = ds.unusable = 0;
7335 cs.padding = ds.padding = 0;
7336
7337 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7338 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7339 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7340 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7341 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7342 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7343
d6321d49 7344 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7345 kvm_x86_ops->set_efer(vcpu, 0);
7346
7347 kvm_update_cpuid(vcpu);
7348 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7349}
7350
ee2cd4b7 7351static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7352{
7353 vcpu->arch.smi_pending = true;
7354 kvm_make_request(KVM_REQ_EVENT, vcpu);
7355}
7356
2860c4b1
PB		 7357void kvm_make_scan_ioapic_request(struct kvm *kvm)
7358{
7359 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7360}
7361
3d81bc7e 7362static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7363{
3d81bc7e
YZ		 7364 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7365 return;
c7c9c56c 7366
6308630b 7367 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7368
b053b2ae 7369 if (irqchip_split(vcpu->kvm))
6308630b 7370 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7371 else {
fa59cc00 7372 if (vcpu->arch.apicv_active)
d62caabb 7373 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7374 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7375 }
e40ff1d6
LA		 7376
7377 if (is_guest_mode(vcpu))
7378 vcpu->arch.load_eoi_exitmap_pending = true;
7379 else
7380 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7381}
7382
7383static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7384{
7385 u64 eoi_exit_bitmap[4];
7386
7387 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7388 return;
7389
5c919412
AS		 7390 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7391 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7392 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7393}
7394
93065ac7
MH		 7395int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7396 unsigned long start, unsigned long end,
7397 bool blockable)
b1394e74
RK		 7398{
7399 unsigned long apic_address;
7400
7401 /*
7402 * The physical address of apic access page is stored in the VMCS.
7403 * Update it when it becomes invalid.
7404 */
7405 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7406 if (start <= apic_address && apic_address < end)
7407 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7408
7409 return 0;
b1394e74
RK		 7410}
7411
4256f43f
TC		 7412void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7413{
c24ae0dc
TC		 7414 struct page *page = NULL;
7415
35754c98 7416 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7417 return;
7418
4256f43f
TC		 7419 if (!kvm_x86_ops->set_apic_access_page_addr)
7420 return;
7421
c24ae0dc 7422 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7423 if (is_error_page(page))
7424 return;
c24ae0dc
TC		 7425 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7426
7427 /*
7428 * Do not pin apic access page in memory, the MMU notifier
7429 * will call us again if it is migrated or swapped out.
7430 */
7431 put_page(page);
4256f43f
TC		 7432}
7433EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7434
d264ee0c
SC		 7435void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7436{
7437 smp_send_reschedule(vcpu->cpu);
7438}
7439EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7440
9357d939 7441/*
362c698f 7442 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7443 * exiting to the userspace. Otherwise, the value will be returned to the
7444 * userspace.
7445 */
851ba692 7446static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7447{
7448 int r;
62a193ed
MG		 7449 bool req_int_win =
7450 dm_request_for_irq_injection(vcpu) &&
7451 kvm_cpu_accept_dm_intr(vcpu);
7452
730dca42 7453 bool req_immediate_exit = false;
b6c7a5dc 7454
2fa6e1e1 7455 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7456 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7457 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7458 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7459 kvm_mmu_unload(vcpu);
a8eeb04a 7460 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7461 __kvm_migrate_timers(vcpu);
d828199e
MT		 7462 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7463 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7464 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7465 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7466 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7467 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7468 if (unlikely(r))
7469 goto out;
7470 }
a8eeb04a 7471 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7472 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7473 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7474 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7475 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7476 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7477 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7478 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7479 r = 0;
7480 goto out;
7481 }
a8eeb04a 7482 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7483 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7484 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7485 r = 0;
7486 goto out;
7487 }
af585b92
GN		 7488 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7489 /* Page is swapped out. Do synthetic halt */
7490 vcpu->arch.apf.halted = true;
7491 r = 1;
7492 goto out;
7493 }
c9aaa895
GC		 7494 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7495 record_steal_time(vcpu);
64d60670
PB		 7496 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7497 process_smi(vcpu);
7460fb4a
AK		 7498 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7499 process_nmi(vcpu);
f5132b01 7500 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7501 kvm_pmu_handle_event(vcpu);
f5132b01 7502 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7503 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7504 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7505 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7506 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7507 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7508 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7509 vcpu->run->eoi.vector =
7510 vcpu->arch.pending_ioapic_eoi;
7511 r = 0;
7512 goto out;
7513 }
7514 }
3d81bc7e
YZ		 7515 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7516 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7517 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7518 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7519 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7520 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7521 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7522 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7523 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7524 r = 0;
7525 goto out;
7526 }
e516cebb
AS		 7527 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7528 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7529 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7530 r = 0;
7531 goto out;
7532 }
db397571
AS		 7533 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7534 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7535 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7536 r = 0;
7537 goto out;
7538 }
f3b138c5
AS		 7539
7540 /*
7541 * KVM_REQ_HV_STIMER has to be processed after
7542 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7543 * depend on the guest clock being up-to-date
7544 */
1f4b34f8
AS		 7545 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7546 kvm_hv_process_stimers(vcpu);
2f52d58c 7547 }
b93463aa 7548
b463a6f7 7549 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7550 ++vcpu->stat.req_event;
66450a21
JK		 7551 kvm_apic_accept_events(vcpu);
7552 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7553 r = 1;
7554 goto out;
7555 }
7556
b6b8a145
JK		 7557 if (inject_pending_event(vcpu, req_int_win) != 0)
7558 req_immediate_exit = true;
321c5658 7559 else {
cc3d967f 7560 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7561 *
cc3d967f
LP		 7562 * SMIs have three cases:
7563 * 1) They can be nested, and then there is nothing to
7564 * do here because RSM will cause a vmexit anyway.
7565 * 2) There is an ISA-specific reason why SMI cannot be
7566 * injected, and the moment when this changes can be
7567 * intercepted.
7568 * 3) Or the SMI can be pending because
7569 * inject_pending_event has completed the injection
7570 * of an IRQ or NMI from the previous vmexit, and
7571 * then we request an immediate exit to inject the
7572 * SMI.
c43203ca
PB		 7573 */
7574 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7575 if (!kvm_x86_ops->enable_smi_window(vcpu))
7576 req_immediate_exit = true;
321c5658
YS		 7577 if (vcpu->arch.nmi_pending)
7578 kvm_x86_ops->enable_nmi_window(vcpu);
7579 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7580 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7581 WARN_ON(vcpu->arch.exception.pending);
321c5658 7582 }
b463a6f7
AK		 7583
7584 if (kvm_lapic_enabled(vcpu)) {
7585 update_cr8_intercept(vcpu);
7586 kvm_lapic_sync_to_vapic(vcpu);
7587 }
7588 }
7589
d8368af8
AK		 7590 r = kvm_mmu_reload(vcpu);
7591 if (unlikely(r)) {
d905c069 7592 goto cancel_injection;
d8368af8
AK		 7593 }
7594
b6c7a5dc
HB		 7595 preempt_disable();
7596
7597 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7598
7599 /*
7600 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7601 * IPI are then delayed after guest entry, which ensures that they
7602 * result in virtual interrupt delivery.
7603 */
7604 local_irq_disable();
6b7e2d09
XG		 7605 vcpu->mode = IN_GUEST_MODE;
7606
01b71917
MT		 7607 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7608
0f127d12 7609 /*
b95234c8 7610 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7611 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7612 *
7613 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7614 * pairs with the memory barrier implicit in pi_test_and_set_on
7615 * (see vmx_deliver_posted_interrupt).
7616 *
7617 * 3) This also orders the write to mode from any reads to the page
7618 * tables done while the VCPU is running. Please see the comment
7619 * in kvm_flush_remote_tlbs.
6b7e2d09 7620 */
01b71917 7621 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7622
b95234c8
PB		 7623 /*
7624 * This handles the case where a posted interrupt was
7625 * notified with kvm_vcpu_kick.
7626 */
fa59cc00
LA		 7627 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7628 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7629
2fa6e1e1 7630 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7631 || need_resched() || signal_pending(current)) {
6b7e2d09 7632 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7633 smp_wmb();
6c142801
AK		 7634 local_irq_enable();
7635 preempt_enable();
01b71917 7636 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7637 r = 1;
d905c069 7638 goto cancel_injection;
6c142801
AK		 7639 }
7640
fc5b7f3b
DM		 7641 kvm_load_guest_xcr0(vcpu);
7642
c43203ca
PB		 7643 if (req_immediate_exit) {
7644 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7645 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7646 }
d6185f20 7647
8b89fe1f 7648 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7649 if (lapic_timer_advance_ns)
7650 wait_lapic_expire(vcpu);
6edaa530 7651 guest_enter_irqoff();
b6c7a5dc 7652
42dbaa5a 7653 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7654 set_debugreg(0, 7);
7655 set_debugreg(vcpu->arch.eff_db[0], 0);
7656 set_debugreg(vcpu->arch.eff_db[1], 1);
7657 set_debugreg(vcpu->arch.eff_db[2], 2);
7658 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7659 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7660 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7661 }
b6c7a5dc 7662
851ba692 7663 kvm_x86_ops->run(vcpu);
b6c7a5dc 7664
c77fb5fe
PB		 7665 /*
7666 * Do this here before restoring debug registers on the host. And
7667 * since we do this before handling the vmexit, a DR access vmexit
7668 * can (a) read the correct value of the debug registers, (b) set
7669 * KVM_DEBUGREG_WONT_EXIT again.
7670 */
7671 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7672 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7673 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7674 kvm_update_dr0123(vcpu);
7675 kvm_update_dr6(vcpu);
7676 kvm_update_dr7(vcpu);
7677 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7678 }
7679
24f1e32c
FW		 7680 /*
7681 * If the guest has used debug registers, at least dr7
7682 * will be disabled while returning to the host.
7683 * If we don't have active breakpoints in the host, we don't
7684 * care about the messed up debug address registers. But if
7685 * we have some of them active, restore the old state.
7686 */
59d8eb53 7687 if (hw_breakpoint_active())
24f1e32c 7688 hw_breakpoint_restore();
42dbaa5a 7689
4ba76538 7690 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7691
6b7e2d09 7692 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7693 smp_wmb();
a547c6db 7694
fc5b7f3b
DM		 7695 kvm_put_guest_xcr0(vcpu);
7696
dd60d217 7697 kvm_before_interrupt(vcpu);
a547c6db 7698 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7699 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7700
7701 ++vcpu->stat.exits;
7702
f2485b3e 7703 guest_exit_irqoff();
b6c7a5dc 7704
f2485b3e 7705 local_irq_enable();
b6c7a5dc
HB		 7706 preempt_enable();
7707
f656ce01 7708 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7709
b6c7a5dc
HB		 7710 /*
7711 * Profile KVM exit RIPs:
7712 */
7713 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7714 unsigned long rip = kvm_rip_read(vcpu);
7715 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7716 }
7717
cc578287
ZA		 7718 if (unlikely(vcpu->arch.tsc_always_catchup))
7719 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7720
5cfb1d5a
MT		 7721 if (vcpu->arch.apic_attention)
7722 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7723
618232e2 7724 vcpu->arch.gpa_available = false;
851ba692 7725 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7726 return r;
7727
7728cancel_injection:
7729 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7730 if (unlikely(vcpu->arch.apic_attention))
7731 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7732out:
7733 return r;
7734}
b6c7a5dc 7735
362c698f
PB		 7736static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7737{
bf9f6ac8
FW		 7738 if (!kvm_arch_vcpu_runnable(vcpu) &&
7739 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7740 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7741 kvm_vcpu_block(vcpu);
7742 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7743
7744 if (kvm_x86_ops->post_block)
7745 kvm_x86_ops->post_block(vcpu);
7746
9c8fd1ba
PB		 7747 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7748 return 1;
7749 }
362c698f
PB		 7750
7751 kvm_apic_accept_events(vcpu);
7752 switch(vcpu->arch.mp_state) {
7753 case KVM_MP_STATE_HALTED:
7754 vcpu->arch.pv.pv_unhalted = false;
7755 vcpu->arch.mp_state =
7756 KVM_MP_STATE_RUNNABLE;
7757 case KVM_MP_STATE_RUNNABLE:
7758 vcpu->arch.apf.halted = false;
7759 break;
7760 case KVM_MP_STATE_INIT_RECEIVED:
7761 break;
7762 default:
7763 return -EINTR;
7764 break;
7765 }
7766 return 1;
7767}
09cec754 7768
5d9bc648
PB		 7769static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7770{
0ad3bed6
PB		 7771 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7772 kvm_x86_ops->check_nested_events(vcpu, false);
7773
5d9bc648
PB		 7774 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7775 !vcpu->arch.apf.halted);
7776}
7777
362c698f 7778static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7779{
7780 int r;
f656ce01 7781 struct kvm *kvm = vcpu->kvm;
d7690175 7782
f656ce01 7783 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 7784 vcpu->arch.l1tf_flush_l1d = true;
d7690175 7785
362c698f 7786 for (;;) {
58f800d5 7787 if (kvm_vcpu_running(vcpu)) {
851ba692 7788 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7789 } else {
362c698f 7790 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7791 }
7792
09cec754
GN		 7793 if (r <= 0)
7794 break;
7795
72875d8a 7796 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7797 if (kvm_cpu_has_pending_timer(vcpu))
7798 kvm_inject_pending_timer_irqs(vcpu);
7799
782d422b
MG		 7800 if (dm_request_for_irq_injection(vcpu) &&
7801 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7802 r = 0;
7803 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7804 ++vcpu->stat.request_irq_exits;
362c698f 7805 break;
09cec754 7806 }
af585b92
GN		 7807
7808 kvm_check_async_pf_completion(vcpu);
7809
09cec754
GN		 7810 if (signal_pending(current)) {
7811 r = -EINTR;
851ba692 7812 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7813 ++vcpu->stat.signal_exits;
362c698f 7814 break;
09cec754
GN		 7815 }
7816 if (need_resched()) {
f656ce01 7817 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7818 cond_resched();
f656ce01 7819 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7820 }
b6c7a5dc
HB		 7821 }
7822
f656ce01 7823 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7824
7825 return r;
7826}
7827
716d51ab
GN		 7828static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7829{
7830 int r;
7831 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 7832 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 7833 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7834 if (r != EMULATE_DONE)
7835 return 0;
7836 return 1;
7837}
7838
7839static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7840{
7841 BUG_ON(!vcpu->arch.pio.count);
7842
7843 return complete_emulated_io(vcpu);
7844}
7845
f78146b0
AK		 7846/*
7847 * Implements the following, as a state machine:
7848 *
7849 * read:
7850 * for each fragment
87da7e66
XG		 7851 * for each mmio piece in the fragment
7852 * write gpa, len
7853 * exit
7854 * copy data
f78146b0
AK		 7855 * execute insn
7856 *
7857 * write:
7858 * for each fragment
87da7e66
XG		 7859 * for each mmio piece in the fragment
7860 * write gpa, len
7861 * copy data
7862 * exit
f78146b0 7863 */
716d51ab 7864static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7865{
7866 struct kvm_run *run = vcpu->run;
f78146b0 7867 struct kvm_mmio_fragment *frag;
87da7e66 7868 unsigned len;
5287f194 7869
716d51ab 7870 BUG_ON(!vcpu->mmio_needed);
5287f194 7871
716d51ab 7872 /* Complete previous fragment */
87da7e66
XG		 7873 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7874 len = min(8u, frag->len);
716d51ab 7875 if (!vcpu->mmio_is_write)
87da7e66
XG		 7876 memcpy(frag->data, run->mmio.data, len);
7877
7878 if (frag->len <= 8) {
7879 /* Switch to the next fragment. */
7880 frag++;
7881 vcpu->mmio_cur_fragment++;
7882 } else {
7883 /* Go forward to the next mmio piece. */
7884 frag->data += len;
7885 frag->gpa += len;
7886 frag->len -= len;
7887 }
7888
a08d3b3b 7889 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7890 vcpu->mmio_needed = 0;
0912c977
PB		 7891
7892 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7893 if (vcpu->mmio_is_write)
716d51ab
GN		 7894 return 1;
7895 vcpu->mmio_read_completed = 1;
7896 return complete_emulated_io(vcpu);
7897 }
87da7e66 7898
716d51ab
GN		 7899 run->exit_reason = KVM_EXIT_MMIO;
7900 run->mmio.phys_addr = frag->gpa;
7901 if (vcpu->mmio_is_write)
87da7e66
XG		 7902 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7903 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7904 run->mmio.is_write = vcpu->mmio_is_write;
7905 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7906 return 0;
5287f194
AK		 7907}
7908
822f312d
SAS		 7909/* Swap (qemu) user FPU context for the guest FPU context. */
7910static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7911{
7912 preempt_disable();
7913 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
7914 /* PKRU is separately restored in kvm_x86_ops->run. */
7915 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7916 ~XFEATURE_MASK_PKRU);
7917 preempt_enable();
7918 trace_kvm_fpu(1);
7919}
7920
7921/* When vcpu_run ends, restore user space FPU context. */
7922static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7923{
7924 preempt_disable();
7925 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7926 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7927 preempt_enable();
7928 ++vcpu->stat.fpu_reload;
7929 trace_kvm_fpu(0);
7930}
7931
b6c7a5dc
HB		 7932int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7933{
7934 int r;
b6c7a5dc 7935
accb757d 7936 vcpu_load(vcpu);
20b7035c 7937 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7938 kvm_load_guest_fpu(vcpu);
7939
a4535290 7940 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7941 if (kvm_run->immediate_exit) {
7942 r = -EINTR;
7943 goto out;
7944 }
b6c7a5dc 7945 kvm_vcpu_block(vcpu);
66450a21 7946 kvm_apic_accept_events(vcpu);
72875d8a 7947 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7948 r = -EAGAIN;
a0595000
JS		 7949 if (signal_pending(current)) {
7950 r = -EINTR;
7951 vcpu->run->exit_reason = KVM_EXIT_INTR;
7952 ++vcpu->stat.signal_exits;
7953 }
ac9f6dc0 7954 goto out;
b6c7a5dc
HB		 7955 }
7956
01643c51
KH		 7957 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7958 r = -EINVAL;
7959 goto out;
7960 }
7961
7962 if (vcpu->run->kvm_dirty_regs) {
7963 r = sync_regs(vcpu);
7964 if (r != 0)
7965 goto out;
7966 }
7967
b6c7a5dc 7968 /* re-sync apic's tpr */
35754c98 7969 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7970 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7971 r = -EINVAL;
7972 goto out;
7973 }
7974 }
b6c7a5dc 7975
716d51ab
GN		 7976 if (unlikely(vcpu->arch.complete_userspace_io)) {
7977 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7978 vcpu->arch.complete_userspace_io = NULL;
7979 r = cui(vcpu);
7980 if (r <= 0)
5663d8f9 7981 goto out;
716d51ab
GN		 7982 } else
7983 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7984
460df4c1
PB		 7985 if (kvm_run->immediate_exit)
7986 r = -EINTR;
7987 else
7988 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7989
7990out:
5663d8f9 7991 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7992 if (vcpu->run->kvm_valid_regs)
7993 store_regs(vcpu);
f1d86e46 7994 post_kvm_run_save(vcpu);
20b7035c 7995 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7996
accb757d 7997 vcpu_put(vcpu);
b6c7a5dc
HB		 7998 return r;
7999}
8000
01643c51 8001static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8002{
7ae441ea
GN		 8003 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8004 /*
8005 * We are here if userspace calls get_regs() in the middle of
8006 * instruction emulation. Registers state needs to be copied
4a969980 8007 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8008 * that usually, but some bad designed PV devices (vmware
8009 * backdoor interface) need this to work
8010 */
dd856efa 8011 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8012 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8013 }
5fdbf976
MT		 8014 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
8015 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
8016 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
8017 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
8018 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
8019 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
8020 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8021 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 8022#ifdef CONFIG_X86_64
5fdbf976
MT		 8023 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
8024 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
8025 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
8026 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
8027 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
8028 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
8029 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
8030 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 8031#endif
8032
5fdbf976 8033 regs->rip = kvm_rip_read(vcpu);
91586a3b 8034 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8035}
b6c7a5dc 8036
01643c51
KH		 8037int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8038{
8039 vcpu_load(vcpu);
8040 __get_regs(vcpu, regs);
1fc9b76b 8041 vcpu_put(vcpu);
b6c7a5dc
HB		 8042 return 0;
8043}
8044
01643c51 8045static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8046{
7ae441ea
GN		 8047 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8048 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8049
5fdbf976
MT		 8050 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
8051 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
8052 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
8053 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
8054 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
8055 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
8056 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
8057 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 8058#ifdef CONFIG_X86_64
5fdbf976
MT		 8059 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
8060 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
8061 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
8062 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
8063 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
8064 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
8065 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
8066 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 8067#endif
8068
5fdbf976 8069 kvm_rip_write(vcpu, regs->rip);
d73235d1 8070 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8071
b4f14abd
JK		 8072 vcpu->arch.exception.pending = false;
8073
3842d135 8074 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8075}
3842d135 8076
01643c51
KH		 8077int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8078{
8079 vcpu_load(vcpu);
8080 __set_regs(vcpu, regs);
875656fe 8081 vcpu_put(vcpu);
b6c7a5dc
HB		 8082 return 0;
8083}
8084
b6c7a5dc
HB		 8085void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8086{
8087 struct kvm_segment cs;
8088
3e6e0aab 8089 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8090 *db = cs.db;
8091 *l = cs.l;
8092}
8093EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8094
01643c51 8095static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8096{
89a27f4d 8097 struct desc_ptr dt;
b6c7a5dc 8098
3e6e0aab
GT		 8099 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8100 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8101 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8102 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8103 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8104 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8105
3e6e0aab
GT		 8106 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8107 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8108
8109 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8110 sregs->idt.limit = dt.size;
8111 sregs->idt.base = dt.address;
b6c7a5dc 8112 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8113 sregs->gdt.limit = dt.size;
8114 sregs->gdt.base = dt.address;
b6c7a5dc 8115
4d4ec087 8116 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8117 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8118 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8119 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8120 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8121 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8122 sregs->apic_base = kvm_get_apic_base(vcpu);
8123
923c61bb 8124 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 8125
04140b41 8126 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8127 set_bit(vcpu->arch.interrupt.nr,
8128 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8129}
16d7a191 8130
01643c51
KH		 8131int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8132 struct kvm_sregs *sregs)
8133{
8134 vcpu_load(vcpu);
8135 __get_sregs(vcpu, sregs);
bcdec41c 8136 vcpu_put(vcpu);
b6c7a5dc
HB		 8137 return 0;
8138}
8139
62d9f0db
MT		 8140int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8141 struct kvm_mp_state *mp_state)
8142{
fd232561
CD		 8143 vcpu_load(vcpu);
8144
66450a21 8145 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8146 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8147 vcpu->arch.pv.pv_unhalted)
8148 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8149 else
8150 mp_state->mp_state = vcpu->arch.mp_state;
8151
fd232561 8152 vcpu_put(vcpu);
62d9f0db
MT		 8153 return 0;
8154}
8155
8156int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8157 struct kvm_mp_state *mp_state)
8158{
e83dff5e
CD		 8159 int ret = -EINVAL;
8160
8161 vcpu_load(vcpu);
8162
bce87cce 8163 if (!lapic_in_kernel(vcpu) &&
66450a21 8164 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8165 goto out;
66450a21 8166
28bf2888
DH		 8167 /* INITs are latched while in SMM */
8168 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8169 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8170 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8171 goto out;
28bf2888 8172
66450a21
JK		 8173 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8174 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8175 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8176 } else
8177 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8178 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8179
8180 ret = 0;
8181out:
8182 vcpu_put(vcpu);
8183 return ret;
62d9f0db
MT		 8184}
8185
7f3d35fd
KW		 8186int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8187 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8188{
9d74191a 8189 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8190 int ret;
e01c2426 8191
8ec4722d 8192 init_emulate_ctxt(vcpu);
c697518a 8193
7f3d35fd 8194 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8195 has_error_code, error_code);
c697518a 8196
c697518a 8197 if (ret)
19d04437 8198 return EMULATE_FAIL;
37817f29 8199
9d74191a
TY		 8200 kvm_rip_write(vcpu, ctxt->eip);
8201 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8202 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8203 return EMULATE_DONE;
37817f29
IE		 8204}
8205EXPORT_SYMBOL_GPL(kvm_task_switch);
8206
3140c156 8207static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8208{
74fec5b9
TL		 8209 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8210 (sregs->cr4 & X86_CR4_OSXSAVE))
8211 return -EINVAL;
8212
37b95951 8213 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8214 /*
8215 * When EFER.LME and CR0.PG are set, the processor is in
8216 * 64-bit mode (though maybe in a 32-bit code segment).
8217 * CR4.PAE and EFER.LMA must be set.
8218 */
37b95951 8219 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8220 || !(sregs->efer & EFER_LMA))
8221 return -EINVAL;
8222 } else {
8223 /*
8224 * Not in 64-bit mode: EFER.LMA is clear and the code
8225 * segment cannot be 64-bit.
8226 */
8227 if (sregs->efer & EFER_LMA || sregs->cs.l)
8228 return -EINVAL;
8229 }
8230
8231 return 0;
8232}
8233
01643c51 8234static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8235{
58cb628d 8236 struct msr_data apic_base_msr;
b6c7a5dc 8237 int mmu_reset_needed = 0;
c4d21882 8238 int cpuid_update_needed = 0;
63f42e02 8239 int pending_vec, max_bits, idx;
89a27f4d 8240 struct desc_ptr dt;
b4ef9d4e
CD		 8241 int ret = -EINVAL;
8242
f2981033 8243 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8244 goto out;
f2981033 8245
d3802286
JM		 8246 apic_base_msr.data = sregs->apic_base;
8247 apic_base_msr.host_initiated = true;
8248 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8249 goto out;
6d1068b3 8250
89a27f4d
GN		 8251 dt.size = sregs->idt.limit;
8252 dt.address = sregs->idt.base;
b6c7a5dc 8253 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8254 dt.size = sregs->gdt.limit;
8255 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8256 kvm_x86_ops->set_gdt(vcpu, &dt);
8257
ad312c7c 8258 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8259 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8260 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8261 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8262
2d3ad1f4 8263 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8264
f6801dff 8265 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8266 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8267
4d4ec087 8268 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8269 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8270 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8271
fc78f519 8272 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8273 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8274 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8275 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8276 if (cpuid_update_needed)
00b27a3e 8277 kvm_update_cpuid(vcpu);
63f42e02
XG		 8278
8279 idx = srcu_read_lock(&vcpu->kvm->srcu);
d35b34a9 8280 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
9f8fe504 8281 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8282 mmu_reset_needed = 1;
8283 }
63f42e02 8284 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8285
8286 if (mmu_reset_needed)
8287 kvm_mmu_reset_context(vcpu);
8288
a50abc3b 8289 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8290 pending_vec = find_first_bit(
8291 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8292 if (pending_vec < max_bits) {
66fd3f7f 8293 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8294 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8295 }
8296
3e6e0aab
GT		 8297 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8298 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8299 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8300 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8301 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8302 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8303
3e6e0aab
GT		 8304 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8305 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8306
5f0269f5
ME		 8307 update_cr8_intercept(vcpu);
8308
9c3e4aab 8309 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8310 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8311 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8312 !is_protmode(vcpu))
9c3e4aab
MT		 8313 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8314
3842d135
AK		 8315 kvm_make_request(KVM_REQ_EVENT, vcpu);
8316
b4ef9d4e
CD		 8317 ret = 0;
8318out:
01643c51
KH		 8319 return ret;
8320}
8321
8322int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8323 struct kvm_sregs *sregs)
8324{
8325 int ret;
8326
8327 vcpu_load(vcpu);
8328 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8329 vcpu_put(vcpu);
8330 return ret;
b6c7a5dc
HB		 8331}
8332
d0bfb940
JK		 8333int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8334 struct kvm_guest_debug *dbg)
b6c7a5dc 8335{
355be0b9 8336 unsigned long rflags;
ae675ef0 8337 int i, r;
b6c7a5dc 8338
66b56562
CD		 8339 vcpu_load(vcpu);
8340
4f926bf2
JK		 8341 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8342 r = -EBUSY;
8343 if (vcpu->arch.exception.pending)
2122ff5e 8344 goto out;
4f926bf2
JK		 8345 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8346 kvm_queue_exception(vcpu, DB_VECTOR);
8347 else
8348 kvm_queue_exception(vcpu, BP_VECTOR);
8349 }
8350
91586a3b
JK		 8351 /*
8352 * Read rflags as long as potentially injected trace flags are still
8353 * filtered out.
8354 */
8355 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8356
8357 vcpu->guest_debug = dbg->control;
8358 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8359 vcpu->guest_debug = 0;
8360
8361 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8362 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8363 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8364 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8365 } else {
8366 for (i = 0; i < KVM_NR_DB_REGS; i++)
8367 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8368 }
c8639010 8369 kvm_update_dr7(vcpu);
ae675ef0 8370
f92653ee
JK		 8371 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8372 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8373 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8374
91586a3b
JK		 8375 /*
8376 * Trigger an rflags update that will inject or remove the trace
8377 * flags.
8378 */
8379 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8380
a96036b8 8381 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8382
4f926bf2 8383 r = 0;
d0bfb940 8384
2122ff5e 8385out:
66b56562 8386 vcpu_put(vcpu);
b6c7a5dc
HB		 8387 return r;
8388}
8389
8b006791
ZX		 8390/*
8391 * Translate a guest virtual address to a guest physical address.
8392 */
8393int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8394 struct kvm_translation *tr)
8395{
8396 unsigned long vaddr = tr->linear_address;
8397 gpa_t gpa;
f656ce01 8398 int idx;
8b006791 8399
1da5b61d
CD		 8400 vcpu_load(vcpu);
8401
f656ce01 8402 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8403 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8404 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8405 tr->physical_address = gpa;
8406 tr->valid = gpa != UNMAPPED_GVA;
8407 tr->writeable = 1;
8408 tr->usermode = 0;
8b006791 8409
1da5b61d 8410 vcpu_put(vcpu);
8b006791
ZX		 8411 return 0;
8412}
8413
d0752060
HB		 8414int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8415{
1393123e 8416 struct fxregs_state *fxsave;
d0752060 8417
1393123e 8418 vcpu_load(vcpu);
d0752060 8419
1393123e 8420 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8421 memcpy(fpu->fpr, fxsave->st_space, 128);
8422 fpu->fcw = fxsave->cwd;
8423 fpu->fsw = fxsave->swd;
8424 fpu->ftwx = fxsave->twd;
8425 fpu->last_opcode = fxsave->fop;
8426 fpu->last_ip = fxsave->rip;
8427 fpu->last_dp = fxsave->rdp;
8428 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8429
1393123e 8430 vcpu_put(vcpu);
d0752060
HB		 8431 return 0;
8432}
8433
8434int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8435{
6a96bc7f
CD		 8436 struct fxregs_state *fxsave;
8437
8438 vcpu_load(vcpu);
8439
8440 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8441
d0752060
HB		 8442 memcpy(fxsave->st_space, fpu->fpr, 128);
8443 fxsave->cwd = fpu->fcw;
8444 fxsave->swd = fpu->fsw;
8445 fxsave->twd = fpu->ftwx;
8446 fxsave->fop = fpu->last_opcode;
8447 fxsave->rip = fpu->last_ip;
8448 fxsave->rdp = fpu->last_dp;
8449 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8450
6a96bc7f 8451 vcpu_put(vcpu);
d0752060
HB		 8452 return 0;
8453}
8454
01643c51
KH		 8455static void store_regs(struct kvm_vcpu *vcpu)
8456{
8457 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8458
8459 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8460 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8461
8462 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8463 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8464
8465 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8466 kvm_vcpu_ioctl_x86_get_vcpu_events(
8467 vcpu, &vcpu->run->s.regs.events);
8468}
8469
8470static int sync_regs(struct kvm_vcpu *vcpu)
8471{
8472 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8473 return -EINVAL;
8474
8475 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8476 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8477 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8478 }
8479 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8480 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8481 return -EINVAL;
8482 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8483 }
8484 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8485 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8486 vcpu, &vcpu->run->s.regs.events))
8487 return -EINVAL;
8488 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8489 }
8490
8491 return 0;
8492}
8493
0ee6a517 8494static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8495{
bf935b0b 8496 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8497 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8498 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8499 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8500
2acf923e
DC		 8501 /*
8502 * Ensure guest xcr0 is valid for loading
8503 */
d91cab78 8504 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8505
ad312c7c 8506 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8507}
d0752060 8508
e9b11c17
ZX		 8509void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8510{
bd768e14
IY		 8511 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8512
12f9a48f 8513 kvmclock_reset(vcpu);
7f1ea208 8514
e9b11c17 8515 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8516 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8517}
8518
8519struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8520 unsigned int id)
8521{
c447e76b
LL		 8522 struct kvm_vcpu *vcpu;
8523
b0c39dc6 8524 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8525 printk_once(KERN_WARNING
8526 "kvm: SMP vm created on host with unstable TSC; "
8527 "guest TSC will not be reliable\n");
c447e76b
LL		 8528
8529 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8530
c447e76b 8531 return vcpu;
26e5215f 8532}
e9b11c17 8533
26e5215f
AK		 8534int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8535{
19efffa2 8536 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8537 vcpu_load(vcpu);
d28bc9dd 8538 kvm_vcpu_reset(vcpu, false);
e1732991 8539 kvm_init_mmu(vcpu, false);
e9b11c17 8540 vcpu_put(vcpu);
ec7660cc 8541 return 0;
e9b11c17
ZX		 8542}
8543
31928aa5 8544void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8545{
8fe8ab46 8546 struct msr_data msr;
332967a3 8547 struct kvm *kvm = vcpu->kvm;
42897d86 8548
d3457c87
RK		 8549 kvm_hv_vcpu_postcreate(vcpu);
8550
ec7660cc 8551 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8552 return;
ec7660cc 8553 vcpu_load(vcpu);
8fe8ab46
WA		 8554 msr.data = 0x0;
8555 msr.index = MSR_IA32_TSC;
8556 msr.host_initiated = true;
8557 kvm_write_tsc(vcpu, &msr);
42897d86 8558 vcpu_put(vcpu);
ec7660cc 8559 mutex_unlock(&vcpu->mutex);
42897d86 8560
630994b3
MT		 8561 if (!kvmclock_periodic_sync)
8562 return;
8563
332967a3
AJ		 8564 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8565 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8566}
8567
d40ccc62 8568void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8569{
344d9588
GN		 8570 vcpu->arch.apf.msr_val = 0;
8571
ec7660cc 8572 vcpu_load(vcpu);
e9b11c17
ZX		 8573 kvm_mmu_unload(vcpu);
8574 vcpu_put(vcpu);
8575
8576 kvm_x86_ops->vcpu_free(vcpu);
8577}
8578
d28bc9dd 8579void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8580{
b7e31be3
RK		 8581 kvm_lapic_reset(vcpu, init_event);
8582
e69fab5d
PB		 8583 vcpu->arch.hflags = 0;
8584
c43203ca 8585 vcpu->arch.smi_pending = 0;
52797bf9 8586 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8587 atomic_set(&vcpu->arch.nmi_queued, 0);
8588 vcpu->arch.nmi_pending = 0;
448fa4a9 8589 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8590 kvm_clear_interrupt_queue(vcpu);
8591 kvm_clear_exception_queue(vcpu);
664f8e26 8592 vcpu->arch.exception.pending = false;
448fa4a9 8593
42dbaa5a 8594 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8595 kvm_update_dr0123(vcpu);
6f43ed01 8596 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8597 kvm_update_dr6(vcpu);
42dbaa5a 8598 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8599 kvm_update_dr7(vcpu);
42dbaa5a 8600
1119022c
NA		 8601 vcpu->arch.cr2 = 0;
8602
3842d135 8603 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8604 vcpu->arch.apf.msr_val = 0;
c9aaa895 8605 vcpu->arch.st.msr_val = 0;
3842d135 8606
12f9a48f
GC		 8607 kvmclock_reset(vcpu);
8608
af585b92
GN		 8609 kvm_clear_async_pf_completion_queue(vcpu);
8610 kvm_async_pf_hash_reset(vcpu);
8611 vcpu->arch.apf.halted = false;
3842d135 8612
a554d207
WL		 8613 if (kvm_mpx_supported()) {
8614 void *mpx_state_buffer;
8615
8616 /*
8617 * To avoid have the INIT path from kvm_apic_has_events() that be
8618 * called with loaded FPU and does not let userspace fix the state.
8619 */
f775b13e
RR		 8620 if (init_event)
8621 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8622 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8623 XFEATURE_MASK_BNDREGS);
8624 if (mpx_state_buffer)
8625 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8626 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8627 XFEATURE_MASK_BNDCSR);
8628 if (mpx_state_buffer)
8629 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8630 if (init_event)
8631 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8632 }
8633
64d60670 8634 if (!init_event) {
d28bc9dd 8635 kvm_pmu_reset(vcpu);
64d60670 8636 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8637
8638 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8639 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8640
8641 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8642 }
f5132b01 8643
66f7b72e
JS		 8644 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8645 vcpu->arch.regs_avail = ~0;
8646 vcpu->arch.regs_dirty = ~0;
8647
a554d207
WL		 8648 vcpu->arch.ia32_xss = 0;
8649
d28bc9dd 8650 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8651}
8652
2b4a273b 8653void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8654{
8655 struct kvm_segment cs;
8656
8657 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8658 cs.selector = vector << 8;
8659 cs.base = vector << 12;
8660 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8661 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8662}
8663
13a34e06 8664int kvm_arch_hardware_enable(void)
e9b11c17 8665{
ca84d1a2
ZA		 8666 struct kvm *kvm;
8667 struct kvm_vcpu *vcpu;
8668 int i;
0dd6a6ed
ZA		 8669 int ret;
8670 u64 local_tsc;
8671 u64 max_tsc = 0;
8672 bool stable, backwards_tsc = false;
18863bdd
AK		 8673
8674 kvm_shared_msr_cpu_online();
13a34e06 8675 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8676 if (ret != 0)
8677 return ret;
8678
4ea1636b 8679 local_tsc = rdtsc();
b0c39dc6 8680 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8681 list_for_each_entry(kvm, &vm_list, vm_list) {
8682 kvm_for_each_vcpu(i, vcpu, kvm) {
8683 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8684 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8685 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8686 backwards_tsc = true;
8687 if (vcpu->arch.last_host_tsc > max_tsc)
8688 max_tsc = vcpu->arch.last_host_tsc;
8689 }
8690 }
8691 }
8692
8693 /*
8694 * Sometimes, even reliable TSCs go backwards. This happens on
8695 * platforms that reset TSC during suspend or hibernate actions, but
8696 * maintain synchronization. We must compensate. Fortunately, we can
8697 * detect that condition here, which happens early in CPU bringup,
8698 * before any KVM threads can be running. Unfortunately, we can't
8699 * bring the TSCs fully up to date with real time, as we aren't yet far
8700 * enough into CPU bringup that we know how much real time has actually
108b249c 8701 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8702 * variables that haven't been updated yet.
8703 *
8704 * So we simply find the maximum observed TSC above, then record the
8705 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8706 * the adjustment will be applied. Note that we accumulate
8707 * adjustments, in case multiple suspend cycles happen before some VCPU
8708 * gets a chance to run again. In the event that no KVM threads get a
8709 * chance to run, we will miss the entire elapsed period, as we'll have
8710 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8711 * loose cycle time. This isn't too big a deal, since the loss will be
8712 * uniform across all VCPUs (not to mention the scenario is extremely
8713 * unlikely). It is possible that a second hibernate recovery happens
8714 * much faster than a first, causing the observed TSC here to be
8715 * smaller; this would require additional padding adjustment, which is
8716 * why we set last_host_tsc to the local tsc observed here.
8717 *
8718 * N.B. - this code below runs only on platforms with reliable TSC,
8719 * as that is the only way backwards_tsc is set above. Also note
8720 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8721 * have the same delta_cyc adjustment applied if backwards_tsc
8722 * is detected. Note further, this adjustment is only done once,
8723 * as we reset last_host_tsc on all VCPUs to stop this from being
8724 * called multiple times (one for each physical CPU bringup).
8725 *
4a969980 8726 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8727 * will be compensated by the logic in vcpu_load, which sets the TSC to
8728 * catchup mode. This will catchup all VCPUs to real time, but cannot
8729 * guarantee that they stay in perfect synchronization.
8730 */
8731 if (backwards_tsc) {
8732 u64 delta_cyc = max_tsc - local_tsc;
8733 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8734 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8735 kvm_for_each_vcpu(i, vcpu, kvm) {
8736 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8737 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8738 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8739 }
8740
8741 /*
8742 * We have to disable TSC offset matching.. if you were
8743 * booting a VM while issuing an S4 host suspend....
8744 * you may have some problem. Solving this issue is
8745 * left as an exercise to the reader.
8746 */
8747 kvm->arch.last_tsc_nsec = 0;
8748 kvm->arch.last_tsc_write = 0;
8749 }
8750
8751 }
8752 return 0;
e9b11c17
ZX		 8753}
8754
13a34e06 8755void kvm_arch_hardware_disable(void)
e9b11c17 8756{
13a34e06
RK		 8757 kvm_x86_ops->hardware_disable();
8758 drop_user_return_notifiers();
e9b11c17
ZX		 8759}
8760
8761int kvm_arch_hardware_setup(void)
8762{
9e9c3fe4
NA		 8763 int r;
8764
8765 r = kvm_x86_ops->hardware_setup();
8766 if (r != 0)
8767 return r;
8768
35181e86
HZ		 8769 if (kvm_has_tsc_control) {
8770 /*
8771 * Make sure the user can only configure tsc_khz values that
8772 * fit into a signed integer.
273ba457 8773 * A min value is not calculated because it will always
35181e86
HZ		 8774 * be 1 on all machines.
8775 */
8776 u64 max = min(0x7fffffffULL,
8777 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8778 kvm_max_guest_tsc_khz = max;
8779
ad721883 8780 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8781 }
ad721883 8782
9e9c3fe4
NA		 8783 kvm_init_msr_list();
8784 return 0;
e9b11c17
ZX		 8785}
8786
8787void kvm_arch_hardware_unsetup(void)
8788{
8789 kvm_x86_ops->hardware_unsetup();
8790}
8791
8792void kvm_arch_check_processor_compat(void *rtn)
8793{
8794 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8795}
8796
8797bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8798{
8799 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8800}
8801EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8802
8803bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8804{
8805 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8806}
8807
54e9818f 8808struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8809EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8810
e9b11c17
ZX		 8811int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8812{
8813 struct page *page;
e9b11c17
ZX		 8814 int r;
8815
b2a05fef 8816 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8817 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8818 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8819 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8820 else
a4535290 8821 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8822
8823 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8824 if (!page) {
8825 r = -ENOMEM;
8826 goto fail;
8827 }
ad312c7c 8828 vcpu->arch.pio_data = page_address(page);
e9b11c17 8829
cc578287 8830 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8831
e9b11c17
ZX		 8832 r = kvm_mmu_create(vcpu);
8833 if (r < 0)
8834 goto fail_free_pio_data;
8835
26de7988 8836 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8837 r = kvm_create_lapic(vcpu);
8838 if (r < 0)
8839 goto fail_mmu_destroy;
54e9818f
GN		 8840 } else
8841 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8842
890ca9ae
HY		 8843 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8844 GFP_KERNEL);
8845 if (!vcpu->arch.mce_banks) {
8846 r = -ENOMEM;
443c39bc 8847 goto fail_free_lapic;
890ca9ae
HY		 8848 }
8849 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8850
f1797359
WY		 8851 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8852 r = -ENOMEM;
f5f48ee1 8853 goto fail_free_mce_banks;
f1797359 8854 }
f5f48ee1 8855
0ee6a517 8856 fx_init(vcpu);
66f7b72e 8857
4344ee98 8858 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8859
5a4f55cd
EK		 8860 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8861
74545705
RK		 8862 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8863
af585b92 8864 kvm_async_pf_hash_reset(vcpu);
f5132b01 8865 kvm_pmu_init(vcpu);
af585b92 8866
1c1a9ce9 8867 vcpu->arch.pending_external_vector = -1;
de63ad4c 8868 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8869
5c919412
AS		 8870 kvm_hv_vcpu_init(vcpu);
8871
e9b11c17 8872 return 0;
0ee6a517 8873
f5f48ee1
SY		 8874fail_free_mce_banks:
8875 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8876fail_free_lapic:
8877 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8878fail_mmu_destroy:
8879 kvm_mmu_destroy(vcpu);
8880fail_free_pio_data:
ad312c7c 8881 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8882fail:
8883 return r;
8884}
8885
8886void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8887{
f656ce01
MT		 8888 int idx;
8889
1f4b34f8 8890 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8891 kvm_pmu_destroy(vcpu);
36cb93fd 8892 kfree(vcpu->arch.mce_banks);
e9b11c17 8893 kvm_free_lapic(vcpu);
f656ce01 8894 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8895 kvm_mmu_destroy(vcpu);
f656ce01 8896 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8897 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8898 if (!lapic_in_kernel(vcpu))
54e9818f 8899 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8900}
d19a9cd2 8901
e790d9ef
RK		 8902void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8903{
c595ceee 8904 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 8905 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8906}
8907
e08b9637 8908int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8909{
e08b9637
CO		 8910 if (type)
8911 return -EINVAL;
8912
6ef768fa 8913 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8914 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8915 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8916 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8917 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8918
5550af4d
SY		 8919 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8920 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8921 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8922 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8923 &kvm->arch.irq_sources_bitmap);
5550af4d 8924
038f8c11 8925 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8926 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8927 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8928
108b249c 8929 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8930 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8931
6fbbde9a
DS		 8932 kvm->arch.guest_can_read_msr_platform_info = true;
8933
7e44e449 8934 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8935 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8936
cbc0236a 8937 kvm_hv_init_vm(kvm);
0eb05bf2 8938 kvm_page_track_init(kvm);
13d268ca 8939 kvm_mmu_init_vm(kvm);
0eb05bf2 8940
03543133
SS		 8941 if (kvm_x86_ops->vm_init)
8942 return kvm_x86_ops->vm_init(kvm);
8943
d89f5eff 8944 return 0;
d19a9cd2
ZX		 8945}
8946
8947static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8948{
ec7660cc 8949 vcpu_load(vcpu);
d19a9cd2
ZX		 8950 kvm_mmu_unload(vcpu);
8951 vcpu_put(vcpu);
8952}
8953
8954static void kvm_free_vcpus(struct kvm *kvm)
8955{
8956 unsigned int i;
988a2cae 8957 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8958
8959 /*
8960 * Unpin any mmu pages first.
8961 */
af585b92
GN		 8962 kvm_for_each_vcpu(i, vcpu, kvm) {
8963 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8964 kvm_unload_vcpu_mmu(vcpu);
af585b92 8965 }
988a2cae
GN		 8966 kvm_for_each_vcpu(i, vcpu, kvm)
8967 kvm_arch_vcpu_free(vcpu);
8968
8969 mutex_lock(&kvm->lock);
8970 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8971 kvm->vcpus[i] = NULL;
d19a9cd2 8972
988a2cae
GN		 8973 atomic_set(&kvm->online_vcpus, 0);
8974 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8975}
8976
ad8ba2cd
SY		 8977void kvm_arch_sync_events(struct kvm *kvm)
8978{
332967a3 8979 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8980 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8981 kvm_free_pit(kvm);
ad8ba2cd
SY		 8982}
8983
1d8007bd 8984int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8985{
8986 int i, r;
25188b99 8987 unsigned long hva;
f0d648bd
PB		 8988 struct kvm_memslots *slots = kvm_memslots(kvm);
8989 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8990
8991 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8992 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8993 return -EINVAL;
9da0e4d5 8994
f0d648bd
PB		 8995 slot = id_to_memslot(slots, id);
8996 if (size) {
b21629da 8997 if (slot->npages)
f0d648bd
PB		 8998 return -EEXIST;
8999
9000 /*
9001 * MAP_SHARED to prevent internal slot pages from being moved
9002 * by fork()/COW.
9003 */
9004 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9005 MAP_SHARED | MAP_ANONYMOUS, 0);
9006 if (IS_ERR((void *)hva))
9007 return PTR_ERR((void *)hva);
9008 } else {
9009 if (!slot->npages)
9010 return 0;
9011
9012 hva = 0;
9013 }
9014
9015 old = *slot;
9da0e4d5 9016 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9017 struct kvm_userspace_memory_region m;
9da0e4d5 9018
1d8007bd
PB		 9019 m.slot = id | (i << 16);
9020 m.flags = 0;
9021 m.guest_phys_addr = gpa;
f0d648bd 9022 m.userspace_addr = hva;
1d8007bd 9023 m.memory_size = size;
9da0e4d5
PB		 9024 r = __kvm_set_memory_region(kvm, &m);
9025 if (r < 0)
9026 return r;
9027 }
9028
103c763c
EB		 9029 if (!size)
9030 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9031
9da0e4d5
PB		 9032 return 0;
9033}
9034EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9035
1d8007bd 9036int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9037{
9038 int r;
9039
9040 mutex_lock(&kvm->slots_lock);
1d8007bd 9041 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9042 mutex_unlock(&kvm->slots_lock);
9043
9044 return r;
9045}
9046EXPORT_SYMBOL_GPL(x86_set_memory_region);
9047
d19a9cd2
ZX		 9048void kvm_arch_destroy_vm(struct kvm *kvm)
9049{
27469d29
AH		 9050 if (current->mm == kvm->mm) {
9051 /*
9052 * Free memory regions allocated on behalf of userspace,
9053 * unless the the memory map has changed due to process exit
9054 * or fd copying.
9055 */
1d8007bd
PB		 9056 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9057 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9058 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9059 }
03543133
SS		 9060 if (kvm_x86_ops->vm_destroy)
9061 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9062 kvm_pic_destroy(kvm);
9063 kvm_ioapic_destroy(kvm);
d19a9cd2 9064 kvm_free_vcpus(kvm);
af1bae54 9065 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 9066 kvm_mmu_uninit_vm(kvm);
2beb6dad 9067 kvm_page_track_cleanup(kvm);
cbc0236a 9068 kvm_hv_destroy_vm(kvm);
d19a9cd2 9069}
0de10343 9070
5587027c 9071void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9072 struct kvm_memory_slot *dont)
9073{
9074 int i;
9075
d89cc617
TY		 9076 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9077 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9078 kvfree(free->arch.rmap[i]);
d89cc617 9079 free->arch.rmap[i] = NULL;
77d11309 9080 }
d89cc617
TY		 9081 if (i == 0)
9082 continue;
9083
9084 if (!dont || free->arch.lpage_info[i - 1] !=
9085 dont->arch.lpage_info[i - 1]) {
548ef284 9086 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9087 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9088 }
9089 }
21ebbeda
XG		 9090
9091 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9092}
9093
5587027c
AK		 9094int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9095 unsigned long npages)
db3fe4eb
TY		 9096{
9097 int i;
9098
d89cc617 9099 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9100 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9101 unsigned long ugfn;
9102 int lpages;
d89cc617 9103 int level = i + 1;
db3fe4eb
TY		 9104
9105 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9106 slot->base_gfn, level) + 1;
9107
d89cc617 9108 slot->arch.rmap[i] =
778e1cdd
KC		 9109 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9110 GFP_KERNEL);
d89cc617 9111 if (!slot->arch.rmap[i])
77d11309 9112 goto out_free;
d89cc617
TY		 9113 if (i == 0)
9114 continue;
77d11309 9115
778e1cdd 9116 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
92f94f1e 9117 if (!linfo)
db3fe4eb
TY		 9118 goto out_free;
9119
92f94f1e
XG		 9120 slot->arch.lpage_info[i - 1] = linfo;
9121
db3fe4eb 9122 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9123 linfo[0].disallow_lpage = 1;
db3fe4eb 9124 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9125 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9126 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9127 /*
9128 * If the gfn and userspace address are not aligned wrt each
9129 * other, or if explicitly asked to, disable large page
9130 * support for this slot
9131 */
9132 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9133 !kvm_largepages_enabled()) {
9134 unsigned long j;
9135
9136 for (j = 0; j < lpages; ++j)
92f94f1e 9137 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9138 }
9139 }
9140
21ebbeda
XG		 9141 if (kvm_page_track_create_memslot(slot, npages))
9142 goto out_free;
9143
db3fe4eb
TY		 9144 return 0;
9145
9146out_free:
d89cc617 9147 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9148 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9149 slot->arch.rmap[i] = NULL;
9150 if (i == 0)
9151 continue;
9152
548ef284 9153 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9154 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9155 }
9156 return -ENOMEM;
9157}
9158
15f46015 9159void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 9160{
e6dff7d1
TY		 9161 /*
9162 * memslots->generation has been incremented.
9163 * mmio generation may have reached its maximum value.
9164 */
54bf36aa 9165 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 9166}
9167
f7784b8e
MT		 9168int kvm_arch_prepare_memory_region(struct kvm *kvm,
9169 struct kvm_memory_slot *memslot,
09170a49 9170 const struct kvm_userspace_memory_region *mem,
7b6195a9 9171 enum kvm_mr_change change)
0de10343 9172{
f7784b8e
MT		 9173 return 0;
9174}
9175
88178fd4
KH		 9176static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9177 struct kvm_memory_slot *new)
9178{
9179 /* Still write protect RO slot */
9180 if (new->flags & KVM_MEM_READONLY) {
9181 kvm_mmu_slot_remove_write_access(kvm, new);
9182 return;
9183 }
9184
9185 /*
9186 * Call kvm_x86_ops dirty logging hooks when they are valid.
9187 *
9188 * kvm_x86_ops->slot_disable_log_dirty is called when:
9189 *
9190 * - KVM_MR_CREATE with dirty logging is disabled
9191 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9192 *
9193 * The reason is, in case of PML, we need to set D-bit for any slots
9194 * with dirty logging disabled in order to eliminate unnecessary GPA
9195 * logging in PML buffer (and potential PML buffer full VMEXT). This
9196 * guarantees leaving PML enabled during guest's lifetime won't have
9197 * any additonal overhead from PML when guest is running with dirty
9198 * logging disabled for memory slots.
9199 *
9200 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9201 * to dirty logging mode.
9202 *
9203 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9204 *
9205 * In case of write protect:
9206 *
9207 * Write protect all pages for dirty logging.
9208 *
9209 * All the sptes including the large sptes which point to this
9210 * slot are set to readonly. We can not create any new large
9211 * spte on this slot until the end of the logging.
9212 *
9213 * See the comments in fast_page_fault().
9214 */
9215 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9216 if (kvm_x86_ops->slot_enable_log_dirty)
9217 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9218 else
9219 kvm_mmu_slot_remove_write_access(kvm, new);
9220 } else {
9221 if (kvm_x86_ops->slot_disable_log_dirty)
9222 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9223 }
9224}
9225
f7784b8e 9226void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9227 const struct kvm_userspace_memory_region *mem,
8482644a 9228 const struct kvm_memory_slot *old,
f36f3f28 9229 const struct kvm_memory_slot *new,
8482644a 9230 enum kvm_mr_change change)
f7784b8e 9231{
8482644a 9232 int nr_mmu_pages = 0;
f7784b8e 9233
48c0e4e9
XG		 9234 if (!kvm->arch.n_requested_mmu_pages)
9235 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9236
48c0e4e9 9237 if (nr_mmu_pages)
0de10343 9238 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9239
3ea3b7fa
WL		 9240 /*
9241 * Dirty logging tracks sptes in 4k granularity, meaning that large
9242 * sptes have to be split. If live migration is successful, the guest
9243 * in the source machine will be destroyed and large sptes will be
9244 * created in the destination. However, if the guest continues to run
9245 * in the source machine (for example if live migration fails), small
9246 * sptes will remain around and cause bad performance.
9247 *
9248 * Scan sptes if dirty logging has been stopped, dropping those
9249 * which can be collapsed into a single large-page spte. Later
9250 * page faults will create the large-page sptes.
9251 */
9252 if ((change != KVM_MR_DELETE) &&
9253 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9254 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9255 kvm_mmu_zap_collapsible_sptes(kvm, new);
9256
c972f3b1 9257 /*
88178fd4 9258 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9259 *
88178fd4
KH		 9260 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9261 * been zapped so no dirty logging staff is needed for old slot. For
9262 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9263 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9264 *
9265 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9266 */
88178fd4 9267 if (change != KVM_MR_DELETE)
f36f3f28 9268 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9269}
1d737c8a 9270
2df72e9b 9271void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9272{
6ca18b69 9273 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9274}
9275
2df72e9b
MT		 9276void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9277 struct kvm_memory_slot *slot)
9278{
ae7cd873 9279 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9280}
9281
e6c67d8c
LA		 9282static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9283{
9284 return (is_guest_mode(vcpu) &&
9285 kvm_x86_ops->guest_apic_has_interrupt &&
9286 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9287}
9288
5d9bc648
PB		 9289static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9290{
9291 if (!list_empty_careful(&vcpu->async_pf.done))
9292 return true;
9293
9294 if (kvm_apic_has_events(vcpu))
9295 return true;
9296
9297 if (vcpu->arch.pv.pv_unhalted)
9298 return true;
9299
a5f01f8e
WL		 9300 if (vcpu->arch.exception.pending)
9301 return true;
9302
47a66eed
Z		 9303 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9304 (vcpu->arch.nmi_pending &&
9305 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9306 return true;
9307
47a66eed
Z		 9308 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9309 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9310 return true;
9311
5d9bc648 9312 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9313 (kvm_cpu_has_interrupt(vcpu) ||
9314 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9315 return true;
9316
1f4b34f8
AS		 9317 if (kvm_hv_has_stimer_pending(vcpu))
9318 return true;
9319
5d9bc648
PB		 9320 return false;
9321}
9322
1d737c8a
ZX		 9323int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9324{
5d9bc648 9325 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9326}
5736199a 9327
199b5763
LM		 9328bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9329{
de63ad4c 9330 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9331}
9332
b6d33834 9333int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9334{
b6d33834 9335 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9336}
78646121
GN		 9337
9338int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9339{
9340 return kvm_x86_ops->interrupt_allowed(vcpu);
9341}
229456fc 9342
82b32774 9343unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9344{
82b32774
NA		 9345 if (is_64_bit_mode(vcpu))
9346 return kvm_rip_read(vcpu);
9347 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9348 kvm_rip_read(vcpu));
9349}
9350EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9351
82b32774
NA		 9352bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9353{
9354 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9355}
9356EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9357
94fe45da
JK		 9358unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9359{
9360 unsigned long rflags;
9361
9362 rflags = kvm_x86_ops->get_rflags(vcpu);
9363 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9364 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9365 return rflags;
9366}
9367EXPORT_SYMBOL_GPL(kvm_get_rflags);
9368
6addfc42 9369static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9370{
9371 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9372 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9373 rflags |= X86_EFLAGS_TF;
94fe45da 9374 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9375}
9376
9377void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9378{
9379 __kvm_set_rflags(vcpu, rflags);
3842d135 9380 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9381}
9382EXPORT_SYMBOL_GPL(kvm_set_rflags);
9383
56028d08
GN		 9384void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9385{
9386 int r;
9387
44dd3ffa 9388 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9389 work->wakeup_all)
56028d08
GN		 9390 return;
9391
9392 r = kvm_mmu_reload(vcpu);
9393 if (unlikely(r))
9394 return;
9395
44dd3ffa
VK		 9396 if (!vcpu->arch.mmu->direct_map &&
9397 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9398 return;
9399
44dd3ffa 9400 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9401}
9402
af585b92
GN		 9403static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9404{
9405 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9406}
9407
9408static inline u32 kvm_async_pf_next_probe(u32 key)
9409{
9410 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9411}
9412
9413static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9414{
9415 u32 key = kvm_async_pf_hash_fn(gfn);
9416
9417 while (vcpu->arch.apf.gfns[key] != ~0)
9418 key = kvm_async_pf_next_probe(key);
9419
9420 vcpu->arch.apf.gfns[key] = gfn;
9421}
9422
9423static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9424{
9425 int i;
9426 u32 key = kvm_async_pf_hash_fn(gfn);
9427
9428 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9429 (vcpu->arch.apf.gfns[key] != gfn &&
9430 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9431 key = kvm_async_pf_next_probe(key);
9432
9433 return key;
9434}
9435
9436bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9437{
9438 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9439}
9440
9441static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9442{
9443 u32 i, j, k;
9444
9445 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9446 while (true) {
9447 vcpu->arch.apf.gfns[i] = ~0;
9448 do {
9449 j = kvm_async_pf_next_probe(j);
9450 if (vcpu->arch.apf.gfns[j] == ~0)
9451 return;
9452 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9453 /*
9454 * k lies cyclically in ]i,j]
9455 * | i.k.j |
9456 * |....j i.k.| or |.k..j i...|
9457 */
9458 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9459 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9460 i = j;
9461 }
9462}
9463
7c90705b
GN		 9464static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9465{
4e335d9e
PB		 9466
9467 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9468 sizeof(val));
7c90705b
GN		 9469}
9470
9a6e7c39
WL		 9471static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9472{
9473
9474 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9475 sizeof(u32));
9476}
9477
af585b92
GN		 9478void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9479 struct kvm_async_pf *work)
9480{
6389ee94
AK		 9481 struct x86_exception fault;
9482
7c90705b 9483 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9484 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9485
9486 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9487 (vcpu->arch.apf.send_user_only &&
9488 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9489 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9490 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9491 fault.vector = PF_VECTOR;
9492 fault.error_code_valid = true;
9493 fault.error_code = 0;
9494 fault.nested_page_fault = false;
9495 fault.address = work->arch.token;
adfe20fb 9496 fault.async_page_fault = true;
6389ee94 9497 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9498 }
af585b92
GN		 9499}
9500
9501void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9502 struct kvm_async_pf *work)
9503{
6389ee94 9504 struct x86_exception fault;
9a6e7c39 9505 u32 val;
6389ee94 9506
f2e10669 9507 if (work->wakeup_all)
7c90705b
GN		 9508 work->arch.token = ~0; /* broadcast wakeup */
9509 else
9510 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9511 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9512
9a6e7c39
WL		 9513 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9514 !apf_get_user(vcpu, &val)) {
9515 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9516 vcpu->arch.exception.pending &&
9517 vcpu->arch.exception.nr == PF_VECTOR &&
9518 !apf_put_user(vcpu, 0)) {
9519 vcpu->arch.exception.injected = false;
9520 vcpu->arch.exception.pending = false;
9521 vcpu->arch.exception.nr = 0;
9522 vcpu->arch.exception.has_error_code = false;
9523 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9524 vcpu->arch.exception.has_payload = false;
9525 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9526 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9527 fault.vector = PF_VECTOR;
9528 fault.error_code_valid = true;
9529 fault.error_code = 0;
9530 fault.nested_page_fault = false;
9531 fault.address = work->arch.token;
9532 fault.async_page_fault = true;
9533 kvm_inject_page_fault(vcpu, &fault);
9534 }
7c90705b 9535 }
e6d53e3b 9536 vcpu->arch.apf.halted = false;
a4fa1635 9537 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9538}
9539
9540bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9541{
9542 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9543 return true;
9544 else
9bc1f09f 9545 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9546}
9547
5544eb9b
PB		 9548void kvm_arch_start_assignment(struct kvm *kvm)
9549{
9550 atomic_inc(&kvm->arch.assigned_device_count);
9551}
9552EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9553
9554void kvm_arch_end_assignment(struct kvm *kvm)
9555{
9556 atomic_dec(&kvm->arch.assigned_device_count);
9557}
9558EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9559
9560bool kvm_arch_has_assigned_device(struct kvm *kvm)
9561{
9562 return atomic_read(&kvm->arch.assigned_device_count);
9563}
9564EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9565
e0f0bbc5
AW		 9566void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9567{
9568 atomic_inc(&kvm->arch.noncoherent_dma_count);
9569}
9570EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9571
9572void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9573{
9574 atomic_dec(&kvm->arch.noncoherent_dma_count);
9575}
9576EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9577
9578bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9579{
9580 return atomic_read(&kvm->arch.noncoherent_dma_count);
9581}
9582EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9583
14717e20
AW		 9584bool kvm_arch_has_irq_bypass(void)
9585{
9586 return kvm_x86_ops->update_pi_irte != NULL;
9587}
9588
87276880
FW		 9589int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9590 struct irq_bypass_producer *prod)
9591{
9592 struct kvm_kernel_irqfd *irqfd =
9593 container_of(cons, struct kvm_kernel_irqfd, consumer);
9594
14717e20 9595 irqfd->producer = prod;
87276880 9596
14717e20
AW		 9597 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9598 prod->irq, irqfd->gsi, 1);
87276880
FW		 9599}
9600
9601void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9602 struct irq_bypass_producer *prod)
9603{
9604 int ret;
9605 struct kvm_kernel_irqfd *irqfd =
9606 container_of(cons, struct kvm_kernel_irqfd, consumer);
9607
87276880
FW		 9608 WARN_ON(irqfd->producer != prod);
9609 irqfd->producer = NULL;
9610
9611 /*
9612 * When producer of consumer is unregistered, we change back to
9613 * remapped mode, so we can re-use the current implementation
bb3541f1 9614 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9615 * int this case doesn't want to receive the interrupts.
9616 */
9617 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9618 if (ret)
9619 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9620 " fails: %d\n", irqfd->consumer.token, ret);
9621}
9622
9623int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9624 uint32_t guest_irq, bool set)
9625{
9626 if (!kvm_x86_ops->update_pi_irte)
9627 return -EINVAL;
9628
9629 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9630}
9631
52004014
FW		 9632bool kvm_vector_hashing_enabled(void)
9633{
9634 return vector_hashing;
9635}
9636EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9637
229456fc 9638EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9639EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9640EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9641EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9642EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9643EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9644EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9645EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9646EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9647EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9648EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9649EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9650EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9651EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9652EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9653EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9654EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9655EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9656EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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