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KVM: x86: allow hotplug of VCPU with APIC ID over 0xff
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
1767e931
PG		 39#include <linux/export.h>
40#include <linux/moduleparam.h>
0de10343 41#include <linux/mman.h>
2bacc55c 42#include <linux/highmem.h>
19de40a8 43#include <linux/iommu.h>
62c476c7 44#include <linux/intel-iommu.h>
c8076604 45#include <linux/cpufreq.h>
18863bdd 46#include <linux/user-return-notifier.h>
a983fb23 47#include <linux/srcu.h>
5a0e3ad6 48#include <linux/slab.h>
ff9d07a0 49#include <linux/perf_event.h>
7bee342a 50#include <linux/uaccess.h>
af585b92 51#include <linux/hash.h>
a1b60c1c 52#include <linux/pci.h>
16e8d74d
MT		 53#include <linux/timekeeper_internal.h>
54#include <linux/pvclock_gtod.h>
87276880
FW		 55#include <linux/kvm_irqfd.h>
56#include <linux/irqbypass.h>
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
043405e1 68
d1898b73
DH		 69#define CREATE_TRACE_POINTS
70#include "trace.h"
71
313a3dc7 72#define MAX_IO_MSRS 256
890ca9ae 73#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 74u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
75EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 76
0f65dd70
AK		 77#define emul_to_vcpu(ctxt) \
78 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79
50a37eb4
JR		 80/* EFER defaults:
81 * - enable syscall per default because its emulated by KVM
82 * - enable LME and LMA per default on 64 bit KVM
83 */
84#ifdef CONFIG_X86_64
1260edbe
LJ		 85static
86u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 87#else
1260edbe 88static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 89#endif
313a3dc7 90
ba1389b7
AK		 91#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
92#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 93
c519265f
RK		 94#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
95 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 96
cb142eb7 97static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 98static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 99static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 100static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 101
893590c7 102struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 103EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 104
893590c7 105static bool __read_mostly ignore_msrs = 0;
476bc001 106module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 107
9ed96e87
MT		 108unsigned int min_timer_period_us = 500;
109module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
110
630994b3
MT		 111static bool __read_mostly kvmclock_periodic_sync = true;
112module_param(kvmclock_periodic_sync, bool, S_IRUGO);
113
893590c7 114bool __read_mostly kvm_has_tsc_control;
92a1f12d 115EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 116u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 117EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 118u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
119EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
120u64 __read_mostly kvm_max_tsc_scaling_ratio;
121EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 122u64 __read_mostly kvm_default_tsc_scaling_ratio;
123EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 124
cc578287 125/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 126static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 127module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
128
d0659d94 129/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 130unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 131module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
132
52004014
FW		 133static bool __read_mostly vector_hashing = true;
134module_param(vector_hashing, bool, S_IRUGO);
135
893590c7 136static bool __read_mostly backwards_tsc_observed = false;
16a96021 137
18863bdd
AK		 138#define KVM_NR_SHARED_MSRS 16
139
140struct kvm_shared_msrs_global {
141 int nr;
2bf78fa7 142 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 143};
144
145struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
2bf78fa7
SY		 148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 152};
153
154static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 155static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 156
417bc304 157struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 168 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 173 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 181 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 182 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 190 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 192 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 193 { "max_mmu_page_hash_collisions",
194 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 195 { NULL }
196};
197
2acf923e
DC		 198u64 __read_mostly host_xcr0;
199
b6785def 200static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 201
af585b92
GN		 202static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
203{
204 int i;
205 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
206 vcpu->arch.apf.gfns[i] = ~0;
207}
208
18863bdd
AK		 209static void kvm_on_user_return(struct user_return_notifier *urn)
210{
211 unsigned slot;
18863bdd
AK		 212 struct kvm_shared_msrs *locals
213 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 214 struct kvm_shared_msr_values *values;
1650b4eb
IA		 215 unsigned long flags;
216
217 /*
218 * Disabling irqs at this point since the following code could be
219 * interrupted and executed through kvm_arch_hardware_disable()
220 */
221 local_irq_save(flags);
222 if (locals->registered) {
223 locals->registered = false;
224 user_return_notifier_unregister(urn);
225 }
226 local_irq_restore(flags);
18863bdd 227 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 228 values = &locals->values[slot];
229 if (values->host != values->curr) {
230 wrmsrl(shared_msrs_global.msrs[slot], values->host);
231 values->curr = values->host;
18863bdd
AK		 232 }
233 }
18863bdd
AK		 234}
235
2bf78fa7 236static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 237{
18863bdd 238 u64 value;
013f6a5d
MT		 239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 241
2bf78fa7
SY		 242 /* only read, and nobody should modify it at this time,
243 * so don't need lock */
244 if (slot >= shared_msrs_global.nr) {
245 printk(KERN_ERR "kvm: invalid MSR slot!");
246 return;
247 }
248 rdmsrl_safe(msr, &value);
249 smsr->values[slot].host = value;
250 smsr->values[slot].curr = value;
251}
252
253void kvm_define_shared_msr(unsigned slot, u32 msr)
254{
0123be42 255 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 256 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 257 if (slot >= shared_msrs_global.nr)
258 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 259}
260EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
261
262static void kvm_shared_msr_cpu_online(void)
263{
264 unsigned i;
18863bdd
AK		 265
266 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 267 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 268}
269
8b3c3104 270int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 274 int err;
18863bdd 275
2bf78fa7 276 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 277 return 0;
2bf78fa7 278 smsr->values[slot].curr = value;
8b3c3104
AH		 279 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
280 if (err)
281 return 1;
282
18863bdd
AK		 283 if (!smsr->registered) {
284 smsr->urn.on_user_return = kvm_on_user_return;
285 user_return_notifier_register(&smsr->urn);
286 smsr->registered = true;
287 }
8b3c3104 288 return 0;
18863bdd
AK		 289}
290EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
291
13a34e06 292static void drop_user_return_notifiers(void)
3548bab5 293{
013f6a5d
MT		 294 unsigned int cpu = smp_processor_id();
295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 296
297 if (smsr->registered)
298 kvm_on_user_return(&smsr->urn);
299}
300
6866b83e
CO		 301u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
302{
8a5a87d9 303 return vcpu->arch.apic_base;
6866b83e
CO		 304}
305EXPORT_SYMBOL_GPL(kvm_get_apic_base);
306
58cb628d
JK		 307int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
308{
309 u64 old_state = vcpu->arch.apic_base &
310 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
311 u64 new_state = msr_info->data &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
314 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
315
316 if (!msr_info->host_initiated &&
317 ((msr_info->data & reserved_bits) != 0 ||
318 new_state == X2APIC_ENABLE ||
319 (new_state == MSR_IA32_APICBASE_ENABLE &&
320 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
321 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
322 old_state == 0)))
323 return 1;
324
325 kvm_lapic_set_base(vcpu, msr_info->data);
326 return 0;
6866b83e
CO		 327}
328EXPORT_SYMBOL_GPL(kvm_set_apic_base);
329
2605fc21 330asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 331{
332 /* Fault while not rebooting. We want the trace. */
333 BUG();
334}
335EXPORT_SYMBOL_GPL(kvm_spurious_fault);
336
3fd28fce
ED		 337#define EXCPT_BENIGN 0
338#define EXCPT_CONTRIBUTORY 1
339#define EXCPT_PF 2
340
341static int exception_class(int vector)
342{
343 switch (vector) {
344 case PF_VECTOR:
345 return EXCPT_PF;
346 case DE_VECTOR:
347 case TS_VECTOR:
348 case NP_VECTOR:
349 case SS_VECTOR:
350 case GP_VECTOR:
351 return EXCPT_CONTRIBUTORY;
352 default:
353 break;
354 }
355 return EXCPT_BENIGN;
356}
357
d6e8c854
NA		 358#define EXCPT_FAULT 0
359#define EXCPT_TRAP 1
360#define EXCPT_ABORT 2
361#define EXCPT_INTERRUPT 3
362
363static int exception_type(int vector)
364{
365 unsigned int mask;
366
367 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
368 return EXCPT_INTERRUPT;
369
370 mask = 1 << vector;
371
372 /* #DB is trap, as instruction watchpoints are handled elsewhere */
373 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
374 return EXCPT_TRAP;
375
376 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
377 return EXCPT_ABORT;
378
379 /* Reserved exceptions will result in fault */
380 return EXCPT_FAULT;
381}
382
3fd28fce 383static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 384 unsigned nr, bool has_error, u32 error_code,
385 bool reinject)
3fd28fce
ED		 386{
387 u32 prev_nr;
388 int class1, class2;
389
3842d135
AK		 390 kvm_make_request(KVM_REQ_EVENT, vcpu);
391
3fd28fce
ED		 392 if (!vcpu->arch.exception.pending) {
393 queue:
3ffb2468
NA		 394 if (has_error && !is_protmode(vcpu))
395 has_error = false;
3fd28fce
ED		 396 vcpu->arch.exception.pending = true;
397 vcpu->arch.exception.has_error_code = has_error;
398 vcpu->arch.exception.nr = nr;
399 vcpu->arch.exception.error_code = error_code;
3f0fd292 400 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 401 return;
402 }
403
404 /* to check exception */
405 prev_nr = vcpu->arch.exception.nr;
406 if (prev_nr == DF_VECTOR) {
407 /* triple fault -> shutdown */
a8eeb04a 408 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 409 return;
410 }
411 class1 = exception_class(prev_nr);
412 class2 = exception_class(nr);
413 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
414 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
415 /* generate double fault per SDM Table 5-5 */
416 vcpu->arch.exception.pending = true;
417 vcpu->arch.exception.has_error_code = true;
418 vcpu->arch.exception.nr = DF_VECTOR;
419 vcpu->arch.exception.error_code = 0;
420 } else
421 /* replace previous exception with a new one in a hope
422 that instruction re-execution will regenerate lost
423 exception */
424 goto queue;
425}
426
298101da
AK		 427void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
428{
ce7ddec4 429 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 430}
431EXPORT_SYMBOL_GPL(kvm_queue_exception);
432
ce7ddec4
JR		 433void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
434{
435 kvm_multiple_exception(vcpu, nr, false, 0, true);
436}
437EXPORT_SYMBOL_GPL(kvm_requeue_exception);
438
6affcbed 439int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 440{
db8fcefa
AP		 441 if (err)
442 kvm_inject_gp(vcpu, 0);
443 else
6affcbed
KH		 444 return kvm_skip_emulated_instruction(vcpu);
445
446 return 1;
db8fcefa
AP		 447}
448EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 449
6389ee94 450void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 451{
452 ++vcpu->stat.pf_guest;
6389ee94
AK		 453 vcpu->arch.cr2 = fault->address;
454 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 455}
27d6c865 456EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 457
ef54bcfe 458static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 459{
6389ee94
AK		 460 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
461 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 462 else
6389ee94 463 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 464
465 return fault->nested_page_fault;
d4f8cf66
JR		 466}
467
3419ffc8
SY		 468void kvm_inject_nmi(struct kvm_vcpu *vcpu)
469{
7460fb4a
AK		 470 atomic_inc(&vcpu->arch.nmi_queued);
471 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 472}
473EXPORT_SYMBOL_GPL(kvm_inject_nmi);
474
298101da
AK		 475void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
476{
ce7ddec4 477 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 478}
479EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
480
ce7ddec4
JR		 481void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
482{
483 kvm_multiple_exception(vcpu, nr, true, error_code, true);
484}
485EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
486
0a79b009
AK		 487/*
488 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
489 * a #GP and return false.
490 */
491bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 492{
0a79b009
AK		 493 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
494 return true;
495 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
496 return false;
298101da 497}
0a79b009 498EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 499
16f8a6f9
NA		 500bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
501{
502 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
503 return true;
504
505 kvm_queue_exception(vcpu, UD_VECTOR);
506 return false;
507}
508EXPORT_SYMBOL_GPL(kvm_require_dr);
509
ec92fe44
JR		 510/*
511 * This function will be used to read from the physical memory of the currently
54bf36aa 512 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 513 * can read from guest physical or from the guest's guest physical memory.
514 */
515int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
516 gfn_t ngfn, void *data, int offset, int len,
517 u32 access)
518{
54987b7a 519 struct x86_exception exception;
ec92fe44
JR		 520 gfn_t real_gfn;
521 gpa_t ngpa;
522
523 ngpa = gfn_to_gpa(ngfn);
54987b7a 524 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 525 if (real_gfn == UNMAPPED_GVA)
526 return -EFAULT;
527
528 real_gfn = gpa_to_gfn(real_gfn);
529
54bf36aa 530 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 531}
532EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
533
69b0049a 534static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 535 void *data, int offset, int len, u32 access)
536{
537 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
538 data, offset, len, access);
539}
540
a03490ed
CO		 541/*
542 * Load the pae pdptrs. Return true is they are all valid.
543 */
ff03a073 544int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 545{
546 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
547 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
548 int i;
549 int ret;
ff03a073 550 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 551
ff03a073
JR		 552 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
553 offset * sizeof(u64), sizeof(pdpte),
554 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 555 if (ret < 0) {
556 ret = 0;
557 goto out;
558 }
559 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 560 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 561 (pdpte[i] &
562 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 563 ret = 0;
564 goto out;
565 }
566 }
567 ret = 1;
568
ff03a073 569 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 570 __set_bit(VCPU_EXREG_PDPTR,
571 (unsigned long *)&vcpu->arch.regs_avail);
572 __set_bit(VCPU_EXREG_PDPTR,
573 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 574out:
a03490ed
CO		 575
576 return ret;
577}
cc4b6871 578EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 579
9ed38ffa 580bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 581{
ff03a073 582 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 583 bool changed = true;
3d06b8bf
JR		 584 int offset;
585 gfn_t gfn;
d835dfec
AK		 586 int r;
587
588 if (is_long_mode(vcpu) || !is_pae(vcpu))
589 return false;
590
6de4f3ad
AK		 591 if (!test_bit(VCPU_EXREG_PDPTR,
592 (unsigned long *)&vcpu->arch.regs_avail))
593 return true;
594
9f8fe504
AK		 595 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
596 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 597 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
598 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 599 if (r < 0)
600 goto out;
ff03a073 601 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 602out:
d835dfec
AK		 603
604 return changed;
605}
9ed38ffa 606EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 607
49a9b07e 608int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 609{
aad82703 610 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 611 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 612
f9a48e6a
AK		 613 cr0 |= X86_CR0_ET;
614
ab344828 615#ifdef CONFIG_X86_64
0f12244f
GN		 616 if (cr0 & 0xffffffff00000000UL)
617 return 1;
ab344828
GN		 618#endif
619
620 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 621
0f12244f
GN		 622 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
623 return 1;
a03490ed 624
0f12244f
GN		 625 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
626 return 1;
a03490ed
CO		 627
628 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
629#ifdef CONFIG_X86_64
f6801dff 630 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 631 int cs_db, cs_l;
632
0f12244f
GN		 633 if (!is_pae(vcpu))
634 return 1;
a03490ed 635 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 636 if (cs_l)
637 return 1;
a03490ed
CO		 638 } else
639#endif
ff03a073 640 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 641 kvm_read_cr3(vcpu)))
0f12244f 642 return 1;
a03490ed
CO		 643 }
644
ad756a16
MJ		 645 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
646 return 1;
647
a03490ed 648 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 649
d170c419 650 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 651 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 652 kvm_async_pf_hash_reset(vcpu);
653 }
e5f3f027 654
aad82703
SY		 655 if ((cr0 ^ old_cr0) & update_bits)
656 kvm_mmu_reset_context(vcpu);
b18d5431 657
879ae188
LE		 658 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
659 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
660 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 661 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
662
0f12244f
GN		 663 return 0;
664}
2d3ad1f4 665EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 666
2d3ad1f4 667void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 668{
49a9b07e 669 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 670}
2d3ad1f4 671EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 672
42bdf991
MT		 673static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
674{
675 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
676 !vcpu->guest_xcr0_loaded) {
677 /* kvm_set_xcr() also depends on this */
678 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
679 vcpu->guest_xcr0_loaded = 1;
680 }
681}
682
683static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
684{
685 if (vcpu->guest_xcr0_loaded) {
686 if (vcpu->arch.xcr0 != host_xcr0)
687 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
688 vcpu->guest_xcr0_loaded = 0;
689 }
690}
691
69b0049a 692static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 693{
56c103ec
LJ		 694 u64 xcr0 = xcr;
695 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 696 u64 valid_bits;
2acf923e
DC		 697
698 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
699 if (index != XCR_XFEATURE_ENABLED_MASK)
700 return 1;
d91cab78 701 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 702 return 1;
d91cab78 703 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 704 return 1;
46c34cb0
PB		 705
706 /*
707 * Do not allow the guest to set bits that we do not support
708 * saving. However, xcr0 bit 0 is always set, even if the
709 * emulated CPU does not support XSAVE (see fx_init).
710 */
d91cab78 711 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 712 if (xcr0 & ~valid_bits)
2acf923e 713 return 1;
46c34cb0 714
d91cab78
DH		 715 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
716 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 717 return 1;
718
d91cab78
DH		 719 if (xcr0 & XFEATURE_MASK_AVX512) {
720 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 721 return 1;
d91cab78 722 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 723 return 1;
724 }
2acf923e 725 vcpu->arch.xcr0 = xcr0;
56c103ec 726
d91cab78 727 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 728 kvm_update_cpuid(vcpu);
2acf923e
DC		 729 return 0;
730}
731
732int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
733{
764bcbc5
Z		 734 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
735 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 736 kvm_inject_gp(vcpu, 0);
737 return 1;
738 }
739 return 0;
740}
741EXPORT_SYMBOL_GPL(kvm_set_xcr);
742
a83b29c6 743int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 744{
fc78f519 745 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 746 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 747 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 748
0f12244f
GN		 749 if (cr4 & CR4_RESERVED_BITS)
750 return 1;
a03490ed 751
2acf923e
DC		 752 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
753 return 1;
754
c68b734f
YW		 755 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
756 return 1;
757
97ec8c06
FW		 758 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
759 return 1;
760
afcbf13f 761 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 762 return 1;
763
b9baba86
HH		 764 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
765 return 1;
766
a03490ed 767 if (is_long_mode(vcpu)) {
0f12244f
GN		 768 if (!(cr4 & X86_CR4_PAE))
769 return 1;
a2edf57f
AK		 770 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
771 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 772 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
773 kvm_read_cr3(vcpu)))
0f12244f
GN		 774 return 1;
775
ad756a16
MJ		 776 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
777 if (!guest_cpuid_has_pcid(vcpu))
778 return 1;
779
780 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
781 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
782 return 1;
783 }
784
5e1746d6 785 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 786 return 1;
a03490ed 787
ad756a16
MJ		 788 if (((cr4 ^ old_cr4) & pdptr_bits) ||
789 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 790 kvm_mmu_reset_context(vcpu);
0f12244f 791
b9baba86 792 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 793 kvm_update_cpuid(vcpu);
2acf923e 794
0f12244f
GN		 795 return 0;
796}
2d3ad1f4 797EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 798
2390218b 799int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 800{
ac146235 801#ifdef CONFIG_X86_64
9d88fca7 802 cr3 &= ~CR3_PCID_INVD;
ac146235 803#endif
9d88fca7 804
9f8fe504 805 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 806 kvm_mmu_sync_roots(vcpu);
77c3913b 807 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 808 return 0;
d835dfec
AK		 809 }
810
a03490ed 811 if (is_long_mode(vcpu)) {
d9f89b88
JK		 812 if (cr3 & CR3_L_MODE_RESERVED_BITS)
813 return 1;
814 } else if (is_pae(vcpu) && is_paging(vcpu) &&
815 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 816 return 1;
a03490ed 817
0f12244f 818 vcpu->arch.cr3 = cr3;
aff48baa 819 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 820 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 821 return 0;
822}
2d3ad1f4 823EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 824
eea1cff9 825int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 826{
0f12244f
GN		 827 if (cr8 & CR8_RESERVED_BITS)
828 return 1;
35754c98 829 if (lapic_in_kernel(vcpu))
a03490ed
CO		 830 kvm_lapic_set_tpr(vcpu, cr8);
831 else
ad312c7c 832 vcpu->arch.cr8 = cr8;
0f12244f
GN		 833 return 0;
834}
2d3ad1f4 835EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 836
2d3ad1f4 837unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 838{
35754c98 839 if (lapic_in_kernel(vcpu))
a03490ed
CO		 840 return kvm_lapic_get_cr8(vcpu);
841 else
ad312c7c 842 return vcpu->arch.cr8;
a03490ed 843}
2d3ad1f4 844EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 845
ae561ede
NA		 846static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
847{
848 int i;
849
850 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
851 for (i = 0; i < KVM_NR_DB_REGS; i++)
852 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
853 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
854 }
855}
856
73aaf249
JK		 857static void kvm_update_dr6(struct kvm_vcpu *vcpu)
858{
859 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
860 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
861}
862
c8639010
JK		 863static void kvm_update_dr7(struct kvm_vcpu *vcpu)
864{
865 unsigned long dr7;
866
867 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
868 dr7 = vcpu->arch.guest_debug_dr7;
869 else
870 dr7 = vcpu->arch.dr7;
871 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 872 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
873 if (dr7 & DR7_BP_EN_MASK)
874 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 875}
876
6f43ed01
NA		 877static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
878{
879 u64 fixed = DR6_FIXED_1;
880
881 if (!guest_cpuid_has_rtm(vcpu))
882 fixed |= DR6_RTM;
883 return fixed;
884}
885
338dbc97 886static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 887{
888 switch (dr) {
889 case 0 ... 3:
890 vcpu->arch.db[dr] = val;
891 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
892 vcpu->arch.eff_db[dr] = val;
893 break;
894 case 4:
020df079
GN		 895 /* fall through */
896 case 6:
338dbc97
GN		 897 if (val & 0xffffffff00000000ULL)
898 return -1; /* #GP */
6f43ed01 899 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 900 kvm_update_dr6(vcpu);
020df079
GN		 901 break;
902 case 5:
020df079
GN		 903 /* fall through */
904 default: /* 7 */
338dbc97
GN		 905 if (val & 0xffffffff00000000ULL)
906 return -1; /* #GP */
020df079 907 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 908 kvm_update_dr7(vcpu);
020df079
GN		 909 break;
910 }
911
912 return 0;
913}
338dbc97
GN		 914
915int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
916{
16f8a6f9 917 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 918 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 919 return 1;
920 }
921 return 0;
338dbc97 922}
020df079
GN		 923EXPORT_SYMBOL_GPL(kvm_set_dr);
924
16f8a6f9 925int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 926{
927 switch (dr) {
928 case 0 ... 3:
929 *val = vcpu->arch.db[dr];
930 break;
931 case 4:
020df079
GN		 932 /* fall through */
933 case 6:
73aaf249
JK		 934 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
935 *val = vcpu->arch.dr6;
936 else
937 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 938 break;
939 case 5:
020df079
GN		 940 /* fall through */
941 default: /* 7 */
942 *val = vcpu->arch.dr7;
943 break;
944 }
338dbc97
GN		 945 return 0;
946}
020df079
GN		 947EXPORT_SYMBOL_GPL(kvm_get_dr);
948
022cd0e8
AK		 949bool kvm_rdpmc(struct kvm_vcpu *vcpu)
950{
951 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
952 u64 data;
953 int err;
954
c6702c9d 955 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 956 if (err)
957 return err;
958 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
959 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
960 return err;
961}
962EXPORT_SYMBOL_GPL(kvm_rdpmc);
963
043405e1
CO		 964/*
965 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
966 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
967 *
968 * This list is modified at module load time to reflect the
e3267cbb 969 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 970 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
971 * may depend on host virtualization features rather than host cpu features.
043405e1 972 */
e3267cbb 973
043405e1
CO		 974static u32 msrs_to_save[] = {
975 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 976 MSR_STAR,
043405e1
CO		 977#ifdef CONFIG_X86_64
978 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
979#endif
b3897a49 980 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 981 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 982};
983
984static unsigned num_msrs_to_save;
985
62ef68bb
PB		 986static u32 emulated_msrs[] = {
987 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
988 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
989 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
990 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 991 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
992 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 993 HV_X64_MSR_RESET,
11c4b1ca 994 HV_X64_MSR_VP_INDEX,
9eec50b8 995 HV_X64_MSR_VP_RUNTIME,
5c919412 996 HV_X64_MSR_SCONTROL,
1f4b34f8 997 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 998 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
999 MSR_KVM_PV_EOI_EN,
1000
ba904635 1001 MSR_IA32_TSC_ADJUST,
a3e06bbe 1002 MSR_IA32_TSCDEADLINE,
043405e1 1003 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1004 MSR_IA32_MCG_STATUS,
1005 MSR_IA32_MCG_CTL,
c45dcc71 1006 MSR_IA32_MCG_EXT_CTL,
64d60670 1007 MSR_IA32_SMBASE,
043405e1
CO		 1008};
1009
62ef68bb
PB		 1010static unsigned num_emulated_msrs;
1011
384bb783 1012bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1013{
b69e8cae 1014 if (efer & efer_reserved_bits)
384bb783 1015 return false;
15c4a640 1016
1b2fd70c
AG		 1017 if (efer & EFER_FFXSR) {
1018 struct kvm_cpuid_entry2 *feat;
1019
1020 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1021 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1022 return false;
1b2fd70c
AG		 1023 }
1024
d8017474
AG		 1025 if (efer & EFER_SVME) {
1026 struct kvm_cpuid_entry2 *feat;
1027
1028 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1029 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1030 return false;
d8017474
AG		 1031 }
1032
384bb783
JK		 1033 return true;
1034}
1035EXPORT_SYMBOL_GPL(kvm_valid_efer);
1036
1037static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1038{
1039 u64 old_efer = vcpu->arch.efer;
1040
1041 if (!kvm_valid_efer(vcpu, efer))
1042 return 1;
1043
1044 if (is_paging(vcpu)
1045 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1046 return 1;
1047
15c4a640 1048 efer &= ~EFER_LMA;
f6801dff 1049 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1050
a3d204e2
SY		 1051 kvm_x86_ops->set_efer(vcpu, efer);
1052
aad82703
SY		 1053 /* Update reserved bits */
1054 if ((efer ^ old_efer) & EFER_NX)
1055 kvm_mmu_reset_context(vcpu);
1056
b69e8cae 1057 return 0;
15c4a640
CO		 1058}
1059
f2b4b7dd
JR		 1060void kvm_enable_efer_bits(u64 mask)
1061{
1062 efer_reserved_bits &= ~mask;
1063}
1064EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1065
15c4a640
CO		 1066/*
1067 * Writes msr value into into the appropriate "register".
1068 * Returns 0 on success, non-0 otherwise.
1069 * Assumes vcpu_load() was already called.
1070 */
8fe8ab46 1071int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1072{
854e8bb1
NA		 1073 switch (msr->index) {
1074 case MSR_FS_BASE:
1075 case MSR_GS_BASE:
1076 case MSR_KERNEL_GS_BASE:
1077 case MSR_CSTAR:
1078 case MSR_LSTAR:
1079 if (is_noncanonical_address(msr->data))
1080 return 1;
1081 break;
1082 case MSR_IA32_SYSENTER_EIP:
1083 case MSR_IA32_SYSENTER_ESP:
1084 /*
1085 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1086 * non-canonical address is written on Intel but not on
1087 * AMD (which ignores the top 32-bits, because it does
1088 * not implement 64-bit SYSENTER).
1089 *
1090 * 64-bit code should hence be able to write a non-canonical
1091 * value on AMD. Making the address canonical ensures that
1092 * vmentry does not fail on Intel after writing a non-canonical
1093 * value, and that something deterministic happens if the guest
1094 * invokes 64-bit SYSENTER.
1095 */
1096 msr->data = get_canonical(msr->data);
1097 }
8fe8ab46 1098 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1099}
854e8bb1 1100EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1101
313a3dc7
CO		 1102/*
1103 * Adapt set_msr() to msr_io()'s calling convention
1104 */
609e36d3
PB		 1105static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1106{
1107 struct msr_data msr;
1108 int r;
1109
1110 msr.index = index;
1111 msr.host_initiated = true;
1112 r = kvm_get_msr(vcpu, &msr);
1113 if (r)
1114 return r;
1115
1116 *data = msr.data;
1117 return 0;
1118}
1119
313a3dc7
CO		 1120static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1121{
8fe8ab46
WA		 1122 struct msr_data msr;
1123
1124 msr.data = *data;
1125 msr.index = index;
1126 msr.host_initiated = true;
1127 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1128}
1129
16e8d74d
MT		 1130#ifdef CONFIG_X86_64
1131struct pvclock_gtod_data {
1132 seqcount_t seq;
1133
1134 struct { /* extract of a clocksource struct */
1135 int vclock_mode;
a5a1d1c2
TG		 1136 u64 cycle_last;
1137 u64 mask;
16e8d74d
MT		 1138 u32 mult;
1139 u32 shift;
1140 } clock;
1141
cbcf2dd3
TG		 1142 u64 boot_ns;
1143 u64 nsec_base;
16e8d74d
MT		 1144};
1145
1146static struct pvclock_gtod_data pvclock_gtod_data;
1147
1148static void update_pvclock_gtod(struct timekeeper *tk)
1149{
1150 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1151 u64 boot_ns;
1152
876e7881 1153 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1154
1155 write_seqcount_begin(&vdata->seq);
1156
1157 /* copy pvclock gtod data */
876e7881
PZ		 1158 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1159 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1160 vdata->clock.mask = tk->tkr_mono.mask;
1161 vdata->clock.mult = tk->tkr_mono.mult;
1162 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1163
cbcf2dd3 1164 vdata->boot_ns = boot_ns;
876e7881 1165 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1166
1167 write_seqcount_end(&vdata->seq);
1168}
1169#endif
1170
bab5bb39
NK		 1171void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1172{
1173 /*
1174 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1175 * vcpu_enter_guest. This function is only called from
1176 * the physical CPU that is running vcpu.
1177 */
1178 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1179}
16e8d74d 1180
18068523
GOC		 1181static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1182{
9ed3c444
AK		 1183 int version;
1184 int r;
50d0a0f9 1185 struct pvclock_wall_clock wc;
87aeb54f 1186 struct timespec64 boot;
18068523
GOC		 1187
1188 if (!wall_clock)
1189 return;
1190
9ed3c444
AK		 1191 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1192 if (r)
1193 return;
1194
1195 if (version & 1)
1196 ++version; /* first time write, random junk */
1197
1198 ++version;
18068523 1199
1dab1345
NK		 1200 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1201 return;
18068523 1202
50d0a0f9
GH		 1203 /*
1204 * The guest calculates current wall clock time by adding
34c238a1 1205 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1206 * wall clock specified here. guest system time equals host
1207 * system time for us, thus we must fill in host boot time here.
1208 */
87aeb54f 1209 getboottime64(&boot);
50d0a0f9 1210
4b648665 1211 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1212 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1213 boot = timespec64_sub(boot, ts);
4b648665 1214 }
87aeb54f 1215 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1216 wc.nsec = boot.tv_nsec;
1217 wc.version = version;
18068523
GOC		 1218
1219 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1220
1221 version++;
1222 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1223}
1224
50d0a0f9
GH		 1225static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1226{
b51012de
PB		 1227 do_shl32_div32(dividend, divisor);
1228 return dividend;
50d0a0f9
GH		 1229}
1230
3ae13faa 1231static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1232 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1233{
5f4e3f88 1234 uint64_t scaled64;
50d0a0f9
GH		 1235 int32_t shift = 0;
1236 uint64_t tps64;
1237 uint32_t tps32;
1238
3ae13faa
PB		 1239 tps64 = base_hz;
1240 scaled64 = scaled_hz;
50933623 1241 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1242 tps64 >>= 1;
1243 shift--;
1244 }
1245
1246 tps32 = (uint32_t)tps64;
50933623
JK		 1247 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1248 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1249 scaled64 >>= 1;
1250 else
1251 tps32 <<= 1;
50d0a0f9
GH		 1252 shift++;
1253 }
1254
5f4e3f88
ZA		 1255 *pshift = shift;
1256 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1257
3ae13faa
PB		 1258 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1259 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1260}
1261
d828199e 1262#ifdef CONFIG_X86_64
16e8d74d 1263static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1264#endif
16e8d74d 1265
c8076604 1266static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1267static unsigned long max_tsc_khz;
c8076604 1268
cc578287 1269static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1270{
cc578287
ZA		 1271 u64 v = (u64)khz * (1000000 + ppm);
1272 do_div(v, 1000000);
1273 return v;
1e993611
JR		 1274}
1275
381d585c
HZ		 1276static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1277{
1278 u64 ratio;
1279
1280 /* Guest TSC same frequency as host TSC? */
1281 if (!scale) {
1282 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1283 return 0;
1284 }
1285
1286 /* TSC scaling supported? */
1287 if (!kvm_has_tsc_control) {
1288 if (user_tsc_khz > tsc_khz) {
1289 vcpu->arch.tsc_catchup = 1;
1290 vcpu->arch.tsc_always_catchup = 1;
1291 return 0;
1292 } else {
1293 WARN(1, "user requested TSC rate below hardware speed\n");
1294 return -1;
1295 }
1296 }
1297
1298 /* TSC scaling required - calculate ratio */
1299 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1300 user_tsc_khz, tsc_khz);
1301
1302 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1303 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1304 user_tsc_khz);
1305 return -1;
1306 }
1307
1308 vcpu->arch.tsc_scaling_ratio = ratio;
1309 return 0;
1310}
1311
4941b8cb 1312static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1313{
cc578287
ZA		 1314 u32 thresh_lo, thresh_hi;
1315 int use_scaling = 0;
217fc9cf 1316
03ba32ca 1317 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1318 if (user_tsc_khz == 0) {
ad721883
HZ		 1319 /* set tsc_scaling_ratio to a safe value */
1320 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1321 return -1;
ad721883 1322 }
03ba32ca 1323
c285545f 1324 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1325 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1326 &vcpu->arch.virtual_tsc_shift,
1327 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1328 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1329
1330 /*
1331 * Compute the variation in TSC rate which is acceptable
1332 * within the range of tolerance and decide if the
1333 * rate being applied is within that bounds of the hardware
1334 * rate. If so, no scaling or compensation need be done.
1335 */
1336 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1337 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1338 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1339 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1340 use_scaling = 1;
1341 }
4941b8cb 1342 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1343}
1344
1345static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1346{
e26101b1 1347 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1348 vcpu->arch.virtual_tsc_mult,
1349 vcpu->arch.virtual_tsc_shift);
e26101b1 1350 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1351 return tsc;
1352}
1353
69b0049a 1354static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1355{
1356#ifdef CONFIG_X86_64
1357 bool vcpus_matched;
b48aa97e
MT		 1358 struct kvm_arch *ka = &vcpu->kvm->arch;
1359 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1360
1361 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1362 atomic_read(&vcpu->kvm->online_vcpus));
1363
7f187922
MT		 1364 /*
1365 * Once the masterclock is enabled, always perform request in
1366 * order to update it.
1367 *
1368 * In order to enable masterclock, the host clocksource must be TSC
1369 * and the vcpus need to have matched TSCs. When that happens,
1370 * perform request to enable masterclock.
1371 */
1372 if (ka->use_master_clock ||
1373 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1374 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1375
1376 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1377 atomic_read(&vcpu->kvm->online_vcpus),
1378 ka->use_master_clock, gtod->clock.vclock_mode);
1379#endif
1380}
1381
ba904635
WA		 1382static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1383{
3e3f5026 1384 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1385 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1386}
1387
35181e86
HZ		 1388/*
1389 * Multiply tsc by a fixed point number represented by ratio.
1390 *
1391 * The most significant 64-N bits (mult) of ratio represent the
1392 * integral part of the fixed point number; the remaining N bits
1393 * (frac) represent the fractional part, ie. ratio represents a fixed
1394 * point number (mult + frac * 2^(-N)).
1395 *
1396 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1397 */
1398static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1399{
1400 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1401}
1402
1403u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1404{
1405 u64 _tsc = tsc;
1406 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1407
1408 if (ratio != kvm_default_tsc_scaling_ratio)
1409 _tsc = __scale_tsc(ratio, tsc);
1410
1411 return _tsc;
1412}
1413EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1414
07c1419a
HZ		 1415static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1416{
1417 u64 tsc;
1418
1419 tsc = kvm_scale_tsc(vcpu, rdtsc());
1420
1421 return target_tsc - tsc;
1422}
1423
4ba76538
HZ		 1424u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1425{
ea26e4ec 1426 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1427}
1428EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1429
a545ab6a
LC		 1430static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1431{
1432 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1433 vcpu->arch.tsc_offset = offset;
1434}
1435
8fe8ab46 1436void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1437{
1438 struct kvm *kvm = vcpu->kvm;
f38e098f 1439 u64 offset, ns, elapsed;
99e3e30a 1440 unsigned long flags;
02626b6a 1441 s64 usdiff;
b48aa97e 1442 bool matched;
0d3da0d2 1443 bool already_matched;
8fe8ab46 1444 u64 data = msr->data;
99e3e30a 1445
038f8c11 1446 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1447 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1448 ns = ktime_get_boot_ns();
f38e098f 1449 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1450
03ba32ca 1451 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1452 int faulted = 0;
1453
03ba32ca
MT		 1454 /* n.b - signed multiplication and division required */
1455 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1456#ifdef CONFIG_X86_64
03ba32ca 1457 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1458#else
03ba32ca 1459 /* do_div() only does unsigned */
8915aa27
MT		 1460 asm("1: idivl %[divisor]\n"
1461 "2: xor %%edx, %%edx\n"
1462 " movl $0, %[faulted]\n"
1463 "3:\n"
1464 ".section .fixup,\"ax\"\n"
1465 "4: movl $1, %[faulted]\n"
1466 " jmp 3b\n"
1467 ".previous\n"
1468
1469 _ASM_EXTABLE(1b, 4b)
1470
1471 : "=A"(usdiff), [faulted] "=r" (faulted)
1472 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1473
5d3cb0f6 1474#endif
03ba32ca
MT		 1475 do_div(elapsed, 1000);
1476 usdiff -= elapsed;
1477 if (usdiff < 0)
1478 usdiff = -usdiff;
8915aa27
MT		 1479
1480 /* idivl overflow => difference is larger than USEC_PER_SEC */
1481 if (faulted)
1482 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1483 } else
1484 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1485
1486 /*
5d3cb0f6
ZA		 1487 * Special case: TSC write with a small delta (1 second) of virtual
1488 * cycle time against real time is interpreted as an attempt to
1489 * synchronize the CPU.
1490 *
1491 * For a reliable TSC, we can match TSC offsets, and for an unstable
1492 * TSC, we add elapsed time in this computation. We could let the
1493 * compensation code attempt to catch up if we fall behind, but
1494 * it's better to try to match offsets from the beginning.
1495 */
02626b6a 1496 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1497 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1498 if (!check_tsc_unstable()) {
e26101b1 1499 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1500 pr_debug("kvm: matched tsc offset for %llu\n", data);
1501 } else {
857e4099 1502 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1503 data += delta;
07c1419a 1504 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1505 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1506 }
b48aa97e 1507 matched = true;
0d3da0d2 1508 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1509 } else {
1510 /*
1511 * We split periods of matched TSC writes into generations.
1512 * For each generation, we track the original measured
1513 * nanosecond time, offset, and write, so if TSCs are in
1514 * sync, we can match exact offset, and if not, we can match
4a969980 1515 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1516 *
1517 * These values are tracked in kvm->arch.cur_xxx variables.
1518 */
1519 kvm->arch.cur_tsc_generation++;
1520 kvm->arch.cur_tsc_nsec = ns;
1521 kvm->arch.cur_tsc_write = data;
1522 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1523 matched = false;
0d3da0d2 1524 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1525 kvm->arch.cur_tsc_generation, data);
f38e098f 1526 }
e26101b1
ZA		 1527
1528 /*
1529 * We also track th most recent recorded KHZ, write and time to
1530 * allow the matching interval to be extended at each write.
1531 */
f38e098f
ZA		 1532 kvm->arch.last_tsc_nsec = ns;
1533 kvm->arch.last_tsc_write = data;
5d3cb0f6 1534 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1535
b183aa58 1536 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1537
1538 /* Keep track of which generation this VCPU has synchronized to */
1539 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1540 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1541 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1542
ba904635
WA		 1543 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1544 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1545 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1546 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1547
1548 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1549 if (!matched) {
b48aa97e 1550 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1551 } else if (!already_matched) {
1552 kvm->arch.nr_vcpus_matched_tsc++;
1553 }
b48aa97e
MT		 1554
1555 kvm_track_tsc_matching(vcpu);
1556 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1557}
e26101b1 1558
99e3e30a
ZA		 1559EXPORT_SYMBOL_GPL(kvm_write_tsc);
1560
58ea6767
HZ		 1561static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1562 s64 adjustment)
1563{
ea26e4ec 1564 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1565}
1566
1567static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1568{
1569 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1570 WARN_ON(adjustment < 0);
1571 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1572 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1573}
1574
d828199e
MT		 1575#ifdef CONFIG_X86_64
1576
a5a1d1c2 1577static u64 read_tsc(void)
d828199e 1578{
a5a1d1c2 1579 u64 ret = (u64)rdtsc_ordered();
03b9730b 1580 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1581
1582 if (likely(ret >= last))
1583 return ret;
1584
1585 /*
1586 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1587 * predictable (it's just a function of time and the likely is
d828199e
MT		 1588 * very likely) and there's a data dependence, so force GCC
1589 * to generate a branch instead. I don't barrier() because
1590 * we don't actually need a barrier, and if this function
1591 * ever gets inlined it will generate worse code.
1592 */
1593 asm volatile ("");
1594 return last;
1595}
1596
a5a1d1c2 1597static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1598{
1599 long v;
1600 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1601
1602 *cycle_now = read_tsc();
1603
1604 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1605 return v * gtod->clock.mult;
1606}
1607
a5a1d1c2 1608static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1609{
cbcf2dd3 1610 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1611 unsigned long seq;
d828199e 1612 int mode;
cbcf2dd3 1613 u64 ns;
d828199e 1614
d828199e
MT		 1615 do {
1616 seq = read_seqcount_begin(&gtod->seq);
1617 mode = gtod->clock.vclock_mode;
cbcf2dd3 1618 ns = gtod->nsec_base;
d828199e
MT		 1619 ns += vgettsc(cycle_now);
1620 ns >>= gtod->clock.shift;
cbcf2dd3 1621 ns += gtod->boot_ns;
d828199e 1622 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1623 *t = ns;
d828199e
MT		 1624
1625 return mode;
1626}
1627
1628/* returns true if host is using tsc clocksource */
a5a1d1c2 1629static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1630{
d828199e
MT		 1631 /* checked again under seqlock below */
1632 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1633 return false;
1634
cbcf2dd3 1635 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1636}
1637#endif
1638
1639/*
1640 *
b48aa97e
MT		 1641 * Assuming a stable TSC across physical CPUS, and a stable TSC
1642 * across virtual CPUs, the following condition is possible.
1643 * Each numbered line represents an event visible to both
d828199e
MT		 1644 * CPUs at the next numbered event.
1645 *
1646 * "timespecX" represents host monotonic time. "tscX" represents
1647 * RDTSC value.
1648 *
1649 * VCPU0 on CPU0 | VCPU1 on CPU1
1650 *
1651 * 1. read timespec0,tsc0
1652 * 2. | timespec1 = timespec0 + N
1653 * | tsc1 = tsc0 + M
1654 * 3. transition to guest | transition to guest
1655 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1656 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1657 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1658 *
1659 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1660 *
1661 * - ret0 < ret1
1662 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1663 * ...
1664 * - 0 < N - M => M < N
1665 *
1666 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1667 * always the case (the difference between two distinct xtime instances
1668 * might be smaller then the difference between corresponding TSC reads,
1669 * when updating guest vcpus pvclock areas).
1670 *
1671 * To avoid that problem, do not allow visibility of distinct
1672 * system_timestamp/tsc_timestamp values simultaneously: use a master
1673 * copy of host monotonic time values. Update that master copy
1674 * in lockstep.
1675 *
b48aa97e 1676 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1677 *
1678 */
1679
1680static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1681{
1682#ifdef CONFIG_X86_64
1683 struct kvm_arch *ka = &kvm->arch;
1684 int vclock_mode;
b48aa97e
MT		 1685 bool host_tsc_clocksource, vcpus_matched;
1686
1687 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1688 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1689
1690 /*
1691 * If the host uses TSC clock, then passthrough TSC as stable
1692 * to the guest.
1693 */
b48aa97e 1694 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1695 &ka->master_kernel_ns,
1696 &ka->master_cycle_now);
1697
16a96021 1698 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1699 && !backwards_tsc_observed
1700 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1701
d828199e
MT		 1702 if (ka->use_master_clock)
1703 atomic_set(&kvm_guest_has_master_clock, 1);
1704
1705 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1706 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1707 vcpus_matched);
d828199e
MT		 1708#endif
1709}
1710
2860c4b1
PB		 1711void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1712{
1713 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1714}
1715
2e762ff7
MT		 1716static void kvm_gen_update_masterclock(struct kvm *kvm)
1717{
1718#ifdef CONFIG_X86_64
1719 int i;
1720 struct kvm_vcpu *vcpu;
1721 struct kvm_arch *ka = &kvm->arch;
1722
1723 spin_lock(&ka->pvclock_gtod_sync_lock);
1724 kvm_make_mclock_inprogress_request(kvm);
1725 /* no guest entries from this point */
1726 pvclock_update_vm_gtod_copy(kvm);
1727
1728 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1729 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1730
1731 /* guest entries allowed */
1732 kvm_for_each_vcpu(i, vcpu, kvm)
1733 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1734
1735 spin_unlock(&ka->pvclock_gtod_sync_lock);
1736#endif
1737}
1738
108b249c
PB		 1739static u64 __get_kvmclock_ns(struct kvm *kvm)
1740{
108b249c 1741 struct kvm_arch *ka = &kvm->arch;
8b953440 1742 struct pvclock_vcpu_time_info hv_clock;
108b249c 1743
8b953440
PB		 1744 spin_lock(&ka->pvclock_gtod_sync_lock);
1745 if (!ka->use_master_clock) {
1746 spin_unlock(&ka->pvclock_gtod_sync_lock);
1747 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1748 }
1749
8b953440
PB		 1750 hv_clock.tsc_timestamp = ka->master_cycle_now;
1751 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1752 spin_unlock(&ka->pvclock_gtod_sync_lock);
1753
1754 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1755 &hv_clock.tsc_shift,
1756 &hv_clock.tsc_to_system_mul);
1757 return __pvclock_read_cycles(&hv_clock, rdtsc());
108b249c
PB		 1758}
1759
1760u64 get_kvmclock_ns(struct kvm *kvm)
1761{
1762 unsigned long flags;
1763 s64 ns;
1764
1765 local_irq_save(flags);
1766 ns = __get_kvmclock_ns(kvm);
1767 local_irq_restore(flags);
1768
1769 return ns;
1770}
1771
0d6dd2ff
PB		 1772static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1773{
1774 struct kvm_vcpu_arch *vcpu = &v->arch;
1775 struct pvclock_vcpu_time_info guest_hv_clock;
1776
1777 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1778 &guest_hv_clock, sizeof(guest_hv_clock))))
1779 return;
1780
1781 /* This VCPU is paused, but it's legal for a guest to read another
1782 * VCPU's kvmclock, so we really have to follow the specification where
1783 * it says that version is odd if data is being modified, and even after
1784 * it is consistent.
1785 *
1786 * Version field updates must be kept separate. This is because
1787 * kvm_write_guest_cached might use a "rep movs" instruction, and
1788 * writes within a string instruction are weakly ordered. So there
1789 * are three writes overall.
1790 *
1791 * As a small optimization, only write the version field in the first
1792 * and third write. The vcpu->pv_time cache is still valid, because the
1793 * version field is the first in the struct.
1794 */
1795 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1796
1797 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1798 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1799 &vcpu->hv_clock,
1800 sizeof(vcpu->hv_clock.version));
1801
1802 smp_wmb();
1803
1804 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1805 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1806
1807 if (vcpu->pvclock_set_guest_stopped_request) {
1808 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1809 vcpu->pvclock_set_guest_stopped_request = false;
1810 }
1811
1812 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1813
1814 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1815 &vcpu->hv_clock,
1816 sizeof(vcpu->hv_clock));
1817
1818 smp_wmb();
1819
1820 vcpu->hv_clock.version++;
1821 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1822 &vcpu->hv_clock,
1823 sizeof(vcpu->hv_clock.version));
1824}
1825
34c238a1 1826static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1827{
78db6a50 1828 unsigned long flags, tgt_tsc_khz;
18068523 1829 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1830 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1831 s64 kernel_ns;
d828199e 1832 u64 tsc_timestamp, host_tsc;
51d59c6b 1833 u8 pvclock_flags;
d828199e
MT		 1834 bool use_master_clock;
1835
1836 kernel_ns = 0;
1837 host_tsc = 0;
18068523 1838
d828199e
MT		 1839 /*
1840 * If the host uses TSC clock, then passthrough TSC as stable
1841 * to the guest.
1842 */
1843 spin_lock(&ka->pvclock_gtod_sync_lock);
1844 use_master_clock = ka->use_master_clock;
1845 if (use_master_clock) {
1846 host_tsc = ka->master_cycle_now;
1847 kernel_ns = ka->master_kernel_ns;
1848 }
1849 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1850
1851 /* Keep irq disabled to prevent changes to the clock */
1852 local_irq_save(flags);
78db6a50
PB		 1853 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1854 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1855 local_irq_restore(flags);
1856 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1857 return 1;
1858 }
d828199e 1859 if (!use_master_clock) {
4ea1636b 1860 host_tsc = rdtsc();
108b249c 1861 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1862 }
1863
4ba76538 1864 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1865
c285545f
ZA		 1866 /*
1867 * We may have to catch up the TSC to match elapsed wall clock
1868 * time for two reasons, even if kvmclock is used.
1869 * 1) CPU could have been running below the maximum TSC rate
1870 * 2) Broken TSC compensation resets the base at each VCPU
1871 * entry to avoid unknown leaps of TSC even when running
1872 * again on the same CPU. This may cause apparent elapsed
1873 * time to disappear, and the guest to stand still or run
1874 * very slowly.
1875 */
1876 if (vcpu->tsc_catchup) {
1877 u64 tsc = compute_guest_tsc(v, kernel_ns);
1878 if (tsc > tsc_timestamp) {
f1e2b260 1879 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1880 tsc_timestamp = tsc;
1881 }
50d0a0f9
GH		 1882 }
1883
18068523
GOC		 1884 local_irq_restore(flags);
1885
0d6dd2ff 1886 /* With all the info we got, fill in the values */
18068523 1887
78db6a50
PB		 1888 if (kvm_has_tsc_control)
1889 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1890
1891 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1892 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1893 &vcpu->hv_clock.tsc_shift,
1894 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1895 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1896 }
1897
1d5f066e 1898 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1899 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1900 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1901
d828199e 1902 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1903 pvclock_flags = 0;
d828199e
MT		 1904 if (use_master_clock)
1905 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1906
78c0337a
MT		 1907 vcpu->hv_clock.flags = pvclock_flags;
1908
095cf55d
PB		 1909 if (vcpu->pv_time_enabled)
1910 kvm_setup_pvclock_page(v);
1911 if (v == kvm_get_vcpu(v->kvm, 0))
1912 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1913 return 0;
c8076604
GH		 1914}
1915
0061d53d
MT		 1916/*
1917 * kvmclock updates which are isolated to a given vcpu, such as
1918 * vcpu->cpu migration, should not allow system_timestamp from
1919 * the rest of the vcpus to remain static. Otherwise ntp frequency
1920 * correction applies to one vcpu's system_timestamp but not
1921 * the others.
1922 *
1923 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1924 * We need to rate-limit these requests though, as they can
1925 * considerably slow guests that have a large number of vcpus.
1926 * The time for a remote vcpu to update its kvmclock is bound
1927 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1928 */
1929
7e44e449
AJ		 1930#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1931
1932static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1933{
1934 int i;
7e44e449
AJ		 1935 struct delayed_work *dwork = to_delayed_work(work);
1936 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1937 kvmclock_update_work);
1938 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1939 struct kvm_vcpu *vcpu;
1940
1941 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1942 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1943 kvm_vcpu_kick(vcpu);
1944 }
1945}
1946
7e44e449
AJ		 1947static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1948{
1949 struct kvm *kvm = v->kvm;
1950
105b21bb 1951 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1952 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1953 KVMCLOCK_UPDATE_DELAY);
1954}
1955
332967a3
AJ		 1956#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1957
1958static void kvmclock_sync_fn(struct work_struct *work)
1959{
1960 struct delayed_work *dwork = to_delayed_work(work);
1961 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1962 kvmclock_sync_work);
1963 struct kvm *kvm = container_of(ka, struct kvm, arch);
1964
630994b3
MT		 1965 if (!kvmclock_periodic_sync)
1966 return;
1967
332967a3
AJ		 1968 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1969 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1970 KVMCLOCK_SYNC_PERIOD);
1971}
1972
890ca9ae 1973static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1974{
890ca9ae
HY		 1975 u64 mcg_cap = vcpu->arch.mcg_cap;
1976 unsigned bank_num = mcg_cap & 0xff;
1977
15c4a640 1978 switch (msr) {
15c4a640 1979 case MSR_IA32_MCG_STATUS:
890ca9ae 1980 vcpu->arch.mcg_status = data;
15c4a640 1981 break;
c7ac679c 1982 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1983 if (!(mcg_cap & MCG_CTL_P))
1984 return 1;
1985 if (data != 0 && data != ~(u64)0)
1986 return -1;
1987 vcpu->arch.mcg_ctl = data;
1988 break;
1989 default:
1990 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1991 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1992 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1993 /* only 0 or all 1s can be written to IA32_MCi_CTL
1994 * some Linux kernels though clear bit 10 in bank 4 to
1995 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1996 * this to avoid an uncatched #GP in the guest
1997 */
890ca9ae 1998 if ((offset & 0x3) == 0 &&
114be429 1999 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2000 return -1;
2001 vcpu->arch.mce_banks[offset] = data;
2002 break;
2003 }
2004 return 1;
2005 }
2006 return 0;
2007}
2008
ffde22ac
ES		 2009static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2010{
2011 struct kvm *kvm = vcpu->kvm;
2012 int lm = is_long_mode(vcpu);
2013 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2014 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2015 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2016 : kvm->arch.xen_hvm_config.blob_size_32;
2017 u32 page_num = data & ~PAGE_MASK;
2018 u64 page_addr = data & PAGE_MASK;
2019 u8 *page;
2020 int r;
2021
2022 r = -E2BIG;
2023 if (page_num >= blob_size)
2024 goto out;
2025 r = -ENOMEM;
ff5c2c03
SL		 2026 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2027 if (IS_ERR(page)) {
2028 r = PTR_ERR(page);
ffde22ac 2029 goto out;
ff5c2c03 2030 }
54bf36aa 2031 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2032 goto out_free;
2033 r = 0;
2034out_free:
2035 kfree(page);
2036out:
2037 return r;
2038}
2039
344d9588
GN		 2040static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2041{
2042 gpa_t gpa = data & ~0x3f;
2043
4a969980 2044 /* Bits 2:5 are reserved, Should be zero */
6adba527 2045 if (data & 0x3c)
344d9588
GN		 2046 return 1;
2047
2048 vcpu->arch.apf.msr_val = data;
2049
2050 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2051 kvm_clear_async_pf_completion_queue(vcpu);
2052 kvm_async_pf_hash_reset(vcpu);
2053 return 0;
2054 }
2055
8f964525
AH		 2056 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2057 sizeof(u32)))
344d9588
GN		 2058 return 1;
2059
6adba527 2060 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2061 kvm_async_pf_wakeup_all(vcpu);
2062 return 0;
2063}
2064
12f9a48f
GC		 2065static void kvmclock_reset(struct kvm_vcpu *vcpu)
2066{
0b79459b 2067 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2068}
2069
c9aaa895
GC		 2070static void record_steal_time(struct kvm_vcpu *vcpu)
2071{
2072 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2073 return;
2074
2075 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2076 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2077 return;
2078
0b9f6c46
PX		 2079 vcpu->arch.st.steal.preempted = 0;
2080
35f3fae1
WL		 2081 if (vcpu->arch.st.steal.version & 1)
2082 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2083
2084 vcpu->arch.st.steal.version += 1;
2085
2086 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2087 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2088
2089 smp_wmb();
2090
c54cdf14
LC		 2091 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2092 vcpu->arch.st.last_steal;
2093 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1
WL		 2094
2095 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2096 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2097
2098 smp_wmb();
2099
2100 vcpu->arch.st.steal.version += 1;
c9aaa895
GC		 2101
2102 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2103 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2104}
2105
8fe8ab46 2106int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2107{
5753785f 2108 bool pr = false;
8fe8ab46
WA		 2109 u32 msr = msr_info->index;
2110 u64 data = msr_info->data;
5753785f 2111
15c4a640 2112 switch (msr) {
2e32b719
BP		 2113 case MSR_AMD64_NB_CFG:
2114 case MSR_IA32_UCODE_REV:
2115 case MSR_IA32_UCODE_WRITE:
2116 case MSR_VM_HSAVE_PA:
2117 case MSR_AMD64_PATCH_LOADER:
2118 case MSR_AMD64_BU_CFG2:
2119 break;
2120
15c4a640 2121 case MSR_EFER:
b69e8cae 2122 return set_efer(vcpu, data);
8f1589d9
AP		 2123 case MSR_K7_HWCR:
2124 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2125 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2126 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2127 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2128 if (data != 0) {
a737f256
CD		 2129 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2130 data);
8f1589d9
AP		 2131 return 1;
2132 }
15c4a640 2133 break;
f7c6d140
AP		 2134 case MSR_FAM10H_MMIO_CONF_BASE:
2135 if (data != 0) {
a737f256
CD		 2136 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2137 "0x%llx\n", data);
f7c6d140
AP		 2138 return 1;
2139 }
15c4a640 2140 break;
b5e2fec0
AG		 2141 case MSR_IA32_DEBUGCTLMSR:
2142 if (!data) {
2143 /* We support the non-activated case already */
2144 break;
2145 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2146 /* Values other than LBR and BTF are vendor-specific,
2147 thus reserved and should throw a #GP */
2148 return 1;
2149 }
a737f256
CD		 2150 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2151 __func__, data);
b5e2fec0 2152 break;
9ba075a6 2153 case 0x200 ... 0x2ff:
ff53604b 2154 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2155 case MSR_IA32_APICBASE:
58cb628d 2156 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2157 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2158 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2159 case MSR_IA32_TSCDEADLINE:
2160 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2161 break;
ba904635
WA		 2162 case MSR_IA32_TSC_ADJUST:
2163 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2164 if (!msr_info->host_initiated) {
d913b904 2165 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2166 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2167 }
2168 vcpu->arch.ia32_tsc_adjust_msr = data;
2169 }
2170 break;
15c4a640 2171 case MSR_IA32_MISC_ENABLE:
ad312c7c 2172 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2173 break;
64d60670
PB		 2174 case MSR_IA32_SMBASE:
2175 if (!msr_info->host_initiated)
2176 return 1;
2177 vcpu->arch.smbase = data;
2178 break;
11c6bffa 2179 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2180 case MSR_KVM_WALL_CLOCK:
2181 vcpu->kvm->arch.wall_clock = data;
2182 kvm_write_wall_clock(vcpu->kvm, data);
2183 break;
11c6bffa 2184 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2185 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2186 struct kvm_arch *ka = &vcpu->kvm->arch;
2187
12f9a48f 2188 kvmclock_reset(vcpu);
18068523 2189
54750f2c
MT		 2190 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2191 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2192
2193 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2194 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2195 &vcpu->requests);
2196
2197 ka->boot_vcpu_runs_old_kvmclock = tmp;
2198 }
2199
18068523 2200 vcpu->arch.time = data;
0061d53d 2201 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2202
2203 /* we verify if the enable bit is set... */
2204 if (!(data & 1))
2205 break;
2206
0b79459b 2207 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2208 &vcpu->arch.pv_time, data & ~1ULL,
2209 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2210 vcpu->arch.pv_time_enabled = false;
2211 else
2212 vcpu->arch.pv_time_enabled = true;
32cad84f 2213
18068523
GOC		 2214 break;
2215 }
344d9588
GN		 2216 case MSR_KVM_ASYNC_PF_EN:
2217 if (kvm_pv_enable_async_pf(vcpu, data))
2218 return 1;
2219 break;
c9aaa895
GC		 2220 case MSR_KVM_STEAL_TIME:
2221
2222 if (unlikely(!sched_info_on()))
2223 return 1;
2224
2225 if (data & KVM_STEAL_RESERVED_MASK)
2226 return 1;
2227
2228 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2229 data & KVM_STEAL_VALID_BITS,
2230 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2231 return 1;
2232
2233 vcpu->arch.st.msr_val = data;
2234
2235 if (!(data & KVM_MSR_ENABLED))
2236 break;
2237
c9aaa895
GC		 2238 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2239
2240 break;
ae7a2a3f
MT		 2241 case MSR_KVM_PV_EOI_EN:
2242 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2243 return 1;
2244 break;
c9aaa895 2245
890ca9ae
HY		 2246 case MSR_IA32_MCG_CTL:
2247 case MSR_IA32_MCG_STATUS:
81760dcc 2248 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2249 return set_msr_mce(vcpu, msr, data);
71db6023 2250
6912ac32
WH		 2251 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2252 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2253 pr = true; /* fall through */
2254 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2255 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2256 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2257 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2258
2259 if (pr || data != 0)
a737f256
CD		 2260 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2261 "0x%x data 0x%llx\n", msr, data);
5753785f 2262 break;
84e0cefa
JS		 2263 case MSR_K7_CLK_CTL:
2264 /*
2265 * Ignore all writes to this no longer documented MSR.
2266 * Writes are only relevant for old K7 processors,
2267 * all pre-dating SVM, but a recommended workaround from
4a969980 2268 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2269 * affected processor models on the command line, hence
2270 * the need to ignore the workaround.
2271 */
2272 break;
55cd8e5a 2273 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2274 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2275 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2276 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2277 return kvm_hv_set_msr_common(vcpu, msr, data,
2278 msr_info->host_initiated);
91c9c3ed 2279 case MSR_IA32_BBL_CR_CTL3:
2280 /* Drop writes to this legacy MSR -- see rdmsr
2281 * counterpart for further detail.
2282 */
796f4687 2283 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2284 break;
2b036c6b
BO		 2285 case MSR_AMD64_OSVW_ID_LENGTH:
2286 if (!guest_cpuid_has_osvw(vcpu))
2287 return 1;
2288 vcpu->arch.osvw.length = data;
2289 break;
2290 case MSR_AMD64_OSVW_STATUS:
2291 if (!guest_cpuid_has_osvw(vcpu))
2292 return 1;
2293 vcpu->arch.osvw.status = data;
2294 break;
15c4a640 2295 default:
ffde22ac
ES		 2296 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2297 return xen_hvm_config(vcpu, data);
c6702c9d 2298 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2299 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2300 if (!ignore_msrs) {
ae0f5499 2301 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2302 msr, data);
ed85c068
AP		 2303 return 1;
2304 } else {
796f4687 2305 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2306 msr, data);
ed85c068
AP		 2307 break;
2308 }
15c4a640
CO		 2309 }
2310 return 0;
2311}
2312EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2313
2314
2315/*
2316 * Reads an msr value (of 'msr_index') into 'pdata'.
2317 * Returns 0 on success, non-0 otherwise.
2318 * Assumes vcpu_load() was already called.
2319 */
609e36d3 2320int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2321{
609e36d3 2322 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2323}
ff651cb6 2324EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2325
890ca9ae 2326static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2327{
2328 u64 data;
890ca9ae
HY		 2329 u64 mcg_cap = vcpu->arch.mcg_cap;
2330 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2331
2332 switch (msr) {
15c4a640
CO		 2333 case MSR_IA32_P5_MC_ADDR:
2334 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2335 data = 0;
2336 break;
15c4a640 2337 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2338 data = vcpu->arch.mcg_cap;
2339 break;
c7ac679c 2340 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2341 if (!(mcg_cap & MCG_CTL_P))
2342 return 1;
2343 data = vcpu->arch.mcg_ctl;
2344 break;
2345 case MSR_IA32_MCG_STATUS:
2346 data = vcpu->arch.mcg_status;
2347 break;
2348 default:
2349 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2350 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2351 u32 offset = msr - MSR_IA32_MC0_CTL;
2352 data = vcpu->arch.mce_banks[offset];
2353 break;
2354 }
2355 return 1;
2356 }
2357 *pdata = data;
2358 return 0;
2359}
2360
609e36d3 2361int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2362{
609e36d3 2363 switch (msr_info->index) {
890ca9ae 2364 case MSR_IA32_PLATFORM_ID:
15c4a640 2365 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2366 case MSR_IA32_DEBUGCTLMSR:
2367 case MSR_IA32_LASTBRANCHFROMIP:
2368 case MSR_IA32_LASTBRANCHTOIP:
2369 case MSR_IA32_LASTINTFROMIP:
2370 case MSR_IA32_LASTINTTOIP:
60af2ecd 2371 case MSR_K8_SYSCFG:
3afb1121
PB		 2372 case MSR_K8_TSEG_ADDR:
2373 case MSR_K8_TSEG_MASK:
60af2ecd 2374 case MSR_K7_HWCR:
61a6bd67 2375 case MSR_VM_HSAVE_PA:
1fdbd48c 2376 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2377 case MSR_AMD64_NB_CFG:
f7c6d140 2378 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2379 case MSR_AMD64_BU_CFG2:
0c2df2a1 2380 case MSR_IA32_PERF_CTL:
609e36d3 2381 msr_info->data = 0;
15c4a640 2382 break;
6912ac32
WH		 2383 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2384 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2385 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2386 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2387 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2388 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2389 msr_info->data = 0;
5753785f 2390 break;
742bc670 2391 case MSR_IA32_UCODE_REV:
609e36d3 2392 msr_info->data = 0x100000000ULL;
742bc670 2393 break;
9ba075a6 2394 case MSR_MTRRcap:
9ba075a6 2395 case 0x200 ... 0x2ff:
ff53604b 2396 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2397 case 0xcd: /* fsb frequency */
609e36d3 2398 msr_info->data = 3;
15c4a640 2399 break;
7b914098
JS		 2400 /*
2401 * MSR_EBC_FREQUENCY_ID
2402 * Conservative value valid for even the basic CPU models.
2403 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2404 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2405 * and 266MHz for model 3, or 4. Set Core Clock
2406 * Frequency to System Bus Frequency Ratio to 1 (bits
2407 * 31:24) even though these are only valid for CPU
2408 * models > 2, however guests may end up dividing or
2409 * multiplying by zero otherwise.
2410 */
2411 case MSR_EBC_FREQUENCY_ID:
609e36d3 2412 msr_info->data = 1 << 24;
7b914098 2413 break;
15c4a640 2414 case MSR_IA32_APICBASE:
609e36d3 2415 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2416 break;
0105d1a5 2417 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2418 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2419 break;
a3e06bbe 2420 case MSR_IA32_TSCDEADLINE:
609e36d3 2421 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2422 break;
ba904635 2423 case MSR_IA32_TSC_ADJUST:
609e36d3 2424 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2425 break;
15c4a640 2426 case MSR_IA32_MISC_ENABLE:
609e36d3 2427 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2428 break;
64d60670
PB		 2429 case MSR_IA32_SMBASE:
2430 if (!msr_info->host_initiated)
2431 return 1;
2432 msr_info->data = vcpu->arch.smbase;
15c4a640 2433 break;
847f0ad8
AG		 2434 case MSR_IA32_PERF_STATUS:
2435 /* TSC increment by tick */
609e36d3 2436 msr_info->data = 1000ULL;
847f0ad8 2437 /* CPU multiplier */
b0996ae4 2438 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2439 break;
15c4a640 2440 case MSR_EFER:
609e36d3 2441 msr_info->data = vcpu->arch.efer;
15c4a640 2442 break;
18068523 2443 case MSR_KVM_WALL_CLOCK:
11c6bffa 2444 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2445 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2446 break;
2447 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2448 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2449 msr_info->data = vcpu->arch.time;
18068523 2450 break;
344d9588 2451 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2452 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2453 break;
c9aaa895 2454 case MSR_KVM_STEAL_TIME:
609e36d3 2455 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2456 break;
1d92128f 2457 case MSR_KVM_PV_EOI_EN:
609e36d3 2458 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2459 break;
890ca9ae
HY		 2460 case MSR_IA32_P5_MC_ADDR:
2461 case MSR_IA32_P5_MC_TYPE:
2462 case MSR_IA32_MCG_CAP:
2463 case MSR_IA32_MCG_CTL:
2464 case MSR_IA32_MCG_STATUS:
81760dcc 2465 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2466 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2467 case MSR_K7_CLK_CTL:
2468 /*
2469 * Provide expected ramp-up count for K7. All other
2470 * are set to zero, indicating minimum divisors for
2471 * every field.
2472 *
2473 * This prevents guest kernels on AMD host with CPU
2474 * type 6, model 8 and higher from exploding due to
2475 * the rdmsr failing.
2476 */
609e36d3 2477 msr_info->data = 0x20000000;
84e0cefa 2478 break;
55cd8e5a 2479 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2480 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2481 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2482 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2483 return kvm_hv_get_msr_common(vcpu,
2484 msr_info->index, &msr_info->data);
55cd8e5a 2485 break;
91c9c3ed 2486 case MSR_IA32_BBL_CR_CTL3:
2487 /* This legacy MSR exists but isn't fully documented in current
2488 * silicon. It is however accessed by winxp in very narrow
2489 * scenarios where it sets bit #19, itself documented as
2490 * a "reserved" bit. Best effort attempt to source coherent
2491 * read data here should the balance of the register be
2492 * interpreted by the guest:
2493 *
2494 * L2 cache control register 3: 64GB range, 256KB size,
2495 * enabled, latency 0x1, configured
2496 */
609e36d3 2497 msr_info->data = 0xbe702111;
91c9c3ed 2498 break;
2b036c6b
BO		 2499 case MSR_AMD64_OSVW_ID_LENGTH:
2500 if (!guest_cpuid_has_osvw(vcpu))
2501 return 1;
609e36d3 2502 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2503 break;
2504 case MSR_AMD64_OSVW_STATUS:
2505 if (!guest_cpuid_has_osvw(vcpu))
2506 return 1;
609e36d3 2507 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2508 break;
15c4a640 2509 default:
c6702c9d 2510 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2511 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2512 if (!ignore_msrs) {
ae0f5499
BD		 2513 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2514 msr_info->index);
ed85c068
AP		 2515 return 1;
2516 } else {
609e36d3
PB		 2517 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2518 msr_info->data = 0;
ed85c068
AP		 2519 }
2520 break;
15c4a640 2521 }
15c4a640
CO		 2522 return 0;
2523}
2524EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2525
313a3dc7
CO		 2526/*
2527 * Read or write a bunch of msrs. All parameters are kernel addresses.
2528 *
2529 * @return number of msrs set successfully.
2530 */
2531static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2532 struct kvm_msr_entry *entries,
2533 int (*do_msr)(struct kvm_vcpu *vcpu,
2534 unsigned index, u64 *data))
2535{
f656ce01 2536 int i, idx;
313a3dc7 2537
f656ce01 2538 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2539 for (i = 0; i < msrs->nmsrs; ++i)
2540 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2541 break;
f656ce01 2542 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2543
313a3dc7
CO		 2544 return i;
2545}
2546
2547/*
2548 * Read or write a bunch of msrs. Parameters are user addresses.
2549 *
2550 * @return number of msrs set successfully.
2551 */
2552static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2553 int (*do_msr)(struct kvm_vcpu *vcpu,
2554 unsigned index, u64 *data),
2555 int writeback)
2556{
2557 struct kvm_msrs msrs;
2558 struct kvm_msr_entry *entries;
2559 int r, n;
2560 unsigned size;
2561
2562 r = -EFAULT;
2563 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2564 goto out;
2565
2566 r = -E2BIG;
2567 if (msrs.nmsrs >= MAX_IO_MSRS)
2568 goto out;
2569
313a3dc7 2570 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2571 entries = memdup_user(user_msrs->entries, size);
2572 if (IS_ERR(entries)) {
2573 r = PTR_ERR(entries);
313a3dc7 2574 goto out;
ff5c2c03 2575 }
313a3dc7
CO		 2576
2577 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2578 if (r < 0)
2579 goto out_free;
2580
2581 r = -EFAULT;
2582 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2583 goto out_free;
2584
2585 r = n;
2586
2587out_free:
7a73c028 2588 kfree(entries);
313a3dc7
CO		 2589out:
2590 return r;
2591}
2592
784aa3d7 2593int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2594{
2595 int r;
2596
2597 switch (ext) {
2598 case KVM_CAP_IRQCHIP:
2599 case KVM_CAP_HLT:
2600 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2601 case KVM_CAP_SET_TSS_ADDR:
07716717 2602 case KVM_CAP_EXT_CPUID:
9c15bb1d 2603 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2604 case KVM_CAP_CLOCKSOURCE:
7837699f 2605 case KVM_CAP_PIT:
a28e4f5a 2606 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2607 case KVM_CAP_MP_STATE:
ed848624 2608 case KVM_CAP_SYNC_MMU:
a355c85c 2609 case KVM_CAP_USER_NMI:
52d939a0 2610 case KVM_CAP_REINJECT_CONTROL:
4925663a 2611 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2612 case KVM_CAP_IOEVENTFD:
f848a5a8 2613 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2614 case KVM_CAP_PIT2:
e9f42757 2615 case KVM_CAP_PIT_STATE2:
b927a3ce 2616 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2617 case KVM_CAP_XEN_HVM:
3cfc3092 2618 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2619 case KVM_CAP_HYPERV:
10388a07 2620 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2621 case KVM_CAP_HYPERV_SPIN:
5c919412 2622 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2623 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2624 case KVM_CAP_DEBUGREGS:
d2be1651 2625 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2626 case KVM_CAP_XSAVE:
344d9588 2627 case KVM_CAP_ASYNC_PF:
92a1f12d 2628 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2629 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2630 case KVM_CAP_READONLY_MEM:
5f66b620 2631 case KVM_CAP_HYPERV_TIME:
100943c5 2632 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2633 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2634 case KVM_CAP_ENABLE_CAP_VM:
2635 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2636 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2637 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2638#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2639 case KVM_CAP_ASSIGN_DEV_IRQ:
2640 case KVM_CAP_PCI_2_3:
2641#endif
018d00d2
ZX		 2642 r = 1;
2643 break;
e3fd9a93
PB		 2644 case KVM_CAP_ADJUST_CLOCK:
2645 r = KVM_CLOCK_TSC_STABLE;
2646 break;
6d396b55
PB		 2647 case KVM_CAP_X86_SMM:
2648 /* SMBASE is usually relocated above 1M on modern chipsets,
2649 * and SMM handlers might indeed rely on 4G segment limits,
2650 * so do not report SMM to be available if real mode is
2651 * emulated via vm86 mode. Still, do not go to great lengths
2652 * to avoid userspace's usage of the feature, because it is a
2653 * fringe case that is not enabled except via specific settings
2654 * of the module parameters.
2655 */
2656 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2657 break;
542472b5
LV		 2658 case KVM_CAP_COALESCED_MMIO:
2659 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2660 break;
774ead3a
AK		 2661 case KVM_CAP_VAPIC:
2662 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2663 break;
f725230a 2664 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2665 r = KVM_SOFT_MAX_VCPUS;
2666 break;
2667 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2668 r = KVM_MAX_VCPUS;
2669 break;
a988b910 2670 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2671 r = KVM_USER_MEM_SLOTS;
a988b910 2672 break;
a68a6a72
MT		 2673 case KVM_CAP_PV_MMU: /* obsolete */
2674 r = 0;
2f333bcb 2675 break;
4cee4b72 2676#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2677 case KVM_CAP_IOMMU:
a1b60c1c 2678 r = iommu_present(&pci_bus_type);
62c476c7 2679 break;
4cee4b72 2680#endif
890ca9ae
HY		 2681 case KVM_CAP_MCE:
2682 r = KVM_MAX_MCE_BANKS;
2683 break;
2d5b5a66 2684 case KVM_CAP_XCRS:
d366bf7e 2685 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2686 break;
92a1f12d
JR		 2687 case KVM_CAP_TSC_CONTROL:
2688 r = kvm_has_tsc_control;
2689 break;
37131313
RK		 2690 case KVM_CAP_X2APIC_API:
2691 r = KVM_X2APIC_API_VALID_FLAGS;
2692 break;
018d00d2
ZX		 2693 default:
2694 r = 0;
2695 break;
2696 }
2697 return r;
2698
2699}
2700
043405e1
CO		 2701long kvm_arch_dev_ioctl(struct file *filp,
2702 unsigned int ioctl, unsigned long arg)
2703{
2704 void __user *argp = (void __user *)arg;
2705 long r;
2706
2707 switch (ioctl) {
2708 case KVM_GET_MSR_INDEX_LIST: {
2709 struct kvm_msr_list __user *user_msr_list = argp;
2710 struct kvm_msr_list msr_list;
2711 unsigned n;
2712
2713 r = -EFAULT;
2714 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2715 goto out;
2716 n = msr_list.nmsrs;
62ef68bb 2717 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2718 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2719 goto out;
2720 r = -E2BIG;
e125e7b6 2721 if (n < msr_list.nmsrs)
043405e1
CO		 2722 goto out;
2723 r = -EFAULT;
2724 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2725 num_msrs_to_save * sizeof(u32)))
2726 goto out;
e125e7b6 2727 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2728 &emulated_msrs,
62ef68bb 2729 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2730 goto out;
2731 r = 0;
2732 break;
2733 }
9c15bb1d
BP		 2734 case KVM_GET_SUPPORTED_CPUID:
2735 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2736 struct kvm_cpuid2 __user *cpuid_arg = argp;
2737 struct kvm_cpuid2 cpuid;
2738
2739 r = -EFAULT;
2740 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2741 goto out;
9c15bb1d
BP		 2742
2743 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2744 ioctl);
674eea0f
AK		 2745 if (r)
2746 goto out;
2747
2748 r = -EFAULT;
2749 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2750 goto out;
2751 r = 0;
2752 break;
2753 }
890ca9ae 2754 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2755 r = -EFAULT;
c45dcc71
AR		 2756 if (copy_to_user(argp, &kvm_mce_cap_supported,
2757 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2758 goto out;
2759 r = 0;
2760 break;
2761 }
043405e1
CO		 2762 default:
2763 r = -EINVAL;
2764 }
2765out:
2766 return r;
2767}
2768
f5f48ee1
SY		 2769static void wbinvd_ipi(void *garbage)
2770{
2771 wbinvd();
2772}
2773
2774static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2775{
e0f0bbc5 2776 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2777}
2778
2860c4b1
PB		 2779static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2780{
2781 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2782}
2783
313a3dc7
CO		 2784void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2785{
f5f48ee1
SY		 2786 /* Address WBINVD may be executed by guest */
2787 if (need_emulate_wbinvd(vcpu)) {
2788 if (kvm_x86_ops->has_wbinvd_exit())
2789 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2790 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2791 smp_call_function_single(vcpu->cpu,
2792 wbinvd_ipi, NULL, 1);
2793 }
2794
313a3dc7 2795 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2796
0dd6a6ed
ZA		 2797 /* Apply any externally detected TSC adjustments (due to suspend) */
2798 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2799 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2800 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2801 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2802 }
8f6055cb 2803
48434c20 2804 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2805 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2806 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2807 if (tsc_delta < 0)
2808 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2809
c285545f 2810 if (check_tsc_unstable()) {
07c1419a 2811 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2812 vcpu->arch.last_guest_tsc);
a545ab6a 2813 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2814 vcpu->arch.tsc_catchup = 1;
c285545f 2815 }
e12c8f36
WL		 2816 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2817 kvm_x86_ops->set_hv_timer(vcpu,
498f8162 2818 kvm_get_lapic_target_expiration_tsc(vcpu)))
e12c8f36 2819 kvm_lapic_switch_to_sw_timer(vcpu);
d98d07ca
MT		 2820 /*
2821 * On a host with synchronized TSC, there is no need to update
2822 * kvmclock on vcpu->cpu migration
2823 */
2824 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2825 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2826 if (vcpu->cpu != cpu)
2827 kvm_migrate_timers(vcpu);
e48672fa 2828 vcpu->cpu = cpu;
6b7d7e76 2829 }
c9aaa895 2830
c9aaa895 2831 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2832}
2833
0b9f6c46
PX		 2834static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2835{
2836 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2837 return;
2838
2839 vcpu->arch.st.steal.preempted = 1;
2840
2841 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
2842 &vcpu->arch.st.steal.preempted,
2843 offsetof(struct kvm_steal_time, preempted),
2844 sizeof(vcpu->arch.st.steal.preempted));
2845}
2846
313a3dc7
CO		 2847void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2848{
cc0d907c 2849 int idx;
931f261b
AA		 2850 /*
2851 * Disable page faults because we're in atomic context here.
2852 * kvm_write_guest_offset_cached() would call might_fault()
2853 * that relies on pagefault_disable() to tell if there's a
2854 * bug. NOTE: the write to guest memory may not go through if
2855 * during postcopy live migration or if there's heavy guest
2856 * paging.
2857 */
2858 pagefault_disable();
cc0d907c
AA		 2859 /*
2860 * kvm_memslots() will be called by
2861 * kvm_write_guest_offset_cached() so take the srcu lock.
2862 */
2863 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2864 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2865 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2866 pagefault_enable();
02daab21 2867 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2868 kvm_put_guest_fpu(vcpu);
4ea1636b 2869 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2870}
2871
313a3dc7
CO		 2872static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2873 struct kvm_lapic_state *s)
2874{
d62caabb
AS		 2875 if (vcpu->arch.apicv_active)
2876 kvm_x86_ops->sync_pir_to_irr(vcpu);
2877
a92e2543 2878 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2879}
2880
2881static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2882 struct kvm_lapic_state *s)
2883{
a92e2543
RK		 2884 int r;
2885
2886 r = kvm_apic_set_state(vcpu, s);
2887 if (r)
2888 return r;
cb142eb7 2889 update_cr8_intercept(vcpu);
313a3dc7
CO		 2890
2891 return 0;
2892}
2893
127a457a
MG		 2894static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2895{
2896 return (!lapic_in_kernel(vcpu) ||
2897 kvm_apic_accept_pic_intr(vcpu));
2898}
2899
782d422b
MG		 2900/*
2901 * if userspace requested an interrupt window, check that the
2902 * interrupt window is open.
2903 *
2904 * No need to exit to userspace if we already have an interrupt queued.
2905 */
2906static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2907{
2908 return kvm_arch_interrupt_allowed(vcpu) &&
2909 !kvm_cpu_has_interrupt(vcpu) &&
2910 !kvm_event_needs_reinjection(vcpu) &&
2911 kvm_cpu_accept_dm_intr(vcpu);
2912}
2913
f77bc6a4
ZX		 2914static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2915 struct kvm_interrupt *irq)
2916{
02cdb50f 2917 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2918 return -EINVAL;
1c1a9ce9
SR		 2919
2920 if (!irqchip_in_kernel(vcpu->kvm)) {
2921 kvm_queue_interrupt(vcpu, irq->irq, false);
2922 kvm_make_request(KVM_REQ_EVENT, vcpu);
2923 return 0;
2924 }
2925
2926 /*
2927 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2928 * fail for in-kernel 8259.
2929 */
2930 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2931 return -ENXIO;
f77bc6a4 2932
1c1a9ce9
SR		 2933 if (vcpu->arch.pending_external_vector != -1)
2934 return -EEXIST;
f77bc6a4 2935
1c1a9ce9 2936 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2937 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2938 return 0;
2939}
2940
c4abb7c9
JK		 2941static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2942{
c4abb7c9 2943 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2944
2945 return 0;
2946}
2947
f077825a
PB		 2948static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2949{
64d60670
PB		 2950 kvm_make_request(KVM_REQ_SMI, vcpu);
2951
f077825a
PB		 2952 return 0;
2953}
2954
b209749f
AK		 2955static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2956 struct kvm_tpr_access_ctl *tac)
2957{
2958 if (tac->flags)
2959 return -EINVAL;
2960 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2961 return 0;
2962}
2963
890ca9ae
HY		 2964static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2965 u64 mcg_cap)
2966{
2967 int r;
2968 unsigned bank_num = mcg_cap & 0xff, bank;
2969
2970 r = -EINVAL;
a9e38c3e 2971 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 2972 goto out;
c45dcc71 2973 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 2974 goto out;
2975 r = 0;
2976 vcpu->arch.mcg_cap = mcg_cap;
2977 /* Init IA32_MCG_CTL to all 1s */
2978 if (mcg_cap & MCG_CTL_P)
2979 vcpu->arch.mcg_ctl = ~(u64)0;
2980 /* Init IA32_MCi_CTL to all 1s */
2981 for (bank = 0; bank < bank_num; bank++)
2982 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 2983
2984 if (kvm_x86_ops->setup_mce)
2985 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 2986out:
2987 return r;
2988}
2989
2990static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2991 struct kvm_x86_mce *mce)
2992{
2993 u64 mcg_cap = vcpu->arch.mcg_cap;
2994 unsigned bank_num = mcg_cap & 0xff;
2995 u64 *banks = vcpu->arch.mce_banks;
2996
2997 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2998 return -EINVAL;
2999 /*
3000 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3001 * reporting is disabled
3002 */
3003 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3004 vcpu->arch.mcg_ctl != ~(u64)0)
3005 return 0;
3006 banks += 4 * mce->bank;
3007 /*
3008 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3009 * reporting is disabled for the bank
3010 */
3011 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3012 return 0;
3013 if (mce->status & MCI_STATUS_UC) {
3014 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3015 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3016 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3017 return 0;
3018 }
3019 if (banks[1] & MCI_STATUS_VAL)
3020 mce->status |= MCI_STATUS_OVER;
3021 banks[2] = mce->addr;
3022 banks[3] = mce->misc;
3023 vcpu->arch.mcg_status = mce->mcg_status;
3024 banks[1] = mce->status;
3025 kvm_queue_exception(vcpu, MC_VECTOR);
3026 } else if (!(banks[1] & MCI_STATUS_VAL)
3027 || !(banks[1] & MCI_STATUS_UC)) {
3028 if (banks[1] & MCI_STATUS_VAL)
3029 mce->status |= MCI_STATUS_OVER;
3030 banks[2] = mce->addr;
3031 banks[3] = mce->misc;
3032 banks[1] = mce->status;
3033 } else
3034 banks[1] |= MCI_STATUS_OVER;
3035 return 0;
3036}
3037
3cfc3092
JK		 3038static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3039 struct kvm_vcpu_events *events)
3040{
7460fb4a 3041 process_nmi(vcpu);
03b82a30
JK		 3042 events->exception.injected =
3043 vcpu->arch.exception.pending &&
3044 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3045 events->exception.nr = vcpu->arch.exception.nr;
3046 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3047 events->exception.pad = 0;
3cfc3092
JK		 3048 events->exception.error_code = vcpu->arch.exception.error_code;
3049
03b82a30
JK		 3050 events->interrupt.injected =
3051 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3052 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3053 events->interrupt.soft = 0;
37ccdcbe 3054 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3055
3056 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3057 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3058 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3059 events->nmi.pad = 0;
3cfc3092 3060
66450a21 3061 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3062
f077825a
PB		 3063 events->smi.smm = is_smm(vcpu);
3064 events->smi.pending = vcpu->arch.smi_pending;
3065 events->smi.smm_inside_nmi =
3066 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3067 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3068
dab4b911 3069 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3070 | KVM_VCPUEVENT_VALID_SHADOW
3071 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3072 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3073}
3074
6ef4e07e
XG		 3075static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3076
3cfc3092
JK		 3077static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3078 struct kvm_vcpu_events *events)
3079{
dab4b911 3080 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3081 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3082 | KVM_VCPUEVENT_VALID_SHADOW
3083 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3084 return -EINVAL;
3085
78e546c8
PB		 3086 if (events->exception.injected &&
3087 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3088 return -EINVAL;
3089
7460fb4a 3090 process_nmi(vcpu);
3cfc3092
JK		 3091 vcpu->arch.exception.pending = events->exception.injected;
3092 vcpu->arch.exception.nr = events->exception.nr;
3093 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3094 vcpu->arch.exception.error_code = events->exception.error_code;
3095
3096 vcpu->arch.interrupt.pending = events->interrupt.injected;
3097 vcpu->arch.interrupt.nr = events->interrupt.nr;
3098 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3099 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3100 kvm_x86_ops->set_interrupt_shadow(vcpu,
3101 events->interrupt.shadow);
3cfc3092
JK		 3102
3103 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3104 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3105 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3106 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3107
66450a21 3108 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3109 lapic_in_kernel(vcpu))
66450a21 3110 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3111
f077825a 3112 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3113 u32 hflags = vcpu->arch.hflags;
f077825a 3114 if (events->smi.smm)
6ef4e07e 3115 hflags |= HF_SMM_MASK;
f077825a 3116 else
6ef4e07e
XG		 3117 hflags &= ~HF_SMM_MASK;
3118 kvm_set_hflags(vcpu, hflags);
3119
f077825a
PB		 3120 vcpu->arch.smi_pending = events->smi.pending;
3121 if (events->smi.smm_inside_nmi)
3122 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3123 else
3124 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3125 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3126 if (events->smi.latched_init)
3127 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3128 else
3129 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3130 }
3131 }
3132
3842d135
AK		 3133 kvm_make_request(KVM_REQ_EVENT, vcpu);
3134
3cfc3092
JK		 3135 return 0;
3136}
3137
a1efbe77
JK		 3138static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3139 struct kvm_debugregs *dbgregs)
3140{
73aaf249
JK		 3141 unsigned long val;
3142
a1efbe77 3143 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3144 kvm_get_dr(vcpu, 6, &val);
73aaf249 3145 dbgregs->dr6 = val;
a1efbe77
JK		 3146 dbgregs->dr7 = vcpu->arch.dr7;
3147 dbgregs->flags = 0;
97e69aa6 3148 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3149}
3150
3151static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3152 struct kvm_debugregs *dbgregs)
3153{
3154 if (dbgregs->flags)
3155 return -EINVAL;
3156
d14bdb55
PB		 3157 if (dbgregs->dr6 & ~0xffffffffull)
3158 return -EINVAL;
3159 if (dbgregs->dr7 & ~0xffffffffull)
3160 return -EINVAL;
3161
a1efbe77 3162 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3163 kvm_update_dr0123(vcpu);
a1efbe77 3164 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3165 kvm_update_dr6(vcpu);
a1efbe77 3166 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3167 kvm_update_dr7(vcpu);
a1efbe77 3168
a1efbe77
JK		 3169 return 0;
3170}
3171
df1daba7
PB		 3172#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3173
3174static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3175{
c47ada30 3176 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3177 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3178 u64 valid;
3179
3180 /*
3181 * Copy legacy XSAVE area, to avoid complications with CPUID
3182 * leaves 0 and 1 in the loop below.
3183 */
3184 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3185
3186 /* Set XSTATE_BV */
3187 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3188
3189 /*
3190 * Copy each region from the possibly compacted offset to the
3191 * non-compacted offset.
3192 */
d91cab78 3193 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3194 while (valid) {
3195 u64 feature = valid & -valid;
3196 int index = fls64(feature) - 1;
3197 void *src = get_xsave_addr(xsave, feature);
3198
3199 if (src) {
3200 u32 size, offset, ecx, edx;
3201 cpuid_count(XSTATE_CPUID, index,
3202 &size, &offset, &ecx, &edx);
3203 memcpy(dest + offset, src, size);
3204 }
3205
3206 valid -= feature;
3207 }
3208}
3209
3210static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3211{
c47ada30 3212 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3213 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3214 u64 valid;
3215
3216 /*
3217 * Copy legacy XSAVE area, to avoid complications with CPUID
3218 * leaves 0 and 1 in the loop below.
3219 */
3220 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3221
3222 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3223 xsave->header.xfeatures = xstate_bv;
782511b0 3224 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3225 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3226
3227 /*
3228 * Copy each region from the non-compacted offset to the
3229 * possibly compacted offset.
3230 */
d91cab78 3231 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3232 while (valid) {
3233 u64 feature = valid & -valid;
3234 int index = fls64(feature) - 1;
3235 void *dest = get_xsave_addr(xsave, feature);
3236
3237 if (dest) {
3238 u32 size, offset, ecx, edx;
3239 cpuid_count(XSTATE_CPUID, index,
3240 &size, &offset, &ecx, &edx);
3241 memcpy(dest, src + offset, size);
ee4100da 3242 }
df1daba7
PB		 3243
3244 valid -= feature;
3245 }
3246}
3247
2d5b5a66
SY		 3248static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3249 struct kvm_xsave *guest_xsave)
3250{
d366bf7e 3251 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3252 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3253 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3254 } else {
2d5b5a66 3255 memcpy(guest_xsave->region,
7366ed77 3256 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3257 sizeof(struct fxregs_state));
2d5b5a66 3258 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3259 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3260 }
3261}
3262
3263static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3264 struct kvm_xsave *guest_xsave)
3265{
3266 u64 xstate_bv =
3267 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3268
d366bf7e 3269 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3270 /*
3271 * Here we allow setting states that are not present in
3272 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3273 * with old userspace.
3274 */
4ff41732 3275 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3276 return -EINVAL;
df1daba7 3277 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3278 } else {
d91cab78 3279 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3280 return -EINVAL;
7366ed77 3281 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3282 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3283 }
3284 return 0;
3285}
3286
3287static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3288 struct kvm_xcrs *guest_xcrs)
3289{
d366bf7e 3290 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3291 guest_xcrs->nr_xcrs = 0;
3292 return;
3293 }
3294
3295 guest_xcrs->nr_xcrs = 1;
3296 guest_xcrs->flags = 0;
3297 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3298 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3299}
3300
3301static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3302 struct kvm_xcrs *guest_xcrs)
3303{
3304 int i, r = 0;
3305
d366bf7e 3306 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3307 return -EINVAL;
3308
3309 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3310 return -EINVAL;
3311
3312 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3313 /* Only support XCR0 currently */
c67a04cb 3314 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3315 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3316 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3317 break;
3318 }
3319 if (r)
3320 r = -EINVAL;
3321 return r;
3322}
3323
1c0b28c2
EM		 3324/*
3325 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3326 * stopped by the hypervisor. This function will be called from the host only.
3327 * EINVAL is returned when the host attempts to set the flag for a guest that
3328 * does not support pv clocks.
3329 */
3330static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3331{
0b79459b 3332 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3333 return -EINVAL;
51d59c6b 3334 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3335 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3336 return 0;
3337}
3338
5c919412
AS		 3339static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3340 struct kvm_enable_cap *cap)
3341{
3342 if (cap->flags)
3343 return -EINVAL;
3344
3345 switch (cap->cap) {
3346 case KVM_CAP_HYPERV_SYNIC:
3347 return kvm_hv_activate_synic(vcpu);
3348 default:
3349 return -EINVAL;
3350 }
3351}
3352
313a3dc7
CO		 3353long kvm_arch_vcpu_ioctl(struct file *filp,
3354 unsigned int ioctl, unsigned long arg)
3355{
3356 struct kvm_vcpu *vcpu = filp->private_data;
3357 void __user *argp = (void __user *)arg;
3358 int r;
d1ac91d8
AK		 3359 union {
3360 struct kvm_lapic_state *lapic;
3361 struct kvm_xsave *xsave;
3362 struct kvm_xcrs *xcrs;
3363 void *buffer;
3364 } u;
3365
3366 u.buffer = NULL;
313a3dc7
CO		 3367 switch (ioctl) {
3368 case KVM_GET_LAPIC: {
2204ae3c 3369 r = -EINVAL;
bce87cce 3370 if (!lapic_in_kernel(vcpu))
2204ae3c 3371 goto out;
d1ac91d8 3372 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3373
b772ff36 3374 r = -ENOMEM;
d1ac91d8 3375 if (!u.lapic)
b772ff36 3376 goto out;
d1ac91d8 3377 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3378 if (r)
3379 goto out;
3380 r = -EFAULT;
d1ac91d8 3381 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3382 goto out;
3383 r = 0;
3384 break;
3385 }
3386 case KVM_SET_LAPIC: {
2204ae3c 3387 r = -EINVAL;
bce87cce 3388 if (!lapic_in_kernel(vcpu))
2204ae3c 3389 goto out;
ff5c2c03 3390 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3391 if (IS_ERR(u.lapic))
3392 return PTR_ERR(u.lapic);
ff5c2c03 3393
d1ac91d8 3394 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3395 break;
3396 }
f77bc6a4
ZX		 3397 case KVM_INTERRUPT: {
3398 struct kvm_interrupt irq;
3399
3400 r = -EFAULT;
3401 if (copy_from_user(&irq, argp, sizeof irq))
3402 goto out;
3403 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3404 break;
3405 }
c4abb7c9
JK		 3406 case KVM_NMI: {
3407 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3408 break;
3409 }
f077825a
PB		 3410 case KVM_SMI: {
3411 r = kvm_vcpu_ioctl_smi(vcpu);
3412 break;
3413 }
313a3dc7
CO		 3414 case KVM_SET_CPUID: {
3415 struct kvm_cpuid __user *cpuid_arg = argp;
3416 struct kvm_cpuid cpuid;
3417
3418 r = -EFAULT;
3419 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3420 goto out;
3421 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3422 break;
3423 }
07716717
DK		 3424 case KVM_SET_CPUID2: {
3425 struct kvm_cpuid2 __user *cpuid_arg = argp;
3426 struct kvm_cpuid2 cpuid;
3427
3428 r = -EFAULT;
3429 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3430 goto out;
3431 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3432 cpuid_arg->entries);
07716717
DK		 3433 break;
3434 }
3435 case KVM_GET_CPUID2: {
3436 struct kvm_cpuid2 __user *cpuid_arg = argp;
3437 struct kvm_cpuid2 cpuid;
3438
3439 r = -EFAULT;
3440 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3441 goto out;
3442 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3443 cpuid_arg->entries);
07716717
DK		 3444 if (r)
3445 goto out;
3446 r = -EFAULT;
3447 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3448 goto out;
3449 r = 0;
3450 break;
3451 }
313a3dc7 3452 case KVM_GET_MSRS:
609e36d3 3453 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3454 break;
3455 case KVM_SET_MSRS:
3456 r = msr_io(vcpu, argp, do_set_msr, 0);
3457 break;
b209749f
AK		 3458 case KVM_TPR_ACCESS_REPORTING: {
3459 struct kvm_tpr_access_ctl tac;
3460
3461 r = -EFAULT;
3462 if (copy_from_user(&tac, argp, sizeof tac))
3463 goto out;
3464 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3465 if (r)
3466 goto out;
3467 r = -EFAULT;
3468 if (copy_to_user(argp, &tac, sizeof tac))
3469 goto out;
3470 r = 0;
3471 break;
3472 };
b93463aa
AK		 3473 case KVM_SET_VAPIC_ADDR: {
3474 struct kvm_vapic_addr va;
7301d6ab 3475 int idx;
b93463aa
AK		 3476
3477 r = -EINVAL;
35754c98 3478 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3479 goto out;
3480 r = -EFAULT;
3481 if (copy_from_user(&va, argp, sizeof va))
3482 goto out;
7301d6ab 3483 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3484 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3485 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3486 break;
3487 }
890ca9ae
HY		 3488 case KVM_X86_SETUP_MCE: {
3489 u64 mcg_cap;
3490
3491 r = -EFAULT;
3492 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3493 goto out;
3494 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3495 break;
3496 }
3497 case KVM_X86_SET_MCE: {
3498 struct kvm_x86_mce mce;
3499
3500 r = -EFAULT;
3501 if (copy_from_user(&mce, argp, sizeof mce))
3502 goto out;
3503 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3504 break;
3505 }
3cfc3092
JK		 3506 case KVM_GET_VCPU_EVENTS: {
3507 struct kvm_vcpu_events events;
3508
3509 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3510
3511 r = -EFAULT;
3512 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3513 break;
3514 r = 0;
3515 break;
3516 }
3517 case KVM_SET_VCPU_EVENTS: {
3518 struct kvm_vcpu_events events;
3519
3520 r = -EFAULT;
3521 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3522 break;
3523
3524 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3525 break;
3526 }
a1efbe77
JK		 3527 case KVM_GET_DEBUGREGS: {
3528 struct kvm_debugregs dbgregs;
3529
3530 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3531
3532 r = -EFAULT;
3533 if (copy_to_user(argp, &dbgregs,
3534 sizeof(struct kvm_debugregs)))
3535 break;
3536 r = 0;
3537 break;
3538 }
3539 case KVM_SET_DEBUGREGS: {
3540 struct kvm_debugregs dbgregs;
3541
3542 r = -EFAULT;
3543 if (copy_from_user(&dbgregs, argp,
3544 sizeof(struct kvm_debugregs)))
3545 break;
3546
3547 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3548 break;
3549 }
2d5b5a66 3550 case KVM_GET_XSAVE: {
d1ac91d8 3551 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3552 r = -ENOMEM;
d1ac91d8 3553 if (!u.xsave)
2d5b5a66
SY		 3554 break;
3555
d1ac91d8 3556 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3557
3558 r = -EFAULT;
d1ac91d8 3559 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3560 break;
3561 r = 0;
3562 break;
3563 }
3564 case KVM_SET_XSAVE: {
ff5c2c03 3565 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3566 if (IS_ERR(u.xsave))
3567 return PTR_ERR(u.xsave);
2d5b5a66 3568
d1ac91d8 3569 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3570 break;
3571 }
3572 case KVM_GET_XCRS: {
d1ac91d8 3573 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3574 r = -ENOMEM;
d1ac91d8 3575 if (!u.xcrs)
2d5b5a66
SY		 3576 break;
3577
d1ac91d8 3578 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3579
3580 r = -EFAULT;
d1ac91d8 3581 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3582 sizeof(struct kvm_xcrs)))
3583 break;
3584 r = 0;
3585 break;
3586 }
3587 case KVM_SET_XCRS: {
ff5c2c03 3588 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3589 if (IS_ERR(u.xcrs))
3590 return PTR_ERR(u.xcrs);
2d5b5a66 3591
d1ac91d8 3592 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3593 break;
3594 }
92a1f12d
JR		 3595 case KVM_SET_TSC_KHZ: {
3596 u32 user_tsc_khz;
3597
3598 r = -EINVAL;
92a1f12d
JR		 3599 user_tsc_khz = (u32)arg;
3600
3601 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3602 goto out;
3603
cc578287
ZA		 3604 if (user_tsc_khz == 0)
3605 user_tsc_khz = tsc_khz;
3606
381d585c
HZ		 3607 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3608 r = 0;
92a1f12d 3609
92a1f12d
JR		 3610 goto out;
3611 }
3612 case KVM_GET_TSC_KHZ: {
cc578287 3613 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3614 goto out;
3615 }
1c0b28c2
EM		 3616 case KVM_KVMCLOCK_CTRL: {
3617 r = kvm_set_guest_paused(vcpu);
3618 goto out;
3619 }
5c919412
AS		 3620 case KVM_ENABLE_CAP: {
3621 struct kvm_enable_cap cap;
3622
3623 r = -EFAULT;
3624 if (copy_from_user(&cap, argp, sizeof(cap)))
3625 goto out;
3626 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3627 break;
3628 }
313a3dc7
CO		 3629 default:
3630 r = -EINVAL;
3631 }
3632out:
d1ac91d8 3633 kfree(u.buffer);
313a3dc7
CO		 3634 return r;
3635}
3636
5b1c1493
CO		 3637int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3638{
3639 return VM_FAULT_SIGBUS;
3640}
3641
1fe779f8
CO		 3642static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3643{
3644 int ret;
3645
3646 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3647 return -EINVAL;
1fe779f8
CO		 3648 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3649 return ret;
3650}
3651
b927a3ce
SY		 3652static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3653 u64 ident_addr)
3654{
3655 kvm->arch.ept_identity_map_addr = ident_addr;
3656 return 0;
3657}
3658
1fe779f8
CO		 3659static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3660 u32 kvm_nr_mmu_pages)
3661{
3662 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3663 return -EINVAL;
3664
79fac95e 3665 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3666
3667 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3668 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3669
79fac95e 3670 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3671 return 0;
3672}
3673
3674static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3675{
39de71ec 3676 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3677}
3678
1fe779f8
CO		 3679static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3680{
3681 int r;
3682
3683 r = 0;
3684 switch (chip->chip_id) {
3685 case KVM_IRQCHIP_PIC_MASTER:
3686 memcpy(&chip->chip.pic,
3687 &pic_irqchip(kvm)->pics[0],
3688 sizeof(struct kvm_pic_state));
3689 break;
3690 case KVM_IRQCHIP_PIC_SLAVE:
3691 memcpy(&chip->chip.pic,
3692 &pic_irqchip(kvm)->pics[1],
3693 sizeof(struct kvm_pic_state));
3694 break;
3695 case KVM_IRQCHIP_IOAPIC:
eba0226b 3696 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3697 break;
3698 default:
3699 r = -EINVAL;
3700 break;
3701 }
3702 return r;
3703}
3704
3705static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3706{
3707 int r;
3708
3709 r = 0;
3710 switch (chip->chip_id) {
3711 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3712 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3713 memcpy(&pic_irqchip(kvm)->pics[0],
3714 &chip->chip.pic,
3715 sizeof(struct kvm_pic_state));
f4f51050 3716 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3717 break;
3718 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3719 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3720 memcpy(&pic_irqchip(kvm)->pics[1],
3721 &chip->chip.pic,
3722 sizeof(struct kvm_pic_state));
f4f51050 3723 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3724 break;
3725 case KVM_IRQCHIP_IOAPIC:
eba0226b 3726 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3727 break;
3728 default:
3729 r = -EINVAL;
3730 break;
3731 }
3732 kvm_pic_update_irq(pic_irqchip(kvm));
3733 return r;
3734}
3735
e0f63cb9
SY		 3736static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3737{
34f3941c
RK		 3738 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3739
3740 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3741
3742 mutex_lock(&kps->lock);
3743 memcpy(ps, &kps->channels, sizeof(*ps));
3744 mutex_unlock(&kps->lock);
2da29bcc 3745 return 0;
e0f63cb9
SY		 3746}
3747
3748static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3749{
0185604c 3750 int i;
09edea72
RK		 3751 struct kvm_pit *pit = kvm->arch.vpit;
3752
3753 mutex_lock(&pit->pit_state.lock);
34f3941c 3754 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3755 for (i = 0; i < 3; i++)
09edea72
RK		 3756 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3757 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3758 return 0;
e9f42757
BK		 3759}
3760
3761static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3762{
e9f42757
BK		 3763 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3764 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3765 sizeof(ps->channels));
3766 ps->flags = kvm->arch.vpit->pit_state.flags;
3767 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3768 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3769 return 0;
e9f42757
BK		 3770}
3771
3772static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3773{
2da29bcc 3774 int start = 0;
0185604c 3775 int i;
e9f42757 3776 u32 prev_legacy, cur_legacy;
09edea72
RK		 3777 struct kvm_pit *pit = kvm->arch.vpit;
3778
3779 mutex_lock(&pit->pit_state.lock);
3780 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3781 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3782 if (!prev_legacy && cur_legacy)
3783 start = 1;
09edea72
RK		 3784 memcpy(&pit->pit_state.channels, &ps->channels,
3785 sizeof(pit->pit_state.channels));
3786 pit->pit_state.flags = ps->flags;
0185604c 3787 for (i = 0; i < 3; i++)
09edea72 3788 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3789 start && i == 0);
09edea72 3790 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3791 return 0;
e0f63cb9
SY		 3792}
3793
52d939a0
MT		 3794static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3795 struct kvm_reinject_control *control)
3796{
71474e2f
RK		 3797 struct kvm_pit *pit = kvm->arch.vpit;
3798
3799 if (!pit)
52d939a0 3800 return -ENXIO;
b39c90b6 3801
71474e2f
RK		 3802 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3803 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3804 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3805 */
3806 mutex_lock(&pit->pit_state.lock);
3807 kvm_pit_set_reinject(pit, control->pit_reinject);
3808 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3809
52d939a0
MT		 3810 return 0;
3811}
3812
95d4c16c 3813/**
60c34612
TY		 3814 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3815 * @kvm: kvm instance
3816 * @log: slot id and address to which we copy the log
95d4c16c 3817 *
e108ff2f
PB		 3818 * Steps 1-4 below provide general overview of dirty page logging. See
3819 * kvm_get_dirty_log_protect() function description for additional details.
3820 *
3821 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3822 * always flush the TLB (step 4) even if previous step failed and the dirty
3823 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3824 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3825 * writes will be marked dirty for next log read.
95d4c16c 3826 *
60c34612
TY		 3827 * 1. Take a snapshot of the bit and clear it if needed.
3828 * 2. Write protect the corresponding page.
e108ff2f
PB		 3829 * 3. Copy the snapshot to the userspace.
3830 * 4. Flush TLB's if needed.
5bb064dc 3831 */
60c34612 3832int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3833{
60c34612 3834 bool is_dirty = false;
e108ff2f 3835 int r;
5bb064dc 3836
79fac95e 3837 mutex_lock(&kvm->slots_lock);
5bb064dc 3838
88178fd4
KH		 3839 /*
3840 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3841 */
3842 if (kvm_x86_ops->flush_log_dirty)
3843 kvm_x86_ops->flush_log_dirty(kvm);
3844
e108ff2f 3845 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3846
3847 /*
3848 * All the TLBs can be flushed out of mmu lock, see the comments in
3849 * kvm_mmu_slot_remove_write_access().
3850 */
e108ff2f 3851 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3852 if (is_dirty)
3853 kvm_flush_remote_tlbs(kvm);
3854
79fac95e 3855 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3856 return r;
3857}
3858
aa2fbe6d
YZ		 3859int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3860 bool line_status)
23d43cf9
CD		 3861{
3862 if (!irqchip_in_kernel(kvm))
3863 return -ENXIO;
3864
3865 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3866 irq_event->irq, irq_event->level,
3867 line_status);
23d43cf9
CD		 3868 return 0;
3869}
3870
90de4a18
NA		 3871static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3872 struct kvm_enable_cap *cap)
3873{
3874 int r;
3875
3876 if (cap->flags)
3877 return -EINVAL;
3878
3879 switch (cap->cap) {
3880 case KVM_CAP_DISABLE_QUIRKS:
3881 kvm->arch.disabled_quirks = cap->args[0];
3882 r = 0;
3883 break;
49df6397
SR		 3884 case KVM_CAP_SPLIT_IRQCHIP: {
3885 mutex_lock(&kvm->lock);
b053b2ae
SR		 3886 r = -EINVAL;
3887 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3888 goto split_irqchip_unlock;
49df6397
SR		 3889 r = -EEXIST;
3890 if (irqchip_in_kernel(kvm))
3891 goto split_irqchip_unlock;
557abc40 3892 if (kvm->created_vcpus)
49df6397
SR		 3893 goto split_irqchip_unlock;
3894 r = kvm_setup_empty_irq_routing(kvm);
3895 if (r)
3896 goto split_irqchip_unlock;
3897 /* Pairs with irqchip_in_kernel. */
3898 smp_wmb();
49776faf 3899 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3900 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3901 r = 0;
3902split_irqchip_unlock:
3903 mutex_unlock(&kvm->lock);
3904 break;
3905 }
37131313
RK		 3906 case KVM_CAP_X2APIC_API:
3907 r = -EINVAL;
3908 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3909 break;
3910
3911 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3912 kvm->arch.x2apic_format = true;
c519265f
RK		 3913 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3914 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3915
3916 r = 0;
3917 break;
90de4a18
NA		 3918 default:
3919 r = -EINVAL;
3920 break;
3921 }
3922 return r;
3923}
3924
1fe779f8
CO		 3925long kvm_arch_vm_ioctl(struct file *filp,
3926 unsigned int ioctl, unsigned long arg)
3927{
3928 struct kvm *kvm = filp->private_data;
3929 void __user *argp = (void __user *)arg;
367e1319 3930 int r = -ENOTTY;
f0d66275
DH		 3931 /*
3932 * This union makes it completely explicit to gcc-3.x
3933 * that these two variables' stack usage should be
3934 * combined, not added together.
3935 */
3936 union {
3937 struct kvm_pit_state ps;
e9f42757 3938 struct kvm_pit_state2 ps2;
c5ff41ce 3939 struct kvm_pit_config pit_config;
f0d66275 3940 } u;
1fe779f8
CO		 3941
3942 switch (ioctl) {
3943 case KVM_SET_TSS_ADDR:
3944 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3945 break;
b927a3ce
SY		 3946 case KVM_SET_IDENTITY_MAP_ADDR: {
3947 u64 ident_addr;
3948
3949 r = -EFAULT;
3950 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3951 goto out;
3952 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3953 break;
3954 }
1fe779f8
CO		 3955 case KVM_SET_NR_MMU_PAGES:
3956 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3957 break;
3958 case KVM_GET_NR_MMU_PAGES:
3959 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3960 break;
3ddea128 3961 case KVM_CREATE_IRQCHIP: {
3ddea128 3962 mutex_lock(&kvm->lock);
09941366 3963
3ddea128 3964 r = -EEXIST;
35e6eaa3 3965 if (irqchip_in_kernel(kvm))
3ddea128 3966 goto create_irqchip_unlock;
09941366 3967
3e515705 3968 r = -EINVAL;
557abc40 3969 if (kvm->created_vcpus)
3e515705 3970 goto create_irqchip_unlock;
09941366
RK		 3971
3972 r = kvm_pic_init(kvm);
3973 if (r)
3ddea128 3974 goto create_irqchip_unlock;
09941366
RK		 3975
3976 r = kvm_ioapic_init(kvm);
3977 if (r) {
3978 mutex_lock(&kvm->slots_lock);
3979 kvm_pic_destroy(kvm);
3980 mutex_unlock(&kvm->slots_lock);
3981 goto create_irqchip_unlock;
3982 }
3983
399ec807
AK		 3984 r = kvm_setup_default_irq_routing(kvm);
3985 if (r) {
175504cd 3986 mutex_lock(&kvm->slots_lock);
3ddea128 3987 mutex_lock(&kvm->irq_lock);
72bb2fcd 3988 kvm_ioapic_destroy(kvm);
09941366 3989 kvm_pic_destroy(kvm);
3ddea128 3990 mutex_unlock(&kvm->irq_lock);
175504cd 3991 mutex_unlock(&kvm->slots_lock);
71ba994c 3992 goto create_irqchip_unlock;
399ec807 3993 }
49776faf 3994 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 3995 smp_wmb();
49776faf 3996 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 3997 create_irqchip_unlock:
3998 mutex_unlock(&kvm->lock);
1fe779f8 3999 break;
3ddea128 4000 }
7837699f 4001 case KVM_CREATE_PIT:
c5ff41ce
JK		 4002 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4003 goto create_pit;
4004 case KVM_CREATE_PIT2:
4005 r = -EFAULT;
4006 if (copy_from_user(&u.pit_config, argp,
4007 sizeof(struct kvm_pit_config)))
4008 goto out;
4009 create_pit:
250715a6 4010 mutex_lock(&kvm->lock);
269e05e4
AK		 4011 r = -EEXIST;
4012 if (kvm->arch.vpit)
4013 goto create_pit_unlock;
7837699f 4014 r = -ENOMEM;
c5ff41ce 4015 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4016 if (kvm->arch.vpit)
4017 r = 0;
269e05e4 4018 create_pit_unlock:
250715a6 4019 mutex_unlock(&kvm->lock);
7837699f 4020 break;
1fe779f8
CO		 4021 case KVM_GET_IRQCHIP: {
4022 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4023 struct kvm_irqchip *chip;
1fe779f8 4024
ff5c2c03
SL		 4025 chip = memdup_user(argp, sizeof(*chip));
4026 if (IS_ERR(chip)) {
4027 r = PTR_ERR(chip);
1fe779f8 4028 goto out;
ff5c2c03
SL		 4029 }
4030
1fe779f8 4031 r = -ENXIO;
826da321 4032 if (!irqchip_kernel(kvm))
f0d66275
DH		 4033 goto get_irqchip_out;
4034 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4035 if (r)
f0d66275 4036 goto get_irqchip_out;
1fe779f8 4037 r = -EFAULT;
f0d66275
DH		 4038 if (copy_to_user(argp, chip, sizeof *chip))
4039 goto get_irqchip_out;
1fe779f8 4040 r = 0;
f0d66275
DH		 4041 get_irqchip_out:
4042 kfree(chip);
1fe779f8
CO		 4043 break;
4044 }
4045 case KVM_SET_IRQCHIP: {
4046 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4047 struct kvm_irqchip *chip;
1fe779f8 4048
ff5c2c03
SL		 4049 chip = memdup_user(argp, sizeof(*chip));
4050 if (IS_ERR(chip)) {
4051 r = PTR_ERR(chip);
1fe779f8 4052 goto out;
ff5c2c03
SL		 4053 }
4054
1fe779f8 4055 r = -ENXIO;
826da321 4056 if (!irqchip_kernel(kvm))
f0d66275
DH		 4057 goto set_irqchip_out;
4058 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4059 if (r)
f0d66275 4060 goto set_irqchip_out;
1fe779f8 4061 r = 0;
f0d66275
DH		 4062 set_irqchip_out:
4063 kfree(chip);
1fe779f8
CO		 4064 break;
4065 }
e0f63cb9 4066 case KVM_GET_PIT: {
e0f63cb9 4067 r = -EFAULT;
f0d66275 4068 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4069 goto out;
4070 r = -ENXIO;
4071 if (!kvm->arch.vpit)
4072 goto out;
f0d66275 4073 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4074 if (r)
4075 goto out;
4076 r = -EFAULT;
f0d66275 4077 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4078 goto out;
4079 r = 0;
4080 break;
4081 }
4082 case KVM_SET_PIT: {
e0f63cb9 4083 r = -EFAULT;
f0d66275 4084 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4085 goto out;
4086 r = -ENXIO;
4087 if (!kvm->arch.vpit)
4088 goto out;
f0d66275 4089 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4090 break;
4091 }
e9f42757
BK		 4092 case KVM_GET_PIT2: {
4093 r = -ENXIO;
4094 if (!kvm->arch.vpit)
4095 goto out;
4096 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4097 if (r)
4098 goto out;
4099 r = -EFAULT;
4100 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4101 goto out;
4102 r = 0;
4103 break;
4104 }
4105 case KVM_SET_PIT2: {
4106 r = -EFAULT;
4107 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4108 goto out;
4109 r = -ENXIO;
4110 if (!kvm->arch.vpit)
4111 goto out;
4112 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4113 break;
4114 }
52d939a0
MT		 4115 case KVM_REINJECT_CONTROL: {
4116 struct kvm_reinject_control control;
4117 r = -EFAULT;
4118 if (copy_from_user(&control, argp, sizeof(control)))
4119 goto out;
4120 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4121 break;
4122 }
d71ba788
PB		 4123 case KVM_SET_BOOT_CPU_ID:
4124 r = 0;
4125 mutex_lock(&kvm->lock);
557abc40 4126 if (kvm->created_vcpus)
d71ba788
PB		 4127 r = -EBUSY;
4128 else
4129 kvm->arch.bsp_vcpu_id = arg;
4130 mutex_unlock(&kvm->lock);
4131 break;
ffde22ac
ES		 4132 case KVM_XEN_HVM_CONFIG: {
4133 r = -EFAULT;
4134 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4135 sizeof(struct kvm_xen_hvm_config)))
4136 goto out;
4137 r = -EINVAL;
4138 if (kvm->arch.xen_hvm_config.flags)
4139 goto out;
4140 r = 0;
4141 break;
4142 }
afbcf7ab 4143 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4144 struct kvm_clock_data user_ns;
4145 u64 now_ns;
afbcf7ab
GC		 4146
4147 r = -EFAULT;
4148 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4149 goto out;
4150
4151 r = -EINVAL;
4152 if (user_ns.flags)
4153 goto out;
4154
4155 r = 0;
395c6b0a 4156 local_irq_disable();
108b249c
PB		 4157 now_ns = __get_kvmclock_ns(kvm);
4158 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
395c6b0a 4159 local_irq_enable();
2e762ff7 4160 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4161 break;
4162 }
4163 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4164 struct kvm_clock_data user_ns;
4165 u64 now_ns;
4166
e3fd9a93
PB		 4167 local_irq_disable();
4168 now_ns = __get_kvmclock_ns(kvm);
108b249c 4169 user_ns.clock = now_ns;
e3fd9a93
PB		 4170 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4171 local_irq_enable();
97e69aa6 4172 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4173
4174 r = -EFAULT;
4175 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4176 goto out;
4177 r = 0;
4178 break;
4179 }
90de4a18
NA		 4180 case KVM_ENABLE_CAP: {
4181 struct kvm_enable_cap cap;
afbcf7ab 4182
90de4a18
NA		 4183 r = -EFAULT;
4184 if (copy_from_user(&cap, argp, sizeof(cap)))
4185 goto out;
4186 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4187 break;
4188 }
1fe779f8 4189 default:
c274e03a 4190 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4191 }
4192out:
4193 return r;
4194}
4195
a16b043c 4196static void kvm_init_msr_list(void)
043405e1
CO		 4197{
4198 u32 dummy[2];
4199 unsigned i, j;
4200
62ef68bb 4201 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4202 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4203 continue;
93c4adc7
PB		 4204
4205 /*
4206 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4207 * to the guests in some cases.
93c4adc7
PB		 4208 */
4209 switch (msrs_to_save[i]) {
4210 case MSR_IA32_BNDCFGS:
4211 if (!kvm_x86_ops->mpx_supported())
4212 continue;
4213 break;
9dbe6cf9
PB		 4214 case MSR_TSC_AUX:
4215 if (!kvm_x86_ops->rdtscp_supported())
4216 continue;
4217 break;
93c4adc7
PB		 4218 default:
4219 break;
4220 }
4221
043405e1
CO		 4222 if (j < i)
4223 msrs_to_save[j] = msrs_to_save[i];
4224 j++;
4225 }
4226 num_msrs_to_save = j;
62ef68bb
PB		 4227
4228 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4229 switch (emulated_msrs[i]) {
6d396b55
PB		 4230 case MSR_IA32_SMBASE:
4231 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4232 continue;
4233 break;
62ef68bb
PB		 4234 default:
4235 break;
4236 }
4237
4238 if (j < i)
4239 emulated_msrs[j] = emulated_msrs[i];
4240 j++;
4241 }
4242 num_emulated_msrs = j;
043405e1
CO		 4243}
4244
bda9020e
MT		 4245static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4246 const void *v)
bbd9b64e 4247{
70252a10
AK		 4248 int handled = 0;
4249 int n;
4250
4251 do {
4252 n = min(len, 8);
bce87cce 4253 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4254 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4255 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4256 break;
4257 handled += n;
4258 addr += n;
4259 len -= n;
4260 v += n;
4261 } while (len);
bbd9b64e 4262
70252a10 4263 return handled;
bbd9b64e
CO		 4264}
4265
bda9020e 4266static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4267{
70252a10
AK		 4268 int handled = 0;
4269 int n;
4270
4271 do {
4272 n = min(len, 8);
bce87cce 4273 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4274 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4275 addr, n, v))
4276 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4277 break;
4278 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4279 handled += n;
4280 addr += n;
4281 len -= n;
4282 v += n;
4283 } while (len);
bbd9b64e 4284
70252a10 4285 return handled;
bbd9b64e
CO		 4286}
4287
2dafc6c2
GN		 4288static void kvm_set_segment(struct kvm_vcpu *vcpu,
4289 struct kvm_segment *var, int seg)
4290{
4291 kvm_x86_ops->set_segment(vcpu, var, seg);
4292}
4293
4294void kvm_get_segment(struct kvm_vcpu *vcpu,
4295 struct kvm_segment *var, int seg)
4296{
4297 kvm_x86_ops->get_segment(vcpu, var, seg);
4298}
4299
54987b7a
PB		 4300gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4301 struct x86_exception *exception)
02f59dc9
JR		 4302{
4303 gpa_t t_gpa;
02f59dc9
JR		 4304
4305 BUG_ON(!mmu_is_nested(vcpu));
4306
4307 /* NPT walks are always user-walks */
4308 access |= PFERR_USER_MASK;
54987b7a 4309 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4310
4311 return t_gpa;
4312}
4313
ab9ae313
AK		 4314gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4315 struct x86_exception *exception)
1871c602
GN		 4316{
4317 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4318 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4319}
4320
ab9ae313
AK		 4321 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4322 struct x86_exception *exception)
1871c602
GN		 4323{
4324 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4325 access |= PFERR_FETCH_MASK;
ab9ae313 4326 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4327}
4328
ab9ae313
AK		 4329gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4330 struct x86_exception *exception)
1871c602
GN		 4331{
4332 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4333 access |= PFERR_WRITE_MASK;
ab9ae313 4334 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4335}
4336
4337/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4338gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4339 struct x86_exception *exception)
1871c602 4340{
ab9ae313 4341 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4342}
4343
4344static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4345 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4346 struct x86_exception *exception)
bbd9b64e
CO		 4347{
4348 void *data = val;
10589a46 4349 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4350
4351 while (bytes) {
14dfe855 4352 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4353 exception);
bbd9b64e 4354 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4355 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4356 int ret;
4357
bcc55cba 4358 if (gpa == UNMAPPED_GVA)
ab9ae313 4359 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4360 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4361 offset, toread);
10589a46 4362 if (ret < 0) {
c3cd7ffa 4363 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4364 goto out;
4365 }
bbd9b64e 4366
77c2002e
IE		 4367 bytes -= toread;
4368 data += toread;
4369 addr += toread;
bbd9b64e 4370 }
10589a46 4371out:
10589a46 4372 return r;
bbd9b64e 4373}
77c2002e 4374
1871c602 4375/* used for instruction fetching */
0f65dd70
AK		 4376static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4377 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4378 struct x86_exception *exception)
1871c602 4379{
0f65dd70 4380 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4381 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4382 unsigned offset;
4383 int ret;
0f65dd70 4384
44583cba
PB		 4385 /* Inline kvm_read_guest_virt_helper for speed. */
4386 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4387 exception);
4388 if (unlikely(gpa == UNMAPPED_GVA))
4389 return X86EMUL_PROPAGATE_FAULT;
4390
4391 offset = addr & (PAGE_SIZE-1);
4392 if (WARN_ON(offset + bytes > PAGE_SIZE))
4393 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4394 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4395 offset, bytes);
44583cba
PB		 4396 if (unlikely(ret < 0))
4397 return X86EMUL_IO_NEEDED;
4398
4399 return X86EMUL_CONTINUE;
1871c602
GN		 4400}
4401
064aea77 4402int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4403 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4404 struct x86_exception *exception)
1871c602 4405{
0f65dd70 4406 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4407 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4408
1871c602 4409 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4410 exception);
1871c602 4411}
064aea77 4412EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4413
0f65dd70
AK		 4414static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4415 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4416 struct x86_exception *exception)
1871c602 4417{
0f65dd70 4418 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4419 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4420}
4421
7a036a6f
RK		 4422static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4423 unsigned long addr, void *val, unsigned int bytes)
4424{
4425 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4426 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4427
4428 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4429}
4430
6a4d7550 4431int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4432 gva_t addr, void *val,
2dafc6c2 4433 unsigned int bytes,
bcc55cba 4434 struct x86_exception *exception)
77c2002e 4435{
0f65dd70 4436 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4437 void *data = val;
4438 int r = X86EMUL_CONTINUE;
4439
4440 while (bytes) {
14dfe855
JR		 4441 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4442 PFERR_WRITE_MASK,
ab9ae313 4443 exception);
77c2002e
IE		 4444 unsigned offset = addr & (PAGE_SIZE-1);
4445 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4446 int ret;
4447
bcc55cba 4448 if (gpa == UNMAPPED_GVA)
ab9ae313 4449 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4450 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4451 if (ret < 0) {
c3cd7ffa 4452 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4453 goto out;
4454 }
4455
4456 bytes -= towrite;
4457 data += towrite;
4458 addr += towrite;
4459 }
4460out:
4461 return r;
4462}
6a4d7550 4463EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4464
af7cc7d1
XG		 4465static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4466 gpa_t *gpa, struct x86_exception *exception,
4467 bool write)
4468{
97d64b78
AK		 4469 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4470 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4471
be94f6b7
HH		 4472 /*
4473 * currently PKRU is only applied to ept enabled guest so
4474 * there is no pkey in EPT page table for L1 guest or EPT
4475 * shadow page table for L2 guest.
4476 */
97d64b78 4477 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4478 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4479 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4480 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4481 (gva & (PAGE_SIZE - 1));
4f022648 4482 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4483 return 1;
4484 }
4485
af7cc7d1
XG		 4486 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4487
4488 if (*gpa == UNMAPPED_GVA)
4489 return -1;
4490
4491 /* For APIC access vmexit */
4492 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4493 return 1;
4494
4f022648
XG		 4495 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4496 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4497 return 1;
4f022648 4498 }
bebb106a 4499
af7cc7d1
XG		 4500 return 0;
4501}
4502
3200f405 4503int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4504 const void *val, int bytes)
bbd9b64e
CO		 4505{
4506 int ret;
4507
54bf36aa 4508 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4509 if (ret < 0)
bbd9b64e 4510 return 0;
0eb05bf2 4511 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4512 return 1;
4513}
4514
77d197b2
XG		 4515struct read_write_emulator_ops {
4516 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4517 int bytes);
4518 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4519 void *val, int bytes);
4520 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4521 int bytes, void *val);
4522 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4523 void *val, int bytes);
4524 bool write;
4525};
4526
4527static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4528{
4529 if (vcpu->mmio_read_completed) {
77d197b2 4530 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4531 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4532 vcpu->mmio_read_completed = 0;
4533 return 1;
4534 }
4535
4536 return 0;
4537}
4538
4539static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4540 void *val, int bytes)
4541{
54bf36aa 4542 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4543}
4544
4545static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4546 void *val, int bytes)
4547{
4548 return emulator_write_phys(vcpu, gpa, val, bytes);
4549}
4550
4551static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4552{
4553 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4554 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4555}
4556
4557static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4558 void *val, int bytes)
4559{
4560 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4561 return X86EMUL_IO_NEEDED;
4562}
4563
4564static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4565 void *val, int bytes)
4566{
f78146b0
AK		 4567 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4568
87da7e66 4569 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4570 return X86EMUL_CONTINUE;
4571}
4572
0fbe9b0b 4573static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4574 .read_write_prepare = read_prepare,
4575 .read_write_emulate = read_emulate,
4576 .read_write_mmio = vcpu_mmio_read,
4577 .read_write_exit_mmio = read_exit_mmio,
4578};
4579
0fbe9b0b 4580static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4581 .read_write_emulate = write_emulate,
4582 .read_write_mmio = write_mmio,
4583 .read_write_exit_mmio = write_exit_mmio,
4584 .write = true,
4585};
4586
22388a3c
XG		 4587static int emulator_read_write_onepage(unsigned long addr, void *val,
4588 unsigned int bytes,
4589 struct x86_exception *exception,
4590 struct kvm_vcpu *vcpu,
0fbe9b0b 4591 const struct read_write_emulator_ops *ops)
bbd9b64e 4592{
af7cc7d1
XG		 4593 gpa_t gpa;
4594 int handled, ret;
22388a3c 4595 bool write = ops->write;
f78146b0 4596 struct kvm_mmio_fragment *frag;
10589a46 4597
22388a3c 4598 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4599
af7cc7d1 4600 if (ret < 0)
bbd9b64e 4601 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4602
4603 /* For APIC access vmexit */
af7cc7d1 4604 if (ret)
bbd9b64e
CO		 4605 goto mmio;
4606
22388a3c 4607 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4608 return X86EMUL_CONTINUE;
4609
4610mmio:
4611 /*
4612 * Is this MMIO handled locally?
4613 */
22388a3c 4614 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4615 if (handled == bytes)
bbd9b64e 4616 return X86EMUL_CONTINUE;
bbd9b64e 4617
70252a10
AK		 4618 gpa += handled;
4619 bytes -= handled;
4620 val += handled;
4621
87da7e66
XG		 4622 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4623 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4624 frag->gpa = gpa;
4625 frag->data = val;
4626 frag->len = bytes;
f78146b0 4627 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4628}
4629
52eb5a6d
XL		 4630static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4631 unsigned long addr,
22388a3c
XG		 4632 void *val, unsigned int bytes,
4633 struct x86_exception *exception,
0fbe9b0b 4634 const struct read_write_emulator_ops *ops)
bbd9b64e 4635{
0f65dd70 4636 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4637 gpa_t gpa;
4638 int rc;
4639
4640 if (ops->read_write_prepare &&
4641 ops->read_write_prepare(vcpu, val, bytes))
4642 return X86EMUL_CONTINUE;
4643
4644 vcpu->mmio_nr_fragments = 0;
0f65dd70 4645
bbd9b64e
CO		 4646 /* Crossing a page boundary? */
4647 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4648 int now;
bbd9b64e
CO		 4649
4650 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4651 rc = emulator_read_write_onepage(addr, val, now, exception,
4652 vcpu, ops);
4653
bbd9b64e
CO		 4654 if (rc != X86EMUL_CONTINUE)
4655 return rc;
4656 addr += now;
bac15531
NA		 4657 if (ctxt->mode != X86EMUL_MODE_PROT64)
4658 addr = (u32)addr;
bbd9b64e
CO		 4659 val += now;
4660 bytes -= now;
4661 }
22388a3c 4662
f78146b0
AK		 4663 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4664 vcpu, ops);
4665 if (rc != X86EMUL_CONTINUE)
4666 return rc;
4667
4668 if (!vcpu->mmio_nr_fragments)
4669 return rc;
4670
4671 gpa = vcpu->mmio_fragments[0].gpa;
4672
4673 vcpu->mmio_needed = 1;
4674 vcpu->mmio_cur_fragment = 0;
4675
87da7e66 4676 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4677 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4678 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4679 vcpu->run->mmio.phys_addr = gpa;
4680
4681 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4682}
4683
4684static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4685 unsigned long addr,
4686 void *val,
4687 unsigned int bytes,
4688 struct x86_exception *exception)
4689{
4690 return emulator_read_write(ctxt, addr, val, bytes,
4691 exception, &read_emultor);
4692}
4693
52eb5a6d 4694static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4695 unsigned long addr,
4696 const void *val,
4697 unsigned int bytes,
4698 struct x86_exception *exception)
4699{
4700 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4701 exception, &write_emultor);
bbd9b64e 4702}
bbd9b64e 4703
daea3e73
AK		 4704#define CMPXCHG_TYPE(t, ptr, old, new) \
4705 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4706
4707#ifdef CONFIG_X86_64
4708# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4709#else
4710# define CMPXCHG64(ptr, old, new) \
9749a6c0 4711 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4712#endif
4713
0f65dd70
AK		 4714static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4715 unsigned long addr,
bbd9b64e
CO		 4716 const void *old,
4717 const void *new,
4718 unsigned int bytes,
0f65dd70 4719 struct x86_exception *exception)
bbd9b64e 4720{
0f65dd70 4721 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4722 gpa_t gpa;
4723 struct page *page;
4724 char *kaddr;
4725 bool exchanged;
2bacc55c 4726
daea3e73
AK		 4727 /* guests cmpxchg8b have to be emulated atomically */
4728 if (bytes > 8 || (bytes & (bytes - 1)))
4729 goto emul_write;
10589a46 4730
daea3e73 4731 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4732
daea3e73
AK		 4733 if (gpa == UNMAPPED_GVA ||
4734 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4735 goto emul_write;
2bacc55c 4736
daea3e73
AK		 4737 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4738 goto emul_write;
72dc67a6 4739
54bf36aa 4740 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4741 if (is_error_page(page))
c19b8bd6 4742 goto emul_write;
72dc67a6 4743
8fd75e12 4744 kaddr = kmap_atomic(page);
daea3e73
AK		 4745 kaddr += offset_in_page(gpa);
4746 switch (bytes) {
4747 case 1:
4748 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4749 break;
4750 case 2:
4751 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4752 break;
4753 case 4:
4754 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4755 break;
4756 case 8:
4757 exchanged = CMPXCHG64(kaddr, old, new);
4758 break;
4759 default:
4760 BUG();
2bacc55c 4761 }
8fd75e12 4762 kunmap_atomic(kaddr);
daea3e73
AK		 4763 kvm_release_page_dirty(page);
4764
4765 if (!exchanged)
4766 return X86EMUL_CMPXCHG_FAILED;
4767
54bf36aa 4768 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4769 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4770
4771 return X86EMUL_CONTINUE;
4a5f48f6 4772
3200f405 4773emul_write:
daea3e73 4774 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4775
0f65dd70 4776 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4777}
4778
cf8f70bf
GN		 4779static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4780{
4781 /* TODO: String I/O for in kernel device */
4782 int r;
4783
4784 if (vcpu->arch.pio.in)
e32edf4f 4785 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4786 vcpu->arch.pio.size, pd);
4787 else
e32edf4f 4788 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4789 vcpu->arch.pio.port, vcpu->arch.pio.size,
4790 pd);
4791 return r;
4792}
4793
6f6fbe98
XG		 4794static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4795 unsigned short port, void *val,
4796 unsigned int count, bool in)
cf8f70bf 4797{
cf8f70bf 4798 vcpu->arch.pio.port = port;
6f6fbe98 4799 vcpu->arch.pio.in = in;
7972995b 4800 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4801 vcpu->arch.pio.size = size;
4802
4803 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4804 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4805 return 1;
4806 }
4807
4808 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4809 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4810 vcpu->run->io.size = size;
4811 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4812 vcpu->run->io.count = count;
4813 vcpu->run->io.port = port;
4814
4815 return 0;
4816}
4817
6f6fbe98
XG		 4818static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4819 int size, unsigned short port, void *val,
4820 unsigned int count)
cf8f70bf 4821{
ca1d4a9e 4822 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4823 int ret;
ca1d4a9e 4824
6f6fbe98
XG		 4825 if (vcpu->arch.pio.count)
4826 goto data_avail;
cf8f70bf 4827
6f6fbe98
XG		 4828 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4829 if (ret) {
4830data_avail:
4831 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4832 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4833 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4834 return 1;
4835 }
4836
cf8f70bf
GN		 4837 return 0;
4838}
4839
6f6fbe98
XG		 4840static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4841 int size, unsigned short port,
4842 const void *val, unsigned int count)
4843{
4844 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4845
4846 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4847 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4848 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4849}
4850
bbd9b64e
CO		 4851static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4852{
4853 return kvm_x86_ops->get_segment_base(vcpu, seg);
4854}
4855
3cb16fe7 4856static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4857{
3cb16fe7 4858 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4859}
4860
ae6a2375 4861static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4862{
4863 if (!need_emulate_wbinvd(vcpu))
4864 return X86EMUL_CONTINUE;
4865
4866 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4867 int cpu = get_cpu();
4868
4869 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4870 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4871 wbinvd_ipi, NULL, 1);
2eec7343 4872 put_cpu();
f5f48ee1 4873 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4874 } else
4875 wbinvd();
f5f48ee1
SY		 4876 return X86EMUL_CONTINUE;
4877}
5cb56059
JS		 4878
4879int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4880{
6affcbed
KH		 4881 kvm_emulate_wbinvd_noskip(vcpu);
4882 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4883}
f5f48ee1
SY		 4884EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4885
5cb56059
JS		 4886
4887
bcaf5cc5
AK		 4888static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4889{
5cb56059 4890 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4891}
4892
52eb5a6d
XL		 4893static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4894 unsigned long *dest)
bbd9b64e 4895{
16f8a6f9 4896 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4897}
4898
52eb5a6d
XL		 4899static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4900 unsigned long value)
bbd9b64e 4901{
338dbc97 4902
717746e3 4903 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4904}
4905
52a46617 4906static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4907{
52a46617 4908 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4909}
4910
717746e3 4911static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4912{
717746e3 4913 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4914 unsigned long value;
4915
4916 switch (cr) {
4917 case 0:
4918 value = kvm_read_cr0(vcpu);
4919 break;
4920 case 2:
4921 value = vcpu->arch.cr2;
4922 break;
4923 case 3:
9f8fe504 4924 value = kvm_read_cr3(vcpu);
52a46617
GN		 4925 break;
4926 case 4:
4927 value = kvm_read_cr4(vcpu);
4928 break;
4929 case 8:
4930 value = kvm_get_cr8(vcpu);
4931 break;
4932 default:
a737f256 4933 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4934 return 0;
4935 }
4936
4937 return value;
4938}
4939
717746e3 4940static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4941{
717746e3 4942 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4943 int res = 0;
4944
52a46617
GN		 4945 switch (cr) {
4946 case 0:
49a9b07e 4947 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4948 break;
4949 case 2:
4950 vcpu->arch.cr2 = val;
4951 break;
4952 case 3:
2390218b 4953 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4954 break;
4955 case 4:
a83b29c6 4956 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4957 break;
4958 case 8:
eea1cff9 4959 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4960 break;
4961 default:
a737f256 4962 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4963 res = -1;
52a46617 4964 }
0f12244f
GN		 4965
4966 return res;
52a46617
GN		 4967}
4968
717746e3 4969static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4970{
717746e3 4971 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4972}
4973
4bff1e86 4974static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4975{
4bff1e86 4976 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4977}
4978
4bff1e86 4979static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4980{
4bff1e86 4981 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4982}
4983
1ac9d0cf
AK		 4984static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4985{
4986 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4987}
4988
4989static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4990{
4991 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4992}
4993
4bff1e86
AK		 4994static unsigned long emulator_get_cached_segment_base(
4995 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4996{
4bff1e86 4997 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4998}
4999
1aa36616
AK		 5000static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5001 struct desc_struct *desc, u32 *base3,
5002 int seg)
2dafc6c2
GN		 5003{
5004 struct kvm_segment var;
5005
4bff1e86 5006 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5007 *selector = var.selector;
2dafc6c2 5008
378a8b09
GN		 5009 if (var.unusable) {
5010 memset(desc, 0, sizeof(*desc));
2dafc6c2 5011 return false;
378a8b09 5012 }
2dafc6c2
GN		 5013
5014 if (var.g)
5015 var.limit >>= 12;
5016 set_desc_limit(desc, var.limit);
5017 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5018#ifdef CONFIG_X86_64
5019 if (base3)
5020 *base3 = var.base >> 32;
5021#endif
2dafc6c2
GN		 5022 desc->type = var.type;
5023 desc->s = var.s;
5024 desc->dpl = var.dpl;
5025 desc->p = var.present;
5026 desc->avl = var.avl;
5027 desc->l = var.l;
5028 desc->d = var.db;
5029 desc->g = var.g;
5030
5031 return true;
5032}
5033
1aa36616
AK		 5034static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5035 struct desc_struct *desc, u32 base3,
5036 int seg)
2dafc6c2 5037{
4bff1e86 5038 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5039 struct kvm_segment var;
5040
1aa36616 5041 var.selector = selector;
2dafc6c2 5042 var.base = get_desc_base(desc);
5601d05b
GN		 5043#ifdef CONFIG_X86_64
5044 var.base |= ((u64)base3) << 32;
5045#endif
2dafc6c2
GN		 5046 var.limit = get_desc_limit(desc);
5047 if (desc->g)
5048 var.limit = (var.limit << 12) | 0xfff;
5049 var.type = desc->type;
2dafc6c2
GN		 5050 var.dpl = desc->dpl;
5051 var.db = desc->d;
5052 var.s = desc->s;
5053 var.l = desc->l;
5054 var.g = desc->g;
5055 var.avl = desc->avl;
5056 var.present = desc->p;
5057 var.unusable = !var.present;
5058 var.padding = 0;
5059
5060 kvm_set_segment(vcpu, &var, seg);
5061 return;
5062}
5063
717746e3
AK		 5064static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5065 u32 msr_index, u64 *pdata)
5066{
609e36d3
PB		 5067 struct msr_data msr;
5068 int r;
5069
5070 msr.index = msr_index;
5071 msr.host_initiated = false;
5072 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5073 if (r)
5074 return r;
5075
5076 *pdata = msr.data;
5077 return 0;
717746e3
AK		 5078}
5079
5080static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5081 u32 msr_index, u64 data)
5082{
8fe8ab46
WA		 5083 struct msr_data msr;
5084
5085 msr.data = data;
5086 msr.index = msr_index;
5087 msr.host_initiated = false;
5088 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5089}
5090
64d60670
PB		 5091static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5092{
5093 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5094
5095 return vcpu->arch.smbase;
5096}
5097
5098static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5099{
5100 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5101
5102 vcpu->arch.smbase = smbase;
5103}
5104
67f4d428
NA		 5105static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5106 u32 pmc)
5107{
c6702c9d 5108 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5109}
5110
222d21aa
AK		 5111static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5112 u32 pmc, u64 *pdata)
5113{
c6702c9d 5114 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5115}
5116
6c3287f7
AK		 5117static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5118{
5119 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5120}
5121
5037f6f3
AK		 5122static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5123{
5124 preempt_disable();
5197b808 5125 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5126}
5127
5128static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5129{
5130 preempt_enable();
5131}
5132
2953538e 5133static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5134 struct x86_instruction_info *info,
c4f035c6
AK		 5135 enum x86_intercept_stage stage)
5136{
2953538e 5137 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5138}
5139
0017f93a 5140static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5141 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5142{
0017f93a 5143 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5144}
5145
dd856efa
AK		 5146static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5147{
5148 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5149}
5150
5151static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5152{
5153 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5154}
5155
801806d9
NA		 5156static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5157{
5158 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5159}
5160
0225fb50 5161static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5162 .read_gpr = emulator_read_gpr,
5163 .write_gpr = emulator_write_gpr,
1871c602 5164 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5165 .write_std = kvm_write_guest_virt_system,
7a036a6f 5166 .read_phys = kvm_read_guest_phys_system,
1871c602 5167 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5168 .read_emulated = emulator_read_emulated,
5169 .write_emulated = emulator_write_emulated,
5170 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5171 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5172 .pio_in_emulated = emulator_pio_in_emulated,
5173 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5174 .get_segment = emulator_get_segment,
5175 .set_segment = emulator_set_segment,
5951c442 5176 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5177 .get_gdt = emulator_get_gdt,
160ce1f1 5178 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5179 .set_gdt = emulator_set_gdt,
5180 .set_idt = emulator_set_idt,
52a46617
GN		 5181 .get_cr = emulator_get_cr,
5182 .set_cr = emulator_set_cr,
9c537244 5183 .cpl = emulator_get_cpl,
35aa5375
GN		 5184 .get_dr = emulator_get_dr,
5185 .set_dr = emulator_set_dr,
64d60670
PB		 5186 .get_smbase = emulator_get_smbase,
5187 .set_smbase = emulator_set_smbase,
717746e3
AK		 5188 .set_msr = emulator_set_msr,
5189 .get_msr = emulator_get_msr,
67f4d428 5190 .check_pmc = emulator_check_pmc,
222d21aa 5191 .read_pmc = emulator_read_pmc,
6c3287f7 5192 .halt = emulator_halt,
bcaf5cc5 5193 .wbinvd = emulator_wbinvd,
d6aa1000 5194 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5195 .get_fpu = emulator_get_fpu,
5196 .put_fpu = emulator_put_fpu,
c4f035c6 5197 .intercept = emulator_intercept,
bdb42f5a 5198 .get_cpuid = emulator_get_cpuid,
801806d9 5199 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5200};
5201
95cb2295
GN		 5202static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5203{
37ccdcbe 5204 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5205 /*
5206 * an sti; sti; sequence only disable interrupts for the first
5207 * instruction. So, if the last instruction, be it emulated or
5208 * not, left the system with the INT_STI flag enabled, it
5209 * means that the last instruction is an sti. We should not
5210 * leave the flag on in this case. The same goes for mov ss
5211 */
37ccdcbe
PB		 5212 if (int_shadow & mask)
5213 mask = 0;
6addfc42 5214 if (unlikely(int_shadow || mask)) {
95cb2295 5215 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5216 if (!mask)
5217 kvm_make_request(KVM_REQ_EVENT, vcpu);
5218 }
95cb2295
GN		 5219}
5220
ef54bcfe 5221static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5222{
5223 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5224 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5225 return kvm_propagate_fault(vcpu, &ctxt->exception);
5226
5227 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5228 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5229 ctxt->exception.error_code);
54b8486f 5230 else
da9cb575 5231 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5232 return false;
54b8486f
GN		 5233}
5234
8ec4722d
MG		 5235static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5236{
adf52235 5237 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5238 int cs_db, cs_l;
5239
8ec4722d
MG		 5240 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5241
adf52235
TY		 5242 ctxt->eflags = kvm_get_rflags(vcpu);
5243 ctxt->eip = kvm_rip_read(vcpu);
5244 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5245 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5246 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5247 cs_db ? X86EMUL_MODE_PROT32 :
5248 X86EMUL_MODE_PROT16;
a584539b 5249 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5250 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5251 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5252 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5253
dd856efa 5254 init_decode_cache(ctxt);
7ae441ea 5255 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5256}
5257
71f9833b 5258int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5259{
9d74191a 5260 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5261 int ret;
5262
5263 init_emulate_ctxt(vcpu);
5264
9dac77fa
AK		 5265 ctxt->op_bytes = 2;
5266 ctxt->ad_bytes = 2;
5267 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5268 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5269
5270 if (ret != X86EMUL_CONTINUE)
5271 return EMULATE_FAIL;
5272
9dac77fa 5273 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5274 kvm_rip_write(vcpu, ctxt->eip);
5275 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5276
5277 if (irq == NMI_VECTOR)
7460fb4a 5278 vcpu->arch.nmi_pending = 0;
63995653
MG		 5279 else
5280 vcpu->arch.interrupt.pending = false;
5281
5282 return EMULATE_DONE;
5283}
5284EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5285
6d77dbfc
GN		 5286static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5287{
fc3a9157
JR		 5288 int r = EMULATE_DONE;
5289
6d77dbfc
GN		 5290 ++vcpu->stat.insn_emulation_fail;
5291 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5292 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5293 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5294 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5295 vcpu->run->internal.ndata = 0;
5296 r = EMULATE_FAIL;
5297 }
6d77dbfc 5298 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5299
5300 return r;
6d77dbfc
GN		 5301}
5302
93c05d3e 5303static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5304 bool write_fault_to_shadow_pgtable,
5305 int emulation_type)
a6f177ef 5306{
95b3cf69 5307 gpa_t gpa = cr2;
ba049e93 5308 kvm_pfn_t pfn;
a6f177ef 5309
991eebf9
GN		 5310 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5311 return false;
5312
95b3cf69
XG		 5313 if (!vcpu->arch.mmu.direct_map) {
5314 /*
5315 * Write permission should be allowed since only
5316 * write access need to be emulated.
5317 */
5318 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5319
95b3cf69
XG		 5320 /*
5321 * If the mapping is invalid in guest, let cpu retry
5322 * it to generate fault.
5323 */
5324 if (gpa == UNMAPPED_GVA)
5325 return true;
5326 }
a6f177ef 5327
8e3d9d06
XG		 5328 /*
5329 * Do not retry the unhandleable instruction if it faults on the
5330 * readonly host memory, otherwise it will goto a infinite loop:
5331 * retry instruction -> write #PF -> emulation fail -> retry
5332 * instruction -> ...
5333 */
5334 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5335
5336 /*
5337 * If the instruction failed on the error pfn, it can not be fixed,
5338 * report the error to userspace.
5339 */
5340 if (is_error_noslot_pfn(pfn))
5341 return false;
5342
5343 kvm_release_pfn_clean(pfn);
5344
5345 /* The instructions are well-emulated on direct mmu. */
5346 if (vcpu->arch.mmu.direct_map) {
5347 unsigned int indirect_shadow_pages;
5348
5349 spin_lock(&vcpu->kvm->mmu_lock);
5350 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5351 spin_unlock(&vcpu->kvm->mmu_lock);
5352
5353 if (indirect_shadow_pages)
5354 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5355
a6f177ef 5356 return true;
8e3d9d06 5357 }
a6f177ef 5358
95b3cf69
XG		 5359 /*
5360 * if emulation was due to access to shadowed page table
5361 * and it failed try to unshadow page and re-enter the
5362 * guest to let CPU execute the instruction.
5363 */
5364 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5365
5366 /*
5367 * If the access faults on its page table, it can not
5368 * be fixed by unprotecting shadow page and it should
5369 * be reported to userspace.
5370 */
5371 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5372}
5373
1cb3f3ae
XG		 5374static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5375 unsigned long cr2, int emulation_type)
5376{
5377 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5378 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5379
5380 last_retry_eip = vcpu->arch.last_retry_eip;
5381 last_retry_addr = vcpu->arch.last_retry_addr;
5382
5383 /*
5384 * If the emulation is caused by #PF and it is non-page_table
5385 * writing instruction, it means the VM-EXIT is caused by shadow
5386 * page protected, we can zap the shadow page and retry this
5387 * instruction directly.
5388 *
5389 * Note: if the guest uses a non-page-table modifying instruction
5390 * on the PDE that points to the instruction, then we will unmap
5391 * the instruction and go to an infinite loop. So, we cache the
5392 * last retried eip and the last fault address, if we meet the eip
5393 * and the address again, we can break out of the potential infinite
5394 * loop.
5395 */
5396 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5397
5398 if (!(emulation_type & EMULTYPE_RETRY))
5399 return false;
5400
5401 if (x86_page_table_writing_insn(ctxt))
5402 return false;
5403
5404 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5405 return false;
5406
5407 vcpu->arch.last_retry_eip = ctxt->eip;
5408 vcpu->arch.last_retry_addr = cr2;
5409
5410 if (!vcpu->arch.mmu.direct_map)
5411 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5412
22368028 5413 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5414
5415 return true;
5416}
5417
716d51ab
GN		 5418static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5419static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5420
64d60670 5421static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5422{
64d60670 5423 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5424 /* This is a good place to trace that we are exiting SMM. */
5425 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5426
c43203ca
PB		 5427 /* Process a latched INIT or SMI, if any. */
5428 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5429 }
699023e2
PB		 5430
5431 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5432}
5433
5434static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5435{
5436 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5437
a584539b 5438 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5439
5440 if (changed & HF_SMM_MASK)
5441 kvm_smm_changed(vcpu);
a584539b
PB		 5442}
5443
4a1e10d5
PB		 5444static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5445 unsigned long *db)
5446{
5447 u32 dr6 = 0;
5448 int i;
5449 u32 enable, rwlen;
5450
5451 enable = dr7;
5452 rwlen = dr7 >> 16;
5453 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5454 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5455 dr6 |= (1 << i);
5456 return dr6;
5457}
5458
6addfc42 5459static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5460{
5461 struct kvm_run *kvm_run = vcpu->run;
5462
5463 /*
6addfc42
PB		 5464 * rflags is the old, "raw" value of the flags. The new value has
5465 * not been saved yet.
663f4c61
PB		 5466 *
5467 * This is correct even for TF set by the guest, because "the
5468 * processor will not generate this exception after the instruction
5469 * that sets the TF flag".
5470 */
663f4c61
PB		 5471 if (unlikely(rflags & X86_EFLAGS_TF)) {
5472 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5473 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5474 DR6_RTM;
663f4c61
PB		 5475 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5476 kvm_run->debug.arch.exception = DB_VECTOR;
5477 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5478 *r = EMULATE_USER_EXIT;
5479 } else {
663f4c61
PB		 5480 /*
5481 * "Certain debug exceptions may clear bit 0-3. The
5482 * remaining contents of the DR6 register are never
5483 * cleared by the processor".
5484 */
5485 vcpu->arch.dr6 &= ~15;
6f43ed01 5486 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5487 kvm_queue_exception(vcpu, DB_VECTOR);
5488 }
5489 }
5490}
5491
6affcbed
KH		 5492int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5493{
5494 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5495 int r = EMULATE_DONE;
5496
5497 kvm_x86_ops->skip_emulated_instruction(vcpu);
5498 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5499 return r == EMULATE_DONE;
5500}
5501EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5502
4a1e10d5
PB		 5503static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5504{
4a1e10d5
PB		 5505 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5506 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5507 struct kvm_run *kvm_run = vcpu->run;
5508 unsigned long eip = kvm_get_linear_rip(vcpu);
5509 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5510 vcpu->arch.guest_debug_dr7,
5511 vcpu->arch.eff_db);
5512
5513 if (dr6 != 0) {
6f43ed01 5514 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5515 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5516 kvm_run->debug.arch.exception = DB_VECTOR;
5517 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5518 *r = EMULATE_USER_EXIT;
5519 return true;
5520 }
5521 }
5522
4161a569
NA		 5523 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5524 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5525 unsigned long eip = kvm_get_linear_rip(vcpu);
5526 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5527 vcpu->arch.dr7,
5528 vcpu->arch.db);
5529
5530 if (dr6 != 0) {
5531 vcpu->arch.dr6 &= ~15;
6f43ed01 5532 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5533 kvm_queue_exception(vcpu, DB_VECTOR);
5534 *r = EMULATE_DONE;
5535 return true;
5536 }
5537 }
5538
5539 return false;
5540}
5541
51d8b661
AP		 5542int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5543 unsigned long cr2,
dc25e89e
AP		 5544 int emulation_type,
5545 void *insn,
5546 int insn_len)
bbd9b64e 5547{
95cb2295 5548 int r;
9d74191a 5549 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5550 bool writeback = true;
93c05d3e 5551 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5552
93c05d3e
XG		 5553 /*
5554 * Clear write_fault_to_shadow_pgtable here to ensure it is
5555 * never reused.
5556 */
5557 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5558 kvm_clear_exception_queue(vcpu);
8d7d8102 5559
571008da 5560 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5561 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5562
5563 /*
5564 * We will reenter on the same instruction since
5565 * we do not set complete_userspace_io. This does not
5566 * handle watchpoints yet, those would be handled in
5567 * the emulate_ops.
5568 */
5569 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5570 return r;
5571
9d74191a
TY		 5572 ctxt->interruptibility = 0;
5573 ctxt->have_exception = false;
e0ad0b47 5574 ctxt->exception.vector = -1;
9d74191a 5575 ctxt->perm_ok = false;
bbd9b64e 5576
b51e974f 5577 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5578
9d74191a 5579 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5580
e46479f8 5581 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5582 ++vcpu->stat.insn_emulation;
1d2887e2 5583 if (r != EMULATION_OK) {
4005996e
AK		 5584 if (emulation_type & EMULTYPE_TRAP_UD)
5585 return EMULATE_FAIL;
991eebf9
GN		 5586 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5587 emulation_type))
bbd9b64e 5588 return EMULATE_DONE;
6d77dbfc
GN		 5589 if (emulation_type & EMULTYPE_SKIP)
5590 return EMULATE_FAIL;
5591 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5592 }
5593 }
5594
ba8afb6b 5595 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5596 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5597 if (ctxt->eflags & X86_EFLAGS_RF)
5598 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5599 return EMULATE_DONE;
5600 }
5601
1cb3f3ae
XG		 5602 if (retry_instruction(ctxt, cr2, emulation_type))
5603 return EMULATE_DONE;
5604
7ae441ea 5605 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5606 changes registers values during IO operation */
7ae441ea
GN		 5607 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5608 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5609 emulator_invalidate_register_cache(ctxt);
7ae441ea 5610 }
4d2179e1 5611
5cd21917 5612restart:
9d74191a 5613 r = x86_emulate_insn(ctxt);
bbd9b64e 5614
775fde86
JR		 5615 if (r == EMULATION_INTERCEPTED)
5616 return EMULATE_DONE;
5617
d2ddd1c4 5618 if (r == EMULATION_FAILED) {
991eebf9
GN		 5619 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5620 emulation_type))
c3cd7ffa
GN		 5621 return EMULATE_DONE;
5622
6d77dbfc 5623 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5624 }
5625
9d74191a 5626 if (ctxt->have_exception) {
d2ddd1c4 5627 r = EMULATE_DONE;
ef54bcfe
PB		 5628 if (inject_emulated_exception(vcpu))
5629 return r;
d2ddd1c4 5630 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5631 if (!vcpu->arch.pio.in) {
5632 /* FIXME: return into emulator if single-stepping. */
3457e419 5633 vcpu->arch.pio.count = 0;
0912c977 5634 } else {
7ae441ea 5635 writeback = false;
716d51ab
GN		 5636 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5637 }
ac0a48c3 5638 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5639 } else if (vcpu->mmio_needed) {
5640 if (!vcpu->mmio_is_write)
5641 writeback = false;
ac0a48c3 5642 r = EMULATE_USER_EXIT;
716d51ab 5643 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5644 } else if (r == EMULATION_RESTART)
5cd21917 5645 goto restart;
d2ddd1c4
GN		 5646 else
5647 r = EMULATE_DONE;
f850e2e6 5648
7ae441ea 5649 if (writeback) {
6addfc42 5650 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5651 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5652 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5653 if (vcpu->arch.hflags != ctxt->emul_flags)
5654 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5655 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5656 if (r == EMULATE_DONE)
6addfc42 5657 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5658 if (!ctxt->have_exception ||
5659 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5660 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5661
5662 /*
5663 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5664 * do nothing, and it will be requested again as soon as
5665 * the shadow expires. But we still need to check here,
5666 * because POPF has no interrupt shadow.
5667 */
5668 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5669 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5670 } else
5671 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5672
5673 return r;
de7d789a 5674}
51d8b661 5675EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5676
cf8f70bf 5677int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5678{
cf8f70bf 5679 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5680 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5681 size, port, &val, 1);
cf8f70bf 5682 /* do not return to emulator after return from userspace */
7972995b 5683 vcpu->arch.pio.count = 0;
de7d789a
CO		 5684 return ret;
5685}
cf8f70bf 5686EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5687
8370c3d0
TL		 5688static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5689{
5690 unsigned long val;
5691
5692 /* We should only ever be called with arch.pio.count equal to 1 */
5693 BUG_ON(vcpu->arch.pio.count != 1);
5694
5695 /* For size less than 4 we merge, else we zero extend */
5696 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5697 : 0;
5698
5699 /*
5700 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5701 * the copy and tracing
5702 */
5703 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5704 vcpu->arch.pio.port, &val, 1);
5705 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5706
5707 return 1;
5708}
5709
5710int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5711{
5712 unsigned long val;
5713 int ret;
5714
5715 /* For size less than 4 we merge, else we zero extend */
5716 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5717
5718 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5719 &val, 1);
5720 if (ret) {
5721 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5722 return ret;
5723 }
5724
5725 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5726
5727 return 0;
5728}
5729EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5730
251a5fd6 5731static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5732{
0a3aee0d 5733 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5734 return 0;
8cfdc000
ZA		 5735}
5736
5737static void tsc_khz_changed(void *data)
c8076604 5738{
8cfdc000
ZA		 5739 struct cpufreq_freqs *freq = data;
5740 unsigned long khz = 0;
5741
5742 if (data)
5743 khz = freq->new;
5744 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5745 khz = cpufreq_quick_get(raw_smp_processor_id());
5746 if (!khz)
5747 khz = tsc_khz;
0a3aee0d 5748 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5749}
5750
c8076604
GH		 5751static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5752 void *data)
5753{
5754 struct cpufreq_freqs *freq = data;
5755 struct kvm *kvm;
5756 struct kvm_vcpu *vcpu;
5757 int i, send_ipi = 0;
5758
8cfdc000
ZA		 5759 /*
5760 * We allow guests to temporarily run on slowing clocks,
5761 * provided we notify them after, or to run on accelerating
5762 * clocks, provided we notify them before. Thus time never
5763 * goes backwards.
5764 *
5765 * However, we have a problem. We can't atomically update
5766 * the frequency of a given CPU from this function; it is
5767 * merely a notifier, which can be called from any CPU.
5768 * Changing the TSC frequency at arbitrary points in time
5769 * requires a recomputation of local variables related to
5770 * the TSC for each VCPU. We must flag these local variables
5771 * to be updated and be sure the update takes place with the
5772 * new frequency before any guests proceed.
5773 *
5774 * Unfortunately, the combination of hotplug CPU and frequency
5775 * change creates an intractable locking scenario; the order
5776 * of when these callouts happen is undefined with respect to
5777 * CPU hotplug, and they can race with each other. As such,
5778 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5779 * undefined; you can actually have a CPU frequency change take
5780 * place in between the computation of X and the setting of the
5781 * variable. To protect against this problem, all updates of
5782 * the per_cpu tsc_khz variable are done in an interrupt
5783 * protected IPI, and all callers wishing to update the value
5784 * must wait for a synchronous IPI to complete (which is trivial
5785 * if the caller is on the CPU already). This establishes the
5786 * necessary total order on variable updates.
5787 *
5788 * Note that because a guest time update may take place
5789 * anytime after the setting of the VCPU's request bit, the
5790 * correct TSC value must be set before the request. However,
5791 * to ensure the update actually makes it to any guest which
5792 * starts running in hardware virtualization between the set
5793 * and the acquisition of the spinlock, we must also ping the
5794 * CPU after setting the request bit.
5795 *
5796 */
5797
c8076604
GH		 5798 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5799 return 0;
5800 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5801 return 0;
8cfdc000
ZA		 5802
5803 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5804
2f303b74 5805 spin_lock(&kvm_lock);
c8076604 5806 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5807 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5808 if (vcpu->cpu != freq->cpu)
5809 continue;
c285545f 5810 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5811 if (vcpu->cpu != smp_processor_id())
8cfdc000 5812 send_ipi = 1;
c8076604
GH		 5813 }
5814 }
2f303b74 5815 spin_unlock(&kvm_lock);
c8076604
GH		 5816
5817 if (freq->old < freq->new && send_ipi) {
5818 /*
5819 * We upscale the frequency. Must make the guest
5820 * doesn't see old kvmclock values while running with
5821 * the new frequency, otherwise we risk the guest sees
5822 * time go backwards.
5823 *
5824 * In case we update the frequency for another cpu
5825 * (which might be in guest context) send an interrupt
5826 * to kick the cpu out of guest context. Next time
5827 * guest context is entered kvmclock will be updated,
5828 * so the guest will not see stale values.
5829 */
8cfdc000 5830 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5831 }
5832 return 0;
5833}
5834
5835static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5836 .notifier_call = kvmclock_cpufreq_notifier
5837};
5838
251a5fd6 5839static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5840{
251a5fd6
SAS		 5841 tsc_khz_changed(NULL);
5842 return 0;
8cfdc000
ZA		 5843}
5844
b820cc0c
ZA		 5845static void kvm_timer_init(void)
5846{
c285545f 5847 max_tsc_khz = tsc_khz;
460dd42e 5848
b820cc0c 5849 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5850#ifdef CONFIG_CPU_FREQ
5851 struct cpufreq_policy policy;
758f588d
BP		 5852 int cpu;
5853
c285545f 5854 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5855 cpu = get_cpu();
5856 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5857 if (policy.cpuinfo.max_freq)
5858 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5859 put_cpu();
c285545f 5860#endif
b820cc0c
ZA		 5861 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5862 CPUFREQ_TRANSITION_NOTIFIER);
5863 }
c285545f 5864 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5865
73c1b41e 5866 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5867 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5868}
5869
ff9d07a0
ZY		 5870static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5871
f5132b01 5872int kvm_is_in_guest(void)
ff9d07a0 5873{
086c9855 5874 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5875}
5876
5877static int kvm_is_user_mode(void)
5878{
5879 int user_mode = 3;
dcf46b94 5880
086c9855
AS		 5881 if (__this_cpu_read(current_vcpu))
5882 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5883
ff9d07a0
ZY		 5884 return user_mode != 0;
5885}
5886
5887static unsigned long kvm_get_guest_ip(void)
5888{
5889 unsigned long ip = 0;
dcf46b94 5890
086c9855
AS		 5891 if (__this_cpu_read(current_vcpu))
5892 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5893
ff9d07a0
ZY		 5894 return ip;
5895}
5896
5897static struct perf_guest_info_callbacks kvm_guest_cbs = {
5898 .is_in_guest = kvm_is_in_guest,
5899 .is_user_mode = kvm_is_user_mode,
5900 .get_guest_ip = kvm_get_guest_ip,
5901};
5902
5903void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5904{
086c9855 5905 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5906}
5907EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5908
5909void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5910{
086c9855 5911 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5912}
5913EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5914
ce88decf
XG		 5915static void kvm_set_mmio_spte_mask(void)
5916{
5917 u64 mask;
5918 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5919
5920 /*
5921 * Set the reserved bits and the present bit of an paging-structure
5922 * entry to generate page fault with PFER.RSV = 1.
5923 */
885032b9 5924 /* Mask the reserved physical address bits. */
d1431483 5925 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5926
5927 /* Bit 62 is always reserved for 32bit host. */
5928 mask |= 0x3ull << 62;
5929
5930 /* Set the present bit. */
ce88decf
XG		 5931 mask |= 1ull;
5932
5933#ifdef CONFIG_X86_64
5934 /*
5935 * If reserved bit is not supported, clear the present bit to disable
5936 * mmio page fault.
5937 */
5938 if (maxphyaddr == 52)
5939 mask &= ~1ull;
5940#endif
5941
5942 kvm_mmu_set_mmio_spte_mask(mask);
5943}
5944
16e8d74d
MT		 5945#ifdef CONFIG_X86_64
5946static void pvclock_gtod_update_fn(struct work_struct *work)
5947{
d828199e
MT		 5948 struct kvm *kvm;
5949
5950 struct kvm_vcpu *vcpu;
5951 int i;
5952
2f303b74 5953 spin_lock(&kvm_lock);
d828199e
MT		 5954 list_for_each_entry(kvm, &vm_list, vm_list)
5955 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5956 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5957 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5958 spin_unlock(&kvm_lock);
16e8d74d
MT		 5959}
5960
5961static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5962
5963/*
5964 * Notification about pvclock gtod data update.
5965 */
5966static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5967 void *priv)
5968{
5969 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5970 struct timekeeper *tk = priv;
5971
5972 update_pvclock_gtod(tk);
5973
5974 /* disable master clock if host does not trust, or does not
5975 * use, TSC clocksource
5976 */
5977 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5978 atomic_read(&kvm_guest_has_master_clock) != 0)
5979 queue_work(system_long_wq, &pvclock_gtod_work);
5980
5981 return 0;
5982}
5983
5984static struct notifier_block pvclock_gtod_notifier = {
5985 .notifier_call = pvclock_gtod_notify,
5986};
5987#endif
5988
f8c16bba 5989int kvm_arch_init(void *opaque)
043405e1 5990{
b820cc0c 5991 int r;
6b61edf7 5992 struct kvm_x86_ops *ops = opaque;
f8c16bba 5993
f8c16bba
ZX		 5994 if (kvm_x86_ops) {
5995 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5996 r = -EEXIST;
5997 goto out;
f8c16bba
ZX		 5998 }
5999
6000 if (!ops->cpu_has_kvm_support()) {
6001 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6002 r = -EOPNOTSUPP;
6003 goto out;
f8c16bba
ZX		 6004 }
6005 if (ops->disabled_by_bios()) {
6006 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6007 r = -EOPNOTSUPP;
6008 goto out;
f8c16bba
ZX		 6009 }
6010
013f6a5d
MT		 6011 r = -ENOMEM;
6012 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6013 if (!shared_msrs) {
6014 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6015 goto out;
6016 }
6017
97db56ce
AK		 6018 r = kvm_mmu_module_init();
6019 if (r)
013f6a5d 6020 goto out_free_percpu;
97db56ce 6021
ce88decf 6022 kvm_set_mmio_spte_mask();
97db56ce 6023
f8c16bba 6024 kvm_x86_ops = ops;
920c8377 6025
7b52345e 6026 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6027 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6028 PT_PRESENT_MASK, 0);
b820cc0c 6029 kvm_timer_init();
c8076604 6030
ff9d07a0
ZY		 6031 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6032
d366bf7e 6033 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6034 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6035
c5cc421b 6036 kvm_lapic_init();
16e8d74d
MT		 6037#ifdef CONFIG_X86_64
6038 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6039#endif
6040
f8c16bba 6041 return 0;
56c6d28a 6042
013f6a5d
MT		 6043out_free_percpu:
6044 free_percpu(shared_msrs);
56c6d28a 6045out:
56c6d28a 6046 return r;
043405e1 6047}
8776e519 6048
f8c16bba
ZX		 6049void kvm_arch_exit(void)
6050{
ff9d07a0
ZY		 6051 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6052
888d256e
JK		 6053 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6054 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6055 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6056 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6057#ifdef CONFIG_X86_64
6058 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6059#endif
f8c16bba 6060 kvm_x86_ops = NULL;
56c6d28a 6061 kvm_mmu_module_exit();
013f6a5d 6062 free_percpu(shared_msrs);
56c6d28a 6063}
f8c16bba 6064
5cb56059 6065int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6066{
6067 ++vcpu->stat.halt_exits;
35754c98 6068 if (lapic_in_kernel(vcpu)) {
a4535290 6069 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6070 return 1;
6071 } else {
6072 vcpu->run->exit_reason = KVM_EXIT_HLT;
6073 return 0;
6074 }
6075}
5cb56059
JS		 6076EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6077
6078int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6079{
6affcbed
KH		 6080 int ret = kvm_skip_emulated_instruction(vcpu);
6081 /*
6082 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6083 * KVM_EXIT_DEBUG here.
6084 */
6085 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6086}
8776e519
HB		 6087EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6088
6aef266c
SV		 6089/*
6090 * kvm_pv_kick_cpu_op: Kick a vcpu.
6091 *
6092 * @apicid - apicid of vcpu to be kicked.
6093 */
6094static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6095{
24d2166b 6096 struct kvm_lapic_irq lapic_irq;
6aef266c 6097
24d2166b
R		 6098 lapic_irq.shorthand = 0;
6099 lapic_irq.dest_mode = 0;
6100 lapic_irq.dest_id = apicid;
93bbf0b8 6101 lapic_irq.msi_redir_hint = false;
6aef266c 6102
24d2166b 6103 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6104 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6105}
6106
d62caabb
AS		 6107void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6108{
6109 vcpu->arch.apicv_active = false;
6110 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6111}
6112
8776e519
HB		 6113int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6114{
6115 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6116 int op_64_bit, r;
8776e519 6117
6affcbed 6118 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6119
55cd8e5a
GN		 6120 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6121 return kvm_hv_hypercall(vcpu);
6122
5fdbf976
MT		 6123 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6124 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6125 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6126 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6127 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6128
229456fc 6129 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6130
a449c7aa
NA		 6131 op_64_bit = is_64_bit_mode(vcpu);
6132 if (!op_64_bit) {
8776e519
HB		 6133 nr &= 0xFFFFFFFF;
6134 a0 &= 0xFFFFFFFF;
6135 a1 &= 0xFFFFFFFF;
6136 a2 &= 0xFFFFFFFF;
6137 a3 &= 0xFFFFFFFF;
6138 }
6139
07708c4a
JK		 6140 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6141 ret = -KVM_EPERM;
6142 goto out;
6143 }
6144
8776e519 6145 switch (nr) {
b93463aa
AK		 6146 case KVM_HC_VAPIC_POLL_IRQ:
6147 ret = 0;
6148 break;
6aef266c
SV		 6149 case KVM_HC_KICK_CPU:
6150 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6151 ret = 0;
6152 break;
8776e519
HB		 6153 default:
6154 ret = -KVM_ENOSYS;
6155 break;
6156 }
07708c4a 6157out:
a449c7aa
NA		 6158 if (!op_64_bit)
6159 ret = (u32)ret;
5fdbf976 6160 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6161 ++vcpu->stat.hypercalls;
2f333bcb 6162 return r;
8776e519
HB		 6163}
6164EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6165
b6785def 6166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6167{
d6aa1000 6168 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6169 char instruction[3];
5fdbf976 6170 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6171
8776e519 6172 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6173
9d74191a 6174 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6175}
6176
851ba692 6177static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6178{
782d422b
MG		 6179 return vcpu->run->request_interrupt_window &&
6180 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6181}
6182
851ba692 6183static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6184{
851ba692
AK		 6185 struct kvm_run *kvm_run = vcpu->run;
6186
91586a3b 6187 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6188 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6189 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6190 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6191 kvm_run->ready_for_interrupt_injection =
6192 pic_in_kernel(vcpu->kvm) ||
782d422b 6193 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6194}
6195
95ba8273
GN		 6196static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6197{
6198 int max_irr, tpr;
6199
6200 if (!kvm_x86_ops->update_cr8_intercept)
6201 return;
6202
bce87cce 6203 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6204 return;
6205
d62caabb
AS		 6206 if (vcpu->arch.apicv_active)
6207 return;
6208
8db3baa2
GN		 6209 if (!vcpu->arch.apic->vapic_addr)
6210 max_irr = kvm_lapic_find_highest_irr(vcpu);
6211 else
6212 max_irr = -1;
95ba8273
GN		 6213
6214 if (max_irr != -1)
6215 max_irr >>= 4;
6216
6217 tpr = kvm_lapic_get_cr8(vcpu);
6218
6219 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6220}
6221
b6b8a145 6222static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6223{
b6b8a145
JK		 6224 int r;
6225
95ba8273 6226 /* try to reinject previous events if any */
b59bb7bd 6227 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6228 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6229 vcpu->arch.exception.has_error_code,
6230 vcpu->arch.exception.error_code);
d6e8c854
NA		 6231
6232 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6233 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6234 X86_EFLAGS_RF);
6235
6bdf0662
NA		 6236 if (vcpu->arch.exception.nr == DB_VECTOR &&
6237 (vcpu->arch.dr7 & DR7_GD)) {
6238 vcpu->arch.dr7 &= ~DR7_GD;
6239 kvm_update_dr7(vcpu);
6240 }
6241
b59bb7bd
GN		 6242 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6243 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6244 vcpu->arch.exception.error_code,
6245 vcpu->arch.exception.reinject);
b6b8a145 6246 return 0;
b59bb7bd
GN		 6247 }
6248
95ba8273
GN		 6249 if (vcpu->arch.nmi_injected) {
6250 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6251 return 0;
95ba8273
GN		 6252 }
6253
6254 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6255 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6256 return 0;
6257 }
6258
6259 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6260 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6261 if (r != 0)
6262 return r;
95ba8273
GN		 6263 }
6264
6265 /* try to inject new event if pending */
c43203ca
PB		 6266 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6267 vcpu->arch.smi_pending = false;
ee2cd4b7 6268 enter_smm(vcpu);
c43203ca 6269 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6270 --vcpu->arch.nmi_pending;
6271 vcpu->arch.nmi_injected = true;
6272 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6273 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6274 /*
6275 * Because interrupts can be injected asynchronously, we are
6276 * calling check_nested_events again here to avoid a race condition.
6277 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6278 * proposal and current concerns. Perhaps we should be setting
6279 * KVM_REQ_EVENT only on certain events and not unconditionally?
6280 */
6281 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6282 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6283 if (r != 0)
6284 return r;
6285 }
95ba8273 6286 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6287 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6288 false);
6289 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6290 }
6291 }
ee2cd4b7 6292
b6b8a145 6293 return 0;
95ba8273
GN		 6294}
6295
7460fb4a
AK		 6296static void process_nmi(struct kvm_vcpu *vcpu)
6297{
6298 unsigned limit = 2;
6299
6300 /*
6301 * x86 is limited to one NMI running, and one NMI pending after it.
6302 * If an NMI is already in progress, limit further NMIs to just one.
6303 * Otherwise, allow two (and we'll inject the first one immediately).
6304 */
6305 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6306 limit = 1;
6307
6308 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6309 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6310 kvm_make_request(KVM_REQ_EVENT, vcpu);
6311}
6312
660a5d51
PB		 6313#define put_smstate(type, buf, offset, val) \
6314 *(type *)((buf) + (offset) - 0x7e00) = val
6315
ee2cd4b7 6316static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6317{
6318 u32 flags = 0;
6319 flags |= seg->g << 23;
6320 flags |= seg->db << 22;
6321 flags |= seg->l << 21;
6322 flags |= seg->avl << 20;
6323 flags |= seg->present << 15;
6324 flags |= seg->dpl << 13;
6325 flags |= seg->s << 12;
6326 flags |= seg->type << 8;
6327 return flags;
6328}
6329
ee2cd4b7 6330static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6331{
6332 struct kvm_segment seg;
6333 int offset;
6334
6335 kvm_get_segment(vcpu, &seg, n);
6336 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6337
6338 if (n < 3)
6339 offset = 0x7f84 + n * 12;
6340 else
6341 offset = 0x7f2c + (n - 3) * 12;
6342
6343 put_smstate(u32, buf, offset + 8, seg.base);
6344 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6345 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6346}
6347
efbb288a 6348#ifdef CONFIG_X86_64
ee2cd4b7 6349static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6350{
6351 struct kvm_segment seg;
6352 int offset;
6353 u16 flags;
6354
6355 kvm_get_segment(vcpu, &seg, n);
6356 offset = 0x7e00 + n * 16;
6357
ee2cd4b7 6358 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6359 put_smstate(u16, buf, offset, seg.selector);
6360 put_smstate(u16, buf, offset + 2, flags);
6361 put_smstate(u32, buf, offset + 4, seg.limit);
6362 put_smstate(u64, buf, offset + 8, seg.base);
6363}
efbb288a 6364#endif
660a5d51 6365
ee2cd4b7 6366static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6367{
6368 struct desc_ptr dt;
6369 struct kvm_segment seg;
6370 unsigned long val;
6371 int i;
6372
6373 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6374 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6375 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6376 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6377
6378 for (i = 0; i < 8; i++)
6379 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6380
6381 kvm_get_dr(vcpu, 6, &val);
6382 put_smstate(u32, buf, 0x7fcc, (u32)val);
6383 kvm_get_dr(vcpu, 7, &val);
6384 put_smstate(u32, buf, 0x7fc8, (u32)val);
6385
6386 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6387 put_smstate(u32, buf, 0x7fc4, seg.selector);
6388 put_smstate(u32, buf, 0x7f64, seg.base);
6389 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6390 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6391
6392 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6393 put_smstate(u32, buf, 0x7fc0, seg.selector);
6394 put_smstate(u32, buf, 0x7f80, seg.base);
6395 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6396 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6397
6398 kvm_x86_ops->get_gdt(vcpu, &dt);
6399 put_smstate(u32, buf, 0x7f74, dt.address);
6400 put_smstate(u32, buf, 0x7f70, dt.size);
6401
6402 kvm_x86_ops->get_idt(vcpu, &dt);
6403 put_smstate(u32, buf, 0x7f58, dt.address);
6404 put_smstate(u32, buf, 0x7f54, dt.size);
6405
6406 for (i = 0; i < 6; i++)
ee2cd4b7 6407 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6408
6409 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6410
6411 /* revision id */
6412 put_smstate(u32, buf, 0x7efc, 0x00020000);
6413 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6414}
6415
ee2cd4b7 6416static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6417{
6418#ifdef CONFIG_X86_64
6419 struct desc_ptr dt;
6420 struct kvm_segment seg;
6421 unsigned long val;
6422 int i;
6423
6424 for (i = 0; i < 16; i++)
6425 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6426
6427 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6428 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6429
6430 kvm_get_dr(vcpu, 6, &val);
6431 put_smstate(u64, buf, 0x7f68, val);
6432 kvm_get_dr(vcpu, 7, &val);
6433 put_smstate(u64, buf, 0x7f60, val);
6434
6435 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6436 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6437 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6438
6439 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6440
6441 /* revision id */
6442 put_smstate(u32, buf, 0x7efc, 0x00020064);
6443
6444 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6445
6446 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6447 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6448 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6449 put_smstate(u32, buf, 0x7e94, seg.limit);
6450 put_smstate(u64, buf, 0x7e98, seg.base);
6451
6452 kvm_x86_ops->get_idt(vcpu, &dt);
6453 put_smstate(u32, buf, 0x7e84, dt.size);
6454 put_smstate(u64, buf, 0x7e88, dt.address);
6455
6456 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6457 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6458 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6459 put_smstate(u32, buf, 0x7e74, seg.limit);
6460 put_smstate(u64, buf, 0x7e78, seg.base);
6461
6462 kvm_x86_ops->get_gdt(vcpu, &dt);
6463 put_smstate(u32, buf, 0x7e64, dt.size);
6464 put_smstate(u64, buf, 0x7e68, dt.address);
6465
6466 for (i = 0; i < 6; i++)
ee2cd4b7 6467 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6468#else
6469 WARN_ON_ONCE(1);
6470#endif
6471}
6472
ee2cd4b7 6473static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6474{
660a5d51 6475 struct kvm_segment cs, ds;
18c3626e 6476 struct desc_ptr dt;
660a5d51
PB		 6477 char buf[512];
6478 u32 cr0;
6479
660a5d51
PB		 6480 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6481 vcpu->arch.hflags |= HF_SMM_MASK;
6482 memset(buf, 0, 512);
6483 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6484 enter_smm_save_state_64(vcpu, buf);
660a5d51 6485 else
ee2cd4b7 6486 enter_smm_save_state_32(vcpu, buf);
660a5d51 6487
54bf36aa 6488 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6489
6490 if (kvm_x86_ops->get_nmi_mask(vcpu))
6491 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6492 else
6493 kvm_x86_ops->set_nmi_mask(vcpu, true);
6494
6495 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6496 kvm_rip_write(vcpu, 0x8000);
6497
6498 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6499 kvm_x86_ops->set_cr0(vcpu, cr0);
6500 vcpu->arch.cr0 = cr0;
6501
6502 kvm_x86_ops->set_cr4(vcpu, 0);
6503
18c3626e
PB		 6504 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6505 dt.address = dt.size = 0;
6506 kvm_x86_ops->set_idt(vcpu, &dt);
6507
660a5d51
PB		 6508 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6509
6510 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6511 cs.base = vcpu->arch.smbase;
6512
6513 ds.selector = 0;
6514 ds.base = 0;
6515
6516 cs.limit = ds.limit = 0xffffffff;
6517 cs.type = ds.type = 0x3;
6518 cs.dpl = ds.dpl = 0;
6519 cs.db = ds.db = 0;
6520 cs.s = ds.s = 1;
6521 cs.l = ds.l = 0;
6522 cs.g = ds.g = 1;
6523 cs.avl = ds.avl = 0;
6524 cs.present = ds.present = 1;
6525 cs.unusable = ds.unusable = 0;
6526 cs.padding = ds.padding = 0;
6527
6528 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6529 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6530 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6531 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6532 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6533 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6534
6535 if (guest_cpuid_has_longmode(vcpu))
6536 kvm_x86_ops->set_efer(vcpu, 0);
6537
6538 kvm_update_cpuid(vcpu);
6539 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6540}
6541
ee2cd4b7 6542static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6543{
6544 vcpu->arch.smi_pending = true;
6545 kvm_make_request(KVM_REQ_EVENT, vcpu);
6546}
6547
2860c4b1
PB		 6548void kvm_make_scan_ioapic_request(struct kvm *kvm)
6549{
6550 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6551}
6552
3d81bc7e 6553static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6554{
5c919412
AS		 6555 u64 eoi_exit_bitmap[4];
6556
3d81bc7e
YZ		 6557 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6558 return;
c7c9c56c 6559
6308630b 6560 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6561
b053b2ae 6562 if (irqchip_split(vcpu->kvm))
6308630b 6563 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6564 else {
d62caabb
AS		 6565 if (vcpu->arch.apicv_active)
6566 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6567 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6568 }
5c919412
AS		 6569 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6570 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6571 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6572}
6573
a70656b6
RK		 6574static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6575{
6576 ++vcpu->stat.tlb_flush;
6577 kvm_x86_ops->tlb_flush(vcpu);
6578}
6579
4256f43f
TC		 6580void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6581{
c24ae0dc
TC		 6582 struct page *page = NULL;
6583
35754c98 6584 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6585 return;
6586
4256f43f
TC		 6587 if (!kvm_x86_ops->set_apic_access_page_addr)
6588 return;
6589
c24ae0dc 6590 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6591 if (is_error_page(page))
6592 return;
c24ae0dc
TC		 6593 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6594
6595 /*
6596 * Do not pin apic access page in memory, the MMU notifier
6597 * will call us again if it is migrated or swapped out.
6598 */
6599 put_page(page);
4256f43f
TC		 6600}
6601EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6602
fe71557a
TC		 6603void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6604 unsigned long address)
6605{
c24ae0dc
TC		 6606 /*
6607 * The physical address of apic access page is stored in the VMCS.
6608 * Update it when it becomes invalid.
6609 */
6610 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6611 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6612}
6613
9357d939 6614/*
362c698f 6615 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6616 * exiting to the userspace. Otherwise, the value will be returned to the
6617 * userspace.
6618 */
851ba692 6619static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6620{
6621 int r;
62a193ed
MG		 6622 bool req_int_win =
6623 dm_request_for_irq_injection(vcpu) &&
6624 kvm_cpu_accept_dm_intr(vcpu);
6625
730dca42 6626 bool req_immediate_exit = false;
b6c7a5dc 6627
3e007509 6628 if (vcpu->requests) {
a8eeb04a 6629 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6630 kvm_mmu_unload(vcpu);
a8eeb04a 6631 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6632 __kvm_migrate_timers(vcpu);
d828199e
MT		 6633 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6634 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6635 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6636 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6637 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6638 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6639 if (unlikely(r))
6640 goto out;
6641 }
a8eeb04a 6642 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6643 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6644 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6645 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6646 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6647 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6648 r = 0;
6649 goto out;
6650 }
a8eeb04a 6651 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6652 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6653 r = 0;
6654 goto out;
6655 }
a8eeb04a 6656 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6657 vcpu->fpu_active = 0;
6658 kvm_x86_ops->fpu_deactivate(vcpu);
6659 }
af585b92
GN		 6660 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6661 /* Page is swapped out. Do synthetic halt */
6662 vcpu->arch.apf.halted = true;
6663 r = 1;
6664 goto out;
6665 }
c9aaa895
GC		 6666 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6667 record_steal_time(vcpu);
64d60670
PB		 6668 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6669 process_smi(vcpu);
7460fb4a
AK		 6670 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6671 process_nmi(vcpu);
f5132b01 6672 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6673 kvm_pmu_handle_event(vcpu);
f5132b01 6674 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6675 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6676 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6677 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6678 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6679 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6680 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6681 vcpu->run->eoi.vector =
6682 vcpu->arch.pending_ioapic_eoi;
6683 r = 0;
6684 goto out;
6685 }
6686 }
3d81bc7e
YZ		 6687 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6688 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6689 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6690 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6691 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6692 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6693 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6694 r = 0;
6695 goto out;
6696 }
e516cebb
AS		 6697 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6698 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6699 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6700 r = 0;
6701 goto out;
6702 }
db397571
AS		 6703 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6704 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6705 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6706 r = 0;
6707 goto out;
6708 }
f3b138c5
AS		 6709
6710 /*
6711 * KVM_REQ_HV_STIMER has to be processed after
6712 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6713 * depend on the guest clock being up-to-date
6714 */
1f4b34f8
AS		 6715 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6716 kvm_hv_process_stimers(vcpu);
2f52d58c 6717 }
b93463aa 6718
bf9f6ac8
FW		 6719 /*
6720 * KVM_REQ_EVENT is not set when posted interrupts are set by
6721 * VT-d hardware, so we have to update RVI unconditionally.
6722 */
6723 if (kvm_lapic_enabled(vcpu)) {
6724 /*
6725 * Update architecture specific hints for APIC
6726 * virtual interrupt delivery.
6727 */
d62caabb 6728 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6729 kvm_x86_ops->hwapic_irr_update(vcpu,
6730 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6731 }
b93463aa 6732
b463a6f7 6733 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6734 kvm_apic_accept_events(vcpu);
6735 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6736 r = 1;
6737 goto out;
6738 }
6739
b6b8a145
JK		 6740 if (inject_pending_event(vcpu, req_int_win) != 0)
6741 req_immediate_exit = true;
321c5658 6742 else {
c43203ca
PB		 6743 /* Enable NMI/IRQ window open exits if needed.
6744 *
6745 * SMIs have two cases: 1) they can be nested, and
6746 * then there is nothing to do here because RSM will
6747 * cause a vmexit anyway; 2) or the SMI can be pending
6748 * because inject_pending_event has completed the
6749 * injection of an IRQ or NMI from the previous vmexit,
6750 * and then we request an immediate exit to inject the SMI.
6751 */
6752 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6753 req_immediate_exit = true;
321c5658
YS		 6754 if (vcpu->arch.nmi_pending)
6755 kvm_x86_ops->enable_nmi_window(vcpu);
6756 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6757 kvm_x86_ops->enable_irq_window(vcpu);
6758 }
b463a6f7
AK		 6759
6760 if (kvm_lapic_enabled(vcpu)) {
6761 update_cr8_intercept(vcpu);
6762 kvm_lapic_sync_to_vapic(vcpu);
6763 }
6764 }
6765
d8368af8
AK		 6766 r = kvm_mmu_reload(vcpu);
6767 if (unlikely(r)) {
d905c069 6768 goto cancel_injection;
d8368af8
AK		 6769 }
6770
b6c7a5dc
HB		 6771 preempt_disable();
6772
6773 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6774 if (vcpu->fpu_active)
6775 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6776 vcpu->mode = IN_GUEST_MODE;
6777
01b71917
MT		 6778 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6779
0f127d12
LT		 6780 /*
6781 * We should set ->mode before check ->requests,
6782 * Please see the comment in kvm_make_all_cpus_request.
6783 * This also orders the write to mode from any reads
6784 * to the page tables done while the VCPU is running.
6785 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6786 */
01b71917 6787 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6788
d94e1dc9 6789 local_irq_disable();
32f88400 6790
6b7e2d09 6791 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6792 || need_resched() || signal_pending(current)) {
6b7e2d09 6793 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6794 smp_wmb();
6c142801
AK		 6795 local_irq_enable();
6796 preempt_enable();
01b71917 6797 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6798 r = 1;
d905c069 6799 goto cancel_injection;
6c142801
AK		 6800 }
6801
fc5b7f3b
DM		 6802 kvm_load_guest_xcr0(vcpu);
6803
c43203ca
PB		 6804 if (req_immediate_exit) {
6805 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6806 smp_send_reschedule(vcpu->cpu);
c43203ca 6807 }
d6185f20 6808
8b89fe1f
PB		 6809 trace_kvm_entry(vcpu->vcpu_id);
6810 wait_lapic_expire(vcpu);
6edaa530 6811 guest_enter_irqoff();
b6c7a5dc 6812
42dbaa5a 6813 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6814 set_debugreg(0, 7);
6815 set_debugreg(vcpu->arch.eff_db[0], 0);
6816 set_debugreg(vcpu->arch.eff_db[1], 1);
6817 set_debugreg(vcpu->arch.eff_db[2], 2);
6818 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6819 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6820 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6821 }
b6c7a5dc 6822
851ba692 6823 kvm_x86_ops->run(vcpu);
b6c7a5dc 6824
c77fb5fe
PB		 6825 /*
6826 * Do this here before restoring debug registers on the host. And
6827 * since we do this before handling the vmexit, a DR access vmexit
6828 * can (a) read the correct value of the debug registers, (b) set
6829 * KVM_DEBUGREG_WONT_EXIT again.
6830 */
6831 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6832 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6833 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6834 kvm_update_dr0123(vcpu);
6835 kvm_update_dr6(vcpu);
6836 kvm_update_dr7(vcpu);
6837 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6838 }
6839
24f1e32c
FW		 6840 /*
6841 * If the guest has used debug registers, at least dr7
6842 * will be disabled while returning to the host.
6843 * If we don't have active breakpoints in the host, we don't
6844 * care about the messed up debug address registers. But if
6845 * we have some of them active, restore the old state.
6846 */
59d8eb53 6847 if (hw_breakpoint_active())
24f1e32c 6848 hw_breakpoint_restore();
42dbaa5a 6849
4ba76538 6850 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6851
6b7e2d09 6852 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6853 smp_wmb();
a547c6db 6854
fc5b7f3b
DM		 6855 kvm_put_guest_xcr0(vcpu);
6856
a547c6db 6857 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6858
6859 ++vcpu->stat.exits;
6860
f2485b3e 6861 guest_exit_irqoff();
b6c7a5dc 6862
f2485b3e 6863 local_irq_enable();
b6c7a5dc
HB		 6864 preempt_enable();
6865
f656ce01 6866 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6867
b6c7a5dc
HB		 6868 /*
6869 * Profile KVM exit RIPs:
6870 */
6871 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6872 unsigned long rip = kvm_rip_read(vcpu);
6873 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6874 }
6875
cc578287
ZA		 6876 if (unlikely(vcpu->arch.tsc_always_catchup))
6877 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6878
5cfb1d5a
MT		 6879 if (vcpu->arch.apic_attention)
6880 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6881
851ba692 6882 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6883 return r;
6884
6885cancel_injection:
6886 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6887 if (unlikely(vcpu->arch.apic_attention))
6888 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6889out:
6890 return r;
6891}
b6c7a5dc 6892
362c698f
PB		 6893static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6894{
bf9f6ac8
FW		 6895 if (!kvm_arch_vcpu_runnable(vcpu) &&
6896 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6897 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6898 kvm_vcpu_block(vcpu);
6899 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6900
6901 if (kvm_x86_ops->post_block)
6902 kvm_x86_ops->post_block(vcpu);
6903
9c8fd1ba
PB		 6904 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6905 return 1;
6906 }
362c698f
PB		 6907
6908 kvm_apic_accept_events(vcpu);
6909 switch(vcpu->arch.mp_state) {
6910 case KVM_MP_STATE_HALTED:
6911 vcpu->arch.pv.pv_unhalted = false;
6912 vcpu->arch.mp_state =
6913 KVM_MP_STATE_RUNNABLE;
6914 case KVM_MP_STATE_RUNNABLE:
6915 vcpu->arch.apf.halted = false;
6916 break;
6917 case KVM_MP_STATE_INIT_RECEIVED:
6918 break;
6919 default:
6920 return -EINTR;
6921 break;
6922 }
6923 return 1;
6924}
09cec754 6925
5d9bc648
PB		 6926static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6927{
6928 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6929 !vcpu->arch.apf.halted);
6930}
6931
362c698f 6932static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6933{
6934 int r;
f656ce01 6935 struct kvm *kvm = vcpu->kvm;
d7690175 6936
f656ce01 6937 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6938
362c698f 6939 for (;;) {
58f800d5 6940 if (kvm_vcpu_running(vcpu)) {
851ba692 6941 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6942 } else {
362c698f 6943 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6944 }
6945
09cec754
GN		 6946 if (r <= 0)
6947 break;
6948
6949 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6950 if (kvm_cpu_has_pending_timer(vcpu))
6951 kvm_inject_pending_timer_irqs(vcpu);
6952
782d422b
MG		 6953 if (dm_request_for_irq_injection(vcpu) &&
6954 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6955 r = 0;
6956 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6957 ++vcpu->stat.request_irq_exits;
362c698f 6958 break;
09cec754 6959 }
af585b92
GN		 6960
6961 kvm_check_async_pf_completion(vcpu);
6962
09cec754
GN		 6963 if (signal_pending(current)) {
6964 r = -EINTR;
851ba692 6965 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6966 ++vcpu->stat.signal_exits;
362c698f 6967 break;
09cec754
GN		 6968 }
6969 if (need_resched()) {
f656ce01 6970 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6971 cond_resched();
f656ce01 6972 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6973 }
b6c7a5dc
HB		 6974 }
6975
f656ce01 6976 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6977
6978 return r;
6979}
6980
716d51ab
GN		 6981static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6982{
6983 int r;
6984 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6985 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6986 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6987 if (r != EMULATE_DONE)
6988 return 0;
6989 return 1;
6990}
6991
6992static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6993{
6994 BUG_ON(!vcpu->arch.pio.count);
6995
6996 return complete_emulated_io(vcpu);
6997}
6998
f78146b0
AK		 6999/*
7000 * Implements the following, as a state machine:
7001 *
7002 * read:
7003 * for each fragment
87da7e66
XG		 7004 * for each mmio piece in the fragment
7005 * write gpa, len
7006 * exit
7007 * copy data
f78146b0
AK		 7008 * execute insn
7009 *
7010 * write:
7011 * for each fragment
87da7e66
XG		 7012 * for each mmio piece in the fragment
7013 * write gpa, len
7014 * copy data
7015 * exit
f78146b0 7016 */
716d51ab 7017static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7018{
7019 struct kvm_run *run = vcpu->run;
f78146b0 7020 struct kvm_mmio_fragment *frag;
87da7e66 7021 unsigned len;
5287f194 7022
716d51ab 7023 BUG_ON(!vcpu->mmio_needed);
5287f194 7024
716d51ab 7025 /* Complete previous fragment */
87da7e66
XG		 7026 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7027 len = min(8u, frag->len);
716d51ab 7028 if (!vcpu->mmio_is_write)
87da7e66
XG		 7029 memcpy(frag->data, run->mmio.data, len);
7030
7031 if (frag->len <= 8) {
7032 /* Switch to the next fragment. */
7033 frag++;
7034 vcpu->mmio_cur_fragment++;
7035 } else {
7036 /* Go forward to the next mmio piece. */
7037 frag->data += len;
7038 frag->gpa += len;
7039 frag->len -= len;
7040 }
7041
a08d3b3b 7042 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7043 vcpu->mmio_needed = 0;
0912c977
PB		 7044
7045 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7046 if (vcpu->mmio_is_write)
716d51ab
GN		 7047 return 1;
7048 vcpu->mmio_read_completed = 1;
7049 return complete_emulated_io(vcpu);
7050 }
87da7e66 7051
716d51ab
GN		 7052 run->exit_reason = KVM_EXIT_MMIO;
7053 run->mmio.phys_addr = frag->gpa;
7054 if (vcpu->mmio_is_write)
87da7e66
XG		 7055 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7056 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7057 run->mmio.is_write = vcpu->mmio_is_write;
7058 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7059 return 0;
5287f194
AK		 7060}
7061
716d51ab 7062
b6c7a5dc
HB		 7063int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7064{
c5bedc68 7065 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7066 int r;
7067 sigset_t sigsaved;
7068
c4d72e2d 7069 fpu__activate_curr(fpu);
e5c30142 7070
ac9f6dc0
AK		 7071 if (vcpu->sigset_active)
7072 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7073
a4535290 7074 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7075 kvm_vcpu_block(vcpu);
66450a21 7076 kvm_apic_accept_events(vcpu);
d7690175 7077 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 7078 r = -EAGAIN;
7079 goto out;
b6c7a5dc
HB		 7080 }
7081
b6c7a5dc 7082 /* re-sync apic's tpr */
35754c98 7083 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7084 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7085 r = -EINVAL;
7086 goto out;
7087 }
7088 }
b6c7a5dc 7089
716d51ab
GN		 7090 if (unlikely(vcpu->arch.complete_userspace_io)) {
7091 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7092 vcpu->arch.complete_userspace_io = NULL;
7093 r = cui(vcpu);
7094 if (r <= 0)
7095 goto out;
7096 } else
7097 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7098
362c698f 7099 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7100
7101out:
f1d86e46 7102 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7103 if (vcpu->sigset_active)
7104 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7105
b6c7a5dc
HB		 7106 return r;
7107}
7108
7109int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7110{
7ae441ea
GN		 7111 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7112 /*
7113 * We are here if userspace calls get_regs() in the middle of
7114 * instruction emulation. Registers state needs to be copied
4a969980 7115 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7116 * that usually, but some bad designed PV devices (vmware
7117 * backdoor interface) need this to work
7118 */
dd856efa 7119 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7120 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7121 }
5fdbf976
MT		 7122 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7123 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7124 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7125 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7126 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7127 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7128 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7129 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7130#ifdef CONFIG_X86_64
5fdbf976
MT		 7131 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7132 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7133 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7134 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7135 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7136 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7137 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7138 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7139#endif
7140
5fdbf976 7141 regs->rip = kvm_rip_read(vcpu);
91586a3b 7142 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7143
b6c7a5dc
HB		 7144 return 0;
7145}
7146
7147int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7148{
7ae441ea
GN		 7149 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7150 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7151
5fdbf976
MT		 7152 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7153 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7154 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7155 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7156 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7157 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7158 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7159 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7160#ifdef CONFIG_X86_64
5fdbf976
MT		 7161 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7162 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7163 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7164 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7165 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7166 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7167 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7168 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7169#endif
7170
5fdbf976 7171 kvm_rip_write(vcpu, regs->rip);
91586a3b 7172 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7173
b4f14abd
JK		 7174 vcpu->arch.exception.pending = false;
7175
3842d135
AK		 7176 kvm_make_request(KVM_REQ_EVENT, vcpu);
7177
b6c7a5dc
HB		 7178 return 0;
7179}
7180
b6c7a5dc
HB		 7181void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7182{
7183 struct kvm_segment cs;
7184
3e6e0aab 7185 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7186 *db = cs.db;
7187 *l = cs.l;
7188}
7189EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7190
7191int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7192 struct kvm_sregs *sregs)
7193{
89a27f4d 7194 struct desc_ptr dt;
b6c7a5dc 7195
3e6e0aab
GT		 7196 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7197 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7198 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7199 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7200 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7201 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7202
3e6e0aab
GT		 7203 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7204 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7205
7206 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7207 sregs->idt.limit = dt.size;
7208 sregs->idt.base = dt.address;
b6c7a5dc 7209 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7210 sregs->gdt.limit = dt.size;
7211 sregs->gdt.base = dt.address;
b6c7a5dc 7212
4d4ec087 7213 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7214 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7215 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7216 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7217 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7218 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7219 sregs->apic_base = kvm_get_apic_base(vcpu);
7220
923c61bb 7221 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7222
36752c9b 7223 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7224 set_bit(vcpu->arch.interrupt.nr,
7225 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7226
b6c7a5dc
HB		 7227 return 0;
7228}
7229
62d9f0db
MT		 7230int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7231 struct kvm_mp_state *mp_state)
7232{
66450a21 7233 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7234 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7235 vcpu->arch.pv.pv_unhalted)
7236 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7237 else
7238 mp_state->mp_state = vcpu->arch.mp_state;
7239
62d9f0db
MT		 7240 return 0;
7241}
7242
7243int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7244 struct kvm_mp_state *mp_state)
7245{
bce87cce 7246 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7247 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7248 return -EINVAL;
7249
7250 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7251 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7252 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7253 } else
7254 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7255 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7256 return 0;
7257}
7258
7f3d35fd
KW		 7259int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7260 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7261{
9d74191a 7262 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7263 int ret;
e01c2426 7264
8ec4722d 7265 init_emulate_ctxt(vcpu);
c697518a 7266
7f3d35fd 7267 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7268 has_error_code, error_code);
c697518a 7269
c697518a 7270 if (ret)
19d04437 7271 return EMULATE_FAIL;
37817f29 7272
9d74191a
TY		 7273 kvm_rip_write(vcpu, ctxt->eip);
7274 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7275 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7276 return EMULATE_DONE;
37817f29
IE		 7277}
7278EXPORT_SYMBOL_GPL(kvm_task_switch);
7279
b6c7a5dc
HB		 7280int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7281 struct kvm_sregs *sregs)
7282{
58cb628d 7283 struct msr_data apic_base_msr;
b6c7a5dc 7284 int mmu_reset_needed = 0;
63f42e02 7285 int pending_vec, max_bits, idx;
89a27f4d 7286 struct desc_ptr dt;
b6c7a5dc 7287
6d1068b3
PM		 7288 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7289 return -EINVAL;
7290
89a27f4d
GN		 7291 dt.size = sregs->idt.limit;
7292 dt.address = sregs->idt.base;
b6c7a5dc 7293 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7294 dt.size = sregs->gdt.limit;
7295 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7296 kvm_x86_ops->set_gdt(vcpu, &dt);
7297
ad312c7c 7298 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7299 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7300 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7301 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7302
2d3ad1f4 7303 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7304
f6801dff 7305 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7306 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7307 apic_base_msr.data = sregs->apic_base;
7308 apic_base_msr.host_initiated = true;
7309 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7310
4d4ec087 7311 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7312 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7313 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7314
fc78f519 7315 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7316 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7317 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7318 kvm_update_cpuid(vcpu);
63f42e02
XG		 7319
7320 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7321 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7322 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7323 mmu_reset_needed = 1;
7324 }
63f42e02 7325 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7326
7327 if (mmu_reset_needed)
7328 kvm_mmu_reset_context(vcpu);
7329
a50abc3b 7330 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7331 pending_vec = find_first_bit(
7332 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7333 if (pending_vec < max_bits) {
66fd3f7f 7334 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7335 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7336 }
7337
3e6e0aab
GT		 7338 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7339 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7340 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7341 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7342 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7343 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7344
3e6e0aab
GT		 7345 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7346 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7347
5f0269f5
ME		 7348 update_cr8_intercept(vcpu);
7349
9c3e4aab 7350 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7351 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7352 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7353 !is_protmode(vcpu))
9c3e4aab
MT		 7354 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7355
3842d135
AK		 7356 kvm_make_request(KVM_REQ_EVENT, vcpu);
7357
b6c7a5dc
HB		 7358 return 0;
7359}
7360
d0bfb940
JK		 7361int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7362 struct kvm_guest_debug *dbg)
b6c7a5dc 7363{
355be0b9 7364 unsigned long rflags;
ae675ef0 7365 int i, r;
b6c7a5dc 7366
4f926bf2
JK		 7367 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7368 r = -EBUSY;
7369 if (vcpu->arch.exception.pending)
2122ff5e 7370 goto out;
4f926bf2
JK		 7371 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7372 kvm_queue_exception(vcpu, DB_VECTOR);
7373 else
7374 kvm_queue_exception(vcpu, BP_VECTOR);
7375 }
7376
91586a3b
JK		 7377 /*
7378 * Read rflags as long as potentially injected trace flags are still
7379 * filtered out.
7380 */
7381 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7382
7383 vcpu->guest_debug = dbg->control;
7384 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7385 vcpu->guest_debug = 0;
7386
7387 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7388 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7389 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7390 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7391 } else {
7392 for (i = 0; i < KVM_NR_DB_REGS; i++)
7393 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7394 }
c8639010 7395 kvm_update_dr7(vcpu);
ae675ef0 7396
f92653ee
JK		 7397 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7398 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7399 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7400
91586a3b
JK		 7401 /*
7402 * Trigger an rflags update that will inject or remove the trace
7403 * flags.
7404 */
7405 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7406
a96036b8 7407 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7408
4f926bf2 7409 r = 0;
d0bfb940 7410
2122ff5e 7411out:
b6c7a5dc
HB		 7412
7413 return r;
7414}
7415
8b006791
ZX		 7416/*
7417 * Translate a guest virtual address to a guest physical address.
7418 */
7419int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7420 struct kvm_translation *tr)
7421{
7422 unsigned long vaddr = tr->linear_address;
7423 gpa_t gpa;
f656ce01 7424 int idx;
8b006791 7425
f656ce01 7426 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7427 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7428 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7429 tr->physical_address = gpa;
7430 tr->valid = gpa != UNMAPPED_GVA;
7431 tr->writeable = 1;
7432 tr->usermode = 0;
8b006791
ZX		 7433
7434 return 0;
7435}
7436
d0752060
HB		 7437int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7438{
c47ada30 7439 struct fxregs_state *fxsave =
7366ed77 7440 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7441
d0752060
HB		 7442 memcpy(fpu->fpr, fxsave->st_space, 128);
7443 fpu->fcw = fxsave->cwd;
7444 fpu->fsw = fxsave->swd;
7445 fpu->ftwx = fxsave->twd;
7446 fpu->last_opcode = fxsave->fop;
7447 fpu->last_ip = fxsave->rip;
7448 fpu->last_dp = fxsave->rdp;
7449 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7450
d0752060
HB		 7451 return 0;
7452}
7453
7454int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7455{
c47ada30 7456 struct fxregs_state *fxsave =
7366ed77 7457 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7458
d0752060
HB		 7459 memcpy(fxsave->st_space, fpu->fpr, 128);
7460 fxsave->cwd = fpu->fcw;
7461 fxsave->swd = fpu->fsw;
7462 fxsave->twd = fpu->ftwx;
7463 fxsave->fop = fpu->last_opcode;
7464 fxsave->rip = fpu->last_ip;
7465 fxsave->rdp = fpu->last_dp;
7466 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7467
d0752060
HB		 7468 return 0;
7469}
7470
0ee6a517 7471static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7472{
bf935b0b 7473 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7474 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7475 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7476 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7477
2acf923e
DC		 7478 /*
7479 * Ensure guest xcr0 is valid for loading
7480 */
d91cab78 7481 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7482
ad312c7c 7483 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7484}
d0752060
HB		 7485
7486void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7487{
2608d7a1 7488 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7489 return;
7490
2acf923e
DC		 7491 /*
7492 * Restore all possible states in the guest,
7493 * and assume host would use all available bits.
7494 * Guest xcr0 would be loaded later.
7495 */
d0752060 7496 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7497 __kernel_fpu_begin();
003e2e8b 7498 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7499 trace_kvm_fpu(1);
d0752060 7500}
d0752060
HB		 7501
7502void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7503{
3d42de25 7504 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7505 return;
7506
7507 vcpu->guest_fpu_loaded = 0;
4f836347 7508 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7509 __kernel_fpu_end();
f096ed85 7510 ++vcpu->stat.fpu_reload;
0c04851c 7511 trace_kvm_fpu(0);
d0752060 7512}
e9b11c17
ZX		 7513
7514void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7515{
bd768e14
IY		 7516 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7517
12f9a48f 7518 kvmclock_reset(vcpu);
7f1ea208 7519
e9b11c17 7520 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7521 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7522}
7523
7524struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7525 unsigned int id)
7526{
c447e76b
LL		 7527 struct kvm_vcpu *vcpu;
7528
6755bae8
ZA		 7529 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7530 printk_once(KERN_WARNING
7531 "kvm: SMP vm created on host with unstable TSC; "
7532 "guest TSC will not be reliable\n");
c447e76b
LL		 7533
7534 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7535
c447e76b 7536 return vcpu;
26e5215f 7537}
e9b11c17 7538
26e5215f
AK		 7539int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7540{
7541 int r;
e9b11c17 7542
19efffa2 7543 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7544 r = vcpu_load(vcpu);
7545 if (r)
7546 return r;
d28bc9dd 7547 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7548 kvm_mmu_setup(vcpu);
e9b11c17 7549 vcpu_put(vcpu);
26e5215f 7550 return r;
e9b11c17
ZX		 7551}
7552
31928aa5 7553void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7554{
8fe8ab46 7555 struct msr_data msr;
332967a3 7556 struct kvm *kvm = vcpu->kvm;
42897d86 7557
31928aa5
DD		 7558 if (vcpu_load(vcpu))
7559 return;
8fe8ab46
WA		 7560 msr.data = 0x0;
7561 msr.index = MSR_IA32_TSC;
7562 msr.host_initiated = true;
7563 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7564 vcpu_put(vcpu);
7565
630994b3
MT		 7566 if (!kvmclock_periodic_sync)
7567 return;
7568
332967a3
AJ		 7569 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7570 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7571}
7572
d40ccc62 7573void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7574{
9fc77441 7575 int r;
344d9588
GN		 7576 vcpu->arch.apf.msr_val = 0;
7577
9fc77441
MT		 7578 r = vcpu_load(vcpu);
7579 BUG_ON(r);
e9b11c17
ZX		 7580 kvm_mmu_unload(vcpu);
7581 vcpu_put(vcpu);
7582
7583 kvm_x86_ops->vcpu_free(vcpu);
7584}
7585
d28bc9dd 7586void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7587{
e69fab5d
PB		 7588 vcpu->arch.hflags = 0;
7589
c43203ca 7590 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7591 atomic_set(&vcpu->arch.nmi_queued, 0);
7592 vcpu->arch.nmi_pending = 0;
448fa4a9 7593 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7594 kvm_clear_interrupt_queue(vcpu);
7595 kvm_clear_exception_queue(vcpu);
448fa4a9 7596
42dbaa5a 7597 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7598 kvm_update_dr0123(vcpu);
6f43ed01 7599 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7600 kvm_update_dr6(vcpu);
42dbaa5a 7601 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7602 kvm_update_dr7(vcpu);
42dbaa5a 7603
1119022c
NA		 7604 vcpu->arch.cr2 = 0;
7605
3842d135 7606 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7607 vcpu->arch.apf.msr_val = 0;
c9aaa895 7608 vcpu->arch.st.msr_val = 0;
3842d135 7609
12f9a48f
GC		 7610 kvmclock_reset(vcpu);
7611
af585b92
GN		 7612 kvm_clear_async_pf_completion_queue(vcpu);
7613 kvm_async_pf_hash_reset(vcpu);
7614 vcpu->arch.apf.halted = false;
3842d135 7615
64d60670 7616 if (!init_event) {
d28bc9dd 7617 kvm_pmu_reset(vcpu);
64d60670
PB		 7618 vcpu->arch.smbase = 0x30000;
7619 }
f5132b01 7620
66f7b72e
JS		 7621 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7622 vcpu->arch.regs_avail = ~0;
7623 vcpu->arch.regs_dirty = ~0;
7624
d28bc9dd 7625 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7626}
7627
2b4a273b 7628void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7629{
7630 struct kvm_segment cs;
7631
7632 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7633 cs.selector = vector << 8;
7634 cs.base = vector << 12;
7635 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7636 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7637}
7638
13a34e06 7639int kvm_arch_hardware_enable(void)
e9b11c17 7640{
ca84d1a2
ZA		 7641 struct kvm *kvm;
7642 struct kvm_vcpu *vcpu;
7643 int i;
0dd6a6ed
ZA		 7644 int ret;
7645 u64 local_tsc;
7646 u64 max_tsc = 0;
7647 bool stable, backwards_tsc = false;
18863bdd
AK		 7648
7649 kvm_shared_msr_cpu_online();
13a34e06 7650 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7651 if (ret != 0)
7652 return ret;
7653
4ea1636b 7654 local_tsc = rdtsc();
0dd6a6ed
ZA		 7655 stable = !check_tsc_unstable();
7656 list_for_each_entry(kvm, &vm_list, vm_list) {
7657 kvm_for_each_vcpu(i, vcpu, kvm) {
7658 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7659 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7660 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7661 backwards_tsc = true;
7662 if (vcpu->arch.last_host_tsc > max_tsc)
7663 max_tsc = vcpu->arch.last_host_tsc;
7664 }
7665 }
7666 }
7667
7668 /*
7669 * Sometimes, even reliable TSCs go backwards. This happens on
7670 * platforms that reset TSC during suspend or hibernate actions, but
7671 * maintain synchronization. We must compensate. Fortunately, we can
7672 * detect that condition here, which happens early in CPU bringup,
7673 * before any KVM threads can be running. Unfortunately, we can't
7674 * bring the TSCs fully up to date with real time, as we aren't yet far
7675 * enough into CPU bringup that we know how much real time has actually
108b249c 7676 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7677 * variables that haven't been updated yet.
7678 *
7679 * So we simply find the maximum observed TSC above, then record the
7680 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7681 * the adjustment will be applied. Note that we accumulate
7682 * adjustments, in case multiple suspend cycles happen before some VCPU
7683 * gets a chance to run again. In the event that no KVM threads get a
7684 * chance to run, we will miss the entire elapsed period, as we'll have
7685 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7686 * loose cycle time. This isn't too big a deal, since the loss will be
7687 * uniform across all VCPUs (not to mention the scenario is extremely
7688 * unlikely). It is possible that a second hibernate recovery happens
7689 * much faster than a first, causing the observed TSC here to be
7690 * smaller; this would require additional padding adjustment, which is
7691 * why we set last_host_tsc to the local tsc observed here.
7692 *
7693 * N.B. - this code below runs only on platforms with reliable TSC,
7694 * as that is the only way backwards_tsc is set above. Also note
7695 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7696 * have the same delta_cyc adjustment applied if backwards_tsc
7697 * is detected. Note further, this adjustment is only done once,
7698 * as we reset last_host_tsc on all VCPUs to stop this from being
7699 * called multiple times (one for each physical CPU bringup).
7700 *
4a969980 7701 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7702 * will be compensated by the logic in vcpu_load, which sets the TSC to
7703 * catchup mode. This will catchup all VCPUs to real time, but cannot
7704 * guarantee that they stay in perfect synchronization.
7705 */
7706 if (backwards_tsc) {
7707 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7708 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7709 list_for_each_entry(kvm, &vm_list, vm_list) {
7710 kvm_for_each_vcpu(i, vcpu, kvm) {
7711 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7712 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7713 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7714 }
7715
7716 /*
7717 * We have to disable TSC offset matching.. if you were
7718 * booting a VM while issuing an S4 host suspend....
7719 * you may have some problem. Solving this issue is
7720 * left as an exercise to the reader.
7721 */
7722 kvm->arch.last_tsc_nsec = 0;
7723 kvm->arch.last_tsc_write = 0;
7724 }
7725
7726 }
7727 return 0;
e9b11c17
ZX		 7728}
7729
13a34e06 7730void kvm_arch_hardware_disable(void)
e9b11c17 7731{
13a34e06
RK		 7732 kvm_x86_ops->hardware_disable();
7733 drop_user_return_notifiers();
e9b11c17
ZX		 7734}
7735
7736int kvm_arch_hardware_setup(void)
7737{
9e9c3fe4
NA		 7738 int r;
7739
7740 r = kvm_x86_ops->hardware_setup();
7741 if (r != 0)
7742 return r;
7743
35181e86
HZ		 7744 if (kvm_has_tsc_control) {
7745 /*
7746 * Make sure the user can only configure tsc_khz values that
7747 * fit into a signed integer.
7748 * A min value is not calculated needed because it will always
7749 * be 1 on all machines.
7750 */
7751 u64 max = min(0x7fffffffULL,
7752 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7753 kvm_max_guest_tsc_khz = max;
7754
ad721883 7755 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7756 }
ad721883 7757
9e9c3fe4
NA		 7758 kvm_init_msr_list();
7759 return 0;
e9b11c17
ZX		 7760}
7761
7762void kvm_arch_hardware_unsetup(void)
7763{
7764 kvm_x86_ops->hardware_unsetup();
7765}
7766
7767void kvm_arch_check_processor_compat(void *rtn)
7768{
7769 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7770}
7771
7772bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7773{
7774 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7775}
7776EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7777
7778bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7779{
7780 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7781}
7782
54e9818f 7783struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7784EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7785
e9b11c17
ZX		 7786int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7787{
7788 struct page *page;
7789 struct kvm *kvm;
7790 int r;
7791
7792 BUG_ON(vcpu->kvm == NULL);
7793 kvm = vcpu->kvm;
7794
d62caabb 7795 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7796 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7797 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7798 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7799 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7800 else
a4535290 7801 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7802
7803 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7804 if (!page) {
7805 r = -ENOMEM;
7806 goto fail;
7807 }
ad312c7c 7808 vcpu->arch.pio_data = page_address(page);
e9b11c17 7809
cc578287 7810 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7811
e9b11c17
ZX		 7812 r = kvm_mmu_create(vcpu);
7813 if (r < 0)
7814 goto fail_free_pio_data;
7815
7816 if (irqchip_in_kernel(kvm)) {
7817 r = kvm_create_lapic(vcpu);
7818 if (r < 0)
7819 goto fail_mmu_destroy;
54e9818f
GN		 7820 } else
7821 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7822
890ca9ae
HY		 7823 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7824 GFP_KERNEL);
7825 if (!vcpu->arch.mce_banks) {
7826 r = -ENOMEM;
443c39bc 7827 goto fail_free_lapic;
890ca9ae
HY		 7828 }
7829 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7830
f1797359
WY		 7831 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7832 r = -ENOMEM;
f5f48ee1 7833 goto fail_free_mce_banks;
f1797359 7834 }
f5f48ee1 7835
0ee6a517 7836 fx_init(vcpu);
66f7b72e 7837
ba904635 7838 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7839 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7840
7841 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7842 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7843
5a4f55cd
EK		 7844 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7845
74545705
RK		 7846 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7847
af585b92 7848 kvm_async_pf_hash_reset(vcpu);
f5132b01 7849 kvm_pmu_init(vcpu);
af585b92 7850
1c1a9ce9
SR		 7851 vcpu->arch.pending_external_vector = -1;
7852
5c919412
AS		 7853 kvm_hv_vcpu_init(vcpu);
7854
e9b11c17 7855 return 0;
0ee6a517 7856
f5f48ee1
SY		 7857fail_free_mce_banks:
7858 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7859fail_free_lapic:
7860 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7861fail_mmu_destroy:
7862 kvm_mmu_destroy(vcpu);
7863fail_free_pio_data:
ad312c7c 7864 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7865fail:
7866 return r;
7867}
7868
7869void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7870{
f656ce01
MT		 7871 int idx;
7872
1f4b34f8 7873 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7874 kvm_pmu_destroy(vcpu);
36cb93fd 7875 kfree(vcpu->arch.mce_banks);
e9b11c17 7876 kvm_free_lapic(vcpu);
f656ce01 7877 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7878 kvm_mmu_destroy(vcpu);
f656ce01 7879 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7880 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7881 if (!lapic_in_kernel(vcpu))
54e9818f 7882 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7883}
d19a9cd2 7884
e790d9ef
RK		 7885void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7886{
ae97a3b8 7887 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7888}
7889
e08b9637 7890int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7891{
e08b9637
CO		 7892 if (type)
7893 return -EINVAL;
7894
6ef768fa 7895 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7896 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7897 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7898 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7899 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7900
5550af4d
SY		 7901 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7902 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7903 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7904 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7905 &kvm->arch.irq_sources_bitmap);
5550af4d 7906
038f8c11 7907 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7908 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 7909 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 7910 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7911
108b249c 7912 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 7913 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7914
7e44e449 7915 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7916 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7917
0eb05bf2 7918 kvm_page_track_init(kvm);
13d268ca 7919 kvm_mmu_init_vm(kvm);
0eb05bf2 7920
03543133
SS		 7921 if (kvm_x86_ops->vm_init)
7922 return kvm_x86_ops->vm_init(kvm);
7923
d89f5eff 7924 return 0;
d19a9cd2
ZX		 7925}
7926
7927static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7928{
9fc77441
MT		 7929 int r;
7930 r = vcpu_load(vcpu);
7931 BUG_ON(r);
d19a9cd2
ZX		 7932 kvm_mmu_unload(vcpu);
7933 vcpu_put(vcpu);
7934}
7935
7936static void kvm_free_vcpus(struct kvm *kvm)
7937{
7938 unsigned int i;
988a2cae 7939 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7940
7941 /*
7942 * Unpin any mmu pages first.
7943 */
af585b92
GN		 7944 kvm_for_each_vcpu(i, vcpu, kvm) {
7945 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7946 kvm_unload_vcpu_mmu(vcpu);
af585b92 7947 }
988a2cae
GN		 7948 kvm_for_each_vcpu(i, vcpu, kvm)
7949 kvm_arch_vcpu_free(vcpu);
7950
7951 mutex_lock(&kvm->lock);
7952 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7953 kvm->vcpus[i] = NULL;
d19a9cd2 7954
988a2cae
GN		 7955 atomic_set(&kvm->online_vcpus, 0);
7956 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7957}
7958
ad8ba2cd
SY		 7959void kvm_arch_sync_events(struct kvm *kvm)
7960{
332967a3 7961 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7962 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7963 kvm_free_all_assigned_devices(kvm);
aea924f6 7964 kvm_free_pit(kvm);
ad8ba2cd
SY		 7965}
7966
1d8007bd 7967int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7968{
7969 int i, r;
25188b99 7970 unsigned long hva;
f0d648bd
PB		 7971 struct kvm_memslots *slots = kvm_memslots(kvm);
7972 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7973
7974 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7975 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7976 return -EINVAL;
9da0e4d5 7977
f0d648bd
PB		 7978 slot = id_to_memslot(slots, id);
7979 if (size) {
b21629da 7980 if (slot->npages)
f0d648bd
PB		 7981 return -EEXIST;
7982
7983 /*
7984 * MAP_SHARED to prevent internal slot pages from being moved
7985 * by fork()/COW.
7986 */
7987 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7988 MAP_SHARED | MAP_ANONYMOUS, 0);
7989 if (IS_ERR((void *)hva))
7990 return PTR_ERR((void *)hva);
7991 } else {
7992 if (!slot->npages)
7993 return 0;
7994
7995 hva = 0;
7996 }
7997
7998 old = *slot;
9da0e4d5 7999 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8000 struct kvm_userspace_memory_region m;
9da0e4d5 8001
1d8007bd
PB		 8002 m.slot = id | (i << 16);
8003 m.flags = 0;
8004 m.guest_phys_addr = gpa;
f0d648bd 8005 m.userspace_addr = hva;
1d8007bd 8006 m.memory_size = size;
9da0e4d5
PB		 8007 r = __kvm_set_memory_region(kvm, &m);
8008 if (r < 0)
8009 return r;
8010 }
8011
f0d648bd
PB		 8012 if (!size) {
8013 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8014 WARN_ON(r < 0);
8015 }
8016
9da0e4d5
PB		 8017 return 0;
8018}
8019EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8020
1d8007bd 8021int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8022{
8023 int r;
8024
8025 mutex_lock(&kvm->slots_lock);
1d8007bd 8026 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8027 mutex_unlock(&kvm->slots_lock);
8028
8029 return r;
8030}
8031EXPORT_SYMBOL_GPL(x86_set_memory_region);
8032
d19a9cd2
ZX		 8033void kvm_arch_destroy_vm(struct kvm *kvm)
8034{
27469d29
AH		 8035 if (current->mm == kvm->mm) {
8036 /*
8037 * Free memory regions allocated on behalf of userspace,
8038 * unless the the memory map has changed due to process exit
8039 * or fd copying.
8040 */
1d8007bd
PB		 8041 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8042 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8043 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8044 }
03543133
SS		 8045 if (kvm_x86_ops->vm_destroy)
8046 kvm_x86_ops->vm_destroy(kvm);
6eb55818 8047 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 8048 kfree(kvm->arch.vpic);
8049 kfree(kvm->arch.vioapic);
d19a9cd2 8050 kvm_free_vcpus(kvm);
af1bae54 8051 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8052 kvm_mmu_uninit_vm(kvm);
d19a9cd2 8053}
0de10343 8054
5587027c 8055void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8056 struct kvm_memory_slot *dont)
8057{
8058 int i;
8059
d89cc617
TY		 8060 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8061 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8062 kvfree(free->arch.rmap[i]);
d89cc617 8063 free->arch.rmap[i] = NULL;
77d11309 8064 }
d89cc617
TY		 8065 if (i == 0)
8066 continue;
8067
8068 if (!dont || free->arch.lpage_info[i - 1] !=
8069 dont->arch.lpage_info[i - 1]) {
548ef284 8070 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8071 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8072 }
8073 }
21ebbeda
XG		 8074
8075 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8076}
8077
5587027c
AK		 8078int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8079 unsigned long npages)
db3fe4eb
TY		 8080{
8081 int i;
8082
d89cc617 8083 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8084 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8085 unsigned long ugfn;
8086 int lpages;
d89cc617 8087 int level = i + 1;
db3fe4eb
TY		 8088
8089 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8090 slot->base_gfn, level) + 1;
8091
d89cc617
TY		 8092 slot->arch.rmap[i] =
8093 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
8094 if (!slot->arch.rmap[i])
77d11309 8095 goto out_free;
d89cc617
TY		 8096 if (i == 0)
8097 continue;
77d11309 8098
92f94f1e
XG		 8099 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
8100 if (!linfo)
db3fe4eb
TY		 8101 goto out_free;
8102
92f94f1e
XG		 8103 slot->arch.lpage_info[i - 1] = linfo;
8104
db3fe4eb 8105 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8106 linfo[0].disallow_lpage = 1;
db3fe4eb 8107 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8108 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8109 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8110 /*
8111 * If the gfn and userspace address are not aligned wrt each
8112 * other, or if explicitly asked to, disable large page
8113 * support for this slot
8114 */
8115 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8116 !kvm_largepages_enabled()) {
8117 unsigned long j;
8118
8119 for (j = 0; j < lpages; ++j)
92f94f1e 8120 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8121 }
8122 }
8123
21ebbeda
XG		 8124 if (kvm_page_track_create_memslot(slot, npages))
8125 goto out_free;
8126
db3fe4eb
TY		 8127 return 0;
8128
8129out_free:
d89cc617 8130 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8131 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8132 slot->arch.rmap[i] = NULL;
8133 if (i == 0)
8134 continue;
8135
548ef284 8136 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8137 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8138 }
8139 return -ENOMEM;
8140}
8141
15f46015 8142void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8143{
e6dff7d1
TY		 8144 /*
8145 * memslots->generation has been incremented.
8146 * mmio generation may have reached its maximum value.
8147 */
54bf36aa 8148 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8149}
8150
f7784b8e
MT		 8151int kvm_arch_prepare_memory_region(struct kvm *kvm,
8152 struct kvm_memory_slot *memslot,
09170a49 8153 const struct kvm_userspace_memory_region *mem,
7b6195a9 8154 enum kvm_mr_change change)
0de10343 8155{
f7784b8e
MT		 8156 return 0;
8157}
8158
88178fd4
KH		 8159static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8160 struct kvm_memory_slot *new)
8161{
8162 /* Still write protect RO slot */
8163 if (new->flags & KVM_MEM_READONLY) {
8164 kvm_mmu_slot_remove_write_access(kvm, new);
8165 return;
8166 }
8167
8168 /*
8169 * Call kvm_x86_ops dirty logging hooks when they are valid.
8170 *
8171 * kvm_x86_ops->slot_disable_log_dirty is called when:
8172 *
8173 * - KVM_MR_CREATE with dirty logging is disabled
8174 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8175 *
8176 * The reason is, in case of PML, we need to set D-bit for any slots
8177 * with dirty logging disabled in order to eliminate unnecessary GPA
8178 * logging in PML buffer (and potential PML buffer full VMEXT). This
8179 * guarantees leaving PML enabled during guest's lifetime won't have
8180 * any additonal overhead from PML when guest is running with dirty
8181 * logging disabled for memory slots.
8182 *
8183 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8184 * to dirty logging mode.
8185 *
8186 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8187 *
8188 * In case of write protect:
8189 *
8190 * Write protect all pages for dirty logging.
8191 *
8192 * All the sptes including the large sptes which point to this
8193 * slot are set to readonly. We can not create any new large
8194 * spte on this slot until the end of the logging.
8195 *
8196 * See the comments in fast_page_fault().
8197 */
8198 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8199 if (kvm_x86_ops->slot_enable_log_dirty)
8200 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8201 else
8202 kvm_mmu_slot_remove_write_access(kvm, new);
8203 } else {
8204 if (kvm_x86_ops->slot_disable_log_dirty)
8205 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8206 }
8207}
8208
f7784b8e 8209void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8210 const struct kvm_userspace_memory_region *mem,
8482644a 8211 const struct kvm_memory_slot *old,
f36f3f28 8212 const struct kvm_memory_slot *new,
8482644a 8213 enum kvm_mr_change change)
f7784b8e 8214{
8482644a 8215 int nr_mmu_pages = 0;
f7784b8e 8216
48c0e4e9
XG		 8217 if (!kvm->arch.n_requested_mmu_pages)
8218 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8219
48c0e4e9 8220 if (nr_mmu_pages)
0de10343 8221 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8222
3ea3b7fa
WL		 8223 /*
8224 * Dirty logging tracks sptes in 4k granularity, meaning that large
8225 * sptes have to be split. If live migration is successful, the guest
8226 * in the source machine will be destroyed and large sptes will be
8227 * created in the destination. However, if the guest continues to run
8228 * in the source machine (for example if live migration fails), small
8229 * sptes will remain around and cause bad performance.
8230 *
8231 * Scan sptes if dirty logging has been stopped, dropping those
8232 * which can be collapsed into a single large-page spte. Later
8233 * page faults will create the large-page sptes.
8234 */
8235 if ((change != KVM_MR_DELETE) &&
8236 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8237 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8238 kvm_mmu_zap_collapsible_sptes(kvm, new);
8239
c972f3b1 8240 /*
88178fd4 8241 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8242 *
88178fd4
KH		 8243 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8244 * been zapped so no dirty logging staff is needed for old slot. For
8245 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8246 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8247 *
8248 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8249 */
88178fd4 8250 if (change != KVM_MR_DELETE)
f36f3f28 8251 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8252}
1d737c8a 8253
2df72e9b 8254void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8255{
6ca18b69 8256 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8257}
8258
2df72e9b
MT		 8259void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8260 struct kvm_memory_slot *slot)
8261{
ae7cd873 8262 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8263}
8264
5d9bc648
PB		 8265static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8266{
8267 if (!list_empty_careful(&vcpu->async_pf.done))
8268 return true;
8269
8270 if (kvm_apic_has_events(vcpu))
8271 return true;
8272
8273 if (vcpu->arch.pv.pv_unhalted)
8274 return true;
8275
8276 if (atomic_read(&vcpu->arch.nmi_queued))
8277 return true;
8278
73917739
PB		 8279 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8280 return true;
8281
5d9bc648
PB		 8282 if (kvm_arch_interrupt_allowed(vcpu) &&
8283 kvm_cpu_has_interrupt(vcpu))
8284 return true;
8285
1f4b34f8
AS		 8286 if (kvm_hv_has_stimer_pending(vcpu))
8287 return true;
8288
5d9bc648
PB		 8289 return false;
8290}
8291
1d737c8a
ZX		 8292int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8293{
b6b8a145
JK		 8294 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8295 kvm_x86_ops->check_nested_events(vcpu, false);
8296
5d9bc648 8297 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8298}
5736199a 8299
b6d33834 8300int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8301{
b6d33834 8302 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8303}
78646121
GN		 8304
8305int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8306{
8307 return kvm_x86_ops->interrupt_allowed(vcpu);
8308}
229456fc 8309
82b32774 8310unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8311{
82b32774
NA		 8312 if (is_64_bit_mode(vcpu))
8313 return kvm_rip_read(vcpu);
8314 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8315 kvm_rip_read(vcpu));
8316}
8317EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8318
82b32774
NA		 8319bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8320{
8321 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8322}
8323EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8324
94fe45da
JK		 8325unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8326{
8327 unsigned long rflags;
8328
8329 rflags = kvm_x86_ops->get_rflags(vcpu);
8330 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8331 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8332 return rflags;
8333}
8334EXPORT_SYMBOL_GPL(kvm_get_rflags);
8335
6addfc42 8336static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8337{
8338 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8339 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8340 rflags |= X86_EFLAGS_TF;
94fe45da 8341 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8342}
8343
8344void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8345{
8346 __kvm_set_rflags(vcpu, rflags);
3842d135 8347 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8348}
8349EXPORT_SYMBOL_GPL(kvm_set_rflags);
8350
56028d08
GN		 8351void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8352{
8353 int r;
8354
fb67e14f 8355 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8356 work->wakeup_all)
56028d08
GN		 8357 return;
8358
8359 r = kvm_mmu_reload(vcpu);
8360 if (unlikely(r))
8361 return;
8362
fb67e14f
XG		 8363 if (!vcpu->arch.mmu.direct_map &&
8364 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8365 return;
8366
56028d08
GN		 8367 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8368}
8369
af585b92
GN		 8370static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8371{
8372 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8373}
8374
8375static inline u32 kvm_async_pf_next_probe(u32 key)
8376{
8377 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8378}
8379
8380static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8381{
8382 u32 key = kvm_async_pf_hash_fn(gfn);
8383
8384 while (vcpu->arch.apf.gfns[key] != ~0)
8385 key = kvm_async_pf_next_probe(key);
8386
8387 vcpu->arch.apf.gfns[key] = gfn;
8388}
8389
8390static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8391{
8392 int i;
8393 u32 key = kvm_async_pf_hash_fn(gfn);
8394
8395 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8396 (vcpu->arch.apf.gfns[key] != gfn &&
8397 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8398 key = kvm_async_pf_next_probe(key);
8399
8400 return key;
8401}
8402
8403bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8404{
8405 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8406}
8407
8408static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8409{
8410 u32 i, j, k;
8411
8412 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8413 while (true) {
8414 vcpu->arch.apf.gfns[i] = ~0;
8415 do {
8416 j = kvm_async_pf_next_probe(j);
8417 if (vcpu->arch.apf.gfns[j] == ~0)
8418 return;
8419 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8420 /*
8421 * k lies cyclically in ]i,j]
8422 * | i.k.j |
8423 * |....j i.k.| or |.k..j i...|
8424 */
8425 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8426 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8427 i = j;
8428 }
8429}
8430
7c90705b
GN		 8431static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8432{
8433
8434 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8435 sizeof(val));
8436}
8437
af585b92
GN		 8438void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8439 struct kvm_async_pf *work)
8440{
6389ee94
AK		 8441 struct x86_exception fault;
8442
7c90705b 8443 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8444 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8445
8446 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8447 (vcpu->arch.apf.send_user_only &&
8448 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8449 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8450 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8451 fault.vector = PF_VECTOR;
8452 fault.error_code_valid = true;
8453 fault.error_code = 0;
8454 fault.nested_page_fault = false;
8455 fault.address = work->arch.token;
8456 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8457 }
af585b92
GN		 8458}
8459
8460void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8461 struct kvm_async_pf *work)
8462{
6389ee94
AK		 8463 struct x86_exception fault;
8464
7c90705b 8465 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8466 if (work->wakeup_all)
7c90705b
GN		 8467 work->arch.token = ~0; /* broadcast wakeup */
8468 else
8469 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8470
8471 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8472 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8473 fault.vector = PF_VECTOR;
8474 fault.error_code_valid = true;
8475 fault.error_code = 0;
8476 fault.nested_page_fault = false;
8477 fault.address = work->arch.token;
8478 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8479 }
e6d53e3b 8480 vcpu->arch.apf.halted = false;
a4fa1635 8481 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8482}
8483
8484bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8485{
8486 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8487 return true;
8488 else
8489 return !kvm_event_needs_reinjection(vcpu) &&
8490 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8491}
8492
5544eb9b
PB		 8493void kvm_arch_start_assignment(struct kvm *kvm)
8494{
8495 atomic_inc(&kvm->arch.assigned_device_count);
8496}
8497EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8498
8499void kvm_arch_end_assignment(struct kvm *kvm)
8500{
8501 atomic_dec(&kvm->arch.assigned_device_count);
8502}
8503EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8504
8505bool kvm_arch_has_assigned_device(struct kvm *kvm)
8506{
8507 return atomic_read(&kvm->arch.assigned_device_count);
8508}
8509EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8510
e0f0bbc5
AW		 8511void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8512{
8513 atomic_inc(&kvm->arch.noncoherent_dma_count);
8514}
8515EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8516
8517void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8518{
8519 atomic_dec(&kvm->arch.noncoherent_dma_count);
8520}
8521EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8522
8523bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8524{
8525 return atomic_read(&kvm->arch.noncoherent_dma_count);
8526}
8527EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8528
14717e20
AW		 8529bool kvm_arch_has_irq_bypass(void)
8530{
8531 return kvm_x86_ops->update_pi_irte != NULL;
8532}
8533
87276880
FW		 8534int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8535 struct irq_bypass_producer *prod)
8536{
8537 struct kvm_kernel_irqfd *irqfd =
8538 container_of(cons, struct kvm_kernel_irqfd, consumer);
8539
14717e20 8540 irqfd->producer = prod;
87276880 8541
14717e20
AW		 8542 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8543 prod->irq, irqfd->gsi, 1);
87276880
FW		 8544}
8545
8546void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8547 struct irq_bypass_producer *prod)
8548{
8549 int ret;
8550 struct kvm_kernel_irqfd *irqfd =
8551 container_of(cons, struct kvm_kernel_irqfd, consumer);
8552
87276880
FW		 8553 WARN_ON(irqfd->producer != prod);
8554 irqfd->producer = NULL;
8555
8556 /*
8557 * When producer of consumer is unregistered, we change back to
8558 * remapped mode, so we can re-use the current implementation
bb3541f1 8559 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8560 * int this case doesn't want to receive the interrupts.
8561 */
8562 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8563 if (ret)
8564 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8565 " fails: %d\n", irqfd->consumer.token, ret);
8566}
8567
8568int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8569 uint32_t guest_irq, bool set)
8570{
8571 if (!kvm_x86_ops->update_pi_irte)
8572 return -EINVAL;
8573
8574 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8575}
8576
52004014
FW		 8577bool kvm_vector_hashing_enabled(void)
8578{
8579 return vector_hashing;
8580}
8581EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8582
229456fc 8583EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8584EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8585EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8586EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8587EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8588EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8589EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8590EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8591EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8592EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8593EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8594EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8595EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8596EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8597EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8598EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8599EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8600EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8601EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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