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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
88197e6a | 21 | #include "ioapic.h" |
1d737c8a | 22 | #include "mmu.h" |
7837699f | 23 | #include "i8254.h" |
37817f29 | 24 | #include "tss.h" |
5fdbf976 | 25 | #include "kvm_cache_regs.h" |
2f728d66 | 26 | #include "kvm_emulate.h" |
26eef70c | 27 | #include "x86.h" |
00b27a3e | 28 | #include "cpuid.h" |
474a5bb9 | 29 | #include "pmu.h" |
e83d5887 | 30 | #include "hyperv.h" |
8df14af4 | 31 | #include "lapic.h" |
313a3dc7 | 32 | |
18068523 | 33 | #include <linux/clocksource.h> |
4d5c5d0f | 34 | #include <linux/interrupt.h> |
313a3dc7 CO |
35 | #include <linux/kvm.h> |
36 | #include <linux/fs.h> | |
37 | #include <linux/vmalloc.h> | |
1767e931 PG |
38 | #include <linux/export.h> |
39 | #include <linux/moduleparam.h> | |
0de10343 | 40 | #include <linux/mman.h> |
2bacc55c | 41 | #include <linux/highmem.h> |
19de40a8 | 42 | #include <linux/iommu.h> |
62c476c7 | 43 | #include <linux/intel-iommu.h> |
c8076604 | 44 | #include <linux/cpufreq.h> |
18863bdd | 45 | #include <linux/user-return-notifier.h> |
a983fb23 | 46 | #include <linux/srcu.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
ff9d07a0 | 48 | #include <linux/perf_event.h> |
7bee342a | 49 | #include <linux/uaccess.h> |
af585b92 | 50 | #include <linux/hash.h> |
a1b60c1c | 51 | #include <linux/pci.h> |
16e8d74d MT |
52 | #include <linux/timekeeper_internal.h> |
53 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
54 | #include <linux/kvm_irqfd.h> |
55 | #include <linux/irqbypass.h> | |
3905f9ad | 56 | #include <linux/sched/stat.h> |
0c5f81da | 57 | #include <linux/sched/isolation.h> |
d0ec49d4 | 58 | #include <linux/mem_encrypt.h> |
72c3c0fe | 59 | #include <linux/entry-kvm.h> |
3905f9ad | 60 | |
aec51dc4 | 61 | #include <trace/events/kvm.h> |
2ed152af | 62 | |
24f1e32c | 63 | #include <asm/debugreg.h> |
d825ed0a | 64 | #include <asm/msr.h> |
a5f61300 | 65 | #include <asm/desc.h> |
890ca9ae | 66 | #include <asm/mce.h> |
f89e32e0 | 67 | #include <linux/kernel_stat.h> |
78f7f1e5 | 68 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 69 | #include <asm/pvclock.h> |
217fc9cf | 70 | #include <asm/div64.h> |
efc64404 | 71 | #include <asm/irq_remapping.h> |
b0c39dc6 | 72 | #include <asm/mshyperv.h> |
0092e434 | 73 | #include <asm/hypervisor.h> |
9715092f | 74 | #include <asm/tlbflush.h> |
bf8c55d8 | 75 | #include <asm/intel_pt.h> |
b3dc0695 | 76 | #include <asm/emulate_prefix.h> |
dd2cb348 | 77 | #include <clocksource/hyperv_timer.h> |
043405e1 | 78 | |
d1898b73 DH |
79 | #define CREATE_TRACE_POINTS |
80 | #include "trace.h" | |
81 | ||
313a3dc7 | 82 | #define MAX_IO_MSRS 256 |
890ca9ae | 83 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
84 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
85 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 86 | |
0f65dd70 | 87 | #define emul_to_vcpu(ctxt) \ |
c9b8b07c | 88 | ((struct kvm_vcpu *)(ctxt)->vcpu) |
0f65dd70 | 89 | |
50a37eb4 JR |
90 | /* EFER defaults: |
91 | * - enable syscall per default because its emulated by KVM | |
92 | * - enable LME and LMA per default on 64 bit KVM | |
93 | */ | |
94 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
95 | static |
96 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 97 | #else |
1260edbe | 98 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 99 | #endif |
313a3dc7 | 100 | |
b11306b5 SC |
101 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
102 | ||
c519265f RK |
103 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
104 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 105 | |
cb142eb7 | 106 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 107 | static void process_nmi(struct kvm_vcpu *vcpu); |
1f7becf1 | 108 | static void process_smi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 109 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 110 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
111 | static void store_regs(struct kvm_vcpu *vcpu); |
112 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 113 | |
afaf0b2f | 114 | struct kvm_x86_ops kvm_x86_ops __read_mostly; |
5fdbf976 | 115 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 116 | |
893590c7 | 117 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 118 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 119 | |
fab0aa3b EM |
120 | static bool __read_mostly report_ignored_msrs = true; |
121 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); | |
122 | ||
4c27625b | 123 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
124 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
125 | ||
630994b3 MT |
126 | static bool __read_mostly kvmclock_periodic_sync = true; |
127 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
128 | ||
893590c7 | 129 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 130 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 131 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 132 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
133 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
134 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
135 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
136 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
137 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
138 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
92a1f12d | 139 | |
cc578287 | 140 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 141 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
142 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
143 | ||
c3941d9e SC |
144 | /* |
145 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
146 | * adaptive tuning starting from default advancment of 1000ns. '0' disables | |
147 | * advancement entirely. Any other value is used as-is and disables adaptive | |
148 | * tuning, i.e. allows priveleged userspace to set an exact advancement time. | |
149 | */ | |
150 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 151 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 152 | |
52004014 FW |
153 | static bool __read_mostly vector_hashing = true; |
154 | module_param(vector_hashing, bool, S_IRUGO); | |
155 | ||
c4ae60e4 LA |
156 | bool __read_mostly enable_vmware_backdoor = false; |
157 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
158 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
159 | ||
6c86eedc WL |
160 | static bool __read_mostly force_emulation_prefix = false; |
161 | module_param(force_emulation_prefix, bool, S_IRUGO); | |
162 | ||
0c5f81da WL |
163 | int __read_mostly pi_inject_timer = -1; |
164 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
165 | ||
7e34fbd0 SC |
166 | /* |
167 | * Restoring the host value for MSRs that are only consumed when running in | |
168 | * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU | |
169 | * returns to userspace, i.e. the kernel can run with the guest's value. | |
170 | */ | |
171 | #define KVM_MAX_NR_USER_RETURN_MSRS 16 | |
18863bdd | 172 | |
7e34fbd0 | 173 | struct kvm_user_return_msrs_global { |
18863bdd | 174 | int nr; |
7e34fbd0 | 175 | u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
176 | }; |
177 | ||
7e34fbd0 | 178 | struct kvm_user_return_msrs { |
18863bdd AK |
179 | struct user_return_notifier urn; |
180 | bool registered; | |
7e34fbd0 | 181 | struct kvm_user_return_msr_values { |
2bf78fa7 SY |
182 | u64 host; |
183 | u64 curr; | |
7e34fbd0 | 184 | } values[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
185 | }; |
186 | ||
7e34fbd0 SC |
187 | static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global; |
188 | static struct kvm_user_return_msrs __percpu *user_return_msrs; | |
18863bdd | 189 | |
cfc48181 SC |
190 | #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ |
191 | | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | |
192 | | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | |
193 | | XFEATURE_MASK_PKRU) | |
194 | ||
91661989 SC |
195 | u64 __read_mostly host_efer; |
196 | EXPORT_SYMBOL_GPL(host_efer); | |
197 | ||
b96e6506 | 198 | bool __read_mostly allow_smaller_maxphyaddr = 0; |
3edd6839 MG |
199 | EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); |
200 | ||
86137773 TL |
201 | u64 __read_mostly host_xss; |
202 | EXPORT_SYMBOL_GPL(host_xss); | |
408e9a31 PB |
203 | u64 __read_mostly supported_xss; |
204 | EXPORT_SYMBOL_GPL(supported_xss); | |
139a12cf | 205 | |
417bc304 | 206 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
812756a8 EGE |
207 | VCPU_STAT("pf_fixed", pf_fixed), |
208 | VCPU_STAT("pf_guest", pf_guest), | |
209 | VCPU_STAT("tlb_flush", tlb_flush), | |
210 | VCPU_STAT("invlpg", invlpg), | |
211 | VCPU_STAT("exits", exits), | |
212 | VCPU_STAT("io_exits", io_exits), | |
213 | VCPU_STAT("mmio_exits", mmio_exits), | |
214 | VCPU_STAT("signal_exits", signal_exits), | |
215 | VCPU_STAT("irq_window", irq_window_exits), | |
216 | VCPU_STAT("nmi_window", nmi_window_exits), | |
217 | VCPU_STAT("halt_exits", halt_exits), | |
218 | VCPU_STAT("halt_successful_poll", halt_successful_poll), | |
219 | VCPU_STAT("halt_attempted_poll", halt_attempted_poll), | |
220 | VCPU_STAT("halt_poll_invalid", halt_poll_invalid), | |
221 | VCPU_STAT("halt_wakeup", halt_wakeup), | |
222 | VCPU_STAT("hypercalls", hypercalls), | |
223 | VCPU_STAT("request_irq", request_irq_exits), | |
224 | VCPU_STAT("irq_exits", irq_exits), | |
225 | VCPU_STAT("host_state_reload", host_state_reload), | |
226 | VCPU_STAT("fpu_reload", fpu_reload), | |
227 | VCPU_STAT("insn_emulation", insn_emulation), | |
228 | VCPU_STAT("insn_emulation_fail", insn_emulation_fail), | |
229 | VCPU_STAT("irq_injections", irq_injections), | |
230 | VCPU_STAT("nmi_injections", nmi_injections), | |
231 | VCPU_STAT("req_event", req_event), | |
232 | VCPU_STAT("l1d_flush", l1d_flush), | |
cb953129 DM |
233 | VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns), |
234 | VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns), | |
812756a8 EGE |
235 | VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped), |
236 | VM_STAT("mmu_pte_write", mmu_pte_write), | |
237 | VM_STAT("mmu_pte_updated", mmu_pte_updated), | |
238 | VM_STAT("mmu_pde_zapped", mmu_pde_zapped), | |
239 | VM_STAT("mmu_flooded", mmu_flooded), | |
240 | VM_STAT("mmu_recycled", mmu_recycled), | |
241 | VM_STAT("mmu_cache_miss", mmu_cache_miss), | |
242 | VM_STAT("mmu_unsync", mmu_unsync), | |
243 | VM_STAT("remote_tlb_flush", remote_tlb_flush), | |
244 | VM_STAT("largepages", lpages, .mode = 0444), | |
245 | VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444), | |
246 | VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions), | |
417bc304 HB |
247 | { NULL } |
248 | }; | |
249 | ||
2acf923e | 250 | u64 __read_mostly host_xcr0; |
cfc48181 SC |
251 | u64 __read_mostly supported_xcr0; |
252 | EXPORT_SYMBOL_GPL(supported_xcr0); | |
2acf923e | 253 | |
80fbd280 | 254 | static struct kmem_cache *x86_fpu_cache; |
b666a4b6 | 255 | |
c9b8b07c SC |
256 | static struct kmem_cache *x86_emulator_cache; |
257 | ||
6abe9c13 PX |
258 | /* |
259 | * When called, it means the previous get/set msr reached an invalid msr. | |
cc4cb017 | 260 | * Return true if we want to ignore/silent this failed msr access. |
6abe9c13 | 261 | */ |
cc4cb017 ML |
262 | static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr, |
263 | u64 data, bool write) | |
6abe9c13 PX |
264 | { |
265 | const char *op = write ? "wrmsr" : "rdmsr"; | |
266 | ||
267 | if (ignore_msrs) { | |
268 | if (report_ignored_msrs) | |
d383b314 TI |
269 | kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", |
270 | op, msr, data); | |
6abe9c13 | 271 | /* Mask the error */ |
cc4cb017 | 272 | return true; |
6abe9c13 | 273 | } else { |
d383b314 TI |
274 | kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", |
275 | op, msr, data); | |
cc4cb017 | 276 | return false; |
6abe9c13 PX |
277 | } |
278 | } | |
279 | ||
c9b8b07c SC |
280 | static struct kmem_cache *kvm_alloc_emulator_cache(void) |
281 | { | |
06add254 SC |
282 | unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); |
283 | unsigned int size = sizeof(struct x86_emulate_ctxt); | |
284 | ||
285 | return kmem_cache_create_usercopy("x86_emulator", size, | |
c9b8b07c | 286 | __alignof__(struct x86_emulate_ctxt), |
06add254 SC |
287 | SLAB_ACCOUNT, useroffset, |
288 | size - useroffset, NULL); | |
c9b8b07c SC |
289 | } |
290 | ||
b6785def | 291 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 292 | |
af585b92 GN |
293 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
294 | { | |
295 | int i; | |
dd03bcaa | 296 | for (i = 0; i < ASYNC_PF_PER_VCPU; i++) |
af585b92 GN |
297 | vcpu->arch.apf.gfns[i] = ~0; |
298 | } | |
299 | ||
18863bdd AK |
300 | static void kvm_on_user_return(struct user_return_notifier *urn) |
301 | { | |
302 | unsigned slot; | |
7e34fbd0 SC |
303 | struct kvm_user_return_msrs *msrs |
304 | = container_of(urn, struct kvm_user_return_msrs, urn); | |
305 | struct kvm_user_return_msr_values *values; | |
1650b4eb IA |
306 | unsigned long flags; |
307 | ||
308 | /* | |
309 | * Disabling irqs at this point since the following code could be | |
310 | * interrupted and executed through kvm_arch_hardware_disable() | |
311 | */ | |
312 | local_irq_save(flags); | |
7e34fbd0 SC |
313 | if (msrs->registered) { |
314 | msrs->registered = false; | |
1650b4eb IA |
315 | user_return_notifier_unregister(urn); |
316 | } | |
317 | local_irq_restore(flags); | |
7e34fbd0 SC |
318 | for (slot = 0; slot < user_return_msrs_global.nr; ++slot) { |
319 | values = &msrs->values[slot]; | |
2bf78fa7 | 320 | if (values->host != values->curr) { |
7e34fbd0 | 321 | wrmsrl(user_return_msrs_global.msrs[slot], values->host); |
2bf78fa7 | 322 | values->curr = values->host; |
18863bdd AK |
323 | } |
324 | } | |
18863bdd AK |
325 | } |
326 | ||
7e34fbd0 | 327 | void kvm_define_user_return_msr(unsigned slot, u32 msr) |
2bf78fa7 | 328 | { |
7e34fbd0 SC |
329 | BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS); |
330 | user_return_msrs_global.msrs[slot] = msr; | |
331 | if (slot >= user_return_msrs_global.nr) | |
332 | user_return_msrs_global.nr = slot + 1; | |
18863bdd | 333 | } |
7e34fbd0 | 334 | EXPORT_SYMBOL_GPL(kvm_define_user_return_msr); |
18863bdd | 335 | |
7e34fbd0 | 336 | static void kvm_user_return_msr_cpu_online(void) |
18863bdd | 337 | { |
05c19c2f | 338 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 339 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
05c19c2f SC |
340 | u64 value; |
341 | int i; | |
18863bdd | 342 | |
7e34fbd0 SC |
343 | for (i = 0; i < user_return_msrs_global.nr; ++i) { |
344 | rdmsrl_safe(user_return_msrs_global.msrs[i], &value); | |
345 | msrs->values[i].host = value; | |
346 | msrs->values[i].curr = value; | |
05c19c2f | 347 | } |
18863bdd AK |
348 | } |
349 | ||
7e34fbd0 | 350 | int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 351 | { |
013f6a5d | 352 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 353 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
8b3c3104 | 354 | int err; |
18863bdd | 355 | |
7e34fbd0 SC |
356 | value = (value & mask) | (msrs->values[slot].host & ~mask); |
357 | if (value == msrs->values[slot].curr) | |
8b3c3104 | 358 | return 0; |
7e34fbd0 | 359 | err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value); |
8b3c3104 AH |
360 | if (err) |
361 | return 1; | |
362 | ||
7e34fbd0 SC |
363 | msrs->values[slot].curr = value; |
364 | if (!msrs->registered) { | |
365 | msrs->urn.on_user_return = kvm_on_user_return; | |
366 | user_return_notifier_register(&msrs->urn); | |
367 | msrs->registered = true; | |
18863bdd | 368 | } |
8b3c3104 | 369 | return 0; |
18863bdd | 370 | } |
7e34fbd0 | 371 | EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); |
18863bdd | 372 | |
13a34e06 | 373 | static void drop_user_return_notifiers(void) |
3548bab5 | 374 | { |
013f6a5d | 375 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 376 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
3548bab5 | 377 | |
7e34fbd0 SC |
378 | if (msrs->registered) |
379 | kvm_on_user_return(&msrs->urn); | |
3548bab5 AK |
380 | } |
381 | ||
6866b83e CO |
382 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
383 | { | |
8a5a87d9 | 384 | return vcpu->arch.apic_base; |
6866b83e CO |
385 | } |
386 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
387 | ||
58871649 JM |
388 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
389 | { | |
390 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
391 | } | |
392 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
393 | ||
58cb628d JK |
394 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
395 | { | |
58871649 JM |
396 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
397 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
d6321d49 RK |
398 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | |
399 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); | |
58cb628d | 400 | |
58871649 | 401 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 402 | return 1; |
58871649 JM |
403 | if (!msr_info->host_initiated) { |
404 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
405 | return 1; | |
406 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
407 | return 1; | |
408 | } | |
58cb628d JK |
409 | |
410 | kvm_lapic_set_base(vcpu, msr_info->data); | |
4abaffce | 411 | kvm_recalculate_apic_map(vcpu->kvm); |
58cb628d | 412 | return 0; |
6866b83e CO |
413 | } |
414 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
415 | ||
3ebccdf3 | 416 | asmlinkage __visible noinstr void kvm_spurious_fault(void) |
e3ba45b8 GL |
417 | { |
418 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 419 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
420 | } |
421 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
422 | ||
3fd28fce ED |
423 | #define EXCPT_BENIGN 0 |
424 | #define EXCPT_CONTRIBUTORY 1 | |
425 | #define EXCPT_PF 2 | |
426 | ||
427 | static int exception_class(int vector) | |
428 | { | |
429 | switch (vector) { | |
430 | case PF_VECTOR: | |
431 | return EXCPT_PF; | |
432 | case DE_VECTOR: | |
433 | case TS_VECTOR: | |
434 | case NP_VECTOR: | |
435 | case SS_VECTOR: | |
436 | case GP_VECTOR: | |
437 | return EXCPT_CONTRIBUTORY; | |
438 | default: | |
439 | break; | |
440 | } | |
441 | return EXCPT_BENIGN; | |
442 | } | |
443 | ||
d6e8c854 NA |
444 | #define EXCPT_FAULT 0 |
445 | #define EXCPT_TRAP 1 | |
446 | #define EXCPT_ABORT 2 | |
447 | #define EXCPT_INTERRUPT 3 | |
448 | ||
449 | static int exception_type(int vector) | |
450 | { | |
451 | unsigned int mask; | |
452 | ||
453 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
454 | return EXCPT_INTERRUPT; | |
455 | ||
456 | mask = 1 << vector; | |
457 | ||
458 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
459 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
460 | return EXCPT_TRAP; | |
461 | ||
462 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
463 | return EXCPT_ABORT; | |
464 | ||
465 | /* Reserved exceptions will result in fault */ | |
466 | return EXCPT_FAULT; | |
467 | } | |
468 | ||
da998b46 JM |
469 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
470 | { | |
471 | unsigned nr = vcpu->arch.exception.nr; | |
472 | bool has_payload = vcpu->arch.exception.has_payload; | |
473 | unsigned long payload = vcpu->arch.exception.payload; | |
474 | ||
475 | if (!has_payload) | |
476 | return; | |
477 | ||
478 | switch (nr) { | |
f10c729f JM |
479 | case DB_VECTOR: |
480 | /* | |
481 | * "Certain debug exceptions may clear bit 0-3. The | |
482 | * remaining contents of the DR6 register are never | |
483 | * cleared by the processor". | |
484 | */ | |
485 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
486 | /* | |
487 | * DR6.RTM is set by all #DB exceptions that don't clear it. | |
488 | */ | |
489 | vcpu->arch.dr6 |= DR6_RTM; | |
490 | vcpu->arch.dr6 |= payload; | |
491 | /* | |
492 | * Bit 16 should be set in the payload whenever the #DB | |
493 | * exception should clear DR6.RTM. This makes the payload | |
494 | * compatible with the pending debug exceptions under VMX. | |
495 | * Though not currently documented in the SDM, this also | |
496 | * makes the payload compatible with the exit qualification | |
497 | * for #DB exceptions under VMX. | |
498 | */ | |
499 | vcpu->arch.dr6 ^= payload & DR6_RTM; | |
307f1cfa OU |
500 | |
501 | /* | |
502 | * The #DB payload is defined as compatible with the 'pending | |
503 | * debug exceptions' field under VMX, not DR6. While bit 12 is | |
504 | * defined in the 'pending debug exceptions' field (enabled | |
505 | * breakpoint), it is reserved and must be zero in DR6. | |
506 | */ | |
507 | vcpu->arch.dr6 &= ~BIT(12); | |
f10c729f | 508 | break; |
da998b46 JM |
509 | case PF_VECTOR: |
510 | vcpu->arch.cr2 = payload; | |
511 | break; | |
512 | } | |
513 | ||
514 | vcpu->arch.exception.has_payload = false; | |
515 | vcpu->arch.exception.payload = 0; | |
516 | } | |
517 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
518 | ||
3fd28fce | 519 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 520 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 521 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
522 | { |
523 | u32 prev_nr; | |
524 | int class1, class2; | |
525 | ||
3842d135 AK |
526 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
527 | ||
664f8e26 | 528 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 529 | queue: |
3ffb2468 NA |
530 | if (has_error && !is_protmode(vcpu)) |
531 | has_error = false; | |
664f8e26 WL |
532 | if (reinject) { |
533 | /* | |
534 | * On vmentry, vcpu->arch.exception.pending is only | |
535 | * true if an event injection was blocked by | |
536 | * nested_run_pending. In that case, however, | |
537 | * vcpu_enter_guest requests an immediate exit, | |
538 | * and the guest shouldn't proceed far enough to | |
539 | * need reinjection. | |
540 | */ | |
541 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
542 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
543 | if (WARN_ON_ONCE(has_payload)) { |
544 | /* | |
545 | * A reinjected event has already | |
546 | * delivered its payload. | |
547 | */ | |
548 | has_payload = false; | |
549 | payload = 0; | |
550 | } | |
664f8e26 WL |
551 | } else { |
552 | vcpu->arch.exception.pending = true; | |
553 | vcpu->arch.exception.injected = false; | |
554 | } | |
3fd28fce ED |
555 | vcpu->arch.exception.has_error_code = has_error; |
556 | vcpu->arch.exception.nr = nr; | |
557 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
558 | vcpu->arch.exception.has_payload = has_payload; |
559 | vcpu->arch.exception.payload = payload; | |
a06230b6 | 560 | if (!is_guest_mode(vcpu)) |
da998b46 | 561 | kvm_deliver_exception_payload(vcpu); |
3fd28fce ED |
562 | return; |
563 | } | |
564 | ||
565 | /* to check exception */ | |
566 | prev_nr = vcpu->arch.exception.nr; | |
567 | if (prev_nr == DF_VECTOR) { | |
568 | /* triple fault -> shutdown */ | |
a8eeb04a | 569 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
570 | return; |
571 | } | |
572 | class1 = exception_class(prev_nr); | |
573 | class2 = exception_class(nr); | |
574 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
575 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
576 | /* |
577 | * Generate double fault per SDM Table 5-5. Set | |
578 | * exception.pending = true so that the double fault | |
579 | * can trigger a nested vmexit. | |
580 | */ | |
3fd28fce | 581 | vcpu->arch.exception.pending = true; |
664f8e26 | 582 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
583 | vcpu->arch.exception.has_error_code = true; |
584 | vcpu->arch.exception.nr = DF_VECTOR; | |
585 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
586 | vcpu->arch.exception.has_payload = false; |
587 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
588 | } else |
589 | /* replace previous exception with a new one in a hope | |
590 | that instruction re-execution will regenerate lost | |
591 | exception */ | |
592 | goto queue; | |
593 | } | |
594 | ||
298101da AK |
595 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
596 | { | |
91e86d22 | 597 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
598 | } |
599 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
600 | ||
ce7ddec4 JR |
601 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
602 | { | |
91e86d22 | 603 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
604 | } |
605 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
606 | ||
4d5523cf PB |
607 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
608 | unsigned long payload) | |
f10c729f JM |
609 | { |
610 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
611 | } | |
4d5523cf | 612 | EXPORT_SYMBOL_GPL(kvm_queue_exception_p); |
f10c729f | 613 | |
da998b46 JM |
614 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
615 | u32 error_code, unsigned long payload) | |
616 | { | |
617 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
618 | true, payload, false); | |
619 | } | |
620 | ||
6affcbed | 621 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 622 | { |
db8fcefa AP |
623 | if (err) |
624 | kvm_inject_gp(vcpu, 0); | |
625 | else | |
6affcbed KH |
626 | return kvm_skip_emulated_instruction(vcpu); |
627 | ||
628 | return 1; | |
db8fcefa AP |
629 | } |
630 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 631 | |
6389ee94 | 632 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
633 | { |
634 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
635 | vcpu->arch.exception.nested_apf = |
636 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 637 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 638 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
639 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
640 | } else { | |
641 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
642 | fault->address); | |
643 | } | |
c3c91fee | 644 | } |
27d6c865 | 645 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 646 | |
53b3d8e9 SC |
647 | bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
648 | struct x86_exception *fault) | |
d4f8cf66 | 649 | { |
0cd665bd | 650 | struct kvm_mmu *fault_mmu; |
53b3d8e9 SC |
651 | WARN_ON_ONCE(fault->vector != PF_VECTOR); |
652 | ||
0cd665bd PB |
653 | fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : |
654 | vcpu->arch.walk_mmu; | |
ef54bcfe | 655 | |
ee1fa209 JS |
656 | /* |
657 | * Invalidate the TLB entry for the faulting address, if it exists, | |
658 | * else the access will fault indefinitely (and to emulate hardware). | |
659 | */ | |
660 | if ((fault->error_code & PFERR_PRESENT_MASK) && | |
661 | !(fault->error_code & PFERR_RSVD_MASK)) | |
662 | kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, | |
663 | fault_mmu->root_hpa); | |
664 | ||
665 | fault_mmu->inject_page_fault(vcpu, fault); | |
ef54bcfe | 666 | return fault->nested_page_fault; |
d4f8cf66 | 667 | } |
53b3d8e9 | 668 | EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); |
d4f8cf66 | 669 | |
3419ffc8 SY |
670 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
671 | { | |
7460fb4a AK |
672 | atomic_inc(&vcpu->arch.nmi_queued); |
673 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
674 | } |
675 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
676 | ||
298101da AK |
677 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
678 | { | |
91e86d22 | 679 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
680 | } |
681 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
682 | ||
ce7ddec4 JR |
683 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
684 | { | |
91e86d22 | 685 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
686 | } |
687 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
688 | ||
0a79b009 AK |
689 | /* |
690 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
691 | * a #GP and return false. | |
692 | */ | |
693 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 694 | { |
afaf0b2f | 695 | if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl) |
0a79b009 AK |
696 | return true; |
697 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
698 | return false; | |
298101da | 699 | } |
0a79b009 | 700 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 701 | |
16f8a6f9 NA |
702 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
703 | { | |
704 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
705 | return true; | |
706 | ||
707 | kvm_queue_exception(vcpu, UD_VECTOR); | |
708 | return false; | |
709 | } | |
710 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
711 | ||
ec92fe44 JR |
712 | /* |
713 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 714 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
715 | * can read from guest physical or from the guest's guest physical memory. |
716 | */ | |
717 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
718 | gfn_t ngfn, void *data, int offset, int len, | |
719 | u32 access) | |
720 | { | |
54987b7a | 721 | struct x86_exception exception; |
ec92fe44 JR |
722 | gfn_t real_gfn; |
723 | gpa_t ngpa; | |
724 | ||
725 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 726 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
727 | if (real_gfn == UNMAPPED_GVA) |
728 | return -EFAULT; | |
729 | ||
730 | real_gfn = gpa_to_gfn(real_gfn); | |
731 | ||
54bf36aa | 732 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
733 | } |
734 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
735 | ||
69b0049a | 736 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
737 | void *data, int offset, int len, u32 access) |
738 | { | |
739 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
740 | data, offset, len, access); | |
741 | } | |
742 | ||
16cfacc8 SC |
743 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
744 | { | |
745 | return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) | | |
746 | rsvd_bits(1, 2); | |
747 | } | |
748 | ||
a03490ed | 749 | /* |
16cfacc8 | 750 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 751 | */ |
ff03a073 | 752 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
753 | { |
754 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
755 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
756 | int i; | |
757 | int ret; | |
ff03a073 | 758 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 759 | |
ff03a073 JR |
760 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
761 | offset * sizeof(u64), sizeof(pdpte), | |
762 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
763 | if (ret < 0) { |
764 | ret = 0; | |
765 | goto out; | |
766 | } | |
767 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
812f30b2 | 768 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 769 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
a03490ed CO |
770 | ret = 0; |
771 | goto out; | |
772 | } | |
773 | } | |
774 | ret = 1; | |
775 | ||
ff03a073 | 776 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
cb3c1e2f SC |
777 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); |
778 | ||
a03490ed | 779 | out: |
a03490ed CO |
780 | |
781 | return ret; | |
782 | } | |
cc4b6871 | 783 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 784 | |
9ed38ffa | 785 | bool pdptrs_changed(struct kvm_vcpu *vcpu) |
d835dfec | 786 | { |
ff03a073 | 787 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
3d06b8bf JR |
788 | int offset; |
789 | gfn_t gfn; | |
d835dfec AK |
790 | int r; |
791 | ||
bf03d4f9 | 792 | if (!is_pae_paging(vcpu)) |
d835dfec AK |
793 | return false; |
794 | ||
cb3c1e2f | 795 | if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) |
6de4f3ad AK |
796 | return true; |
797 | ||
a512177e PB |
798 | gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; |
799 | offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
800 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
801 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec | 802 | if (r < 0) |
7f7f0d9c | 803 | return true; |
d835dfec | 804 | |
7f7f0d9c | 805 | return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 806 | } |
9ed38ffa | 807 | EXPORT_SYMBOL_GPL(pdptrs_changed); |
d835dfec | 808 | |
f27ad38a TL |
809 | void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) |
810 | { | |
811 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; | |
812 | ||
813 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { | |
814 | kvm_clear_async_pf_completion_queue(vcpu); | |
815 | kvm_async_pf_hash_reset(vcpu); | |
816 | } | |
817 | ||
818 | if ((cr0 ^ old_cr0) & update_bits) | |
819 | kvm_mmu_reset_context(vcpu); | |
820 | ||
821 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && | |
822 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
823 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
824 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); | |
825 | } | |
826 | EXPORT_SYMBOL_GPL(kvm_post_set_cr0); | |
827 | ||
49a9b07e | 828 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 829 | { |
aad82703 | 830 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d42e3fae | 831 | unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; |
aad82703 | 832 | |
f9a48e6a AK |
833 | cr0 |= X86_CR0_ET; |
834 | ||
ab344828 | 835 | #ifdef CONFIG_X86_64 |
0f12244f GN |
836 | if (cr0 & 0xffffffff00000000UL) |
837 | return 1; | |
ab344828 GN |
838 | #endif |
839 | ||
840 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 841 | |
0f12244f GN |
842 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
843 | return 1; | |
a03490ed | 844 | |
0f12244f GN |
845 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
846 | return 1; | |
a03490ed | 847 | |
a03490ed | 848 | #ifdef CONFIG_X86_64 |
05487215 SC |
849 | if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && |
850 | (cr0 & X86_CR0_PG)) { | |
851 | int cs_db, cs_l; | |
852 | ||
853 | if (!is_pae(vcpu)) | |
854 | return 1; | |
855 | kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
856 | if (cs_l) | |
0f12244f | 857 | return 1; |
a03490ed | 858 | } |
05487215 SC |
859 | #endif |
860 | if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && | |
861 | is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && | |
862 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) | |
863 | return 1; | |
a03490ed | 864 | |
ad756a16 MJ |
865 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
866 | return 1; | |
867 | ||
afaf0b2f | 868 | kvm_x86_ops.set_cr0(vcpu, cr0); |
a03490ed | 869 | |
f27ad38a | 870 | kvm_post_set_cr0(vcpu, old_cr0, cr0); |
b18d5431 | 871 | |
0f12244f GN |
872 | return 0; |
873 | } | |
2d3ad1f4 | 874 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 875 | |
2d3ad1f4 | 876 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 877 | { |
49a9b07e | 878 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 879 | } |
2d3ad1f4 | 880 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 881 | |
139a12cf | 882 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 883 | { |
16809ecd TL |
884 | if (vcpu->arch.guest_state_protected) |
885 | return; | |
886 | ||
139a12cf AL |
887 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
888 | ||
889 | if (vcpu->arch.xcr0 != host_xcr0) | |
890 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
891 | ||
892 | if (vcpu->arch.xsaves_enabled && | |
893 | vcpu->arch.ia32_xss != host_xss) | |
894 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
895 | } | |
37486135 BM |
896 | |
897 | if (static_cpu_has(X86_FEATURE_PKU) && | |
898 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
899 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && | |
900 | vcpu->arch.pkru != vcpu->arch.host_pkru) | |
901 | __write_pkru(vcpu->arch.pkru); | |
42bdf991 | 902 | } |
139a12cf | 903 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 904 | |
139a12cf | 905 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 906 | { |
16809ecd TL |
907 | if (vcpu->arch.guest_state_protected) |
908 | return; | |
909 | ||
37486135 BM |
910 | if (static_cpu_has(X86_FEATURE_PKU) && |
911 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
912 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { | |
913 | vcpu->arch.pkru = rdpkru(); | |
914 | if (vcpu->arch.pkru != vcpu->arch.host_pkru) | |
915 | __write_pkru(vcpu->arch.host_pkru); | |
916 | } | |
917 | ||
139a12cf AL |
918 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
919 | ||
920 | if (vcpu->arch.xcr0 != host_xcr0) | |
921 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
922 | ||
923 | if (vcpu->arch.xsaves_enabled && | |
924 | vcpu->arch.ia32_xss != host_xss) | |
925 | wrmsrl(MSR_IA32_XSS, host_xss); | |
926 | } | |
927 | ||
42bdf991 | 928 | } |
139a12cf | 929 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 930 | |
69b0049a | 931 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 932 | { |
56c103ec LJ |
933 | u64 xcr0 = xcr; |
934 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 935 | u64 valid_bits; |
2acf923e DC |
936 | |
937 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
938 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
939 | return 1; | |
d91cab78 | 940 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 941 | return 1; |
d91cab78 | 942 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 943 | return 1; |
46c34cb0 PB |
944 | |
945 | /* | |
946 | * Do not allow the guest to set bits that we do not support | |
947 | * saving. However, xcr0 bit 0 is always set, even if the | |
948 | * emulated CPU does not support XSAVE (see fx_init). | |
949 | */ | |
d91cab78 | 950 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 951 | if (xcr0 & ~valid_bits) |
2acf923e | 952 | return 1; |
46c34cb0 | 953 | |
d91cab78 DH |
954 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
955 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
956 | return 1; |
957 | ||
d91cab78 DH |
958 | if (xcr0 & XFEATURE_MASK_AVX512) { |
959 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 960 | return 1; |
d91cab78 | 961 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
962 | return 1; |
963 | } | |
2acf923e | 964 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 965 | |
d91cab78 | 966 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
aedbaf4f | 967 | kvm_update_cpuid_runtime(vcpu); |
2acf923e DC |
968 | return 0; |
969 | } | |
970 | ||
971 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
972 | { | |
afaf0b2f | 973 | if (kvm_x86_ops.get_cpl(vcpu) != 0 || |
764bcbc5 | 974 | __kvm_set_xcr(vcpu, index, xcr)) { |
2acf923e DC |
975 | kvm_inject_gp(vcpu, 0); |
976 | return 1; | |
977 | } | |
978 | return 0; | |
979 | } | |
980 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
981 | ||
ee69c92b | 982 | bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 983 | { |
b11306b5 | 984 | if (cr4 & cr4_reserved_bits) |
ee69c92b | 985 | return false; |
b9baba86 | 986 | |
b899c132 | 987 | if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) |
ee69c92b | 988 | return false; |
3ca94192 | 989 | |
ee69c92b | 990 | return kvm_x86_ops.is_valid_cr4(vcpu, cr4); |
3ca94192 | 991 | } |
ee69c92b | 992 | EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); |
3ca94192 | 993 | |
5b51cb13 TL |
994 | void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) |
995 | { | |
996 | unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
997 | X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; | |
998 | ||
999 | if (((cr4 ^ old_cr4) & mmu_role_bits) || | |
1000 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
1001 | kvm_mmu_reset_context(vcpu); | |
3ca94192 | 1002 | } |
5b51cb13 | 1003 | EXPORT_SYMBOL_GPL(kvm_post_set_cr4); |
3ca94192 WL |
1004 | |
1005 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1006 | { | |
1007 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
1008 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
cb957adb | 1009 | X86_CR4_SMEP; |
3ca94192 | 1010 | |
ee69c92b | 1011 | if (!kvm_is_valid_cr4(vcpu, cr4)) |
ae3e61e1 PB |
1012 | return 1; |
1013 | ||
a03490ed | 1014 | if (is_long_mode(vcpu)) { |
0f12244f GN |
1015 | if (!(cr4 & X86_CR4_PAE)) |
1016 | return 1; | |
d74fcfc1 SC |
1017 | if ((cr4 ^ old_cr4) & X86_CR4_LA57) |
1018 | return 1; | |
a2edf57f AK |
1019 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
1020 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
1021 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
1022 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
1023 | return 1; |
1024 | ||
ad756a16 | 1025 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 1026 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
1027 | return 1; |
1028 | ||
1029 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
1030 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
1031 | return 1; | |
1032 | } | |
1033 | ||
c2fe3cd4 | 1034 | kvm_x86_ops.set_cr4(vcpu, cr4); |
a03490ed | 1035 | |
5b51cb13 | 1036 | kvm_post_set_cr4(vcpu, old_cr4, cr4); |
2acf923e | 1037 | |
0f12244f GN |
1038 | return 0; |
1039 | } | |
2d3ad1f4 | 1040 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 1041 | |
2390218b | 1042 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 1043 | { |
ade61e28 | 1044 | bool skip_tlb_flush = false; |
ac146235 | 1045 | #ifdef CONFIG_X86_64 |
c19986fe JS |
1046 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
1047 | ||
ade61e28 | 1048 | if (pcid_enabled) { |
208320ba JS |
1049 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
1050 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
ade61e28 | 1051 | } |
ac146235 | 1052 | #endif |
9d88fca7 | 1053 | |
9f8fe504 | 1054 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
956bf353 JS |
1055 | if (!skip_tlb_flush) { |
1056 | kvm_mmu_sync_roots(vcpu); | |
eeeb4f67 | 1057 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
956bf353 | 1058 | } |
0f12244f | 1059 | return 0; |
d835dfec AK |
1060 | } |
1061 | ||
d1cd3ce9 | 1062 | if (is_long_mode(vcpu) && |
0107973a | 1063 | (cr3 & vcpu->arch.cr3_lm_rsvd_bits)) |
d1cd3ce9 | 1064 | return 1; |
bf03d4f9 PB |
1065 | else if (is_pae_paging(vcpu) && |
1066 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 1067 | return 1; |
a03490ed | 1068 | |
be01e8e2 | 1069 | kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush); |
0f12244f | 1070 | vcpu->arch.cr3 = cr3; |
cb3c1e2f | 1071 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
7c390d35 | 1072 | |
0f12244f GN |
1073 | return 0; |
1074 | } | |
2d3ad1f4 | 1075 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1076 | |
eea1cff9 | 1077 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1078 | { |
0f12244f GN |
1079 | if (cr8 & CR8_RESERVED_BITS) |
1080 | return 1; | |
35754c98 | 1081 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1082 | kvm_lapic_set_tpr(vcpu, cr8); |
1083 | else | |
ad312c7c | 1084 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1085 | return 0; |
1086 | } | |
2d3ad1f4 | 1087 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1088 | |
2d3ad1f4 | 1089 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1090 | { |
35754c98 | 1091 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1092 | return kvm_lapic_get_cr8(vcpu); |
1093 | else | |
ad312c7c | 1094 | return vcpu->arch.cr8; |
a03490ed | 1095 | } |
2d3ad1f4 | 1096 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1097 | |
ae561ede NA |
1098 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1099 | { | |
1100 | int i; | |
1101 | ||
1102 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1103 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1104 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
1105 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
1106 | } | |
1107 | } | |
1108 | ||
7c86663b | 1109 | void kvm_update_dr7(struct kvm_vcpu *vcpu) |
c8639010 JK |
1110 | { |
1111 | unsigned long dr7; | |
1112 | ||
1113 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1114 | dr7 = vcpu->arch.guest_debug_dr7; | |
1115 | else | |
1116 | dr7 = vcpu->arch.dr7; | |
afaf0b2f | 1117 | kvm_x86_ops.set_dr7(vcpu, dr7); |
360b948d PB |
1118 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1119 | if (dr7 & DR7_BP_EN_MASK) | |
1120 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 | 1121 | } |
7c86663b | 1122 | EXPORT_SYMBOL_GPL(kvm_update_dr7); |
c8639010 | 1123 | |
6f43ed01 NA |
1124 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1125 | { | |
1126 | u64 fixed = DR6_FIXED_1; | |
1127 | ||
d6321d49 | 1128 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 NA |
1129 | fixed |= DR6_RTM; |
1130 | return fixed; | |
1131 | } | |
1132 | ||
338dbc97 | 1133 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1134 | { |
ea740059 MP |
1135 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1136 | ||
020df079 GN |
1137 | switch (dr) { |
1138 | case 0 ... 3: | |
ea740059 | 1139 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1140 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1141 | vcpu->arch.eff_db[dr] = val; | |
1142 | break; | |
1143 | case 4: | |
020df079 | 1144 | case 6: |
f5f6145e | 1145 | if (!kvm_dr6_valid(val)) |
338dbc97 | 1146 | return -1; /* #GP */ |
6f43ed01 | 1147 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
020df079 GN |
1148 | break; |
1149 | case 5: | |
020df079 | 1150 | default: /* 7 */ |
b91991bf | 1151 | if (!kvm_dr7_valid(val)) |
338dbc97 | 1152 | return -1; /* #GP */ |
020df079 | 1153 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1154 | kvm_update_dr7(vcpu); |
020df079 GN |
1155 | break; |
1156 | } | |
1157 | ||
1158 | return 0; | |
1159 | } | |
338dbc97 GN |
1160 | |
1161 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
1162 | { | |
16f8a6f9 | 1163 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 1164 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
1165 | return 1; |
1166 | } | |
1167 | return 0; | |
338dbc97 | 1168 | } |
020df079 GN |
1169 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
1170 | ||
16f8a6f9 | 1171 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1172 | { |
ea740059 MP |
1173 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1174 | ||
020df079 GN |
1175 | switch (dr) { |
1176 | case 0 ... 3: | |
ea740059 | 1177 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1178 | break; |
1179 | case 4: | |
020df079 | 1180 | case 6: |
5679b803 | 1181 | *val = vcpu->arch.dr6; |
020df079 GN |
1182 | break; |
1183 | case 5: | |
020df079 GN |
1184 | default: /* 7 */ |
1185 | *val = vcpu->arch.dr7; | |
1186 | break; | |
1187 | } | |
338dbc97 GN |
1188 | return 0; |
1189 | } | |
020df079 GN |
1190 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1191 | ||
022cd0e8 AK |
1192 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
1193 | { | |
de3cd117 | 1194 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 AK |
1195 | u64 data; |
1196 | int err; | |
1197 | ||
c6702c9d | 1198 | err = kvm_pmu_rdpmc(vcpu, ecx, &data); |
022cd0e8 AK |
1199 | if (err) |
1200 | return err; | |
de3cd117 SC |
1201 | kvm_rax_write(vcpu, (u32)data); |
1202 | kvm_rdx_write(vcpu, data >> 32); | |
022cd0e8 AK |
1203 | return err; |
1204 | } | |
1205 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
1206 | ||
043405e1 CO |
1207 | /* |
1208 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1209 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1210 | * | |
7a5ee6ed CQ |
1211 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) |
1212 | * extract the supported MSRs from the related const lists. | |
1213 | * msrs_to_save is selected from the msrs_to_save_all to reflect the | |
e3267cbb | 1214 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
7a5ee6ed | 1215 | * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs |
62ef68bb | 1216 | * may depend on host virtualization features rather than host cpu features. |
043405e1 | 1217 | */ |
e3267cbb | 1218 | |
7a5ee6ed | 1219 | static const u32 msrs_to_save_all[] = { |
043405e1 | 1220 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1221 | MSR_STAR, |
043405e1 CO |
1222 | #ifdef CONFIG_X86_64 |
1223 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1224 | #endif | |
b3897a49 | 1225 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1226 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1227 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1228 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1229 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1230 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1231 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1232 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1233 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1234 | MSR_IA32_UMWAIT_CONTROL, |
1235 | ||
e2ada66e JM |
1236 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
1237 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, | |
1238 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, | |
1239 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1240 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, | |
1241 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1242 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1243 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
1244 | MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, | |
1245 | MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, | |
1246 | MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, | |
1247 | MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, | |
1248 | MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, | |
e2ada66e JM |
1249 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1250 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1251 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1252 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
1253 | MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, | |
1254 | MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, | |
1255 | MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, | |
1256 | MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, | |
1257 | MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, | |
043405e1 CO |
1258 | }; |
1259 | ||
7a5ee6ed | 1260 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; |
043405e1 CO |
1261 | static unsigned num_msrs_to_save; |
1262 | ||
7a5ee6ed | 1263 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1264 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1265 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1266 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1267 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1268 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1269 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1270 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1271 | HV_X64_MSR_RESET, |
11c4b1ca | 1272 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1273 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1274 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1275 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1276 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1277 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1278 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
f97f5a56 JD |
1279 | HV_X64_MSR_SYNDBG_OPTIONS, |
1280 | HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, | |
1281 | HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, | |
1282 | HV_X64_MSR_SYNDBG_PENDING_BUFFER, | |
a2e164e7 VK |
1283 | |
1284 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
557a961a | 1285 | MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, |
62ef68bb | 1286 | |
ba904635 | 1287 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 1288 | MSR_IA32_TSCDEADLINE, |
2bdb76c0 | 1289 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1290 | MSR_IA32_PERF_CAPABILITIES, |
043405e1 | 1291 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1292 | MSR_IA32_MCG_STATUS, |
1293 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1294 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1295 | MSR_IA32_SMBASE, |
52797bf9 | 1296 | MSR_SMI_COUNT, |
db2336a8 KH |
1297 | MSR_PLATFORM_INFO, |
1298 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1299 | MSR_AMD64_VIRT_SPEC_CTRL, |
6c6a2ab9 | 1300 | MSR_IA32_POWER_CTL, |
99634e3e | 1301 | MSR_IA32_UCODE_REV, |
191c8137 | 1302 | |
95c5c7c7 PB |
1303 | /* |
1304 | * The following list leaves out MSRs whose values are determined | |
1305 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1306 | * We always support the "true" VMX control MSRs, even if the host | |
1307 | * processor does not, so I am putting these registers here rather | |
7a5ee6ed | 1308 | * than in msrs_to_save_all. |
95c5c7c7 PB |
1309 | */ |
1310 | MSR_IA32_VMX_BASIC, | |
1311 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1312 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1313 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1314 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1315 | MSR_IA32_VMX_MISC, | |
1316 | MSR_IA32_VMX_CR0_FIXED0, | |
1317 | MSR_IA32_VMX_CR4_FIXED0, | |
1318 | MSR_IA32_VMX_VMCS_ENUM, | |
1319 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1320 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1321 | MSR_IA32_VMX_VMFUNC, | |
1322 | ||
191c8137 | 1323 | MSR_K7_HWCR, |
2d5ba19b | 1324 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1325 | }; |
1326 | ||
7a5ee6ed | 1327 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1328 | static unsigned num_emulated_msrs; |
1329 | ||
801e459a TL |
1330 | /* |
1331 | * List of msr numbers which are used to expose MSR-based features that | |
1332 | * can be used by a hypervisor to validate requested CPU features. | |
1333 | */ | |
7a5ee6ed | 1334 | static const u32 msr_based_features_all[] = { |
1389309c PB |
1335 | MSR_IA32_VMX_BASIC, |
1336 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1337 | MSR_IA32_VMX_PINBASED_CTLS, | |
1338 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1339 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1340 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1341 | MSR_IA32_VMX_EXIT_CTLS, | |
1342 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1343 | MSR_IA32_VMX_ENTRY_CTLS, | |
1344 | MSR_IA32_VMX_MISC, | |
1345 | MSR_IA32_VMX_CR0_FIXED0, | |
1346 | MSR_IA32_VMX_CR0_FIXED1, | |
1347 | MSR_IA32_VMX_CR4_FIXED0, | |
1348 | MSR_IA32_VMX_CR4_FIXED1, | |
1349 | MSR_IA32_VMX_VMCS_ENUM, | |
1350 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1351 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1352 | MSR_IA32_VMX_VMFUNC, | |
1353 | ||
d1d93fa9 | 1354 | MSR_F10H_DECFG, |
518e7b94 | 1355 | MSR_IA32_UCODE_REV, |
cd283252 | 1356 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1357 | MSR_IA32_PERF_CAPABILITIES, |
801e459a TL |
1358 | }; |
1359 | ||
7a5ee6ed | 1360 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; |
801e459a TL |
1361 | static unsigned int num_msr_based_features; |
1362 | ||
4d22c17c | 1363 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1364 | { |
4d22c17c | 1365 | u64 data = 0; |
5b76a3cf | 1366 | |
4d22c17c XL |
1367 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1368 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf | 1369 | |
b8e8c830 PB |
1370 | /* |
1371 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1372 | * the nested hypervisor runs with NX huge pages. If it is not, | |
1373 | * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other | |
1374 | * L1 guests, so it need not worry about its own (L2) guests. | |
1375 | */ | |
1376 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1377 | ||
5b76a3cf PB |
1378 | /* |
1379 | * If we're doing cache flushes (either "always" or "cond") | |
1380 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1381 | * If an outer hypervisor is doing the cache flush for us | |
1382 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1383 | * capability to the guest too, and if EPT is disabled we're not | |
1384 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1385 | * require a nested hypervisor to do a flush of its own. | |
1386 | */ | |
1387 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1388 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1389 | ||
0c54914d PB |
1390 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1391 | data |= ARCH_CAP_RDCL_NO; | |
1392 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1393 | data |= ARCH_CAP_SSB_NO; | |
1394 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1395 | data |= ARCH_CAP_MDS_NO; | |
1396 | ||
7131636e PB |
1397 | if (!boot_cpu_has(X86_FEATURE_RTM)) { |
1398 | /* | |
1399 | * If RTM=0 because the kernel has disabled TSX, the host might | |
1400 | * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 | |
1401 | * and therefore knows that there cannot be TAA) but keep | |
1402 | * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, | |
1403 | * and we want to allow migrating those guests to tsx=off hosts. | |
1404 | */ | |
1405 | data &= ~ARCH_CAP_TAA_NO; | |
1406 | } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { | |
cbbaa272 | 1407 | data |= ARCH_CAP_TAA_NO; |
7131636e PB |
1408 | } else { |
1409 | /* | |
1410 | * Nothing to do here; we emulate TSX_CTRL if present on the | |
1411 | * host so the guest can choose between disabling TSX or | |
1412 | * using VERW to clear CPU buffers. | |
1413 | */ | |
1414 | } | |
e1d38b63 | 1415 | |
5b76a3cf PB |
1416 | return data; |
1417 | } | |
5b76a3cf | 1418 | |
66421c1e WL |
1419 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1420 | { | |
1421 | switch (msr->index) { | |
cd283252 | 1422 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1423 | msr->data = kvm_get_arch_capabilities(); |
1424 | break; | |
1425 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1426 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1427 | break; |
66421c1e | 1428 | default: |
12bc2132 | 1429 | return kvm_x86_ops.get_msr_feature(msr); |
66421c1e WL |
1430 | } |
1431 | return 0; | |
1432 | } | |
1433 | ||
801e459a TL |
1434 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1435 | { | |
1436 | struct kvm_msr_entry msr; | |
66421c1e | 1437 | int r; |
801e459a TL |
1438 | |
1439 | msr.index = index; | |
66421c1e | 1440 | r = kvm_get_msr_feature(&msr); |
12bc2132 PX |
1441 | |
1442 | if (r == KVM_MSR_RET_INVALID) { | |
1443 | /* Unconditionally clear the output for simplicity */ | |
1444 | *data = 0; | |
cc4cb017 ML |
1445 | if (kvm_msr_ignored_check(vcpu, index, 0, false)) |
1446 | r = 0; | |
12bc2132 PX |
1447 | } |
1448 | ||
66421c1e WL |
1449 | if (r) |
1450 | return r; | |
801e459a TL |
1451 | |
1452 | *data = msr.data; | |
1453 | ||
1454 | return 0; | |
1455 | } | |
1456 | ||
11988499 | 1457 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1458 | { |
1b4d56b8 | 1459 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1460 | return false; |
1b2fd70c | 1461 | |
1b4d56b8 | 1462 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1463 | return false; |
d8017474 | 1464 | |
0a629563 SC |
1465 | if (efer & (EFER_LME | EFER_LMA) && |
1466 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1467 | return false; | |
1468 | ||
1469 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1470 | return false; | |
d8017474 | 1471 | |
384bb783 | 1472 | return true; |
11988499 SC |
1473 | |
1474 | } | |
1475 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1476 | { | |
1477 | if (efer & efer_reserved_bits) | |
1478 | return false; | |
1479 | ||
1480 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1481 | } |
1482 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1483 | ||
11988499 | 1484 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1485 | { |
1486 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1487 | u64 efer = msr_info->data; |
72f211ec | 1488 | int r; |
384bb783 | 1489 | |
11988499 | 1490 | if (efer & efer_reserved_bits) |
66f61c92 | 1491 | return 1; |
384bb783 | 1492 | |
11988499 SC |
1493 | if (!msr_info->host_initiated) { |
1494 | if (!__kvm_valid_efer(vcpu, efer)) | |
1495 | return 1; | |
1496 | ||
1497 | if (is_paging(vcpu) && | |
1498 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1499 | return 1; | |
1500 | } | |
384bb783 | 1501 | |
15c4a640 | 1502 | efer &= ~EFER_LMA; |
f6801dff | 1503 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1504 | |
72f211ec ML |
1505 | r = kvm_x86_ops.set_efer(vcpu, efer); |
1506 | if (r) { | |
1507 | WARN_ON(r > 0); | |
1508 | return r; | |
1509 | } | |
a3d204e2 | 1510 | |
aad82703 SY |
1511 | /* Update reserved bits */ |
1512 | if ((efer ^ old_efer) & EFER_NX) | |
1513 | kvm_mmu_reset_context(vcpu); | |
1514 | ||
b69e8cae | 1515 | return 0; |
15c4a640 CO |
1516 | } |
1517 | ||
f2b4b7dd JR |
1518 | void kvm_enable_efer_bits(u64 mask) |
1519 | { | |
1520 | efer_reserved_bits &= ~mask; | |
1521 | } | |
1522 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1523 | ||
51de8151 AG |
1524 | bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) |
1525 | { | |
1a155254 AG |
1526 | struct kvm *kvm = vcpu->kvm; |
1527 | struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges; | |
1528 | u32 count = kvm->arch.msr_filter.count; | |
1529 | u32 i; | |
1530 | bool r = kvm->arch.msr_filter.default_allow; | |
1531 | int idx; | |
1532 | ||
9389b9d5 SC |
1533 | /* MSR filtering not set up or x2APIC enabled, allow everything */ |
1534 | if (!count || (index >= 0x800 && index <= 0x8ff)) | |
1a155254 AG |
1535 | return true; |
1536 | ||
1537 | /* Prevent collision with set_msr_filter */ | |
1538 | idx = srcu_read_lock(&kvm->srcu); | |
1539 | ||
1540 | for (i = 0; i < count; i++) { | |
1541 | u32 start = ranges[i].base; | |
1542 | u32 end = start + ranges[i].nmsrs; | |
1543 | u32 flags = ranges[i].flags; | |
1544 | unsigned long *bitmap = ranges[i].bitmap; | |
1545 | ||
1546 | if ((index >= start) && (index < end) && (flags & type)) { | |
1547 | r = !!test_bit(index - start, bitmap); | |
1548 | break; | |
1549 | } | |
1550 | } | |
1551 | ||
1552 | srcu_read_unlock(&kvm->srcu, idx); | |
1553 | ||
1554 | return r; | |
51de8151 AG |
1555 | } |
1556 | EXPORT_SYMBOL_GPL(kvm_msr_allowed); | |
1557 | ||
15c4a640 | 1558 | /* |
f20935d8 SC |
1559 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1560 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1561 | * Returns 0 on success, non-0 otherwise. |
1562 | * Assumes vcpu_load() was already called. | |
1563 | */ | |
f20935d8 SC |
1564 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1565 | bool host_initiated) | |
15c4a640 | 1566 | { |
f20935d8 SC |
1567 | struct msr_data msr; |
1568 | ||
1a155254 | 1569 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) |
cc4cb017 | 1570 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1571 | |
f20935d8 | 1572 | switch (index) { |
854e8bb1 NA |
1573 | case MSR_FS_BASE: |
1574 | case MSR_GS_BASE: | |
1575 | case MSR_KERNEL_GS_BASE: | |
1576 | case MSR_CSTAR: | |
1577 | case MSR_LSTAR: | |
f20935d8 | 1578 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1579 | return 1; |
1580 | break; | |
1581 | case MSR_IA32_SYSENTER_EIP: | |
1582 | case MSR_IA32_SYSENTER_ESP: | |
1583 | /* | |
1584 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1585 | * non-canonical address is written on Intel but not on | |
1586 | * AMD (which ignores the top 32-bits, because it does | |
1587 | * not implement 64-bit SYSENTER). | |
1588 | * | |
1589 | * 64-bit code should hence be able to write a non-canonical | |
1590 | * value on AMD. Making the address canonical ensures that | |
1591 | * vmentry does not fail on Intel after writing a non-canonical | |
1592 | * value, and that something deterministic happens if the guest | |
1593 | * invokes 64-bit SYSENTER. | |
1594 | */ | |
f20935d8 | 1595 | data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); |
854e8bb1 | 1596 | } |
f20935d8 SC |
1597 | |
1598 | msr.data = data; | |
1599 | msr.index = index; | |
1600 | msr.host_initiated = host_initiated; | |
1601 | ||
afaf0b2f | 1602 | return kvm_x86_ops.set_msr(vcpu, &msr); |
15c4a640 CO |
1603 | } |
1604 | ||
6abe9c13 PX |
1605 | static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, |
1606 | u32 index, u64 data, bool host_initiated) | |
1607 | { | |
1608 | int ret = __kvm_set_msr(vcpu, index, data, host_initiated); | |
1609 | ||
1610 | if (ret == KVM_MSR_RET_INVALID) | |
cc4cb017 ML |
1611 | if (kvm_msr_ignored_check(vcpu, index, data, true)) |
1612 | ret = 0; | |
6abe9c13 PX |
1613 | |
1614 | return ret; | |
1615 | } | |
1616 | ||
313a3dc7 | 1617 | /* |
f20935d8 SC |
1618 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1619 | * checks are bypassed if @host_initiated is %true. | |
1620 | * Returns 0 on success, non-0 otherwise. | |
1621 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1622 | */ |
edef5c36 PB |
1623 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1624 | bool host_initiated) | |
609e36d3 PB |
1625 | { |
1626 | struct msr_data msr; | |
f20935d8 | 1627 | int ret; |
609e36d3 | 1628 | |
1a155254 | 1629 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) |
cc4cb017 | 1630 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1631 | |
609e36d3 | 1632 | msr.index = index; |
f20935d8 | 1633 | msr.host_initiated = host_initiated; |
609e36d3 | 1634 | |
afaf0b2f | 1635 | ret = kvm_x86_ops.get_msr(vcpu, &msr); |
f20935d8 SC |
1636 | if (!ret) |
1637 | *data = msr.data; | |
1638 | return ret; | |
609e36d3 PB |
1639 | } |
1640 | ||
6abe9c13 PX |
1641 | static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, |
1642 | u32 index, u64 *data, bool host_initiated) | |
1643 | { | |
1644 | int ret = __kvm_get_msr(vcpu, index, data, host_initiated); | |
1645 | ||
1646 | if (ret == KVM_MSR_RET_INVALID) { | |
1647 | /* Unconditionally clear *data for simplicity */ | |
1648 | *data = 0; | |
cc4cb017 ML |
1649 | if (kvm_msr_ignored_check(vcpu, index, 0, false)) |
1650 | ret = 0; | |
6abe9c13 PX |
1651 | } |
1652 | ||
1653 | return ret; | |
1654 | } | |
1655 | ||
f20935d8 | 1656 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1657 | { |
6abe9c13 | 1658 | return kvm_get_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1659 | } |
1660 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1661 | |
f20935d8 SC |
1662 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1663 | { | |
6abe9c13 | 1664 | return kvm_set_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1665 | } |
1666 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1667 | ||
8b474427 | 1668 | static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) |
1ae09954 | 1669 | { |
8b474427 PB |
1670 | int err = vcpu->run->msr.error; |
1671 | if (!err) { | |
1ae09954 AG |
1672 | kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); |
1673 | kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); | |
1674 | } | |
1675 | ||
f9a4d621 | 1676 | return kvm_x86_ops.complete_emulated_msr(vcpu, err); |
1ae09954 AG |
1677 | } |
1678 | ||
1679 | static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) | |
1680 | { | |
f9a4d621 | 1681 | return kvm_x86_ops.complete_emulated_msr(vcpu, vcpu->run->msr.error); |
1ae09954 AG |
1682 | } |
1683 | ||
1684 | static u64 kvm_msr_reason(int r) | |
1685 | { | |
1686 | switch (r) { | |
cc4cb017 | 1687 | case KVM_MSR_RET_INVALID: |
1ae09954 | 1688 | return KVM_MSR_EXIT_REASON_UNKNOWN; |
cc4cb017 | 1689 | case KVM_MSR_RET_FILTERED: |
1a155254 | 1690 | return KVM_MSR_EXIT_REASON_FILTER; |
1ae09954 AG |
1691 | default: |
1692 | return KVM_MSR_EXIT_REASON_INVAL; | |
1693 | } | |
1694 | } | |
1695 | ||
1696 | static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, | |
1697 | u32 exit_reason, u64 data, | |
1698 | int (*completion)(struct kvm_vcpu *vcpu), | |
1699 | int r) | |
1700 | { | |
1701 | u64 msr_reason = kvm_msr_reason(r); | |
1702 | ||
1703 | /* Check if the user wanted to know about this MSR fault */ | |
1704 | if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) | |
1705 | return 0; | |
1706 | ||
1707 | vcpu->run->exit_reason = exit_reason; | |
1708 | vcpu->run->msr.error = 0; | |
1709 | memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); | |
1710 | vcpu->run->msr.reason = msr_reason; | |
1711 | vcpu->run->msr.index = index; | |
1712 | vcpu->run->msr.data = data; | |
1713 | vcpu->arch.complete_userspace_io = completion; | |
1714 | ||
1715 | return 1; | |
1716 | } | |
1717 | ||
1718 | static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) | |
1719 | { | |
1720 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, | |
1721 | complete_emulated_rdmsr, r); | |
1722 | } | |
1723 | ||
1724 | static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) | |
1725 | { | |
1726 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, | |
1727 | complete_emulated_wrmsr, r); | |
1728 | } | |
1729 | ||
1edce0a9 SC |
1730 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
1731 | { | |
1732 | u32 ecx = kvm_rcx_read(vcpu); | |
1733 | u64 data; | |
1ae09954 AG |
1734 | int r; |
1735 | ||
1736 | r = kvm_get_msr(vcpu, ecx, &data); | |
1edce0a9 | 1737 | |
1ae09954 AG |
1738 | /* MSR read failed? See if we should ask user space */ |
1739 | if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { | |
1740 | /* Bounce to user space */ | |
1741 | return 0; | |
1742 | } | |
1743 | ||
8b474427 PB |
1744 | if (!r) { |
1745 | trace_kvm_msr_read(ecx, data); | |
1746 | ||
1747 | kvm_rax_write(vcpu, data & -1u); | |
1748 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
1749 | } else { | |
1edce0a9 | 1750 | trace_kvm_msr_read_ex(ecx); |
1edce0a9 SC |
1751 | } |
1752 | ||
f9a4d621 | 1753 | return kvm_x86_ops.complete_emulated_msr(vcpu, r); |
1edce0a9 SC |
1754 | } |
1755 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
1756 | ||
1757 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
1758 | { | |
1759 | u32 ecx = kvm_rcx_read(vcpu); | |
1760 | u64 data = kvm_read_edx_eax(vcpu); | |
1ae09954 | 1761 | int r; |
1edce0a9 | 1762 | |
1ae09954 AG |
1763 | r = kvm_set_msr(vcpu, ecx, data); |
1764 | ||
1765 | /* MSR write failed? See if we should ask user space */ | |
7dffecaf | 1766 | if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) |
1ae09954 AG |
1767 | /* Bounce to user space */ |
1768 | return 0; | |
7dffecaf ML |
1769 | |
1770 | /* Signal all other negative errors to userspace */ | |
1771 | if (r < 0) | |
1772 | return r; | |
1ae09954 | 1773 | |
8b474427 PB |
1774 | if (!r) |
1775 | trace_kvm_msr_write(ecx, data); | |
1776 | else | |
1edce0a9 | 1777 | trace_kvm_msr_write_ex(ecx, data); |
1edce0a9 | 1778 | |
f9a4d621 | 1779 | return kvm_x86_ops.complete_emulated_msr(vcpu, r); |
1edce0a9 SC |
1780 | } |
1781 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
1782 | ||
5a9f5443 WL |
1783 | bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) |
1784 | { | |
1785 | return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || | |
72c3c0fe | 1786 | xfer_to_guest_mode_work_pending(); |
5a9f5443 WL |
1787 | } |
1788 | EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request); | |
1789 | ||
1e9e2622 WL |
1790 | /* |
1791 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
1792 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
1793 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
1794 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
1795 | * other cases which must be called after interrupts are enabled on the host. | |
1796 | */ | |
1797 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
1798 | { | |
e1be9ac8 WL |
1799 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) |
1800 | return 1; | |
1801 | ||
1802 | if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && | |
1e9e2622 | 1803 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && |
4064a4c6 WL |
1804 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && |
1805 | ((u32)(data >> 32) != X2APIC_BROADCAST)) { | |
1e9e2622 | 1806 | |
d5361678 WL |
1807 | data &= ~(1 << 12); |
1808 | kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); | |
1e9e2622 | 1809 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); |
d5361678 WL |
1810 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); |
1811 | trace_kvm_apic_write(APIC_ICR, (u32)data); | |
1812 | return 0; | |
1e9e2622 WL |
1813 | } |
1814 | ||
1815 | return 1; | |
1816 | } | |
1817 | ||
ae95f566 WL |
1818 | static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) |
1819 | { | |
1820 | if (!kvm_can_use_hv_timer(vcpu)) | |
1821 | return 1; | |
1822 | ||
1823 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
1824 | return 0; | |
1825 | } | |
1826 | ||
404d5d7b | 1827 | fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) |
1e9e2622 WL |
1828 | { |
1829 | u32 msr = kvm_rcx_read(vcpu); | |
8a1038de | 1830 | u64 data; |
404d5d7b | 1831 | fastpath_t ret = EXIT_FASTPATH_NONE; |
1e9e2622 WL |
1832 | |
1833 | switch (msr) { | |
1834 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
8a1038de | 1835 | data = kvm_read_edx_eax(vcpu); |
404d5d7b WL |
1836 | if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { |
1837 | kvm_skip_emulated_instruction(vcpu); | |
1838 | ret = EXIT_FASTPATH_EXIT_HANDLED; | |
80bc97f2 | 1839 | } |
1e9e2622 | 1840 | break; |
ae95f566 WL |
1841 | case MSR_IA32_TSCDEADLINE: |
1842 | data = kvm_read_edx_eax(vcpu); | |
1843 | if (!handle_fastpath_set_tscdeadline(vcpu, data)) { | |
1844 | kvm_skip_emulated_instruction(vcpu); | |
1845 | ret = EXIT_FASTPATH_REENTER_GUEST; | |
1846 | } | |
1847 | break; | |
1e9e2622 | 1848 | default: |
404d5d7b | 1849 | break; |
1e9e2622 WL |
1850 | } |
1851 | ||
404d5d7b | 1852 | if (ret != EXIT_FASTPATH_NONE) |
1e9e2622 | 1853 | trace_kvm_msr_write(msr, data); |
1e9e2622 | 1854 | |
404d5d7b | 1855 | return ret; |
1e9e2622 WL |
1856 | } |
1857 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
1858 | ||
f20935d8 SC |
1859 | /* |
1860 | * Adapt set_msr() to msr_io()'s calling convention | |
1861 | */ | |
1862 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1863 | { | |
6abe9c13 | 1864 | return kvm_get_msr_ignored_check(vcpu, index, data, true); |
f20935d8 SC |
1865 | } |
1866 | ||
1867 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1868 | { | |
6abe9c13 | 1869 | return kvm_set_msr_ignored_check(vcpu, index, *data, true); |
313a3dc7 CO |
1870 | } |
1871 | ||
16e8d74d | 1872 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
1873 | struct pvclock_clock { |
1874 | int vclock_mode; | |
1875 | u64 cycle_last; | |
1876 | u64 mask; | |
1877 | u32 mult; | |
1878 | u32 shift; | |
917f9475 PB |
1879 | u64 base_cycles; |
1880 | u64 offset; | |
53fafdbb MT |
1881 | }; |
1882 | ||
16e8d74d MT |
1883 | struct pvclock_gtod_data { |
1884 | seqcount_t seq; | |
1885 | ||
53fafdbb MT |
1886 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
1887 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 1888 | |
917f9475 | 1889 | ktime_t offs_boot; |
55dd00a7 | 1890 | u64 wall_time_sec; |
16e8d74d MT |
1891 | }; |
1892 | ||
1893 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1894 | ||
1895 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1896 | { | |
1897 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
1898 | ||
1899 | write_seqcount_begin(&vdata->seq); | |
1900 | ||
1901 | /* copy pvclock gtod data */ | |
b95a8a27 | 1902 | vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; |
876e7881 PZ |
1903 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; |
1904 | vdata->clock.mask = tk->tkr_mono.mask; | |
1905 | vdata->clock.mult = tk->tkr_mono.mult; | |
1906 | vdata->clock.shift = tk->tkr_mono.shift; | |
917f9475 PB |
1907 | vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; |
1908 | vdata->clock.offset = tk->tkr_mono.base; | |
16e8d74d | 1909 | |
b95a8a27 | 1910 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; |
53fafdbb MT |
1911 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; |
1912 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
1913 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
1914 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
917f9475 PB |
1915 | vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; |
1916 | vdata->raw_clock.offset = tk->tkr_raw.base; | |
16e8d74d | 1917 | |
55dd00a7 MT |
1918 | vdata->wall_time_sec = tk->xtime_sec; |
1919 | ||
917f9475 | 1920 | vdata->offs_boot = tk->offs_boot; |
53fafdbb | 1921 | |
16e8d74d MT |
1922 | write_seqcount_end(&vdata->seq); |
1923 | } | |
8171cd68 PB |
1924 | |
1925 | static s64 get_kvmclock_base_ns(void) | |
1926 | { | |
1927 | /* Count up from boot time, but with the frequency of the raw clock. */ | |
1928 | return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); | |
1929 | } | |
1930 | #else | |
1931 | static s64 get_kvmclock_base_ns(void) | |
1932 | { | |
1933 | /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ | |
1934 | return ktime_get_boottime_ns(); | |
1935 | } | |
16e8d74d MT |
1936 | #endif |
1937 | ||
18068523 GOC |
1938 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1939 | { | |
9ed3c444 AK |
1940 | int version; |
1941 | int r; | |
50d0a0f9 | 1942 | struct pvclock_wall_clock wc; |
8171cd68 | 1943 | u64 wall_nsec; |
18068523 | 1944 | |
210dfd93 OU |
1945 | kvm->arch.wall_clock = wall_clock; |
1946 | ||
18068523 GOC |
1947 | if (!wall_clock) |
1948 | return; | |
1949 | ||
9ed3c444 AK |
1950 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1951 | if (r) | |
1952 | return; | |
1953 | ||
1954 | if (version & 1) | |
1955 | ++version; /* first time write, random junk */ | |
1956 | ||
1957 | ++version; | |
18068523 | 1958 | |
1dab1345 NK |
1959 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
1960 | return; | |
18068523 | 1961 | |
50d0a0f9 GH |
1962 | /* |
1963 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1964 | * system time (updated by kvm_guest_time_update below) to the |
8171cd68 | 1965 | * wall clock specified here. We do the reverse here. |
50d0a0f9 | 1966 | */ |
8171cd68 | 1967 | wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); |
50d0a0f9 | 1968 | |
8171cd68 PB |
1969 | wc.nsec = do_div(wall_nsec, 1000000000); |
1970 | wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ | |
50d0a0f9 | 1971 | wc.version = version; |
18068523 GOC |
1972 | |
1973 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1974 | ||
1975 | version++; | |
1976 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1977 | } |
1978 | ||
5b9bb0eb OU |
1979 | static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, |
1980 | bool old_msr, bool host_initiated) | |
1981 | { | |
1982 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
1983 | ||
1984 | if (vcpu->vcpu_id == 0 && !host_initiated) { | |
1e293d1a | 1985 | if (ka->boot_vcpu_runs_old_kvmclock != old_msr) |
5b9bb0eb OU |
1986 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1987 | ||
1988 | ka->boot_vcpu_runs_old_kvmclock = old_msr; | |
1989 | } | |
1990 | ||
1991 | vcpu->arch.time = system_time; | |
1992 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
1993 | ||
1994 | /* we verify if the enable bit is set... */ | |
1995 | vcpu->arch.pv_time_enabled = false; | |
1996 | if (!(system_time & 1)) | |
1997 | return; | |
1998 | ||
1999 | if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
2000 | &vcpu->arch.pv_time, system_time & ~1ULL, | |
2001 | sizeof(struct pvclock_vcpu_time_info))) | |
2002 | vcpu->arch.pv_time_enabled = true; | |
2003 | ||
2004 | return; | |
2005 | } | |
2006 | ||
50d0a0f9 GH |
2007 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
2008 | { | |
b51012de PB |
2009 | do_shl32_div32(dividend, divisor); |
2010 | return dividend; | |
50d0a0f9 GH |
2011 | } |
2012 | ||
3ae13faa | 2013 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 2014 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 2015 | { |
5f4e3f88 | 2016 | uint64_t scaled64; |
50d0a0f9 GH |
2017 | int32_t shift = 0; |
2018 | uint64_t tps64; | |
2019 | uint32_t tps32; | |
2020 | ||
3ae13faa PB |
2021 | tps64 = base_hz; |
2022 | scaled64 = scaled_hz; | |
50933623 | 2023 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
2024 | tps64 >>= 1; |
2025 | shift--; | |
2026 | } | |
2027 | ||
2028 | tps32 = (uint32_t)tps64; | |
50933623 JK |
2029 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
2030 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
2031 | scaled64 >>= 1; |
2032 | else | |
2033 | tps32 <<= 1; | |
50d0a0f9 GH |
2034 | shift++; |
2035 | } | |
2036 | ||
5f4e3f88 ZA |
2037 | *pshift = shift; |
2038 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
2039 | } |
2040 | ||
d828199e | 2041 | #ifdef CONFIG_X86_64 |
16e8d74d | 2042 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 2043 | #endif |
16e8d74d | 2044 | |
c8076604 | 2045 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 2046 | static unsigned long max_tsc_khz; |
c8076604 | 2047 | |
cc578287 | 2048 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 2049 | { |
cc578287 ZA |
2050 | u64 v = (u64)khz * (1000000 + ppm); |
2051 | do_div(v, 1000000); | |
2052 | return v; | |
1e993611 JR |
2053 | } |
2054 | ||
381d585c HZ |
2055 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
2056 | { | |
2057 | u64 ratio; | |
2058 | ||
2059 | /* Guest TSC same frequency as host TSC? */ | |
2060 | if (!scale) { | |
2061 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
2062 | return 0; | |
2063 | } | |
2064 | ||
2065 | /* TSC scaling supported? */ | |
2066 | if (!kvm_has_tsc_control) { | |
2067 | if (user_tsc_khz > tsc_khz) { | |
2068 | vcpu->arch.tsc_catchup = 1; | |
2069 | vcpu->arch.tsc_always_catchup = 1; | |
2070 | return 0; | |
2071 | } else { | |
3f16a5c3 | 2072 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
2073 | return -1; |
2074 | } | |
2075 | } | |
2076 | ||
2077 | /* TSC scaling required - calculate ratio */ | |
2078 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
2079 | user_tsc_khz, tsc_khz); | |
2080 | ||
2081 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
3f16a5c3 PB |
2082 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
2083 | user_tsc_khz); | |
381d585c HZ |
2084 | return -1; |
2085 | } | |
2086 | ||
2087 | vcpu->arch.tsc_scaling_ratio = ratio; | |
2088 | return 0; | |
2089 | } | |
2090 | ||
4941b8cb | 2091 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 2092 | { |
cc578287 ZA |
2093 | u32 thresh_lo, thresh_hi; |
2094 | int use_scaling = 0; | |
217fc9cf | 2095 | |
03ba32ca | 2096 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 2097 | if (user_tsc_khz == 0) { |
ad721883 HZ |
2098 | /* set tsc_scaling_ratio to a safe value */ |
2099 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
381d585c | 2100 | return -1; |
ad721883 | 2101 | } |
03ba32ca | 2102 | |
c285545f | 2103 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 2104 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
2105 | &vcpu->arch.virtual_tsc_shift, |
2106 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 2107 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
2108 | |
2109 | /* | |
2110 | * Compute the variation in TSC rate which is acceptable | |
2111 | * within the range of tolerance and decide if the | |
2112 | * rate being applied is within that bounds of the hardware | |
2113 | * rate. If so, no scaling or compensation need be done. | |
2114 | */ | |
2115 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
2116 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
2117 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
2118 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
2119 | use_scaling = 1; |
2120 | } | |
4941b8cb | 2121 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
2122 | } |
2123 | ||
2124 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
2125 | { | |
e26101b1 | 2126 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
2127 | vcpu->arch.virtual_tsc_mult, |
2128 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 2129 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
2130 | return tsc; |
2131 | } | |
2132 | ||
b0c39dc6 VK |
2133 | static inline int gtod_is_based_on_tsc(int mode) |
2134 | { | |
b95a8a27 | 2135 | return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; |
b0c39dc6 VK |
2136 | } |
2137 | ||
69b0049a | 2138 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
2139 | { |
2140 | #ifdef CONFIG_X86_64 | |
2141 | bool vcpus_matched; | |
b48aa97e MT |
2142 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2143 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2144 | ||
2145 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2146 | atomic_read(&vcpu->kvm->online_vcpus)); | |
2147 | ||
7f187922 MT |
2148 | /* |
2149 | * Once the masterclock is enabled, always perform request in | |
2150 | * order to update it. | |
2151 | * | |
2152 | * In order to enable masterclock, the host clocksource must be TSC | |
2153 | * and the vcpus need to have matched TSCs. When that happens, | |
2154 | * perform request to enable masterclock. | |
2155 | */ | |
2156 | if (ka->use_master_clock || | |
b0c39dc6 | 2157 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
2158 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2159 | ||
2160 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
2161 | atomic_read(&vcpu->kvm->online_vcpus), | |
2162 | ka->use_master_clock, gtod->clock.vclock_mode); | |
2163 | #endif | |
2164 | } | |
2165 | ||
35181e86 HZ |
2166 | /* |
2167 | * Multiply tsc by a fixed point number represented by ratio. | |
2168 | * | |
2169 | * The most significant 64-N bits (mult) of ratio represent the | |
2170 | * integral part of the fixed point number; the remaining N bits | |
2171 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
2172 | * point number (mult + frac * 2^(-N)). | |
2173 | * | |
2174 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
2175 | */ | |
2176 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
2177 | { | |
2178 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
2179 | } | |
2180 | ||
2181 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
2182 | { | |
2183 | u64 _tsc = tsc; | |
2184 | u64 ratio = vcpu->arch.tsc_scaling_ratio; | |
2185 | ||
2186 | if (ratio != kvm_default_tsc_scaling_ratio) | |
2187 | _tsc = __scale_tsc(ratio, tsc); | |
2188 | ||
2189 | return _tsc; | |
2190 | } | |
2191 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
2192 | ||
07c1419a HZ |
2193 | static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
2194 | { | |
2195 | u64 tsc; | |
2196 | ||
2197 | tsc = kvm_scale_tsc(vcpu, rdtsc()); | |
2198 | ||
2199 | return target_tsc - tsc; | |
2200 | } | |
2201 | ||
4ba76538 HZ |
2202 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
2203 | { | |
56ba77a4 | 2204 | return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc); |
4ba76538 HZ |
2205 | } |
2206 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
2207 | ||
a545ab6a LC |
2208 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
2209 | { | |
56ba77a4 | 2210 | vcpu->arch.l1_tsc_offset = offset; |
afaf0b2f | 2211 | vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset); |
a545ab6a LC |
2212 | } |
2213 | ||
b0c39dc6 VK |
2214 | static inline bool kvm_check_tsc_unstable(void) |
2215 | { | |
2216 | #ifdef CONFIG_X86_64 | |
2217 | /* | |
2218 | * TSC is marked unstable when we're running on Hyper-V, | |
2219 | * 'TSC page' clocksource is good. | |
2220 | */ | |
b95a8a27 | 2221 | if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) |
b0c39dc6 VK |
2222 | return false; |
2223 | #endif | |
2224 | return check_tsc_unstable(); | |
2225 | } | |
2226 | ||
0c899c25 | 2227 | static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) |
99e3e30a ZA |
2228 | { |
2229 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 2230 | u64 offset, ns, elapsed; |
99e3e30a | 2231 | unsigned long flags; |
b48aa97e | 2232 | bool matched; |
0d3da0d2 | 2233 | bool already_matched; |
c5e8ec8e | 2234 | bool synchronizing = false; |
99e3e30a | 2235 | |
038f8c11 | 2236 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
07c1419a | 2237 | offset = kvm_compute_tsc_offset(vcpu, data); |
8171cd68 | 2238 | ns = get_kvmclock_base_ns(); |
f38e098f | 2239 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 2240 | |
03ba32ca | 2241 | if (vcpu->arch.virtual_tsc_khz) { |
0c899c25 | 2242 | if (data == 0) { |
bd8fab39 DP |
2243 | /* |
2244 | * detection of vcpu initialization -- need to sync | |
2245 | * with other vCPUs. This particularly helps to keep | |
2246 | * kvm_clock stable after CPU hotplug | |
2247 | */ | |
2248 | synchronizing = true; | |
2249 | } else { | |
2250 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
2251 | nsec_to_cycles(vcpu, elapsed); | |
2252 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
2253 | /* | |
2254 | * Special case: TSC write with a small delta (1 second) | |
2255 | * of virtual cycle time against real time is | |
2256 | * interpreted as an attempt to synchronize the CPU. | |
2257 | */ | |
2258 | synchronizing = data < tsc_exp + tsc_hz && | |
2259 | data + tsc_hz > tsc_exp; | |
2260 | } | |
c5e8ec8e | 2261 | } |
f38e098f ZA |
2262 | |
2263 | /* | |
5d3cb0f6 ZA |
2264 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
2265 | * TSC, we add elapsed time in this computation. We could let the | |
2266 | * compensation code attempt to catch up if we fall behind, but | |
2267 | * it's better to try to match offsets from the beginning. | |
2268 | */ | |
c5e8ec8e | 2269 | if (synchronizing && |
5d3cb0f6 | 2270 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 2271 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 2272 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 2273 | } else { |
857e4099 | 2274 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 2275 | data += delta; |
07c1419a | 2276 | offset = kvm_compute_tsc_offset(vcpu, data); |
f38e098f | 2277 | } |
b48aa97e | 2278 | matched = true; |
0d3da0d2 | 2279 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
2280 | } else { |
2281 | /* | |
2282 | * We split periods of matched TSC writes into generations. | |
2283 | * For each generation, we track the original measured | |
2284 | * nanosecond time, offset, and write, so if TSCs are in | |
2285 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 2286 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
2287 | * |
2288 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2289 | */ | |
2290 | kvm->arch.cur_tsc_generation++; | |
2291 | kvm->arch.cur_tsc_nsec = ns; | |
2292 | kvm->arch.cur_tsc_write = data; | |
2293 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 2294 | matched = false; |
f38e098f | 2295 | } |
e26101b1 ZA |
2296 | |
2297 | /* | |
2298 | * We also track th most recent recorded KHZ, write and time to | |
2299 | * allow the matching interval to be extended at each write. | |
2300 | */ | |
f38e098f ZA |
2301 | kvm->arch.last_tsc_nsec = ns; |
2302 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 2303 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 2304 | |
b183aa58 | 2305 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
2306 | |
2307 | /* Keep track of which generation this VCPU has synchronized to */ | |
2308 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2309 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2310 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2311 | ||
a545ab6a | 2312 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
e26101b1 | 2313 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
b48aa97e MT |
2314 | |
2315 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 2316 | if (!matched) { |
b48aa97e | 2317 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
2318 | } else if (!already_matched) { |
2319 | kvm->arch.nr_vcpus_matched_tsc++; | |
2320 | } | |
b48aa97e MT |
2321 | |
2322 | kvm_track_tsc_matching(vcpu); | |
2323 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 2324 | } |
e26101b1 | 2325 | |
58ea6767 HZ |
2326 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2327 | s64 adjustment) | |
2328 | { | |
56ba77a4 | 2329 | u64 tsc_offset = vcpu->arch.l1_tsc_offset; |
326e7425 | 2330 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); |
58ea6767 HZ |
2331 | } |
2332 | ||
2333 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2334 | { | |
2335 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) | |
2336 | WARN_ON(adjustment < 0); | |
2337 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); | |
ea26e4ec | 2338 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2339 | } |
2340 | ||
d828199e MT |
2341 | #ifdef CONFIG_X86_64 |
2342 | ||
a5a1d1c2 | 2343 | static u64 read_tsc(void) |
d828199e | 2344 | { |
a5a1d1c2 | 2345 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2346 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2347 | |
2348 | if (likely(ret >= last)) | |
2349 | return ret; | |
2350 | ||
2351 | /* | |
2352 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2353 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2354 | * very likely) and there's a data dependence, so force GCC |
2355 | * to generate a branch instead. I don't barrier() because | |
2356 | * we don't actually need a barrier, and if this function | |
2357 | * ever gets inlined it will generate worse code. | |
2358 | */ | |
2359 | asm volatile (""); | |
2360 | return last; | |
2361 | } | |
2362 | ||
53fafdbb MT |
2363 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2364 | int *mode) | |
d828199e MT |
2365 | { |
2366 | long v; | |
b0c39dc6 VK |
2367 | u64 tsc_pg_val; |
2368 | ||
53fafdbb | 2369 | switch (clock->vclock_mode) { |
b95a8a27 | 2370 | case VDSO_CLOCKMODE_HVCLOCK: |
b0c39dc6 VK |
2371 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), |
2372 | tsc_timestamp); | |
2373 | if (tsc_pg_val != U64_MAX) { | |
2374 | /* TSC page valid */ | |
b95a8a27 | 2375 | *mode = VDSO_CLOCKMODE_HVCLOCK; |
53fafdbb MT |
2376 | v = (tsc_pg_val - clock->cycle_last) & |
2377 | clock->mask; | |
b0c39dc6 VK |
2378 | } else { |
2379 | /* TSC page invalid */ | |
b95a8a27 | 2380 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 VK |
2381 | } |
2382 | break; | |
b95a8a27 TG |
2383 | case VDSO_CLOCKMODE_TSC: |
2384 | *mode = VDSO_CLOCKMODE_TSC; | |
b0c39dc6 | 2385 | *tsc_timestamp = read_tsc(); |
53fafdbb MT |
2386 | v = (*tsc_timestamp - clock->cycle_last) & |
2387 | clock->mask; | |
b0c39dc6 VK |
2388 | break; |
2389 | default: | |
b95a8a27 | 2390 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 | 2391 | } |
d828199e | 2392 | |
b95a8a27 | 2393 | if (*mode == VDSO_CLOCKMODE_NONE) |
b0c39dc6 | 2394 | *tsc_timestamp = v = 0; |
d828199e | 2395 | |
53fafdbb | 2396 | return v * clock->mult; |
d828199e MT |
2397 | } |
2398 | ||
53fafdbb | 2399 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2400 | { |
cbcf2dd3 | 2401 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2402 | unsigned long seq; |
d828199e | 2403 | int mode; |
cbcf2dd3 | 2404 | u64 ns; |
d828199e | 2405 | |
d828199e MT |
2406 | do { |
2407 | seq = read_seqcount_begin(>od->seq); | |
917f9475 | 2408 | ns = gtod->raw_clock.base_cycles; |
53fafdbb | 2409 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); |
917f9475 PB |
2410 | ns >>= gtod->raw_clock.shift; |
2411 | ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); | |
d828199e | 2412 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2413 | *t = ns; |
d828199e MT |
2414 | |
2415 | return mode; | |
2416 | } | |
2417 | ||
899a31f5 | 2418 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2419 | { |
2420 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2421 | unsigned long seq; | |
2422 | int mode; | |
2423 | u64 ns; | |
2424 | ||
2425 | do { | |
2426 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 | 2427 | ts->tv_sec = gtod->wall_time_sec; |
917f9475 | 2428 | ns = gtod->clock.base_cycles; |
53fafdbb | 2429 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2430 | ns >>= gtod->clock.shift; |
2431 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2432 | ||
2433 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2434 | ts->tv_nsec = ns; | |
2435 | ||
2436 | return mode; | |
2437 | } | |
2438 | ||
b0c39dc6 VK |
2439 | /* returns true if host is using TSC based clocksource */ |
2440 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2441 | { |
d828199e | 2442 | /* checked again under seqlock below */ |
b0c39dc6 | 2443 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2444 | return false; |
2445 | ||
53fafdbb | 2446 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2447 | tsc_timestamp)); |
d828199e | 2448 | } |
55dd00a7 | 2449 | |
b0c39dc6 | 2450 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2451 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2452 | u64 *tsc_timestamp) |
55dd00a7 MT |
2453 | { |
2454 | /* checked again under seqlock below */ | |
b0c39dc6 | 2455 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2456 | return false; |
2457 | ||
b0c39dc6 | 2458 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2459 | } |
d828199e MT |
2460 | #endif |
2461 | ||
2462 | /* | |
2463 | * | |
b48aa97e MT |
2464 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2465 | * across virtual CPUs, the following condition is possible. | |
2466 | * Each numbered line represents an event visible to both | |
d828199e MT |
2467 | * CPUs at the next numbered event. |
2468 | * | |
2469 | * "timespecX" represents host monotonic time. "tscX" represents | |
2470 | * RDTSC value. | |
2471 | * | |
2472 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2473 | * | |
2474 | * 1. read timespec0,tsc0 | |
2475 | * 2. | timespec1 = timespec0 + N | |
2476 | * | tsc1 = tsc0 + M | |
2477 | * 3. transition to guest | transition to guest | |
2478 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2479 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2480 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2481 | * | |
2482 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2483 | * | |
2484 | * - ret0 < ret1 | |
2485 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2486 | * ... | |
2487 | * - 0 < N - M => M < N | |
2488 | * | |
2489 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2490 | * always the case (the difference between two distinct xtime instances | |
2491 | * might be smaller then the difference between corresponding TSC reads, | |
2492 | * when updating guest vcpus pvclock areas). | |
2493 | * | |
2494 | * To avoid that problem, do not allow visibility of distinct | |
2495 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2496 | * copy of host monotonic time values. Update that master copy | |
2497 | * in lockstep. | |
2498 | * | |
b48aa97e | 2499 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2500 | * |
2501 | */ | |
2502 | ||
2503 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2504 | { | |
2505 | #ifdef CONFIG_X86_64 | |
2506 | struct kvm_arch *ka = &kvm->arch; | |
2507 | int vclock_mode; | |
b48aa97e MT |
2508 | bool host_tsc_clocksource, vcpus_matched; |
2509 | ||
2510 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2511 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2512 | |
2513 | /* | |
2514 | * If the host uses TSC clock, then passthrough TSC as stable | |
2515 | * to the guest. | |
2516 | */ | |
b48aa97e | 2517 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2518 | &ka->master_kernel_ns, |
2519 | &ka->master_cycle_now); | |
2520 | ||
16a96021 | 2521 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2522 | && !ka->backwards_tsc_observed |
54750f2c | 2523 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2524 | |
d828199e MT |
2525 | if (ka->use_master_clock) |
2526 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2527 | ||
2528 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2529 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2530 | vcpus_matched); | |
d828199e MT |
2531 | #endif |
2532 | } | |
2533 | ||
2860c4b1 PB |
2534 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2535 | { | |
2536 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2537 | } | |
2538 | ||
2e762ff7 MT |
2539 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
2540 | { | |
2541 | #ifdef CONFIG_X86_64 | |
2542 | int i; | |
2543 | struct kvm_vcpu *vcpu; | |
2544 | struct kvm_arch *ka = &kvm->arch; | |
2545 | ||
2546 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2547 | kvm_make_mclock_inprogress_request(kvm); | |
2548 | /* no guest entries from this point */ | |
2549 | pvclock_update_vm_gtod_copy(kvm); | |
2550 | ||
2551 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 2552 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2553 | |
2554 | /* guest entries allowed */ | |
2555 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2556 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
2557 | |
2558 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2559 | #endif | |
2560 | } | |
2561 | ||
e891a32e | 2562 | u64 get_kvmclock_ns(struct kvm *kvm) |
108b249c | 2563 | { |
108b249c | 2564 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2565 | struct pvclock_vcpu_time_info hv_clock; |
e2c2206a | 2566 | u64 ret; |
108b249c | 2567 | |
8b953440 PB |
2568 | spin_lock(&ka->pvclock_gtod_sync_lock); |
2569 | if (!ka->use_master_clock) { | |
2570 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
8171cd68 | 2571 | return get_kvmclock_base_ns() + ka->kvmclock_offset; |
108b249c PB |
2572 | } |
2573 | ||
8b953440 PB |
2574 | hv_clock.tsc_timestamp = ka->master_cycle_now; |
2575 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
2576 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2577 | ||
e2c2206a WL |
2578 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2579 | get_cpu(); | |
2580 | ||
e70b57a6 WL |
2581 | if (__this_cpu_read(cpu_tsc_khz)) { |
2582 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, | |
2583 | &hv_clock.tsc_shift, | |
2584 | &hv_clock.tsc_to_system_mul); | |
2585 | ret = __pvclock_read_cycles(&hv_clock, rdtsc()); | |
2586 | } else | |
8171cd68 | 2587 | ret = get_kvmclock_base_ns() + ka->kvmclock_offset; |
e2c2206a WL |
2588 | |
2589 | put_cpu(); | |
2590 | ||
2591 | return ret; | |
108b249c PB |
2592 | } |
2593 | ||
0d6dd2ff PB |
2594 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v) |
2595 | { | |
2596 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
2597 | struct pvclock_vcpu_time_info guest_hv_clock; | |
2598 | ||
4e335d9e | 2599 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
0d6dd2ff PB |
2600 | &guest_hv_clock, sizeof(guest_hv_clock)))) |
2601 | return; | |
2602 | ||
2603 | /* This VCPU is paused, but it's legal for a guest to read another | |
2604 | * VCPU's kvmclock, so we really have to follow the specification where | |
2605 | * it says that version is odd if data is being modified, and even after | |
2606 | * it is consistent. | |
2607 | * | |
2608 | * Version field updates must be kept separate. This is because | |
2609 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
2610 | * writes within a string instruction are weakly ordered. So there | |
2611 | * are three writes overall. | |
2612 | * | |
2613 | * As a small optimization, only write the version field in the first | |
2614 | * and third write. The vcpu->pv_time cache is still valid, because the | |
2615 | * version field is the first in the struct. | |
2616 | */ | |
2617 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
2618 | ||
51c4b8bb LA |
2619 | if (guest_hv_clock.version & 1) |
2620 | ++guest_hv_clock.version; /* first time write, random junk */ | |
2621 | ||
0d6dd2ff | 2622 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
4e335d9e PB |
2623 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2624 | &vcpu->hv_clock, | |
2625 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2626 | |
2627 | smp_wmb(); | |
2628 | ||
2629 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
2630 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
2631 | ||
2632 | if (vcpu->pvclock_set_guest_stopped_request) { | |
2633 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
2634 | vcpu->pvclock_set_guest_stopped_request = false; | |
2635 | } | |
2636 | ||
2637 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
2638 | ||
4e335d9e PB |
2639 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2640 | &vcpu->hv_clock, | |
2641 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
2642 | |
2643 | smp_wmb(); | |
2644 | ||
2645 | vcpu->hv_clock.version++; | |
4e335d9e PB |
2646 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2647 | &vcpu->hv_clock, | |
2648 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2649 | } |
2650 | ||
34c238a1 | 2651 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 2652 | { |
78db6a50 | 2653 | unsigned long flags, tgt_tsc_khz; |
18068523 | 2654 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 2655 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 2656 | s64 kernel_ns; |
d828199e | 2657 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 2658 | u8 pvclock_flags; |
d828199e MT |
2659 | bool use_master_clock; |
2660 | ||
2661 | kernel_ns = 0; | |
2662 | host_tsc = 0; | |
18068523 | 2663 | |
d828199e MT |
2664 | /* |
2665 | * If the host uses TSC clock, then passthrough TSC as stable | |
2666 | * to the guest. | |
2667 | */ | |
2668 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2669 | use_master_clock = ka->use_master_clock; | |
2670 | if (use_master_clock) { | |
2671 | host_tsc = ka->master_cycle_now; | |
2672 | kernel_ns = ka->master_kernel_ns; | |
2673 | } | |
2674 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
2675 | |
2676 | /* Keep irq disabled to prevent changes to the clock */ | |
2677 | local_irq_save(flags); | |
78db6a50 PB |
2678 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2679 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2680 | local_irq_restore(flags); |
2681 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2682 | return 1; | |
2683 | } | |
d828199e | 2684 | if (!use_master_clock) { |
4ea1636b | 2685 | host_tsc = rdtsc(); |
8171cd68 | 2686 | kernel_ns = get_kvmclock_base_ns(); |
d828199e MT |
2687 | } |
2688 | ||
4ba76538 | 2689 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2690 | |
c285545f ZA |
2691 | /* |
2692 | * We may have to catch up the TSC to match elapsed wall clock | |
2693 | * time for two reasons, even if kvmclock is used. | |
2694 | * 1) CPU could have been running below the maximum TSC rate | |
2695 | * 2) Broken TSC compensation resets the base at each VCPU | |
2696 | * entry to avoid unknown leaps of TSC even when running | |
2697 | * again on the same CPU. This may cause apparent elapsed | |
2698 | * time to disappear, and the guest to stand still or run | |
2699 | * very slowly. | |
2700 | */ | |
2701 | if (vcpu->tsc_catchup) { | |
2702 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
2703 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 2704 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
2705 | tsc_timestamp = tsc; |
2706 | } | |
50d0a0f9 GH |
2707 | } |
2708 | ||
18068523 GOC |
2709 | local_irq_restore(flags); |
2710 | ||
0d6dd2ff | 2711 | /* With all the info we got, fill in the values */ |
18068523 | 2712 | |
78db6a50 PB |
2713 | if (kvm_has_tsc_control) |
2714 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); | |
2715 | ||
2716 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 2717 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
2718 | &vcpu->hv_clock.tsc_shift, |
2719 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 2720 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
2721 | } |
2722 | ||
1d5f066e | 2723 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 2724 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 2725 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 2726 | |
d828199e | 2727 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 2728 | pvclock_flags = 0; |
d828199e MT |
2729 | if (use_master_clock) |
2730 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
2731 | ||
78c0337a MT |
2732 | vcpu->hv_clock.flags = pvclock_flags; |
2733 | ||
095cf55d PB |
2734 | if (vcpu->pv_time_enabled) |
2735 | kvm_setup_pvclock_page(v); | |
2736 | if (v == kvm_get_vcpu(v->kvm, 0)) | |
2737 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); | |
8cfdc000 | 2738 | return 0; |
c8076604 GH |
2739 | } |
2740 | ||
0061d53d MT |
2741 | /* |
2742 | * kvmclock updates which are isolated to a given vcpu, such as | |
2743 | * vcpu->cpu migration, should not allow system_timestamp from | |
2744 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
2745 | * correction applies to one vcpu's system_timestamp but not | |
2746 | * the others. | |
2747 | * | |
2748 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
2749 | * We need to rate-limit these requests though, as they can |
2750 | * considerably slow guests that have a large number of vcpus. | |
2751 | * The time for a remote vcpu to update its kvmclock is bound | |
2752 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
2753 | */ |
2754 | ||
7e44e449 AJ |
2755 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
2756 | ||
2757 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
2758 | { |
2759 | int i; | |
7e44e449 AJ |
2760 | struct delayed_work *dwork = to_delayed_work(work); |
2761 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2762 | kvmclock_update_work); | |
2763 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
2764 | struct kvm_vcpu *vcpu; |
2765 | ||
2766 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 2767 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
2768 | kvm_vcpu_kick(vcpu); |
2769 | } | |
2770 | } | |
2771 | ||
7e44e449 AJ |
2772 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
2773 | { | |
2774 | struct kvm *kvm = v->kvm; | |
2775 | ||
105b21bb | 2776 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
2777 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
2778 | KVMCLOCK_UPDATE_DELAY); | |
2779 | } | |
2780 | ||
332967a3 AJ |
2781 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
2782 | ||
2783 | static void kvmclock_sync_fn(struct work_struct *work) | |
2784 | { | |
2785 | struct delayed_work *dwork = to_delayed_work(work); | |
2786 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2787 | kvmclock_sync_work); | |
2788 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
2789 | ||
630994b3 MT |
2790 | if (!kvmclock_periodic_sync) |
2791 | return; | |
2792 | ||
332967a3 AJ |
2793 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
2794 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
2795 | KVMCLOCK_SYNC_PERIOD); | |
2796 | } | |
2797 | ||
191c8137 BP |
2798 | /* |
2799 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
2800 | */ | |
2801 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
2802 | { | |
2803 | /* McStatusWrEn enabled? */ | |
23493d0a | 2804 | if (guest_cpuid_is_amd_or_hygon(vcpu)) |
191c8137 BP |
2805 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); |
2806 | ||
2807 | return false; | |
2808 | } | |
2809 | ||
9ffd986c | 2810 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2811 | { |
890ca9ae HY |
2812 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2813 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
2814 | u32 msr = msr_info->index; |
2815 | u64 data = msr_info->data; | |
890ca9ae | 2816 | |
15c4a640 | 2817 | switch (msr) { |
15c4a640 | 2818 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 2819 | vcpu->arch.mcg_status = data; |
15c4a640 | 2820 | break; |
c7ac679c | 2821 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
2822 | if (!(mcg_cap & MCG_CTL_P) && |
2823 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
2824 | return 1; |
2825 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 2826 | return 1; |
890ca9ae HY |
2827 | vcpu->arch.mcg_ctl = data; |
2828 | break; | |
2829 | default: | |
2830 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2831 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
2832 | u32 offset = array_index_nospec( |
2833 | msr - MSR_IA32_MC0_CTL, | |
2834 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
2835 | ||
114be429 AP |
2836 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
2837 | * some Linux kernels though clear bit 10 in bank 4 to | |
2838 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
2839 | * this to avoid an uncatched #GP in the guest | |
2840 | */ | |
890ca9ae | 2841 | if ((offset & 0x3) == 0 && |
114be429 | 2842 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 2843 | return -1; |
191c8137 BP |
2844 | |
2845 | /* MCi_STATUS */ | |
9ffd986c | 2846 | if (!msr_info->host_initiated && |
191c8137 BP |
2847 | (offset & 0x3) == 1 && data != 0) { |
2848 | if (!can_set_mci_status(vcpu)) | |
2849 | return -1; | |
2850 | } | |
2851 | ||
890ca9ae HY |
2852 | vcpu->arch.mce_banks[offset] = data; |
2853 | break; | |
2854 | } | |
2855 | return 1; | |
2856 | } | |
2857 | return 0; | |
2858 | } | |
2859 | ||
ffde22ac ES |
2860 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
2861 | { | |
2862 | struct kvm *kvm = vcpu->kvm; | |
2863 | int lm = is_long_mode(vcpu); | |
2864 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
2865 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
2866 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
2867 | : kvm->arch.xen_hvm_config.blob_size_32; | |
2868 | u32 page_num = data & ~PAGE_MASK; | |
2869 | u64 page_addr = data & PAGE_MASK; | |
2870 | u8 *page; | |
ffde22ac | 2871 | |
ffde22ac | 2872 | if (page_num >= blob_size) |
36385ccc ML |
2873 | return 1; |
2874 | ||
ff5c2c03 | 2875 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
36385ccc ML |
2876 | if (IS_ERR(page)) |
2877 | return PTR_ERR(page); | |
2878 | ||
2879 | if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) { | |
2880 | kfree(page); | |
2881 | return 1; | |
ff5c2c03 | 2882 | } |
36385ccc | 2883 | return 0; |
ffde22ac ES |
2884 | } |
2885 | ||
2635b5c4 VK |
2886 | static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) |
2887 | { | |
2888 | u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; | |
2889 | ||
2890 | return (vcpu->arch.apf.msr_en_val & mask) == mask; | |
2891 | } | |
2892 | ||
344d9588 GN |
2893 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
2894 | { | |
2895 | gpa_t gpa = data & ~0x3f; | |
2896 | ||
2635b5c4 VK |
2897 | /* Bits 4:5 are reserved, Should be zero */ |
2898 | if (data & 0x30) | |
344d9588 GN |
2899 | return 1; |
2900 | ||
66570e96 OU |
2901 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && |
2902 | (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) | |
2903 | return 1; | |
2904 | ||
2905 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && | |
2906 | (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) | |
2907 | return 1; | |
2908 | ||
9d3c447c | 2909 | if (!lapic_in_kernel(vcpu)) |
d831de17 | 2910 | return data ? 1 : 0; |
9d3c447c | 2911 | |
2635b5c4 | 2912 | vcpu->arch.apf.msr_en_val = data; |
344d9588 | 2913 | |
2635b5c4 | 2914 | if (!kvm_pv_async_pf_enabled(vcpu)) { |
344d9588 GN |
2915 | kvm_clear_async_pf_completion_queue(vcpu); |
2916 | kvm_async_pf_hash_reset(vcpu); | |
2917 | return 0; | |
2918 | } | |
2919 | ||
4e335d9e | 2920 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
68fd66f1 | 2921 | sizeof(u64))) |
344d9588 GN |
2922 | return 1; |
2923 | ||
6adba527 | 2924 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 2925 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
2635b5c4 | 2926 | |
344d9588 | 2927 | kvm_async_pf_wakeup_all(vcpu); |
2635b5c4 VK |
2928 | |
2929 | return 0; | |
2930 | } | |
2931 | ||
2932 | static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) | |
2933 | { | |
2934 | /* Bits 8-63 are reserved */ | |
2935 | if (data >> 8) | |
2936 | return 1; | |
2937 | ||
2938 | if (!lapic_in_kernel(vcpu)) | |
2939 | return 1; | |
2940 | ||
2941 | vcpu->arch.apf.msr_int_val = data; | |
2942 | ||
2943 | vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; | |
2944 | ||
344d9588 GN |
2945 | return 0; |
2946 | } | |
2947 | ||
12f9a48f GC |
2948 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2949 | { | |
0b79459b | 2950 | vcpu->arch.pv_time_enabled = false; |
49dedf0d | 2951 | vcpu->arch.time = 0; |
12f9a48f GC |
2952 | } |
2953 | ||
7780938c | 2954 | static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) |
f38a7b75 WL |
2955 | { |
2956 | ++vcpu->stat.tlb_flush; | |
7780938c | 2957 | kvm_x86_ops.tlb_flush_all(vcpu); |
f38a7b75 WL |
2958 | } |
2959 | ||
0baedd79 VK |
2960 | static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) |
2961 | { | |
2962 | ++vcpu->stat.tlb_flush; | |
2963 | kvm_x86_ops.tlb_flush_guest(vcpu); | |
2964 | } | |
2965 | ||
c9aaa895 GC |
2966 | static void record_steal_time(struct kvm_vcpu *vcpu) |
2967 | { | |
b0431382 BO |
2968 | struct kvm_host_map map; |
2969 | struct kvm_steal_time *st; | |
2970 | ||
c9aaa895 GC |
2971 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
2972 | return; | |
2973 | ||
b0431382 BO |
2974 | /* -EAGAIN is returned in atomic context so we can just return. */ |
2975 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, | |
2976 | &map, &vcpu->arch.st.cache, false)) | |
c9aaa895 GC |
2977 | return; |
2978 | ||
b0431382 BO |
2979 | st = map.hva + |
2980 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
2981 | ||
f38a7b75 WL |
2982 | /* |
2983 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
2984 | * expensive IPIs. | |
2985 | */ | |
66570e96 OU |
2986 | if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { |
2987 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, | |
2988 | st->preempted & KVM_VCPU_FLUSH_TLB); | |
2989 | if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB) | |
2990 | kvm_vcpu_flush_tlb_guest(vcpu); | |
2991 | } | |
0b9f6c46 | 2992 | |
a6bd811f | 2993 | vcpu->arch.st.preempted = 0; |
35f3fae1 | 2994 | |
b0431382 BO |
2995 | if (st->version & 1) |
2996 | st->version += 1; /* first time write, random junk */ | |
35f3fae1 | 2997 | |
b0431382 | 2998 | st->version += 1; |
35f3fae1 WL |
2999 | |
3000 | smp_wmb(); | |
3001 | ||
b0431382 | 3002 | st->steal += current->sched_info.run_delay - |
c54cdf14 LC |
3003 | vcpu->arch.st.last_steal; |
3004 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
35f3fae1 | 3005 | |
35f3fae1 WL |
3006 | smp_wmb(); |
3007 | ||
b0431382 | 3008 | st->version += 1; |
c9aaa895 | 3009 | |
b0431382 | 3010 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); |
c9aaa895 GC |
3011 | } |
3012 | ||
8fe8ab46 | 3013 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3014 | { |
5753785f | 3015 | bool pr = false; |
8fe8ab46 WA |
3016 | u32 msr = msr_info->index; |
3017 | u64 data = msr_info->data; | |
5753785f | 3018 | |
15c4a640 | 3019 | switch (msr) { |
2e32b719 | 3020 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
3021 | case MSR_IA32_UCODE_WRITE: |
3022 | case MSR_VM_HSAVE_PA: | |
3023 | case MSR_AMD64_PATCH_LOADER: | |
3024 | case MSR_AMD64_BU_CFG2: | |
405a353a | 3025 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3026 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
3027 | break; |
3028 | ||
518e7b94 WL |
3029 | case MSR_IA32_UCODE_REV: |
3030 | if (msr_info->host_initiated) | |
3031 | vcpu->arch.microcode_version = data; | |
3032 | break; | |
0cf9135b SC |
3033 | case MSR_IA32_ARCH_CAPABILITIES: |
3034 | if (!msr_info->host_initiated) | |
3035 | return 1; | |
3036 | vcpu->arch.arch_capabilities = data; | |
3037 | break; | |
d574c539 VK |
3038 | case MSR_IA32_PERF_CAPABILITIES: { |
3039 | struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; | |
3040 | ||
3041 | if (!msr_info->host_initiated) | |
3042 | return 1; | |
3043 | if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) | |
3044 | return 1; | |
3045 | if (data & ~msr_ent.data) | |
3046 | return 1; | |
3047 | ||
3048 | vcpu->arch.perf_capabilities = data; | |
3049 | ||
3050 | return 0; | |
3051 | } | |
15c4a640 | 3052 | case MSR_EFER: |
11988499 | 3053 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
3054 | case MSR_K7_HWCR: |
3055 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 3056 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 3057 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
3058 | |
3059 | /* Handle McStatusWrEn */ | |
3060 | if (data == BIT_ULL(18)) { | |
3061 | vcpu->arch.msr_hwcr = data; | |
3062 | } else if (data != 0) { | |
a737f256 CD |
3063 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
3064 | data); | |
8f1589d9 AP |
3065 | return 1; |
3066 | } | |
15c4a640 | 3067 | break; |
f7c6d140 AP |
3068 | case MSR_FAM10H_MMIO_CONF_BASE: |
3069 | if (data != 0) { | |
a737f256 CD |
3070 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
3071 | "0x%llx\n", data); | |
f7c6d140 AP |
3072 | return 1; |
3073 | } | |
15c4a640 | 3074 | break; |
b5e2fec0 AG |
3075 | case MSR_IA32_DEBUGCTLMSR: |
3076 | if (!data) { | |
3077 | /* We support the non-activated case already */ | |
3078 | break; | |
3079 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
3080 | /* Values other than LBR and BTF are vendor-specific, | |
3081 | thus reserved and should throw a #GP */ | |
3082 | return 1; | |
2cdef91c PG |
3083 | } else if (report_ignored_msrs) |
3084 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
3085 | __func__, data); | |
b5e2fec0 | 3086 | break; |
9ba075a6 | 3087 | case 0x200 ... 0x2ff: |
ff53604b | 3088 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 3089 | case MSR_IA32_APICBASE: |
58cb628d | 3090 | return kvm_set_apic_base(vcpu, msr_info); |
bf10bd0b | 3091 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
0105d1a5 | 3092 | return kvm_x2apic_msr_write(vcpu, msr, data); |
a3e06bbe LJ |
3093 | case MSR_IA32_TSCDEADLINE: |
3094 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
3095 | break; | |
ba904635 | 3096 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 3097 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 3098 | if (!msr_info->host_initiated) { |
d913b904 | 3099 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 3100 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
3101 | } |
3102 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
3103 | } | |
3104 | break; | |
15c4a640 | 3105 | case MSR_IA32_MISC_ENABLE: |
511a8556 WL |
3106 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
3107 | ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { | |
3108 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) | |
3109 | return 1; | |
3110 | vcpu->arch.ia32_misc_enable_msr = data; | |
aedbaf4f | 3111 | kvm_update_cpuid_runtime(vcpu); |
511a8556 WL |
3112 | } else { |
3113 | vcpu->arch.ia32_misc_enable_msr = data; | |
3114 | } | |
15c4a640 | 3115 | break; |
64d60670 PB |
3116 | case MSR_IA32_SMBASE: |
3117 | if (!msr_info->host_initiated) | |
3118 | return 1; | |
3119 | vcpu->arch.smbase = data; | |
3120 | break; | |
73f624f4 PB |
3121 | case MSR_IA32_POWER_CTL: |
3122 | vcpu->arch.msr_ia32_power_ctl = data; | |
3123 | break; | |
dd259935 | 3124 | case MSR_IA32_TSC: |
0c899c25 PB |
3125 | if (msr_info->host_initiated) { |
3126 | kvm_synchronize_tsc(vcpu, data); | |
3127 | } else { | |
3128 | u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; | |
3129 | adjust_tsc_offset_guest(vcpu, adj); | |
3130 | vcpu->arch.ia32_tsc_adjust_msr += adj; | |
3131 | } | |
dd259935 | 3132 | break; |
864e2ab2 AL |
3133 | case MSR_IA32_XSS: |
3134 | if (!msr_info->host_initiated && | |
3135 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3136 | return 1; | |
3137 | /* | |
a1bead2a SC |
3138 | * KVM supports exposing PT to the guest, but does not support |
3139 | * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than | |
3140 | * XSAVES/XRSTORS to save/restore PT MSRs. | |
864e2ab2 | 3141 | */ |
408e9a31 | 3142 | if (data & ~supported_xss) |
864e2ab2 AL |
3143 | return 1; |
3144 | vcpu->arch.ia32_xss = data; | |
3145 | break; | |
52797bf9 LA |
3146 | case MSR_SMI_COUNT: |
3147 | if (!msr_info->host_initiated) | |
3148 | return 1; | |
3149 | vcpu->arch.smi_count = data; | |
3150 | break; | |
11c6bffa | 3151 | case MSR_KVM_WALL_CLOCK_NEW: |
66570e96 OU |
3152 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3153 | return 1; | |
3154 | ||
3155 | kvm_write_wall_clock(vcpu->kvm, data); | |
3156 | break; | |
18068523 | 3157 | case MSR_KVM_WALL_CLOCK: |
66570e96 OU |
3158 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3159 | return 1; | |
3160 | ||
18068523 GOC |
3161 | kvm_write_wall_clock(vcpu->kvm, data); |
3162 | break; | |
11c6bffa | 3163 | case MSR_KVM_SYSTEM_TIME_NEW: |
66570e96 OU |
3164 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3165 | return 1; | |
3166 | ||
5b9bb0eb OU |
3167 | kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); |
3168 | break; | |
3169 | case MSR_KVM_SYSTEM_TIME: | |
66570e96 OU |
3170 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3171 | return 1; | |
3172 | ||
3173 | kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); | |
18068523 | 3174 | break; |
344d9588 | 3175 | case MSR_KVM_ASYNC_PF_EN: |
66570e96 OU |
3176 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3177 | return 1; | |
3178 | ||
344d9588 GN |
3179 | if (kvm_pv_enable_async_pf(vcpu, data)) |
3180 | return 1; | |
3181 | break; | |
2635b5c4 | 3182 | case MSR_KVM_ASYNC_PF_INT: |
66570e96 OU |
3183 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3184 | return 1; | |
3185 | ||
2635b5c4 VK |
3186 | if (kvm_pv_enable_async_pf_int(vcpu, data)) |
3187 | return 1; | |
3188 | break; | |
557a961a | 3189 | case MSR_KVM_ASYNC_PF_ACK: |
66570e96 OU |
3190 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3191 | return 1; | |
557a961a VK |
3192 | if (data & 0x1) { |
3193 | vcpu->arch.apf.pageready_pending = false; | |
3194 | kvm_check_async_pf_completion(vcpu); | |
3195 | } | |
3196 | break; | |
c9aaa895 | 3197 | case MSR_KVM_STEAL_TIME: |
66570e96 OU |
3198 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3199 | return 1; | |
c9aaa895 GC |
3200 | |
3201 | if (unlikely(!sched_info_on())) | |
3202 | return 1; | |
3203 | ||
3204 | if (data & KVM_STEAL_RESERVED_MASK) | |
3205 | return 1; | |
3206 | ||
c9aaa895 GC |
3207 | vcpu->arch.st.msr_val = data; |
3208 | ||
3209 | if (!(data & KVM_MSR_ENABLED)) | |
3210 | break; | |
3211 | ||
c9aaa895 GC |
3212 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
3213 | ||
3214 | break; | |
ae7a2a3f | 3215 | case MSR_KVM_PV_EOI_EN: |
66570e96 OU |
3216 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3217 | return 1; | |
3218 | ||
72bbf935 | 3219 | if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
3220 | return 1; |
3221 | break; | |
c9aaa895 | 3222 | |
2d5ba19b | 3223 | case MSR_KVM_POLL_CONTROL: |
66570e96 OU |
3224 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3225 | return 1; | |
3226 | ||
2d5ba19b MT |
3227 | /* only enable bit supported */ |
3228 | if (data & (-1ULL << 1)) | |
3229 | return 1; | |
3230 | ||
3231 | vcpu->arch.msr_kvm_poll_control = data; | |
3232 | break; | |
3233 | ||
890ca9ae HY |
3234 | case MSR_IA32_MCG_CTL: |
3235 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3236 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 3237 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 3238 | |
6912ac32 WH |
3239 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
3240 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
df561f66 GS |
3241 | pr = true; |
3242 | fallthrough; | |
6912ac32 WH |
3243 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3244 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3245 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3246 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
3247 | |
3248 | if (pr || data != 0) | |
a737f256 CD |
3249 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
3250 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 3251 | break; |
84e0cefa JS |
3252 | case MSR_K7_CLK_CTL: |
3253 | /* | |
3254 | * Ignore all writes to this no longer documented MSR. | |
3255 | * Writes are only relevant for old K7 processors, | |
3256 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 3257 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
3258 | * affected processor models on the command line, hence |
3259 | * the need to ignore the workaround. | |
3260 | */ | |
3261 | break; | |
55cd8e5a | 3262 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3263 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3264 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3265 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3266 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3267 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3268 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3269 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3270 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
3271 | return kvm_hv_set_msr_common(vcpu, msr, data, |
3272 | msr_info->host_initiated); | |
91c9c3ed | 3273 | case MSR_IA32_BBL_CR_CTL3: |
3274 | /* Drop writes to this legacy MSR -- see rdmsr | |
3275 | * counterpart for further detail. | |
3276 | */ | |
fab0aa3b EM |
3277 | if (report_ignored_msrs) |
3278 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
3279 | msr, data); | |
91c9c3ed | 3280 | break; |
2b036c6b | 3281 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3282 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3283 | return 1; |
3284 | vcpu->arch.osvw.length = data; | |
3285 | break; | |
3286 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3287 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3288 | return 1; |
3289 | vcpu->arch.osvw.status = data; | |
3290 | break; | |
db2336a8 KH |
3291 | case MSR_PLATFORM_INFO: |
3292 | if (!msr_info->host_initiated || | |
db2336a8 KH |
3293 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
3294 | cpuid_fault_enabled(vcpu))) | |
3295 | return 1; | |
3296 | vcpu->arch.msr_platform_info = data; | |
3297 | break; | |
3298 | case MSR_MISC_FEATURES_ENABLES: | |
3299 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
3300 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
3301 | !supports_cpuid_fault(vcpu))) | |
3302 | return 1; | |
3303 | vcpu->arch.msr_misc_features_enables = data; | |
3304 | break; | |
15c4a640 | 3305 | default: |
ffde22ac ES |
3306 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
3307 | return xen_hvm_config(vcpu, data); | |
c6702c9d | 3308 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3309 | return kvm_pmu_set_msr(vcpu, msr_info); |
6abe9c13 | 3310 | return KVM_MSR_RET_INVALID; |
15c4a640 CO |
3311 | } |
3312 | return 0; | |
3313 | } | |
3314 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
3315 | ||
44883f01 | 3316 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
3317 | { |
3318 | u64 data; | |
890ca9ae HY |
3319 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3320 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
3321 | |
3322 | switch (msr) { | |
15c4a640 CO |
3323 | case MSR_IA32_P5_MC_ADDR: |
3324 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
3325 | data = 0; |
3326 | break; | |
15c4a640 | 3327 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
3328 | data = vcpu->arch.mcg_cap; |
3329 | break; | |
c7ac679c | 3330 | case MSR_IA32_MCG_CTL: |
44883f01 | 3331 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
3332 | return 1; |
3333 | data = vcpu->arch.mcg_ctl; | |
3334 | break; | |
3335 | case MSR_IA32_MCG_STATUS: | |
3336 | data = vcpu->arch.mcg_status; | |
3337 | break; | |
3338 | default: | |
3339 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3340 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3341 | u32 offset = array_index_nospec( |
3342 | msr - MSR_IA32_MC0_CTL, | |
3343 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3344 | ||
890ca9ae HY |
3345 | data = vcpu->arch.mce_banks[offset]; |
3346 | break; | |
3347 | } | |
3348 | return 1; | |
3349 | } | |
3350 | *pdata = data; | |
3351 | return 0; | |
3352 | } | |
3353 | ||
609e36d3 | 3354 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 3355 | { |
609e36d3 | 3356 | switch (msr_info->index) { |
890ca9ae | 3357 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 3358 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
3359 | case MSR_IA32_DEBUGCTLMSR: |
3360 | case MSR_IA32_LASTBRANCHFROMIP: | |
3361 | case MSR_IA32_LASTBRANCHTOIP: | |
3362 | case MSR_IA32_LASTINTFROMIP: | |
3363 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd | 3364 | case MSR_K8_SYSCFG: |
3afb1121 PB |
3365 | case MSR_K8_TSEG_ADDR: |
3366 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 3367 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 3368 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 3369 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 3370 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 3371 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 3372 | case MSR_IA32_PERF_CTL: |
405a353a | 3373 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3374 | case MSR_F15H_EX_CFG: |
2ca1a06a VS |
3375 | /* |
3376 | * Intel Sandy Bridge CPUs must support the RAPL (running average power | |
3377 | * limit) MSRs. Just return 0, as we do not want to expose the host | |
3378 | * data here. Do not conditionalize this on CPUID, as KVM does not do | |
3379 | * so for existing CPU-specific MSRs. | |
3380 | */ | |
3381 | case MSR_RAPL_POWER_UNIT: | |
3382 | case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ | |
3383 | case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ | |
3384 | case MSR_PKG_ENERGY_STATUS: /* Total package */ | |
3385 | case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ | |
609e36d3 | 3386 | msr_info->data = 0; |
15c4a640 | 3387 | break; |
c51eb52b | 3388 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
6912ac32 WH |
3389 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3390 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
3391 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
3392 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3393 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3394 | return kvm_pmu_get_msr(vcpu, msr_info); |
609e36d3 | 3395 | msr_info->data = 0; |
5753785f | 3396 | break; |
742bc670 | 3397 | case MSR_IA32_UCODE_REV: |
518e7b94 | 3398 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 3399 | break; |
0cf9135b SC |
3400 | case MSR_IA32_ARCH_CAPABILITIES: |
3401 | if (!msr_info->host_initiated && | |
3402 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3403 | return 1; | |
3404 | msr_info->data = vcpu->arch.arch_capabilities; | |
3405 | break; | |
d574c539 VK |
3406 | case MSR_IA32_PERF_CAPABILITIES: |
3407 | if (!msr_info->host_initiated && | |
3408 | !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) | |
3409 | return 1; | |
3410 | msr_info->data = vcpu->arch.perf_capabilities; | |
3411 | break; | |
73f624f4 PB |
3412 | case MSR_IA32_POWER_CTL: |
3413 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
3414 | break; | |
cc5b54dd ML |
3415 | case MSR_IA32_TSC: { |
3416 | /* | |
3417 | * Intel SDM states that MSR_IA32_TSC read adds the TSC offset | |
3418 | * even when not intercepted. AMD manual doesn't explicitly | |
3419 | * state this but appears to behave the same. | |
3420 | * | |
ee6fa053 | 3421 | * On userspace reads and writes, however, we unconditionally |
c0623f5e | 3422 | * return L1's TSC value to ensure backwards-compatible |
ee6fa053 | 3423 | * behavior for migration. |
cc5b54dd ML |
3424 | */ |
3425 | u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset : | |
3426 | vcpu->arch.tsc_offset; | |
3427 | ||
3428 | msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset; | |
dd259935 | 3429 | break; |
cc5b54dd | 3430 | } |
9ba075a6 | 3431 | case MSR_MTRRcap: |
9ba075a6 | 3432 | case 0x200 ... 0x2ff: |
ff53604b | 3433 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 3434 | case 0xcd: /* fsb frequency */ |
609e36d3 | 3435 | msr_info->data = 3; |
15c4a640 | 3436 | break; |
7b914098 JS |
3437 | /* |
3438 | * MSR_EBC_FREQUENCY_ID | |
3439 | * Conservative value valid for even the basic CPU models. | |
3440 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
3441 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
3442 | * and 266MHz for model 3, or 4. Set Core Clock | |
3443 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
3444 | * 31:24) even though these are only valid for CPU | |
3445 | * models > 2, however guests may end up dividing or | |
3446 | * multiplying by zero otherwise. | |
3447 | */ | |
3448 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 3449 | msr_info->data = 1 << 24; |
7b914098 | 3450 | break; |
15c4a640 | 3451 | case MSR_IA32_APICBASE: |
609e36d3 | 3452 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 3453 | break; |
bf10bd0b | 3454 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
609e36d3 | 3455 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
a3e06bbe | 3456 | case MSR_IA32_TSCDEADLINE: |
609e36d3 | 3457 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 3458 | break; |
ba904635 | 3459 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 3460 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 3461 | break; |
15c4a640 | 3462 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 3463 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 3464 | break; |
64d60670 PB |
3465 | case MSR_IA32_SMBASE: |
3466 | if (!msr_info->host_initiated) | |
3467 | return 1; | |
3468 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 3469 | break; |
52797bf9 LA |
3470 | case MSR_SMI_COUNT: |
3471 | msr_info->data = vcpu->arch.smi_count; | |
3472 | break; | |
847f0ad8 AG |
3473 | case MSR_IA32_PERF_STATUS: |
3474 | /* TSC increment by tick */ | |
609e36d3 | 3475 | msr_info->data = 1000ULL; |
847f0ad8 | 3476 | /* CPU multiplier */ |
b0996ae4 | 3477 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 3478 | break; |
15c4a640 | 3479 | case MSR_EFER: |
609e36d3 | 3480 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 3481 | break; |
18068523 | 3482 | case MSR_KVM_WALL_CLOCK: |
1930e5dd OU |
3483 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3484 | return 1; | |
3485 | ||
3486 | msr_info->data = vcpu->kvm->arch.wall_clock; | |
3487 | break; | |
11c6bffa | 3488 | case MSR_KVM_WALL_CLOCK_NEW: |
1930e5dd OU |
3489 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3490 | return 1; | |
3491 | ||
609e36d3 | 3492 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
3493 | break; |
3494 | case MSR_KVM_SYSTEM_TIME: | |
1930e5dd OU |
3495 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3496 | return 1; | |
3497 | ||
3498 | msr_info->data = vcpu->arch.time; | |
3499 | break; | |
11c6bffa | 3500 | case MSR_KVM_SYSTEM_TIME_NEW: |
1930e5dd OU |
3501 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3502 | return 1; | |
3503 | ||
609e36d3 | 3504 | msr_info->data = vcpu->arch.time; |
18068523 | 3505 | break; |
344d9588 | 3506 | case MSR_KVM_ASYNC_PF_EN: |
1930e5dd OU |
3507 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3508 | return 1; | |
3509 | ||
2635b5c4 VK |
3510 | msr_info->data = vcpu->arch.apf.msr_en_val; |
3511 | break; | |
3512 | case MSR_KVM_ASYNC_PF_INT: | |
1930e5dd OU |
3513 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3514 | return 1; | |
3515 | ||
2635b5c4 | 3516 | msr_info->data = vcpu->arch.apf.msr_int_val; |
344d9588 | 3517 | break; |
557a961a | 3518 | case MSR_KVM_ASYNC_PF_ACK: |
1930e5dd OU |
3519 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3520 | return 1; | |
3521 | ||
557a961a VK |
3522 | msr_info->data = 0; |
3523 | break; | |
c9aaa895 | 3524 | case MSR_KVM_STEAL_TIME: |
1930e5dd OU |
3525 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3526 | return 1; | |
3527 | ||
609e36d3 | 3528 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 3529 | break; |
1d92128f | 3530 | case MSR_KVM_PV_EOI_EN: |
1930e5dd OU |
3531 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3532 | return 1; | |
3533 | ||
609e36d3 | 3534 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 3535 | break; |
2d5ba19b | 3536 | case MSR_KVM_POLL_CONTROL: |
1930e5dd OU |
3537 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3538 | return 1; | |
3539 | ||
2d5ba19b MT |
3540 | msr_info->data = vcpu->arch.msr_kvm_poll_control; |
3541 | break; | |
890ca9ae HY |
3542 | case MSR_IA32_P5_MC_ADDR: |
3543 | case MSR_IA32_P5_MC_TYPE: | |
3544 | case MSR_IA32_MCG_CAP: | |
3545 | case MSR_IA32_MCG_CTL: | |
3546 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3547 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
3548 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
3549 | msr_info->host_initiated); | |
864e2ab2 AL |
3550 | case MSR_IA32_XSS: |
3551 | if (!msr_info->host_initiated && | |
3552 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3553 | return 1; | |
3554 | msr_info->data = vcpu->arch.ia32_xss; | |
3555 | break; | |
84e0cefa JS |
3556 | case MSR_K7_CLK_CTL: |
3557 | /* | |
3558 | * Provide expected ramp-up count for K7. All other | |
3559 | * are set to zero, indicating minimum divisors for | |
3560 | * every field. | |
3561 | * | |
3562 | * This prevents guest kernels on AMD host with CPU | |
3563 | * type 6, model 8 and higher from exploding due to | |
3564 | * the rdmsr failing. | |
3565 | */ | |
609e36d3 | 3566 | msr_info->data = 0x20000000; |
84e0cefa | 3567 | break; |
55cd8e5a | 3568 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3569 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3570 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3571 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3572 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3573 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3574 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3575 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3576 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 3577 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
3578 | msr_info->index, &msr_info->data, |
3579 | msr_info->host_initiated); | |
91c9c3ed | 3580 | case MSR_IA32_BBL_CR_CTL3: |
3581 | /* This legacy MSR exists but isn't fully documented in current | |
3582 | * silicon. It is however accessed by winxp in very narrow | |
3583 | * scenarios where it sets bit #19, itself documented as | |
3584 | * a "reserved" bit. Best effort attempt to source coherent | |
3585 | * read data here should the balance of the register be | |
3586 | * interpreted by the guest: | |
3587 | * | |
3588 | * L2 cache control register 3: 64GB range, 256KB size, | |
3589 | * enabled, latency 0x1, configured | |
3590 | */ | |
609e36d3 | 3591 | msr_info->data = 0xbe702111; |
91c9c3ed | 3592 | break; |
2b036c6b | 3593 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3594 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3595 | return 1; |
609e36d3 | 3596 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
3597 | break; |
3598 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3599 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3600 | return 1; |
609e36d3 | 3601 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 3602 | break; |
db2336a8 | 3603 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
3604 | if (!msr_info->host_initiated && |
3605 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
3606 | return 1; | |
db2336a8 KH |
3607 | msr_info->data = vcpu->arch.msr_platform_info; |
3608 | break; | |
3609 | case MSR_MISC_FEATURES_ENABLES: | |
3610 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
3611 | break; | |
191c8137 BP |
3612 | case MSR_K7_HWCR: |
3613 | msr_info->data = vcpu->arch.msr_hwcr; | |
3614 | break; | |
15c4a640 | 3615 | default: |
c6702c9d | 3616 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3617 | return kvm_pmu_get_msr(vcpu, msr_info); |
6abe9c13 | 3618 | return KVM_MSR_RET_INVALID; |
15c4a640 | 3619 | } |
15c4a640 CO |
3620 | return 0; |
3621 | } | |
3622 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
3623 | ||
313a3dc7 CO |
3624 | /* |
3625 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
3626 | * | |
3627 | * @return number of msrs set successfully. | |
3628 | */ | |
3629 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
3630 | struct kvm_msr_entry *entries, | |
3631 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3632 | unsigned index, u64 *data)) | |
3633 | { | |
801e459a | 3634 | int i; |
313a3dc7 | 3635 | |
313a3dc7 CO |
3636 | for (i = 0; i < msrs->nmsrs; ++i) |
3637 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
3638 | break; | |
3639 | ||
313a3dc7 CO |
3640 | return i; |
3641 | } | |
3642 | ||
3643 | /* | |
3644 | * Read or write a bunch of msrs. Parameters are user addresses. | |
3645 | * | |
3646 | * @return number of msrs set successfully. | |
3647 | */ | |
3648 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
3649 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3650 | unsigned index, u64 *data), | |
3651 | int writeback) | |
3652 | { | |
3653 | struct kvm_msrs msrs; | |
3654 | struct kvm_msr_entry *entries; | |
3655 | int r, n; | |
3656 | unsigned size; | |
3657 | ||
3658 | r = -EFAULT; | |
0e96f31e | 3659 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
3660 | goto out; |
3661 | ||
3662 | r = -E2BIG; | |
3663 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
3664 | goto out; | |
3665 | ||
313a3dc7 | 3666 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
3667 | entries = memdup_user(user_msrs->entries, size); |
3668 | if (IS_ERR(entries)) { | |
3669 | r = PTR_ERR(entries); | |
313a3dc7 | 3670 | goto out; |
ff5c2c03 | 3671 | } |
313a3dc7 CO |
3672 | |
3673 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
3674 | if (r < 0) | |
3675 | goto out_free; | |
3676 | ||
3677 | r = -EFAULT; | |
3678 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
3679 | goto out_free; | |
3680 | ||
3681 | r = n; | |
3682 | ||
3683 | out_free: | |
7a73c028 | 3684 | kfree(entries); |
313a3dc7 CO |
3685 | out: |
3686 | return r; | |
3687 | } | |
3688 | ||
4d5422ce WL |
3689 | static inline bool kvm_can_mwait_in_guest(void) |
3690 | { | |
3691 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
3692 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
3693 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
3694 | } |
3695 | ||
c21d54f0 VK |
3696 | static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, |
3697 | struct kvm_cpuid2 __user *cpuid_arg) | |
3698 | { | |
3699 | struct kvm_cpuid2 cpuid; | |
3700 | int r; | |
3701 | ||
3702 | r = -EFAULT; | |
3703 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
3704 | return r; | |
3705 | ||
3706 | r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
3707 | if (r) | |
3708 | return r; | |
3709 | ||
3710 | r = -EFAULT; | |
3711 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
3712 | return r; | |
3713 | ||
3714 | return 0; | |
3715 | } | |
3716 | ||
784aa3d7 | 3717 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 3718 | { |
4d5422ce | 3719 | int r = 0; |
018d00d2 ZX |
3720 | |
3721 | switch (ext) { | |
3722 | case KVM_CAP_IRQCHIP: | |
3723 | case KVM_CAP_HLT: | |
3724 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 3725 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 3726 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 3727 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 3728 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 3729 | case KVM_CAP_PIT: |
a28e4f5a | 3730 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 3731 | case KVM_CAP_MP_STATE: |
ed848624 | 3732 | case KVM_CAP_SYNC_MMU: |
a355c85c | 3733 | case KVM_CAP_USER_NMI: |
52d939a0 | 3734 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 3735 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 3736 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 3737 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 3738 | case KVM_CAP_PIT2: |
e9f42757 | 3739 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 3740 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 3741 | case KVM_CAP_XEN_HVM: |
3cfc3092 | 3742 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 3743 | case KVM_CAP_HYPERV: |
10388a07 | 3744 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 3745 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 3746 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 3747 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 3748 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 3749 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 3750 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 3751 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 3752 | case KVM_CAP_HYPERV_CPUID: |
c21d54f0 | 3753 | case KVM_CAP_SYS_HYPERV_CPUID: |
ab9f4ecb | 3754 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 3755 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 3756 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 3757 | case KVM_CAP_XSAVE: |
344d9588 | 3758 | case KVM_CAP_ASYNC_PF: |
72de5fa4 | 3759 | case KVM_CAP_ASYNC_PF_INT: |
92a1f12d | 3760 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 3761 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 3762 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 3763 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 3764 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 3765 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 3766 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 3767 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 3768 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 3769 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 3770 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 3771 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 3772 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 3773 | case KVM_CAP_EXCEPTION_PAYLOAD: |
b9b2782c | 3774 | case KVM_CAP_SET_GUEST_DEBUG: |
1aa561b1 | 3775 | case KVM_CAP_LAST_CPU: |
1ae09954 | 3776 | case KVM_CAP_X86_USER_SPACE_MSR: |
1a155254 | 3777 | case KVM_CAP_X86_MSR_FILTER: |
66570e96 | 3778 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
018d00d2 ZX |
3779 | r = 1; |
3780 | break; | |
01643c51 KH |
3781 | case KVM_CAP_SYNC_REGS: |
3782 | r = KVM_SYNC_X86_VALID_FIELDS; | |
3783 | break; | |
e3fd9a93 PB |
3784 | case KVM_CAP_ADJUST_CLOCK: |
3785 | r = KVM_CLOCK_TSC_STABLE; | |
3786 | break; | |
4d5422ce | 3787 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
3788 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
3789 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
3790 | if(kvm_can_mwait_in_guest()) |
3791 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 3792 | break; |
6d396b55 PB |
3793 | case KVM_CAP_X86_SMM: |
3794 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
3795 | * and SMM handlers might indeed rely on 4G segment limits, | |
3796 | * so do not report SMM to be available if real mode is | |
3797 | * emulated via vm86 mode. Still, do not go to great lengths | |
3798 | * to avoid userspace's usage of the feature, because it is a | |
3799 | * fringe case that is not enabled except via specific settings | |
3800 | * of the module parameters. | |
3801 | */ | |
5719455f | 3802 | r = kvm_x86_ops.has_emulated_msr(kvm, MSR_IA32_SMBASE); |
6d396b55 | 3803 | break; |
774ead3a | 3804 | case KVM_CAP_VAPIC: |
afaf0b2f | 3805 | r = !kvm_x86_ops.cpu_has_accelerated_tpr(); |
774ead3a | 3806 | break; |
f725230a | 3807 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
3808 | r = KVM_SOFT_MAX_VCPUS; |
3809 | break; | |
3810 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
3811 | r = KVM_MAX_VCPUS; |
3812 | break; | |
a86cb413 TH |
3813 | case KVM_CAP_MAX_VCPU_ID: |
3814 | r = KVM_MAX_VCPU_ID; | |
3815 | break; | |
a68a6a72 MT |
3816 | case KVM_CAP_PV_MMU: /* obsolete */ |
3817 | r = 0; | |
2f333bcb | 3818 | break; |
890ca9ae HY |
3819 | case KVM_CAP_MCE: |
3820 | r = KVM_MAX_MCE_BANKS; | |
3821 | break; | |
2d5b5a66 | 3822 | case KVM_CAP_XCRS: |
d366bf7e | 3823 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 3824 | break; |
92a1f12d JR |
3825 | case KVM_CAP_TSC_CONTROL: |
3826 | r = kvm_has_tsc_control; | |
3827 | break; | |
37131313 RK |
3828 | case KVM_CAP_X2APIC_API: |
3829 | r = KVM_X2APIC_API_VALID_FLAGS; | |
3830 | break; | |
8fcc4b59 | 3831 | case KVM_CAP_NESTED_STATE: |
33b22172 PB |
3832 | r = kvm_x86_ops.nested_ops->get_state ? |
3833 | kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; | |
8fcc4b59 | 3834 | break; |
344c6c80 | 3835 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 3836 | r = kvm_x86_ops.enable_direct_tlbflush != NULL; |
5a0165f6 VK |
3837 | break; |
3838 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
33b22172 | 3839 | r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; |
344c6c80 | 3840 | break; |
3edd6839 MG |
3841 | case KVM_CAP_SMALLER_MAXPHYADDR: |
3842 | r = (int) allow_smaller_maxphyaddr; | |
3843 | break; | |
004a0124 AJ |
3844 | case KVM_CAP_STEAL_TIME: |
3845 | r = sched_info_on(); | |
3846 | break; | |
018d00d2 | 3847 | default: |
018d00d2 ZX |
3848 | break; |
3849 | } | |
3850 | return r; | |
3851 | ||
3852 | } | |
3853 | ||
043405e1 CO |
3854 | long kvm_arch_dev_ioctl(struct file *filp, |
3855 | unsigned int ioctl, unsigned long arg) | |
3856 | { | |
3857 | void __user *argp = (void __user *)arg; | |
3858 | long r; | |
3859 | ||
3860 | switch (ioctl) { | |
3861 | case KVM_GET_MSR_INDEX_LIST: { | |
3862 | struct kvm_msr_list __user *user_msr_list = argp; | |
3863 | struct kvm_msr_list msr_list; | |
3864 | unsigned n; | |
3865 | ||
3866 | r = -EFAULT; | |
0e96f31e | 3867 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
3868 | goto out; |
3869 | n = msr_list.nmsrs; | |
62ef68bb | 3870 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 3871 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
3872 | goto out; |
3873 | r = -E2BIG; | |
e125e7b6 | 3874 | if (n < msr_list.nmsrs) |
043405e1 CO |
3875 | goto out; |
3876 | r = -EFAULT; | |
3877 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
3878 | num_msrs_to_save * sizeof(u32))) | |
3879 | goto out; | |
e125e7b6 | 3880 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 3881 | &emulated_msrs, |
62ef68bb | 3882 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
3883 | goto out; |
3884 | r = 0; | |
3885 | break; | |
3886 | } | |
9c15bb1d BP |
3887 | case KVM_GET_SUPPORTED_CPUID: |
3888 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
3889 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
3890 | struct kvm_cpuid2 cpuid; | |
3891 | ||
3892 | r = -EFAULT; | |
0e96f31e | 3893 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 3894 | goto out; |
9c15bb1d BP |
3895 | |
3896 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
3897 | ioctl); | |
674eea0f AK |
3898 | if (r) |
3899 | goto out; | |
3900 | ||
3901 | r = -EFAULT; | |
0e96f31e | 3902 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
3903 | goto out; |
3904 | r = 0; | |
3905 | break; | |
3906 | } | |
cf6c26ec | 3907 | case KVM_X86_GET_MCE_CAP_SUPPORTED: |
890ca9ae | 3908 | r = -EFAULT; |
c45dcc71 AR |
3909 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
3910 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
3911 | goto out; |
3912 | r = 0; | |
3913 | break; | |
801e459a TL |
3914 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
3915 | struct kvm_msr_list __user *user_msr_list = argp; | |
3916 | struct kvm_msr_list msr_list; | |
3917 | unsigned int n; | |
3918 | ||
3919 | r = -EFAULT; | |
3920 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
3921 | goto out; | |
3922 | n = msr_list.nmsrs; | |
3923 | msr_list.nmsrs = num_msr_based_features; | |
3924 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
3925 | goto out; | |
3926 | r = -E2BIG; | |
3927 | if (n < msr_list.nmsrs) | |
3928 | goto out; | |
3929 | r = -EFAULT; | |
3930 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
3931 | num_msr_based_features * sizeof(u32))) | |
3932 | goto out; | |
3933 | r = 0; | |
3934 | break; | |
3935 | } | |
3936 | case KVM_GET_MSRS: | |
3937 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
3938 | break; | |
c21d54f0 VK |
3939 | case KVM_GET_SUPPORTED_HV_CPUID: |
3940 | r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); | |
3941 | break; | |
043405e1 CO |
3942 | default: |
3943 | r = -EINVAL; | |
cf6c26ec | 3944 | break; |
043405e1 CO |
3945 | } |
3946 | out: | |
3947 | return r; | |
3948 | } | |
3949 | ||
f5f48ee1 SY |
3950 | static void wbinvd_ipi(void *garbage) |
3951 | { | |
3952 | wbinvd(); | |
3953 | } | |
3954 | ||
3955 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
3956 | { | |
e0f0bbc5 | 3957 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
3958 | } |
3959 | ||
313a3dc7 CO |
3960 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
3961 | { | |
f5f48ee1 SY |
3962 | /* Address WBINVD may be executed by guest */ |
3963 | if (need_emulate_wbinvd(vcpu)) { | |
afaf0b2f | 3964 | if (kvm_x86_ops.has_wbinvd_exit()) |
f5f48ee1 SY |
3965 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); |
3966 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
3967 | smp_call_function_single(vcpu->cpu, | |
3968 | wbinvd_ipi, NULL, 1); | |
3969 | } | |
3970 | ||
afaf0b2f | 3971 | kvm_x86_ops.vcpu_load(vcpu, cpu); |
8f6055cb | 3972 | |
37486135 BM |
3973 | /* Save host pkru register if supported */ |
3974 | vcpu->arch.host_pkru = read_pkru(); | |
3975 | ||
0dd6a6ed ZA |
3976 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
3977 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
3978 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
3979 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 3980 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 3981 | } |
8f6055cb | 3982 | |
b0c39dc6 | 3983 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 3984 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 3985 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
3986 | if (tsc_delta < 0) |
3987 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 3988 | |
b0c39dc6 | 3989 | if (kvm_check_tsc_unstable()) { |
07c1419a | 3990 | u64 offset = kvm_compute_tsc_offset(vcpu, |
b183aa58 | 3991 | vcpu->arch.last_guest_tsc); |
a545ab6a | 3992 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 3993 | vcpu->arch.tsc_catchup = 1; |
c285545f | 3994 | } |
a749e247 PB |
3995 | |
3996 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
3997 | kvm_lapic_restart_hv_timer(vcpu); | |
3998 | ||
d98d07ca MT |
3999 | /* |
4000 | * On a host with synchronized TSC, there is no need to update | |
4001 | * kvmclock on vcpu->cpu migration | |
4002 | */ | |
4003 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 4004 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 4005 | if (vcpu->cpu != cpu) |
1bd2009e | 4006 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 4007 | vcpu->cpu = cpu; |
6b7d7e76 | 4008 | } |
c9aaa895 | 4009 | |
c9aaa895 | 4010 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
4011 | } |
4012 | ||
0b9f6c46 PX |
4013 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
4014 | { | |
b0431382 BO |
4015 | struct kvm_host_map map; |
4016 | struct kvm_steal_time *st; | |
4017 | ||
0b9f6c46 PX |
4018 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
4019 | return; | |
4020 | ||
a6bd811f | 4021 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
4022 | return; |
4023 | ||
b0431382 BO |
4024 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, |
4025 | &vcpu->arch.st.cache, true)) | |
4026 | return; | |
4027 | ||
4028 | st = map.hva + | |
4029 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
0b9f6c46 | 4030 | |
a6bd811f | 4031 | st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; |
0b9f6c46 | 4032 | |
b0431382 | 4033 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); |
0b9f6c46 PX |
4034 | } |
4035 | ||
313a3dc7 CO |
4036 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
4037 | { | |
cc0d907c | 4038 | int idx; |
de63ad4c | 4039 | |
f1c6366e | 4040 | if (vcpu->preempted && !vcpu->arch.guest_state_protected) |
afaf0b2f | 4041 | vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu); |
de63ad4c | 4042 | |
931f261b AA |
4043 | /* |
4044 | * Disable page faults because we're in atomic context here. | |
4045 | * kvm_write_guest_offset_cached() would call might_fault() | |
4046 | * that relies on pagefault_disable() to tell if there's a | |
4047 | * bug. NOTE: the write to guest memory may not go through if | |
4048 | * during postcopy live migration or if there's heavy guest | |
4049 | * paging. | |
4050 | */ | |
4051 | pagefault_disable(); | |
cc0d907c AA |
4052 | /* |
4053 | * kvm_memslots() will be called by | |
4054 | * kvm_write_guest_offset_cached() so take the srcu lock. | |
4055 | */ | |
4056 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
0b9f6c46 | 4057 | kvm_steal_time_set_preempted(vcpu); |
cc0d907c | 4058 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
931f261b | 4059 | pagefault_enable(); |
afaf0b2f | 4060 | kvm_x86_ops.vcpu_put(vcpu); |
4ea1636b | 4061 | vcpu->arch.last_host_tsc = rdtsc(); |
efdab992 | 4062 | /* |
f9dcf08e RK |
4063 | * If userspace has set any breakpoints or watchpoints, dr6 is restored |
4064 | * on every vmexit, but if not, we might have a stale dr6 from the | |
4065 | * guest. do_debug expects dr6 to be cleared after it runs, do the same. | |
efdab992 | 4066 | */ |
f9dcf08e | 4067 | set_debugreg(0, 6); |
313a3dc7 CO |
4068 | } |
4069 | ||
313a3dc7 CO |
4070 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
4071 | struct kvm_lapic_state *s) | |
4072 | { | |
fa59cc00 | 4073 | if (vcpu->arch.apicv_active) |
afaf0b2f | 4074 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
d62caabb | 4075 | |
a92e2543 | 4076 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
4077 | } |
4078 | ||
4079 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
4080 | struct kvm_lapic_state *s) | |
4081 | { | |
a92e2543 RK |
4082 | int r; |
4083 | ||
4084 | r = kvm_apic_set_state(vcpu, s); | |
4085 | if (r) | |
4086 | return r; | |
cb142eb7 | 4087 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
4088 | |
4089 | return 0; | |
4090 | } | |
4091 | ||
127a457a MG |
4092 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
4093 | { | |
71cc849b PB |
4094 | /* |
4095 | * We can accept userspace's request for interrupt injection | |
4096 | * as long as we have a place to store the interrupt number. | |
4097 | * The actual injection will happen when the CPU is able to | |
4098 | * deliver the interrupt. | |
4099 | */ | |
4100 | if (kvm_cpu_has_extint(vcpu)) | |
4101 | return false; | |
4102 | ||
4103 | /* Acknowledging ExtINT does not happen if LINT0 is masked. */ | |
127a457a MG |
4104 | return (!lapic_in_kernel(vcpu) || |
4105 | kvm_apic_accept_pic_intr(vcpu)); | |
4106 | } | |
4107 | ||
782d422b MG |
4108 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) |
4109 | { | |
4110 | return kvm_arch_interrupt_allowed(vcpu) && | |
782d422b MG |
4111 | kvm_cpu_accept_dm_intr(vcpu); |
4112 | } | |
4113 | ||
f77bc6a4 ZX |
4114 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
4115 | struct kvm_interrupt *irq) | |
4116 | { | |
02cdb50f | 4117 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 4118 | return -EINVAL; |
1c1a9ce9 SR |
4119 | |
4120 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
4121 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
4122 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4123 | return 0; | |
4124 | } | |
4125 | ||
4126 | /* | |
4127 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
4128 | * fail for in-kernel 8259. | |
4129 | */ | |
4130 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 4131 | return -ENXIO; |
f77bc6a4 | 4132 | |
1c1a9ce9 SR |
4133 | if (vcpu->arch.pending_external_vector != -1) |
4134 | return -EEXIST; | |
f77bc6a4 | 4135 | |
1c1a9ce9 | 4136 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 4137 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
4138 | return 0; |
4139 | } | |
4140 | ||
c4abb7c9 JK |
4141 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
4142 | { | |
c4abb7c9 | 4143 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
4144 | |
4145 | return 0; | |
4146 | } | |
4147 | ||
f077825a PB |
4148 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
4149 | { | |
64d60670 PB |
4150 | kvm_make_request(KVM_REQ_SMI, vcpu); |
4151 | ||
f077825a PB |
4152 | return 0; |
4153 | } | |
4154 | ||
b209749f AK |
4155 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
4156 | struct kvm_tpr_access_ctl *tac) | |
4157 | { | |
4158 | if (tac->flags) | |
4159 | return -EINVAL; | |
4160 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
4161 | return 0; | |
4162 | } | |
4163 | ||
890ca9ae HY |
4164 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
4165 | u64 mcg_cap) | |
4166 | { | |
4167 | int r; | |
4168 | unsigned bank_num = mcg_cap & 0xff, bank; | |
4169 | ||
4170 | r = -EINVAL; | |
c4e0e4ab | 4171 | if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) |
890ca9ae | 4172 | goto out; |
c45dcc71 | 4173 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
4174 | goto out; |
4175 | r = 0; | |
4176 | vcpu->arch.mcg_cap = mcg_cap; | |
4177 | /* Init IA32_MCG_CTL to all 1s */ | |
4178 | if (mcg_cap & MCG_CTL_P) | |
4179 | vcpu->arch.mcg_ctl = ~(u64)0; | |
4180 | /* Init IA32_MCi_CTL to all 1s */ | |
4181 | for (bank = 0; bank < bank_num; bank++) | |
4182 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 | 4183 | |
afaf0b2f | 4184 | kvm_x86_ops.setup_mce(vcpu); |
890ca9ae HY |
4185 | out: |
4186 | return r; | |
4187 | } | |
4188 | ||
4189 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
4190 | struct kvm_x86_mce *mce) | |
4191 | { | |
4192 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
4193 | unsigned bank_num = mcg_cap & 0xff; | |
4194 | u64 *banks = vcpu->arch.mce_banks; | |
4195 | ||
4196 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
4197 | return -EINVAL; | |
4198 | /* | |
4199 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
4200 | * reporting is disabled | |
4201 | */ | |
4202 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
4203 | vcpu->arch.mcg_ctl != ~(u64)0) | |
4204 | return 0; | |
4205 | banks += 4 * mce->bank; | |
4206 | /* | |
4207 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
4208 | * reporting is disabled for the bank | |
4209 | */ | |
4210 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
4211 | return 0; | |
4212 | if (mce->status & MCI_STATUS_UC) { | |
4213 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 4214 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 4215 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
4216 | return 0; |
4217 | } | |
4218 | if (banks[1] & MCI_STATUS_VAL) | |
4219 | mce->status |= MCI_STATUS_OVER; | |
4220 | banks[2] = mce->addr; | |
4221 | banks[3] = mce->misc; | |
4222 | vcpu->arch.mcg_status = mce->mcg_status; | |
4223 | banks[1] = mce->status; | |
4224 | kvm_queue_exception(vcpu, MC_VECTOR); | |
4225 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
4226 | || !(banks[1] & MCI_STATUS_UC)) { | |
4227 | if (banks[1] & MCI_STATUS_VAL) | |
4228 | mce->status |= MCI_STATUS_OVER; | |
4229 | banks[2] = mce->addr; | |
4230 | banks[3] = mce->misc; | |
4231 | banks[1] = mce->status; | |
4232 | } else | |
4233 | banks[1] |= MCI_STATUS_OVER; | |
4234 | return 0; | |
4235 | } | |
4236 | ||
3cfc3092 JK |
4237 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
4238 | struct kvm_vcpu_events *events) | |
4239 | { | |
7460fb4a | 4240 | process_nmi(vcpu); |
59073aaf | 4241 | |
1f7becf1 JZ |
4242 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
4243 | process_smi(vcpu); | |
4244 | ||
a06230b6 OU |
4245 | /* |
4246 | * In guest mode, payload delivery should be deferred, | |
4247 | * so that the L1 hypervisor can intercept #PF before | |
4248 | * CR2 is modified (or intercept #DB before DR6 is | |
4249 | * modified under nVMX). Unless the per-VM capability, | |
4250 | * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of | |
4251 | * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we | |
4252 | * opportunistically defer the exception payload, deliver it if the | |
4253 | * capability hasn't been requested before processing a | |
4254 | * KVM_GET_VCPU_EVENTS. | |
4255 | */ | |
4256 | if (!vcpu->kvm->arch.exception_payload_enabled && | |
4257 | vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) | |
4258 | kvm_deliver_exception_payload(vcpu); | |
4259 | ||
664f8e26 | 4260 | /* |
59073aaf JM |
4261 | * The API doesn't provide the instruction length for software |
4262 | * exceptions, so don't report them. As long as the guest RIP | |
4263 | * isn't advanced, we should expect to encounter the exception | |
4264 | * again. | |
664f8e26 | 4265 | */ |
59073aaf JM |
4266 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
4267 | events->exception.injected = 0; | |
4268 | events->exception.pending = 0; | |
4269 | } else { | |
4270 | events->exception.injected = vcpu->arch.exception.injected; | |
4271 | events->exception.pending = vcpu->arch.exception.pending; | |
4272 | /* | |
4273 | * For ABI compatibility, deliberately conflate | |
4274 | * pending and injected exceptions when | |
4275 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
4276 | */ | |
4277 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4278 | events->exception.injected |= | |
4279 | vcpu->arch.exception.pending; | |
4280 | } | |
3cfc3092 JK |
4281 | events->exception.nr = vcpu->arch.exception.nr; |
4282 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
4283 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
4284 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
4285 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 4286 | |
03b82a30 | 4287 | events->interrupt.injected = |
04140b41 | 4288 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 4289 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 4290 | events->interrupt.soft = 0; |
afaf0b2f | 4291 | events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); |
3cfc3092 JK |
4292 | |
4293 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 4294 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
afaf0b2f | 4295 | events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu); |
97e69aa6 | 4296 | events->nmi.pad = 0; |
3cfc3092 | 4297 | |
66450a21 | 4298 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 4299 | |
f077825a PB |
4300 | events->smi.smm = is_smm(vcpu); |
4301 | events->smi.pending = vcpu->arch.smi_pending; | |
4302 | events->smi.smm_inside_nmi = | |
4303 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
4304 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
4305 | ||
dab4b911 | 4306 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
4307 | | KVM_VCPUEVENT_VALID_SHADOW |
4308 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
4309 | if (vcpu->kvm->arch.exception_payload_enabled) |
4310 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
4311 | ||
97e69aa6 | 4312 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
4313 | } |
4314 | ||
c5833c7a | 4315 | static void kvm_smm_changed(struct kvm_vcpu *vcpu); |
6ef4e07e | 4316 | |
3cfc3092 JK |
4317 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
4318 | struct kvm_vcpu_events *events) | |
4319 | { | |
dab4b911 | 4320 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 4321 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 4322 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf JM |
4323 | | KVM_VCPUEVENT_VALID_SMM |
4324 | | KVM_VCPUEVENT_VALID_PAYLOAD)) | |
3cfc3092 JK |
4325 | return -EINVAL; |
4326 | ||
59073aaf JM |
4327 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
4328 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4329 | return -EINVAL; | |
4330 | if (events->exception.pending) | |
4331 | events->exception.injected = 0; | |
4332 | else | |
4333 | events->exception_has_payload = 0; | |
4334 | } else { | |
4335 | events->exception.pending = 0; | |
4336 | events->exception_has_payload = 0; | |
4337 | } | |
4338 | ||
4339 | if ((events->exception.injected || events->exception.pending) && | |
4340 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
4341 | return -EINVAL; |
4342 | ||
28bf2888 DH |
4343 | /* INITs are latched while in SMM */ |
4344 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
4345 | (events->smi.smm || events->smi.pending) && | |
4346 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
4347 | return -EINVAL; | |
4348 | ||
7460fb4a | 4349 | process_nmi(vcpu); |
59073aaf JM |
4350 | vcpu->arch.exception.injected = events->exception.injected; |
4351 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
4352 | vcpu->arch.exception.nr = events->exception.nr; |
4353 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
4354 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
4355 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
4356 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 4357 | |
04140b41 | 4358 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
4359 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
4360 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 | 4361 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
afaf0b2f | 4362 | kvm_x86_ops.set_interrupt_shadow(vcpu, |
48005f64 | 4363 | events->interrupt.shadow); |
3cfc3092 JK |
4364 | |
4365 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
4366 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
4367 | vcpu->arch.nmi_pending = events->nmi.pending; | |
afaf0b2f | 4368 | kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked); |
3cfc3092 | 4369 | |
66450a21 | 4370 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 4371 | lapic_in_kernel(vcpu)) |
66450a21 | 4372 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 4373 | |
f077825a | 4374 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
c5833c7a SC |
4375 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { |
4376 | if (events->smi.smm) | |
4377 | vcpu->arch.hflags |= HF_SMM_MASK; | |
4378 | else | |
4379 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
4380 | kvm_smm_changed(vcpu); | |
4381 | } | |
6ef4e07e | 4382 | |
f077825a | 4383 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
4384 | |
4385 | if (events->smi.smm) { | |
4386 | if (events->smi.smm_inside_nmi) | |
4387 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 4388 | else |
f4ef1910 | 4389 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
4390 | } |
4391 | ||
4392 | if (lapic_in_kernel(vcpu)) { | |
4393 | if (events->smi.latched_init) | |
4394 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
4395 | else | |
4396 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
4397 | } |
4398 | } | |
4399 | ||
3842d135 AK |
4400 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
4401 | ||
3cfc3092 JK |
4402 | return 0; |
4403 | } | |
4404 | ||
a1efbe77 JK |
4405 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
4406 | struct kvm_debugregs *dbgregs) | |
4407 | { | |
73aaf249 JK |
4408 | unsigned long val; |
4409 | ||
a1efbe77 | 4410 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 4411 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 4412 | dbgregs->dr6 = val; |
a1efbe77 JK |
4413 | dbgregs->dr7 = vcpu->arch.dr7; |
4414 | dbgregs->flags = 0; | |
97e69aa6 | 4415 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
4416 | } |
4417 | ||
4418 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
4419 | struct kvm_debugregs *dbgregs) | |
4420 | { | |
4421 | if (dbgregs->flags) | |
4422 | return -EINVAL; | |
4423 | ||
d14bdb55 PB |
4424 | if (dbgregs->dr6 & ~0xffffffffull) |
4425 | return -EINVAL; | |
4426 | if (dbgregs->dr7 & ~0xffffffffull) | |
4427 | return -EINVAL; | |
4428 | ||
a1efbe77 | 4429 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 4430 | kvm_update_dr0123(vcpu); |
a1efbe77 JK |
4431 | vcpu->arch.dr6 = dbgregs->dr6; |
4432 | vcpu->arch.dr7 = dbgregs->dr7; | |
9926c9fd | 4433 | kvm_update_dr7(vcpu); |
a1efbe77 | 4434 | |
a1efbe77 JK |
4435 | return 0; |
4436 | } | |
4437 | ||
df1daba7 PB |
4438 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
4439 | ||
4440 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
4441 | { | |
b666a4b6 | 4442 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
400e4b20 | 4443 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
4444 | u64 valid; |
4445 | ||
4446 | /* | |
4447 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4448 | * leaves 0 and 1 in the loop below. | |
4449 | */ | |
4450 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
4451 | ||
4452 | /* Set XSTATE_BV */ | |
00c87e9a | 4453 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
4454 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
4455 | ||
4456 | /* | |
4457 | * Copy each region from the possibly compacted offset to the | |
4458 | * non-compacted offset. | |
4459 | */ | |
d91cab78 | 4460 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4461 | while (valid) { |
abd16d68 SAS |
4462 | u64 xfeature_mask = valid & -valid; |
4463 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
4464 | void *src = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
4465 | |
4466 | if (src) { | |
4467 | u32 size, offset, ecx, edx; | |
abd16d68 | 4468 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 4469 | &size, &offset, &ecx, &edx); |
abd16d68 | 4470 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
4471 | memcpy(dest + offset, &vcpu->arch.pkru, |
4472 | sizeof(vcpu->arch.pkru)); | |
4473 | else | |
4474 | memcpy(dest + offset, src, size); | |
4475 | ||
df1daba7 PB |
4476 | } |
4477 | ||
abd16d68 | 4478 | valid -= xfeature_mask; |
df1daba7 PB |
4479 | } |
4480 | } | |
4481 | ||
4482 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
4483 | { | |
b666a4b6 | 4484 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
df1daba7 PB |
4485 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
4486 | u64 valid; | |
4487 | ||
4488 | /* | |
4489 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4490 | * leaves 0 and 1 in the loop below. | |
4491 | */ | |
4492 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
4493 | ||
4494 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 4495 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 4496 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 4497 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
4498 | |
4499 | /* | |
4500 | * Copy each region from the non-compacted offset to the | |
4501 | * possibly compacted offset. | |
4502 | */ | |
d91cab78 | 4503 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4504 | while (valid) { |
abd16d68 SAS |
4505 | u64 xfeature_mask = valid & -valid; |
4506 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
4507 | void *dest = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
4508 | |
4509 | if (dest) { | |
4510 | u32 size, offset, ecx, edx; | |
abd16d68 | 4511 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 4512 | &size, &offset, &ecx, &edx); |
abd16d68 | 4513 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
4514 | memcpy(&vcpu->arch.pkru, src + offset, |
4515 | sizeof(vcpu->arch.pkru)); | |
4516 | else | |
4517 | memcpy(dest, src + offset, size); | |
ee4100da | 4518 | } |
df1daba7 | 4519 | |
abd16d68 | 4520 | valid -= xfeature_mask; |
df1daba7 PB |
4521 | } |
4522 | } | |
4523 | ||
2d5b5a66 SY |
4524 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
4525 | struct kvm_xsave *guest_xsave) | |
4526 | { | |
ed02b213 TL |
4527 | if (!vcpu->arch.guest_fpu) |
4528 | return; | |
4529 | ||
d366bf7e | 4530 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
4531 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
4532 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 4533 | } else { |
2d5b5a66 | 4534 | memcpy(guest_xsave->region, |
b666a4b6 | 4535 | &vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4536 | sizeof(struct fxregs_state)); |
2d5b5a66 | 4537 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 4538 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
4539 | } |
4540 | } | |
4541 | ||
a575813b WL |
4542 | #define XSAVE_MXCSR_OFFSET 24 |
4543 | ||
2d5b5a66 SY |
4544 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
4545 | struct kvm_xsave *guest_xsave) | |
4546 | { | |
ed02b213 TL |
4547 | u64 xstate_bv; |
4548 | u32 mxcsr; | |
4549 | ||
4550 | if (!vcpu->arch.guest_fpu) | |
4551 | return 0; | |
4552 | ||
4553 | xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
4554 | mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; | |
2d5b5a66 | 4555 | |
d366bf7e | 4556 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
4557 | /* |
4558 | * Here we allow setting states that are not present in | |
4559 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
4560 | * with old userspace. | |
4561 | */ | |
cfc48181 | 4562 | if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) |
d7876f1b | 4563 | return -EINVAL; |
df1daba7 | 4564 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 4565 | } else { |
a575813b WL |
4566 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
4567 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 4568 | return -EINVAL; |
b666a4b6 | 4569 | memcpy(&vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4570 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
4571 | } |
4572 | return 0; | |
4573 | } | |
4574 | ||
4575 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
4576 | struct kvm_xcrs *guest_xcrs) | |
4577 | { | |
d366bf7e | 4578 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
4579 | guest_xcrs->nr_xcrs = 0; |
4580 | return; | |
4581 | } | |
4582 | ||
4583 | guest_xcrs->nr_xcrs = 1; | |
4584 | guest_xcrs->flags = 0; | |
4585 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
4586 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
4587 | } | |
4588 | ||
4589 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
4590 | struct kvm_xcrs *guest_xcrs) | |
4591 | { | |
4592 | int i, r = 0; | |
4593 | ||
d366bf7e | 4594 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
4595 | return -EINVAL; |
4596 | ||
4597 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
4598 | return -EINVAL; | |
4599 | ||
4600 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
4601 | /* Only support XCR0 currently */ | |
c67a04cb | 4602 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 4603 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 4604 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
4605 | break; |
4606 | } | |
4607 | if (r) | |
4608 | r = -EINVAL; | |
4609 | return r; | |
4610 | } | |
4611 | ||
1c0b28c2 EM |
4612 | /* |
4613 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
4614 | * stopped by the hypervisor. This function will be called from the host only. | |
4615 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
4616 | * does not support pv clocks. | |
4617 | */ | |
4618 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
4619 | { | |
0b79459b | 4620 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 4621 | return -EINVAL; |
51d59c6b | 4622 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
4623 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
4624 | return 0; | |
4625 | } | |
4626 | ||
5c919412 AS |
4627 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
4628 | struct kvm_enable_cap *cap) | |
4629 | { | |
57b119da VK |
4630 | int r; |
4631 | uint16_t vmcs_version; | |
4632 | void __user *user_ptr; | |
4633 | ||
5c919412 AS |
4634 | if (cap->flags) |
4635 | return -EINVAL; | |
4636 | ||
4637 | switch (cap->cap) { | |
efc479e6 RK |
4638 | case KVM_CAP_HYPERV_SYNIC2: |
4639 | if (cap->args[0]) | |
4640 | return -EINVAL; | |
df561f66 | 4641 | fallthrough; |
b2869f28 | 4642 | |
5c919412 | 4643 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
4644 | if (!irqchip_in_kernel(vcpu->kvm)) |
4645 | return -EINVAL; | |
efc479e6 RK |
4646 | return kvm_hv_activate_synic(vcpu, cap->cap == |
4647 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 4648 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
33b22172 | 4649 | if (!kvm_x86_ops.nested_ops->enable_evmcs) |
5158917c | 4650 | return -ENOTTY; |
33b22172 | 4651 | r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); |
57b119da VK |
4652 | if (!r) { |
4653 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
4654 | if (copy_to_user(user_ptr, &vmcs_version, | |
4655 | sizeof(vmcs_version))) | |
4656 | r = -EFAULT; | |
4657 | } | |
4658 | return r; | |
344c6c80 | 4659 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4660 | if (!kvm_x86_ops.enable_direct_tlbflush) |
344c6c80 TL |
4661 | return -ENOTTY; |
4662 | ||
afaf0b2f | 4663 | return kvm_x86_ops.enable_direct_tlbflush(vcpu); |
57b119da | 4664 | |
66570e96 OU |
4665 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
4666 | vcpu->arch.pv_cpuid.enforce = cap->args[0]; | |
01b4f510 OU |
4667 | if (vcpu->arch.pv_cpuid.enforce) |
4668 | kvm_update_pv_runtime(vcpu); | |
66570e96 OU |
4669 | |
4670 | return 0; | |
4671 | ||
5c919412 AS |
4672 | default: |
4673 | return -EINVAL; | |
4674 | } | |
4675 | } | |
4676 | ||
313a3dc7 CO |
4677 | long kvm_arch_vcpu_ioctl(struct file *filp, |
4678 | unsigned int ioctl, unsigned long arg) | |
4679 | { | |
4680 | struct kvm_vcpu *vcpu = filp->private_data; | |
4681 | void __user *argp = (void __user *)arg; | |
4682 | int r; | |
d1ac91d8 AK |
4683 | union { |
4684 | struct kvm_lapic_state *lapic; | |
4685 | struct kvm_xsave *xsave; | |
4686 | struct kvm_xcrs *xcrs; | |
4687 | void *buffer; | |
4688 | } u; | |
4689 | ||
9b062471 CD |
4690 | vcpu_load(vcpu); |
4691 | ||
d1ac91d8 | 4692 | u.buffer = NULL; |
313a3dc7 CO |
4693 | switch (ioctl) { |
4694 | case KVM_GET_LAPIC: { | |
2204ae3c | 4695 | r = -EINVAL; |
bce87cce | 4696 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4697 | goto out; |
254272ce BG |
4698 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
4699 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 4700 | |
b772ff36 | 4701 | r = -ENOMEM; |
d1ac91d8 | 4702 | if (!u.lapic) |
b772ff36 | 4703 | goto out; |
d1ac91d8 | 4704 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4705 | if (r) |
4706 | goto out; | |
4707 | r = -EFAULT; | |
d1ac91d8 | 4708 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
4709 | goto out; |
4710 | r = 0; | |
4711 | break; | |
4712 | } | |
4713 | case KVM_SET_LAPIC: { | |
2204ae3c | 4714 | r = -EINVAL; |
bce87cce | 4715 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4716 | goto out; |
ff5c2c03 | 4717 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
4718 | if (IS_ERR(u.lapic)) { |
4719 | r = PTR_ERR(u.lapic); | |
4720 | goto out_nofree; | |
4721 | } | |
ff5c2c03 | 4722 | |
d1ac91d8 | 4723 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4724 | break; |
4725 | } | |
f77bc6a4 ZX |
4726 | case KVM_INTERRUPT: { |
4727 | struct kvm_interrupt irq; | |
4728 | ||
4729 | r = -EFAULT; | |
0e96f31e | 4730 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
4731 | goto out; |
4732 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
4733 | break; |
4734 | } | |
c4abb7c9 JK |
4735 | case KVM_NMI: { |
4736 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
4737 | break; |
4738 | } | |
f077825a PB |
4739 | case KVM_SMI: { |
4740 | r = kvm_vcpu_ioctl_smi(vcpu); | |
4741 | break; | |
4742 | } | |
313a3dc7 CO |
4743 | case KVM_SET_CPUID: { |
4744 | struct kvm_cpuid __user *cpuid_arg = argp; | |
4745 | struct kvm_cpuid cpuid; | |
4746 | ||
4747 | r = -EFAULT; | |
0e96f31e | 4748 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
4749 | goto out; |
4750 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
4751 | break; |
4752 | } | |
07716717 DK |
4753 | case KVM_SET_CPUID2: { |
4754 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4755 | struct kvm_cpuid2 cpuid; | |
4756 | ||
4757 | r = -EFAULT; | |
0e96f31e | 4758 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4759 | goto out; |
4760 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 4761 | cpuid_arg->entries); |
07716717 DK |
4762 | break; |
4763 | } | |
4764 | case KVM_GET_CPUID2: { | |
4765 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4766 | struct kvm_cpuid2 cpuid; | |
4767 | ||
4768 | r = -EFAULT; | |
0e96f31e | 4769 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4770 | goto out; |
4771 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 4772 | cpuid_arg->entries); |
07716717 DK |
4773 | if (r) |
4774 | goto out; | |
4775 | r = -EFAULT; | |
0e96f31e | 4776 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
4777 | goto out; |
4778 | r = 0; | |
4779 | break; | |
4780 | } | |
801e459a TL |
4781 | case KVM_GET_MSRS: { |
4782 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 4783 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 4784 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4785 | break; |
801e459a TL |
4786 | } |
4787 | case KVM_SET_MSRS: { | |
4788 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 4789 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 4790 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4791 | break; |
801e459a | 4792 | } |
b209749f AK |
4793 | case KVM_TPR_ACCESS_REPORTING: { |
4794 | struct kvm_tpr_access_ctl tac; | |
4795 | ||
4796 | r = -EFAULT; | |
0e96f31e | 4797 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
4798 | goto out; |
4799 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
4800 | if (r) | |
4801 | goto out; | |
4802 | r = -EFAULT; | |
0e96f31e | 4803 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
4804 | goto out; |
4805 | r = 0; | |
4806 | break; | |
4807 | }; | |
b93463aa AK |
4808 | case KVM_SET_VAPIC_ADDR: { |
4809 | struct kvm_vapic_addr va; | |
7301d6ab | 4810 | int idx; |
b93463aa AK |
4811 | |
4812 | r = -EINVAL; | |
35754c98 | 4813 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
4814 | goto out; |
4815 | r = -EFAULT; | |
0e96f31e | 4816 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 4817 | goto out; |
7301d6ab | 4818 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 4819 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 4820 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
4821 | break; |
4822 | } | |
890ca9ae HY |
4823 | case KVM_X86_SETUP_MCE: { |
4824 | u64 mcg_cap; | |
4825 | ||
4826 | r = -EFAULT; | |
0e96f31e | 4827 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
4828 | goto out; |
4829 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
4830 | break; | |
4831 | } | |
4832 | case KVM_X86_SET_MCE: { | |
4833 | struct kvm_x86_mce mce; | |
4834 | ||
4835 | r = -EFAULT; | |
0e96f31e | 4836 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
4837 | goto out; |
4838 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
4839 | break; | |
4840 | } | |
3cfc3092 JK |
4841 | case KVM_GET_VCPU_EVENTS: { |
4842 | struct kvm_vcpu_events events; | |
4843 | ||
4844 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
4845 | ||
4846 | r = -EFAULT; | |
4847 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
4848 | break; | |
4849 | r = 0; | |
4850 | break; | |
4851 | } | |
4852 | case KVM_SET_VCPU_EVENTS: { | |
4853 | struct kvm_vcpu_events events; | |
4854 | ||
4855 | r = -EFAULT; | |
4856 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
4857 | break; | |
4858 | ||
4859 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
4860 | break; | |
4861 | } | |
a1efbe77 JK |
4862 | case KVM_GET_DEBUGREGS: { |
4863 | struct kvm_debugregs dbgregs; | |
4864 | ||
4865 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
4866 | ||
4867 | r = -EFAULT; | |
4868 | if (copy_to_user(argp, &dbgregs, | |
4869 | sizeof(struct kvm_debugregs))) | |
4870 | break; | |
4871 | r = 0; | |
4872 | break; | |
4873 | } | |
4874 | case KVM_SET_DEBUGREGS: { | |
4875 | struct kvm_debugregs dbgregs; | |
4876 | ||
4877 | r = -EFAULT; | |
4878 | if (copy_from_user(&dbgregs, argp, | |
4879 | sizeof(struct kvm_debugregs))) | |
4880 | break; | |
4881 | ||
4882 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
4883 | break; | |
4884 | } | |
2d5b5a66 | 4885 | case KVM_GET_XSAVE: { |
254272ce | 4886 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4887 | r = -ENOMEM; |
d1ac91d8 | 4888 | if (!u.xsave) |
2d5b5a66 SY |
4889 | break; |
4890 | ||
d1ac91d8 | 4891 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4892 | |
4893 | r = -EFAULT; | |
d1ac91d8 | 4894 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
4895 | break; |
4896 | r = 0; | |
4897 | break; | |
4898 | } | |
4899 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 4900 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
4901 | if (IS_ERR(u.xsave)) { |
4902 | r = PTR_ERR(u.xsave); | |
4903 | goto out_nofree; | |
4904 | } | |
2d5b5a66 | 4905 | |
d1ac91d8 | 4906 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4907 | break; |
4908 | } | |
4909 | case KVM_GET_XCRS: { | |
254272ce | 4910 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4911 | r = -ENOMEM; |
d1ac91d8 | 4912 | if (!u.xcrs) |
2d5b5a66 SY |
4913 | break; |
4914 | ||
d1ac91d8 | 4915 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4916 | |
4917 | r = -EFAULT; | |
d1ac91d8 | 4918 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
4919 | sizeof(struct kvm_xcrs))) |
4920 | break; | |
4921 | r = 0; | |
4922 | break; | |
4923 | } | |
4924 | case KVM_SET_XCRS: { | |
ff5c2c03 | 4925 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
4926 | if (IS_ERR(u.xcrs)) { |
4927 | r = PTR_ERR(u.xcrs); | |
4928 | goto out_nofree; | |
4929 | } | |
2d5b5a66 | 4930 | |
d1ac91d8 | 4931 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4932 | break; |
4933 | } | |
92a1f12d JR |
4934 | case KVM_SET_TSC_KHZ: { |
4935 | u32 user_tsc_khz; | |
4936 | ||
4937 | r = -EINVAL; | |
92a1f12d JR |
4938 | user_tsc_khz = (u32)arg; |
4939 | ||
26769f96 MT |
4940 | if (kvm_has_tsc_control && |
4941 | user_tsc_khz >= kvm_max_guest_tsc_khz) | |
92a1f12d JR |
4942 | goto out; |
4943 | ||
cc578287 ZA |
4944 | if (user_tsc_khz == 0) |
4945 | user_tsc_khz = tsc_khz; | |
4946 | ||
381d585c HZ |
4947 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
4948 | r = 0; | |
92a1f12d | 4949 | |
92a1f12d JR |
4950 | goto out; |
4951 | } | |
4952 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 4953 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
4954 | goto out; |
4955 | } | |
1c0b28c2 EM |
4956 | case KVM_KVMCLOCK_CTRL: { |
4957 | r = kvm_set_guest_paused(vcpu); | |
4958 | goto out; | |
4959 | } | |
5c919412 AS |
4960 | case KVM_ENABLE_CAP: { |
4961 | struct kvm_enable_cap cap; | |
4962 | ||
4963 | r = -EFAULT; | |
4964 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
4965 | goto out; | |
4966 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
4967 | break; | |
4968 | } | |
8fcc4b59 JM |
4969 | case KVM_GET_NESTED_STATE: { |
4970 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
4971 | u32 user_data_size; | |
4972 | ||
4973 | r = -EINVAL; | |
33b22172 | 4974 | if (!kvm_x86_ops.nested_ops->get_state) |
8fcc4b59 JM |
4975 | break; |
4976 | ||
4977 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 4978 | r = -EFAULT; |
8fcc4b59 | 4979 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 4980 | break; |
8fcc4b59 | 4981 | |
33b22172 PB |
4982 | r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, |
4983 | user_data_size); | |
8fcc4b59 | 4984 | if (r < 0) |
26b471c7 | 4985 | break; |
8fcc4b59 JM |
4986 | |
4987 | if (r > user_data_size) { | |
4988 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
4989 | r = -EFAULT; |
4990 | else | |
4991 | r = -E2BIG; | |
4992 | break; | |
8fcc4b59 | 4993 | } |
26b471c7 | 4994 | |
8fcc4b59 JM |
4995 | r = 0; |
4996 | break; | |
4997 | } | |
4998 | case KVM_SET_NESTED_STATE: { | |
4999 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5000 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 5001 | int idx; |
8fcc4b59 JM |
5002 | |
5003 | r = -EINVAL; | |
33b22172 | 5004 | if (!kvm_x86_ops.nested_ops->set_state) |
8fcc4b59 JM |
5005 | break; |
5006 | ||
26b471c7 | 5007 | r = -EFAULT; |
8fcc4b59 | 5008 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 5009 | break; |
8fcc4b59 | 5010 | |
26b471c7 | 5011 | r = -EINVAL; |
8fcc4b59 | 5012 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 5013 | break; |
8fcc4b59 JM |
5014 | |
5015 | if (kvm_state.flags & | |
8cab6507 | 5016 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
cc440cda PB |
5017 | | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING |
5018 | | KVM_STATE_NESTED_GIF_SET)) | |
26b471c7 | 5019 | break; |
8fcc4b59 JM |
5020 | |
5021 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
5022 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
5023 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 5024 | break; |
8fcc4b59 | 5025 | |
ad5996d9 | 5026 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
33b22172 | 5027 | r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 5028 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
5029 | break; |
5030 | } | |
c21d54f0 VK |
5031 | case KVM_GET_SUPPORTED_HV_CPUID: |
5032 | r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); | |
2bc39970 | 5033 | break; |
313a3dc7 CO |
5034 | default: |
5035 | r = -EINVAL; | |
5036 | } | |
5037 | out: | |
d1ac91d8 | 5038 | kfree(u.buffer); |
9b062471 CD |
5039 | out_nofree: |
5040 | vcpu_put(vcpu); | |
313a3dc7 CO |
5041 | return r; |
5042 | } | |
5043 | ||
1499fa80 | 5044 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
5045 | { |
5046 | return VM_FAULT_SIGBUS; | |
5047 | } | |
5048 | ||
1fe779f8 CO |
5049 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
5050 | { | |
5051 | int ret; | |
5052 | ||
5053 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 5054 | return -EINVAL; |
afaf0b2f | 5055 | ret = kvm_x86_ops.set_tss_addr(kvm, addr); |
1fe779f8 CO |
5056 | return ret; |
5057 | } | |
5058 | ||
b927a3ce SY |
5059 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
5060 | u64 ident_addr) | |
5061 | { | |
afaf0b2f | 5062 | return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr); |
b927a3ce SY |
5063 | } |
5064 | ||
1fe779f8 | 5065 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 5066 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
5067 | { |
5068 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
5069 | return -EINVAL; | |
5070 | ||
79fac95e | 5071 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
5072 | |
5073 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 5074 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 5075 | |
79fac95e | 5076 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
5077 | return 0; |
5078 | } | |
5079 | ||
bc8a3d89 | 5080 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 5081 | { |
39de71ec | 5082 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
5083 | } |
5084 | ||
1fe779f8 CO |
5085 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
5086 | { | |
90bca052 | 5087 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5088 | int r; |
5089 | ||
5090 | r = 0; | |
5091 | switch (chip->chip_id) { | |
5092 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 5093 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
5094 | sizeof(struct kvm_pic_state)); |
5095 | break; | |
5096 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 5097 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
5098 | sizeof(struct kvm_pic_state)); |
5099 | break; | |
5100 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5101 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5102 | break; |
5103 | default: | |
5104 | r = -EINVAL; | |
5105 | break; | |
5106 | } | |
5107 | return r; | |
5108 | } | |
5109 | ||
5110 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
5111 | { | |
90bca052 | 5112 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5113 | int r; |
5114 | ||
5115 | r = 0; | |
5116 | switch (chip->chip_id) { | |
5117 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
5118 | spin_lock(&pic->lock); |
5119 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 5120 | sizeof(struct kvm_pic_state)); |
90bca052 | 5121 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5122 | break; |
5123 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
5124 | spin_lock(&pic->lock); |
5125 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 5126 | sizeof(struct kvm_pic_state)); |
90bca052 | 5127 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5128 | break; |
5129 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5130 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5131 | break; |
5132 | default: | |
5133 | r = -EINVAL; | |
5134 | break; | |
5135 | } | |
90bca052 | 5136 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
5137 | return r; |
5138 | } | |
5139 | ||
e0f63cb9 SY |
5140 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
5141 | { | |
34f3941c RK |
5142 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
5143 | ||
5144 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
5145 | ||
5146 | mutex_lock(&kps->lock); | |
5147 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
5148 | mutex_unlock(&kps->lock); | |
2da29bcc | 5149 | return 0; |
e0f63cb9 SY |
5150 | } |
5151 | ||
5152 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
5153 | { | |
0185604c | 5154 | int i; |
09edea72 RK |
5155 | struct kvm_pit *pit = kvm->arch.vpit; |
5156 | ||
5157 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 5158 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 5159 | for (i = 0; i < 3; i++) |
09edea72 RK |
5160 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
5161 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 5162 | return 0; |
e9f42757 BK |
5163 | } |
5164 | ||
5165 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5166 | { | |
e9f42757 BK |
5167 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
5168 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
5169 | sizeof(ps->channels)); | |
5170 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
5171 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 5172 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 5173 | return 0; |
e9f42757 BK |
5174 | } |
5175 | ||
5176 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5177 | { | |
2da29bcc | 5178 | int start = 0; |
0185604c | 5179 | int i; |
e9f42757 | 5180 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
5181 | struct kvm_pit *pit = kvm->arch.vpit; |
5182 | ||
5183 | mutex_lock(&pit->pit_state.lock); | |
5184 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
5185 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
5186 | if (!prev_legacy && cur_legacy) | |
5187 | start = 1; | |
09edea72 RK |
5188 | memcpy(&pit->pit_state.channels, &ps->channels, |
5189 | sizeof(pit->pit_state.channels)); | |
5190 | pit->pit_state.flags = ps->flags; | |
0185604c | 5191 | for (i = 0; i < 3; i++) |
09edea72 | 5192 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 5193 | start && i == 0); |
09edea72 | 5194 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 5195 | return 0; |
e0f63cb9 SY |
5196 | } |
5197 | ||
52d939a0 MT |
5198 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
5199 | struct kvm_reinject_control *control) | |
5200 | { | |
71474e2f RK |
5201 | struct kvm_pit *pit = kvm->arch.vpit; |
5202 | ||
71474e2f RK |
5203 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
5204 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
5205 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
5206 | */ | |
5207 | mutex_lock(&pit->pit_state.lock); | |
5208 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
5209 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 5210 | |
52d939a0 MT |
5211 | return 0; |
5212 | } | |
5213 | ||
0dff0846 | 5214 | void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) |
5bb064dc | 5215 | { |
88178fd4 KH |
5216 | /* |
5217 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
5218 | */ | |
afaf0b2f SC |
5219 | if (kvm_x86_ops.flush_log_dirty) |
5220 | kvm_x86_ops.flush_log_dirty(kvm); | |
5bb064dc ZX |
5221 | } |
5222 | ||
aa2fbe6d YZ |
5223 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
5224 | bool line_status) | |
23d43cf9 CD |
5225 | { |
5226 | if (!irqchip_in_kernel(kvm)) | |
5227 | return -ENXIO; | |
5228 | ||
5229 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
5230 | irq_event->irq, irq_event->level, |
5231 | line_status); | |
23d43cf9 CD |
5232 | return 0; |
5233 | } | |
5234 | ||
e5d83c74 PB |
5235 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
5236 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
5237 | { |
5238 | int r; | |
5239 | ||
5240 | if (cap->flags) | |
5241 | return -EINVAL; | |
5242 | ||
5243 | switch (cap->cap) { | |
5244 | case KVM_CAP_DISABLE_QUIRKS: | |
5245 | kvm->arch.disabled_quirks = cap->args[0]; | |
5246 | r = 0; | |
5247 | break; | |
49df6397 SR |
5248 | case KVM_CAP_SPLIT_IRQCHIP: { |
5249 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
5250 | r = -EINVAL; |
5251 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
5252 | goto split_irqchip_unlock; | |
49df6397 SR |
5253 | r = -EEXIST; |
5254 | if (irqchip_in_kernel(kvm)) | |
5255 | goto split_irqchip_unlock; | |
557abc40 | 5256 | if (kvm->created_vcpus) |
49df6397 SR |
5257 | goto split_irqchip_unlock; |
5258 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 5259 | if (r) |
49df6397 SR |
5260 | goto split_irqchip_unlock; |
5261 | /* Pairs with irqchip_in_kernel. */ | |
5262 | smp_wmb(); | |
49776faf | 5263 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 5264 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
5265 | r = 0; |
5266 | split_irqchip_unlock: | |
5267 | mutex_unlock(&kvm->lock); | |
5268 | break; | |
5269 | } | |
37131313 RK |
5270 | case KVM_CAP_X2APIC_API: |
5271 | r = -EINVAL; | |
5272 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
5273 | break; | |
5274 | ||
5275 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
5276 | kvm->arch.x2apic_format = true; | |
c519265f RK |
5277 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
5278 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
5279 | |
5280 | r = 0; | |
5281 | break; | |
4d5422ce WL |
5282 | case KVM_CAP_X86_DISABLE_EXITS: |
5283 | r = -EINVAL; | |
5284 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
5285 | break; | |
5286 | ||
5287 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
5288 | kvm_can_mwait_in_guest()) | |
5289 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 5290 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 5291 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
5292 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
5293 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
5294 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
5295 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
5296 | r = 0; |
5297 | break; | |
6fbbde9a DS |
5298 | case KVM_CAP_MSR_PLATFORM_INFO: |
5299 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
5300 | r = 0; | |
c4f55198 JM |
5301 | break; |
5302 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
5303 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
5304 | r = 0; | |
6fbbde9a | 5305 | break; |
1ae09954 AG |
5306 | case KVM_CAP_X86_USER_SPACE_MSR: |
5307 | kvm->arch.user_space_msr_mask = cap->args[0]; | |
5308 | r = 0; | |
5309 | break; | |
90de4a18 NA |
5310 | default: |
5311 | r = -EINVAL; | |
5312 | break; | |
5313 | } | |
5314 | return r; | |
5315 | } | |
5316 | ||
1a155254 AG |
5317 | static void kvm_clear_msr_filter(struct kvm *kvm) |
5318 | { | |
5319 | u32 i; | |
5320 | u32 count = kvm->arch.msr_filter.count; | |
5321 | struct msr_bitmap_range ranges[16]; | |
5322 | ||
5323 | mutex_lock(&kvm->lock); | |
5324 | kvm->arch.msr_filter.count = 0; | |
5325 | memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0])); | |
5326 | mutex_unlock(&kvm->lock); | |
5327 | synchronize_srcu(&kvm->srcu); | |
5328 | ||
5329 | for (i = 0; i < count; i++) | |
5330 | kfree(ranges[i].bitmap); | |
5331 | } | |
5332 | ||
5333 | static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range) | |
5334 | { | |
5335 | struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges; | |
5336 | struct msr_bitmap_range range; | |
5337 | unsigned long *bitmap = NULL; | |
5338 | size_t bitmap_size; | |
5339 | int r; | |
5340 | ||
5341 | if (!user_range->nmsrs) | |
5342 | return 0; | |
5343 | ||
5344 | bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); | |
5345 | if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) | |
5346 | return -EINVAL; | |
5347 | ||
5348 | bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); | |
5349 | if (IS_ERR(bitmap)) | |
5350 | return PTR_ERR(bitmap); | |
5351 | ||
5352 | range = (struct msr_bitmap_range) { | |
5353 | .flags = user_range->flags, | |
5354 | .base = user_range->base, | |
5355 | .nmsrs = user_range->nmsrs, | |
5356 | .bitmap = bitmap, | |
5357 | }; | |
5358 | ||
5359 | if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) { | |
5360 | r = -EINVAL; | |
5361 | goto err; | |
5362 | } | |
5363 | ||
5364 | if (!range.flags) { | |
5365 | r = -EINVAL; | |
5366 | goto err; | |
5367 | } | |
5368 | ||
5369 | /* Everything ok, add this range identifier to our global pool */ | |
5370 | ranges[kvm->arch.msr_filter.count] = range; | |
5371 | /* Make sure we filled the array before we tell anyone to walk it */ | |
5372 | smp_wmb(); | |
5373 | kvm->arch.msr_filter.count++; | |
5374 | ||
5375 | return 0; | |
5376 | err: | |
5377 | kfree(bitmap); | |
5378 | return r; | |
5379 | } | |
5380 | ||
5381 | static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) | |
5382 | { | |
5383 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
5384 | struct kvm_msr_filter filter; | |
5385 | bool default_allow; | |
5386 | int r = 0; | |
043248b3 | 5387 | bool empty = true; |
1a155254 AG |
5388 | u32 i; |
5389 | ||
5390 | if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) | |
5391 | return -EFAULT; | |
5392 | ||
043248b3 PB |
5393 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) |
5394 | empty &= !filter.ranges[i].nmsrs; | |
1a155254 AG |
5395 | |
5396 | default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); | |
043248b3 PB |
5397 | if (empty && !default_allow) |
5398 | return -EINVAL; | |
5399 | ||
5400 | kvm_clear_msr_filter(kvm); | |
5401 | ||
1a155254 AG |
5402 | kvm->arch.msr_filter.default_allow = default_allow; |
5403 | ||
5404 | /* | |
5405 | * Protect from concurrent calls to this function that could trigger | |
5406 | * a TOCTOU violation on kvm->arch.msr_filter.count. | |
5407 | */ | |
5408 | mutex_lock(&kvm->lock); | |
5409 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { | |
5410 | r = kvm_add_msr_filter(kvm, &filter.ranges[i]); | |
5411 | if (r) | |
5412 | break; | |
5413 | } | |
5414 | ||
5415 | kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); | |
5416 | mutex_unlock(&kvm->lock); | |
5417 | ||
5418 | return r; | |
5419 | } | |
5420 | ||
1fe779f8 CO |
5421 | long kvm_arch_vm_ioctl(struct file *filp, |
5422 | unsigned int ioctl, unsigned long arg) | |
5423 | { | |
5424 | struct kvm *kvm = filp->private_data; | |
5425 | void __user *argp = (void __user *)arg; | |
367e1319 | 5426 | int r = -ENOTTY; |
f0d66275 DH |
5427 | /* |
5428 | * This union makes it completely explicit to gcc-3.x | |
5429 | * that these two variables' stack usage should be | |
5430 | * combined, not added together. | |
5431 | */ | |
5432 | union { | |
5433 | struct kvm_pit_state ps; | |
e9f42757 | 5434 | struct kvm_pit_state2 ps2; |
c5ff41ce | 5435 | struct kvm_pit_config pit_config; |
f0d66275 | 5436 | } u; |
1fe779f8 CO |
5437 | |
5438 | switch (ioctl) { | |
5439 | case KVM_SET_TSS_ADDR: | |
5440 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 5441 | break; |
b927a3ce SY |
5442 | case KVM_SET_IDENTITY_MAP_ADDR: { |
5443 | u64 ident_addr; | |
5444 | ||
1af1ac91 DH |
5445 | mutex_lock(&kvm->lock); |
5446 | r = -EINVAL; | |
5447 | if (kvm->created_vcpus) | |
5448 | goto set_identity_unlock; | |
b927a3ce | 5449 | r = -EFAULT; |
0e96f31e | 5450 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 5451 | goto set_identity_unlock; |
b927a3ce | 5452 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
5453 | set_identity_unlock: |
5454 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
5455 | break; |
5456 | } | |
1fe779f8 CO |
5457 | case KVM_SET_NR_MMU_PAGES: |
5458 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
5459 | break; |
5460 | case KVM_GET_NR_MMU_PAGES: | |
5461 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
5462 | break; | |
3ddea128 | 5463 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 5464 | mutex_lock(&kvm->lock); |
09941366 | 5465 | |
3ddea128 | 5466 | r = -EEXIST; |
35e6eaa3 | 5467 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 5468 | goto create_irqchip_unlock; |
09941366 | 5469 | |
3e515705 | 5470 | r = -EINVAL; |
557abc40 | 5471 | if (kvm->created_vcpus) |
3e515705 | 5472 | goto create_irqchip_unlock; |
09941366 RK |
5473 | |
5474 | r = kvm_pic_init(kvm); | |
5475 | if (r) | |
3ddea128 | 5476 | goto create_irqchip_unlock; |
09941366 RK |
5477 | |
5478 | r = kvm_ioapic_init(kvm); | |
5479 | if (r) { | |
09941366 | 5480 | kvm_pic_destroy(kvm); |
3ddea128 | 5481 | goto create_irqchip_unlock; |
09941366 RK |
5482 | } |
5483 | ||
399ec807 AK |
5484 | r = kvm_setup_default_irq_routing(kvm); |
5485 | if (r) { | |
72bb2fcd | 5486 | kvm_ioapic_destroy(kvm); |
09941366 | 5487 | kvm_pic_destroy(kvm); |
71ba994c | 5488 | goto create_irqchip_unlock; |
399ec807 | 5489 | } |
49776faf | 5490 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 5491 | smp_wmb(); |
49776faf | 5492 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
5493 | create_irqchip_unlock: |
5494 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 5495 | break; |
3ddea128 | 5496 | } |
7837699f | 5497 | case KVM_CREATE_PIT: |
c5ff41ce JK |
5498 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
5499 | goto create_pit; | |
5500 | case KVM_CREATE_PIT2: | |
5501 | r = -EFAULT; | |
5502 | if (copy_from_user(&u.pit_config, argp, | |
5503 | sizeof(struct kvm_pit_config))) | |
5504 | goto out; | |
5505 | create_pit: | |
250715a6 | 5506 | mutex_lock(&kvm->lock); |
269e05e4 AK |
5507 | r = -EEXIST; |
5508 | if (kvm->arch.vpit) | |
5509 | goto create_pit_unlock; | |
7837699f | 5510 | r = -ENOMEM; |
c5ff41ce | 5511 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
5512 | if (kvm->arch.vpit) |
5513 | r = 0; | |
269e05e4 | 5514 | create_pit_unlock: |
250715a6 | 5515 | mutex_unlock(&kvm->lock); |
7837699f | 5516 | break; |
1fe779f8 CO |
5517 | case KVM_GET_IRQCHIP: { |
5518 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5519 | struct kvm_irqchip *chip; |
1fe779f8 | 5520 | |
ff5c2c03 SL |
5521 | chip = memdup_user(argp, sizeof(*chip)); |
5522 | if (IS_ERR(chip)) { | |
5523 | r = PTR_ERR(chip); | |
1fe779f8 | 5524 | goto out; |
ff5c2c03 SL |
5525 | } |
5526 | ||
1fe779f8 | 5527 | r = -ENXIO; |
826da321 | 5528 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5529 | goto get_irqchip_out; |
5530 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 5531 | if (r) |
f0d66275 | 5532 | goto get_irqchip_out; |
1fe779f8 | 5533 | r = -EFAULT; |
0e96f31e | 5534 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 5535 | goto get_irqchip_out; |
1fe779f8 | 5536 | r = 0; |
f0d66275 DH |
5537 | get_irqchip_out: |
5538 | kfree(chip); | |
1fe779f8 CO |
5539 | break; |
5540 | } | |
5541 | case KVM_SET_IRQCHIP: { | |
5542 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5543 | struct kvm_irqchip *chip; |
1fe779f8 | 5544 | |
ff5c2c03 SL |
5545 | chip = memdup_user(argp, sizeof(*chip)); |
5546 | if (IS_ERR(chip)) { | |
5547 | r = PTR_ERR(chip); | |
1fe779f8 | 5548 | goto out; |
ff5c2c03 SL |
5549 | } |
5550 | ||
1fe779f8 | 5551 | r = -ENXIO; |
826da321 | 5552 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5553 | goto set_irqchip_out; |
5554 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
5555 | set_irqchip_out: |
5556 | kfree(chip); | |
1fe779f8 CO |
5557 | break; |
5558 | } | |
e0f63cb9 | 5559 | case KVM_GET_PIT: { |
e0f63cb9 | 5560 | r = -EFAULT; |
f0d66275 | 5561 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5562 | goto out; |
5563 | r = -ENXIO; | |
5564 | if (!kvm->arch.vpit) | |
5565 | goto out; | |
f0d66275 | 5566 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
5567 | if (r) |
5568 | goto out; | |
5569 | r = -EFAULT; | |
f0d66275 | 5570 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5571 | goto out; |
5572 | r = 0; | |
5573 | break; | |
5574 | } | |
5575 | case KVM_SET_PIT: { | |
e0f63cb9 | 5576 | r = -EFAULT; |
0e96f31e | 5577 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 | 5578 | goto out; |
7289fdb5 | 5579 | mutex_lock(&kvm->lock); |
e0f63cb9 SY |
5580 | r = -ENXIO; |
5581 | if (!kvm->arch.vpit) | |
7289fdb5 | 5582 | goto set_pit_out; |
f0d66275 | 5583 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
7289fdb5 SR |
5584 | set_pit_out: |
5585 | mutex_unlock(&kvm->lock); | |
e0f63cb9 SY |
5586 | break; |
5587 | } | |
e9f42757 BK |
5588 | case KVM_GET_PIT2: { |
5589 | r = -ENXIO; | |
5590 | if (!kvm->arch.vpit) | |
5591 | goto out; | |
5592 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
5593 | if (r) | |
5594 | goto out; | |
5595 | r = -EFAULT; | |
5596 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
5597 | goto out; | |
5598 | r = 0; | |
5599 | break; | |
5600 | } | |
5601 | case KVM_SET_PIT2: { | |
5602 | r = -EFAULT; | |
5603 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
5604 | goto out; | |
7289fdb5 | 5605 | mutex_lock(&kvm->lock); |
e9f42757 BK |
5606 | r = -ENXIO; |
5607 | if (!kvm->arch.vpit) | |
7289fdb5 | 5608 | goto set_pit2_out; |
e9f42757 | 5609 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); |
7289fdb5 SR |
5610 | set_pit2_out: |
5611 | mutex_unlock(&kvm->lock); | |
e9f42757 BK |
5612 | break; |
5613 | } | |
52d939a0 MT |
5614 | case KVM_REINJECT_CONTROL: { |
5615 | struct kvm_reinject_control control; | |
5616 | r = -EFAULT; | |
5617 | if (copy_from_user(&control, argp, sizeof(control))) | |
5618 | goto out; | |
cad23e72 ML |
5619 | r = -ENXIO; |
5620 | if (!kvm->arch.vpit) | |
5621 | goto out; | |
52d939a0 | 5622 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
5623 | break; |
5624 | } | |
d71ba788 PB |
5625 | case KVM_SET_BOOT_CPU_ID: |
5626 | r = 0; | |
5627 | mutex_lock(&kvm->lock); | |
557abc40 | 5628 | if (kvm->created_vcpus) |
d71ba788 PB |
5629 | r = -EBUSY; |
5630 | else | |
5631 | kvm->arch.bsp_vcpu_id = arg; | |
5632 | mutex_unlock(&kvm->lock); | |
5633 | break; | |
ffde22ac | 5634 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 5635 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 5636 | r = -EFAULT; |
51776043 | 5637 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac ES |
5638 | goto out; |
5639 | r = -EINVAL; | |
51776043 | 5640 | if (xhc.flags) |
ffde22ac | 5641 | goto out; |
51776043 | 5642 | memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); |
ffde22ac ES |
5643 | r = 0; |
5644 | break; | |
5645 | } | |
afbcf7ab | 5646 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
5647 | struct kvm_clock_data user_ns; |
5648 | u64 now_ns; | |
afbcf7ab GC |
5649 | |
5650 | r = -EFAULT; | |
5651 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
5652 | goto out; | |
5653 | ||
5654 | r = -EINVAL; | |
5655 | if (user_ns.flags) | |
5656 | goto out; | |
5657 | ||
5658 | r = 0; | |
0bc48bea RK |
5659 | /* |
5660 | * TODO: userspace has to take care of races with VCPU_RUN, so | |
5661 | * kvm_gen_update_masterclock() can be cut down to locked | |
5662 | * pvclock_update_vm_gtod_copy(). | |
5663 | */ | |
5664 | kvm_gen_update_masterclock(kvm); | |
e891a32e | 5665 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5666 | kvm->arch.kvmclock_offset += user_ns.clock - now_ns; |
0bc48bea | 5667 | kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); |
afbcf7ab GC |
5668 | break; |
5669 | } | |
5670 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
5671 | struct kvm_clock_data user_ns; |
5672 | u64 now_ns; | |
5673 | ||
e891a32e | 5674 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5675 | user_ns.clock = now_ns; |
e3fd9a93 | 5676 | user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; |
97e69aa6 | 5677 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
5678 | |
5679 | r = -EFAULT; | |
5680 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
5681 | goto out; | |
5682 | r = 0; | |
5683 | break; | |
5684 | } | |
5acc5c06 BS |
5685 | case KVM_MEMORY_ENCRYPT_OP: { |
5686 | r = -ENOTTY; | |
afaf0b2f SC |
5687 | if (kvm_x86_ops.mem_enc_op) |
5688 | r = kvm_x86_ops.mem_enc_op(kvm, argp); | |
5acc5c06 BS |
5689 | break; |
5690 | } | |
69eaedee BS |
5691 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
5692 | struct kvm_enc_region region; | |
5693 | ||
5694 | r = -EFAULT; | |
5695 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5696 | goto out; | |
5697 | ||
5698 | r = -ENOTTY; | |
afaf0b2f SC |
5699 | if (kvm_x86_ops.mem_enc_reg_region) |
5700 | r = kvm_x86_ops.mem_enc_reg_region(kvm, ®ion); | |
69eaedee BS |
5701 | break; |
5702 | } | |
5703 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
5704 | struct kvm_enc_region region; | |
5705 | ||
5706 | r = -EFAULT; | |
5707 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5708 | goto out; | |
5709 | ||
5710 | r = -ENOTTY; | |
afaf0b2f SC |
5711 | if (kvm_x86_ops.mem_enc_unreg_region) |
5712 | r = kvm_x86_ops.mem_enc_unreg_region(kvm, ®ion); | |
69eaedee BS |
5713 | break; |
5714 | } | |
faeb7833 RK |
5715 | case KVM_HYPERV_EVENTFD: { |
5716 | struct kvm_hyperv_eventfd hvevfd; | |
5717 | ||
5718 | r = -EFAULT; | |
5719 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
5720 | goto out; | |
5721 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
5722 | break; | |
5723 | } | |
66bb8a06 EH |
5724 | case KVM_SET_PMU_EVENT_FILTER: |
5725 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
5726 | break; | |
1a155254 AG |
5727 | case KVM_X86_SET_MSR_FILTER: |
5728 | r = kvm_vm_ioctl_set_msr_filter(kvm, argp); | |
5729 | break; | |
1fe779f8 | 5730 | default: |
ad6260da | 5731 | r = -ENOTTY; |
1fe779f8 CO |
5732 | } |
5733 | out: | |
5734 | return r; | |
5735 | } | |
5736 | ||
a16b043c | 5737 | static void kvm_init_msr_list(void) |
043405e1 | 5738 | { |
24c29b7a | 5739 | struct x86_pmu_capability x86_pmu; |
043405e1 | 5740 | u32 dummy[2]; |
7a5ee6ed | 5741 | unsigned i; |
043405e1 | 5742 | |
e2ada66e | 5743 | BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, |
7a5ee6ed | 5744 | "Please update the fixed PMCs in msrs_to_saved_all[]"); |
24c29b7a PB |
5745 | |
5746 | perf_get_x86_pmu_capability(&x86_pmu); | |
e2ada66e | 5747 | |
6cbee2b9 XL |
5748 | num_msrs_to_save = 0; |
5749 | num_emulated_msrs = 0; | |
5750 | num_msr_based_features = 0; | |
5751 | ||
7a5ee6ed CQ |
5752 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { |
5753 | if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) | |
043405e1 | 5754 | continue; |
93c4adc7 PB |
5755 | |
5756 | /* | |
5757 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 5758 | * to the guests in some cases. |
93c4adc7 | 5759 | */ |
7a5ee6ed | 5760 | switch (msrs_to_save_all[i]) { |
93c4adc7 | 5761 | case MSR_IA32_BNDCFGS: |
503234b3 | 5762 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
5763 | continue; |
5764 | break; | |
9dbe6cf9 | 5765 | case MSR_TSC_AUX: |
13908510 | 5766 | if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) |
9dbe6cf9 PB |
5767 | continue; |
5768 | break; | |
f4cfcd2d ML |
5769 | case MSR_IA32_UMWAIT_CONTROL: |
5770 | if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) | |
5771 | continue; | |
5772 | break; | |
bf8c55d8 CP |
5773 | case MSR_IA32_RTIT_CTL: |
5774 | case MSR_IA32_RTIT_STATUS: | |
7b874c26 | 5775 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) |
bf8c55d8 CP |
5776 | continue; |
5777 | break; | |
5778 | case MSR_IA32_RTIT_CR3_MATCH: | |
7b874c26 | 5779 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
5780 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) |
5781 | continue; | |
5782 | break; | |
5783 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
5784 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
7b874c26 | 5785 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
5786 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && |
5787 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
5788 | continue; | |
5789 | break; | |
7cb85fc4 | 5790 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: |
7b874c26 | 5791 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
7a5ee6ed | 5792 | msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= |
bf8c55d8 CP |
5793 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) |
5794 | continue; | |
5795 | break; | |
cf05a67b | 5796 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: |
7a5ee6ed | 5797 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= |
24c29b7a PB |
5798 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
5799 | continue; | |
5800 | break; | |
cf05a67b | 5801 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: |
7a5ee6ed | 5802 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= |
24c29b7a PB |
5803 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
5804 | continue; | |
7cb85fc4 | 5805 | break; |
93c4adc7 PB |
5806 | default: |
5807 | break; | |
5808 | } | |
5809 | ||
7a5ee6ed | 5810 | msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; |
043405e1 | 5811 | } |
62ef68bb | 5812 | |
7a5ee6ed | 5813 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
5719455f | 5814 | if (!kvm_x86_ops.has_emulated_msr(NULL, emulated_msrs_all[i])) |
bc226f07 | 5815 | continue; |
62ef68bb | 5816 | |
7a5ee6ed | 5817 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 5818 | } |
801e459a | 5819 | |
7a5ee6ed | 5820 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { |
801e459a TL |
5821 | struct kvm_msr_entry msr; |
5822 | ||
7a5ee6ed | 5823 | msr.index = msr_based_features_all[i]; |
66421c1e | 5824 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
5825 | continue; |
5826 | ||
7a5ee6ed | 5827 | msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; |
801e459a | 5828 | } |
043405e1 CO |
5829 | } |
5830 | ||
bda9020e MT |
5831 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
5832 | const void *v) | |
bbd9b64e | 5833 | { |
70252a10 AK |
5834 | int handled = 0; |
5835 | int n; | |
5836 | ||
5837 | do { | |
5838 | n = min(len, 8); | |
bce87cce | 5839 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5840 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
5841 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
5842 | break; |
5843 | handled += n; | |
5844 | addr += n; | |
5845 | len -= n; | |
5846 | v += n; | |
5847 | } while (len); | |
bbd9b64e | 5848 | |
70252a10 | 5849 | return handled; |
bbd9b64e CO |
5850 | } |
5851 | ||
bda9020e | 5852 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 5853 | { |
70252a10 AK |
5854 | int handled = 0; |
5855 | int n; | |
5856 | ||
5857 | do { | |
5858 | n = min(len, 8); | |
bce87cce | 5859 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5860 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
5861 | addr, n, v)) | |
5862 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 5863 | break; |
e39d200f | 5864 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
5865 | handled += n; |
5866 | addr += n; | |
5867 | len -= n; | |
5868 | v += n; | |
5869 | } while (len); | |
bbd9b64e | 5870 | |
70252a10 | 5871 | return handled; |
bbd9b64e CO |
5872 | } |
5873 | ||
2dafc6c2 GN |
5874 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
5875 | struct kvm_segment *var, int seg) | |
5876 | { | |
afaf0b2f | 5877 | kvm_x86_ops.set_segment(vcpu, var, seg); |
2dafc6c2 GN |
5878 | } |
5879 | ||
5880 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
5881 | struct kvm_segment *var, int seg) | |
5882 | { | |
afaf0b2f | 5883 | kvm_x86_ops.get_segment(vcpu, var, seg); |
2dafc6c2 GN |
5884 | } |
5885 | ||
54987b7a PB |
5886 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
5887 | struct x86_exception *exception) | |
02f59dc9 JR |
5888 | { |
5889 | gpa_t t_gpa; | |
02f59dc9 JR |
5890 | |
5891 | BUG_ON(!mmu_is_nested(vcpu)); | |
5892 | ||
5893 | /* NPT walks are always user-walks */ | |
5894 | access |= PFERR_USER_MASK; | |
44dd3ffa | 5895 | t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
5896 | |
5897 | return t_gpa; | |
5898 | } | |
5899 | ||
ab9ae313 AK |
5900 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
5901 | struct x86_exception *exception) | |
1871c602 | 5902 | { |
afaf0b2f | 5903 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
ab9ae313 | 5904 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5905 | } |
5906 | ||
ab9ae313 AK |
5907 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
5908 | struct x86_exception *exception) | |
1871c602 | 5909 | { |
afaf0b2f | 5910 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 5911 | access |= PFERR_FETCH_MASK; |
ab9ae313 | 5912 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5913 | } |
5914 | ||
ab9ae313 AK |
5915 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
5916 | struct x86_exception *exception) | |
1871c602 | 5917 | { |
afaf0b2f | 5918 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 5919 | access |= PFERR_WRITE_MASK; |
ab9ae313 | 5920 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5921 | } |
5922 | ||
5923 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
5924 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
5925 | struct x86_exception *exception) | |
1871c602 | 5926 | { |
ab9ae313 | 5927 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
5928 | } |
5929 | ||
5930 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
5931 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 5932 | struct x86_exception *exception) |
bbd9b64e CO |
5933 | { |
5934 | void *data = val; | |
10589a46 | 5935 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
5936 | |
5937 | while (bytes) { | |
14dfe855 | 5938 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 5939 | exception); |
bbd9b64e | 5940 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 5941 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
5942 | int ret; |
5943 | ||
bcc55cba | 5944 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 5945 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
5946 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
5947 | offset, toread); | |
10589a46 | 5948 | if (ret < 0) { |
c3cd7ffa | 5949 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
5950 | goto out; |
5951 | } | |
bbd9b64e | 5952 | |
77c2002e IE |
5953 | bytes -= toread; |
5954 | data += toread; | |
5955 | addr += toread; | |
bbd9b64e | 5956 | } |
10589a46 | 5957 | out: |
10589a46 | 5958 | return r; |
bbd9b64e | 5959 | } |
77c2002e | 5960 | |
1871c602 | 5961 | /* used for instruction fetching */ |
0f65dd70 AK |
5962 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
5963 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 5964 | struct x86_exception *exception) |
1871c602 | 5965 | { |
0f65dd70 | 5966 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
afaf0b2f | 5967 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
5968 | unsigned offset; |
5969 | int ret; | |
0f65dd70 | 5970 | |
44583cba PB |
5971 | /* Inline kvm_read_guest_virt_helper for speed. */ |
5972 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
5973 | exception); | |
5974 | if (unlikely(gpa == UNMAPPED_GVA)) | |
5975 | return X86EMUL_PROPAGATE_FAULT; | |
5976 | ||
5977 | offset = addr & (PAGE_SIZE-1); | |
5978 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
5979 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
5980 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
5981 | offset, bytes); | |
44583cba PB |
5982 | if (unlikely(ret < 0)) |
5983 | return X86EMUL_IO_NEEDED; | |
5984 | ||
5985 | return X86EMUL_CONTINUE; | |
1871c602 GN |
5986 | } |
5987 | ||
ce14e868 | 5988 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 5989 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 5990 | struct x86_exception *exception) |
1871c602 | 5991 | { |
afaf0b2f | 5992 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 5993 | |
353c0956 PB |
5994 | /* |
5995 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
5996 | * is returned, but our callers are not ready for that and they blindly | |
5997 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
5998 | * uninitialized kernel stack memory into cr2 and error code. | |
5999 | */ | |
6000 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 6001 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 6002 | exception); |
1871c602 | 6003 | } |
064aea77 | 6004 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 6005 | |
ce14e868 PB |
6006 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
6007 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 6008 | struct x86_exception *exception, bool system) |
1871c602 | 6009 | { |
0f65dd70 | 6010 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3c9fa24c PB |
6011 | u32 access = 0; |
6012 | ||
afaf0b2f | 6013 | if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) |
3c9fa24c PB |
6014 | access |= PFERR_USER_MASK; |
6015 | ||
6016 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
6017 | } |
6018 | ||
7a036a6f RK |
6019 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
6020 | unsigned long addr, void *val, unsigned int bytes) | |
6021 | { | |
6022 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6023 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
6024 | ||
6025 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
6026 | } | |
6027 | ||
ce14e868 PB |
6028 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
6029 | struct kvm_vcpu *vcpu, u32 access, | |
6030 | struct x86_exception *exception) | |
77c2002e IE |
6031 | { |
6032 | void *data = val; | |
6033 | int r = X86EMUL_CONTINUE; | |
6034 | ||
6035 | while (bytes) { | |
14dfe855 | 6036 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
ce14e868 | 6037 | access, |
ab9ae313 | 6038 | exception); |
77c2002e IE |
6039 | unsigned offset = addr & (PAGE_SIZE-1); |
6040 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
6041 | int ret; | |
6042 | ||
bcc55cba | 6043 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6044 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 6045 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 6046 | if (ret < 0) { |
c3cd7ffa | 6047 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
6048 | goto out; |
6049 | } | |
6050 | ||
6051 | bytes -= towrite; | |
6052 | data += towrite; | |
6053 | addr += towrite; | |
6054 | } | |
6055 | out: | |
6056 | return r; | |
6057 | } | |
ce14e868 PB |
6058 | |
6059 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
6060 | unsigned int bytes, struct x86_exception *exception, |
6061 | bool system) | |
ce14e868 PB |
6062 | { |
6063 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
3c9fa24c PB |
6064 | u32 access = PFERR_WRITE_MASK; |
6065 | ||
afaf0b2f | 6066 | if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) |
3c9fa24c | 6067 | access |= PFERR_USER_MASK; |
ce14e868 PB |
6068 | |
6069 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 6070 | access, exception); |
ce14e868 PB |
6071 | } |
6072 | ||
6073 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
6074 | unsigned int bytes, struct x86_exception *exception) | |
6075 | { | |
c595ceee PB |
6076 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
6077 | vcpu->arch.l1tf_flush_l1d = true; | |
6078 | ||
ce14e868 PB |
6079 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
6080 | PFERR_WRITE_MASK, exception); | |
6081 | } | |
6a4d7550 | 6082 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 6083 | |
082d06ed WL |
6084 | int handle_ud(struct kvm_vcpu *vcpu) |
6085 | { | |
b3dc0695 | 6086 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
6c86eedc | 6087 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
6088 | char sig[5]; /* ud2; .ascii "kvm" */ |
6089 | struct x86_exception e; | |
6090 | ||
09e3e2a1 SC |
6091 | if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, NULL, 0))) |
6092 | return 1; | |
6093 | ||
6c86eedc | 6094 | if (force_emulation_prefix && |
3c9fa24c PB |
6095 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
6096 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 6097 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
6c86eedc | 6098 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 6099 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 6100 | } |
082d06ed | 6101 | |
60fc3d02 | 6102 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
6103 | } |
6104 | EXPORT_SYMBOL_GPL(handle_ud); | |
6105 | ||
0f89b207 TL |
6106 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6107 | gpa_t gpa, bool write) | |
6108 | { | |
6109 | /* For APIC access vmexit */ | |
6110 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6111 | return 1; | |
6112 | ||
6113 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
6114 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
6115 | return 1; | |
6116 | } | |
6117 | ||
6118 | return 0; | |
6119 | } | |
6120 | ||
af7cc7d1 XG |
6121 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6122 | gpa_t *gpa, struct x86_exception *exception, | |
6123 | bool write) | |
6124 | { | |
afaf0b2f | 6125 | u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
97d64b78 | 6126 | | (write ? PFERR_WRITE_MASK : 0); |
af7cc7d1 | 6127 | |
be94f6b7 HH |
6128 | /* |
6129 | * currently PKRU is only applied to ept enabled guest so | |
6130 | * there is no pkey in EPT page table for L1 guest or EPT | |
6131 | * shadow page table for L2 guest. | |
6132 | */ | |
97d64b78 | 6133 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 | 6134 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
871bd034 | 6135 | vcpu->arch.mmio_access, 0, access)) { |
bebb106a XG |
6136 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
6137 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 6138 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
6139 | return 1; |
6140 | } | |
6141 | ||
af7cc7d1 XG |
6142 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
6143 | ||
6144 | if (*gpa == UNMAPPED_GVA) | |
6145 | return -1; | |
6146 | ||
0f89b207 | 6147 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
6148 | } |
6149 | ||
3200f405 | 6150 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 6151 | const void *val, int bytes) |
bbd9b64e CO |
6152 | { |
6153 | int ret; | |
6154 | ||
54bf36aa | 6155 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 6156 | if (ret < 0) |
bbd9b64e | 6157 | return 0; |
0eb05bf2 | 6158 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
6159 | return 1; |
6160 | } | |
6161 | ||
77d197b2 XG |
6162 | struct read_write_emulator_ops { |
6163 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
6164 | int bytes); | |
6165 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6166 | void *val, int bytes); | |
6167 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6168 | int bytes, void *val); | |
6169 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6170 | void *val, int bytes); | |
6171 | bool write; | |
6172 | }; | |
6173 | ||
6174 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
6175 | { | |
6176 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 6177 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 6178 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
6179 | vcpu->mmio_read_completed = 0; |
6180 | return 1; | |
6181 | } | |
6182 | ||
6183 | return 0; | |
6184 | } | |
6185 | ||
6186 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6187 | void *val, int bytes) | |
6188 | { | |
54bf36aa | 6189 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
6190 | } |
6191 | ||
6192 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6193 | void *val, int bytes) | |
6194 | { | |
6195 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
6196 | } | |
6197 | ||
6198 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
6199 | { | |
e39d200f | 6200 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
6201 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
6202 | } | |
6203 | ||
6204 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6205 | void *val, int bytes) | |
6206 | { | |
e39d200f | 6207 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
6208 | return X86EMUL_IO_NEEDED; |
6209 | } | |
6210 | ||
6211 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6212 | void *val, int bytes) | |
6213 | { | |
f78146b0 AK |
6214 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
6215 | ||
87da7e66 | 6216 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
6217 | return X86EMUL_CONTINUE; |
6218 | } | |
6219 | ||
0fbe9b0b | 6220 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
6221 | .read_write_prepare = read_prepare, |
6222 | .read_write_emulate = read_emulate, | |
6223 | .read_write_mmio = vcpu_mmio_read, | |
6224 | .read_write_exit_mmio = read_exit_mmio, | |
6225 | }; | |
6226 | ||
0fbe9b0b | 6227 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
6228 | .read_write_emulate = write_emulate, |
6229 | .read_write_mmio = write_mmio, | |
6230 | .read_write_exit_mmio = write_exit_mmio, | |
6231 | .write = true, | |
6232 | }; | |
6233 | ||
22388a3c XG |
6234 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
6235 | unsigned int bytes, | |
6236 | struct x86_exception *exception, | |
6237 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 6238 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6239 | { |
af7cc7d1 XG |
6240 | gpa_t gpa; |
6241 | int handled, ret; | |
22388a3c | 6242 | bool write = ops->write; |
f78146b0 | 6243 | struct kvm_mmio_fragment *frag; |
c9b8b07c | 6244 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
0f89b207 TL |
6245 | |
6246 | /* | |
6247 | * If the exit was due to a NPF we may already have a GPA. | |
6248 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
6249 | * Note, this cannot be used on string operations since string | |
6250 | * operation using rep will only have the initial GPA from the NPF | |
6251 | * occurred. | |
6252 | */ | |
744e699c SC |
6253 | if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && |
6254 | (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { | |
6255 | gpa = ctxt->gpa_val; | |
618232e2 BS |
6256 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); |
6257 | } else { | |
6258 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
6259 | if (ret < 0) | |
6260 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 6261 | } |
10589a46 | 6262 | |
618232e2 | 6263 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
6264 | return X86EMUL_CONTINUE; |
6265 | ||
bbd9b64e CO |
6266 | /* |
6267 | * Is this MMIO handled locally? | |
6268 | */ | |
22388a3c | 6269 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 6270 | if (handled == bytes) |
bbd9b64e | 6271 | return X86EMUL_CONTINUE; |
bbd9b64e | 6272 | |
70252a10 AK |
6273 | gpa += handled; |
6274 | bytes -= handled; | |
6275 | val += handled; | |
6276 | ||
87da7e66 XG |
6277 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
6278 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
6279 | frag->gpa = gpa; | |
6280 | frag->data = val; | |
6281 | frag->len = bytes; | |
f78146b0 | 6282 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
6283 | } |
6284 | ||
52eb5a6d XL |
6285 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
6286 | unsigned long addr, | |
22388a3c XG |
6287 | void *val, unsigned int bytes, |
6288 | struct x86_exception *exception, | |
0fbe9b0b | 6289 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6290 | { |
0f65dd70 | 6291 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
6292 | gpa_t gpa; |
6293 | int rc; | |
6294 | ||
6295 | if (ops->read_write_prepare && | |
6296 | ops->read_write_prepare(vcpu, val, bytes)) | |
6297 | return X86EMUL_CONTINUE; | |
6298 | ||
6299 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 6300 | |
bbd9b64e CO |
6301 | /* Crossing a page boundary? */ |
6302 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 6303 | int now; |
bbd9b64e CO |
6304 | |
6305 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
6306 | rc = emulator_read_write_onepage(addr, val, now, exception, |
6307 | vcpu, ops); | |
6308 | ||
bbd9b64e CO |
6309 | if (rc != X86EMUL_CONTINUE) |
6310 | return rc; | |
6311 | addr += now; | |
bac15531 NA |
6312 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6313 | addr = (u32)addr; | |
bbd9b64e CO |
6314 | val += now; |
6315 | bytes -= now; | |
6316 | } | |
22388a3c | 6317 | |
f78146b0 AK |
6318 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
6319 | vcpu, ops); | |
6320 | if (rc != X86EMUL_CONTINUE) | |
6321 | return rc; | |
6322 | ||
6323 | if (!vcpu->mmio_nr_fragments) | |
6324 | return rc; | |
6325 | ||
6326 | gpa = vcpu->mmio_fragments[0].gpa; | |
6327 | ||
6328 | vcpu->mmio_needed = 1; | |
6329 | vcpu->mmio_cur_fragment = 0; | |
6330 | ||
87da7e66 | 6331 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
6332 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
6333 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
6334 | vcpu->run->mmio.phys_addr = gpa; | |
6335 | ||
6336 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
6337 | } |
6338 | ||
6339 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
6340 | unsigned long addr, | |
6341 | void *val, | |
6342 | unsigned int bytes, | |
6343 | struct x86_exception *exception) | |
6344 | { | |
6345 | return emulator_read_write(ctxt, addr, val, bytes, | |
6346 | exception, &read_emultor); | |
6347 | } | |
6348 | ||
52eb5a6d | 6349 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
6350 | unsigned long addr, |
6351 | const void *val, | |
6352 | unsigned int bytes, | |
6353 | struct x86_exception *exception) | |
6354 | { | |
6355 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
6356 | exception, &write_emultor); | |
bbd9b64e | 6357 | } |
bbd9b64e | 6358 | |
daea3e73 AK |
6359 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
6360 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
6361 | ||
6362 | #ifdef CONFIG_X86_64 | |
6363 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
6364 | #else | |
6365 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 6366 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
6367 | #endif |
6368 | ||
0f65dd70 AK |
6369 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
6370 | unsigned long addr, | |
bbd9b64e CO |
6371 | const void *old, |
6372 | const void *new, | |
6373 | unsigned int bytes, | |
0f65dd70 | 6374 | struct x86_exception *exception) |
bbd9b64e | 6375 | { |
42e35f80 | 6376 | struct kvm_host_map map; |
0f65dd70 | 6377 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
9de6fe3c | 6378 | u64 page_line_mask; |
daea3e73 | 6379 | gpa_t gpa; |
daea3e73 AK |
6380 | char *kaddr; |
6381 | bool exchanged; | |
2bacc55c | 6382 | |
daea3e73 AK |
6383 | /* guests cmpxchg8b have to be emulated atomically */ |
6384 | if (bytes > 8 || (bytes & (bytes - 1))) | |
6385 | goto emul_write; | |
10589a46 | 6386 | |
daea3e73 | 6387 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 6388 | |
daea3e73 AK |
6389 | if (gpa == UNMAPPED_GVA || |
6390 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6391 | goto emul_write; | |
2bacc55c | 6392 | |
9de6fe3c XL |
6393 | /* |
6394 | * Emulate the atomic as a straight write to avoid #AC if SLD is | |
6395 | * enabled in the host and the access splits a cache line. | |
6396 | */ | |
6397 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
6398 | page_line_mask = ~(cache_line_size() - 1); | |
6399 | else | |
6400 | page_line_mask = PAGE_MASK; | |
6401 | ||
6402 | if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) | |
daea3e73 | 6403 | goto emul_write; |
72dc67a6 | 6404 | |
42e35f80 | 6405 | if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) |
c19b8bd6 | 6406 | goto emul_write; |
72dc67a6 | 6407 | |
42e35f80 KA |
6408 | kaddr = map.hva + offset_in_page(gpa); |
6409 | ||
daea3e73 AK |
6410 | switch (bytes) { |
6411 | case 1: | |
6412 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
6413 | break; | |
6414 | case 2: | |
6415 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
6416 | break; | |
6417 | case 4: | |
6418 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
6419 | break; | |
6420 | case 8: | |
6421 | exchanged = CMPXCHG64(kaddr, old, new); | |
6422 | break; | |
6423 | default: | |
6424 | BUG(); | |
2bacc55c | 6425 | } |
42e35f80 KA |
6426 | |
6427 | kvm_vcpu_unmap(vcpu, &map, true); | |
daea3e73 AK |
6428 | |
6429 | if (!exchanged) | |
6430 | return X86EMUL_CMPXCHG_FAILED; | |
6431 | ||
0eb05bf2 | 6432 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
6433 | |
6434 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 6435 | |
3200f405 | 6436 | emul_write: |
daea3e73 | 6437 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 6438 | |
0f65dd70 | 6439 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
6440 | } |
6441 | ||
cf8f70bf GN |
6442 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
6443 | { | |
cbfc6c91 | 6444 | int r = 0, i; |
cf8f70bf | 6445 | |
cbfc6c91 WL |
6446 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
6447 | if (vcpu->arch.pio.in) | |
6448 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
6449 | vcpu->arch.pio.size, pd); | |
6450 | else | |
6451 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
6452 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
6453 | pd); | |
6454 | if (r) | |
6455 | break; | |
6456 | pd += vcpu->arch.pio.size; | |
6457 | } | |
cf8f70bf GN |
6458 | return r; |
6459 | } | |
6460 | ||
6f6fbe98 XG |
6461 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
6462 | unsigned short port, void *val, | |
6463 | unsigned int count, bool in) | |
cf8f70bf | 6464 | { |
cf8f70bf | 6465 | vcpu->arch.pio.port = port; |
6f6fbe98 | 6466 | vcpu->arch.pio.in = in; |
7972995b | 6467 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
6468 | vcpu->arch.pio.size = size; |
6469 | ||
6470 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 6471 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6472 | return 1; |
6473 | } | |
6474 | ||
6475 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 6476 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
6477 | vcpu->run->io.size = size; |
6478 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
6479 | vcpu->run->io.count = count; | |
6480 | vcpu->run->io.port = port; | |
6481 | ||
6482 | return 0; | |
6483 | } | |
6484 | ||
2e3bb4d8 SC |
6485 | static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
6486 | unsigned short port, void *val, unsigned int count) | |
cf8f70bf | 6487 | { |
6f6fbe98 | 6488 | int ret; |
ca1d4a9e | 6489 | |
6f6fbe98 XG |
6490 | if (vcpu->arch.pio.count) |
6491 | goto data_avail; | |
cf8f70bf | 6492 | |
cbfc6c91 WL |
6493 | memset(vcpu->arch.pio_data, 0, size * count); |
6494 | ||
6f6fbe98 XG |
6495 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
6496 | if (ret) { | |
6497 | data_avail: | |
6498 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 6499 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 6500 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6501 | return 1; |
6502 | } | |
6503 | ||
cf8f70bf GN |
6504 | return 0; |
6505 | } | |
6506 | ||
2e3bb4d8 SC |
6507 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
6508 | int size, unsigned short port, void *val, | |
6509 | unsigned int count) | |
6f6fbe98 | 6510 | { |
2e3bb4d8 | 6511 | return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); |
6f6fbe98 | 6512 | |
2e3bb4d8 | 6513 | } |
6f6fbe98 | 6514 | |
2e3bb4d8 SC |
6515 | static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, |
6516 | unsigned short port, const void *val, | |
6517 | unsigned int count) | |
6518 | { | |
6f6fbe98 | 6519 | memcpy(vcpu->arch.pio_data, val, size * count); |
1171903d | 6520 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
6521 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
6522 | } | |
6523 | ||
2e3bb4d8 SC |
6524 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
6525 | int size, unsigned short port, | |
6526 | const void *val, unsigned int count) | |
6527 | { | |
6528 | return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); | |
6529 | } | |
6530 | ||
bbd9b64e CO |
6531 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
6532 | { | |
afaf0b2f | 6533 | return kvm_x86_ops.get_segment_base(vcpu, seg); |
bbd9b64e CO |
6534 | } |
6535 | ||
3cb16fe7 | 6536 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 6537 | { |
3cb16fe7 | 6538 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
6539 | } |
6540 | ||
ae6a2375 | 6541 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
6542 | { |
6543 | if (!need_emulate_wbinvd(vcpu)) | |
6544 | return X86EMUL_CONTINUE; | |
6545 | ||
afaf0b2f | 6546 | if (kvm_x86_ops.has_wbinvd_exit()) { |
2eec7343 JK |
6547 | int cpu = get_cpu(); |
6548 | ||
6549 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
6550 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
6551 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 6552 | put_cpu(); |
f5f48ee1 | 6553 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
6554 | } else |
6555 | wbinvd(); | |
f5f48ee1 SY |
6556 | return X86EMUL_CONTINUE; |
6557 | } | |
5cb56059 JS |
6558 | |
6559 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
6560 | { | |
6affcbed KH |
6561 | kvm_emulate_wbinvd_noskip(vcpu); |
6562 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 6563 | } |
f5f48ee1 SY |
6564 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
6565 | ||
5cb56059 JS |
6566 | |
6567 | ||
bcaf5cc5 AK |
6568 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
6569 | { | |
5cb56059 | 6570 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
6571 | } |
6572 | ||
52eb5a6d XL |
6573 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6574 | unsigned long *dest) | |
bbd9b64e | 6575 | { |
16f8a6f9 | 6576 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
6577 | } |
6578 | ||
52eb5a6d XL |
6579 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6580 | unsigned long value) | |
bbd9b64e | 6581 | { |
338dbc97 | 6582 | |
717746e3 | 6583 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
6584 | } |
6585 | ||
52a46617 | 6586 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 6587 | { |
52a46617 | 6588 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
6589 | } |
6590 | ||
717746e3 | 6591 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 6592 | { |
717746e3 | 6593 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
6594 | unsigned long value; |
6595 | ||
6596 | switch (cr) { | |
6597 | case 0: | |
6598 | value = kvm_read_cr0(vcpu); | |
6599 | break; | |
6600 | case 2: | |
6601 | value = vcpu->arch.cr2; | |
6602 | break; | |
6603 | case 3: | |
9f8fe504 | 6604 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
6605 | break; |
6606 | case 4: | |
6607 | value = kvm_read_cr4(vcpu); | |
6608 | break; | |
6609 | case 8: | |
6610 | value = kvm_get_cr8(vcpu); | |
6611 | break; | |
6612 | default: | |
a737f256 | 6613 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
6614 | return 0; |
6615 | } | |
6616 | ||
6617 | return value; | |
6618 | } | |
6619 | ||
717746e3 | 6620 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 6621 | { |
717746e3 | 6622 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
6623 | int res = 0; |
6624 | ||
52a46617 GN |
6625 | switch (cr) { |
6626 | case 0: | |
49a9b07e | 6627 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
6628 | break; |
6629 | case 2: | |
6630 | vcpu->arch.cr2 = val; | |
6631 | break; | |
6632 | case 3: | |
2390218b | 6633 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
6634 | break; |
6635 | case 4: | |
a83b29c6 | 6636 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
6637 | break; |
6638 | case 8: | |
eea1cff9 | 6639 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
6640 | break; |
6641 | default: | |
a737f256 | 6642 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 6643 | res = -1; |
52a46617 | 6644 | } |
0f12244f GN |
6645 | |
6646 | return res; | |
52a46617 GN |
6647 | } |
6648 | ||
717746e3 | 6649 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 6650 | { |
afaf0b2f | 6651 | return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
6652 | } |
6653 | ||
4bff1e86 | 6654 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 6655 | { |
afaf0b2f | 6656 | kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
6657 | } |
6658 | ||
4bff1e86 | 6659 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 6660 | { |
afaf0b2f | 6661 | kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
6662 | } |
6663 | ||
1ac9d0cf AK |
6664 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
6665 | { | |
afaf0b2f | 6666 | kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
6667 | } |
6668 | ||
6669 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
6670 | { | |
afaf0b2f | 6671 | kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
6672 | } |
6673 | ||
4bff1e86 AK |
6674 | static unsigned long emulator_get_cached_segment_base( |
6675 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 6676 | { |
4bff1e86 | 6677 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
6678 | } |
6679 | ||
1aa36616 AK |
6680 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
6681 | struct desc_struct *desc, u32 *base3, | |
6682 | int seg) | |
2dafc6c2 GN |
6683 | { |
6684 | struct kvm_segment var; | |
6685 | ||
4bff1e86 | 6686 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 6687 | *selector = var.selector; |
2dafc6c2 | 6688 | |
378a8b09 GN |
6689 | if (var.unusable) { |
6690 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
6691 | if (base3) |
6692 | *base3 = 0; | |
2dafc6c2 | 6693 | return false; |
378a8b09 | 6694 | } |
2dafc6c2 GN |
6695 | |
6696 | if (var.g) | |
6697 | var.limit >>= 12; | |
6698 | set_desc_limit(desc, var.limit); | |
6699 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
6700 | #ifdef CONFIG_X86_64 |
6701 | if (base3) | |
6702 | *base3 = var.base >> 32; | |
6703 | #endif | |
2dafc6c2 GN |
6704 | desc->type = var.type; |
6705 | desc->s = var.s; | |
6706 | desc->dpl = var.dpl; | |
6707 | desc->p = var.present; | |
6708 | desc->avl = var.avl; | |
6709 | desc->l = var.l; | |
6710 | desc->d = var.db; | |
6711 | desc->g = var.g; | |
6712 | ||
6713 | return true; | |
6714 | } | |
6715 | ||
1aa36616 AK |
6716 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
6717 | struct desc_struct *desc, u32 base3, | |
6718 | int seg) | |
2dafc6c2 | 6719 | { |
4bff1e86 | 6720 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
6721 | struct kvm_segment var; |
6722 | ||
1aa36616 | 6723 | var.selector = selector; |
2dafc6c2 | 6724 | var.base = get_desc_base(desc); |
5601d05b GN |
6725 | #ifdef CONFIG_X86_64 |
6726 | var.base |= ((u64)base3) << 32; | |
6727 | #endif | |
2dafc6c2 GN |
6728 | var.limit = get_desc_limit(desc); |
6729 | if (desc->g) | |
6730 | var.limit = (var.limit << 12) | 0xfff; | |
6731 | var.type = desc->type; | |
2dafc6c2 GN |
6732 | var.dpl = desc->dpl; |
6733 | var.db = desc->d; | |
6734 | var.s = desc->s; | |
6735 | var.l = desc->l; | |
6736 | var.g = desc->g; | |
6737 | var.avl = desc->avl; | |
6738 | var.present = desc->p; | |
6739 | var.unusable = !var.present; | |
6740 | var.padding = 0; | |
6741 | ||
6742 | kvm_set_segment(vcpu, &var, seg); | |
6743 | return; | |
6744 | } | |
6745 | ||
717746e3 AK |
6746 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
6747 | u32 msr_index, u64 *pdata) | |
6748 | { | |
1ae09954 AG |
6749 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6750 | int r; | |
6751 | ||
6752 | r = kvm_get_msr(vcpu, msr_index, pdata); | |
6753 | ||
6754 | if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { | |
6755 | /* Bounce to user space */ | |
6756 | return X86EMUL_IO_NEEDED; | |
6757 | } | |
6758 | ||
6759 | return r; | |
717746e3 AK |
6760 | } |
6761 | ||
6762 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
6763 | u32 msr_index, u64 data) | |
6764 | { | |
1ae09954 AG |
6765 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6766 | int r; | |
6767 | ||
6768 | r = kvm_set_msr(vcpu, msr_index, data); | |
6769 | ||
6770 | if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { | |
6771 | /* Bounce to user space */ | |
6772 | return X86EMUL_IO_NEEDED; | |
6773 | } | |
6774 | ||
6775 | return r; | |
717746e3 AK |
6776 | } |
6777 | ||
64d60670 PB |
6778 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
6779 | { | |
6780 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6781 | ||
6782 | return vcpu->arch.smbase; | |
6783 | } | |
6784 | ||
6785 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
6786 | { | |
6787 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6788 | ||
6789 | vcpu->arch.smbase = smbase; | |
6790 | } | |
6791 | ||
67f4d428 NA |
6792 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
6793 | u32 pmc) | |
6794 | { | |
98ff80f5 | 6795 | return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
6796 | } |
6797 | ||
222d21aa AK |
6798 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
6799 | u32 pmc, u64 *pdata) | |
6800 | { | |
c6702c9d | 6801 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
6802 | } |
6803 | ||
6c3287f7 AK |
6804 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
6805 | { | |
6806 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
6807 | } | |
6808 | ||
2953538e | 6809 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 6810 | struct x86_instruction_info *info, |
c4f035c6 AK |
6811 | enum x86_intercept_stage stage) |
6812 | { | |
afaf0b2f | 6813 | return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage, |
21f1b8f2 | 6814 | &ctxt->exception); |
c4f035c6 AK |
6815 | } |
6816 | ||
e911eb3b | 6817 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
f91af517 SC |
6818 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, |
6819 | bool exact_only) | |
bdb42f5a | 6820 | { |
f91af517 | 6821 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); |
bdb42f5a SB |
6822 | } |
6823 | ||
5ae78e95 SC |
6824 | static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) |
6825 | { | |
6826 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); | |
6827 | } | |
6828 | ||
6829 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) | |
6830 | { | |
6831 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
6832 | } | |
6833 | ||
6834 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
6835 | { | |
6836 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
6837 | } | |
6838 | ||
dd856efa AK |
6839 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
6840 | { | |
6841 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
6842 | } | |
6843 | ||
6844 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
6845 | { | |
6846 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
6847 | } | |
6848 | ||
801806d9 NA |
6849 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
6850 | { | |
afaf0b2f | 6851 | kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked); |
801806d9 NA |
6852 | } |
6853 | ||
6ed071f0 LP |
6854 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
6855 | { | |
6856 | return emul_to_vcpu(ctxt)->arch.hflags; | |
6857 | } | |
6858 | ||
6859 | static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) | |
6860 | { | |
c5833c7a | 6861 | emul_to_vcpu(ctxt)->arch.hflags = emul_flags; |
6ed071f0 LP |
6862 | } |
6863 | ||
ed19321f SC |
6864 | static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, |
6865 | const char *smstate) | |
0234bf88 | 6866 | { |
afaf0b2f | 6867 | return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
6868 | } |
6869 | ||
c5833c7a SC |
6870 | static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) |
6871 | { | |
6872 | kvm_smm_changed(emul_to_vcpu(ctxt)); | |
6873 | } | |
6874 | ||
02d4160f VK |
6875 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
6876 | { | |
6877 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
6878 | } | |
6879 | ||
0225fb50 | 6880 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
6881 | .read_gpr = emulator_read_gpr, |
6882 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
6883 | .read_std = emulator_read_std, |
6884 | .write_std = emulator_write_std, | |
7a036a6f | 6885 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 6886 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
6887 | .read_emulated = emulator_read_emulated, |
6888 | .write_emulated = emulator_write_emulated, | |
6889 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 6890 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
6891 | .pio_in_emulated = emulator_pio_in_emulated, |
6892 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
6893 | .get_segment = emulator_get_segment, |
6894 | .set_segment = emulator_set_segment, | |
5951c442 | 6895 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 6896 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 6897 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
6898 | .set_gdt = emulator_set_gdt, |
6899 | .set_idt = emulator_set_idt, | |
52a46617 GN |
6900 | .get_cr = emulator_get_cr, |
6901 | .set_cr = emulator_set_cr, | |
9c537244 | 6902 | .cpl = emulator_get_cpl, |
35aa5375 GN |
6903 | .get_dr = emulator_get_dr, |
6904 | .set_dr = emulator_set_dr, | |
64d60670 PB |
6905 | .get_smbase = emulator_get_smbase, |
6906 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
6907 | .set_msr = emulator_set_msr, |
6908 | .get_msr = emulator_get_msr, | |
67f4d428 | 6909 | .check_pmc = emulator_check_pmc, |
222d21aa | 6910 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 6911 | .halt = emulator_halt, |
bcaf5cc5 | 6912 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 6913 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 6914 | .intercept = emulator_intercept, |
bdb42f5a | 6915 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
6916 | .guest_has_long_mode = emulator_guest_has_long_mode, |
6917 | .guest_has_movbe = emulator_guest_has_movbe, | |
6918 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
801806d9 | 6919 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 LP |
6920 | .get_hflags = emulator_get_hflags, |
6921 | .set_hflags = emulator_set_hflags, | |
0234bf88 | 6922 | .pre_leave_smm = emulator_pre_leave_smm, |
c5833c7a | 6923 | .post_leave_smm = emulator_post_leave_smm, |
02d4160f | 6924 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
6925 | }; |
6926 | ||
95cb2295 GN |
6927 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
6928 | { | |
afaf0b2f | 6929 | u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); |
95cb2295 GN |
6930 | /* |
6931 | * an sti; sti; sequence only disable interrupts for the first | |
6932 | * instruction. So, if the last instruction, be it emulated or | |
6933 | * not, left the system with the INT_STI flag enabled, it | |
6934 | * means that the last instruction is an sti. We should not | |
6935 | * leave the flag on in this case. The same goes for mov ss | |
6936 | */ | |
37ccdcbe PB |
6937 | if (int_shadow & mask) |
6938 | mask = 0; | |
6addfc42 | 6939 | if (unlikely(int_shadow || mask)) { |
afaf0b2f | 6940 | kvm_x86_ops.set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
6941 | if (!mask) |
6942 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6943 | } | |
95cb2295 GN |
6944 | } |
6945 | ||
ef54bcfe | 6946 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f | 6947 | { |
c9b8b07c | 6948 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
da9cb575 | 6949 | if (ctxt->exception.vector == PF_VECTOR) |
53b3d8e9 | 6950 | return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); |
ef54bcfe PB |
6951 | |
6952 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
6953 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
6954 | ctxt->exception.error_code); | |
54b8486f | 6955 | else |
da9cb575 | 6956 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 6957 | return false; |
54b8486f GN |
6958 | } |
6959 | ||
c9b8b07c SC |
6960 | static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) |
6961 | { | |
6962 | struct x86_emulate_ctxt *ctxt; | |
6963 | ||
6964 | ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); | |
6965 | if (!ctxt) { | |
6966 | pr_err("kvm: failed to allocate vcpu's emulator\n"); | |
6967 | return NULL; | |
6968 | } | |
6969 | ||
6970 | ctxt->vcpu = vcpu; | |
6971 | ctxt->ops = &emulate_ops; | |
6972 | vcpu->arch.emulate_ctxt = ctxt; | |
6973 | ||
6974 | return ctxt; | |
6975 | } | |
6976 | ||
8ec4722d MG |
6977 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
6978 | { | |
c9b8b07c | 6979 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d MG |
6980 | int cs_db, cs_l; |
6981 | ||
afaf0b2f | 6982 | kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
8ec4722d | 6983 | |
744e699c | 6984 | ctxt->gpa_available = false; |
adf52235 | 6985 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
6986 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
6987 | ||
adf52235 TY |
6988 | ctxt->eip = kvm_rip_read(vcpu); |
6989 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
6990 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 6991 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
6992 | cs_db ? X86EMUL_MODE_PROT32 : |
6993 | X86EMUL_MODE_PROT16; | |
a584539b | 6994 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
6995 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
6996 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 6997 | |
dd856efa | 6998 | init_decode_cache(ctxt); |
7ae441ea | 6999 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
7000 | } |
7001 | ||
9497e1f2 | 7002 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 7003 | { |
c9b8b07c | 7004 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
63995653 MG |
7005 | int ret; |
7006 | ||
7007 | init_emulate_ctxt(vcpu); | |
7008 | ||
9dac77fa AK |
7009 | ctxt->op_bytes = 2; |
7010 | ctxt->ad_bytes = 2; | |
7011 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 7012 | ret = emulate_int_real(ctxt, irq); |
63995653 | 7013 | |
9497e1f2 SC |
7014 | if (ret != X86EMUL_CONTINUE) { |
7015 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
7016 | } else { | |
7017 | ctxt->eip = ctxt->_eip; | |
7018 | kvm_rip_write(vcpu, ctxt->eip); | |
7019 | kvm_set_rflags(vcpu, ctxt->eflags); | |
7020 | } | |
63995653 MG |
7021 | } |
7022 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
7023 | ||
e2366171 | 7024 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 7025 | { |
6d77dbfc GN |
7026 | ++vcpu->stat.insn_emulation_fail; |
7027 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 7028 | |
42cbf068 SC |
7029 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
7030 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7031 | return 1; |
42cbf068 | 7032 | } |
e2366171 | 7033 | |
738fece4 SC |
7034 | if (emulation_type & EMULTYPE_SKIP) { |
7035 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7036 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7037 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7038 | return 0; |
738fece4 SC |
7039 | } |
7040 | ||
22da61c9 SC |
7041 | kvm_queue_exception(vcpu, UD_VECTOR); |
7042 | ||
afaf0b2f | 7043 | if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) { |
fc3a9157 JR |
7044 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
7045 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7046 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7047 | return 0; |
fc3a9157 | 7048 | } |
e2366171 | 7049 | |
60fc3d02 | 7050 | return 1; |
6d77dbfc GN |
7051 | } |
7052 | ||
736c291c | 7053 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 GN |
7054 | bool write_fault_to_shadow_pgtable, |
7055 | int emulation_type) | |
a6f177ef | 7056 | { |
736c291c | 7057 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 7058 | kvm_pfn_t pfn; |
a6f177ef | 7059 | |
92daa48b | 7060 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
991eebf9 GN |
7061 | return false; |
7062 | ||
92daa48b SC |
7063 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7064 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7065 | return false; |
7066 | ||
44dd3ffa | 7067 | if (!vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7068 | /* |
7069 | * Write permission should be allowed since only | |
7070 | * write access need to be emulated. | |
7071 | */ | |
736c291c | 7072 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 7073 | |
95b3cf69 XG |
7074 | /* |
7075 | * If the mapping is invalid in guest, let cpu retry | |
7076 | * it to generate fault. | |
7077 | */ | |
7078 | if (gpa == UNMAPPED_GVA) | |
7079 | return true; | |
7080 | } | |
a6f177ef | 7081 | |
8e3d9d06 XG |
7082 | /* |
7083 | * Do not retry the unhandleable instruction if it faults on the | |
7084 | * readonly host memory, otherwise it will goto a infinite loop: | |
7085 | * retry instruction -> write #PF -> emulation fail -> retry | |
7086 | * instruction -> ... | |
7087 | */ | |
7088 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
7089 | |
7090 | /* | |
7091 | * If the instruction failed on the error pfn, it can not be fixed, | |
7092 | * report the error to userspace. | |
7093 | */ | |
7094 | if (is_error_noslot_pfn(pfn)) | |
7095 | return false; | |
7096 | ||
7097 | kvm_release_pfn_clean(pfn); | |
7098 | ||
7099 | /* The instructions are well-emulated on direct mmu. */ | |
44dd3ffa | 7100 | if (vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7101 | unsigned int indirect_shadow_pages; |
7102 | ||
7103 | spin_lock(&vcpu->kvm->mmu_lock); | |
7104 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
7105 | spin_unlock(&vcpu->kvm->mmu_lock); | |
7106 | ||
7107 | if (indirect_shadow_pages) | |
7108 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
7109 | ||
a6f177ef | 7110 | return true; |
8e3d9d06 | 7111 | } |
a6f177ef | 7112 | |
95b3cf69 XG |
7113 | /* |
7114 | * if emulation was due to access to shadowed page table | |
7115 | * and it failed try to unshadow page and re-enter the | |
7116 | * guest to let CPU execute the instruction. | |
7117 | */ | |
7118 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
7119 | |
7120 | /* | |
7121 | * If the access faults on its page table, it can not | |
7122 | * be fixed by unprotecting shadow page and it should | |
7123 | * be reported to userspace. | |
7124 | */ | |
7125 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
7126 | } |
7127 | ||
1cb3f3ae | 7128 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 7129 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
7130 | { |
7131 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 7132 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
7133 | |
7134 | last_retry_eip = vcpu->arch.last_retry_eip; | |
7135 | last_retry_addr = vcpu->arch.last_retry_addr; | |
7136 | ||
7137 | /* | |
7138 | * If the emulation is caused by #PF and it is non-page_table | |
7139 | * writing instruction, it means the VM-EXIT is caused by shadow | |
7140 | * page protected, we can zap the shadow page and retry this | |
7141 | * instruction directly. | |
7142 | * | |
7143 | * Note: if the guest uses a non-page-table modifying instruction | |
7144 | * on the PDE that points to the instruction, then we will unmap | |
7145 | * the instruction and go to an infinite loop. So, we cache the | |
7146 | * last retried eip and the last fault address, if we meet the eip | |
7147 | * and the address again, we can break out of the potential infinite | |
7148 | * loop. | |
7149 | */ | |
7150 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
7151 | ||
92daa48b | 7152 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
1cb3f3ae XG |
7153 | return false; |
7154 | ||
92daa48b SC |
7155 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7156 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7157 | return false; |
7158 | ||
1cb3f3ae XG |
7159 | if (x86_page_table_writing_insn(ctxt)) |
7160 | return false; | |
7161 | ||
736c291c | 7162 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
7163 | return false; |
7164 | ||
7165 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 7166 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 7167 | |
44dd3ffa | 7168 | if (!vcpu->arch.mmu->direct_map) |
736c291c | 7169 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 7170 | |
22368028 | 7171 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
7172 | |
7173 | return true; | |
7174 | } | |
7175 | ||
716d51ab GN |
7176 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
7177 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
7178 | ||
64d60670 | 7179 | static void kvm_smm_changed(struct kvm_vcpu *vcpu) |
a584539b | 7180 | { |
64d60670 | 7181 | if (!(vcpu->arch.hflags & HF_SMM_MASK)) { |
660a5d51 PB |
7182 | /* This is a good place to trace that we are exiting SMM. */ |
7183 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); | |
7184 | ||
c43203ca PB |
7185 | /* Process a latched INIT or SMI, if any. */ |
7186 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 | 7187 | } |
699023e2 PB |
7188 | |
7189 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
7190 | } |
7191 | ||
4a1e10d5 PB |
7192 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
7193 | unsigned long *db) | |
7194 | { | |
7195 | u32 dr6 = 0; | |
7196 | int i; | |
7197 | u32 enable, rwlen; | |
7198 | ||
7199 | enable = dr7; | |
7200 | rwlen = dr7 >> 16; | |
7201 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
7202 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
7203 | dr6 |= (1 << i); | |
7204 | return dr6; | |
7205 | } | |
7206 | ||
120c2c4f | 7207 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
7208 | { |
7209 | struct kvm_run *kvm_run = vcpu->run; | |
7210 | ||
c8401dda PB |
7211 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
7212 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; | |
d5d260c5 | 7213 | kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
c8401dda PB |
7214 | kvm_run->debug.arch.exception = DB_VECTOR; |
7215 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7216 | return 0; |
663f4c61 | 7217 | } |
120c2c4f | 7218 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 7219 | return 1; |
663f4c61 PB |
7220 | } |
7221 | ||
6affcbed KH |
7222 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
7223 | { | |
afaf0b2f | 7224 | unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); |
f8ea7c60 | 7225 | int r; |
6affcbed | 7226 | |
afaf0b2f | 7227 | r = kvm_x86_ops.skip_emulated_instruction(vcpu); |
60fc3d02 | 7228 | if (unlikely(!r)) |
f8ea7c60 | 7229 | return 0; |
c8401dda PB |
7230 | |
7231 | /* | |
7232 | * rflags is the old, "raw" value of the flags. The new value has | |
7233 | * not been saved yet. | |
7234 | * | |
7235 | * This is correct even for TF set by the guest, because "the | |
7236 | * processor will not generate this exception after the instruction | |
7237 | * that sets the TF flag". | |
7238 | */ | |
7239 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 7240 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 7241 | return r; |
6affcbed KH |
7242 | } |
7243 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
7244 | ||
4a1e10d5 PB |
7245 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
7246 | { | |
4a1e10d5 PB |
7247 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
7248 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
7249 | struct kvm_run *kvm_run = vcpu->run; |
7250 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
7251 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7252 | vcpu->arch.guest_debug_dr7, |
7253 | vcpu->arch.eff_db); | |
7254 | ||
7255 | if (dr6 != 0) { | |
6f43ed01 | 7256 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 7257 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
7258 | kvm_run->debug.arch.exception = DB_VECTOR; |
7259 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7260 | *r = 0; |
4a1e10d5 PB |
7261 | return true; |
7262 | } | |
7263 | } | |
7264 | ||
4161a569 NA |
7265 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
7266 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
7267 | unsigned long eip = kvm_get_linear_rip(vcpu); |
7268 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7269 | vcpu->arch.dr7, |
7270 | vcpu->arch.db); | |
7271 | ||
7272 | if (dr6 != 0) { | |
4d5523cf | 7273 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
60fc3d02 | 7274 | *r = 1; |
4a1e10d5 PB |
7275 | return true; |
7276 | } | |
7277 | } | |
7278 | ||
7279 | return false; | |
7280 | } | |
7281 | ||
04789b66 LA |
7282 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
7283 | { | |
2d7921c4 AM |
7284 | switch (ctxt->opcode_len) { |
7285 | case 1: | |
7286 | switch (ctxt->b) { | |
7287 | case 0xe4: /* IN */ | |
7288 | case 0xe5: | |
7289 | case 0xec: | |
7290 | case 0xed: | |
7291 | case 0xe6: /* OUT */ | |
7292 | case 0xe7: | |
7293 | case 0xee: | |
7294 | case 0xef: | |
7295 | case 0x6c: /* INS */ | |
7296 | case 0x6d: | |
7297 | case 0x6e: /* OUTS */ | |
7298 | case 0x6f: | |
7299 | return true; | |
7300 | } | |
7301 | break; | |
7302 | case 2: | |
7303 | switch (ctxt->b) { | |
7304 | case 0x33: /* RDPMC */ | |
7305 | return true; | |
7306 | } | |
7307 | break; | |
04789b66 LA |
7308 | } |
7309 | ||
7310 | return false; | |
7311 | } | |
7312 | ||
736c291c SC |
7313 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
7314 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 7315 | { |
95cb2295 | 7316 | int r; |
c9b8b07c | 7317 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
7ae441ea | 7318 | bool writeback = true; |
09e3e2a1 SC |
7319 | bool write_fault_to_spt; |
7320 | ||
7321 | if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, insn, insn_len))) | |
7322 | return 1; | |
bbd9b64e | 7323 | |
c595ceee PB |
7324 | vcpu->arch.l1tf_flush_l1d = true; |
7325 | ||
93c05d3e XG |
7326 | /* |
7327 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
7328 | * never reused. | |
7329 | */ | |
09e3e2a1 | 7330 | write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
93c05d3e | 7331 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
26eef70c | 7332 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 7333 | |
571008da | 7334 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 7335 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
7336 | |
7337 | /* | |
7338 | * We will reenter on the same instruction since | |
7339 | * we do not set complete_userspace_io. This does not | |
7340 | * handle watchpoints yet, those would be handled in | |
7341 | * the emulate_ops. | |
7342 | */ | |
d391f120 VK |
7343 | if (!(emulation_type & EMULTYPE_SKIP) && |
7344 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
4a1e10d5 PB |
7345 | return r; |
7346 | ||
9d74191a TY |
7347 | ctxt->interruptibility = 0; |
7348 | ctxt->have_exception = false; | |
e0ad0b47 | 7349 | ctxt->exception.vector = -1; |
9d74191a | 7350 | ctxt->perm_ok = false; |
bbd9b64e | 7351 | |
b51e974f | 7352 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 7353 | |
9d74191a | 7354 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 7355 | |
e46479f8 | 7356 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 7357 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 7358 | if (r != EMULATION_OK) { |
b4000606 | 7359 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
7360 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
7361 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 7362 | return 1; |
c83fad65 | 7363 | } |
736c291c SC |
7364 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
7365 | write_fault_to_spt, | |
7366 | emulation_type)) | |
60fc3d02 | 7367 | return 1; |
8530a79c | 7368 | if (ctxt->have_exception) { |
c8848cee JD |
7369 | /* |
7370 | * #UD should result in just EMULATION_FAILED, and trap-like | |
7371 | * exception should not be encountered during decode. | |
7372 | */ | |
7373 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
7374 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 7375 | inject_emulated_exception(vcpu); |
60fc3d02 | 7376 | return 1; |
8530a79c | 7377 | } |
e2366171 | 7378 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7379 | } |
7380 | } | |
7381 | ||
42cbf068 SC |
7382 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
7383 | !is_vmware_backdoor_opcode(ctxt)) { | |
7384 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7385 | return 1; |
42cbf068 | 7386 | } |
04789b66 | 7387 | |
1957aa63 SC |
7388 | /* |
7389 | * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks | |
7390 | * for kvm_skip_emulated_instruction(). The caller is responsible for | |
7391 | * updating interruptibility state and injecting single-step #DBs. | |
7392 | */ | |
ba8afb6b | 7393 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 7394 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
7395 | if (ctxt->eflags & X86_EFLAGS_RF) |
7396 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 7397 | return 1; |
ba8afb6b GN |
7398 | } |
7399 | ||
736c291c | 7400 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 7401 | return 1; |
1cb3f3ae | 7402 | |
7ae441ea | 7403 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 7404 | changes registers values during IO operation */ |
7ae441ea GN |
7405 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
7406 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 7407 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 7408 | } |
4d2179e1 | 7409 | |
5cd21917 | 7410 | restart: |
92daa48b SC |
7411 | if (emulation_type & EMULTYPE_PF) { |
7412 | /* Save the faulting GPA (cr2) in the address field */ | |
7413 | ctxt->exception.address = cr2_or_gpa; | |
7414 | ||
7415 | /* With shadow page tables, cr2 contains a GVA or nGPA. */ | |
7416 | if (vcpu->arch.mmu->direct_map) { | |
744e699c SC |
7417 | ctxt->gpa_available = true; |
7418 | ctxt->gpa_val = cr2_or_gpa; | |
92daa48b SC |
7419 | } |
7420 | } else { | |
7421 | /* Sanitize the address out of an abundance of paranoia. */ | |
7422 | ctxt->exception.address = 0; | |
7423 | } | |
0f89b207 | 7424 | |
9d74191a | 7425 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 7426 | |
775fde86 | 7427 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 7428 | return 1; |
775fde86 | 7429 | |
d2ddd1c4 | 7430 | if (r == EMULATION_FAILED) { |
736c291c | 7431 | if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, |
991eebf9 | 7432 | emulation_type)) |
60fc3d02 | 7433 | return 1; |
c3cd7ffa | 7434 | |
e2366171 | 7435 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7436 | } |
7437 | ||
9d74191a | 7438 | if (ctxt->have_exception) { |
60fc3d02 | 7439 | r = 1; |
ef54bcfe PB |
7440 | if (inject_emulated_exception(vcpu)) |
7441 | return r; | |
d2ddd1c4 | 7442 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
7443 | if (!vcpu->arch.pio.in) { |
7444 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 7445 | vcpu->arch.pio.count = 0; |
0912c977 | 7446 | } else { |
7ae441ea | 7447 | writeback = false; |
716d51ab GN |
7448 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
7449 | } | |
60fc3d02 | 7450 | r = 0; |
7ae441ea | 7451 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
7452 | ++vcpu->stat.mmio_exits; |
7453 | ||
7ae441ea GN |
7454 | if (!vcpu->mmio_is_write) |
7455 | writeback = false; | |
60fc3d02 | 7456 | r = 0; |
716d51ab | 7457 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 7458 | } else if (r == EMULATION_RESTART) |
5cd21917 | 7459 | goto restart; |
d2ddd1c4 | 7460 | else |
60fc3d02 | 7461 | r = 1; |
f850e2e6 | 7462 | |
7ae441ea | 7463 | if (writeback) { |
afaf0b2f | 7464 | unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); |
9d74191a | 7465 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 7466 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
38827dbd | 7467 | if (!ctxt->have_exception || |
75ee23b3 SC |
7468 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
7469 | kvm_rip_write(vcpu, ctxt->eip); | |
384dea1c | 7470 | if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) |
120c2c4f | 7471 | r = kvm_vcpu_do_singlestep(vcpu); |
afaf0b2f SC |
7472 | if (kvm_x86_ops.update_emulated_instruction) |
7473 | kvm_x86_ops.update_emulated_instruction(vcpu); | |
38827dbd | 7474 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 7475 | } |
6addfc42 PB |
7476 | |
7477 | /* | |
7478 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
7479 | * do nothing, and it will be requested again as soon as | |
7480 | * the shadow expires. But we still need to check here, | |
7481 | * because POPF has no interrupt shadow. | |
7482 | */ | |
7483 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
7484 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
7485 | } else |
7486 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
7487 | |
7488 | return r; | |
de7d789a | 7489 | } |
c60658d1 SC |
7490 | |
7491 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
7492 | { | |
7493 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
7494 | } | |
7495 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
7496 | ||
7497 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
7498 | void *insn, int insn_len) | |
7499 | { | |
7500 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
7501 | } | |
7502 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 7503 | |
8764ed55 SC |
7504 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
7505 | { | |
7506 | vcpu->arch.pio.count = 0; | |
7507 | return 1; | |
7508 | } | |
7509 | ||
45def77e SC |
7510 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
7511 | { | |
7512 | vcpu->arch.pio.count = 0; | |
7513 | ||
7514 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
7515 | return 1; | |
7516 | ||
7517 | return kvm_skip_emulated_instruction(vcpu); | |
7518 | } | |
7519 | ||
dca7f128 SC |
7520 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
7521 | unsigned short port) | |
de7d789a | 7522 | { |
de3cd117 | 7523 | unsigned long val = kvm_rax_read(vcpu); |
2e3bb4d8 SC |
7524 | int ret = emulator_pio_out(vcpu, size, port, &val, 1); |
7525 | ||
8764ed55 SC |
7526 | if (ret) |
7527 | return ret; | |
45def77e | 7528 | |
8764ed55 SC |
7529 | /* |
7530 | * Workaround userspace that relies on old KVM behavior of %rip being | |
7531 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
7532 | */ | |
7533 | if (port == 0x7e && | |
7534 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
7535 | vcpu->arch.complete_userspace_io = | |
7536 | complete_fast_pio_out_port_0x7e; | |
7537 | kvm_skip_emulated_instruction(vcpu); | |
7538 | } else { | |
45def77e SC |
7539 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
7540 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
7541 | } | |
8764ed55 | 7542 | return 0; |
de7d789a | 7543 | } |
de7d789a | 7544 | |
8370c3d0 TL |
7545 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
7546 | { | |
7547 | unsigned long val; | |
7548 | ||
7549 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
7550 | BUG_ON(vcpu->arch.pio.count != 1); | |
7551 | ||
45def77e SC |
7552 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
7553 | vcpu->arch.pio.count = 0; | |
7554 | return 1; | |
7555 | } | |
7556 | ||
8370c3d0 | 7557 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 7558 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
7559 | |
7560 | /* | |
2e3bb4d8 | 7561 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform |
8370c3d0 TL |
7562 | * the copy and tracing |
7563 | */ | |
2e3bb4d8 | 7564 | emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); |
de3cd117 | 7565 | kvm_rax_write(vcpu, val); |
8370c3d0 | 7566 | |
45def77e | 7567 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
7568 | } |
7569 | ||
dca7f128 SC |
7570 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
7571 | unsigned short port) | |
8370c3d0 TL |
7572 | { |
7573 | unsigned long val; | |
7574 | int ret; | |
7575 | ||
7576 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 7577 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 7578 | |
2e3bb4d8 | 7579 | ret = emulator_pio_in(vcpu, size, port, &val, 1); |
8370c3d0 | 7580 | if (ret) { |
de3cd117 | 7581 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
7582 | return ret; |
7583 | } | |
7584 | ||
45def77e | 7585 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
7586 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
7587 | ||
7588 | return 0; | |
7589 | } | |
dca7f128 SC |
7590 | |
7591 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
7592 | { | |
45def77e | 7593 | int ret; |
dca7f128 | 7594 | |
dca7f128 | 7595 | if (in) |
45def77e | 7596 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 7597 | else |
45def77e SC |
7598 | ret = kvm_fast_pio_out(vcpu, size, port); |
7599 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
7600 | } |
7601 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 7602 | |
251a5fd6 | 7603 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 7604 | { |
0a3aee0d | 7605 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 7606 | return 0; |
8cfdc000 ZA |
7607 | } |
7608 | ||
7609 | static void tsc_khz_changed(void *data) | |
c8076604 | 7610 | { |
8cfdc000 ZA |
7611 | struct cpufreq_freqs *freq = data; |
7612 | unsigned long khz = 0; | |
7613 | ||
7614 | if (data) | |
7615 | khz = freq->new; | |
7616 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
7617 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
7618 | if (!khz) | |
7619 | khz = tsc_khz; | |
0a3aee0d | 7620 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
7621 | } |
7622 | ||
5fa4ec9c | 7623 | #ifdef CONFIG_X86_64 |
0092e434 VK |
7624 | static void kvm_hyperv_tsc_notifier(void) |
7625 | { | |
0092e434 VK |
7626 | struct kvm *kvm; |
7627 | struct kvm_vcpu *vcpu; | |
7628 | int cpu; | |
7629 | ||
0d9ce162 | 7630 | mutex_lock(&kvm_lock); |
0092e434 VK |
7631 | list_for_each_entry(kvm, &vm_list, vm_list) |
7632 | kvm_make_mclock_inprogress_request(kvm); | |
7633 | ||
7634 | hyperv_stop_tsc_emulation(); | |
7635 | ||
7636 | /* TSC frequency always matches when on Hyper-V */ | |
7637 | for_each_present_cpu(cpu) | |
7638 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
7639 | kvm_max_guest_tsc_khz = tsc_khz; | |
7640 | ||
7641 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
7642 | struct kvm_arch *ka = &kvm->arch; | |
7643 | ||
7644 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
7645 | ||
7646 | pvclock_update_vm_gtod_copy(kvm); | |
7647 | ||
7648 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
7649 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
7650 | ||
7651 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
7652 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); | |
7653 | ||
7654 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
7655 | } | |
0d9ce162 | 7656 | mutex_unlock(&kvm_lock); |
0092e434 | 7657 | } |
5fa4ec9c | 7658 | #endif |
0092e434 | 7659 | |
df24014a | 7660 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 7661 | { |
c8076604 GH |
7662 | struct kvm *kvm; |
7663 | struct kvm_vcpu *vcpu; | |
7664 | int i, send_ipi = 0; | |
7665 | ||
8cfdc000 ZA |
7666 | /* |
7667 | * We allow guests to temporarily run on slowing clocks, | |
7668 | * provided we notify them after, or to run on accelerating | |
7669 | * clocks, provided we notify them before. Thus time never | |
7670 | * goes backwards. | |
7671 | * | |
7672 | * However, we have a problem. We can't atomically update | |
7673 | * the frequency of a given CPU from this function; it is | |
7674 | * merely a notifier, which can be called from any CPU. | |
7675 | * Changing the TSC frequency at arbitrary points in time | |
7676 | * requires a recomputation of local variables related to | |
7677 | * the TSC for each VCPU. We must flag these local variables | |
7678 | * to be updated and be sure the update takes place with the | |
7679 | * new frequency before any guests proceed. | |
7680 | * | |
7681 | * Unfortunately, the combination of hotplug CPU and frequency | |
7682 | * change creates an intractable locking scenario; the order | |
7683 | * of when these callouts happen is undefined with respect to | |
7684 | * CPU hotplug, and they can race with each other. As such, | |
7685 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
7686 | * undefined; you can actually have a CPU frequency change take | |
7687 | * place in between the computation of X and the setting of the | |
7688 | * variable. To protect against this problem, all updates of | |
7689 | * the per_cpu tsc_khz variable are done in an interrupt | |
7690 | * protected IPI, and all callers wishing to update the value | |
7691 | * must wait for a synchronous IPI to complete (which is trivial | |
7692 | * if the caller is on the CPU already). This establishes the | |
7693 | * necessary total order on variable updates. | |
7694 | * | |
7695 | * Note that because a guest time update may take place | |
7696 | * anytime after the setting of the VCPU's request bit, the | |
7697 | * correct TSC value must be set before the request. However, | |
7698 | * to ensure the update actually makes it to any guest which | |
7699 | * starts running in hardware virtualization between the set | |
7700 | * and the acquisition of the spinlock, we must also ping the | |
7701 | * CPU after setting the request bit. | |
7702 | * | |
7703 | */ | |
7704 | ||
df24014a | 7705 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 7706 | |
0d9ce162 | 7707 | mutex_lock(&kvm_lock); |
c8076604 | 7708 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 7709 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 7710 | if (vcpu->cpu != cpu) |
c8076604 | 7711 | continue; |
c285545f | 7712 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 7713 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 7714 | send_ipi = 1; |
c8076604 GH |
7715 | } |
7716 | } | |
0d9ce162 | 7717 | mutex_unlock(&kvm_lock); |
c8076604 GH |
7718 | |
7719 | if (freq->old < freq->new && send_ipi) { | |
7720 | /* | |
7721 | * We upscale the frequency. Must make the guest | |
7722 | * doesn't see old kvmclock values while running with | |
7723 | * the new frequency, otherwise we risk the guest sees | |
7724 | * time go backwards. | |
7725 | * | |
7726 | * In case we update the frequency for another cpu | |
7727 | * (which might be in guest context) send an interrupt | |
7728 | * to kick the cpu out of guest context. Next time | |
7729 | * guest context is entered kvmclock will be updated, | |
7730 | * so the guest will not see stale values. | |
7731 | */ | |
df24014a | 7732 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 7733 | } |
df24014a VK |
7734 | } |
7735 | ||
7736 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
7737 | void *data) | |
7738 | { | |
7739 | struct cpufreq_freqs *freq = data; | |
7740 | int cpu; | |
7741 | ||
7742 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
7743 | return 0; | |
7744 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
7745 | return 0; | |
7746 | ||
7747 | for_each_cpu(cpu, freq->policy->cpus) | |
7748 | __kvmclock_cpufreq_notifier(freq, cpu); | |
7749 | ||
c8076604 GH |
7750 | return 0; |
7751 | } | |
7752 | ||
7753 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
7754 | .notifier_call = kvmclock_cpufreq_notifier |
7755 | }; | |
7756 | ||
251a5fd6 | 7757 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 7758 | { |
251a5fd6 SAS |
7759 | tsc_khz_changed(NULL); |
7760 | return 0; | |
8cfdc000 ZA |
7761 | } |
7762 | ||
b820cc0c ZA |
7763 | static void kvm_timer_init(void) |
7764 | { | |
c285545f | 7765 | max_tsc_khz = tsc_khz; |
460dd42e | 7766 | |
b820cc0c | 7767 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f | 7768 | #ifdef CONFIG_CPU_FREQ |
aaec7c03 | 7769 | struct cpufreq_policy *policy; |
758f588d BP |
7770 | int cpu; |
7771 | ||
3e26f230 | 7772 | cpu = get_cpu(); |
aaec7c03 | 7773 | policy = cpufreq_cpu_get(cpu); |
9a11997e WL |
7774 | if (policy) { |
7775 | if (policy->cpuinfo.max_freq) | |
7776 | max_tsc_khz = policy->cpuinfo.max_freq; | |
7777 | cpufreq_cpu_put(policy); | |
7778 | } | |
3e26f230 | 7779 | put_cpu(); |
c285545f | 7780 | #endif |
b820cc0c ZA |
7781 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
7782 | CPUFREQ_TRANSITION_NOTIFIER); | |
7783 | } | |
460dd42e | 7784 | |
73c1b41e | 7785 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 7786 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
7787 | } |
7788 | ||
dd60d217 AK |
7789 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
7790 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 7791 | |
f5132b01 | 7792 | int kvm_is_in_guest(void) |
ff9d07a0 | 7793 | { |
086c9855 | 7794 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
7795 | } |
7796 | ||
7797 | static int kvm_is_user_mode(void) | |
7798 | { | |
7799 | int user_mode = 3; | |
dcf46b94 | 7800 | |
086c9855 | 7801 | if (__this_cpu_read(current_vcpu)) |
afaf0b2f | 7802 | user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu)); |
dcf46b94 | 7803 | |
ff9d07a0 ZY |
7804 | return user_mode != 0; |
7805 | } | |
7806 | ||
7807 | static unsigned long kvm_get_guest_ip(void) | |
7808 | { | |
7809 | unsigned long ip = 0; | |
dcf46b94 | 7810 | |
086c9855 AS |
7811 | if (__this_cpu_read(current_vcpu)) |
7812 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 7813 | |
ff9d07a0 ZY |
7814 | return ip; |
7815 | } | |
7816 | ||
8479e04e LK |
7817 | static void kvm_handle_intel_pt_intr(void) |
7818 | { | |
7819 | struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); | |
7820 | ||
7821 | kvm_make_request(KVM_REQ_PMI, vcpu); | |
7822 | __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, | |
7823 | (unsigned long *)&vcpu->arch.pmu.global_status); | |
7824 | } | |
7825 | ||
ff9d07a0 ZY |
7826 | static struct perf_guest_info_callbacks kvm_guest_cbs = { |
7827 | .is_in_guest = kvm_is_in_guest, | |
7828 | .is_user_mode = kvm_is_user_mode, | |
7829 | .get_guest_ip = kvm_get_guest_ip, | |
8479e04e | 7830 | .handle_intel_pt_intr = kvm_handle_intel_pt_intr, |
ff9d07a0 ZY |
7831 | }; |
7832 | ||
16e8d74d MT |
7833 | #ifdef CONFIG_X86_64 |
7834 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
7835 | { | |
d828199e MT |
7836 | struct kvm *kvm; |
7837 | ||
7838 | struct kvm_vcpu *vcpu; | |
7839 | int i; | |
7840 | ||
0d9ce162 | 7841 | mutex_lock(&kvm_lock); |
d828199e MT |
7842 | list_for_each_entry(kvm, &vm_list, vm_list) |
7843 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 7844 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 7845 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 7846 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
7847 | } |
7848 | ||
7849 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
7850 | ||
7851 | /* | |
7852 | * Notification about pvclock gtod data update. | |
7853 | */ | |
7854 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
7855 | void *priv) | |
7856 | { | |
7857 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
7858 | struct timekeeper *tk = priv; | |
7859 | ||
7860 | update_pvclock_gtod(tk); | |
7861 | ||
7862 | /* disable master clock if host does not trust, or does not | |
b0c39dc6 | 7863 | * use, TSC based clocksource. |
16e8d74d | 7864 | */ |
b0c39dc6 | 7865 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d MT |
7866 | atomic_read(&kvm_guest_has_master_clock) != 0) |
7867 | queue_work(system_long_wq, &pvclock_gtod_work); | |
7868 | ||
7869 | return 0; | |
7870 | } | |
7871 | ||
7872 | static struct notifier_block pvclock_gtod_notifier = { | |
7873 | .notifier_call = pvclock_gtod_notify, | |
7874 | }; | |
7875 | #endif | |
7876 | ||
f8c16bba | 7877 | int kvm_arch_init(void *opaque) |
043405e1 | 7878 | { |
d008dfdb | 7879 | struct kvm_x86_init_ops *ops = opaque; |
b820cc0c | 7880 | int r; |
f8c16bba | 7881 | |
afaf0b2f | 7882 | if (kvm_x86_ops.hardware_enable) { |
f8c16bba | 7883 | printk(KERN_ERR "kvm: already loaded the other module\n"); |
56c6d28a ZX |
7884 | r = -EEXIST; |
7885 | goto out; | |
f8c16bba ZX |
7886 | } |
7887 | ||
7888 | if (!ops->cpu_has_kvm_support()) { | |
ef935c25 | 7889 | pr_err_ratelimited("kvm: no hardware support\n"); |
56c6d28a ZX |
7890 | r = -EOPNOTSUPP; |
7891 | goto out; | |
f8c16bba ZX |
7892 | } |
7893 | if (ops->disabled_by_bios()) { | |
e150c0d6 | 7894 | pr_warn_ratelimited("kvm: disabled by bios\n"); |
56c6d28a ZX |
7895 | r = -EOPNOTSUPP; |
7896 | goto out; | |
f8c16bba ZX |
7897 | } |
7898 | ||
b666a4b6 MO |
7899 | /* |
7900 | * KVM explicitly assumes that the guest has an FPU and | |
7901 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
7902 | * vCPU's FPU state as a fxregs_state struct. | |
7903 | */ | |
7904 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
7905 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
7906 | r = -EOPNOTSUPP; | |
7907 | goto out; | |
7908 | } | |
7909 | ||
013f6a5d | 7910 | r = -ENOMEM; |
ed8e4812 | 7911 | x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), |
b666a4b6 MO |
7912 | __alignof__(struct fpu), SLAB_ACCOUNT, |
7913 | NULL); | |
7914 | if (!x86_fpu_cache) { | |
7915 | printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); | |
7916 | goto out; | |
7917 | } | |
7918 | ||
c9b8b07c SC |
7919 | x86_emulator_cache = kvm_alloc_emulator_cache(); |
7920 | if (!x86_emulator_cache) { | |
7921 | pr_err("kvm: failed to allocate cache for x86 emulator\n"); | |
7922 | goto out_free_x86_fpu_cache; | |
7923 | } | |
7924 | ||
7e34fbd0 SC |
7925 | user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); |
7926 | if (!user_return_msrs) { | |
7927 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); | |
c9b8b07c | 7928 | goto out_free_x86_emulator_cache; |
013f6a5d MT |
7929 | } |
7930 | ||
97db56ce AK |
7931 | r = kvm_mmu_module_init(); |
7932 | if (r) | |
013f6a5d | 7933 | goto out_free_percpu; |
97db56ce | 7934 | |
7b52345e | 7935 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
ffb128c8 | 7936 | PT_DIRTY_MASK, PT64_NX_MASK, 0, |
d0ec49d4 | 7937 | PT_PRESENT_MASK, 0, sme_me_mask); |
b820cc0c | 7938 | kvm_timer_init(); |
c8076604 | 7939 | |
ff9d07a0 ZY |
7940 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
7941 | ||
cfc48181 | 7942 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
2acf923e | 7943 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
cfc48181 SC |
7944 | supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; |
7945 | } | |
2acf923e | 7946 | |
c5cc421b | 7947 | kvm_lapic_init(); |
0c5f81da WL |
7948 | if (pi_inject_timer == -1) |
7949 | pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); | |
16e8d74d MT |
7950 | #ifdef CONFIG_X86_64 |
7951 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 7952 | |
5fa4ec9c | 7953 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 7954 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
7955 | #endif |
7956 | ||
f8c16bba | 7957 | return 0; |
56c6d28a | 7958 | |
013f6a5d | 7959 | out_free_percpu: |
7e34fbd0 | 7960 | free_percpu(user_return_msrs); |
c9b8b07c SC |
7961 | out_free_x86_emulator_cache: |
7962 | kmem_cache_destroy(x86_emulator_cache); | |
b666a4b6 MO |
7963 | out_free_x86_fpu_cache: |
7964 | kmem_cache_destroy(x86_fpu_cache); | |
56c6d28a | 7965 | out: |
56c6d28a | 7966 | return r; |
043405e1 | 7967 | } |
8776e519 | 7968 | |
f8c16bba ZX |
7969 | void kvm_arch_exit(void) |
7970 | { | |
0092e434 | 7971 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 7972 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
7973 | clear_hv_tscchange_cb(); |
7974 | #endif | |
cef84c30 | 7975 | kvm_lapic_exit(); |
ff9d07a0 ZY |
7976 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
7977 | ||
888d256e JK |
7978 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
7979 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
7980 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 7981 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
7982 | #ifdef CONFIG_X86_64 |
7983 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
7984 | #endif | |
afaf0b2f | 7985 | kvm_x86_ops.hardware_enable = NULL; |
56c6d28a | 7986 | kvm_mmu_module_exit(); |
7e34fbd0 | 7987 | free_percpu(user_return_msrs); |
b666a4b6 | 7988 | kmem_cache_destroy(x86_fpu_cache); |
56c6d28a | 7989 | } |
f8c16bba | 7990 | |
872f36eb | 7991 | static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) |
8776e519 HB |
7992 | { |
7993 | ++vcpu->stat.halt_exits; | |
35754c98 | 7994 | if (lapic_in_kernel(vcpu)) { |
647daca2 | 7995 | vcpu->arch.mp_state = state; |
8776e519 HB |
7996 | return 1; |
7997 | } else { | |
647daca2 | 7998 | vcpu->run->exit_reason = reason; |
8776e519 HB |
7999 | return 0; |
8000 | } | |
8001 | } | |
647daca2 TL |
8002 | |
8003 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) | |
8004 | { | |
8005 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); | |
8006 | } | |
5cb56059 JS |
8007 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
8008 | ||
8009 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
8010 | { | |
6affcbed KH |
8011 | int ret = kvm_skip_emulated_instruction(vcpu); |
8012 | /* | |
8013 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
8014 | * KVM_EXIT_DEBUG here. | |
8015 | */ | |
8016 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 8017 | } |
8776e519 HB |
8018 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
8019 | ||
647daca2 TL |
8020 | int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) |
8021 | { | |
8022 | int ret = kvm_skip_emulated_instruction(vcpu); | |
8023 | ||
8024 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; | |
8025 | } | |
8026 | EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); | |
8027 | ||
8ef81a9a | 8028 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8029 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
8030 | unsigned long clock_type) | |
8031 | { | |
8032 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 8033 | struct timespec64 ts; |
80fbd89c | 8034 | u64 cycle; |
55dd00a7 MT |
8035 | int ret; |
8036 | ||
8037 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
8038 | return -KVM_EOPNOTSUPP; | |
8039 | ||
8040 | if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) | |
8041 | return -KVM_EOPNOTSUPP; | |
8042 | ||
8043 | clock_pairing.sec = ts.tv_sec; | |
8044 | clock_pairing.nsec = ts.tv_nsec; | |
8045 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
8046 | clock_pairing.flags = 0; | |
bcbfbd8e | 8047 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
8048 | |
8049 | ret = 0; | |
8050 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
8051 | sizeof(struct kvm_clock_pairing))) | |
8052 | ret = -KVM_EFAULT; | |
8053 | ||
8054 | return ret; | |
8055 | } | |
8ef81a9a | 8056 | #endif |
55dd00a7 | 8057 | |
6aef266c SV |
8058 | /* |
8059 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
8060 | * | |
8061 | * @apicid - apicid of vcpu to be kicked. | |
8062 | */ | |
8063 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
8064 | { | |
24d2166b | 8065 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 8066 | |
150a84fe | 8067 | lapic_irq.shorthand = APIC_DEST_NOSHORT; |
c96001c5 | 8068 | lapic_irq.dest_mode = APIC_DEST_PHYSICAL; |
ebd28fcb | 8069 | lapic_irq.level = 0; |
24d2166b | 8070 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 8071 | lapic_irq.msi_redir_hint = false; |
6aef266c | 8072 | |
24d2166b | 8073 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 8074 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
8075 | } |
8076 | ||
4e19c36f SS |
8077 | bool kvm_apicv_activated(struct kvm *kvm) |
8078 | { | |
8079 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
8080 | } | |
8081 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
8082 | ||
8083 | void kvm_apicv_init(struct kvm *kvm, bool enable) | |
8084 | { | |
8085 | if (enable) | |
8086 | clear_bit(APICV_INHIBIT_REASON_DISABLE, | |
8087 | &kvm->arch.apicv_inhibit_reasons); | |
8088 | else | |
8089 | set_bit(APICV_INHIBIT_REASON_DISABLE, | |
8090 | &kvm->arch.apicv_inhibit_reasons); | |
8091 | } | |
8092 | EXPORT_SYMBOL_GPL(kvm_apicv_init); | |
8093 | ||
71506297 WL |
8094 | static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) |
8095 | { | |
8096 | struct kvm_vcpu *target = NULL; | |
8097 | struct kvm_apic_map *map; | |
8098 | ||
8099 | rcu_read_lock(); | |
8100 | map = rcu_dereference(kvm->arch.apic_map); | |
8101 | ||
8102 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
8103 | target = map->phys_map[dest_id]->vcpu; | |
8104 | ||
8105 | rcu_read_unlock(); | |
8106 | ||
266e85a5 | 8107 | if (target && READ_ONCE(target->ready)) |
71506297 WL |
8108 | kvm_vcpu_yield_to(target); |
8109 | } | |
8110 | ||
8776e519 HB |
8111 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
8112 | { | |
8113 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 8114 | int op_64_bit; |
8776e519 | 8115 | |
696ca779 RK |
8116 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
8117 | return kvm_hv_hypercall(vcpu); | |
55cd8e5a | 8118 | |
de3cd117 SC |
8119 | nr = kvm_rax_read(vcpu); |
8120 | a0 = kvm_rbx_read(vcpu); | |
8121 | a1 = kvm_rcx_read(vcpu); | |
8122 | a2 = kvm_rdx_read(vcpu); | |
8123 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 8124 | |
229456fc | 8125 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 8126 | |
a449c7aa NA |
8127 | op_64_bit = is_64_bit_mode(vcpu); |
8128 | if (!op_64_bit) { | |
8776e519 HB |
8129 | nr &= 0xFFFFFFFF; |
8130 | a0 &= 0xFFFFFFFF; | |
8131 | a1 &= 0xFFFFFFFF; | |
8132 | a2 &= 0xFFFFFFFF; | |
8133 | a3 &= 0xFFFFFFFF; | |
8134 | } | |
8135 | ||
afaf0b2f | 8136 | if (kvm_x86_ops.get_cpl(vcpu) != 0) { |
07708c4a | 8137 | ret = -KVM_EPERM; |
696ca779 | 8138 | goto out; |
07708c4a JK |
8139 | } |
8140 | ||
66570e96 OU |
8141 | ret = -KVM_ENOSYS; |
8142 | ||
8776e519 | 8143 | switch (nr) { |
b93463aa AK |
8144 | case KVM_HC_VAPIC_POLL_IRQ: |
8145 | ret = 0; | |
8146 | break; | |
6aef266c | 8147 | case KVM_HC_KICK_CPU: |
66570e96 OU |
8148 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) |
8149 | break; | |
8150 | ||
6aef266c | 8151 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); |
266e85a5 | 8152 | kvm_sched_yield(vcpu->kvm, a1); |
6aef266c SV |
8153 | ret = 0; |
8154 | break; | |
8ef81a9a | 8155 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8156 | case KVM_HC_CLOCK_PAIRING: |
8157 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
8158 | break; | |
1ed199a4 | 8159 | #endif |
4180bf1b | 8160 | case KVM_HC_SEND_IPI: |
66570e96 OU |
8161 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) |
8162 | break; | |
8163 | ||
4180bf1b WL |
8164 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); |
8165 | break; | |
71506297 | 8166 | case KVM_HC_SCHED_YIELD: |
66570e96 OU |
8167 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) |
8168 | break; | |
8169 | ||
71506297 WL |
8170 | kvm_sched_yield(vcpu->kvm, a0); |
8171 | ret = 0; | |
8172 | break; | |
8776e519 HB |
8173 | default: |
8174 | ret = -KVM_ENOSYS; | |
8175 | break; | |
8176 | } | |
696ca779 | 8177 | out: |
a449c7aa NA |
8178 | if (!op_64_bit) |
8179 | ret = (u32)ret; | |
de3cd117 | 8180 | kvm_rax_write(vcpu, ret); |
6356ee0c | 8181 | |
f11c3a8d | 8182 | ++vcpu->stat.hypercalls; |
6356ee0c | 8183 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
8184 | } |
8185 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
8186 | ||
b6785def | 8187 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 8188 | { |
d6aa1000 | 8189 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 8190 | char instruction[3]; |
5fdbf976 | 8191 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 8192 | |
afaf0b2f | 8193 | kvm_x86_ops.patch_hypercall(vcpu, instruction); |
8776e519 | 8194 | |
ce2e852e DV |
8195 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
8196 | &ctxt->exception); | |
8776e519 HB |
8197 | } |
8198 | ||
851ba692 | 8199 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8200 | { |
782d422b MG |
8201 | return vcpu->run->request_interrupt_window && |
8202 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
8203 | } |
8204 | ||
851ba692 | 8205 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8206 | { |
851ba692 AK |
8207 | struct kvm_run *kvm_run = vcpu->run; |
8208 | ||
f1c6366e TL |
8209 | /* |
8210 | * if_flag is obsolete and useless, so do not bother | |
8211 | * setting it for SEV-ES guests. Userspace can just | |
8212 | * use kvm_run->ready_for_interrupt_injection. | |
8213 | */ | |
8214 | kvm_run->if_flag = !vcpu->arch.guest_state_protected | |
8215 | && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; | |
8216 | ||
f077825a | 8217 | kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; |
2d3ad1f4 | 8218 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 8219 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
8220 | kvm_run->ready_for_interrupt_injection = |
8221 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 8222 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
b6c7a5dc HB |
8223 | } |
8224 | ||
95ba8273 GN |
8225 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
8226 | { | |
8227 | int max_irr, tpr; | |
8228 | ||
afaf0b2f | 8229 | if (!kvm_x86_ops.update_cr8_intercept) |
95ba8273 GN |
8230 | return; |
8231 | ||
bce87cce | 8232 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
8233 | return; |
8234 | ||
d62caabb AS |
8235 | if (vcpu->arch.apicv_active) |
8236 | return; | |
8237 | ||
8db3baa2 GN |
8238 | if (!vcpu->arch.apic->vapic_addr) |
8239 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
8240 | else | |
8241 | max_irr = -1; | |
95ba8273 GN |
8242 | |
8243 | if (max_irr != -1) | |
8244 | max_irr >>= 4; | |
8245 | ||
8246 | tpr = kvm_lapic_get_cr8(vcpu); | |
8247 | ||
afaf0b2f | 8248 | kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr); |
95ba8273 GN |
8249 | } |
8250 | ||
c9d40913 | 8251 | static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) |
95ba8273 | 8252 | { |
b6b8a145 | 8253 | int r; |
c6b22f59 | 8254 | bool can_inject = true; |
b6b8a145 | 8255 | |
95ba8273 | 8256 | /* try to reinject previous events if any */ |
664f8e26 | 8257 | |
c6b22f59 | 8258 | if (vcpu->arch.exception.injected) { |
afaf0b2f | 8259 | kvm_x86_ops.queue_exception(vcpu); |
c6b22f59 PB |
8260 | can_inject = false; |
8261 | } | |
664f8e26 | 8262 | /* |
a042c26f LA |
8263 | * Do not inject an NMI or interrupt if there is a pending |
8264 | * exception. Exceptions and interrupts are recognized at | |
8265 | * instruction boundaries, i.e. the start of an instruction. | |
8266 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
8267 | * NMIs and interrupts, i.e. traps are recognized before an | |
8268 | * NMI/interrupt that's pending on the same instruction. | |
8269 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
8270 | * priority, but are only generated (pended) during instruction | |
8271 | * execution, i.e. a pending fault-like exception means the | |
8272 | * fault occurred on the *previous* instruction and must be | |
8273 | * serviced prior to recognizing any new events in order to | |
8274 | * fully complete the previous instruction. | |
664f8e26 | 8275 | */ |
1a680e35 | 8276 | else if (!vcpu->arch.exception.pending) { |
c6b22f59 | 8277 | if (vcpu->arch.nmi_injected) { |
afaf0b2f | 8278 | kvm_x86_ops.set_nmi(vcpu); |
c6b22f59 PB |
8279 | can_inject = false; |
8280 | } else if (vcpu->arch.interrupt.injected) { | |
afaf0b2f | 8281 | kvm_x86_ops.set_irq(vcpu); |
c6b22f59 PB |
8282 | can_inject = false; |
8283 | } | |
664f8e26 WL |
8284 | } |
8285 | ||
3b82b8d7 SC |
8286 | WARN_ON_ONCE(vcpu->arch.exception.injected && |
8287 | vcpu->arch.exception.pending); | |
8288 | ||
1a680e35 LA |
8289 | /* |
8290 | * Call check_nested_events() even if we reinjected a previous event | |
8291 | * in order for caller to determine if it should require immediate-exit | |
8292 | * from L2 to L1 due to pending L1 events which require exit | |
8293 | * from L2 to L1. | |
8294 | */ | |
56083bdf | 8295 | if (is_guest_mode(vcpu)) { |
33b22172 | 8296 | r = kvm_x86_ops.nested_ops->check_events(vcpu); |
c9d40913 PB |
8297 | if (r < 0) |
8298 | goto busy; | |
664f8e26 WL |
8299 | } |
8300 | ||
8301 | /* try to inject new event if pending */ | |
b59bb7bd | 8302 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
8303 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
8304 | vcpu->arch.exception.has_error_code, | |
8305 | vcpu->arch.exception.error_code); | |
d6e8c854 | 8306 | |
664f8e26 WL |
8307 | vcpu->arch.exception.pending = false; |
8308 | vcpu->arch.exception.injected = true; | |
8309 | ||
d6e8c854 NA |
8310 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
8311 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
8312 | X86_EFLAGS_RF); | |
8313 | ||
f10c729f | 8314 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
f10c729f JM |
8315 | kvm_deliver_exception_payload(vcpu); |
8316 | if (vcpu->arch.dr7 & DR7_GD) { | |
8317 | vcpu->arch.dr7 &= ~DR7_GD; | |
8318 | kvm_update_dr7(vcpu); | |
8319 | } | |
6bdf0662 NA |
8320 | } |
8321 | ||
afaf0b2f | 8322 | kvm_x86_ops.queue_exception(vcpu); |
c6b22f59 | 8323 | can_inject = false; |
1a680e35 LA |
8324 | } |
8325 | ||
c9d40913 PB |
8326 | /* |
8327 | * Finally, inject interrupt events. If an event cannot be injected | |
8328 | * due to architectural conditions (e.g. IF=0) a window-open exit | |
8329 | * will re-request KVM_REQ_EVENT. Sometimes however an event is pending | |
8330 | * and can architecturally be injected, but we cannot do it right now: | |
8331 | * an interrupt could have arrived just now and we have to inject it | |
8332 | * as a vmexit, or there could already an event in the queue, which is | |
8333 | * indicated by can_inject. In that case we request an immediate exit | |
8334 | * in order to make progress and get back here for another iteration. | |
8335 | * The kvm_x86_ops hooks communicate this by returning -EBUSY. | |
8336 | */ | |
8337 | if (vcpu->arch.smi_pending) { | |
8338 | r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY; | |
8339 | if (r < 0) | |
8340 | goto busy; | |
8341 | if (r) { | |
8342 | vcpu->arch.smi_pending = false; | |
8343 | ++vcpu->arch.smi_count; | |
8344 | enter_smm(vcpu); | |
8345 | can_inject = false; | |
8346 | } else | |
8347 | kvm_x86_ops.enable_smi_window(vcpu); | |
8348 | } | |
8349 | ||
8350 | if (vcpu->arch.nmi_pending) { | |
8351 | r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY; | |
8352 | if (r < 0) | |
8353 | goto busy; | |
8354 | if (r) { | |
8355 | --vcpu->arch.nmi_pending; | |
8356 | vcpu->arch.nmi_injected = true; | |
8357 | kvm_x86_ops.set_nmi(vcpu); | |
8358 | can_inject = false; | |
8359 | WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0); | |
8360 | } | |
8361 | if (vcpu->arch.nmi_pending) | |
8362 | kvm_x86_ops.enable_nmi_window(vcpu); | |
8363 | } | |
1a680e35 | 8364 | |
c9d40913 PB |
8365 | if (kvm_cpu_has_injectable_intr(vcpu)) { |
8366 | r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY; | |
8367 | if (r < 0) | |
8368 | goto busy; | |
8369 | if (r) { | |
8370 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); | |
8371 | kvm_x86_ops.set_irq(vcpu); | |
8372 | WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0); | |
8373 | } | |
8374 | if (kvm_cpu_has_injectable_intr(vcpu)) | |
8375 | kvm_x86_ops.enable_irq_window(vcpu); | |
95ba8273 | 8376 | } |
ee2cd4b7 | 8377 | |
c9d40913 PB |
8378 | if (is_guest_mode(vcpu) && |
8379 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
8380 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
8381 | *req_immediate_exit = true; | |
8382 | ||
8383 | WARN_ON(vcpu->arch.exception.pending); | |
8384 | return; | |
8385 | ||
8386 | busy: | |
8387 | *req_immediate_exit = true; | |
8388 | return; | |
95ba8273 GN |
8389 | } |
8390 | ||
7460fb4a AK |
8391 | static void process_nmi(struct kvm_vcpu *vcpu) |
8392 | { | |
8393 | unsigned limit = 2; | |
8394 | ||
8395 | /* | |
8396 | * x86 is limited to one NMI running, and one NMI pending after it. | |
8397 | * If an NMI is already in progress, limit further NMIs to just one. | |
8398 | * Otherwise, allow two (and we'll inject the first one immediately). | |
8399 | */ | |
afaf0b2f | 8400 | if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) |
7460fb4a AK |
8401 | limit = 1; |
8402 | ||
8403 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
8404 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
8405 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8406 | } | |
8407 | ||
ee2cd4b7 | 8408 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
8409 | { |
8410 | u32 flags = 0; | |
8411 | flags |= seg->g << 23; | |
8412 | flags |= seg->db << 22; | |
8413 | flags |= seg->l << 21; | |
8414 | flags |= seg->avl << 20; | |
8415 | flags |= seg->present << 15; | |
8416 | flags |= seg->dpl << 13; | |
8417 | flags |= seg->s << 12; | |
8418 | flags |= seg->type << 8; | |
8419 | return flags; | |
8420 | } | |
8421 | ||
ee2cd4b7 | 8422 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
8423 | { |
8424 | struct kvm_segment seg; | |
8425 | int offset; | |
8426 | ||
8427 | kvm_get_segment(vcpu, &seg, n); | |
8428 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
8429 | ||
8430 | if (n < 3) | |
8431 | offset = 0x7f84 + n * 12; | |
8432 | else | |
8433 | offset = 0x7f2c + (n - 3) * 12; | |
8434 | ||
8435 | put_smstate(u32, buf, offset + 8, seg.base); | |
8436 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 8437 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
8438 | } |
8439 | ||
efbb288a | 8440 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 8441 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
8442 | { |
8443 | struct kvm_segment seg; | |
8444 | int offset; | |
8445 | u16 flags; | |
8446 | ||
8447 | kvm_get_segment(vcpu, &seg, n); | |
8448 | offset = 0x7e00 + n * 16; | |
8449 | ||
ee2cd4b7 | 8450 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
8451 | put_smstate(u16, buf, offset, seg.selector); |
8452 | put_smstate(u16, buf, offset + 2, flags); | |
8453 | put_smstate(u32, buf, offset + 4, seg.limit); | |
8454 | put_smstate(u64, buf, offset + 8, seg.base); | |
8455 | } | |
efbb288a | 8456 | #endif |
660a5d51 | 8457 | |
ee2cd4b7 | 8458 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
8459 | { |
8460 | struct desc_ptr dt; | |
8461 | struct kvm_segment seg; | |
8462 | unsigned long val; | |
8463 | int i; | |
8464 | ||
8465 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
8466 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
8467 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
8468 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
8469 | ||
8470 | for (i = 0; i < 8; i++) | |
8471 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); | |
8472 | ||
8473 | kvm_get_dr(vcpu, 6, &val); | |
8474 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
8475 | kvm_get_dr(vcpu, 7, &val); | |
8476 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
8477 | ||
8478 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
8479 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
8480 | put_smstate(u32, buf, 0x7f64, seg.base); | |
8481 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 8482 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
8483 | |
8484 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
8485 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
8486 | put_smstate(u32, buf, 0x7f80, seg.base); | |
8487 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 8488 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 | 8489 | |
afaf0b2f | 8490 | kvm_x86_ops.get_gdt(vcpu, &dt); |
660a5d51 PB |
8491 | put_smstate(u32, buf, 0x7f74, dt.address); |
8492 | put_smstate(u32, buf, 0x7f70, dt.size); | |
8493 | ||
afaf0b2f | 8494 | kvm_x86_ops.get_idt(vcpu, &dt); |
660a5d51 PB |
8495 | put_smstate(u32, buf, 0x7f58, dt.address); |
8496 | put_smstate(u32, buf, 0x7f54, dt.size); | |
8497 | ||
8498 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 8499 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
8500 | |
8501 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
8502 | ||
8503 | /* revision id */ | |
8504 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
8505 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
8506 | } | |
8507 | ||
b68f3cc7 | 8508 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 8509 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 8510 | { |
660a5d51 PB |
8511 | struct desc_ptr dt; |
8512 | struct kvm_segment seg; | |
8513 | unsigned long val; | |
8514 | int i; | |
8515 | ||
8516 | for (i = 0; i < 16; i++) | |
8517 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); | |
8518 | ||
8519 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
8520 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
8521 | ||
8522 | kvm_get_dr(vcpu, 6, &val); | |
8523 | put_smstate(u64, buf, 0x7f68, val); | |
8524 | kvm_get_dr(vcpu, 7, &val); | |
8525 | put_smstate(u64, buf, 0x7f60, val); | |
8526 | ||
8527 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
8528 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
8529 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
8530 | ||
8531 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
8532 | ||
8533 | /* revision id */ | |
8534 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
8535 | ||
8536 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
8537 | ||
8538 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
8539 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 8540 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
8541 | put_smstate(u32, buf, 0x7e94, seg.limit); |
8542 | put_smstate(u64, buf, 0x7e98, seg.base); | |
8543 | ||
afaf0b2f | 8544 | kvm_x86_ops.get_idt(vcpu, &dt); |
660a5d51 PB |
8545 | put_smstate(u32, buf, 0x7e84, dt.size); |
8546 | put_smstate(u64, buf, 0x7e88, dt.address); | |
8547 | ||
8548 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
8549 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 8550 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
8551 | put_smstate(u32, buf, 0x7e74, seg.limit); |
8552 | put_smstate(u64, buf, 0x7e78, seg.base); | |
8553 | ||
afaf0b2f | 8554 | kvm_x86_ops.get_gdt(vcpu, &dt); |
660a5d51 PB |
8555 | put_smstate(u32, buf, 0x7e64, dt.size); |
8556 | put_smstate(u64, buf, 0x7e68, dt.address); | |
8557 | ||
8558 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 8559 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 8560 | } |
b68f3cc7 | 8561 | #endif |
660a5d51 | 8562 | |
ee2cd4b7 | 8563 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 8564 | { |
660a5d51 | 8565 | struct kvm_segment cs, ds; |
18c3626e | 8566 | struct desc_ptr dt; |
660a5d51 PB |
8567 | char buf[512]; |
8568 | u32 cr0; | |
8569 | ||
660a5d51 | 8570 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); |
660a5d51 | 8571 | memset(buf, 0, 512); |
b68f3cc7 | 8572 | #ifdef CONFIG_X86_64 |
d6321d49 | 8573 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 8574 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 8575 | else |
b68f3cc7 | 8576 | #endif |
ee2cd4b7 | 8577 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 8578 | |
0234bf88 LP |
8579 | /* |
8580 | * Give pre_enter_smm() a chance to make ISA-specific changes to the | |
8581 | * vCPU state (e.g. leave guest mode) after we've saved the state into | |
8582 | * the SMM state-save area. | |
8583 | */ | |
afaf0b2f | 8584 | kvm_x86_ops.pre_enter_smm(vcpu, buf); |
0234bf88 LP |
8585 | |
8586 | vcpu->arch.hflags |= HF_SMM_MASK; | |
54bf36aa | 8587 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 | 8588 | |
afaf0b2f | 8589 | if (kvm_x86_ops.get_nmi_mask(vcpu)) |
660a5d51 PB |
8590 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; |
8591 | else | |
afaf0b2f | 8592 | kvm_x86_ops.set_nmi_mask(vcpu, true); |
660a5d51 PB |
8593 | |
8594 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
8595 | kvm_rip_write(vcpu, 0x8000); | |
8596 | ||
8597 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
afaf0b2f | 8598 | kvm_x86_ops.set_cr0(vcpu, cr0); |
660a5d51 PB |
8599 | vcpu->arch.cr0 = cr0; |
8600 | ||
afaf0b2f | 8601 | kvm_x86_ops.set_cr4(vcpu, 0); |
660a5d51 | 8602 | |
18c3626e PB |
8603 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
8604 | dt.address = dt.size = 0; | |
afaf0b2f | 8605 | kvm_x86_ops.set_idt(vcpu, &dt); |
18c3626e | 8606 | |
660a5d51 PB |
8607 | __kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
8608 | ||
8609 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
8610 | cs.base = vcpu->arch.smbase; | |
8611 | ||
8612 | ds.selector = 0; | |
8613 | ds.base = 0; | |
8614 | ||
8615 | cs.limit = ds.limit = 0xffffffff; | |
8616 | cs.type = ds.type = 0x3; | |
8617 | cs.dpl = ds.dpl = 0; | |
8618 | cs.db = ds.db = 0; | |
8619 | cs.s = ds.s = 1; | |
8620 | cs.l = ds.l = 0; | |
8621 | cs.g = ds.g = 1; | |
8622 | cs.avl = ds.avl = 0; | |
8623 | cs.present = ds.present = 1; | |
8624 | cs.unusable = ds.unusable = 0; | |
8625 | cs.padding = ds.padding = 0; | |
8626 | ||
8627 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
8628 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
8629 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
8630 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
8631 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
8632 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
8633 | ||
b68f3cc7 | 8634 | #ifdef CONFIG_X86_64 |
d6321d49 | 8635 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
afaf0b2f | 8636 | kvm_x86_ops.set_efer(vcpu, 0); |
b68f3cc7 | 8637 | #endif |
660a5d51 | 8638 | |
aedbaf4f | 8639 | kvm_update_cpuid_runtime(vcpu); |
660a5d51 | 8640 | kvm_mmu_reset_context(vcpu); |
64d60670 PB |
8641 | } |
8642 | ||
ee2cd4b7 | 8643 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
8644 | { |
8645 | vcpu->arch.smi_pending = true; | |
8646 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8647 | } | |
8648 | ||
7ee30bc1 NNL |
8649 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
8650 | unsigned long *vcpu_bitmap) | |
8651 | { | |
8652 | cpumask_var_t cpus; | |
7ee30bc1 NNL |
8653 | |
8654 | zalloc_cpumask_var(&cpus, GFP_ATOMIC); | |
8655 | ||
db5a95ec | 8656 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, |
54163a34 | 8657 | NULL, vcpu_bitmap, cpus); |
7ee30bc1 NNL |
8658 | |
8659 | free_cpumask_var(cpus); | |
8660 | } | |
8661 | ||
2860c4b1 PB |
8662 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
8663 | { | |
8664 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
8665 | } | |
8666 | ||
8df14af4 SS |
8667 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
8668 | { | |
8669 | if (!lapic_in_kernel(vcpu)) | |
8670 | return; | |
8671 | ||
8672 | vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); | |
8673 | kvm_apic_update_apicv(vcpu); | |
afaf0b2f | 8674 | kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu); |
8df14af4 SS |
8675 | } |
8676 | EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); | |
8677 | ||
8678 | /* | |
8679 | * NOTE: Do not hold any lock prior to calling this. | |
8680 | * | |
8681 | * In particular, kvm_request_apicv_update() expects kvm->srcu not to be | |
8682 | * locked, because it calls __x86_set_memory_region() which does | |
8683 | * synchronize_srcu(&kvm->srcu). | |
8684 | */ | |
8685 | void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) | |
8686 | { | |
7d611233 | 8687 | struct kvm_vcpu *except; |
8e205a6b PB |
8688 | unsigned long old, new, expected; |
8689 | ||
afaf0b2f SC |
8690 | if (!kvm_x86_ops.check_apicv_inhibit_reasons || |
8691 | !kvm_x86_ops.check_apicv_inhibit_reasons(bit)) | |
ef8efd7a SS |
8692 | return; |
8693 | ||
8e205a6b PB |
8694 | old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); |
8695 | do { | |
8696 | expected = new = old; | |
8697 | if (activate) | |
8698 | __clear_bit(bit, &new); | |
8699 | else | |
8700 | __set_bit(bit, &new); | |
8701 | if (new == old) | |
8702 | break; | |
8703 | old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); | |
8704 | } while (old != expected); | |
8705 | ||
8706 | if (!!old == !!new) | |
8707 | return; | |
8df14af4 | 8708 | |
24bbf74c | 8709 | trace_kvm_apicv_update_request(activate, bit); |
afaf0b2f SC |
8710 | if (kvm_x86_ops.pre_update_apicv_exec_ctrl) |
8711 | kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate); | |
7d611233 SS |
8712 | |
8713 | /* | |
8714 | * Sending request to update APICV for all other vcpus, | |
8715 | * while update the calling vcpu immediately instead of | |
8716 | * waiting for another #VMEXIT to handle the request. | |
8717 | */ | |
8718 | except = kvm_get_running_vcpu(); | |
8719 | kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE, | |
8720 | except); | |
8721 | if (except) | |
8722 | kvm_vcpu_update_apicv(except); | |
8df14af4 SS |
8723 | } |
8724 | EXPORT_SYMBOL_GPL(kvm_request_apicv_update); | |
8725 | ||
3d81bc7e | 8726 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 8727 | { |
dcbd3e49 | 8728 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 8729 | return; |
c7c9c56c | 8730 | |
6308630b | 8731 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 8732 | |
b053b2ae | 8733 | if (irqchip_split(vcpu->kvm)) |
6308630b | 8734 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 8735 | else { |
fa59cc00 | 8736 | if (vcpu->arch.apicv_active) |
afaf0b2f | 8737 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
e97f852f WL |
8738 | if (ioapic_in_kernel(vcpu->kvm)) |
8739 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 8740 | } |
e40ff1d6 LA |
8741 | |
8742 | if (is_guest_mode(vcpu)) | |
8743 | vcpu->arch.load_eoi_exitmap_pending = true; | |
8744 | else | |
8745 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
8746 | } | |
8747 | ||
8748 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
8749 | { | |
8750 | u64 eoi_exit_bitmap[4]; | |
8751 | ||
8752 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
8753 | return; | |
8754 | ||
5c919412 AS |
8755 | bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, |
8756 | vcpu_to_synic(vcpu)->vec_bitmap, 256); | |
afaf0b2f | 8757 | kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap); |
c7c9c56c YZ |
8758 | } |
8759 | ||
e649b3f0 ET |
8760 | void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
8761 | unsigned long start, unsigned long end) | |
b1394e74 RK |
8762 | { |
8763 | unsigned long apic_address; | |
8764 | ||
8765 | /* | |
8766 | * The physical address of apic access page is stored in the VMCS. | |
8767 | * Update it when it becomes invalid. | |
8768 | */ | |
8769 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
8770 | if (start <= apic_address && apic_address < end) | |
8771 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
8772 | } | |
8773 | ||
4256f43f TC |
8774 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
8775 | { | |
35754c98 | 8776 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
8777 | return; |
8778 | ||
afaf0b2f | 8779 | if (!kvm_x86_ops.set_apic_access_page_addr) |
4256f43f TC |
8780 | return; |
8781 | ||
a4148b7c | 8782 | kvm_x86_ops.set_apic_access_page_addr(vcpu); |
4256f43f | 8783 | } |
4256f43f | 8784 | |
d264ee0c SC |
8785 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
8786 | { | |
8787 | smp_send_reschedule(vcpu->cpu); | |
8788 | } | |
8789 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
8790 | ||
9357d939 | 8791 | /* |
362c698f | 8792 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
8793 | * exiting to the userspace. Otherwise, the value will be returned to the |
8794 | * userspace. | |
8795 | */ | |
851ba692 | 8796 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
8797 | { |
8798 | int r; | |
62a193ed MG |
8799 | bool req_int_win = |
8800 | dm_request_for_irq_injection(vcpu) && | |
8801 | kvm_cpu_accept_dm_intr(vcpu); | |
404d5d7b | 8802 | fastpath_t exit_fastpath; |
62a193ed | 8803 | |
730dca42 | 8804 | bool req_immediate_exit = false; |
b6c7a5dc | 8805 | |
fb04a1ed PX |
8806 | /* Forbid vmenter if vcpu dirty ring is soft-full */ |
8807 | if (unlikely(vcpu->kvm->dirty_ring_size && | |
8808 | kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { | |
8809 | vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; | |
8810 | trace_kvm_dirty_ring_exit(vcpu); | |
8811 | r = 0; | |
8812 | goto out; | |
8813 | } | |
8814 | ||
2fa6e1e1 | 8815 | if (kvm_request_pending(vcpu)) { |
729c15c2 | 8816 | if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { |
9a78e158 | 8817 | if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { |
671ddc70 JM |
8818 | r = 0; |
8819 | goto out; | |
8820 | } | |
8821 | } | |
a8eeb04a | 8822 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 8823 | kvm_mmu_unload(vcpu); |
a8eeb04a | 8824 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 8825 | __kvm_migrate_timers(vcpu); |
d828199e MT |
8826 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
8827 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
8828 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
8829 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
8830 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
8831 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
8832 | if (unlikely(r)) |
8833 | goto out; | |
8834 | } | |
a8eeb04a | 8835 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 8836 | kvm_mmu_sync_roots(vcpu); |
727a7e27 PB |
8837 | if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) |
8838 | kvm_mmu_load_pgd(vcpu); | |
eeeb4f67 | 8839 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { |
7780938c | 8840 | kvm_vcpu_flush_tlb_all(vcpu); |
eeeb4f67 SC |
8841 | |
8842 | /* Flushing all ASIDs flushes the current ASID... */ | |
8843 | kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
8844 | } | |
8845 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) | |
8846 | kvm_vcpu_flush_tlb_current(vcpu); | |
0baedd79 VK |
8847 | if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu)) |
8848 | kvm_vcpu_flush_tlb_guest(vcpu); | |
eeeb4f67 | 8849 | |
a8eeb04a | 8850 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 8851 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
8852 | r = 0; |
8853 | goto out; | |
8854 | } | |
a8eeb04a | 8855 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 8856 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 8857 | vcpu->mmio_needed = 0; |
71c4dfaf JR |
8858 | r = 0; |
8859 | goto out; | |
8860 | } | |
af585b92 GN |
8861 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
8862 | /* Page is swapped out. Do synthetic halt */ | |
8863 | vcpu->arch.apf.halted = true; | |
8864 | r = 1; | |
8865 | goto out; | |
8866 | } | |
c9aaa895 GC |
8867 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
8868 | record_steal_time(vcpu); | |
64d60670 PB |
8869 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
8870 | process_smi(vcpu); | |
7460fb4a AK |
8871 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
8872 | process_nmi(vcpu); | |
f5132b01 | 8873 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 8874 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 8875 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 8876 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
8877 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
8878 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
8879 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 8880 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
8881 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
8882 | vcpu->run->eoi.vector = | |
8883 | vcpu->arch.pending_ioapic_eoi; | |
8884 | r = 0; | |
8885 | goto out; | |
8886 | } | |
8887 | } | |
3d81bc7e YZ |
8888 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
8889 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
8890 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
8891 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
8892 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
8893 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
8894 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
8895 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
8896 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
8897 | r = 0; | |
8898 | goto out; | |
8899 | } | |
e516cebb AS |
8900 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
8901 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
8902 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
8903 | r = 0; | |
8904 | goto out; | |
8905 | } | |
db397571 AS |
8906 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
8907 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; | |
8908 | vcpu->run->hyperv = vcpu->arch.hyperv.exit; | |
8909 | r = 0; | |
8910 | goto out; | |
8911 | } | |
f3b138c5 AS |
8912 | |
8913 | /* | |
8914 | * KVM_REQ_HV_STIMER has to be processed after | |
8915 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
8916 | * depend on the guest clock being up-to-date | |
8917 | */ | |
1f4b34f8 AS |
8918 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
8919 | kvm_hv_process_stimers(vcpu); | |
8df14af4 SS |
8920 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
8921 | kvm_vcpu_update_apicv(vcpu); | |
557a961a VK |
8922 | if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) |
8923 | kvm_check_async_pf_completion(vcpu); | |
1a155254 AG |
8924 | if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) |
8925 | kvm_x86_ops.msr_filter_changed(vcpu); | |
2f52d58c | 8926 | } |
b93463aa | 8927 | |
b463a6f7 | 8928 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
0f1e261e | 8929 | ++vcpu->stat.req_event; |
66450a21 JK |
8930 | kvm_apic_accept_events(vcpu); |
8931 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
8932 | r = 1; | |
8933 | goto out; | |
8934 | } | |
8935 | ||
c9d40913 PB |
8936 | inject_pending_event(vcpu, &req_immediate_exit); |
8937 | if (req_int_win) | |
8938 | kvm_x86_ops.enable_irq_window(vcpu); | |
b463a6f7 AK |
8939 | |
8940 | if (kvm_lapic_enabled(vcpu)) { | |
8941 | update_cr8_intercept(vcpu); | |
8942 | kvm_lapic_sync_to_vapic(vcpu); | |
8943 | } | |
8944 | } | |
8945 | ||
d8368af8 AK |
8946 | r = kvm_mmu_reload(vcpu); |
8947 | if (unlikely(r)) { | |
d905c069 | 8948 | goto cancel_injection; |
d8368af8 AK |
8949 | } |
8950 | ||
b6c7a5dc HB |
8951 | preempt_disable(); |
8952 | ||
afaf0b2f | 8953 | kvm_x86_ops.prepare_guest_switch(vcpu); |
b95234c8 PB |
8954 | |
8955 | /* | |
8956 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
8957 | * IPI are then delayed after guest entry, which ensures that they | |
8958 | * result in virtual interrupt delivery. | |
8959 | */ | |
8960 | local_irq_disable(); | |
6b7e2d09 XG |
8961 | vcpu->mode = IN_GUEST_MODE; |
8962 | ||
01b71917 MT |
8963 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
8964 | ||
0f127d12 | 8965 | /* |
b95234c8 | 8966 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 8967 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 8968 | * |
81b01667 | 8969 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
8970 | * pairs with the memory barrier implicit in pi_test_and_set_on |
8971 | * (see vmx_deliver_posted_interrupt). | |
8972 | * | |
8973 | * 3) This also orders the write to mode from any reads to the page | |
8974 | * tables done while the VCPU is running. Please see the comment | |
8975 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 8976 | */ |
01b71917 | 8977 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 8978 | |
b95234c8 PB |
8979 | /* |
8980 | * This handles the case where a posted interrupt was | |
8981 | * notified with kvm_vcpu_kick. | |
8982 | */ | |
fa59cc00 | 8983 | if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) |
afaf0b2f | 8984 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
32f88400 | 8985 | |
5a9f5443 | 8986 | if (kvm_vcpu_exit_request(vcpu)) { |
6b7e2d09 | 8987 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 8988 | smp_wmb(); |
6c142801 AK |
8989 | local_irq_enable(); |
8990 | preempt_enable(); | |
01b71917 | 8991 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 8992 | r = 1; |
d905c069 | 8993 | goto cancel_injection; |
6c142801 AK |
8994 | } |
8995 | ||
c43203ca PB |
8996 | if (req_immediate_exit) { |
8997 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
afaf0b2f | 8998 | kvm_x86_ops.request_immediate_exit(vcpu); |
c43203ca | 8999 | } |
d6185f20 | 9000 | |
2620fe26 SC |
9001 | fpregs_assert_state_consistent(); |
9002 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9003 | switch_fpu_return(); | |
5f409e20 | 9004 | |
42dbaa5a | 9005 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
9006 | set_debugreg(0, 7); |
9007 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
9008 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
9009 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
9010 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 9011 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 9012 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 9013 | } |
b6c7a5dc | 9014 | |
a9ab13ff | 9015 | exit_fastpath = kvm_x86_ops.run(vcpu); |
b6c7a5dc | 9016 | |
c77fb5fe PB |
9017 | /* |
9018 | * Do this here before restoring debug registers on the host. And | |
9019 | * since we do this before handling the vmexit, a DR access vmexit | |
9020 | * can (a) read the correct value of the debug registers, (b) set | |
9021 | * KVM_DEBUGREG_WONT_EXIT again. | |
9022 | */ | |
9023 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe | 9024 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
afaf0b2f | 9025 | kvm_x86_ops.sync_dirty_debug_regs(vcpu); |
70e4da7a | 9026 | kvm_update_dr0123(vcpu); |
70e4da7a PB |
9027 | kvm_update_dr7(vcpu); |
9028 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; | |
c77fb5fe PB |
9029 | } |
9030 | ||
24f1e32c FW |
9031 | /* |
9032 | * If the guest has used debug registers, at least dr7 | |
9033 | * will be disabled while returning to the host. | |
9034 | * If we don't have active breakpoints in the host, we don't | |
9035 | * care about the messed up debug address registers. But if | |
9036 | * we have some of them active, restore the old state. | |
9037 | */ | |
59d8eb53 | 9038 | if (hw_breakpoint_active()) |
24f1e32c | 9039 | hw_breakpoint_restore(); |
42dbaa5a | 9040 | |
c967118d | 9041 | vcpu->arch.last_vmentry_cpu = vcpu->cpu; |
4ba76538 | 9042 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 9043 | |
6b7e2d09 | 9044 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9045 | smp_wmb(); |
a547c6db | 9046 | |
a9ab13ff | 9047 | kvm_x86_ops.handle_exit_irqoff(vcpu); |
b6c7a5dc | 9048 | |
d7a08882 SC |
9049 | /* |
9050 | * Consume any pending interrupts, including the possible source of | |
9051 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
9052 | * An instruction is required after local_irq_enable() to fully unblock | |
9053 | * interrupts on processors that implement an interrupt shadow, the | |
9054 | * stat.exits increment will do nicely. | |
9055 | */ | |
9056 | kvm_before_interrupt(vcpu); | |
9057 | local_irq_enable(); | |
b6c7a5dc | 9058 | ++vcpu->stat.exits; |
d7a08882 SC |
9059 | local_irq_disable(); |
9060 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 9061 | |
ec0671d5 WL |
9062 | if (lapic_in_kernel(vcpu)) { |
9063 | s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; | |
9064 | if (delta != S64_MIN) { | |
9065 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); | |
9066 | vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; | |
9067 | } | |
9068 | } | |
b6c7a5dc | 9069 | |
f2485b3e | 9070 | local_irq_enable(); |
b6c7a5dc HB |
9071 | preempt_enable(); |
9072 | ||
f656ce01 | 9073 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 9074 | |
b6c7a5dc HB |
9075 | /* |
9076 | * Profile KVM exit RIPs: | |
9077 | */ | |
9078 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
9079 | unsigned long rip = kvm_rip_read(vcpu); |
9080 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
9081 | } |
9082 | ||
cc578287 ZA |
9083 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
9084 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 9085 | |
5cfb1d5a MT |
9086 | if (vcpu->arch.apic_attention) |
9087 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 9088 | |
afaf0b2f | 9089 | r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath); |
d905c069 MT |
9090 | return r; |
9091 | ||
9092 | cancel_injection: | |
8081ad06 SC |
9093 | if (req_immediate_exit) |
9094 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
afaf0b2f | 9095 | kvm_x86_ops.cancel_injection(vcpu); |
ae7a2a3f MT |
9096 | if (unlikely(vcpu->arch.apic_attention)) |
9097 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
9098 | out: |
9099 | return r; | |
9100 | } | |
b6c7a5dc | 9101 | |
362c698f PB |
9102 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
9103 | { | |
bf9f6ac8 | 9104 | if (!kvm_arch_vcpu_runnable(vcpu) && |
afaf0b2f | 9105 | (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) { |
9c8fd1ba PB |
9106 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
9107 | kvm_vcpu_block(vcpu); | |
9108 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 | 9109 | |
afaf0b2f SC |
9110 | if (kvm_x86_ops.post_block) |
9111 | kvm_x86_ops.post_block(vcpu); | |
bf9f6ac8 | 9112 | |
9c8fd1ba PB |
9113 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
9114 | return 1; | |
9115 | } | |
362c698f PB |
9116 | |
9117 | kvm_apic_accept_events(vcpu); | |
9118 | switch(vcpu->arch.mp_state) { | |
9119 | case KVM_MP_STATE_HALTED: | |
647daca2 | 9120 | case KVM_MP_STATE_AP_RESET_HOLD: |
362c698f PB |
9121 | vcpu->arch.pv.pv_unhalted = false; |
9122 | vcpu->arch.mp_state = | |
9123 | KVM_MP_STATE_RUNNABLE; | |
df561f66 | 9124 | fallthrough; |
362c698f PB |
9125 | case KVM_MP_STATE_RUNNABLE: |
9126 | vcpu->arch.apf.halted = false; | |
9127 | break; | |
9128 | case KVM_MP_STATE_INIT_RECEIVED: | |
9129 | break; | |
9130 | default: | |
9131 | return -EINTR; | |
362c698f PB |
9132 | } |
9133 | return 1; | |
9134 | } | |
09cec754 | 9135 | |
5d9bc648 PB |
9136 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
9137 | { | |
56083bdf | 9138 | if (is_guest_mode(vcpu)) |
33b22172 | 9139 | kvm_x86_ops.nested_ops->check_events(vcpu); |
0ad3bed6 | 9140 | |
5d9bc648 PB |
9141 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
9142 | !vcpu->arch.apf.halted); | |
9143 | } | |
9144 | ||
362c698f | 9145 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
9146 | { |
9147 | int r; | |
f656ce01 | 9148 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 9149 | |
f656ce01 | 9150 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
c595ceee | 9151 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 9152 | |
362c698f | 9153 | for (;;) { |
58f800d5 | 9154 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 9155 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 9156 | } else { |
362c698f | 9157 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
9158 | } |
9159 | ||
09cec754 GN |
9160 | if (r <= 0) |
9161 | break; | |
9162 | ||
72875d8a | 9163 | kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); |
09cec754 GN |
9164 | if (kvm_cpu_has_pending_timer(vcpu)) |
9165 | kvm_inject_pending_timer_irqs(vcpu); | |
9166 | ||
782d422b MG |
9167 | if (dm_request_for_irq_injection(vcpu) && |
9168 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
9169 | r = 0; |
9170 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 9171 | ++vcpu->stat.request_irq_exits; |
362c698f | 9172 | break; |
09cec754 | 9173 | } |
af585b92 | 9174 | |
f3020b88 | 9175 | if (__xfer_to_guest_mode_work_pending()) { |
f656ce01 | 9176 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
72c3c0fe TG |
9177 | r = xfer_to_guest_mode_handle_work(vcpu); |
9178 | if (r) | |
9179 | return r; | |
f656ce01 | 9180 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 9181 | } |
b6c7a5dc HB |
9182 | } |
9183 | ||
f656ce01 | 9184 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
9185 | |
9186 | return r; | |
9187 | } | |
9188 | ||
716d51ab GN |
9189 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
9190 | { | |
9191 | int r; | |
60fc3d02 | 9192 | |
716d51ab | 9193 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
0ce97a2b | 9194 | r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab | 9195 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
60fc3d02 | 9196 | return r; |
716d51ab GN |
9197 | } |
9198 | ||
9199 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
9200 | { | |
9201 | BUG_ON(!vcpu->arch.pio.count); | |
9202 | ||
9203 | return complete_emulated_io(vcpu); | |
9204 | } | |
9205 | ||
f78146b0 AK |
9206 | /* |
9207 | * Implements the following, as a state machine: | |
9208 | * | |
9209 | * read: | |
9210 | * for each fragment | |
87da7e66 XG |
9211 | * for each mmio piece in the fragment |
9212 | * write gpa, len | |
9213 | * exit | |
9214 | * copy data | |
f78146b0 AK |
9215 | * execute insn |
9216 | * | |
9217 | * write: | |
9218 | * for each fragment | |
87da7e66 XG |
9219 | * for each mmio piece in the fragment |
9220 | * write gpa, len | |
9221 | * copy data | |
9222 | * exit | |
f78146b0 | 9223 | */ |
716d51ab | 9224 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
9225 | { |
9226 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 9227 | struct kvm_mmio_fragment *frag; |
87da7e66 | 9228 | unsigned len; |
5287f194 | 9229 | |
716d51ab | 9230 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 9231 | |
716d51ab | 9232 | /* Complete previous fragment */ |
87da7e66 XG |
9233 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
9234 | len = min(8u, frag->len); | |
716d51ab | 9235 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
9236 | memcpy(frag->data, run->mmio.data, len); |
9237 | ||
9238 | if (frag->len <= 8) { | |
9239 | /* Switch to the next fragment. */ | |
9240 | frag++; | |
9241 | vcpu->mmio_cur_fragment++; | |
9242 | } else { | |
9243 | /* Go forward to the next mmio piece. */ | |
9244 | frag->data += len; | |
9245 | frag->gpa += len; | |
9246 | frag->len -= len; | |
9247 | } | |
9248 | ||
a08d3b3b | 9249 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 9250 | vcpu->mmio_needed = 0; |
0912c977 PB |
9251 | |
9252 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 9253 | if (vcpu->mmio_is_write) |
716d51ab GN |
9254 | return 1; |
9255 | vcpu->mmio_read_completed = 1; | |
9256 | return complete_emulated_io(vcpu); | |
9257 | } | |
87da7e66 | 9258 | |
716d51ab GN |
9259 | run->exit_reason = KVM_EXIT_MMIO; |
9260 | run->mmio.phys_addr = frag->gpa; | |
9261 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
9262 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
9263 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
9264 | run->mmio.is_write = vcpu->mmio_is_write; |
9265 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
9266 | return 0; | |
5287f194 AK |
9267 | } |
9268 | ||
c9aef3b8 SC |
9269 | static void kvm_save_current_fpu(struct fpu *fpu) |
9270 | { | |
9271 | /* | |
9272 | * If the target FPU state is not resident in the CPU registers, just | |
9273 | * memcpy() from current, else save CPU state directly to the target. | |
9274 | */ | |
9275 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9276 | memcpy(&fpu->state, ¤t->thread.fpu.state, | |
9277 | fpu_kernel_xstate_size); | |
9278 | else | |
9279 | copy_fpregs_to_fpstate(fpu); | |
9280 | } | |
9281 | ||
822f312d SAS |
9282 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
9283 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
9284 | { | |
5f409e20 RR |
9285 | fpregs_lock(); |
9286 | ||
c9aef3b8 SC |
9287 | kvm_save_current_fpu(vcpu->arch.user_fpu); |
9288 | ||
ed02b213 TL |
9289 | /* |
9290 | * Guests with protected state can't have it set by the hypervisor, | |
9291 | * so skip trying to set it. | |
9292 | */ | |
9293 | if (vcpu->arch.guest_fpu) | |
9294 | /* PKRU is separately restored in kvm_x86_ops.run. */ | |
9295 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, | |
9296 | ~XFEATURE_MASK_PKRU); | |
5f409e20 RR |
9297 | |
9298 | fpregs_mark_activate(); | |
9299 | fpregs_unlock(); | |
9300 | ||
822f312d SAS |
9301 | trace_kvm_fpu(1); |
9302 | } | |
9303 | ||
9304 | /* When vcpu_run ends, restore user space FPU context. */ | |
9305 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
9306 | { | |
5f409e20 RR |
9307 | fpregs_lock(); |
9308 | ||
ed02b213 TL |
9309 | /* |
9310 | * Guests with protected state can't have it read by the hypervisor, | |
9311 | * so skip trying to save it. | |
9312 | */ | |
9313 | if (vcpu->arch.guest_fpu) | |
9314 | kvm_save_current_fpu(vcpu->arch.guest_fpu); | |
c9aef3b8 | 9315 | |
d9a710e5 | 9316 | copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); |
5f409e20 RR |
9317 | |
9318 | fpregs_mark_activate(); | |
9319 | fpregs_unlock(); | |
9320 | ||
822f312d SAS |
9321 | ++vcpu->stat.fpu_reload; |
9322 | trace_kvm_fpu(0); | |
9323 | } | |
9324 | ||
1b94f6f8 | 9325 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) |
b6c7a5dc | 9326 | { |
1b94f6f8 | 9327 | struct kvm_run *kvm_run = vcpu->run; |
b6c7a5dc | 9328 | int r; |
b6c7a5dc | 9329 | |
accb757d | 9330 | vcpu_load(vcpu); |
20b7035c | 9331 | kvm_sigset_activate(vcpu); |
5663d8f9 PX |
9332 | kvm_load_guest_fpu(vcpu); |
9333 | ||
a4535290 | 9334 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
9335 | if (kvm_run->immediate_exit) { |
9336 | r = -EINTR; | |
9337 | goto out; | |
9338 | } | |
b6c7a5dc | 9339 | kvm_vcpu_block(vcpu); |
66450a21 | 9340 | kvm_apic_accept_events(vcpu); |
72875d8a | 9341 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 9342 | r = -EAGAIN; |
a0595000 JS |
9343 | if (signal_pending(current)) { |
9344 | r = -EINTR; | |
1b94f6f8 | 9345 | kvm_run->exit_reason = KVM_EXIT_INTR; |
a0595000 JS |
9346 | ++vcpu->stat.signal_exits; |
9347 | } | |
ac9f6dc0 | 9348 | goto out; |
b6c7a5dc HB |
9349 | } |
9350 | ||
1b94f6f8 | 9351 | if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { |
01643c51 KH |
9352 | r = -EINVAL; |
9353 | goto out; | |
9354 | } | |
9355 | ||
1b94f6f8 | 9356 | if (kvm_run->kvm_dirty_regs) { |
01643c51 KH |
9357 | r = sync_regs(vcpu); |
9358 | if (r != 0) | |
9359 | goto out; | |
9360 | } | |
9361 | ||
b6c7a5dc | 9362 | /* re-sync apic's tpr */ |
35754c98 | 9363 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
9364 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
9365 | r = -EINVAL; | |
9366 | goto out; | |
9367 | } | |
9368 | } | |
b6c7a5dc | 9369 | |
716d51ab GN |
9370 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
9371 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
9372 | vcpu->arch.complete_userspace_io = NULL; | |
9373 | r = cui(vcpu); | |
9374 | if (r <= 0) | |
5663d8f9 | 9375 | goto out; |
716d51ab GN |
9376 | } else |
9377 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 9378 | |
460df4c1 PB |
9379 | if (kvm_run->immediate_exit) |
9380 | r = -EINTR; | |
9381 | else | |
9382 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
9383 | |
9384 | out: | |
5663d8f9 | 9385 | kvm_put_guest_fpu(vcpu); |
1b94f6f8 | 9386 | if (kvm_run->kvm_valid_regs) |
01643c51 | 9387 | store_regs(vcpu); |
f1d86e46 | 9388 | post_kvm_run_save(vcpu); |
20b7035c | 9389 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 9390 | |
accb757d | 9391 | vcpu_put(vcpu); |
b6c7a5dc HB |
9392 | return r; |
9393 | } | |
9394 | ||
01643c51 | 9395 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 9396 | { |
7ae441ea GN |
9397 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
9398 | /* | |
9399 | * We are here if userspace calls get_regs() in the middle of | |
9400 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 9401 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
9402 | * that usually, but some bad designed PV devices (vmware |
9403 | * backdoor interface) need this to work | |
9404 | */ | |
c9b8b07c | 9405 | emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); |
7ae441ea GN |
9406 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
9407 | } | |
de3cd117 SC |
9408 | regs->rax = kvm_rax_read(vcpu); |
9409 | regs->rbx = kvm_rbx_read(vcpu); | |
9410 | regs->rcx = kvm_rcx_read(vcpu); | |
9411 | regs->rdx = kvm_rdx_read(vcpu); | |
9412 | regs->rsi = kvm_rsi_read(vcpu); | |
9413 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 9414 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 9415 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 9416 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
9417 | regs->r8 = kvm_r8_read(vcpu); |
9418 | regs->r9 = kvm_r9_read(vcpu); | |
9419 | regs->r10 = kvm_r10_read(vcpu); | |
9420 | regs->r11 = kvm_r11_read(vcpu); | |
9421 | regs->r12 = kvm_r12_read(vcpu); | |
9422 | regs->r13 = kvm_r13_read(vcpu); | |
9423 | regs->r14 = kvm_r14_read(vcpu); | |
9424 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
9425 | #endif |
9426 | ||
5fdbf976 | 9427 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 9428 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 9429 | } |
b6c7a5dc | 9430 | |
01643c51 KH |
9431 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
9432 | { | |
9433 | vcpu_load(vcpu); | |
9434 | __get_regs(vcpu, regs); | |
1fc9b76b | 9435 | vcpu_put(vcpu); |
b6c7a5dc HB |
9436 | return 0; |
9437 | } | |
9438 | ||
01643c51 | 9439 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 9440 | { |
7ae441ea GN |
9441 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
9442 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
9443 | ||
de3cd117 SC |
9444 | kvm_rax_write(vcpu, regs->rax); |
9445 | kvm_rbx_write(vcpu, regs->rbx); | |
9446 | kvm_rcx_write(vcpu, regs->rcx); | |
9447 | kvm_rdx_write(vcpu, regs->rdx); | |
9448 | kvm_rsi_write(vcpu, regs->rsi); | |
9449 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 9450 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 9451 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 9452 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
9453 | kvm_r8_write(vcpu, regs->r8); |
9454 | kvm_r9_write(vcpu, regs->r9); | |
9455 | kvm_r10_write(vcpu, regs->r10); | |
9456 | kvm_r11_write(vcpu, regs->r11); | |
9457 | kvm_r12_write(vcpu, regs->r12); | |
9458 | kvm_r13_write(vcpu, regs->r13); | |
9459 | kvm_r14_write(vcpu, regs->r14); | |
9460 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
9461 | #endif |
9462 | ||
5fdbf976 | 9463 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 9464 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 9465 | |
b4f14abd JK |
9466 | vcpu->arch.exception.pending = false; |
9467 | ||
3842d135 | 9468 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 9469 | } |
3842d135 | 9470 | |
01643c51 KH |
9471 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
9472 | { | |
9473 | vcpu_load(vcpu); | |
9474 | __set_regs(vcpu, regs); | |
875656fe | 9475 | vcpu_put(vcpu); |
b6c7a5dc HB |
9476 | return 0; |
9477 | } | |
9478 | ||
b6c7a5dc HB |
9479 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
9480 | { | |
9481 | struct kvm_segment cs; | |
9482 | ||
3e6e0aab | 9483 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
9484 | *db = cs.db; |
9485 | *l = cs.l; | |
9486 | } | |
9487 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
9488 | ||
01643c51 | 9489 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 9490 | { |
89a27f4d | 9491 | struct desc_ptr dt; |
b6c7a5dc | 9492 | |
5265713a TL |
9493 | if (vcpu->arch.guest_state_protected) |
9494 | goto skip_protected_regs; | |
9495 | ||
3e6e0aab GT |
9496 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
9497 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
9498 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
9499 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
9500 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
9501 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 9502 | |
3e6e0aab GT |
9503 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
9504 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 9505 | |
afaf0b2f | 9506 | kvm_x86_ops.get_idt(vcpu, &dt); |
89a27f4d GN |
9507 | sregs->idt.limit = dt.size; |
9508 | sregs->idt.base = dt.address; | |
afaf0b2f | 9509 | kvm_x86_ops.get_gdt(vcpu, &dt); |
89a27f4d GN |
9510 | sregs->gdt.limit = dt.size; |
9511 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 9512 | |
ad312c7c | 9513 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 9514 | sregs->cr3 = kvm_read_cr3(vcpu); |
5265713a TL |
9515 | |
9516 | skip_protected_regs: | |
9517 | sregs->cr0 = kvm_read_cr0(vcpu); | |
fc78f519 | 9518 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 9519 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 9520 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
9521 | sregs->apic_base = kvm_get_apic_base(vcpu); |
9522 | ||
0e96f31e | 9523 | memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); |
b6c7a5dc | 9524 | |
04140b41 | 9525 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
9526 | set_bit(vcpu->arch.interrupt.nr, |
9527 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 9528 | } |
16d7a191 | 9529 | |
01643c51 KH |
9530 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
9531 | struct kvm_sregs *sregs) | |
9532 | { | |
9533 | vcpu_load(vcpu); | |
9534 | __get_sregs(vcpu, sregs); | |
bcdec41c | 9535 | vcpu_put(vcpu); |
b6c7a5dc HB |
9536 | return 0; |
9537 | } | |
9538 | ||
62d9f0db MT |
9539 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
9540 | struct kvm_mp_state *mp_state) | |
9541 | { | |
fd232561 | 9542 | vcpu_load(vcpu); |
f958bd23 SC |
9543 | if (kvm_mpx_supported()) |
9544 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 9545 | |
66450a21 | 9546 | kvm_apic_accept_events(vcpu); |
647daca2 TL |
9547 | if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || |
9548 | vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && | |
9549 | vcpu->arch.pv.pv_unhalted) | |
6aef266c SV |
9550 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; |
9551 | else | |
9552 | mp_state->mp_state = vcpu->arch.mp_state; | |
9553 | ||
f958bd23 SC |
9554 | if (kvm_mpx_supported()) |
9555 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 9556 | vcpu_put(vcpu); |
62d9f0db MT |
9557 | return 0; |
9558 | } | |
9559 | ||
9560 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
9561 | struct kvm_mp_state *mp_state) | |
9562 | { | |
e83dff5e CD |
9563 | int ret = -EINVAL; |
9564 | ||
9565 | vcpu_load(vcpu); | |
9566 | ||
bce87cce | 9567 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 9568 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 9569 | goto out; |
66450a21 | 9570 | |
27cbe7d6 LA |
9571 | /* |
9572 | * KVM_MP_STATE_INIT_RECEIVED means the processor is in | |
9573 | * INIT state; latched init should be reported using | |
9574 | * KVM_SET_VCPU_EVENTS, so reject it here. | |
9575 | */ | |
9576 | if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && | |
28bf2888 DH |
9577 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
9578 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 9579 | goto out; |
28bf2888 | 9580 | |
66450a21 JK |
9581 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
9582 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
9583 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
9584 | } else | |
9585 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 9586 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
9587 | |
9588 | ret = 0; | |
9589 | out: | |
9590 | vcpu_put(vcpu); | |
9591 | return ret; | |
62d9f0db MT |
9592 | } |
9593 | ||
7f3d35fd KW |
9594 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
9595 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 9596 | { |
c9b8b07c | 9597 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d | 9598 | int ret; |
e01c2426 | 9599 | |
8ec4722d | 9600 | init_emulate_ctxt(vcpu); |
c697518a | 9601 | |
7f3d35fd | 9602 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 9603 | has_error_code, error_code); |
1051778f SC |
9604 | if (ret) { |
9605 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
9606 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
9607 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 9608 | return 0; |
1051778f | 9609 | } |
37817f29 | 9610 | |
9d74191a TY |
9611 | kvm_rip_write(vcpu, ctxt->eip); |
9612 | kvm_set_rflags(vcpu, ctxt->eflags); | |
60fc3d02 | 9613 | return 1; |
37817f29 IE |
9614 | } |
9615 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
9616 | ||
ee69c92b | 9617 | static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 9618 | { |
37b95951 | 9619 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
9620 | /* |
9621 | * When EFER.LME and CR0.PG are set, the processor is in | |
9622 | * 64-bit mode (though maybe in a 32-bit code segment). | |
9623 | * CR4.PAE and EFER.LMA must be set. | |
9624 | */ | |
ee69c92b SC |
9625 | if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) |
9626 | return false; | |
c1c35cf7 PB |
9627 | if (sregs->cr3 & vcpu->arch.cr3_lm_rsvd_bits) |
9628 | return false; | |
f2981033 LT |
9629 | } else { |
9630 | /* | |
9631 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
9632 | * segment cannot be 64-bit. | |
9633 | */ | |
9634 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
ee69c92b | 9635 | return false; |
f2981033 LT |
9636 | } |
9637 | ||
ee69c92b | 9638 | return kvm_is_valid_cr4(vcpu, sregs->cr4); |
f2981033 LT |
9639 | } |
9640 | ||
01643c51 | 9641 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 9642 | { |
58cb628d | 9643 | struct msr_data apic_base_msr; |
b6c7a5dc | 9644 | int mmu_reset_needed = 0; |
63f42e02 | 9645 | int pending_vec, max_bits, idx; |
89a27f4d | 9646 | struct desc_ptr dt; |
b4ef9d4e CD |
9647 | int ret = -EINVAL; |
9648 | ||
ee69c92b | 9649 | if (!kvm_is_valid_sregs(vcpu, sregs)) |
8dbfb2bf | 9650 | goto out; |
f2981033 | 9651 | |
d3802286 JM |
9652 | apic_base_msr.data = sregs->apic_base; |
9653 | apic_base_msr.host_initiated = true; | |
9654 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
b4ef9d4e | 9655 | goto out; |
6d1068b3 | 9656 | |
5265713a TL |
9657 | if (vcpu->arch.guest_state_protected) |
9658 | goto skip_protected_regs; | |
9659 | ||
89a27f4d GN |
9660 | dt.size = sregs->idt.limit; |
9661 | dt.address = sregs->idt.base; | |
afaf0b2f | 9662 | kvm_x86_ops.set_idt(vcpu, &dt); |
89a27f4d GN |
9663 | dt.size = sregs->gdt.limit; |
9664 | dt.address = sregs->gdt.base; | |
afaf0b2f | 9665 | kvm_x86_ops.set_gdt(vcpu, &dt); |
b6c7a5dc | 9666 | |
ad312c7c | 9667 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 9668 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 9669 | vcpu->arch.cr3 = sregs->cr3; |
cb3c1e2f | 9670 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
b6c7a5dc | 9671 | |
2d3ad1f4 | 9672 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 9673 | |
f6801dff | 9674 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
afaf0b2f | 9675 | kvm_x86_ops.set_efer(vcpu, sregs->efer); |
b6c7a5dc | 9676 | |
4d4ec087 | 9677 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
afaf0b2f | 9678 | kvm_x86_ops.set_cr0(vcpu, sregs->cr0); |
d7306163 | 9679 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 9680 | |
fc78f519 | 9681 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
afaf0b2f | 9682 | kvm_x86_ops.set_cr4(vcpu, sregs->cr4); |
63f42e02 XG |
9683 | |
9684 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
bf03d4f9 | 9685 | if (is_pae_paging(vcpu)) { |
9f8fe504 | 9686 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
9687 | mmu_reset_needed = 1; |
9688 | } | |
63f42e02 | 9689 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
9690 | |
9691 | if (mmu_reset_needed) | |
9692 | kvm_mmu_reset_context(vcpu); | |
9693 | ||
3e6e0aab GT |
9694 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
9695 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
9696 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
9697 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
9698 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
9699 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 9700 | |
3e6e0aab GT |
9701 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
9702 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 9703 | |
5f0269f5 ME |
9704 | update_cr8_intercept(vcpu); |
9705 | ||
9c3e4aab | 9706 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 9707 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 9708 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 9709 | !is_protmode(vcpu)) |
9c3e4aab MT |
9710 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
9711 | ||
5265713a TL |
9712 | skip_protected_regs: |
9713 | max_bits = KVM_NR_INTERRUPTS; | |
9714 | pending_vec = find_first_bit( | |
9715 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
9716 | if (pending_vec < max_bits) { | |
9717 | kvm_queue_interrupt(vcpu, pending_vec, false); | |
9718 | pr_debug("Set back pending irq %d\n", pending_vec); | |
9719 | } | |
9720 | ||
3842d135 AK |
9721 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
9722 | ||
b4ef9d4e CD |
9723 | ret = 0; |
9724 | out: | |
01643c51 KH |
9725 | return ret; |
9726 | } | |
9727 | ||
9728 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
9729 | struct kvm_sregs *sregs) | |
9730 | { | |
9731 | int ret; | |
9732 | ||
9733 | vcpu_load(vcpu); | |
9734 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
9735 | vcpu_put(vcpu); |
9736 | return ret; | |
b6c7a5dc HB |
9737 | } |
9738 | ||
d0bfb940 JK |
9739 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
9740 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 9741 | { |
355be0b9 | 9742 | unsigned long rflags; |
ae675ef0 | 9743 | int i, r; |
b6c7a5dc | 9744 | |
8d4846b9 TL |
9745 | if (vcpu->arch.guest_state_protected) |
9746 | return -EINVAL; | |
9747 | ||
66b56562 CD |
9748 | vcpu_load(vcpu); |
9749 | ||
4f926bf2 JK |
9750 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
9751 | r = -EBUSY; | |
9752 | if (vcpu->arch.exception.pending) | |
2122ff5e | 9753 | goto out; |
4f926bf2 JK |
9754 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
9755 | kvm_queue_exception(vcpu, DB_VECTOR); | |
9756 | else | |
9757 | kvm_queue_exception(vcpu, BP_VECTOR); | |
9758 | } | |
9759 | ||
91586a3b JK |
9760 | /* |
9761 | * Read rflags as long as potentially injected trace flags are still | |
9762 | * filtered out. | |
9763 | */ | |
9764 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
9765 | |
9766 | vcpu->guest_debug = dbg->control; | |
9767 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
9768 | vcpu->guest_debug = 0; | |
9769 | ||
9770 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
9771 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
9772 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 9773 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
9774 | } else { |
9775 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
9776 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 9777 | } |
c8639010 | 9778 | kvm_update_dr7(vcpu); |
ae675ef0 | 9779 | |
f92653ee JK |
9780 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
9781 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
9782 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 9783 | |
91586a3b JK |
9784 | /* |
9785 | * Trigger an rflags update that will inject or remove the trace | |
9786 | * flags. | |
9787 | */ | |
9788 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 9789 | |
6986982f | 9790 | kvm_x86_ops.update_exception_bitmap(vcpu); |
b6c7a5dc | 9791 | |
4f926bf2 | 9792 | r = 0; |
d0bfb940 | 9793 | |
2122ff5e | 9794 | out: |
66b56562 | 9795 | vcpu_put(vcpu); |
b6c7a5dc HB |
9796 | return r; |
9797 | } | |
9798 | ||
8b006791 ZX |
9799 | /* |
9800 | * Translate a guest virtual address to a guest physical address. | |
9801 | */ | |
9802 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
9803 | struct kvm_translation *tr) | |
9804 | { | |
9805 | unsigned long vaddr = tr->linear_address; | |
9806 | gpa_t gpa; | |
f656ce01 | 9807 | int idx; |
8b006791 | 9808 | |
1da5b61d CD |
9809 | vcpu_load(vcpu); |
9810 | ||
f656ce01 | 9811 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 9812 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 9813 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
9814 | tr->physical_address = gpa; |
9815 | tr->valid = gpa != UNMAPPED_GVA; | |
9816 | tr->writeable = 1; | |
9817 | tr->usermode = 0; | |
8b006791 | 9818 | |
1da5b61d | 9819 | vcpu_put(vcpu); |
8b006791 ZX |
9820 | return 0; |
9821 | } | |
9822 | ||
d0752060 HB |
9823 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
9824 | { | |
1393123e | 9825 | struct fxregs_state *fxsave; |
d0752060 | 9826 | |
ed02b213 TL |
9827 | if (!vcpu->arch.guest_fpu) |
9828 | return 0; | |
9829 | ||
1393123e | 9830 | vcpu_load(vcpu); |
d0752060 | 9831 | |
b666a4b6 | 9832 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 HB |
9833 | memcpy(fpu->fpr, fxsave->st_space, 128); |
9834 | fpu->fcw = fxsave->cwd; | |
9835 | fpu->fsw = fxsave->swd; | |
9836 | fpu->ftwx = fxsave->twd; | |
9837 | fpu->last_opcode = fxsave->fop; | |
9838 | fpu->last_ip = fxsave->rip; | |
9839 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 9840 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 9841 | |
1393123e | 9842 | vcpu_put(vcpu); |
d0752060 HB |
9843 | return 0; |
9844 | } | |
9845 | ||
9846 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
9847 | { | |
6a96bc7f CD |
9848 | struct fxregs_state *fxsave; |
9849 | ||
ed02b213 TL |
9850 | if (!vcpu->arch.guest_fpu) |
9851 | return 0; | |
9852 | ||
6a96bc7f CD |
9853 | vcpu_load(vcpu); |
9854 | ||
b666a4b6 | 9855 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 | 9856 | |
d0752060 HB |
9857 | memcpy(fxsave->st_space, fpu->fpr, 128); |
9858 | fxsave->cwd = fpu->fcw; | |
9859 | fxsave->swd = fpu->fsw; | |
9860 | fxsave->twd = fpu->ftwx; | |
9861 | fxsave->fop = fpu->last_opcode; | |
9862 | fxsave->rip = fpu->last_ip; | |
9863 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 9864 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 9865 | |
6a96bc7f | 9866 | vcpu_put(vcpu); |
d0752060 HB |
9867 | return 0; |
9868 | } | |
9869 | ||
01643c51 KH |
9870 | static void store_regs(struct kvm_vcpu *vcpu) |
9871 | { | |
9872 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
9873 | ||
9874 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
9875 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
9876 | ||
9877 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
9878 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
9879 | ||
9880 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
9881 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
9882 | vcpu, &vcpu->run->s.regs.events); | |
9883 | } | |
9884 | ||
9885 | static int sync_regs(struct kvm_vcpu *vcpu) | |
9886 | { | |
9887 | if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) | |
9888 | return -EINVAL; | |
9889 | ||
9890 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { | |
9891 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
9892 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
9893 | } | |
9894 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
9895 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
9896 | return -EINVAL; | |
9897 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
9898 | } | |
9899 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
9900 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
9901 | vcpu, &vcpu->run->s.regs.events)) | |
9902 | return -EINVAL; | |
9903 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
9904 | } | |
9905 | ||
9906 | return 0; | |
9907 | } | |
9908 | ||
0ee6a517 | 9909 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 9910 | { |
ed02b213 TL |
9911 | if (!vcpu->arch.guest_fpu) |
9912 | return; | |
9913 | ||
b666a4b6 | 9914 | fpstate_init(&vcpu->arch.guest_fpu->state); |
782511b0 | 9915 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
b666a4b6 | 9916 | vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = |
df1daba7 | 9917 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 9918 | |
2acf923e DC |
9919 | /* |
9920 | * Ensure guest xcr0 is valid for loading | |
9921 | */ | |
d91cab78 | 9922 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 9923 | |
ad312c7c | 9924 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 9925 | } |
d0752060 | 9926 | |
ed02b213 TL |
9927 | void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) |
9928 | { | |
9929 | if (vcpu->arch.guest_fpu) { | |
9930 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
9931 | vcpu->arch.guest_fpu = NULL; | |
9932 | } | |
9933 | } | |
9934 | EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); | |
9935 | ||
897cc38e | 9936 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 9937 | { |
897cc38e SC |
9938 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
9939 | pr_warn_once("kvm: SMP vm created on host with unstable TSC; " | |
9940 | "guest TSC will not be reliable\n"); | |
7f1ea208 | 9941 | |
897cc38e | 9942 | return 0; |
e9b11c17 ZX |
9943 | } |
9944 | ||
e529ef66 | 9945 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 9946 | { |
95a0d01e SC |
9947 | struct page *page; |
9948 | int r; | |
c447e76b | 9949 | |
95a0d01e SC |
9950 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
9951 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
9952 | else | |
9953 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 9954 | |
95a0d01e | 9955 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c447e76b | 9956 | |
95a0d01e SC |
9957 | r = kvm_mmu_create(vcpu); |
9958 | if (r < 0) | |
9959 | return r; | |
9960 | ||
9961 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
9962 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
9963 | if (r < 0) | |
9964 | goto fail_mmu_destroy; | |
4e19c36f SS |
9965 | if (kvm_apicv_activated(vcpu->kvm)) |
9966 | vcpu->arch.apicv_active = true; | |
95a0d01e SC |
9967 | } else |
9968 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
9969 | ||
9970 | r = -ENOMEM; | |
9971 | ||
93bb59ca | 9972 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); |
95a0d01e SC |
9973 | if (!page) |
9974 | goto fail_free_lapic; | |
9975 | vcpu->arch.pio_data = page_address(page); | |
9976 | ||
9977 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, | |
9978 | GFP_KERNEL_ACCOUNT); | |
9979 | if (!vcpu->arch.mce_banks) | |
9980 | goto fail_free_pio_data; | |
9981 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
9982 | ||
9983 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
9984 | GFP_KERNEL_ACCOUNT)) | |
9985 | goto fail_free_mce_banks; | |
9986 | ||
c9b8b07c SC |
9987 | if (!alloc_emulate_ctxt(vcpu)) |
9988 | goto free_wbinvd_dirty_mask; | |
9989 | ||
95a0d01e SC |
9990 | vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, |
9991 | GFP_KERNEL_ACCOUNT); | |
9992 | if (!vcpu->arch.user_fpu) { | |
9993 | pr_err("kvm: failed to allocate userspace's fpu\n"); | |
c9b8b07c | 9994 | goto free_emulate_ctxt; |
95a0d01e SC |
9995 | } |
9996 | ||
9997 | vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, | |
9998 | GFP_KERNEL_ACCOUNT); | |
9999 | if (!vcpu->arch.guest_fpu) { | |
10000 | pr_err("kvm: failed to allocate vcpu's fpu\n"); | |
10001 | goto free_user_fpu; | |
10002 | } | |
10003 | fx_init(vcpu); | |
10004 | ||
95a0d01e | 10005 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
031b91a5 | 10006 | vcpu->arch.cr3_lm_rsvd_bits = rsvd_bits(cpuid_maxphyaddr(vcpu), 63); |
95a0d01e SC |
10007 | |
10008 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
10009 | ||
10010 | kvm_async_pf_hash_reset(vcpu); | |
10011 | kvm_pmu_init(vcpu); | |
10012 | ||
10013 | vcpu->arch.pending_external_vector = -1; | |
10014 | vcpu->arch.preempted_in_kernel = false; | |
10015 | ||
10016 | kvm_hv_vcpu_init(vcpu); | |
10017 | ||
afaf0b2f | 10018 | r = kvm_x86_ops.vcpu_create(vcpu); |
95a0d01e SC |
10019 | if (r) |
10020 | goto free_guest_fpu; | |
e9b11c17 | 10021 | |
0cf9135b | 10022 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 10023 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
19efffa2 | 10024 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 10025 | vcpu_load(vcpu); |
d28bc9dd | 10026 | kvm_vcpu_reset(vcpu, false); |
e1732991 | 10027 | kvm_init_mmu(vcpu, false); |
e9b11c17 | 10028 | vcpu_put(vcpu); |
ec7660cc | 10029 | return 0; |
95a0d01e SC |
10030 | |
10031 | free_guest_fpu: | |
ed02b213 | 10032 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10033 | free_user_fpu: |
10034 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
c9b8b07c SC |
10035 | free_emulate_ctxt: |
10036 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); | |
95a0d01e SC |
10037 | free_wbinvd_dirty_mask: |
10038 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
10039 | fail_free_mce_banks: | |
10040 | kfree(vcpu->arch.mce_banks); | |
10041 | fail_free_pio_data: | |
10042 | free_page((unsigned long)vcpu->arch.pio_data); | |
10043 | fail_free_lapic: | |
10044 | kvm_free_lapic(vcpu); | |
10045 | fail_mmu_destroy: | |
10046 | kvm_mmu_destroy(vcpu); | |
10047 | return r; | |
e9b11c17 ZX |
10048 | } |
10049 | ||
31928aa5 | 10050 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 10051 | { |
332967a3 | 10052 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 10053 | |
d3457c87 RK |
10054 | kvm_hv_vcpu_postcreate(vcpu); |
10055 | ||
ec7660cc | 10056 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 10057 | return; |
ec7660cc | 10058 | vcpu_load(vcpu); |
0c899c25 | 10059 | kvm_synchronize_tsc(vcpu, 0); |
42897d86 | 10060 | vcpu_put(vcpu); |
2d5ba19b MT |
10061 | |
10062 | /* poll control enabled by default */ | |
10063 | vcpu->arch.msr_kvm_poll_control = 1; | |
10064 | ||
ec7660cc | 10065 | mutex_unlock(&vcpu->mutex); |
42897d86 | 10066 | |
b34de572 WL |
10067 | if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) |
10068 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
10069 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
10070 | } |
10071 | ||
d40ccc62 | 10072 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 10073 | { |
4cbc418a | 10074 | struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; |
95a0d01e | 10075 | int idx; |
344d9588 | 10076 | |
4cbc418a PB |
10077 | kvm_release_pfn(cache->pfn, cache->dirty, cache); |
10078 | ||
50b143e1 | 10079 | kvmclock_reset(vcpu); |
e9b11c17 | 10080 | |
afaf0b2f | 10081 | kvm_x86_ops.vcpu_free(vcpu); |
50b143e1 | 10082 | |
c9b8b07c | 10083 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); |
50b143e1 SC |
10084 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
10085 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
ed02b213 | 10086 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10087 | |
10088 | kvm_hv_vcpu_uninit(vcpu); | |
10089 | kvm_pmu_destroy(vcpu); | |
10090 | kfree(vcpu->arch.mce_banks); | |
10091 | kvm_free_lapic(vcpu); | |
10092 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
10093 | kvm_mmu_destroy(vcpu); | |
10094 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
10095 | free_page((unsigned long)vcpu->arch.pio_data); | |
255cbecf | 10096 | kvfree(vcpu->arch.cpuid_entries); |
95a0d01e SC |
10097 | if (!lapic_in_kernel(vcpu)) |
10098 | static_key_slow_dec(&kvm_no_apic_vcpu); | |
e9b11c17 ZX |
10099 | } |
10100 | ||
d28bc9dd | 10101 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 10102 | { |
b7e31be3 RK |
10103 | kvm_lapic_reset(vcpu, init_event); |
10104 | ||
e69fab5d PB |
10105 | vcpu->arch.hflags = 0; |
10106 | ||
c43203ca | 10107 | vcpu->arch.smi_pending = 0; |
52797bf9 | 10108 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
10109 | atomic_set(&vcpu->arch.nmi_queued, 0); |
10110 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 10111 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
10112 | kvm_clear_interrupt_queue(vcpu); |
10113 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 10114 | |
42dbaa5a | 10115 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 10116 | kvm_update_dr0123(vcpu); |
6f43ed01 | 10117 | vcpu->arch.dr6 = DR6_INIT; |
42dbaa5a | 10118 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 10119 | kvm_update_dr7(vcpu); |
42dbaa5a | 10120 | |
1119022c NA |
10121 | vcpu->arch.cr2 = 0; |
10122 | ||
3842d135 | 10123 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2635b5c4 VK |
10124 | vcpu->arch.apf.msr_en_val = 0; |
10125 | vcpu->arch.apf.msr_int_val = 0; | |
c9aaa895 | 10126 | vcpu->arch.st.msr_val = 0; |
3842d135 | 10127 | |
12f9a48f GC |
10128 | kvmclock_reset(vcpu); |
10129 | ||
af585b92 GN |
10130 | kvm_clear_async_pf_completion_queue(vcpu); |
10131 | kvm_async_pf_hash_reset(vcpu); | |
10132 | vcpu->arch.apf.halted = false; | |
3842d135 | 10133 | |
ed02b213 | 10134 | if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { |
a554d207 WL |
10135 | void *mpx_state_buffer; |
10136 | ||
10137 | /* | |
10138 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
10139 | * called with loaded FPU and does not let userspace fix the state. | |
10140 | */ | |
f775b13e RR |
10141 | if (init_event) |
10142 | kvm_put_guest_fpu(vcpu); | |
b666a4b6 | 10143 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10144 | XFEATURE_BNDREGS); |
a554d207 WL |
10145 | if (mpx_state_buffer) |
10146 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
b666a4b6 | 10147 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10148 | XFEATURE_BNDCSR); |
a554d207 WL |
10149 | if (mpx_state_buffer) |
10150 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
10151 | if (init_event) |
10152 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
10153 | } |
10154 | ||
64d60670 | 10155 | if (!init_event) { |
d28bc9dd | 10156 | kvm_pmu_reset(vcpu); |
64d60670 | 10157 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 10158 | |
db2336a8 | 10159 | vcpu->arch.msr_misc_features_enables = 0; |
a554d207 WL |
10160 | |
10161 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; | |
64d60670 | 10162 | } |
f5132b01 | 10163 | |
66f7b72e JS |
10164 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
10165 | vcpu->arch.regs_avail = ~0; | |
10166 | vcpu->arch.regs_dirty = ~0; | |
10167 | ||
a554d207 WL |
10168 | vcpu->arch.ia32_xss = 0; |
10169 | ||
afaf0b2f | 10170 | kvm_x86_ops.vcpu_reset(vcpu, init_event); |
e9b11c17 ZX |
10171 | } |
10172 | ||
2b4a273b | 10173 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
10174 | { |
10175 | struct kvm_segment cs; | |
10176 | ||
10177 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
10178 | cs.selector = vector << 8; | |
10179 | cs.base = vector << 12; | |
10180 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
10181 | kvm_rip_write(vcpu, 0); | |
e9b11c17 | 10182 | } |
647daca2 | 10183 | EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); |
e9b11c17 | 10184 | |
13a34e06 | 10185 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 10186 | { |
ca84d1a2 ZA |
10187 | struct kvm *kvm; |
10188 | struct kvm_vcpu *vcpu; | |
10189 | int i; | |
0dd6a6ed ZA |
10190 | int ret; |
10191 | u64 local_tsc; | |
10192 | u64 max_tsc = 0; | |
10193 | bool stable, backwards_tsc = false; | |
18863bdd | 10194 | |
7e34fbd0 | 10195 | kvm_user_return_msr_cpu_online(); |
afaf0b2f | 10196 | ret = kvm_x86_ops.hardware_enable(); |
0dd6a6ed ZA |
10197 | if (ret != 0) |
10198 | return ret; | |
10199 | ||
4ea1636b | 10200 | local_tsc = rdtsc(); |
b0c39dc6 | 10201 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
10202 | list_for_each_entry(kvm, &vm_list, vm_list) { |
10203 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
10204 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 10205 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10206 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
10207 | backwards_tsc = true; | |
10208 | if (vcpu->arch.last_host_tsc > max_tsc) | |
10209 | max_tsc = vcpu->arch.last_host_tsc; | |
10210 | } | |
10211 | } | |
10212 | } | |
10213 | ||
10214 | /* | |
10215 | * Sometimes, even reliable TSCs go backwards. This happens on | |
10216 | * platforms that reset TSC during suspend or hibernate actions, but | |
10217 | * maintain synchronization. We must compensate. Fortunately, we can | |
10218 | * detect that condition here, which happens early in CPU bringup, | |
10219 | * before any KVM threads can be running. Unfortunately, we can't | |
10220 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
10221 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 10222 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
10223 | * variables that haven't been updated yet. |
10224 | * | |
10225 | * So we simply find the maximum observed TSC above, then record the | |
10226 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
10227 | * the adjustment will be applied. Note that we accumulate | |
10228 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
10229 | * gets a chance to run again. In the event that no KVM threads get a | |
10230 | * chance to run, we will miss the entire elapsed period, as we'll have | |
10231 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
10232 | * loose cycle time. This isn't too big a deal, since the loss will be | |
10233 | * uniform across all VCPUs (not to mention the scenario is extremely | |
10234 | * unlikely). It is possible that a second hibernate recovery happens | |
10235 | * much faster than a first, causing the observed TSC here to be | |
10236 | * smaller; this would require additional padding adjustment, which is | |
10237 | * why we set last_host_tsc to the local tsc observed here. | |
10238 | * | |
10239 | * N.B. - this code below runs only on platforms with reliable TSC, | |
10240 | * as that is the only way backwards_tsc is set above. Also note | |
10241 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
10242 | * have the same delta_cyc adjustment applied if backwards_tsc | |
10243 | * is detected. Note further, this adjustment is only done once, | |
10244 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
10245 | * called multiple times (one for each physical CPU bringup). | |
10246 | * | |
4a969980 | 10247 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
10248 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
10249 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
10250 | * guarantee that they stay in perfect synchronization. | |
10251 | */ | |
10252 | if (backwards_tsc) { | |
10253 | u64 delta_cyc = max_tsc - local_tsc; | |
10254 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 10255 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
10256 | kvm_for_each_vcpu(i, vcpu, kvm) { |
10257 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
10258 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 10259 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10260 | } |
10261 | ||
10262 | /* | |
10263 | * We have to disable TSC offset matching.. if you were | |
10264 | * booting a VM while issuing an S4 host suspend.... | |
10265 | * you may have some problem. Solving this issue is | |
10266 | * left as an exercise to the reader. | |
10267 | */ | |
10268 | kvm->arch.last_tsc_nsec = 0; | |
10269 | kvm->arch.last_tsc_write = 0; | |
10270 | } | |
10271 | ||
10272 | } | |
10273 | return 0; | |
e9b11c17 ZX |
10274 | } |
10275 | ||
13a34e06 | 10276 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 10277 | { |
afaf0b2f | 10278 | kvm_x86_ops.hardware_disable(); |
13a34e06 | 10279 | drop_user_return_notifiers(); |
e9b11c17 ZX |
10280 | } |
10281 | ||
b9904085 | 10282 | int kvm_arch_hardware_setup(void *opaque) |
e9b11c17 | 10283 | { |
d008dfdb | 10284 | struct kvm_x86_init_ops *ops = opaque; |
9e9c3fe4 NA |
10285 | int r; |
10286 | ||
91661989 SC |
10287 | rdmsrl_safe(MSR_EFER, &host_efer); |
10288 | ||
408e9a31 PB |
10289 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
10290 | rdmsrl(MSR_IA32_XSS, host_xss); | |
10291 | ||
d008dfdb | 10292 | r = ops->hardware_setup(); |
9e9c3fe4 NA |
10293 | if (r != 0) |
10294 | return r; | |
10295 | ||
afaf0b2f | 10296 | memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); |
69c6f69a | 10297 | |
408e9a31 PB |
10298 | if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) |
10299 | supported_xss = 0; | |
10300 | ||
139f7425 PB |
10301 | #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) |
10302 | cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); | |
10303 | #undef __kvm_cpu_cap_has | |
b11306b5 | 10304 | |
35181e86 HZ |
10305 | if (kvm_has_tsc_control) { |
10306 | /* | |
10307 | * Make sure the user can only configure tsc_khz values that | |
10308 | * fit into a signed integer. | |
273ba457 | 10309 | * A min value is not calculated because it will always |
35181e86 HZ |
10310 | * be 1 on all machines. |
10311 | */ | |
10312 | u64 max = min(0x7fffffffULL, | |
10313 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
10314 | kvm_max_guest_tsc_khz = max; | |
10315 | ||
ad721883 | 10316 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 10317 | } |
ad721883 | 10318 | |
9e9c3fe4 NA |
10319 | kvm_init_msr_list(); |
10320 | return 0; | |
e9b11c17 ZX |
10321 | } |
10322 | ||
10323 | void kvm_arch_hardware_unsetup(void) | |
10324 | { | |
afaf0b2f | 10325 | kvm_x86_ops.hardware_unsetup(); |
e9b11c17 ZX |
10326 | } |
10327 | ||
b9904085 | 10328 | int kvm_arch_check_processor_compat(void *opaque) |
e9b11c17 | 10329 | { |
f1cdecf5 | 10330 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); |
d008dfdb | 10331 | struct kvm_x86_init_ops *ops = opaque; |
f1cdecf5 SC |
10332 | |
10333 | WARN_ON(!irqs_disabled()); | |
10334 | ||
139f7425 PB |
10335 | if (__cr4_reserved_bits(cpu_has, c) != |
10336 | __cr4_reserved_bits(cpu_has, &boot_cpu_data)) | |
f1cdecf5 SC |
10337 | return -EIO; |
10338 | ||
d008dfdb | 10339 | return ops->check_processor_compatibility(); |
d71ba788 PB |
10340 | } |
10341 | ||
10342 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
10343 | { | |
10344 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
10345 | } | |
10346 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
10347 | ||
10348 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
10349 | { | |
10350 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
10351 | } |
10352 | ||
54e9818f | 10353 | struct static_key kvm_no_apic_vcpu __read_mostly; |
bce87cce | 10354 | EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); |
54e9818f | 10355 | |
e790d9ef RK |
10356 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
10357 | { | |
b35e5548 LX |
10358 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
10359 | ||
c595ceee | 10360 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
10361 | if (pmu->version && unlikely(pmu->event_count)) { |
10362 | pmu->need_cleanup = true; | |
10363 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
10364 | } | |
afaf0b2f | 10365 | kvm_x86_ops.sched_in(vcpu, cpu); |
e790d9ef RK |
10366 | } |
10367 | ||
562b6b08 SC |
10368 | void kvm_arch_free_vm(struct kvm *kvm) |
10369 | { | |
10370 | kfree(kvm->arch.hyperv.hv_pa_pg); | |
10371 | vfree(kvm); | |
e790d9ef RK |
10372 | } |
10373 | ||
562b6b08 | 10374 | |
e08b9637 | 10375 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 10376 | { |
e08b9637 CO |
10377 | if (type) |
10378 | return -EINVAL; | |
10379 | ||
6ef768fa | 10380 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 10381 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
10605204 | 10382 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
1aa9b957 | 10383 | INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); |
4d5c5d0f | 10384 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 10385 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 10386 | |
5550af4d SY |
10387 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
10388 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
10389 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
10390 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
10391 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 10392 | |
038f8c11 | 10393 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 10394 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
10395 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
10396 | ||
8171cd68 | 10397 | kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); |
d828199e | 10398 | pvclock_update_vm_gtod_copy(kvm); |
53f658b3 | 10399 | |
6fbbde9a DS |
10400 | kvm->arch.guest_can_read_msr_platform_info = true; |
10401 | ||
7e44e449 | 10402 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 10403 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 10404 | |
cbc0236a | 10405 | kvm_hv_init_vm(kvm); |
0eb05bf2 | 10406 | kvm_page_track_init(kvm); |
13d268ca | 10407 | kvm_mmu_init_vm(kvm); |
0eb05bf2 | 10408 | |
afaf0b2f | 10409 | return kvm_x86_ops.vm_init(kvm); |
d19a9cd2 ZX |
10410 | } |
10411 | ||
1aa9b957 JS |
10412 | int kvm_arch_post_init_vm(struct kvm *kvm) |
10413 | { | |
10414 | return kvm_mmu_post_init_vm(kvm); | |
10415 | } | |
10416 | ||
d19a9cd2 ZX |
10417 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
10418 | { | |
ec7660cc | 10419 | vcpu_load(vcpu); |
d19a9cd2 ZX |
10420 | kvm_mmu_unload(vcpu); |
10421 | vcpu_put(vcpu); | |
10422 | } | |
10423 | ||
10424 | static void kvm_free_vcpus(struct kvm *kvm) | |
10425 | { | |
10426 | unsigned int i; | |
988a2cae | 10427 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
10428 | |
10429 | /* | |
10430 | * Unpin any mmu pages first. | |
10431 | */ | |
af585b92 GN |
10432 | kvm_for_each_vcpu(i, vcpu, kvm) { |
10433 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 10434 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 10435 | } |
988a2cae | 10436 | kvm_for_each_vcpu(i, vcpu, kvm) |
4543bdc0 | 10437 | kvm_vcpu_destroy(vcpu); |
988a2cae GN |
10438 | |
10439 | mutex_lock(&kvm->lock); | |
10440 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
10441 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 10442 | |
988a2cae GN |
10443 | atomic_set(&kvm->online_vcpus, 0); |
10444 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
10445 | } |
10446 | ||
ad8ba2cd SY |
10447 | void kvm_arch_sync_events(struct kvm *kvm) |
10448 | { | |
332967a3 | 10449 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 10450 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 10451 | kvm_free_pit(kvm); |
ad8ba2cd SY |
10452 | } |
10453 | ||
ff5a983c PX |
10454 | #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) |
10455 | ||
10456 | /** | |
10457 | * __x86_set_memory_region: Setup KVM internal memory slot | |
10458 | * | |
10459 | * @kvm: the kvm pointer to the VM. | |
10460 | * @id: the slot ID to setup. | |
10461 | * @gpa: the GPA to install the slot (unused when @size == 0). | |
10462 | * @size: the size of the slot. Set to zero to uninstall a slot. | |
10463 | * | |
10464 | * This function helps to setup a KVM internal memory slot. Specify | |
10465 | * @size > 0 to install a new slot, while @size == 0 to uninstall a | |
10466 | * slot. The return code can be one of the following: | |
10467 | * | |
10468 | * HVA: on success (uninstall will return a bogus HVA) | |
10469 | * -errno: on error | |
10470 | * | |
10471 | * The caller should always use IS_ERR() to check the return value | |
10472 | * before use. Note, the KVM internal memory slots are guaranteed to | |
10473 | * remain valid and unchanged until the VM is destroyed, i.e., the | |
10474 | * GPA->HVA translation will not change. However, the HVA is a user | |
10475 | * address, i.e. its accessibility is not guaranteed, and must be | |
10476 | * accessed via __copy_{to,from}_user(). | |
10477 | */ | |
10478 | void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, | |
10479 | u32 size) | |
9da0e4d5 PB |
10480 | { |
10481 | int i, r; | |
3f649ab7 | 10482 | unsigned long hva, old_npages; |
f0d648bd | 10483 | struct kvm_memslots *slots = kvm_memslots(kvm); |
0577d1ab | 10484 | struct kvm_memory_slot *slot; |
9da0e4d5 PB |
10485 | |
10486 | /* Called with kvm->slots_lock held. */ | |
1d8007bd | 10487 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
ff5a983c | 10488 | return ERR_PTR_USR(-EINVAL); |
9da0e4d5 | 10489 | |
f0d648bd PB |
10490 | slot = id_to_memslot(slots, id); |
10491 | if (size) { | |
0577d1ab | 10492 | if (slot && slot->npages) |
ff5a983c | 10493 | return ERR_PTR_USR(-EEXIST); |
f0d648bd PB |
10494 | |
10495 | /* | |
10496 | * MAP_SHARED to prevent internal slot pages from being moved | |
10497 | * by fork()/COW. | |
10498 | */ | |
10499 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
10500 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
10501 | if (IS_ERR((void *)hva)) | |
ff5a983c | 10502 | return (void __user *)hva; |
f0d648bd | 10503 | } else { |
0577d1ab | 10504 | if (!slot || !slot->npages) |
f0d648bd PB |
10505 | return 0; |
10506 | ||
0577d1ab | 10507 | old_npages = slot->npages; |
b66f9bab | 10508 | hva = slot->userspace_addr; |
f0d648bd PB |
10509 | } |
10510 | ||
9da0e4d5 | 10511 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 10512 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 10513 | |
1d8007bd PB |
10514 | m.slot = id | (i << 16); |
10515 | m.flags = 0; | |
10516 | m.guest_phys_addr = gpa; | |
f0d648bd | 10517 | m.userspace_addr = hva; |
1d8007bd | 10518 | m.memory_size = size; |
9da0e4d5 PB |
10519 | r = __kvm_set_memory_region(kvm, &m); |
10520 | if (r < 0) | |
ff5a983c | 10521 | return ERR_PTR_USR(r); |
9da0e4d5 PB |
10522 | } |
10523 | ||
103c763c | 10524 | if (!size) |
0577d1ab | 10525 | vm_munmap(hva, old_npages * PAGE_SIZE); |
f0d648bd | 10526 | |
ff5a983c | 10527 | return (void __user *)hva; |
9da0e4d5 PB |
10528 | } |
10529 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
10530 | ||
1aa9b957 JS |
10531 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
10532 | { | |
10533 | kvm_mmu_pre_destroy_vm(kvm); | |
10534 | } | |
10535 | ||
d19a9cd2 ZX |
10536 | void kvm_arch_destroy_vm(struct kvm *kvm) |
10537 | { | |
1a155254 AG |
10538 | u32 i; |
10539 | ||
27469d29 AH |
10540 | if (current->mm == kvm->mm) { |
10541 | /* | |
10542 | * Free memory regions allocated on behalf of userspace, | |
10543 | * unless the the memory map has changed due to process exit | |
10544 | * or fd copying. | |
10545 | */ | |
6a3c623b PX |
10546 | mutex_lock(&kvm->slots_lock); |
10547 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
10548 | 0, 0); | |
10549 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
10550 | 0, 0); | |
10551 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
10552 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 10553 | } |
afaf0b2f SC |
10554 | if (kvm_x86_ops.vm_destroy) |
10555 | kvm_x86_ops.vm_destroy(kvm); | |
1a155254 AG |
10556 | for (i = 0; i < kvm->arch.msr_filter.count; i++) |
10557 | kfree(kvm->arch.msr_filter.ranges[i].bitmap); | |
c761159c PX |
10558 | kvm_pic_destroy(kvm); |
10559 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 10560 | kvm_free_vcpus(kvm); |
af1bae54 | 10561 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 10562 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 10563 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 10564 | kvm_page_track_cleanup(kvm); |
cbc0236a | 10565 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 10566 | } |
0de10343 | 10567 | |
e96c81ee | 10568 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
db3fe4eb TY |
10569 | { |
10570 | int i; | |
10571 | ||
d89cc617 | 10572 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
10573 | kvfree(slot->arch.rmap[i]); |
10574 | slot->arch.rmap[i] = NULL; | |
10575 | ||
d89cc617 TY |
10576 | if (i == 0) |
10577 | continue; | |
10578 | ||
e96c81ee SC |
10579 | kvfree(slot->arch.lpage_info[i - 1]); |
10580 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb | 10581 | } |
21ebbeda | 10582 | |
e96c81ee | 10583 | kvm_page_track_free_memslot(slot); |
db3fe4eb TY |
10584 | } |
10585 | ||
0dab98b7 SC |
10586 | static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot, |
10587 | unsigned long npages) | |
db3fe4eb TY |
10588 | { |
10589 | int i; | |
10590 | ||
edd4fa37 SC |
10591 | /* |
10592 | * Clear out the previous array pointers for the KVM_MR_MOVE case. The | |
10593 | * old arrays will be freed by __kvm_set_memory_region() if installing | |
10594 | * the new memslot is successful. | |
10595 | */ | |
10596 | memset(&slot->arch, 0, sizeof(slot->arch)); | |
10597 | ||
d89cc617 | 10598 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
92f94f1e | 10599 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
10600 | unsigned long ugfn; |
10601 | int lpages; | |
d89cc617 | 10602 | int level = i + 1; |
db3fe4eb TY |
10603 | |
10604 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
10605 | slot->base_gfn, level) + 1; | |
10606 | ||
d89cc617 | 10607 | slot->arch.rmap[i] = |
778e1cdd | 10608 | kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), |
254272ce | 10609 | GFP_KERNEL_ACCOUNT); |
d89cc617 | 10610 | if (!slot->arch.rmap[i]) |
77d11309 | 10611 | goto out_free; |
d89cc617 TY |
10612 | if (i == 0) |
10613 | continue; | |
77d11309 | 10614 | |
254272ce | 10615 | linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 10616 | if (!linfo) |
db3fe4eb TY |
10617 | goto out_free; |
10618 | ||
92f94f1e XG |
10619 | slot->arch.lpage_info[i - 1] = linfo; |
10620 | ||
db3fe4eb | 10621 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 10622 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 10623 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 10624 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
10625 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
10626 | /* | |
10627 | * If the gfn and userspace address are not aligned wrt each | |
600087b6 | 10628 | * other, disable large page support for this slot. |
db3fe4eb | 10629 | */ |
600087b6 | 10630 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { |
db3fe4eb TY |
10631 | unsigned long j; |
10632 | ||
10633 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 10634 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
10635 | } |
10636 | } | |
10637 | ||
21ebbeda XG |
10638 | if (kvm_page_track_create_memslot(slot, npages)) |
10639 | goto out_free; | |
10640 | ||
db3fe4eb TY |
10641 | return 0; |
10642 | ||
10643 | out_free: | |
d89cc617 | 10644 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 10645 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
10646 | slot->arch.rmap[i] = NULL; |
10647 | if (i == 0) | |
10648 | continue; | |
10649 | ||
548ef284 | 10650 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 10651 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
10652 | } |
10653 | return -ENOMEM; | |
10654 | } | |
10655 | ||
15248258 | 10656 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 10657 | { |
91724814 BO |
10658 | struct kvm_vcpu *vcpu; |
10659 | int i; | |
10660 | ||
e6dff7d1 TY |
10661 | /* |
10662 | * memslots->generation has been incremented. | |
10663 | * mmio generation may have reached its maximum value. | |
10664 | */ | |
15248258 | 10665 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
10666 | |
10667 | /* Force re-initialization of steal_time cache */ | |
10668 | kvm_for_each_vcpu(i, vcpu, kvm) | |
10669 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
10670 | } |
10671 | ||
f7784b8e MT |
10672 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
10673 | struct kvm_memory_slot *memslot, | |
09170a49 | 10674 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 10675 | enum kvm_mr_change change) |
0de10343 | 10676 | { |
0dab98b7 SC |
10677 | if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) |
10678 | return kvm_alloc_memslot_metadata(memslot, | |
10679 | mem->memory_size >> PAGE_SHIFT); | |
f7784b8e MT |
10680 | return 0; |
10681 | } | |
10682 | ||
88178fd4 | 10683 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
3741679b AY |
10684 | struct kvm_memory_slot *old, |
10685 | struct kvm_memory_slot *new, | |
10686 | enum kvm_mr_change change) | |
88178fd4 | 10687 | { |
3741679b AY |
10688 | /* |
10689 | * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot. | |
10690 | * See comments below. | |
10691 | */ | |
10692 | if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) | |
88178fd4 | 10693 | return; |
88178fd4 KH |
10694 | |
10695 | /* | |
3741679b AY |
10696 | * Dirty logging tracks sptes in 4k granularity, meaning that large |
10697 | * sptes have to be split. If live migration is successful, the guest | |
10698 | * in the source machine will be destroyed and large sptes will be | |
10699 | * created in the destination. However, if the guest continues to run | |
10700 | * in the source machine (for example if live migration fails), small | |
10701 | * sptes will remain around and cause bad performance. | |
88178fd4 | 10702 | * |
3741679b AY |
10703 | * Scan sptes if dirty logging has been stopped, dropping those |
10704 | * which can be collapsed into a single large-page spte. Later | |
10705 | * page faults will create the large-page sptes. | |
88178fd4 | 10706 | * |
3741679b AY |
10707 | * There is no need to do this in any of the following cases: |
10708 | * CREATE: No dirty mappings will already exist. | |
10709 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
10710 | * kvm_arch_flush_shadow_memslot() | |
10711 | */ | |
10712 | if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) && | |
10713 | !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
10714 | kvm_mmu_zap_collapsible_sptes(kvm, new); | |
10715 | ||
10716 | /* | |
10717 | * Enable or disable dirty logging for the slot. | |
88178fd4 | 10718 | * |
3741679b AY |
10719 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old |
10720 | * slot have been zapped so no dirty logging updates are needed for | |
10721 | * the old slot. | |
10722 | * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible | |
10723 | * any mappings that might be created in it will consume the | |
10724 | * properties of the new slot and do not need to be updated here. | |
88178fd4 | 10725 | * |
3741679b AY |
10726 | * When PML is enabled, the kvm_x86_ops dirty logging hooks are |
10727 | * called to enable/disable dirty logging. | |
88178fd4 | 10728 | * |
3741679b AY |
10729 | * When disabling dirty logging with PML enabled, the D-bit is set |
10730 | * for sptes in the slot in order to prevent unnecessary GPA | |
10731 | * logging in the PML buffer (and potential PML buffer full VMEXIT). | |
10732 | * This guarantees leaving PML enabled for the guest's lifetime | |
10733 | * won't have any additional overhead from PML when the guest is | |
10734 | * running with dirty logging disabled. | |
88178fd4 | 10735 | * |
3741679b AY |
10736 | * When enabling dirty logging, large sptes are write-protected |
10737 | * so they can be split on first write. New large sptes cannot | |
10738 | * be created for this slot until the end of the logging. | |
88178fd4 | 10739 | * See the comments in fast_page_fault(). |
3741679b AY |
10740 | * For small sptes, nothing is done if the dirty log is in the |
10741 | * initial-all-set state. Otherwise, depending on whether pml | |
10742 | * is enabled the D-bit or the W-bit will be cleared. | |
88178fd4 KH |
10743 | */ |
10744 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
afaf0b2f SC |
10745 | if (kvm_x86_ops.slot_enable_log_dirty) { |
10746 | kvm_x86_ops.slot_enable_log_dirty(kvm, new); | |
3c9bd400 JZ |
10747 | } else { |
10748 | int level = | |
10749 | kvm_dirty_log_manual_protect_and_init_set(kvm) ? | |
3bae0459 | 10750 | PG_LEVEL_2M : PG_LEVEL_4K; |
3c9bd400 JZ |
10751 | |
10752 | /* | |
10753 | * If we're with initial-all-set, we don't need | |
10754 | * to write protect any small page because | |
10755 | * they're reported as dirty already. However | |
10756 | * we still need to write-protect huge pages | |
10757 | * so that the page split can happen lazily on | |
10758 | * the first write to the huge page. | |
10759 | */ | |
10760 | kvm_mmu_slot_remove_write_access(kvm, new, level); | |
10761 | } | |
88178fd4 | 10762 | } else { |
afaf0b2f SC |
10763 | if (kvm_x86_ops.slot_disable_log_dirty) |
10764 | kvm_x86_ops.slot_disable_log_dirty(kvm, new); | |
88178fd4 KH |
10765 | } |
10766 | } | |
10767 | ||
f7784b8e | 10768 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 10769 | const struct kvm_userspace_memory_region *mem, |
9d4c197c | 10770 | struct kvm_memory_slot *old, |
f36f3f28 | 10771 | const struct kvm_memory_slot *new, |
8482644a | 10772 | enum kvm_mr_change change) |
f7784b8e | 10773 | { |
48c0e4e9 | 10774 | if (!kvm->arch.n_requested_mmu_pages) |
4d66623c WY |
10775 | kvm_mmu_change_mmu_pages(kvm, |
10776 | kvm_mmu_calculate_default_mmu_pages(kvm)); | |
1c91cad4 | 10777 | |
3ea3b7fa | 10778 | /* |
f36f3f28 | 10779 | * FIXME: const-ify all uses of struct kvm_memory_slot. |
c972f3b1 | 10780 | */ |
3741679b | 10781 | kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change); |
21198846 SC |
10782 | |
10783 | /* Free the arrays associated with the old memslot. */ | |
10784 | if (change == KVM_MR_MOVE) | |
e96c81ee | 10785 | kvm_arch_free_memslot(kvm, old); |
0de10343 | 10786 | } |
1d737c8a | 10787 | |
2df72e9b | 10788 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 10789 | { |
7390de1e | 10790 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
10791 | } |
10792 | ||
2df72e9b MT |
10793 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
10794 | struct kvm_memory_slot *slot) | |
10795 | { | |
ae7cd873 | 10796 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
10797 | } |
10798 | ||
e6c67d8c LA |
10799 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
10800 | { | |
10801 | return (is_guest_mode(vcpu) && | |
afaf0b2f SC |
10802 | kvm_x86_ops.guest_apic_has_interrupt && |
10803 | kvm_x86_ops.guest_apic_has_interrupt(vcpu)); | |
e6c67d8c LA |
10804 | } |
10805 | ||
5d9bc648 PB |
10806 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
10807 | { | |
10808 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
10809 | return true; | |
10810 | ||
10811 | if (kvm_apic_has_events(vcpu)) | |
10812 | return true; | |
10813 | ||
10814 | if (vcpu->arch.pv.pv_unhalted) | |
10815 | return true; | |
10816 | ||
a5f01f8e WL |
10817 | if (vcpu->arch.exception.pending) |
10818 | return true; | |
10819 | ||
47a66eed Z |
10820 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
10821 | (vcpu->arch.nmi_pending && | |
c300ab9f | 10822 | kvm_x86_ops.nmi_allowed(vcpu, false))) |
5d9bc648 PB |
10823 | return true; |
10824 | ||
47a66eed | 10825 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
a9fa7cb6 | 10826 | (vcpu->arch.smi_pending && |
c300ab9f | 10827 | kvm_x86_ops.smi_allowed(vcpu, false))) |
73917739 PB |
10828 | return true; |
10829 | ||
5d9bc648 | 10830 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
10831 | (kvm_cpu_has_interrupt(vcpu) || |
10832 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
10833 | return true; |
10834 | ||
1f4b34f8 AS |
10835 | if (kvm_hv_has_stimer_pending(vcpu)) |
10836 | return true; | |
10837 | ||
d2060bd4 SC |
10838 | if (is_guest_mode(vcpu) && |
10839 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
10840 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
10841 | return true; | |
10842 | ||
5d9bc648 PB |
10843 | return false; |
10844 | } | |
10845 | ||
1d737c8a ZX |
10846 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
10847 | { | |
5d9bc648 | 10848 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 10849 | } |
5736199a | 10850 | |
17e433b5 WL |
10851 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
10852 | { | |
10853 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
10854 | return true; | |
10855 | ||
10856 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
10857 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
10858 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
10859 | return true; | |
10860 | ||
afaf0b2f | 10861 | if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu)) |
17e433b5 WL |
10862 | return true; |
10863 | ||
10864 | return false; | |
10865 | } | |
10866 | ||
199b5763 LM |
10867 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
10868 | { | |
de63ad4c | 10869 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
10870 | } |
10871 | ||
b6d33834 | 10872 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 10873 | { |
b6d33834 | 10874 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 10875 | } |
78646121 GN |
10876 | |
10877 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
10878 | { | |
c300ab9f | 10879 | return kvm_x86_ops.interrupt_allowed(vcpu, false); |
78646121 | 10880 | } |
229456fc | 10881 | |
82b32774 | 10882 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 10883 | { |
7ed9abfe TL |
10884 | /* Can't read the RIP when guest state is protected, just return 0 */ |
10885 | if (vcpu->arch.guest_state_protected) | |
10886 | return 0; | |
10887 | ||
82b32774 NA |
10888 | if (is_64_bit_mode(vcpu)) |
10889 | return kvm_rip_read(vcpu); | |
10890 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
10891 | kvm_rip_read(vcpu)); | |
10892 | } | |
10893 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 10894 | |
82b32774 NA |
10895 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
10896 | { | |
10897 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
10898 | } |
10899 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
10900 | ||
94fe45da JK |
10901 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
10902 | { | |
10903 | unsigned long rflags; | |
10904 | ||
afaf0b2f | 10905 | rflags = kvm_x86_ops.get_rflags(vcpu); |
94fe45da | 10906 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
c310bac5 | 10907 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
10908 | return rflags; |
10909 | } | |
10910 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
10911 | ||
6addfc42 | 10912 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
10913 | { |
10914 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 10915 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 10916 | rflags |= X86_EFLAGS_TF; |
afaf0b2f | 10917 | kvm_x86_ops.set_rflags(vcpu, rflags); |
6addfc42 PB |
10918 | } |
10919 | ||
10920 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
10921 | { | |
10922 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 10923 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
10924 | } |
10925 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
10926 | ||
56028d08 GN |
10927 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
10928 | { | |
10929 | int r; | |
10930 | ||
44dd3ffa | 10931 | if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || |
f2e10669 | 10932 | work->wakeup_all) |
56028d08 GN |
10933 | return; |
10934 | ||
10935 | r = kvm_mmu_reload(vcpu); | |
10936 | if (unlikely(r)) | |
10937 | return; | |
10938 | ||
44dd3ffa | 10939 | if (!vcpu->arch.mmu->direct_map && |
d8dd54e0 | 10940 | work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) |
fb67e14f XG |
10941 | return; |
10942 | ||
7a02674d | 10943 | kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); |
56028d08 GN |
10944 | } |
10945 | ||
af585b92 GN |
10946 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
10947 | { | |
dd03bcaa PX |
10948 | BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); |
10949 | ||
af585b92 GN |
10950 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); |
10951 | } | |
10952 | ||
10953 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
10954 | { | |
dd03bcaa | 10955 | return (key + 1) & (ASYNC_PF_PER_VCPU - 1); |
af585b92 GN |
10956 | } |
10957 | ||
10958 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10959 | { | |
10960 | u32 key = kvm_async_pf_hash_fn(gfn); | |
10961 | ||
10962 | while (vcpu->arch.apf.gfns[key] != ~0) | |
10963 | key = kvm_async_pf_next_probe(key); | |
10964 | ||
10965 | vcpu->arch.apf.gfns[key] = gfn; | |
10966 | } | |
10967 | ||
10968 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10969 | { | |
10970 | int i; | |
10971 | u32 key = kvm_async_pf_hash_fn(gfn); | |
10972 | ||
dd03bcaa | 10973 | for (i = 0; i < ASYNC_PF_PER_VCPU && |
c7d28c24 XG |
10974 | (vcpu->arch.apf.gfns[key] != gfn && |
10975 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
10976 | key = kvm_async_pf_next_probe(key); |
10977 | ||
10978 | return key; | |
10979 | } | |
10980 | ||
10981 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10982 | { | |
10983 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
10984 | } | |
10985 | ||
10986 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10987 | { | |
10988 | u32 i, j, k; | |
10989 | ||
10990 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
0fd46044 PX |
10991 | |
10992 | if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) | |
10993 | return; | |
10994 | ||
af585b92 GN |
10995 | while (true) { |
10996 | vcpu->arch.apf.gfns[i] = ~0; | |
10997 | do { | |
10998 | j = kvm_async_pf_next_probe(j); | |
10999 | if (vcpu->arch.apf.gfns[j] == ~0) | |
11000 | return; | |
11001 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
11002 | /* | |
11003 | * k lies cyclically in ]i,j] | |
11004 | * | i.k.j | | |
11005 | * |....j i.k.| or |.k..j i...| | |
11006 | */ | |
11007 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
11008 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
11009 | i = j; | |
11010 | } | |
11011 | } | |
11012 | ||
68fd66f1 | 11013 | static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) |
7c90705b | 11014 | { |
68fd66f1 VK |
11015 | u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; |
11016 | ||
11017 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, | |
11018 | sizeof(reason)); | |
11019 | } | |
11020 | ||
11021 | static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) | |
11022 | { | |
2635b5c4 | 11023 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); |
4e335d9e | 11024 | |
2635b5c4 VK |
11025 | return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, |
11026 | &token, offset, sizeof(token)); | |
11027 | } | |
11028 | ||
11029 | static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) | |
11030 | { | |
11031 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); | |
11032 | u32 val; | |
11033 | ||
11034 | if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, | |
11035 | &val, offset, sizeof(val))) | |
11036 | return false; | |
11037 | ||
11038 | return !val; | |
7c90705b GN |
11039 | } |
11040 | ||
1dfdb45e PB |
11041 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
11042 | { | |
11043 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) | |
11044 | return false; | |
11045 | ||
2635b5c4 VK |
11046 | if (!kvm_pv_async_pf_enabled(vcpu) || |
11047 | (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0)) | |
1dfdb45e PB |
11048 | return false; |
11049 | ||
11050 | return true; | |
11051 | } | |
11052 | ||
11053 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
11054 | { | |
11055 | if (unlikely(!lapic_in_kernel(vcpu) || | |
11056 | kvm_event_needs_reinjection(vcpu) || | |
11057 | vcpu->arch.exception.pending)) | |
11058 | return false; | |
11059 | ||
11060 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
11061 | return false; | |
11062 | ||
11063 | /* | |
11064 | * If interrupts are off we cannot even use an artificial | |
11065 | * halt state. | |
11066 | */ | |
c300ab9f | 11067 | return kvm_arch_interrupt_allowed(vcpu); |
1dfdb45e PB |
11068 | } |
11069 | ||
2a18b7e7 | 11070 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
11071 | struct kvm_async_pf *work) |
11072 | { | |
6389ee94 AK |
11073 | struct x86_exception fault; |
11074 | ||
736c291c | 11075 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 11076 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 11077 | |
1dfdb45e | 11078 | if (kvm_can_deliver_async_pf(vcpu) && |
68fd66f1 | 11079 | !apf_put_user_notpresent(vcpu)) { |
6389ee94 AK |
11080 | fault.vector = PF_VECTOR; |
11081 | fault.error_code_valid = true; | |
11082 | fault.error_code = 0; | |
11083 | fault.nested_page_fault = false; | |
11084 | fault.address = work->arch.token; | |
adfe20fb | 11085 | fault.async_page_fault = true; |
6389ee94 | 11086 | kvm_inject_page_fault(vcpu, &fault); |
2a18b7e7 | 11087 | return true; |
1dfdb45e PB |
11088 | } else { |
11089 | /* | |
11090 | * It is not possible to deliver a paravirtualized asynchronous | |
11091 | * page fault, but putting the guest in an artificial halt state | |
11092 | * can be beneficial nevertheless: if an interrupt arrives, we | |
11093 | * can deliver it timely and perhaps the guest will schedule | |
11094 | * another process. When the instruction that triggered a page | |
11095 | * fault is retried, hopefully the page will be ready in the host. | |
11096 | */ | |
11097 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2a18b7e7 | 11098 | return false; |
7c90705b | 11099 | } |
af585b92 GN |
11100 | } |
11101 | ||
11102 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
11103 | struct kvm_async_pf *work) | |
11104 | { | |
2635b5c4 VK |
11105 | struct kvm_lapic_irq irq = { |
11106 | .delivery_mode = APIC_DM_FIXED, | |
11107 | .vector = vcpu->arch.apf.vec | |
11108 | }; | |
6389ee94 | 11109 | |
f2e10669 | 11110 | if (work->wakeup_all) |
7c90705b GN |
11111 | work->arch.token = ~0; /* broadcast wakeup */ |
11112 | else | |
11113 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 11114 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 11115 | |
2a18b7e7 VK |
11116 | if ((work->wakeup_all || work->notpresent_injected) && |
11117 | kvm_pv_async_pf_enabled(vcpu) && | |
557a961a VK |
11118 | !apf_put_user_ready(vcpu, work->arch.token)) { |
11119 | vcpu->arch.apf.pageready_pending = true; | |
2635b5c4 | 11120 | kvm_apic_set_irq(vcpu, &irq, NULL); |
557a961a | 11121 | } |
2635b5c4 | 11122 | |
e6d53e3b | 11123 | vcpu->arch.apf.halted = false; |
a4fa1635 | 11124 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
11125 | } |
11126 | ||
557a961a VK |
11127 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) |
11128 | { | |
11129 | kvm_make_request(KVM_REQ_APF_READY, vcpu); | |
11130 | if (!vcpu->arch.apf.pageready_pending) | |
11131 | kvm_vcpu_kick(vcpu); | |
11132 | } | |
11133 | ||
7c0ade6c | 11134 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) |
7c90705b | 11135 | { |
2635b5c4 | 11136 | if (!kvm_pv_async_pf_enabled(vcpu)) |
7c90705b GN |
11137 | return true; |
11138 | else | |
2635b5c4 | 11139 | return apf_pageready_slot_free(vcpu); |
af585b92 GN |
11140 | } |
11141 | ||
5544eb9b PB |
11142 | void kvm_arch_start_assignment(struct kvm *kvm) |
11143 | { | |
11144 | atomic_inc(&kvm->arch.assigned_device_count); | |
11145 | } | |
11146 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
11147 | ||
11148 | void kvm_arch_end_assignment(struct kvm *kvm) | |
11149 | { | |
11150 | atomic_dec(&kvm->arch.assigned_device_count); | |
11151 | } | |
11152 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
11153 | ||
11154 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
11155 | { | |
11156 | return atomic_read(&kvm->arch.assigned_device_count); | |
11157 | } | |
11158 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
11159 | ||
e0f0bbc5 AW |
11160 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
11161 | { | |
11162 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
11163 | } | |
11164 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
11165 | ||
11166 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
11167 | { | |
11168 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
11169 | } | |
11170 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
11171 | ||
11172 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
11173 | { | |
11174 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
11175 | } | |
11176 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
11177 | ||
14717e20 AW |
11178 | bool kvm_arch_has_irq_bypass(void) |
11179 | { | |
92735b1b | 11180 | return true; |
14717e20 AW |
11181 | } |
11182 | ||
87276880 FW |
11183 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
11184 | struct irq_bypass_producer *prod) | |
11185 | { | |
11186 | struct kvm_kernel_irqfd *irqfd = | |
11187 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
2edd9cb7 | 11188 | int ret; |
87276880 | 11189 | |
14717e20 | 11190 | irqfd->producer = prod; |
2edd9cb7 ZL |
11191 | kvm_arch_start_assignment(irqfd->kvm); |
11192 | ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, | |
11193 | prod->irq, irqfd->gsi, 1); | |
11194 | ||
11195 | if (ret) | |
11196 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 | 11197 | |
2edd9cb7 | 11198 | return ret; |
87276880 FW |
11199 | } |
11200 | ||
11201 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
11202 | struct irq_bypass_producer *prod) | |
11203 | { | |
11204 | int ret; | |
11205 | struct kvm_kernel_irqfd *irqfd = | |
11206 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
11207 | ||
87276880 FW |
11208 | WARN_ON(irqfd->producer != prod); |
11209 | irqfd->producer = NULL; | |
11210 | ||
11211 | /* | |
11212 | * When producer of consumer is unregistered, we change back to | |
11213 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 11214 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
11215 | * int this case doesn't want to receive the interrupts. |
11216 | */ | |
afaf0b2f | 11217 | ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); |
87276880 FW |
11218 | if (ret) |
11219 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
11220 | " fails: %d\n", irqfd->consumer.token, ret); | |
2edd9cb7 ZL |
11221 | |
11222 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 FW |
11223 | } |
11224 | ||
11225 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
11226 | uint32_t guest_irq, bool set) | |
11227 | { | |
afaf0b2f | 11228 | return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set); |
87276880 FW |
11229 | } |
11230 | ||
52004014 FW |
11231 | bool kvm_vector_hashing_enabled(void) |
11232 | { | |
11233 | return vector_hashing; | |
11234 | } | |
52004014 | 11235 | |
2d5ba19b MT |
11236 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
11237 | { | |
11238 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
11239 | } | |
11240 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
11241 | ||
841c2be0 ML |
11242 | |
11243 | int kvm_spec_ctrl_test_value(u64 value) | |
6441fa61 | 11244 | { |
841c2be0 ML |
11245 | /* |
11246 | * test that setting IA32_SPEC_CTRL to given value | |
11247 | * is allowed by the host processor | |
11248 | */ | |
6441fa61 | 11249 | |
841c2be0 ML |
11250 | u64 saved_value; |
11251 | unsigned long flags; | |
11252 | int ret = 0; | |
6441fa61 | 11253 | |
841c2be0 | 11254 | local_irq_save(flags); |
6441fa61 | 11255 | |
841c2be0 ML |
11256 | if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) |
11257 | ret = 1; | |
11258 | else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) | |
11259 | ret = 1; | |
11260 | else | |
11261 | wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); | |
6441fa61 | 11262 | |
841c2be0 | 11263 | local_irq_restore(flags); |
6441fa61 | 11264 | |
841c2be0 | 11265 | return ret; |
6441fa61 | 11266 | } |
841c2be0 | 11267 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); |
2d5ba19b | 11268 | |
89786147 MG |
11269 | void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) |
11270 | { | |
11271 | struct x86_exception fault; | |
19cf4b7e PB |
11272 | u32 access = error_code & |
11273 | (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); | |
89786147 MG |
11274 | |
11275 | if (!(error_code & PFERR_PRESENT_MASK) || | |
19cf4b7e | 11276 | vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { |
89786147 MG |
11277 | /* |
11278 | * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page | |
11279 | * tables probably do not match the TLB. Just proceed | |
11280 | * with the error code that the processor gave. | |
11281 | */ | |
11282 | fault.vector = PF_VECTOR; | |
11283 | fault.error_code_valid = true; | |
11284 | fault.error_code = error_code; | |
11285 | fault.nested_page_fault = false; | |
11286 | fault.address = gva; | |
11287 | } | |
11288 | vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); | |
6441fa61 | 11289 | } |
89786147 | 11290 | EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); |
2d5ba19b | 11291 | |
3f3393b3 BM |
11292 | /* |
11293 | * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns | |
11294 | * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value | |
11295 | * indicates whether exit to userspace is needed. | |
11296 | */ | |
11297 | int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, | |
11298 | struct x86_exception *e) | |
11299 | { | |
11300 | if (r == X86EMUL_PROPAGATE_FAULT) { | |
11301 | kvm_inject_emulated_page_fault(vcpu, e); | |
11302 | return 1; | |
11303 | } | |
11304 | ||
11305 | /* | |
11306 | * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED | |
11307 | * while handling a VMX instruction KVM could've handled the request | |
11308 | * correctly by exiting to userspace and performing I/O but there | |
11309 | * doesn't seem to be a real use-case behind such requests, just return | |
11310 | * KVM_EXIT_INTERNAL_ERROR for now. | |
11311 | */ | |
11312 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
11313 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
11314 | vcpu->run->internal.ndata = 0; | |
11315 | ||
11316 | return 0; | |
11317 | } | |
11318 | EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); | |
11319 | ||
9715092f BM |
11320 | int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) |
11321 | { | |
11322 | bool pcid_enabled; | |
11323 | struct x86_exception e; | |
11324 | unsigned i; | |
11325 | unsigned long roots_to_free = 0; | |
11326 | struct { | |
11327 | u64 pcid; | |
11328 | u64 gla; | |
11329 | } operand; | |
11330 | int r; | |
11331 | ||
11332 | r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); | |
11333 | if (r != X86EMUL_CONTINUE) | |
11334 | return kvm_handle_memory_failure(vcpu, r, &e); | |
11335 | ||
11336 | if (operand.pcid >> 12 != 0) { | |
11337 | kvm_inject_gp(vcpu, 0); | |
11338 | return 1; | |
11339 | } | |
11340 | ||
11341 | pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); | |
11342 | ||
11343 | switch (type) { | |
11344 | case INVPCID_TYPE_INDIV_ADDR: | |
11345 | if ((!pcid_enabled && (operand.pcid != 0)) || | |
11346 | is_noncanonical_address(operand.gla, vcpu)) { | |
11347 | kvm_inject_gp(vcpu, 0); | |
11348 | return 1; | |
11349 | } | |
11350 | kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); | |
11351 | return kvm_skip_emulated_instruction(vcpu); | |
11352 | ||
11353 | case INVPCID_TYPE_SINGLE_CTXT: | |
11354 | if (!pcid_enabled && (operand.pcid != 0)) { | |
11355 | kvm_inject_gp(vcpu, 0); | |
11356 | return 1; | |
11357 | } | |
11358 | ||
11359 | if (kvm_get_active_pcid(vcpu) == operand.pcid) { | |
11360 | kvm_mmu_sync_roots(vcpu); | |
11361 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
11362 | } | |
11363 | ||
11364 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
11365 | if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd) | |
11366 | == operand.pcid) | |
11367 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
11368 | ||
11369 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); | |
11370 | /* | |
11371 | * If neither the current cr3 nor any of the prev_roots use the | |
11372 | * given PCID, then nothing needs to be done here because a | |
11373 | * resync will happen anyway before switching to any other CR3. | |
11374 | */ | |
11375 | ||
11376 | return kvm_skip_emulated_instruction(vcpu); | |
11377 | ||
11378 | case INVPCID_TYPE_ALL_NON_GLOBAL: | |
11379 | /* | |
11380 | * Currently, KVM doesn't mark global entries in the shadow | |
11381 | * page tables, so a non-global flush just degenerates to a | |
11382 | * global flush. If needed, we could optimize this later by | |
11383 | * keeping track of global entries in shadow page tables. | |
11384 | */ | |
11385 | ||
11386 | fallthrough; | |
11387 | case INVPCID_TYPE_ALL_INCL_GLOBAL: | |
11388 | kvm_mmu_unload(vcpu); | |
11389 | return kvm_skip_emulated_instruction(vcpu); | |
11390 | ||
11391 | default: | |
11392 | BUG(); /* We have already checked above that type <= 3 */ | |
11393 | } | |
11394 | } | |
11395 | EXPORT_SYMBOL_GPL(kvm_handle_invpcid); | |
11396 | ||
8f423a80 TL |
11397 | static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) |
11398 | { | |
11399 | struct kvm_run *run = vcpu->run; | |
11400 | struct kvm_mmio_fragment *frag; | |
11401 | unsigned int len; | |
11402 | ||
11403 | BUG_ON(!vcpu->mmio_needed); | |
11404 | ||
11405 | /* Complete previous fragment */ | |
11406 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; | |
11407 | len = min(8u, frag->len); | |
11408 | if (!vcpu->mmio_is_write) | |
11409 | memcpy(frag->data, run->mmio.data, len); | |
11410 | ||
11411 | if (frag->len <= 8) { | |
11412 | /* Switch to the next fragment. */ | |
11413 | frag++; | |
11414 | vcpu->mmio_cur_fragment++; | |
11415 | } else { | |
11416 | /* Go forward to the next mmio piece. */ | |
11417 | frag->data += len; | |
11418 | frag->gpa += len; | |
11419 | frag->len -= len; | |
11420 | } | |
11421 | ||
11422 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { | |
11423 | vcpu->mmio_needed = 0; | |
11424 | ||
11425 | // VMG change, at this point, we're always done | |
11426 | // RIP has already been advanced | |
11427 | return 1; | |
11428 | } | |
11429 | ||
11430 | // More MMIO is needed | |
11431 | run->mmio.phys_addr = frag->gpa; | |
11432 | run->mmio.len = min(8u, frag->len); | |
11433 | run->mmio.is_write = vcpu->mmio_is_write; | |
11434 | if (run->mmio.is_write) | |
11435 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); | |
11436 | run->exit_reason = KVM_EXIT_MMIO; | |
11437 | ||
11438 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
11439 | ||
11440 | return 0; | |
11441 | } | |
11442 | ||
11443 | int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
11444 | void *data) | |
11445 | { | |
11446 | int handled; | |
11447 | struct kvm_mmio_fragment *frag; | |
11448 | ||
11449 | if (!data) | |
11450 | return -EINVAL; | |
11451 | ||
11452 | handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
11453 | if (handled == bytes) | |
11454 | return 1; | |
11455 | ||
11456 | bytes -= handled; | |
11457 | gpa += handled; | |
11458 | data += handled; | |
11459 | ||
11460 | /*TODO: Check if need to increment number of frags */ | |
11461 | frag = vcpu->mmio_fragments; | |
11462 | vcpu->mmio_nr_fragments = 1; | |
11463 | frag->len = bytes; | |
11464 | frag->gpa = gpa; | |
11465 | frag->data = data; | |
11466 | ||
11467 | vcpu->mmio_needed = 1; | |
11468 | vcpu->mmio_cur_fragment = 0; | |
11469 | ||
11470 | vcpu->run->mmio.phys_addr = gpa; | |
11471 | vcpu->run->mmio.len = min(8u, frag->len); | |
11472 | vcpu->run->mmio.is_write = 1; | |
11473 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); | |
11474 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
11475 | ||
11476 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
11477 | ||
11478 | return 0; | |
11479 | } | |
11480 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); | |
11481 | ||
11482 | int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
11483 | void *data) | |
11484 | { | |
11485 | int handled; | |
11486 | struct kvm_mmio_fragment *frag; | |
11487 | ||
11488 | if (!data) | |
11489 | return -EINVAL; | |
11490 | ||
11491 | handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
11492 | if (handled == bytes) | |
11493 | return 1; | |
11494 | ||
11495 | bytes -= handled; | |
11496 | gpa += handled; | |
11497 | data += handled; | |
11498 | ||
11499 | /*TODO: Check if need to increment number of frags */ | |
11500 | frag = vcpu->mmio_fragments; | |
11501 | vcpu->mmio_nr_fragments = 1; | |
11502 | frag->len = bytes; | |
11503 | frag->gpa = gpa; | |
11504 | frag->data = data; | |
11505 | ||
11506 | vcpu->mmio_needed = 1; | |
11507 | vcpu->mmio_cur_fragment = 0; | |
11508 | ||
11509 | vcpu->run->mmio.phys_addr = gpa; | |
11510 | vcpu->run->mmio.len = min(8u, frag->len); | |
11511 | vcpu->run->mmio.is_write = 0; | |
11512 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
11513 | ||
11514 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
11515 | ||
11516 | return 0; | |
11517 | } | |
11518 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); | |
11519 | ||
7ed9abfe TL |
11520 | static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) |
11521 | { | |
11522 | memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data, | |
11523 | vcpu->arch.pio.count * vcpu->arch.pio.size); | |
11524 | vcpu->arch.pio.count = 0; | |
11525 | ||
11526 | return 1; | |
11527 | } | |
11528 | ||
11529 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, | |
11530 | unsigned int port, void *data, unsigned int count) | |
11531 | { | |
11532 | int ret; | |
11533 | ||
11534 | ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port, | |
11535 | data, count); | |
11536 | if (ret) | |
11537 | return ret; | |
11538 | ||
11539 | vcpu->arch.pio.count = 0; | |
11540 | ||
11541 | return 0; | |
11542 | } | |
11543 | ||
11544 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, | |
11545 | unsigned int port, void *data, unsigned int count) | |
11546 | { | |
11547 | int ret; | |
11548 | ||
11549 | ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port, | |
11550 | data, count); | |
11551 | if (ret) { | |
11552 | vcpu->arch.pio.count = 0; | |
11553 | } else { | |
11554 | vcpu->arch.guest_ins_data = data; | |
11555 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; | |
11556 | } | |
11557 | ||
11558 | return 0; | |
11559 | } | |
11560 | ||
11561 | int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, | |
11562 | unsigned int port, void *data, unsigned int count, | |
11563 | int in) | |
11564 | { | |
11565 | return in ? kvm_sev_es_ins(vcpu, size, port, data, count) | |
11566 | : kvm_sev_es_outs(vcpu, size, port, data, count); | |
11567 | } | |
11568 | EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); | |
11569 | ||
d95df951 | 11570 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); |
229456fc | 11571 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 11572 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
11573 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
11574 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
11575 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
11576 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 11577 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 11578 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 11579 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 11580 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 11581 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 11582 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 11583 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 11584 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 11585 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 11586 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 11587 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 11588 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
11589 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
11590 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
ab56f8e6 | 11591 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); |
24bbf74c | 11592 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); |
d523ab6b TL |
11593 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); |
11594 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); | |
59e38b58 TL |
11595 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); |
11596 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); |