]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blame - arch/x86/kvm/x86.c
projects / mirror_ubuntu-focal-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
kvm: nVMX: Use nested_run_pending rather than from_vmentry
[mirror_ubuntu-focal-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
9ed96e87
MT		 117unsigned int min_timer_period_us = 500;
118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
141
52004014
FW		 142static bool __read_mostly vector_hashing = true;
143module_param(vector_hashing, bool, S_IRUGO);
144
c4ae60e4
LA		 145bool __read_mostly enable_vmware_backdoor = false;
146module_param(enable_vmware_backdoor, bool, S_IRUGO);
147EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
148
6c86eedc
WL		 149static bool __read_mostly force_emulation_prefix = false;
150module_param(force_emulation_prefix, bool, S_IRUGO);
151
18863bdd
AK		 152#define KVM_NR_SHARED_MSRS 16
153
154struct kvm_shared_msrs_global {
155 int nr;
2bf78fa7 156 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 157};
158
159struct kvm_shared_msrs {
160 struct user_return_notifier urn;
161 bool registered;
2bf78fa7
SY		 162 struct kvm_shared_msr_values {
163 u64 host;
164 u64 curr;
165 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 166};
167
168static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 169static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 170
417bc304 171struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 172 { "pf_fixed", VCPU_STAT(pf_fixed) },
173 { "pf_guest", VCPU_STAT(pf_guest) },
174 { "tlb_flush", VCPU_STAT(tlb_flush) },
175 { "invlpg", VCPU_STAT(invlpg) },
176 { "exits", VCPU_STAT(exits) },
177 { "io_exits", VCPU_STAT(io_exits) },
178 { "mmio_exits", VCPU_STAT(mmio_exits) },
179 { "signal_exits", VCPU_STAT(signal_exits) },
180 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 181 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 182 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 183 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 184 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 185 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 186 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 187 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 188 { "request_irq", VCPU_STAT(request_irq_exits) },
189 { "irq_exits", VCPU_STAT(irq_exits) },
190 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 191 { "fpu_reload", VCPU_STAT(fpu_reload) },
192 { "insn_emulation", VCPU_STAT(insn_emulation) },
193 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 194 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 195 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 196 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 197 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
198 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
199 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
200 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
201 { "mmu_flooded", VM_STAT(mmu_flooded) },
202 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 203 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 204 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 205 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 206 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 207 { "max_mmu_page_hash_collisions",
208 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 209 { NULL }
210};
211
2acf923e
DC		 212u64 __read_mostly host_xcr0;
213
b6785def 214static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 215
af585b92
GN		 216static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
217{
218 int i;
219 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
220 vcpu->arch.apf.gfns[i] = ~0;
221}
222
18863bdd
AK		 223static void kvm_on_user_return(struct user_return_notifier *urn)
224{
225 unsigned slot;
18863bdd
AK		 226 struct kvm_shared_msrs *locals
227 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 228 struct kvm_shared_msr_values *values;
1650b4eb
IA		 229 unsigned long flags;
230
231 /*
232 * Disabling irqs at this point since the following code could be
233 * interrupted and executed through kvm_arch_hardware_disable()
234 */
235 local_irq_save(flags);
236 if (locals->registered) {
237 locals->registered = false;
238 user_return_notifier_unregister(urn);
239 }
240 local_irq_restore(flags);
18863bdd 241 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 242 values = &locals->values[slot];
243 if (values->host != values->curr) {
244 wrmsrl(shared_msrs_global.msrs[slot], values->host);
245 values->curr = values->host;
18863bdd
AK		 246 }
247 }
18863bdd
AK		 248}
249
2bf78fa7 250static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 251{
18863bdd 252 u64 value;
013f6a5d
MT		 253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 255
2bf78fa7
SY		 256 /* only read, and nobody should modify it at this time,
257 * so don't need lock */
258 if (slot >= shared_msrs_global.nr) {
259 printk(KERN_ERR "kvm: invalid MSR slot!");
260 return;
261 }
262 rdmsrl_safe(msr, &value);
263 smsr->values[slot].host = value;
264 smsr->values[slot].curr = value;
265}
266
267void kvm_define_shared_msr(unsigned slot, u32 msr)
268{
0123be42 269 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 270 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 271 if (slot >= shared_msrs_global.nr)
272 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 273}
274EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
275
276static void kvm_shared_msr_cpu_online(void)
277{
278 unsigned i;
18863bdd
AK		 279
280 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 281 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 282}
283
8b3c3104 284int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 285{
013f6a5d
MT		 286 unsigned int cpu = smp_processor_id();
287 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 288 int err;
18863bdd 289
2bf78fa7 290 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 291 return 0;
2bf78fa7 292 smsr->values[slot].curr = value;
8b3c3104
AH		 293 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
294 if (err)
295 return 1;
296
18863bdd
AK		 297 if (!smsr->registered) {
298 smsr->urn.on_user_return = kvm_on_user_return;
299 user_return_notifier_register(&smsr->urn);
300 smsr->registered = true;
301 }
8b3c3104 302 return 0;
18863bdd
AK		 303}
304EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
305
13a34e06 306static void drop_user_return_notifiers(void)
3548bab5 307{
013f6a5d
MT		 308 unsigned int cpu = smp_processor_id();
309 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 310
311 if (smsr->registered)
312 kvm_on_user_return(&smsr->urn);
313}
314
6866b83e
CO		 315u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
316{
8a5a87d9 317 return vcpu->arch.apic_base;
6866b83e
CO		 318}
319EXPORT_SYMBOL_GPL(kvm_get_apic_base);
320
58871649
JM		 321enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
322{
323 return kvm_apic_mode(kvm_get_apic_base(vcpu));
324}
325EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
326
58cb628d
JK		 327int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
328{
58871649
JM		 329 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
330 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 331 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
332 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 333
58871649 334 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 335 return 1;
58871649
JM		 336 if (!msr_info->host_initiated) {
337 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
338 return 1;
339 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
340 return 1;
341 }
58cb628d
JK		 342
343 kvm_lapic_set_base(vcpu, msr_info->data);
344 return 0;
6866b83e
CO		 345}
346EXPORT_SYMBOL_GPL(kvm_set_apic_base);
347
2605fc21 348asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 349{
350 /* Fault while not rebooting. We want the trace. */
351 BUG();
352}
353EXPORT_SYMBOL_GPL(kvm_spurious_fault);
354
3fd28fce
ED		 355#define EXCPT_BENIGN 0
356#define EXCPT_CONTRIBUTORY 1
357#define EXCPT_PF 2
358
359static int exception_class(int vector)
360{
361 switch (vector) {
362 case PF_VECTOR:
363 return EXCPT_PF;
364 case DE_VECTOR:
365 case TS_VECTOR:
366 case NP_VECTOR:
367 case SS_VECTOR:
368 case GP_VECTOR:
369 return EXCPT_CONTRIBUTORY;
370 default:
371 break;
372 }
373 return EXCPT_BENIGN;
374}
375
d6e8c854
NA		 376#define EXCPT_FAULT 0
377#define EXCPT_TRAP 1
378#define EXCPT_ABORT 2
379#define EXCPT_INTERRUPT 3
380
381static int exception_type(int vector)
382{
383 unsigned int mask;
384
385 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
386 return EXCPT_INTERRUPT;
387
388 mask = 1 << vector;
389
390 /* #DB is trap, as instruction watchpoints are handled elsewhere */
391 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
392 return EXCPT_TRAP;
393
394 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
395 return EXCPT_ABORT;
396
397 /* Reserved exceptions will result in fault */
398 return EXCPT_FAULT;
399}
400
3fd28fce 401static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 402 unsigned nr, bool has_error, u32 error_code,
403 bool reinject)
3fd28fce
ED		 404{
405 u32 prev_nr;
406 int class1, class2;
407
3842d135
AK		 408 kvm_make_request(KVM_REQ_EVENT, vcpu);
409
664f8e26 410 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 411 queue:
3ffb2468
NA		 412 if (has_error && !is_protmode(vcpu))
413 has_error = false;
664f8e26
WL		 414 if (reinject) {
415 /*
416 * On vmentry, vcpu->arch.exception.pending is only
417 * true if an event injection was blocked by
418 * nested_run_pending. In that case, however,
419 * vcpu_enter_guest requests an immediate exit,
420 * and the guest shouldn't proceed far enough to
421 * need reinjection.
422 */
423 WARN_ON_ONCE(vcpu->arch.exception.pending);
424 vcpu->arch.exception.injected = true;
425 } else {
426 vcpu->arch.exception.pending = true;
427 vcpu->arch.exception.injected = false;
428 }
3fd28fce
ED		 429 vcpu->arch.exception.has_error_code = has_error;
430 vcpu->arch.exception.nr = nr;
431 vcpu->arch.exception.error_code = error_code;
432 return;
433 }
434
435 /* to check exception */
436 prev_nr = vcpu->arch.exception.nr;
437 if (prev_nr == DF_VECTOR) {
438 /* triple fault -> shutdown */
a8eeb04a 439 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 440 return;
441 }
442 class1 = exception_class(prev_nr);
443 class2 = exception_class(nr);
444 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
445 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 446 /*
447 * Generate double fault per SDM Table 5-5. Set
448 * exception.pending = true so that the double fault
449 * can trigger a nested vmexit.
450 */
3fd28fce 451 vcpu->arch.exception.pending = true;
664f8e26 452 vcpu->arch.exception.injected = false;
3fd28fce
ED		 453 vcpu->arch.exception.has_error_code = true;
454 vcpu->arch.exception.nr = DF_VECTOR;
455 vcpu->arch.exception.error_code = 0;
456 } else
457 /* replace previous exception with a new one in a hope
458 that instruction re-execution will regenerate lost
459 exception */
460 goto queue;
461}
462
298101da
AK		 463void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
464{
ce7ddec4 465 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 466}
467EXPORT_SYMBOL_GPL(kvm_queue_exception);
468
ce7ddec4
JR		 469void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
470{
471 kvm_multiple_exception(vcpu, nr, false, 0, true);
472}
473EXPORT_SYMBOL_GPL(kvm_requeue_exception);
474
6affcbed 475int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 476{
db8fcefa
AP		 477 if (err)
478 kvm_inject_gp(vcpu, 0);
479 else
6affcbed
KH		 480 return kvm_skip_emulated_instruction(vcpu);
481
482 return 1;
db8fcefa
AP		 483}
484EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 485
6389ee94 486void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 487{
488 ++vcpu->stat.pf_guest;
adfe20fb
WL		 489 vcpu->arch.exception.nested_apf =
490 is_guest_mode(vcpu) && fault->async_page_fault;
491 if (vcpu->arch.exception.nested_apf)
492 vcpu->arch.apf.nested_apf_token = fault->address;
493 else
494 vcpu->arch.cr2 = fault->address;
6389ee94 495 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 496}
27d6c865 497EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 498
ef54bcfe 499static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 500{
6389ee94
AK		 501 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
502 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 503 else
6389ee94 504 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 505
506 return fault->nested_page_fault;
d4f8cf66
JR		 507}
508
3419ffc8
SY		 509void kvm_inject_nmi(struct kvm_vcpu *vcpu)
510{
7460fb4a
AK		 511 atomic_inc(&vcpu->arch.nmi_queued);
512 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 513}
514EXPORT_SYMBOL_GPL(kvm_inject_nmi);
515
298101da
AK		 516void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
517{
ce7ddec4 518 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 519}
520EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
521
ce7ddec4
JR		 522void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
523{
524 kvm_multiple_exception(vcpu, nr, true, error_code, true);
525}
526EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
527
0a79b009
AK		 528/*
529 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
530 * a #GP and return false.
531 */
532bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 533{
0a79b009
AK		 534 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
535 return true;
536 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
537 return false;
298101da 538}
0a79b009 539EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 540
16f8a6f9
NA		 541bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
542{
543 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
544 return true;
545
546 kvm_queue_exception(vcpu, UD_VECTOR);
547 return false;
548}
549EXPORT_SYMBOL_GPL(kvm_require_dr);
550
ec92fe44
JR		 551/*
552 * This function will be used to read from the physical memory of the currently
54bf36aa 553 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 554 * can read from guest physical or from the guest's guest physical memory.
555 */
556int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
557 gfn_t ngfn, void *data, int offset, int len,
558 u32 access)
559{
54987b7a 560 struct x86_exception exception;
ec92fe44
JR		 561 gfn_t real_gfn;
562 gpa_t ngpa;
563
564 ngpa = gfn_to_gpa(ngfn);
54987b7a 565 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 566 if (real_gfn == UNMAPPED_GVA)
567 return -EFAULT;
568
569 real_gfn = gpa_to_gfn(real_gfn);
570
54bf36aa 571 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 572}
573EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
574
69b0049a 575static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 576 void *data, int offset, int len, u32 access)
577{
578 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
579 data, offset, len, access);
580}
581
a03490ed
CO		 582/*
583 * Load the pae pdptrs. Return true is they are all valid.
584 */
ff03a073 585int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 586{
587 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
588 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
589 int i;
590 int ret;
ff03a073 591 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 592
ff03a073
JR		 593 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
594 offset * sizeof(u64), sizeof(pdpte),
595 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 596 if (ret < 0) {
597 ret = 0;
598 goto out;
599 }
600 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 601 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 602 (pdpte[i] &
603 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 604 ret = 0;
605 goto out;
606 }
607 }
608 ret = 1;
609
ff03a073 610 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 611 __set_bit(VCPU_EXREG_PDPTR,
612 (unsigned long *)&vcpu->arch.regs_avail);
613 __set_bit(VCPU_EXREG_PDPTR,
614 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 615out:
a03490ed
CO		 616
617 return ret;
618}
cc4b6871 619EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 620
9ed38ffa 621bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 622{
ff03a073 623 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 624 bool changed = true;
3d06b8bf
JR		 625 int offset;
626 gfn_t gfn;
d835dfec
AK		 627 int r;
628
629 if (is_long_mode(vcpu) || !is_pae(vcpu))
630 return false;
631
6de4f3ad
AK		 632 if (!test_bit(VCPU_EXREG_PDPTR,
633 (unsigned long *)&vcpu->arch.regs_avail))
634 return true;
635
a512177e
PB		 636 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
637 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 638 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
639 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 640 if (r < 0)
641 goto out;
ff03a073 642 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 643out:
d835dfec
AK		 644
645 return changed;
646}
9ed38ffa 647EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 648
49a9b07e 649int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 650{
aad82703 651 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 652 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 653
f9a48e6a
AK		 654 cr0 |= X86_CR0_ET;
655
ab344828 656#ifdef CONFIG_X86_64
0f12244f
GN		 657 if (cr0 & 0xffffffff00000000UL)
658 return 1;
ab344828
GN		 659#endif
660
661 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 662
0f12244f
GN		 663 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
664 return 1;
a03490ed 665
0f12244f
GN		 666 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
667 return 1;
a03490ed
CO		 668
669 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
670#ifdef CONFIG_X86_64
f6801dff 671 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 672 int cs_db, cs_l;
673
0f12244f
GN		 674 if (!is_pae(vcpu))
675 return 1;
a03490ed 676 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 677 if (cs_l)
678 return 1;
a03490ed
CO		 679 } else
680#endif
ff03a073 681 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 682 kvm_read_cr3(vcpu)))
0f12244f 683 return 1;
a03490ed
CO		 684 }
685
ad756a16
MJ		 686 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
687 return 1;
688
a03490ed 689 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 690
d170c419 691 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 692 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 693 kvm_async_pf_hash_reset(vcpu);
694 }
e5f3f027 695
aad82703
SY		 696 if ((cr0 ^ old_cr0) & update_bits)
697 kvm_mmu_reset_context(vcpu);
b18d5431 698
879ae188
LE		 699 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
700 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
701 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 702 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
703
0f12244f
GN		 704 return 0;
705}
2d3ad1f4 706EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 707
2d3ad1f4 708void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 709{
49a9b07e 710 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 711}
2d3ad1f4 712EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 713
42bdf991
MT		 714static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
715{
716 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
717 !vcpu->guest_xcr0_loaded) {
718 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 719 if (vcpu->arch.xcr0 != host_xcr0)
720 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 721 vcpu->guest_xcr0_loaded = 1;
722 }
723}
724
725static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
726{
727 if (vcpu->guest_xcr0_loaded) {
728 if (vcpu->arch.xcr0 != host_xcr0)
729 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
730 vcpu->guest_xcr0_loaded = 0;
731 }
732}
733
69b0049a 734static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 735{
56c103ec
LJ		 736 u64 xcr0 = xcr;
737 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 738 u64 valid_bits;
2acf923e
DC		 739
740 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
741 if (index != XCR_XFEATURE_ENABLED_MASK)
742 return 1;
d91cab78 743 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 744 return 1;
d91cab78 745 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 746 return 1;
46c34cb0
PB		 747
748 /*
749 * Do not allow the guest to set bits that we do not support
750 * saving. However, xcr0 bit 0 is always set, even if the
751 * emulated CPU does not support XSAVE (see fx_init).
752 */
d91cab78 753 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 754 if (xcr0 & ~valid_bits)
2acf923e 755 return 1;
46c34cb0 756
d91cab78
DH		 757 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
758 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 759 return 1;
760
d91cab78
DH		 761 if (xcr0 & XFEATURE_MASK_AVX512) {
762 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 763 return 1;
d91cab78 764 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 765 return 1;
766 }
2acf923e 767 vcpu->arch.xcr0 = xcr0;
56c103ec 768
d91cab78 769 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 770 kvm_update_cpuid(vcpu);
2acf923e
DC		 771 return 0;
772}
773
774int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
775{
764bcbc5
Z		 776 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
777 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 778 kvm_inject_gp(vcpu, 0);
779 return 1;
780 }
781 return 0;
782}
783EXPORT_SYMBOL_GPL(kvm_set_xcr);
784
a83b29c6 785int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 786{
fc78f519 787 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 788 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 789 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 790
0f12244f
GN		 791 if (cr4 & CR4_RESERVED_BITS)
792 return 1;
a03490ed 793
d6321d49 794 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 795 return 1;
796
d6321d49 797 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 798 return 1;
799
d6321d49 800 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 801 return 1;
802
d6321d49 803 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 804 return 1;
805
d6321d49 806 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 807 return 1;
808
fd8cb433 809 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 810 return 1;
811
ae3e61e1
PB		 812 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
813 return 1;
814
a03490ed 815 if (is_long_mode(vcpu)) {
0f12244f
GN		 816 if (!(cr4 & X86_CR4_PAE))
817 return 1;
a2edf57f
AK		 818 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
819 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 820 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
821 kvm_read_cr3(vcpu)))
0f12244f
GN		 822 return 1;
823
ad756a16 824 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 825 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 826 return 1;
827
828 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
829 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
830 return 1;
831 }
832
5e1746d6 833 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 834 return 1;
a03490ed 835
ad756a16
MJ		 836 if (((cr4 ^ old_cr4) & pdptr_bits) ||
837 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 838 kvm_mmu_reset_context(vcpu);
0f12244f 839
b9baba86 840 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 841 kvm_update_cpuid(vcpu);
2acf923e 842
0f12244f
GN		 843 return 0;
844}
2d3ad1f4 845EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 846
2390218b 847int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 848{
ac146235 849#ifdef CONFIG_X86_64
c19986fe
JS		 850 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
851
852 if (pcid_enabled)
853 cr3 &= ~CR3_PCID_INVD;
ac146235 854#endif
9d88fca7 855
9f8fe504 856 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 857 kvm_mmu_sync_roots(vcpu);
77c3913b 858 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 859 return 0;
d835dfec
AK		 860 }
861
d1cd3ce9 862 if (is_long_mode(vcpu) &&
a780a3ea 863 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 864 return 1;
865 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 866 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 867 return 1;
a03490ed 868
0f12244f 869 vcpu->arch.cr3 = cr3;
aff48baa 870 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 871 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 872 return 0;
873}
2d3ad1f4 874EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 875
eea1cff9 876int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 877{
0f12244f
GN		 878 if (cr8 & CR8_RESERVED_BITS)
879 return 1;
35754c98 880 if (lapic_in_kernel(vcpu))
a03490ed
CO		 881 kvm_lapic_set_tpr(vcpu, cr8);
882 else
ad312c7c 883 vcpu->arch.cr8 = cr8;
0f12244f
GN		 884 return 0;
885}
2d3ad1f4 886EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 887
2d3ad1f4 888unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 889{
35754c98 890 if (lapic_in_kernel(vcpu))
a03490ed
CO		 891 return kvm_lapic_get_cr8(vcpu);
892 else
ad312c7c 893 return vcpu->arch.cr8;
a03490ed 894}
2d3ad1f4 895EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 896
ae561ede
NA		 897static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
898{
899 int i;
900
901 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
902 for (i = 0; i < KVM_NR_DB_REGS; i++)
903 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
904 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
905 }
906}
907
73aaf249
JK		 908static void kvm_update_dr6(struct kvm_vcpu *vcpu)
909{
910 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
911 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
912}
913
c8639010
JK		 914static void kvm_update_dr7(struct kvm_vcpu *vcpu)
915{
916 unsigned long dr7;
917
918 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
919 dr7 = vcpu->arch.guest_debug_dr7;
920 else
921 dr7 = vcpu->arch.dr7;
922 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 923 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
924 if (dr7 & DR7_BP_EN_MASK)
925 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 926}
927
6f43ed01
NA		 928static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
929{
930 u64 fixed = DR6_FIXED_1;
931
d6321d49 932 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 933 fixed |= DR6_RTM;
934 return fixed;
935}
936
338dbc97 937static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 938{
939 switch (dr) {
940 case 0 ... 3:
941 vcpu->arch.db[dr] = val;
942 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
943 vcpu->arch.eff_db[dr] = val;
944 break;
945 case 4:
020df079
GN		 946 /* fall through */
947 case 6:
338dbc97
GN		 948 if (val & 0xffffffff00000000ULL)
949 return -1; /* #GP */
6f43ed01 950 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 951 kvm_update_dr6(vcpu);
020df079
GN		 952 break;
953 case 5:
020df079
GN		 954 /* fall through */
955 default: /* 7 */
338dbc97
GN		 956 if (val & 0xffffffff00000000ULL)
957 return -1; /* #GP */
020df079 958 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 959 kvm_update_dr7(vcpu);
020df079
GN		 960 break;
961 }
962
963 return 0;
964}
338dbc97
GN		 965
966int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
967{
16f8a6f9 968 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 969 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 970 return 1;
971 }
972 return 0;
338dbc97 973}
020df079
GN		 974EXPORT_SYMBOL_GPL(kvm_set_dr);
975
16f8a6f9 976int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 977{
978 switch (dr) {
979 case 0 ... 3:
980 *val = vcpu->arch.db[dr];
981 break;
982 case 4:
020df079
GN		 983 /* fall through */
984 case 6:
73aaf249
JK		 985 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
986 *val = vcpu->arch.dr6;
987 else
988 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 989 break;
990 case 5:
020df079
GN		 991 /* fall through */
992 default: /* 7 */
993 *val = vcpu->arch.dr7;
994 break;
995 }
338dbc97
GN		 996 return 0;
997}
020df079
GN		 998EXPORT_SYMBOL_GPL(kvm_get_dr);
999
022cd0e8
AK		 1000bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1001{
1002 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1003 u64 data;
1004 int err;
1005
c6702c9d 1006 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1007 if (err)
1008 return err;
1009 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1010 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1011 return err;
1012}
1013EXPORT_SYMBOL_GPL(kvm_rdpmc);
1014
043405e1
CO		 1015/*
1016 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1017 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1018 *
1019 * This list is modified at module load time to reflect the
e3267cbb 1020 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1021 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1022 * may depend on host virtualization features rather than host cpu features.
043405e1 1023 */
e3267cbb 1024
043405e1
CO		 1025static u32 msrs_to_save[] = {
1026 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1027 MSR_STAR,
043405e1
CO		 1028#ifdef CONFIG_X86_64
1029 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1030#endif
b3897a49 1031 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1032 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1033 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1034};
1035
1036static unsigned num_msrs_to_save;
1037
62ef68bb
PB		 1038static u32 emulated_msrs[] = {
1039 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1040 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1041 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1042 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1043 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1044 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1045 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1046 HV_X64_MSR_RESET,
11c4b1ca 1047 HV_X64_MSR_VP_INDEX,
9eec50b8 1048 HV_X64_MSR_VP_RUNTIME,
5c919412 1049 HV_X64_MSR_SCONTROL,
1f4b34f8 1050 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1051 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1052 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1053 HV_X64_MSR_TSC_EMULATION_STATUS,
1054
1055 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1056 MSR_KVM_PV_EOI_EN,
1057
ba904635 1058 MSR_IA32_TSC_ADJUST,
a3e06bbe 1059 MSR_IA32_TSCDEADLINE,
043405e1 1060 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1061 MSR_IA32_MCG_STATUS,
1062 MSR_IA32_MCG_CTL,
c45dcc71 1063 MSR_IA32_MCG_EXT_CTL,
64d60670 1064 MSR_IA32_SMBASE,
52797bf9 1065 MSR_SMI_COUNT,
db2336a8
KH		 1066 MSR_PLATFORM_INFO,
1067 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1068};
1069
62ef68bb
PB		 1070static unsigned num_emulated_msrs;
1071
801e459a
TL		 1072/*
1073 * List of msr numbers which are used to expose MSR-based features that
1074 * can be used by a hypervisor to validate requested CPU features.
1075 */
1076static u32 msr_based_features[] = {
1389309c
PB		 1077 MSR_IA32_VMX_BASIC,
1078 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1079 MSR_IA32_VMX_PINBASED_CTLS,
1080 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1081 MSR_IA32_VMX_PROCBASED_CTLS,
1082 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1083 MSR_IA32_VMX_EXIT_CTLS,
1084 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1085 MSR_IA32_VMX_ENTRY_CTLS,
1086 MSR_IA32_VMX_MISC,
1087 MSR_IA32_VMX_CR0_FIXED0,
1088 MSR_IA32_VMX_CR0_FIXED1,
1089 MSR_IA32_VMX_CR4_FIXED0,
1090 MSR_IA32_VMX_CR4_FIXED1,
1091 MSR_IA32_VMX_VMCS_ENUM,
1092 MSR_IA32_VMX_PROCBASED_CTLS2,
1093 MSR_IA32_VMX_EPT_VPID_CAP,
1094 MSR_IA32_VMX_VMFUNC,
1095
d1d93fa9 1096 MSR_F10H_DECFG,
518e7b94 1097 MSR_IA32_UCODE_REV,
801e459a
TL		 1098};
1099
1100static unsigned int num_msr_based_features;
1101
66421c1e
WL		 1102static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1103{
1104 switch (msr->index) {
518e7b94
WL		 1105 case MSR_IA32_UCODE_REV:
1106 rdmsrl(msr->index, msr->data);
1107 break;
66421c1e
WL		 1108 default:
1109 if (kvm_x86_ops->get_msr_feature(msr))
1110 return 1;
1111 }
1112 return 0;
1113}
1114
801e459a
TL		 1115static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1116{
1117 struct kvm_msr_entry msr;
66421c1e 1118 int r;
801e459a
TL		 1119
1120 msr.index = index;
66421c1e
WL		 1121 r = kvm_get_msr_feature(&msr);
1122 if (r)
1123 return r;
801e459a
TL		 1124
1125 *data = msr.data;
1126
1127 return 0;
1128}
1129
384bb783 1130bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1131{
b69e8cae 1132 if (efer & efer_reserved_bits)
384bb783 1133 return false;
15c4a640 1134
1b4d56b8 1135 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1136 return false;
1b2fd70c 1137
1b4d56b8 1138 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1139 return false;
d8017474 1140
384bb783
JK		 1141 return true;
1142}
1143EXPORT_SYMBOL_GPL(kvm_valid_efer);
1144
1145static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1146{
1147 u64 old_efer = vcpu->arch.efer;
1148
1149 if (!kvm_valid_efer(vcpu, efer))
1150 return 1;
1151
1152 if (is_paging(vcpu)
1153 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1154 return 1;
1155
15c4a640 1156 efer &= ~EFER_LMA;
f6801dff 1157 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1158
a3d204e2
SY		 1159 kvm_x86_ops->set_efer(vcpu, efer);
1160
aad82703
SY		 1161 /* Update reserved bits */
1162 if ((efer ^ old_efer) & EFER_NX)
1163 kvm_mmu_reset_context(vcpu);
1164
b69e8cae 1165 return 0;
15c4a640
CO		 1166}
1167
f2b4b7dd
JR		 1168void kvm_enable_efer_bits(u64 mask)
1169{
1170 efer_reserved_bits &= ~mask;
1171}
1172EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1173
15c4a640
CO		 1174/*
1175 * Writes msr value into into the appropriate "register".
1176 * Returns 0 on success, non-0 otherwise.
1177 * Assumes vcpu_load() was already called.
1178 */
8fe8ab46 1179int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1180{
854e8bb1
NA		 1181 switch (msr->index) {
1182 case MSR_FS_BASE:
1183 case MSR_GS_BASE:
1184 case MSR_KERNEL_GS_BASE:
1185 case MSR_CSTAR:
1186 case MSR_LSTAR:
fd8cb433 1187 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1188 return 1;
1189 break;
1190 case MSR_IA32_SYSENTER_EIP:
1191 case MSR_IA32_SYSENTER_ESP:
1192 /*
1193 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1194 * non-canonical address is written on Intel but not on
1195 * AMD (which ignores the top 32-bits, because it does
1196 * not implement 64-bit SYSENTER).
1197 *
1198 * 64-bit code should hence be able to write a non-canonical
1199 * value on AMD. Making the address canonical ensures that
1200 * vmentry does not fail on Intel after writing a non-canonical
1201 * value, and that something deterministic happens if the guest
1202 * invokes 64-bit SYSENTER.
1203 */
fd8cb433 1204 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1205 }
8fe8ab46 1206 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1207}
854e8bb1 1208EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1209
313a3dc7
CO		 1210/*
1211 * Adapt set_msr() to msr_io()'s calling convention
1212 */
609e36d3
PB		 1213static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1214{
1215 struct msr_data msr;
1216 int r;
1217
1218 msr.index = index;
1219 msr.host_initiated = true;
1220 r = kvm_get_msr(vcpu, &msr);
1221 if (r)
1222 return r;
1223
1224 *data = msr.data;
1225 return 0;
1226}
1227
313a3dc7
CO		 1228static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1229{
8fe8ab46
WA		 1230 struct msr_data msr;
1231
1232 msr.data = *data;
1233 msr.index = index;
1234 msr.host_initiated = true;
1235 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1236}
1237
16e8d74d
MT		 1238#ifdef CONFIG_X86_64
1239struct pvclock_gtod_data {
1240 seqcount_t seq;
1241
1242 struct { /* extract of a clocksource struct */
1243 int vclock_mode;
a5a1d1c2
TG		 1244 u64 cycle_last;
1245 u64 mask;
16e8d74d
MT		 1246 u32 mult;
1247 u32 shift;
1248 } clock;
1249
cbcf2dd3
TG		 1250 u64 boot_ns;
1251 u64 nsec_base;
55dd00a7 1252 u64 wall_time_sec;
16e8d74d
MT		 1253};
1254
1255static struct pvclock_gtod_data pvclock_gtod_data;
1256
1257static void update_pvclock_gtod(struct timekeeper *tk)
1258{
1259 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1260 u64 boot_ns;
1261
876e7881 1262 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1263
1264 write_seqcount_begin(&vdata->seq);
1265
1266 /* copy pvclock gtod data */
876e7881
PZ		 1267 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1268 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1269 vdata->clock.mask = tk->tkr_mono.mask;
1270 vdata->clock.mult = tk->tkr_mono.mult;
1271 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1272
cbcf2dd3 1273 vdata->boot_ns = boot_ns;
876e7881 1274 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1275
55dd00a7
MT		 1276 vdata->wall_time_sec = tk->xtime_sec;
1277
16e8d74d
MT		 1278 write_seqcount_end(&vdata->seq);
1279}
1280#endif
1281
bab5bb39
NK		 1282void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1283{
1284 /*
1285 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1286 * vcpu_enter_guest. This function is only called from
1287 * the physical CPU that is running vcpu.
1288 */
1289 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1290}
16e8d74d 1291
18068523
GOC		 1292static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1293{
9ed3c444
AK		 1294 int version;
1295 int r;
50d0a0f9 1296 struct pvclock_wall_clock wc;
87aeb54f 1297 struct timespec64 boot;
18068523
GOC		 1298
1299 if (!wall_clock)
1300 return;
1301
9ed3c444
AK		 1302 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1303 if (r)
1304 return;
1305
1306 if (version & 1)
1307 ++version; /* first time write, random junk */
1308
1309 ++version;
18068523 1310
1dab1345
NK		 1311 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1312 return;
18068523 1313
50d0a0f9
GH		 1314 /*
1315 * The guest calculates current wall clock time by adding
34c238a1 1316 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1317 * wall clock specified here. guest system time equals host
1318 * system time for us, thus we must fill in host boot time here.
1319 */
87aeb54f 1320 getboottime64(&boot);
50d0a0f9 1321
4b648665 1322 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1323 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1324 boot = timespec64_sub(boot, ts);
4b648665 1325 }
87aeb54f 1326 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1327 wc.nsec = boot.tv_nsec;
1328 wc.version = version;
18068523
GOC		 1329
1330 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1331
1332 version++;
1333 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1334}
1335
50d0a0f9
GH		 1336static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1337{
b51012de
PB		 1338 do_shl32_div32(dividend, divisor);
1339 return dividend;
50d0a0f9
GH		 1340}
1341
3ae13faa 1342static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1343 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1344{
5f4e3f88 1345 uint64_t scaled64;
50d0a0f9
GH		 1346 int32_t shift = 0;
1347 uint64_t tps64;
1348 uint32_t tps32;
1349
3ae13faa
PB		 1350 tps64 = base_hz;
1351 scaled64 = scaled_hz;
50933623 1352 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1353 tps64 >>= 1;
1354 shift--;
1355 }
1356
1357 tps32 = (uint32_t)tps64;
50933623
JK		 1358 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1359 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1360 scaled64 >>= 1;
1361 else
1362 tps32 <<= 1;
50d0a0f9
GH		 1363 shift++;
1364 }
1365
5f4e3f88
ZA		 1366 *pshift = shift;
1367 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1368
3ae13faa
PB		 1369 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1370 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1371}
1372
d828199e 1373#ifdef CONFIG_X86_64
16e8d74d 1374static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1375#endif
16e8d74d 1376
c8076604 1377static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1378static unsigned long max_tsc_khz;
c8076604 1379
cc578287 1380static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1381{
cc578287
ZA		 1382 u64 v = (u64)khz * (1000000 + ppm);
1383 do_div(v, 1000000);
1384 return v;
1e993611
JR		 1385}
1386
381d585c
HZ		 1387static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1388{
1389 u64 ratio;
1390
1391 /* Guest TSC same frequency as host TSC? */
1392 if (!scale) {
1393 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1394 return 0;
1395 }
1396
1397 /* TSC scaling supported? */
1398 if (!kvm_has_tsc_control) {
1399 if (user_tsc_khz > tsc_khz) {
1400 vcpu->arch.tsc_catchup = 1;
1401 vcpu->arch.tsc_always_catchup = 1;
1402 return 0;
1403 } else {
1404 WARN(1, "user requested TSC rate below hardware speed\n");
1405 return -1;
1406 }
1407 }
1408
1409 /* TSC scaling required - calculate ratio */
1410 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1411 user_tsc_khz, tsc_khz);
1412
1413 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1414 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1415 user_tsc_khz);
1416 return -1;
1417 }
1418
1419 vcpu->arch.tsc_scaling_ratio = ratio;
1420 return 0;
1421}
1422
4941b8cb 1423static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1424{
cc578287
ZA		 1425 u32 thresh_lo, thresh_hi;
1426 int use_scaling = 0;
217fc9cf 1427
03ba32ca 1428 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1429 if (user_tsc_khz == 0) {
ad721883
HZ		 1430 /* set tsc_scaling_ratio to a safe value */
1431 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1432 return -1;
ad721883 1433 }
03ba32ca 1434
c285545f 1435 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1436 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1437 &vcpu->arch.virtual_tsc_shift,
1438 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1439 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1440
1441 /*
1442 * Compute the variation in TSC rate which is acceptable
1443 * within the range of tolerance and decide if the
1444 * rate being applied is within that bounds of the hardware
1445 * rate. If so, no scaling or compensation need be done.
1446 */
1447 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1448 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1449 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1450 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1451 use_scaling = 1;
1452 }
4941b8cb 1453 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1454}
1455
1456static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1457{
e26101b1 1458 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1459 vcpu->arch.virtual_tsc_mult,
1460 vcpu->arch.virtual_tsc_shift);
e26101b1 1461 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1462 return tsc;
1463}
1464
b0c39dc6
VK		 1465static inline int gtod_is_based_on_tsc(int mode)
1466{
1467 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1468}
1469
69b0049a 1470static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1471{
1472#ifdef CONFIG_X86_64
1473 bool vcpus_matched;
b48aa97e
MT		 1474 struct kvm_arch *ka = &vcpu->kvm->arch;
1475 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1476
1477 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1478 atomic_read(&vcpu->kvm->online_vcpus));
1479
7f187922
MT		 1480 /*
1481 * Once the masterclock is enabled, always perform request in
1482 * order to update it.
1483 *
1484 * In order to enable masterclock, the host clocksource must be TSC
1485 * and the vcpus need to have matched TSCs. When that happens,
1486 * perform request to enable masterclock.
1487 */
1488 if (ka->use_master_clock ||
b0c39dc6 1489 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1490 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1491
1492 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1493 atomic_read(&vcpu->kvm->online_vcpus),
1494 ka->use_master_clock, gtod->clock.vclock_mode);
1495#endif
1496}
1497
ba904635
WA		 1498static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1499{
e79f245d 1500 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1501 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1502}
1503
35181e86
HZ		 1504/*
1505 * Multiply tsc by a fixed point number represented by ratio.
1506 *
1507 * The most significant 64-N bits (mult) of ratio represent the
1508 * integral part of the fixed point number; the remaining N bits
1509 * (frac) represent the fractional part, ie. ratio represents a fixed
1510 * point number (mult + frac * 2^(-N)).
1511 *
1512 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1513 */
1514static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1515{
1516 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1517}
1518
1519u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1520{
1521 u64 _tsc = tsc;
1522 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1523
1524 if (ratio != kvm_default_tsc_scaling_ratio)
1525 _tsc = __scale_tsc(ratio, tsc);
1526
1527 return _tsc;
1528}
1529EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1530
07c1419a
HZ		 1531static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1532{
1533 u64 tsc;
1534
1535 tsc = kvm_scale_tsc(vcpu, rdtsc());
1536
1537 return target_tsc - tsc;
1538}
1539
4ba76538
HZ		 1540u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1541{
e79f245d
KA		 1542 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1543
1544 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1545}
1546EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1547
a545ab6a
LC		 1548static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1549{
1550 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1551 vcpu->arch.tsc_offset = offset;
1552}
1553
b0c39dc6
VK		 1554static inline bool kvm_check_tsc_unstable(void)
1555{
1556#ifdef CONFIG_X86_64
1557 /*
1558 * TSC is marked unstable when we're running on Hyper-V,
1559 * 'TSC page' clocksource is good.
1560 */
1561 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1562 return false;
1563#endif
1564 return check_tsc_unstable();
1565}
1566
8fe8ab46 1567void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1568{
1569 struct kvm *kvm = vcpu->kvm;
f38e098f 1570 u64 offset, ns, elapsed;
99e3e30a 1571 unsigned long flags;
b48aa97e 1572 bool matched;
0d3da0d2 1573 bool already_matched;
8fe8ab46 1574 u64 data = msr->data;
c5e8ec8e 1575 bool synchronizing = false;
99e3e30a 1576
038f8c11 1577 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1578 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1579 ns = ktime_get_boot_ns();
f38e098f 1580 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1581
03ba32ca 1582 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1583 if (data == 0 && msr->host_initiated) {
1584 /*
1585 * detection of vcpu initialization -- need to sync
1586 * with other vCPUs. This particularly helps to keep
1587 * kvm_clock stable after CPU hotplug
1588 */
1589 synchronizing = true;
1590 } else {
1591 u64 tsc_exp = kvm->arch.last_tsc_write +
1592 nsec_to_cycles(vcpu, elapsed);
1593 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1594 /*
1595 * Special case: TSC write with a small delta (1 second)
1596 * of virtual cycle time against real time is
1597 * interpreted as an attempt to synchronize the CPU.
1598 */
1599 synchronizing = data < tsc_exp + tsc_hz &&
1600 data + tsc_hz > tsc_exp;
1601 }
c5e8ec8e 1602 }
f38e098f
ZA		 1603
1604 /*
5d3cb0f6
ZA		 1605 * For a reliable TSC, we can match TSC offsets, and for an unstable
1606 * TSC, we add elapsed time in this computation. We could let the
1607 * compensation code attempt to catch up if we fall behind, but
1608 * it's better to try to match offsets from the beginning.
1609 */
c5e8ec8e 1610 if (synchronizing &&
5d3cb0f6 1611 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1612 if (!kvm_check_tsc_unstable()) {
e26101b1 1613 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1614 pr_debug("kvm: matched tsc offset for %llu\n", data);
1615 } else {
857e4099 1616 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1617 data += delta;
07c1419a 1618 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1619 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1620 }
b48aa97e 1621 matched = true;
0d3da0d2 1622 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1623 } else {
1624 /*
1625 * We split periods of matched TSC writes into generations.
1626 * For each generation, we track the original measured
1627 * nanosecond time, offset, and write, so if TSCs are in
1628 * sync, we can match exact offset, and if not, we can match
4a969980 1629 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1630 *
1631 * These values are tracked in kvm->arch.cur_xxx variables.
1632 */
1633 kvm->arch.cur_tsc_generation++;
1634 kvm->arch.cur_tsc_nsec = ns;
1635 kvm->arch.cur_tsc_write = data;
1636 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1637 matched = false;
0d3da0d2 1638 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1639 kvm->arch.cur_tsc_generation, data);
f38e098f 1640 }
e26101b1
ZA		 1641
1642 /*
1643 * We also track th most recent recorded KHZ, write and time to
1644 * allow the matching interval to be extended at each write.
1645 */
f38e098f
ZA		 1646 kvm->arch.last_tsc_nsec = ns;
1647 kvm->arch.last_tsc_write = data;
5d3cb0f6 1648 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1649
b183aa58 1650 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1651
1652 /* Keep track of which generation this VCPU has synchronized to */
1653 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1654 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1655 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1656
d6321d49 1657 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1658 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1659
a545ab6a 1660 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1661 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1662
1663 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1664 if (!matched) {
b48aa97e 1665 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1666 } else if (!already_matched) {
1667 kvm->arch.nr_vcpus_matched_tsc++;
1668 }
b48aa97e
MT		 1669
1670 kvm_track_tsc_matching(vcpu);
1671 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1672}
e26101b1 1673
99e3e30a
ZA		 1674EXPORT_SYMBOL_GPL(kvm_write_tsc);
1675
58ea6767
HZ		 1676static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1677 s64 adjustment)
1678{
ea26e4ec 1679 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1680}
1681
1682static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1683{
1684 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1685 WARN_ON(adjustment < 0);
1686 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1687 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1688}
1689
d828199e
MT		 1690#ifdef CONFIG_X86_64
1691
a5a1d1c2 1692static u64 read_tsc(void)
d828199e 1693{
a5a1d1c2 1694 u64 ret = (u64)rdtsc_ordered();
03b9730b 1695 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1696
1697 if (likely(ret >= last))
1698 return ret;
1699
1700 /*
1701 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1702 * predictable (it's just a function of time and the likely is
d828199e
MT		 1703 * very likely) and there's a data dependence, so force GCC
1704 * to generate a branch instead. I don't barrier() because
1705 * we don't actually need a barrier, and if this function
1706 * ever gets inlined it will generate worse code.
1707 */
1708 asm volatile ("");
1709 return last;
1710}
1711
b0c39dc6 1712static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1713{
1714 long v;
1715 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1716 u64 tsc_pg_val;
1717
1718 switch (gtod->clock.vclock_mode) {
1719 case VCLOCK_HVCLOCK:
1720 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1721 tsc_timestamp);
1722 if (tsc_pg_val != U64_MAX) {
1723 /* TSC page valid */
1724 *mode = VCLOCK_HVCLOCK;
1725 v = (tsc_pg_val - gtod->clock.cycle_last) &
1726 gtod->clock.mask;
1727 } else {
1728 /* TSC page invalid */
1729 *mode = VCLOCK_NONE;
1730 }
1731 break;
1732 case VCLOCK_TSC:
1733 *mode = VCLOCK_TSC;
1734 *tsc_timestamp = read_tsc();
1735 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1736 gtod->clock.mask;
1737 break;
1738 default:
1739 *mode = VCLOCK_NONE;
1740 }
d828199e 1741
b0c39dc6
VK		 1742 if (*mode == VCLOCK_NONE)
1743 *tsc_timestamp = v = 0;
d828199e 1744
d828199e
MT		 1745 return v * gtod->clock.mult;
1746}
1747
b0c39dc6 1748static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1749{
cbcf2dd3 1750 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1751 unsigned long seq;
d828199e 1752 int mode;
cbcf2dd3 1753 u64 ns;
d828199e 1754
d828199e
MT		 1755 do {
1756 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1757 ns = gtod->nsec_base;
b0c39dc6 1758 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1759 ns >>= gtod->clock.shift;
cbcf2dd3 1760 ns += gtod->boot_ns;
d828199e 1761 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1762 *t = ns;
d828199e
MT		 1763
1764 return mode;
1765}
1766
b0c39dc6 1767static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1768{
1769 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1770 unsigned long seq;
1771 int mode;
1772 u64 ns;
1773
1774 do {
1775 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1776 ts->tv_sec = gtod->wall_time_sec;
1777 ns = gtod->nsec_base;
b0c39dc6 1778 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1779 ns >>= gtod->clock.shift;
1780 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1781
1782 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1783 ts->tv_nsec = ns;
1784
1785 return mode;
1786}
1787
b0c39dc6
VK		 1788/* returns true if host is using TSC based clocksource */
1789static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1790{
d828199e 1791 /* checked again under seqlock below */
b0c39dc6 1792 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1793 return false;
1794
b0c39dc6
VK		 1795 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1796 tsc_timestamp));
d828199e 1797}
55dd00a7 1798
b0c39dc6 1799/* returns true if host is using TSC based clocksource */
55dd00a7 1800static bool kvm_get_walltime_and_clockread(struct timespec *ts,
b0c39dc6 1801 u64 *tsc_timestamp)
55dd00a7
MT		 1802{
1803 /* checked again under seqlock below */
b0c39dc6 1804 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1805 return false;
1806
b0c39dc6 1807 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1808}
d828199e
MT		 1809#endif
1810
1811/*
1812 *
b48aa97e
MT		 1813 * Assuming a stable TSC across physical CPUS, and a stable TSC
1814 * across virtual CPUs, the following condition is possible.
1815 * Each numbered line represents an event visible to both
d828199e
MT		 1816 * CPUs at the next numbered event.
1817 *
1818 * "timespecX" represents host monotonic time. "tscX" represents
1819 * RDTSC value.
1820 *
1821 * VCPU0 on CPU0 | VCPU1 on CPU1
1822 *
1823 * 1. read timespec0,tsc0
1824 * 2. | timespec1 = timespec0 + N
1825 * | tsc1 = tsc0 + M
1826 * 3. transition to guest | transition to guest
1827 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1828 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1829 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1830 *
1831 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1832 *
1833 * - ret0 < ret1
1834 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1835 * ...
1836 * - 0 < N - M => M < N
1837 *
1838 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1839 * always the case (the difference between two distinct xtime instances
1840 * might be smaller then the difference between corresponding TSC reads,
1841 * when updating guest vcpus pvclock areas).
1842 *
1843 * To avoid that problem, do not allow visibility of distinct
1844 * system_timestamp/tsc_timestamp values simultaneously: use a master
1845 * copy of host monotonic time values. Update that master copy
1846 * in lockstep.
1847 *
b48aa97e 1848 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1849 *
1850 */
1851
1852static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1853{
1854#ifdef CONFIG_X86_64
1855 struct kvm_arch *ka = &kvm->arch;
1856 int vclock_mode;
b48aa97e
MT		 1857 bool host_tsc_clocksource, vcpus_matched;
1858
1859 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1860 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1861
1862 /*
1863 * If the host uses TSC clock, then passthrough TSC as stable
1864 * to the guest.
1865 */
b48aa97e 1866 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1867 &ka->master_kernel_ns,
1868 &ka->master_cycle_now);
1869
16a96021 1870 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1871 && !ka->backwards_tsc_observed
54750f2c 1872 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1873
d828199e
MT		 1874 if (ka->use_master_clock)
1875 atomic_set(&kvm_guest_has_master_clock, 1);
1876
1877 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1878 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1879 vcpus_matched);
d828199e
MT		 1880#endif
1881}
1882
2860c4b1
PB		 1883void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1884{
1885 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1886}
1887
2e762ff7
MT		 1888static void kvm_gen_update_masterclock(struct kvm *kvm)
1889{
1890#ifdef CONFIG_X86_64
1891 int i;
1892 struct kvm_vcpu *vcpu;
1893 struct kvm_arch *ka = &kvm->arch;
1894
1895 spin_lock(&ka->pvclock_gtod_sync_lock);
1896 kvm_make_mclock_inprogress_request(kvm);
1897 /* no guest entries from this point */
1898 pvclock_update_vm_gtod_copy(kvm);
1899
1900 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1901 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1902
1903 /* guest entries allowed */
1904 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1905 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1906
1907 spin_unlock(&ka->pvclock_gtod_sync_lock);
1908#endif
1909}
1910
e891a32e 1911u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1912{
108b249c 1913 struct kvm_arch *ka = &kvm->arch;
8b953440 1914 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1915 u64 ret;
108b249c 1916
8b953440
PB		 1917 spin_lock(&ka->pvclock_gtod_sync_lock);
1918 if (!ka->use_master_clock) {
1919 spin_unlock(&ka->pvclock_gtod_sync_lock);
1920 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1921 }
1922
8b953440
PB		 1923 hv_clock.tsc_timestamp = ka->master_cycle_now;
1924 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1925 spin_unlock(&ka->pvclock_gtod_sync_lock);
1926
e2c2206a
WL		 1927 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1928 get_cpu();
1929
e70b57a6
WL		 1930 if (__this_cpu_read(cpu_tsc_khz)) {
1931 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1932 &hv_clock.tsc_shift,
1933 &hv_clock.tsc_to_system_mul);
1934 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1935 } else
1936 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1937
1938 put_cpu();
1939
1940 return ret;
108b249c
PB		 1941}
1942
0d6dd2ff
PB		 1943static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1944{
1945 struct kvm_vcpu_arch *vcpu = &v->arch;
1946 struct pvclock_vcpu_time_info guest_hv_clock;
1947
4e335d9e 1948 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1949 &guest_hv_clock, sizeof(guest_hv_clock))))
1950 return;
1951
1952 /* This VCPU is paused, but it's legal for a guest to read another
1953 * VCPU's kvmclock, so we really have to follow the specification where
1954 * it says that version is odd if data is being modified, and even after
1955 * it is consistent.
1956 *
1957 * Version field updates must be kept separate. This is because
1958 * kvm_write_guest_cached might use a "rep movs" instruction, and
1959 * writes within a string instruction are weakly ordered. So there
1960 * are three writes overall.
1961 *
1962 * As a small optimization, only write the version field in the first
1963 * and third write. The vcpu->pv_time cache is still valid, because the
1964 * version field is the first in the struct.
1965 */
1966 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1967
51c4b8bb
LA		 1968 if (guest_hv_clock.version & 1)
1969 ++guest_hv_clock.version; /* first time write, random junk */
1970
0d6dd2ff 1971 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1972 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1973 &vcpu->hv_clock,
1974 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1975
1976 smp_wmb();
1977
1978 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1979 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1980
1981 if (vcpu->pvclock_set_guest_stopped_request) {
1982 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1983 vcpu->pvclock_set_guest_stopped_request = false;
1984 }
1985
1986 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1987
4e335d9e
PB		 1988 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1989 &vcpu->hv_clock,
1990 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1991
1992 smp_wmb();
1993
1994 vcpu->hv_clock.version++;
4e335d9e
PB		 1995 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1996 &vcpu->hv_clock,
1997 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1998}
1999
34c238a1 2000static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2001{
78db6a50 2002 unsigned long flags, tgt_tsc_khz;
18068523 2003 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2004 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2005 s64 kernel_ns;
d828199e 2006 u64 tsc_timestamp, host_tsc;
51d59c6b 2007 u8 pvclock_flags;
d828199e
MT		 2008 bool use_master_clock;
2009
2010 kernel_ns = 0;
2011 host_tsc = 0;
18068523 2012
d828199e
MT		 2013 /*
2014 * If the host uses TSC clock, then passthrough TSC as stable
2015 * to the guest.
2016 */
2017 spin_lock(&ka->pvclock_gtod_sync_lock);
2018 use_master_clock = ka->use_master_clock;
2019 if (use_master_clock) {
2020 host_tsc = ka->master_cycle_now;
2021 kernel_ns = ka->master_kernel_ns;
2022 }
2023 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2024
2025 /* Keep irq disabled to prevent changes to the clock */
2026 local_irq_save(flags);
78db6a50
PB		 2027 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2028 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2029 local_irq_restore(flags);
2030 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2031 return 1;
2032 }
d828199e 2033 if (!use_master_clock) {
4ea1636b 2034 host_tsc = rdtsc();
108b249c 2035 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2036 }
2037
4ba76538 2038 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2039
c285545f
ZA		 2040 /*
2041 * We may have to catch up the TSC to match elapsed wall clock
2042 * time for two reasons, even if kvmclock is used.
2043 * 1) CPU could have been running below the maximum TSC rate
2044 * 2) Broken TSC compensation resets the base at each VCPU
2045 * entry to avoid unknown leaps of TSC even when running
2046 * again on the same CPU. This may cause apparent elapsed
2047 * time to disappear, and the guest to stand still or run
2048 * very slowly.
2049 */
2050 if (vcpu->tsc_catchup) {
2051 u64 tsc = compute_guest_tsc(v, kernel_ns);
2052 if (tsc > tsc_timestamp) {
f1e2b260 2053 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2054 tsc_timestamp = tsc;
2055 }
50d0a0f9
GH		 2056 }
2057
18068523
GOC		 2058 local_irq_restore(flags);
2059
0d6dd2ff 2060 /* With all the info we got, fill in the values */
18068523 2061
78db6a50
PB		 2062 if (kvm_has_tsc_control)
2063 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2064
2065 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2066 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2067 &vcpu->hv_clock.tsc_shift,
2068 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2069 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2070 }
2071
1d5f066e 2072 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2073 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2074 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2075
d828199e 2076 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2077 pvclock_flags = 0;
d828199e
MT		 2078 if (use_master_clock)
2079 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2080
78c0337a
MT		 2081 vcpu->hv_clock.flags = pvclock_flags;
2082
095cf55d
PB		 2083 if (vcpu->pv_time_enabled)
2084 kvm_setup_pvclock_page(v);
2085 if (v == kvm_get_vcpu(v->kvm, 0))
2086 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2087 return 0;
c8076604
GH		 2088}
2089
0061d53d
MT		 2090/*
2091 * kvmclock updates which are isolated to a given vcpu, such as
2092 * vcpu->cpu migration, should not allow system_timestamp from
2093 * the rest of the vcpus to remain static. Otherwise ntp frequency
2094 * correction applies to one vcpu's system_timestamp but not
2095 * the others.
2096 *
2097 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2098 * We need to rate-limit these requests though, as they can
2099 * considerably slow guests that have a large number of vcpus.
2100 * The time for a remote vcpu to update its kvmclock is bound
2101 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2102 */
2103
7e44e449
AJ		 2104#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2105
2106static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2107{
2108 int i;
7e44e449
AJ		 2109 struct delayed_work *dwork = to_delayed_work(work);
2110 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2111 kvmclock_update_work);
2112 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2113 struct kvm_vcpu *vcpu;
2114
2115 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2116 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2117 kvm_vcpu_kick(vcpu);
2118 }
2119}
2120
7e44e449
AJ		 2121static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2122{
2123 struct kvm *kvm = v->kvm;
2124
105b21bb 2125 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2126 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2127 KVMCLOCK_UPDATE_DELAY);
2128}
2129
332967a3
AJ		 2130#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2131
2132static void kvmclock_sync_fn(struct work_struct *work)
2133{
2134 struct delayed_work *dwork = to_delayed_work(work);
2135 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2136 kvmclock_sync_work);
2137 struct kvm *kvm = container_of(ka, struct kvm, arch);
2138
630994b3
MT		 2139 if (!kvmclock_periodic_sync)
2140 return;
2141
332967a3
AJ		 2142 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2143 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2144 KVMCLOCK_SYNC_PERIOD);
2145}
2146
9ffd986c 2147static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2148{
890ca9ae
HY		 2149 u64 mcg_cap = vcpu->arch.mcg_cap;
2150 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2151 u32 msr = msr_info->index;
2152 u64 data = msr_info->data;
890ca9ae 2153
15c4a640 2154 switch (msr) {
15c4a640 2155 case MSR_IA32_MCG_STATUS:
890ca9ae 2156 vcpu->arch.mcg_status = data;
15c4a640 2157 break;
c7ac679c 2158 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2159 if (!(mcg_cap & MCG_CTL_P))
2160 return 1;
2161 if (data != 0 && data != ~(u64)0)
2162 return -1;
2163 vcpu->arch.mcg_ctl = data;
2164 break;
2165 default:
2166 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2167 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2168 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2169 /* only 0 or all 1s can be written to IA32_MCi_CTL
2170 * some Linux kernels though clear bit 10 in bank 4 to
2171 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2172 * this to avoid an uncatched #GP in the guest
2173 */
890ca9ae 2174 if ((offset & 0x3) == 0 &&
114be429 2175 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2176 return -1;
9ffd986c
WL		 2177 if (!msr_info->host_initiated &&
2178 (offset & 0x3) == 1 && data != 0)
2179 return -1;
890ca9ae
HY		 2180 vcpu->arch.mce_banks[offset] = data;
2181 break;
2182 }
2183 return 1;
2184 }
2185 return 0;
2186}
2187
ffde22ac
ES		 2188static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2189{
2190 struct kvm *kvm = vcpu->kvm;
2191 int lm = is_long_mode(vcpu);
2192 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2193 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2194 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2195 : kvm->arch.xen_hvm_config.blob_size_32;
2196 u32 page_num = data & ~PAGE_MASK;
2197 u64 page_addr = data & PAGE_MASK;
2198 u8 *page;
2199 int r;
2200
2201 r = -E2BIG;
2202 if (page_num >= blob_size)
2203 goto out;
2204 r = -ENOMEM;
ff5c2c03
SL		 2205 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2206 if (IS_ERR(page)) {
2207 r = PTR_ERR(page);
ffde22ac 2208 goto out;
ff5c2c03 2209 }
54bf36aa 2210 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2211 goto out_free;
2212 r = 0;
2213out_free:
2214 kfree(page);
2215out:
2216 return r;
2217}
2218
344d9588
GN		 2219static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2220{
2221 gpa_t gpa = data & ~0x3f;
2222
52a5c155
WL		 2223 /* Bits 3:5 are reserved, Should be zero */
2224 if (data & 0x38)
344d9588
GN		 2225 return 1;
2226
2227 vcpu->arch.apf.msr_val = data;
2228
2229 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2230 kvm_clear_async_pf_completion_queue(vcpu);
2231 kvm_async_pf_hash_reset(vcpu);
2232 return 0;
2233 }
2234
4e335d9e 2235 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2236 sizeof(u32)))
344d9588
GN		 2237 return 1;
2238
6adba527 2239 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2240 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2241 kvm_async_pf_wakeup_all(vcpu);
2242 return 0;
2243}
2244
12f9a48f
GC		 2245static void kvmclock_reset(struct kvm_vcpu *vcpu)
2246{
0b79459b 2247 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2248}
2249
f38a7b75
WL		 2250static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2251{
2252 ++vcpu->stat.tlb_flush;
2253 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2254}
2255
c9aaa895
GC		 2256static void record_steal_time(struct kvm_vcpu *vcpu)
2257{
2258 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2259 return;
2260
4e335d9e 2261 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2262 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2263 return;
2264
f38a7b75
WL		 2265 /*
2266 * Doing a TLB flush here, on the guest's behalf, can avoid
2267 * expensive IPIs.
2268 */
2269 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2270 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2271
35f3fae1
WL		 2272 if (vcpu->arch.st.steal.version & 1)
2273 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2274
2275 vcpu->arch.st.steal.version += 1;
2276
4e335d9e 2277 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2278 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2279
2280 smp_wmb();
2281
c54cdf14
LC		 2282 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2283 vcpu->arch.st.last_steal;
2284 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2285
4e335d9e 2286 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2287 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2288
2289 smp_wmb();
2290
2291 vcpu->arch.st.steal.version += 1;
c9aaa895 2292
4e335d9e 2293 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2294 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2295}
2296
8fe8ab46 2297int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2298{
5753785f 2299 bool pr = false;
8fe8ab46
WA		 2300 u32 msr = msr_info->index;
2301 u64 data = msr_info->data;
5753785f 2302
15c4a640 2303 switch (msr) {
2e32b719 2304 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2305 case MSR_IA32_UCODE_WRITE:
2306 case MSR_VM_HSAVE_PA:
2307 case MSR_AMD64_PATCH_LOADER:
2308 case MSR_AMD64_BU_CFG2:
405a353a 2309 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2310 break;
2311
518e7b94
WL		 2312 case MSR_IA32_UCODE_REV:
2313 if (msr_info->host_initiated)
2314 vcpu->arch.microcode_version = data;
2315 break;
15c4a640 2316 case MSR_EFER:
b69e8cae 2317 return set_efer(vcpu, data);
8f1589d9
AP		 2318 case MSR_K7_HWCR:
2319 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2320 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2321 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2322 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2323 if (data != 0) {
a737f256
CD		 2324 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2325 data);
8f1589d9
AP		 2326 return 1;
2327 }
15c4a640 2328 break;
f7c6d140
AP		 2329 case MSR_FAM10H_MMIO_CONF_BASE:
2330 if (data != 0) {
a737f256
CD		 2331 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2332 "0x%llx\n", data);
f7c6d140
AP		 2333 return 1;
2334 }
15c4a640 2335 break;
b5e2fec0
AG		 2336 case MSR_IA32_DEBUGCTLMSR:
2337 if (!data) {
2338 /* We support the non-activated case already */
2339 break;
2340 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2341 /* Values other than LBR and BTF are vendor-specific,
2342 thus reserved and should throw a #GP */
2343 return 1;
2344 }
a737f256
CD		 2345 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2346 __func__, data);
b5e2fec0 2347 break;
9ba075a6 2348 case 0x200 ... 0x2ff:
ff53604b 2349 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2350 case MSR_IA32_APICBASE:
58cb628d 2351 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2352 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2353 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2354 case MSR_IA32_TSCDEADLINE:
2355 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2356 break;
ba904635 2357 case MSR_IA32_TSC_ADJUST:
d6321d49 2358 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2359 if (!msr_info->host_initiated) {
d913b904 2360 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2361 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2362 }
2363 vcpu->arch.ia32_tsc_adjust_msr = data;
2364 }
2365 break;
15c4a640 2366 case MSR_IA32_MISC_ENABLE:
ad312c7c 2367 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2368 break;
64d60670
PB		 2369 case MSR_IA32_SMBASE:
2370 if (!msr_info->host_initiated)
2371 return 1;
2372 vcpu->arch.smbase = data;
2373 break;
dd259935
PB		 2374 case MSR_IA32_TSC:
2375 kvm_write_tsc(vcpu, msr_info);
2376 break;
52797bf9
LA		 2377 case MSR_SMI_COUNT:
2378 if (!msr_info->host_initiated)
2379 return 1;
2380 vcpu->arch.smi_count = data;
2381 break;
11c6bffa 2382 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2383 case MSR_KVM_WALL_CLOCK:
2384 vcpu->kvm->arch.wall_clock = data;
2385 kvm_write_wall_clock(vcpu->kvm, data);
2386 break;
11c6bffa 2387 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2388 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2389 struct kvm_arch *ka = &vcpu->kvm->arch;
2390
12f9a48f 2391 kvmclock_reset(vcpu);
18068523 2392
54750f2c
MT		 2393 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2394 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2395
2396 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2397 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2398
2399 ka->boot_vcpu_runs_old_kvmclock = tmp;
2400 }
2401
18068523 2402 vcpu->arch.time = data;
0061d53d 2403 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2404
2405 /* we verify if the enable bit is set... */
2406 if (!(data & 1))
2407 break;
2408
4e335d9e 2409 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2410 &vcpu->arch.pv_time, data & ~1ULL,
2411 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2412 vcpu->arch.pv_time_enabled = false;
2413 else
2414 vcpu->arch.pv_time_enabled = true;
32cad84f 2415
18068523
GOC		 2416 break;
2417 }
344d9588
GN		 2418 case MSR_KVM_ASYNC_PF_EN:
2419 if (kvm_pv_enable_async_pf(vcpu, data))
2420 return 1;
2421 break;
c9aaa895
GC		 2422 case MSR_KVM_STEAL_TIME:
2423
2424 if (unlikely(!sched_info_on()))
2425 return 1;
2426
2427 if (data & KVM_STEAL_RESERVED_MASK)
2428 return 1;
2429
4e335d9e 2430 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2431 data & KVM_STEAL_VALID_BITS,
2432 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2433 return 1;
2434
2435 vcpu->arch.st.msr_val = data;
2436
2437 if (!(data & KVM_MSR_ENABLED))
2438 break;
2439
c9aaa895
GC		 2440 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2441
2442 break;
ae7a2a3f
MT		 2443 case MSR_KVM_PV_EOI_EN:
2444 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2445 return 1;
2446 break;
c9aaa895 2447
890ca9ae
HY		 2448 case MSR_IA32_MCG_CTL:
2449 case MSR_IA32_MCG_STATUS:
81760dcc 2450 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2451 return set_msr_mce(vcpu, msr_info);
71db6023 2452
6912ac32
WH		 2453 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2454 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2455 pr = true; /* fall through */
2456 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2457 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2458 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2459 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2460
2461 if (pr || data != 0)
a737f256
CD		 2462 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2463 "0x%x data 0x%llx\n", msr, data);
5753785f 2464 break;
84e0cefa
JS		 2465 case MSR_K7_CLK_CTL:
2466 /*
2467 * Ignore all writes to this no longer documented MSR.
2468 * Writes are only relevant for old K7 processors,
2469 * all pre-dating SVM, but a recommended workaround from
4a969980 2470 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2471 * affected processor models on the command line, hence
2472 * the need to ignore the workaround.
2473 */
2474 break;
55cd8e5a 2475 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2476 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2477 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2478 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2479 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2480 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2481 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2482 return kvm_hv_set_msr_common(vcpu, msr, data,
2483 msr_info->host_initiated);
91c9c3ed 2484 case MSR_IA32_BBL_CR_CTL3:
2485 /* Drop writes to this legacy MSR -- see rdmsr
2486 * counterpart for further detail.
2487 */
fab0aa3b
EM		 2488 if (report_ignored_msrs)
2489 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2490 msr, data);
91c9c3ed 2491 break;
2b036c6b 2492 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2493 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2494 return 1;
2495 vcpu->arch.osvw.length = data;
2496 break;
2497 case MSR_AMD64_OSVW_STATUS:
d6321d49 2498 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2499 return 1;
2500 vcpu->arch.osvw.status = data;
2501 break;
db2336a8
KH		 2502 case MSR_PLATFORM_INFO:
2503 if (!msr_info->host_initiated ||
2504 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2505 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2506 cpuid_fault_enabled(vcpu)))
2507 return 1;
2508 vcpu->arch.msr_platform_info = data;
2509 break;
2510 case MSR_MISC_FEATURES_ENABLES:
2511 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2512 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2513 !supports_cpuid_fault(vcpu)))
2514 return 1;
2515 vcpu->arch.msr_misc_features_enables = data;
2516 break;
15c4a640 2517 default:
ffde22ac
ES		 2518 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2519 return xen_hvm_config(vcpu, data);
c6702c9d 2520 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2521 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2522 if (!ignore_msrs) {
ae0f5499 2523 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2524 msr, data);
ed85c068
AP		 2525 return 1;
2526 } else {
fab0aa3b
EM		 2527 if (report_ignored_msrs)
2528 vcpu_unimpl(vcpu,
2529 "ignored wrmsr: 0x%x data 0x%llx\n",
2530 msr, data);
ed85c068
AP		 2531 break;
2532 }
15c4a640
CO		 2533 }
2534 return 0;
2535}
2536EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2537
2538
2539/*
2540 * Reads an msr value (of 'msr_index') into 'pdata'.
2541 * Returns 0 on success, non-0 otherwise.
2542 * Assumes vcpu_load() was already called.
2543 */
609e36d3 2544int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2545{
609e36d3 2546 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2547}
ff651cb6 2548EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2549
890ca9ae 2550static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2551{
2552 u64 data;
890ca9ae
HY		 2553 u64 mcg_cap = vcpu->arch.mcg_cap;
2554 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2555
2556 switch (msr) {
15c4a640
CO		 2557 case MSR_IA32_P5_MC_ADDR:
2558 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2559 data = 0;
2560 break;
15c4a640 2561 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2562 data = vcpu->arch.mcg_cap;
2563 break;
c7ac679c 2564 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2565 if (!(mcg_cap & MCG_CTL_P))
2566 return 1;
2567 data = vcpu->arch.mcg_ctl;
2568 break;
2569 case MSR_IA32_MCG_STATUS:
2570 data = vcpu->arch.mcg_status;
2571 break;
2572 default:
2573 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2574 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2575 u32 offset = msr - MSR_IA32_MC0_CTL;
2576 data = vcpu->arch.mce_banks[offset];
2577 break;
2578 }
2579 return 1;
2580 }
2581 *pdata = data;
2582 return 0;
2583}
2584
609e36d3 2585int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2586{
609e36d3 2587 switch (msr_info->index) {
890ca9ae 2588 case MSR_IA32_PLATFORM_ID:
15c4a640 2589 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2590 case MSR_IA32_DEBUGCTLMSR:
2591 case MSR_IA32_LASTBRANCHFROMIP:
2592 case MSR_IA32_LASTBRANCHTOIP:
2593 case MSR_IA32_LASTINTFROMIP:
2594 case MSR_IA32_LASTINTTOIP:
60af2ecd 2595 case MSR_K8_SYSCFG:
3afb1121
PB		 2596 case MSR_K8_TSEG_ADDR:
2597 case MSR_K8_TSEG_MASK:
60af2ecd 2598 case MSR_K7_HWCR:
61a6bd67 2599 case MSR_VM_HSAVE_PA:
1fdbd48c 2600 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2601 case MSR_AMD64_NB_CFG:
f7c6d140 2602 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2603 case MSR_AMD64_BU_CFG2:
0c2df2a1 2604 case MSR_IA32_PERF_CTL:
405a353a 2605 case MSR_AMD64_DC_CFG:
609e36d3 2606 msr_info->data = 0;
15c4a640 2607 break;
c51eb52b 2608 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2609 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2610 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2611 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2612 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2613 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2614 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2615 msr_info->data = 0;
5753785f 2616 break;
742bc670 2617 case MSR_IA32_UCODE_REV:
518e7b94 2618 msr_info->data = vcpu->arch.microcode_version;
742bc670 2619 break;
dd259935
PB		 2620 case MSR_IA32_TSC:
2621 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2622 break;
9ba075a6 2623 case MSR_MTRRcap:
9ba075a6 2624 case 0x200 ... 0x2ff:
ff53604b 2625 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2626 case 0xcd: /* fsb frequency */
609e36d3 2627 msr_info->data = 3;
15c4a640 2628 break;
7b914098
JS		 2629 /*
2630 * MSR_EBC_FREQUENCY_ID
2631 * Conservative value valid for even the basic CPU models.
2632 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2633 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2634 * and 266MHz for model 3, or 4. Set Core Clock
2635 * Frequency to System Bus Frequency Ratio to 1 (bits
2636 * 31:24) even though these are only valid for CPU
2637 * models > 2, however guests may end up dividing or
2638 * multiplying by zero otherwise.
2639 */
2640 case MSR_EBC_FREQUENCY_ID:
609e36d3 2641 msr_info->data = 1 << 24;
7b914098 2642 break;
15c4a640 2643 case MSR_IA32_APICBASE:
609e36d3 2644 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2645 break;
0105d1a5 2646 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2647 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2648 break;
a3e06bbe 2649 case MSR_IA32_TSCDEADLINE:
609e36d3 2650 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2651 break;
ba904635 2652 case MSR_IA32_TSC_ADJUST:
609e36d3 2653 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2654 break;
15c4a640 2655 case MSR_IA32_MISC_ENABLE:
609e36d3 2656 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2657 break;
64d60670
PB		 2658 case MSR_IA32_SMBASE:
2659 if (!msr_info->host_initiated)
2660 return 1;
2661 msr_info->data = vcpu->arch.smbase;
15c4a640 2662 break;
52797bf9
LA		 2663 case MSR_SMI_COUNT:
2664 msr_info->data = vcpu->arch.smi_count;
2665 break;
847f0ad8
AG		 2666 case MSR_IA32_PERF_STATUS:
2667 /* TSC increment by tick */
609e36d3 2668 msr_info->data = 1000ULL;
847f0ad8 2669 /* CPU multiplier */
b0996ae4 2670 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2671 break;
15c4a640 2672 case MSR_EFER:
609e36d3 2673 msr_info->data = vcpu->arch.efer;
15c4a640 2674 break;
18068523 2675 case MSR_KVM_WALL_CLOCK:
11c6bffa 2676 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2677 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2678 break;
2679 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2680 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2681 msr_info->data = vcpu->arch.time;
18068523 2682 break;
344d9588 2683 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2684 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2685 break;
c9aaa895 2686 case MSR_KVM_STEAL_TIME:
609e36d3 2687 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2688 break;
1d92128f 2689 case MSR_KVM_PV_EOI_EN:
609e36d3 2690 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2691 break;
890ca9ae
HY		 2692 case MSR_IA32_P5_MC_ADDR:
2693 case MSR_IA32_P5_MC_TYPE:
2694 case MSR_IA32_MCG_CAP:
2695 case MSR_IA32_MCG_CTL:
2696 case MSR_IA32_MCG_STATUS:
81760dcc 2697 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2698 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2699 case MSR_K7_CLK_CTL:
2700 /*
2701 * Provide expected ramp-up count for K7. All other
2702 * are set to zero, indicating minimum divisors for
2703 * every field.
2704 *
2705 * This prevents guest kernels on AMD host with CPU
2706 * type 6, model 8 and higher from exploding due to
2707 * the rdmsr failing.
2708 */
609e36d3 2709 msr_info->data = 0x20000000;
84e0cefa 2710 break;
55cd8e5a 2711 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2712 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2713 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2714 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2715 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2716 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2717 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887
AS		 2718 return kvm_hv_get_msr_common(vcpu,
2719 msr_info->index, &msr_info->data);
55cd8e5a 2720 break;
91c9c3ed 2721 case MSR_IA32_BBL_CR_CTL3:
2722 /* This legacy MSR exists but isn't fully documented in current
2723 * silicon. It is however accessed by winxp in very narrow
2724 * scenarios where it sets bit #19, itself documented as
2725 * a "reserved" bit. Best effort attempt to source coherent
2726 * read data here should the balance of the register be
2727 * interpreted by the guest:
2728 *
2729 * L2 cache control register 3: 64GB range, 256KB size,
2730 * enabled, latency 0x1, configured
2731 */
609e36d3 2732 msr_info->data = 0xbe702111;
91c9c3ed 2733 break;
2b036c6b 2734 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2735 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2736 return 1;
609e36d3 2737 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2738 break;
2739 case MSR_AMD64_OSVW_STATUS:
d6321d49 2740 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2741 return 1;
609e36d3 2742 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2743 break;
db2336a8
KH		 2744 case MSR_PLATFORM_INFO:
2745 msr_info->data = vcpu->arch.msr_platform_info;
2746 break;
2747 case MSR_MISC_FEATURES_ENABLES:
2748 msr_info->data = vcpu->arch.msr_misc_features_enables;
2749 break;
15c4a640 2750 default:
c6702c9d 2751 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2752 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2753 if (!ignore_msrs) {
ae0f5499
BD		 2754 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2755 msr_info->index);
ed85c068
AP		 2756 return 1;
2757 } else {
fab0aa3b
EM		 2758 if (report_ignored_msrs)
2759 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2760 msr_info->index);
609e36d3 2761 msr_info->data = 0;
ed85c068
AP		 2762 }
2763 break;
15c4a640 2764 }
15c4a640
CO		 2765 return 0;
2766}
2767EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2768
313a3dc7
CO		 2769/*
2770 * Read or write a bunch of msrs. All parameters are kernel addresses.
2771 *
2772 * @return number of msrs set successfully.
2773 */
2774static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2775 struct kvm_msr_entry *entries,
2776 int (*do_msr)(struct kvm_vcpu *vcpu,
2777 unsigned index, u64 *data))
2778{
801e459a 2779 int i;
313a3dc7 2780
313a3dc7
CO		 2781 for (i = 0; i < msrs->nmsrs; ++i)
2782 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2783 break;
2784
313a3dc7
CO		 2785 return i;
2786}
2787
2788/*
2789 * Read or write a bunch of msrs. Parameters are user addresses.
2790 *
2791 * @return number of msrs set successfully.
2792 */
2793static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2794 int (*do_msr)(struct kvm_vcpu *vcpu,
2795 unsigned index, u64 *data),
2796 int writeback)
2797{
2798 struct kvm_msrs msrs;
2799 struct kvm_msr_entry *entries;
2800 int r, n;
2801 unsigned size;
2802
2803 r = -EFAULT;
2804 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2805 goto out;
2806
2807 r = -E2BIG;
2808 if (msrs.nmsrs >= MAX_IO_MSRS)
2809 goto out;
2810
313a3dc7 2811 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2812 entries = memdup_user(user_msrs->entries, size);
2813 if (IS_ERR(entries)) {
2814 r = PTR_ERR(entries);
313a3dc7 2815 goto out;
ff5c2c03 2816 }
313a3dc7
CO		 2817
2818 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2819 if (r < 0)
2820 goto out_free;
2821
2822 r = -EFAULT;
2823 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2824 goto out_free;
2825
2826 r = n;
2827
2828out_free:
7a73c028 2829 kfree(entries);
313a3dc7
CO		 2830out:
2831 return r;
2832}
2833
4d5422ce
WL		 2834static inline bool kvm_can_mwait_in_guest(void)
2835{
2836 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2837 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2838 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2839}
2840
784aa3d7 2841int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2842{
4d5422ce 2843 int r = 0;
018d00d2
ZX		 2844
2845 switch (ext) {
2846 case KVM_CAP_IRQCHIP:
2847 case KVM_CAP_HLT:
2848 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2849 case KVM_CAP_SET_TSS_ADDR:
07716717 2850 case KVM_CAP_EXT_CPUID:
9c15bb1d 2851 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2852 case KVM_CAP_CLOCKSOURCE:
7837699f 2853 case KVM_CAP_PIT:
a28e4f5a 2854 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2855 case KVM_CAP_MP_STATE:
ed848624 2856 case KVM_CAP_SYNC_MMU:
a355c85c 2857 case KVM_CAP_USER_NMI:
52d939a0 2858 case KVM_CAP_REINJECT_CONTROL:
4925663a 2859 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2860 case KVM_CAP_IOEVENTFD:
f848a5a8 2861 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2862 case KVM_CAP_PIT2:
e9f42757 2863 case KVM_CAP_PIT_STATE2:
b927a3ce 2864 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2865 case KVM_CAP_XEN_HVM:
3cfc3092 2866 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2867 case KVM_CAP_HYPERV:
10388a07 2868 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2869 case KVM_CAP_HYPERV_SPIN:
5c919412 2870 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2871 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2872 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2873 case KVM_CAP_HYPERV_EVENTFD:
ab9f4ecb 2874 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2875 case KVM_CAP_DEBUGREGS:
d2be1651 2876 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2877 case KVM_CAP_XSAVE:
344d9588 2878 case KVM_CAP_ASYNC_PF:
92a1f12d 2879 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2880 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2881 case KVM_CAP_READONLY_MEM:
5f66b620 2882 case KVM_CAP_HYPERV_TIME:
100943c5 2883 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2884 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2885 case KVM_CAP_ENABLE_CAP_VM:
2886 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2887 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2888 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2889 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2890 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2891 r = 1;
2892 break;
01643c51
KH		 2893 case KVM_CAP_SYNC_REGS:
2894 r = KVM_SYNC_X86_VALID_FIELDS;
2895 break;
e3fd9a93
PB		 2896 case KVM_CAP_ADJUST_CLOCK:
2897 r = KVM_CLOCK_TSC_STABLE;
2898 break;
4d5422ce 2899 case KVM_CAP_X86_DISABLE_EXITS:
b31c114b 2900 r |= KVM_X86_DISABLE_EXITS_HTL | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2901 if(kvm_can_mwait_in_guest())
2902 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2903 break;
6d396b55
PB		 2904 case KVM_CAP_X86_SMM:
2905 /* SMBASE is usually relocated above 1M on modern chipsets,
2906 * and SMM handlers might indeed rely on 4G segment limits,
2907 * so do not report SMM to be available if real mode is
2908 * emulated via vm86 mode. Still, do not go to great lengths
2909 * to avoid userspace's usage of the feature, because it is a
2910 * fringe case that is not enabled except via specific settings
2911 * of the module parameters.
2912 */
2913 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2914 break;
774ead3a
AK		 2915 case KVM_CAP_VAPIC:
2916 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2917 break;
f725230a 2918 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2919 r = KVM_SOFT_MAX_VCPUS;
2920 break;
2921 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2922 r = KVM_MAX_VCPUS;
2923 break;
a988b910 2924 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2925 r = KVM_USER_MEM_SLOTS;
a988b910 2926 break;
a68a6a72
MT		 2927 case KVM_CAP_PV_MMU: /* obsolete */
2928 r = 0;
2f333bcb 2929 break;
890ca9ae
HY		 2930 case KVM_CAP_MCE:
2931 r = KVM_MAX_MCE_BANKS;
2932 break;
2d5b5a66 2933 case KVM_CAP_XCRS:
d366bf7e 2934 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2935 break;
92a1f12d
JR		 2936 case KVM_CAP_TSC_CONTROL:
2937 r = kvm_has_tsc_control;
2938 break;
37131313
RK		 2939 case KVM_CAP_X2APIC_API:
2940 r = KVM_X2APIC_API_VALID_FLAGS;
2941 break;
018d00d2 2942 default:
018d00d2
ZX		 2943 break;
2944 }
2945 return r;
2946
2947}
2948
043405e1
CO		 2949long kvm_arch_dev_ioctl(struct file *filp,
2950 unsigned int ioctl, unsigned long arg)
2951{
2952 void __user *argp = (void __user *)arg;
2953 long r;
2954
2955 switch (ioctl) {
2956 case KVM_GET_MSR_INDEX_LIST: {
2957 struct kvm_msr_list __user *user_msr_list = argp;
2958 struct kvm_msr_list msr_list;
2959 unsigned n;
2960
2961 r = -EFAULT;
2962 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2963 goto out;
2964 n = msr_list.nmsrs;
62ef68bb 2965 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2966 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2967 goto out;
2968 r = -E2BIG;
e125e7b6 2969 if (n < msr_list.nmsrs)
043405e1
CO		 2970 goto out;
2971 r = -EFAULT;
2972 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2973 num_msrs_to_save * sizeof(u32)))
2974 goto out;
e125e7b6 2975 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2976 &emulated_msrs,
62ef68bb 2977 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2978 goto out;
2979 r = 0;
2980 break;
2981 }
9c15bb1d
BP		 2982 case KVM_GET_SUPPORTED_CPUID:
2983 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2984 struct kvm_cpuid2 __user *cpuid_arg = argp;
2985 struct kvm_cpuid2 cpuid;
2986
2987 r = -EFAULT;
2988 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2989 goto out;
9c15bb1d
BP		 2990
2991 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2992 ioctl);
674eea0f
AK		 2993 if (r)
2994 goto out;
2995
2996 r = -EFAULT;
2997 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2998 goto out;
2999 r = 0;
3000 break;
3001 }
890ca9ae 3002 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3003 r = -EFAULT;
c45dcc71
AR		 3004 if (copy_to_user(argp, &kvm_mce_cap_supported,
3005 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3006 goto out;
3007 r = 0;
3008 break;
801e459a
TL		 3009 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3010 struct kvm_msr_list __user *user_msr_list = argp;
3011 struct kvm_msr_list msr_list;
3012 unsigned int n;
3013
3014 r = -EFAULT;
3015 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3016 goto out;
3017 n = msr_list.nmsrs;
3018 msr_list.nmsrs = num_msr_based_features;
3019 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3020 goto out;
3021 r = -E2BIG;
3022 if (n < msr_list.nmsrs)
3023 goto out;
3024 r = -EFAULT;
3025 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3026 num_msr_based_features * sizeof(u32)))
3027 goto out;
3028 r = 0;
3029 break;
3030 }
3031 case KVM_GET_MSRS:
3032 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3033 break;
890ca9ae 3034 }
043405e1
CO		 3035 default:
3036 r = -EINVAL;
3037 }
3038out:
3039 return r;
3040}
3041
f5f48ee1
SY		 3042static void wbinvd_ipi(void *garbage)
3043{
3044 wbinvd();
3045}
3046
3047static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3048{
e0f0bbc5 3049 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3050}
3051
313a3dc7
CO		 3052void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3053{
f5f48ee1
SY		 3054 /* Address WBINVD may be executed by guest */
3055 if (need_emulate_wbinvd(vcpu)) {
3056 if (kvm_x86_ops->has_wbinvd_exit())
3057 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3058 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3059 smp_call_function_single(vcpu->cpu,
3060 wbinvd_ipi, NULL, 1);
3061 }
3062
313a3dc7 3063 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3064
0dd6a6ed
ZA		 3065 /* Apply any externally detected TSC adjustments (due to suspend) */
3066 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3067 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3068 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3069 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3070 }
8f6055cb 3071
b0c39dc6 3072 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3073 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3074 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3075 if (tsc_delta < 0)
3076 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3077
b0c39dc6 3078 if (kvm_check_tsc_unstable()) {
07c1419a 3079 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3080 vcpu->arch.last_guest_tsc);
a545ab6a 3081 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3082 vcpu->arch.tsc_catchup = 1;
c285545f 3083 }
a749e247
PB		 3084
3085 if (kvm_lapic_hv_timer_in_use(vcpu))
3086 kvm_lapic_restart_hv_timer(vcpu);
3087
d98d07ca
MT		 3088 /*
3089 * On a host with synchronized TSC, there is no need to update
3090 * kvmclock on vcpu->cpu migration
3091 */
3092 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3093 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3094 if (vcpu->cpu != cpu)
1bd2009e 3095 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3096 vcpu->cpu = cpu;
6b7d7e76 3097 }
c9aaa895 3098
c9aaa895 3099 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3100}
3101
0b9f6c46
PX		 3102static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3103{
3104 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3105 return;
3106
fa55eedd 3107 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3108
4e335d9e 3109 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3110 &vcpu->arch.st.steal.preempted,
3111 offsetof(struct kvm_steal_time, preempted),
3112 sizeof(vcpu->arch.st.steal.preempted));
3113}
3114
313a3dc7
CO		 3115void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3116{
cc0d907c 3117 int idx;
de63ad4c
LM		 3118
3119 if (vcpu->preempted)
3120 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3121
931f261b
AA		 3122 /*
3123 * Disable page faults because we're in atomic context here.
3124 * kvm_write_guest_offset_cached() would call might_fault()
3125 * that relies on pagefault_disable() to tell if there's a
3126 * bug. NOTE: the write to guest memory may not go through if
3127 * during postcopy live migration or if there's heavy guest
3128 * paging.
3129 */
3130 pagefault_disable();
cc0d907c
AA		 3131 /*
3132 * kvm_memslots() will be called by
3133 * kvm_write_guest_offset_cached() so take the srcu lock.
3134 */
3135 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3136 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3137 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3138 pagefault_enable();
02daab21 3139 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3140 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3141 /*
3142 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3143 * on every vmexit, but if not, we might have a stale dr6 from the
3144 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3145 */
3146 set_debugreg(0, 6);
313a3dc7
CO		 3147}
3148
313a3dc7
CO		 3149static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3150 struct kvm_lapic_state *s)
3151{
fa59cc00 3152 if (vcpu->arch.apicv_active)
d62caabb
AS		 3153 kvm_x86_ops->sync_pir_to_irr(vcpu);
3154
a92e2543 3155 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3156}
3157
3158static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3159 struct kvm_lapic_state *s)
3160{
a92e2543
RK		 3161 int r;
3162
3163 r = kvm_apic_set_state(vcpu, s);
3164 if (r)
3165 return r;
cb142eb7 3166 update_cr8_intercept(vcpu);
313a3dc7
CO		 3167
3168 return 0;
3169}
3170
127a457a
MG		 3171static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3172{
3173 return (!lapic_in_kernel(vcpu) ||
3174 kvm_apic_accept_pic_intr(vcpu));
3175}
3176
782d422b
MG		 3177/*
3178 * if userspace requested an interrupt window, check that the
3179 * interrupt window is open.
3180 *
3181 * No need to exit to userspace if we already have an interrupt queued.
3182 */
3183static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3184{
3185 return kvm_arch_interrupt_allowed(vcpu) &&
3186 !kvm_cpu_has_interrupt(vcpu) &&
3187 !kvm_event_needs_reinjection(vcpu) &&
3188 kvm_cpu_accept_dm_intr(vcpu);
3189}
3190
f77bc6a4
ZX		 3191static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3192 struct kvm_interrupt *irq)
3193{
02cdb50f 3194 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3195 return -EINVAL;
1c1a9ce9
SR		 3196
3197 if (!irqchip_in_kernel(vcpu->kvm)) {
3198 kvm_queue_interrupt(vcpu, irq->irq, false);
3199 kvm_make_request(KVM_REQ_EVENT, vcpu);
3200 return 0;
3201 }
3202
3203 /*
3204 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3205 * fail for in-kernel 8259.
3206 */
3207 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3208 return -ENXIO;
f77bc6a4 3209
1c1a9ce9
SR		 3210 if (vcpu->arch.pending_external_vector != -1)
3211 return -EEXIST;
f77bc6a4 3212
1c1a9ce9 3213 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3214 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3215 return 0;
3216}
3217
c4abb7c9
JK		 3218static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3219{
c4abb7c9 3220 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3221
3222 return 0;
3223}
3224
f077825a
PB		 3225static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3226{
64d60670
PB		 3227 kvm_make_request(KVM_REQ_SMI, vcpu);
3228
f077825a
PB		 3229 return 0;
3230}
3231
b209749f
AK		 3232static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3233 struct kvm_tpr_access_ctl *tac)
3234{
3235 if (tac->flags)
3236 return -EINVAL;
3237 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3238 return 0;
3239}
3240
890ca9ae
HY		 3241static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3242 u64 mcg_cap)
3243{
3244 int r;
3245 unsigned bank_num = mcg_cap & 0xff, bank;
3246
3247 r = -EINVAL;
a9e38c3e 3248 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3249 goto out;
c45dcc71 3250 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3251 goto out;
3252 r = 0;
3253 vcpu->arch.mcg_cap = mcg_cap;
3254 /* Init IA32_MCG_CTL to all 1s */
3255 if (mcg_cap & MCG_CTL_P)
3256 vcpu->arch.mcg_ctl = ~(u64)0;
3257 /* Init IA32_MCi_CTL to all 1s */
3258 for (bank = 0; bank < bank_num; bank++)
3259 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3260
3261 if (kvm_x86_ops->setup_mce)
3262 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3263out:
3264 return r;
3265}
3266
3267static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3268 struct kvm_x86_mce *mce)
3269{
3270 u64 mcg_cap = vcpu->arch.mcg_cap;
3271 unsigned bank_num = mcg_cap & 0xff;
3272 u64 *banks = vcpu->arch.mce_banks;
3273
3274 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3275 return -EINVAL;
3276 /*
3277 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3278 * reporting is disabled
3279 */
3280 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3281 vcpu->arch.mcg_ctl != ~(u64)0)
3282 return 0;
3283 banks += 4 * mce->bank;
3284 /*
3285 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3286 * reporting is disabled for the bank
3287 */
3288 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3289 return 0;
3290 if (mce->status & MCI_STATUS_UC) {
3291 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3292 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3293 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3294 return 0;
3295 }
3296 if (banks[1] & MCI_STATUS_VAL)
3297 mce->status |= MCI_STATUS_OVER;
3298 banks[2] = mce->addr;
3299 banks[3] = mce->misc;
3300 vcpu->arch.mcg_status = mce->mcg_status;
3301 banks[1] = mce->status;
3302 kvm_queue_exception(vcpu, MC_VECTOR);
3303 } else if (!(banks[1] & MCI_STATUS_VAL)
3304 || !(banks[1] & MCI_STATUS_UC)) {
3305 if (banks[1] & MCI_STATUS_VAL)
3306 mce->status |= MCI_STATUS_OVER;
3307 banks[2] = mce->addr;
3308 banks[3] = mce->misc;
3309 banks[1] = mce->status;
3310 } else
3311 banks[1] |= MCI_STATUS_OVER;
3312 return 0;
3313}
3314
3cfc3092
JK		 3315static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3316 struct kvm_vcpu_events *events)
3317{
7460fb4a 3318 process_nmi(vcpu);
664f8e26
WL		 3319 /*
3320 * FIXME: pass injected and pending separately. This is only
3321 * needed for nested virtualization, whose state cannot be
3322 * migrated yet. For now we can combine them.
3323 */
03b82a30 3324 events->exception.injected =
664f8e26
WL		 3325 (vcpu->arch.exception.pending ||
3326 vcpu->arch.exception.injected) &&
03b82a30 3327 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3328 events->exception.nr = vcpu->arch.exception.nr;
3329 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3330 events->exception.pad = 0;
3cfc3092
JK		 3331 events->exception.error_code = vcpu->arch.exception.error_code;
3332
03b82a30 3333 events->interrupt.injected =
04140b41 3334 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3335 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3336 events->interrupt.soft = 0;
37ccdcbe 3337 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3338
3339 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3340 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3341 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3342 events->nmi.pad = 0;
3cfc3092 3343
66450a21 3344 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3345
f077825a
PB		 3346 events->smi.smm = is_smm(vcpu);
3347 events->smi.pending = vcpu->arch.smi_pending;
3348 events->smi.smm_inside_nmi =
3349 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3350 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3351
dab4b911 3352 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3353 | KVM_VCPUEVENT_VALID_SHADOW
3354 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3355 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3356}
3357
6ef4e07e
XG		 3358static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3359
3cfc3092
JK		 3360static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3361 struct kvm_vcpu_events *events)
3362{
dab4b911 3363 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3364 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3365 | KVM_VCPUEVENT_VALID_SHADOW
3366 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3367 return -EINVAL;
3368
78e546c8 3369 if (events->exception.injected &&
28d06353
JM		 3370 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3371 is_guest_mode(vcpu)))
78e546c8
PB		 3372 return -EINVAL;
3373
28bf2888
DH		 3374 /* INITs are latched while in SMM */
3375 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3376 (events->smi.smm || events->smi.pending) &&
3377 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3378 return -EINVAL;
3379
7460fb4a 3380 process_nmi(vcpu);
664f8e26 3381 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3382 vcpu->arch.exception.pending = events->exception.injected;
3383 vcpu->arch.exception.nr = events->exception.nr;
3384 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3385 vcpu->arch.exception.error_code = events->exception.error_code;
3386
04140b41 3387 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3388 vcpu->arch.interrupt.nr = events->interrupt.nr;
3389 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3390 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3391 kvm_x86_ops->set_interrupt_shadow(vcpu,
3392 events->interrupt.shadow);
3cfc3092
JK		 3393
3394 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3395 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3396 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3397 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3398
66450a21 3399 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3400 lapic_in_kernel(vcpu))
66450a21 3401 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3402
f077825a 3403 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3404 u32 hflags = vcpu->arch.hflags;
f077825a 3405 if (events->smi.smm)
6ef4e07e 3406 hflags |= HF_SMM_MASK;
f077825a 3407 else
6ef4e07e
XG		 3408 hflags &= ~HF_SMM_MASK;
3409 kvm_set_hflags(vcpu, hflags);
3410
f077825a 3411 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3412
3413 if (events->smi.smm) {
3414 if (events->smi.smm_inside_nmi)
3415 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3416 else
f4ef1910
WL		 3417 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3418 if (lapic_in_kernel(vcpu)) {
3419 if (events->smi.latched_init)
3420 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3421 else
3422 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3423 }
f077825a
PB		 3424 }
3425 }
3426
3842d135
AK		 3427 kvm_make_request(KVM_REQ_EVENT, vcpu);
3428
3cfc3092
JK		 3429 return 0;
3430}
3431
a1efbe77
JK		 3432static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3433 struct kvm_debugregs *dbgregs)
3434{
73aaf249
JK		 3435 unsigned long val;
3436
a1efbe77 3437 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3438 kvm_get_dr(vcpu, 6, &val);
73aaf249 3439 dbgregs->dr6 = val;
a1efbe77
JK		 3440 dbgregs->dr7 = vcpu->arch.dr7;
3441 dbgregs->flags = 0;
97e69aa6 3442 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3443}
3444
3445static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3446 struct kvm_debugregs *dbgregs)
3447{
3448 if (dbgregs->flags)
3449 return -EINVAL;
3450
d14bdb55
PB		 3451 if (dbgregs->dr6 & ~0xffffffffull)
3452 return -EINVAL;
3453 if (dbgregs->dr7 & ~0xffffffffull)
3454 return -EINVAL;
3455
a1efbe77 3456 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3457 kvm_update_dr0123(vcpu);
a1efbe77 3458 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3459 kvm_update_dr6(vcpu);
a1efbe77 3460 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3461 kvm_update_dr7(vcpu);
a1efbe77 3462
a1efbe77
JK		 3463 return 0;
3464}
3465
df1daba7
PB		 3466#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3467
3468static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3469{
c47ada30 3470 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3471 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3472 u64 valid;
3473
3474 /*
3475 * Copy legacy XSAVE area, to avoid complications with CPUID
3476 * leaves 0 and 1 in the loop below.
3477 */
3478 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3479
3480 /* Set XSTATE_BV */
00c87e9a 3481 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3482 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3483
3484 /*
3485 * Copy each region from the possibly compacted offset to the
3486 * non-compacted offset.
3487 */
d91cab78 3488 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3489 while (valid) {
3490 u64 feature = valid & -valid;
3491 int index = fls64(feature) - 1;
3492 void *src = get_xsave_addr(xsave, feature);
3493
3494 if (src) {
3495 u32 size, offset, ecx, edx;
3496 cpuid_count(XSTATE_CPUID, index,
3497 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3498 if (feature == XFEATURE_MASK_PKRU)
3499 memcpy(dest + offset, &vcpu->arch.pkru,
3500 sizeof(vcpu->arch.pkru));
3501 else
3502 memcpy(dest + offset, src, size);
3503
df1daba7
PB		 3504 }
3505
3506 valid -= feature;
3507 }
3508}
3509
3510static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3511{
c47ada30 3512 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3513 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3514 u64 valid;
3515
3516 /*
3517 * Copy legacy XSAVE area, to avoid complications with CPUID
3518 * leaves 0 and 1 in the loop below.
3519 */
3520 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3521
3522 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3523 xsave->header.xfeatures = xstate_bv;
782511b0 3524 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3525 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3526
3527 /*
3528 * Copy each region from the non-compacted offset to the
3529 * possibly compacted offset.
3530 */
d91cab78 3531 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3532 while (valid) {
3533 u64 feature = valid & -valid;
3534 int index = fls64(feature) - 1;
3535 void *dest = get_xsave_addr(xsave, feature);
3536
3537 if (dest) {
3538 u32 size, offset, ecx, edx;
3539 cpuid_count(XSTATE_CPUID, index,
3540 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3541 if (feature == XFEATURE_MASK_PKRU)
3542 memcpy(&vcpu->arch.pkru, src + offset,
3543 sizeof(vcpu->arch.pkru));
3544 else
3545 memcpy(dest, src + offset, size);
ee4100da 3546 }
df1daba7
PB		 3547
3548 valid -= feature;
3549 }
3550}
3551
2d5b5a66
SY		 3552static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3553 struct kvm_xsave *guest_xsave)
3554{
d366bf7e 3555 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3556 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3557 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3558 } else {
2d5b5a66 3559 memcpy(guest_xsave->region,
7366ed77 3560 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3561 sizeof(struct fxregs_state));
2d5b5a66 3562 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3563 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3564 }
3565}
3566
a575813b
WL		 3567#define XSAVE_MXCSR_OFFSET 24
3568
2d5b5a66
SY		 3569static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3570 struct kvm_xsave *guest_xsave)
3571{
3572 u64 xstate_bv =
3573 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3574 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3575
d366bf7e 3576 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3577 /*
3578 * Here we allow setting states that are not present in
3579 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3580 * with old userspace.
3581 */
a575813b
WL		 3582 if (xstate_bv & ~kvm_supported_xcr0() ||
3583 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3584 return -EINVAL;
df1daba7 3585 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3586 } else {
a575813b
WL		 3587 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3588 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3589 return -EINVAL;
7366ed77 3590 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3591 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3592 }
3593 return 0;
3594}
3595
3596static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3597 struct kvm_xcrs *guest_xcrs)
3598{
d366bf7e 3599 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3600 guest_xcrs->nr_xcrs = 0;
3601 return;
3602 }
3603
3604 guest_xcrs->nr_xcrs = 1;
3605 guest_xcrs->flags = 0;
3606 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3607 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3608}
3609
3610static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3611 struct kvm_xcrs *guest_xcrs)
3612{
3613 int i, r = 0;
3614
d366bf7e 3615 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3616 return -EINVAL;
3617
3618 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3619 return -EINVAL;
3620
3621 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3622 /* Only support XCR0 currently */
c67a04cb 3623 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3624 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3625 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3626 break;
3627 }
3628 if (r)
3629 r = -EINVAL;
3630 return r;
3631}
3632
1c0b28c2
EM		 3633/*
3634 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3635 * stopped by the hypervisor. This function will be called from the host only.
3636 * EINVAL is returned when the host attempts to set the flag for a guest that
3637 * does not support pv clocks.
3638 */
3639static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3640{
0b79459b 3641 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3642 return -EINVAL;
51d59c6b 3643 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3644 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3645 return 0;
3646}
3647
5c919412
AS		 3648static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3649 struct kvm_enable_cap *cap)
3650{
3651 if (cap->flags)
3652 return -EINVAL;
3653
3654 switch (cap->cap) {
efc479e6
RK		 3655 case KVM_CAP_HYPERV_SYNIC2:
3656 if (cap->args[0])
3657 return -EINVAL;
5c919412 3658 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3659 if (!irqchip_in_kernel(vcpu->kvm))
3660 return -EINVAL;
efc479e6
RK		 3661 return kvm_hv_activate_synic(vcpu, cap->cap ==
3662 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3663 default:
3664 return -EINVAL;
3665 }
3666}
3667
313a3dc7
CO		 3668long kvm_arch_vcpu_ioctl(struct file *filp,
3669 unsigned int ioctl, unsigned long arg)
3670{
3671 struct kvm_vcpu *vcpu = filp->private_data;
3672 void __user *argp = (void __user *)arg;
3673 int r;
d1ac91d8
AK		 3674 union {
3675 struct kvm_lapic_state *lapic;
3676 struct kvm_xsave *xsave;
3677 struct kvm_xcrs *xcrs;
3678 void *buffer;
3679 } u;
3680
9b062471
CD		 3681 vcpu_load(vcpu);
3682
d1ac91d8 3683 u.buffer = NULL;
313a3dc7
CO		 3684 switch (ioctl) {
3685 case KVM_GET_LAPIC: {
2204ae3c 3686 r = -EINVAL;
bce87cce 3687 if (!lapic_in_kernel(vcpu))
2204ae3c 3688 goto out;
d1ac91d8 3689 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3690
b772ff36 3691 r = -ENOMEM;
d1ac91d8 3692 if (!u.lapic)
b772ff36 3693 goto out;
d1ac91d8 3694 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3695 if (r)
3696 goto out;
3697 r = -EFAULT;
d1ac91d8 3698 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3699 goto out;
3700 r = 0;
3701 break;
3702 }
3703 case KVM_SET_LAPIC: {
2204ae3c 3704 r = -EINVAL;
bce87cce 3705 if (!lapic_in_kernel(vcpu))
2204ae3c 3706 goto out;
ff5c2c03 3707 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3708 if (IS_ERR(u.lapic)) {
3709 r = PTR_ERR(u.lapic);
3710 goto out_nofree;
3711 }
ff5c2c03 3712
d1ac91d8 3713 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3714 break;
3715 }
f77bc6a4
ZX		 3716 case KVM_INTERRUPT: {
3717 struct kvm_interrupt irq;
3718
3719 r = -EFAULT;
3720 if (copy_from_user(&irq, argp, sizeof irq))
3721 goto out;
3722 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3723 break;
3724 }
c4abb7c9
JK		 3725 case KVM_NMI: {
3726 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3727 break;
3728 }
f077825a
PB		 3729 case KVM_SMI: {
3730 r = kvm_vcpu_ioctl_smi(vcpu);
3731 break;
3732 }
313a3dc7
CO		 3733 case KVM_SET_CPUID: {
3734 struct kvm_cpuid __user *cpuid_arg = argp;
3735 struct kvm_cpuid cpuid;
3736
3737 r = -EFAULT;
3738 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3739 goto out;
3740 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3741 break;
3742 }
07716717
DK		 3743 case KVM_SET_CPUID2: {
3744 struct kvm_cpuid2 __user *cpuid_arg = argp;
3745 struct kvm_cpuid2 cpuid;
3746
3747 r = -EFAULT;
3748 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3749 goto out;
3750 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3751 cpuid_arg->entries);
07716717
DK		 3752 break;
3753 }
3754 case KVM_GET_CPUID2: {
3755 struct kvm_cpuid2 __user *cpuid_arg = argp;
3756 struct kvm_cpuid2 cpuid;
3757
3758 r = -EFAULT;
3759 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3760 goto out;
3761 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3762 cpuid_arg->entries);
07716717
DK		 3763 if (r)
3764 goto out;
3765 r = -EFAULT;
3766 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3767 goto out;
3768 r = 0;
3769 break;
3770 }
801e459a
TL		 3771 case KVM_GET_MSRS: {
3772 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3773 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3774 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3775 break;
801e459a
TL		 3776 }
3777 case KVM_SET_MSRS: {
3778 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3779 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3780 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3781 break;
801e459a 3782 }
b209749f
AK		 3783 case KVM_TPR_ACCESS_REPORTING: {
3784 struct kvm_tpr_access_ctl tac;
3785
3786 r = -EFAULT;
3787 if (copy_from_user(&tac, argp, sizeof tac))
3788 goto out;
3789 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3790 if (r)
3791 goto out;
3792 r = -EFAULT;
3793 if (copy_to_user(argp, &tac, sizeof tac))
3794 goto out;
3795 r = 0;
3796 break;
3797 };
b93463aa
AK		 3798 case KVM_SET_VAPIC_ADDR: {
3799 struct kvm_vapic_addr va;
7301d6ab 3800 int idx;
b93463aa
AK		 3801
3802 r = -EINVAL;
35754c98 3803 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3804 goto out;
3805 r = -EFAULT;
3806 if (copy_from_user(&va, argp, sizeof va))
3807 goto out;
7301d6ab 3808 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3809 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3810 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3811 break;
3812 }
890ca9ae
HY		 3813 case KVM_X86_SETUP_MCE: {
3814 u64 mcg_cap;
3815
3816 r = -EFAULT;
3817 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3818 goto out;
3819 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3820 break;
3821 }
3822 case KVM_X86_SET_MCE: {
3823 struct kvm_x86_mce mce;
3824
3825 r = -EFAULT;
3826 if (copy_from_user(&mce, argp, sizeof mce))
3827 goto out;
3828 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3829 break;
3830 }
3cfc3092
JK		 3831 case KVM_GET_VCPU_EVENTS: {
3832 struct kvm_vcpu_events events;
3833
3834 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3835
3836 r = -EFAULT;
3837 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3838 break;
3839 r = 0;
3840 break;
3841 }
3842 case KVM_SET_VCPU_EVENTS: {
3843 struct kvm_vcpu_events events;
3844
3845 r = -EFAULT;
3846 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3847 break;
3848
3849 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3850 break;
3851 }
a1efbe77
JK		 3852 case KVM_GET_DEBUGREGS: {
3853 struct kvm_debugregs dbgregs;
3854
3855 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3856
3857 r = -EFAULT;
3858 if (copy_to_user(argp, &dbgregs,
3859 sizeof(struct kvm_debugregs)))
3860 break;
3861 r = 0;
3862 break;
3863 }
3864 case KVM_SET_DEBUGREGS: {
3865 struct kvm_debugregs dbgregs;
3866
3867 r = -EFAULT;
3868 if (copy_from_user(&dbgregs, argp,
3869 sizeof(struct kvm_debugregs)))
3870 break;
3871
3872 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3873 break;
3874 }
2d5b5a66 3875 case KVM_GET_XSAVE: {
d1ac91d8 3876 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3877 r = -ENOMEM;
d1ac91d8 3878 if (!u.xsave)
2d5b5a66
SY		 3879 break;
3880
d1ac91d8 3881 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3882
3883 r = -EFAULT;
d1ac91d8 3884 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3885 break;
3886 r = 0;
3887 break;
3888 }
3889 case KVM_SET_XSAVE: {
ff5c2c03 3890 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3891 if (IS_ERR(u.xsave)) {
3892 r = PTR_ERR(u.xsave);
3893 goto out_nofree;
3894 }
2d5b5a66 3895
d1ac91d8 3896 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3897 break;
3898 }
3899 case KVM_GET_XCRS: {
d1ac91d8 3900 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3901 r = -ENOMEM;
d1ac91d8 3902 if (!u.xcrs)
2d5b5a66
SY		 3903 break;
3904
d1ac91d8 3905 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3906
3907 r = -EFAULT;
d1ac91d8 3908 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3909 sizeof(struct kvm_xcrs)))
3910 break;
3911 r = 0;
3912 break;
3913 }
3914 case KVM_SET_XCRS: {
ff5c2c03 3915 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3916 if (IS_ERR(u.xcrs)) {
3917 r = PTR_ERR(u.xcrs);
3918 goto out_nofree;
3919 }
2d5b5a66 3920
d1ac91d8 3921 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3922 break;
3923 }
92a1f12d
JR		 3924 case KVM_SET_TSC_KHZ: {
3925 u32 user_tsc_khz;
3926
3927 r = -EINVAL;
92a1f12d
JR		 3928 user_tsc_khz = (u32)arg;
3929
3930 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3931 goto out;
3932
cc578287
ZA		 3933 if (user_tsc_khz == 0)
3934 user_tsc_khz = tsc_khz;
3935
381d585c
HZ		 3936 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3937 r = 0;
92a1f12d 3938
92a1f12d
JR		 3939 goto out;
3940 }
3941 case KVM_GET_TSC_KHZ: {
cc578287 3942 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3943 goto out;
3944 }
1c0b28c2
EM		 3945 case KVM_KVMCLOCK_CTRL: {
3946 r = kvm_set_guest_paused(vcpu);
3947 goto out;
3948 }
5c919412
AS		 3949 case KVM_ENABLE_CAP: {
3950 struct kvm_enable_cap cap;
3951
3952 r = -EFAULT;
3953 if (copy_from_user(&cap, argp, sizeof(cap)))
3954 goto out;
3955 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3956 break;
3957 }
313a3dc7
CO		 3958 default:
3959 r = -EINVAL;
3960 }
3961out:
d1ac91d8 3962 kfree(u.buffer);
9b062471
CD		 3963out_nofree:
3964 vcpu_put(vcpu);
313a3dc7
CO		 3965 return r;
3966}
3967
5b1c1493
CO		 3968int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3969{
3970 return VM_FAULT_SIGBUS;
3971}
3972
1fe779f8
CO		 3973static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3974{
3975 int ret;
3976
3977 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3978 return -EINVAL;
1fe779f8
CO		 3979 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3980 return ret;
3981}
3982
b927a3ce
SY		 3983static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3984 u64 ident_addr)
3985{
2ac52ab8 3986 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3987}
3988
1fe779f8
CO		 3989static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3990 u32 kvm_nr_mmu_pages)
3991{
3992 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3993 return -EINVAL;
3994
79fac95e 3995 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3996
3997 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3998 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3999
79fac95e 4000 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4001 return 0;
4002}
4003
4004static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4005{
39de71ec 4006 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4007}
4008
1fe779f8
CO		 4009static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4010{
90bca052 4011 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4012 int r;
4013
4014 r = 0;
4015 switch (chip->chip_id) {
4016 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4017 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4018 sizeof(struct kvm_pic_state));
4019 break;
4020 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4021 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4022 sizeof(struct kvm_pic_state));
4023 break;
4024 case KVM_IRQCHIP_IOAPIC:
33392b49 4025 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4026 break;
4027 default:
4028 r = -EINVAL;
4029 break;
4030 }
4031 return r;
4032}
4033
4034static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4035{
90bca052 4036 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4037 int r;
4038
4039 r = 0;
4040 switch (chip->chip_id) {
4041 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4042 spin_lock(&pic->lock);
4043 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4044 sizeof(struct kvm_pic_state));
90bca052 4045 spin_unlock(&pic->lock);
1fe779f8
CO		 4046 break;
4047 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4048 spin_lock(&pic->lock);
4049 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4050 sizeof(struct kvm_pic_state));
90bca052 4051 spin_unlock(&pic->lock);
1fe779f8
CO		 4052 break;
4053 case KVM_IRQCHIP_IOAPIC:
33392b49 4054 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4055 break;
4056 default:
4057 r = -EINVAL;
4058 break;
4059 }
90bca052 4060 kvm_pic_update_irq(pic);
1fe779f8
CO		 4061 return r;
4062}
4063
e0f63cb9
SY		 4064static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4065{
34f3941c
RK		 4066 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4067
4068 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4069
4070 mutex_lock(&kps->lock);
4071 memcpy(ps, &kps->channels, sizeof(*ps));
4072 mutex_unlock(&kps->lock);
2da29bcc 4073 return 0;
e0f63cb9
SY		 4074}
4075
4076static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4077{
0185604c 4078 int i;
09edea72
RK		 4079 struct kvm_pit *pit = kvm->arch.vpit;
4080
4081 mutex_lock(&pit->pit_state.lock);
34f3941c 4082 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4083 for (i = 0; i < 3; i++)
09edea72
RK		 4084 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4085 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4086 return 0;
e9f42757
BK		 4087}
4088
4089static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4090{
e9f42757
BK		 4091 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4092 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4093 sizeof(ps->channels));
4094 ps->flags = kvm->arch.vpit->pit_state.flags;
4095 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4096 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4097 return 0;
e9f42757
BK		 4098}
4099
4100static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4101{
2da29bcc 4102 int start = 0;
0185604c 4103 int i;
e9f42757 4104 u32 prev_legacy, cur_legacy;
09edea72
RK		 4105 struct kvm_pit *pit = kvm->arch.vpit;
4106
4107 mutex_lock(&pit->pit_state.lock);
4108 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4109 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4110 if (!prev_legacy && cur_legacy)
4111 start = 1;
09edea72
RK		 4112 memcpy(&pit->pit_state.channels, &ps->channels,
4113 sizeof(pit->pit_state.channels));
4114 pit->pit_state.flags = ps->flags;
0185604c 4115 for (i = 0; i < 3; i++)
09edea72 4116 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4117 start && i == 0);
09edea72 4118 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4119 return 0;
e0f63cb9
SY		 4120}
4121
52d939a0
MT		 4122static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4123 struct kvm_reinject_control *control)
4124{
71474e2f
RK		 4125 struct kvm_pit *pit = kvm->arch.vpit;
4126
4127 if (!pit)
52d939a0 4128 return -ENXIO;
b39c90b6 4129
71474e2f
RK		 4130 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4131 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4132 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4133 */
4134 mutex_lock(&pit->pit_state.lock);
4135 kvm_pit_set_reinject(pit, control->pit_reinject);
4136 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4137
52d939a0
MT		 4138 return 0;
4139}
4140
95d4c16c 4141/**
60c34612
TY		 4142 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4143 * @kvm: kvm instance
4144 * @log: slot id and address to which we copy the log
95d4c16c 4145 *
e108ff2f
PB		 4146 * Steps 1-4 below provide general overview of dirty page logging. See
4147 * kvm_get_dirty_log_protect() function description for additional details.
4148 *
4149 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4150 * always flush the TLB (step 4) even if previous step failed and the dirty
4151 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4152 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4153 * writes will be marked dirty for next log read.
95d4c16c 4154 *
60c34612
TY		 4155 * 1. Take a snapshot of the bit and clear it if needed.
4156 * 2. Write protect the corresponding page.
e108ff2f
PB		 4157 * 3. Copy the snapshot to the userspace.
4158 * 4. Flush TLB's if needed.
5bb064dc 4159 */
60c34612 4160int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4161{
60c34612 4162 bool is_dirty = false;
e108ff2f 4163 int r;
5bb064dc 4164
79fac95e 4165 mutex_lock(&kvm->slots_lock);
5bb064dc 4166
88178fd4
KH		 4167 /*
4168 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4169 */
4170 if (kvm_x86_ops->flush_log_dirty)
4171 kvm_x86_ops->flush_log_dirty(kvm);
4172
e108ff2f 4173 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4174
4175 /*
4176 * All the TLBs can be flushed out of mmu lock, see the comments in
4177 * kvm_mmu_slot_remove_write_access().
4178 */
e108ff2f 4179 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4180 if (is_dirty)
4181 kvm_flush_remote_tlbs(kvm);
4182
79fac95e 4183 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4184 return r;
4185}
4186
aa2fbe6d
YZ		 4187int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4188 bool line_status)
23d43cf9
CD		 4189{
4190 if (!irqchip_in_kernel(kvm))
4191 return -ENXIO;
4192
4193 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4194 irq_event->irq, irq_event->level,
4195 line_status);
23d43cf9
CD		 4196 return 0;
4197}
4198
90de4a18
NA		 4199static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4200 struct kvm_enable_cap *cap)
4201{
4202 int r;
4203
4204 if (cap->flags)
4205 return -EINVAL;
4206
4207 switch (cap->cap) {
4208 case KVM_CAP_DISABLE_QUIRKS:
4209 kvm->arch.disabled_quirks = cap->args[0];
4210 r = 0;
4211 break;
49df6397
SR		 4212 case KVM_CAP_SPLIT_IRQCHIP: {
4213 mutex_lock(&kvm->lock);
b053b2ae
SR		 4214 r = -EINVAL;
4215 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4216 goto split_irqchip_unlock;
49df6397
SR		 4217 r = -EEXIST;
4218 if (irqchip_in_kernel(kvm))
4219 goto split_irqchip_unlock;
557abc40 4220 if (kvm->created_vcpus)
49df6397
SR		 4221 goto split_irqchip_unlock;
4222 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4223 if (r)
49df6397
SR		 4224 goto split_irqchip_unlock;
4225 /* Pairs with irqchip_in_kernel. */
4226 smp_wmb();
49776faf 4227 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4228 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4229 r = 0;
4230split_irqchip_unlock:
4231 mutex_unlock(&kvm->lock);
4232 break;
4233 }
37131313
RK		 4234 case KVM_CAP_X2APIC_API:
4235 r = -EINVAL;
4236 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4237 break;
4238
4239 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4240 kvm->arch.x2apic_format = true;
c519265f
RK		 4241 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4242 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4243
4244 r = 0;
4245 break;
4d5422ce
WL		 4246 case KVM_CAP_X86_DISABLE_EXITS:
4247 r = -EINVAL;
4248 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4249 break;
4250
4251 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4252 kvm_can_mwait_in_guest())
4253 kvm->arch.mwait_in_guest = true;
caa057a2
WL		 4254 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HTL)
4255 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4256 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4257 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4258 r = 0;
4259 break;
90de4a18
NA		 4260 default:
4261 r = -EINVAL;
4262 break;
4263 }
4264 return r;
4265}
4266
1fe779f8
CO		 4267long kvm_arch_vm_ioctl(struct file *filp,
4268 unsigned int ioctl, unsigned long arg)
4269{
4270 struct kvm *kvm = filp->private_data;
4271 void __user *argp = (void __user *)arg;
367e1319 4272 int r = -ENOTTY;
f0d66275
DH		 4273 /*
4274 * This union makes it completely explicit to gcc-3.x
4275 * that these two variables' stack usage should be
4276 * combined, not added together.
4277 */
4278 union {
4279 struct kvm_pit_state ps;
e9f42757 4280 struct kvm_pit_state2 ps2;
c5ff41ce 4281 struct kvm_pit_config pit_config;
f0d66275 4282 } u;
1fe779f8
CO		 4283
4284 switch (ioctl) {
4285 case KVM_SET_TSS_ADDR:
4286 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4287 break;
b927a3ce
SY		 4288 case KVM_SET_IDENTITY_MAP_ADDR: {
4289 u64 ident_addr;
4290
1af1ac91
DH		 4291 mutex_lock(&kvm->lock);
4292 r = -EINVAL;
4293 if (kvm->created_vcpus)
4294 goto set_identity_unlock;
b927a3ce
SY		 4295 r = -EFAULT;
4296 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4297 goto set_identity_unlock;
b927a3ce 4298 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4299set_identity_unlock:
4300 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4301 break;
4302 }
1fe779f8
CO		 4303 case KVM_SET_NR_MMU_PAGES:
4304 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4305 break;
4306 case KVM_GET_NR_MMU_PAGES:
4307 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4308 break;
3ddea128 4309 case KVM_CREATE_IRQCHIP: {
3ddea128 4310 mutex_lock(&kvm->lock);
09941366 4311
3ddea128 4312 r = -EEXIST;
35e6eaa3 4313 if (irqchip_in_kernel(kvm))
3ddea128 4314 goto create_irqchip_unlock;
09941366 4315
3e515705 4316 r = -EINVAL;
557abc40 4317 if (kvm->created_vcpus)
3e515705 4318 goto create_irqchip_unlock;
09941366
RK		 4319
4320 r = kvm_pic_init(kvm);
4321 if (r)
3ddea128 4322 goto create_irqchip_unlock;
09941366
RK		 4323
4324 r = kvm_ioapic_init(kvm);
4325 if (r) {
09941366 4326 kvm_pic_destroy(kvm);
3ddea128 4327 goto create_irqchip_unlock;
09941366
RK		 4328 }
4329
399ec807
AK		 4330 r = kvm_setup_default_irq_routing(kvm);
4331 if (r) {
72bb2fcd 4332 kvm_ioapic_destroy(kvm);
09941366 4333 kvm_pic_destroy(kvm);
71ba994c 4334 goto create_irqchip_unlock;
399ec807 4335 }
49776faf 4336 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4337 smp_wmb();
49776faf 4338 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4339 create_irqchip_unlock:
4340 mutex_unlock(&kvm->lock);
1fe779f8 4341 break;
3ddea128 4342 }
7837699f 4343 case KVM_CREATE_PIT:
c5ff41ce
JK		 4344 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4345 goto create_pit;
4346 case KVM_CREATE_PIT2:
4347 r = -EFAULT;
4348 if (copy_from_user(&u.pit_config, argp,
4349 sizeof(struct kvm_pit_config)))
4350 goto out;
4351 create_pit:
250715a6 4352 mutex_lock(&kvm->lock);
269e05e4
AK		 4353 r = -EEXIST;
4354 if (kvm->arch.vpit)
4355 goto create_pit_unlock;
7837699f 4356 r = -ENOMEM;
c5ff41ce 4357 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4358 if (kvm->arch.vpit)
4359 r = 0;
269e05e4 4360 create_pit_unlock:
250715a6 4361 mutex_unlock(&kvm->lock);
7837699f 4362 break;
1fe779f8
CO		 4363 case KVM_GET_IRQCHIP: {
4364 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4365 struct kvm_irqchip *chip;
1fe779f8 4366
ff5c2c03
SL		 4367 chip = memdup_user(argp, sizeof(*chip));
4368 if (IS_ERR(chip)) {
4369 r = PTR_ERR(chip);
1fe779f8 4370 goto out;
ff5c2c03
SL		 4371 }
4372
1fe779f8 4373 r = -ENXIO;
826da321 4374 if (!irqchip_kernel(kvm))
f0d66275
DH		 4375 goto get_irqchip_out;
4376 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4377 if (r)
f0d66275 4378 goto get_irqchip_out;
1fe779f8 4379 r = -EFAULT;
f0d66275
DH		 4380 if (copy_to_user(argp, chip, sizeof *chip))
4381 goto get_irqchip_out;
1fe779f8 4382 r = 0;
f0d66275
DH		 4383 get_irqchip_out:
4384 kfree(chip);
1fe779f8
CO		 4385 break;
4386 }
4387 case KVM_SET_IRQCHIP: {
4388 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4389 struct kvm_irqchip *chip;
1fe779f8 4390
ff5c2c03
SL		 4391 chip = memdup_user(argp, sizeof(*chip));
4392 if (IS_ERR(chip)) {
4393 r = PTR_ERR(chip);
1fe779f8 4394 goto out;
ff5c2c03
SL		 4395 }
4396
1fe779f8 4397 r = -ENXIO;
826da321 4398 if (!irqchip_kernel(kvm))
f0d66275
DH		 4399 goto set_irqchip_out;
4400 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4401 if (r)
f0d66275 4402 goto set_irqchip_out;
1fe779f8 4403 r = 0;
f0d66275
DH		 4404 set_irqchip_out:
4405 kfree(chip);
1fe779f8
CO		 4406 break;
4407 }
e0f63cb9 4408 case KVM_GET_PIT: {
e0f63cb9 4409 r = -EFAULT;
f0d66275 4410 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4411 goto out;
4412 r = -ENXIO;
4413 if (!kvm->arch.vpit)
4414 goto out;
f0d66275 4415 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4416 if (r)
4417 goto out;
4418 r = -EFAULT;
f0d66275 4419 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4420 goto out;
4421 r = 0;
4422 break;
4423 }
4424 case KVM_SET_PIT: {
e0f63cb9 4425 r = -EFAULT;
f0d66275 4426 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4427 goto out;
4428 r = -ENXIO;
4429 if (!kvm->arch.vpit)
4430 goto out;
f0d66275 4431 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4432 break;
4433 }
e9f42757
BK		 4434 case KVM_GET_PIT2: {
4435 r = -ENXIO;
4436 if (!kvm->arch.vpit)
4437 goto out;
4438 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4439 if (r)
4440 goto out;
4441 r = -EFAULT;
4442 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4443 goto out;
4444 r = 0;
4445 break;
4446 }
4447 case KVM_SET_PIT2: {
4448 r = -EFAULT;
4449 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4450 goto out;
4451 r = -ENXIO;
4452 if (!kvm->arch.vpit)
4453 goto out;
4454 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4455 break;
4456 }
52d939a0
MT		 4457 case KVM_REINJECT_CONTROL: {
4458 struct kvm_reinject_control control;
4459 r = -EFAULT;
4460 if (copy_from_user(&control, argp, sizeof(control)))
4461 goto out;
4462 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4463 break;
4464 }
d71ba788
PB		 4465 case KVM_SET_BOOT_CPU_ID:
4466 r = 0;
4467 mutex_lock(&kvm->lock);
557abc40 4468 if (kvm->created_vcpus)
d71ba788
PB		 4469 r = -EBUSY;
4470 else
4471 kvm->arch.bsp_vcpu_id = arg;
4472 mutex_unlock(&kvm->lock);
4473 break;
ffde22ac 4474 case KVM_XEN_HVM_CONFIG: {
51776043 4475 struct kvm_xen_hvm_config xhc;
ffde22ac 4476 r = -EFAULT;
51776043 4477 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4478 goto out;
4479 r = -EINVAL;
51776043 4480 if (xhc.flags)
ffde22ac 4481 goto out;
51776043 4482 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4483 r = 0;
4484 break;
4485 }
afbcf7ab 4486 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4487 struct kvm_clock_data user_ns;
4488 u64 now_ns;
afbcf7ab
GC		 4489
4490 r = -EFAULT;
4491 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4492 goto out;
4493
4494 r = -EINVAL;
4495 if (user_ns.flags)
4496 goto out;
4497
4498 r = 0;
0bc48bea
RK		 4499 /*
4500 * TODO: userspace has to take care of races with VCPU_RUN, so
4501 * kvm_gen_update_masterclock() can be cut down to locked
4502 * pvclock_update_vm_gtod_copy().
4503 */
4504 kvm_gen_update_masterclock(kvm);
e891a32e 4505 now_ns = get_kvmclock_ns(kvm);
108b249c 4506 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4507 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4508 break;
4509 }
4510 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4511 struct kvm_clock_data user_ns;
4512 u64 now_ns;
4513
e891a32e 4514 now_ns = get_kvmclock_ns(kvm);
108b249c 4515 user_ns.clock = now_ns;
e3fd9a93 4516 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4517 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4518
4519 r = -EFAULT;
4520 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4521 goto out;
4522 r = 0;
4523 break;
4524 }
90de4a18
NA		 4525 case KVM_ENABLE_CAP: {
4526 struct kvm_enable_cap cap;
afbcf7ab 4527
90de4a18
NA		 4528 r = -EFAULT;
4529 if (copy_from_user(&cap, argp, sizeof(cap)))
4530 goto out;
4531 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4532 break;
4533 }
5acc5c06
BS		 4534 case KVM_MEMORY_ENCRYPT_OP: {
4535 r = -ENOTTY;
4536 if (kvm_x86_ops->mem_enc_op)
4537 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4538 break;
4539 }
69eaedee
BS		 4540 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4541 struct kvm_enc_region region;
4542
4543 r = -EFAULT;
4544 if (copy_from_user(&region, argp, sizeof(region)))
4545 goto out;
4546
4547 r = -ENOTTY;
4548 if (kvm_x86_ops->mem_enc_reg_region)
4549 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4550 break;
4551 }
4552 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4553 struct kvm_enc_region region;
4554
4555 r = -EFAULT;
4556 if (copy_from_user(&region, argp, sizeof(region)))
4557 goto out;
4558
4559 r = -ENOTTY;
4560 if (kvm_x86_ops->mem_enc_unreg_region)
4561 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4562 break;
4563 }
faeb7833
RK		 4564 case KVM_HYPERV_EVENTFD: {
4565 struct kvm_hyperv_eventfd hvevfd;
4566
4567 r = -EFAULT;
4568 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4569 goto out;
4570 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4571 break;
4572 }
1fe779f8 4573 default:
ad6260da 4574 r = -ENOTTY;
1fe779f8
CO		 4575 }
4576out:
4577 return r;
4578}
4579
a16b043c 4580static void kvm_init_msr_list(void)
043405e1
CO		 4581{
4582 u32 dummy[2];
4583 unsigned i, j;
4584
62ef68bb 4585 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4586 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4587 continue;
93c4adc7
PB		 4588
4589 /*
4590 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4591 * to the guests in some cases.
93c4adc7
PB		 4592 */
4593 switch (msrs_to_save[i]) {
4594 case MSR_IA32_BNDCFGS:
4595 if (!kvm_x86_ops->mpx_supported())
4596 continue;
4597 break;
9dbe6cf9
PB		 4598 case MSR_TSC_AUX:
4599 if (!kvm_x86_ops->rdtscp_supported())
4600 continue;
4601 break;
93c4adc7
PB		 4602 default:
4603 break;
4604 }
4605
043405e1
CO		 4606 if (j < i)
4607 msrs_to_save[j] = msrs_to_save[i];
4608 j++;
4609 }
4610 num_msrs_to_save = j;
62ef68bb
PB		 4611
4612 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4613 switch (emulated_msrs[i]) {
6d396b55
PB		 4614 case MSR_IA32_SMBASE:
4615 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4616 continue;
4617 break;
62ef68bb
PB		 4618 default:
4619 break;
4620 }
4621
4622 if (j < i)
4623 emulated_msrs[j] = emulated_msrs[i];
4624 j++;
4625 }
4626 num_emulated_msrs = j;
801e459a
TL		 4627
4628 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4629 struct kvm_msr_entry msr;
4630
4631 msr.index = msr_based_features[i];
66421c1e 4632 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4633 continue;
4634
4635 if (j < i)
4636 msr_based_features[j] = msr_based_features[i];
4637 j++;
4638 }
4639 num_msr_based_features = j;
043405e1
CO		 4640}
4641
bda9020e
MT		 4642static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4643 const void *v)
bbd9b64e 4644{
70252a10
AK		 4645 int handled = 0;
4646 int n;
4647
4648 do {
4649 n = min(len, 8);
bce87cce 4650 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4651 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4652 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4653 break;
4654 handled += n;
4655 addr += n;
4656 len -= n;
4657 v += n;
4658 } while (len);
bbd9b64e 4659
70252a10 4660 return handled;
bbd9b64e
CO		 4661}
4662
bda9020e 4663static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4664{
70252a10
AK		 4665 int handled = 0;
4666 int n;
4667
4668 do {
4669 n = min(len, 8);
bce87cce 4670 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4671 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4672 addr, n, v))
4673 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4674 break;
e39d200f 4675 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4676 handled += n;
4677 addr += n;
4678 len -= n;
4679 v += n;
4680 } while (len);
bbd9b64e 4681
70252a10 4682 return handled;
bbd9b64e
CO		 4683}
4684
2dafc6c2
GN		 4685static void kvm_set_segment(struct kvm_vcpu *vcpu,
4686 struct kvm_segment *var, int seg)
4687{
4688 kvm_x86_ops->set_segment(vcpu, var, seg);
4689}
4690
4691void kvm_get_segment(struct kvm_vcpu *vcpu,
4692 struct kvm_segment *var, int seg)
4693{
4694 kvm_x86_ops->get_segment(vcpu, var, seg);
4695}
4696
54987b7a
PB		 4697gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4698 struct x86_exception *exception)
02f59dc9
JR		 4699{
4700 gpa_t t_gpa;
02f59dc9
JR		 4701
4702 BUG_ON(!mmu_is_nested(vcpu));
4703
4704 /* NPT walks are always user-walks */
4705 access |= PFERR_USER_MASK;
54987b7a 4706 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4707
4708 return t_gpa;
4709}
4710
ab9ae313
AK		 4711gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4712 struct x86_exception *exception)
1871c602
GN		 4713{
4714 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4715 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4716}
4717
ab9ae313
AK		 4718 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4719 struct x86_exception *exception)
1871c602
GN		 4720{
4721 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4722 access |= PFERR_FETCH_MASK;
ab9ae313 4723 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4724}
4725
ab9ae313
AK		 4726gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4727 struct x86_exception *exception)
1871c602
GN		 4728{
4729 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4730 access |= PFERR_WRITE_MASK;
ab9ae313 4731 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4732}
4733
4734/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4735gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4736 struct x86_exception *exception)
1871c602 4737{
ab9ae313 4738 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4739}
4740
4741static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4742 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4743 struct x86_exception *exception)
bbd9b64e
CO		 4744{
4745 void *data = val;
10589a46 4746 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4747
4748 while (bytes) {
14dfe855 4749 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4750 exception);
bbd9b64e 4751 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4752 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4753 int ret;
4754
bcc55cba 4755 if (gpa == UNMAPPED_GVA)
ab9ae313 4756 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4757 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4758 offset, toread);
10589a46 4759 if (ret < 0) {
c3cd7ffa 4760 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4761 goto out;
4762 }
bbd9b64e 4763
77c2002e
IE		 4764 bytes -= toread;
4765 data += toread;
4766 addr += toread;
bbd9b64e 4767 }
10589a46 4768out:
10589a46 4769 return r;
bbd9b64e 4770}
77c2002e 4771
1871c602 4772/* used for instruction fetching */
0f65dd70
AK		 4773static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4774 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4775 struct x86_exception *exception)
1871c602 4776{
0f65dd70 4777 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4778 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4779 unsigned offset;
4780 int ret;
0f65dd70 4781
44583cba
PB		 4782 /* Inline kvm_read_guest_virt_helper for speed. */
4783 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4784 exception);
4785 if (unlikely(gpa == UNMAPPED_GVA))
4786 return X86EMUL_PROPAGATE_FAULT;
4787
4788 offset = addr & (PAGE_SIZE-1);
4789 if (WARN_ON(offset + bytes > PAGE_SIZE))
4790 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4791 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4792 offset, bytes);
44583cba
PB		 4793 if (unlikely(ret < 0))
4794 return X86EMUL_IO_NEEDED;
4795
4796 return X86EMUL_CONTINUE;
1871c602
GN		 4797}
4798
064aea77 4799int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4800 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4801 struct x86_exception *exception)
1871c602 4802{
0f65dd70 4803 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4804 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4805
1871c602 4806 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4807 exception);
1871c602 4808}
064aea77 4809EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4810
0f65dd70
AK		 4811static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4812 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4813 struct x86_exception *exception)
1871c602 4814{
0f65dd70 4815 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4816 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4817}
4818
7a036a6f
RK		 4819static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4820 unsigned long addr, void *val, unsigned int bytes)
4821{
4822 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4823 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4824
4825 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4826}
4827
6a4d7550 4828int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4829 gva_t addr, void *val,
2dafc6c2 4830 unsigned int bytes,
bcc55cba 4831 struct x86_exception *exception)
77c2002e 4832{
0f65dd70 4833 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4834 void *data = val;
4835 int r = X86EMUL_CONTINUE;
4836
4837 while (bytes) {
14dfe855
JR		 4838 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4839 PFERR_WRITE_MASK,
ab9ae313 4840 exception);
77c2002e
IE		 4841 unsigned offset = addr & (PAGE_SIZE-1);
4842 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4843 int ret;
4844
bcc55cba 4845 if (gpa == UNMAPPED_GVA)
ab9ae313 4846 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4847 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4848 if (ret < 0) {
c3cd7ffa 4849 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4850 goto out;
4851 }
4852
4853 bytes -= towrite;
4854 data += towrite;
4855 addr += towrite;
4856 }
4857out:
4858 return r;
4859}
6a4d7550 4860EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4861
082d06ed
WL		 4862int handle_ud(struct kvm_vcpu *vcpu)
4863{
6c86eedc 4864 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 4865 enum emulation_result er;
6c86eedc
WL		 4866 char sig[5]; /* ud2; .ascii "kvm" */
4867 struct x86_exception e;
4868
4869 if (force_emulation_prefix &&
4870 kvm_read_guest_virt(&vcpu->arch.emulate_ctxt,
4871 kvm_get_linear_rip(vcpu), sig, sizeof(sig), &e) == 0 &&
4872 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
4873 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
4874 emul_type = 0;
4875 }
082d06ed 4876
6c86eedc 4877 er = emulate_instruction(vcpu, emul_type);
082d06ed
WL		 4878 if (er == EMULATE_USER_EXIT)
4879 return 0;
4880 if (er != EMULATE_DONE)
4881 kvm_queue_exception(vcpu, UD_VECTOR);
4882 return 1;
4883}
4884EXPORT_SYMBOL_GPL(handle_ud);
4885
0f89b207
TL		 4886static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4887 gpa_t gpa, bool write)
4888{
4889 /* For APIC access vmexit */
4890 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4891 return 1;
4892
4893 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4894 trace_vcpu_match_mmio(gva, gpa, write, true);
4895 return 1;
4896 }
4897
4898 return 0;
4899}
4900
af7cc7d1
XG		 4901static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4902 gpa_t *gpa, struct x86_exception *exception,
4903 bool write)
4904{
97d64b78
AK		 4905 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4906 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4907
be94f6b7
HH		 4908 /*
4909 * currently PKRU is only applied to ept enabled guest so
4910 * there is no pkey in EPT page table for L1 guest or EPT
4911 * shadow page table for L2 guest.
4912 */
97d64b78 4913 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4914 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4915 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4916 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4917 (gva & (PAGE_SIZE - 1));
4f022648 4918 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4919 return 1;
4920 }
4921
af7cc7d1
XG		 4922 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4923
4924 if (*gpa == UNMAPPED_GVA)
4925 return -1;
4926
0f89b207 4927 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4928}
4929
3200f405 4930int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4931 const void *val, int bytes)
bbd9b64e
CO		 4932{
4933 int ret;
4934
54bf36aa 4935 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4936 if (ret < 0)
bbd9b64e 4937 return 0;
0eb05bf2 4938 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4939 return 1;
4940}
4941
77d197b2
XG		 4942struct read_write_emulator_ops {
4943 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4944 int bytes);
4945 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4946 void *val, int bytes);
4947 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4948 int bytes, void *val);
4949 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4950 void *val, int bytes);
4951 bool write;
4952};
4953
4954static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4955{
4956 if (vcpu->mmio_read_completed) {
77d197b2 4957 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4958 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4959 vcpu->mmio_read_completed = 0;
4960 return 1;
4961 }
4962
4963 return 0;
4964}
4965
4966static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4967 void *val, int bytes)
4968{
54bf36aa 4969 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4970}
4971
4972static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4973 void *val, int bytes)
4974{
4975 return emulator_write_phys(vcpu, gpa, val, bytes);
4976}
4977
4978static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4979{
e39d200f 4980 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4981 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4982}
4983
4984static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4985 void *val, int bytes)
4986{
e39d200f 4987 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4988 return X86EMUL_IO_NEEDED;
4989}
4990
4991static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4992 void *val, int bytes)
4993{
f78146b0
AK		 4994 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4995
87da7e66 4996 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4997 return X86EMUL_CONTINUE;
4998}
4999
0fbe9b0b 5000static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5001 .read_write_prepare = read_prepare,
5002 .read_write_emulate = read_emulate,
5003 .read_write_mmio = vcpu_mmio_read,
5004 .read_write_exit_mmio = read_exit_mmio,
5005};
5006
0fbe9b0b 5007static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5008 .read_write_emulate = write_emulate,
5009 .read_write_mmio = write_mmio,
5010 .read_write_exit_mmio = write_exit_mmio,
5011 .write = true,
5012};
5013
22388a3c
XG		 5014static int emulator_read_write_onepage(unsigned long addr, void *val,
5015 unsigned int bytes,
5016 struct x86_exception *exception,
5017 struct kvm_vcpu *vcpu,
0fbe9b0b 5018 const struct read_write_emulator_ops *ops)
bbd9b64e 5019{
af7cc7d1
XG		 5020 gpa_t gpa;
5021 int handled, ret;
22388a3c 5022 bool write = ops->write;
f78146b0 5023 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5024 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5025
5026 /*
5027 * If the exit was due to a NPF we may already have a GPA.
5028 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5029 * Note, this cannot be used on string operations since string
5030 * operation using rep will only have the initial GPA from the NPF
5031 * occurred.
5032 */
5033 if (vcpu->arch.gpa_available &&
5034 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5035 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5036 gpa = vcpu->arch.gpa_val;
5037 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5038 } else {
5039 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5040 if (ret < 0)
5041 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5042 }
10589a46 5043
618232e2 5044 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5045 return X86EMUL_CONTINUE;
5046
bbd9b64e
CO		 5047 /*
5048 * Is this MMIO handled locally?
5049 */
22388a3c 5050 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5051 if (handled == bytes)
bbd9b64e 5052 return X86EMUL_CONTINUE;
bbd9b64e 5053
70252a10
AK		 5054 gpa += handled;
5055 bytes -= handled;
5056 val += handled;
5057
87da7e66
XG		 5058 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5059 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5060 frag->gpa = gpa;
5061 frag->data = val;
5062 frag->len = bytes;
f78146b0 5063 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5064}
5065
52eb5a6d
XL		 5066static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5067 unsigned long addr,
22388a3c
XG		 5068 void *val, unsigned int bytes,
5069 struct x86_exception *exception,
0fbe9b0b 5070 const struct read_write_emulator_ops *ops)
bbd9b64e 5071{
0f65dd70 5072 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5073 gpa_t gpa;
5074 int rc;
5075
5076 if (ops->read_write_prepare &&
5077 ops->read_write_prepare(vcpu, val, bytes))
5078 return X86EMUL_CONTINUE;
5079
5080 vcpu->mmio_nr_fragments = 0;
0f65dd70 5081
bbd9b64e
CO		 5082 /* Crossing a page boundary? */
5083 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5084 int now;
bbd9b64e
CO		 5085
5086 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5087 rc = emulator_read_write_onepage(addr, val, now, exception,
5088 vcpu, ops);
5089
bbd9b64e
CO		 5090 if (rc != X86EMUL_CONTINUE)
5091 return rc;
5092 addr += now;
bac15531
NA		 5093 if (ctxt->mode != X86EMUL_MODE_PROT64)
5094 addr = (u32)addr;
bbd9b64e
CO		 5095 val += now;
5096 bytes -= now;
5097 }
22388a3c 5098
f78146b0
AK		 5099 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5100 vcpu, ops);
5101 if (rc != X86EMUL_CONTINUE)
5102 return rc;
5103
5104 if (!vcpu->mmio_nr_fragments)
5105 return rc;
5106
5107 gpa = vcpu->mmio_fragments[0].gpa;
5108
5109 vcpu->mmio_needed = 1;
5110 vcpu->mmio_cur_fragment = 0;
5111
87da7e66 5112 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5113 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5114 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5115 vcpu->run->mmio.phys_addr = gpa;
5116
5117 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5118}
5119
5120static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5121 unsigned long addr,
5122 void *val,
5123 unsigned int bytes,
5124 struct x86_exception *exception)
5125{
5126 return emulator_read_write(ctxt, addr, val, bytes,
5127 exception, &read_emultor);
5128}
5129
52eb5a6d 5130static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5131 unsigned long addr,
5132 const void *val,
5133 unsigned int bytes,
5134 struct x86_exception *exception)
5135{
5136 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5137 exception, &write_emultor);
bbd9b64e 5138}
bbd9b64e 5139
daea3e73
AK		 5140#define CMPXCHG_TYPE(t, ptr, old, new) \
5141 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5142
5143#ifdef CONFIG_X86_64
5144# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5145#else
5146# define CMPXCHG64(ptr, old, new) \
9749a6c0 5147 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5148#endif
5149
0f65dd70
AK		 5150static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5151 unsigned long addr,
bbd9b64e
CO		 5152 const void *old,
5153 const void *new,
5154 unsigned int bytes,
0f65dd70 5155 struct x86_exception *exception)
bbd9b64e 5156{
0f65dd70 5157 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5158 gpa_t gpa;
5159 struct page *page;
5160 char *kaddr;
5161 bool exchanged;
2bacc55c 5162
daea3e73
AK		 5163 /* guests cmpxchg8b have to be emulated atomically */
5164 if (bytes > 8 || (bytes & (bytes - 1)))
5165 goto emul_write;
10589a46 5166
daea3e73 5167 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5168
daea3e73
AK		 5169 if (gpa == UNMAPPED_GVA ||
5170 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5171 goto emul_write;
2bacc55c 5172
daea3e73
AK		 5173 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5174 goto emul_write;
72dc67a6 5175
54bf36aa 5176 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5177 if (is_error_page(page))
c19b8bd6 5178 goto emul_write;
72dc67a6 5179
8fd75e12 5180 kaddr = kmap_atomic(page);
daea3e73
AK		 5181 kaddr += offset_in_page(gpa);
5182 switch (bytes) {
5183 case 1:
5184 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5185 break;
5186 case 2:
5187 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5188 break;
5189 case 4:
5190 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5191 break;
5192 case 8:
5193 exchanged = CMPXCHG64(kaddr, old, new);
5194 break;
5195 default:
5196 BUG();
2bacc55c 5197 }
8fd75e12 5198 kunmap_atomic(kaddr);
daea3e73
AK		 5199 kvm_release_page_dirty(page);
5200
5201 if (!exchanged)
5202 return X86EMUL_CMPXCHG_FAILED;
5203
54bf36aa 5204 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5205 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5206
5207 return X86EMUL_CONTINUE;
4a5f48f6 5208
3200f405 5209emul_write:
daea3e73 5210 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5211
0f65dd70 5212 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5213}
5214
cf8f70bf
GN		 5215static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5216{
cbfc6c91 5217 int r = 0, i;
cf8f70bf 5218
cbfc6c91
WL		 5219 for (i = 0; i < vcpu->arch.pio.count; i++) {
5220 if (vcpu->arch.pio.in)
5221 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5222 vcpu->arch.pio.size, pd);
5223 else
5224 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5225 vcpu->arch.pio.port, vcpu->arch.pio.size,
5226 pd);
5227 if (r)
5228 break;
5229 pd += vcpu->arch.pio.size;
5230 }
cf8f70bf
GN		 5231 return r;
5232}
5233
6f6fbe98
XG		 5234static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5235 unsigned short port, void *val,
5236 unsigned int count, bool in)
cf8f70bf 5237{
cf8f70bf 5238 vcpu->arch.pio.port = port;
6f6fbe98 5239 vcpu->arch.pio.in = in;
7972995b 5240 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5241 vcpu->arch.pio.size = size;
5242
5243 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5244 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5245 return 1;
5246 }
5247
5248 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5249 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5250 vcpu->run->io.size = size;
5251 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5252 vcpu->run->io.count = count;
5253 vcpu->run->io.port = port;
5254
5255 return 0;
5256}
5257
6f6fbe98
XG		 5258static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5259 int size, unsigned short port, void *val,
5260 unsigned int count)
cf8f70bf 5261{
ca1d4a9e 5262 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5263 int ret;
ca1d4a9e 5264
6f6fbe98
XG		 5265 if (vcpu->arch.pio.count)
5266 goto data_avail;
cf8f70bf 5267
cbfc6c91
WL		 5268 memset(vcpu->arch.pio_data, 0, size * count);
5269
6f6fbe98
XG		 5270 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5271 if (ret) {
5272data_avail:
5273 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5274 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5275 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5276 return 1;
5277 }
5278
cf8f70bf
GN		 5279 return 0;
5280}
5281
6f6fbe98
XG		 5282static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5283 int size, unsigned short port,
5284 const void *val, unsigned int count)
5285{
5286 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5287
5288 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5289 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5290 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5291}
5292
bbd9b64e
CO		 5293static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5294{
5295 return kvm_x86_ops->get_segment_base(vcpu, seg);
5296}
5297
3cb16fe7 5298static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5299{
3cb16fe7 5300 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5301}
5302
ae6a2375 5303static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5304{
5305 if (!need_emulate_wbinvd(vcpu))
5306 return X86EMUL_CONTINUE;
5307
5308 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5309 int cpu = get_cpu();
5310
5311 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5312 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5313 wbinvd_ipi, NULL, 1);
2eec7343 5314 put_cpu();
f5f48ee1 5315 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5316 } else
5317 wbinvd();
f5f48ee1
SY		 5318 return X86EMUL_CONTINUE;
5319}
5cb56059
JS		 5320
5321int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5322{
6affcbed
KH		 5323 kvm_emulate_wbinvd_noskip(vcpu);
5324 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5325}
f5f48ee1
SY		 5326EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5327
5cb56059
JS		 5328
5329
bcaf5cc5
AK		 5330static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5331{
5cb56059 5332 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5333}
5334
52eb5a6d
XL		 5335static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5336 unsigned long *dest)
bbd9b64e 5337{
16f8a6f9 5338 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5339}
5340
52eb5a6d
XL		 5341static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5342 unsigned long value)
bbd9b64e 5343{
338dbc97 5344
717746e3 5345 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5346}
5347
52a46617 5348static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5349{
52a46617 5350 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5351}
5352
717746e3 5353static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5354{
717746e3 5355 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5356 unsigned long value;
5357
5358 switch (cr) {
5359 case 0:
5360 value = kvm_read_cr0(vcpu);
5361 break;
5362 case 2:
5363 value = vcpu->arch.cr2;
5364 break;
5365 case 3:
9f8fe504 5366 value = kvm_read_cr3(vcpu);
52a46617
GN		 5367 break;
5368 case 4:
5369 value = kvm_read_cr4(vcpu);
5370 break;
5371 case 8:
5372 value = kvm_get_cr8(vcpu);
5373 break;
5374 default:
a737f256 5375 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5376 return 0;
5377 }
5378
5379 return value;
5380}
5381
717746e3 5382static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5383{
717746e3 5384 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5385 int res = 0;
5386
52a46617
GN		 5387 switch (cr) {
5388 case 0:
49a9b07e 5389 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5390 break;
5391 case 2:
5392 vcpu->arch.cr2 = val;
5393 break;
5394 case 3:
2390218b 5395 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5396 break;
5397 case 4:
a83b29c6 5398 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5399 break;
5400 case 8:
eea1cff9 5401 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5402 break;
5403 default:
a737f256 5404 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5405 res = -1;
52a46617 5406 }
0f12244f
GN		 5407
5408 return res;
52a46617
GN		 5409}
5410
717746e3 5411static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5412{
717746e3 5413 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5414}
5415
4bff1e86 5416static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5417{
4bff1e86 5418 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5419}
5420
4bff1e86 5421static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5422{
4bff1e86 5423 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5424}
5425
1ac9d0cf
AK		 5426static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5427{
5428 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5429}
5430
5431static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5432{
5433 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5434}
5435
4bff1e86
AK		 5436static unsigned long emulator_get_cached_segment_base(
5437 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5438{
4bff1e86 5439 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5440}
5441
1aa36616
AK		 5442static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5443 struct desc_struct *desc, u32 *base3,
5444 int seg)
2dafc6c2
GN		 5445{
5446 struct kvm_segment var;
5447
4bff1e86 5448 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5449 *selector = var.selector;
2dafc6c2 5450
378a8b09
GN		 5451 if (var.unusable) {
5452 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5453 if (base3)
5454 *base3 = 0;
2dafc6c2 5455 return false;
378a8b09 5456 }
2dafc6c2
GN		 5457
5458 if (var.g)
5459 var.limit >>= 12;
5460 set_desc_limit(desc, var.limit);
5461 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5462#ifdef CONFIG_X86_64
5463 if (base3)
5464 *base3 = var.base >> 32;
5465#endif
2dafc6c2
GN		 5466 desc->type = var.type;
5467 desc->s = var.s;
5468 desc->dpl = var.dpl;
5469 desc->p = var.present;
5470 desc->avl = var.avl;
5471 desc->l = var.l;
5472 desc->d = var.db;
5473 desc->g = var.g;
5474
5475 return true;
5476}
5477
1aa36616
AK		 5478static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5479 struct desc_struct *desc, u32 base3,
5480 int seg)
2dafc6c2 5481{
4bff1e86 5482 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5483 struct kvm_segment var;
5484
1aa36616 5485 var.selector = selector;
2dafc6c2 5486 var.base = get_desc_base(desc);
5601d05b
GN		 5487#ifdef CONFIG_X86_64
5488 var.base |= ((u64)base3) << 32;
5489#endif
2dafc6c2
GN		 5490 var.limit = get_desc_limit(desc);
5491 if (desc->g)
5492 var.limit = (var.limit << 12) | 0xfff;
5493 var.type = desc->type;
2dafc6c2
GN		 5494 var.dpl = desc->dpl;
5495 var.db = desc->d;
5496 var.s = desc->s;
5497 var.l = desc->l;
5498 var.g = desc->g;
5499 var.avl = desc->avl;
5500 var.present = desc->p;
5501 var.unusable = !var.present;
5502 var.padding = 0;
5503
5504 kvm_set_segment(vcpu, &var, seg);
5505 return;
5506}
5507
717746e3
AK		 5508static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5509 u32 msr_index, u64 *pdata)
5510{
609e36d3
PB		 5511 struct msr_data msr;
5512 int r;
5513
5514 msr.index = msr_index;
5515 msr.host_initiated = false;
5516 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5517 if (r)
5518 return r;
5519
5520 *pdata = msr.data;
5521 return 0;
717746e3
AK		 5522}
5523
5524static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5525 u32 msr_index, u64 data)
5526{
8fe8ab46
WA		 5527 struct msr_data msr;
5528
5529 msr.data = data;
5530 msr.index = msr_index;
5531 msr.host_initiated = false;
5532 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5533}
5534
64d60670
PB		 5535static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5536{
5537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5538
5539 return vcpu->arch.smbase;
5540}
5541
5542static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5543{
5544 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5545
5546 vcpu->arch.smbase = smbase;
5547}
5548
67f4d428
NA		 5549static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5550 u32 pmc)
5551{
c6702c9d 5552 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5553}
5554
222d21aa
AK		 5555static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5556 u32 pmc, u64 *pdata)
5557{
c6702c9d 5558 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5559}
5560
6c3287f7
AK		 5561static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5562{
5563 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5564}
5565
2953538e 5566static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5567 struct x86_instruction_info *info,
c4f035c6
AK		 5568 enum x86_intercept_stage stage)
5569{
2953538e 5570 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5571}
5572
e911eb3b
YZ		 5573static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5574 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5575{
e911eb3b 5576 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5577}
5578
dd856efa
AK		 5579static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5580{
5581 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5582}
5583
5584static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5585{
5586 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5587}
5588
801806d9
NA		 5589static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5590{
5591 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5592}
5593
6ed071f0
LP		 5594static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5595{
5596 return emul_to_vcpu(ctxt)->arch.hflags;
5597}
5598
5599static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5600{
5601 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5602}
5603
0234bf88
LP		 5604static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5605{
5606 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5607}
5608
0225fb50 5609static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5610 .read_gpr = emulator_read_gpr,
5611 .write_gpr = emulator_write_gpr,
1871c602 5612 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5613 .write_std = kvm_write_guest_virt_system,
7a036a6f 5614 .read_phys = kvm_read_guest_phys_system,
1871c602 5615 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5616 .read_emulated = emulator_read_emulated,
5617 .write_emulated = emulator_write_emulated,
5618 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5619 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5620 .pio_in_emulated = emulator_pio_in_emulated,
5621 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5622 .get_segment = emulator_get_segment,
5623 .set_segment = emulator_set_segment,
5951c442 5624 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5625 .get_gdt = emulator_get_gdt,
160ce1f1 5626 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5627 .set_gdt = emulator_set_gdt,
5628 .set_idt = emulator_set_idt,
52a46617
GN		 5629 .get_cr = emulator_get_cr,
5630 .set_cr = emulator_set_cr,
9c537244 5631 .cpl = emulator_get_cpl,
35aa5375
GN		 5632 .get_dr = emulator_get_dr,
5633 .set_dr = emulator_set_dr,
64d60670
PB		 5634 .get_smbase = emulator_get_smbase,
5635 .set_smbase = emulator_set_smbase,
717746e3
AK		 5636 .set_msr = emulator_set_msr,
5637 .get_msr = emulator_get_msr,
67f4d428 5638 .check_pmc = emulator_check_pmc,
222d21aa 5639 .read_pmc = emulator_read_pmc,
6c3287f7 5640 .halt = emulator_halt,
bcaf5cc5 5641 .wbinvd = emulator_wbinvd,
d6aa1000 5642 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5643 .intercept = emulator_intercept,
bdb42f5a 5644 .get_cpuid = emulator_get_cpuid,
801806d9 5645 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5646 .get_hflags = emulator_get_hflags,
5647 .set_hflags = emulator_set_hflags,
0234bf88 5648 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5649};
5650
95cb2295
GN		 5651static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5652{
37ccdcbe 5653 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5654 /*
5655 * an sti; sti; sequence only disable interrupts for the first
5656 * instruction. So, if the last instruction, be it emulated or
5657 * not, left the system with the INT_STI flag enabled, it
5658 * means that the last instruction is an sti. We should not
5659 * leave the flag on in this case. The same goes for mov ss
5660 */
37ccdcbe
PB		 5661 if (int_shadow & mask)
5662 mask = 0;
6addfc42 5663 if (unlikely(int_shadow || mask)) {
95cb2295 5664 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5665 if (!mask)
5666 kvm_make_request(KVM_REQ_EVENT, vcpu);
5667 }
95cb2295
GN		 5668}
5669
ef54bcfe 5670static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5671{
5672 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5673 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5674 return kvm_propagate_fault(vcpu, &ctxt->exception);
5675
5676 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5677 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5678 ctxt->exception.error_code);
54b8486f 5679 else
da9cb575 5680 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5681 return false;
54b8486f
GN		 5682}
5683
8ec4722d
MG		 5684static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5685{
adf52235 5686 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5687 int cs_db, cs_l;
5688
8ec4722d
MG		 5689 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5690
adf52235 5691 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5692 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5693
adf52235
TY		 5694 ctxt->eip = kvm_rip_read(vcpu);
5695 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5696 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5697 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5698 cs_db ? X86EMUL_MODE_PROT32 :
5699 X86EMUL_MODE_PROT16;
a584539b 5700 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5701 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5702 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5703
dd856efa 5704 init_decode_cache(ctxt);
7ae441ea 5705 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5706}
5707
71f9833b 5708int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5709{
9d74191a 5710 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5711 int ret;
5712
5713 init_emulate_ctxt(vcpu);
5714
9dac77fa
AK		 5715 ctxt->op_bytes = 2;
5716 ctxt->ad_bytes = 2;
5717 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5718 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5719
5720 if (ret != X86EMUL_CONTINUE)
5721 return EMULATE_FAIL;
5722
9dac77fa 5723 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5724 kvm_rip_write(vcpu, ctxt->eip);
5725 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5726
63995653
MG		 5727 return EMULATE_DONE;
5728}
5729EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5730
e2366171 5731static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5732{
fc3a9157
JR		 5733 int r = EMULATE_DONE;
5734
6d77dbfc
GN		 5735 ++vcpu->stat.insn_emulation_fail;
5736 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5737
5738 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5739 return EMULATE_FAIL;
5740
a2b9e6c1 5741 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5742 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5743 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5744 vcpu->run->internal.ndata = 0;
1f4dcb3b 5745 r = EMULATE_USER_EXIT;
fc3a9157 5746 }
e2366171 5747
6d77dbfc 5748 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5749
5750 return r;
6d77dbfc
GN		 5751}
5752
93c05d3e 5753static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5754 bool write_fault_to_shadow_pgtable,
5755 int emulation_type)
a6f177ef 5756{
95b3cf69 5757 gpa_t gpa = cr2;
ba049e93 5758 kvm_pfn_t pfn;
a6f177ef 5759
991eebf9
GN		 5760 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5761 return false;
5762
95b3cf69
XG		 5763 if (!vcpu->arch.mmu.direct_map) {
5764 /*
5765 * Write permission should be allowed since only
5766 * write access need to be emulated.
5767 */
5768 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5769
95b3cf69
XG		 5770 /*
5771 * If the mapping is invalid in guest, let cpu retry
5772 * it to generate fault.
5773 */
5774 if (gpa == UNMAPPED_GVA)
5775 return true;
5776 }
a6f177ef 5777
8e3d9d06
XG		 5778 /*
5779 * Do not retry the unhandleable instruction if it faults on the
5780 * readonly host memory, otherwise it will goto a infinite loop:
5781 * retry instruction -> write #PF -> emulation fail -> retry
5782 * instruction -> ...
5783 */
5784 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5785
5786 /*
5787 * If the instruction failed on the error pfn, it can not be fixed,
5788 * report the error to userspace.
5789 */
5790 if (is_error_noslot_pfn(pfn))
5791 return false;
5792
5793 kvm_release_pfn_clean(pfn);
5794
5795 /* The instructions are well-emulated on direct mmu. */
5796 if (vcpu->arch.mmu.direct_map) {
5797 unsigned int indirect_shadow_pages;
5798
5799 spin_lock(&vcpu->kvm->mmu_lock);
5800 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5801 spin_unlock(&vcpu->kvm->mmu_lock);
5802
5803 if (indirect_shadow_pages)
5804 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5805
a6f177ef 5806 return true;
8e3d9d06 5807 }
a6f177ef 5808
95b3cf69
XG		 5809 /*
5810 * if emulation was due to access to shadowed page table
5811 * and it failed try to unshadow page and re-enter the
5812 * guest to let CPU execute the instruction.
5813 */
5814 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5815
5816 /*
5817 * If the access faults on its page table, it can not
5818 * be fixed by unprotecting shadow page and it should
5819 * be reported to userspace.
5820 */
5821 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5822}
5823
1cb3f3ae
XG		 5824static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5825 unsigned long cr2, int emulation_type)
5826{
5827 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5828 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5829
5830 last_retry_eip = vcpu->arch.last_retry_eip;
5831 last_retry_addr = vcpu->arch.last_retry_addr;
5832
5833 /*
5834 * If the emulation is caused by #PF and it is non-page_table
5835 * writing instruction, it means the VM-EXIT is caused by shadow
5836 * page protected, we can zap the shadow page and retry this
5837 * instruction directly.
5838 *
5839 * Note: if the guest uses a non-page-table modifying instruction
5840 * on the PDE that points to the instruction, then we will unmap
5841 * the instruction and go to an infinite loop. So, we cache the
5842 * last retried eip and the last fault address, if we meet the eip
5843 * and the address again, we can break out of the potential infinite
5844 * loop.
5845 */
5846 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5847
5848 if (!(emulation_type & EMULTYPE_RETRY))
5849 return false;
5850
5851 if (x86_page_table_writing_insn(ctxt))
5852 return false;
5853
5854 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5855 return false;
5856
5857 vcpu->arch.last_retry_eip = ctxt->eip;
5858 vcpu->arch.last_retry_addr = cr2;
5859
5860 if (!vcpu->arch.mmu.direct_map)
5861 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5862
22368028 5863 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5864
5865 return true;
5866}
5867
716d51ab
GN		 5868static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5869static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5870
64d60670 5871static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5872{
64d60670 5873 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5874 /* This is a good place to trace that we are exiting SMM. */
5875 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5876
c43203ca
PB		 5877 /* Process a latched INIT or SMI, if any. */
5878 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5879 }
699023e2
PB		 5880
5881 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5882}
5883
5884static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5885{
5886 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5887
a584539b 5888 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5889
5890 if (changed & HF_SMM_MASK)
5891 kvm_smm_changed(vcpu);
a584539b
PB		 5892}
5893
4a1e10d5
PB		 5894static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5895 unsigned long *db)
5896{
5897 u32 dr6 = 0;
5898 int i;
5899 u32 enable, rwlen;
5900
5901 enable = dr7;
5902 rwlen = dr7 >> 16;
5903 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5904 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5905 dr6 |= (1 << i);
5906 return dr6;
5907}
5908
c8401dda 5909static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5910{
5911 struct kvm_run *kvm_run = vcpu->run;
5912
c8401dda
PB		 5913 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5914 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5915 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5916 kvm_run->debug.arch.exception = DB_VECTOR;
5917 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5918 *r = EMULATE_USER_EXIT;
5919 } else {
5920 /*
5921 * "Certain debug exceptions may clear bit 0-3. The
5922 * remaining contents of the DR6 register are never
5923 * cleared by the processor".
5924 */
5925 vcpu->arch.dr6 &= ~15;
5926 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5927 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5928 }
5929}
5930
6affcbed
KH		 5931int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5932{
5933 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5934 int r = EMULATE_DONE;
5935
5936 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5937
5938 /*
5939 * rflags is the old, "raw" value of the flags. The new value has
5940 * not been saved yet.
5941 *
5942 * This is correct even for TF set by the guest, because "the
5943 * processor will not generate this exception after the instruction
5944 * that sets the TF flag".
5945 */
5946 if (unlikely(rflags & X86_EFLAGS_TF))
5947 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5948 return r == EMULATE_DONE;
5949}
5950EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5951
4a1e10d5
PB		 5952static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5953{
4a1e10d5
PB		 5954 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5955 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5956 struct kvm_run *kvm_run = vcpu->run;
5957 unsigned long eip = kvm_get_linear_rip(vcpu);
5958 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5959 vcpu->arch.guest_debug_dr7,
5960 vcpu->arch.eff_db);
5961
5962 if (dr6 != 0) {
6f43ed01 5963 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5964 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5965 kvm_run->debug.arch.exception = DB_VECTOR;
5966 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5967 *r = EMULATE_USER_EXIT;
5968 return true;
5969 }
5970 }
5971
4161a569
NA		 5972 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5973 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5974 unsigned long eip = kvm_get_linear_rip(vcpu);
5975 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5976 vcpu->arch.dr7,
5977 vcpu->arch.db);
5978
5979 if (dr6 != 0) {
5980 vcpu->arch.dr6 &= ~15;
6f43ed01 5981 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5982 kvm_queue_exception(vcpu, DB_VECTOR);
5983 *r = EMULATE_DONE;
5984 return true;
5985 }
5986 }
5987
5988 return false;
5989}
5990
04789b66
LA		 5991static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
5992{
2d7921c4
AM		 5993 switch (ctxt->opcode_len) {
5994 case 1:
5995 switch (ctxt->b) {
5996 case 0xe4: /* IN */
5997 case 0xe5:
5998 case 0xec:
5999 case 0xed:
6000 case 0xe6: /* OUT */
6001 case 0xe7:
6002 case 0xee:
6003 case 0xef:
6004 case 0x6c: /* INS */
6005 case 0x6d:
6006 case 0x6e: /* OUTS */
6007 case 0x6f:
6008 return true;
6009 }
6010 break;
6011 case 2:
6012 switch (ctxt->b) {
6013 case 0x33: /* RDPMC */
6014 return true;
6015 }
6016 break;
04789b66
LA		 6017 }
6018
6019 return false;
6020}
6021
51d8b661
AP		 6022int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6023 unsigned long cr2,
dc25e89e
AP		 6024 int emulation_type,
6025 void *insn,
6026 int insn_len)
bbd9b64e 6027{
95cb2295 6028 int r;
9d74191a 6029 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6030 bool writeback = true;
93c05d3e 6031 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6032
93c05d3e
XG		 6033 /*
6034 * Clear write_fault_to_shadow_pgtable here to ensure it is
6035 * never reused.
6036 */
6037 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6038 kvm_clear_exception_queue(vcpu);
8d7d8102 6039
571008da 6040 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6041 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6042
6043 /*
6044 * We will reenter on the same instruction since
6045 * we do not set complete_userspace_io. This does not
6046 * handle watchpoints yet, those would be handled in
6047 * the emulate_ops.
6048 */
d391f120
VK		 6049 if (!(emulation_type & EMULTYPE_SKIP) &&
6050 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6051 return r;
6052
9d74191a
TY		 6053 ctxt->interruptibility = 0;
6054 ctxt->have_exception = false;
e0ad0b47 6055 ctxt->exception.vector = -1;
9d74191a 6056 ctxt->perm_ok = false;
bbd9b64e 6057
b51e974f 6058 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6059
9d74191a 6060 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6061
e46479f8 6062 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6063 ++vcpu->stat.insn_emulation;
1d2887e2 6064 if (r != EMULATION_OK) {
4005996e
AK		 6065 if (emulation_type & EMULTYPE_TRAP_UD)
6066 return EMULATE_FAIL;
991eebf9
GN		 6067 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6068 emulation_type))
bbd9b64e 6069 return EMULATE_DONE;
6ea6e843
PB		 6070 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6071 return EMULATE_DONE;
6d77dbfc
GN		 6072 if (emulation_type & EMULTYPE_SKIP)
6073 return EMULATE_FAIL;
e2366171 6074 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6075 }
6076 }
6077
04789b66
LA		 6078 if ((emulation_type & EMULTYPE_VMWARE) &&
6079 !is_vmware_backdoor_opcode(ctxt))
6080 return EMULATE_FAIL;
6081
ba8afb6b 6082 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6083 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6084 if (ctxt->eflags & X86_EFLAGS_RF)
6085 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6086 return EMULATE_DONE;
6087 }
6088
1cb3f3ae
XG		 6089 if (retry_instruction(ctxt, cr2, emulation_type))
6090 return EMULATE_DONE;
6091
7ae441ea 6092 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6093 changes registers values during IO operation */
7ae441ea
GN		 6094 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6095 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6096 emulator_invalidate_register_cache(ctxt);
7ae441ea 6097 }
4d2179e1 6098
5cd21917 6099restart:
0f89b207
TL		 6100 /* Save the faulting GPA (cr2) in the address field */
6101 ctxt->exception.address = cr2;
6102
9d74191a 6103 r = x86_emulate_insn(ctxt);
bbd9b64e 6104
775fde86
JR		 6105 if (r == EMULATION_INTERCEPTED)
6106 return EMULATE_DONE;
6107
d2ddd1c4 6108 if (r == EMULATION_FAILED) {
991eebf9
GN		 6109 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6110 emulation_type))
c3cd7ffa
GN		 6111 return EMULATE_DONE;
6112
e2366171 6113 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6114 }
6115
9d74191a 6116 if (ctxt->have_exception) {
d2ddd1c4 6117 r = EMULATE_DONE;
ef54bcfe
PB		 6118 if (inject_emulated_exception(vcpu))
6119 return r;
d2ddd1c4 6120 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6121 if (!vcpu->arch.pio.in) {
6122 /* FIXME: return into emulator if single-stepping. */
3457e419 6123 vcpu->arch.pio.count = 0;
0912c977 6124 } else {
7ae441ea 6125 writeback = false;
716d51ab
GN		 6126 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6127 }
ac0a48c3 6128 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6129 } else if (vcpu->mmio_needed) {
6130 if (!vcpu->mmio_is_write)
6131 writeback = false;
ac0a48c3 6132 r = EMULATE_USER_EXIT;
716d51ab 6133 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6134 } else if (r == EMULATION_RESTART)
5cd21917 6135 goto restart;
d2ddd1c4
GN		 6136 else
6137 r = EMULATE_DONE;
f850e2e6 6138
7ae441ea 6139 if (writeback) {
6addfc42 6140 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6141 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6142 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6143 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6144 if (r == EMULATE_DONE &&
6145 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6146 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6147 if (!ctxt->have_exception ||
6148 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6149 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6150
6151 /*
6152 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6153 * do nothing, and it will be requested again as soon as
6154 * the shadow expires. But we still need to check here,
6155 * because POPF has no interrupt shadow.
6156 */
6157 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6158 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6159 } else
6160 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6161
6162 return r;
de7d789a 6163}
51d8b661 6164EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6165
dca7f128
SC		 6166static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6167 unsigned short port)
de7d789a 6168{
cf8f70bf 6169 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6170 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6171 size, port, &val, 1);
cf8f70bf 6172 /* do not return to emulator after return from userspace */
7972995b 6173 vcpu->arch.pio.count = 0;
de7d789a
CO		 6174 return ret;
6175}
de7d789a 6176
8370c3d0
TL		 6177static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6178{
6179 unsigned long val;
6180
6181 /* We should only ever be called with arch.pio.count equal to 1 */
6182 BUG_ON(vcpu->arch.pio.count != 1);
6183
6184 /* For size less than 4 we merge, else we zero extend */
6185 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6186 : 0;
6187
6188 /*
6189 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6190 * the copy and tracing
6191 */
6192 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6193 vcpu->arch.pio.port, &val, 1);
6194 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6195
6196 return 1;
6197}
6198
dca7f128
SC		 6199static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6200 unsigned short port)
8370c3d0
TL		 6201{
6202 unsigned long val;
6203 int ret;
6204
6205 /* For size less than 4 we merge, else we zero extend */
6206 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6207
6208 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6209 &val, 1);
6210 if (ret) {
6211 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6212 return ret;
6213 }
6214
6215 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6216
6217 return 0;
6218}
dca7f128
SC		 6219
6220int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6221{
6222 int ret = kvm_skip_emulated_instruction(vcpu);
6223
6224 /*
6225 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6226 * KVM_EXIT_DEBUG here.
6227 */
6228 if (in)
6229 return kvm_fast_pio_in(vcpu, size, port) && ret;
6230 else
6231 return kvm_fast_pio_out(vcpu, size, port) && ret;
6232}
6233EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6234
251a5fd6 6235static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6236{
0a3aee0d 6237 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6238 return 0;
8cfdc000
ZA		 6239}
6240
6241static void tsc_khz_changed(void *data)
c8076604 6242{
8cfdc000
ZA		 6243 struct cpufreq_freqs *freq = data;
6244 unsigned long khz = 0;
6245
6246 if (data)
6247 khz = freq->new;
6248 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6249 khz = cpufreq_quick_get(raw_smp_processor_id());
6250 if (!khz)
6251 khz = tsc_khz;
0a3aee0d 6252 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6253}
6254
5fa4ec9c 6255#ifdef CONFIG_X86_64
0092e434
VK		 6256static void kvm_hyperv_tsc_notifier(void)
6257{
0092e434
VK		 6258 struct kvm *kvm;
6259 struct kvm_vcpu *vcpu;
6260 int cpu;
6261
6262 spin_lock(&kvm_lock);
6263 list_for_each_entry(kvm, &vm_list, vm_list)
6264 kvm_make_mclock_inprogress_request(kvm);
6265
6266 hyperv_stop_tsc_emulation();
6267
6268 /* TSC frequency always matches when on Hyper-V */
6269 for_each_present_cpu(cpu)
6270 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6271 kvm_max_guest_tsc_khz = tsc_khz;
6272
6273 list_for_each_entry(kvm, &vm_list, vm_list) {
6274 struct kvm_arch *ka = &kvm->arch;
6275
6276 spin_lock(&ka->pvclock_gtod_sync_lock);
6277
6278 pvclock_update_vm_gtod_copy(kvm);
6279
6280 kvm_for_each_vcpu(cpu, vcpu, kvm)
6281 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6282
6283 kvm_for_each_vcpu(cpu, vcpu, kvm)
6284 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6285
6286 spin_unlock(&ka->pvclock_gtod_sync_lock);
6287 }
6288 spin_unlock(&kvm_lock);
0092e434 6289}
5fa4ec9c 6290#endif
0092e434 6291
c8076604
GH		 6292static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6293 void *data)
6294{
6295 struct cpufreq_freqs *freq = data;
6296 struct kvm *kvm;
6297 struct kvm_vcpu *vcpu;
6298 int i, send_ipi = 0;
6299
8cfdc000
ZA		 6300 /*
6301 * We allow guests to temporarily run on slowing clocks,
6302 * provided we notify them after, or to run on accelerating
6303 * clocks, provided we notify them before. Thus time never
6304 * goes backwards.
6305 *
6306 * However, we have a problem. We can't atomically update
6307 * the frequency of a given CPU from this function; it is
6308 * merely a notifier, which can be called from any CPU.
6309 * Changing the TSC frequency at arbitrary points in time
6310 * requires a recomputation of local variables related to
6311 * the TSC for each VCPU. We must flag these local variables
6312 * to be updated and be sure the update takes place with the
6313 * new frequency before any guests proceed.
6314 *
6315 * Unfortunately, the combination of hotplug CPU and frequency
6316 * change creates an intractable locking scenario; the order
6317 * of when these callouts happen is undefined with respect to
6318 * CPU hotplug, and they can race with each other. As such,
6319 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6320 * undefined; you can actually have a CPU frequency change take
6321 * place in between the computation of X and the setting of the
6322 * variable. To protect against this problem, all updates of
6323 * the per_cpu tsc_khz variable are done in an interrupt
6324 * protected IPI, and all callers wishing to update the value
6325 * must wait for a synchronous IPI to complete (which is trivial
6326 * if the caller is on the CPU already). This establishes the
6327 * necessary total order on variable updates.
6328 *
6329 * Note that because a guest time update may take place
6330 * anytime after the setting of the VCPU's request bit, the
6331 * correct TSC value must be set before the request. However,
6332 * to ensure the update actually makes it to any guest which
6333 * starts running in hardware virtualization between the set
6334 * and the acquisition of the spinlock, we must also ping the
6335 * CPU after setting the request bit.
6336 *
6337 */
6338
c8076604
GH		 6339 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6340 return 0;
6341 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6342 return 0;
8cfdc000
ZA		 6343
6344 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6345
2f303b74 6346 spin_lock(&kvm_lock);
c8076604 6347 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6348 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6349 if (vcpu->cpu != freq->cpu)
6350 continue;
c285545f 6351 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6352 if (vcpu->cpu != smp_processor_id())
8cfdc000 6353 send_ipi = 1;
c8076604
GH		 6354 }
6355 }
2f303b74 6356 spin_unlock(&kvm_lock);
c8076604
GH		 6357
6358 if (freq->old < freq->new && send_ipi) {
6359 /*
6360 * We upscale the frequency. Must make the guest
6361 * doesn't see old kvmclock values while running with
6362 * the new frequency, otherwise we risk the guest sees
6363 * time go backwards.
6364 *
6365 * In case we update the frequency for another cpu
6366 * (which might be in guest context) send an interrupt
6367 * to kick the cpu out of guest context. Next time
6368 * guest context is entered kvmclock will be updated,
6369 * so the guest will not see stale values.
6370 */
8cfdc000 6371 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6372 }
6373 return 0;
6374}
6375
6376static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6377 .notifier_call = kvmclock_cpufreq_notifier
6378};
6379
251a5fd6 6380static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6381{
251a5fd6
SAS		 6382 tsc_khz_changed(NULL);
6383 return 0;
8cfdc000
ZA		 6384}
6385
b820cc0c
ZA		 6386static void kvm_timer_init(void)
6387{
c285545f 6388 max_tsc_khz = tsc_khz;
460dd42e 6389
b820cc0c 6390 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6391#ifdef CONFIG_CPU_FREQ
6392 struct cpufreq_policy policy;
758f588d
BP		 6393 int cpu;
6394
c285545f 6395 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6396 cpu = get_cpu();
6397 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6398 if (policy.cpuinfo.max_freq)
6399 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6400 put_cpu();
c285545f 6401#endif
b820cc0c
ZA		 6402 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6403 CPUFREQ_TRANSITION_NOTIFIER);
6404 }
c285545f 6405 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6406
73c1b41e 6407 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6408 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6409}
6410
dd60d217
AK		 6411DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6412EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6413
f5132b01 6414int kvm_is_in_guest(void)
ff9d07a0 6415{
086c9855 6416 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6417}
6418
6419static int kvm_is_user_mode(void)
6420{
6421 int user_mode = 3;
dcf46b94 6422
086c9855
AS		 6423 if (__this_cpu_read(current_vcpu))
6424 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6425
ff9d07a0
ZY		 6426 return user_mode != 0;
6427}
6428
6429static unsigned long kvm_get_guest_ip(void)
6430{
6431 unsigned long ip = 0;
dcf46b94 6432
086c9855
AS		 6433 if (__this_cpu_read(current_vcpu))
6434 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6435
ff9d07a0
ZY		 6436 return ip;
6437}
6438
6439static struct perf_guest_info_callbacks kvm_guest_cbs = {
6440 .is_in_guest = kvm_is_in_guest,
6441 .is_user_mode = kvm_is_user_mode,
6442 .get_guest_ip = kvm_get_guest_ip,
6443};
6444
ce88decf
XG		 6445static void kvm_set_mmio_spte_mask(void)
6446{
6447 u64 mask;
6448 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6449
6450 /*
6451 * Set the reserved bits and the present bit of an paging-structure
6452 * entry to generate page fault with PFER.RSV = 1.
6453 */
885032b9 6454 /* Mask the reserved physical address bits. */
d1431483 6455 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6456
885032b9 6457 /* Set the present bit. */
ce88decf
XG		 6458 mask |= 1ull;
6459
6460#ifdef CONFIG_X86_64
6461 /*
6462 * If reserved bit is not supported, clear the present bit to disable
6463 * mmio page fault.
6464 */
6465 if (maxphyaddr == 52)
6466 mask &= ~1ull;
6467#endif
6468
dcdca5fe 6469 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6470}
6471
16e8d74d
MT		 6472#ifdef CONFIG_X86_64
6473static void pvclock_gtod_update_fn(struct work_struct *work)
6474{
d828199e
MT		 6475 struct kvm *kvm;
6476
6477 struct kvm_vcpu *vcpu;
6478 int i;
6479
2f303b74 6480 spin_lock(&kvm_lock);
d828199e
MT		 6481 list_for_each_entry(kvm, &vm_list, vm_list)
6482 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6483 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6484 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6485 spin_unlock(&kvm_lock);
16e8d74d
MT		 6486}
6487
6488static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6489
6490/*
6491 * Notification about pvclock gtod data update.
6492 */
6493static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6494 void *priv)
6495{
6496 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6497 struct timekeeper *tk = priv;
6498
6499 update_pvclock_gtod(tk);
6500
6501 /* disable master clock if host does not trust, or does not
b0c39dc6 6502 * use, TSC based clocksource.
16e8d74d 6503 */
b0c39dc6 6504 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6505 atomic_read(&kvm_guest_has_master_clock) != 0)
6506 queue_work(system_long_wq, &pvclock_gtod_work);
6507
6508 return 0;
6509}
6510
6511static struct notifier_block pvclock_gtod_notifier = {
6512 .notifier_call = pvclock_gtod_notify,
6513};
6514#endif
6515
f8c16bba 6516int kvm_arch_init(void *opaque)
043405e1 6517{
b820cc0c 6518 int r;
6b61edf7 6519 struct kvm_x86_ops *ops = opaque;
f8c16bba 6520
f8c16bba
ZX		 6521 if (kvm_x86_ops) {
6522 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6523 r = -EEXIST;
6524 goto out;
f8c16bba
ZX		 6525 }
6526
6527 if (!ops->cpu_has_kvm_support()) {
6528 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6529 r = -EOPNOTSUPP;
6530 goto out;
f8c16bba
ZX		 6531 }
6532 if (ops->disabled_by_bios()) {
6533 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6534 r = -EOPNOTSUPP;
6535 goto out;
f8c16bba
ZX		 6536 }
6537
013f6a5d
MT		 6538 r = -ENOMEM;
6539 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6540 if (!shared_msrs) {
6541 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6542 goto out;
6543 }
6544
97db56ce
AK		 6545 r = kvm_mmu_module_init();
6546 if (r)
013f6a5d 6547 goto out_free_percpu;
97db56ce 6548
ce88decf 6549 kvm_set_mmio_spte_mask();
97db56ce 6550
f8c16bba 6551 kvm_x86_ops = ops;
920c8377 6552
7b52345e 6553 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6554 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6555 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6556 kvm_timer_init();
c8076604 6557
ff9d07a0
ZY		 6558 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6559
d366bf7e 6560 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6561 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6562
c5cc421b 6563 kvm_lapic_init();
16e8d74d
MT		 6564#ifdef CONFIG_X86_64
6565 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6566
5fa4ec9c 6567 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6568 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6569#endif
6570
f8c16bba 6571 return 0;
56c6d28a 6572
013f6a5d
MT		 6573out_free_percpu:
6574 free_percpu(shared_msrs);
56c6d28a 6575out:
56c6d28a 6576 return r;
043405e1 6577}
8776e519 6578
f8c16bba
ZX		 6579void kvm_arch_exit(void)
6580{
0092e434 6581#ifdef CONFIG_X86_64
5fa4ec9c 6582 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6583 clear_hv_tscchange_cb();
6584#endif
cef84c30 6585 kvm_lapic_exit();
ff9d07a0
ZY		 6586 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6587
888d256e
JK		 6588 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6589 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6590 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6591 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6592#ifdef CONFIG_X86_64
6593 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6594#endif
f8c16bba 6595 kvm_x86_ops = NULL;
56c6d28a 6596 kvm_mmu_module_exit();
013f6a5d 6597 free_percpu(shared_msrs);
56c6d28a 6598}
f8c16bba 6599
5cb56059 6600int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6601{
6602 ++vcpu->stat.halt_exits;
35754c98 6603 if (lapic_in_kernel(vcpu)) {
a4535290 6604 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6605 return 1;
6606 } else {
6607 vcpu->run->exit_reason = KVM_EXIT_HLT;
6608 return 0;
6609 }
6610}
5cb56059
JS		 6611EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6612
6613int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6614{
6affcbed
KH		 6615 int ret = kvm_skip_emulated_instruction(vcpu);
6616 /*
6617 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6618 * KVM_EXIT_DEBUG here.
6619 */
6620 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6621}
8776e519
HB		 6622EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6623
8ef81a9a 6624#ifdef CONFIG_X86_64
55dd00a7
MT		 6625static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6626 unsigned long clock_type)
6627{
6628 struct kvm_clock_pairing clock_pairing;
6629 struct timespec ts;
80fbd89c 6630 u64 cycle;
55dd00a7
MT		 6631 int ret;
6632
6633 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6634 return -KVM_EOPNOTSUPP;
6635
6636 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6637 return -KVM_EOPNOTSUPP;
6638
6639 clock_pairing.sec = ts.tv_sec;
6640 clock_pairing.nsec = ts.tv_nsec;
6641 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6642 clock_pairing.flags = 0;
6643
6644 ret = 0;
6645 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6646 sizeof(struct kvm_clock_pairing)))
6647 ret = -KVM_EFAULT;
6648
6649 return ret;
6650}
8ef81a9a 6651#endif
55dd00a7 6652
6aef266c
SV		 6653/*
6654 * kvm_pv_kick_cpu_op: Kick a vcpu.
6655 *
6656 * @apicid - apicid of vcpu to be kicked.
6657 */
6658static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6659{
24d2166b 6660 struct kvm_lapic_irq lapic_irq;
6aef266c 6661
24d2166b
R		 6662 lapic_irq.shorthand = 0;
6663 lapic_irq.dest_mode = 0;
ebd28fcb 6664 lapic_irq.level = 0;
24d2166b 6665 lapic_irq.dest_id = apicid;
93bbf0b8 6666 lapic_irq.msi_redir_hint = false;
6aef266c 6667
24d2166b 6668 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6669 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6670}
6671
d62caabb
AS		 6672void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6673{
6674 vcpu->arch.apicv_active = false;
6675 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6676}
6677
8776e519
HB		 6678int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6679{
6680 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6681 int op_64_bit;
8776e519 6682
6356ee0c
MR		 6683 if (kvm_hv_hypercall_enabled(vcpu->kvm)) {
6684 if (!kvm_hv_hypercall(vcpu))
6685 return 0;
6686 goto out;
6687 }
55cd8e5a 6688
5fdbf976
MT		 6689 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6690 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6691 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6692 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6693 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6694
229456fc 6695 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6696
a449c7aa
NA		 6697 op_64_bit = is_64_bit_mode(vcpu);
6698 if (!op_64_bit) {
8776e519
HB		 6699 nr &= 0xFFFFFFFF;
6700 a0 &= 0xFFFFFFFF;
6701 a1 &= 0xFFFFFFFF;
6702 a2 &= 0xFFFFFFFF;
6703 a3 &= 0xFFFFFFFF;
6704 }
6705
07708c4a
JK		 6706 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6707 ret = -KVM_EPERM;
6356ee0c 6708 goto out_error;
07708c4a
JK		 6709 }
6710
8776e519 6711 switch (nr) {
b93463aa
AK		 6712 case KVM_HC_VAPIC_POLL_IRQ:
6713 ret = 0;
6714 break;
6aef266c
SV		 6715 case KVM_HC_KICK_CPU:
6716 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6717 ret = 0;
6718 break;
8ef81a9a 6719#ifdef CONFIG_X86_64
55dd00a7
MT		 6720 case KVM_HC_CLOCK_PAIRING:
6721 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6722 break;
8ef81a9a 6723#endif
8776e519
HB		 6724 default:
6725 ret = -KVM_ENOSYS;
6726 break;
6727 }
6356ee0c 6728out_error:
a449c7aa
NA		 6729 if (!op_64_bit)
6730 ret = (u32)ret;
5fdbf976 6731 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c
MR		 6732
6733out:
f11c3a8d 6734 ++vcpu->stat.hypercalls;
6356ee0c 6735 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6736}
6737EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6738
b6785def 6739static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6740{
d6aa1000 6741 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6742 char instruction[3];
5fdbf976 6743 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6744
8776e519 6745 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6746
ce2e852e
DV		 6747 return emulator_write_emulated(ctxt, rip, instruction, 3,
6748 &ctxt->exception);
8776e519
HB		 6749}
6750
851ba692 6751static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6752{
782d422b
MG		 6753 return vcpu->run->request_interrupt_window &&
6754 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6755}
6756
851ba692 6757static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6758{
851ba692
AK		 6759 struct kvm_run *kvm_run = vcpu->run;
6760
91586a3b 6761 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6762 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6763 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6764 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6765 kvm_run->ready_for_interrupt_injection =
6766 pic_in_kernel(vcpu->kvm) ||
782d422b 6767 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6768}
6769
95ba8273
GN		 6770static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6771{
6772 int max_irr, tpr;
6773
6774 if (!kvm_x86_ops->update_cr8_intercept)
6775 return;
6776
bce87cce 6777 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6778 return;
6779
d62caabb
AS		 6780 if (vcpu->arch.apicv_active)
6781 return;
6782
8db3baa2
GN		 6783 if (!vcpu->arch.apic->vapic_addr)
6784 max_irr = kvm_lapic_find_highest_irr(vcpu);
6785 else
6786 max_irr = -1;
95ba8273
GN		 6787
6788 if (max_irr != -1)
6789 max_irr >>= 4;
6790
6791 tpr = kvm_lapic_get_cr8(vcpu);
6792
6793 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6794}
6795
b6b8a145 6796static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6797{
b6b8a145
JK		 6798 int r;
6799
95ba8273 6800 /* try to reinject previous events if any */
664f8e26 6801
1a680e35
LA		 6802 if (vcpu->arch.exception.injected)
6803 kvm_x86_ops->queue_exception(vcpu);
664f8e26 6804 /*
a042c26f
LA		 6805 * Do not inject an NMI or interrupt if there is a pending
6806 * exception. Exceptions and interrupts are recognized at
6807 * instruction boundaries, i.e. the start of an instruction.
6808 * Trap-like exceptions, e.g. #DB, have higher priority than
6809 * NMIs and interrupts, i.e. traps are recognized before an
6810 * NMI/interrupt that's pending on the same instruction.
6811 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6812 * priority, but are only generated (pended) during instruction
6813 * execution, i.e. a pending fault-like exception means the
6814 * fault occurred on the *previous* instruction and must be
6815 * serviced prior to recognizing any new events in order to
6816 * fully complete the previous instruction.
664f8e26 6817 */
1a680e35
LA		 6818 else if (!vcpu->arch.exception.pending) {
6819 if (vcpu->arch.nmi_injected)
664f8e26 6820 kvm_x86_ops->set_nmi(vcpu);
1a680e35 6821 else if (vcpu->arch.interrupt.injected)
664f8e26 6822 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 6823 }
6824
1a680e35
LA		 6825 /*
6826 * Call check_nested_events() even if we reinjected a previous event
6827 * in order for caller to determine if it should require immediate-exit
6828 * from L2 to L1 due to pending L1 events which require exit
6829 * from L2 to L1.
6830 */
664f8e26
WL		 6831 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6832 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6833 if (r != 0)
6834 return r;
6835 }
6836
6837 /* try to inject new event if pending */
b59bb7bd 6838 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6839 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6840 vcpu->arch.exception.has_error_code,
6841 vcpu->arch.exception.error_code);
d6e8c854 6842
1a680e35 6843 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 6844 vcpu->arch.exception.pending = false;
6845 vcpu->arch.exception.injected = true;
6846
d6e8c854
NA		 6847 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6848 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6849 X86_EFLAGS_RF);
6850
6bdf0662
NA		 6851 if (vcpu->arch.exception.nr == DB_VECTOR &&
6852 (vcpu->arch.dr7 & DR7_GD)) {
6853 vcpu->arch.dr7 &= ~DR7_GD;
6854 kvm_update_dr7(vcpu);
6855 }
6856
cfcd20e5 6857 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 6858 }
6859
6860 /* Don't consider new event if we re-injected an event */
6861 if (kvm_event_needs_reinjection(vcpu))
6862 return 0;
6863
6864 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
6865 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6866 vcpu->arch.smi_pending = false;
52797bf9 6867 ++vcpu->arch.smi_count;
ee2cd4b7 6868 enter_smm(vcpu);
c43203ca 6869 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6870 --vcpu->arch.nmi_pending;
6871 vcpu->arch.nmi_injected = true;
6872 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6873 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6874 /*
6875 * Because interrupts can be injected asynchronously, we are
6876 * calling check_nested_events again here to avoid a race condition.
6877 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6878 * proposal and current concerns. Perhaps we should be setting
6879 * KVM_REQ_EVENT only on certain events and not unconditionally?
6880 */
6881 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6882 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6883 if (r != 0)
6884 return r;
6885 }
95ba8273 6886 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6887 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6888 false);
6889 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6890 }
6891 }
ee2cd4b7 6892
b6b8a145 6893 return 0;
95ba8273
GN		 6894}
6895
7460fb4a
AK		 6896static void process_nmi(struct kvm_vcpu *vcpu)
6897{
6898 unsigned limit = 2;
6899
6900 /*
6901 * x86 is limited to one NMI running, and one NMI pending after it.
6902 * If an NMI is already in progress, limit further NMIs to just one.
6903 * Otherwise, allow two (and we'll inject the first one immediately).
6904 */
6905 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6906 limit = 1;
6907
6908 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6909 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6910 kvm_make_request(KVM_REQ_EVENT, vcpu);
6911}
6912
ee2cd4b7 6913static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6914{
6915 u32 flags = 0;
6916 flags |= seg->g << 23;
6917 flags |= seg->db << 22;
6918 flags |= seg->l << 21;
6919 flags |= seg->avl << 20;
6920 flags |= seg->present << 15;
6921 flags |= seg->dpl << 13;
6922 flags |= seg->s << 12;
6923 flags |= seg->type << 8;
6924 return flags;
6925}
6926
ee2cd4b7 6927static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6928{
6929 struct kvm_segment seg;
6930 int offset;
6931
6932 kvm_get_segment(vcpu, &seg, n);
6933 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6934
6935 if (n < 3)
6936 offset = 0x7f84 + n * 12;
6937 else
6938 offset = 0x7f2c + (n - 3) * 12;
6939
6940 put_smstate(u32, buf, offset + 8, seg.base);
6941 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6942 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6943}
6944
efbb288a 6945#ifdef CONFIG_X86_64
ee2cd4b7 6946static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6947{
6948 struct kvm_segment seg;
6949 int offset;
6950 u16 flags;
6951
6952 kvm_get_segment(vcpu, &seg, n);
6953 offset = 0x7e00 + n * 16;
6954
ee2cd4b7 6955 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6956 put_smstate(u16, buf, offset, seg.selector);
6957 put_smstate(u16, buf, offset + 2, flags);
6958 put_smstate(u32, buf, offset + 4, seg.limit);
6959 put_smstate(u64, buf, offset + 8, seg.base);
6960}
efbb288a 6961#endif
660a5d51 6962
ee2cd4b7 6963static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6964{
6965 struct desc_ptr dt;
6966 struct kvm_segment seg;
6967 unsigned long val;
6968 int i;
6969
6970 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6971 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6972 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6973 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6974
6975 for (i = 0; i < 8; i++)
6976 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6977
6978 kvm_get_dr(vcpu, 6, &val);
6979 put_smstate(u32, buf, 0x7fcc, (u32)val);
6980 kvm_get_dr(vcpu, 7, &val);
6981 put_smstate(u32, buf, 0x7fc8, (u32)val);
6982
6983 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6984 put_smstate(u32, buf, 0x7fc4, seg.selector);
6985 put_smstate(u32, buf, 0x7f64, seg.base);
6986 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6987 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6988
6989 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6990 put_smstate(u32, buf, 0x7fc0, seg.selector);
6991 put_smstate(u32, buf, 0x7f80, seg.base);
6992 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6993 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6994
6995 kvm_x86_ops->get_gdt(vcpu, &dt);
6996 put_smstate(u32, buf, 0x7f74, dt.address);
6997 put_smstate(u32, buf, 0x7f70, dt.size);
6998
6999 kvm_x86_ops->get_idt(vcpu, &dt);
7000 put_smstate(u32, buf, 0x7f58, dt.address);
7001 put_smstate(u32, buf, 0x7f54, dt.size);
7002
7003 for (i = 0; i < 6; i++)
ee2cd4b7 7004 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7005
7006 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7007
7008 /* revision id */
7009 put_smstate(u32, buf, 0x7efc, 0x00020000);
7010 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7011}
7012
ee2cd4b7 7013static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7014{
7015#ifdef CONFIG_X86_64
7016 struct desc_ptr dt;
7017 struct kvm_segment seg;
7018 unsigned long val;
7019 int i;
7020
7021 for (i = 0; i < 16; i++)
7022 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7023
7024 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7025 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7026
7027 kvm_get_dr(vcpu, 6, &val);
7028 put_smstate(u64, buf, 0x7f68, val);
7029 kvm_get_dr(vcpu, 7, &val);
7030 put_smstate(u64, buf, 0x7f60, val);
7031
7032 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7033 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7034 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7035
7036 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7037
7038 /* revision id */
7039 put_smstate(u32, buf, 0x7efc, 0x00020064);
7040
7041 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7042
7043 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7044 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7045 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7046 put_smstate(u32, buf, 0x7e94, seg.limit);
7047 put_smstate(u64, buf, 0x7e98, seg.base);
7048
7049 kvm_x86_ops->get_idt(vcpu, &dt);
7050 put_smstate(u32, buf, 0x7e84, dt.size);
7051 put_smstate(u64, buf, 0x7e88, dt.address);
7052
7053 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7054 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7055 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7056 put_smstate(u32, buf, 0x7e74, seg.limit);
7057 put_smstate(u64, buf, 0x7e78, seg.base);
7058
7059 kvm_x86_ops->get_gdt(vcpu, &dt);
7060 put_smstate(u32, buf, 0x7e64, dt.size);
7061 put_smstate(u64, buf, 0x7e68, dt.address);
7062
7063 for (i = 0; i < 6; i++)
ee2cd4b7 7064 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7065#else
7066 WARN_ON_ONCE(1);
7067#endif
7068}
7069
ee2cd4b7 7070static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7071{
660a5d51 7072 struct kvm_segment cs, ds;
18c3626e 7073 struct desc_ptr dt;
660a5d51
PB		 7074 char buf[512];
7075 u32 cr0;
7076
660a5d51 7077 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7078 memset(buf, 0, 512);
d6321d49 7079 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7080 enter_smm_save_state_64(vcpu, buf);
660a5d51 7081 else
ee2cd4b7 7082 enter_smm_save_state_32(vcpu, buf);
660a5d51 7083
0234bf88
LP		 7084 /*
7085 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7086 * vCPU state (e.g. leave guest mode) after we've saved the state into
7087 * the SMM state-save area.
7088 */
7089 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7090
7091 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7092 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7093
7094 if (kvm_x86_ops->get_nmi_mask(vcpu))
7095 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7096 else
7097 kvm_x86_ops->set_nmi_mask(vcpu, true);
7098
7099 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7100 kvm_rip_write(vcpu, 0x8000);
7101
7102 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7103 kvm_x86_ops->set_cr0(vcpu, cr0);
7104 vcpu->arch.cr0 = cr0;
7105
7106 kvm_x86_ops->set_cr4(vcpu, 0);
7107
18c3626e
PB		 7108 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7109 dt.address = dt.size = 0;
7110 kvm_x86_ops->set_idt(vcpu, &dt);
7111
660a5d51
PB		 7112 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7113
7114 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7115 cs.base = vcpu->arch.smbase;
7116
7117 ds.selector = 0;
7118 ds.base = 0;
7119
7120 cs.limit = ds.limit = 0xffffffff;
7121 cs.type = ds.type = 0x3;
7122 cs.dpl = ds.dpl = 0;
7123 cs.db = ds.db = 0;
7124 cs.s = ds.s = 1;
7125 cs.l = ds.l = 0;
7126 cs.g = ds.g = 1;
7127 cs.avl = ds.avl = 0;
7128 cs.present = ds.present = 1;
7129 cs.unusable = ds.unusable = 0;
7130 cs.padding = ds.padding = 0;
7131
7132 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7133 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7134 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7135 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7136 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7137 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7138
d6321d49 7139 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7140 kvm_x86_ops->set_efer(vcpu, 0);
7141
7142 kvm_update_cpuid(vcpu);
7143 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7144}
7145
ee2cd4b7 7146static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7147{
7148 vcpu->arch.smi_pending = true;
7149 kvm_make_request(KVM_REQ_EVENT, vcpu);
7150}
7151
2860c4b1
PB		 7152void kvm_make_scan_ioapic_request(struct kvm *kvm)
7153{
7154 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7155}
7156
3d81bc7e 7157static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7158{
3d81bc7e
YZ		 7159 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7160 return;
c7c9c56c 7161
6308630b 7162 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7163
b053b2ae 7164 if (irqchip_split(vcpu->kvm))
6308630b 7165 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7166 else {
fa59cc00 7167 if (vcpu->arch.apicv_active)
d62caabb 7168 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7169 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7170 }
e40ff1d6
LA		 7171
7172 if (is_guest_mode(vcpu))
7173 vcpu->arch.load_eoi_exitmap_pending = true;
7174 else
7175 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7176}
7177
7178static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7179{
7180 u64 eoi_exit_bitmap[4];
7181
7182 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7183 return;
7184
5c919412
AS		 7185 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7186 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7187 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7188}
7189
b1394e74
RK		 7190void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7191 unsigned long start, unsigned long end)
7192{
7193 unsigned long apic_address;
7194
7195 /*
7196 * The physical address of apic access page is stored in the VMCS.
7197 * Update it when it becomes invalid.
7198 */
7199 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7200 if (start <= apic_address && apic_address < end)
7201 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7202}
7203
4256f43f
TC		 7204void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7205{
c24ae0dc
TC		 7206 struct page *page = NULL;
7207
35754c98 7208 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7209 return;
7210
4256f43f
TC		 7211 if (!kvm_x86_ops->set_apic_access_page_addr)
7212 return;
7213
c24ae0dc 7214 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7215 if (is_error_page(page))
7216 return;
c24ae0dc
TC		 7217 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7218
7219 /*
7220 * Do not pin apic access page in memory, the MMU notifier
7221 * will call us again if it is migrated or swapped out.
7222 */
7223 put_page(page);
4256f43f
TC		 7224}
7225EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7226
9357d939 7227/*
362c698f 7228 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7229 * exiting to the userspace. Otherwise, the value will be returned to the
7230 * userspace.
7231 */
851ba692 7232static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7233{
7234 int r;
62a193ed
MG		 7235 bool req_int_win =
7236 dm_request_for_irq_injection(vcpu) &&
7237 kvm_cpu_accept_dm_intr(vcpu);
7238
730dca42 7239 bool req_immediate_exit = false;
b6c7a5dc 7240
2fa6e1e1 7241 if (kvm_request_pending(vcpu)) {
a8eeb04a 7242 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7243 kvm_mmu_unload(vcpu);
a8eeb04a 7244 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7245 __kvm_migrate_timers(vcpu);
d828199e
MT		 7246 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7247 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7248 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7249 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7250 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7251 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7252 if (unlikely(r))
7253 goto out;
7254 }
a8eeb04a 7255 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7256 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7257 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7258 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7259 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7260 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7261 r = 0;
7262 goto out;
7263 }
a8eeb04a 7264 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7265 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7266 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7267 r = 0;
7268 goto out;
7269 }
af585b92
GN		 7270 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7271 /* Page is swapped out. Do synthetic halt */
7272 vcpu->arch.apf.halted = true;
7273 r = 1;
7274 goto out;
7275 }
c9aaa895
GC		 7276 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7277 record_steal_time(vcpu);
64d60670
PB		 7278 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7279 process_smi(vcpu);
7460fb4a
AK		 7280 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7281 process_nmi(vcpu);
f5132b01 7282 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7283 kvm_pmu_handle_event(vcpu);
f5132b01 7284 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7285 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7286 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7287 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7288 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7289 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7290 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7291 vcpu->run->eoi.vector =
7292 vcpu->arch.pending_ioapic_eoi;
7293 r = 0;
7294 goto out;
7295 }
7296 }
3d81bc7e
YZ		 7297 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7298 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7299 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7300 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7301 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7302 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7303 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7304 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7305 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7306 r = 0;
7307 goto out;
7308 }
e516cebb
AS		 7309 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7310 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7311 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7312 r = 0;
7313 goto out;
7314 }
db397571
AS		 7315 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7316 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7317 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7318 r = 0;
7319 goto out;
7320 }
f3b138c5
AS		 7321
7322 /*
7323 * KVM_REQ_HV_STIMER has to be processed after
7324 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7325 * depend on the guest clock being up-to-date
7326 */
1f4b34f8
AS		 7327 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7328 kvm_hv_process_stimers(vcpu);
2f52d58c 7329 }
b93463aa 7330
b463a6f7 7331 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7332 ++vcpu->stat.req_event;
66450a21
JK		 7333 kvm_apic_accept_events(vcpu);
7334 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7335 r = 1;
7336 goto out;
7337 }
7338
b6b8a145
JK		 7339 if (inject_pending_event(vcpu, req_int_win) != 0)
7340 req_immediate_exit = true;
321c5658 7341 else {
cc3d967f 7342 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7343 *
cc3d967f
LP		 7344 * SMIs have three cases:
7345 * 1) They can be nested, and then there is nothing to
7346 * do here because RSM will cause a vmexit anyway.
7347 * 2) There is an ISA-specific reason why SMI cannot be
7348 * injected, and the moment when this changes can be
7349 * intercepted.
7350 * 3) Or the SMI can be pending because
7351 * inject_pending_event has completed the injection
7352 * of an IRQ or NMI from the previous vmexit, and
7353 * then we request an immediate exit to inject the
7354 * SMI.
c43203ca
PB		 7355 */
7356 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7357 if (!kvm_x86_ops->enable_smi_window(vcpu))
7358 req_immediate_exit = true;
321c5658
YS		 7359 if (vcpu->arch.nmi_pending)
7360 kvm_x86_ops->enable_nmi_window(vcpu);
7361 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7362 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7363 WARN_ON(vcpu->arch.exception.pending);
321c5658 7364 }
b463a6f7
AK		 7365
7366 if (kvm_lapic_enabled(vcpu)) {
7367 update_cr8_intercept(vcpu);
7368 kvm_lapic_sync_to_vapic(vcpu);
7369 }
7370 }
7371
d8368af8
AK		 7372 r = kvm_mmu_reload(vcpu);
7373 if (unlikely(r)) {
d905c069 7374 goto cancel_injection;
d8368af8
AK		 7375 }
7376
b6c7a5dc
HB		 7377 preempt_disable();
7378
7379 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7380
7381 /*
7382 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7383 * IPI are then delayed after guest entry, which ensures that they
7384 * result in virtual interrupt delivery.
7385 */
7386 local_irq_disable();
6b7e2d09
XG		 7387 vcpu->mode = IN_GUEST_MODE;
7388
01b71917
MT		 7389 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7390
0f127d12 7391 /*
b95234c8 7392 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7393 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7394 *
7395 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7396 * pairs with the memory barrier implicit in pi_test_and_set_on
7397 * (see vmx_deliver_posted_interrupt).
7398 *
7399 * 3) This also orders the write to mode from any reads to the page
7400 * tables done while the VCPU is running. Please see the comment
7401 * in kvm_flush_remote_tlbs.
6b7e2d09 7402 */
01b71917 7403 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7404
b95234c8
PB		 7405 /*
7406 * This handles the case where a posted interrupt was
7407 * notified with kvm_vcpu_kick.
7408 */
fa59cc00
LA		 7409 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7410 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7411
2fa6e1e1 7412 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7413 || need_resched() || signal_pending(current)) {
6b7e2d09 7414 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7415 smp_wmb();
6c142801
AK		 7416 local_irq_enable();
7417 preempt_enable();
01b71917 7418 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7419 r = 1;
d905c069 7420 goto cancel_injection;
6c142801
AK		 7421 }
7422
fc5b7f3b
DM		 7423 kvm_load_guest_xcr0(vcpu);
7424
c43203ca
PB		 7425 if (req_immediate_exit) {
7426 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7427 smp_send_reschedule(vcpu->cpu);
c43203ca 7428 }
d6185f20 7429
8b89fe1f 7430 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7431 if (lapic_timer_advance_ns)
7432 wait_lapic_expire(vcpu);
6edaa530 7433 guest_enter_irqoff();
b6c7a5dc 7434
42dbaa5a 7435 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7436 set_debugreg(0, 7);
7437 set_debugreg(vcpu->arch.eff_db[0], 0);
7438 set_debugreg(vcpu->arch.eff_db[1], 1);
7439 set_debugreg(vcpu->arch.eff_db[2], 2);
7440 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7441 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7442 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7443 }
b6c7a5dc 7444
851ba692 7445 kvm_x86_ops->run(vcpu);
b6c7a5dc 7446
c77fb5fe
PB		 7447 /*
7448 * Do this here before restoring debug registers on the host. And
7449 * since we do this before handling the vmexit, a DR access vmexit
7450 * can (a) read the correct value of the debug registers, (b) set
7451 * KVM_DEBUGREG_WONT_EXIT again.
7452 */
7453 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7454 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7455 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7456 kvm_update_dr0123(vcpu);
7457 kvm_update_dr6(vcpu);
7458 kvm_update_dr7(vcpu);
7459 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7460 }
7461
24f1e32c
FW		 7462 /*
7463 * If the guest has used debug registers, at least dr7
7464 * will be disabled while returning to the host.
7465 * If we don't have active breakpoints in the host, we don't
7466 * care about the messed up debug address registers. But if
7467 * we have some of them active, restore the old state.
7468 */
59d8eb53 7469 if (hw_breakpoint_active())
24f1e32c 7470 hw_breakpoint_restore();
42dbaa5a 7471
4ba76538 7472 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7473
6b7e2d09 7474 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7475 smp_wmb();
a547c6db 7476
fc5b7f3b
DM		 7477 kvm_put_guest_xcr0(vcpu);
7478
dd60d217 7479 kvm_before_interrupt(vcpu);
a547c6db 7480 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7481 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7482
7483 ++vcpu->stat.exits;
7484
f2485b3e 7485 guest_exit_irqoff();
b6c7a5dc 7486
f2485b3e 7487 local_irq_enable();
b6c7a5dc
HB		 7488 preempt_enable();
7489
f656ce01 7490 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7491
b6c7a5dc
HB		 7492 /*
7493 * Profile KVM exit RIPs:
7494 */
7495 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7496 unsigned long rip = kvm_rip_read(vcpu);
7497 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7498 }
7499
cc578287
ZA		 7500 if (unlikely(vcpu->arch.tsc_always_catchup))
7501 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7502
5cfb1d5a
MT		 7503 if (vcpu->arch.apic_attention)
7504 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7505
618232e2 7506 vcpu->arch.gpa_available = false;
851ba692 7507 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7508 return r;
7509
7510cancel_injection:
7511 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7512 if (unlikely(vcpu->arch.apic_attention))
7513 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7514out:
7515 return r;
7516}
b6c7a5dc 7517
362c698f
PB		 7518static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7519{
bf9f6ac8
FW		 7520 if (!kvm_arch_vcpu_runnable(vcpu) &&
7521 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7522 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7523 kvm_vcpu_block(vcpu);
7524 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7525
7526 if (kvm_x86_ops->post_block)
7527 kvm_x86_ops->post_block(vcpu);
7528
9c8fd1ba
PB		 7529 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7530 return 1;
7531 }
362c698f
PB		 7532
7533 kvm_apic_accept_events(vcpu);
7534 switch(vcpu->arch.mp_state) {
7535 case KVM_MP_STATE_HALTED:
7536 vcpu->arch.pv.pv_unhalted = false;
7537 vcpu->arch.mp_state =
7538 KVM_MP_STATE_RUNNABLE;
7539 case KVM_MP_STATE_RUNNABLE:
7540 vcpu->arch.apf.halted = false;
7541 break;
7542 case KVM_MP_STATE_INIT_RECEIVED:
7543 break;
7544 default:
7545 return -EINTR;
7546 break;
7547 }
7548 return 1;
7549}
09cec754 7550
5d9bc648
PB		 7551static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7552{
0ad3bed6
PB		 7553 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7554 kvm_x86_ops->check_nested_events(vcpu, false);
7555
5d9bc648
PB		 7556 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7557 !vcpu->arch.apf.halted);
7558}
7559
362c698f 7560static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7561{
7562 int r;
f656ce01 7563 struct kvm *kvm = vcpu->kvm;
d7690175 7564
f656ce01 7565 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7566
362c698f 7567 for (;;) {
58f800d5 7568 if (kvm_vcpu_running(vcpu)) {
851ba692 7569 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7570 } else {
362c698f 7571 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7572 }
7573
09cec754
GN		 7574 if (r <= 0)
7575 break;
7576
72875d8a 7577 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7578 if (kvm_cpu_has_pending_timer(vcpu))
7579 kvm_inject_pending_timer_irqs(vcpu);
7580
782d422b
MG		 7581 if (dm_request_for_irq_injection(vcpu) &&
7582 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7583 r = 0;
7584 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7585 ++vcpu->stat.request_irq_exits;
362c698f 7586 break;
09cec754 7587 }
af585b92
GN		 7588
7589 kvm_check_async_pf_completion(vcpu);
7590
09cec754
GN		 7591 if (signal_pending(current)) {
7592 r = -EINTR;
851ba692 7593 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7594 ++vcpu->stat.signal_exits;
362c698f 7595 break;
09cec754
GN		 7596 }
7597 if (need_resched()) {
f656ce01 7598 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7599 cond_resched();
f656ce01 7600 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7601 }
b6c7a5dc
HB		 7602 }
7603
f656ce01 7604 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7605
7606 return r;
7607}
7608
716d51ab
GN		 7609static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7610{
7611 int r;
7612 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7613 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7614 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7615 if (r != EMULATE_DONE)
7616 return 0;
7617 return 1;
7618}
7619
7620static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7621{
7622 BUG_ON(!vcpu->arch.pio.count);
7623
7624 return complete_emulated_io(vcpu);
7625}
7626
f78146b0
AK		 7627/*
7628 * Implements the following, as a state machine:
7629 *
7630 * read:
7631 * for each fragment
87da7e66
XG		 7632 * for each mmio piece in the fragment
7633 * write gpa, len
7634 * exit
7635 * copy data
f78146b0
AK		 7636 * execute insn
7637 *
7638 * write:
7639 * for each fragment
87da7e66
XG		 7640 * for each mmio piece in the fragment
7641 * write gpa, len
7642 * copy data
7643 * exit
f78146b0 7644 */
716d51ab 7645static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7646{
7647 struct kvm_run *run = vcpu->run;
f78146b0 7648 struct kvm_mmio_fragment *frag;
87da7e66 7649 unsigned len;
5287f194 7650
716d51ab 7651 BUG_ON(!vcpu->mmio_needed);
5287f194 7652
716d51ab 7653 /* Complete previous fragment */
87da7e66
XG		 7654 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7655 len = min(8u, frag->len);
716d51ab 7656 if (!vcpu->mmio_is_write)
87da7e66
XG		 7657 memcpy(frag->data, run->mmio.data, len);
7658
7659 if (frag->len <= 8) {
7660 /* Switch to the next fragment. */
7661 frag++;
7662 vcpu->mmio_cur_fragment++;
7663 } else {
7664 /* Go forward to the next mmio piece. */
7665 frag->data += len;
7666 frag->gpa += len;
7667 frag->len -= len;
7668 }
7669
a08d3b3b 7670 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7671 vcpu->mmio_needed = 0;
0912c977
PB		 7672
7673 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7674 if (vcpu->mmio_is_write)
716d51ab
GN		 7675 return 1;
7676 vcpu->mmio_read_completed = 1;
7677 return complete_emulated_io(vcpu);
7678 }
87da7e66 7679
716d51ab
GN		 7680 run->exit_reason = KVM_EXIT_MMIO;
7681 run->mmio.phys_addr = frag->gpa;
7682 if (vcpu->mmio_is_write)
87da7e66
XG		 7683 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7684 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7685 run->mmio.is_write = vcpu->mmio_is_write;
7686 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7687 return 0;
5287f194
AK		 7688}
7689
b6c7a5dc
HB		 7690int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7691{
7692 int r;
b6c7a5dc 7693
accb757d 7694 vcpu_load(vcpu);
20b7035c 7695 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7696 kvm_load_guest_fpu(vcpu);
7697
a4535290 7698 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7699 if (kvm_run->immediate_exit) {
7700 r = -EINTR;
7701 goto out;
7702 }
b6c7a5dc 7703 kvm_vcpu_block(vcpu);
66450a21 7704 kvm_apic_accept_events(vcpu);
72875d8a 7705 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7706 r = -EAGAIN;
a0595000
JS		 7707 if (signal_pending(current)) {
7708 r = -EINTR;
7709 vcpu->run->exit_reason = KVM_EXIT_INTR;
7710 ++vcpu->stat.signal_exits;
7711 }
ac9f6dc0 7712 goto out;
b6c7a5dc
HB		 7713 }
7714
01643c51
KH		 7715 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7716 r = -EINVAL;
7717 goto out;
7718 }
7719
7720 if (vcpu->run->kvm_dirty_regs) {
7721 r = sync_regs(vcpu);
7722 if (r != 0)
7723 goto out;
7724 }
7725
b6c7a5dc 7726 /* re-sync apic's tpr */
35754c98 7727 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7728 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7729 r = -EINVAL;
7730 goto out;
7731 }
7732 }
b6c7a5dc 7733
716d51ab
GN		 7734 if (unlikely(vcpu->arch.complete_userspace_io)) {
7735 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7736 vcpu->arch.complete_userspace_io = NULL;
7737 r = cui(vcpu);
7738 if (r <= 0)
5663d8f9 7739 goto out;
716d51ab
GN		 7740 } else
7741 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7742
460df4c1
PB		 7743 if (kvm_run->immediate_exit)
7744 r = -EINTR;
7745 else
7746 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7747
7748out:
5663d8f9 7749 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7750 if (vcpu->run->kvm_valid_regs)
7751 store_regs(vcpu);
f1d86e46 7752 post_kvm_run_save(vcpu);
20b7035c 7753 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7754
accb757d 7755 vcpu_put(vcpu);
b6c7a5dc
HB		 7756 return r;
7757}
7758
01643c51 7759static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7760{
7ae441ea
GN		 7761 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7762 /*
7763 * We are here if userspace calls get_regs() in the middle of
7764 * instruction emulation. Registers state needs to be copied
4a969980 7765 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7766 * that usually, but some bad designed PV devices (vmware
7767 * backdoor interface) need this to work
7768 */
dd856efa 7769 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7770 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7771 }
5fdbf976
MT		 7772 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7773 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7774 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7775 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7776 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7777 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7778 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7779 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7780#ifdef CONFIG_X86_64
5fdbf976
MT		 7781 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7782 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7783 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7784 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7785 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7786 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7787 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7788 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7789#endif
7790
5fdbf976 7791 regs->rip = kvm_rip_read(vcpu);
91586a3b 7792 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7793}
b6c7a5dc 7794
01643c51
KH		 7795int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7796{
7797 vcpu_load(vcpu);
7798 __get_regs(vcpu, regs);
1fc9b76b 7799 vcpu_put(vcpu);
b6c7a5dc
HB		 7800 return 0;
7801}
7802
01643c51 7803static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7804{
7ae441ea
GN		 7805 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7806 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7807
5fdbf976
MT		 7808 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7809 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7810 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7811 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7812 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7813 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7814 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7815 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7816#ifdef CONFIG_X86_64
5fdbf976
MT		 7817 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7818 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7819 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7820 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7821 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7822 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7823 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7824 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7825#endif
7826
5fdbf976 7827 kvm_rip_write(vcpu, regs->rip);
d73235d1 7828 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7829
b4f14abd
JK		 7830 vcpu->arch.exception.pending = false;
7831
3842d135 7832 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7833}
3842d135 7834
01643c51
KH		 7835int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7836{
7837 vcpu_load(vcpu);
7838 __set_regs(vcpu, regs);
875656fe 7839 vcpu_put(vcpu);
b6c7a5dc
HB		 7840 return 0;
7841}
7842
b6c7a5dc
HB		 7843void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7844{
7845 struct kvm_segment cs;
7846
3e6e0aab 7847 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7848 *db = cs.db;
7849 *l = cs.l;
7850}
7851EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7852
01643c51 7853static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7854{
89a27f4d 7855 struct desc_ptr dt;
b6c7a5dc 7856
3e6e0aab
GT		 7857 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7858 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7859 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7860 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7861 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7862 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7863
3e6e0aab
GT		 7864 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7865 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7866
7867 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7868 sregs->idt.limit = dt.size;
7869 sregs->idt.base = dt.address;
b6c7a5dc 7870 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7871 sregs->gdt.limit = dt.size;
7872 sregs->gdt.base = dt.address;
b6c7a5dc 7873
4d4ec087 7874 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7875 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7876 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7877 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7878 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7879 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7880 sregs->apic_base = kvm_get_apic_base(vcpu);
7881
923c61bb 7882 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7883
04140b41 7884 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7885 set_bit(vcpu->arch.interrupt.nr,
7886 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7887}
16d7a191 7888
01643c51
KH		 7889int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7890 struct kvm_sregs *sregs)
7891{
7892 vcpu_load(vcpu);
7893 __get_sregs(vcpu, sregs);
bcdec41c 7894 vcpu_put(vcpu);
b6c7a5dc
HB		 7895 return 0;
7896}
7897
62d9f0db
MT		 7898int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7899 struct kvm_mp_state *mp_state)
7900{
fd232561
CD		 7901 vcpu_load(vcpu);
7902
66450a21 7903 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7904 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7905 vcpu->arch.pv.pv_unhalted)
7906 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7907 else
7908 mp_state->mp_state = vcpu->arch.mp_state;
7909
fd232561 7910 vcpu_put(vcpu);
62d9f0db
MT		 7911 return 0;
7912}
7913
7914int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7915 struct kvm_mp_state *mp_state)
7916{
e83dff5e
CD		 7917 int ret = -EINVAL;
7918
7919 vcpu_load(vcpu);
7920
bce87cce 7921 if (!lapic_in_kernel(vcpu) &&
66450a21 7922 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7923 goto out;
66450a21 7924
28bf2888
DH		 7925 /* INITs are latched while in SMM */
7926 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7927 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7928 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7929 goto out;
28bf2888 7930
66450a21
JK		 7931 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7932 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7933 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7934 } else
7935 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7936 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7937
7938 ret = 0;
7939out:
7940 vcpu_put(vcpu);
7941 return ret;
62d9f0db
MT		 7942}
7943
7f3d35fd
KW		 7944int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7945 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7946{
9d74191a 7947 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7948 int ret;
e01c2426 7949
8ec4722d 7950 init_emulate_ctxt(vcpu);
c697518a 7951
7f3d35fd 7952 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7953 has_error_code, error_code);
c697518a 7954
c697518a 7955 if (ret)
19d04437 7956 return EMULATE_FAIL;
37817f29 7957
9d74191a
TY		 7958 kvm_rip_write(vcpu, ctxt->eip);
7959 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7960 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7961 return EMULATE_DONE;
37817f29
IE		 7962}
7963EXPORT_SYMBOL_GPL(kvm_task_switch);
7964
3140c156 7965static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 7966{
37b95951 7967 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7968 /*
7969 * When EFER.LME and CR0.PG are set, the processor is in
7970 * 64-bit mode (though maybe in a 32-bit code segment).
7971 * CR4.PAE and EFER.LMA must be set.
7972 */
37b95951 7973 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7974 || !(sregs->efer & EFER_LMA))
7975 return -EINVAL;
7976 } else {
7977 /*
7978 * Not in 64-bit mode: EFER.LMA is clear and the code
7979 * segment cannot be 64-bit.
7980 */
7981 if (sregs->efer & EFER_LMA || sregs->cs.l)
7982 return -EINVAL;
7983 }
7984
7985 return 0;
7986}
7987
01643c51 7988static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7989{
58cb628d 7990 struct msr_data apic_base_msr;
b6c7a5dc 7991 int mmu_reset_needed = 0;
63f42e02 7992 int pending_vec, max_bits, idx;
89a27f4d 7993 struct desc_ptr dt;
b4ef9d4e
CD		 7994 int ret = -EINVAL;
7995
d6321d49
RK		 7996 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7997 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7998 goto out;
6d1068b3 7999
f2981033 8000 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8001 goto out;
f2981033 8002
d3802286
JM		 8003 apic_base_msr.data = sregs->apic_base;
8004 apic_base_msr.host_initiated = true;
8005 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8006 goto out;
6d1068b3 8007
89a27f4d
GN		 8008 dt.size = sregs->idt.limit;
8009 dt.address = sregs->idt.base;
b6c7a5dc 8010 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8011 dt.size = sregs->gdt.limit;
8012 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8013 kvm_x86_ops->set_gdt(vcpu, &dt);
8014
ad312c7c 8015 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8016 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8017 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8018 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8019
2d3ad1f4 8020 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8021
f6801dff 8022 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8023 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8024
4d4ec087 8025 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8026 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8027 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8028
fc78f519 8029 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 8030 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 8031 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 8032 kvm_update_cpuid(vcpu);
63f42e02
XG		 8033
8034 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 8035 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 8036 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8037 mmu_reset_needed = 1;
8038 }
63f42e02 8039 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8040
8041 if (mmu_reset_needed)
8042 kvm_mmu_reset_context(vcpu);
8043
a50abc3b 8044 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8045 pending_vec = find_first_bit(
8046 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8047 if (pending_vec < max_bits) {
66fd3f7f 8048 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8049 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8050 }
8051
3e6e0aab
GT		 8052 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8053 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8054 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8055 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8056 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8057 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8058
3e6e0aab
GT		 8059 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8060 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8061
5f0269f5
ME		 8062 update_cr8_intercept(vcpu);
8063
9c3e4aab 8064 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8065 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8066 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8067 !is_protmode(vcpu))
9c3e4aab
MT		 8068 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8069
3842d135
AK		 8070 kvm_make_request(KVM_REQ_EVENT, vcpu);
8071
b4ef9d4e
CD		 8072 ret = 0;
8073out:
01643c51
KH		 8074 return ret;
8075}
8076
8077int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8078 struct kvm_sregs *sregs)
8079{
8080 int ret;
8081
8082 vcpu_load(vcpu);
8083 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8084 vcpu_put(vcpu);
8085 return ret;
b6c7a5dc
HB		 8086}
8087
d0bfb940
JK		 8088int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8089 struct kvm_guest_debug *dbg)
b6c7a5dc 8090{
355be0b9 8091 unsigned long rflags;
ae675ef0 8092 int i, r;
b6c7a5dc 8093
66b56562
CD		 8094 vcpu_load(vcpu);
8095
4f926bf2
JK		 8096 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8097 r = -EBUSY;
8098 if (vcpu->arch.exception.pending)
2122ff5e 8099 goto out;
4f926bf2
JK		 8100 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8101 kvm_queue_exception(vcpu, DB_VECTOR);
8102 else
8103 kvm_queue_exception(vcpu, BP_VECTOR);
8104 }
8105
91586a3b
JK		 8106 /*
8107 * Read rflags as long as potentially injected trace flags are still
8108 * filtered out.
8109 */
8110 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8111
8112 vcpu->guest_debug = dbg->control;
8113 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8114 vcpu->guest_debug = 0;
8115
8116 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8117 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8118 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8119 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8120 } else {
8121 for (i = 0; i < KVM_NR_DB_REGS; i++)
8122 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8123 }
c8639010 8124 kvm_update_dr7(vcpu);
ae675ef0 8125
f92653ee
JK		 8126 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8127 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8128 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8129
91586a3b
JK		 8130 /*
8131 * Trigger an rflags update that will inject or remove the trace
8132 * flags.
8133 */
8134 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8135
a96036b8 8136 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8137
4f926bf2 8138 r = 0;
d0bfb940 8139
2122ff5e 8140out:
66b56562 8141 vcpu_put(vcpu);
b6c7a5dc
HB		 8142 return r;
8143}
8144
8b006791
ZX		 8145/*
8146 * Translate a guest virtual address to a guest physical address.
8147 */
8148int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8149 struct kvm_translation *tr)
8150{
8151 unsigned long vaddr = tr->linear_address;
8152 gpa_t gpa;
f656ce01 8153 int idx;
8b006791 8154
1da5b61d
CD		 8155 vcpu_load(vcpu);
8156
f656ce01 8157 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8158 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8159 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8160 tr->physical_address = gpa;
8161 tr->valid = gpa != UNMAPPED_GVA;
8162 tr->writeable = 1;
8163 tr->usermode = 0;
8b006791 8164
1da5b61d 8165 vcpu_put(vcpu);
8b006791
ZX		 8166 return 0;
8167}
8168
d0752060
HB		 8169int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8170{
1393123e 8171 struct fxregs_state *fxsave;
d0752060 8172
1393123e 8173 vcpu_load(vcpu);
d0752060 8174
1393123e 8175 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8176 memcpy(fpu->fpr, fxsave->st_space, 128);
8177 fpu->fcw = fxsave->cwd;
8178 fpu->fsw = fxsave->swd;
8179 fpu->ftwx = fxsave->twd;
8180 fpu->last_opcode = fxsave->fop;
8181 fpu->last_ip = fxsave->rip;
8182 fpu->last_dp = fxsave->rdp;
8183 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8184
1393123e 8185 vcpu_put(vcpu);
d0752060
HB		 8186 return 0;
8187}
8188
8189int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8190{
6a96bc7f
CD		 8191 struct fxregs_state *fxsave;
8192
8193 vcpu_load(vcpu);
8194
8195 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8196
d0752060
HB		 8197 memcpy(fxsave->st_space, fpu->fpr, 128);
8198 fxsave->cwd = fpu->fcw;
8199 fxsave->swd = fpu->fsw;
8200 fxsave->twd = fpu->ftwx;
8201 fxsave->fop = fpu->last_opcode;
8202 fxsave->rip = fpu->last_ip;
8203 fxsave->rdp = fpu->last_dp;
8204 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8205
6a96bc7f 8206 vcpu_put(vcpu);
d0752060
HB		 8207 return 0;
8208}
8209
01643c51
KH		 8210static void store_regs(struct kvm_vcpu *vcpu)
8211{
8212 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8213
8214 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8215 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8216
8217 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8218 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8219
8220 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8221 kvm_vcpu_ioctl_x86_get_vcpu_events(
8222 vcpu, &vcpu->run->s.regs.events);
8223}
8224
8225static int sync_regs(struct kvm_vcpu *vcpu)
8226{
8227 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8228 return -EINVAL;
8229
8230 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8231 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8232 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8233 }
8234 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8235 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8236 return -EINVAL;
8237 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8238 }
8239 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8240 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8241 vcpu, &vcpu->run->s.regs.events))
8242 return -EINVAL;
8243 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8244 }
8245
8246 return 0;
8247}
8248
0ee6a517 8249static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8250{
bf935b0b 8251 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8252 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8253 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8254 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8255
2acf923e
DC		 8256 /*
8257 * Ensure guest xcr0 is valid for loading
8258 */
d91cab78 8259 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8260
ad312c7c 8261 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8262}
d0752060 8263
f775b13e 8264/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8265void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8266{
f775b13e
RR		 8267 preempt_disable();
8268 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8269 /* PKRU is separately restored in kvm_x86_ops->run. */
8270 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8271 ~XFEATURE_MASK_PKRU);
f775b13e 8272 preempt_enable();
0c04851c 8273 trace_kvm_fpu(1);
d0752060 8274}
d0752060 8275
f775b13e 8276/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8277void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8278{
f775b13e 8279 preempt_disable();
4f836347 8280 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8281 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8282 preempt_enable();
f096ed85 8283 ++vcpu->stat.fpu_reload;
0c04851c 8284 trace_kvm_fpu(0);
d0752060 8285}
e9b11c17
ZX		 8286
8287void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8288{
bd768e14
IY		 8289 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8290
12f9a48f 8291 kvmclock_reset(vcpu);
7f1ea208 8292
e9b11c17 8293 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8294 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8295}
8296
8297struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8298 unsigned int id)
8299{
c447e76b
LL		 8300 struct kvm_vcpu *vcpu;
8301
b0c39dc6 8302 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8303 printk_once(KERN_WARNING
8304 "kvm: SMP vm created on host with unstable TSC; "
8305 "guest TSC will not be reliable\n");
c447e76b
LL		 8306
8307 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8308
c447e76b 8309 return vcpu;
26e5215f 8310}
e9b11c17 8311
26e5215f
AK		 8312int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8313{
19efffa2 8314 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8315 vcpu_load(vcpu);
d28bc9dd 8316 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8317 kvm_mmu_setup(vcpu);
e9b11c17 8318 vcpu_put(vcpu);
ec7660cc 8319 return 0;
e9b11c17
ZX		 8320}
8321
31928aa5 8322void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8323{
8fe8ab46 8324 struct msr_data msr;
332967a3 8325 struct kvm *kvm = vcpu->kvm;
42897d86 8326
d3457c87
RK		 8327 kvm_hv_vcpu_postcreate(vcpu);
8328
ec7660cc 8329 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8330 return;
ec7660cc 8331 vcpu_load(vcpu);
8fe8ab46
WA		 8332 msr.data = 0x0;
8333 msr.index = MSR_IA32_TSC;
8334 msr.host_initiated = true;
8335 kvm_write_tsc(vcpu, &msr);
42897d86 8336 vcpu_put(vcpu);
ec7660cc 8337 mutex_unlock(&vcpu->mutex);
42897d86 8338
630994b3
MT		 8339 if (!kvmclock_periodic_sync)
8340 return;
8341
332967a3
AJ		 8342 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8343 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8344}
8345
d40ccc62 8346void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8347{
344d9588
GN		 8348 vcpu->arch.apf.msr_val = 0;
8349
ec7660cc 8350 vcpu_load(vcpu);
e9b11c17
ZX		 8351 kvm_mmu_unload(vcpu);
8352 vcpu_put(vcpu);
8353
8354 kvm_x86_ops->vcpu_free(vcpu);
8355}
8356
d28bc9dd 8357void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8358{
b7e31be3
RK		 8359 kvm_lapic_reset(vcpu, init_event);
8360
e69fab5d
PB		 8361 vcpu->arch.hflags = 0;
8362
c43203ca 8363 vcpu->arch.smi_pending = 0;
52797bf9 8364 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8365 atomic_set(&vcpu->arch.nmi_queued, 0);
8366 vcpu->arch.nmi_pending = 0;
448fa4a9 8367 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8368 kvm_clear_interrupt_queue(vcpu);
8369 kvm_clear_exception_queue(vcpu);
664f8e26 8370 vcpu->arch.exception.pending = false;
448fa4a9 8371
42dbaa5a 8372 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8373 kvm_update_dr0123(vcpu);
6f43ed01 8374 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8375 kvm_update_dr6(vcpu);
42dbaa5a 8376 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8377 kvm_update_dr7(vcpu);
42dbaa5a 8378
1119022c
NA		 8379 vcpu->arch.cr2 = 0;
8380
3842d135 8381 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8382 vcpu->arch.apf.msr_val = 0;
c9aaa895 8383 vcpu->arch.st.msr_val = 0;
3842d135 8384
12f9a48f
GC		 8385 kvmclock_reset(vcpu);
8386
af585b92
GN		 8387 kvm_clear_async_pf_completion_queue(vcpu);
8388 kvm_async_pf_hash_reset(vcpu);
8389 vcpu->arch.apf.halted = false;
3842d135 8390
a554d207
WL		 8391 if (kvm_mpx_supported()) {
8392 void *mpx_state_buffer;
8393
8394 /*
8395 * To avoid have the INIT path from kvm_apic_has_events() that be
8396 * called with loaded FPU and does not let userspace fix the state.
8397 */
f775b13e
RR		 8398 if (init_event)
8399 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8400 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8401 XFEATURE_MASK_BNDREGS);
8402 if (mpx_state_buffer)
8403 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8404 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8405 XFEATURE_MASK_BNDCSR);
8406 if (mpx_state_buffer)
8407 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8408 if (init_event)
8409 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8410 }
8411
64d60670 8412 if (!init_event) {
d28bc9dd 8413 kvm_pmu_reset(vcpu);
64d60670 8414 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8415
8416 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8417 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8418
8419 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8420 }
f5132b01 8421
66f7b72e
JS		 8422 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8423 vcpu->arch.regs_avail = ~0;
8424 vcpu->arch.regs_dirty = ~0;
8425
a554d207
WL		 8426 vcpu->arch.ia32_xss = 0;
8427
d28bc9dd 8428 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8429}
8430
2b4a273b 8431void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8432{
8433 struct kvm_segment cs;
8434
8435 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8436 cs.selector = vector << 8;
8437 cs.base = vector << 12;
8438 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8439 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8440}
8441
13a34e06 8442int kvm_arch_hardware_enable(void)
e9b11c17 8443{
ca84d1a2
ZA		 8444 struct kvm *kvm;
8445 struct kvm_vcpu *vcpu;
8446 int i;
0dd6a6ed
ZA		 8447 int ret;
8448 u64 local_tsc;
8449 u64 max_tsc = 0;
8450 bool stable, backwards_tsc = false;
18863bdd
AK		 8451
8452 kvm_shared_msr_cpu_online();
13a34e06 8453 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8454 if (ret != 0)
8455 return ret;
8456
4ea1636b 8457 local_tsc = rdtsc();
b0c39dc6 8458 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8459 list_for_each_entry(kvm, &vm_list, vm_list) {
8460 kvm_for_each_vcpu(i, vcpu, kvm) {
8461 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8462 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8463 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8464 backwards_tsc = true;
8465 if (vcpu->arch.last_host_tsc > max_tsc)
8466 max_tsc = vcpu->arch.last_host_tsc;
8467 }
8468 }
8469 }
8470
8471 /*
8472 * Sometimes, even reliable TSCs go backwards. This happens on
8473 * platforms that reset TSC during suspend or hibernate actions, but
8474 * maintain synchronization. We must compensate. Fortunately, we can
8475 * detect that condition here, which happens early in CPU bringup,
8476 * before any KVM threads can be running. Unfortunately, we can't
8477 * bring the TSCs fully up to date with real time, as we aren't yet far
8478 * enough into CPU bringup that we know how much real time has actually
108b249c 8479 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8480 * variables that haven't been updated yet.
8481 *
8482 * So we simply find the maximum observed TSC above, then record the
8483 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8484 * the adjustment will be applied. Note that we accumulate
8485 * adjustments, in case multiple suspend cycles happen before some VCPU
8486 * gets a chance to run again. In the event that no KVM threads get a
8487 * chance to run, we will miss the entire elapsed period, as we'll have
8488 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8489 * loose cycle time. This isn't too big a deal, since the loss will be
8490 * uniform across all VCPUs (not to mention the scenario is extremely
8491 * unlikely). It is possible that a second hibernate recovery happens
8492 * much faster than a first, causing the observed TSC here to be
8493 * smaller; this would require additional padding adjustment, which is
8494 * why we set last_host_tsc to the local tsc observed here.
8495 *
8496 * N.B. - this code below runs only on platforms with reliable TSC,
8497 * as that is the only way backwards_tsc is set above. Also note
8498 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8499 * have the same delta_cyc adjustment applied if backwards_tsc
8500 * is detected. Note further, this adjustment is only done once,
8501 * as we reset last_host_tsc on all VCPUs to stop this from being
8502 * called multiple times (one for each physical CPU bringup).
8503 *
4a969980 8504 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8505 * will be compensated by the logic in vcpu_load, which sets the TSC to
8506 * catchup mode. This will catchup all VCPUs to real time, but cannot
8507 * guarantee that they stay in perfect synchronization.
8508 */
8509 if (backwards_tsc) {
8510 u64 delta_cyc = max_tsc - local_tsc;
8511 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8512 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8513 kvm_for_each_vcpu(i, vcpu, kvm) {
8514 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8515 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8516 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8517 }
8518
8519 /*
8520 * We have to disable TSC offset matching.. if you were
8521 * booting a VM while issuing an S4 host suspend....
8522 * you may have some problem. Solving this issue is
8523 * left as an exercise to the reader.
8524 */
8525 kvm->arch.last_tsc_nsec = 0;
8526 kvm->arch.last_tsc_write = 0;
8527 }
8528
8529 }
8530 return 0;
e9b11c17
ZX		 8531}
8532
13a34e06 8533void kvm_arch_hardware_disable(void)
e9b11c17 8534{
13a34e06
RK		 8535 kvm_x86_ops->hardware_disable();
8536 drop_user_return_notifiers();
e9b11c17
ZX		 8537}
8538
8539int kvm_arch_hardware_setup(void)
8540{
9e9c3fe4
NA		 8541 int r;
8542
8543 r = kvm_x86_ops->hardware_setup();
8544 if (r != 0)
8545 return r;
8546
35181e86
HZ		 8547 if (kvm_has_tsc_control) {
8548 /*
8549 * Make sure the user can only configure tsc_khz values that
8550 * fit into a signed integer.
8551 * A min value is not calculated needed because it will always
8552 * be 1 on all machines.
8553 */
8554 u64 max = min(0x7fffffffULL,
8555 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8556 kvm_max_guest_tsc_khz = max;
8557
ad721883 8558 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8559 }
ad721883 8560
9e9c3fe4
NA		 8561 kvm_init_msr_list();
8562 return 0;
e9b11c17
ZX		 8563}
8564
8565void kvm_arch_hardware_unsetup(void)
8566{
8567 kvm_x86_ops->hardware_unsetup();
8568}
8569
8570void kvm_arch_check_processor_compat(void *rtn)
8571{
8572 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8573}
8574
8575bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8576{
8577 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8578}
8579EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8580
8581bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8582{
8583 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8584}
8585
54e9818f 8586struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8587EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8588
e9b11c17
ZX		 8589int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8590{
8591 struct page *page;
e9b11c17
ZX		 8592 int r;
8593
b2a05fef 8594 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8595 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8596 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8597 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8598 else
a4535290 8599 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8600
8601 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8602 if (!page) {
8603 r = -ENOMEM;
8604 goto fail;
8605 }
ad312c7c 8606 vcpu->arch.pio_data = page_address(page);
e9b11c17 8607
cc578287 8608 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8609
e9b11c17
ZX		 8610 r = kvm_mmu_create(vcpu);
8611 if (r < 0)
8612 goto fail_free_pio_data;
8613
26de7988 8614 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8615 r = kvm_create_lapic(vcpu);
8616 if (r < 0)
8617 goto fail_mmu_destroy;
54e9818f
GN		 8618 } else
8619 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8620
890ca9ae
HY		 8621 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8622 GFP_KERNEL);
8623 if (!vcpu->arch.mce_banks) {
8624 r = -ENOMEM;
443c39bc 8625 goto fail_free_lapic;
890ca9ae
HY		 8626 }
8627 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8628
f1797359
WY		 8629 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8630 r = -ENOMEM;
f5f48ee1 8631 goto fail_free_mce_banks;
f1797359 8632 }
f5f48ee1 8633
0ee6a517 8634 fx_init(vcpu);
66f7b72e 8635
4344ee98 8636 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8637
5a4f55cd
EK		 8638 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8639
74545705
RK		 8640 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8641
af585b92 8642 kvm_async_pf_hash_reset(vcpu);
f5132b01 8643 kvm_pmu_init(vcpu);
af585b92 8644
1c1a9ce9 8645 vcpu->arch.pending_external_vector = -1;
de63ad4c 8646 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8647
5c919412
AS		 8648 kvm_hv_vcpu_init(vcpu);
8649
e9b11c17 8650 return 0;
0ee6a517 8651
f5f48ee1
SY		 8652fail_free_mce_banks:
8653 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8654fail_free_lapic:
8655 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8656fail_mmu_destroy:
8657 kvm_mmu_destroy(vcpu);
8658fail_free_pio_data:
ad312c7c 8659 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8660fail:
8661 return r;
8662}
8663
8664void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8665{
f656ce01
MT		 8666 int idx;
8667
1f4b34f8 8668 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8669 kvm_pmu_destroy(vcpu);
36cb93fd 8670 kfree(vcpu->arch.mce_banks);
e9b11c17 8671 kvm_free_lapic(vcpu);
f656ce01 8672 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8673 kvm_mmu_destroy(vcpu);
f656ce01 8674 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8675 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8676 if (!lapic_in_kernel(vcpu))
54e9818f 8677 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8678}
d19a9cd2 8679
e790d9ef
RK		 8680void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8681{
ae97a3b8 8682 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8683}
8684
e08b9637 8685int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8686{
e08b9637
CO		 8687 if (type)
8688 return -EINVAL;
8689
6ef768fa 8690 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8691 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8692 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8693 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8694 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8695
5550af4d
SY		 8696 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8697 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8698 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8699 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8700 &kvm->arch.irq_sources_bitmap);
5550af4d 8701
038f8c11 8702 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8703 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8704 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8705
108b249c 8706 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8707 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8708
7e44e449 8709 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8710 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8711
cbc0236a 8712 kvm_hv_init_vm(kvm);
0eb05bf2 8713 kvm_page_track_init(kvm);
13d268ca 8714 kvm_mmu_init_vm(kvm);
0eb05bf2 8715
03543133
SS		 8716 if (kvm_x86_ops->vm_init)
8717 return kvm_x86_ops->vm_init(kvm);
8718
d89f5eff 8719 return 0;
d19a9cd2
ZX		 8720}
8721
8722static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8723{
ec7660cc 8724 vcpu_load(vcpu);
d19a9cd2
ZX		 8725 kvm_mmu_unload(vcpu);
8726 vcpu_put(vcpu);
8727}
8728
8729static void kvm_free_vcpus(struct kvm *kvm)
8730{
8731 unsigned int i;
988a2cae 8732 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8733
8734 /*
8735 * Unpin any mmu pages first.
8736 */
af585b92
GN		 8737 kvm_for_each_vcpu(i, vcpu, kvm) {
8738 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8739 kvm_unload_vcpu_mmu(vcpu);
af585b92 8740 }
988a2cae
GN		 8741 kvm_for_each_vcpu(i, vcpu, kvm)
8742 kvm_arch_vcpu_free(vcpu);
8743
8744 mutex_lock(&kvm->lock);
8745 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8746 kvm->vcpus[i] = NULL;
d19a9cd2 8747
988a2cae
GN		 8748 atomic_set(&kvm->online_vcpus, 0);
8749 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8750}
8751
ad8ba2cd
SY		 8752void kvm_arch_sync_events(struct kvm *kvm)
8753{
332967a3 8754 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8755 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8756 kvm_free_pit(kvm);
ad8ba2cd
SY		 8757}
8758
1d8007bd 8759int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8760{
8761 int i, r;
25188b99 8762 unsigned long hva;
f0d648bd
PB		 8763 struct kvm_memslots *slots = kvm_memslots(kvm);
8764 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8765
8766 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8767 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8768 return -EINVAL;
9da0e4d5 8769
f0d648bd
PB		 8770 slot = id_to_memslot(slots, id);
8771 if (size) {
b21629da 8772 if (slot->npages)
f0d648bd
PB		 8773 return -EEXIST;
8774
8775 /*
8776 * MAP_SHARED to prevent internal slot pages from being moved
8777 * by fork()/COW.
8778 */
8779 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8780 MAP_SHARED | MAP_ANONYMOUS, 0);
8781 if (IS_ERR((void *)hva))
8782 return PTR_ERR((void *)hva);
8783 } else {
8784 if (!slot->npages)
8785 return 0;
8786
8787 hva = 0;
8788 }
8789
8790 old = *slot;
9da0e4d5 8791 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8792 struct kvm_userspace_memory_region m;
9da0e4d5 8793
1d8007bd
PB		 8794 m.slot = id | (i << 16);
8795 m.flags = 0;
8796 m.guest_phys_addr = gpa;
f0d648bd 8797 m.userspace_addr = hva;
1d8007bd 8798 m.memory_size = size;
9da0e4d5
PB		 8799 r = __kvm_set_memory_region(kvm, &m);
8800 if (r < 0)
8801 return r;
8802 }
8803
103c763c
EB		 8804 if (!size)
8805 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8806
9da0e4d5
PB		 8807 return 0;
8808}
8809EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8810
1d8007bd 8811int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8812{
8813 int r;
8814
8815 mutex_lock(&kvm->slots_lock);
1d8007bd 8816 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8817 mutex_unlock(&kvm->slots_lock);
8818
8819 return r;
8820}
8821EXPORT_SYMBOL_GPL(x86_set_memory_region);
8822
d19a9cd2
ZX		 8823void kvm_arch_destroy_vm(struct kvm *kvm)
8824{
27469d29
AH		 8825 if (current->mm == kvm->mm) {
8826 /*
8827 * Free memory regions allocated on behalf of userspace,
8828 * unless the the memory map has changed due to process exit
8829 * or fd copying.
8830 */
1d8007bd
PB		 8831 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8832 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8833 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8834 }
03543133
SS		 8835 if (kvm_x86_ops->vm_destroy)
8836 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8837 kvm_pic_destroy(kvm);
8838 kvm_ioapic_destroy(kvm);
d19a9cd2 8839 kvm_free_vcpus(kvm);
af1bae54 8840 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8841 kvm_mmu_uninit_vm(kvm);
2beb6dad 8842 kvm_page_track_cleanup(kvm);
cbc0236a 8843 kvm_hv_destroy_vm(kvm);
d19a9cd2 8844}
0de10343 8845
5587027c 8846void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8847 struct kvm_memory_slot *dont)
8848{
8849 int i;
8850
d89cc617
TY		 8851 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8852 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8853 kvfree(free->arch.rmap[i]);
d89cc617 8854 free->arch.rmap[i] = NULL;
77d11309 8855 }
d89cc617
TY		 8856 if (i == 0)
8857 continue;
8858
8859 if (!dont || free->arch.lpage_info[i - 1] !=
8860 dont->arch.lpage_info[i - 1]) {
548ef284 8861 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8862 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8863 }
8864 }
21ebbeda
XG		 8865
8866 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8867}
8868
5587027c
AK		 8869int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8870 unsigned long npages)
db3fe4eb
TY		 8871{
8872 int i;
8873
d89cc617 8874 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8875 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8876 unsigned long ugfn;
8877 int lpages;
d89cc617 8878 int level = i + 1;
db3fe4eb
TY		 8879
8880 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8881 slot->base_gfn, level) + 1;
8882
d89cc617 8883 slot->arch.rmap[i] =
a7c3e901 8884 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8885 if (!slot->arch.rmap[i])
77d11309 8886 goto out_free;
d89cc617
TY		 8887 if (i == 0)
8888 continue;
77d11309 8889
a7c3e901 8890 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8891 if (!linfo)
db3fe4eb
TY		 8892 goto out_free;
8893
92f94f1e
XG		 8894 slot->arch.lpage_info[i - 1] = linfo;
8895
db3fe4eb 8896 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8897 linfo[0].disallow_lpage = 1;
db3fe4eb 8898 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8899 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8900 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8901 /*
8902 * If the gfn and userspace address are not aligned wrt each
8903 * other, or if explicitly asked to, disable large page
8904 * support for this slot
8905 */
8906 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8907 !kvm_largepages_enabled()) {
8908 unsigned long j;
8909
8910 for (j = 0; j < lpages; ++j)
92f94f1e 8911 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8912 }
8913 }
8914
21ebbeda
XG		 8915 if (kvm_page_track_create_memslot(slot, npages))
8916 goto out_free;
8917
db3fe4eb
TY		 8918 return 0;
8919
8920out_free:
d89cc617 8921 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8922 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8923 slot->arch.rmap[i] = NULL;
8924 if (i == 0)
8925 continue;
8926
548ef284 8927 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8928 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8929 }
8930 return -ENOMEM;
8931}
8932
15f46015 8933void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8934{
e6dff7d1
TY		 8935 /*
8936 * memslots->generation has been incremented.
8937 * mmio generation may have reached its maximum value.
8938 */
54bf36aa 8939 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8940}
8941
f7784b8e
MT		 8942int kvm_arch_prepare_memory_region(struct kvm *kvm,
8943 struct kvm_memory_slot *memslot,
09170a49 8944 const struct kvm_userspace_memory_region *mem,
7b6195a9 8945 enum kvm_mr_change change)
0de10343 8946{
f7784b8e
MT		 8947 return 0;
8948}
8949
88178fd4
KH		 8950static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8951 struct kvm_memory_slot *new)
8952{
8953 /* Still write protect RO slot */
8954 if (new->flags & KVM_MEM_READONLY) {
8955 kvm_mmu_slot_remove_write_access(kvm, new);
8956 return;
8957 }
8958
8959 /*
8960 * Call kvm_x86_ops dirty logging hooks when they are valid.
8961 *
8962 * kvm_x86_ops->slot_disable_log_dirty is called when:
8963 *
8964 * - KVM_MR_CREATE with dirty logging is disabled
8965 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8966 *
8967 * The reason is, in case of PML, we need to set D-bit for any slots
8968 * with dirty logging disabled in order to eliminate unnecessary GPA
8969 * logging in PML buffer (and potential PML buffer full VMEXT). This
8970 * guarantees leaving PML enabled during guest's lifetime won't have
8971 * any additonal overhead from PML when guest is running with dirty
8972 * logging disabled for memory slots.
8973 *
8974 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8975 * to dirty logging mode.
8976 *
8977 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8978 *
8979 * In case of write protect:
8980 *
8981 * Write protect all pages for dirty logging.
8982 *
8983 * All the sptes including the large sptes which point to this
8984 * slot are set to readonly. We can not create any new large
8985 * spte on this slot until the end of the logging.
8986 *
8987 * See the comments in fast_page_fault().
8988 */
8989 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8990 if (kvm_x86_ops->slot_enable_log_dirty)
8991 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8992 else
8993 kvm_mmu_slot_remove_write_access(kvm, new);
8994 } else {
8995 if (kvm_x86_ops->slot_disable_log_dirty)
8996 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8997 }
8998}
8999
f7784b8e 9000void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9001 const struct kvm_userspace_memory_region *mem,
8482644a 9002 const struct kvm_memory_slot *old,
f36f3f28 9003 const struct kvm_memory_slot *new,
8482644a 9004 enum kvm_mr_change change)
f7784b8e 9005{
8482644a 9006 int nr_mmu_pages = 0;
f7784b8e 9007
48c0e4e9
XG		 9008 if (!kvm->arch.n_requested_mmu_pages)
9009 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9010
48c0e4e9 9011 if (nr_mmu_pages)
0de10343 9012 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9013
3ea3b7fa
WL		 9014 /*
9015 * Dirty logging tracks sptes in 4k granularity, meaning that large
9016 * sptes have to be split. If live migration is successful, the guest
9017 * in the source machine will be destroyed and large sptes will be
9018 * created in the destination. However, if the guest continues to run
9019 * in the source machine (for example if live migration fails), small
9020 * sptes will remain around and cause bad performance.
9021 *
9022 * Scan sptes if dirty logging has been stopped, dropping those
9023 * which can be collapsed into a single large-page spte. Later
9024 * page faults will create the large-page sptes.
9025 */
9026 if ((change != KVM_MR_DELETE) &&
9027 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9028 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9029 kvm_mmu_zap_collapsible_sptes(kvm, new);
9030
c972f3b1 9031 /*
88178fd4 9032 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9033 *
88178fd4
KH		 9034 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9035 * been zapped so no dirty logging staff is needed for old slot. For
9036 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9037 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9038 *
9039 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9040 */
88178fd4 9041 if (change != KVM_MR_DELETE)
f36f3f28 9042 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9043}
1d737c8a 9044
2df72e9b 9045void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9046{
6ca18b69 9047 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9048}
9049
2df72e9b
MT		 9050void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9051 struct kvm_memory_slot *slot)
9052{
ae7cd873 9053 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9054}
9055
5d9bc648
PB		 9056static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9057{
9058 if (!list_empty_careful(&vcpu->async_pf.done))
9059 return true;
9060
9061 if (kvm_apic_has_events(vcpu))
9062 return true;
9063
9064 if (vcpu->arch.pv.pv_unhalted)
9065 return true;
9066
a5f01f8e
WL		 9067 if (vcpu->arch.exception.pending)
9068 return true;
9069
47a66eed
Z		 9070 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9071 (vcpu->arch.nmi_pending &&
9072 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9073 return true;
9074
47a66eed
Z		 9075 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9076 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9077 return true;
9078
5d9bc648
PB		 9079 if (kvm_arch_interrupt_allowed(vcpu) &&
9080 kvm_cpu_has_interrupt(vcpu))
9081 return true;
9082
1f4b34f8
AS		 9083 if (kvm_hv_has_stimer_pending(vcpu))
9084 return true;
9085
5d9bc648
PB		 9086 return false;
9087}
9088
1d737c8a
ZX		 9089int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9090{
5d9bc648 9091 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9092}
5736199a 9093
199b5763
LM		 9094bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9095{
de63ad4c 9096 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9097}
9098
b6d33834 9099int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9100{
b6d33834 9101 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9102}
78646121
GN		 9103
9104int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9105{
9106 return kvm_x86_ops->interrupt_allowed(vcpu);
9107}
229456fc 9108
82b32774 9109unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9110{
82b32774
NA		 9111 if (is_64_bit_mode(vcpu))
9112 return kvm_rip_read(vcpu);
9113 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9114 kvm_rip_read(vcpu));
9115}
9116EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9117
82b32774
NA		 9118bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9119{
9120 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9121}
9122EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9123
94fe45da
JK		 9124unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9125{
9126 unsigned long rflags;
9127
9128 rflags = kvm_x86_ops->get_rflags(vcpu);
9129 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9130 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9131 return rflags;
9132}
9133EXPORT_SYMBOL_GPL(kvm_get_rflags);
9134
6addfc42 9135static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9136{
9137 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9138 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9139 rflags |= X86_EFLAGS_TF;
94fe45da 9140 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9141}
9142
9143void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9144{
9145 __kvm_set_rflags(vcpu, rflags);
3842d135 9146 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9147}
9148EXPORT_SYMBOL_GPL(kvm_set_rflags);
9149
56028d08
GN		 9150void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9151{
9152 int r;
9153
fb67e14f 9154 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9155 work->wakeup_all)
56028d08
GN		 9156 return;
9157
9158 r = kvm_mmu_reload(vcpu);
9159 if (unlikely(r))
9160 return;
9161
fb67e14f
XG		 9162 if (!vcpu->arch.mmu.direct_map &&
9163 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9164 return;
9165
56028d08
GN		 9166 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9167}
9168
af585b92
GN		 9169static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9170{
9171 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9172}
9173
9174static inline u32 kvm_async_pf_next_probe(u32 key)
9175{
9176 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9177}
9178
9179static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9180{
9181 u32 key = kvm_async_pf_hash_fn(gfn);
9182
9183 while (vcpu->arch.apf.gfns[key] != ~0)
9184 key = kvm_async_pf_next_probe(key);
9185
9186 vcpu->arch.apf.gfns[key] = gfn;
9187}
9188
9189static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9190{
9191 int i;
9192 u32 key = kvm_async_pf_hash_fn(gfn);
9193
9194 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9195 (vcpu->arch.apf.gfns[key] != gfn &&
9196 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9197 key = kvm_async_pf_next_probe(key);
9198
9199 return key;
9200}
9201
9202bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9203{
9204 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9205}
9206
9207static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9208{
9209 u32 i, j, k;
9210
9211 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9212 while (true) {
9213 vcpu->arch.apf.gfns[i] = ~0;
9214 do {
9215 j = kvm_async_pf_next_probe(j);
9216 if (vcpu->arch.apf.gfns[j] == ~0)
9217 return;
9218 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9219 /*
9220 * k lies cyclically in ]i,j]
9221 * | i.k.j |
9222 * |....j i.k.| or |.k..j i...|
9223 */
9224 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9225 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9226 i = j;
9227 }
9228}
9229
7c90705b
GN		 9230static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9231{
4e335d9e
PB		 9232
9233 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9234 sizeof(val));
7c90705b
GN		 9235}
9236
9a6e7c39
WL		 9237static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9238{
9239
9240 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9241 sizeof(u32));
9242}
9243
af585b92
GN		 9244void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9245 struct kvm_async_pf *work)
9246{
6389ee94
AK		 9247 struct x86_exception fault;
9248
7c90705b 9249 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9250 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9251
9252 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9253 (vcpu->arch.apf.send_user_only &&
9254 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9255 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9256 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9257 fault.vector = PF_VECTOR;
9258 fault.error_code_valid = true;
9259 fault.error_code = 0;
9260 fault.nested_page_fault = false;
9261 fault.address = work->arch.token;
adfe20fb 9262 fault.async_page_fault = true;
6389ee94 9263 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9264 }
af585b92
GN		 9265}
9266
9267void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9268 struct kvm_async_pf *work)
9269{
6389ee94 9270 struct x86_exception fault;
9a6e7c39 9271 u32 val;
6389ee94 9272
f2e10669 9273 if (work->wakeup_all)
7c90705b
GN		 9274 work->arch.token = ~0; /* broadcast wakeup */
9275 else
9276 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9277 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9278
9a6e7c39
WL		 9279 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9280 !apf_get_user(vcpu, &val)) {
9281 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9282 vcpu->arch.exception.pending &&
9283 vcpu->arch.exception.nr == PF_VECTOR &&
9284 !apf_put_user(vcpu, 0)) {
9285 vcpu->arch.exception.injected = false;
9286 vcpu->arch.exception.pending = false;
9287 vcpu->arch.exception.nr = 0;
9288 vcpu->arch.exception.has_error_code = false;
9289 vcpu->arch.exception.error_code = 0;
9290 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9291 fault.vector = PF_VECTOR;
9292 fault.error_code_valid = true;
9293 fault.error_code = 0;
9294 fault.nested_page_fault = false;
9295 fault.address = work->arch.token;
9296 fault.async_page_fault = true;
9297 kvm_inject_page_fault(vcpu, &fault);
9298 }
7c90705b 9299 }
e6d53e3b 9300 vcpu->arch.apf.halted = false;
a4fa1635 9301 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9302}
9303
9304bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9305{
9306 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9307 return true;
9308 else
9bc1f09f 9309 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9310}
9311
5544eb9b
PB		 9312void kvm_arch_start_assignment(struct kvm *kvm)
9313{
9314 atomic_inc(&kvm->arch.assigned_device_count);
9315}
9316EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9317
9318void kvm_arch_end_assignment(struct kvm *kvm)
9319{
9320 atomic_dec(&kvm->arch.assigned_device_count);
9321}
9322EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9323
9324bool kvm_arch_has_assigned_device(struct kvm *kvm)
9325{
9326 return atomic_read(&kvm->arch.assigned_device_count);
9327}
9328EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9329
e0f0bbc5
AW		 9330void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9331{
9332 atomic_inc(&kvm->arch.noncoherent_dma_count);
9333}
9334EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9335
9336void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9337{
9338 atomic_dec(&kvm->arch.noncoherent_dma_count);
9339}
9340EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9341
9342bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9343{
9344 return atomic_read(&kvm->arch.noncoherent_dma_count);
9345}
9346EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9347
14717e20
AW		 9348bool kvm_arch_has_irq_bypass(void)
9349{
9350 return kvm_x86_ops->update_pi_irte != NULL;
9351}
9352
87276880
FW		 9353int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9354 struct irq_bypass_producer *prod)
9355{
9356 struct kvm_kernel_irqfd *irqfd =
9357 container_of(cons, struct kvm_kernel_irqfd, consumer);
9358
14717e20 9359 irqfd->producer = prod;
87276880 9360
14717e20
AW		 9361 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9362 prod->irq, irqfd->gsi, 1);
87276880
FW		 9363}
9364
9365void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9366 struct irq_bypass_producer *prod)
9367{
9368 int ret;
9369 struct kvm_kernel_irqfd *irqfd =
9370 container_of(cons, struct kvm_kernel_irqfd, consumer);
9371
87276880
FW		 9372 WARN_ON(irqfd->producer != prod);
9373 irqfd->producer = NULL;
9374
9375 /*
9376 * When producer of consumer is unregistered, we change back to
9377 * remapped mode, so we can re-use the current implementation
bb3541f1 9378 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9379 * int this case doesn't want to receive the interrupts.
9380 */
9381 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9382 if (ret)
9383 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9384 " fails: %d\n", irqfd->consumer.token, ret);
9385}
9386
9387int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9388 uint32_t guest_irq, bool set)
9389{
9390 if (!kvm_x86_ops->update_pi_irte)
9391 return -EINVAL;
9392
9393 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9394}
9395
52004014
FW		 9396bool kvm_vector_hashing_enabled(void)
9397{
9398 return vector_hashing;
9399}
9400EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9401
229456fc 9402EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9403EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9404EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9405EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9406EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9407EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9408EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9409EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9410EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9411EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9412EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9413EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9414EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9415EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9416EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9417EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9418EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9419EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9420EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Ubuntu Focal Linux kernel mirror