]>
Commit | Line | Data |
---|---|---|
043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
00b27a3e | 29 | #include "cpuid.h" |
c9eab58f | 30 | #include "assigned-dev.h" |
313a3dc7 | 31 | |
18068523 | 32 | #include <linux/clocksource.h> |
4d5c5d0f | 33 | #include <linux/interrupt.h> |
313a3dc7 CO |
34 | #include <linux/kvm.h> |
35 | #include <linux/fs.h> | |
36 | #include <linux/vmalloc.h> | |
5fb76f9b | 37 | #include <linux/module.h> |
0de10343 | 38 | #include <linux/mman.h> |
2bacc55c | 39 | #include <linux/highmem.h> |
19de40a8 | 40 | #include <linux/iommu.h> |
62c476c7 | 41 | #include <linux/intel-iommu.h> |
c8076604 | 42 | #include <linux/cpufreq.h> |
18863bdd | 43 | #include <linux/user-return-notifier.h> |
a983fb23 | 44 | #include <linux/srcu.h> |
5a0e3ad6 | 45 | #include <linux/slab.h> |
ff9d07a0 | 46 | #include <linux/perf_event.h> |
7bee342a | 47 | #include <linux/uaccess.h> |
af585b92 | 48 | #include <linux/hash.h> |
a1b60c1c | 49 | #include <linux/pci.h> |
16e8d74d MT |
50 | #include <linux/timekeeper_internal.h> |
51 | #include <linux/pvclock_gtod.h> | |
aec51dc4 | 52 | #include <trace/events/kvm.h> |
2ed152af | 53 | |
229456fc MT |
54 | #define CREATE_TRACE_POINTS |
55 | #include "trace.h" | |
043405e1 | 56 | |
24f1e32c | 57 | #include <asm/debugreg.h> |
d825ed0a | 58 | #include <asm/msr.h> |
a5f61300 | 59 | #include <asm/desc.h> |
890ca9ae | 60 | #include <asm/mce.h> |
7cf30855 | 61 | #include <asm/i387.h> |
1361b83a | 62 | #include <asm/fpu-internal.h> /* Ugh! */ |
98918833 | 63 | #include <asm/xcr.h> |
1d5f066e | 64 | #include <asm/pvclock.h> |
217fc9cf | 65 | #include <asm/div64.h> |
043405e1 | 66 | |
313a3dc7 | 67 | #define MAX_IO_MSRS 256 |
890ca9ae | 68 | #define KVM_MAX_MCE_BANKS 32 |
5854dbca | 69 | #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) |
890ca9ae | 70 | |
0f65dd70 AK |
71 | #define emul_to_vcpu(ctxt) \ |
72 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
73 | ||
50a37eb4 JR |
74 | /* EFER defaults: |
75 | * - enable syscall per default because its emulated by KVM | |
76 | * - enable LME and LMA per default on 64 bit KVM | |
77 | */ | |
78 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
79 | static |
80 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 81 | #else |
1260edbe | 82 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 83 | #endif |
313a3dc7 | 84 | |
ba1389b7 AK |
85 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
86 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 87 | |
cb142eb7 | 88 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 89 | static void process_nmi(struct kvm_vcpu *vcpu); |
6addfc42 | 90 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
674eea0f | 91 | |
97896d04 | 92 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 93 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 94 | |
476bc001 RR |
95 | static bool ignore_msrs = 0; |
96 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
ed85c068 | 97 | |
9ed96e87 MT |
98 | unsigned int min_timer_period_us = 500; |
99 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); | |
100 | ||
630994b3 MT |
101 | static bool __read_mostly kvmclock_periodic_sync = true; |
102 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
103 | ||
92a1f12d JR |
104 | bool kvm_has_tsc_control; |
105 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); | |
106 | u32 kvm_max_guest_tsc_khz; | |
107 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); | |
108 | ||
cc578287 ZA |
109 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
110 | static u32 tsc_tolerance_ppm = 250; | |
111 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); | |
112 | ||
d0659d94 MT |
113 | /* lapic timer advance (tscdeadline mode only) in nanoseconds */ |
114 | unsigned int lapic_timer_advance_ns = 0; | |
115 | module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); | |
116 | ||
16a96021 MT |
117 | static bool backwards_tsc_observed = false; |
118 | ||
18863bdd AK |
119 | #define KVM_NR_SHARED_MSRS 16 |
120 | ||
121 | struct kvm_shared_msrs_global { | |
122 | int nr; | |
2bf78fa7 | 123 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
124 | }; |
125 | ||
126 | struct kvm_shared_msrs { | |
127 | struct user_return_notifier urn; | |
128 | bool registered; | |
2bf78fa7 SY |
129 | struct kvm_shared_msr_values { |
130 | u64 host; | |
131 | u64 curr; | |
132 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
133 | }; |
134 | ||
135 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
013f6a5d | 136 | static struct kvm_shared_msrs __percpu *shared_msrs; |
18863bdd | 137 | |
417bc304 | 138 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
139 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
140 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
141 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
142 | { "invlpg", VCPU_STAT(invlpg) }, | |
143 | { "exits", VCPU_STAT(exits) }, | |
144 | { "io_exits", VCPU_STAT(io_exits) }, | |
145 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
146 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
147 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 148 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 | 149 | { "halt_exits", VCPU_STAT(halt_exits) }, |
f7819512 | 150 | { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, |
ba1389b7 | 151 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
f11c3a8d | 152 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
153 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
154 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
155 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
156 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
157 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
158 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
159 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 160 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 161 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
162 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
163 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
164 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
165 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
166 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
167 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 168 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 169 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 170 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 171 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
172 | { NULL } |
173 | }; | |
174 | ||
2acf923e DC |
175 | u64 __read_mostly host_xcr0; |
176 | ||
b6785def | 177 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 178 | |
af585b92 GN |
179 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
180 | { | |
181 | int i; | |
182 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
183 | vcpu->arch.apf.gfns[i] = ~0; | |
184 | } | |
185 | ||
18863bdd AK |
186 | static void kvm_on_user_return(struct user_return_notifier *urn) |
187 | { | |
188 | unsigned slot; | |
18863bdd AK |
189 | struct kvm_shared_msrs *locals |
190 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 191 | struct kvm_shared_msr_values *values; |
18863bdd AK |
192 | |
193 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
194 | values = &locals->values[slot]; |
195 | if (values->host != values->curr) { | |
196 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
197 | values->curr = values->host; | |
18863bdd AK |
198 | } |
199 | } | |
200 | locals->registered = false; | |
201 | user_return_notifier_unregister(urn); | |
202 | } | |
203 | ||
2bf78fa7 | 204 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 205 | { |
18863bdd | 206 | u64 value; |
013f6a5d MT |
207 | unsigned int cpu = smp_processor_id(); |
208 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
18863bdd | 209 | |
2bf78fa7 SY |
210 | /* only read, and nobody should modify it at this time, |
211 | * so don't need lock */ | |
212 | if (slot >= shared_msrs_global.nr) { | |
213 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
214 | return; | |
215 | } | |
216 | rdmsrl_safe(msr, &value); | |
217 | smsr->values[slot].host = value; | |
218 | smsr->values[slot].curr = value; | |
219 | } | |
220 | ||
221 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
222 | { | |
0123be42 | 223 | BUG_ON(slot >= KVM_NR_SHARED_MSRS); |
18863bdd AK |
224 | if (slot >= shared_msrs_global.nr) |
225 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
226 | shared_msrs_global.msrs[slot] = msr; |
227 | /* we need ensured the shared_msr_global have been updated */ | |
228 | smp_wmb(); | |
18863bdd AK |
229 | } |
230 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
231 | ||
232 | static void kvm_shared_msr_cpu_online(void) | |
233 | { | |
234 | unsigned i; | |
18863bdd AK |
235 | |
236 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 237 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
238 | } |
239 | ||
8b3c3104 | 240 | int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 241 | { |
013f6a5d MT |
242 | unsigned int cpu = smp_processor_id(); |
243 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
8b3c3104 | 244 | int err; |
18863bdd | 245 | |
2bf78fa7 | 246 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
8b3c3104 | 247 | return 0; |
2bf78fa7 | 248 | smsr->values[slot].curr = value; |
8b3c3104 AH |
249 | err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); |
250 | if (err) | |
251 | return 1; | |
252 | ||
18863bdd AK |
253 | if (!smsr->registered) { |
254 | smsr->urn.on_user_return = kvm_on_user_return; | |
255 | user_return_notifier_register(&smsr->urn); | |
256 | smsr->registered = true; | |
257 | } | |
8b3c3104 | 258 | return 0; |
18863bdd AK |
259 | } |
260 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
261 | ||
13a34e06 | 262 | static void drop_user_return_notifiers(void) |
3548bab5 | 263 | { |
013f6a5d MT |
264 | unsigned int cpu = smp_processor_id(); |
265 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
3548bab5 AK |
266 | |
267 | if (smsr->registered) | |
268 | kvm_on_user_return(&smsr->urn); | |
269 | } | |
270 | ||
6866b83e CO |
271 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
272 | { | |
8a5a87d9 | 273 | return vcpu->arch.apic_base; |
6866b83e CO |
274 | } |
275 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
276 | ||
58cb628d JK |
277 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
278 | { | |
279 | u64 old_state = vcpu->arch.apic_base & | |
280 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
281 | u64 new_state = msr_info->data & | |
282 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
283 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | | |
284 | 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); | |
285 | ||
286 | if (!msr_info->host_initiated && | |
287 | ((msr_info->data & reserved_bits) != 0 || | |
288 | new_state == X2APIC_ENABLE || | |
289 | (new_state == MSR_IA32_APICBASE_ENABLE && | |
290 | old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || | |
291 | (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && | |
292 | old_state == 0))) | |
293 | return 1; | |
294 | ||
295 | kvm_lapic_set_base(vcpu, msr_info->data); | |
296 | return 0; | |
6866b83e CO |
297 | } |
298 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
299 | ||
2605fc21 | 300 | asmlinkage __visible void kvm_spurious_fault(void) |
e3ba45b8 GL |
301 | { |
302 | /* Fault while not rebooting. We want the trace. */ | |
303 | BUG(); | |
304 | } | |
305 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
306 | ||
3fd28fce ED |
307 | #define EXCPT_BENIGN 0 |
308 | #define EXCPT_CONTRIBUTORY 1 | |
309 | #define EXCPT_PF 2 | |
310 | ||
311 | static int exception_class(int vector) | |
312 | { | |
313 | switch (vector) { | |
314 | case PF_VECTOR: | |
315 | return EXCPT_PF; | |
316 | case DE_VECTOR: | |
317 | case TS_VECTOR: | |
318 | case NP_VECTOR: | |
319 | case SS_VECTOR: | |
320 | case GP_VECTOR: | |
321 | return EXCPT_CONTRIBUTORY; | |
322 | default: | |
323 | break; | |
324 | } | |
325 | return EXCPT_BENIGN; | |
326 | } | |
327 | ||
d6e8c854 NA |
328 | #define EXCPT_FAULT 0 |
329 | #define EXCPT_TRAP 1 | |
330 | #define EXCPT_ABORT 2 | |
331 | #define EXCPT_INTERRUPT 3 | |
332 | ||
333 | static int exception_type(int vector) | |
334 | { | |
335 | unsigned int mask; | |
336 | ||
337 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
338 | return EXCPT_INTERRUPT; | |
339 | ||
340 | mask = 1 << vector; | |
341 | ||
342 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
343 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
344 | return EXCPT_TRAP; | |
345 | ||
346 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
347 | return EXCPT_ABORT; | |
348 | ||
349 | /* Reserved exceptions will result in fault */ | |
350 | return EXCPT_FAULT; | |
351 | } | |
352 | ||
3fd28fce | 353 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 JR |
354 | unsigned nr, bool has_error, u32 error_code, |
355 | bool reinject) | |
3fd28fce ED |
356 | { |
357 | u32 prev_nr; | |
358 | int class1, class2; | |
359 | ||
3842d135 AK |
360 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
361 | ||
3fd28fce ED |
362 | if (!vcpu->arch.exception.pending) { |
363 | queue: | |
3ffb2468 NA |
364 | if (has_error && !is_protmode(vcpu)) |
365 | has_error = false; | |
3fd28fce ED |
366 | vcpu->arch.exception.pending = true; |
367 | vcpu->arch.exception.has_error_code = has_error; | |
368 | vcpu->arch.exception.nr = nr; | |
369 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 370 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
371 | return; |
372 | } | |
373 | ||
374 | /* to check exception */ | |
375 | prev_nr = vcpu->arch.exception.nr; | |
376 | if (prev_nr == DF_VECTOR) { | |
377 | /* triple fault -> shutdown */ | |
a8eeb04a | 378 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
379 | return; |
380 | } | |
381 | class1 = exception_class(prev_nr); | |
382 | class2 = exception_class(nr); | |
383 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
384 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
385 | /* generate double fault per SDM Table 5-5 */ | |
386 | vcpu->arch.exception.pending = true; | |
387 | vcpu->arch.exception.has_error_code = true; | |
388 | vcpu->arch.exception.nr = DF_VECTOR; | |
389 | vcpu->arch.exception.error_code = 0; | |
390 | } else | |
391 | /* replace previous exception with a new one in a hope | |
392 | that instruction re-execution will regenerate lost | |
393 | exception */ | |
394 | goto queue; | |
395 | } | |
396 | ||
298101da AK |
397 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
398 | { | |
ce7ddec4 | 399 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
400 | } |
401 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
402 | ||
ce7ddec4 JR |
403 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
404 | { | |
405 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
406 | } | |
407 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
408 | ||
db8fcefa | 409 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 410 | { |
db8fcefa AP |
411 | if (err) |
412 | kvm_inject_gp(vcpu, 0); | |
413 | else | |
414 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
415 | } | |
416 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 417 | |
6389ee94 | 418 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
419 | { |
420 | ++vcpu->stat.pf_guest; | |
6389ee94 AK |
421 | vcpu->arch.cr2 = fault->address; |
422 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); | |
c3c91fee | 423 | } |
27d6c865 | 424 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 425 | |
ef54bcfe | 426 | static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 427 | { |
6389ee94 AK |
428 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
429 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 430 | else |
6389ee94 | 431 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
ef54bcfe PB |
432 | |
433 | return fault->nested_page_fault; | |
d4f8cf66 JR |
434 | } |
435 | ||
3419ffc8 SY |
436 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
437 | { | |
7460fb4a AK |
438 | atomic_inc(&vcpu->arch.nmi_queued); |
439 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
440 | } |
441 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
442 | ||
298101da AK |
443 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
444 | { | |
ce7ddec4 | 445 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
446 | } |
447 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
448 | ||
ce7ddec4 JR |
449 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
450 | { | |
451 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
452 | } | |
453 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
454 | ||
0a79b009 AK |
455 | /* |
456 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
457 | * a #GP and return false. | |
458 | */ | |
459 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 460 | { |
0a79b009 AK |
461 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
462 | return true; | |
463 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
464 | return false; | |
298101da | 465 | } |
0a79b009 | 466 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 467 | |
16f8a6f9 NA |
468 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
469 | { | |
470 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
471 | return true; | |
472 | ||
473 | kvm_queue_exception(vcpu, UD_VECTOR); | |
474 | return false; | |
475 | } | |
476 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
477 | ||
ec92fe44 JR |
478 | /* |
479 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 480 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
481 | * can read from guest physical or from the guest's guest physical memory. |
482 | */ | |
483 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
484 | gfn_t ngfn, void *data, int offset, int len, | |
485 | u32 access) | |
486 | { | |
54987b7a | 487 | struct x86_exception exception; |
ec92fe44 JR |
488 | gfn_t real_gfn; |
489 | gpa_t ngpa; | |
490 | ||
491 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 492 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
493 | if (real_gfn == UNMAPPED_GVA) |
494 | return -EFAULT; | |
495 | ||
496 | real_gfn = gpa_to_gfn(real_gfn); | |
497 | ||
54bf36aa | 498 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
499 | } |
500 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
501 | ||
69b0049a | 502 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
503 | void *data, int offset, int len, u32 access) |
504 | { | |
505 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
506 | data, offset, len, access); | |
507 | } | |
508 | ||
a03490ed CO |
509 | /* |
510 | * Load the pae pdptrs. Return true is they are all valid. | |
511 | */ | |
ff03a073 | 512 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
513 | { |
514 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
515 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
516 | int i; | |
517 | int ret; | |
ff03a073 | 518 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 519 | |
ff03a073 JR |
520 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
521 | offset * sizeof(u64), sizeof(pdpte), | |
522 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
523 | if (ret < 0) { |
524 | ret = 0; | |
525 | goto out; | |
526 | } | |
527 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 528 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 529 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
530 | ret = 0; |
531 | goto out; | |
532 | } | |
533 | } | |
534 | ret = 1; | |
535 | ||
ff03a073 | 536 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
537 | __set_bit(VCPU_EXREG_PDPTR, |
538 | (unsigned long *)&vcpu->arch.regs_avail); | |
539 | __set_bit(VCPU_EXREG_PDPTR, | |
540 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 541 | out: |
a03490ed CO |
542 | |
543 | return ret; | |
544 | } | |
cc4b6871 | 545 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 546 | |
d835dfec AK |
547 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
548 | { | |
ff03a073 | 549 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 550 | bool changed = true; |
3d06b8bf JR |
551 | int offset; |
552 | gfn_t gfn; | |
d835dfec AK |
553 | int r; |
554 | ||
555 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
556 | return false; | |
557 | ||
6de4f3ad AK |
558 | if (!test_bit(VCPU_EXREG_PDPTR, |
559 | (unsigned long *)&vcpu->arch.regs_avail)) | |
560 | return true; | |
561 | ||
9f8fe504 AK |
562 | gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; |
563 | offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
564 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
565 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
566 | if (r < 0) |
567 | goto out; | |
ff03a073 | 568 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 569 | out: |
d835dfec AK |
570 | |
571 | return changed; | |
572 | } | |
573 | ||
49a9b07e | 574 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 575 | { |
aad82703 | 576 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d81135a5 | 577 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; |
aad82703 | 578 | |
f9a48e6a AK |
579 | cr0 |= X86_CR0_ET; |
580 | ||
ab344828 | 581 | #ifdef CONFIG_X86_64 |
0f12244f GN |
582 | if (cr0 & 0xffffffff00000000UL) |
583 | return 1; | |
ab344828 GN |
584 | #endif |
585 | ||
586 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 587 | |
0f12244f GN |
588 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
589 | return 1; | |
a03490ed | 590 | |
0f12244f GN |
591 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
592 | return 1; | |
a03490ed CO |
593 | |
594 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
595 | #ifdef CONFIG_X86_64 | |
f6801dff | 596 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
597 | int cs_db, cs_l; |
598 | ||
0f12244f GN |
599 | if (!is_pae(vcpu)) |
600 | return 1; | |
a03490ed | 601 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
602 | if (cs_l) |
603 | return 1; | |
a03490ed CO |
604 | } else |
605 | #endif | |
ff03a073 | 606 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 607 | kvm_read_cr3(vcpu))) |
0f12244f | 608 | return 1; |
a03490ed CO |
609 | } |
610 | ||
ad756a16 MJ |
611 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
612 | return 1; | |
613 | ||
a03490ed | 614 | kvm_x86_ops->set_cr0(vcpu, cr0); |
a03490ed | 615 | |
d170c419 | 616 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 617 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
618 | kvm_async_pf_hash_reset(vcpu); |
619 | } | |
e5f3f027 | 620 | |
aad82703 SY |
621 | if ((cr0 ^ old_cr0) & update_bits) |
622 | kvm_mmu_reset_context(vcpu); | |
b18d5431 XG |
623 | |
624 | if ((cr0 ^ old_cr0) & X86_CR0_CD) | |
625 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); | |
626 | ||
0f12244f GN |
627 | return 0; |
628 | } | |
2d3ad1f4 | 629 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 630 | |
2d3ad1f4 | 631 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 632 | { |
49a9b07e | 633 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 634 | } |
2d3ad1f4 | 635 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 636 | |
42bdf991 MT |
637 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
638 | { | |
639 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
640 | !vcpu->guest_xcr0_loaded) { | |
641 | /* kvm_set_xcr() also depends on this */ | |
642 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
643 | vcpu->guest_xcr0_loaded = 1; | |
644 | } | |
645 | } | |
646 | ||
647 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
648 | { | |
649 | if (vcpu->guest_xcr0_loaded) { | |
650 | if (vcpu->arch.xcr0 != host_xcr0) | |
651 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
652 | vcpu->guest_xcr0_loaded = 0; | |
653 | } | |
654 | } | |
655 | ||
69b0049a | 656 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 657 | { |
56c103ec LJ |
658 | u64 xcr0 = xcr; |
659 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 660 | u64 valid_bits; |
2acf923e DC |
661 | |
662 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
663 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
664 | return 1; | |
2acf923e DC |
665 | if (!(xcr0 & XSTATE_FP)) |
666 | return 1; | |
667 | if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) | |
668 | return 1; | |
46c34cb0 PB |
669 | |
670 | /* | |
671 | * Do not allow the guest to set bits that we do not support | |
672 | * saving. However, xcr0 bit 0 is always set, even if the | |
673 | * emulated CPU does not support XSAVE (see fx_init). | |
674 | */ | |
675 | valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP; | |
676 | if (xcr0 & ~valid_bits) | |
2acf923e | 677 | return 1; |
46c34cb0 | 678 | |
390bd528 LJ |
679 | if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR))) |
680 | return 1; | |
681 | ||
612263b3 CP |
682 | if (xcr0 & XSTATE_AVX512) { |
683 | if (!(xcr0 & XSTATE_YMM)) | |
684 | return 1; | |
685 | if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512) | |
686 | return 1; | |
687 | } | |
42bdf991 | 688 | kvm_put_guest_xcr0(vcpu); |
2acf923e | 689 | vcpu->arch.xcr0 = xcr0; |
56c103ec LJ |
690 | |
691 | if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK) | |
692 | kvm_update_cpuid(vcpu); | |
2acf923e DC |
693 | return 0; |
694 | } | |
695 | ||
696 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
697 | { | |
764bcbc5 Z |
698 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || |
699 | __kvm_set_xcr(vcpu, index, xcr)) { | |
2acf923e DC |
700 | kvm_inject_gp(vcpu, 0); |
701 | return 1; | |
702 | } | |
703 | return 0; | |
704 | } | |
705 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
706 | ||
a83b29c6 | 707 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 708 | { |
fc78f519 | 709 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
edc90b7d XG |
710 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | |
711 | X86_CR4_SMEP | X86_CR4_SMAP; | |
712 | ||
0f12244f GN |
713 | if (cr4 & CR4_RESERVED_BITS) |
714 | return 1; | |
a03490ed | 715 | |
2acf923e DC |
716 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
717 | return 1; | |
718 | ||
c68b734f YW |
719 | if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) |
720 | return 1; | |
721 | ||
97ec8c06 FW |
722 | if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) |
723 | return 1; | |
724 | ||
afcbf13f | 725 | if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) |
74dc2b4f YW |
726 | return 1; |
727 | ||
a03490ed | 728 | if (is_long_mode(vcpu)) { |
0f12244f GN |
729 | if (!(cr4 & X86_CR4_PAE)) |
730 | return 1; | |
a2edf57f AK |
731 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
732 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
733 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
734 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
735 | return 1; |
736 | ||
ad756a16 MJ |
737 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
738 | if (!guest_cpuid_has_pcid(vcpu)) | |
739 | return 1; | |
740 | ||
741 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
742 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
743 | return 1; | |
744 | } | |
745 | ||
5e1746d6 | 746 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) |
0f12244f | 747 | return 1; |
a03490ed | 748 | |
ad756a16 MJ |
749 | if (((cr4 ^ old_cr4) & pdptr_bits) || |
750 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
aad82703 | 751 | kvm_mmu_reset_context(vcpu); |
0f12244f | 752 | |
2acf923e | 753 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) |
00b27a3e | 754 | kvm_update_cpuid(vcpu); |
2acf923e | 755 | |
0f12244f GN |
756 | return 0; |
757 | } | |
2d3ad1f4 | 758 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 759 | |
2390218b | 760 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 761 | { |
ac146235 | 762 | #ifdef CONFIG_X86_64 |
9d88fca7 | 763 | cr3 &= ~CR3_PCID_INVD; |
ac146235 | 764 | #endif |
9d88fca7 | 765 | |
9f8fe504 | 766 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
0ba73cda | 767 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 768 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
0f12244f | 769 | return 0; |
d835dfec AK |
770 | } |
771 | ||
a03490ed | 772 | if (is_long_mode(vcpu)) { |
d9f89b88 JK |
773 | if (cr3 & CR3_L_MODE_RESERVED_BITS) |
774 | return 1; | |
775 | } else if (is_pae(vcpu) && is_paging(vcpu) && | |
776 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 777 | return 1; |
a03490ed | 778 | |
0f12244f | 779 | vcpu->arch.cr3 = cr3; |
aff48baa | 780 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
d8d173da | 781 | kvm_mmu_new_cr3(vcpu); |
0f12244f GN |
782 | return 0; |
783 | } | |
2d3ad1f4 | 784 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 785 | |
eea1cff9 | 786 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 787 | { |
0f12244f GN |
788 | if (cr8 & CR8_RESERVED_BITS) |
789 | return 1; | |
a03490ed CO |
790 | if (irqchip_in_kernel(vcpu->kvm)) |
791 | kvm_lapic_set_tpr(vcpu, cr8); | |
792 | else | |
ad312c7c | 793 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
794 | return 0; |
795 | } | |
2d3ad1f4 | 796 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 797 | |
2d3ad1f4 | 798 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
799 | { |
800 | if (irqchip_in_kernel(vcpu->kvm)) | |
801 | return kvm_lapic_get_cr8(vcpu); | |
802 | else | |
ad312c7c | 803 | return vcpu->arch.cr8; |
a03490ed | 804 | } |
2d3ad1f4 | 805 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 806 | |
ae561ede NA |
807 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
808 | { | |
809 | int i; | |
810 | ||
811 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
812 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
813 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
814 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
815 | } | |
816 | } | |
817 | ||
73aaf249 JK |
818 | static void kvm_update_dr6(struct kvm_vcpu *vcpu) |
819 | { | |
820 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
821 | kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); | |
822 | } | |
823 | ||
c8639010 JK |
824 | static void kvm_update_dr7(struct kvm_vcpu *vcpu) |
825 | { | |
826 | unsigned long dr7; | |
827 | ||
828 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
829 | dr7 = vcpu->arch.guest_debug_dr7; | |
830 | else | |
831 | dr7 = vcpu->arch.dr7; | |
832 | kvm_x86_ops->set_dr7(vcpu, dr7); | |
360b948d PB |
833 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
834 | if (dr7 & DR7_BP_EN_MASK) | |
835 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 JK |
836 | } |
837 | ||
6f43ed01 NA |
838 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
839 | { | |
840 | u64 fixed = DR6_FIXED_1; | |
841 | ||
842 | if (!guest_cpuid_has_rtm(vcpu)) | |
843 | fixed |= DR6_RTM; | |
844 | return fixed; | |
845 | } | |
846 | ||
338dbc97 | 847 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
848 | { |
849 | switch (dr) { | |
850 | case 0 ... 3: | |
851 | vcpu->arch.db[dr] = val; | |
852 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
853 | vcpu->arch.eff_db[dr] = val; | |
854 | break; | |
855 | case 4: | |
020df079 GN |
856 | /* fall through */ |
857 | case 6: | |
338dbc97 GN |
858 | if (val & 0xffffffff00000000ULL) |
859 | return -1; /* #GP */ | |
6f43ed01 | 860 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
73aaf249 | 861 | kvm_update_dr6(vcpu); |
020df079 GN |
862 | break; |
863 | case 5: | |
020df079 GN |
864 | /* fall through */ |
865 | default: /* 7 */ | |
338dbc97 GN |
866 | if (val & 0xffffffff00000000ULL) |
867 | return -1; /* #GP */ | |
020df079 | 868 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 869 | kvm_update_dr7(vcpu); |
020df079 GN |
870 | break; |
871 | } | |
872 | ||
873 | return 0; | |
874 | } | |
338dbc97 GN |
875 | |
876 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
877 | { | |
16f8a6f9 | 878 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 879 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
880 | return 1; |
881 | } | |
882 | return 0; | |
338dbc97 | 883 | } |
020df079 GN |
884 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
885 | ||
16f8a6f9 | 886 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
887 | { |
888 | switch (dr) { | |
889 | case 0 ... 3: | |
890 | *val = vcpu->arch.db[dr]; | |
891 | break; | |
892 | case 4: | |
020df079 GN |
893 | /* fall through */ |
894 | case 6: | |
73aaf249 JK |
895 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
896 | *val = vcpu->arch.dr6; | |
897 | else | |
898 | *val = kvm_x86_ops->get_dr6(vcpu); | |
020df079 GN |
899 | break; |
900 | case 5: | |
020df079 GN |
901 | /* fall through */ |
902 | default: /* 7 */ | |
903 | *val = vcpu->arch.dr7; | |
904 | break; | |
905 | } | |
338dbc97 GN |
906 | return 0; |
907 | } | |
020df079 GN |
908 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
909 | ||
022cd0e8 AK |
910 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
911 | { | |
912 | u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
913 | u64 data; | |
914 | int err; | |
915 | ||
916 | err = kvm_pmu_read_pmc(vcpu, ecx, &data); | |
917 | if (err) | |
918 | return err; | |
919 | kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); | |
920 | kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); | |
921 | return err; | |
922 | } | |
923 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
924 | ||
043405e1 CO |
925 | /* |
926 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
927 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
928 | * | |
929 | * This list is modified at module load time to reflect the | |
e3267cbb | 930 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
62ef68bb PB |
931 | * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs |
932 | * may depend on host virtualization features rather than host cpu features. | |
043405e1 | 933 | */ |
e3267cbb | 934 | |
043405e1 CO |
935 | static u32 msrs_to_save[] = { |
936 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
8c06585d | 937 | MSR_STAR, |
043405e1 CO |
938 | #ifdef CONFIG_X86_64 |
939 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
940 | #endif | |
b3897a49 | 941 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
0dd376e7 | 942 | MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS |
043405e1 CO |
943 | }; |
944 | ||
945 | static unsigned num_msrs_to_save; | |
946 | ||
62ef68bb PB |
947 | static u32 emulated_msrs[] = { |
948 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, | |
949 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
950 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
951 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
952 | HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
953 | MSR_KVM_PV_EOI_EN, | |
954 | ||
ba904635 | 955 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 956 | MSR_IA32_TSCDEADLINE, |
043405e1 | 957 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
958 | MSR_IA32_MCG_STATUS, |
959 | MSR_IA32_MCG_CTL, | |
64d60670 | 960 | MSR_IA32_SMBASE, |
043405e1 CO |
961 | }; |
962 | ||
62ef68bb PB |
963 | static unsigned num_emulated_msrs; |
964 | ||
384bb783 | 965 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 966 | { |
b69e8cae | 967 | if (efer & efer_reserved_bits) |
384bb783 | 968 | return false; |
15c4a640 | 969 | |
1b2fd70c AG |
970 | if (efer & EFER_FFXSR) { |
971 | struct kvm_cpuid_entry2 *feat; | |
972 | ||
973 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 974 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
384bb783 | 975 | return false; |
1b2fd70c AG |
976 | } |
977 | ||
d8017474 AG |
978 | if (efer & EFER_SVME) { |
979 | struct kvm_cpuid_entry2 *feat; | |
980 | ||
981 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 982 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
384bb783 | 983 | return false; |
d8017474 AG |
984 | } |
985 | ||
384bb783 JK |
986 | return true; |
987 | } | |
988 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
989 | ||
990 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
991 | { | |
992 | u64 old_efer = vcpu->arch.efer; | |
993 | ||
994 | if (!kvm_valid_efer(vcpu, efer)) | |
995 | return 1; | |
996 | ||
997 | if (is_paging(vcpu) | |
998 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
999 | return 1; | |
1000 | ||
15c4a640 | 1001 | efer &= ~EFER_LMA; |
f6801dff | 1002 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1003 | |
a3d204e2 SY |
1004 | kvm_x86_ops->set_efer(vcpu, efer); |
1005 | ||
aad82703 SY |
1006 | /* Update reserved bits */ |
1007 | if ((efer ^ old_efer) & EFER_NX) | |
1008 | kvm_mmu_reset_context(vcpu); | |
1009 | ||
b69e8cae | 1010 | return 0; |
15c4a640 CO |
1011 | } |
1012 | ||
f2b4b7dd JR |
1013 | void kvm_enable_efer_bits(u64 mask) |
1014 | { | |
1015 | efer_reserved_bits &= ~mask; | |
1016 | } | |
1017 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1018 | ||
15c4a640 CO |
1019 | /* |
1020 | * Writes msr value into into the appropriate "register". | |
1021 | * Returns 0 on success, non-0 otherwise. | |
1022 | * Assumes vcpu_load() was already called. | |
1023 | */ | |
8fe8ab46 | 1024 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 1025 | { |
854e8bb1 NA |
1026 | switch (msr->index) { |
1027 | case MSR_FS_BASE: | |
1028 | case MSR_GS_BASE: | |
1029 | case MSR_KERNEL_GS_BASE: | |
1030 | case MSR_CSTAR: | |
1031 | case MSR_LSTAR: | |
1032 | if (is_noncanonical_address(msr->data)) | |
1033 | return 1; | |
1034 | break; | |
1035 | case MSR_IA32_SYSENTER_EIP: | |
1036 | case MSR_IA32_SYSENTER_ESP: | |
1037 | /* | |
1038 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1039 | * non-canonical address is written on Intel but not on | |
1040 | * AMD (which ignores the top 32-bits, because it does | |
1041 | * not implement 64-bit SYSENTER). | |
1042 | * | |
1043 | * 64-bit code should hence be able to write a non-canonical | |
1044 | * value on AMD. Making the address canonical ensures that | |
1045 | * vmentry does not fail on Intel after writing a non-canonical | |
1046 | * value, and that something deterministic happens if the guest | |
1047 | * invokes 64-bit SYSENTER. | |
1048 | */ | |
1049 | msr->data = get_canonical(msr->data); | |
1050 | } | |
8fe8ab46 | 1051 | return kvm_x86_ops->set_msr(vcpu, msr); |
15c4a640 | 1052 | } |
854e8bb1 | 1053 | EXPORT_SYMBOL_GPL(kvm_set_msr); |
15c4a640 | 1054 | |
313a3dc7 CO |
1055 | /* |
1056 | * Adapt set_msr() to msr_io()'s calling convention | |
1057 | */ | |
609e36d3 PB |
1058 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1059 | { | |
1060 | struct msr_data msr; | |
1061 | int r; | |
1062 | ||
1063 | msr.index = index; | |
1064 | msr.host_initiated = true; | |
1065 | r = kvm_get_msr(vcpu, &msr); | |
1066 | if (r) | |
1067 | return r; | |
1068 | ||
1069 | *data = msr.data; | |
1070 | return 0; | |
1071 | } | |
1072 | ||
313a3dc7 CO |
1073 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1074 | { | |
8fe8ab46 WA |
1075 | struct msr_data msr; |
1076 | ||
1077 | msr.data = *data; | |
1078 | msr.index = index; | |
1079 | msr.host_initiated = true; | |
1080 | return kvm_set_msr(vcpu, &msr); | |
313a3dc7 CO |
1081 | } |
1082 | ||
16e8d74d MT |
1083 | #ifdef CONFIG_X86_64 |
1084 | struct pvclock_gtod_data { | |
1085 | seqcount_t seq; | |
1086 | ||
1087 | struct { /* extract of a clocksource struct */ | |
1088 | int vclock_mode; | |
1089 | cycle_t cycle_last; | |
1090 | cycle_t mask; | |
1091 | u32 mult; | |
1092 | u32 shift; | |
1093 | } clock; | |
1094 | ||
cbcf2dd3 TG |
1095 | u64 boot_ns; |
1096 | u64 nsec_base; | |
16e8d74d MT |
1097 | }; |
1098 | ||
1099 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1100 | ||
1101 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1102 | { | |
1103 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
cbcf2dd3 TG |
1104 | u64 boot_ns; |
1105 | ||
876e7881 | 1106 | boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); |
16e8d74d MT |
1107 | |
1108 | write_seqcount_begin(&vdata->seq); | |
1109 | ||
1110 | /* copy pvclock gtod data */ | |
876e7881 PZ |
1111 | vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; |
1112 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; | |
1113 | vdata->clock.mask = tk->tkr_mono.mask; | |
1114 | vdata->clock.mult = tk->tkr_mono.mult; | |
1115 | vdata->clock.shift = tk->tkr_mono.shift; | |
16e8d74d | 1116 | |
cbcf2dd3 | 1117 | vdata->boot_ns = boot_ns; |
876e7881 | 1118 | vdata->nsec_base = tk->tkr_mono.xtime_nsec; |
16e8d74d MT |
1119 | |
1120 | write_seqcount_end(&vdata->seq); | |
1121 | } | |
1122 | #endif | |
1123 | ||
bab5bb39 NK |
1124 | void kvm_set_pending_timer(struct kvm_vcpu *vcpu) |
1125 | { | |
1126 | /* | |
1127 | * Note: KVM_REQ_PENDING_TIMER is implicitly checked in | |
1128 | * vcpu_enter_guest. This function is only called from | |
1129 | * the physical CPU that is running vcpu. | |
1130 | */ | |
1131 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
1132 | } | |
16e8d74d | 1133 | |
18068523 GOC |
1134 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1135 | { | |
9ed3c444 AK |
1136 | int version; |
1137 | int r; | |
50d0a0f9 | 1138 | struct pvclock_wall_clock wc; |
923de3cf | 1139 | struct timespec boot; |
18068523 GOC |
1140 | |
1141 | if (!wall_clock) | |
1142 | return; | |
1143 | ||
9ed3c444 AK |
1144 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1145 | if (r) | |
1146 | return; | |
1147 | ||
1148 | if (version & 1) | |
1149 | ++version; /* first time write, random junk */ | |
1150 | ||
1151 | ++version; | |
18068523 | 1152 | |
18068523 GOC |
1153 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
1154 | ||
50d0a0f9 GH |
1155 | /* |
1156 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1157 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
1158 | * wall clock specified here. guest system time equals host |
1159 | * system time for us, thus we must fill in host boot time here. | |
1160 | */ | |
923de3cf | 1161 | getboottime(&boot); |
50d0a0f9 | 1162 | |
4b648665 BR |
1163 | if (kvm->arch.kvmclock_offset) { |
1164 | struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); | |
1165 | boot = timespec_sub(boot, ts); | |
1166 | } | |
50d0a0f9 GH |
1167 | wc.sec = boot.tv_sec; |
1168 | wc.nsec = boot.tv_nsec; | |
1169 | wc.version = version; | |
18068523 GOC |
1170 | |
1171 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1172 | ||
1173 | version++; | |
1174 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1175 | } |
1176 | ||
50d0a0f9 GH |
1177 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
1178 | { | |
1179 | uint32_t quotient, remainder; | |
1180 | ||
1181 | /* Don't try to replace with do_div(), this one calculates | |
1182 | * "(dividend << 32) / divisor" */ | |
1183 | __asm__ ( "divl %4" | |
1184 | : "=a" (quotient), "=d" (remainder) | |
1185 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
1186 | return quotient; | |
1187 | } | |
1188 | ||
5f4e3f88 ZA |
1189 | static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, |
1190 | s8 *pshift, u32 *pmultiplier) | |
50d0a0f9 | 1191 | { |
5f4e3f88 | 1192 | uint64_t scaled64; |
50d0a0f9 GH |
1193 | int32_t shift = 0; |
1194 | uint64_t tps64; | |
1195 | uint32_t tps32; | |
1196 | ||
5f4e3f88 ZA |
1197 | tps64 = base_khz * 1000LL; |
1198 | scaled64 = scaled_khz * 1000LL; | |
50933623 | 1199 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
1200 | tps64 >>= 1; |
1201 | shift--; | |
1202 | } | |
1203 | ||
1204 | tps32 = (uint32_t)tps64; | |
50933623 JK |
1205 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
1206 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
1207 | scaled64 >>= 1; |
1208 | else | |
1209 | tps32 <<= 1; | |
50d0a0f9 GH |
1210 | shift++; |
1211 | } | |
1212 | ||
5f4e3f88 ZA |
1213 | *pshift = shift; |
1214 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 | 1215 | |
5f4e3f88 ZA |
1216 | pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", |
1217 | __func__, base_khz, scaled_khz, shift, *pmultiplier); | |
50d0a0f9 GH |
1218 | } |
1219 | ||
759379dd ZA |
1220 | static inline u64 get_kernel_ns(void) |
1221 | { | |
bb0b5812 | 1222 | return ktime_get_boot_ns(); |
50d0a0f9 GH |
1223 | } |
1224 | ||
d828199e | 1225 | #ifdef CONFIG_X86_64 |
16e8d74d | 1226 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 1227 | #endif |
16e8d74d | 1228 | |
c8076604 | 1229 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 1230 | static unsigned long max_tsc_khz; |
c8076604 | 1231 | |
cc578287 | 1232 | static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) |
8cfdc000 | 1233 | { |
cc578287 ZA |
1234 | return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, |
1235 | vcpu->arch.virtual_tsc_shift); | |
8cfdc000 ZA |
1236 | } |
1237 | ||
cc578287 | 1238 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 1239 | { |
cc578287 ZA |
1240 | u64 v = (u64)khz * (1000000 + ppm); |
1241 | do_div(v, 1000000); | |
1242 | return v; | |
1e993611 JR |
1243 | } |
1244 | ||
cc578287 | 1245 | static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) |
759379dd | 1246 | { |
cc578287 ZA |
1247 | u32 thresh_lo, thresh_hi; |
1248 | int use_scaling = 0; | |
217fc9cf | 1249 | |
03ba32ca MT |
1250 | /* tsc_khz can be zero if TSC calibration fails */ |
1251 | if (this_tsc_khz == 0) | |
1252 | return; | |
1253 | ||
c285545f ZA |
1254 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
1255 | kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, | |
cc578287 ZA |
1256 | &vcpu->arch.virtual_tsc_shift, |
1257 | &vcpu->arch.virtual_tsc_mult); | |
1258 | vcpu->arch.virtual_tsc_khz = this_tsc_khz; | |
1259 | ||
1260 | /* | |
1261 | * Compute the variation in TSC rate which is acceptable | |
1262 | * within the range of tolerance and decide if the | |
1263 | * rate being applied is within that bounds of the hardware | |
1264 | * rate. If so, no scaling or compensation need be done. | |
1265 | */ | |
1266 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1267 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
1268 | if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { | |
1269 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); | |
1270 | use_scaling = 1; | |
1271 | } | |
1272 | kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); | |
c285545f ZA |
1273 | } |
1274 | ||
1275 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1276 | { | |
e26101b1 | 1277 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1278 | vcpu->arch.virtual_tsc_mult, |
1279 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1280 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1281 | return tsc; |
1282 | } | |
1283 | ||
69b0049a | 1284 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
1285 | { |
1286 | #ifdef CONFIG_X86_64 | |
1287 | bool vcpus_matched; | |
b48aa97e MT |
1288 | struct kvm_arch *ka = &vcpu->kvm->arch; |
1289 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1290 | ||
1291 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1292 | atomic_read(&vcpu->kvm->online_vcpus)); | |
1293 | ||
7f187922 MT |
1294 | /* |
1295 | * Once the masterclock is enabled, always perform request in | |
1296 | * order to update it. | |
1297 | * | |
1298 | * In order to enable masterclock, the host clocksource must be TSC | |
1299 | * and the vcpus need to have matched TSCs. When that happens, | |
1300 | * perform request to enable masterclock. | |
1301 | */ | |
1302 | if (ka->use_master_clock || | |
1303 | (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) | |
b48aa97e MT |
1304 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1305 | ||
1306 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
1307 | atomic_read(&vcpu->kvm->online_vcpus), | |
1308 | ka->use_master_clock, gtod->clock.vclock_mode); | |
1309 | #endif | |
1310 | } | |
1311 | ||
ba904635 WA |
1312 | static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) |
1313 | { | |
1314 | u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); | |
1315 | vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; | |
1316 | } | |
1317 | ||
8fe8ab46 | 1318 | void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) |
99e3e30a ZA |
1319 | { |
1320 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1321 | u64 offset, ns, elapsed; |
99e3e30a | 1322 | unsigned long flags; |
02626b6a | 1323 | s64 usdiff; |
b48aa97e | 1324 | bool matched; |
0d3da0d2 | 1325 | bool already_matched; |
8fe8ab46 | 1326 | u64 data = msr->data; |
99e3e30a | 1327 | |
038f8c11 | 1328 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
857e4099 | 1329 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); |
759379dd | 1330 | ns = get_kernel_ns(); |
f38e098f | 1331 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 1332 | |
03ba32ca | 1333 | if (vcpu->arch.virtual_tsc_khz) { |
8915aa27 MT |
1334 | int faulted = 0; |
1335 | ||
03ba32ca MT |
1336 | /* n.b - signed multiplication and division required */ |
1337 | usdiff = data - kvm->arch.last_tsc_write; | |
5d3cb0f6 | 1338 | #ifdef CONFIG_X86_64 |
03ba32ca | 1339 | usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; |
5d3cb0f6 | 1340 | #else |
03ba32ca | 1341 | /* do_div() only does unsigned */ |
8915aa27 MT |
1342 | asm("1: idivl %[divisor]\n" |
1343 | "2: xor %%edx, %%edx\n" | |
1344 | " movl $0, %[faulted]\n" | |
1345 | "3:\n" | |
1346 | ".section .fixup,\"ax\"\n" | |
1347 | "4: movl $1, %[faulted]\n" | |
1348 | " jmp 3b\n" | |
1349 | ".previous\n" | |
1350 | ||
1351 | _ASM_EXTABLE(1b, 4b) | |
1352 | ||
1353 | : "=A"(usdiff), [faulted] "=r" (faulted) | |
1354 | : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); | |
1355 | ||
5d3cb0f6 | 1356 | #endif |
03ba32ca MT |
1357 | do_div(elapsed, 1000); |
1358 | usdiff -= elapsed; | |
1359 | if (usdiff < 0) | |
1360 | usdiff = -usdiff; | |
8915aa27 MT |
1361 | |
1362 | /* idivl overflow => difference is larger than USEC_PER_SEC */ | |
1363 | if (faulted) | |
1364 | usdiff = USEC_PER_SEC; | |
03ba32ca MT |
1365 | } else |
1366 | usdiff = USEC_PER_SEC; /* disable TSC match window below */ | |
f38e098f ZA |
1367 | |
1368 | /* | |
5d3cb0f6 ZA |
1369 | * Special case: TSC write with a small delta (1 second) of virtual |
1370 | * cycle time against real time is interpreted as an attempt to | |
1371 | * synchronize the CPU. | |
1372 | * | |
1373 | * For a reliable TSC, we can match TSC offsets, and for an unstable | |
1374 | * TSC, we add elapsed time in this computation. We could let the | |
1375 | * compensation code attempt to catch up if we fall behind, but | |
1376 | * it's better to try to match offsets from the beginning. | |
1377 | */ | |
02626b6a | 1378 | if (usdiff < USEC_PER_SEC && |
5d3cb0f6 | 1379 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
f38e098f | 1380 | if (!check_tsc_unstable()) { |
e26101b1 | 1381 | offset = kvm->arch.cur_tsc_offset; |
f38e098f ZA |
1382 | pr_debug("kvm: matched tsc offset for %llu\n", data); |
1383 | } else { | |
857e4099 | 1384 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 ZA |
1385 | data += delta; |
1386 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); | |
759379dd | 1387 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); |
f38e098f | 1388 | } |
b48aa97e | 1389 | matched = true; |
0d3da0d2 | 1390 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
1391 | } else { |
1392 | /* | |
1393 | * We split periods of matched TSC writes into generations. | |
1394 | * For each generation, we track the original measured | |
1395 | * nanosecond time, offset, and write, so if TSCs are in | |
1396 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 1397 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
1398 | * |
1399 | * These values are tracked in kvm->arch.cur_xxx variables. | |
1400 | */ | |
1401 | kvm->arch.cur_tsc_generation++; | |
1402 | kvm->arch.cur_tsc_nsec = ns; | |
1403 | kvm->arch.cur_tsc_write = data; | |
1404 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 1405 | matched = false; |
0d3da0d2 | 1406 | pr_debug("kvm: new tsc generation %llu, clock %llu\n", |
e26101b1 | 1407 | kvm->arch.cur_tsc_generation, data); |
f38e098f | 1408 | } |
e26101b1 ZA |
1409 | |
1410 | /* | |
1411 | * We also track th most recent recorded KHZ, write and time to | |
1412 | * allow the matching interval to be extended at each write. | |
1413 | */ | |
f38e098f ZA |
1414 | kvm->arch.last_tsc_nsec = ns; |
1415 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 1416 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 1417 | |
b183aa58 | 1418 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
1419 | |
1420 | /* Keep track of which generation this VCPU has synchronized to */ | |
1421 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
1422 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
1423 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
1424 | ||
ba904635 WA |
1425 | if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) |
1426 | update_ia32_tsc_adjust_msr(vcpu, offset); | |
e26101b1 ZA |
1427 | kvm_x86_ops->write_tsc_offset(vcpu, offset); |
1428 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
b48aa97e MT |
1429 | |
1430 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 1431 | if (!matched) { |
b48aa97e | 1432 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
1433 | } else if (!already_matched) { |
1434 | kvm->arch.nr_vcpus_matched_tsc++; | |
1435 | } | |
b48aa97e MT |
1436 | |
1437 | kvm_track_tsc_matching(vcpu); | |
1438 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 1439 | } |
e26101b1 | 1440 | |
99e3e30a ZA |
1441 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
1442 | ||
d828199e MT |
1443 | #ifdef CONFIG_X86_64 |
1444 | ||
1445 | static cycle_t read_tsc(void) | |
1446 | { | |
1447 | cycle_t ret; | |
1448 | u64 last; | |
1449 | ||
1450 | /* | |
1451 | * Empirically, a fence (of type that depends on the CPU) | |
1452 | * before rdtsc is enough to ensure that rdtsc is ordered | |
1453 | * with respect to loads. The various CPU manuals are unclear | |
1454 | * as to whether rdtsc can be reordered with later loads, | |
1455 | * but no one has ever seen it happen. | |
1456 | */ | |
1457 | rdtsc_barrier(); | |
1458 | ret = (cycle_t)vget_cycles(); | |
1459 | ||
1460 | last = pvclock_gtod_data.clock.cycle_last; | |
1461 | ||
1462 | if (likely(ret >= last)) | |
1463 | return ret; | |
1464 | ||
1465 | /* | |
1466 | * GCC likes to generate cmov here, but this branch is extremely | |
1467 | * predictable (it's just a funciton of time and the likely is | |
1468 | * very likely) and there's a data dependence, so force GCC | |
1469 | * to generate a branch instead. I don't barrier() because | |
1470 | * we don't actually need a barrier, and if this function | |
1471 | * ever gets inlined it will generate worse code. | |
1472 | */ | |
1473 | asm volatile (""); | |
1474 | return last; | |
1475 | } | |
1476 | ||
1477 | static inline u64 vgettsc(cycle_t *cycle_now) | |
1478 | { | |
1479 | long v; | |
1480 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1481 | ||
1482 | *cycle_now = read_tsc(); | |
1483 | ||
1484 | v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; | |
1485 | return v * gtod->clock.mult; | |
1486 | } | |
1487 | ||
cbcf2dd3 | 1488 | static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) |
d828199e | 1489 | { |
cbcf2dd3 | 1490 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 1491 | unsigned long seq; |
d828199e | 1492 | int mode; |
cbcf2dd3 | 1493 | u64 ns; |
d828199e | 1494 | |
d828199e MT |
1495 | do { |
1496 | seq = read_seqcount_begin(>od->seq); | |
1497 | mode = gtod->clock.vclock_mode; | |
cbcf2dd3 | 1498 | ns = gtod->nsec_base; |
d828199e MT |
1499 | ns += vgettsc(cycle_now); |
1500 | ns >>= gtod->clock.shift; | |
cbcf2dd3 | 1501 | ns += gtod->boot_ns; |
d828199e | 1502 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 1503 | *t = ns; |
d828199e MT |
1504 | |
1505 | return mode; | |
1506 | } | |
1507 | ||
1508 | /* returns true if host is using tsc clocksource */ | |
1509 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) | |
1510 | { | |
d828199e MT |
1511 | /* checked again under seqlock below */ |
1512 | if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) | |
1513 | return false; | |
1514 | ||
cbcf2dd3 | 1515 | return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; |
d828199e MT |
1516 | } |
1517 | #endif | |
1518 | ||
1519 | /* | |
1520 | * | |
b48aa97e MT |
1521 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
1522 | * across virtual CPUs, the following condition is possible. | |
1523 | * Each numbered line represents an event visible to both | |
d828199e MT |
1524 | * CPUs at the next numbered event. |
1525 | * | |
1526 | * "timespecX" represents host monotonic time. "tscX" represents | |
1527 | * RDTSC value. | |
1528 | * | |
1529 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
1530 | * | |
1531 | * 1. read timespec0,tsc0 | |
1532 | * 2. | timespec1 = timespec0 + N | |
1533 | * | tsc1 = tsc0 + M | |
1534 | * 3. transition to guest | transition to guest | |
1535 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
1536 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
1537 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
1538 | * | |
1539 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
1540 | * | |
1541 | * - ret0 < ret1 | |
1542 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
1543 | * ... | |
1544 | * - 0 < N - M => M < N | |
1545 | * | |
1546 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
1547 | * always the case (the difference between two distinct xtime instances | |
1548 | * might be smaller then the difference between corresponding TSC reads, | |
1549 | * when updating guest vcpus pvclock areas). | |
1550 | * | |
1551 | * To avoid that problem, do not allow visibility of distinct | |
1552 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
1553 | * copy of host monotonic time values. Update that master copy | |
1554 | * in lockstep. | |
1555 | * | |
b48aa97e | 1556 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
1557 | * |
1558 | */ | |
1559 | ||
1560 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
1561 | { | |
1562 | #ifdef CONFIG_X86_64 | |
1563 | struct kvm_arch *ka = &kvm->arch; | |
1564 | int vclock_mode; | |
b48aa97e MT |
1565 | bool host_tsc_clocksource, vcpus_matched; |
1566 | ||
1567 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1568 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
1569 | |
1570 | /* | |
1571 | * If the host uses TSC clock, then passthrough TSC as stable | |
1572 | * to the guest. | |
1573 | */ | |
b48aa97e | 1574 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
1575 | &ka->master_kernel_ns, |
1576 | &ka->master_cycle_now); | |
1577 | ||
16a96021 | 1578 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
54750f2c MT |
1579 | && !backwards_tsc_observed |
1580 | && !ka->boot_vcpu_runs_old_kvmclock; | |
b48aa97e | 1581 | |
d828199e MT |
1582 | if (ka->use_master_clock) |
1583 | atomic_set(&kvm_guest_has_master_clock, 1); | |
1584 | ||
1585 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
1586 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
1587 | vcpus_matched); | |
d828199e MT |
1588 | #endif |
1589 | } | |
1590 | ||
2e762ff7 MT |
1591 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
1592 | { | |
1593 | #ifdef CONFIG_X86_64 | |
1594 | int i; | |
1595 | struct kvm_vcpu *vcpu; | |
1596 | struct kvm_arch *ka = &kvm->arch; | |
1597 | ||
1598 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1599 | kvm_make_mclock_inprogress_request(kvm); | |
1600 | /* no guest entries from this point */ | |
1601 | pvclock_update_vm_gtod_copy(kvm); | |
1602 | ||
1603 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 1604 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
1605 | |
1606 | /* guest entries allowed */ | |
1607 | kvm_for_each_vcpu(i, vcpu, kvm) | |
1608 | clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); | |
1609 | ||
1610 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
1611 | #endif | |
1612 | } | |
1613 | ||
34c238a1 | 1614 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 1615 | { |
d828199e | 1616 | unsigned long flags, this_tsc_khz; |
18068523 | 1617 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 1618 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 1619 | s64 kernel_ns; |
d828199e | 1620 | u64 tsc_timestamp, host_tsc; |
0b79459b | 1621 | struct pvclock_vcpu_time_info guest_hv_clock; |
51d59c6b | 1622 | u8 pvclock_flags; |
d828199e MT |
1623 | bool use_master_clock; |
1624 | ||
1625 | kernel_ns = 0; | |
1626 | host_tsc = 0; | |
18068523 | 1627 | |
d828199e MT |
1628 | /* |
1629 | * If the host uses TSC clock, then passthrough TSC as stable | |
1630 | * to the guest. | |
1631 | */ | |
1632 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1633 | use_master_clock = ka->use_master_clock; | |
1634 | if (use_master_clock) { | |
1635 | host_tsc = ka->master_cycle_now; | |
1636 | kernel_ns = ka->master_kernel_ns; | |
1637 | } | |
1638 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
1639 | |
1640 | /* Keep irq disabled to prevent changes to the clock */ | |
1641 | local_irq_save(flags); | |
89cbc767 | 1642 | this_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
c09664bb MT |
1643 | if (unlikely(this_tsc_khz == 0)) { |
1644 | local_irq_restore(flags); | |
1645 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
1646 | return 1; | |
1647 | } | |
d828199e MT |
1648 | if (!use_master_clock) { |
1649 | host_tsc = native_read_tsc(); | |
1650 | kernel_ns = get_kernel_ns(); | |
1651 | } | |
1652 | ||
1653 | tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc); | |
1654 | ||
c285545f ZA |
1655 | /* |
1656 | * We may have to catch up the TSC to match elapsed wall clock | |
1657 | * time for two reasons, even if kvmclock is used. | |
1658 | * 1) CPU could have been running below the maximum TSC rate | |
1659 | * 2) Broken TSC compensation resets the base at each VCPU | |
1660 | * entry to avoid unknown leaps of TSC even when running | |
1661 | * again on the same CPU. This may cause apparent elapsed | |
1662 | * time to disappear, and the guest to stand still or run | |
1663 | * very slowly. | |
1664 | */ | |
1665 | if (vcpu->tsc_catchup) { | |
1666 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
1667 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 1668 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
1669 | tsc_timestamp = tsc; |
1670 | } | |
50d0a0f9 GH |
1671 | } |
1672 | ||
18068523 GOC |
1673 | local_irq_restore(flags); |
1674 | ||
0b79459b | 1675 | if (!vcpu->pv_time_enabled) |
c285545f | 1676 | return 0; |
18068523 | 1677 | |
e48672fa | 1678 | if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { |
5f4e3f88 ZA |
1679 | kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, |
1680 | &vcpu->hv_clock.tsc_shift, | |
1681 | &vcpu->hv_clock.tsc_to_system_mul); | |
e48672fa | 1682 | vcpu->hw_tsc_khz = this_tsc_khz; |
8cfdc000 ZA |
1683 | } |
1684 | ||
1685 | /* With all the info we got, fill in the values */ | |
1d5f066e | 1686 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 1687 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 1688 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 1689 | |
09a0c3f1 OH |
1690 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
1691 | &guest_hv_clock, sizeof(guest_hv_clock)))) | |
1692 | return 0; | |
1693 | ||
5dca0d91 RK |
1694 | /* This VCPU is paused, but it's legal for a guest to read another |
1695 | * VCPU's kvmclock, so we really have to follow the specification where | |
1696 | * it says that version is odd if data is being modified, and even after | |
1697 | * it is consistent. | |
1698 | * | |
1699 | * Version field updates must be kept separate. This is because | |
1700 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
1701 | * writes within a string instruction are weakly ordered. So there | |
1702 | * are three writes overall. | |
1703 | * | |
1704 | * As a small optimization, only write the version field in the first | |
1705 | * and third write. The vcpu->pv_time cache is still valid, because the | |
1706 | * version field is the first in the struct. | |
18068523 | 1707 | */ |
5dca0d91 RK |
1708 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); |
1709 | ||
1710 | vcpu->hv_clock.version = guest_hv_clock.version + 1; | |
1711 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, | |
1712 | &vcpu->hv_clock, | |
1713 | sizeof(vcpu->hv_clock.version)); | |
1714 | ||
1715 | smp_wmb(); | |
78c0337a MT |
1716 | |
1717 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
0b79459b | 1718 | pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); |
78c0337a MT |
1719 | |
1720 | if (vcpu->pvclock_set_guest_stopped_request) { | |
1721 | pvclock_flags |= PVCLOCK_GUEST_STOPPED; | |
1722 | vcpu->pvclock_set_guest_stopped_request = false; | |
1723 | } | |
1724 | ||
b7e60c5a MT |
1725 | pvclock_flags |= PVCLOCK_COUNTS_FROM_ZERO; |
1726 | ||
d828199e MT |
1727 | /* If the host uses TSC clocksource, then it is stable */ |
1728 | if (use_master_clock) | |
1729 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
1730 | ||
78c0337a MT |
1731 | vcpu->hv_clock.flags = pvclock_flags; |
1732 | ||
ce1a5e60 DM |
1733 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); |
1734 | ||
0b79459b AH |
1735 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
1736 | &vcpu->hv_clock, | |
1737 | sizeof(vcpu->hv_clock)); | |
5dca0d91 RK |
1738 | |
1739 | smp_wmb(); | |
1740 | ||
1741 | vcpu->hv_clock.version++; | |
1742 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, | |
1743 | &vcpu->hv_clock, | |
1744 | sizeof(vcpu->hv_clock.version)); | |
8cfdc000 | 1745 | return 0; |
c8076604 GH |
1746 | } |
1747 | ||
0061d53d MT |
1748 | /* |
1749 | * kvmclock updates which are isolated to a given vcpu, such as | |
1750 | * vcpu->cpu migration, should not allow system_timestamp from | |
1751 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
1752 | * correction applies to one vcpu's system_timestamp but not | |
1753 | * the others. | |
1754 | * | |
1755 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
1756 | * We need to rate-limit these requests though, as they can |
1757 | * considerably slow guests that have a large number of vcpus. | |
1758 | * The time for a remote vcpu to update its kvmclock is bound | |
1759 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
1760 | */ |
1761 | ||
7e44e449 AJ |
1762 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
1763 | ||
1764 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
1765 | { |
1766 | int i; | |
7e44e449 AJ |
1767 | struct delayed_work *dwork = to_delayed_work(work); |
1768 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
1769 | kvmclock_update_work); | |
1770 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
1771 | struct kvm_vcpu *vcpu; |
1772 | ||
1773 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 1774 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
1775 | kvm_vcpu_kick(vcpu); |
1776 | } | |
1777 | } | |
1778 | ||
7e44e449 AJ |
1779 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
1780 | { | |
1781 | struct kvm *kvm = v->kvm; | |
1782 | ||
105b21bb | 1783 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
1784 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
1785 | KVMCLOCK_UPDATE_DELAY); | |
1786 | } | |
1787 | ||
332967a3 AJ |
1788 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
1789 | ||
1790 | static void kvmclock_sync_fn(struct work_struct *work) | |
1791 | { | |
1792 | struct delayed_work *dwork = to_delayed_work(work); | |
1793 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
1794 | kvmclock_sync_work); | |
1795 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
1796 | ||
630994b3 MT |
1797 | if (!kvmclock_periodic_sync) |
1798 | return; | |
1799 | ||
332967a3 AJ |
1800 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
1801 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
1802 | KVMCLOCK_SYNC_PERIOD); | |
1803 | } | |
1804 | ||
890ca9ae | 1805 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1806 | { |
890ca9ae HY |
1807 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1808 | unsigned bank_num = mcg_cap & 0xff; | |
1809 | ||
15c4a640 | 1810 | switch (msr) { |
15c4a640 | 1811 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1812 | vcpu->arch.mcg_status = data; |
15c4a640 | 1813 | break; |
c7ac679c | 1814 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1815 | if (!(mcg_cap & MCG_CTL_P)) |
1816 | return 1; | |
1817 | if (data != 0 && data != ~(u64)0) | |
1818 | return -1; | |
1819 | vcpu->arch.mcg_ctl = data; | |
1820 | break; | |
1821 | default: | |
1822 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 1823 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae | 1824 | u32 offset = msr - MSR_IA32_MC0_CTL; |
114be429 AP |
1825 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1826 | * some Linux kernels though clear bit 10 in bank 4 to | |
1827 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1828 | * this to avoid an uncatched #GP in the guest | |
1829 | */ | |
890ca9ae | 1830 | if ((offset & 0x3) == 0 && |
114be429 | 1831 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
1832 | return -1; |
1833 | vcpu->arch.mce_banks[offset] = data; | |
1834 | break; | |
1835 | } | |
1836 | return 1; | |
1837 | } | |
1838 | return 0; | |
1839 | } | |
1840 | ||
ffde22ac ES |
1841 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
1842 | { | |
1843 | struct kvm *kvm = vcpu->kvm; | |
1844 | int lm = is_long_mode(vcpu); | |
1845 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1846 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1847 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1848 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1849 | u32 page_num = data & ~PAGE_MASK; | |
1850 | u64 page_addr = data & PAGE_MASK; | |
1851 | u8 *page; | |
1852 | int r; | |
1853 | ||
1854 | r = -E2BIG; | |
1855 | if (page_num >= blob_size) | |
1856 | goto out; | |
1857 | r = -ENOMEM; | |
ff5c2c03 SL |
1858 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
1859 | if (IS_ERR(page)) { | |
1860 | r = PTR_ERR(page); | |
ffde22ac | 1861 | goto out; |
ff5c2c03 | 1862 | } |
54bf36aa | 1863 | if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) |
ffde22ac ES |
1864 | goto out_free; |
1865 | r = 0; | |
1866 | out_free: | |
1867 | kfree(page); | |
1868 | out: | |
1869 | return r; | |
1870 | } | |
1871 | ||
55cd8e5a GN |
1872 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
1873 | { | |
1874 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
1875 | } | |
1876 | ||
1877 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
1878 | { | |
1879 | bool r = false; | |
1880 | switch (msr) { | |
1881 | case HV_X64_MSR_GUEST_OS_ID: | |
1882 | case HV_X64_MSR_HYPERCALL: | |
e984097b VR |
1883 | case HV_X64_MSR_REFERENCE_TSC: |
1884 | case HV_X64_MSR_TIME_REF_COUNT: | |
55cd8e5a GN |
1885 | r = true; |
1886 | break; | |
1887 | } | |
1888 | ||
1889 | return r; | |
1890 | } | |
1891 | ||
1892 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1893 | { | |
1894 | struct kvm *kvm = vcpu->kvm; | |
1895 | ||
1896 | switch (msr) { | |
1897 | case HV_X64_MSR_GUEST_OS_ID: | |
1898 | kvm->arch.hv_guest_os_id = data; | |
1899 | /* setting guest os id to zero disables hypercall page */ | |
1900 | if (!kvm->arch.hv_guest_os_id) | |
1901 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
1902 | break; | |
1903 | case HV_X64_MSR_HYPERCALL: { | |
1904 | u64 gfn; | |
1905 | unsigned long addr; | |
1906 | u8 instructions[4]; | |
1907 | ||
1908 | /* if guest os id is not set hypercall should remain disabled */ | |
1909 | if (!kvm->arch.hv_guest_os_id) | |
1910 | break; | |
1911 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
1912 | kvm->arch.hv_hypercall = data; | |
1913 | break; | |
1914 | } | |
1915 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
1916 | addr = gfn_to_hva(kvm, gfn); | |
1917 | if (kvm_is_error_hva(addr)) | |
1918 | return 1; | |
1919 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
1920 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
8b0cedff | 1921 | if (__copy_to_user((void __user *)addr, instructions, 4)) |
55cd8e5a GN |
1922 | return 1; |
1923 | kvm->arch.hv_hypercall = data; | |
b94b64c9 | 1924 | mark_page_dirty(kvm, gfn); |
55cd8e5a GN |
1925 | break; |
1926 | } | |
e984097b VR |
1927 | case HV_X64_MSR_REFERENCE_TSC: { |
1928 | u64 gfn; | |
1929 | HV_REFERENCE_TSC_PAGE tsc_ref; | |
1930 | memset(&tsc_ref, 0, sizeof(tsc_ref)); | |
1931 | kvm->arch.hv_tsc_page = data; | |
1932 | if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE)) | |
1933 | break; | |
1934 | gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT; | |
e1fa108d | 1935 | if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT, |
e984097b VR |
1936 | &tsc_ref, sizeof(tsc_ref))) |
1937 | return 1; | |
1938 | mark_page_dirty(kvm, gfn); | |
1939 | break; | |
1940 | } | |
55cd8e5a | 1941 | default: |
a737f256 CD |
1942 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
1943 | "data 0x%llx\n", msr, data); | |
55cd8e5a GN |
1944 | return 1; |
1945 | } | |
1946 | return 0; | |
1947 | } | |
1948 | ||
1949 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1950 | { | |
10388a07 GN |
1951 | switch (msr) { |
1952 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
b3af1e88 | 1953 | u64 gfn; |
10388a07 | 1954 | unsigned long addr; |
55cd8e5a | 1955 | |
10388a07 GN |
1956 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
1957 | vcpu->arch.hv_vapic = data; | |
b63cf42f MT |
1958 | if (kvm_lapic_enable_pv_eoi(vcpu, 0)) |
1959 | return 1; | |
10388a07 GN |
1960 | break; |
1961 | } | |
b3af1e88 | 1962 | gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT; |
54bf36aa | 1963 | addr = kvm_vcpu_gfn_to_hva(vcpu, gfn); |
10388a07 GN |
1964 | if (kvm_is_error_hva(addr)) |
1965 | return 1; | |
8b0cedff | 1966 | if (__clear_user((void __user *)addr, PAGE_SIZE)) |
10388a07 GN |
1967 | return 1; |
1968 | vcpu->arch.hv_vapic = data; | |
54bf36aa | 1969 | kvm_vcpu_mark_page_dirty(vcpu, gfn); |
b63cf42f MT |
1970 | if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED)) |
1971 | return 1; | |
10388a07 GN |
1972 | break; |
1973 | } | |
1974 | case HV_X64_MSR_EOI: | |
1975 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
1976 | case HV_X64_MSR_ICR: | |
1977 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
1978 | case HV_X64_MSR_TPR: | |
1979 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
1980 | default: | |
a737f256 CD |
1981 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
1982 | "data 0x%llx\n", msr, data); | |
10388a07 GN |
1983 | return 1; |
1984 | } | |
1985 | ||
1986 | return 0; | |
55cd8e5a GN |
1987 | } |
1988 | ||
344d9588 GN |
1989 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
1990 | { | |
1991 | gpa_t gpa = data & ~0x3f; | |
1992 | ||
4a969980 | 1993 | /* Bits 2:5 are reserved, Should be zero */ |
6adba527 | 1994 | if (data & 0x3c) |
344d9588 GN |
1995 | return 1; |
1996 | ||
1997 | vcpu->arch.apf.msr_val = data; | |
1998 | ||
1999 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
2000 | kvm_clear_async_pf_completion_queue(vcpu); | |
2001 | kvm_async_pf_hash_reset(vcpu); | |
2002 | return 0; | |
2003 | } | |
2004 | ||
8f964525 AH |
2005 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
2006 | sizeof(u32))) | |
344d9588 GN |
2007 | return 1; |
2008 | ||
6adba527 | 2009 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
344d9588 GN |
2010 | kvm_async_pf_wakeup_all(vcpu); |
2011 | return 0; | |
2012 | } | |
2013 | ||
12f9a48f GC |
2014 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2015 | { | |
0b79459b | 2016 | vcpu->arch.pv_time_enabled = false; |
12f9a48f GC |
2017 | } |
2018 | ||
c9aaa895 GC |
2019 | static void accumulate_steal_time(struct kvm_vcpu *vcpu) |
2020 | { | |
2021 | u64 delta; | |
2022 | ||
2023 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2024 | return; | |
2025 | ||
2026 | delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; | |
2027 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
2028 | vcpu->arch.st.accum_steal = delta; | |
2029 | } | |
2030 | ||
2031 | static void record_steal_time(struct kvm_vcpu *vcpu) | |
2032 | { | |
2033 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2034 | return; | |
2035 | ||
2036 | if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2037 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) | |
2038 | return; | |
2039 | ||
2040 | vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; | |
2041 | vcpu->arch.st.steal.version += 2; | |
2042 | vcpu->arch.st.accum_steal = 0; | |
2043 | ||
2044 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2045 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); | |
2046 | } | |
2047 | ||
8fe8ab46 | 2048 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2049 | { |
5753785f | 2050 | bool pr = false; |
8fe8ab46 WA |
2051 | u32 msr = msr_info->index; |
2052 | u64 data = msr_info->data; | |
5753785f | 2053 | |
15c4a640 | 2054 | switch (msr) { |
2e32b719 BP |
2055 | case MSR_AMD64_NB_CFG: |
2056 | case MSR_IA32_UCODE_REV: | |
2057 | case MSR_IA32_UCODE_WRITE: | |
2058 | case MSR_VM_HSAVE_PA: | |
2059 | case MSR_AMD64_PATCH_LOADER: | |
2060 | case MSR_AMD64_BU_CFG2: | |
2061 | break; | |
2062 | ||
15c4a640 | 2063 | case MSR_EFER: |
b69e8cae | 2064 | return set_efer(vcpu, data); |
8f1589d9 AP |
2065 | case MSR_K7_HWCR: |
2066 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 2067 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 2068 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
22d48b2d | 2069 | data &= ~(u64)0x40000; /* ignore Mc status write enable */ |
8f1589d9 | 2070 | if (data != 0) { |
a737f256 CD |
2071 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
2072 | data); | |
8f1589d9 AP |
2073 | return 1; |
2074 | } | |
15c4a640 | 2075 | break; |
f7c6d140 AP |
2076 | case MSR_FAM10H_MMIO_CONF_BASE: |
2077 | if (data != 0) { | |
a737f256 CD |
2078 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
2079 | "0x%llx\n", data); | |
f7c6d140 AP |
2080 | return 1; |
2081 | } | |
15c4a640 | 2082 | break; |
b5e2fec0 AG |
2083 | case MSR_IA32_DEBUGCTLMSR: |
2084 | if (!data) { | |
2085 | /* We support the non-activated case already */ | |
2086 | break; | |
2087 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
2088 | /* Values other than LBR and BTF are vendor-specific, | |
2089 | thus reserved and should throw a #GP */ | |
2090 | return 1; | |
2091 | } | |
a737f256 CD |
2092 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
2093 | __func__, data); | |
b5e2fec0 | 2094 | break; |
9ba075a6 | 2095 | case 0x200 ... 0x2ff: |
ff53604b | 2096 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 2097 | case MSR_IA32_APICBASE: |
58cb628d | 2098 | return kvm_set_apic_base(vcpu, msr_info); |
0105d1a5 GN |
2099 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2100 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
a3e06bbe LJ |
2101 | case MSR_IA32_TSCDEADLINE: |
2102 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2103 | break; | |
ba904635 WA |
2104 | case MSR_IA32_TSC_ADJUST: |
2105 | if (guest_cpuid_has_tsc_adjust(vcpu)) { | |
2106 | if (!msr_info->host_initiated) { | |
d913b904 | 2107 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 WA |
2108 | kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true); |
2109 | } | |
2110 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
2111 | } | |
2112 | break; | |
15c4a640 | 2113 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 2114 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 2115 | break; |
64d60670 PB |
2116 | case MSR_IA32_SMBASE: |
2117 | if (!msr_info->host_initiated) | |
2118 | return 1; | |
2119 | vcpu->arch.smbase = data; | |
2120 | break; | |
11c6bffa | 2121 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2122 | case MSR_KVM_WALL_CLOCK: |
2123 | vcpu->kvm->arch.wall_clock = data; | |
2124 | kvm_write_wall_clock(vcpu->kvm, data); | |
2125 | break; | |
11c6bffa | 2126 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 2127 | case MSR_KVM_SYSTEM_TIME: { |
0b79459b | 2128 | u64 gpa_offset; |
54750f2c MT |
2129 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2130 | ||
12f9a48f | 2131 | kvmclock_reset(vcpu); |
18068523 | 2132 | |
54750f2c MT |
2133 | if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { |
2134 | bool tmp = (msr == MSR_KVM_SYSTEM_TIME); | |
2135 | ||
2136 | if (ka->boot_vcpu_runs_old_kvmclock != tmp) | |
2137 | set_bit(KVM_REQ_MASTERCLOCK_UPDATE, | |
2138 | &vcpu->requests); | |
2139 | ||
2140 | ka->boot_vcpu_runs_old_kvmclock = tmp; | |
b7e60c5a MT |
2141 | |
2142 | ka->kvmclock_offset = -get_kernel_ns(); | |
54750f2c MT |
2143 | } |
2144 | ||
18068523 | 2145 | vcpu->arch.time = data; |
0061d53d | 2146 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
18068523 GOC |
2147 | |
2148 | /* we verify if the enable bit is set... */ | |
2149 | if (!(data & 1)) | |
2150 | break; | |
2151 | ||
0b79459b | 2152 | gpa_offset = data & ~(PAGE_MASK | 1); |
18068523 | 2153 | |
0b79459b | 2154 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
8f964525 AH |
2155 | &vcpu->arch.pv_time, data & ~1ULL, |
2156 | sizeof(struct pvclock_vcpu_time_info))) | |
0b79459b AH |
2157 | vcpu->arch.pv_time_enabled = false; |
2158 | else | |
2159 | vcpu->arch.pv_time_enabled = true; | |
32cad84f | 2160 | |
18068523 GOC |
2161 | break; |
2162 | } | |
344d9588 GN |
2163 | case MSR_KVM_ASYNC_PF_EN: |
2164 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
2165 | return 1; | |
2166 | break; | |
c9aaa895 GC |
2167 | case MSR_KVM_STEAL_TIME: |
2168 | ||
2169 | if (unlikely(!sched_info_on())) | |
2170 | return 1; | |
2171 | ||
2172 | if (data & KVM_STEAL_RESERVED_MASK) | |
2173 | return 1; | |
2174 | ||
2175 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, | |
8f964525 AH |
2176 | data & KVM_STEAL_VALID_BITS, |
2177 | sizeof(struct kvm_steal_time))) | |
c9aaa895 GC |
2178 | return 1; |
2179 | ||
2180 | vcpu->arch.st.msr_val = data; | |
2181 | ||
2182 | if (!(data & KVM_MSR_ENABLED)) | |
2183 | break; | |
2184 | ||
2185 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
2186 | ||
2187 | preempt_disable(); | |
2188 | accumulate_steal_time(vcpu); | |
2189 | preempt_enable(); | |
2190 | ||
2191 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
2192 | ||
2193 | break; | |
ae7a2a3f MT |
2194 | case MSR_KVM_PV_EOI_EN: |
2195 | if (kvm_lapic_enable_pv_eoi(vcpu, data)) | |
2196 | return 1; | |
2197 | break; | |
c9aaa895 | 2198 | |
890ca9ae HY |
2199 | case MSR_IA32_MCG_CTL: |
2200 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2201 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
890ca9ae | 2202 | return set_msr_mce(vcpu, msr, data); |
71db6023 AP |
2203 | |
2204 | /* Performance counters are not protected by a CPUID bit, | |
2205 | * so we should check all of them in the generic path for the sake of | |
2206 | * cross vendor migration. | |
2207 | * Writing a zero into the event select MSRs disables them, | |
2208 | * which we perfectly emulate ;-). Any other value should be at least | |
2209 | * reported, some guests depend on them. | |
2210 | */ | |
71db6023 AP |
2211 | case MSR_K7_EVNTSEL0: |
2212 | case MSR_K7_EVNTSEL1: | |
2213 | case MSR_K7_EVNTSEL2: | |
2214 | case MSR_K7_EVNTSEL3: | |
2215 | if (data != 0) | |
a737f256 CD |
2216 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
2217 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 AP |
2218 | break; |
2219 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
2220 | * so we ignore writes to make it happy. | |
2221 | */ | |
71db6023 AP |
2222 | case MSR_K7_PERFCTR0: |
2223 | case MSR_K7_PERFCTR1: | |
2224 | case MSR_K7_PERFCTR2: | |
2225 | case MSR_K7_PERFCTR3: | |
a737f256 CD |
2226 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
2227 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 | 2228 | break; |
5753785f GN |
2229 | case MSR_P6_PERFCTR0: |
2230 | case MSR_P6_PERFCTR1: | |
2231 | pr = true; | |
2232 | case MSR_P6_EVNTSEL0: | |
2233 | case MSR_P6_EVNTSEL1: | |
2234 | if (kvm_pmu_msr(vcpu, msr)) | |
afd80d85 | 2235 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
2236 | |
2237 | if (pr || data != 0) | |
a737f256 CD |
2238 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
2239 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 2240 | break; |
84e0cefa JS |
2241 | case MSR_K7_CLK_CTL: |
2242 | /* | |
2243 | * Ignore all writes to this no longer documented MSR. | |
2244 | * Writes are only relevant for old K7 processors, | |
2245 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 2246 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
2247 | * affected processor models on the command line, hence |
2248 | * the need to ignore the workaround. | |
2249 | */ | |
2250 | break; | |
55cd8e5a GN |
2251 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
2252 | if (kvm_hv_msr_partition_wide(msr)) { | |
2253 | int r; | |
2254 | mutex_lock(&vcpu->kvm->lock); | |
2255 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
2256 | mutex_unlock(&vcpu->kvm->lock); | |
2257 | return r; | |
2258 | } else | |
2259 | return set_msr_hyperv(vcpu, msr, data); | |
2260 | break; | |
91c9c3ed | 2261 | case MSR_IA32_BBL_CR_CTL3: |
2262 | /* Drop writes to this legacy MSR -- see rdmsr | |
2263 | * counterpart for further detail. | |
2264 | */ | |
a737f256 | 2265 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); |
91c9c3ed | 2266 | break; |
2b036c6b BO |
2267 | case MSR_AMD64_OSVW_ID_LENGTH: |
2268 | if (!guest_cpuid_has_osvw(vcpu)) | |
2269 | return 1; | |
2270 | vcpu->arch.osvw.length = data; | |
2271 | break; | |
2272 | case MSR_AMD64_OSVW_STATUS: | |
2273 | if (!guest_cpuid_has_osvw(vcpu)) | |
2274 | return 1; | |
2275 | vcpu->arch.osvw.status = data; | |
2276 | break; | |
15c4a640 | 2277 | default: |
ffde22ac ES |
2278 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
2279 | return xen_hvm_config(vcpu, data); | |
f5132b01 | 2280 | if (kvm_pmu_msr(vcpu, msr)) |
afd80d85 | 2281 | return kvm_pmu_set_msr(vcpu, msr_info); |
ed85c068 | 2282 | if (!ignore_msrs) { |
a737f256 CD |
2283 | vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", |
2284 | msr, data); | |
ed85c068 AP |
2285 | return 1; |
2286 | } else { | |
a737f256 CD |
2287 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", |
2288 | msr, data); | |
ed85c068 AP |
2289 | break; |
2290 | } | |
15c4a640 CO |
2291 | } |
2292 | return 0; | |
2293 | } | |
2294 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
2295 | ||
2296 | ||
2297 | /* | |
2298 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2299 | * Returns 0 on success, non-0 otherwise. | |
2300 | * Assumes vcpu_load() was already called. | |
2301 | */ | |
609e36d3 | 2302 | int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 2303 | { |
609e36d3 | 2304 | return kvm_x86_ops->get_msr(vcpu, msr); |
15c4a640 | 2305 | } |
ff651cb6 | 2306 | EXPORT_SYMBOL_GPL(kvm_get_msr); |
15c4a640 | 2307 | |
890ca9ae | 2308 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
2309 | { |
2310 | u64 data; | |
890ca9ae HY |
2311 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2312 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
2313 | |
2314 | switch (msr) { | |
15c4a640 CO |
2315 | case MSR_IA32_P5_MC_ADDR: |
2316 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
2317 | data = 0; |
2318 | break; | |
15c4a640 | 2319 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
2320 | data = vcpu->arch.mcg_cap; |
2321 | break; | |
c7ac679c | 2322 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
2323 | if (!(mcg_cap & MCG_CTL_P)) |
2324 | return 1; | |
2325 | data = vcpu->arch.mcg_ctl; | |
2326 | break; | |
2327 | case MSR_IA32_MCG_STATUS: | |
2328 | data = vcpu->arch.mcg_status; | |
2329 | break; | |
2330 | default: | |
2331 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2332 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae HY |
2333 | u32 offset = msr - MSR_IA32_MC0_CTL; |
2334 | data = vcpu->arch.mce_banks[offset]; | |
2335 | break; | |
2336 | } | |
2337 | return 1; | |
2338 | } | |
2339 | *pdata = data; | |
2340 | return 0; | |
2341 | } | |
2342 | ||
55cd8e5a GN |
2343 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2344 | { | |
2345 | u64 data = 0; | |
2346 | struct kvm *kvm = vcpu->kvm; | |
2347 | ||
2348 | switch (msr) { | |
2349 | case HV_X64_MSR_GUEST_OS_ID: | |
2350 | data = kvm->arch.hv_guest_os_id; | |
2351 | break; | |
2352 | case HV_X64_MSR_HYPERCALL: | |
2353 | data = kvm->arch.hv_hypercall; | |
2354 | break; | |
e984097b VR |
2355 | case HV_X64_MSR_TIME_REF_COUNT: { |
2356 | data = | |
2357 | div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100); | |
2358 | break; | |
2359 | } | |
2360 | case HV_X64_MSR_REFERENCE_TSC: | |
2361 | data = kvm->arch.hv_tsc_page; | |
2362 | break; | |
55cd8e5a | 2363 | default: |
a737f256 | 2364 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
2365 | return 1; |
2366 | } | |
2367 | ||
2368 | *pdata = data; | |
2369 | return 0; | |
2370 | } | |
2371 | ||
2372 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
2373 | { | |
2374 | u64 data = 0; | |
2375 | ||
2376 | switch (msr) { | |
2377 | case HV_X64_MSR_VP_INDEX: { | |
2378 | int r; | |
2379 | struct kvm_vcpu *v; | |
684851a1 TY |
2380 | kvm_for_each_vcpu(r, v, vcpu->kvm) { |
2381 | if (v == vcpu) { | |
55cd8e5a | 2382 | data = r; |
684851a1 TY |
2383 | break; |
2384 | } | |
2385 | } | |
55cd8e5a GN |
2386 | break; |
2387 | } | |
10388a07 GN |
2388 | case HV_X64_MSR_EOI: |
2389 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
2390 | case HV_X64_MSR_ICR: | |
2391 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
2392 | case HV_X64_MSR_TPR: | |
2393 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
14fa67ee | 2394 | case HV_X64_MSR_APIC_ASSIST_PAGE: |
d1613ad5 MW |
2395 | data = vcpu->arch.hv_vapic; |
2396 | break; | |
55cd8e5a | 2397 | default: |
a737f256 | 2398 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
2399 | return 1; |
2400 | } | |
2401 | *pdata = data; | |
2402 | return 0; | |
2403 | } | |
2404 | ||
609e36d3 | 2405 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae HY |
2406 | { |
2407 | u64 data; | |
2408 | ||
609e36d3 | 2409 | switch (msr_info->index) { |
890ca9ae | 2410 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 2411 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
2412 | case MSR_IA32_DEBUGCTLMSR: |
2413 | case MSR_IA32_LASTBRANCHFROMIP: | |
2414 | case MSR_IA32_LASTBRANCHTOIP: | |
2415 | case MSR_IA32_LASTINTFROMIP: | |
2416 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
2417 | case MSR_K8_SYSCFG: |
2418 | case MSR_K7_HWCR: | |
61a6bd67 | 2419 | case MSR_VM_HSAVE_PA: |
9e699624 | 2420 | case MSR_K7_EVNTSEL0: |
dc9b2d93 WH |
2421 | case MSR_K7_EVNTSEL1: |
2422 | case MSR_K7_EVNTSEL2: | |
2423 | case MSR_K7_EVNTSEL3: | |
1f3ee616 | 2424 | case MSR_K7_PERFCTR0: |
dc9b2d93 WH |
2425 | case MSR_K7_PERFCTR1: |
2426 | case MSR_K7_PERFCTR2: | |
2427 | case MSR_K7_PERFCTR3: | |
1fdbd48c | 2428 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 2429 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 2430 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 2431 | case MSR_AMD64_BU_CFG2: |
609e36d3 | 2432 | msr_info->data = 0; |
15c4a640 | 2433 | break; |
5753785f GN |
2434 | case MSR_P6_PERFCTR0: |
2435 | case MSR_P6_PERFCTR1: | |
2436 | case MSR_P6_EVNTSEL0: | |
2437 | case MSR_P6_EVNTSEL1: | |
609e36d3 PB |
2438 | if (kvm_pmu_msr(vcpu, msr_info->index)) |
2439 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); | |
2440 | msr_info->data = 0; | |
5753785f | 2441 | break; |
742bc670 | 2442 | case MSR_IA32_UCODE_REV: |
609e36d3 | 2443 | msr_info->data = 0x100000000ULL; |
742bc670 | 2444 | break; |
9ba075a6 | 2445 | case MSR_MTRRcap: |
9ba075a6 | 2446 | case 0x200 ... 0x2ff: |
ff53604b | 2447 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 2448 | case 0xcd: /* fsb frequency */ |
609e36d3 | 2449 | msr_info->data = 3; |
15c4a640 | 2450 | break; |
7b914098 JS |
2451 | /* |
2452 | * MSR_EBC_FREQUENCY_ID | |
2453 | * Conservative value valid for even the basic CPU models. | |
2454 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
2455 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
2456 | * and 266MHz for model 3, or 4. Set Core Clock | |
2457 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
2458 | * 31:24) even though these are only valid for CPU | |
2459 | * models > 2, however guests may end up dividing or | |
2460 | * multiplying by zero otherwise. | |
2461 | */ | |
2462 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 2463 | msr_info->data = 1 << 24; |
7b914098 | 2464 | break; |
15c4a640 | 2465 | case MSR_IA32_APICBASE: |
609e36d3 | 2466 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 2467 | break; |
0105d1a5 | 2468 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
609e36d3 | 2469 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
0105d1a5 | 2470 | break; |
a3e06bbe | 2471 | case MSR_IA32_TSCDEADLINE: |
609e36d3 | 2472 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 2473 | break; |
ba904635 | 2474 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 2475 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 2476 | break; |
15c4a640 | 2477 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 2478 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 2479 | break; |
64d60670 PB |
2480 | case MSR_IA32_SMBASE: |
2481 | if (!msr_info->host_initiated) | |
2482 | return 1; | |
2483 | msr_info->data = vcpu->arch.smbase; | |
2484 | break; | |
847f0ad8 AG |
2485 | case MSR_IA32_PERF_STATUS: |
2486 | /* TSC increment by tick */ | |
609e36d3 | 2487 | msr_info->data = 1000ULL; |
847f0ad8 AG |
2488 | /* CPU multiplier */ |
2489 | data |= (((uint64_t)4ULL) << 40); | |
2490 | break; | |
15c4a640 | 2491 | case MSR_EFER: |
609e36d3 | 2492 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 2493 | break; |
18068523 | 2494 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 2495 | case MSR_KVM_WALL_CLOCK_NEW: |
609e36d3 | 2496 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
2497 | break; |
2498 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 2499 | case MSR_KVM_SYSTEM_TIME_NEW: |
609e36d3 | 2500 | msr_info->data = vcpu->arch.time; |
18068523 | 2501 | break; |
344d9588 | 2502 | case MSR_KVM_ASYNC_PF_EN: |
609e36d3 | 2503 | msr_info->data = vcpu->arch.apf.msr_val; |
344d9588 | 2504 | break; |
c9aaa895 | 2505 | case MSR_KVM_STEAL_TIME: |
609e36d3 | 2506 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 2507 | break; |
1d92128f | 2508 | case MSR_KVM_PV_EOI_EN: |
609e36d3 | 2509 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 2510 | break; |
890ca9ae HY |
2511 | case MSR_IA32_P5_MC_ADDR: |
2512 | case MSR_IA32_P5_MC_TYPE: | |
2513 | case MSR_IA32_MCG_CAP: | |
2514 | case MSR_IA32_MCG_CTL: | |
2515 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2516 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
609e36d3 | 2517 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data); |
84e0cefa JS |
2518 | case MSR_K7_CLK_CTL: |
2519 | /* | |
2520 | * Provide expected ramp-up count for K7. All other | |
2521 | * are set to zero, indicating minimum divisors for | |
2522 | * every field. | |
2523 | * | |
2524 | * This prevents guest kernels on AMD host with CPU | |
2525 | * type 6, model 8 and higher from exploding due to | |
2526 | * the rdmsr failing. | |
2527 | */ | |
609e36d3 | 2528 | msr_info->data = 0x20000000; |
84e0cefa | 2529 | break; |
55cd8e5a | 2530 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
609e36d3 | 2531 | if (kvm_hv_msr_partition_wide(msr_info->index)) { |
55cd8e5a GN |
2532 | int r; |
2533 | mutex_lock(&vcpu->kvm->lock); | |
609e36d3 | 2534 | r = get_msr_hyperv_pw(vcpu, msr_info->index, &msr_info->data); |
55cd8e5a GN |
2535 | mutex_unlock(&vcpu->kvm->lock); |
2536 | return r; | |
2537 | } else | |
609e36d3 | 2538 | return get_msr_hyperv(vcpu, msr_info->index, &msr_info->data); |
55cd8e5a | 2539 | break; |
91c9c3ed | 2540 | case MSR_IA32_BBL_CR_CTL3: |
2541 | /* This legacy MSR exists but isn't fully documented in current | |
2542 | * silicon. It is however accessed by winxp in very narrow | |
2543 | * scenarios where it sets bit #19, itself documented as | |
2544 | * a "reserved" bit. Best effort attempt to source coherent | |
2545 | * read data here should the balance of the register be | |
2546 | * interpreted by the guest: | |
2547 | * | |
2548 | * L2 cache control register 3: 64GB range, 256KB size, | |
2549 | * enabled, latency 0x1, configured | |
2550 | */ | |
609e36d3 | 2551 | msr_info->data = 0xbe702111; |
91c9c3ed | 2552 | break; |
2b036c6b BO |
2553 | case MSR_AMD64_OSVW_ID_LENGTH: |
2554 | if (!guest_cpuid_has_osvw(vcpu)) | |
2555 | return 1; | |
609e36d3 | 2556 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
2557 | break; |
2558 | case MSR_AMD64_OSVW_STATUS: | |
2559 | if (!guest_cpuid_has_osvw(vcpu)) | |
2560 | return 1; | |
609e36d3 | 2561 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 2562 | break; |
15c4a640 | 2563 | default: |
609e36d3 PB |
2564 | if (kvm_pmu_msr(vcpu, msr_info->index)) |
2565 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); | |
ed85c068 | 2566 | if (!ignore_msrs) { |
609e36d3 | 2567 | vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index); |
ed85c068 AP |
2568 | return 1; |
2569 | } else { | |
609e36d3 PB |
2570 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index); |
2571 | msr_info->data = 0; | |
ed85c068 AP |
2572 | } |
2573 | break; | |
15c4a640 | 2574 | } |
15c4a640 CO |
2575 | return 0; |
2576 | } | |
2577 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
2578 | ||
313a3dc7 CO |
2579 | /* |
2580 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
2581 | * | |
2582 | * @return number of msrs set successfully. | |
2583 | */ | |
2584 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
2585 | struct kvm_msr_entry *entries, | |
2586 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2587 | unsigned index, u64 *data)) | |
2588 | { | |
f656ce01 | 2589 | int i, idx; |
313a3dc7 | 2590 | |
f656ce01 | 2591 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
2592 | for (i = 0; i < msrs->nmsrs; ++i) |
2593 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
2594 | break; | |
f656ce01 | 2595 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 2596 | |
313a3dc7 CO |
2597 | return i; |
2598 | } | |
2599 | ||
2600 | /* | |
2601 | * Read or write a bunch of msrs. Parameters are user addresses. | |
2602 | * | |
2603 | * @return number of msrs set successfully. | |
2604 | */ | |
2605 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
2606 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2607 | unsigned index, u64 *data), | |
2608 | int writeback) | |
2609 | { | |
2610 | struct kvm_msrs msrs; | |
2611 | struct kvm_msr_entry *entries; | |
2612 | int r, n; | |
2613 | unsigned size; | |
2614 | ||
2615 | r = -EFAULT; | |
2616 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
2617 | goto out; | |
2618 | ||
2619 | r = -E2BIG; | |
2620 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
2621 | goto out; | |
2622 | ||
313a3dc7 | 2623 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
2624 | entries = memdup_user(user_msrs->entries, size); |
2625 | if (IS_ERR(entries)) { | |
2626 | r = PTR_ERR(entries); | |
313a3dc7 | 2627 | goto out; |
ff5c2c03 | 2628 | } |
313a3dc7 CO |
2629 | |
2630 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
2631 | if (r < 0) | |
2632 | goto out_free; | |
2633 | ||
2634 | r = -EFAULT; | |
2635 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
2636 | goto out_free; | |
2637 | ||
2638 | r = n; | |
2639 | ||
2640 | out_free: | |
7a73c028 | 2641 | kfree(entries); |
313a3dc7 CO |
2642 | out: |
2643 | return r; | |
2644 | } | |
2645 | ||
784aa3d7 | 2646 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 ZX |
2647 | { |
2648 | int r; | |
2649 | ||
2650 | switch (ext) { | |
2651 | case KVM_CAP_IRQCHIP: | |
2652 | case KVM_CAP_HLT: | |
2653 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 2654 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 2655 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 2656 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 2657 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 2658 | case KVM_CAP_PIT: |
a28e4f5a | 2659 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 2660 | case KVM_CAP_MP_STATE: |
ed848624 | 2661 | case KVM_CAP_SYNC_MMU: |
a355c85c | 2662 | case KVM_CAP_USER_NMI: |
52d939a0 | 2663 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 2664 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 2665 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 2666 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 2667 | case KVM_CAP_PIT2: |
e9f42757 | 2668 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 2669 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 2670 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 2671 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 2672 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 2673 | case KVM_CAP_HYPERV: |
10388a07 | 2674 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 2675 | case KVM_CAP_HYPERV_SPIN: |
ab9f4ecb | 2676 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 2677 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 2678 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 2679 | case KVM_CAP_XSAVE: |
344d9588 | 2680 | case KVM_CAP_ASYNC_PF: |
92a1f12d | 2681 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 2682 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 2683 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 2684 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 2685 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 2686 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 NA |
2687 | case KVM_CAP_ENABLE_CAP_VM: |
2688 | case KVM_CAP_DISABLE_QUIRKS: | |
2a5bab10 AW |
2689 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
2690 | case KVM_CAP_ASSIGN_DEV_IRQ: | |
2691 | case KVM_CAP_PCI_2_3: | |
2692 | #endif | |
018d00d2 ZX |
2693 | r = 1; |
2694 | break; | |
6d396b55 PB |
2695 | case KVM_CAP_X86_SMM: |
2696 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
2697 | * and SMM handlers might indeed rely on 4G segment limits, | |
2698 | * so do not report SMM to be available if real mode is | |
2699 | * emulated via vm86 mode. Still, do not go to great lengths | |
2700 | * to avoid userspace's usage of the feature, because it is a | |
2701 | * fringe case that is not enabled except via specific settings | |
2702 | * of the module parameters. | |
2703 | */ | |
2704 | r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); | |
2705 | break; | |
542472b5 LV |
2706 | case KVM_CAP_COALESCED_MMIO: |
2707 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
2708 | break; | |
774ead3a AK |
2709 | case KVM_CAP_VAPIC: |
2710 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
2711 | break; | |
f725230a | 2712 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
2713 | r = KVM_SOFT_MAX_VCPUS; |
2714 | break; | |
2715 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
2716 | r = KVM_MAX_VCPUS; |
2717 | break; | |
a988b910 | 2718 | case KVM_CAP_NR_MEMSLOTS: |
bbacc0c1 | 2719 | r = KVM_USER_MEM_SLOTS; |
a988b910 | 2720 | break; |
a68a6a72 MT |
2721 | case KVM_CAP_PV_MMU: /* obsolete */ |
2722 | r = 0; | |
2f333bcb | 2723 | break; |
4cee4b72 | 2724 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
62c476c7 | 2725 | case KVM_CAP_IOMMU: |
a1b60c1c | 2726 | r = iommu_present(&pci_bus_type); |
62c476c7 | 2727 | break; |
4cee4b72 | 2728 | #endif |
890ca9ae HY |
2729 | case KVM_CAP_MCE: |
2730 | r = KVM_MAX_MCE_BANKS; | |
2731 | break; | |
2d5b5a66 SY |
2732 | case KVM_CAP_XCRS: |
2733 | r = cpu_has_xsave; | |
2734 | break; | |
92a1f12d JR |
2735 | case KVM_CAP_TSC_CONTROL: |
2736 | r = kvm_has_tsc_control; | |
2737 | break; | |
018d00d2 ZX |
2738 | default: |
2739 | r = 0; | |
2740 | break; | |
2741 | } | |
2742 | return r; | |
2743 | ||
2744 | } | |
2745 | ||
043405e1 CO |
2746 | long kvm_arch_dev_ioctl(struct file *filp, |
2747 | unsigned int ioctl, unsigned long arg) | |
2748 | { | |
2749 | void __user *argp = (void __user *)arg; | |
2750 | long r; | |
2751 | ||
2752 | switch (ioctl) { | |
2753 | case KVM_GET_MSR_INDEX_LIST: { | |
2754 | struct kvm_msr_list __user *user_msr_list = argp; | |
2755 | struct kvm_msr_list msr_list; | |
2756 | unsigned n; | |
2757 | ||
2758 | r = -EFAULT; | |
2759 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2760 | goto out; | |
2761 | n = msr_list.nmsrs; | |
62ef68bb | 2762 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
043405e1 CO |
2763 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) |
2764 | goto out; | |
2765 | r = -E2BIG; | |
e125e7b6 | 2766 | if (n < msr_list.nmsrs) |
043405e1 CO |
2767 | goto out; |
2768 | r = -EFAULT; | |
2769 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2770 | num_msrs_to_save * sizeof(u32))) | |
2771 | goto out; | |
e125e7b6 | 2772 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 2773 | &emulated_msrs, |
62ef68bb | 2774 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
2775 | goto out; |
2776 | r = 0; | |
2777 | break; | |
2778 | } | |
9c15bb1d BP |
2779 | case KVM_GET_SUPPORTED_CPUID: |
2780 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
2781 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
2782 | struct kvm_cpuid2 cpuid; | |
2783 | ||
2784 | r = -EFAULT; | |
2785 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2786 | goto out; | |
9c15bb1d BP |
2787 | |
2788 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
2789 | ioctl); | |
674eea0f AK |
2790 | if (r) |
2791 | goto out; | |
2792 | ||
2793 | r = -EFAULT; | |
2794 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2795 | goto out; | |
2796 | r = 0; | |
2797 | break; | |
2798 | } | |
890ca9ae HY |
2799 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
2800 | u64 mce_cap; | |
2801 | ||
2802 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
2803 | r = -EFAULT; | |
2804 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
2805 | goto out; | |
2806 | r = 0; | |
2807 | break; | |
2808 | } | |
043405e1 CO |
2809 | default: |
2810 | r = -EINVAL; | |
2811 | } | |
2812 | out: | |
2813 | return r; | |
2814 | } | |
2815 | ||
f5f48ee1 SY |
2816 | static void wbinvd_ipi(void *garbage) |
2817 | { | |
2818 | wbinvd(); | |
2819 | } | |
2820 | ||
2821 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
2822 | { | |
e0f0bbc5 | 2823 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
2824 | } |
2825 | ||
313a3dc7 CO |
2826 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
2827 | { | |
f5f48ee1 SY |
2828 | /* Address WBINVD may be executed by guest */ |
2829 | if (need_emulate_wbinvd(vcpu)) { | |
2830 | if (kvm_x86_ops->has_wbinvd_exit()) | |
2831 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
2832 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
2833 | smp_call_function_single(vcpu->cpu, | |
2834 | wbinvd_ipi, NULL, 1); | |
2835 | } | |
2836 | ||
313a3dc7 | 2837 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
8f6055cb | 2838 | |
0dd6a6ed ZA |
2839 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
2840 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
2841 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
2842 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 2843 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 2844 | } |
8f6055cb | 2845 | |
48434c20 | 2846 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { |
6f526ec5 ZA |
2847 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
2848 | native_read_tsc() - vcpu->arch.last_host_tsc; | |
e48672fa ZA |
2849 | if (tsc_delta < 0) |
2850 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
c285545f | 2851 | if (check_tsc_unstable()) { |
b183aa58 ZA |
2852 | u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, |
2853 | vcpu->arch.last_guest_tsc); | |
2854 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
c285545f | 2855 | vcpu->arch.tsc_catchup = 1; |
c285545f | 2856 | } |
d98d07ca MT |
2857 | /* |
2858 | * On a host with synchronized TSC, there is no need to update | |
2859 | * kvmclock on vcpu->cpu migration | |
2860 | */ | |
2861 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 2862 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f ZA |
2863 | if (vcpu->cpu != cpu) |
2864 | kvm_migrate_timers(vcpu); | |
e48672fa | 2865 | vcpu->cpu = cpu; |
6b7d7e76 | 2866 | } |
c9aaa895 GC |
2867 | |
2868 | accumulate_steal_time(vcpu); | |
2869 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
313a3dc7 CO |
2870 | } |
2871 | ||
2872 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
2873 | { | |
02daab21 | 2874 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 2875 | kvm_put_guest_fpu(vcpu); |
6f526ec5 | 2876 | vcpu->arch.last_host_tsc = native_read_tsc(); |
313a3dc7 CO |
2877 | } |
2878 | ||
313a3dc7 CO |
2879 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
2880 | struct kvm_lapic_state *s) | |
2881 | { | |
5a71785d | 2882 | kvm_x86_ops->sync_pir_to_irr(vcpu); |
ad312c7c | 2883 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
2884 | |
2885 | return 0; | |
2886 | } | |
2887 | ||
2888 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2889 | struct kvm_lapic_state *s) | |
2890 | { | |
64eb0620 | 2891 | kvm_apic_post_state_restore(vcpu, s); |
cb142eb7 | 2892 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2893 | |
2894 | return 0; | |
2895 | } | |
2896 | ||
f77bc6a4 ZX |
2897 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
2898 | struct kvm_interrupt *irq) | |
2899 | { | |
02cdb50f | 2900 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 ZX |
2901 | return -EINVAL; |
2902 | if (irqchip_in_kernel(vcpu->kvm)) | |
2903 | return -ENXIO; | |
f77bc6a4 | 2904 | |
66fd3f7f | 2905 | kvm_queue_interrupt(vcpu, irq->irq, false); |
3842d135 | 2906 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 | 2907 | |
f77bc6a4 ZX |
2908 | return 0; |
2909 | } | |
2910 | ||
c4abb7c9 JK |
2911 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
2912 | { | |
c4abb7c9 | 2913 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
2914 | |
2915 | return 0; | |
2916 | } | |
2917 | ||
f077825a PB |
2918 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
2919 | { | |
64d60670 PB |
2920 | kvm_make_request(KVM_REQ_SMI, vcpu); |
2921 | ||
f077825a PB |
2922 | return 0; |
2923 | } | |
2924 | ||
b209749f AK |
2925 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
2926 | struct kvm_tpr_access_ctl *tac) | |
2927 | { | |
2928 | if (tac->flags) | |
2929 | return -EINVAL; | |
2930 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2931 | return 0; | |
2932 | } | |
2933 | ||
890ca9ae HY |
2934 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
2935 | u64 mcg_cap) | |
2936 | { | |
2937 | int r; | |
2938 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2939 | ||
2940 | r = -EINVAL; | |
a9e38c3e | 2941 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
2942 | goto out; |
2943 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2944 | goto out; | |
2945 | r = 0; | |
2946 | vcpu->arch.mcg_cap = mcg_cap; | |
2947 | /* Init IA32_MCG_CTL to all 1s */ | |
2948 | if (mcg_cap & MCG_CTL_P) | |
2949 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2950 | /* Init IA32_MCi_CTL to all 1s */ | |
2951 | for (bank = 0; bank < bank_num; bank++) | |
2952 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2953 | out: | |
2954 | return r; | |
2955 | } | |
2956 | ||
2957 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2958 | struct kvm_x86_mce *mce) | |
2959 | { | |
2960 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2961 | unsigned bank_num = mcg_cap & 0xff; | |
2962 | u64 *banks = vcpu->arch.mce_banks; | |
2963 | ||
2964 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
2965 | return -EINVAL; | |
2966 | /* | |
2967 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
2968 | * reporting is disabled | |
2969 | */ | |
2970 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
2971 | vcpu->arch.mcg_ctl != ~(u64)0) | |
2972 | return 0; | |
2973 | banks += 4 * mce->bank; | |
2974 | /* | |
2975 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
2976 | * reporting is disabled for the bank | |
2977 | */ | |
2978 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
2979 | return 0; | |
2980 | if (mce->status & MCI_STATUS_UC) { | |
2981 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 2982 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 2983 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
2984 | return 0; |
2985 | } | |
2986 | if (banks[1] & MCI_STATUS_VAL) | |
2987 | mce->status |= MCI_STATUS_OVER; | |
2988 | banks[2] = mce->addr; | |
2989 | banks[3] = mce->misc; | |
2990 | vcpu->arch.mcg_status = mce->mcg_status; | |
2991 | banks[1] = mce->status; | |
2992 | kvm_queue_exception(vcpu, MC_VECTOR); | |
2993 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
2994 | || !(banks[1] & MCI_STATUS_UC)) { | |
2995 | if (banks[1] & MCI_STATUS_VAL) | |
2996 | mce->status |= MCI_STATUS_OVER; | |
2997 | banks[2] = mce->addr; | |
2998 | banks[3] = mce->misc; | |
2999 | banks[1] = mce->status; | |
3000 | } else | |
3001 | banks[1] |= MCI_STATUS_OVER; | |
3002 | return 0; | |
3003 | } | |
3004 | ||
3cfc3092 JK |
3005 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
3006 | struct kvm_vcpu_events *events) | |
3007 | { | |
7460fb4a | 3008 | process_nmi(vcpu); |
03b82a30 JK |
3009 | events->exception.injected = |
3010 | vcpu->arch.exception.pending && | |
3011 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
3012 | events->exception.nr = vcpu->arch.exception.nr; |
3013 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
97e69aa6 | 3014 | events->exception.pad = 0; |
3cfc3092 JK |
3015 | events->exception.error_code = vcpu->arch.exception.error_code; |
3016 | ||
03b82a30 JK |
3017 | events->interrupt.injected = |
3018 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 3019 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 3020 | events->interrupt.soft = 0; |
37ccdcbe | 3021 | events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
3cfc3092 JK |
3022 | |
3023 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 3024 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
3cfc3092 | 3025 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); |
97e69aa6 | 3026 | events->nmi.pad = 0; |
3cfc3092 | 3027 | |
66450a21 | 3028 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 3029 | |
f077825a PB |
3030 | events->smi.smm = is_smm(vcpu); |
3031 | events->smi.pending = vcpu->arch.smi_pending; | |
3032 | events->smi.smm_inside_nmi = | |
3033 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
3034 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
3035 | ||
dab4b911 | 3036 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
3037 | | KVM_VCPUEVENT_VALID_SHADOW |
3038 | | KVM_VCPUEVENT_VALID_SMM); | |
97e69aa6 | 3039 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
3040 | } |
3041 | ||
3042 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
3043 | struct kvm_vcpu_events *events) | |
3044 | { | |
dab4b911 | 3045 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 3046 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a PB |
3047 | | KVM_VCPUEVENT_VALID_SHADOW |
3048 | | KVM_VCPUEVENT_VALID_SMM)) | |
3cfc3092 JK |
3049 | return -EINVAL; |
3050 | ||
7460fb4a | 3051 | process_nmi(vcpu); |
3cfc3092 JK |
3052 | vcpu->arch.exception.pending = events->exception.injected; |
3053 | vcpu->arch.exception.nr = events->exception.nr; | |
3054 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
3055 | vcpu->arch.exception.error_code = events->exception.error_code; | |
3056 | ||
3057 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
3058 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
3059 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
3060 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
3061 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
3062 | events->interrupt.shadow); | |
3cfc3092 JK |
3063 | |
3064 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
3065 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
3066 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
3067 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
3068 | ||
66450a21 JK |
3069 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
3070 | kvm_vcpu_has_lapic(vcpu)) | |
3071 | vcpu->arch.apic->sipi_vector = events->sipi_vector; | |
3cfc3092 | 3072 | |
f077825a PB |
3073 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
3074 | if (events->smi.smm) | |
3075 | vcpu->arch.hflags |= HF_SMM_MASK; | |
3076 | else | |
3077 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
3078 | vcpu->arch.smi_pending = events->smi.pending; | |
3079 | if (events->smi.smm_inside_nmi) | |
3080 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
3081 | else | |
3082 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; | |
3083 | if (kvm_vcpu_has_lapic(vcpu)) { | |
3084 | if (events->smi.latched_init) | |
3085 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
3086 | else | |
3087 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
3088 | } | |
3089 | } | |
3090 | ||
3842d135 AK |
3091 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3092 | ||
3cfc3092 JK |
3093 | return 0; |
3094 | } | |
3095 | ||
a1efbe77 JK |
3096 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
3097 | struct kvm_debugregs *dbgregs) | |
3098 | { | |
73aaf249 JK |
3099 | unsigned long val; |
3100 | ||
a1efbe77 | 3101 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 3102 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 3103 | dbgregs->dr6 = val; |
a1efbe77 JK |
3104 | dbgregs->dr7 = vcpu->arch.dr7; |
3105 | dbgregs->flags = 0; | |
97e69aa6 | 3106 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
3107 | } |
3108 | ||
3109 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
3110 | struct kvm_debugregs *dbgregs) | |
3111 | { | |
3112 | if (dbgregs->flags) | |
3113 | return -EINVAL; | |
3114 | ||
a1efbe77 | 3115 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 3116 | kvm_update_dr0123(vcpu); |
a1efbe77 | 3117 | vcpu->arch.dr6 = dbgregs->dr6; |
73aaf249 | 3118 | kvm_update_dr6(vcpu); |
a1efbe77 | 3119 | vcpu->arch.dr7 = dbgregs->dr7; |
9926c9fd | 3120 | kvm_update_dr7(vcpu); |
a1efbe77 | 3121 | |
a1efbe77 JK |
3122 | return 0; |
3123 | } | |
3124 | ||
df1daba7 PB |
3125 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
3126 | ||
3127 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
3128 | { | |
3129 | struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; | |
3130 | u64 xstate_bv = xsave->xsave_hdr.xstate_bv; | |
3131 | u64 valid; | |
3132 | ||
3133 | /* | |
3134 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3135 | * leaves 0 and 1 in the loop below. | |
3136 | */ | |
3137 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
3138 | ||
3139 | /* Set XSTATE_BV */ | |
3140 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; | |
3141 | ||
3142 | /* | |
3143 | * Copy each region from the possibly compacted offset to the | |
3144 | * non-compacted offset. | |
3145 | */ | |
3146 | valid = xstate_bv & ~XSTATE_FPSSE; | |
3147 | while (valid) { | |
3148 | u64 feature = valid & -valid; | |
3149 | int index = fls64(feature) - 1; | |
3150 | void *src = get_xsave_addr(xsave, feature); | |
3151 | ||
3152 | if (src) { | |
3153 | u32 size, offset, ecx, edx; | |
3154 | cpuid_count(XSTATE_CPUID, index, | |
3155 | &size, &offset, &ecx, &edx); | |
3156 | memcpy(dest + offset, src, size); | |
3157 | } | |
3158 | ||
3159 | valid -= feature; | |
3160 | } | |
3161 | } | |
3162 | ||
3163 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
3164 | { | |
3165 | struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; | |
3166 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); | |
3167 | u64 valid; | |
3168 | ||
3169 | /* | |
3170 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3171 | * leaves 0 and 1 in the loop below. | |
3172 | */ | |
3173 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
3174 | ||
3175 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
3176 | xsave->xsave_hdr.xstate_bv = xstate_bv; | |
3177 | if (cpu_has_xsaves) | |
3178 | xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; | |
3179 | ||
3180 | /* | |
3181 | * Copy each region from the non-compacted offset to the | |
3182 | * possibly compacted offset. | |
3183 | */ | |
3184 | valid = xstate_bv & ~XSTATE_FPSSE; | |
3185 | while (valid) { | |
3186 | u64 feature = valid & -valid; | |
3187 | int index = fls64(feature) - 1; | |
3188 | void *dest = get_xsave_addr(xsave, feature); | |
3189 | ||
3190 | if (dest) { | |
3191 | u32 size, offset, ecx, edx; | |
3192 | cpuid_count(XSTATE_CPUID, index, | |
3193 | &size, &offset, &ecx, &edx); | |
3194 | memcpy(dest, src + offset, size); | |
3195 | } else | |
3196 | WARN_ON_ONCE(1); | |
3197 | ||
3198 | valid -= feature; | |
3199 | } | |
3200 | } | |
3201 | ||
2d5b5a66 SY |
3202 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
3203 | struct kvm_xsave *guest_xsave) | |
3204 | { | |
4344ee98 | 3205 | if (cpu_has_xsave) { |
df1daba7 PB |
3206 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
3207 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 3208 | } else { |
2d5b5a66 SY |
3209 | memcpy(guest_xsave->region, |
3210 | &vcpu->arch.guest_fpu.state->fxsave, | |
3211 | sizeof(struct i387_fxsave_struct)); | |
3212 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = | |
3213 | XSTATE_FPSSE; | |
3214 | } | |
3215 | } | |
3216 | ||
3217 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
3218 | struct kvm_xsave *guest_xsave) | |
3219 | { | |
3220 | u64 xstate_bv = | |
3221 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
3222 | ||
d7876f1b PB |
3223 | if (cpu_has_xsave) { |
3224 | /* | |
3225 | * Here we allow setting states that are not present in | |
3226 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
3227 | * with old userspace. | |
3228 | */ | |
4ff41732 | 3229 | if (xstate_bv & ~kvm_supported_xcr0()) |
d7876f1b | 3230 | return -EINVAL; |
df1daba7 | 3231 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 3232 | } else { |
2d5b5a66 SY |
3233 | if (xstate_bv & ~XSTATE_FPSSE) |
3234 | return -EINVAL; | |
3235 | memcpy(&vcpu->arch.guest_fpu.state->fxsave, | |
3236 | guest_xsave->region, sizeof(struct i387_fxsave_struct)); | |
3237 | } | |
3238 | return 0; | |
3239 | } | |
3240 | ||
3241 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
3242 | struct kvm_xcrs *guest_xcrs) | |
3243 | { | |
3244 | if (!cpu_has_xsave) { | |
3245 | guest_xcrs->nr_xcrs = 0; | |
3246 | return; | |
3247 | } | |
3248 | ||
3249 | guest_xcrs->nr_xcrs = 1; | |
3250 | guest_xcrs->flags = 0; | |
3251 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
3252 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
3253 | } | |
3254 | ||
3255 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
3256 | struct kvm_xcrs *guest_xcrs) | |
3257 | { | |
3258 | int i, r = 0; | |
3259 | ||
3260 | if (!cpu_has_xsave) | |
3261 | return -EINVAL; | |
3262 | ||
3263 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
3264 | return -EINVAL; | |
3265 | ||
3266 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
3267 | /* Only support XCR0 currently */ | |
c67a04cb | 3268 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 3269 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 3270 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
3271 | break; |
3272 | } | |
3273 | if (r) | |
3274 | r = -EINVAL; | |
3275 | return r; | |
3276 | } | |
3277 | ||
1c0b28c2 EM |
3278 | /* |
3279 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
3280 | * stopped by the hypervisor. This function will be called from the host only. | |
3281 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
3282 | * does not support pv clocks. | |
3283 | */ | |
3284 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
3285 | { | |
0b79459b | 3286 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 3287 | return -EINVAL; |
51d59c6b | 3288 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
3289 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
3290 | return 0; | |
3291 | } | |
3292 | ||
313a3dc7 CO |
3293 | long kvm_arch_vcpu_ioctl(struct file *filp, |
3294 | unsigned int ioctl, unsigned long arg) | |
3295 | { | |
3296 | struct kvm_vcpu *vcpu = filp->private_data; | |
3297 | void __user *argp = (void __user *)arg; | |
3298 | int r; | |
d1ac91d8 AK |
3299 | union { |
3300 | struct kvm_lapic_state *lapic; | |
3301 | struct kvm_xsave *xsave; | |
3302 | struct kvm_xcrs *xcrs; | |
3303 | void *buffer; | |
3304 | } u; | |
3305 | ||
3306 | u.buffer = NULL; | |
313a3dc7 CO |
3307 | switch (ioctl) { |
3308 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
3309 | r = -EINVAL; |
3310 | if (!vcpu->arch.apic) | |
3311 | goto out; | |
d1ac91d8 | 3312 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 3313 | |
b772ff36 | 3314 | r = -ENOMEM; |
d1ac91d8 | 3315 | if (!u.lapic) |
b772ff36 | 3316 | goto out; |
d1ac91d8 | 3317 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3318 | if (r) |
3319 | goto out; | |
3320 | r = -EFAULT; | |
d1ac91d8 | 3321 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
3322 | goto out; |
3323 | r = 0; | |
3324 | break; | |
3325 | } | |
3326 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
3327 | r = -EINVAL; |
3328 | if (!vcpu->arch.apic) | |
3329 | goto out; | |
ff5c2c03 | 3330 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
18595411 GC |
3331 | if (IS_ERR(u.lapic)) |
3332 | return PTR_ERR(u.lapic); | |
ff5c2c03 | 3333 | |
d1ac91d8 | 3334 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3335 | break; |
3336 | } | |
f77bc6a4 ZX |
3337 | case KVM_INTERRUPT: { |
3338 | struct kvm_interrupt irq; | |
3339 | ||
3340 | r = -EFAULT; | |
3341 | if (copy_from_user(&irq, argp, sizeof irq)) | |
3342 | goto out; | |
3343 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
3344 | break; |
3345 | } | |
c4abb7c9 JK |
3346 | case KVM_NMI: { |
3347 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
3348 | break; |
3349 | } | |
f077825a PB |
3350 | case KVM_SMI: { |
3351 | r = kvm_vcpu_ioctl_smi(vcpu); | |
3352 | break; | |
3353 | } | |
313a3dc7 CO |
3354 | case KVM_SET_CPUID: { |
3355 | struct kvm_cpuid __user *cpuid_arg = argp; | |
3356 | struct kvm_cpuid cpuid; | |
3357 | ||
3358 | r = -EFAULT; | |
3359 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3360 | goto out; | |
3361 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
3362 | break; |
3363 | } | |
07716717 DK |
3364 | case KVM_SET_CPUID2: { |
3365 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3366 | struct kvm_cpuid2 cpuid; | |
3367 | ||
3368 | r = -EFAULT; | |
3369 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3370 | goto out; | |
3371 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 3372 | cpuid_arg->entries); |
07716717 DK |
3373 | break; |
3374 | } | |
3375 | case KVM_GET_CPUID2: { | |
3376 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3377 | struct kvm_cpuid2 cpuid; | |
3378 | ||
3379 | r = -EFAULT; | |
3380 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3381 | goto out; | |
3382 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 3383 | cpuid_arg->entries); |
07716717 DK |
3384 | if (r) |
3385 | goto out; | |
3386 | r = -EFAULT; | |
3387 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
3388 | goto out; | |
3389 | r = 0; | |
3390 | break; | |
3391 | } | |
313a3dc7 | 3392 | case KVM_GET_MSRS: |
609e36d3 | 3393 | r = msr_io(vcpu, argp, do_get_msr, 1); |
313a3dc7 CO |
3394 | break; |
3395 | case KVM_SET_MSRS: | |
3396 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
3397 | break; | |
b209749f AK |
3398 | case KVM_TPR_ACCESS_REPORTING: { |
3399 | struct kvm_tpr_access_ctl tac; | |
3400 | ||
3401 | r = -EFAULT; | |
3402 | if (copy_from_user(&tac, argp, sizeof tac)) | |
3403 | goto out; | |
3404 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
3405 | if (r) | |
3406 | goto out; | |
3407 | r = -EFAULT; | |
3408 | if (copy_to_user(argp, &tac, sizeof tac)) | |
3409 | goto out; | |
3410 | r = 0; | |
3411 | break; | |
3412 | }; | |
b93463aa AK |
3413 | case KVM_SET_VAPIC_ADDR: { |
3414 | struct kvm_vapic_addr va; | |
3415 | ||
3416 | r = -EINVAL; | |
3417 | if (!irqchip_in_kernel(vcpu->kvm)) | |
3418 | goto out; | |
3419 | r = -EFAULT; | |
3420 | if (copy_from_user(&va, argp, sizeof va)) | |
3421 | goto out; | |
fda4e2e8 | 3422 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
b93463aa AK |
3423 | break; |
3424 | } | |
890ca9ae HY |
3425 | case KVM_X86_SETUP_MCE: { |
3426 | u64 mcg_cap; | |
3427 | ||
3428 | r = -EFAULT; | |
3429 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
3430 | goto out; | |
3431 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
3432 | break; | |
3433 | } | |
3434 | case KVM_X86_SET_MCE: { | |
3435 | struct kvm_x86_mce mce; | |
3436 | ||
3437 | r = -EFAULT; | |
3438 | if (copy_from_user(&mce, argp, sizeof mce)) | |
3439 | goto out; | |
3440 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
3441 | break; | |
3442 | } | |
3cfc3092 JK |
3443 | case KVM_GET_VCPU_EVENTS: { |
3444 | struct kvm_vcpu_events events; | |
3445 | ||
3446 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
3447 | ||
3448 | r = -EFAULT; | |
3449 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
3450 | break; | |
3451 | r = 0; | |
3452 | break; | |
3453 | } | |
3454 | case KVM_SET_VCPU_EVENTS: { | |
3455 | struct kvm_vcpu_events events; | |
3456 | ||
3457 | r = -EFAULT; | |
3458 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
3459 | break; | |
3460 | ||
3461 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
3462 | break; | |
3463 | } | |
a1efbe77 JK |
3464 | case KVM_GET_DEBUGREGS: { |
3465 | struct kvm_debugregs dbgregs; | |
3466 | ||
3467 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
3468 | ||
3469 | r = -EFAULT; | |
3470 | if (copy_to_user(argp, &dbgregs, | |
3471 | sizeof(struct kvm_debugregs))) | |
3472 | break; | |
3473 | r = 0; | |
3474 | break; | |
3475 | } | |
3476 | case KVM_SET_DEBUGREGS: { | |
3477 | struct kvm_debugregs dbgregs; | |
3478 | ||
3479 | r = -EFAULT; | |
3480 | if (copy_from_user(&dbgregs, argp, | |
3481 | sizeof(struct kvm_debugregs))) | |
3482 | break; | |
3483 | ||
3484 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
3485 | break; | |
3486 | } | |
2d5b5a66 | 3487 | case KVM_GET_XSAVE: { |
d1ac91d8 | 3488 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 3489 | r = -ENOMEM; |
d1ac91d8 | 3490 | if (!u.xsave) |
2d5b5a66 SY |
3491 | break; |
3492 | ||
d1ac91d8 | 3493 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3494 | |
3495 | r = -EFAULT; | |
d1ac91d8 | 3496 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
3497 | break; |
3498 | r = 0; | |
3499 | break; | |
3500 | } | |
3501 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 3502 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
18595411 GC |
3503 | if (IS_ERR(u.xsave)) |
3504 | return PTR_ERR(u.xsave); | |
2d5b5a66 | 3505 | |
d1ac91d8 | 3506 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3507 | break; |
3508 | } | |
3509 | case KVM_GET_XCRS: { | |
d1ac91d8 | 3510 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 3511 | r = -ENOMEM; |
d1ac91d8 | 3512 | if (!u.xcrs) |
2d5b5a66 SY |
3513 | break; |
3514 | ||
d1ac91d8 | 3515 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3516 | |
3517 | r = -EFAULT; | |
d1ac91d8 | 3518 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
3519 | sizeof(struct kvm_xcrs))) |
3520 | break; | |
3521 | r = 0; | |
3522 | break; | |
3523 | } | |
3524 | case KVM_SET_XCRS: { | |
ff5c2c03 | 3525 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
18595411 GC |
3526 | if (IS_ERR(u.xcrs)) |
3527 | return PTR_ERR(u.xcrs); | |
2d5b5a66 | 3528 | |
d1ac91d8 | 3529 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3530 | break; |
3531 | } | |
92a1f12d JR |
3532 | case KVM_SET_TSC_KHZ: { |
3533 | u32 user_tsc_khz; | |
3534 | ||
3535 | r = -EINVAL; | |
92a1f12d JR |
3536 | user_tsc_khz = (u32)arg; |
3537 | ||
3538 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
3539 | goto out; | |
3540 | ||
cc578287 ZA |
3541 | if (user_tsc_khz == 0) |
3542 | user_tsc_khz = tsc_khz; | |
3543 | ||
3544 | kvm_set_tsc_khz(vcpu, user_tsc_khz); | |
92a1f12d JR |
3545 | |
3546 | r = 0; | |
3547 | goto out; | |
3548 | } | |
3549 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 3550 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
3551 | goto out; |
3552 | } | |
1c0b28c2 EM |
3553 | case KVM_KVMCLOCK_CTRL: { |
3554 | r = kvm_set_guest_paused(vcpu); | |
3555 | goto out; | |
3556 | } | |
313a3dc7 CO |
3557 | default: |
3558 | r = -EINVAL; | |
3559 | } | |
3560 | out: | |
d1ac91d8 | 3561 | kfree(u.buffer); |
313a3dc7 CO |
3562 | return r; |
3563 | } | |
3564 | ||
5b1c1493 CO |
3565 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
3566 | { | |
3567 | return VM_FAULT_SIGBUS; | |
3568 | } | |
3569 | ||
1fe779f8 CO |
3570 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
3571 | { | |
3572 | int ret; | |
3573 | ||
3574 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 3575 | return -EINVAL; |
1fe779f8 CO |
3576 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); |
3577 | return ret; | |
3578 | } | |
3579 | ||
b927a3ce SY |
3580 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
3581 | u64 ident_addr) | |
3582 | { | |
3583 | kvm->arch.ept_identity_map_addr = ident_addr; | |
3584 | return 0; | |
3585 | } | |
3586 | ||
1fe779f8 CO |
3587 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
3588 | u32 kvm_nr_mmu_pages) | |
3589 | { | |
3590 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
3591 | return -EINVAL; | |
3592 | ||
79fac95e | 3593 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
3594 | |
3595 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 3596 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 3597 | |
79fac95e | 3598 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
3599 | return 0; |
3600 | } | |
3601 | ||
3602 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
3603 | { | |
39de71ec | 3604 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
3605 | } |
3606 | ||
1fe779f8 CO |
3607 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
3608 | { | |
3609 | int r; | |
3610 | ||
3611 | r = 0; | |
3612 | switch (chip->chip_id) { | |
3613 | case KVM_IRQCHIP_PIC_MASTER: | |
3614 | memcpy(&chip->chip.pic, | |
3615 | &pic_irqchip(kvm)->pics[0], | |
3616 | sizeof(struct kvm_pic_state)); | |
3617 | break; | |
3618 | case KVM_IRQCHIP_PIC_SLAVE: | |
3619 | memcpy(&chip->chip.pic, | |
3620 | &pic_irqchip(kvm)->pics[1], | |
3621 | sizeof(struct kvm_pic_state)); | |
3622 | break; | |
3623 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3624 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3625 | break; |
3626 | default: | |
3627 | r = -EINVAL; | |
3628 | break; | |
3629 | } | |
3630 | return r; | |
3631 | } | |
3632 | ||
3633 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
3634 | { | |
3635 | int r; | |
3636 | ||
3637 | r = 0; | |
3638 | switch (chip->chip_id) { | |
3639 | case KVM_IRQCHIP_PIC_MASTER: | |
f4f51050 | 3640 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3641 | memcpy(&pic_irqchip(kvm)->pics[0], |
3642 | &chip->chip.pic, | |
3643 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3644 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3645 | break; |
3646 | case KVM_IRQCHIP_PIC_SLAVE: | |
f4f51050 | 3647 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3648 | memcpy(&pic_irqchip(kvm)->pics[1], |
3649 | &chip->chip.pic, | |
3650 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3651 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3652 | break; |
3653 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3654 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3655 | break; |
3656 | default: | |
3657 | r = -EINVAL; | |
3658 | break; | |
3659 | } | |
3660 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
3661 | return r; | |
3662 | } | |
3663 | ||
e0f63cb9 SY |
3664 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
3665 | { | |
3666 | int r = 0; | |
3667 | ||
894a9c55 | 3668 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3669 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 3670 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3671 | return r; |
3672 | } | |
3673 | ||
3674 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3675 | { | |
3676 | int r = 0; | |
3677 | ||
894a9c55 | 3678 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3679 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
3680 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
3681 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3682 | return r; | |
3683 | } | |
3684 | ||
3685 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3686 | { | |
3687 | int r = 0; | |
3688 | ||
3689 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3690 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3691 | sizeof(ps->channels)); | |
3692 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3693 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 3694 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
e9f42757 BK |
3695 | return r; |
3696 | } | |
3697 | ||
3698 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3699 | { | |
3700 | int r = 0, start = 0; | |
3701 | u32 prev_legacy, cur_legacy; | |
3702 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3703 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3704 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3705 | if (!prev_legacy && cur_legacy) | |
3706 | start = 1; | |
3707 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
3708 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
3709 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
3710 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 3711 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3712 | return r; |
3713 | } | |
3714 | ||
52d939a0 MT |
3715 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
3716 | struct kvm_reinject_control *control) | |
3717 | { | |
3718 | if (!kvm->arch.vpit) | |
3719 | return -ENXIO; | |
894a9c55 | 3720 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
26ef1924 | 3721 | kvm->arch.vpit->pit_state.reinject = control->pit_reinject; |
894a9c55 | 3722 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
3723 | return 0; |
3724 | } | |
3725 | ||
95d4c16c | 3726 | /** |
60c34612 TY |
3727 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot |
3728 | * @kvm: kvm instance | |
3729 | * @log: slot id and address to which we copy the log | |
95d4c16c | 3730 | * |
e108ff2f PB |
3731 | * Steps 1-4 below provide general overview of dirty page logging. See |
3732 | * kvm_get_dirty_log_protect() function description for additional details. | |
3733 | * | |
3734 | * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we | |
3735 | * always flush the TLB (step 4) even if previous step failed and the dirty | |
3736 | * bitmap may be corrupt. Regardless of previous outcome the KVM logging API | |
3737 | * does not preclude user space subsequent dirty log read. Flushing TLB ensures | |
3738 | * writes will be marked dirty for next log read. | |
95d4c16c | 3739 | * |
60c34612 TY |
3740 | * 1. Take a snapshot of the bit and clear it if needed. |
3741 | * 2. Write protect the corresponding page. | |
e108ff2f PB |
3742 | * 3. Copy the snapshot to the userspace. |
3743 | * 4. Flush TLB's if needed. | |
5bb064dc | 3744 | */ |
60c34612 | 3745 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
5bb064dc | 3746 | { |
60c34612 | 3747 | bool is_dirty = false; |
e108ff2f | 3748 | int r; |
5bb064dc | 3749 | |
79fac95e | 3750 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 3751 | |
88178fd4 KH |
3752 | /* |
3753 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
3754 | */ | |
3755 | if (kvm_x86_ops->flush_log_dirty) | |
3756 | kvm_x86_ops->flush_log_dirty(kvm); | |
3757 | ||
e108ff2f | 3758 | r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); |
198c74f4 XG |
3759 | |
3760 | /* | |
3761 | * All the TLBs can be flushed out of mmu lock, see the comments in | |
3762 | * kvm_mmu_slot_remove_write_access(). | |
3763 | */ | |
e108ff2f | 3764 | lockdep_assert_held(&kvm->slots_lock); |
198c74f4 XG |
3765 | if (is_dirty) |
3766 | kvm_flush_remote_tlbs(kvm); | |
3767 | ||
79fac95e | 3768 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
3769 | return r; |
3770 | } | |
3771 | ||
aa2fbe6d YZ |
3772 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
3773 | bool line_status) | |
23d43cf9 CD |
3774 | { |
3775 | if (!irqchip_in_kernel(kvm)) | |
3776 | return -ENXIO; | |
3777 | ||
3778 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
3779 | irq_event->irq, irq_event->level, |
3780 | line_status); | |
23d43cf9 CD |
3781 | return 0; |
3782 | } | |
3783 | ||
90de4a18 NA |
3784 | static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
3785 | struct kvm_enable_cap *cap) | |
3786 | { | |
3787 | int r; | |
3788 | ||
3789 | if (cap->flags) | |
3790 | return -EINVAL; | |
3791 | ||
3792 | switch (cap->cap) { | |
3793 | case KVM_CAP_DISABLE_QUIRKS: | |
3794 | kvm->arch.disabled_quirks = cap->args[0]; | |
3795 | r = 0; | |
3796 | break; | |
3797 | default: | |
3798 | r = -EINVAL; | |
3799 | break; | |
3800 | } | |
3801 | return r; | |
3802 | } | |
3803 | ||
1fe779f8 CO |
3804 | long kvm_arch_vm_ioctl(struct file *filp, |
3805 | unsigned int ioctl, unsigned long arg) | |
3806 | { | |
3807 | struct kvm *kvm = filp->private_data; | |
3808 | void __user *argp = (void __user *)arg; | |
367e1319 | 3809 | int r = -ENOTTY; |
f0d66275 DH |
3810 | /* |
3811 | * This union makes it completely explicit to gcc-3.x | |
3812 | * that these two variables' stack usage should be | |
3813 | * combined, not added together. | |
3814 | */ | |
3815 | union { | |
3816 | struct kvm_pit_state ps; | |
e9f42757 | 3817 | struct kvm_pit_state2 ps2; |
c5ff41ce | 3818 | struct kvm_pit_config pit_config; |
f0d66275 | 3819 | } u; |
1fe779f8 CO |
3820 | |
3821 | switch (ioctl) { | |
3822 | case KVM_SET_TSS_ADDR: | |
3823 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 3824 | break; |
b927a3ce SY |
3825 | case KVM_SET_IDENTITY_MAP_ADDR: { |
3826 | u64 ident_addr; | |
3827 | ||
3828 | r = -EFAULT; | |
3829 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
3830 | goto out; | |
3831 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
b927a3ce SY |
3832 | break; |
3833 | } | |
1fe779f8 CO |
3834 | case KVM_SET_NR_MMU_PAGES: |
3835 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
3836 | break; |
3837 | case KVM_GET_NR_MMU_PAGES: | |
3838 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
3839 | break; | |
3ddea128 MT |
3840 | case KVM_CREATE_IRQCHIP: { |
3841 | struct kvm_pic *vpic; | |
3842 | ||
3843 | mutex_lock(&kvm->lock); | |
3844 | r = -EEXIST; | |
3845 | if (kvm->arch.vpic) | |
3846 | goto create_irqchip_unlock; | |
3e515705 AK |
3847 | r = -EINVAL; |
3848 | if (atomic_read(&kvm->online_vcpus)) | |
3849 | goto create_irqchip_unlock; | |
1fe779f8 | 3850 | r = -ENOMEM; |
3ddea128 MT |
3851 | vpic = kvm_create_pic(kvm); |
3852 | if (vpic) { | |
1fe779f8 CO |
3853 | r = kvm_ioapic_init(kvm); |
3854 | if (r) { | |
175504cd | 3855 | mutex_lock(&kvm->slots_lock); |
72bb2fcd | 3856 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, |
743eeb0b SL |
3857 | &vpic->dev_master); |
3858 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3859 | &vpic->dev_slave); | |
3860 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3861 | &vpic->dev_eclr); | |
175504cd | 3862 | mutex_unlock(&kvm->slots_lock); |
3ddea128 MT |
3863 | kfree(vpic); |
3864 | goto create_irqchip_unlock; | |
1fe779f8 CO |
3865 | } |
3866 | } else | |
3ddea128 MT |
3867 | goto create_irqchip_unlock; |
3868 | smp_wmb(); | |
3869 | kvm->arch.vpic = vpic; | |
3870 | smp_wmb(); | |
399ec807 AK |
3871 | r = kvm_setup_default_irq_routing(kvm); |
3872 | if (r) { | |
175504cd | 3873 | mutex_lock(&kvm->slots_lock); |
3ddea128 | 3874 | mutex_lock(&kvm->irq_lock); |
72bb2fcd WY |
3875 | kvm_ioapic_destroy(kvm); |
3876 | kvm_destroy_pic(kvm); | |
3ddea128 | 3877 | mutex_unlock(&kvm->irq_lock); |
175504cd | 3878 | mutex_unlock(&kvm->slots_lock); |
399ec807 | 3879 | } |
3ddea128 MT |
3880 | create_irqchip_unlock: |
3881 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 3882 | break; |
3ddea128 | 3883 | } |
7837699f | 3884 | case KVM_CREATE_PIT: |
c5ff41ce JK |
3885 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
3886 | goto create_pit; | |
3887 | case KVM_CREATE_PIT2: | |
3888 | r = -EFAULT; | |
3889 | if (copy_from_user(&u.pit_config, argp, | |
3890 | sizeof(struct kvm_pit_config))) | |
3891 | goto out; | |
3892 | create_pit: | |
79fac95e | 3893 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
3894 | r = -EEXIST; |
3895 | if (kvm->arch.vpit) | |
3896 | goto create_pit_unlock; | |
7837699f | 3897 | r = -ENOMEM; |
c5ff41ce | 3898 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
3899 | if (kvm->arch.vpit) |
3900 | r = 0; | |
269e05e4 | 3901 | create_pit_unlock: |
79fac95e | 3902 | mutex_unlock(&kvm->slots_lock); |
7837699f | 3903 | break; |
1fe779f8 CO |
3904 | case KVM_GET_IRQCHIP: { |
3905 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3906 | struct kvm_irqchip *chip; |
1fe779f8 | 3907 | |
ff5c2c03 SL |
3908 | chip = memdup_user(argp, sizeof(*chip)); |
3909 | if (IS_ERR(chip)) { | |
3910 | r = PTR_ERR(chip); | |
1fe779f8 | 3911 | goto out; |
ff5c2c03 SL |
3912 | } |
3913 | ||
1fe779f8 CO |
3914 | r = -ENXIO; |
3915 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3916 | goto get_irqchip_out; |
3917 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 3918 | if (r) |
f0d66275 | 3919 | goto get_irqchip_out; |
1fe779f8 | 3920 | r = -EFAULT; |
f0d66275 DH |
3921 | if (copy_to_user(argp, chip, sizeof *chip)) |
3922 | goto get_irqchip_out; | |
1fe779f8 | 3923 | r = 0; |
f0d66275 DH |
3924 | get_irqchip_out: |
3925 | kfree(chip); | |
1fe779f8 CO |
3926 | break; |
3927 | } | |
3928 | case KVM_SET_IRQCHIP: { | |
3929 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3930 | struct kvm_irqchip *chip; |
1fe779f8 | 3931 | |
ff5c2c03 SL |
3932 | chip = memdup_user(argp, sizeof(*chip)); |
3933 | if (IS_ERR(chip)) { | |
3934 | r = PTR_ERR(chip); | |
1fe779f8 | 3935 | goto out; |
ff5c2c03 SL |
3936 | } |
3937 | ||
1fe779f8 CO |
3938 | r = -ENXIO; |
3939 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3940 | goto set_irqchip_out; |
3941 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 3942 | if (r) |
f0d66275 | 3943 | goto set_irqchip_out; |
1fe779f8 | 3944 | r = 0; |
f0d66275 DH |
3945 | set_irqchip_out: |
3946 | kfree(chip); | |
1fe779f8 CO |
3947 | break; |
3948 | } | |
e0f63cb9 | 3949 | case KVM_GET_PIT: { |
e0f63cb9 | 3950 | r = -EFAULT; |
f0d66275 | 3951 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3952 | goto out; |
3953 | r = -ENXIO; | |
3954 | if (!kvm->arch.vpit) | |
3955 | goto out; | |
f0d66275 | 3956 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
3957 | if (r) |
3958 | goto out; | |
3959 | r = -EFAULT; | |
f0d66275 | 3960 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3961 | goto out; |
3962 | r = 0; | |
3963 | break; | |
3964 | } | |
3965 | case KVM_SET_PIT: { | |
e0f63cb9 | 3966 | r = -EFAULT; |
f0d66275 | 3967 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
3968 | goto out; |
3969 | r = -ENXIO; | |
3970 | if (!kvm->arch.vpit) | |
3971 | goto out; | |
f0d66275 | 3972 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
3973 | break; |
3974 | } | |
e9f42757 BK |
3975 | case KVM_GET_PIT2: { |
3976 | r = -ENXIO; | |
3977 | if (!kvm->arch.vpit) | |
3978 | goto out; | |
3979 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
3980 | if (r) | |
3981 | goto out; | |
3982 | r = -EFAULT; | |
3983 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
3984 | goto out; | |
3985 | r = 0; | |
3986 | break; | |
3987 | } | |
3988 | case KVM_SET_PIT2: { | |
3989 | r = -EFAULT; | |
3990 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
3991 | goto out; | |
3992 | r = -ENXIO; | |
3993 | if (!kvm->arch.vpit) | |
3994 | goto out; | |
3995 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
e9f42757 BK |
3996 | break; |
3997 | } | |
52d939a0 MT |
3998 | case KVM_REINJECT_CONTROL: { |
3999 | struct kvm_reinject_control control; | |
4000 | r = -EFAULT; | |
4001 | if (copy_from_user(&control, argp, sizeof(control))) | |
4002 | goto out; | |
4003 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
52d939a0 MT |
4004 | break; |
4005 | } | |
ffde22ac ES |
4006 | case KVM_XEN_HVM_CONFIG: { |
4007 | r = -EFAULT; | |
4008 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
4009 | sizeof(struct kvm_xen_hvm_config))) | |
4010 | goto out; | |
4011 | r = -EINVAL; | |
4012 | if (kvm->arch.xen_hvm_config.flags) | |
4013 | goto out; | |
4014 | r = 0; | |
4015 | break; | |
4016 | } | |
afbcf7ab | 4017 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
4018 | struct kvm_clock_data user_ns; |
4019 | u64 now_ns; | |
4020 | s64 delta; | |
4021 | ||
4022 | r = -EFAULT; | |
4023 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
4024 | goto out; | |
4025 | ||
4026 | r = -EINVAL; | |
4027 | if (user_ns.flags) | |
4028 | goto out; | |
4029 | ||
4030 | r = 0; | |
395c6b0a | 4031 | local_irq_disable(); |
759379dd | 4032 | now_ns = get_kernel_ns(); |
afbcf7ab | 4033 | delta = user_ns.clock - now_ns; |
395c6b0a | 4034 | local_irq_enable(); |
afbcf7ab | 4035 | kvm->arch.kvmclock_offset = delta; |
2e762ff7 | 4036 | kvm_gen_update_masterclock(kvm); |
afbcf7ab GC |
4037 | break; |
4038 | } | |
4039 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
4040 | struct kvm_clock_data user_ns; |
4041 | u64 now_ns; | |
4042 | ||
395c6b0a | 4043 | local_irq_disable(); |
759379dd | 4044 | now_ns = get_kernel_ns(); |
afbcf7ab | 4045 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; |
395c6b0a | 4046 | local_irq_enable(); |
afbcf7ab | 4047 | user_ns.flags = 0; |
97e69aa6 | 4048 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
4049 | |
4050 | r = -EFAULT; | |
4051 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
4052 | goto out; | |
4053 | r = 0; | |
4054 | break; | |
4055 | } | |
90de4a18 NA |
4056 | case KVM_ENABLE_CAP: { |
4057 | struct kvm_enable_cap cap; | |
afbcf7ab | 4058 | |
90de4a18 NA |
4059 | r = -EFAULT; |
4060 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
4061 | goto out; | |
4062 | r = kvm_vm_ioctl_enable_cap(kvm, &cap); | |
4063 | break; | |
4064 | } | |
1fe779f8 | 4065 | default: |
c274e03a | 4066 | r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); |
1fe779f8 CO |
4067 | } |
4068 | out: | |
4069 | return r; | |
4070 | } | |
4071 | ||
a16b043c | 4072 | static void kvm_init_msr_list(void) |
043405e1 CO |
4073 | { |
4074 | u32 dummy[2]; | |
4075 | unsigned i, j; | |
4076 | ||
62ef68bb | 4077 | for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { |
043405e1 CO |
4078 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
4079 | continue; | |
93c4adc7 PB |
4080 | |
4081 | /* | |
4082 | * Even MSRs that are valid in the host may not be exposed | |
4083 | * to the guests in some cases. We could work around this | |
4084 | * in VMX with the generic MSR save/load machinery, but it | |
4085 | * is not really worthwhile since it will really only | |
4086 | * happen with nested virtualization. | |
4087 | */ | |
4088 | switch (msrs_to_save[i]) { | |
4089 | case MSR_IA32_BNDCFGS: | |
4090 | if (!kvm_x86_ops->mpx_supported()) | |
4091 | continue; | |
4092 | break; | |
4093 | default: | |
4094 | break; | |
4095 | } | |
4096 | ||
043405e1 CO |
4097 | if (j < i) |
4098 | msrs_to_save[j] = msrs_to_save[i]; | |
4099 | j++; | |
4100 | } | |
4101 | num_msrs_to_save = j; | |
62ef68bb PB |
4102 | |
4103 | for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { | |
4104 | switch (emulated_msrs[i]) { | |
6d396b55 PB |
4105 | case MSR_IA32_SMBASE: |
4106 | if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) | |
4107 | continue; | |
4108 | break; | |
62ef68bb PB |
4109 | default: |
4110 | break; | |
4111 | } | |
4112 | ||
4113 | if (j < i) | |
4114 | emulated_msrs[j] = emulated_msrs[i]; | |
4115 | j++; | |
4116 | } | |
4117 | num_emulated_msrs = j; | |
043405e1 CO |
4118 | } |
4119 | ||
bda9020e MT |
4120 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
4121 | const void *v) | |
bbd9b64e | 4122 | { |
70252a10 AK |
4123 | int handled = 0; |
4124 | int n; | |
4125 | ||
4126 | do { | |
4127 | n = min(len, 8); | |
4128 | if (!(vcpu->arch.apic && | |
e32edf4f NN |
4129 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
4130 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
4131 | break; |
4132 | handled += n; | |
4133 | addr += n; | |
4134 | len -= n; | |
4135 | v += n; | |
4136 | } while (len); | |
bbd9b64e | 4137 | |
70252a10 | 4138 | return handled; |
bbd9b64e CO |
4139 | } |
4140 | ||
bda9020e | 4141 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 4142 | { |
70252a10 AK |
4143 | int handled = 0; |
4144 | int n; | |
4145 | ||
4146 | do { | |
4147 | n = min(len, 8); | |
4148 | if (!(vcpu->arch.apic && | |
e32edf4f NN |
4149 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
4150 | addr, n, v)) | |
4151 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
4152 | break; |
4153 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); | |
4154 | handled += n; | |
4155 | addr += n; | |
4156 | len -= n; | |
4157 | v += n; | |
4158 | } while (len); | |
bbd9b64e | 4159 | |
70252a10 | 4160 | return handled; |
bbd9b64e CO |
4161 | } |
4162 | ||
2dafc6c2 GN |
4163 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
4164 | struct kvm_segment *var, int seg) | |
4165 | { | |
4166 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
4167 | } | |
4168 | ||
4169 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
4170 | struct kvm_segment *var, int seg) | |
4171 | { | |
4172 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
4173 | } | |
4174 | ||
54987b7a PB |
4175 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
4176 | struct x86_exception *exception) | |
02f59dc9 JR |
4177 | { |
4178 | gpa_t t_gpa; | |
02f59dc9 JR |
4179 | |
4180 | BUG_ON(!mmu_is_nested(vcpu)); | |
4181 | ||
4182 | /* NPT walks are always user-walks */ | |
4183 | access |= PFERR_USER_MASK; | |
54987b7a | 4184 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
4185 | |
4186 | return t_gpa; | |
4187 | } | |
4188 | ||
ab9ae313 AK |
4189 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
4190 | struct x86_exception *exception) | |
1871c602 GN |
4191 | { |
4192 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 4193 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4194 | } |
4195 | ||
ab9ae313 AK |
4196 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
4197 | struct x86_exception *exception) | |
1871c602 GN |
4198 | { |
4199 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4200 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 4201 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4202 | } |
4203 | ||
ab9ae313 AK |
4204 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
4205 | struct x86_exception *exception) | |
1871c602 GN |
4206 | { |
4207 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4208 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 4209 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4210 | } |
4211 | ||
4212 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
4213 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
4214 | struct x86_exception *exception) | |
1871c602 | 4215 | { |
ab9ae313 | 4216 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
4217 | } |
4218 | ||
4219 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
4220 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 4221 | struct x86_exception *exception) |
bbd9b64e CO |
4222 | { |
4223 | void *data = val; | |
10589a46 | 4224 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
4225 | |
4226 | while (bytes) { | |
14dfe855 | 4227 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 4228 | exception); |
bbd9b64e | 4229 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 4230 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
4231 | int ret; |
4232 | ||
bcc55cba | 4233 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4234 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
4235 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
4236 | offset, toread); | |
10589a46 | 4237 | if (ret < 0) { |
c3cd7ffa | 4238 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
4239 | goto out; |
4240 | } | |
bbd9b64e | 4241 | |
77c2002e IE |
4242 | bytes -= toread; |
4243 | data += toread; | |
4244 | addr += toread; | |
bbd9b64e | 4245 | } |
10589a46 | 4246 | out: |
10589a46 | 4247 | return r; |
bbd9b64e | 4248 | } |
77c2002e | 4249 | |
1871c602 | 4250 | /* used for instruction fetching */ |
0f65dd70 AK |
4251 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
4252 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4253 | struct x86_exception *exception) |
1871c602 | 4254 | { |
0f65dd70 | 4255 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4256 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
4257 | unsigned offset; |
4258 | int ret; | |
0f65dd70 | 4259 | |
44583cba PB |
4260 | /* Inline kvm_read_guest_virt_helper for speed. */ |
4261 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
4262 | exception); | |
4263 | if (unlikely(gpa == UNMAPPED_GVA)) | |
4264 | return X86EMUL_PROPAGATE_FAULT; | |
4265 | ||
4266 | offset = addr & (PAGE_SIZE-1); | |
4267 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
4268 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
4269 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
4270 | offset, bytes); | |
44583cba PB |
4271 | if (unlikely(ret < 0)) |
4272 | return X86EMUL_IO_NEEDED; | |
4273 | ||
4274 | return X86EMUL_CONTINUE; | |
1871c602 GN |
4275 | } |
4276 | ||
064aea77 | 4277 | int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4278 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 4279 | struct x86_exception *exception) |
1871c602 | 4280 | { |
0f65dd70 | 4281 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4282 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 4283 | |
1871c602 | 4284 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 4285 | exception); |
1871c602 | 4286 | } |
064aea77 | 4287 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 4288 | |
0f65dd70 AK |
4289 | static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
4290 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4291 | struct x86_exception *exception) |
1871c602 | 4292 | { |
0f65dd70 | 4293 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
bcc55cba | 4294 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); |
1871c602 GN |
4295 | } |
4296 | ||
6a4d7550 | 4297 | int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4298 | gva_t addr, void *val, |
2dafc6c2 | 4299 | unsigned int bytes, |
bcc55cba | 4300 | struct x86_exception *exception) |
77c2002e | 4301 | { |
0f65dd70 | 4302 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
77c2002e IE |
4303 | void *data = val; |
4304 | int r = X86EMUL_CONTINUE; | |
4305 | ||
4306 | while (bytes) { | |
14dfe855 JR |
4307 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
4308 | PFERR_WRITE_MASK, | |
ab9ae313 | 4309 | exception); |
77c2002e IE |
4310 | unsigned offset = addr & (PAGE_SIZE-1); |
4311 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
4312 | int ret; | |
4313 | ||
bcc55cba | 4314 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4315 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 4316 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 4317 | if (ret < 0) { |
c3cd7ffa | 4318 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
4319 | goto out; |
4320 | } | |
4321 | ||
4322 | bytes -= towrite; | |
4323 | data += towrite; | |
4324 | addr += towrite; | |
4325 | } | |
4326 | out: | |
4327 | return r; | |
4328 | } | |
6a4d7550 | 4329 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 4330 | |
af7cc7d1 XG |
4331 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
4332 | gpa_t *gpa, struct x86_exception *exception, | |
4333 | bool write) | |
4334 | { | |
97d64b78 AK |
4335 | u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
4336 | | (write ? PFERR_WRITE_MASK : 0); | |
af7cc7d1 | 4337 | |
97d64b78 | 4338 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 FW |
4339 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
4340 | vcpu->arch.access, access)) { | |
bebb106a XG |
4341 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
4342 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 4343 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
4344 | return 1; |
4345 | } | |
4346 | ||
af7cc7d1 XG |
4347 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
4348 | ||
4349 | if (*gpa == UNMAPPED_GVA) | |
4350 | return -1; | |
4351 | ||
4352 | /* For APIC access vmexit */ | |
4353 | if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4354 | return 1; | |
4355 | ||
4f022648 XG |
4356 | if (vcpu_match_mmio_gpa(vcpu, *gpa)) { |
4357 | trace_vcpu_match_mmio(gva, *gpa, write, true); | |
bebb106a | 4358 | return 1; |
4f022648 | 4359 | } |
bebb106a | 4360 | |
af7cc7d1 XG |
4361 | return 0; |
4362 | } | |
4363 | ||
3200f405 | 4364 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 4365 | const void *val, int bytes) |
bbd9b64e CO |
4366 | { |
4367 | int ret; | |
4368 | ||
54bf36aa | 4369 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 4370 | if (ret < 0) |
bbd9b64e | 4371 | return 0; |
f57f2ef5 | 4372 | kvm_mmu_pte_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
4373 | return 1; |
4374 | } | |
4375 | ||
77d197b2 XG |
4376 | struct read_write_emulator_ops { |
4377 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
4378 | int bytes); | |
4379 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4380 | void *val, int bytes); | |
4381 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4382 | int bytes, void *val); | |
4383 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4384 | void *val, int bytes); | |
4385 | bool write; | |
4386 | }; | |
4387 | ||
4388 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
4389 | { | |
4390 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 4391 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
f78146b0 | 4392 | vcpu->mmio_fragments[0].gpa, *(u64 *)val); |
77d197b2 XG |
4393 | vcpu->mmio_read_completed = 0; |
4394 | return 1; | |
4395 | } | |
4396 | ||
4397 | return 0; | |
4398 | } | |
4399 | ||
4400 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4401 | void *val, int bytes) | |
4402 | { | |
54bf36aa | 4403 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
4404 | } |
4405 | ||
4406 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4407 | void *val, int bytes) | |
4408 | { | |
4409 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
4410 | } | |
4411 | ||
4412 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
4413 | { | |
4414 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); | |
4415 | return vcpu_mmio_write(vcpu, gpa, bytes, val); | |
4416 | } | |
4417 | ||
4418 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4419 | void *val, int bytes) | |
4420 | { | |
4421 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
4422 | return X86EMUL_IO_NEEDED; | |
4423 | } | |
4424 | ||
4425 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4426 | void *val, int bytes) | |
4427 | { | |
f78146b0 AK |
4428 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
4429 | ||
87da7e66 | 4430 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
4431 | return X86EMUL_CONTINUE; |
4432 | } | |
4433 | ||
0fbe9b0b | 4434 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
4435 | .read_write_prepare = read_prepare, |
4436 | .read_write_emulate = read_emulate, | |
4437 | .read_write_mmio = vcpu_mmio_read, | |
4438 | .read_write_exit_mmio = read_exit_mmio, | |
4439 | }; | |
4440 | ||
0fbe9b0b | 4441 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
4442 | .read_write_emulate = write_emulate, |
4443 | .read_write_mmio = write_mmio, | |
4444 | .read_write_exit_mmio = write_exit_mmio, | |
4445 | .write = true, | |
4446 | }; | |
4447 | ||
22388a3c XG |
4448 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
4449 | unsigned int bytes, | |
4450 | struct x86_exception *exception, | |
4451 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 4452 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4453 | { |
af7cc7d1 XG |
4454 | gpa_t gpa; |
4455 | int handled, ret; | |
22388a3c | 4456 | bool write = ops->write; |
f78146b0 | 4457 | struct kvm_mmio_fragment *frag; |
10589a46 | 4458 | |
22388a3c | 4459 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); |
bbd9b64e | 4460 | |
af7cc7d1 | 4461 | if (ret < 0) |
bbd9b64e | 4462 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
4463 | |
4464 | /* For APIC access vmexit */ | |
af7cc7d1 | 4465 | if (ret) |
bbd9b64e CO |
4466 | goto mmio; |
4467 | ||
22388a3c | 4468 | if (ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
4469 | return X86EMUL_CONTINUE; |
4470 | ||
4471 | mmio: | |
4472 | /* | |
4473 | * Is this MMIO handled locally? | |
4474 | */ | |
22388a3c | 4475 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 4476 | if (handled == bytes) |
bbd9b64e | 4477 | return X86EMUL_CONTINUE; |
bbd9b64e | 4478 | |
70252a10 AK |
4479 | gpa += handled; |
4480 | bytes -= handled; | |
4481 | val += handled; | |
4482 | ||
87da7e66 XG |
4483 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
4484 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
4485 | frag->gpa = gpa; | |
4486 | frag->data = val; | |
4487 | frag->len = bytes; | |
f78146b0 | 4488 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
4489 | } |
4490 | ||
52eb5a6d XL |
4491 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
4492 | unsigned long addr, | |
22388a3c XG |
4493 | void *val, unsigned int bytes, |
4494 | struct x86_exception *exception, | |
0fbe9b0b | 4495 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4496 | { |
0f65dd70 | 4497 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
4498 | gpa_t gpa; |
4499 | int rc; | |
4500 | ||
4501 | if (ops->read_write_prepare && | |
4502 | ops->read_write_prepare(vcpu, val, bytes)) | |
4503 | return X86EMUL_CONTINUE; | |
4504 | ||
4505 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 4506 | |
bbd9b64e CO |
4507 | /* Crossing a page boundary? */ |
4508 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 4509 | int now; |
bbd9b64e CO |
4510 | |
4511 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
4512 | rc = emulator_read_write_onepage(addr, val, now, exception, |
4513 | vcpu, ops); | |
4514 | ||
bbd9b64e CO |
4515 | if (rc != X86EMUL_CONTINUE) |
4516 | return rc; | |
4517 | addr += now; | |
bac15531 NA |
4518 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
4519 | addr = (u32)addr; | |
bbd9b64e CO |
4520 | val += now; |
4521 | bytes -= now; | |
4522 | } | |
22388a3c | 4523 | |
f78146b0 AK |
4524 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
4525 | vcpu, ops); | |
4526 | if (rc != X86EMUL_CONTINUE) | |
4527 | return rc; | |
4528 | ||
4529 | if (!vcpu->mmio_nr_fragments) | |
4530 | return rc; | |
4531 | ||
4532 | gpa = vcpu->mmio_fragments[0].gpa; | |
4533 | ||
4534 | vcpu->mmio_needed = 1; | |
4535 | vcpu->mmio_cur_fragment = 0; | |
4536 | ||
87da7e66 | 4537 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
4538 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
4539 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
4540 | vcpu->run->mmio.phys_addr = gpa; | |
4541 | ||
4542 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
4543 | } |
4544 | ||
4545 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
4546 | unsigned long addr, | |
4547 | void *val, | |
4548 | unsigned int bytes, | |
4549 | struct x86_exception *exception) | |
4550 | { | |
4551 | return emulator_read_write(ctxt, addr, val, bytes, | |
4552 | exception, &read_emultor); | |
4553 | } | |
4554 | ||
52eb5a6d | 4555 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
4556 | unsigned long addr, |
4557 | const void *val, | |
4558 | unsigned int bytes, | |
4559 | struct x86_exception *exception) | |
4560 | { | |
4561 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
4562 | exception, &write_emultor); | |
bbd9b64e | 4563 | } |
bbd9b64e | 4564 | |
daea3e73 AK |
4565 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
4566 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
4567 | ||
4568 | #ifdef CONFIG_X86_64 | |
4569 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
4570 | #else | |
4571 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 4572 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
4573 | #endif |
4574 | ||
0f65dd70 AK |
4575 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
4576 | unsigned long addr, | |
bbd9b64e CO |
4577 | const void *old, |
4578 | const void *new, | |
4579 | unsigned int bytes, | |
0f65dd70 | 4580 | struct x86_exception *exception) |
bbd9b64e | 4581 | { |
0f65dd70 | 4582 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
daea3e73 AK |
4583 | gpa_t gpa; |
4584 | struct page *page; | |
4585 | char *kaddr; | |
4586 | bool exchanged; | |
2bacc55c | 4587 | |
daea3e73 AK |
4588 | /* guests cmpxchg8b have to be emulated atomically */ |
4589 | if (bytes > 8 || (bytes & (bytes - 1))) | |
4590 | goto emul_write; | |
10589a46 | 4591 | |
daea3e73 | 4592 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 4593 | |
daea3e73 AK |
4594 | if (gpa == UNMAPPED_GVA || |
4595 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4596 | goto emul_write; | |
2bacc55c | 4597 | |
daea3e73 AK |
4598 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
4599 | goto emul_write; | |
72dc67a6 | 4600 | |
54bf36aa | 4601 | page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); |
32cad84f | 4602 | if (is_error_page(page)) |
c19b8bd6 | 4603 | goto emul_write; |
72dc67a6 | 4604 | |
8fd75e12 | 4605 | kaddr = kmap_atomic(page); |
daea3e73 AK |
4606 | kaddr += offset_in_page(gpa); |
4607 | switch (bytes) { | |
4608 | case 1: | |
4609 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
4610 | break; | |
4611 | case 2: | |
4612 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
4613 | break; | |
4614 | case 4: | |
4615 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
4616 | break; | |
4617 | case 8: | |
4618 | exchanged = CMPXCHG64(kaddr, old, new); | |
4619 | break; | |
4620 | default: | |
4621 | BUG(); | |
2bacc55c | 4622 | } |
8fd75e12 | 4623 | kunmap_atomic(kaddr); |
daea3e73 AK |
4624 | kvm_release_page_dirty(page); |
4625 | ||
4626 | if (!exchanged) | |
4627 | return X86EMUL_CMPXCHG_FAILED; | |
4628 | ||
54bf36aa | 4629 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
f57f2ef5 | 4630 | kvm_mmu_pte_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
4631 | |
4632 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 4633 | |
3200f405 | 4634 | emul_write: |
daea3e73 | 4635 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 4636 | |
0f65dd70 | 4637 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
4638 | } |
4639 | ||
cf8f70bf GN |
4640 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
4641 | { | |
4642 | /* TODO: String I/O for in kernel device */ | |
4643 | int r; | |
4644 | ||
4645 | if (vcpu->arch.pio.in) | |
e32edf4f | 4646 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, |
cf8f70bf GN |
4647 | vcpu->arch.pio.size, pd); |
4648 | else | |
e32edf4f | 4649 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, |
cf8f70bf GN |
4650 | vcpu->arch.pio.port, vcpu->arch.pio.size, |
4651 | pd); | |
4652 | return r; | |
4653 | } | |
4654 | ||
6f6fbe98 XG |
4655 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
4656 | unsigned short port, void *val, | |
4657 | unsigned int count, bool in) | |
cf8f70bf | 4658 | { |
cf8f70bf | 4659 | vcpu->arch.pio.port = port; |
6f6fbe98 | 4660 | vcpu->arch.pio.in = in; |
7972995b | 4661 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
4662 | vcpu->arch.pio.size = size; |
4663 | ||
4664 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 4665 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4666 | return 1; |
4667 | } | |
4668 | ||
4669 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 4670 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
4671 | vcpu->run->io.size = size; |
4672 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
4673 | vcpu->run->io.count = count; | |
4674 | vcpu->run->io.port = port; | |
4675 | ||
4676 | return 0; | |
4677 | } | |
4678 | ||
6f6fbe98 XG |
4679 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
4680 | int size, unsigned short port, void *val, | |
4681 | unsigned int count) | |
cf8f70bf | 4682 | { |
ca1d4a9e | 4683 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6f6fbe98 | 4684 | int ret; |
ca1d4a9e | 4685 | |
6f6fbe98 XG |
4686 | if (vcpu->arch.pio.count) |
4687 | goto data_avail; | |
cf8f70bf | 4688 | |
6f6fbe98 XG |
4689 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
4690 | if (ret) { | |
4691 | data_avail: | |
4692 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 4693 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 4694 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4695 | return 1; |
4696 | } | |
4697 | ||
cf8f70bf GN |
4698 | return 0; |
4699 | } | |
4700 | ||
6f6fbe98 XG |
4701 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
4702 | int size, unsigned short port, | |
4703 | const void *val, unsigned int count) | |
4704 | { | |
4705 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4706 | ||
4707 | memcpy(vcpu->arch.pio_data, val, size * count); | |
1171903d | 4708 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
4709 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
4710 | } | |
4711 | ||
bbd9b64e CO |
4712 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4713 | { | |
4714 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
4715 | } | |
4716 | ||
3cb16fe7 | 4717 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 4718 | { |
3cb16fe7 | 4719 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
4720 | } |
4721 | ||
5cb56059 | 4722 | int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
4723 | { |
4724 | if (!need_emulate_wbinvd(vcpu)) | |
4725 | return X86EMUL_CONTINUE; | |
4726 | ||
4727 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
4728 | int cpu = get_cpu(); |
4729 | ||
4730 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
4731 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
4732 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 4733 | put_cpu(); |
f5f48ee1 | 4734 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
4735 | } else |
4736 | wbinvd(); | |
f5f48ee1 SY |
4737 | return X86EMUL_CONTINUE; |
4738 | } | |
5cb56059 JS |
4739 | |
4740 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4741 | { | |
4742 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
4743 | return kvm_emulate_wbinvd_noskip(vcpu); | |
4744 | } | |
f5f48ee1 SY |
4745 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
4746 | ||
5cb56059 JS |
4747 | |
4748 | ||
bcaf5cc5 AK |
4749 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
4750 | { | |
5cb56059 | 4751 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
4752 | } |
4753 | ||
52eb5a6d XL |
4754 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
4755 | unsigned long *dest) | |
bbd9b64e | 4756 | { |
16f8a6f9 | 4757 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
4758 | } |
4759 | ||
52eb5a6d XL |
4760 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
4761 | unsigned long value) | |
bbd9b64e | 4762 | { |
338dbc97 | 4763 | |
717746e3 | 4764 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
4765 | } |
4766 | ||
52a46617 | 4767 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 4768 | { |
52a46617 | 4769 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
4770 | } |
4771 | ||
717746e3 | 4772 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 4773 | { |
717746e3 | 4774 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
4775 | unsigned long value; |
4776 | ||
4777 | switch (cr) { | |
4778 | case 0: | |
4779 | value = kvm_read_cr0(vcpu); | |
4780 | break; | |
4781 | case 2: | |
4782 | value = vcpu->arch.cr2; | |
4783 | break; | |
4784 | case 3: | |
9f8fe504 | 4785 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
4786 | break; |
4787 | case 4: | |
4788 | value = kvm_read_cr4(vcpu); | |
4789 | break; | |
4790 | case 8: | |
4791 | value = kvm_get_cr8(vcpu); | |
4792 | break; | |
4793 | default: | |
a737f256 | 4794 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
4795 | return 0; |
4796 | } | |
4797 | ||
4798 | return value; | |
4799 | } | |
4800 | ||
717746e3 | 4801 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 4802 | { |
717746e3 | 4803 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
4804 | int res = 0; |
4805 | ||
52a46617 GN |
4806 | switch (cr) { |
4807 | case 0: | |
49a9b07e | 4808 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
4809 | break; |
4810 | case 2: | |
4811 | vcpu->arch.cr2 = val; | |
4812 | break; | |
4813 | case 3: | |
2390218b | 4814 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
4815 | break; |
4816 | case 4: | |
a83b29c6 | 4817 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
4818 | break; |
4819 | case 8: | |
eea1cff9 | 4820 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
4821 | break; |
4822 | default: | |
a737f256 | 4823 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 4824 | res = -1; |
52a46617 | 4825 | } |
0f12244f GN |
4826 | |
4827 | return res; | |
52a46617 GN |
4828 | } |
4829 | ||
717746e3 | 4830 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 4831 | { |
717746e3 | 4832 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
4833 | } |
4834 | ||
4bff1e86 | 4835 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 4836 | { |
4bff1e86 | 4837 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
4838 | } |
4839 | ||
4bff1e86 | 4840 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 4841 | { |
4bff1e86 | 4842 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
4843 | } |
4844 | ||
1ac9d0cf AK |
4845 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
4846 | { | |
4847 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
4848 | } | |
4849 | ||
4850 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
4851 | { | |
4852 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
4853 | } | |
4854 | ||
4bff1e86 AK |
4855 | static unsigned long emulator_get_cached_segment_base( |
4856 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 4857 | { |
4bff1e86 | 4858 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
4859 | } |
4860 | ||
1aa36616 AK |
4861 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
4862 | struct desc_struct *desc, u32 *base3, | |
4863 | int seg) | |
2dafc6c2 GN |
4864 | { |
4865 | struct kvm_segment var; | |
4866 | ||
4bff1e86 | 4867 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 4868 | *selector = var.selector; |
2dafc6c2 | 4869 | |
378a8b09 GN |
4870 | if (var.unusable) { |
4871 | memset(desc, 0, sizeof(*desc)); | |
2dafc6c2 | 4872 | return false; |
378a8b09 | 4873 | } |
2dafc6c2 GN |
4874 | |
4875 | if (var.g) | |
4876 | var.limit >>= 12; | |
4877 | set_desc_limit(desc, var.limit); | |
4878 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
4879 | #ifdef CONFIG_X86_64 |
4880 | if (base3) | |
4881 | *base3 = var.base >> 32; | |
4882 | #endif | |
2dafc6c2 GN |
4883 | desc->type = var.type; |
4884 | desc->s = var.s; | |
4885 | desc->dpl = var.dpl; | |
4886 | desc->p = var.present; | |
4887 | desc->avl = var.avl; | |
4888 | desc->l = var.l; | |
4889 | desc->d = var.db; | |
4890 | desc->g = var.g; | |
4891 | ||
4892 | return true; | |
4893 | } | |
4894 | ||
1aa36616 AK |
4895 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
4896 | struct desc_struct *desc, u32 base3, | |
4897 | int seg) | |
2dafc6c2 | 4898 | { |
4bff1e86 | 4899 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
4900 | struct kvm_segment var; |
4901 | ||
1aa36616 | 4902 | var.selector = selector; |
2dafc6c2 | 4903 | var.base = get_desc_base(desc); |
5601d05b GN |
4904 | #ifdef CONFIG_X86_64 |
4905 | var.base |= ((u64)base3) << 32; | |
4906 | #endif | |
2dafc6c2 GN |
4907 | var.limit = get_desc_limit(desc); |
4908 | if (desc->g) | |
4909 | var.limit = (var.limit << 12) | 0xfff; | |
4910 | var.type = desc->type; | |
2dafc6c2 GN |
4911 | var.dpl = desc->dpl; |
4912 | var.db = desc->d; | |
4913 | var.s = desc->s; | |
4914 | var.l = desc->l; | |
4915 | var.g = desc->g; | |
4916 | var.avl = desc->avl; | |
4917 | var.present = desc->p; | |
4918 | var.unusable = !var.present; | |
4919 | var.padding = 0; | |
4920 | ||
4921 | kvm_set_segment(vcpu, &var, seg); | |
4922 | return; | |
4923 | } | |
4924 | ||
717746e3 AK |
4925 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
4926 | u32 msr_index, u64 *pdata) | |
4927 | { | |
609e36d3 PB |
4928 | struct msr_data msr; |
4929 | int r; | |
4930 | ||
4931 | msr.index = msr_index; | |
4932 | msr.host_initiated = false; | |
4933 | r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); | |
4934 | if (r) | |
4935 | return r; | |
4936 | ||
4937 | *pdata = msr.data; | |
4938 | return 0; | |
717746e3 AK |
4939 | } |
4940 | ||
4941 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
4942 | u32 msr_index, u64 data) | |
4943 | { | |
8fe8ab46 WA |
4944 | struct msr_data msr; |
4945 | ||
4946 | msr.data = data; | |
4947 | msr.index = msr_index; | |
4948 | msr.host_initiated = false; | |
4949 | return kvm_set_msr(emul_to_vcpu(ctxt), &msr); | |
717746e3 AK |
4950 | } |
4951 | ||
64d60670 PB |
4952 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
4953 | { | |
4954 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4955 | ||
4956 | return vcpu->arch.smbase; | |
4957 | } | |
4958 | ||
4959 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
4960 | { | |
4961 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4962 | ||
4963 | vcpu->arch.smbase = smbase; | |
4964 | } | |
4965 | ||
67f4d428 NA |
4966 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
4967 | u32 pmc) | |
4968 | { | |
4969 | return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc); | |
4970 | } | |
4971 | ||
222d21aa AK |
4972 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
4973 | u32 pmc, u64 *pdata) | |
4974 | { | |
4975 | return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); | |
4976 | } | |
4977 | ||
6c3287f7 AK |
4978 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
4979 | { | |
4980 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
4981 | } | |
4982 | ||
5037f6f3 AK |
4983 | static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) |
4984 | { | |
4985 | preempt_disable(); | |
5197b808 | 4986 | kvm_load_guest_fpu(emul_to_vcpu(ctxt)); |
5037f6f3 AK |
4987 | /* |
4988 | * CR0.TS may reference the host fpu state, not the guest fpu state, | |
4989 | * so it may be clear at this point. | |
4990 | */ | |
4991 | clts(); | |
4992 | } | |
4993 | ||
4994 | static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) | |
4995 | { | |
4996 | preempt_enable(); | |
4997 | } | |
4998 | ||
2953538e | 4999 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 5000 | struct x86_instruction_info *info, |
c4f035c6 AK |
5001 | enum x86_intercept_stage stage) |
5002 | { | |
2953538e | 5003 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
c4f035c6 AK |
5004 | } |
5005 | ||
0017f93a | 5006 | static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
bdb42f5a SB |
5007 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) |
5008 | { | |
0017f93a | 5009 | kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); |
bdb42f5a SB |
5010 | } |
5011 | ||
dd856efa AK |
5012 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
5013 | { | |
5014 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
5015 | } | |
5016 | ||
5017 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
5018 | { | |
5019 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
5020 | } | |
5021 | ||
801806d9 NA |
5022 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
5023 | { | |
5024 | kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); | |
5025 | } | |
5026 | ||
0225fb50 | 5027 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
5028 | .read_gpr = emulator_read_gpr, |
5029 | .write_gpr = emulator_write_gpr, | |
1871c602 | 5030 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 5031 | .write_std = kvm_write_guest_virt_system, |
1871c602 | 5032 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
5033 | .read_emulated = emulator_read_emulated, |
5034 | .write_emulated = emulator_write_emulated, | |
5035 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 5036 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
5037 | .pio_in_emulated = emulator_pio_in_emulated, |
5038 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
5039 | .get_segment = emulator_get_segment, |
5040 | .set_segment = emulator_set_segment, | |
5951c442 | 5041 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 5042 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 5043 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
5044 | .set_gdt = emulator_set_gdt, |
5045 | .set_idt = emulator_set_idt, | |
52a46617 GN |
5046 | .get_cr = emulator_get_cr, |
5047 | .set_cr = emulator_set_cr, | |
9c537244 | 5048 | .cpl = emulator_get_cpl, |
35aa5375 GN |
5049 | .get_dr = emulator_get_dr, |
5050 | .set_dr = emulator_set_dr, | |
64d60670 PB |
5051 | .get_smbase = emulator_get_smbase, |
5052 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
5053 | .set_msr = emulator_set_msr, |
5054 | .get_msr = emulator_get_msr, | |
67f4d428 | 5055 | .check_pmc = emulator_check_pmc, |
222d21aa | 5056 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 5057 | .halt = emulator_halt, |
bcaf5cc5 | 5058 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 5059 | .fix_hypercall = emulator_fix_hypercall, |
5037f6f3 AK |
5060 | .get_fpu = emulator_get_fpu, |
5061 | .put_fpu = emulator_put_fpu, | |
c4f035c6 | 5062 | .intercept = emulator_intercept, |
bdb42f5a | 5063 | .get_cpuid = emulator_get_cpuid, |
801806d9 | 5064 | .set_nmi_mask = emulator_set_nmi_mask, |
bbd9b64e CO |
5065 | }; |
5066 | ||
95cb2295 GN |
5067 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
5068 | { | |
37ccdcbe | 5069 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
95cb2295 GN |
5070 | /* |
5071 | * an sti; sti; sequence only disable interrupts for the first | |
5072 | * instruction. So, if the last instruction, be it emulated or | |
5073 | * not, left the system with the INT_STI flag enabled, it | |
5074 | * means that the last instruction is an sti. We should not | |
5075 | * leave the flag on in this case. The same goes for mov ss | |
5076 | */ | |
37ccdcbe PB |
5077 | if (int_shadow & mask) |
5078 | mask = 0; | |
6addfc42 | 5079 | if (unlikely(int_shadow || mask)) { |
95cb2295 | 5080 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
5081 | if (!mask) |
5082 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5083 | } | |
95cb2295 GN |
5084 | } |
5085 | ||
ef54bcfe | 5086 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f GN |
5087 | { |
5088 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 5089 | if (ctxt->exception.vector == PF_VECTOR) |
ef54bcfe PB |
5090 | return kvm_propagate_fault(vcpu, &ctxt->exception); |
5091 | ||
5092 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
5093 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
5094 | ctxt->exception.error_code); | |
54b8486f | 5095 | else |
da9cb575 | 5096 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 5097 | return false; |
54b8486f GN |
5098 | } |
5099 | ||
8ec4722d MG |
5100 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
5101 | { | |
adf52235 | 5102 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d MG |
5103 | int cs_db, cs_l; |
5104 | ||
8ec4722d MG |
5105 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
5106 | ||
adf52235 TY |
5107 | ctxt->eflags = kvm_get_rflags(vcpu); |
5108 | ctxt->eip = kvm_rip_read(vcpu); | |
5109 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
5110 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 5111 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
5112 | cs_db ? X86EMUL_MODE_PROT32 : |
5113 | X86EMUL_MODE_PROT16; | |
a584539b | 5114 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
5115 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
5116 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
a584539b | 5117 | ctxt->emul_flags = vcpu->arch.hflags; |
adf52235 | 5118 | |
dd856efa | 5119 | init_decode_cache(ctxt); |
7ae441ea | 5120 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
5121 | } |
5122 | ||
71f9833b | 5123 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 5124 | { |
9d74191a | 5125 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
63995653 MG |
5126 | int ret; |
5127 | ||
5128 | init_emulate_ctxt(vcpu); | |
5129 | ||
9dac77fa AK |
5130 | ctxt->op_bytes = 2; |
5131 | ctxt->ad_bytes = 2; | |
5132 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 5133 | ret = emulate_int_real(ctxt, irq); |
63995653 MG |
5134 | |
5135 | if (ret != X86EMUL_CONTINUE) | |
5136 | return EMULATE_FAIL; | |
5137 | ||
9dac77fa | 5138 | ctxt->eip = ctxt->_eip; |
9d74191a TY |
5139 | kvm_rip_write(vcpu, ctxt->eip); |
5140 | kvm_set_rflags(vcpu, ctxt->eflags); | |
63995653 MG |
5141 | |
5142 | if (irq == NMI_VECTOR) | |
7460fb4a | 5143 | vcpu->arch.nmi_pending = 0; |
63995653 MG |
5144 | else |
5145 | vcpu->arch.interrupt.pending = false; | |
5146 | ||
5147 | return EMULATE_DONE; | |
5148 | } | |
5149 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
5150 | ||
6d77dbfc GN |
5151 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
5152 | { | |
fc3a9157 JR |
5153 | int r = EMULATE_DONE; |
5154 | ||
6d77dbfc GN |
5155 | ++vcpu->stat.insn_emulation_fail; |
5156 | trace_kvm_emulate_insn_failed(vcpu); | |
a2b9e6c1 | 5157 | if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { |
fc3a9157 JR |
5158 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
5159 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
5160 | vcpu->run->internal.ndata = 0; | |
5161 | r = EMULATE_FAIL; | |
5162 | } | |
6d77dbfc | 5163 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
5164 | |
5165 | return r; | |
6d77dbfc GN |
5166 | } |
5167 | ||
93c05d3e | 5168 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, |
991eebf9 GN |
5169 | bool write_fault_to_shadow_pgtable, |
5170 | int emulation_type) | |
a6f177ef | 5171 | { |
95b3cf69 | 5172 | gpa_t gpa = cr2; |
8e3d9d06 | 5173 | pfn_t pfn; |
a6f177ef | 5174 | |
991eebf9 GN |
5175 | if (emulation_type & EMULTYPE_NO_REEXECUTE) |
5176 | return false; | |
5177 | ||
95b3cf69 XG |
5178 | if (!vcpu->arch.mmu.direct_map) { |
5179 | /* | |
5180 | * Write permission should be allowed since only | |
5181 | * write access need to be emulated. | |
5182 | */ | |
5183 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
a6f177ef | 5184 | |
95b3cf69 XG |
5185 | /* |
5186 | * If the mapping is invalid in guest, let cpu retry | |
5187 | * it to generate fault. | |
5188 | */ | |
5189 | if (gpa == UNMAPPED_GVA) | |
5190 | return true; | |
5191 | } | |
a6f177ef | 5192 | |
8e3d9d06 XG |
5193 | /* |
5194 | * Do not retry the unhandleable instruction if it faults on the | |
5195 | * readonly host memory, otherwise it will goto a infinite loop: | |
5196 | * retry instruction -> write #PF -> emulation fail -> retry | |
5197 | * instruction -> ... | |
5198 | */ | |
5199 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
5200 | |
5201 | /* | |
5202 | * If the instruction failed on the error pfn, it can not be fixed, | |
5203 | * report the error to userspace. | |
5204 | */ | |
5205 | if (is_error_noslot_pfn(pfn)) | |
5206 | return false; | |
5207 | ||
5208 | kvm_release_pfn_clean(pfn); | |
5209 | ||
5210 | /* The instructions are well-emulated on direct mmu. */ | |
5211 | if (vcpu->arch.mmu.direct_map) { | |
5212 | unsigned int indirect_shadow_pages; | |
5213 | ||
5214 | spin_lock(&vcpu->kvm->mmu_lock); | |
5215 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
5216 | spin_unlock(&vcpu->kvm->mmu_lock); | |
5217 | ||
5218 | if (indirect_shadow_pages) | |
5219 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
5220 | ||
a6f177ef | 5221 | return true; |
8e3d9d06 | 5222 | } |
a6f177ef | 5223 | |
95b3cf69 XG |
5224 | /* |
5225 | * if emulation was due to access to shadowed page table | |
5226 | * and it failed try to unshadow page and re-enter the | |
5227 | * guest to let CPU execute the instruction. | |
5228 | */ | |
5229 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
5230 | |
5231 | /* | |
5232 | * If the access faults on its page table, it can not | |
5233 | * be fixed by unprotecting shadow page and it should | |
5234 | * be reported to userspace. | |
5235 | */ | |
5236 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
5237 | } |
5238 | ||
1cb3f3ae XG |
5239 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
5240 | unsigned long cr2, int emulation_type) | |
5241 | { | |
5242 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5243 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2; | |
5244 | ||
5245 | last_retry_eip = vcpu->arch.last_retry_eip; | |
5246 | last_retry_addr = vcpu->arch.last_retry_addr; | |
5247 | ||
5248 | /* | |
5249 | * If the emulation is caused by #PF and it is non-page_table | |
5250 | * writing instruction, it means the VM-EXIT is caused by shadow | |
5251 | * page protected, we can zap the shadow page and retry this | |
5252 | * instruction directly. | |
5253 | * | |
5254 | * Note: if the guest uses a non-page-table modifying instruction | |
5255 | * on the PDE that points to the instruction, then we will unmap | |
5256 | * the instruction and go to an infinite loop. So, we cache the | |
5257 | * last retried eip and the last fault address, if we meet the eip | |
5258 | * and the address again, we can break out of the potential infinite | |
5259 | * loop. | |
5260 | */ | |
5261 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
5262 | ||
5263 | if (!(emulation_type & EMULTYPE_RETRY)) | |
5264 | return false; | |
5265 | ||
5266 | if (x86_page_table_writing_insn(ctxt)) | |
5267 | return false; | |
5268 | ||
5269 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) | |
5270 | return false; | |
5271 | ||
5272 | vcpu->arch.last_retry_eip = ctxt->eip; | |
5273 | vcpu->arch.last_retry_addr = cr2; | |
5274 | ||
5275 | if (!vcpu->arch.mmu.direct_map) | |
5276 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
5277 | ||
22368028 | 5278 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
5279 | |
5280 | return true; | |
5281 | } | |
5282 | ||
716d51ab GN |
5283 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
5284 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
5285 | ||
64d60670 | 5286 | static void kvm_smm_changed(struct kvm_vcpu *vcpu) |
a584539b | 5287 | { |
64d60670 | 5288 | if (!(vcpu->arch.hflags & HF_SMM_MASK)) { |
660a5d51 PB |
5289 | /* This is a good place to trace that we are exiting SMM. */ |
5290 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); | |
5291 | ||
64d60670 PB |
5292 | if (unlikely(vcpu->arch.smi_pending)) { |
5293 | kvm_make_request(KVM_REQ_SMI, vcpu); | |
5294 | vcpu->arch.smi_pending = 0; | |
cd7764fe PB |
5295 | } else { |
5296 | /* Process a latched INIT, if any. */ | |
5297 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 PB |
5298 | } |
5299 | } | |
699023e2 PB |
5300 | |
5301 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
5302 | } |
5303 | ||
5304 | static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) | |
5305 | { | |
5306 | unsigned changed = vcpu->arch.hflags ^ emul_flags; | |
5307 | ||
a584539b | 5308 | vcpu->arch.hflags = emul_flags; |
64d60670 PB |
5309 | |
5310 | if (changed & HF_SMM_MASK) | |
5311 | kvm_smm_changed(vcpu); | |
a584539b PB |
5312 | } |
5313 | ||
4a1e10d5 PB |
5314 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
5315 | unsigned long *db) | |
5316 | { | |
5317 | u32 dr6 = 0; | |
5318 | int i; | |
5319 | u32 enable, rwlen; | |
5320 | ||
5321 | enable = dr7; | |
5322 | rwlen = dr7 >> 16; | |
5323 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
5324 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
5325 | dr6 |= (1 << i); | |
5326 | return dr6; | |
5327 | } | |
5328 | ||
6addfc42 | 5329 | static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) |
663f4c61 PB |
5330 | { |
5331 | struct kvm_run *kvm_run = vcpu->run; | |
5332 | ||
5333 | /* | |
6addfc42 PB |
5334 | * rflags is the old, "raw" value of the flags. The new value has |
5335 | * not been saved yet. | |
663f4c61 PB |
5336 | * |
5337 | * This is correct even for TF set by the guest, because "the | |
5338 | * processor will not generate this exception after the instruction | |
5339 | * that sets the TF flag". | |
5340 | */ | |
663f4c61 PB |
5341 | if (unlikely(rflags & X86_EFLAGS_TF)) { |
5342 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { | |
6f43ed01 NA |
5343 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | |
5344 | DR6_RTM; | |
663f4c61 PB |
5345 | kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; |
5346 | kvm_run->debug.arch.exception = DB_VECTOR; | |
5347 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5348 | *r = EMULATE_USER_EXIT; | |
5349 | } else { | |
5350 | vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; | |
5351 | /* | |
5352 | * "Certain debug exceptions may clear bit 0-3. The | |
5353 | * remaining contents of the DR6 register are never | |
5354 | * cleared by the processor". | |
5355 | */ | |
5356 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5357 | vcpu->arch.dr6 |= DR6_BS | DR6_RTM; |
663f4c61 PB |
5358 | kvm_queue_exception(vcpu, DB_VECTOR); |
5359 | } | |
5360 | } | |
5361 | } | |
5362 | ||
4a1e10d5 PB |
5363 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
5364 | { | |
4a1e10d5 PB |
5365 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
5366 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
5367 | struct kvm_run *kvm_run = vcpu->run; |
5368 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
5369 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5370 | vcpu->arch.guest_debug_dr7, |
5371 | vcpu->arch.eff_db); | |
5372 | ||
5373 | if (dr6 != 0) { | |
6f43ed01 | 5374 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 5375 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
5376 | kvm_run->debug.arch.exception = DB_VECTOR; |
5377 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5378 | *r = EMULATE_USER_EXIT; | |
5379 | return true; | |
5380 | } | |
5381 | } | |
5382 | ||
4161a569 NA |
5383 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
5384 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
5385 | unsigned long eip = kvm_get_linear_rip(vcpu); |
5386 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5387 | vcpu->arch.dr7, |
5388 | vcpu->arch.db); | |
5389 | ||
5390 | if (dr6 != 0) { | |
5391 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5392 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
4a1e10d5 PB |
5393 | kvm_queue_exception(vcpu, DB_VECTOR); |
5394 | *r = EMULATE_DONE; | |
5395 | return true; | |
5396 | } | |
5397 | } | |
5398 | ||
5399 | return false; | |
5400 | } | |
5401 | ||
51d8b661 AP |
5402 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
5403 | unsigned long cr2, | |
dc25e89e AP |
5404 | int emulation_type, |
5405 | void *insn, | |
5406 | int insn_len) | |
bbd9b64e | 5407 | { |
95cb2295 | 5408 | int r; |
9d74191a | 5409 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
7ae441ea | 5410 | bool writeback = true; |
93c05d3e | 5411 | bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
bbd9b64e | 5412 | |
93c05d3e XG |
5413 | /* |
5414 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
5415 | * never reused. | |
5416 | */ | |
5417 | vcpu->arch.write_fault_to_shadow_pgtable = false; | |
26eef70c | 5418 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 5419 | |
571008da | 5420 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 5421 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
5422 | |
5423 | /* | |
5424 | * We will reenter on the same instruction since | |
5425 | * we do not set complete_userspace_io. This does not | |
5426 | * handle watchpoints yet, those would be handled in | |
5427 | * the emulate_ops. | |
5428 | */ | |
5429 | if (kvm_vcpu_check_breakpoint(vcpu, &r)) | |
5430 | return r; | |
5431 | ||
9d74191a TY |
5432 | ctxt->interruptibility = 0; |
5433 | ctxt->have_exception = false; | |
e0ad0b47 | 5434 | ctxt->exception.vector = -1; |
9d74191a | 5435 | ctxt->perm_ok = false; |
bbd9b64e | 5436 | |
b51e974f | 5437 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 5438 | |
9d74191a | 5439 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 5440 | |
e46479f8 | 5441 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 5442 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 5443 | if (r != EMULATION_OK) { |
4005996e AK |
5444 | if (emulation_type & EMULTYPE_TRAP_UD) |
5445 | return EMULATE_FAIL; | |
991eebf9 GN |
5446 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
5447 | emulation_type)) | |
bbd9b64e | 5448 | return EMULATE_DONE; |
6d77dbfc GN |
5449 | if (emulation_type & EMULTYPE_SKIP) |
5450 | return EMULATE_FAIL; | |
5451 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
5452 | } |
5453 | } | |
5454 | ||
ba8afb6b | 5455 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 5456 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
5457 | if (ctxt->eflags & X86_EFLAGS_RF) |
5458 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
ba8afb6b GN |
5459 | return EMULATE_DONE; |
5460 | } | |
5461 | ||
1cb3f3ae XG |
5462 | if (retry_instruction(ctxt, cr2, emulation_type)) |
5463 | return EMULATE_DONE; | |
5464 | ||
7ae441ea | 5465 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 5466 | changes registers values during IO operation */ |
7ae441ea GN |
5467 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
5468 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 5469 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 5470 | } |
4d2179e1 | 5471 | |
5cd21917 | 5472 | restart: |
9d74191a | 5473 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 5474 | |
775fde86 JR |
5475 | if (r == EMULATION_INTERCEPTED) |
5476 | return EMULATE_DONE; | |
5477 | ||
d2ddd1c4 | 5478 | if (r == EMULATION_FAILED) { |
991eebf9 GN |
5479 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
5480 | emulation_type)) | |
c3cd7ffa GN |
5481 | return EMULATE_DONE; |
5482 | ||
6d77dbfc | 5483 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
5484 | } |
5485 | ||
9d74191a | 5486 | if (ctxt->have_exception) { |
d2ddd1c4 | 5487 | r = EMULATE_DONE; |
ef54bcfe PB |
5488 | if (inject_emulated_exception(vcpu)) |
5489 | return r; | |
d2ddd1c4 | 5490 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
5491 | if (!vcpu->arch.pio.in) { |
5492 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 5493 | vcpu->arch.pio.count = 0; |
0912c977 | 5494 | } else { |
7ae441ea | 5495 | writeback = false; |
716d51ab GN |
5496 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
5497 | } | |
ac0a48c3 | 5498 | r = EMULATE_USER_EXIT; |
7ae441ea GN |
5499 | } else if (vcpu->mmio_needed) { |
5500 | if (!vcpu->mmio_is_write) | |
5501 | writeback = false; | |
ac0a48c3 | 5502 | r = EMULATE_USER_EXIT; |
716d51ab | 5503 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 5504 | } else if (r == EMULATION_RESTART) |
5cd21917 | 5505 | goto restart; |
d2ddd1c4 GN |
5506 | else |
5507 | r = EMULATE_DONE; | |
f850e2e6 | 5508 | |
7ae441ea | 5509 | if (writeback) { |
6addfc42 | 5510 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); |
9d74191a | 5511 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 5512 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
a584539b PB |
5513 | if (vcpu->arch.hflags != ctxt->emul_flags) |
5514 | kvm_set_hflags(vcpu, ctxt->emul_flags); | |
9d74191a | 5515 | kvm_rip_write(vcpu, ctxt->eip); |
663f4c61 | 5516 | if (r == EMULATE_DONE) |
6addfc42 | 5517 | kvm_vcpu_check_singlestep(vcpu, rflags, &r); |
38827dbd NA |
5518 | if (!ctxt->have_exception || |
5519 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) | |
5520 | __kvm_set_rflags(vcpu, ctxt->eflags); | |
6addfc42 PB |
5521 | |
5522 | /* | |
5523 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
5524 | * do nothing, and it will be requested again as soon as | |
5525 | * the shadow expires. But we still need to check here, | |
5526 | * because POPF has no interrupt shadow. | |
5527 | */ | |
5528 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
5529 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
5530 | } else |
5531 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
5532 | |
5533 | return r; | |
de7d789a | 5534 | } |
51d8b661 | 5535 | EXPORT_SYMBOL_GPL(x86_emulate_instruction); |
de7d789a | 5536 | |
cf8f70bf | 5537 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 5538 | { |
cf8f70bf | 5539 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
ca1d4a9e AK |
5540 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, |
5541 | size, port, &val, 1); | |
cf8f70bf | 5542 | /* do not return to emulator after return from userspace */ |
7972995b | 5543 | vcpu->arch.pio.count = 0; |
de7d789a CO |
5544 | return ret; |
5545 | } | |
cf8f70bf | 5546 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 5547 | |
8cfdc000 ZA |
5548 | static void tsc_bad(void *info) |
5549 | { | |
0a3aee0d | 5550 | __this_cpu_write(cpu_tsc_khz, 0); |
8cfdc000 ZA |
5551 | } |
5552 | ||
5553 | static void tsc_khz_changed(void *data) | |
c8076604 | 5554 | { |
8cfdc000 ZA |
5555 | struct cpufreq_freqs *freq = data; |
5556 | unsigned long khz = 0; | |
5557 | ||
5558 | if (data) | |
5559 | khz = freq->new; | |
5560 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
5561 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
5562 | if (!khz) | |
5563 | khz = tsc_khz; | |
0a3aee0d | 5564 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
5565 | } |
5566 | ||
c8076604 GH |
5567 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
5568 | void *data) | |
5569 | { | |
5570 | struct cpufreq_freqs *freq = data; | |
5571 | struct kvm *kvm; | |
5572 | struct kvm_vcpu *vcpu; | |
5573 | int i, send_ipi = 0; | |
5574 | ||
8cfdc000 ZA |
5575 | /* |
5576 | * We allow guests to temporarily run on slowing clocks, | |
5577 | * provided we notify them after, or to run on accelerating | |
5578 | * clocks, provided we notify them before. Thus time never | |
5579 | * goes backwards. | |
5580 | * | |
5581 | * However, we have a problem. We can't atomically update | |
5582 | * the frequency of a given CPU from this function; it is | |
5583 | * merely a notifier, which can be called from any CPU. | |
5584 | * Changing the TSC frequency at arbitrary points in time | |
5585 | * requires a recomputation of local variables related to | |
5586 | * the TSC for each VCPU. We must flag these local variables | |
5587 | * to be updated and be sure the update takes place with the | |
5588 | * new frequency before any guests proceed. | |
5589 | * | |
5590 | * Unfortunately, the combination of hotplug CPU and frequency | |
5591 | * change creates an intractable locking scenario; the order | |
5592 | * of when these callouts happen is undefined with respect to | |
5593 | * CPU hotplug, and they can race with each other. As such, | |
5594 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
5595 | * undefined; you can actually have a CPU frequency change take | |
5596 | * place in between the computation of X and the setting of the | |
5597 | * variable. To protect against this problem, all updates of | |
5598 | * the per_cpu tsc_khz variable are done in an interrupt | |
5599 | * protected IPI, and all callers wishing to update the value | |
5600 | * must wait for a synchronous IPI to complete (which is trivial | |
5601 | * if the caller is on the CPU already). This establishes the | |
5602 | * necessary total order on variable updates. | |
5603 | * | |
5604 | * Note that because a guest time update may take place | |
5605 | * anytime after the setting of the VCPU's request bit, the | |
5606 | * correct TSC value must be set before the request. However, | |
5607 | * to ensure the update actually makes it to any guest which | |
5608 | * starts running in hardware virtualization between the set | |
5609 | * and the acquisition of the spinlock, we must also ping the | |
5610 | * CPU after setting the request bit. | |
5611 | * | |
5612 | */ | |
5613 | ||
c8076604 GH |
5614 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
5615 | return 0; | |
5616 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
5617 | return 0; | |
8cfdc000 ZA |
5618 | |
5619 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 | 5620 | |
2f303b74 | 5621 | spin_lock(&kvm_lock); |
c8076604 | 5622 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 5623 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
5624 | if (vcpu->cpu != freq->cpu) |
5625 | continue; | |
c285545f | 5626 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c8076604 | 5627 | if (vcpu->cpu != smp_processor_id()) |
8cfdc000 | 5628 | send_ipi = 1; |
c8076604 GH |
5629 | } |
5630 | } | |
2f303b74 | 5631 | spin_unlock(&kvm_lock); |
c8076604 GH |
5632 | |
5633 | if (freq->old < freq->new && send_ipi) { | |
5634 | /* | |
5635 | * We upscale the frequency. Must make the guest | |
5636 | * doesn't see old kvmclock values while running with | |
5637 | * the new frequency, otherwise we risk the guest sees | |
5638 | * time go backwards. | |
5639 | * | |
5640 | * In case we update the frequency for another cpu | |
5641 | * (which might be in guest context) send an interrupt | |
5642 | * to kick the cpu out of guest context. Next time | |
5643 | * guest context is entered kvmclock will be updated, | |
5644 | * so the guest will not see stale values. | |
5645 | */ | |
8cfdc000 | 5646 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
5647 | } |
5648 | return 0; | |
5649 | } | |
5650 | ||
5651 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
5652 | .notifier_call = kvmclock_cpufreq_notifier |
5653 | }; | |
5654 | ||
5655 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
5656 | unsigned long action, void *hcpu) | |
5657 | { | |
5658 | unsigned int cpu = (unsigned long)hcpu; | |
5659 | ||
5660 | switch (action) { | |
5661 | case CPU_ONLINE: | |
5662 | case CPU_DOWN_FAILED: | |
5663 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
5664 | break; | |
5665 | case CPU_DOWN_PREPARE: | |
5666 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
5667 | break; | |
5668 | } | |
5669 | return NOTIFY_OK; | |
5670 | } | |
5671 | ||
5672 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
5673 | .notifier_call = kvmclock_cpu_notifier, | |
5674 | .priority = -INT_MAX | |
c8076604 GH |
5675 | }; |
5676 | ||
b820cc0c ZA |
5677 | static void kvm_timer_init(void) |
5678 | { | |
5679 | int cpu; | |
5680 | ||
c285545f | 5681 | max_tsc_khz = tsc_khz; |
460dd42e SB |
5682 | |
5683 | cpu_notifier_register_begin(); | |
b820cc0c | 5684 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
5685 | #ifdef CONFIG_CPU_FREQ |
5686 | struct cpufreq_policy policy; | |
5687 | memset(&policy, 0, sizeof(policy)); | |
3e26f230 AK |
5688 | cpu = get_cpu(); |
5689 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
5690 | if (policy.cpuinfo.max_freq) |
5691 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 5692 | put_cpu(); |
c285545f | 5693 | #endif |
b820cc0c ZA |
5694 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
5695 | CPUFREQ_TRANSITION_NOTIFIER); | |
5696 | } | |
c285545f | 5697 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); |
8cfdc000 ZA |
5698 | for_each_online_cpu(cpu) |
5699 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
460dd42e SB |
5700 | |
5701 | __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); | |
5702 | cpu_notifier_register_done(); | |
5703 | ||
b820cc0c ZA |
5704 | } |
5705 | ||
ff9d07a0 ZY |
5706 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
5707 | ||
f5132b01 | 5708 | int kvm_is_in_guest(void) |
ff9d07a0 | 5709 | { |
086c9855 | 5710 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
5711 | } |
5712 | ||
5713 | static int kvm_is_user_mode(void) | |
5714 | { | |
5715 | int user_mode = 3; | |
dcf46b94 | 5716 | |
086c9855 AS |
5717 | if (__this_cpu_read(current_vcpu)) |
5718 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5719 | |
ff9d07a0 ZY |
5720 | return user_mode != 0; |
5721 | } | |
5722 | ||
5723 | static unsigned long kvm_get_guest_ip(void) | |
5724 | { | |
5725 | unsigned long ip = 0; | |
dcf46b94 | 5726 | |
086c9855 AS |
5727 | if (__this_cpu_read(current_vcpu)) |
5728 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5729 | |
ff9d07a0 ZY |
5730 | return ip; |
5731 | } | |
5732 | ||
5733 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
5734 | .is_in_guest = kvm_is_in_guest, | |
5735 | .is_user_mode = kvm_is_user_mode, | |
5736 | .get_guest_ip = kvm_get_guest_ip, | |
5737 | }; | |
5738 | ||
5739 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
5740 | { | |
086c9855 | 5741 | __this_cpu_write(current_vcpu, vcpu); |
ff9d07a0 ZY |
5742 | } |
5743 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
5744 | ||
5745 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
5746 | { | |
086c9855 | 5747 | __this_cpu_write(current_vcpu, NULL); |
ff9d07a0 ZY |
5748 | } |
5749 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
5750 | ||
ce88decf XG |
5751 | static void kvm_set_mmio_spte_mask(void) |
5752 | { | |
5753 | u64 mask; | |
5754 | int maxphyaddr = boot_cpu_data.x86_phys_bits; | |
5755 | ||
5756 | /* | |
5757 | * Set the reserved bits and the present bit of an paging-structure | |
5758 | * entry to generate page fault with PFER.RSV = 1. | |
5759 | */ | |
885032b9 | 5760 | /* Mask the reserved physical address bits. */ |
d1431483 | 5761 | mask = rsvd_bits(maxphyaddr, 51); |
885032b9 XG |
5762 | |
5763 | /* Bit 62 is always reserved for 32bit host. */ | |
5764 | mask |= 0x3ull << 62; | |
5765 | ||
5766 | /* Set the present bit. */ | |
ce88decf XG |
5767 | mask |= 1ull; |
5768 | ||
5769 | #ifdef CONFIG_X86_64 | |
5770 | /* | |
5771 | * If reserved bit is not supported, clear the present bit to disable | |
5772 | * mmio page fault. | |
5773 | */ | |
5774 | if (maxphyaddr == 52) | |
5775 | mask &= ~1ull; | |
5776 | #endif | |
5777 | ||
5778 | kvm_mmu_set_mmio_spte_mask(mask); | |
5779 | } | |
5780 | ||
16e8d74d MT |
5781 | #ifdef CONFIG_X86_64 |
5782 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
5783 | { | |
d828199e MT |
5784 | struct kvm *kvm; |
5785 | ||
5786 | struct kvm_vcpu *vcpu; | |
5787 | int i; | |
5788 | ||
2f303b74 | 5789 | spin_lock(&kvm_lock); |
d828199e MT |
5790 | list_for_each_entry(kvm, &vm_list, vm_list) |
5791 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 5792 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 5793 | atomic_set(&kvm_guest_has_master_clock, 0); |
2f303b74 | 5794 | spin_unlock(&kvm_lock); |
16e8d74d MT |
5795 | } |
5796 | ||
5797 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
5798 | ||
5799 | /* | |
5800 | * Notification about pvclock gtod data update. | |
5801 | */ | |
5802 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
5803 | void *priv) | |
5804 | { | |
5805 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
5806 | struct timekeeper *tk = priv; | |
5807 | ||
5808 | update_pvclock_gtod(tk); | |
5809 | ||
5810 | /* disable master clock if host does not trust, or does not | |
5811 | * use, TSC clocksource | |
5812 | */ | |
5813 | if (gtod->clock.vclock_mode != VCLOCK_TSC && | |
5814 | atomic_read(&kvm_guest_has_master_clock) != 0) | |
5815 | queue_work(system_long_wq, &pvclock_gtod_work); | |
5816 | ||
5817 | return 0; | |
5818 | } | |
5819 | ||
5820 | static struct notifier_block pvclock_gtod_notifier = { | |
5821 | .notifier_call = pvclock_gtod_notify, | |
5822 | }; | |
5823 | #endif | |
5824 | ||
f8c16bba | 5825 | int kvm_arch_init(void *opaque) |
043405e1 | 5826 | { |
b820cc0c | 5827 | int r; |
6b61edf7 | 5828 | struct kvm_x86_ops *ops = opaque; |
f8c16bba | 5829 | |
f8c16bba ZX |
5830 | if (kvm_x86_ops) { |
5831 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
5832 | r = -EEXIST; |
5833 | goto out; | |
f8c16bba ZX |
5834 | } |
5835 | ||
5836 | if (!ops->cpu_has_kvm_support()) { | |
5837 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
5838 | r = -EOPNOTSUPP; |
5839 | goto out; | |
f8c16bba ZX |
5840 | } |
5841 | if (ops->disabled_by_bios()) { | |
5842 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
5843 | r = -EOPNOTSUPP; |
5844 | goto out; | |
f8c16bba ZX |
5845 | } |
5846 | ||
013f6a5d MT |
5847 | r = -ENOMEM; |
5848 | shared_msrs = alloc_percpu(struct kvm_shared_msrs); | |
5849 | if (!shared_msrs) { | |
5850 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); | |
5851 | goto out; | |
5852 | } | |
5853 | ||
97db56ce AK |
5854 | r = kvm_mmu_module_init(); |
5855 | if (r) | |
013f6a5d | 5856 | goto out_free_percpu; |
97db56ce | 5857 | |
ce88decf | 5858 | kvm_set_mmio_spte_mask(); |
97db56ce | 5859 | |
f8c16bba | 5860 | kvm_x86_ops = ops; |
920c8377 | 5861 | |
7b52345e | 5862 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
4b12f0de | 5863 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 5864 | |
b820cc0c | 5865 | kvm_timer_init(); |
c8076604 | 5866 | |
ff9d07a0 ZY |
5867 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
5868 | ||
2acf923e DC |
5869 | if (cpu_has_xsave) |
5870 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
5871 | ||
c5cc421b | 5872 | kvm_lapic_init(); |
16e8d74d MT |
5873 | #ifdef CONFIG_X86_64 |
5874 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
5875 | #endif | |
5876 | ||
f8c16bba | 5877 | return 0; |
56c6d28a | 5878 | |
013f6a5d MT |
5879 | out_free_percpu: |
5880 | free_percpu(shared_msrs); | |
56c6d28a | 5881 | out: |
56c6d28a | 5882 | return r; |
043405e1 | 5883 | } |
8776e519 | 5884 | |
f8c16bba ZX |
5885 | void kvm_arch_exit(void) |
5886 | { | |
ff9d07a0 ZY |
5887 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
5888 | ||
888d256e JK |
5889 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
5890 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
5891 | CPUFREQ_TRANSITION_NOTIFIER); | |
8cfdc000 | 5892 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
16e8d74d MT |
5893 | #ifdef CONFIG_X86_64 |
5894 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
5895 | #endif | |
f8c16bba | 5896 | kvm_x86_ops = NULL; |
56c6d28a | 5897 | kvm_mmu_module_exit(); |
013f6a5d | 5898 | free_percpu(shared_msrs); |
56c6d28a | 5899 | } |
f8c16bba | 5900 | |
5cb56059 | 5901 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) |
8776e519 HB |
5902 | { |
5903 | ++vcpu->stat.halt_exits; | |
5904 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 5905 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
5906 | return 1; |
5907 | } else { | |
5908 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
5909 | return 0; | |
5910 | } | |
5911 | } | |
5cb56059 JS |
5912 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
5913 | ||
5914 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
5915 | { | |
5916 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
5917 | return kvm_vcpu_halt(vcpu); | |
5918 | } | |
8776e519 HB |
5919 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
5920 | ||
55cd8e5a GN |
5921 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
5922 | { | |
5923 | u64 param, ingpa, outgpa, ret; | |
5924 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
5925 | bool fast, longmode; | |
55cd8e5a GN |
5926 | |
5927 | /* | |
5928 | * hypercall generates UD from non zero cpl and real mode | |
5929 | * per HYPER-V spec | |
5930 | */ | |
3eeb3288 | 5931 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { |
55cd8e5a GN |
5932 | kvm_queue_exception(vcpu, UD_VECTOR); |
5933 | return 0; | |
5934 | } | |
5935 | ||
a449c7aa | 5936 | longmode = is_64_bit_mode(vcpu); |
55cd8e5a GN |
5937 | |
5938 | if (!longmode) { | |
ccd46936 GN |
5939 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
5940 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
5941 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
5942 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
5943 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
5944 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
5945 | } |
5946 | #ifdef CONFIG_X86_64 | |
5947 | else { | |
5948 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5949 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5950 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
5951 | } | |
5952 | #endif | |
5953 | ||
5954 | code = param & 0xffff; | |
5955 | fast = (param >> 16) & 0x1; | |
5956 | rep_cnt = (param >> 32) & 0xfff; | |
5957 | rep_idx = (param >> 48) & 0xfff; | |
5958 | ||
5959 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
5960 | ||
c25bc163 GN |
5961 | switch (code) { |
5962 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
5963 | kvm_vcpu_on_spin(vcpu); | |
5964 | break; | |
5965 | default: | |
5966 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
5967 | break; | |
5968 | } | |
55cd8e5a GN |
5969 | |
5970 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
5971 | if (longmode) { | |
5972 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
5973 | } else { | |
5974 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
5975 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
5976 | } | |
5977 | ||
5978 | return 1; | |
5979 | } | |
5980 | ||
6aef266c SV |
5981 | /* |
5982 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
5983 | * | |
5984 | * @apicid - apicid of vcpu to be kicked. | |
5985 | */ | |
5986 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
5987 | { | |
24d2166b | 5988 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 5989 | |
24d2166b R |
5990 | lapic_irq.shorthand = 0; |
5991 | lapic_irq.dest_mode = 0; | |
5992 | lapic_irq.dest_id = apicid; | |
93bbf0b8 | 5993 | lapic_irq.msi_redir_hint = false; |
6aef266c | 5994 | |
24d2166b | 5995 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 5996 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
5997 | } |
5998 | ||
8776e519 HB |
5999 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
6000 | { | |
6001 | unsigned long nr, a0, a1, a2, a3, ret; | |
a449c7aa | 6002 | int op_64_bit, r = 1; |
8776e519 | 6003 | |
5cb56059 JS |
6004 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
6005 | ||
55cd8e5a GN |
6006 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
6007 | return kvm_hv_hypercall(vcpu); | |
6008 | ||
5fdbf976 MT |
6009 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
6010 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
6011 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6012 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
6013 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 6014 | |
229456fc | 6015 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 6016 | |
a449c7aa NA |
6017 | op_64_bit = is_64_bit_mode(vcpu); |
6018 | if (!op_64_bit) { | |
8776e519 HB |
6019 | nr &= 0xFFFFFFFF; |
6020 | a0 &= 0xFFFFFFFF; | |
6021 | a1 &= 0xFFFFFFFF; | |
6022 | a2 &= 0xFFFFFFFF; | |
6023 | a3 &= 0xFFFFFFFF; | |
6024 | } | |
6025 | ||
07708c4a JK |
6026 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
6027 | ret = -KVM_EPERM; | |
6028 | goto out; | |
6029 | } | |
6030 | ||
8776e519 | 6031 | switch (nr) { |
b93463aa AK |
6032 | case KVM_HC_VAPIC_POLL_IRQ: |
6033 | ret = 0; | |
6034 | break; | |
6aef266c SV |
6035 | case KVM_HC_KICK_CPU: |
6036 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); | |
6037 | ret = 0; | |
6038 | break; | |
8776e519 HB |
6039 | default: |
6040 | ret = -KVM_ENOSYS; | |
6041 | break; | |
6042 | } | |
07708c4a | 6043 | out: |
a449c7aa NA |
6044 | if (!op_64_bit) |
6045 | ret = (u32)ret; | |
5fdbf976 | 6046 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 6047 | ++vcpu->stat.hypercalls; |
2f333bcb | 6048 | return r; |
8776e519 HB |
6049 | } |
6050 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
6051 | ||
b6785def | 6052 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 6053 | { |
d6aa1000 | 6054 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 6055 | char instruction[3]; |
5fdbf976 | 6056 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 6057 | |
8776e519 | 6058 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 6059 | |
9d74191a | 6060 | return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); |
8776e519 HB |
6061 | } |
6062 | ||
b6c7a5dc HB |
6063 | /* |
6064 | * Check if userspace requested an interrupt window, and that the | |
6065 | * interrupt window is open. | |
6066 | * | |
6067 | * No need to exit to userspace if we already have an interrupt queued. | |
6068 | */ | |
851ba692 | 6069 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 6070 | { |
8061823a | 6071 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 6072 | vcpu->run->request_interrupt_window && |
5df56646 | 6073 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
6074 | } |
6075 | ||
851ba692 | 6076 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 6077 | { |
851ba692 AK |
6078 | struct kvm_run *kvm_run = vcpu->run; |
6079 | ||
91586a3b | 6080 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
f077825a | 6081 | kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; |
2d3ad1f4 | 6082 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 6083 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 6084 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 6085 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 6086 | else |
b6c7a5dc | 6087 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
6088 | kvm_arch_interrupt_allowed(vcpu) && |
6089 | !kvm_cpu_has_interrupt(vcpu) && | |
6090 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
6091 | } |
6092 | ||
95ba8273 GN |
6093 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
6094 | { | |
6095 | int max_irr, tpr; | |
6096 | ||
6097 | if (!kvm_x86_ops->update_cr8_intercept) | |
6098 | return; | |
6099 | ||
88c808fd AK |
6100 | if (!vcpu->arch.apic) |
6101 | return; | |
6102 | ||
8db3baa2 GN |
6103 | if (!vcpu->arch.apic->vapic_addr) |
6104 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
6105 | else | |
6106 | max_irr = -1; | |
95ba8273 GN |
6107 | |
6108 | if (max_irr != -1) | |
6109 | max_irr >>= 4; | |
6110 | ||
6111 | tpr = kvm_lapic_get_cr8(vcpu); | |
6112 | ||
6113 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
6114 | } | |
6115 | ||
b6b8a145 | 6116 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) |
95ba8273 | 6117 | { |
b6b8a145 JK |
6118 | int r; |
6119 | ||
95ba8273 | 6120 | /* try to reinject previous events if any */ |
b59bb7bd | 6121 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
6122 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
6123 | vcpu->arch.exception.has_error_code, | |
6124 | vcpu->arch.exception.error_code); | |
d6e8c854 NA |
6125 | |
6126 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) | |
6127 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
6128 | X86_EFLAGS_RF); | |
6129 | ||
6bdf0662 NA |
6130 | if (vcpu->arch.exception.nr == DB_VECTOR && |
6131 | (vcpu->arch.dr7 & DR7_GD)) { | |
6132 | vcpu->arch.dr7 &= ~DR7_GD; | |
6133 | kvm_update_dr7(vcpu); | |
6134 | } | |
6135 | ||
b59bb7bd GN |
6136 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
6137 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
6138 | vcpu->arch.exception.error_code, |
6139 | vcpu->arch.exception.reinject); | |
b6b8a145 | 6140 | return 0; |
b59bb7bd GN |
6141 | } |
6142 | ||
95ba8273 GN |
6143 | if (vcpu->arch.nmi_injected) { |
6144 | kvm_x86_ops->set_nmi(vcpu); | |
b6b8a145 | 6145 | return 0; |
95ba8273 GN |
6146 | } |
6147 | ||
6148 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 6149 | kvm_x86_ops->set_irq(vcpu); |
b6b8a145 JK |
6150 | return 0; |
6151 | } | |
6152 | ||
6153 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6154 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6155 | if (r != 0) | |
6156 | return r; | |
95ba8273 GN |
6157 | } |
6158 | ||
6159 | /* try to inject new event if pending */ | |
6160 | if (vcpu->arch.nmi_pending) { | |
6161 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
7460fb4a | 6162 | --vcpu->arch.nmi_pending; |
95ba8273 GN |
6163 | vcpu->arch.nmi_injected = true; |
6164 | kvm_x86_ops->set_nmi(vcpu); | |
6165 | } | |
c7c9c56c | 6166 | } else if (kvm_cpu_has_injectable_intr(vcpu)) { |
9242b5b6 BD |
6167 | /* |
6168 | * Because interrupts can be injected asynchronously, we are | |
6169 | * calling check_nested_events again here to avoid a race condition. | |
6170 | * See https://lkml.org/lkml/2014/7/2/60 for discussion about this | |
6171 | * proposal and current concerns. Perhaps we should be setting | |
6172 | * KVM_REQ_EVENT only on certain events and not unconditionally? | |
6173 | */ | |
6174 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6175 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6176 | if (r != 0) | |
6177 | return r; | |
6178 | } | |
95ba8273 | 6179 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { |
66fd3f7f GN |
6180 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
6181 | false); | |
6182 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
6183 | } |
6184 | } | |
b6b8a145 | 6185 | return 0; |
95ba8273 GN |
6186 | } |
6187 | ||
7460fb4a AK |
6188 | static void process_nmi(struct kvm_vcpu *vcpu) |
6189 | { | |
6190 | unsigned limit = 2; | |
6191 | ||
6192 | /* | |
6193 | * x86 is limited to one NMI running, and one NMI pending after it. | |
6194 | * If an NMI is already in progress, limit further NMIs to just one. | |
6195 | * Otherwise, allow two (and we'll inject the first one immediately). | |
6196 | */ | |
6197 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
6198 | limit = 1; | |
6199 | ||
6200 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
6201 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
6202 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6203 | } | |
6204 | ||
660a5d51 PB |
6205 | #define put_smstate(type, buf, offset, val) \ |
6206 | *(type *)((buf) + (offset) - 0x7e00) = val | |
6207 | ||
6208 | static u32 process_smi_get_segment_flags(struct kvm_segment *seg) | |
6209 | { | |
6210 | u32 flags = 0; | |
6211 | flags |= seg->g << 23; | |
6212 | flags |= seg->db << 22; | |
6213 | flags |= seg->l << 21; | |
6214 | flags |= seg->avl << 20; | |
6215 | flags |= seg->present << 15; | |
6216 | flags |= seg->dpl << 13; | |
6217 | flags |= seg->s << 12; | |
6218 | flags |= seg->type << 8; | |
6219 | return flags; | |
6220 | } | |
6221 | ||
6222 | static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) | |
6223 | { | |
6224 | struct kvm_segment seg; | |
6225 | int offset; | |
6226 | ||
6227 | kvm_get_segment(vcpu, &seg, n); | |
6228 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
6229 | ||
6230 | if (n < 3) | |
6231 | offset = 0x7f84 + n * 12; | |
6232 | else | |
6233 | offset = 0x7f2c + (n - 3) * 12; | |
6234 | ||
6235 | put_smstate(u32, buf, offset + 8, seg.base); | |
6236 | put_smstate(u32, buf, offset + 4, seg.limit); | |
6237 | put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg)); | |
6238 | } | |
6239 | ||
6240 | static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) | |
6241 | { | |
6242 | struct kvm_segment seg; | |
6243 | int offset; | |
6244 | u16 flags; | |
6245 | ||
6246 | kvm_get_segment(vcpu, &seg, n); | |
6247 | offset = 0x7e00 + n * 16; | |
6248 | ||
6249 | flags = process_smi_get_segment_flags(&seg) >> 8; | |
6250 | put_smstate(u16, buf, offset, seg.selector); | |
6251 | put_smstate(u16, buf, offset + 2, flags); | |
6252 | put_smstate(u32, buf, offset + 4, seg.limit); | |
6253 | put_smstate(u64, buf, offset + 8, seg.base); | |
6254 | } | |
6255 | ||
6256 | static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf) | |
6257 | { | |
6258 | struct desc_ptr dt; | |
6259 | struct kvm_segment seg; | |
6260 | unsigned long val; | |
6261 | int i; | |
6262 | ||
6263 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
6264 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
6265 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
6266 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
6267 | ||
6268 | for (i = 0; i < 8; i++) | |
6269 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); | |
6270 | ||
6271 | kvm_get_dr(vcpu, 6, &val); | |
6272 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
6273 | kvm_get_dr(vcpu, 7, &val); | |
6274 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
6275 | ||
6276 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
6277 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
6278 | put_smstate(u32, buf, 0x7f64, seg.base); | |
6279 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
6280 | put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg)); | |
6281 | ||
6282 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
6283 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
6284 | put_smstate(u32, buf, 0x7f80, seg.base); | |
6285 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
6286 | put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg)); | |
6287 | ||
6288 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
6289 | put_smstate(u32, buf, 0x7f74, dt.address); | |
6290 | put_smstate(u32, buf, 0x7f70, dt.size); | |
6291 | ||
6292 | kvm_x86_ops->get_idt(vcpu, &dt); | |
6293 | put_smstate(u32, buf, 0x7f58, dt.address); | |
6294 | put_smstate(u32, buf, 0x7f54, dt.size); | |
6295 | ||
6296 | for (i = 0; i < 6; i++) | |
6297 | process_smi_save_seg_32(vcpu, buf, i); | |
6298 | ||
6299 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
6300 | ||
6301 | /* revision id */ | |
6302 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
6303 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
6304 | } | |
6305 | ||
6306 | static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf) | |
6307 | { | |
6308 | #ifdef CONFIG_X86_64 | |
6309 | struct desc_ptr dt; | |
6310 | struct kvm_segment seg; | |
6311 | unsigned long val; | |
6312 | int i; | |
6313 | ||
6314 | for (i = 0; i < 16; i++) | |
6315 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); | |
6316 | ||
6317 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
6318 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
6319 | ||
6320 | kvm_get_dr(vcpu, 6, &val); | |
6321 | put_smstate(u64, buf, 0x7f68, val); | |
6322 | kvm_get_dr(vcpu, 7, &val); | |
6323 | put_smstate(u64, buf, 0x7f60, val); | |
6324 | ||
6325 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
6326 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
6327 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
6328 | ||
6329 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
6330 | ||
6331 | /* revision id */ | |
6332 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
6333 | ||
6334 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
6335 | ||
6336 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
6337 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
6338 | put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8); | |
6339 | put_smstate(u32, buf, 0x7e94, seg.limit); | |
6340 | put_smstate(u64, buf, 0x7e98, seg.base); | |
6341 | ||
6342 | kvm_x86_ops->get_idt(vcpu, &dt); | |
6343 | put_smstate(u32, buf, 0x7e84, dt.size); | |
6344 | put_smstate(u64, buf, 0x7e88, dt.address); | |
6345 | ||
6346 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
6347 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
6348 | put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8); | |
6349 | put_smstate(u32, buf, 0x7e74, seg.limit); | |
6350 | put_smstate(u64, buf, 0x7e78, seg.base); | |
6351 | ||
6352 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
6353 | put_smstate(u32, buf, 0x7e64, dt.size); | |
6354 | put_smstate(u64, buf, 0x7e68, dt.address); | |
6355 | ||
6356 | for (i = 0; i < 6; i++) | |
6357 | process_smi_save_seg_64(vcpu, buf, i); | |
6358 | #else | |
6359 | WARN_ON_ONCE(1); | |
6360 | #endif | |
6361 | } | |
6362 | ||
64d60670 PB |
6363 | static void process_smi(struct kvm_vcpu *vcpu) |
6364 | { | |
660a5d51 PB |
6365 | struct kvm_segment cs, ds; |
6366 | char buf[512]; | |
6367 | u32 cr0; | |
6368 | ||
64d60670 PB |
6369 | if (is_smm(vcpu)) { |
6370 | vcpu->arch.smi_pending = true; | |
6371 | return; | |
6372 | } | |
6373 | ||
660a5d51 PB |
6374 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); |
6375 | vcpu->arch.hflags |= HF_SMM_MASK; | |
6376 | memset(buf, 0, 512); | |
6377 | if (guest_cpuid_has_longmode(vcpu)) | |
6378 | process_smi_save_state_64(vcpu, buf); | |
6379 | else | |
6380 | process_smi_save_state_32(vcpu, buf); | |
6381 | ||
54bf36aa | 6382 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 PB |
6383 | |
6384 | if (kvm_x86_ops->get_nmi_mask(vcpu)) | |
6385 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
6386 | else | |
6387 | kvm_x86_ops->set_nmi_mask(vcpu, true); | |
6388 | ||
6389 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
6390 | kvm_rip_write(vcpu, 0x8000); | |
6391 | ||
6392 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
6393 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
6394 | vcpu->arch.cr0 = cr0; | |
6395 | ||
6396 | kvm_x86_ops->set_cr4(vcpu, 0); | |
6397 | ||
6398 | __kvm_set_dr(vcpu, 7, DR7_FIXED_1); | |
6399 | ||
6400 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
6401 | cs.base = vcpu->arch.smbase; | |
6402 | ||
6403 | ds.selector = 0; | |
6404 | ds.base = 0; | |
6405 | ||
6406 | cs.limit = ds.limit = 0xffffffff; | |
6407 | cs.type = ds.type = 0x3; | |
6408 | cs.dpl = ds.dpl = 0; | |
6409 | cs.db = ds.db = 0; | |
6410 | cs.s = ds.s = 1; | |
6411 | cs.l = ds.l = 0; | |
6412 | cs.g = ds.g = 1; | |
6413 | cs.avl = ds.avl = 0; | |
6414 | cs.present = ds.present = 1; | |
6415 | cs.unusable = ds.unusable = 0; | |
6416 | cs.padding = ds.padding = 0; | |
6417 | ||
6418 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
6419 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
6420 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
6421 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
6422 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
6423 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
6424 | ||
6425 | if (guest_cpuid_has_longmode(vcpu)) | |
6426 | kvm_x86_ops->set_efer(vcpu, 0); | |
6427 | ||
6428 | kvm_update_cpuid(vcpu); | |
6429 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
6430 | } |
6431 | ||
3d81bc7e | 6432 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c YZ |
6433 | { |
6434 | u64 eoi_exit_bitmap[4]; | |
cf9e65b7 | 6435 | u32 tmr[8]; |
c7c9c56c | 6436 | |
3d81bc7e YZ |
6437 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
6438 | return; | |
c7c9c56c YZ |
6439 | |
6440 | memset(eoi_exit_bitmap, 0, 32); | |
cf9e65b7 | 6441 | memset(tmr, 0, 32); |
c7c9c56c | 6442 | |
cf9e65b7 | 6443 | kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr); |
c7c9c56c | 6444 | kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); |
cf9e65b7 | 6445 | kvm_apic_update_tmr(vcpu, tmr); |
c7c9c56c YZ |
6446 | } |
6447 | ||
a70656b6 RK |
6448 | static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) |
6449 | { | |
6450 | ++vcpu->stat.tlb_flush; | |
6451 | kvm_x86_ops->tlb_flush(vcpu); | |
6452 | } | |
6453 | ||
4256f43f TC |
6454 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
6455 | { | |
c24ae0dc TC |
6456 | struct page *page = NULL; |
6457 | ||
f439ed27 PB |
6458 | if (!irqchip_in_kernel(vcpu->kvm)) |
6459 | return; | |
6460 | ||
4256f43f TC |
6461 | if (!kvm_x86_ops->set_apic_access_page_addr) |
6462 | return; | |
6463 | ||
c24ae0dc | 6464 | page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
e8fd5e9e AA |
6465 | if (is_error_page(page)) |
6466 | return; | |
c24ae0dc TC |
6467 | kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); |
6468 | ||
6469 | /* | |
6470 | * Do not pin apic access page in memory, the MMU notifier | |
6471 | * will call us again if it is migrated or swapped out. | |
6472 | */ | |
6473 | put_page(page); | |
4256f43f TC |
6474 | } |
6475 | EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); | |
6476 | ||
fe71557a TC |
6477 | void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, |
6478 | unsigned long address) | |
6479 | { | |
c24ae0dc TC |
6480 | /* |
6481 | * The physical address of apic access page is stored in the VMCS. | |
6482 | * Update it when it becomes invalid. | |
6483 | */ | |
6484 | if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) | |
6485 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
fe71557a TC |
6486 | } |
6487 | ||
9357d939 | 6488 | /* |
362c698f | 6489 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
6490 | * exiting to the userspace. Otherwise, the value will be returned to the |
6491 | * userspace. | |
6492 | */ | |
851ba692 | 6493 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
6494 | { |
6495 | int r; | |
6a8b1d13 | 6496 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 6497 | vcpu->run->request_interrupt_window; |
730dca42 | 6498 | bool req_immediate_exit = false; |
b6c7a5dc | 6499 | |
3e007509 | 6500 | if (vcpu->requests) { |
a8eeb04a | 6501 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 6502 | kvm_mmu_unload(vcpu); |
a8eeb04a | 6503 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 6504 | __kvm_migrate_timers(vcpu); |
d828199e MT |
6505 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
6506 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
6507 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
6508 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
6509 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
6510 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
6511 | if (unlikely(r)) |
6512 | goto out; | |
6513 | } | |
a8eeb04a | 6514 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 6515 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 6516 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
a70656b6 | 6517 | kvm_vcpu_flush_tlb(vcpu); |
a8eeb04a | 6518 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 6519 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
6520 | r = 0; |
6521 | goto out; | |
6522 | } | |
a8eeb04a | 6523 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 6524 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
6525 | r = 0; |
6526 | goto out; | |
6527 | } | |
a8eeb04a | 6528 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
6529 | vcpu->fpu_active = 0; |
6530 | kvm_x86_ops->fpu_deactivate(vcpu); | |
6531 | } | |
af585b92 GN |
6532 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
6533 | /* Page is swapped out. Do synthetic halt */ | |
6534 | vcpu->arch.apf.halted = true; | |
6535 | r = 1; | |
6536 | goto out; | |
6537 | } | |
c9aaa895 GC |
6538 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
6539 | record_steal_time(vcpu); | |
64d60670 PB |
6540 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
6541 | process_smi(vcpu); | |
7460fb4a AK |
6542 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
6543 | process_nmi(vcpu); | |
f5132b01 GN |
6544 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
6545 | kvm_handle_pmu_event(vcpu); | |
6546 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) | |
6547 | kvm_deliver_pmi(vcpu); | |
3d81bc7e YZ |
6548 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
6549 | vcpu_scan_ioapic(vcpu); | |
4256f43f TC |
6550 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
6551 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2f52d58c | 6552 | } |
b93463aa | 6553 | |
b463a6f7 | 6554 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
66450a21 JK |
6555 | kvm_apic_accept_events(vcpu); |
6556 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
6557 | r = 1; | |
6558 | goto out; | |
6559 | } | |
6560 | ||
b6b8a145 JK |
6561 | if (inject_pending_event(vcpu, req_int_win) != 0) |
6562 | req_immediate_exit = true; | |
b463a6f7 | 6563 | /* enable NMI/IRQ window open exits if needed */ |
b6b8a145 | 6564 | else if (vcpu->arch.nmi_pending) |
c9a7953f | 6565 | kvm_x86_ops->enable_nmi_window(vcpu); |
c7c9c56c | 6566 | else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) |
c9a7953f | 6567 | kvm_x86_ops->enable_irq_window(vcpu); |
b463a6f7 AK |
6568 | |
6569 | if (kvm_lapic_enabled(vcpu)) { | |
c7c9c56c YZ |
6570 | /* |
6571 | * Update architecture specific hints for APIC | |
6572 | * virtual interrupt delivery. | |
6573 | */ | |
6574 | if (kvm_x86_ops->hwapic_irr_update) | |
6575 | kvm_x86_ops->hwapic_irr_update(vcpu, | |
6576 | kvm_lapic_find_highest_irr(vcpu)); | |
b463a6f7 AK |
6577 | update_cr8_intercept(vcpu); |
6578 | kvm_lapic_sync_to_vapic(vcpu); | |
6579 | } | |
6580 | } | |
6581 | ||
d8368af8 AK |
6582 | r = kvm_mmu_reload(vcpu); |
6583 | if (unlikely(r)) { | |
d905c069 | 6584 | goto cancel_injection; |
d8368af8 AK |
6585 | } |
6586 | ||
b6c7a5dc HB |
6587 | preempt_disable(); |
6588 | ||
6589 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
6590 | if (vcpu->fpu_active) |
6591 | kvm_load_guest_fpu(vcpu); | |
2acf923e | 6592 | kvm_load_guest_xcr0(vcpu); |
b6c7a5dc | 6593 | |
6b7e2d09 XG |
6594 | vcpu->mode = IN_GUEST_MODE; |
6595 | ||
01b71917 MT |
6596 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
6597 | ||
6b7e2d09 XG |
6598 | /* We should set ->mode before check ->requests, |
6599 | * see the comment in make_all_cpus_request. | |
6600 | */ | |
01b71917 | 6601 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 6602 | |
d94e1dc9 | 6603 | local_irq_disable(); |
32f88400 | 6604 | |
6b7e2d09 | 6605 | if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests |
d94e1dc9 | 6606 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 6607 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 6608 | smp_wmb(); |
6c142801 AK |
6609 | local_irq_enable(); |
6610 | preempt_enable(); | |
01b71917 | 6611 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 6612 | r = 1; |
d905c069 | 6613 | goto cancel_injection; |
6c142801 AK |
6614 | } |
6615 | ||
d6185f20 NHE |
6616 | if (req_immediate_exit) |
6617 | smp_send_reschedule(vcpu->cpu); | |
6618 | ||
ccf73aaf | 6619 | __kvm_guest_enter(); |
b6c7a5dc | 6620 | |
42dbaa5a | 6621 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
6622 | set_debugreg(0, 7); |
6623 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
6624 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
6625 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
6626 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 6627 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 6628 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 6629 | } |
b6c7a5dc | 6630 | |
229456fc | 6631 | trace_kvm_entry(vcpu->vcpu_id); |
d0659d94 | 6632 | wait_lapic_expire(vcpu); |
851ba692 | 6633 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 6634 | |
c77fb5fe PB |
6635 | /* |
6636 | * Do this here before restoring debug registers on the host. And | |
6637 | * since we do this before handling the vmexit, a DR access vmexit | |
6638 | * can (a) read the correct value of the debug registers, (b) set | |
6639 | * KVM_DEBUGREG_WONT_EXIT again. | |
6640 | */ | |
6641 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
6642 | int i; | |
6643 | ||
6644 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); | |
6645 | kvm_x86_ops->sync_dirty_debug_regs(vcpu); | |
6646 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
6647 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
6648 | } | |
6649 | ||
24f1e32c FW |
6650 | /* |
6651 | * If the guest has used debug registers, at least dr7 | |
6652 | * will be disabled while returning to the host. | |
6653 | * If we don't have active breakpoints in the host, we don't | |
6654 | * care about the messed up debug address registers. But if | |
6655 | * we have some of them active, restore the old state. | |
6656 | */ | |
59d8eb53 | 6657 | if (hw_breakpoint_active()) |
24f1e32c | 6658 | hw_breakpoint_restore(); |
42dbaa5a | 6659 | |
886b470c MT |
6660 | vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, |
6661 | native_read_tsc()); | |
1d5f066e | 6662 | |
6b7e2d09 | 6663 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 6664 | smp_wmb(); |
a547c6db YZ |
6665 | |
6666 | /* Interrupt is enabled by handle_external_intr() */ | |
6667 | kvm_x86_ops->handle_external_intr(vcpu); | |
b6c7a5dc HB |
6668 | |
6669 | ++vcpu->stat.exits; | |
6670 | ||
6671 | /* | |
6672 | * We must have an instruction between local_irq_enable() and | |
6673 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
6674 | * the interrupt shadow. The stat.exits increment will do nicely. | |
6675 | * But we need to prevent reordering, hence this barrier(): | |
6676 | */ | |
6677 | barrier(); | |
6678 | ||
6679 | kvm_guest_exit(); | |
6680 | ||
6681 | preempt_enable(); | |
6682 | ||
f656ce01 | 6683 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 6684 | |
b6c7a5dc HB |
6685 | /* |
6686 | * Profile KVM exit RIPs: | |
6687 | */ | |
6688 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
6689 | unsigned long rip = kvm_rip_read(vcpu); |
6690 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
6691 | } |
6692 | ||
cc578287 ZA |
6693 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
6694 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 6695 | |
5cfb1d5a MT |
6696 | if (vcpu->arch.apic_attention) |
6697 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 6698 | |
851ba692 | 6699 | r = kvm_x86_ops->handle_exit(vcpu); |
d905c069 MT |
6700 | return r; |
6701 | ||
6702 | cancel_injection: | |
6703 | kvm_x86_ops->cancel_injection(vcpu); | |
ae7a2a3f MT |
6704 | if (unlikely(vcpu->arch.apic_attention)) |
6705 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
6706 | out: |
6707 | return r; | |
6708 | } | |
b6c7a5dc | 6709 | |
362c698f PB |
6710 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
6711 | { | |
9c8fd1ba PB |
6712 | if (!kvm_arch_vcpu_runnable(vcpu)) { |
6713 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); | |
6714 | kvm_vcpu_block(vcpu); | |
6715 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
6716 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) | |
6717 | return 1; | |
6718 | } | |
362c698f PB |
6719 | |
6720 | kvm_apic_accept_events(vcpu); | |
6721 | switch(vcpu->arch.mp_state) { | |
6722 | case KVM_MP_STATE_HALTED: | |
6723 | vcpu->arch.pv.pv_unhalted = false; | |
6724 | vcpu->arch.mp_state = | |
6725 | KVM_MP_STATE_RUNNABLE; | |
6726 | case KVM_MP_STATE_RUNNABLE: | |
6727 | vcpu->arch.apf.halted = false; | |
6728 | break; | |
6729 | case KVM_MP_STATE_INIT_RECEIVED: | |
6730 | break; | |
6731 | default: | |
6732 | return -EINTR; | |
6733 | break; | |
6734 | } | |
6735 | return 1; | |
6736 | } | |
09cec754 | 6737 | |
362c698f | 6738 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
6739 | { |
6740 | int r; | |
f656ce01 | 6741 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 6742 | |
f656ce01 | 6743 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 6744 | |
362c698f | 6745 | for (;;) { |
af585b92 GN |
6746 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
6747 | !vcpu->arch.apf.halted) | |
851ba692 | 6748 | r = vcpu_enter_guest(vcpu); |
362c698f PB |
6749 | else |
6750 | r = vcpu_block(kvm, vcpu); | |
09cec754 GN |
6751 | if (r <= 0) |
6752 | break; | |
6753 | ||
6754 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
6755 | if (kvm_cpu_has_pending_timer(vcpu)) | |
6756 | kvm_inject_pending_timer_irqs(vcpu); | |
6757 | ||
851ba692 | 6758 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 6759 | r = -EINTR; |
851ba692 | 6760 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 | 6761 | ++vcpu->stat.request_irq_exits; |
362c698f | 6762 | break; |
09cec754 | 6763 | } |
af585b92 GN |
6764 | |
6765 | kvm_check_async_pf_completion(vcpu); | |
6766 | ||
09cec754 GN |
6767 | if (signal_pending(current)) { |
6768 | r = -EINTR; | |
851ba692 | 6769 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 | 6770 | ++vcpu->stat.signal_exits; |
362c698f | 6771 | break; |
09cec754 GN |
6772 | } |
6773 | if (need_resched()) { | |
f656ce01 | 6774 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
c08ac06a | 6775 | cond_resched(); |
f656ce01 | 6776 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 6777 | } |
b6c7a5dc HB |
6778 | } |
6779 | ||
f656ce01 | 6780 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
6781 | |
6782 | return r; | |
6783 | } | |
6784 | ||
716d51ab GN |
6785 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
6786 | { | |
6787 | int r; | |
6788 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
6789 | r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); | |
6790 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
6791 | if (r != EMULATE_DONE) | |
6792 | return 0; | |
6793 | return 1; | |
6794 | } | |
6795 | ||
6796 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
6797 | { | |
6798 | BUG_ON(!vcpu->arch.pio.count); | |
6799 | ||
6800 | return complete_emulated_io(vcpu); | |
6801 | } | |
6802 | ||
f78146b0 AK |
6803 | /* |
6804 | * Implements the following, as a state machine: | |
6805 | * | |
6806 | * read: | |
6807 | * for each fragment | |
87da7e66 XG |
6808 | * for each mmio piece in the fragment |
6809 | * write gpa, len | |
6810 | * exit | |
6811 | * copy data | |
f78146b0 AK |
6812 | * execute insn |
6813 | * | |
6814 | * write: | |
6815 | * for each fragment | |
87da7e66 XG |
6816 | * for each mmio piece in the fragment |
6817 | * write gpa, len | |
6818 | * copy data | |
6819 | * exit | |
f78146b0 | 6820 | */ |
716d51ab | 6821 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
6822 | { |
6823 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 6824 | struct kvm_mmio_fragment *frag; |
87da7e66 | 6825 | unsigned len; |
5287f194 | 6826 | |
716d51ab | 6827 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 6828 | |
716d51ab | 6829 | /* Complete previous fragment */ |
87da7e66 XG |
6830 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
6831 | len = min(8u, frag->len); | |
716d51ab | 6832 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
6833 | memcpy(frag->data, run->mmio.data, len); |
6834 | ||
6835 | if (frag->len <= 8) { | |
6836 | /* Switch to the next fragment. */ | |
6837 | frag++; | |
6838 | vcpu->mmio_cur_fragment++; | |
6839 | } else { | |
6840 | /* Go forward to the next mmio piece. */ | |
6841 | frag->data += len; | |
6842 | frag->gpa += len; | |
6843 | frag->len -= len; | |
6844 | } | |
6845 | ||
a08d3b3b | 6846 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 6847 | vcpu->mmio_needed = 0; |
0912c977 PB |
6848 | |
6849 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 6850 | if (vcpu->mmio_is_write) |
716d51ab GN |
6851 | return 1; |
6852 | vcpu->mmio_read_completed = 1; | |
6853 | return complete_emulated_io(vcpu); | |
6854 | } | |
87da7e66 | 6855 | |
716d51ab GN |
6856 | run->exit_reason = KVM_EXIT_MMIO; |
6857 | run->mmio.phys_addr = frag->gpa; | |
6858 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
6859 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
6860 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
6861 | run->mmio.is_write = vcpu->mmio_is_write; |
6862 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
6863 | return 0; | |
5287f194 AK |
6864 | } |
6865 | ||
716d51ab | 6866 | |
b6c7a5dc HB |
6867 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6868 | { | |
6869 | int r; | |
6870 | sigset_t sigsaved; | |
6871 | ||
e5c30142 AK |
6872 | if (!tsk_used_math(current) && init_fpu(current)) |
6873 | return -ENOMEM; | |
6874 | ||
ac9f6dc0 AK |
6875 | if (vcpu->sigset_active) |
6876 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
6877 | ||
a4535290 | 6878 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 6879 | kvm_vcpu_block(vcpu); |
66450a21 | 6880 | kvm_apic_accept_events(vcpu); |
d7690175 | 6881 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
6882 | r = -EAGAIN; |
6883 | goto out; | |
b6c7a5dc HB |
6884 | } |
6885 | ||
b6c7a5dc | 6886 | /* re-sync apic's tpr */ |
eea1cff9 AP |
6887 | if (!irqchip_in_kernel(vcpu->kvm)) { |
6888 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { | |
6889 | r = -EINVAL; | |
6890 | goto out; | |
6891 | } | |
6892 | } | |
b6c7a5dc | 6893 | |
716d51ab GN |
6894 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
6895 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
6896 | vcpu->arch.complete_userspace_io = NULL; | |
6897 | r = cui(vcpu); | |
6898 | if (r <= 0) | |
6899 | goto out; | |
6900 | } else | |
6901 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 6902 | |
362c698f | 6903 | r = vcpu_run(vcpu); |
b6c7a5dc HB |
6904 | |
6905 | out: | |
f1d86e46 | 6906 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
6907 | if (vcpu->sigset_active) |
6908 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
6909 | ||
b6c7a5dc HB |
6910 | return r; |
6911 | } | |
6912 | ||
6913 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6914 | { | |
7ae441ea GN |
6915 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
6916 | /* | |
6917 | * We are here if userspace calls get_regs() in the middle of | |
6918 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 6919 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
6920 | * that usually, but some bad designed PV devices (vmware |
6921 | * backdoor interface) need this to work | |
6922 | */ | |
dd856efa | 6923 | emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); |
7ae441ea GN |
6924 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
6925 | } | |
5fdbf976 MT |
6926 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
6927 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
6928 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6929 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
6930 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
6931 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
6932 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
6933 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 6934 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6935 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
6936 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
6937 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
6938 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
6939 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
6940 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
6941 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
6942 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
6943 | #endif |
6944 | ||
5fdbf976 | 6945 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 6946 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 6947 | |
b6c7a5dc HB |
6948 | return 0; |
6949 | } | |
6950 | ||
6951 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6952 | { | |
7ae441ea GN |
6953 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
6954 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
6955 | ||
5fdbf976 MT |
6956 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
6957 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
6958 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
6959 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
6960 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
6961 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
6962 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
6963 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 6964 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6965 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
6966 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
6967 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
6968 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
6969 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
6970 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
6971 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
6972 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
6973 | #endif |
6974 | ||
5fdbf976 | 6975 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 6976 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 6977 | |
b4f14abd JK |
6978 | vcpu->arch.exception.pending = false; |
6979 | ||
3842d135 AK |
6980 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6981 | ||
b6c7a5dc HB |
6982 | return 0; |
6983 | } | |
6984 | ||
b6c7a5dc HB |
6985 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
6986 | { | |
6987 | struct kvm_segment cs; | |
6988 | ||
3e6e0aab | 6989 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
6990 | *db = cs.db; |
6991 | *l = cs.l; | |
6992 | } | |
6993 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
6994 | ||
6995 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
6996 | struct kvm_sregs *sregs) | |
6997 | { | |
89a27f4d | 6998 | struct desc_ptr dt; |
b6c7a5dc | 6999 | |
3e6e0aab GT |
7000 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
7001 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
7002 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
7003 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
7004 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
7005 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 7006 | |
3e6e0aab GT |
7007 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
7008 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
7009 | |
7010 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
7011 | sregs->idt.limit = dt.size; |
7012 | sregs->idt.base = dt.address; | |
b6c7a5dc | 7013 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
7014 | sregs->gdt.limit = dt.size; |
7015 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 7016 | |
4d4ec087 | 7017 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 7018 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 7019 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 7020 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 7021 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 7022 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
7023 | sregs->apic_base = kvm_get_apic_base(vcpu); |
7024 | ||
923c61bb | 7025 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 7026 | |
36752c9b | 7027 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
7028 | set_bit(vcpu->arch.interrupt.nr, |
7029 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 7030 | |
b6c7a5dc HB |
7031 | return 0; |
7032 | } | |
7033 | ||
62d9f0db MT |
7034 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
7035 | struct kvm_mp_state *mp_state) | |
7036 | { | |
66450a21 | 7037 | kvm_apic_accept_events(vcpu); |
6aef266c SV |
7038 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && |
7039 | vcpu->arch.pv.pv_unhalted) | |
7040 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; | |
7041 | else | |
7042 | mp_state->mp_state = vcpu->arch.mp_state; | |
7043 | ||
62d9f0db MT |
7044 | return 0; |
7045 | } | |
7046 | ||
7047 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
7048 | struct kvm_mp_state *mp_state) | |
7049 | { | |
66450a21 JK |
7050 | if (!kvm_vcpu_has_lapic(vcpu) && |
7051 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) | |
7052 | return -EINVAL; | |
7053 | ||
7054 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { | |
7055 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
7056 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
7057 | } else | |
7058 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 7059 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
62d9f0db MT |
7060 | return 0; |
7061 | } | |
7062 | ||
7f3d35fd KW |
7063 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
7064 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 7065 | { |
9d74191a | 7066 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d | 7067 | int ret; |
e01c2426 | 7068 | |
8ec4722d | 7069 | init_emulate_ctxt(vcpu); |
c697518a | 7070 | |
7f3d35fd | 7071 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 7072 | has_error_code, error_code); |
c697518a | 7073 | |
c697518a | 7074 | if (ret) |
19d04437 | 7075 | return EMULATE_FAIL; |
37817f29 | 7076 | |
9d74191a TY |
7077 | kvm_rip_write(vcpu, ctxt->eip); |
7078 | kvm_set_rflags(vcpu, ctxt->eflags); | |
3842d135 | 7079 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 7080 | return EMULATE_DONE; |
37817f29 IE |
7081 | } |
7082 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
7083 | ||
b6c7a5dc HB |
7084 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
7085 | struct kvm_sregs *sregs) | |
7086 | { | |
58cb628d | 7087 | struct msr_data apic_base_msr; |
b6c7a5dc | 7088 | int mmu_reset_needed = 0; |
63f42e02 | 7089 | int pending_vec, max_bits, idx; |
89a27f4d | 7090 | struct desc_ptr dt; |
b6c7a5dc | 7091 | |
6d1068b3 PM |
7092 | if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) |
7093 | return -EINVAL; | |
7094 | ||
89a27f4d GN |
7095 | dt.size = sregs->idt.limit; |
7096 | dt.address = sregs->idt.base; | |
b6c7a5dc | 7097 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
7098 | dt.size = sregs->gdt.limit; |
7099 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
7100 | kvm_x86_ops->set_gdt(vcpu, &dt); |
7101 | ||
ad312c7c | 7102 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 7103 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 7104 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 7105 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 7106 | |
2d3ad1f4 | 7107 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 7108 | |
f6801dff | 7109 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 7110 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
58cb628d JK |
7111 | apic_base_msr.data = sregs->apic_base; |
7112 | apic_base_msr.host_initiated = true; | |
7113 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
b6c7a5dc | 7114 | |
4d4ec087 | 7115 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 7116 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 7117 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 7118 | |
fc78f519 | 7119 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 7120 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
3ea3aa8c | 7121 | if (sregs->cr4 & X86_CR4_OSXSAVE) |
00b27a3e | 7122 | kvm_update_cpuid(vcpu); |
63f42e02 XG |
7123 | |
7124 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
7c93be44 | 7125 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
9f8fe504 | 7126 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
7127 | mmu_reset_needed = 1; |
7128 | } | |
63f42e02 | 7129 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
7130 | |
7131 | if (mmu_reset_needed) | |
7132 | kvm_mmu_reset_context(vcpu); | |
7133 | ||
a50abc3b | 7134 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
7135 | pending_vec = find_first_bit( |
7136 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
7137 | if (pending_vec < max_bits) { | |
66fd3f7f | 7138 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 7139 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
7140 | } |
7141 | ||
3e6e0aab GT |
7142 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
7143 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
7144 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
7145 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
7146 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
7147 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 7148 | |
3e6e0aab GT |
7149 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
7150 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 7151 | |
5f0269f5 ME |
7152 | update_cr8_intercept(vcpu); |
7153 | ||
9c3e4aab | 7154 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 7155 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 7156 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 7157 | !is_protmode(vcpu)) |
9c3e4aab MT |
7158 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7159 | ||
3842d135 AK |
7160 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
7161 | ||
b6c7a5dc HB |
7162 | return 0; |
7163 | } | |
7164 | ||
d0bfb940 JK |
7165 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
7166 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 7167 | { |
355be0b9 | 7168 | unsigned long rflags; |
ae675ef0 | 7169 | int i, r; |
b6c7a5dc | 7170 | |
4f926bf2 JK |
7171 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
7172 | r = -EBUSY; | |
7173 | if (vcpu->arch.exception.pending) | |
2122ff5e | 7174 | goto out; |
4f926bf2 JK |
7175 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
7176 | kvm_queue_exception(vcpu, DB_VECTOR); | |
7177 | else | |
7178 | kvm_queue_exception(vcpu, BP_VECTOR); | |
7179 | } | |
7180 | ||
91586a3b JK |
7181 | /* |
7182 | * Read rflags as long as potentially injected trace flags are still | |
7183 | * filtered out. | |
7184 | */ | |
7185 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
7186 | |
7187 | vcpu->guest_debug = dbg->control; | |
7188 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
7189 | vcpu->guest_debug = 0; | |
7190 | ||
7191 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
7192 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
7193 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 7194 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
7195 | } else { |
7196 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
7197 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 7198 | } |
c8639010 | 7199 | kvm_update_dr7(vcpu); |
ae675ef0 | 7200 | |
f92653ee JK |
7201 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
7202 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
7203 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 7204 | |
91586a3b JK |
7205 | /* |
7206 | * Trigger an rflags update that will inject or remove the trace | |
7207 | * flags. | |
7208 | */ | |
7209 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 7210 | |
c8639010 | 7211 | kvm_x86_ops->update_db_bp_intercept(vcpu); |
b6c7a5dc | 7212 | |
4f926bf2 | 7213 | r = 0; |
d0bfb940 | 7214 | |
2122ff5e | 7215 | out: |
b6c7a5dc HB |
7216 | |
7217 | return r; | |
7218 | } | |
7219 | ||
8b006791 ZX |
7220 | /* |
7221 | * Translate a guest virtual address to a guest physical address. | |
7222 | */ | |
7223 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
7224 | struct kvm_translation *tr) | |
7225 | { | |
7226 | unsigned long vaddr = tr->linear_address; | |
7227 | gpa_t gpa; | |
f656ce01 | 7228 | int idx; |
8b006791 | 7229 | |
f656ce01 | 7230 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 7231 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 7232 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
7233 | tr->physical_address = gpa; |
7234 | tr->valid = gpa != UNMAPPED_GVA; | |
7235 | tr->writeable = 1; | |
7236 | tr->usermode = 0; | |
8b006791 ZX |
7237 | |
7238 | return 0; | |
7239 | } | |
7240 | ||
d0752060 HB |
7241 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
7242 | { | |
98918833 SY |
7243 | struct i387_fxsave_struct *fxsave = |
7244 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 7245 | |
d0752060 HB |
7246 | memcpy(fpu->fpr, fxsave->st_space, 128); |
7247 | fpu->fcw = fxsave->cwd; | |
7248 | fpu->fsw = fxsave->swd; | |
7249 | fpu->ftwx = fxsave->twd; | |
7250 | fpu->last_opcode = fxsave->fop; | |
7251 | fpu->last_ip = fxsave->rip; | |
7252 | fpu->last_dp = fxsave->rdp; | |
7253 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
7254 | ||
d0752060 HB |
7255 | return 0; |
7256 | } | |
7257 | ||
7258 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
7259 | { | |
98918833 SY |
7260 | struct i387_fxsave_struct *fxsave = |
7261 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 7262 | |
d0752060 HB |
7263 | memcpy(fxsave->st_space, fpu->fpr, 128); |
7264 | fxsave->cwd = fpu->fcw; | |
7265 | fxsave->swd = fpu->fsw; | |
7266 | fxsave->twd = fpu->ftwx; | |
7267 | fxsave->fop = fpu->last_opcode; | |
7268 | fxsave->rip = fpu->last_ip; | |
7269 | fxsave->rdp = fpu->last_dp; | |
7270 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
7271 | ||
d0752060 HB |
7272 | return 0; |
7273 | } | |
7274 | ||
d28bc9dd | 7275 | int fx_init(struct kvm_vcpu *vcpu, bool init_event) |
d0752060 | 7276 | { |
10ab25cd JK |
7277 | int err; |
7278 | ||
7279 | err = fpu_alloc(&vcpu->arch.guest_fpu); | |
7280 | if (err) | |
7281 | return err; | |
7282 | ||
d28bc9dd NA |
7283 | if (!init_event) |
7284 | fpu_finit(&vcpu->arch.guest_fpu); | |
7285 | ||
df1daba7 PB |
7286 | if (cpu_has_xsaves) |
7287 | vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv = | |
7288 | host_xcr0 | XSTATE_COMPACTION_ENABLED; | |
d0752060 | 7289 | |
2acf923e DC |
7290 | /* |
7291 | * Ensure guest xcr0 is valid for loading | |
7292 | */ | |
7293 | vcpu->arch.xcr0 = XSTATE_FP; | |
7294 | ||
ad312c7c | 7295 | vcpu->arch.cr0 |= X86_CR0_ET; |
10ab25cd JK |
7296 | |
7297 | return 0; | |
d0752060 HB |
7298 | } |
7299 | EXPORT_SYMBOL_GPL(fx_init); | |
7300 | ||
98918833 SY |
7301 | static void fx_free(struct kvm_vcpu *vcpu) |
7302 | { | |
7303 | fpu_free(&vcpu->arch.guest_fpu); | |
7304 | } | |
7305 | ||
d0752060 HB |
7306 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) |
7307 | { | |
2608d7a1 | 7308 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
7309 | return; |
7310 | ||
2acf923e DC |
7311 | /* |
7312 | * Restore all possible states in the guest, | |
7313 | * and assume host would use all available bits. | |
7314 | * Guest xcr0 would be loaded later. | |
7315 | */ | |
7316 | kvm_put_guest_xcr0(vcpu); | |
d0752060 | 7317 | vcpu->guest_fpu_loaded = 1; |
b1a74bf8 | 7318 | __kernel_fpu_begin(); |
98918833 | 7319 | fpu_restore_checking(&vcpu->arch.guest_fpu); |
0c04851c | 7320 | trace_kvm_fpu(1); |
d0752060 | 7321 | } |
d0752060 HB |
7322 | |
7323 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
7324 | { | |
2acf923e DC |
7325 | kvm_put_guest_xcr0(vcpu); |
7326 | ||
653f52c3 RR |
7327 | if (!vcpu->guest_fpu_loaded) { |
7328 | vcpu->fpu_counter = 0; | |
d0752060 | 7329 | return; |
653f52c3 | 7330 | } |
d0752060 HB |
7331 | |
7332 | vcpu->guest_fpu_loaded = 0; | |
98918833 | 7333 | fpu_save_init(&vcpu->arch.guest_fpu); |
b1a74bf8 | 7334 | __kernel_fpu_end(); |
f096ed85 | 7335 | ++vcpu->stat.fpu_reload; |
653f52c3 RR |
7336 | /* |
7337 | * If using eager FPU mode, or if the guest is a frequent user | |
7338 | * of the FPU, just leave the FPU active for next time. | |
7339 | * Every 255 times fpu_counter rolls over to 0; a guest that uses | |
7340 | * the FPU in bursts will revert to loading it on demand. | |
7341 | */ | |
a9b4fb7e | 7342 | if (!vcpu->arch.eager_fpu) { |
653f52c3 RR |
7343 | if (++vcpu->fpu_counter < 5) |
7344 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); | |
7345 | } | |
0c04851c | 7346 | trace_kvm_fpu(0); |
d0752060 | 7347 | } |
e9b11c17 ZX |
7348 | |
7349 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
7350 | { | |
12f9a48f | 7351 | kvmclock_reset(vcpu); |
7f1ea208 | 7352 | |
f5f48ee1 | 7353 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
98918833 | 7354 | fx_free(vcpu); |
e9b11c17 ZX |
7355 | kvm_x86_ops->vcpu_free(vcpu); |
7356 | } | |
7357 | ||
7358 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
7359 | unsigned int id) | |
7360 | { | |
c447e76b LL |
7361 | struct kvm_vcpu *vcpu; |
7362 | ||
6755bae8 ZA |
7363 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
7364 | printk_once(KERN_WARNING | |
7365 | "kvm: SMP vm created on host with unstable TSC; " | |
7366 | "guest TSC will not be reliable\n"); | |
c447e76b LL |
7367 | |
7368 | vcpu = kvm_x86_ops->vcpu_create(kvm, id); | |
7369 | ||
7370 | /* | |
7371 | * Activate fpu unconditionally in case the guest needs eager FPU. It will be | |
7372 | * deactivated soon if it doesn't. | |
7373 | */ | |
7374 | kvm_x86_ops->fpu_activate(vcpu); | |
7375 | return vcpu; | |
26e5215f | 7376 | } |
e9b11c17 | 7377 | |
26e5215f AK |
7378 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
7379 | { | |
7380 | int r; | |
e9b11c17 | 7381 | |
19efffa2 | 7382 | kvm_vcpu_mtrr_init(vcpu); |
9fc77441 MT |
7383 | r = vcpu_load(vcpu); |
7384 | if (r) | |
7385 | return r; | |
d28bc9dd | 7386 | kvm_vcpu_reset(vcpu, false); |
8a3c1a33 | 7387 | kvm_mmu_setup(vcpu); |
e9b11c17 | 7388 | vcpu_put(vcpu); |
26e5215f | 7389 | return r; |
e9b11c17 ZX |
7390 | } |
7391 | ||
31928aa5 | 7392 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 7393 | { |
8fe8ab46 | 7394 | struct msr_data msr; |
332967a3 | 7395 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 7396 | |
31928aa5 DD |
7397 | if (vcpu_load(vcpu)) |
7398 | return; | |
8fe8ab46 WA |
7399 | msr.data = 0x0; |
7400 | msr.index = MSR_IA32_TSC; | |
7401 | msr.host_initiated = true; | |
7402 | kvm_write_tsc(vcpu, &msr); | |
42897d86 MT |
7403 | vcpu_put(vcpu); |
7404 | ||
630994b3 MT |
7405 | if (!kvmclock_periodic_sync) |
7406 | return; | |
7407 | ||
332967a3 AJ |
7408 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, |
7409 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
7410 | } |
7411 | ||
d40ccc62 | 7412 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 7413 | { |
9fc77441 | 7414 | int r; |
344d9588 GN |
7415 | vcpu->arch.apf.msr_val = 0; |
7416 | ||
9fc77441 MT |
7417 | r = vcpu_load(vcpu); |
7418 | BUG_ON(r); | |
e9b11c17 ZX |
7419 | kvm_mmu_unload(vcpu); |
7420 | vcpu_put(vcpu); | |
7421 | ||
98918833 | 7422 | fx_free(vcpu); |
e9b11c17 ZX |
7423 | kvm_x86_ops->vcpu_free(vcpu); |
7424 | } | |
7425 | ||
d28bc9dd | 7426 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 7427 | { |
e69fab5d PB |
7428 | vcpu->arch.hflags = 0; |
7429 | ||
7460fb4a AK |
7430 | atomic_set(&vcpu->arch.nmi_queued, 0); |
7431 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 7432 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
7433 | kvm_clear_interrupt_queue(vcpu); |
7434 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 7435 | |
42dbaa5a | 7436 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 7437 | kvm_update_dr0123(vcpu); |
6f43ed01 | 7438 | vcpu->arch.dr6 = DR6_INIT; |
73aaf249 | 7439 | kvm_update_dr6(vcpu); |
42dbaa5a | 7440 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 7441 | kvm_update_dr7(vcpu); |
42dbaa5a | 7442 | |
1119022c NA |
7443 | vcpu->arch.cr2 = 0; |
7444 | ||
3842d135 | 7445 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 7446 | vcpu->arch.apf.msr_val = 0; |
c9aaa895 | 7447 | vcpu->arch.st.msr_val = 0; |
3842d135 | 7448 | |
12f9a48f GC |
7449 | kvmclock_reset(vcpu); |
7450 | ||
af585b92 GN |
7451 | kvm_clear_async_pf_completion_queue(vcpu); |
7452 | kvm_async_pf_hash_reset(vcpu); | |
7453 | vcpu->arch.apf.halted = false; | |
3842d135 | 7454 | |
64d60670 | 7455 | if (!init_event) { |
d28bc9dd | 7456 | kvm_pmu_reset(vcpu); |
64d60670 PB |
7457 | vcpu->arch.smbase = 0x30000; |
7458 | } | |
f5132b01 | 7459 | |
66f7b72e JS |
7460 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
7461 | vcpu->arch.regs_avail = ~0; | |
7462 | vcpu->arch.regs_dirty = ~0; | |
7463 | ||
d28bc9dd | 7464 | kvm_x86_ops->vcpu_reset(vcpu, init_event); |
e9b11c17 ZX |
7465 | } |
7466 | ||
2b4a273b | 7467 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
7468 | { |
7469 | struct kvm_segment cs; | |
7470 | ||
7471 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
7472 | cs.selector = vector << 8; | |
7473 | cs.base = vector << 12; | |
7474 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
7475 | kvm_rip_write(vcpu, 0); | |
e9b11c17 ZX |
7476 | } |
7477 | ||
13a34e06 | 7478 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 7479 | { |
ca84d1a2 ZA |
7480 | struct kvm *kvm; |
7481 | struct kvm_vcpu *vcpu; | |
7482 | int i; | |
0dd6a6ed ZA |
7483 | int ret; |
7484 | u64 local_tsc; | |
7485 | u64 max_tsc = 0; | |
7486 | bool stable, backwards_tsc = false; | |
18863bdd AK |
7487 | |
7488 | kvm_shared_msr_cpu_online(); | |
13a34e06 | 7489 | ret = kvm_x86_ops->hardware_enable(); |
0dd6a6ed ZA |
7490 | if (ret != 0) |
7491 | return ret; | |
7492 | ||
7493 | local_tsc = native_read_tsc(); | |
7494 | stable = !check_tsc_unstable(); | |
7495 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
7496 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7497 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 7498 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
7499 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
7500 | backwards_tsc = true; | |
7501 | if (vcpu->arch.last_host_tsc > max_tsc) | |
7502 | max_tsc = vcpu->arch.last_host_tsc; | |
7503 | } | |
7504 | } | |
7505 | } | |
7506 | ||
7507 | /* | |
7508 | * Sometimes, even reliable TSCs go backwards. This happens on | |
7509 | * platforms that reset TSC during suspend or hibernate actions, but | |
7510 | * maintain synchronization. We must compensate. Fortunately, we can | |
7511 | * detect that condition here, which happens early in CPU bringup, | |
7512 | * before any KVM threads can be running. Unfortunately, we can't | |
7513 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
7514 | * enough into CPU bringup that we know how much real time has actually | |
7515 | * elapsed; our helper function, get_kernel_ns() will be using boot | |
7516 | * variables that haven't been updated yet. | |
7517 | * | |
7518 | * So we simply find the maximum observed TSC above, then record the | |
7519 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
7520 | * the adjustment will be applied. Note that we accumulate | |
7521 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
7522 | * gets a chance to run again. In the event that no KVM threads get a | |
7523 | * chance to run, we will miss the entire elapsed period, as we'll have | |
7524 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
7525 | * loose cycle time. This isn't too big a deal, since the loss will be | |
7526 | * uniform across all VCPUs (not to mention the scenario is extremely | |
7527 | * unlikely). It is possible that a second hibernate recovery happens | |
7528 | * much faster than a first, causing the observed TSC here to be | |
7529 | * smaller; this would require additional padding adjustment, which is | |
7530 | * why we set last_host_tsc to the local tsc observed here. | |
7531 | * | |
7532 | * N.B. - this code below runs only on platforms with reliable TSC, | |
7533 | * as that is the only way backwards_tsc is set above. Also note | |
7534 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
7535 | * have the same delta_cyc adjustment applied if backwards_tsc | |
7536 | * is detected. Note further, this adjustment is only done once, | |
7537 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
7538 | * called multiple times (one for each physical CPU bringup). | |
7539 | * | |
4a969980 | 7540 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
7541 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
7542 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
7543 | * guarantee that they stay in perfect synchronization. | |
7544 | */ | |
7545 | if (backwards_tsc) { | |
7546 | u64 delta_cyc = max_tsc - local_tsc; | |
16a96021 | 7547 | backwards_tsc_observed = true; |
0dd6a6ed ZA |
7548 | list_for_each_entry(kvm, &vm_list, vm_list) { |
7549 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7550 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
7551 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 7552 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
7553 | } |
7554 | ||
7555 | /* | |
7556 | * We have to disable TSC offset matching.. if you were | |
7557 | * booting a VM while issuing an S4 host suspend.... | |
7558 | * you may have some problem. Solving this issue is | |
7559 | * left as an exercise to the reader. | |
7560 | */ | |
7561 | kvm->arch.last_tsc_nsec = 0; | |
7562 | kvm->arch.last_tsc_write = 0; | |
7563 | } | |
7564 | ||
7565 | } | |
7566 | return 0; | |
e9b11c17 ZX |
7567 | } |
7568 | ||
13a34e06 | 7569 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 7570 | { |
13a34e06 RK |
7571 | kvm_x86_ops->hardware_disable(); |
7572 | drop_user_return_notifiers(); | |
e9b11c17 ZX |
7573 | } |
7574 | ||
7575 | int kvm_arch_hardware_setup(void) | |
7576 | { | |
9e9c3fe4 NA |
7577 | int r; |
7578 | ||
7579 | r = kvm_x86_ops->hardware_setup(); | |
7580 | if (r != 0) | |
7581 | return r; | |
7582 | ||
7583 | kvm_init_msr_list(); | |
7584 | return 0; | |
e9b11c17 ZX |
7585 | } |
7586 | ||
7587 | void kvm_arch_hardware_unsetup(void) | |
7588 | { | |
7589 | kvm_x86_ops->hardware_unsetup(); | |
7590 | } | |
7591 | ||
7592 | void kvm_arch_check_processor_compat(void *rtn) | |
7593 | { | |
7594 | kvm_x86_ops->check_processor_compatibility(rtn); | |
7595 | } | |
7596 | ||
3e515705 AK |
7597 | bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) |
7598 | { | |
7599 | return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); | |
7600 | } | |
7601 | ||
54e9818f GN |
7602 | struct static_key kvm_no_apic_vcpu __read_mostly; |
7603 | ||
e9b11c17 ZX |
7604 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) |
7605 | { | |
7606 | struct page *page; | |
7607 | struct kvm *kvm; | |
7608 | int r; | |
7609 | ||
7610 | BUG_ON(vcpu->kvm == NULL); | |
7611 | kvm = vcpu->kvm; | |
7612 | ||
6aef266c | 7613 | vcpu->arch.pv.pv_unhalted = false; |
9aabc88f | 7614 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
58d269d8 | 7615 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
a4535290 | 7616 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 7617 | else |
a4535290 | 7618 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
7619 | |
7620 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
7621 | if (!page) { | |
7622 | r = -ENOMEM; | |
7623 | goto fail; | |
7624 | } | |
ad312c7c | 7625 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 7626 | |
cc578287 | 7627 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c285545f | 7628 | |
e9b11c17 ZX |
7629 | r = kvm_mmu_create(vcpu); |
7630 | if (r < 0) | |
7631 | goto fail_free_pio_data; | |
7632 | ||
7633 | if (irqchip_in_kernel(kvm)) { | |
7634 | r = kvm_create_lapic(vcpu); | |
7635 | if (r < 0) | |
7636 | goto fail_mmu_destroy; | |
54e9818f GN |
7637 | } else |
7638 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
e9b11c17 | 7639 | |
890ca9ae HY |
7640 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
7641 | GFP_KERNEL); | |
7642 | if (!vcpu->arch.mce_banks) { | |
7643 | r = -ENOMEM; | |
443c39bc | 7644 | goto fail_free_lapic; |
890ca9ae HY |
7645 | } |
7646 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
7647 | ||
f1797359 WY |
7648 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { |
7649 | r = -ENOMEM; | |
f5f48ee1 | 7650 | goto fail_free_mce_banks; |
f1797359 | 7651 | } |
f5f48ee1 | 7652 | |
d28bc9dd | 7653 | r = fx_init(vcpu, false); |
66f7b72e JS |
7654 | if (r) |
7655 | goto fail_free_wbinvd_dirty_mask; | |
7656 | ||
ba904635 | 7657 | vcpu->arch.ia32_tsc_adjust_msr = 0x0; |
0b79459b | 7658 | vcpu->arch.pv_time_enabled = false; |
d7876f1b PB |
7659 | |
7660 | vcpu->arch.guest_supported_xcr0 = 0; | |
4344ee98 | 7661 | vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; |
d7876f1b | 7662 | |
5a4f55cd EK |
7663 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
7664 | ||
74545705 RK |
7665 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; |
7666 | ||
af585b92 | 7667 | kvm_async_pf_hash_reset(vcpu); |
f5132b01 | 7668 | kvm_pmu_init(vcpu); |
af585b92 | 7669 | |
e9b11c17 | 7670 | return 0; |
66f7b72e JS |
7671 | fail_free_wbinvd_dirty_mask: |
7672 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
7673 | fail_free_mce_banks: |
7674 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
7675 | fail_free_lapic: |
7676 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
7677 | fail_mmu_destroy: |
7678 | kvm_mmu_destroy(vcpu); | |
7679 | fail_free_pio_data: | |
ad312c7c | 7680 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
7681 | fail: |
7682 | return r; | |
7683 | } | |
7684 | ||
7685 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
7686 | { | |
f656ce01 MT |
7687 | int idx; |
7688 | ||
f5132b01 | 7689 | kvm_pmu_destroy(vcpu); |
36cb93fd | 7690 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 7691 | kvm_free_lapic(vcpu); |
f656ce01 | 7692 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 7693 | kvm_mmu_destroy(vcpu); |
f656ce01 | 7694 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 7695 | free_page((unsigned long)vcpu->arch.pio_data); |
54e9818f GN |
7696 | if (!irqchip_in_kernel(vcpu->kvm)) |
7697 | static_key_slow_dec(&kvm_no_apic_vcpu); | |
e9b11c17 | 7698 | } |
d19a9cd2 | 7699 | |
e790d9ef RK |
7700 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
7701 | { | |
ae97a3b8 | 7702 | kvm_x86_ops->sched_in(vcpu, cpu); |
e790d9ef RK |
7703 | } |
7704 | ||
e08b9637 | 7705 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 7706 | { |
e08b9637 CO |
7707 | if (type) |
7708 | return -EINVAL; | |
7709 | ||
6ef768fa | 7710 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 7711 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
365c8868 | 7712 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
4d5c5d0f | 7713 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 7714 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 7715 | |
5550af4d SY |
7716 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
7717 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
7718 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
7719 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
7720 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 7721 | |
038f8c11 | 7722 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 7723 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
7724 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
7725 | ||
7726 | pvclock_update_vm_gtod_copy(kvm); | |
53f658b3 | 7727 | |
7e44e449 | 7728 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 7729 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 7730 | |
d89f5eff | 7731 | return 0; |
d19a9cd2 ZX |
7732 | } |
7733 | ||
7734 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
7735 | { | |
9fc77441 MT |
7736 | int r; |
7737 | r = vcpu_load(vcpu); | |
7738 | BUG_ON(r); | |
d19a9cd2 ZX |
7739 | kvm_mmu_unload(vcpu); |
7740 | vcpu_put(vcpu); | |
7741 | } | |
7742 | ||
7743 | static void kvm_free_vcpus(struct kvm *kvm) | |
7744 | { | |
7745 | unsigned int i; | |
988a2cae | 7746 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
7747 | |
7748 | /* | |
7749 | * Unpin any mmu pages first. | |
7750 | */ | |
af585b92 GN |
7751 | kvm_for_each_vcpu(i, vcpu, kvm) { |
7752 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 7753 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 7754 | } |
988a2cae GN |
7755 | kvm_for_each_vcpu(i, vcpu, kvm) |
7756 | kvm_arch_vcpu_free(vcpu); | |
7757 | ||
7758 | mutex_lock(&kvm->lock); | |
7759 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
7760 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 7761 | |
988a2cae GN |
7762 | atomic_set(&kvm->online_vcpus, 0); |
7763 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
7764 | } |
7765 | ||
ad8ba2cd SY |
7766 | void kvm_arch_sync_events(struct kvm *kvm) |
7767 | { | |
332967a3 | 7768 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 7769 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
ba4cef31 | 7770 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 7771 | kvm_free_pit(kvm); |
ad8ba2cd SY |
7772 | } |
7773 | ||
9da0e4d5 PB |
7774 | int __x86_set_memory_region(struct kvm *kvm, |
7775 | const struct kvm_userspace_memory_region *mem) | |
7776 | { | |
7777 | int i, r; | |
7778 | ||
7779 | /* Called with kvm->slots_lock held. */ | |
7780 | BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM); | |
7781 | ||
7782 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { | |
7783 | struct kvm_userspace_memory_region m = *mem; | |
7784 | ||
7785 | m.slot |= i << 16; | |
7786 | r = __kvm_set_memory_region(kvm, &m); | |
7787 | if (r < 0) | |
7788 | return r; | |
7789 | } | |
7790 | ||
7791 | return 0; | |
7792 | } | |
7793 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
7794 | ||
7795 | int x86_set_memory_region(struct kvm *kvm, | |
7796 | const struct kvm_userspace_memory_region *mem) | |
7797 | { | |
7798 | int r; | |
7799 | ||
7800 | mutex_lock(&kvm->slots_lock); | |
7801 | r = __x86_set_memory_region(kvm, mem); | |
7802 | mutex_unlock(&kvm->slots_lock); | |
7803 | ||
7804 | return r; | |
7805 | } | |
7806 | EXPORT_SYMBOL_GPL(x86_set_memory_region); | |
7807 | ||
d19a9cd2 ZX |
7808 | void kvm_arch_destroy_vm(struct kvm *kvm) |
7809 | { | |
27469d29 AH |
7810 | if (current->mm == kvm->mm) { |
7811 | /* | |
7812 | * Free memory regions allocated on behalf of userspace, | |
7813 | * unless the the memory map has changed due to process exit | |
7814 | * or fd copying. | |
7815 | */ | |
7816 | struct kvm_userspace_memory_region mem; | |
7817 | memset(&mem, 0, sizeof(mem)); | |
7818 | mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
9da0e4d5 | 7819 | x86_set_memory_region(kvm, &mem); |
27469d29 AH |
7820 | |
7821 | mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
9da0e4d5 | 7822 | x86_set_memory_region(kvm, &mem); |
27469d29 AH |
7823 | |
7824 | mem.slot = TSS_PRIVATE_MEMSLOT; | |
9da0e4d5 | 7825 | x86_set_memory_region(kvm, &mem); |
27469d29 | 7826 | } |
6eb55818 | 7827 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
7828 | kfree(kvm->arch.vpic); |
7829 | kfree(kvm->arch.vioapic); | |
d19a9cd2 | 7830 | kvm_free_vcpus(kvm); |
1e08ec4a | 7831 | kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
d19a9cd2 | 7832 | } |
0de10343 | 7833 | |
5587027c | 7834 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, |
db3fe4eb TY |
7835 | struct kvm_memory_slot *dont) |
7836 | { | |
7837 | int i; | |
7838 | ||
d89cc617 TY |
7839 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
7840 | if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { | |
548ef284 | 7841 | kvfree(free->arch.rmap[i]); |
d89cc617 | 7842 | free->arch.rmap[i] = NULL; |
77d11309 | 7843 | } |
d89cc617 TY |
7844 | if (i == 0) |
7845 | continue; | |
7846 | ||
7847 | if (!dont || free->arch.lpage_info[i - 1] != | |
7848 | dont->arch.lpage_info[i - 1]) { | |
548ef284 | 7849 | kvfree(free->arch.lpage_info[i - 1]); |
d89cc617 | 7850 | free->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
7851 | } |
7852 | } | |
7853 | } | |
7854 | ||
5587027c AK |
7855 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
7856 | unsigned long npages) | |
db3fe4eb TY |
7857 | { |
7858 | int i; | |
7859 | ||
d89cc617 | 7860 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
db3fe4eb TY |
7861 | unsigned long ugfn; |
7862 | int lpages; | |
d89cc617 | 7863 | int level = i + 1; |
db3fe4eb TY |
7864 | |
7865 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
7866 | slot->base_gfn, level) + 1; | |
7867 | ||
d89cc617 TY |
7868 | slot->arch.rmap[i] = |
7869 | kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); | |
7870 | if (!slot->arch.rmap[i]) | |
77d11309 | 7871 | goto out_free; |
d89cc617 TY |
7872 | if (i == 0) |
7873 | continue; | |
77d11309 | 7874 | |
d89cc617 TY |
7875 | slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * |
7876 | sizeof(*slot->arch.lpage_info[i - 1])); | |
7877 | if (!slot->arch.lpage_info[i - 1]) | |
db3fe4eb TY |
7878 | goto out_free; |
7879 | ||
7880 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) | |
d89cc617 | 7881 | slot->arch.lpage_info[i - 1][0].write_count = 1; |
db3fe4eb | 7882 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
d89cc617 | 7883 | slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; |
db3fe4eb TY |
7884 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
7885 | /* | |
7886 | * If the gfn and userspace address are not aligned wrt each | |
7887 | * other, or if explicitly asked to, disable large page | |
7888 | * support for this slot | |
7889 | */ | |
7890 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
7891 | !kvm_largepages_enabled()) { | |
7892 | unsigned long j; | |
7893 | ||
7894 | for (j = 0; j < lpages; ++j) | |
d89cc617 | 7895 | slot->arch.lpage_info[i - 1][j].write_count = 1; |
db3fe4eb TY |
7896 | } |
7897 | } | |
7898 | ||
7899 | return 0; | |
7900 | ||
7901 | out_free: | |
d89cc617 | 7902 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 7903 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
7904 | slot->arch.rmap[i] = NULL; |
7905 | if (i == 0) | |
7906 | continue; | |
7907 | ||
548ef284 | 7908 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 7909 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
7910 | } |
7911 | return -ENOMEM; | |
7912 | } | |
7913 | ||
15f46015 | 7914 | void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) |
e59dbe09 | 7915 | { |
e6dff7d1 TY |
7916 | /* |
7917 | * memslots->generation has been incremented. | |
7918 | * mmio generation may have reached its maximum value. | |
7919 | */ | |
54bf36aa | 7920 | kvm_mmu_invalidate_mmio_sptes(kvm, slots); |
e59dbe09 TY |
7921 | } |
7922 | ||
f7784b8e MT |
7923 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
7924 | struct kvm_memory_slot *memslot, | |
09170a49 | 7925 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 7926 | enum kvm_mr_change change) |
0de10343 | 7927 | { |
7a905b14 TY |
7928 | /* |
7929 | * Only private memory slots need to be mapped here since | |
7930 | * KVM_SET_MEMORY_REGION ioctl is no longer supported. | |
0de10343 | 7931 | */ |
7b6195a9 | 7932 | if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) { |
7a905b14 | 7933 | unsigned long userspace_addr; |
604b38ac | 7934 | |
7a905b14 TY |
7935 | /* |
7936 | * MAP_SHARED to prevent internal slot pages from being moved | |
7937 | * by fork()/COW. | |
7938 | */ | |
7b6195a9 | 7939 | userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE, |
7a905b14 TY |
7940 | PROT_READ | PROT_WRITE, |
7941 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
0de10343 | 7942 | |
7a905b14 TY |
7943 | if (IS_ERR((void *)userspace_addr)) |
7944 | return PTR_ERR((void *)userspace_addr); | |
604b38ac | 7945 | |
7a905b14 | 7946 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
7947 | } |
7948 | ||
f7784b8e MT |
7949 | return 0; |
7950 | } | |
7951 | ||
88178fd4 KH |
7952 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
7953 | struct kvm_memory_slot *new) | |
7954 | { | |
7955 | /* Still write protect RO slot */ | |
7956 | if (new->flags & KVM_MEM_READONLY) { | |
7957 | kvm_mmu_slot_remove_write_access(kvm, new); | |
7958 | return; | |
7959 | } | |
7960 | ||
7961 | /* | |
7962 | * Call kvm_x86_ops dirty logging hooks when they are valid. | |
7963 | * | |
7964 | * kvm_x86_ops->slot_disable_log_dirty is called when: | |
7965 | * | |
7966 | * - KVM_MR_CREATE with dirty logging is disabled | |
7967 | * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag | |
7968 | * | |
7969 | * The reason is, in case of PML, we need to set D-bit for any slots | |
7970 | * with dirty logging disabled in order to eliminate unnecessary GPA | |
7971 | * logging in PML buffer (and potential PML buffer full VMEXT). This | |
7972 | * guarantees leaving PML enabled during guest's lifetime won't have | |
7973 | * any additonal overhead from PML when guest is running with dirty | |
7974 | * logging disabled for memory slots. | |
7975 | * | |
7976 | * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot | |
7977 | * to dirty logging mode. | |
7978 | * | |
7979 | * If kvm_x86_ops dirty logging hooks are invalid, use write protect. | |
7980 | * | |
7981 | * In case of write protect: | |
7982 | * | |
7983 | * Write protect all pages for dirty logging. | |
7984 | * | |
7985 | * All the sptes including the large sptes which point to this | |
7986 | * slot are set to readonly. We can not create any new large | |
7987 | * spte on this slot until the end of the logging. | |
7988 | * | |
7989 | * See the comments in fast_page_fault(). | |
7990 | */ | |
7991 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
7992 | if (kvm_x86_ops->slot_enable_log_dirty) | |
7993 | kvm_x86_ops->slot_enable_log_dirty(kvm, new); | |
7994 | else | |
7995 | kvm_mmu_slot_remove_write_access(kvm, new); | |
7996 | } else { | |
7997 | if (kvm_x86_ops->slot_disable_log_dirty) | |
7998 | kvm_x86_ops->slot_disable_log_dirty(kvm, new); | |
7999 | } | |
8000 | } | |
8001 | ||
f7784b8e | 8002 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 8003 | const struct kvm_userspace_memory_region *mem, |
8482644a | 8004 | const struct kvm_memory_slot *old, |
f36f3f28 | 8005 | const struct kvm_memory_slot *new, |
8482644a | 8006 | enum kvm_mr_change change) |
f7784b8e | 8007 | { |
8482644a | 8008 | int nr_mmu_pages = 0; |
f7784b8e | 8009 | |
f36f3f28 | 8010 | if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) { |
f7784b8e MT |
8011 | int ret; |
8012 | ||
8482644a TY |
8013 | ret = vm_munmap(old->userspace_addr, |
8014 | old->npages * PAGE_SIZE); | |
f7784b8e MT |
8015 | if (ret < 0) |
8016 | printk(KERN_WARNING | |
8017 | "kvm_vm_ioctl_set_memory_region: " | |
8018 | "failed to munmap memory\n"); | |
8019 | } | |
8020 | ||
48c0e4e9 XG |
8021 | if (!kvm->arch.n_requested_mmu_pages) |
8022 | nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); | |
8023 | ||
48c0e4e9 | 8024 | if (nr_mmu_pages) |
0de10343 | 8025 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); |
1c91cad4 | 8026 | |
3ea3b7fa WL |
8027 | /* |
8028 | * Dirty logging tracks sptes in 4k granularity, meaning that large | |
8029 | * sptes have to be split. If live migration is successful, the guest | |
8030 | * in the source machine will be destroyed and large sptes will be | |
8031 | * created in the destination. However, if the guest continues to run | |
8032 | * in the source machine (for example if live migration fails), small | |
8033 | * sptes will remain around and cause bad performance. | |
8034 | * | |
8035 | * Scan sptes if dirty logging has been stopped, dropping those | |
8036 | * which can be collapsed into a single large-page spte. Later | |
8037 | * page faults will create the large-page sptes. | |
8038 | */ | |
8039 | if ((change != KVM_MR_DELETE) && | |
8040 | (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && | |
8041 | !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
8042 | kvm_mmu_zap_collapsible_sptes(kvm, new); | |
8043 | ||
c972f3b1 | 8044 | /* |
88178fd4 | 8045 | * Set up write protection and/or dirty logging for the new slot. |
c126d94f | 8046 | * |
88178fd4 KH |
8047 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have |
8048 | * been zapped so no dirty logging staff is needed for old slot. For | |
8049 | * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the | |
8050 | * new and it's also covered when dealing with the new slot. | |
f36f3f28 PB |
8051 | * |
8052 | * FIXME: const-ify all uses of struct kvm_memory_slot. | |
c972f3b1 | 8053 | */ |
88178fd4 | 8054 | if (change != KVM_MR_DELETE) |
f36f3f28 | 8055 | kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); |
0de10343 | 8056 | } |
1d737c8a | 8057 | |
2df72e9b | 8058 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 8059 | { |
6ca18b69 | 8060 | kvm_mmu_invalidate_zap_all_pages(kvm); |
34d4cb8f MT |
8061 | } |
8062 | ||
2df72e9b MT |
8063 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
8064 | struct kvm_memory_slot *slot) | |
8065 | { | |
6ca18b69 | 8066 | kvm_mmu_invalidate_zap_all_pages(kvm); |
2df72e9b MT |
8067 | } |
8068 | ||
1d737c8a ZX |
8069 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
8070 | { | |
b6b8a145 JK |
8071 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) |
8072 | kvm_x86_ops->check_nested_events(vcpu, false); | |
8073 | ||
af585b92 GN |
8074 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
8075 | !vcpu->arch.apf.halted) | |
8076 | || !list_empty_careful(&vcpu->async_pf.done) | |
66450a21 | 8077 | || kvm_apic_has_events(vcpu) |
6aef266c | 8078 | || vcpu->arch.pv.pv_unhalted |
7460fb4a | 8079 | || atomic_read(&vcpu->arch.nmi_queued) || |
a1b37100 GN |
8080 | (kvm_arch_interrupt_allowed(vcpu) && |
8081 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 8082 | } |
5736199a | 8083 | |
b6d33834 | 8084 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 8085 | { |
b6d33834 | 8086 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 8087 | } |
78646121 GN |
8088 | |
8089 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
8090 | { | |
8091 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
8092 | } | |
229456fc | 8093 | |
82b32774 | 8094 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 8095 | { |
82b32774 NA |
8096 | if (is_64_bit_mode(vcpu)) |
8097 | return kvm_rip_read(vcpu); | |
8098 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
8099 | kvm_rip_read(vcpu)); | |
8100 | } | |
8101 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 8102 | |
82b32774 NA |
8103 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
8104 | { | |
8105 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
8106 | } |
8107 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
8108 | ||
94fe45da JK |
8109 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
8110 | { | |
8111 | unsigned long rflags; | |
8112 | ||
8113 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
8114 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 8115 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
8116 | return rflags; |
8117 | } | |
8118 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
8119 | ||
6addfc42 | 8120 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
8121 | { |
8122 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 8123 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 8124 | rflags |= X86_EFLAGS_TF; |
94fe45da | 8125 | kvm_x86_ops->set_rflags(vcpu, rflags); |
6addfc42 PB |
8126 | } |
8127 | ||
8128 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
8129 | { | |
8130 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 8131 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
8132 | } |
8133 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
8134 | ||
56028d08 GN |
8135 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
8136 | { | |
8137 | int r; | |
8138 | ||
fb67e14f | 8139 | if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || |
f2e10669 | 8140 | work->wakeup_all) |
56028d08 GN |
8141 | return; |
8142 | ||
8143 | r = kvm_mmu_reload(vcpu); | |
8144 | if (unlikely(r)) | |
8145 | return; | |
8146 | ||
fb67e14f XG |
8147 | if (!vcpu->arch.mmu.direct_map && |
8148 | work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) | |
8149 | return; | |
8150 | ||
56028d08 GN |
8151 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); |
8152 | } | |
8153 | ||
af585b92 GN |
8154 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
8155 | { | |
8156 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
8157 | } | |
8158 | ||
8159 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
8160 | { | |
8161 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
8162 | } | |
8163 | ||
8164 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8165 | { | |
8166 | u32 key = kvm_async_pf_hash_fn(gfn); | |
8167 | ||
8168 | while (vcpu->arch.apf.gfns[key] != ~0) | |
8169 | key = kvm_async_pf_next_probe(key); | |
8170 | ||
8171 | vcpu->arch.apf.gfns[key] = gfn; | |
8172 | } | |
8173 | ||
8174 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8175 | { | |
8176 | int i; | |
8177 | u32 key = kvm_async_pf_hash_fn(gfn); | |
8178 | ||
8179 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
8180 | (vcpu->arch.apf.gfns[key] != gfn && |
8181 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
8182 | key = kvm_async_pf_next_probe(key); |
8183 | ||
8184 | return key; | |
8185 | } | |
8186 | ||
8187 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8188 | { | |
8189 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
8190 | } | |
8191 | ||
8192 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8193 | { | |
8194 | u32 i, j, k; | |
8195 | ||
8196 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
8197 | while (true) { | |
8198 | vcpu->arch.apf.gfns[i] = ~0; | |
8199 | do { | |
8200 | j = kvm_async_pf_next_probe(j); | |
8201 | if (vcpu->arch.apf.gfns[j] == ~0) | |
8202 | return; | |
8203 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
8204 | /* | |
8205 | * k lies cyclically in ]i,j] | |
8206 | * | i.k.j | | |
8207 | * |....j i.k.| or |.k..j i...| | |
8208 | */ | |
8209 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
8210 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
8211 | i = j; | |
8212 | } | |
8213 | } | |
8214 | ||
7c90705b GN |
8215 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
8216 | { | |
8217 | ||
8218 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
8219 | sizeof(val)); | |
8220 | } | |
8221 | ||
af585b92 GN |
8222 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
8223 | struct kvm_async_pf *work) | |
8224 | { | |
6389ee94 AK |
8225 | struct x86_exception fault; |
8226 | ||
7c90705b | 8227 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 8228 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b GN |
8229 | |
8230 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
fc5f06fa GN |
8231 | (vcpu->arch.apf.send_user_only && |
8232 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7c90705b GN |
8233 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
8234 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
8235 | fault.vector = PF_VECTOR; |
8236 | fault.error_code_valid = true; | |
8237 | fault.error_code = 0; | |
8238 | fault.nested_page_fault = false; | |
8239 | fault.address = work->arch.token; | |
8240 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 8241 | } |
af585b92 GN |
8242 | } |
8243 | ||
8244 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
8245 | struct kvm_async_pf *work) | |
8246 | { | |
6389ee94 AK |
8247 | struct x86_exception fault; |
8248 | ||
7c90705b | 8249 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
f2e10669 | 8250 | if (work->wakeup_all) |
7c90705b GN |
8251 | work->arch.token = ~0; /* broadcast wakeup */ |
8252 | else | |
8253 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
8254 | ||
8255 | if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && | |
8256 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
6389ee94 AK |
8257 | fault.vector = PF_VECTOR; |
8258 | fault.error_code_valid = true; | |
8259 | fault.error_code = 0; | |
8260 | fault.nested_page_fault = false; | |
8261 | fault.address = work->arch.token; | |
8262 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 8263 | } |
e6d53e3b | 8264 | vcpu->arch.apf.halted = false; |
a4fa1635 | 8265 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
8266 | } |
8267 | ||
8268 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
8269 | { | |
8270 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
8271 | return true; | |
8272 | else | |
8273 | return !kvm_event_needs_reinjection(vcpu) && | |
8274 | kvm_x86_ops->interrupt_allowed(vcpu); | |
af585b92 GN |
8275 | } |
8276 | ||
e0f0bbc5 AW |
8277 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
8278 | { | |
8279 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
8280 | } | |
8281 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
8282 | ||
8283 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
8284 | { | |
8285 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
8286 | } | |
8287 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
8288 | ||
8289 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
8290 | { | |
8291 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
8292 | } | |
8293 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
8294 | ||
229456fc MT |
8295 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
8296 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
8297 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
8298 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
8299 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 8300 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 8301 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 8302 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 8303 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 8304 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 8305 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 8306 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 8307 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
7b46268d | 8308 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); |
843e4330 | 8309 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |