]>
Commit | Line | Data |
---|---|---|
20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
88197e6a | 21 | #include "ioapic.h" |
1d737c8a | 22 | #include "mmu.h" |
7837699f | 23 | #include "i8254.h" |
37817f29 | 24 | #include "tss.h" |
5fdbf976 | 25 | #include "kvm_cache_regs.h" |
2f728d66 | 26 | #include "kvm_emulate.h" |
26eef70c | 27 | #include "x86.h" |
00b27a3e | 28 | #include "cpuid.h" |
474a5bb9 | 29 | #include "pmu.h" |
e83d5887 | 30 | #include "hyperv.h" |
8df14af4 | 31 | #include "lapic.h" |
23200b7a | 32 | #include "xen.h" |
313a3dc7 | 33 | |
18068523 | 34 | #include <linux/clocksource.h> |
4d5c5d0f | 35 | #include <linux/interrupt.h> |
313a3dc7 CO |
36 | #include <linux/kvm.h> |
37 | #include <linux/fs.h> | |
38 | #include <linux/vmalloc.h> | |
1767e931 PG |
39 | #include <linux/export.h> |
40 | #include <linux/moduleparam.h> | |
0de10343 | 41 | #include <linux/mman.h> |
2bacc55c | 42 | #include <linux/highmem.h> |
19de40a8 | 43 | #include <linux/iommu.h> |
62c476c7 | 44 | #include <linux/intel-iommu.h> |
c8076604 | 45 | #include <linux/cpufreq.h> |
18863bdd | 46 | #include <linux/user-return-notifier.h> |
a983fb23 | 47 | #include <linux/srcu.h> |
5a0e3ad6 | 48 | #include <linux/slab.h> |
ff9d07a0 | 49 | #include <linux/perf_event.h> |
7bee342a | 50 | #include <linux/uaccess.h> |
af585b92 | 51 | #include <linux/hash.h> |
a1b60c1c | 52 | #include <linux/pci.h> |
16e8d74d MT |
53 | #include <linux/timekeeper_internal.h> |
54 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
55 | #include <linux/kvm_irqfd.h> |
56 | #include <linux/irqbypass.h> | |
3905f9ad | 57 | #include <linux/sched/stat.h> |
0c5f81da | 58 | #include <linux/sched/isolation.h> |
d0ec49d4 | 59 | #include <linux/mem_encrypt.h> |
72c3c0fe | 60 | #include <linux/entry-kvm.h> |
7d62874f | 61 | #include <linux/suspend.h> |
3905f9ad | 62 | |
aec51dc4 | 63 | #include <trace/events/kvm.h> |
2ed152af | 64 | |
24f1e32c | 65 | #include <asm/debugreg.h> |
d825ed0a | 66 | #include <asm/msr.h> |
a5f61300 | 67 | #include <asm/desc.h> |
890ca9ae | 68 | #include <asm/mce.h> |
784a4661 | 69 | #include <asm/pkru.h> |
f89e32e0 | 70 | #include <linux/kernel_stat.h> |
78f7f1e5 | 71 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 72 | #include <asm/pvclock.h> |
217fc9cf | 73 | #include <asm/div64.h> |
efc64404 | 74 | #include <asm/irq_remapping.h> |
b0c39dc6 | 75 | #include <asm/mshyperv.h> |
0092e434 | 76 | #include <asm/hypervisor.h> |
9715092f | 77 | #include <asm/tlbflush.h> |
bf8c55d8 | 78 | #include <asm/intel_pt.h> |
b3dc0695 | 79 | #include <asm/emulate_prefix.h> |
fe7e9488 | 80 | #include <asm/sgx.h> |
dd2cb348 | 81 | #include <clocksource/hyperv_timer.h> |
043405e1 | 82 | |
d1898b73 DH |
83 | #define CREATE_TRACE_POINTS |
84 | #include "trace.h" | |
85 | ||
313a3dc7 | 86 | #define MAX_IO_MSRS 256 |
890ca9ae | 87 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
88 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
89 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 90 | |
0f65dd70 | 91 | #define emul_to_vcpu(ctxt) \ |
c9b8b07c | 92 | ((struct kvm_vcpu *)(ctxt)->vcpu) |
0f65dd70 | 93 | |
50a37eb4 JR |
94 | /* EFER defaults: |
95 | * - enable syscall per default because its emulated by KVM | |
96 | * - enable LME and LMA per default on 64 bit KVM | |
97 | */ | |
98 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
99 | static |
100 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 101 | #else |
1260edbe | 102 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 103 | #endif |
313a3dc7 | 104 | |
b11306b5 SC |
105 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
106 | ||
0dbb1123 AK |
107 | #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) |
108 | ||
c519265f RK |
109 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
110 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 111 | |
cb142eb7 | 112 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 113 | static void process_nmi(struct kvm_vcpu *vcpu); |
1f7becf1 | 114 | static void process_smi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 115 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 116 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
117 | static void store_regs(struct kvm_vcpu *vcpu); |
118 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 119 | |
6dba9403 ML |
120 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); |
121 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); | |
122 | ||
afaf0b2f | 123 | struct kvm_x86_ops kvm_x86_ops __read_mostly; |
5fdbf976 | 124 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 125 | |
9af5471b JB |
126 | #define KVM_X86_OP(func) \ |
127 | DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ | |
128 | *(((struct kvm_x86_ops *)0)->func)); | |
129 | #define KVM_X86_OP_NULL KVM_X86_OP | |
130 | #include <asm/kvm-x86-ops.h> | |
131 | EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); | |
132 | EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); | |
133 | EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); | |
134 | ||
893590c7 | 135 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 136 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 137 | |
d855066f | 138 | bool __read_mostly report_ignored_msrs = true; |
fab0aa3b | 139 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); |
d855066f | 140 | EXPORT_SYMBOL_GPL(report_ignored_msrs); |
fab0aa3b | 141 | |
4c27625b | 142 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
143 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
144 | ||
630994b3 MT |
145 | static bool __read_mostly kvmclock_periodic_sync = true; |
146 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
147 | ||
893590c7 | 148 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 149 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 150 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 151 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
152 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
153 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
154 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
155 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
156 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
157 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
fe6b6bc8 CQ |
158 | bool __read_mostly kvm_has_bus_lock_exit; |
159 | EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); | |
92a1f12d | 160 | |
cc578287 | 161 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 162 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
163 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
164 | ||
c3941d9e SC |
165 | /* |
166 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
d9f6e12f | 167 | * adaptive tuning starting from default advancement of 1000ns. '0' disables |
c3941d9e | 168 | * advancement entirely. Any other value is used as-is and disables adaptive |
d9f6e12f | 169 | * tuning, i.e. allows privileged userspace to set an exact advancement time. |
c3941d9e SC |
170 | */ |
171 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 172 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 173 | |
52004014 FW |
174 | static bool __read_mostly vector_hashing = true; |
175 | module_param(vector_hashing, bool, S_IRUGO); | |
176 | ||
c4ae60e4 LA |
177 | bool __read_mostly enable_vmware_backdoor = false; |
178 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
179 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
180 | ||
6c86eedc WL |
181 | static bool __read_mostly force_emulation_prefix = false; |
182 | module_param(force_emulation_prefix, bool, S_IRUGO); | |
183 | ||
0c5f81da WL |
184 | int __read_mostly pi_inject_timer = -1; |
185 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
186 | ||
7e34fbd0 SC |
187 | /* |
188 | * Restoring the host value for MSRs that are only consumed when running in | |
189 | * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU | |
190 | * returns to userspace, i.e. the kernel can run with the guest's value. | |
191 | */ | |
192 | #define KVM_MAX_NR_USER_RETURN_MSRS 16 | |
18863bdd | 193 | |
7e34fbd0 | 194 | struct kvm_user_return_msrs { |
18863bdd AK |
195 | struct user_return_notifier urn; |
196 | bool registered; | |
7e34fbd0 | 197 | struct kvm_user_return_msr_values { |
2bf78fa7 SY |
198 | u64 host; |
199 | u64 curr; | |
7e34fbd0 | 200 | } values[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
201 | }; |
202 | ||
9cc39a5a SC |
203 | u32 __read_mostly kvm_nr_uret_msrs; |
204 | EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); | |
205 | static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; | |
7e34fbd0 | 206 | static struct kvm_user_return_msrs __percpu *user_return_msrs; |
18863bdd | 207 | |
cfc48181 SC |
208 | #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ |
209 | | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | |
210 | | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | |
211 | | XFEATURE_MASK_PKRU) | |
212 | ||
91661989 SC |
213 | u64 __read_mostly host_efer; |
214 | EXPORT_SYMBOL_GPL(host_efer); | |
215 | ||
b96e6506 | 216 | bool __read_mostly allow_smaller_maxphyaddr = 0; |
3edd6839 MG |
217 | EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); |
218 | ||
fdf513e3 VK |
219 | bool __read_mostly enable_apicv = true; |
220 | EXPORT_SYMBOL_GPL(enable_apicv); | |
221 | ||
86137773 TL |
222 | u64 __read_mostly host_xss; |
223 | EXPORT_SYMBOL_GPL(host_xss); | |
408e9a31 PB |
224 | u64 __read_mostly supported_xss; |
225 | EXPORT_SYMBOL_GPL(supported_xss); | |
139a12cf | 226 | |
fcfe1bae JZ |
227 | const struct _kvm_stats_desc kvm_vm_stats_desc[] = { |
228 | KVM_GENERIC_VM_STATS(), | |
229 | STATS_DESC_COUNTER(VM, mmu_shadow_zapped), | |
230 | STATS_DESC_COUNTER(VM, mmu_pte_write), | |
231 | STATS_DESC_COUNTER(VM, mmu_pde_zapped), | |
232 | STATS_DESC_COUNTER(VM, mmu_flooded), | |
233 | STATS_DESC_COUNTER(VM, mmu_recycled), | |
234 | STATS_DESC_COUNTER(VM, mmu_cache_miss), | |
235 | STATS_DESC_ICOUNTER(VM, mmu_unsync), | |
71f51d2c MZ |
236 | STATS_DESC_ICOUNTER(VM, pages_4k), |
237 | STATS_DESC_ICOUNTER(VM, pages_2m), | |
238 | STATS_DESC_ICOUNTER(VM, pages_1g), | |
fcfe1bae | 239 | STATS_DESC_ICOUNTER(VM, nx_lpage_splits), |
ec1cf69c | 240 | STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), |
bc9e9e67 | 241 | STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) |
fcfe1bae | 242 | }; |
fcfe1bae JZ |
243 | |
244 | const struct kvm_stats_header kvm_vm_stats_header = { | |
245 | .name_size = KVM_STATS_NAME_SIZE, | |
246 | .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), | |
247 | .id_offset = sizeof(struct kvm_stats_header), | |
248 | .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, | |
249 | .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + | |
250 | sizeof(kvm_vm_stats_desc), | |
251 | }; | |
252 | ||
ce55c049 JZ |
253 | const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { |
254 | KVM_GENERIC_VCPU_STATS(), | |
255 | STATS_DESC_COUNTER(VCPU, pf_fixed), | |
256 | STATS_DESC_COUNTER(VCPU, pf_guest), | |
257 | STATS_DESC_COUNTER(VCPU, tlb_flush), | |
258 | STATS_DESC_COUNTER(VCPU, invlpg), | |
259 | STATS_DESC_COUNTER(VCPU, exits), | |
260 | STATS_DESC_COUNTER(VCPU, io_exits), | |
261 | STATS_DESC_COUNTER(VCPU, mmio_exits), | |
262 | STATS_DESC_COUNTER(VCPU, signal_exits), | |
263 | STATS_DESC_COUNTER(VCPU, irq_window_exits), | |
264 | STATS_DESC_COUNTER(VCPU, nmi_window_exits), | |
265 | STATS_DESC_COUNTER(VCPU, l1d_flush), | |
266 | STATS_DESC_COUNTER(VCPU, halt_exits), | |
267 | STATS_DESC_COUNTER(VCPU, request_irq_exits), | |
268 | STATS_DESC_COUNTER(VCPU, irq_exits), | |
269 | STATS_DESC_COUNTER(VCPU, host_state_reload), | |
270 | STATS_DESC_COUNTER(VCPU, fpu_reload), | |
271 | STATS_DESC_COUNTER(VCPU, insn_emulation), | |
272 | STATS_DESC_COUNTER(VCPU, insn_emulation_fail), | |
273 | STATS_DESC_COUNTER(VCPU, hypercalls), | |
274 | STATS_DESC_COUNTER(VCPU, irq_injections), | |
275 | STATS_DESC_COUNTER(VCPU, nmi_injections), | |
276 | STATS_DESC_COUNTER(VCPU, req_event), | |
277 | STATS_DESC_COUNTER(VCPU, nested_run), | |
278 | STATS_DESC_COUNTER(VCPU, directed_yield_attempted), | |
279 | STATS_DESC_COUNTER(VCPU, directed_yield_successful), | |
280 | STATS_DESC_ICOUNTER(VCPU, guest_mode) | |
281 | }; | |
ce55c049 JZ |
282 | |
283 | const struct kvm_stats_header kvm_vcpu_stats_header = { | |
284 | .name_size = KVM_STATS_NAME_SIZE, | |
285 | .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), | |
286 | .id_offset = sizeof(struct kvm_stats_header), | |
287 | .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, | |
288 | .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + | |
289 | sizeof(kvm_vcpu_stats_desc), | |
290 | }; | |
291 | ||
2acf923e | 292 | u64 __read_mostly host_xcr0; |
cfc48181 SC |
293 | u64 __read_mostly supported_xcr0; |
294 | EXPORT_SYMBOL_GPL(supported_xcr0); | |
2acf923e | 295 | |
80fbd280 | 296 | static struct kmem_cache *x86_fpu_cache; |
b666a4b6 | 297 | |
c9b8b07c SC |
298 | static struct kmem_cache *x86_emulator_cache; |
299 | ||
6abe9c13 PX |
300 | /* |
301 | * When called, it means the previous get/set msr reached an invalid msr. | |
cc4cb017 | 302 | * Return true if we want to ignore/silent this failed msr access. |
6abe9c13 | 303 | */ |
d632826f | 304 | static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) |
6abe9c13 PX |
305 | { |
306 | const char *op = write ? "wrmsr" : "rdmsr"; | |
307 | ||
308 | if (ignore_msrs) { | |
309 | if (report_ignored_msrs) | |
d383b314 TI |
310 | kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", |
311 | op, msr, data); | |
6abe9c13 | 312 | /* Mask the error */ |
cc4cb017 | 313 | return true; |
6abe9c13 | 314 | } else { |
d383b314 TI |
315 | kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", |
316 | op, msr, data); | |
cc4cb017 | 317 | return false; |
6abe9c13 PX |
318 | } |
319 | } | |
320 | ||
c9b8b07c SC |
321 | static struct kmem_cache *kvm_alloc_emulator_cache(void) |
322 | { | |
06add254 SC |
323 | unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); |
324 | unsigned int size = sizeof(struct x86_emulate_ctxt); | |
325 | ||
326 | return kmem_cache_create_usercopy("x86_emulator", size, | |
c9b8b07c | 327 | __alignof__(struct x86_emulate_ctxt), |
06add254 SC |
328 | SLAB_ACCOUNT, useroffset, |
329 | size - useroffset, NULL); | |
c9b8b07c SC |
330 | } |
331 | ||
b6785def | 332 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 333 | |
af585b92 GN |
334 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
335 | { | |
336 | int i; | |
dd03bcaa | 337 | for (i = 0; i < ASYNC_PF_PER_VCPU; i++) |
af585b92 GN |
338 | vcpu->arch.apf.gfns[i] = ~0; |
339 | } | |
340 | ||
18863bdd AK |
341 | static void kvm_on_user_return(struct user_return_notifier *urn) |
342 | { | |
343 | unsigned slot; | |
7e34fbd0 SC |
344 | struct kvm_user_return_msrs *msrs |
345 | = container_of(urn, struct kvm_user_return_msrs, urn); | |
346 | struct kvm_user_return_msr_values *values; | |
1650b4eb IA |
347 | unsigned long flags; |
348 | ||
349 | /* | |
350 | * Disabling irqs at this point since the following code could be | |
351 | * interrupted and executed through kvm_arch_hardware_disable() | |
352 | */ | |
353 | local_irq_save(flags); | |
7e34fbd0 SC |
354 | if (msrs->registered) { |
355 | msrs->registered = false; | |
1650b4eb IA |
356 | user_return_notifier_unregister(urn); |
357 | } | |
358 | local_irq_restore(flags); | |
9cc39a5a | 359 | for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { |
7e34fbd0 | 360 | values = &msrs->values[slot]; |
2bf78fa7 | 361 | if (values->host != values->curr) { |
9cc39a5a | 362 | wrmsrl(kvm_uret_msrs_list[slot], values->host); |
2bf78fa7 | 363 | values->curr = values->host; |
18863bdd AK |
364 | } |
365 | } | |
18863bdd AK |
366 | } |
367 | ||
e5fda4bb | 368 | static int kvm_probe_user_return_msr(u32 msr) |
5104d7ff SC |
369 | { |
370 | u64 val; | |
371 | int ret; | |
372 | ||
373 | preempt_disable(); | |
374 | ret = rdmsrl_safe(msr, &val); | |
375 | if (ret) | |
376 | goto out; | |
377 | ret = wrmsrl_safe(msr, val); | |
378 | out: | |
379 | preempt_enable(); | |
380 | return ret; | |
381 | } | |
5104d7ff | 382 | |
e5fda4bb | 383 | int kvm_add_user_return_msr(u32 msr) |
2bf78fa7 | 384 | { |
e5fda4bb SC |
385 | BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); |
386 | ||
387 | if (kvm_probe_user_return_msr(msr)) | |
388 | return -1; | |
389 | ||
390 | kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; | |
391 | return kvm_nr_uret_msrs++; | |
18863bdd | 392 | } |
e5fda4bb | 393 | EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); |
18863bdd | 394 | |
8ea8b8d6 SC |
395 | int kvm_find_user_return_msr(u32 msr) |
396 | { | |
397 | int i; | |
398 | ||
9cc39a5a SC |
399 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
400 | if (kvm_uret_msrs_list[i] == msr) | |
8ea8b8d6 SC |
401 | return i; |
402 | } | |
403 | return -1; | |
404 | } | |
405 | EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); | |
406 | ||
7e34fbd0 | 407 | static void kvm_user_return_msr_cpu_online(void) |
18863bdd | 408 | { |
05c19c2f | 409 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 410 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
05c19c2f SC |
411 | u64 value; |
412 | int i; | |
18863bdd | 413 | |
9cc39a5a SC |
414 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
415 | rdmsrl_safe(kvm_uret_msrs_list[i], &value); | |
7e34fbd0 SC |
416 | msrs->values[i].host = value; |
417 | msrs->values[i].curr = value; | |
05c19c2f | 418 | } |
18863bdd AK |
419 | } |
420 | ||
7e34fbd0 | 421 | int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 422 | { |
013f6a5d | 423 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 424 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
8b3c3104 | 425 | int err; |
18863bdd | 426 | |
7e34fbd0 SC |
427 | value = (value & mask) | (msrs->values[slot].host & ~mask); |
428 | if (value == msrs->values[slot].curr) | |
8b3c3104 | 429 | return 0; |
9cc39a5a | 430 | err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); |
8b3c3104 AH |
431 | if (err) |
432 | return 1; | |
433 | ||
7e34fbd0 SC |
434 | msrs->values[slot].curr = value; |
435 | if (!msrs->registered) { | |
436 | msrs->urn.on_user_return = kvm_on_user_return; | |
437 | user_return_notifier_register(&msrs->urn); | |
438 | msrs->registered = true; | |
18863bdd | 439 | } |
8b3c3104 | 440 | return 0; |
18863bdd | 441 | } |
7e34fbd0 | 442 | EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); |
18863bdd | 443 | |
13a34e06 | 444 | static void drop_user_return_notifiers(void) |
3548bab5 | 445 | { |
013f6a5d | 446 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 447 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
3548bab5 | 448 | |
7e34fbd0 SC |
449 | if (msrs->registered) |
450 | kvm_on_user_return(&msrs->urn); | |
3548bab5 AK |
451 | } |
452 | ||
6866b83e CO |
453 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
454 | { | |
8a5a87d9 | 455 | return vcpu->arch.apic_base; |
6866b83e CO |
456 | } |
457 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
458 | ||
58871649 JM |
459 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
460 | { | |
461 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
462 | } | |
463 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
464 | ||
58cb628d JK |
465 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
466 | { | |
58871649 JM |
467 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
468 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
a8ac864a | 469 | u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | |
d6321d49 | 470 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); |
58cb628d | 471 | |
58871649 | 472 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 473 | return 1; |
58871649 JM |
474 | if (!msr_info->host_initiated) { |
475 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
476 | return 1; | |
477 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
478 | return 1; | |
479 | } | |
58cb628d JK |
480 | |
481 | kvm_lapic_set_base(vcpu, msr_info->data); | |
4abaffce | 482 | kvm_recalculate_apic_map(vcpu->kvm); |
58cb628d | 483 | return 0; |
6866b83e CO |
484 | } |
485 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
486 | ||
ad0577c3 SC |
487 | /* |
488 | * Handle a fault on a hardware virtualization (VMX or SVM) instruction. | |
489 | * | |
490 | * Hardware virtualization extension instructions may fault if a reboot turns | |
491 | * off virtualization while processes are running. Usually after catching the | |
492 | * fault we just panic; during reboot instead the instruction is ignored. | |
493 | */ | |
494 | noinstr void kvm_spurious_fault(void) | |
e3ba45b8 GL |
495 | { |
496 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 497 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
498 | } |
499 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
500 | ||
3fd28fce ED |
501 | #define EXCPT_BENIGN 0 |
502 | #define EXCPT_CONTRIBUTORY 1 | |
503 | #define EXCPT_PF 2 | |
504 | ||
505 | static int exception_class(int vector) | |
506 | { | |
507 | switch (vector) { | |
508 | case PF_VECTOR: | |
509 | return EXCPT_PF; | |
510 | case DE_VECTOR: | |
511 | case TS_VECTOR: | |
512 | case NP_VECTOR: | |
513 | case SS_VECTOR: | |
514 | case GP_VECTOR: | |
515 | return EXCPT_CONTRIBUTORY; | |
516 | default: | |
517 | break; | |
518 | } | |
519 | return EXCPT_BENIGN; | |
520 | } | |
521 | ||
d6e8c854 NA |
522 | #define EXCPT_FAULT 0 |
523 | #define EXCPT_TRAP 1 | |
524 | #define EXCPT_ABORT 2 | |
525 | #define EXCPT_INTERRUPT 3 | |
526 | ||
527 | static int exception_type(int vector) | |
528 | { | |
529 | unsigned int mask; | |
530 | ||
531 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
532 | return EXCPT_INTERRUPT; | |
533 | ||
534 | mask = 1 << vector; | |
535 | ||
536 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
537 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
538 | return EXCPT_TRAP; | |
539 | ||
540 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
541 | return EXCPT_ABORT; | |
542 | ||
543 | /* Reserved exceptions will result in fault */ | |
544 | return EXCPT_FAULT; | |
545 | } | |
546 | ||
da998b46 JM |
547 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
548 | { | |
549 | unsigned nr = vcpu->arch.exception.nr; | |
550 | bool has_payload = vcpu->arch.exception.has_payload; | |
551 | unsigned long payload = vcpu->arch.exception.payload; | |
552 | ||
553 | if (!has_payload) | |
554 | return; | |
555 | ||
556 | switch (nr) { | |
f10c729f JM |
557 | case DB_VECTOR: |
558 | /* | |
559 | * "Certain debug exceptions may clear bit 0-3. The | |
560 | * remaining contents of the DR6 register are never | |
561 | * cleared by the processor". | |
562 | */ | |
563 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
564 | /* | |
9a3ecd5e CQ |
565 | * In order to reflect the #DB exception payload in guest |
566 | * dr6, three components need to be considered: active low | |
567 | * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, | |
568 | * DR6_BS and DR6_BT) | |
569 | * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. | |
570 | * In the target guest dr6: | |
571 | * FIXED_1 bits should always be set. | |
572 | * Active low bits should be cleared if 1-setting in payload. | |
573 | * Active high bits should be set if 1-setting in payload. | |
574 | * | |
575 | * Note, the payload is compatible with the pending debug | |
576 | * exceptions/exit qualification under VMX, that active_low bits | |
577 | * are active high in payload. | |
578 | * So they need to be flipped for DR6. | |
f10c729f | 579 | */ |
9a3ecd5e | 580 | vcpu->arch.dr6 |= DR6_ACTIVE_LOW; |
f10c729f | 581 | vcpu->arch.dr6 |= payload; |
9a3ecd5e | 582 | vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; |
307f1cfa OU |
583 | |
584 | /* | |
585 | * The #DB payload is defined as compatible with the 'pending | |
586 | * debug exceptions' field under VMX, not DR6. While bit 12 is | |
587 | * defined in the 'pending debug exceptions' field (enabled | |
588 | * breakpoint), it is reserved and must be zero in DR6. | |
589 | */ | |
590 | vcpu->arch.dr6 &= ~BIT(12); | |
f10c729f | 591 | break; |
da998b46 JM |
592 | case PF_VECTOR: |
593 | vcpu->arch.cr2 = payload; | |
594 | break; | |
595 | } | |
596 | ||
597 | vcpu->arch.exception.has_payload = false; | |
598 | vcpu->arch.exception.payload = 0; | |
599 | } | |
600 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
601 | ||
3fd28fce | 602 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 603 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 604 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
605 | { |
606 | u32 prev_nr; | |
607 | int class1, class2; | |
608 | ||
3842d135 AK |
609 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
610 | ||
664f8e26 | 611 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 612 | queue: |
664f8e26 WL |
613 | if (reinject) { |
614 | /* | |
615 | * On vmentry, vcpu->arch.exception.pending is only | |
616 | * true if an event injection was blocked by | |
617 | * nested_run_pending. In that case, however, | |
618 | * vcpu_enter_guest requests an immediate exit, | |
619 | * and the guest shouldn't proceed far enough to | |
620 | * need reinjection. | |
621 | */ | |
622 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
623 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
624 | if (WARN_ON_ONCE(has_payload)) { |
625 | /* | |
626 | * A reinjected event has already | |
627 | * delivered its payload. | |
628 | */ | |
629 | has_payload = false; | |
630 | payload = 0; | |
631 | } | |
664f8e26 WL |
632 | } else { |
633 | vcpu->arch.exception.pending = true; | |
634 | vcpu->arch.exception.injected = false; | |
635 | } | |
3fd28fce ED |
636 | vcpu->arch.exception.has_error_code = has_error; |
637 | vcpu->arch.exception.nr = nr; | |
638 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
639 | vcpu->arch.exception.has_payload = has_payload; |
640 | vcpu->arch.exception.payload = payload; | |
a06230b6 | 641 | if (!is_guest_mode(vcpu)) |
da998b46 | 642 | kvm_deliver_exception_payload(vcpu); |
3fd28fce ED |
643 | return; |
644 | } | |
645 | ||
646 | /* to check exception */ | |
647 | prev_nr = vcpu->arch.exception.nr; | |
648 | if (prev_nr == DF_VECTOR) { | |
649 | /* triple fault -> shutdown */ | |
a8eeb04a | 650 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
651 | return; |
652 | } | |
653 | class1 = exception_class(prev_nr); | |
654 | class2 = exception_class(nr); | |
655 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
656 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
657 | /* |
658 | * Generate double fault per SDM Table 5-5. Set | |
659 | * exception.pending = true so that the double fault | |
660 | * can trigger a nested vmexit. | |
661 | */ | |
3fd28fce | 662 | vcpu->arch.exception.pending = true; |
664f8e26 | 663 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
664 | vcpu->arch.exception.has_error_code = true; |
665 | vcpu->arch.exception.nr = DF_VECTOR; | |
666 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
667 | vcpu->arch.exception.has_payload = false; |
668 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
669 | } else |
670 | /* replace previous exception with a new one in a hope | |
671 | that instruction re-execution will regenerate lost | |
672 | exception */ | |
673 | goto queue; | |
674 | } | |
675 | ||
298101da AK |
676 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
677 | { | |
91e86d22 | 678 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
679 | } |
680 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
681 | ||
ce7ddec4 JR |
682 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
683 | { | |
91e86d22 | 684 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
685 | } |
686 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
687 | ||
4d5523cf PB |
688 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
689 | unsigned long payload) | |
f10c729f JM |
690 | { |
691 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
692 | } | |
4d5523cf | 693 | EXPORT_SYMBOL_GPL(kvm_queue_exception_p); |
f10c729f | 694 | |
da998b46 JM |
695 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
696 | u32 error_code, unsigned long payload) | |
697 | { | |
698 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
699 | true, payload, false); | |
700 | } | |
701 | ||
6affcbed | 702 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 703 | { |
db8fcefa AP |
704 | if (err) |
705 | kvm_inject_gp(vcpu, 0); | |
706 | else | |
6affcbed KH |
707 | return kvm_skip_emulated_instruction(vcpu); |
708 | ||
709 | return 1; | |
db8fcefa AP |
710 | } |
711 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 712 | |
6389ee94 | 713 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
714 | { |
715 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
716 | vcpu->arch.exception.nested_apf = |
717 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 718 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 719 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
720 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
721 | } else { | |
722 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
723 | fault->address); | |
724 | } | |
c3c91fee | 725 | } |
27d6c865 | 726 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 727 | |
53b3d8e9 SC |
728 | bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
729 | struct x86_exception *fault) | |
d4f8cf66 | 730 | { |
0cd665bd | 731 | struct kvm_mmu *fault_mmu; |
53b3d8e9 SC |
732 | WARN_ON_ONCE(fault->vector != PF_VECTOR); |
733 | ||
0cd665bd PB |
734 | fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : |
735 | vcpu->arch.walk_mmu; | |
ef54bcfe | 736 | |
ee1fa209 JS |
737 | /* |
738 | * Invalidate the TLB entry for the faulting address, if it exists, | |
739 | * else the access will fault indefinitely (and to emulate hardware). | |
740 | */ | |
741 | if ((fault->error_code & PFERR_PRESENT_MASK) && | |
742 | !(fault->error_code & PFERR_RSVD_MASK)) | |
743 | kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, | |
744 | fault_mmu->root_hpa); | |
745 | ||
746 | fault_mmu->inject_page_fault(vcpu, fault); | |
ef54bcfe | 747 | return fault->nested_page_fault; |
d4f8cf66 | 748 | } |
53b3d8e9 | 749 | EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); |
d4f8cf66 | 750 | |
3419ffc8 SY |
751 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
752 | { | |
7460fb4a AK |
753 | atomic_inc(&vcpu->arch.nmi_queued); |
754 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
755 | } |
756 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
757 | ||
298101da AK |
758 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
759 | { | |
91e86d22 | 760 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
761 | } |
762 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
763 | ||
ce7ddec4 JR |
764 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
765 | { | |
91e86d22 | 766 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
767 | } |
768 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
769 | ||
0a79b009 AK |
770 | /* |
771 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
772 | * a #GP and return false. | |
773 | */ | |
774 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 775 | { |
b3646477 | 776 | if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) |
0a79b009 AK |
777 | return true; |
778 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
779 | return false; | |
298101da | 780 | } |
0a79b009 | 781 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 782 | |
16f8a6f9 NA |
783 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
784 | { | |
785 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
786 | return true; | |
787 | ||
788 | kvm_queue_exception(vcpu, UD_VECTOR); | |
789 | return false; | |
790 | } | |
791 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
792 | ||
ec92fe44 JR |
793 | /* |
794 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 795 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
796 | * can read from guest physical or from the guest's guest physical memory. |
797 | */ | |
798 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
799 | gfn_t ngfn, void *data, int offset, int len, | |
800 | u32 access) | |
801 | { | |
54987b7a | 802 | struct x86_exception exception; |
ec92fe44 JR |
803 | gfn_t real_gfn; |
804 | gpa_t ngpa; | |
805 | ||
806 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 807 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
808 | if (real_gfn == UNMAPPED_GVA) |
809 | return -EFAULT; | |
810 | ||
811 | real_gfn = gpa_to_gfn(real_gfn); | |
812 | ||
54bf36aa | 813 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
814 | } |
815 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
816 | ||
16cfacc8 SC |
817 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
818 | { | |
5b7f575c | 819 | return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); |
16cfacc8 SC |
820 | } |
821 | ||
a03490ed | 822 | /* |
16cfacc8 | 823 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 824 | */ |
ff03a073 | 825 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
826 | { |
827 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
828 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
829 | int i; | |
830 | int ret; | |
ff03a073 | 831 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 832 | |
ff03a073 JR |
833 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
834 | offset * sizeof(u64), sizeof(pdpte), | |
835 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
836 | if (ret < 0) { |
837 | ret = 0; | |
838 | goto out; | |
839 | } | |
840 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
812f30b2 | 841 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 842 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
a03490ed CO |
843 | ret = 0; |
844 | goto out; | |
845 | } | |
846 | } | |
847 | ret = 1; | |
848 | ||
ff03a073 | 849 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
cb3c1e2f | 850 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); |
6bee3ca2 | 851 | kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); |
158a48ec ML |
852 | vcpu->arch.pdptrs_from_userspace = false; |
853 | ||
a03490ed | 854 | out: |
a03490ed CO |
855 | |
856 | return ret; | |
857 | } | |
cc4b6871 | 858 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 859 | |
f27ad38a TL |
860 | void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) |
861 | { | |
f27ad38a TL |
862 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
863 | kvm_clear_async_pf_completion_queue(vcpu); | |
864 | kvm_async_pf_hash_reset(vcpu); | |
865 | } | |
866 | ||
20f632bd | 867 | if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) |
f27ad38a TL |
868 | kvm_mmu_reset_context(vcpu); |
869 | ||
870 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && | |
871 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
872 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
873 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); | |
874 | } | |
875 | EXPORT_SYMBOL_GPL(kvm_post_set_cr0); | |
876 | ||
49a9b07e | 877 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 878 | { |
aad82703 | 879 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d42e3fae | 880 | unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; |
aad82703 | 881 | |
f9a48e6a AK |
882 | cr0 |= X86_CR0_ET; |
883 | ||
ab344828 | 884 | #ifdef CONFIG_X86_64 |
0f12244f GN |
885 | if (cr0 & 0xffffffff00000000UL) |
886 | return 1; | |
ab344828 GN |
887 | #endif |
888 | ||
889 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 890 | |
0f12244f GN |
891 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
892 | return 1; | |
a03490ed | 893 | |
0f12244f GN |
894 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
895 | return 1; | |
a03490ed | 896 | |
a03490ed | 897 | #ifdef CONFIG_X86_64 |
05487215 SC |
898 | if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && |
899 | (cr0 & X86_CR0_PG)) { | |
900 | int cs_db, cs_l; | |
901 | ||
902 | if (!is_pae(vcpu)) | |
903 | return 1; | |
b3646477 | 904 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
05487215 | 905 | if (cs_l) |
0f12244f | 906 | return 1; |
a03490ed | 907 | } |
05487215 SC |
908 | #endif |
909 | if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && | |
910 | is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && | |
911 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) | |
912 | return 1; | |
a03490ed | 913 | |
ad756a16 MJ |
914 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
915 | return 1; | |
916 | ||
b3646477 | 917 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
a03490ed | 918 | |
f27ad38a | 919 | kvm_post_set_cr0(vcpu, old_cr0, cr0); |
b18d5431 | 920 | |
0f12244f GN |
921 | return 0; |
922 | } | |
2d3ad1f4 | 923 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 924 | |
2d3ad1f4 | 925 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 926 | { |
49a9b07e | 927 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 928 | } |
2d3ad1f4 | 929 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 930 | |
139a12cf | 931 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 932 | { |
16809ecd TL |
933 | if (vcpu->arch.guest_state_protected) |
934 | return; | |
935 | ||
139a12cf AL |
936 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
937 | ||
938 | if (vcpu->arch.xcr0 != host_xcr0) | |
939 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
940 | ||
941 | if (vcpu->arch.xsaves_enabled && | |
942 | vcpu->arch.ia32_xss != host_xss) | |
943 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
944 | } | |
37486135 BM |
945 | |
946 | if (static_cpu_has(X86_FEATURE_PKU) && | |
947 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
948 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && | |
949 | vcpu->arch.pkru != vcpu->arch.host_pkru) | |
72a6c08c | 950 | write_pkru(vcpu->arch.pkru); |
42bdf991 | 951 | } |
139a12cf | 952 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 953 | |
139a12cf | 954 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 955 | { |
16809ecd TL |
956 | if (vcpu->arch.guest_state_protected) |
957 | return; | |
958 | ||
37486135 BM |
959 | if (static_cpu_has(X86_FEATURE_PKU) && |
960 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
961 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { | |
962 | vcpu->arch.pkru = rdpkru(); | |
963 | if (vcpu->arch.pkru != vcpu->arch.host_pkru) | |
72a6c08c | 964 | write_pkru(vcpu->arch.host_pkru); |
37486135 BM |
965 | } |
966 | ||
139a12cf AL |
967 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
968 | ||
969 | if (vcpu->arch.xcr0 != host_xcr0) | |
970 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
971 | ||
972 | if (vcpu->arch.xsaves_enabled && | |
973 | vcpu->arch.ia32_xss != host_xss) | |
974 | wrmsrl(MSR_IA32_XSS, host_xss); | |
975 | } | |
976 | ||
42bdf991 | 977 | } |
139a12cf | 978 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 979 | |
69b0049a | 980 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 981 | { |
56c103ec LJ |
982 | u64 xcr0 = xcr; |
983 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 984 | u64 valid_bits; |
2acf923e DC |
985 | |
986 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
987 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
988 | return 1; | |
d91cab78 | 989 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 990 | return 1; |
d91cab78 | 991 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 992 | return 1; |
46c34cb0 PB |
993 | |
994 | /* | |
995 | * Do not allow the guest to set bits that we do not support | |
996 | * saving. However, xcr0 bit 0 is always set, even if the | |
997 | * emulated CPU does not support XSAVE (see fx_init). | |
998 | */ | |
d91cab78 | 999 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 1000 | if (xcr0 & ~valid_bits) |
2acf923e | 1001 | return 1; |
46c34cb0 | 1002 | |
d91cab78 DH |
1003 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
1004 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
1005 | return 1; |
1006 | ||
d91cab78 DH |
1007 | if (xcr0 & XFEATURE_MASK_AVX512) { |
1008 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 1009 | return 1; |
d91cab78 | 1010 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
1011 | return 1; |
1012 | } | |
2acf923e | 1013 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 1014 | |
d91cab78 | 1015 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
aedbaf4f | 1016 | kvm_update_cpuid_runtime(vcpu); |
2acf923e DC |
1017 | return 0; |
1018 | } | |
1019 | ||
92f9895c | 1020 | int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) |
2acf923e | 1021 | { |
92f9895c SC |
1022 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || |
1023 | __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { | |
1024 | kvm_inject_gp(vcpu, 0); | |
1025 | return 1; | |
1026 | } | |
bbefd4fc | 1027 | |
92f9895c | 1028 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e | 1029 | } |
92f9895c | 1030 | EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); |
2acf923e | 1031 | |
ee69c92b | 1032 | bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 1033 | { |
b11306b5 | 1034 | if (cr4 & cr4_reserved_bits) |
ee69c92b | 1035 | return false; |
b9baba86 | 1036 | |
b899c132 | 1037 | if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) |
ee69c92b | 1038 | return false; |
3ca94192 | 1039 | |
b3646477 | 1040 | return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); |
3ca94192 | 1041 | } |
ee69c92b | 1042 | EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); |
3ca94192 | 1043 | |
5b51cb13 TL |
1044 | void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) |
1045 | { | |
20f632bd | 1046 | if (((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) || |
5b51cb13 TL |
1047 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) |
1048 | kvm_mmu_reset_context(vcpu); | |
3ca94192 | 1049 | } |
5b51cb13 | 1050 | EXPORT_SYMBOL_GPL(kvm_post_set_cr4); |
3ca94192 WL |
1051 | |
1052 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1053 | { | |
1054 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
1055 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
cb957adb | 1056 | X86_CR4_SMEP; |
3ca94192 | 1057 | |
ee69c92b | 1058 | if (!kvm_is_valid_cr4(vcpu, cr4)) |
ae3e61e1 PB |
1059 | return 1; |
1060 | ||
a03490ed | 1061 | if (is_long_mode(vcpu)) { |
0f12244f GN |
1062 | if (!(cr4 & X86_CR4_PAE)) |
1063 | return 1; | |
d74fcfc1 SC |
1064 | if ((cr4 ^ old_cr4) & X86_CR4_LA57) |
1065 | return 1; | |
a2edf57f AK |
1066 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
1067 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
1068 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
1069 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
1070 | return 1; |
1071 | ||
ad756a16 | 1072 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 1073 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
1074 | return 1; |
1075 | ||
1076 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
1077 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
1078 | return 1; | |
1079 | } | |
1080 | ||
b3646477 | 1081 | static_call(kvm_x86_set_cr4)(vcpu, cr4); |
a03490ed | 1082 | |
5b51cb13 | 1083 | kvm_post_set_cr4(vcpu, old_cr4, cr4); |
2acf923e | 1084 | |
0f12244f GN |
1085 | return 0; |
1086 | } | |
2d3ad1f4 | 1087 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 1088 | |
21823fbd SC |
1089 | static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) |
1090 | { | |
1091 | struct kvm_mmu *mmu = vcpu->arch.mmu; | |
1092 | unsigned long roots_to_free = 0; | |
1093 | int i; | |
1094 | ||
7cbc6450 LJ |
1095 | /* |
1096 | * MOV CR3 and INVPCID are usually not intercepted when using TDP, but | |
1097 | * this is reachable when running EPT=1 and unrestricted_guest=0, and | |
1098 | * also via the emulator. KVM's TDP page tables are not in the scope of | |
1099 | * the invalidation, but the guest's TLB entries need to be flushed as | |
1100 | * the CPU may have cached entries in its TLB for the target PCID. | |
1101 | */ | |
1102 | if (unlikely(tdp_enabled)) { | |
1103 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
1104 | return; | |
1105 | } | |
1106 | ||
21823fbd SC |
1107 | /* |
1108 | * If neither the current CR3 nor any of the prev_roots use the given | |
1109 | * PCID, then nothing needs to be done here because a resync will | |
1110 | * happen anyway before switching to any other CR3. | |
1111 | */ | |
1112 | if (kvm_get_active_pcid(vcpu) == pcid) { | |
e62f1aa8 | 1113 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
21823fbd SC |
1114 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
1115 | } | |
1116 | ||
1117 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
1118 | if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) | |
1119 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
1120 | ||
1121 | kvm_mmu_free_roots(vcpu, mmu, roots_to_free); | |
1122 | } | |
1123 | ||
2390218b | 1124 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 1125 | { |
ade61e28 | 1126 | bool skip_tlb_flush = false; |
21823fbd | 1127 | unsigned long pcid = 0; |
ac146235 | 1128 | #ifdef CONFIG_X86_64 |
c19986fe JS |
1129 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
1130 | ||
ade61e28 | 1131 | if (pcid_enabled) { |
208320ba JS |
1132 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
1133 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
21823fbd | 1134 | pcid = cr3 & X86_CR3_PCID_MASK; |
ade61e28 | 1135 | } |
ac146235 | 1136 | #endif |
9d88fca7 | 1137 | |
c7313155 | 1138 | /* PDPTRs are always reloaded for PAE paging. */ |
21823fbd SC |
1139 | if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) |
1140 | goto handle_tlb_flush; | |
d835dfec | 1141 | |
886bbcc7 SC |
1142 | /* |
1143 | * Do not condition the GPA check on long mode, this helper is used to | |
1144 | * stuff CR3, e.g. for RSM emulation, and there is no guarantee that | |
1145 | * the current vCPU mode is accurate. | |
1146 | */ | |
1147 | if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) | |
d1cd3ce9 | 1148 | return 1; |
886bbcc7 SC |
1149 | |
1150 | if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 1151 | return 1; |
a03490ed | 1152 | |
21823fbd | 1153 | if (cr3 != kvm_read_cr3(vcpu)) |
b5129100 | 1154 | kvm_mmu_new_pgd(vcpu, cr3); |
21823fbd | 1155 | |
0f12244f | 1156 | vcpu->arch.cr3 = cr3; |
cb3c1e2f | 1157 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
7c390d35 | 1158 | |
21823fbd SC |
1159 | handle_tlb_flush: |
1160 | /* | |
1161 | * A load of CR3 that flushes the TLB flushes only the current PCID, | |
1162 | * even if PCID is disabled, in which case PCID=0 is flushed. It's a | |
1163 | * moot point in the end because _disabling_ PCID will flush all PCIDs, | |
1164 | * and it's impossible to use a non-zero PCID when PCID is disabled, | |
1165 | * i.e. only PCID=0 can be relevant. | |
1166 | */ | |
1167 | if (!skip_tlb_flush) | |
1168 | kvm_invalidate_pcid(vcpu, pcid); | |
1169 | ||
0f12244f GN |
1170 | return 0; |
1171 | } | |
2d3ad1f4 | 1172 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1173 | |
eea1cff9 | 1174 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1175 | { |
0f12244f GN |
1176 | if (cr8 & CR8_RESERVED_BITS) |
1177 | return 1; | |
35754c98 | 1178 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1179 | kvm_lapic_set_tpr(vcpu, cr8); |
1180 | else | |
ad312c7c | 1181 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1182 | return 0; |
1183 | } | |
2d3ad1f4 | 1184 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1185 | |
2d3ad1f4 | 1186 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1187 | { |
35754c98 | 1188 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1189 | return kvm_lapic_get_cr8(vcpu); |
1190 | else | |
ad312c7c | 1191 | return vcpu->arch.cr8; |
a03490ed | 1192 | } |
2d3ad1f4 | 1193 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1194 | |
ae561ede NA |
1195 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1196 | { | |
1197 | int i; | |
1198 | ||
1199 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1200 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1201 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae561ede NA |
1202 | } |
1203 | } | |
1204 | ||
7c86663b | 1205 | void kvm_update_dr7(struct kvm_vcpu *vcpu) |
c8639010 JK |
1206 | { |
1207 | unsigned long dr7; | |
1208 | ||
1209 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1210 | dr7 = vcpu->arch.guest_debug_dr7; | |
1211 | else | |
1212 | dr7 = vcpu->arch.dr7; | |
b3646477 | 1213 | static_call(kvm_x86_set_dr7)(vcpu, dr7); |
360b948d PB |
1214 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1215 | if (dr7 & DR7_BP_EN_MASK) | |
1216 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 | 1217 | } |
7c86663b | 1218 | EXPORT_SYMBOL_GPL(kvm_update_dr7); |
c8639010 | 1219 | |
6f43ed01 NA |
1220 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1221 | { | |
1222 | u64 fixed = DR6_FIXED_1; | |
1223 | ||
d6321d49 | 1224 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 | 1225 | fixed |= DR6_RTM; |
e8ea85fb CQ |
1226 | |
1227 | if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) | |
1228 | fixed |= DR6_BUS_LOCK; | |
6f43ed01 NA |
1229 | return fixed; |
1230 | } | |
1231 | ||
996ff542 | 1232 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1233 | { |
ea740059 MP |
1234 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1235 | ||
020df079 GN |
1236 | switch (dr) { |
1237 | case 0 ... 3: | |
ea740059 | 1238 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1239 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1240 | vcpu->arch.eff_db[dr] = val; | |
1241 | break; | |
1242 | case 4: | |
020df079 | 1243 | case 6: |
f5f6145e | 1244 | if (!kvm_dr6_valid(val)) |
996ff542 | 1245 | return 1; /* #GP */ |
6f43ed01 | 1246 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
020df079 GN |
1247 | break; |
1248 | case 5: | |
020df079 | 1249 | default: /* 7 */ |
b91991bf | 1250 | if (!kvm_dr7_valid(val)) |
996ff542 | 1251 | return 1; /* #GP */ |
020df079 | 1252 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1253 | kvm_update_dr7(vcpu); |
020df079 GN |
1254 | break; |
1255 | } | |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | EXPORT_SYMBOL_GPL(kvm_set_dr); | |
1260 | ||
29d6ca41 | 1261 | void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1262 | { |
ea740059 MP |
1263 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1264 | ||
020df079 GN |
1265 | switch (dr) { |
1266 | case 0 ... 3: | |
ea740059 | 1267 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1268 | break; |
1269 | case 4: | |
020df079 | 1270 | case 6: |
5679b803 | 1271 | *val = vcpu->arch.dr6; |
020df079 GN |
1272 | break; |
1273 | case 5: | |
020df079 GN |
1274 | default: /* 7 */ |
1275 | *val = vcpu->arch.dr7; | |
1276 | break; | |
1277 | } | |
338dbc97 | 1278 | } |
020df079 GN |
1279 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1280 | ||
c483c454 | 1281 | int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) |
022cd0e8 | 1282 | { |
de3cd117 | 1283 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 | 1284 | u64 data; |
022cd0e8 | 1285 | |
c483c454 SC |
1286 | if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { |
1287 | kvm_inject_gp(vcpu, 0); | |
1288 | return 1; | |
1289 | } | |
1290 | ||
de3cd117 SC |
1291 | kvm_rax_write(vcpu, (u32)data); |
1292 | kvm_rdx_write(vcpu, data >> 32); | |
c483c454 | 1293 | return kvm_skip_emulated_instruction(vcpu); |
022cd0e8 | 1294 | } |
c483c454 | 1295 | EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); |
022cd0e8 | 1296 | |
043405e1 CO |
1297 | /* |
1298 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1299 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1300 | * | |
7a5ee6ed CQ |
1301 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) |
1302 | * extract the supported MSRs from the related const lists. | |
1303 | * msrs_to_save is selected from the msrs_to_save_all to reflect the | |
e3267cbb | 1304 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
7a5ee6ed | 1305 | * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs |
62ef68bb | 1306 | * may depend on host virtualization features rather than host cpu features. |
043405e1 | 1307 | */ |
e3267cbb | 1308 | |
7a5ee6ed | 1309 | static const u32 msrs_to_save_all[] = { |
043405e1 | 1310 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1311 | MSR_STAR, |
043405e1 CO |
1312 | #ifdef CONFIG_X86_64 |
1313 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1314 | #endif | |
b3897a49 | 1315 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1316 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1317 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1318 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1319 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1320 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1321 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1322 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1323 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1324 | MSR_IA32_UMWAIT_CONTROL, |
1325 | ||
e2ada66e | 1326 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
0f2c0f9f | 1327 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, |
e2ada66e JM |
1328 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, |
1329 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1330 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, | |
1331 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1332 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1333 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
1334 | MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, | |
1335 | MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, | |
1336 | MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, | |
1337 | MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, | |
1338 | MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, | |
e2ada66e JM |
1339 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1340 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1341 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1342 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
1343 | MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, | |
1344 | MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, | |
1345 | MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, | |
1346 | MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, | |
1347 | MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, | |
e1fc1553 FM |
1348 | |
1349 | MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, | |
1350 | MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, | |
1351 | MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, | |
1352 | MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, | |
1353 | MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, | |
1354 | MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, | |
043405e1 CO |
1355 | }; |
1356 | ||
7a5ee6ed | 1357 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; |
043405e1 CO |
1358 | static unsigned num_msrs_to_save; |
1359 | ||
7a5ee6ed | 1360 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1361 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1362 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1363 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1364 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1365 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1366 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1367 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1368 | HV_X64_MSR_RESET, |
11c4b1ca | 1369 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1370 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1371 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1372 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1373 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1374 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1375 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
f97f5a56 JD |
1376 | HV_X64_MSR_SYNDBG_OPTIONS, |
1377 | HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, | |
1378 | HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, | |
1379 | HV_X64_MSR_SYNDBG_PENDING_BUFFER, | |
a2e164e7 VK |
1380 | |
1381 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
557a961a | 1382 | MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, |
62ef68bb | 1383 | |
ba904635 | 1384 | MSR_IA32_TSC_ADJUST, |
09141ec0 | 1385 | MSR_IA32_TSC_DEADLINE, |
2bdb76c0 | 1386 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1387 | MSR_IA32_PERF_CAPABILITIES, |
043405e1 | 1388 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1389 | MSR_IA32_MCG_STATUS, |
1390 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1391 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1392 | MSR_IA32_SMBASE, |
52797bf9 | 1393 | MSR_SMI_COUNT, |
db2336a8 KH |
1394 | MSR_PLATFORM_INFO, |
1395 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1396 | MSR_AMD64_VIRT_SPEC_CTRL, |
6c6a2ab9 | 1397 | MSR_IA32_POWER_CTL, |
99634e3e | 1398 | MSR_IA32_UCODE_REV, |
191c8137 | 1399 | |
95c5c7c7 PB |
1400 | /* |
1401 | * The following list leaves out MSRs whose values are determined | |
1402 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1403 | * We always support the "true" VMX control MSRs, even if the host | |
1404 | * processor does not, so I am putting these registers here rather | |
7a5ee6ed | 1405 | * than in msrs_to_save_all. |
95c5c7c7 PB |
1406 | */ |
1407 | MSR_IA32_VMX_BASIC, | |
1408 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1409 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1410 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1411 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1412 | MSR_IA32_VMX_MISC, | |
1413 | MSR_IA32_VMX_CR0_FIXED0, | |
1414 | MSR_IA32_VMX_CR4_FIXED0, | |
1415 | MSR_IA32_VMX_VMCS_ENUM, | |
1416 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1417 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1418 | MSR_IA32_VMX_VMFUNC, | |
1419 | ||
191c8137 | 1420 | MSR_K7_HWCR, |
2d5ba19b | 1421 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1422 | }; |
1423 | ||
7a5ee6ed | 1424 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1425 | static unsigned num_emulated_msrs; |
1426 | ||
801e459a TL |
1427 | /* |
1428 | * List of msr numbers which are used to expose MSR-based features that | |
1429 | * can be used by a hypervisor to validate requested CPU features. | |
1430 | */ | |
7a5ee6ed | 1431 | static const u32 msr_based_features_all[] = { |
1389309c PB |
1432 | MSR_IA32_VMX_BASIC, |
1433 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1434 | MSR_IA32_VMX_PINBASED_CTLS, | |
1435 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1436 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1437 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1438 | MSR_IA32_VMX_EXIT_CTLS, | |
1439 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1440 | MSR_IA32_VMX_ENTRY_CTLS, | |
1441 | MSR_IA32_VMX_MISC, | |
1442 | MSR_IA32_VMX_CR0_FIXED0, | |
1443 | MSR_IA32_VMX_CR0_FIXED1, | |
1444 | MSR_IA32_VMX_CR4_FIXED0, | |
1445 | MSR_IA32_VMX_CR4_FIXED1, | |
1446 | MSR_IA32_VMX_VMCS_ENUM, | |
1447 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1448 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1449 | MSR_IA32_VMX_VMFUNC, | |
1450 | ||
d1d93fa9 | 1451 | MSR_F10H_DECFG, |
518e7b94 | 1452 | MSR_IA32_UCODE_REV, |
cd283252 | 1453 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1454 | MSR_IA32_PERF_CAPABILITIES, |
801e459a TL |
1455 | }; |
1456 | ||
7a5ee6ed | 1457 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; |
801e459a TL |
1458 | static unsigned int num_msr_based_features; |
1459 | ||
4d22c17c | 1460 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1461 | { |
4d22c17c | 1462 | u64 data = 0; |
5b76a3cf | 1463 | |
4d22c17c XL |
1464 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1465 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf | 1466 | |
b8e8c830 PB |
1467 | /* |
1468 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1469 | * the nested hypervisor runs with NX huge pages. If it is not, | |
d9f6e12f | 1470 | * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other |
b8e8c830 PB |
1471 | * L1 guests, so it need not worry about its own (L2) guests. |
1472 | */ | |
1473 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1474 | ||
5b76a3cf PB |
1475 | /* |
1476 | * If we're doing cache flushes (either "always" or "cond") | |
1477 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1478 | * If an outer hypervisor is doing the cache flush for us | |
1479 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1480 | * capability to the guest too, and if EPT is disabled we're not | |
1481 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1482 | * require a nested hypervisor to do a flush of its own. | |
1483 | */ | |
1484 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1485 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1486 | ||
0c54914d PB |
1487 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1488 | data |= ARCH_CAP_RDCL_NO; | |
1489 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1490 | data |= ARCH_CAP_SSB_NO; | |
1491 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1492 | data |= ARCH_CAP_MDS_NO; | |
1493 | ||
7131636e PB |
1494 | if (!boot_cpu_has(X86_FEATURE_RTM)) { |
1495 | /* | |
1496 | * If RTM=0 because the kernel has disabled TSX, the host might | |
1497 | * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 | |
1498 | * and therefore knows that there cannot be TAA) but keep | |
1499 | * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, | |
1500 | * and we want to allow migrating those guests to tsx=off hosts. | |
1501 | */ | |
1502 | data &= ~ARCH_CAP_TAA_NO; | |
1503 | } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { | |
cbbaa272 | 1504 | data |= ARCH_CAP_TAA_NO; |
7131636e PB |
1505 | } else { |
1506 | /* | |
1507 | * Nothing to do here; we emulate TSX_CTRL if present on the | |
1508 | * host so the guest can choose between disabling TSX or | |
1509 | * using VERW to clear CPU buffers. | |
1510 | */ | |
1511 | } | |
e1d38b63 | 1512 | |
5b76a3cf PB |
1513 | return data; |
1514 | } | |
5b76a3cf | 1515 | |
66421c1e WL |
1516 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1517 | { | |
1518 | switch (msr->index) { | |
cd283252 | 1519 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1520 | msr->data = kvm_get_arch_capabilities(); |
1521 | break; | |
1522 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1523 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1524 | break; |
66421c1e | 1525 | default: |
b3646477 | 1526 | return static_call(kvm_x86_get_msr_feature)(msr); |
66421c1e WL |
1527 | } |
1528 | return 0; | |
1529 | } | |
1530 | ||
801e459a TL |
1531 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1532 | { | |
1533 | struct kvm_msr_entry msr; | |
66421c1e | 1534 | int r; |
801e459a TL |
1535 | |
1536 | msr.index = index; | |
66421c1e | 1537 | r = kvm_get_msr_feature(&msr); |
12bc2132 PX |
1538 | |
1539 | if (r == KVM_MSR_RET_INVALID) { | |
1540 | /* Unconditionally clear the output for simplicity */ | |
1541 | *data = 0; | |
d632826f | 1542 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1543 | r = 0; |
12bc2132 PX |
1544 | } |
1545 | ||
66421c1e WL |
1546 | if (r) |
1547 | return r; | |
801e459a TL |
1548 | |
1549 | *data = msr.data; | |
1550 | ||
1551 | return 0; | |
1552 | } | |
1553 | ||
11988499 | 1554 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1555 | { |
1b4d56b8 | 1556 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1557 | return false; |
1b2fd70c | 1558 | |
1b4d56b8 | 1559 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1560 | return false; |
d8017474 | 1561 | |
0a629563 SC |
1562 | if (efer & (EFER_LME | EFER_LMA) && |
1563 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1564 | return false; | |
1565 | ||
1566 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1567 | return false; | |
d8017474 | 1568 | |
384bb783 | 1569 | return true; |
11988499 SC |
1570 | |
1571 | } | |
1572 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1573 | { | |
1574 | if (efer & efer_reserved_bits) | |
1575 | return false; | |
1576 | ||
1577 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1578 | } |
1579 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1580 | ||
11988499 | 1581 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1582 | { |
1583 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1584 | u64 efer = msr_info->data; |
72f211ec | 1585 | int r; |
384bb783 | 1586 | |
11988499 | 1587 | if (efer & efer_reserved_bits) |
66f61c92 | 1588 | return 1; |
384bb783 | 1589 | |
11988499 SC |
1590 | if (!msr_info->host_initiated) { |
1591 | if (!__kvm_valid_efer(vcpu, efer)) | |
1592 | return 1; | |
1593 | ||
1594 | if (is_paging(vcpu) && | |
1595 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1596 | return 1; | |
1597 | } | |
384bb783 | 1598 | |
15c4a640 | 1599 | efer &= ~EFER_LMA; |
f6801dff | 1600 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1601 | |
b3646477 | 1602 | r = static_call(kvm_x86_set_efer)(vcpu, efer); |
72f211ec ML |
1603 | if (r) { |
1604 | WARN_ON(r > 0); | |
1605 | return r; | |
1606 | } | |
a3d204e2 | 1607 | |
aad82703 SY |
1608 | /* Update reserved bits */ |
1609 | if ((efer ^ old_efer) & EFER_NX) | |
1610 | kvm_mmu_reset_context(vcpu); | |
1611 | ||
b69e8cae | 1612 | return 0; |
15c4a640 CO |
1613 | } |
1614 | ||
f2b4b7dd JR |
1615 | void kvm_enable_efer_bits(u64 mask) |
1616 | { | |
1617 | efer_reserved_bits &= ~mask; | |
1618 | } | |
1619 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1620 | ||
51de8151 AG |
1621 | bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) |
1622 | { | |
b318e8de SC |
1623 | struct kvm_x86_msr_filter *msr_filter; |
1624 | struct msr_bitmap_range *ranges; | |
1a155254 | 1625 | struct kvm *kvm = vcpu->kvm; |
b318e8de | 1626 | bool allowed; |
1a155254 | 1627 | int idx; |
b318e8de | 1628 | u32 i; |
1a155254 | 1629 | |
b318e8de SC |
1630 | /* x2APIC MSRs do not support filtering. */ |
1631 | if (index >= 0x800 && index <= 0x8ff) | |
1a155254 AG |
1632 | return true; |
1633 | ||
1a155254 AG |
1634 | idx = srcu_read_lock(&kvm->srcu); |
1635 | ||
b318e8de SC |
1636 | msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); |
1637 | if (!msr_filter) { | |
1638 | allowed = true; | |
1639 | goto out; | |
1640 | } | |
1641 | ||
1642 | allowed = msr_filter->default_allow; | |
1643 | ranges = msr_filter->ranges; | |
1644 | ||
1645 | for (i = 0; i < msr_filter->count; i++) { | |
1a155254 AG |
1646 | u32 start = ranges[i].base; |
1647 | u32 end = start + ranges[i].nmsrs; | |
1648 | u32 flags = ranges[i].flags; | |
1649 | unsigned long *bitmap = ranges[i].bitmap; | |
1650 | ||
1651 | if ((index >= start) && (index < end) && (flags & type)) { | |
b318e8de | 1652 | allowed = !!test_bit(index - start, bitmap); |
1a155254 AG |
1653 | break; |
1654 | } | |
1655 | } | |
1656 | ||
b318e8de | 1657 | out: |
1a155254 AG |
1658 | srcu_read_unlock(&kvm->srcu, idx); |
1659 | ||
b318e8de | 1660 | return allowed; |
51de8151 AG |
1661 | } |
1662 | EXPORT_SYMBOL_GPL(kvm_msr_allowed); | |
1663 | ||
15c4a640 | 1664 | /* |
f20935d8 SC |
1665 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1666 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1667 | * Returns 0 on success, non-0 otherwise. |
1668 | * Assumes vcpu_load() was already called. | |
1669 | */ | |
f20935d8 SC |
1670 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1671 | bool host_initiated) | |
15c4a640 | 1672 | { |
f20935d8 SC |
1673 | struct msr_data msr; |
1674 | ||
1a155254 | 1675 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) |
cc4cb017 | 1676 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1677 | |
f20935d8 | 1678 | switch (index) { |
854e8bb1 NA |
1679 | case MSR_FS_BASE: |
1680 | case MSR_GS_BASE: | |
1681 | case MSR_KERNEL_GS_BASE: | |
1682 | case MSR_CSTAR: | |
1683 | case MSR_LSTAR: | |
f20935d8 | 1684 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1685 | return 1; |
1686 | break; | |
1687 | case MSR_IA32_SYSENTER_EIP: | |
1688 | case MSR_IA32_SYSENTER_ESP: | |
1689 | /* | |
1690 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1691 | * non-canonical address is written on Intel but not on | |
1692 | * AMD (which ignores the top 32-bits, because it does | |
1693 | * not implement 64-bit SYSENTER). | |
1694 | * | |
1695 | * 64-bit code should hence be able to write a non-canonical | |
1696 | * value on AMD. Making the address canonical ensures that | |
1697 | * vmentry does not fail on Intel after writing a non-canonical | |
1698 | * value, and that something deterministic happens if the guest | |
1699 | * invokes 64-bit SYSENTER. | |
1700 | */ | |
f20935d8 | 1701 | data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); |
61a05d44 SC |
1702 | break; |
1703 | case MSR_TSC_AUX: | |
1704 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1705 | return 1; | |
1706 | ||
1707 | if (!host_initiated && | |
1708 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1709 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1710 | return 1; | |
1711 | ||
1712 | /* | |
1713 | * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has | |
1714 | * incomplete and conflicting architectural behavior. Current | |
1715 | * AMD CPUs completely ignore bits 63:32, i.e. they aren't | |
1716 | * reserved and always read as zeros. Enforce Intel's reserved | |
1717 | * bits check if and only if the guest CPU is Intel, and clear | |
1718 | * the bits in all other cases. This ensures cross-vendor | |
1719 | * migration will provide consistent behavior for the guest. | |
1720 | */ | |
1721 | if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) | |
1722 | return 1; | |
1723 | ||
1724 | data = (u32)data; | |
1725 | break; | |
854e8bb1 | 1726 | } |
f20935d8 SC |
1727 | |
1728 | msr.data = data; | |
1729 | msr.index = index; | |
1730 | msr.host_initiated = host_initiated; | |
1731 | ||
b3646477 | 1732 | return static_call(kvm_x86_set_msr)(vcpu, &msr); |
15c4a640 CO |
1733 | } |
1734 | ||
6abe9c13 PX |
1735 | static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, |
1736 | u32 index, u64 data, bool host_initiated) | |
1737 | { | |
1738 | int ret = __kvm_set_msr(vcpu, index, data, host_initiated); | |
1739 | ||
1740 | if (ret == KVM_MSR_RET_INVALID) | |
d632826f | 1741 | if (kvm_msr_ignored_check(index, data, true)) |
cc4cb017 | 1742 | ret = 0; |
6abe9c13 PX |
1743 | |
1744 | return ret; | |
1745 | } | |
1746 | ||
313a3dc7 | 1747 | /* |
f20935d8 SC |
1748 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1749 | * checks are bypassed if @host_initiated is %true. | |
1750 | * Returns 0 on success, non-0 otherwise. | |
1751 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1752 | */ |
edef5c36 PB |
1753 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1754 | bool host_initiated) | |
609e36d3 PB |
1755 | { |
1756 | struct msr_data msr; | |
f20935d8 | 1757 | int ret; |
609e36d3 | 1758 | |
1a155254 | 1759 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) |
cc4cb017 | 1760 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1761 | |
61a05d44 SC |
1762 | switch (index) { |
1763 | case MSR_TSC_AUX: | |
1764 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1765 | return 1; | |
1766 | ||
1767 | if (!host_initiated && | |
1768 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1769 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1770 | return 1; | |
1771 | break; | |
1772 | } | |
1773 | ||
609e36d3 | 1774 | msr.index = index; |
f20935d8 | 1775 | msr.host_initiated = host_initiated; |
609e36d3 | 1776 | |
b3646477 | 1777 | ret = static_call(kvm_x86_get_msr)(vcpu, &msr); |
f20935d8 SC |
1778 | if (!ret) |
1779 | *data = msr.data; | |
1780 | return ret; | |
609e36d3 PB |
1781 | } |
1782 | ||
6abe9c13 PX |
1783 | static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, |
1784 | u32 index, u64 *data, bool host_initiated) | |
1785 | { | |
1786 | int ret = __kvm_get_msr(vcpu, index, data, host_initiated); | |
1787 | ||
1788 | if (ret == KVM_MSR_RET_INVALID) { | |
1789 | /* Unconditionally clear *data for simplicity */ | |
1790 | *data = 0; | |
d632826f | 1791 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1792 | ret = 0; |
6abe9c13 PX |
1793 | } |
1794 | ||
1795 | return ret; | |
1796 | } | |
1797 | ||
f20935d8 | 1798 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1799 | { |
6abe9c13 | 1800 | return kvm_get_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1801 | } |
1802 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1803 | |
f20935d8 SC |
1804 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1805 | { | |
6abe9c13 | 1806 | return kvm_set_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1807 | } |
1808 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1809 | ||
8b474427 | 1810 | static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) |
1ae09954 | 1811 | { |
8b474427 PB |
1812 | int err = vcpu->run->msr.error; |
1813 | if (!err) { | |
1ae09954 AG |
1814 | kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); |
1815 | kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); | |
1816 | } | |
1817 | ||
b3646477 | 1818 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, err); |
1ae09954 AG |
1819 | } |
1820 | ||
1821 | static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) | |
1822 | { | |
b3646477 | 1823 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); |
1ae09954 AG |
1824 | } |
1825 | ||
1826 | static u64 kvm_msr_reason(int r) | |
1827 | { | |
1828 | switch (r) { | |
cc4cb017 | 1829 | case KVM_MSR_RET_INVALID: |
1ae09954 | 1830 | return KVM_MSR_EXIT_REASON_UNKNOWN; |
cc4cb017 | 1831 | case KVM_MSR_RET_FILTERED: |
1a155254 | 1832 | return KVM_MSR_EXIT_REASON_FILTER; |
1ae09954 AG |
1833 | default: |
1834 | return KVM_MSR_EXIT_REASON_INVAL; | |
1835 | } | |
1836 | } | |
1837 | ||
1838 | static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, | |
1839 | u32 exit_reason, u64 data, | |
1840 | int (*completion)(struct kvm_vcpu *vcpu), | |
1841 | int r) | |
1842 | { | |
1843 | u64 msr_reason = kvm_msr_reason(r); | |
1844 | ||
1845 | /* Check if the user wanted to know about this MSR fault */ | |
1846 | if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) | |
1847 | return 0; | |
1848 | ||
1849 | vcpu->run->exit_reason = exit_reason; | |
1850 | vcpu->run->msr.error = 0; | |
1851 | memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); | |
1852 | vcpu->run->msr.reason = msr_reason; | |
1853 | vcpu->run->msr.index = index; | |
1854 | vcpu->run->msr.data = data; | |
1855 | vcpu->arch.complete_userspace_io = completion; | |
1856 | ||
1857 | return 1; | |
1858 | } | |
1859 | ||
1860 | static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) | |
1861 | { | |
1862 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, | |
1863 | complete_emulated_rdmsr, r); | |
1864 | } | |
1865 | ||
1866 | static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) | |
1867 | { | |
1868 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, | |
1869 | complete_emulated_wrmsr, r); | |
1870 | } | |
1871 | ||
1edce0a9 SC |
1872 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
1873 | { | |
1874 | u32 ecx = kvm_rcx_read(vcpu); | |
1875 | u64 data; | |
1ae09954 AG |
1876 | int r; |
1877 | ||
1878 | r = kvm_get_msr(vcpu, ecx, &data); | |
1edce0a9 | 1879 | |
1ae09954 AG |
1880 | /* MSR read failed? See if we should ask user space */ |
1881 | if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { | |
1882 | /* Bounce to user space */ | |
1883 | return 0; | |
1884 | } | |
1885 | ||
8b474427 PB |
1886 | if (!r) { |
1887 | trace_kvm_msr_read(ecx, data); | |
1888 | ||
1889 | kvm_rax_write(vcpu, data & -1u); | |
1890 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
1891 | } else { | |
1edce0a9 | 1892 | trace_kvm_msr_read_ex(ecx); |
1edce0a9 SC |
1893 | } |
1894 | ||
b3646477 | 1895 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
1896 | } |
1897 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
1898 | ||
1899 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
1900 | { | |
1901 | u32 ecx = kvm_rcx_read(vcpu); | |
1902 | u64 data = kvm_read_edx_eax(vcpu); | |
1ae09954 | 1903 | int r; |
1edce0a9 | 1904 | |
1ae09954 AG |
1905 | r = kvm_set_msr(vcpu, ecx, data); |
1906 | ||
1907 | /* MSR write failed? See if we should ask user space */ | |
7dffecaf | 1908 | if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) |
1ae09954 AG |
1909 | /* Bounce to user space */ |
1910 | return 0; | |
7dffecaf ML |
1911 | |
1912 | /* Signal all other negative errors to userspace */ | |
1913 | if (r < 0) | |
1914 | return r; | |
1ae09954 | 1915 | |
8b474427 PB |
1916 | if (!r) |
1917 | trace_kvm_msr_write(ecx, data); | |
1918 | else | |
1edce0a9 | 1919 | trace_kvm_msr_write_ex(ecx, data); |
1edce0a9 | 1920 | |
b3646477 | 1921 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
1922 | } |
1923 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
1924 | ||
5ff3a351 SC |
1925 | int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) |
1926 | { | |
1927 | return kvm_skip_emulated_instruction(vcpu); | |
1928 | } | |
1929 | EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); | |
1930 | ||
1931 | int kvm_emulate_invd(struct kvm_vcpu *vcpu) | |
1932 | { | |
1933 | /* Treat an INVD instruction as a NOP and just skip it. */ | |
1934 | return kvm_emulate_as_nop(vcpu); | |
1935 | } | |
1936 | EXPORT_SYMBOL_GPL(kvm_emulate_invd); | |
1937 | ||
1938 | int kvm_emulate_mwait(struct kvm_vcpu *vcpu) | |
1939 | { | |
1940 | pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); | |
1941 | return kvm_emulate_as_nop(vcpu); | |
1942 | } | |
1943 | EXPORT_SYMBOL_GPL(kvm_emulate_mwait); | |
1944 | ||
1945 | int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) | |
1946 | { | |
1947 | kvm_queue_exception(vcpu, UD_VECTOR); | |
1948 | return 1; | |
1949 | } | |
1950 | EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); | |
1951 | ||
1952 | int kvm_emulate_monitor(struct kvm_vcpu *vcpu) | |
1953 | { | |
1954 | pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); | |
1955 | return kvm_emulate_as_nop(vcpu); | |
1956 | } | |
1957 | EXPORT_SYMBOL_GPL(kvm_emulate_monitor); | |
1958 | ||
d89d04ab | 1959 | static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) |
5a9f5443 | 1960 | { |
4ae7dc97 | 1961 | xfer_to_guest_mode_prepare(); |
5a9f5443 | 1962 | return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || |
72c3c0fe | 1963 | xfer_to_guest_mode_work_pending(); |
5a9f5443 | 1964 | } |
5a9f5443 | 1965 | |
1e9e2622 WL |
1966 | /* |
1967 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
1968 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
1969 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
1970 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
1971 | * other cases which must be called after interrupts are enabled on the host. | |
1972 | */ | |
1973 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
1974 | { | |
e1be9ac8 WL |
1975 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) |
1976 | return 1; | |
1977 | ||
1978 | if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && | |
1e9e2622 | 1979 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && |
4064a4c6 WL |
1980 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && |
1981 | ((u32)(data >> 32) != X2APIC_BROADCAST)) { | |
1e9e2622 | 1982 | |
d5361678 WL |
1983 | data &= ~(1 << 12); |
1984 | kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); | |
1e9e2622 | 1985 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); |
d5361678 WL |
1986 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); |
1987 | trace_kvm_apic_write(APIC_ICR, (u32)data); | |
1988 | return 0; | |
1e9e2622 WL |
1989 | } |
1990 | ||
1991 | return 1; | |
1992 | } | |
1993 | ||
ae95f566 WL |
1994 | static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) |
1995 | { | |
1996 | if (!kvm_can_use_hv_timer(vcpu)) | |
1997 | return 1; | |
1998 | ||
1999 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2000 | return 0; | |
2001 | } | |
2002 | ||
404d5d7b | 2003 | fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) |
1e9e2622 WL |
2004 | { |
2005 | u32 msr = kvm_rcx_read(vcpu); | |
8a1038de | 2006 | u64 data; |
404d5d7b | 2007 | fastpath_t ret = EXIT_FASTPATH_NONE; |
1e9e2622 WL |
2008 | |
2009 | switch (msr) { | |
2010 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
8a1038de | 2011 | data = kvm_read_edx_eax(vcpu); |
404d5d7b WL |
2012 | if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { |
2013 | kvm_skip_emulated_instruction(vcpu); | |
2014 | ret = EXIT_FASTPATH_EXIT_HANDLED; | |
80bc97f2 | 2015 | } |
1e9e2622 | 2016 | break; |
09141ec0 | 2017 | case MSR_IA32_TSC_DEADLINE: |
ae95f566 WL |
2018 | data = kvm_read_edx_eax(vcpu); |
2019 | if (!handle_fastpath_set_tscdeadline(vcpu, data)) { | |
2020 | kvm_skip_emulated_instruction(vcpu); | |
2021 | ret = EXIT_FASTPATH_REENTER_GUEST; | |
2022 | } | |
2023 | break; | |
1e9e2622 | 2024 | default: |
404d5d7b | 2025 | break; |
1e9e2622 WL |
2026 | } |
2027 | ||
404d5d7b | 2028 | if (ret != EXIT_FASTPATH_NONE) |
1e9e2622 | 2029 | trace_kvm_msr_write(msr, data); |
1e9e2622 | 2030 | |
404d5d7b | 2031 | return ret; |
1e9e2622 WL |
2032 | } |
2033 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
2034 | ||
f20935d8 SC |
2035 | /* |
2036 | * Adapt set_msr() to msr_io()'s calling convention | |
2037 | */ | |
2038 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
2039 | { | |
6abe9c13 | 2040 | return kvm_get_msr_ignored_check(vcpu, index, data, true); |
f20935d8 SC |
2041 | } |
2042 | ||
2043 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
2044 | { | |
6abe9c13 | 2045 | return kvm_set_msr_ignored_check(vcpu, index, *data, true); |
313a3dc7 CO |
2046 | } |
2047 | ||
16e8d74d | 2048 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
2049 | struct pvclock_clock { |
2050 | int vclock_mode; | |
2051 | u64 cycle_last; | |
2052 | u64 mask; | |
2053 | u32 mult; | |
2054 | u32 shift; | |
917f9475 PB |
2055 | u64 base_cycles; |
2056 | u64 offset; | |
53fafdbb MT |
2057 | }; |
2058 | ||
16e8d74d MT |
2059 | struct pvclock_gtod_data { |
2060 | seqcount_t seq; | |
2061 | ||
53fafdbb MT |
2062 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
2063 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 2064 | |
917f9475 | 2065 | ktime_t offs_boot; |
55dd00a7 | 2066 | u64 wall_time_sec; |
16e8d74d MT |
2067 | }; |
2068 | ||
2069 | static struct pvclock_gtod_data pvclock_gtod_data; | |
2070 | ||
2071 | static void update_pvclock_gtod(struct timekeeper *tk) | |
2072 | { | |
2073 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
2074 | ||
2075 | write_seqcount_begin(&vdata->seq); | |
2076 | ||
2077 | /* copy pvclock gtod data */ | |
b95a8a27 | 2078 | vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; |
876e7881 PZ |
2079 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; |
2080 | vdata->clock.mask = tk->tkr_mono.mask; | |
2081 | vdata->clock.mult = tk->tkr_mono.mult; | |
2082 | vdata->clock.shift = tk->tkr_mono.shift; | |
917f9475 PB |
2083 | vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; |
2084 | vdata->clock.offset = tk->tkr_mono.base; | |
16e8d74d | 2085 | |
b95a8a27 | 2086 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; |
53fafdbb MT |
2087 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; |
2088 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
2089 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
2090 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
917f9475 PB |
2091 | vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; |
2092 | vdata->raw_clock.offset = tk->tkr_raw.base; | |
16e8d74d | 2093 | |
55dd00a7 MT |
2094 | vdata->wall_time_sec = tk->xtime_sec; |
2095 | ||
917f9475 | 2096 | vdata->offs_boot = tk->offs_boot; |
53fafdbb | 2097 | |
16e8d74d MT |
2098 | write_seqcount_end(&vdata->seq); |
2099 | } | |
8171cd68 PB |
2100 | |
2101 | static s64 get_kvmclock_base_ns(void) | |
2102 | { | |
2103 | /* Count up from boot time, but with the frequency of the raw clock. */ | |
2104 | return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); | |
2105 | } | |
2106 | #else | |
2107 | static s64 get_kvmclock_base_ns(void) | |
2108 | { | |
2109 | /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ | |
2110 | return ktime_get_boottime_ns(); | |
2111 | } | |
16e8d74d MT |
2112 | #endif |
2113 | ||
629b5348 | 2114 | void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) |
18068523 | 2115 | { |
9ed3c444 AK |
2116 | int version; |
2117 | int r; | |
50d0a0f9 | 2118 | struct pvclock_wall_clock wc; |
629b5348 | 2119 | u32 wc_sec_hi; |
8171cd68 | 2120 | u64 wall_nsec; |
18068523 GOC |
2121 | |
2122 | if (!wall_clock) | |
2123 | return; | |
2124 | ||
9ed3c444 AK |
2125 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
2126 | if (r) | |
2127 | return; | |
2128 | ||
2129 | if (version & 1) | |
2130 | ++version; /* first time write, random junk */ | |
2131 | ||
2132 | ++version; | |
18068523 | 2133 | |
1dab1345 NK |
2134 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
2135 | return; | |
18068523 | 2136 | |
50d0a0f9 GH |
2137 | /* |
2138 | * The guest calculates current wall clock time by adding | |
34c238a1 | 2139 | * system time (updated by kvm_guest_time_update below) to the |
8171cd68 | 2140 | * wall clock specified here. We do the reverse here. |
50d0a0f9 | 2141 | */ |
8171cd68 | 2142 | wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); |
50d0a0f9 | 2143 | |
8171cd68 PB |
2144 | wc.nsec = do_div(wall_nsec, 1000000000); |
2145 | wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ | |
50d0a0f9 | 2146 | wc.version = version; |
18068523 GOC |
2147 | |
2148 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
2149 | ||
629b5348 JM |
2150 | if (sec_hi_ofs) { |
2151 | wc_sec_hi = wall_nsec >> 32; | |
2152 | kvm_write_guest(kvm, wall_clock + sec_hi_ofs, | |
2153 | &wc_sec_hi, sizeof(wc_sec_hi)); | |
2154 | } | |
2155 | ||
18068523 GOC |
2156 | version++; |
2157 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
2158 | } |
2159 | ||
5b9bb0eb OU |
2160 | static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, |
2161 | bool old_msr, bool host_initiated) | |
2162 | { | |
2163 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
2164 | ||
2165 | if (vcpu->vcpu_id == 0 && !host_initiated) { | |
1e293d1a | 2166 | if (ka->boot_vcpu_runs_old_kvmclock != old_msr) |
5b9bb0eb OU |
2167 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2168 | ||
2169 | ka->boot_vcpu_runs_old_kvmclock = old_msr; | |
2170 | } | |
2171 | ||
2172 | vcpu->arch.time = system_time; | |
2173 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
2174 | ||
2175 | /* we verify if the enable bit is set... */ | |
2176 | vcpu->arch.pv_time_enabled = false; | |
2177 | if (!(system_time & 1)) | |
2178 | return; | |
2179 | ||
2180 | if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
2181 | &vcpu->arch.pv_time, system_time & ~1ULL, | |
2182 | sizeof(struct pvclock_vcpu_time_info))) | |
2183 | vcpu->arch.pv_time_enabled = true; | |
2184 | ||
2185 | return; | |
2186 | } | |
2187 | ||
50d0a0f9 GH |
2188 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
2189 | { | |
b51012de PB |
2190 | do_shl32_div32(dividend, divisor); |
2191 | return dividend; | |
50d0a0f9 GH |
2192 | } |
2193 | ||
3ae13faa | 2194 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 2195 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 2196 | { |
5f4e3f88 | 2197 | uint64_t scaled64; |
50d0a0f9 GH |
2198 | int32_t shift = 0; |
2199 | uint64_t tps64; | |
2200 | uint32_t tps32; | |
2201 | ||
3ae13faa PB |
2202 | tps64 = base_hz; |
2203 | scaled64 = scaled_hz; | |
50933623 | 2204 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
2205 | tps64 >>= 1; |
2206 | shift--; | |
2207 | } | |
2208 | ||
2209 | tps32 = (uint32_t)tps64; | |
50933623 JK |
2210 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
2211 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
2212 | scaled64 >>= 1; |
2213 | else | |
2214 | tps32 <<= 1; | |
50d0a0f9 GH |
2215 | shift++; |
2216 | } | |
2217 | ||
5f4e3f88 ZA |
2218 | *pshift = shift; |
2219 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
2220 | } |
2221 | ||
d828199e | 2222 | #ifdef CONFIG_X86_64 |
16e8d74d | 2223 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 2224 | #endif |
16e8d74d | 2225 | |
c8076604 | 2226 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 2227 | static unsigned long max_tsc_khz; |
c8076604 | 2228 | |
cc578287 | 2229 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 2230 | { |
cc578287 ZA |
2231 | u64 v = (u64)khz * (1000000 + ppm); |
2232 | do_div(v, 1000000); | |
2233 | return v; | |
1e993611 JR |
2234 | } |
2235 | ||
1ab9287a IS |
2236 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); |
2237 | ||
381d585c HZ |
2238 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
2239 | { | |
2240 | u64 ratio; | |
2241 | ||
2242 | /* Guest TSC same frequency as host TSC? */ | |
2243 | if (!scale) { | |
1ab9287a | 2244 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); |
381d585c HZ |
2245 | return 0; |
2246 | } | |
2247 | ||
2248 | /* TSC scaling supported? */ | |
2249 | if (!kvm_has_tsc_control) { | |
2250 | if (user_tsc_khz > tsc_khz) { | |
2251 | vcpu->arch.tsc_catchup = 1; | |
2252 | vcpu->arch.tsc_always_catchup = 1; | |
2253 | return 0; | |
2254 | } else { | |
3f16a5c3 | 2255 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
2256 | return -1; |
2257 | } | |
2258 | } | |
2259 | ||
2260 | /* TSC scaling required - calculate ratio */ | |
2261 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
2262 | user_tsc_khz, tsc_khz); | |
2263 | ||
2264 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
3f16a5c3 PB |
2265 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
2266 | user_tsc_khz); | |
381d585c HZ |
2267 | return -1; |
2268 | } | |
2269 | ||
1ab9287a | 2270 | kvm_vcpu_write_tsc_multiplier(vcpu, ratio); |
381d585c HZ |
2271 | return 0; |
2272 | } | |
2273 | ||
4941b8cb | 2274 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 2275 | { |
cc578287 ZA |
2276 | u32 thresh_lo, thresh_hi; |
2277 | int use_scaling = 0; | |
217fc9cf | 2278 | |
03ba32ca | 2279 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 2280 | if (user_tsc_khz == 0) { |
ad721883 | 2281 | /* set tsc_scaling_ratio to a safe value */ |
1ab9287a | 2282 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); |
381d585c | 2283 | return -1; |
ad721883 | 2284 | } |
03ba32ca | 2285 | |
c285545f | 2286 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 2287 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
2288 | &vcpu->arch.virtual_tsc_shift, |
2289 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 2290 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
2291 | |
2292 | /* | |
2293 | * Compute the variation in TSC rate which is acceptable | |
2294 | * within the range of tolerance and decide if the | |
2295 | * rate being applied is within that bounds of the hardware | |
2296 | * rate. If so, no scaling or compensation need be done. | |
2297 | */ | |
2298 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
2299 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
2300 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
2301 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
2302 | use_scaling = 1; |
2303 | } | |
4941b8cb | 2304 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
2305 | } |
2306 | ||
2307 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
2308 | { | |
e26101b1 | 2309 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
2310 | vcpu->arch.virtual_tsc_mult, |
2311 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 2312 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
2313 | return tsc; |
2314 | } | |
2315 | ||
b0c39dc6 VK |
2316 | static inline int gtod_is_based_on_tsc(int mode) |
2317 | { | |
b95a8a27 | 2318 | return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; |
b0c39dc6 VK |
2319 | } |
2320 | ||
69b0049a | 2321 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
2322 | { |
2323 | #ifdef CONFIG_X86_64 | |
2324 | bool vcpus_matched; | |
b48aa97e MT |
2325 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2326 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2327 | ||
2328 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2329 | atomic_read(&vcpu->kvm->online_vcpus)); | |
2330 | ||
7f187922 MT |
2331 | /* |
2332 | * Once the masterclock is enabled, always perform request in | |
2333 | * order to update it. | |
2334 | * | |
2335 | * In order to enable masterclock, the host clocksource must be TSC | |
2336 | * and the vcpus need to have matched TSCs. When that happens, | |
2337 | * perform request to enable masterclock. | |
2338 | */ | |
2339 | if (ka->use_master_clock || | |
b0c39dc6 | 2340 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
2341 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2342 | ||
2343 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
2344 | atomic_read(&vcpu->kvm->online_vcpus), | |
2345 | ka->use_master_clock, gtod->clock.vclock_mode); | |
2346 | #endif | |
2347 | } | |
2348 | ||
35181e86 HZ |
2349 | /* |
2350 | * Multiply tsc by a fixed point number represented by ratio. | |
2351 | * | |
2352 | * The most significant 64-N bits (mult) of ratio represent the | |
2353 | * integral part of the fixed point number; the remaining N bits | |
2354 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
2355 | * point number (mult + frac * 2^(-N)). | |
2356 | * | |
2357 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
2358 | */ | |
2359 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
2360 | { | |
2361 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
2362 | } | |
2363 | ||
fe3eb504 | 2364 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc, u64 ratio) |
35181e86 HZ |
2365 | { |
2366 | u64 _tsc = tsc; | |
35181e86 HZ |
2367 | |
2368 | if (ratio != kvm_default_tsc_scaling_ratio) | |
2369 | _tsc = __scale_tsc(ratio, tsc); | |
2370 | ||
2371 | return _tsc; | |
2372 | } | |
2373 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
2374 | ||
9b399dfd | 2375 | static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
07c1419a HZ |
2376 | { |
2377 | u64 tsc; | |
2378 | ||
fe3eb504 | 2379 | tsc = kvm_scale_tsc(vcpu, rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); |
07c1419a HZ |
2380 | |
2381 | return target_tsc - tsc; | |
2382 | } | |
2383 | ||
4ba76538 HZ |
2384 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
2385 | { | |
fe3eb504 IS |
2386 | return vcpu->arch.l1_tsc_offset + |
2387 | kvm_scale_tsc(vcpu, host_tsc, vcpu->arch.l1_tsc_scaling_ratio); | |
4ba76538 HZ |
2388 | } |
2389 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
2390 | ||
83150f29 IS |
2391 | u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) |
2392 | { | |
2393 | u64 nested_offset; | |
2394 | ||
2395 | if (l2_multiplier == kvm_default_tsc_scaling_ratio) | |
2396 | nested_offset = l1_offset; | |
2397 | else | |
2398 | nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, | |
2399 | kvm_tsc_scaling_ratio_frac_bits); | |
2400 | ||
2401 | nested_offset += l2_offset; | |
2402 | return nested_offset; | |
2403 | } | |
2404 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); | |
2405 | ||
2406 | u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) | |
2407 | { | |
2408 | if (l2_multiplier != kvm_default_tsc_scaling_ratio) | |
2409 | return mul_u64_u64_shr(l1_multiplier, l2_multiplier, | |
2410 | kvm_tsc_scaling_ratio_frac_bits); | |
2411 | ||
2412 | return l1_multiplier; | |
2413 | } | |
2414 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); | |
2415 | ||
edcfe540 | 2416 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) |
a545ab6a | 2417 | { |
edcfe540 IS |
2418 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2419 | vcpu->arch.l1_tsc_offset, | |
2420 | l1_offset); | |
2421 | ||
2422 | vcpu->arch.l1_tsc_offset = l1_offset; | |
2423 | ||
2424 | /* | |
2425 | * If we are here because L1 chose not to trap WRMSR to TSC then | |
2426 | * according to the spec this should set L1's TSC (as opposed to | |
2427 | * setting L1's offset for L2). | |
2428 | */ | |
2429 | if (is_guest_mode(vcpu)) | |
2430 | vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( | |
2431 | l1_offset, | |
2432 | static_call(kvm_x86_get_l2_tsc_offset)(vcpu), | |
2433 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2434 | else | |
2435 | vcpu->arch.tsc_offset = l1_offset; | |
2436 | ||
2437 | static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); | |
a545ab6a LC |
2438 | } |
2439 | ||
1ab9287a IS |
2440 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) |
2441 | { | |
2442 | vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; | |
2443 | ||
2444 | /* Userspace is changing the multiplier while L2 is active */ | |
2445 | if (is_guest_mode(vcpu)) | |
2446 | vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( | |
2447 | l1_multiplier, | |
2448 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2449 | else | |
2450 | vcpu->arch.tsc_scaling_ratio = l1_multiplier; | |
2451 | ||
2452 | if (kvm_has_tsc_control) | |
2453 | static_call(kvm_x86_write_tsc_multiplier)( | |
2454 | vcpu, vcpu->arch.tsc_scaling_ratio); | |
2455 | } | |
2456 | ||
b0c39dc6 VK |
2457 | static inline bool kvm_check_tsc_unstable(void) |
2458 | { | |
2459 | #ifdef CONFIG_X86_64 | |
2460 | /* | |
2461 | * TSC is marked unstable when we're running on Hyper-V, | |
2462 | * 'TSC page' clocksource is good. | |
2463 | */ | |
b95a8a27 | 2464 | if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) |
b0c39dc6 VK |
2465 | return false; |
2466 | #endif | |
2467 | return check_tsc_unstable(); | |
2468 | } | |
2469 | ||
0c899c25 | 2470 | static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) |
99e3e30a ZA |
2471 | { |
2472 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 2473 | u64 offset, ns, elapsed; |
99e3e30a | 2474 | unsigned long flags; |
b48aa97e | 2475 | bool matched; |
0d3da0d2 | 2476 | bool already_matched; |
c5e8ec8e | 2477 | bool synchronizing = false; |
99e3e30a | 2478 | |
038f8c11 | 2479 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
9b399dfd | 2480 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
8171cd68 | 2481 | ns = get_kvmclock_base_ns(); |
f38e098f | 2482 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 2483 | |
03ba32ca | 2484 | if (vcpu->arch.virtual_tsc_khz) { |
0c899c25 | 2485 | if (data == 0) { |
bd8fab39 DP |
2486 | /* |
2487 | * detection of vcpu initialization -- need to sync | |
2488 | * with other vCPUs. This particularly helps to keep | |
2489 | * kvm_clock stable after CPU hotplug | |
2490 | */ | |
2491 | synchronizing = true; | |
2492 | } else { | |
2493 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
2494 | nsec_to_cycles(vcpu, elapsed); | |
2495 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
2496 | /* | |
2497 | * Special case: TSC write with a small delta (1 second) | |
2498 | * of virtual cycle time against real time is | |
2499 | * interpreted as an attempt to synchronize the CPU. | |
2500 | */ | |
2501 | synchronizing = data < tsc_exp + tsc_hz && | |
2502 | data + tsc_hz > tsc_exp; | |
2503 | } | |
c5e8ec8e | 2504 | } |
f38e098f ZA |
2505 | |
2506 | /* | |
5d3cb0f6 ZA |
2507 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
2508 | * TSC, we add elapsed time in this computation. We could let the | |
2509 | * compensation code attempt to catch up if we fall behind, but | |
2510 | * it's better to try to match offsets from the beginning. | |
2511 | */ | |
c5e8ec8e | 2512 | if (synchronizing && |
5d3cb0f6 | 2513 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 2514 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 2515 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 2516 | } else { |
857e4099 | 2517 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 2518 | data += delta; |
9b399dfd | 2519 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
f38e098f | 2520 | } |
b48aa97e | 2521 | matched = true; |
0d3da0d2 | 2522 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
2523 | } else { |
2524 | /* | |
2525 | * We split periods of matched TSC writes into generations. | |
2526 | * For each generation, we track the original measured | |
2527 | * nanosecond time, offset, and write, so if TSCs are in | |
2528 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 2529 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
2530 | * |
2531 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2532 | */ | |
2533 | kvm->arch.cur_tsc_generation++; | |
2534 | kvm->arch.cur_tsc_nsec = ns; | |
2535 | kvm->arch.cur_tsc_write = data; | |
2536 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 2537 | matched = false; |
f38e098f | 2538 | } |
e26101b1 ZA |
2539 | |
2540 | /* | |
2541 | * We also track th most recent recorded KHZ, write and time to | |
2542 | * allow the matching interval to be extended at each write. | |
2543 | */ | |
f38e098f ZA |
2544 | kvm->arch.last_tsc_nsec = ns; |
2545 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 2546 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 2547 | |
b183aa58 | 2548 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
2549 | |
2550 | /* Keep track of which generation this VCPU has synchronized to */ | |
2551 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2552 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2553 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2554 | ||
a545ab6a | 2555 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
e26101b1 | 2556 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
b48aa97e | 2557 | |
8228c77d | 2558 | raw_spin_lock_irqsave(&kvm->arch.pvclock_gtod_sync_lock, flags); |
0d3da0d2 | 2559 | if (!matched) { |
b48aa97e | 2560 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
2561 | } else if (!already_matched) { |
2562 | kvm->arch.nr_vcpus_matched_tsc++; | |
2563 | } | |
b48aa97e MT |
2564 | |
2565 | kvm_track_tsc_matching(vcpu); | |
8228c77d | 2566 | raw_spin_unlock_irqrestore(&kvm->arch.pvclock_gtod_sync_lock, flags); |
99e3e30a | 2567 | } |
e26101b1 | 2568 | |
58ea6767 HZ |
2569 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2570 | s64 adjustment) | |
2571 | { | |
56ba77a4 | 2572 | u64 tsc_offset = vcpu->arch.l1_tsc_offset; |
326e7425 | 2573 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); |
58ea6767 HZ |
2574 | } |
2575 | ||
2576 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2577 | { | |
805d705f | 2578 | if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) |
58ea6767 | 2579 | WARN_ON(adjustment < 0); |
fe3eb504 IS |
2580 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment, |
2581 | vcpu->arch.l1_tsc_scaling_ratio); | |
ea26e4ec | 2582 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2583 | } |
2584 | ||
d828199e MT |
2585 | #ifdef CONFIG_X86_64 |
2586 | ||
a5a1d1c2 | 2587 | static u64 read_tsc(void) |
d828199e | 2588 | { |
a5a1d1c2 | 2589 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2590 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2591 | |
2592 | if (likely(ret >= last)) | |
2593 | return ret; | |
2594 | ||
2595 | /* | |
2596 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2597 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2598 | * very likely) and there's a data dependence, so force GCC |
2599 | * to generate a branch instead. I don't barrier() because | |
2600 | * we don't actually need a barrier, and if this function | |
2601 | * ever gets inlined it will generate worse code. | |
2602 | */ | |
2603 | asm volatile (""); | |
2604 | return last; | |
2605 | } | |
2606 | ||
53fafdbb MT |
2607 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2608 | int *mode) | |
d828199e MT |
2609 | { |
2610 | long v; | |
b0c39dc6 VK |
2611 | u64 tsc_pg_val; |
2612 | ||
53fafdbb | 2613 | switch (clock->vclock_mode) { |
b95a8a27 | 2614 | case VDSO_CLOCKMODE_HVCLOCK: |
b0c39dc6 VK |
2615 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), |
2616 | tsc_timestamp); | |
2617 | if (tsc_pg_val != U64_MAX) { | |
2618 | /* TSC page valid */ | |
b95a8a27 | 2619 | *mode = VDSO_CLOCKMODE_HVCLOCK; |
53fafdbb MT |
2620 | v = (tsc_pg_val - clock->cycle_last) & |
2621 | clock->mask; | |
b0c39dc6 VK |
2622 | } else { |
2623 | /* TSC page invalid */ | |
b95a8a27 | 2624 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 VK |
2625 | } |
2626 | break; | |
b95a8a27 TG |
2627 | case VDSO_CLOCKMODE_TSC: |
2628 | *mode = VDSO_CLOCKMODE_TSC; | |
b0c39dc6 | 2629 | *tsc_timestamp = read_tsc(); |
53fafdbb MT |
2630 | v = (*tsc_timestamp - clock->cycle_last) & |
2631 | clock->mask; | |
b0c39dc6 VK |
2632 | break; |
2633 | default: | |
b95a8a27 | 2634 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 | 2635 | } |
d828199e | 2636 | |
b95a8a27 | 2637 | if (*mode == VDSO_CLOCKMODE_NONE) |
b0c39dc6 | 2638 | *tsc_timestamp = v = 0; |
d828199e | 2639 | |
53fafdbb | 2640 | return v * clock->mult; |
d828199e MT |
2641 | } |
2642 | ||
53fafdbb | 2643 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2644 | { |
cbcf2dd3 | 2645 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2646 | unsigned long seq; |
d828199e | 2647 | int mode; |
cbcf2dd3 | 2648 | u64 ns; |
d828199e | 2649 | |
d828199e MT |
2650 | do { |
2651 | seq = read_seqcount_begin(>od->seq); | |
917f9475 | 2652 | ns = gtod->raw_clock.base_cycles; |
53fafdbb | 2653 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); |
917f9475 PB |
2654 | ns >>= gtod->raw_clock.shift; |
2655 | ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); | |
d828199e | 2656 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2657 | *t = ns; |
d828199e MT |
2658 | |
2659 | return mode; | |
2660 | } | |
2661 | ||
899a31f5 | 2662 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2663 | { |
2664 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2665 | unsigned long seq; | |
2666 | int mode; | |
2667 | u64 ns; | |
2668 | ||
2669 | do { | |
2670 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 | 2671 | ts->tv_sec = gtod->wall_time_sec; |
917f9475 | 2672 | ns = gtod->clock.base_cycles; |
53fafdbb | 2673 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2674 | ns >>= gtod->clock.shift; |
2675 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2676 | ||
2677 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2678 | ts->tv_nsec = ns; | |
2679 | ||
2680 | return mode; | |
2681 | } | |
2682 | ||
b0c39dc6 VK |
2683 | /* returns true if host is using TSC based clocksource */ |
2684 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2685 | { |
d828199e | 2686 | /* checked again under seqlock below */ |
b0c39dc6 | 2687 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2688 | return false; |
2689 | ||
53fafdbb | 2690 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2691 | tsc_timestamp)); |
d828199e | 2692 | } |
55dd00a7 | 2693 | |
b0c39dc6 | 2694 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2695 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2696 | u64 *tsc_timestamp) |
55dd00a7 MT |
2697 | { |
2698 | /* checked again under seqlock below */ | |
b0c39dc6 | 2699 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2700 | return false; |
2701 | ||
b0c39dc6 | 2702 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2703 | } |
d828199e MT |
2704 | #endif |
2705 | ||
2706 | /* | |
2707 | * | |
b48aa97e MT |
2708 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2709 | * across virtual CPUs, the following condition is possible. | |
2710 | * Each numbered line represents an event visible to both | |
d828199e MT |
2711 | * CPUs at the next numbered event. |
2712 | * | |
2713 | * "timespecX" represents host monotonic time. "tscX" represents | |
2714 | * RDTSC value. | |
2715 | * | |
2716 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2717 | * | |
2718 | * 1. read timespec0,tsc0 | |
2719 | * 2. | timespec1 = timespec0 + N | |
2720 | * | tsc1 = tsc0 + M | |
2721 | * 3. transition to guest | transition to guest | |
2722 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2723 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2724 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2725 | * | |
2726 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2727 | * | |
2728 | * - ret0 < ret1 | |
2729 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2730 | * ... | |
2731 | * - 0 < N - M => M < N | |
2732 | * | |
2733 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2734 | * always the case (the difference between two distinct xtime instances | |
2735 | * might be smaller then the difference between corresponding TSC reads, | |
2736 | * when updating guest vcpus pvclock areas). | |
2737 | * | |
2738 | * To avoid that problem, do not allow visibility of distinct | |
2739 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2740 | * copy of host monotonic time values. Update that master copy | |
2741 | * in lockstep. | |
2742 | * | |
b48aa97e | 2743 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2744 | * |
2745 | */ | |
2746 | ||
2747 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2748 | { | |
2749 | #ifdef CONFIG_X86_64 | |
2750 | struct kvm_arch *ka = &kvm->arch; | |
2751 | int vclock_mode; | |
b48aa97e MT |
2752 | bool host_tsc_clocksource, vcpus_matched; |
2753 | ||
2754 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2755 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2756 | |
2757 | /* | |
2758 | * If the host uses TSC clock, then passthrough TSC as stable | |
2759 | * to the guest. | |
2760 | */ | |
b48aa97e | 2761 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2762 | &ka->master_kernel_ns, |
2763 | &ka->master_cycle_now); | |
2764 | ||
16a96021 | 2765 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2766 | && !ka->backwards_tsc_observed |
54750f2c | 2767 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2768 | |
d828199e MT |
2769 | if (ka->use_master_clock) |
2770 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2771 | ||
2772 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2773 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2774 | vcpus_matched); | |
d828199e MT |
2775 | #endif |
2776 | } | |
2777 | ||
2860c4b1 PB |
2778 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2779 | { | |
2780 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2781 | } | |
2782 | ||
2e762ff7 MT |
2783 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
2784 | { | |
2785 | #ifdef CONFIG_X86_64 | |
2786 | int i; | |
2787 | struct kvm_vcpu *vcpu; | |
2788 | struct kvm_arch *ka = &kvm->arch; | |
a83829f5 | 2789 | unsigned long flags; |
2e762ff7 | 2790 | |
e880c6ea VK |
2791 | kvm_hv_invalidate_tsc_page(kvm); |
2792 | ||
2e762ff7 | 2793 | kvm_make_mclock_inprogress_request(kvm); |
c2c647f9 | 2794 | |
2e762ff7 | 2795 | /* no guest entries from this point */ |
8228c77d | 2796 | raw_spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
2e762ff7 | 2797 | pvclock_update_vm_gtod_copy(kvm); |
8228c77d | 2798 | raw_spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
2e762ff7 MT |
2799 | |
2800 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 2801 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2802 | |
2803 | /* guest entries allowed */ | |
2804 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2805 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
2806 | #endif |
2807 | } | |
2808 | ||
e891a32e | 2809 | u64 get_kvmclock_ns(struct kvm *kvm) |
108b249c | 2810 | { |
108b249c | 2811 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2812 | struct pvclock_vcpu_time_info hv_clock; |
a83829f5 | 2813 | unsigned long flags; |
e2c2206a | 2814 | u64 ret; |
108b249c | 2815 | |
8228c77d | 2816 | raw_spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
8b953440 | 2817 | if (!ka->use_master_clock) { |
8228c77d | 2818 | raw_spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
8171cd68 | 2819 | return get_kvmclock_base_ns() + ka->kvmclock_offset; |
108b249c PB |
2820 | } |
2821 | ||
8b953440 PB |
2822 | hv_clock.tsc_timestamp = ka->master_cycle_now; |
2823 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
8228c77d | 2824 | raw_spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
8b953440 | 2825 | |
e2c2206a WL |
2826 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2827 | get_cpu(); | |
2828 | ||
e70b57a6 WL |
2829 | if (__this_cpu_read(cpu_tsc_khz)) { |
2830 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, | |
2831 | &hv_clock.tsc_shift, | |
2832 | &hv_clock.tsc_to_system_mul); | |
2833 | ret = __pvclock_read_cycles(&hv_clock, rdtsc()); | |
2834 | } else | |
8171cd68 | 2835 | ret = get_kvmclock_base_ns() + ka->kvmclock_offset; |
e2c2206a WL |
2836 | |
2837 | put_cpu(); | |
2838 | ||
2839 | return ret; | |
108b249c PB |
2840 | } |
2841 | ||
aa096aa0 JM |
2842 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v, |
2843 | struct gfn_to_hva_cache *cache, | |
2844 | unsigned int offset) | |
0d6dd2ff PB |
2845 | { |
2846 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
2847 | struct pvclock_vcpu_time_info guest_hv_clock; | |
2848 | ||
aa096aa0 JM |
2849 | if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, |
2850 | &guest_hv_clock, offset, sizeof(guest_hv_clock)))) | |
0d6dd2ff PB |
2851 | return; |
2852 | ||
2853 | /* This VCPU is paused, but it's legal for a guest to read another | |
2854 | * VCPU's kvmclock, so we really have to follow the specification where | |
2855 | * it says that version is odd if data is being modified, and even after | |
2856 | * it is consistent. | |
2857 | * | |
2858 | * Version field updates must be kept separate. This is because | |
2859 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
2860 | * writes within a string instruction are weakly ordered. So there | |
2861 | * are three writes overall. | |
2862 | * | |
2863 | * As a small optimization, only write the version field in the first | |
2864 | * and third write. The vcpu->pv_time cache is still valid, because the | |
2865 | * version field is the first in the struct. | |
2866 | */ | |
2867 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
2868 | ||
51c4b8bb LA |
2869 | if (guest_hv_clock.version & 1) |
2870 | ++guest_hv_clock.version; /* first time write, random junk */ | |
2871 | ||
0d6dd2ff | 2872 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
aa096aa0 JM |
2873 | kvm_write_guest_offset_cached(v->kvm, cache, |
2874 | &vcpu->hv_clock, offset, | |
2875 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2876 | |
2877 | smp_wmb(); | |
2878 | ||
2879 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
2880 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
2881 | ||
2882 | if (vcpu->pvclock_set_guest_stopped_request) { | |
2883 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
2884 | vcpu->pvclock_set_guest_stopped_request = false; | |
2885 | } | |
2886 | ||
2887 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
2888 | ||
aa096aa0 JM |
2889 | kvm_write_guest_offset_cached(v->kvm, cache, |
2890 | &vcpu->hv_clock, offset, | |
2891 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
2892 | |
2893 | smp_wmb(); | |
2894 | ||
2895 | vcpu->hv_clock.version++; | |
aa096aa0 JM |
2896 | kvm_write_guest_offset_cached(v->kvm, cache, |
2897 | &vcpu->hv_clock, offset, | |
2898 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2899 | } |
2900 | ||
34c238a1 | 2901 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 2902 | { |
78db6a50 | 2903 | unsigned long flags, tgt_tsc_khz; |
18068523 | 2904 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 2905 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 2906 | s64 kernel_ns; |
d828199e | 2907 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 2908 | u8 pvclock_flags; |
d828199e MT |
2909 | bool use_master_clock; |
2910 | ||
2911 | kernel_ns = 0; | |
2912 | host_tsc = 0; | |
18068523 | 2913 | |
d828199e MT |
2914 | /* |
2915 | * If the host uses TSC clock, then passthrough TSC as stable | |
2916 | * to the guest. | |
2917 | */ | |
8228c77d | 2918 | raw_spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
d828199e MT |
2919 | use_master_clock = ka->use_master_clock; |
2920 | if (use_master_clock) { | |
2921 | host_tsc = ka->master_cycle_now; | |
2922 | kernel_ns = ka->master_kernel_ns; | |
2923 | } | |
8228c77d | 2924 | raw_spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
c09664bb MT |
2925 | |
2926 | /* Keep irq disabled to prevent changes to the clock */ | |
2927 | local_irq_save(flags); | |
78db6a50 PB |
2928 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2929 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2930 | local_irq_restore(flags); |
2931 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2932 | return 1; | |
2933 | } | |
d828199e | 2934 | if (!use_master_clock) { |
4ea1636b | 2935 | host_tsc = rdtsc(); |
8171cd68 | 2936 | kernel_ns = get_kvmclock_base_ns(); |
d828199e MT |
2937 | } |
2938 | ||
4ba76538 | 2939 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2940 | |
c285545f ZA |
2941 | /* |
2942 | * We may have to catch up the TSC to match elapsed wall clock | |
2943 | * time for two reasons, even if kvmclock is used. | |
2944 | * 1) CPU could have been running below the maximum TSC rate | |
2945 | * 2) Broken TSC compensation resets the base at each VCPU | |
2946 | * entry to avoid unknown leaps of TSC even when running | |
2947 | * again on the same CPU. This may cause apparent elapsed | |
2948 | * time to disappear, and the guest to stand still or run | |
2949 | * very slowly. | |
2950 | */ | |
2951 | if (vcpu->tsc_catchup) { | |
2952 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
2953 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 2954 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
2955 | tsc_timestamp = tsc; |
2956 | } | |
50d0a0f9 GH |
2957 | } |
2958 | ||
18068523 GOC |
2959 | local_irq_restore(flags); |
2960 | ||
0d6dd2ff | 2961 | /* With all the info we got, fill in the values */ |
18068523 | 2962 | |
78db6a50 | 2963 | if (kvm_has_tsc_control) |
fe3eb504 IS |
2964 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz, |
2965 | v->arch.l1_tsc_scaling_ratio); | |
78db6a50 PB |
2966 | |
2967 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 2968 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
2969 | &vcpu->hv_clock.tsc_shift, |
2970 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 2971 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
2972 | } |
2973 | ||
1d5f066e | 2974 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 2975 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 2976 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 2977 | |
d828199e | 2978 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 2979 | pvclock_flags = 0; |
d828199e MT |
2980 | if (use_master_clock) |
2981 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
2982 | ||
78c0337a MT |
2983 | vcpu->hv_clock.flags = pvclock_flags; |
2984 | ||
095cf55d | 2985 | if (vcpu->pv_time_enabled) |
aa096aa0 JM |
2986 | kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); |
2987 | if (vcpu->xen.vcpu_info_set) | |
2988 | kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, | |
2989 | offsetof(struct compat_vcpu_info, time)); | |
f2340cd9 JM |
2990 | if (vcpu->xen.vcpu_time_info_set) |
2991 | kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); | |
94c245a2 | 2992 | if (!v->vcpu_idx) |
095cf55d | 2993 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); |
8cfdc000 | 2994 | return 0; |
c8076604 GH |
2995 | } |
2996 | ||
0061d53d MT |
2997 | /* |
2998 | * kvmclock updates which are isolated to a given vcpu, such as | |
2999 | * vcpu->cpu migration, should not allow system_timestamp from | |
3000 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
3001 | * correction applies to one vcpu's system_timestamp but not | |
3002 | * the others. | |
3003 | * | |
3004 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
3005 | * We need to rate-limit these requests though, as they can |
3006 | * considerably slow guests that have a large number of vcpus. | |
3007 | * The time for a remote vcpu to update its kvmclock is bound | |
3008 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
3009 | */ |
3010 | ||
7e44e449 AJ |
3011 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
3012 | ||
3013 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
3014 | { |
3015 | int i; | |
7e44e449 AJ |
3016 | struct delayed_work *dwork = to_delayed_work(work); |
3017 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
3018 | kvmclock_update_work); | |
3019 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
3020 | struct kvm_vcpu *vcpu; |
3021 | ||
3022 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 3023 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
3024 | kvm_vcpu_kick(vcpu); |
3025 | } | |
3026 | } | |
3027 | ||
7e44e449 AJ |
3028 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
3029 | { | |
3030 | struct kvm *kvm = v->kvm; | |
3031 | ||
105b21bb | 3032 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
3033 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
3034 | KVMCLOCK_UPDATE_DELAY); | |
3035 | } | |
3036 | ||
332967a3 AJ |
3037 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
3038 | ||
3039 | static void kvmclock_sync_fn(struct work_struct *work) | |
3040 | { | |
3041 | struct delayed_work *dwork = to_delayed_work(work); | |
3042 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
3043 | kvmclock_sync_work); | |
3044 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
3045 | ||
630994b3 MT |
3046 | if (!kvmclock_periodic_sync) |
3047 | return; | |
3048 | ||
332967a3 AJ |
3049 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
3050 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
3051 | KVMCLOCK_SYNC_PERIOD); | |
3052 | } | |
3053 | ||
191c8137 BP |
3054 | /* |
3055 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
3056 | */ | |
3057 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
3058 | { | |
3059 | /* McStatusWrEn enabled? */ | |
23493d0a | 3060 | if (guest_cpuid_is_amd_or_hygon(vcpu)) |
191c8137 BP |
3061 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); |
3062 | ||
3063 | return false; | |
3064 | } | |
3065 | ||
9ffd986c | 3066 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3067 | { |
890ca9ae HY |
3068 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3069 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
3070 | u32 msr = msr_info->index; |
3071 | u64 data = msr_info->data; | |
890ca9ae | 3072 | |
15c4a640 | 3073 | switch (msr) { |
15c4a640 | 3074 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 3075 | vcpu->arch.mcg_status = data; |
15c4a640 | 3076 | break; |
c7ac679c | 3077 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
3078 | if (!(mcg_cap & MCG_CTL_P) && |
3079 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
3080 | return 1; |
3081 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 3082 | return 1; |
890ca9ae HY |
3083 | vcpu->arch.mcg_ctl = data; |
3084 | break; | |
3085 | default: | |
3086 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3087 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3088 | u32 offset = array_index_nospec( |
3089 | msr - MSR_IA32_MC0_CTL, | |
3090 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3091 | ||
114be429 AP |
3092 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
3093 | * some Linux kernels though clear bit 10 in bank 4 to | |
3094 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
3095 | * this to avoid an uncatched #GP in the guest | |
3096 | */ | |
890ca9ae | 3097 | if ((offset & 0x3) == 0 && |
114be429 | 3098 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 3099 | return -1; |
191c8137 BP |
3100 | |
3101 | /* MCi_STATUS */ | |
9ffd986c | 3102 | if (!msr_info->host_initiated && |
191c8137 BP |
3103 | (offset & 0x3) == 1 && data != 0) { |
3104 | if (!can_set_mci_status(vcpu)) | |
3105 | return -1; | |
3106 | } | |
3107 | ||
890ca9ae HY |
3108 | vcpu->arch.mce_banks[offset] = data; |
3109 | break; | |
3110 | } | |
3111 | return 1; | |
3112 | } | |
3113 | return 0; | |
3114 | } | |
3115 | ||
2635b5c4 VK |
3116 | static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) |
3117 | { | |
3118 | u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; | |
3119 | ||
3120 | return (vcpu->arch.apf.msr_en_val & mask) == mask; | |
3121 | } | |
3122 | ||
344d9588 GN |
3123 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
3124 | { | |
3125 | gpa_t gpa = data & ~0x3f; | |
3126 | ||
2635b5c4 VK |
3127 | /* Bits 4:5 are reserved, Should be zero */ |
3128 | if (data & 0x30) | |
344d9588 GN |
3129 | return 1; |
3130 | ||
66570e96 OU |
3131 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && |
3132 | (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) | |
3133 | return 1; | |
3134 | ||
3135 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && | |
3136 | (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) | |
3137 | return 1; | |
3138 | ||
9d3c447c | 3139 | if (!lapic_in_kernel(vcpu)) |
d831de17 | 3140 | return data ? 1 : 0; |
9d3c447c | 3141 | |
2635b5c4 | 3142 | vcpu->arch.apf.msr_en_val = data; |
344d9588 | 3143 | |
2635b5c4 | 3144 | if (!kvm_pv_async_pf_enabled(vcpu)) { |
344d9588 GN |
3145 | kvm_clear_async_pf_completion_queue(vcpu); |
3146 | kvm_async_pf_hash_reset(vcpu); | |
3147 | return 0; | |
3148 | } | |
3149 | ||
4e335d9e | 3150 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
68fd66f1 | 3151 | sizeof(u64))) |
344d9588 GN |
3152 | return 1; |
3153 | ||
6adba527 | 3154 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 3155 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
2635b5c4 | 3156 | |
344d9588 | 3157 | kvm_async_pf_wakeup_all(vcpu); |
2635b5c4 VK |
3158 | |
3159 | return 0; | |
3160 | } | |
3161 | ||
3162 | static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) | |
3163 | { | |
3164 | /* Bits 8-63 are reserved */ | |
3165 | if (data >> 8) | |
3166 | return 1; | |
3167 | ||
3168 | if (!lapic_in_kernel(vcpu)) | |
3169 | return 1; | |
3170 | ||
3171 | vcpu->arch.apf.msr_int_val = data; | |
3172 | ||
3173 | vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; | |
3174 | ||
344d9588 GN |
3175 | return 0; |
3176 | } | |
3177 | ||
12f9a48f GC |
3178 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
3179 | { | |
0b79459b | 3180 | vcpu->arch.pv_time_enabled = false; |
49dedf0d | 3181 | vcpu->arch.time = 0; |
12f9a48f GC |
3182 | } |
3183 | ||
7780938c | 3184 | static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) |
f38a7b75 WL |
3185 | { |
3186 | ++vcpu->stat.tlb_flush; | |
b3646477 | 3187 | static_call(kvm_x86_tlb_flush_all)(vcpu); |
f38a7b75 WL |
3188 | } |
3189 | ||
0baedd79 VK |
3190 | static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) |
3191 | { | |
3192 | ++vcpu->stat.tlb_flush; | |
b53e84ee LJ |
3193 | |
3194 | if (!tdp_enabled) { | |
3195 | /* | |
3196 | * A TLB flush on behalf of the guest is equivalent to | |
3197 | * INVPCID(all), toggling CR4.PGE, etc., which requires | |
3198 | * a forced sync of the shadow page tables. Unload the | |
3199 | * entire MMU here and the subsequent load will sync the | |
3200 | * shadow page tables, and also flush the TLB. | |
3201 | */ | |
3202 | kvm_mmu_unload(vcpu); | |
3203 | return; | |
3204 | } | |
3205 | ||
b3646477 | 3206 | static_call(kvm_x86_tlb_flush_guest)(vcpu); |
0baedd79 VK |
3207 | } |
3208 | ||
8eb2fc7c SC |
3209 | |
3210 | static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu) | |
3211 | { | |
3212 | ++vcpu->stat.tlb_flush; | |
3213 | static_call(kvm_x86_tlb_flush_current)(vcpu); | |
3214 | } | |
3215 | ||
3216 | /* | |
3217 | * Service "local" TLB flush requests, which are specific to the current MMU | |
3218 | * context. In addition to the generic event handling in vcpu_enter_guest(), | |
3219 | * TLB flushes that are targeted at an MMU context also need to be serviced | |
3220 | * prior before nested VM-Enter/VM-Exit. | |
3221 | */ | |
3222 | void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu) | |
3223 | { | |
3224 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) | |
3225 | kvm_vcpu_flush_tlb_current(vcpu); | |
3226 | ||
3227 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) | |
3228 | kvm_vcpu_flush_tlb_guest(vcpu); | |
3229 | } | |
3230 | EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests); | |
3231 | ||
c9aaa895 GC |
3232 | static void record_steal_time(struct kvm_vcpu *vcpu) |
3233 | { | |
3c811b0f DW |
3234 | struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; |
3235 | struct kvm_steal_time __user *st; | |
3236 | struct kvm_memslots *slots; | |
3237 | u64 steal; | |
3238 | u32 version; | |
b0431382 | 3239 | |
30b5c851 DW |
3240 | if (kvm_xen_msr_enabled(vcpu->kvm)) { |
3241 | kvm_xen_runstate_set_running(vcpu); | |
3242 | return; | |
3243 | } | |
3244 | ||
c9aaa895 GC |
3245 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
3246 | return; | |
3247 | ||
3c811b0f | 3248 | if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm)) |
c9aaa895 GC |
3249 | return; |
3250 | ||
3c811b0f DW |
3251 | slots = kvm_memslots(vcpu->kvm); |
3252 | ||
3253 | if (unlikely(slots->generation != ghc->generation || | |
3254 | kvm_is_error_hva(ghc->hva) || !ghc->memslot)) { | |
3255 | gfn_t gfn = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; | |
3256 | ||
3257 | /* We rely on the fact that it fits in a single page. */ | |
3258 | BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS); | |
3259 | ||
3260 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gfn, sizeof(*st)) || | |
3261 | kvm_is_error_hva(ghc->hva) || !ghc->memslot) | |
3262 | return; | |
3263 | } | |
3264 | ||
3265 | st = (struct kvm_steal_time __user *)ghc->hva; | |
f38a7b75 WL |
3266 | /* |
3267 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
3268 | * expensive IPIs. | |
3269 | */ | |
66570e96 | 3270 | if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { |
3c811b0f DW |
3271 | u8 st_preempted = 0; |
3272 | int err = -EFAULT; | |
3273 | ||
d1fb2538 PB |
3274 | if (!user_access_begin(st, sizeof(*st))) |
3275 | return; | |
3276 | ||
3c811b0f DW |
3277 | asm volatile("1: xchgb %0, %2\n" |
3278 | "xor %1, %1\n" | |
3279 | "2:\n" | |
3280 | _ASM_EXTABLE_UA(1b, 2b) | |
813956c9 DW |
3281 | : "+q" (st_preempted), |
3282 | "+&r" (err), | |
3283 | "+m" (st->preempted)); | |
3c811b0f DW |
3284 | if (err) |
3285 | goto out; | |
3286 | ||
3287 | user_access_end(); | |
3288 | ||
3289 | vcpu->arch.st.preempted = 0; | |
af3511ff | 3290 | |
66570e96 | 3291 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, |
af3511ff LJ |
3292 | st_preempted & KVM_VCPU_FLUSH_TLB); |
3293 | if (st_preempted & KVM_VCPU_FLUSH_TLB) | |
66570e96 | 3294 | kvm_vcpu_flush_tlb_guest(vcpu); |
3c811b0f DW |
3295 | |
3296 | if (!user_access_begin(st, sizeof(*st))) | |
3297 | goto dirty; | |
1eff0ada | 3298 | } else { |
d1fb2538 PB |
3299 | if (!user_access_begin(st, sizeof(*st))) |
3300 | return; | |
3301 | ||
3c811b0f DW |
3302 | unsafe_put_user(0, &st->preempted, out); |
3303 | vcpu->arch.st.preempted = 0; | |
66570e96 | 3304 | } |
0b9f6c46 | 3305 | |
3c811b0f DW |
3306 | unsafe_get_user(version, &st->version, out); |
3307 | if (version & 1) | |
3308 | version += 1; /* first time write, random junk */ | |
35f3fae1 | 3309 | |
3c811b0f DW |
3310 | version += 1; |
3311 | unsafe_put_user(version, &st->version, out); | |
35f3fae1 WL |
3312 | |
3313 | smp_wmb(); | |
3314 | ||
3c811b0f DW |
3315 | unsafe_get_user(steal, &st->steal, out); |
3316 | steal += current->sched_info.run_delay - | |
c54cdf14 LC |
3317 | vcpu->arch.st.last_steal; |
3318 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
3c811b0f | 3319 | unsafe_put_user(steal, &st->steal, out); |
35f3fae1 | 3320 | |
3c811b0f DW |
3321 | version += 1; |
3322 | unsafe_put_user(version, &st->version, out); | |
c9aaa895 | 3323 | |
3c811b0f DW |
3324 | out: |
3325 | user_access_end(); | |
3326 | dirty: | |
3327 | mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); | |
c9aaa895 GC |
3328 | } |
3329 | ||
8fe8ab46 | 3330 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3331 | { |
5753785f | 3332 | bool pr = false; |
8fe8ab46 WA |
3333 | u32 msr = msr_info->index; |
3334 | u64 data = msr_info->data; | |
5753785f | 3335 | |
1232f8e6 | 3336 | if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) |
23200b7a | 3337 | return kvm_xen_write_hypercall_page(vcpu, data); |
1232f8e6 | 3338 | |
15c4a640 | 3339 | switch (msr) { |
2e32b719 | 3340 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
3341 | case MSR_IA32_UCODE_WRITE: |
3342 | case MSR_VM_HSAVE_PA: | |
3343 | case MSR_AMD64_PATCH_LOADER: | |
3344 | case MSR_AMD64_BU_CFG2: | |
405a353a | 3345 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3346 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
3347 | break; |
3348 | ||
518e7b94 WL |
3349 | case MSR_IA32_UCODE_REV: |
3350 | if (msr_info->host_initiated) | |
3351 | vcpu->arch.microcode_version = data; | |
3352 | break; | |
0cf9135b SC |
3353 | case MSR_IA32_ARCH_CAPABILITIES: |
3354 | if (!msr_info->host_initiated) | |
3355 | return 1; | |
3356 | vcpu->arch.arch_capabilities = data; | |
3357 | break; | |
d574c539 VK |
3358 | case MSR_IA32_PERF_CAPABILITIES: { |
3359 | struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; | |
3360 | ||
3361 | if (!msr_info->host_initiated) | |
3362 | return 1; | |
9c8e4293 | 3363 | if (kvm_get_msr_feature(&msr_ent)) |
d574c539 VK |
3364 | return 1; |
3365 | if (data & ~msr_ent.data) | |
3366 | return 1; | |
3367 | ||
3368 | vcpu->arch.perf_capabilities = data; | |
3369 | ||
3370 | return 0; | |
3371 | } | |
15c4a640 | 3372 | case MSR_EFER: |
11988499 | 3373 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
3374 | case MSR_K7_HWCR: |
3375 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 3376 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 3377 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
3378 | |
3379 | /* Handle McStatusWrEn */ | |
3380 | if (data == BIT_ULL(18)) { | |
3381 | vcpu->arch.msr_hwcr = data; | |
3382 | } else if (data != 0) { | |
a737f256 CD |
3383 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
3384 | data); | |
8f1589d9 AP |
3385 | return 1; |
3386 | } | |
15c4a640 | 3387 | break; |
f7c6d140 AP |
3388 | case MSR_FAM10H_MMIO_CONF_BASE: |
3389 | if (data != 0) { | |
a737f256 CD |
3390 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
3391 | "0x%llx\n", data); | |
f7c6d140 AP |
3392 | return 1; |
3393 | } | |
15c4a640 | 3394 | break; |
9ba075a6 | 3395 | case 0x200 ... 0x2ff: |
ff53604b | 3396 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 3397 | case MSR_IA32_APICBASE: |
58cb628d | 3398 | return kvm_set_apic_base(vcpu, msr_info); |
bf10bd0b | 3399 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
0105d1a5 | 3400 | return kvm_x2apic_msr_write(vcpu, msr, data); |
09141ec0 | 3401 | case MSR_IA32_TSC_DEADLINE: |
a3e06bbe LJ |
3402 | kvm_set_lapic_tscdeadline_msr(vcpu, data); |
3403 | break; | |
ba904635 | 3404 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 3405 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 3406 | if (!msr_info->host_initiated) { |
d913b904 | 3407 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 3408 | adjust_tsc_offset_guest(vcpu, adj); |
d9130a2d ZD |
3409 | /* Before back to guest, tsc_timestamp must be adjusted |
3410 | * as well, otherwise guest's percpu pvclock time could jump. | |
3411 | */ | |
3412 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
ba904635 WA |
3413 | } |
3414 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
3415 | } | |
3416 | break; | |
15c4a640 | 3417 | case MSR_IA32_MISC_ENABLE: |
511a8556 WL |
3418 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
3419 | ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { | |
3420 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) | |
3421 | return 1; | |
3422 | vcpu->arch.ia32_misc_enable_msr = data; | |
aedbaf4f | 3423 | kvm_update_cpuid_runtime(vcpu); |
511a8556 WL |
3424 | } else { |
3425 | vcpu->arch.ia32_misc_enable_msr = data; | |
3426 | } | |
15c4a640 | 3427 | break; |
64d60670 PB |
3428 | case MSR_IA32_SMBASE: |
3429 | if (!msr_info->host_initiated) | |
3430 | return 1; | |
3431 | vcpu->arch.smbase = data; | |
3432 | break; | |
73f624f4 PB |
3433 | case MSR_IA32_POWER_CTL: |
3434 | vcpu->arch.msr_ia32_power_ctl = data; | |
3435 | break; | |
dd259935 | 3436 | case MSR_IA32_TSC: |
0c899c25 PB |
3437 | if (msr_info->host_initiated) { |
3438 | kvm_synchronize_tsc(vcpu, data); | |
3439 | } else { | |
9b399dfd | 3440 | u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; |
0c899c25 PB |
3441 | adjust_tsc_offset_guest(vcpu, adj); |
3442 | vcpu->arch.ia32_tsc_adjust_msr += adj; | |
3443 | } | |
dd259935 | 3444 | break; |
864e2ab2 AL |
3445 | case MSR_IA32_XSS: |
3446 | if (!msr_info->host_initiated && | |
3447 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3448 | return 1; | |
3449 | /* | |
a1bead2a SC |
3450 | * KVM supports exposing PT to the guest, but does not support |
3451 | * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than | |
3452 | * XSAVES/XRSTORS to save/restore PT MSRs. | |
864e2ab2 | 3453 | */ |
408e9a31 | 3454 | if (data & ~supported_xss) |
864e2ab2 AL |
3455 | return 1; |
3456 | vcpu->arch.ia32_xss = data; | |
7e20101f | 3457 | kvm_update_cpuid_runtime(vcpu); |
864e2ab2 | 3458 | break; |
52797bf9 LA |
3459 | case MSR_SMI_COUNT: |
3460 | if (!msr_info->host_initiated) | |
3461 | return 1; | |
3462 | vcpu->arch.smi_count = data; | |
3463 | break; | |
11c6bffa | 3464 | case MSR_KVM_WALL_CLOCK_NEW: |
66570e96 OU |
3465 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3466 | return 1; | |
3467 | ||
629b5348 JM |
3468 | vcpu->kvm->arch.wall_clock = data; |
3469 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
66570e96 | 3470 | break; |
18068523 | 3471 | case MSR_KVM_WALL_CLOCK: |
66570e96 OU |
3472 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3473 | return 1; | |
3474 | ||
629b5348 JM |
3475 | vcpu->kvm->arch.wall_clock = data; |
3476 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
18068523 | 3477 | break; |
11c6bffa | 3478 | case MSR_KVM_SYSTEM_TIME_NEW: |
66570e96 OU |
3479 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3480 | return 1; | |
3481 | ||
5b9bb0eb OU |
3482 | kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); |
3483 | break; | |
3484 | case MSR_KVM_SYSTEM_TIME: | |
66570e96 OU |
3485 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3486 | return 1; | |
3487 | ||
3488 | kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); | |
18068523 | 3489 | break; |
344d9588 | 3490 | case MSR_KVM_ASYNC_PF_EN: |
66570e96 OU |
3491 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3492 | return 1; | |
3493 | ||
344d9588 GN |
3494 | if (kvm_pv_enable_async_pf(vcpu, data)) |
3495 | return 1; | |
3496 | break; | |
2635b5c4 | 3497 | case MSR_KVM_ASYNC_PF_INT: |
66570e96 OU |
3498 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3499 | return 1; | |
3500 | ||
2635b5c4 VK |
3501 | if (kvm_pv_enable_async_pf_int(vcpu, data)) |
3502 | return 1; | |
3503 | break; | |
557a961a | 3504 | case MSR_KVM_ASYNC_PF_ACK: |
0a31df68 | 3505 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
66570e96 | 3506 | return 1; |
557a961a VK |
3507 | if (data & 0x1) { |
3508 | vcpu->arch.apf.pageready_pending = false; | |
3509 | kvm_check_async_pf_completion(vcpu); | |
3510 | } | |
3511 | break; | |
c9aaa895 | 3512 | case MSR_KVM_STEAL_TIME: |
66570e96 OU |
3513 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3514 | return 1; | |
c9aaa895 GC |
3515 | |
3516 | if (unlikely(!sched_info_on())) | |
3517 | return 1; | |
3518 | ||
3519 | if (data & KVM_STEAL_RESERVED_MASK) | |
3520 | return 1; | |
3521 | ||
c9aaa895 GC |
3522 | vcpu->arch.st.msr_val = data; |
3523 | ||
3524 | if (!(data & KVM_MSR_ENABLED)) | |
3525 | break; | |
3526 | ||
c9aaa895 GC |
3527 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
3528 | ||
3529 | break; | |
ae7a2a3f | 3530 | case MSR_KVM_PV_EOI_EN: |
66570e96 OU |
3531 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3532 | return 1; | |
3533 | ||
72bbf935 | 3534 | if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
3535 | return 1; |
3536 | break; | |
c9aaa895 | 3537 | |
2d5ba19b | 3538 | case MSR_KVM_POLL_CONTROL: |
66570e96 OU |
3539 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3540 | return 1; | |
3541 | ||
2d5ba19b MT |
3542 | /* only enable bit supported */ |
3543 | if (data & (-1ULL << 1)) | |
3544 | return 1; | |
3545 | ||
3546 | vcpu->arch.msr_kvm_poll_control = data; | |
3547 | break; | |
3548 | ||
890ca9ae HY |
3549 | case MSR_IA32_MCG_CTL: |
3550 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3551 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 3552 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 3553 | |
6912ac32 WH |
3554 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
3555 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
df561f66 GS |
3556 | pr = true; |
3557 | fallthrough; | |
6912ac32 WH |
3558 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3559 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3560 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3561 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
3562 | |
3563 | if (pr || data != 0) | |
a737f256 CD |
3564 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
3565 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 3566 | break; |
84e0cefa JS |
3567 | case MSR_K7_CLK_CTL: |
3568 | /* | |
3569 | * Ignore all writes to this no longer documented MSR. | |
3570 | * Writes are only relevant for old K7 processors, | |
3571 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 3572 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
3573 | * affected processor models on the command line, hence |
3574 | * the need to ignore the workaround. | |
3575 | */ | |
3576 | break; | |
55cd8e5a | 3577 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3578 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3579 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3580 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3581 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3582 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3583 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3584 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3585 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
3586 | return kvm_hv_set_msr_common(vcpu, msr, data, |
3587 | msr_info->host_initiated); | |
91c9c3ed | 3588 | case MSR_IA32_BBL_CR_CTL3: |
3589 | /* Drop writes to this legacy MSR -- see rdmsr | |
3590 | * counterpart for further detail. | |
3591 | */ | |
fab0aa3b EM |
3592 | if (report_ignored_msrs) |
3593 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
3594 | msr, data); | |
91c9c3ed | 3595 | break; |
2b036c6b | 3596 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3597 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3598 | return 1; |
3599 | vcpu->arch.osvw.length = data; | |
3600 | break; | |
3601 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3602 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3603 | return 1; |
3604 | vcpu->arch.osvw.status = data; | |
3605 | break; | |
db2336a8 KH |
3606 | case MSR_PLATFORM_INFO: |
3607 | if (!msr_info->host_initiated || | |
db2336a8 KH |
3608 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
3609 | cpuid_fault_enabled(vcpu))) | |
3610 | return 1; | |
3611 | vcpu->arch.msr_platform_info = data; | |
3612 | break; | |
3613 | case MSR_MISC_FEATURES_ENABLES: | |
3614 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
3615 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
3616 | !supports_cpuid_fault(vcpu))) | |
3617 | return 1; | |
3618 | vcpu->arch.msr_misc_features_enables = data; | |
3619 | break; | |
15c4a640 | 3620 | default: |
c6702c9d | 3621 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3622 | return kvm_pmu_set_msr(vcpu, msr_info); |
6abe9c13 | 3623 | return KVM_MSR_RET_INVALID; |
15c4a640 CO |
3624 | } |
3625 | return 0; | |
3626 | } | |
3627 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
3628 | ||
44883f01 | 3629 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
3630 | { |
3631 | u64 data; | |
890ca9ae HY |
3632 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3633 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
3634 | |
3635 | switch (msr) { | |
15c4a640 CO |
3636 | case MSR_IA32_P5_MC_ADDR: |
3637 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
3638 | data = 0; |
3639 | break; | |
15c4a640 | 3640 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
3641 | data = vcpu->arch.mcg_cap; |
3642 | break; | |
c7ac679c | 3643 | case MSR_IA32_MCG_CTL: |
44883f01 | 3644 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
3645 | return 1; |
3646 | data = vcpu->arch.mcg_ctl; | |
3647 | break; | |
3648 | case MSR_IA32_MCG_STATUS: | |
3649 | data = vcpu->arch.mcg_status; | |
3650 | break; | |
3651 | default: | |
3652 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3653 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3654 | u32 offset = array_index_nospec( |
3655 | msr - MSR_IA32_MC0_CTL, | |
3656 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3657 | ||
890ca9ae HY |
3658 | data = vcpu->arch.mce_banks[offset]; |
3659 | break; | |
3660 | } | |
3661 | return 1; | |
3662 | } | |
3663 | *pdata = data; | |
3664 | return 0; | |
3665 | } | |
3666 | ||
609e36d3 | 3667 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 3668 | { |
609e36d3 | 3669 | switch (msr_info->index) { |
890ca9ae | 3670 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 3671 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
3672 | case MSR_IA32_LASTBRANCHFROMIP: |
3673 | case MSR_IA32_LASTBRANCHTOIP: | |
3674 | case MSR_IA32_LASTINTFROMIP: | |
3675 | case MSR_IA32_LASTINTTOIP: | |
059e5c32 | 3676 | case MSR_AMD64_SYSCFG: |
3afb1121 PB |
3677 | case MSR_K8_TSEG_ADDR: |
3678 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 3679 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 3680 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 3681 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 3682 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 3683 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 3684 | case MSR_IA32_PERF_CTL: |
405a353a | 3685 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3686 | case MSR_F15H_EX_CFG: |
2ca1a06a VS |
3687 | /* |
3688 | * Intel Sandy Bridge CPUs must support the RAPL (running average power | |
3689 | * limit) MSRs. Just return 0, as we do not want to expose the host | |
3690 | * data here. Do not conditionalize this on CPUID, as KVM does not do | |
3691 | * so for existing CPU-specific MSRs. | |
3692 | */ | |
3693 | case MSR_RAPL_POWER_UNIT: | |
3694 | case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ | |
3695 | case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ | |
3696 | case MSR_PKG_ENERGY_STATUS: /* Total package */ | |
3697 | case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ | |
609e36d3 | 3698 | msr_info->data = 0; |
15c4a640 | 3699 | break; |
c51eb52b | 3700 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
c28fa560 VK |
3701 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
3702 | return kvm_pmu_get_msr(vcpu, msr_info); | |
3703 | if (!msr_info->host_initiated) | |
3704 | return 1; | |
3705 | msr_info->data = 0; | |
3706 | break; | |
6912ac32 WH |
3707 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3708 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
3709 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
3710 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3711 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3712 | return kvm_pmu_get_msr(vcpu, msr_info); |
609e36d3 | 3713 | msr_info->data = 0; |
5753785f | 3714 | break; |
742bc670 | 3715 | case MSR_IA32_UCODE_REV: |
518e7b94 | 3716 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 3717 | break; |
0cf9135b SC |
3718 | case MSR_IA32_ARCH_CAPABILITIES: |
3719 | if (!msr_info->host_initiated && | |
3720 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3721 | return 1; | |
3722 | msr_info->data = vcpu->arch.arch_capabilities; | |
3723 | break; | |
d574c539 VK |
3724 | case MSR_IA32_PERF_CAPABILITIES: |
3725 | if (!msr_info->host_initiated && | |
3726 | !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) | |
3727 | return 1; | |
3728 | msr_info->data = vcpu->arch.perf_capabilities; | |
3729 | break; | |
73f624f4 PB |
3730 | case MSR_IA32_POWER_CTL: |
3731 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
3732 | break; | |
cc5b54dd ML |
3733 | case MSR_IA32_TSC: { |
3734 | /* | |
3735 | * Intel SDM states that MSR_IA32_TSC read adds the TSC offset | |
3736 | * even when not intercepted. AMD manual doesn't explicitly | |
3737 | * state this but appears to behave the same. | |
3738 | * | |
ee6fa053 | 3739 | * On userspace reads and writes, however, we unconditionally |
c0623f5e | 3740 | * return L1's TSC value to ensure backwards-compatible |
ee6fa053 | 3741 | * behavior for migration. |
cc5b54dd | 3742 | */ |
fe3eb504 | 3743 | u64 offset, ratio; |
cc5b54dd | 3744 | |
fe3eb504 IS |
3745 | if (msr_info->host_initiated) { |
3746 | offset = vcpu->arch.l1_tsc_offset; | |
3747 | ratio = vcpu->arch.l1_tsc_scaling_ratio; | |
3748 | } else { | |
3749 | offset = vcpu->arch.tsc_offset; | |
3750 | ratio = vcpu->arch.tsc_scaling_ratio; | |
3751 | } | |
3752 | ||
3753 | msr_info->data = kvm_scale_tsc(vcpu, rdtsc(), ratio) + offset; | |
dd259935 | 3754 | break; |
cc5b54dd | 3755 | } |
9ba075a6 | 3756 | case MSR_MTRRcap: |
9ba075a6 | 3757 | case 0x200 ... 0x2ff: |
ff53604b | 3758 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 3759 | case 0xcd: /* fsb frequency */ |
609e36d3 | 3760 | msr_info->data = 3; |
15c4a640 | 3761 | break; |
7b914098 JS |
3762 | /* |
3763 | * MSR_EBC_FREQUENCY_ID | |
3764 | * Conservative value valid for even the basic CPU models. | |
3765 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
3766 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
3767 | * and 266MHz for model 3, or 4. Set Core Clock | |
3768 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
3769 | * 31:24) even though these are only valid for CPU | |
3770 | * models > 2, however guests may end up dividing or | |
3771 | * multiplying by zero otherwise. | |
3772 | */ | |
3773 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 3774 | msr_info->data = 1 << 24; |
7b914098 | 3775 | break; |
15c4a640 | 3776 | case MSR_IA32_APICBASE: |
609e36d3 | 3777 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 3778 | break; |
bf10bd0b | 3779 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
609e36d3 | 3780 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
09141ec0 | 3781 | case MSR_IA32_TSC_DEADLINE: |
609e36d3 | 3782 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 3783 | break; |
ba904635 | 3784 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 3785 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 3786 | break; |
15c4a640 | 3787 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 3788 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 3789 | break; |
64d60670 PB |
3790 | case MSR_IA32_SMBASE: |
3791 | if (!msr_info->host_initiated) | |
3792 | return 1; | |
3793 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 3794 | break; |
52797bf9 LA |
3795 | case MSR_SMI_COUNT: |
3796 | msr_info->data = vcpu->arch.smi_count; | |
3797 | break; | |
847f0ad8 AG |
3798 | case MSR_IA32_PERF_STATUS: |
3799 | /* TSC increment by tick */ | |
609e36d3 | 3800 | msr_info->data = 1000ULL; |
847f0ad8 | 3801 | /* CPU multiplier */ |
b0996ae4 | 3802 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 3803 | break; |
15c4a640 | 3804 | case MSR_EFER: |
609e36d3 | 3805 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 3806 | break; |
18068523 | 3807 | case MSR_KVM_WALL_CLOCK: |
1930e5dd OU |
3808 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3809 | return 1; | |
3810 | ||
3811 | msr_info->data = vcpu->kvm->arch.wall_clock; | |
3812 | break; | |
11c6bffa | 3813 | case MSR_KVM_WALL_CLOCK_NEW: |
1930e5dd OU |
3814 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3815 | return 1; | |
3816 | ||
609e36d3 | 3817 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
3818 | break; |
3819 | case MSR_KVM_SYSTEM_TIME: | |
1930e5dd OU |
3820 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3821 | return 1; | |
3822 | ||
3823 | msr_info->data = vcpu->arch.time; | |
3824 | break; | |
11c6bffa | 3825 | case MSR_KVM_SYSTEM_TIME_NEW: |
1930e5dd OU |
3826 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3827 | return 1; | |
3828 | ||
609e36d3 | 3829 | msr_info->data = vcpu->arch.time; |
18068523 | 3830 | break; |
344d9588 | 3831 | case MSR_KVM_ASYNC_PF_EN: |
1930e5dd OU |
3832 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3833 | return 1; | |
3834 | ||
2635b5c4 VK |
3835 | msr_info->data = vcpu->arch.apf.msr_en_val; |
3836 | break; | |
3837 | case MSR_KVM_ASYNC_PF_INT: | |
1930e5dd OU |
3838 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3839 | return 1; | |
3840 | ||
2635b5c4 | 3841 | msr_info->data = vcpu->arch.apf.msr_int_val; |
344d9588 | 3842 | break; |
557a961a | 3843 | case MSR_KVM_ASYNC_PF_ACK: |
0a31df68 | 3844 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
1930e5dd OU |
3845 | return 1; |
3846 | ||
557a961a VK |
3847 | msr_info->data = 0; |
3848 | break; | |
c9aaa895 | 3849 | case MSR_KVM_STEAL_TIME: |
1930e5dd OU |
3850 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3851 | return 1; | |
3852 | ||
609e36d3 | 3853 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 3854 | break; |
1d92128f | 3855 | case MSR_KVM_PV_EOI_EN: |
1930e5dd OU |
3856 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3857 | return 1; | |
3858 | ||
609e36d3 | 3859 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 3860 | break; |
2d5ba19b | 3861 | case MSR_KVM_POLL_CONTROL: |
1930e5dd OU |
3862 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3863 | return 1; | |
3864 | ||
2d5ba19b MT |
3865 | msr_info->data = vcpu->arch.msr_kvm_poll_control; |
3866 | break; | |
890ca9ae HY |
3867 | case MSR_IA32_P5_MC_ADDR: |
3868 | case MSR_IA32_P5_MC_TYPE: | |
3869 | case MSR_IA32_MCG_CAP: | |
3870 | case MSR_IA32_MCG_CTL: | |
3871 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3872 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
3873 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
3874 | msr_info->host_initiated); | |
864e2ab2 AL |
3875 | case MSR_IA32_XSS: |
3876 | if (!msr_info->host_initiated && | |
3877 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3878 | return 1; | |
3879 | msr_info->data = vcpu->arch.ia32_xss; | |
3880 | break; | |
84e0cefa JS |
3881 | case MSR_K7_CLK_CTL: |
3882 | /* | |
3883 | * Provide expected ramp-up count for K7. All other | |
3884 | * are set to zero, indicating minimum divisors for | |
3885 | * every field. | |
3886 | * | |
3887 | * This prevents guest kernels on AMD host with CPU | |
3888 | * type 6, model 8 and higher from exploding due to | |
3889 | * the rdmsr failing. | |
3890 | */ | |
609e36d3 | 3891 | msr_info->data = 0x20000000; |
84e0cefa | 3892 | break; |
55cd8e5a | 3893 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3894 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3895 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3896 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3897 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3898 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3899 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3900 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3901 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 3902 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
3903 | msr_info->index, &msr_info->data, |
3904 | msr_info->host_initiated); | |
91c9c3ed | 3905 | case MSR_IA32_BBL_CR_CTL3: |
3906 | /* This legacy MSR exists but isn't fully documented in current | |
3907 | * silicon. It is however accessed by winxp in very narrow | |
3908 | * scenarios where it sets bit #19, itself documented as | |
3909 | * a "reserved" bit. Best effort attempt to source coherent | |
3910 | * read data here should the balance of the register be | |
3911 | * interpreted by the guest: | |
3912 | * | |
3913 | * L2 cache control register 3: 64GB range, 256KB size, | |
3914 | * enabled, latency 0x1, configured | |
3915 | */ | |
609e36d3 | 3916 | msr_info->data = 0xbe702111; |
91c9c3ed | 3917 | break; |
2b036c6b | 3918 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3919 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3920 | return 1; |
609e36d3 | 3921 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
3922 | break; |
3923 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3924 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3925 | return 1; |
609e36d3 | 3926 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 3927 | break; |
db2336a8 | 3928 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
3929 | if (!msr_info->host_initiated && |
3930 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
3931 | return 1; | |
db2336a8 KH |
3932 | msr_info->data = vcpu->arch.msr_platform_info; |
3933 | break; | |
3934 | case MSR_MISC_FEATURES_ENABLES: | |
3935 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
3936 | break; | |
191c8137 BP |
3937 | case MSR_K7_HWCR: |
3938 | msr_info->data = vcpu->arch.msr_hwcr; | |
3939 | break; | |
15c4a640 | 3940 | default: |
c6702c9d | 3941 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3942 | return kvm_pmu_get_msr(vcpu, msr_info); |
6abe9c13 | 3943 | return KVM_MSR_RET_INVALID; |
15c4a640 | 3944 | } |
15c4a640 CO |
3945 | return 0; |
3946 | } | |
3947 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
3948 | ||
313a3dc7 CO |
3949 | /* |
3950 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
3951 | * | |
3952 | * @return number of msrs set successfully. | |
3953 | */ | |
3954 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
3955 | struct kvm_msr_entry *entries, | |
3956 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3957 | unsigned index, u64 *data)) | |
3958 | { | |
801e459a | 3959 | int i; |
313a3dc7 | 3960 | |
313a3dc7 CO |
3961 | for (i = 0; i < msrs->nmsrs; ++i) |
3962 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
3963 | break; | |
3964 | ||
313a3dc7 CO |
3965 | return i; |
3966 | } | |
3967 | ||
3968 | /* | |
3969 | * Read or write a bunch of msrs. Parameters are user addresses. | |
3970 | * | |
3971 | * @return number of msrs set successfully. | |
3972 | */ | |
3973 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
3974 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3975 | unsigned index, u64 *data), | |
3976 | int writeback) | |
3977 | { | |
3978 | struct kvm_msrs msrs; | |
3979 | struct kvm_msr_entry *entries; | |
3980 | int r, n; | |
3981 | unsigned size; | |
3982 | ||
3983 | r = -EFAULT; | |
0e96f31e | 3984 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
3985 | goto out; |
3986 | ||
3987 | r = -E2BIG; | |
3988 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
3989 | goto out; | |
3990 | ||
313a3dc7 | 3991 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
3992 | entries = memdup_user(user_msrs->entries, size); |
3993 | if (IS_ERR(entries)) { | |
3994 | r = PTR_ERR(entries); | |
313a3dc7 | 3995 | goto out; |
ff5c2c03 | 3996 | } |
313a3dc7 CO |
3997 | |
3998 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
3999 | if (r < 0) | |
4000 | goto out_free; | |
4001 | ||
4002 | r = -EFAULT; | |
4003 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
4004 | goto out_free; | |
4005 | ||
4006 | r = n; | |
4007 | ||
4008 | out_free: | |
7a73c028 | 4009 | kfree(entries); |
313a3dc7 CO |
4010 | out: |
4011 | return r; | |
4012 | } | |
4013 | ||
4d5422ce WL |
4014 | static inline bool kvm_can_mwait_in_guest(void) |
4015 | { | |
4016 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
4017 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
4018 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
4019 | } |
4020 | ||
c21d54f0 VK |
4021 | static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, |
4022 | struct kvm_cpuid2 __user *cpuid_arg) | |
4023 | { | |
4024 | struct kvm_cpuid2 cpuid; | |
4025 | int r; | |
4026 | ||
4027 | r = -EFAULT; | |
4028 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
4029 | return r; | |
4030 | ||
4031 | r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
4032 | if (r) | |
4033 | return r; | |
4034 | ||
4035 | r = -EFAULT; | |
4036 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
4037 | return r; | |
4038 | ||
4039 | return 0; | |
4040 | } | |
4041 | ||
784aa3d7 | 4042 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 4043 | { |
4d5422ce | 4044 | int r = 0; |
018d00d2 ZX |
4045 | |
4046 | switch (ext) { | |
4047 | case KVM_CAP_IRQCHIP: | |
4048 | case KVM_CAP_HLT: | |
4049 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 4050 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 4051 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 4052 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 4053 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 4054 | case KVM_CAP_PIT: |
a28e4f5a | 4055 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 4056 | case KVM_CAP_MP_STATE: |
ed848624 | 4057 | case KVM_CAP_SYNC_MMU: |
a355c85c | 4058 | case KVM_CAP_USER_NMI: |
52d939a0 | 4059 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 4060 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 4061 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 4062 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 4063 | case KVM_CAP_PIT2: |
e9f42757 | 4064 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 4065 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
3cfc3092 | 4066 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 4067 | case KVM_CAP_HYPERV: |
10388a07 | 4068 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 4069 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 4070 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 4071 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 4072 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 4073 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 4074 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 4075 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 4076 | case KVM_CAP_HYPERV_CPUID: |
644f7067 | 4077 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
c21d54f0 | 4078 | case KVM_CAP_SYS_HYPERV_CPUID: |
ab9f4ecb | 4079 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 4080 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 4081 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 4082 | case KVM_CAP_XSAVE: |
344d9588 | 4083 | case KVM_CAP_ASYNC_PF: |
72de5fa4 | 4084 | case KVM_CAP_ASYNC_PF_INT: |
92a1f12d | 4085 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 4086 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 4087 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 4088 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 4089 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 4090 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 4091 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 4092 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 4093 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 4094 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 4095 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 4096 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 4097 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 4098 | case KVM_CAP_EXCEPTION_PAYLOAD: |
b9b2782c | 4099 | case KVM_CAP_SET_GUEST_DEBUG: |
1aa561b1 | 4100 | case KVM_CAP_LAST_CPU: |
1ae09954 | 4101 | case KVM_CAP_X86_USER_SPACE_MSR: |
1a155254 | 4102 | case KVM_CAP_X86_MSR_FILTER: |
66570e96 | 4103 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
fe7e9488 SC |
4104 | #ifdef CONFIG_X86_SGX_KVM |
4105 | case KVM_CAP_SGX_ATTRIBUTE: | |
4106 | #endif | |
54526d1f | 4107 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
6dba9403 | 4108 | case KVM_CAP_SREGS2: |
19238e75 | 4109 | case KVM_CAP_EXIT_ON_EMULATION_FAILURE: |
018d00d2 ZX |
4110 | r = 1; |
4111 | break; | |
0dbb1123 AK |
4112 | case KVM_CAP_EXIT_HYPERCALL: |
4113 | r = KVM_EXIT_HYPERCALL_VALID_MASK; | |
4114 | break; | |
7e582ccb ML |
4115 | case KVM_CAP_SET_GUEST_DEBUG2: |
4116 | return KVM_GUESTDBG_VALID_MASK; | |
b59b153d | 4117 | #ifdef CONFIG_KVM_XEN |
23200b7a JM |
4118 | case KVM_CAP_XEN_HVM: |
4119 | r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | | |
8d4e7e80 DW |
4120 | KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | |
4121 | KVM_XEN_HVM_CONFIG_SHARED_INFO; | |
30b5c851 DW |
4122 | if (sched_info_on()) |
4123 | r |= KVM_XEN_HVM_CONFIG_RUNSTATE; | |
23200b7a | 4124 | break; |
b59b153d | 4125 | #endif |
01643c51 KH |
4126 | case KVM_CAP_SYNC_REGS: |
4127 | r = KVM_SYNC_X86_VALID_FIELDS; | |
4128 | break; | |
e3fd9a93 PB |
4129 | case KVM_CAP_ADJUST_CLOCK: |
4130 | r = KVM_CLOCK_TSC_STABLE; | |
4131 | break; | |
4d5422ce | 4132 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
4133 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
4134 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
4135 | if(kvm_can_mwait_in_guest()) |
4136 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 4137 | break; |
6d396b55 PB |
4138 | case KVM_CAP_X86_SMM: |
4139 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
4140 | * and SMM handlers might indeed rely on 4G segment limits, | |
4141 | * so do not report SMM to be available if real mode is | |
4142 | * emulated via vm86 mode. Still, do not go to great lengths | |
4143 | * to avoid userspace's usage of the feature, because it is a | |
4144 | * fringe case that is not enabled except via specific settings | |
4145 | * of the module parameters. | |
4146 | */ | |
b3646477 | 4147 | r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); |
6d396b55 | 4148 | break; |
774ead3a | 4149 | case KVM_CAP_VAPIC: |
b3646477 | 4150 | r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); |
774ead3a | 4151 | break; |
f725230a | 4152 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
4153 | r = KVM_SOFT_MAX_VCPUS; |
4154 | break; | |
4155 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
4156 | r = KVM_MAX_VCPUS; |
4157 | break; | |
a86cb413 TH |
4158 | case KVM_CAP_MAX_VCPU_ID: |
4159 | r = KVM_MAX_VCPU_ID; | |
4160 | break; | |
a68a6a72 MT |
4161 | case KVM_CAP_PV_MMU: /* obsolete */ |
4162 | r = 0; | |
2f333bcb | 4163 | break; |
890ca9ae HY |
4164 | case KVM_CAP_MCE: |
4165 | r = KVM_MAX_MCE_BANKS; | |
4166 | break; | |
2d5b5a66 | 4167 | case KVM_CAP_XCRS: |
d366bf7e | 4168 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 4169 | break; |
92a1f12d JR |
4170 | case KVM_CAP_TSC_CONTROL: |
4171 | r = kvm_has_tsc_control; | |
4172 | break; | |
37131313 RK |
4173 | case KVM_CAP_X2APIC_API: |
4174 | r = KVM_X2APIC_API_VALID_FLAGS; | |
4175 | break; | |
8fcc4b59 | 4176 | case KVM_CAP_NESTED_STATE: |
33b22172 PB |
4177 | r = kvm_x86_ops.nested_ops->get_state ? |
4178 | kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; | |
8fcc4b59 | 4179 | break; |
344c6c80 | 4180 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4181 | r = kvm_x86_ops.enable_direct_tlbflush != NULL; |
5a0165f6 VK |
4182 | break; |
4183 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
33b22172 | 4184 | r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; |
344c6c80 | 4185 | break; |
3edd6839 MG |
4186 | case KVM_CAP_SMALLER_MAXPHYADDR: |
4187 | r = (int) allow_smaller_maxphyaddr; | |
4188 | break; | |
004a0124 AJ |
4189 | case KVM_CAP_STEAL_TIME: |
4190 | r = sched_info_on(); | |
4191 | break; | |
fe6b6bc8 CQ |
4192 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
4193 | if (kvm_has_bus_lock_exit) | |
4194 | r = KVM_BUS_LOCK_DETECTION_OFF | | |
4195 | KVM_BUS_LOCK_DETECTION_EXIT; | |
4196 | else | |
4197 | r = 0; | |
4198 | break; | |
018d00d2 | 4199 | default: |
018d00d2 ZX |
4200 | break; |
4201 | } | |
4202 | return r; | |
4203 | ||
4204 | } | |
4205 | ||
043405e1 CO |
4206 | long kvm_arch_dev_ioctl(struct file *filp, |
4207 | unsigned int ioctl, unsigned long arg) | |
4208 | { | |
4209 | void __user *argp = (void __user *)arg; | |
4210 | long r; | |
4211 | ||
4212 | switch (ioctl) { | |
4213 | case KVM_GET_MSR_INDEX_LIST: { | |
4214 | struct kvm_msr_list __user *user_msr_list = argp; | |
4215 | struct kvm_msr_list msr_list; | |
4216 | unsigned n; | |
4217 | ||
4218 | r = -EFAULT; | |
0e96f31e | 4219 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
4220 | goto out; |
4221 | n = msr_list.nmsrs; | |
62ef68bb | 4222 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 4223 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
4224 | goto out; |
4225 | r = -E2BIG; | |
e125e7b6 | 4226 | if (n < msr_list.nmsrs) |
043405e1 CO |
4227 | goto out; |
4228 | r = -EFAULT; | |
4229 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
4230 | num_msrs_to_save * sizeof(u32))) | |
4231 | goto out; | |
e125e7b6 | 4232 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 4233 | &emulated_msrs, |
62ef68bb | 4234 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
4235 | goto out; |
4236 | r = 0; | |
4237 | break; | |
4238 | } | |
9c15bb1d BP |
4239 | case KVM_GET_SUPPORTED_CPUID: |
4240 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
4241 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
4242 | struct kvm_cpuid2 cpuid; | |
4243 | ||
4244 | r = -EFAULT; | |
0e96f31e | 4245 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 4246 | goto out; |
9c15bb1d BP |
4247 | |
4248 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
4249 | ioctl); | |
674eea0f AK |
4250 | if (r) |
4251 | goto out; | |
4252 | ||
4253 | r = -EFAULT; | |
0e96f31e | 4254 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
4255 | goto out; |
4256 | r = 0; | |
4257 | break; | |
4258 | } | |
cf6c26ec | 4259 | case KVM_X86_GET_MCE_CAP_SUPPORTED: |
890ca9ae | 4260 | r = -EFAULT; |
c45dcc71 AR |
4261 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
4262 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
4263 | goto out; |
4264 | r = 0; | |
4265 | break; | |
801e459a TL |
4266 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
4267 | struct kvm_msr_list __user *user_msr_list = argp; | |
4268 | struct kvm_msr_list msr_list; | |
4269 | unsigned int n; | |
4270 | ||
4271 | r = -EFAULT; | |
4272 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
4273 | goto out; | |
4274 | n = msr_list.nmsrs; | |
4275 | msr_list.nmsrs = num_msr_based_features; | |
4276 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
4277 | goto out; | |
4278 | r = -E2BIG; | |
4279 | if (n < msr_list.nmsrs) | |
4280 | goto out; | |
4281 | r = -EFAULT; | |
4282 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
4283 | num_msr_based_features * sizeof(u32))) | |
4284 | goto out; | |
4285 | r = 0; | |
4286 | break; | |
4287 | } | |
4288 | case KVM_GET_MSRS: | |
4289 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
4290 | break; | |
c21d54f0 VK |
4291 | case KVM_GET_SUPPORTED_HV_CPUID: |
4292 | r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); | |
4293 | break; | |
043405e1 CO |
4294 | default: |
4295 | r = -EINVAL; | |
cf6c26ec | 4296 | break; |
043405e1 CO |
4297 | } |
4298 | out: | |
4299 | return r; | |
4300 | } | |
4301 | ||
f5f48ee1 SY |
4302 | static void wbinvd_ipi(void *garbage) |
4303 | { | |
4304 | wbinvd(); | |
4305 | } | |
4306 | ||
4307 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4308 | { | |
e0f0bbc5 | 4309 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
4310 | } |
4311 | ||
313a3dc7 CO |
4312 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
4313 | { | |
f5f48ee1 SY |
4314 | /* Address WBINVD may be executed by guest */ |
4315 | if (need_emulate_wbinvd(vcpu)) { | |
b3646477 | 4316 | if (static_call(kvm_x86_has_wbinvd_exit)()) |
f5f48ee1 SY |
4317 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); |
4318 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
4319 | smp_call_function_single(vcpu->cpu, | |
4320 | wbinvd_ipi, NULL, 1); | |
4321 | } | |
4322 | ||
b3646477 | 4323 | static_call(kvm_x86_vcpu_load)(vcpu, cpu); |
8f6055cb | 4324 | |
37486135 BM |
4325 | /* Save host pkru register if supported */ |
4326 | vcpu->arch.host_pkru = read_pkru(); | |
4327 | ||
0dd6a6ed ZA |
4328 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
4329 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
4330 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
4331 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 4332 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 4333 | } |
8f6055cb | 4334 | |
b0c39dc6 | 4335 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 4336 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 4337 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
4338 | if (tsc_delta < 0) |
4339 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 4340 | |
b0c39dc6 | 4341 | if (kvm_check_tsc_unstable()) { |
9b399dfd | 4342 | u64 offset = kvm_compute_l1_tsc_offset(vcpu, |
b183aa58 | 4343 | vcpu->arch.last_guest_tsc); |
a545ab6a | 4344 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 4345 | vcpu->arch.tsc_catchup = 1; |
c285545f | 4346 | } |
a749e247 PB |
4347 | |
4348 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
4349 | kvm_lapic_restart_hv_timer(vcpu); | |
4350 | ||
d98d07ca MT |
4351 | /* |
4352 | * On a host with synchronized TSC, there is no need to update | |
4353 | * kvmclock on vcpu->cpu migration | |
4354 | */ | |
4355 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 4356 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 4357 | if (vcpu->cpu != cpu) |
1bd2009e | 4358 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 4359 | vcpu->cpu = cpu; |
6b7d7e76 | 4360 | } |
c9aaa895 | 4361 | |
c9aaa895 | 4362 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
4363 | } |
4364 | ||
0b9f6c46 PX |
4365 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
4366 | { | |
3c811b0f DW |
4367 | struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; |
4368 | struct kvm_steal_time __user *st; | |
4369 | struct kvm_memslots *slots; | |
4370 | static const u8 preempted = KVM_VCPU_PREEMPTED; | |
b0431382 | 4371 | |
0b9f6c46 PX |
4372 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
4373 | return; | |
4374 | ||
a6bd811f | 4375 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
4376 | return; |
4377 | ||
3c811b0f DW |
4378 | /* This happens on process exit */ |
4379 | if (unlikely(current->mm != vcpu->kvm->mm)) | |
9c1a0744 | 4380 | return; |
b0431382 | 4381 | |
3c811b0f DW |
4382 | slots = kvm_memslots(vcpu->kvm); |
4383 | ||
4384 | if (unlikely(slots->generation != ghc->generation || | |
4385 | kvm_is_error_hva(ghc->hva) || !ghc->memslot)) | |
4386 | return; | |
0b9f6c46 | 4387 | |
3c811b0f DW |
4388 | st = (struct kvm_steal_time __user *)ghc->hva; |
4389 | BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted)); | |
0b9f6c46 | 4390 | |
3c811b0f DW |
4391 | if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted))) |
4392 | vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; | |
4393 | ||
4394 | mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); | |
0b9f6c46 PX |
4395 | } |
4396 | ||
313a3dc7 CO |
4397 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
4398 | { | |
9c1a0744 WL |
4399 | int idx; |
4400 | ||
f1c6366e | 4401 | if (vcpu->preempted && !vcpu->arch.guest_state_protected) |
b3646477 | 4402 | vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); |
de63ad4c | 4403 | |
9c1a0744 WL |
4404 | /* |
4405 | * Take the srcu lock as memslots will be accessed to check the gfn | |
4406 | * cache generation against the memslots generation. | |
4407 | */ | |
4408 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
30b5c851 DW |
4409 | if (kvm_xen_msr_enabled(vcpu->kvm)) |
4410 | kvm_xen_runstate_set_preempted(vcpu); | |
4411 | else | |
4412 | kvm_steal_time_set_preempted(vcpu); | |
9c1a0744 | 4413 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
30b5c851 | 4414 | |
b3646477 | 4415 | static_call(kvm_x86_vcpu_put)(vcpu); |
4ea1636b | 4416 | vcpu->arch.last_host_tsc = rdtsc(); |
313a3dc7 CO |
4417 | } |
4418 | ||
313a3dc7 CO |
4419 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
4420 | struct kvm_lapic_state *s) | |
4421 | { | |
6a849d3d | 4422 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); |
d62caabb | 4423 | |
a92e2543 | 4424 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
4425 | } |
4426 | ||
4427 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
4428 | struct kvm_lapic_state *s) | |
4429 | { | |
a92e2543 RK |
4430 | int r; |
4431 | ||
4432 | r = kvm_apic_set_state(vcpu, s); | |
4433 | if (r) | |
4434 | return r; | |
cb142eb7 | 4435 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
4436 | |
4437 | return 0; | |
4438 | } | |
4439 | ||
127a457a MG |
4440 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
4441 | { | |
71cc849b PB |
4442 | /* |
4443 | * We can accept userspace's request for interrupt injection | |
4444 | * as long as we have a place to store the interrupt number. | |
4445 | * The actual injection will happen when the CPU is able to | |
4446 | * deliver the interrupt. | |
4447 | */ | |
4448 | if (kvm_cpu_has_extint(vcpu)) | |
4449 | return false; | |
4450 | ||
4451 | /* Acknowledging ExtINT does not happen if LINT0 is masked. */ | |
127a457a MG |
4452 | return (!lapic_in_kernel(vcpu) || |
4453 | kvm_apic_accept_pic_intr(vcpu)); | |
4454 | } | |
4455 | ||
782d422b MG |
4456 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) |
4457 | { | |
fa7a549d PB |
4458 | /* |
4459 | * Do not cause an interrupt window exit if an exception | |
4460 | * is pending or an event needs reinjection; userspace | |
4461 | * might want to inject the interrupt manually using KVM_SET_REGS | |
4462 | * or KVM_SET_SREGS. For that to work, we must be at an | |
4463 | * instruction boundary and with no events half-injected. | |
4464 | */ | |
4465 | return (kvm_arch_interrupt_allowed(vcpu) && | |
4466 | kvm_cpu_accept_dm_intr(vcpu) && | |
4467 | !kvm_event_needs_reinjection(vcpu) && | |
4468 | !vcpu->arch.exception.pending); | |
782d422b MG |
4469 | } |
4470 | ||
f77bc6a4 ZX |
4471 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
4472 | struct kvm_interrupt *irq) | |
4473 | { | |
02cdb50f | 4474 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 4475 | return -EINVAL; |
1c1a9ce9 SR |
4476 | |
4477 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
4478 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
4479 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4480 | return 0; | |
4481 | } | |
4482 | ||
4483 | /* | |
4484 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
4485 | * fail for in-kernel 8259. | |
4486 | */ | |
4487 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 4488 | return -ENXIO; |
f77bc6a4 | 4489 | |
1c1a9ce9 SR |
4490 | if (vcpu->arch.pending_external_vector != -1) |
4491 | return -EEXIST; | |
f77bc6a4 | 4492 | |
1c1a9ce9 | 4493 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 4494 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
4495 | return 0; |
4496 | } | |
4497 | ||
c4abb7c9 JK |
4498 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
4499 | { | |
c4abb7c9 | 4500 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
4501 | |
4502 | return 0; | |
4503 | } | |
4504 | ||
f077825a PB |
4505 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
4506 | { | |
64d60670 PB |
4507 | kvm_make_request(KVM_REQ_SMI, vcpu); |
4508 | ||
f077825a PB |
4509 | return 0; |
4510 | } | |
4511 | ||
b209749f AK |
4512 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
4513 | struct kvm_tpr_access_ctl *tac) | |
4514 | { | |
4515 | if (tac->flags) | |
4516 | return -EINVAL; | |
4517 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
4518 | return 0; | |
4519 | } | |
4520 | ||
890ca9ae HY |
4521 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
4522 | u64 mcg_cap) | |
4523 | { | |
4524 | int r; | |
4525 | unsigned bank_num = mcg_cap & 0xff, bank; | |
4526 | ||
4527 | r = -EINVAL; | |
c4e0e4ab | 4528 | if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) |
890ca9ae | 4529 | goto out; |
c45dcc71 | 4530 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
4531 | goto out; |
4532 | r = 0; | |
4533 | vcpu->arch.mcg_cap = mcg_cap; | |
4534 | /* Init IA32_MCG_CTL to all 1s */ | |
4535 | if (mcg_cap & MCG_CTL_P) | |
4536 | vcpu->arch.mcg_ctl = ~(u64)0; | |
4537 | /* Init IA32_MCi_CTL to all 1s */ | |
4538 | for (bank = 0; bank < bank_num; bank++) | |
4539 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 | 4540 | |
b3646477 | 4541 | static_call(kvm_x86_setup_mce)(vcpu); |
890ca9ae HY |
4542 | out: |
4543 | return r; | |
4544 | } | |
4545 | ||
4546 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
4547 | struct kvm_x86_mce *mce) | |
4548 | { | |
4549 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
4550 | unsigned bank_num = mcg_cap & 0xff; | |
4551 | u64 *banks = vcpu->arch.mce_banks; | |
4552 | ||
4553 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
4554 | return -EINVAL; | |
4555 | /* | |
4556 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
4557 | * reporting is disabled | |
4558 | */ | |
4559 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
4560 | vcpu->arch.mcg_ctl != ~(u64)0) | |
4561 | return 0; | |
4562 | banks += 4 * mce->bank; | |
4563 | /* | |
4564 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
4565 | * reporting is disabled for the bank | |
4566 | */ | |
4567 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
4568 | return 0; | |
4569 | if (mce->status & MCI_STATUS_UC) { | |
4570 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 4571 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 4572 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
4573 | return 0; |
4574 | } | |
4575 | if (banks[1] & MCI_STATUS_VAL) | |
4576 | mce->status |= MCI_STATUS_OVER; | |
4577 | banks[2] = mce->addr; | |
4578 | banks[3] = mce->misc; | |
4579 | vcpu->arch.mcg_status = mce->mcg_status; | |
4580 | banks[1] = mce->status; | |
4581 | kvm_queue_exception(vcpu, MC_VECTOR); | |
4582 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
4583 | || !(banks[1] & MCI_STATUS_UC)) { | |
4584 | if (banks[1] & MCI_STATUS_VAL) | |
4585 | mce->status |= MCI_STATUS_OVER; | |
4586 | banks[2] = mce->addr; | |
4587 | banks[3] = mce->misc; | |
4588 | banks[1] = mce->status; | |
4589 | } else | |
4590 | banks[1] |= MCI_STATUS_OVER; | |
4591 | return 0; | |
4592 | } | |
4593 | ||
3cfc3092 JK |
4594 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
4595 | struct kvm_vcpu_events *events) | |
4596 | { | |
7460fb4a | 4597 | process_nmi(vcpu); |
59073aaf | 4598 | |
1f7becf1 JZ |
4599 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
4600 | process_smi(vcpu); | |
4601 | ||
a06230b6 OU |
4602 | /* |
4603 | * In guest mode, payload delivery should be deferred, | |
4604 | * so that the L1 hypervisor can intercept #PF before | |
4605 | * CR2 is modified (or intercept #DB before DR6 is | |
4606 | * modified under nVMX). Unless the per-VM capability, | |
4607 | * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of | |
4608 | * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we | |
4609 | * opportunistically defer the exception payload, deliver it if the | |
4610 | * capability hasn't been requested before processing a | |
4611 | * KVM_GET_VCPU_EVENTS. | |
4612 | */ | |
4613 | if (!vcpu->kvm->arch.exception_payload_enabled && | |
4614 | vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) | |
4615 | kvm_deliver_exception_payload(vcpu); | |
4616 | ||
664f8e26 | 4617 | /* |
59073aaf JM |
4618 | * The API doesn't provide the instruction length for software |
4619 | * exceptions, so don't report them. As long as the guest RIP | |
4620 | * isn't advanced, we should expect to encounter the exception | |
4621 | * again. | |
664f8e26 | 4622 | */ |
59073aaf JM |
4623 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
4624 | events->exception.injected = 0; | |
4625 | events->exception.pending = 0; | |
4626 | } else { | |
4627 | events->exception.injected = vcpu->arch.exception.injected; | |
4628 | events->exception.pending = vcpu->arch.exception.pending; | |
4629 | /* | |
4630 | * For ABI compatibility, deliberately conflate | |
4631 | * pending and injected exceptions when | |
4632 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
4633 | */ | |
4634 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4635 | events->exception.injected |= | |
4636 | vcpu->arch.exception.pending; | |
4637 | } | |
3cfc3092 JK |
4638 | events->exception.nr = vcpu->arch.exception.nr; |
4639 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
4640 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
4641 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
4642 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 4643 | |
03b82a30 | 4644 | events->interrupt.injected = |
04140b41 | 4645 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 4646 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 4647 | events->interrupt.soft = 0; |
b3646477 | 4648 | events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
3cfc3092 JK |
4649 | |
4650 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 4651 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
b3646477 | 4652 | events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); |
97e69aa6 | 4653 | events->nmi.pad = 0; |
3cfc3092 | 4654 | |
66450a21 | 4655 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 4656 | |
f077825a PB |
4657 | events->smi.smm = is_smm(vcpu); |
4658 | events->smi.pending = vcpu->arch.smi_pending; | |
4659 | events->smi.smm_inside_nmi = | |
4660 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
4661 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
4662 | ||
dab4b911 | 4663 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
4664 | | KVM_VCPUEVENT_VALID_SHADOW |
4665 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
4666 | if (vcpu->kvm->arch.exception_payload_enabled) |
4667 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
4668 | ||
97e69aa6 | 4669 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
4670 | } |
4671 | ||
dc87275f | 4672 | static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); |
6ef4e07e | 4673 | |
3cfc3092 JK |
4674 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
4675 | struct kvm_vcpu_events *events) | |
4676 | { | |
dab4b911 | 4677 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 4678 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 4679 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf JM |
4680 | | KVM_VCPUEVENT_VALID_SMM |
4681 | | KVM_VCPUEVENT_VALID_PAYLOAD)) | |
3cfc3092 JK |
4682 | return -EINVAL; |
4683 | ||
59073aaf JM |
4684 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
4685 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4686 | return -EINVAL; | |
4687 | if (events->exception.pending) | |
4688 | events->exception.injected = 0; | |
4689 | else | |
4690 | events->exception_has_payload = 0; | |
4691 | } else { | |
4692 | events->exception.pending = 0; | |
4693 | events->exception_has_payload = 0; | |
4694 | } | |
4695 | ||
4696 | if ((events->exception.injected || events->exception.pending) && | |
4697 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
4698 | return -EINVAL; |
4699 | ||
28bf2888 DH |
4700 | /* INITs are latched while in SMM */ |
4701 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
4702 | (events->smi.smm || events->smi.pending) && | |
4703 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
4704 | return -EINVAL; | |
4705 | ||
7460fb4a | 4706 | process_nmi(vcpu); |
59073aaf JM |
4707 | vcpu->arch.exception.injected = events->exception.injected; |
4708 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
4709 | vcpu->arch.exception.nr = events->exception.nr; |
4710 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
4711 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
4712 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
4713 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 4714 | |
04140b41 | 4715 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
4716 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
4717 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 | 4718 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
b3646477 JB |
4719 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, |
4720 | events->interrupt.shadow); | |
3cfc3092 JK |
4721 | |
4722 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
4723 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
4724 | vcpu->arch.nmi_pending = events->nmi.pending; | |
b3646477 | 4725 | static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); |
3cfc3092 | 4726 | |
66450a21 | 4727 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 4728 | lapic_in_kernel(vcpu)) |
66450a21 | 4729 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 4730 | |
f077825a | 4731 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
310218e6 SC |
4732 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { |
4733 | kvm_x86_ops.nested_ops->leave_nested(vcpu); | |
dc87275f | 4734 | kvm_smm_changed(vcpu, events->smi.smm); |
310218e6 | 4735 | } |
6ef4e07e | 4736 | |
f077825a | 4737 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
4738 | |
4739 | if (events->smi.smm) { | |
4740 | if (events->smi.smm_inside_nmi) | |
4741 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 4742 | else |
f4ef1910 | 4743 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
4744 | } |
4745 | ||
4746 | if (lapic_in_kernel(vcpu)) { | |
4747 | if (events->smi.latched_init) | |
4748 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
4749 | else | |
4750 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
4751 | } |
4752 | } | |
4753 | ||
3842d135 AK |
4754 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
4755 | ||
3cfc3092 JK |
4756 | return 0; |
4757 | } | |
4758 | ||
a1efbe77 JK |
4759 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
4760 | struct kvm_debugregs *dbgregs) | |
4761 | { | |
73aaf249 JK |
4762 | unsigned long val; |
4763 | ||
a1efbe77 | 4764 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 4765 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 4766 | dbgregs->dr6 = val; |
a1efbe77 JK |
4767 | dbgregs->dr7 = vcpu->arch.dr7; |
4768 | dbgregs->flags = 0; | |
97e69aa6 | 4769 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
4770 | } |
4771 | ||
4772 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
4773 | struct kvm_debugregs *dbgregs) | |
4774 | { | |
4775 | if (dbgregs->flags) | |
4776 | return -EINVAL; | |
4777 | ||
fd238002 | 4778 | if (!kvm_dr6_valid(dbgregs->dr6)) |
d14bdb55 | 4779 | return -EINVAL; |
fd238002 | 4780 | if (!kvm_dr7_valid(dbgregs->dr7)) |
d14bdb55 PB |
4781 | return -EINVAL; |
4782 | ||
a1efbe77 | 4783 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 4784 | kvm_update_dr0123(vcpu); |
a1efbe77 JK |
4785 | vcpu->arch.dr6 = dbgregs->dr6; |
4786 | vcpu->arch.dr7 = dbgregs->dr7; | |
9926c9fd | 4787 | kvm_update_dr7(vcpu); |
a1efbe77 | 4788 | |
a1efbe77 JK |
4789 | return 0; |
4790 | } | |
4791 | ||
df1daba7 PB |
4792 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
4793 | ||
4794 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
4795 | { | |
b666a4b6 | 4796 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
400e4b20 | 4797 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
4798 | u64 valid; |
4799 | ||
4800 | /* | |
4801 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4802 | * leaves 0 and 1 in the loop below. | |
4803 | */ | |
4804 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
4805 | ||
4806 | /* Set XSTATE_BV */ | |
00c87e9a | 4807 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
4808 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
4809 | ||
4810 | /* | |
4811 | * Copy each region from the possibly compacted offset to the | |
4812 | * non-compacted offset. | |
4813 | */ | |
d91cab78 | 4814 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4815 | while (valid) { |
71ef4533 | 4816 | u32 size, offset, ecx, edx; |
abd16d68 SAS |
4817 | u64 xfeature_mask = valid & -valid; |
4818 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
71ef4533 DH |
4819 | void *src; |
4820 | ||
4821 | cpuid_count(XSTATE_CPUID, xfeature_nr, | |
4822 | &size, &offset, &ecx, &edx); | |
38cfd5e3 | 4823 | |
71ef4533 DH |
4824 | if (xfeature_nr == XFEATURE_PKRU) { |
4825 | memcpy(dest + offset, &vcpu->arch.pkru, | |
4826 | sizeof(vcpu->arch.pkru)); | |
4827 | } else { | |
4828 | src = get_xsave_addr(xsave, xfeature_nr); | |
4829 | if (src) | |
4830 | memcpy(dest + offset, src, size); | |
df1daba7 PB |
4831 | } |
4832 | ||
abd16d68 | 4833 | valid -= xfeature_mask; |
df1daba7 PB |
4834 | } |
4835 | } | |
4836 | ||
4837 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
4838 | { | |
b666a4b6 | 4839 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
df1daba7 PB |
4840 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
4841 | u64 valid; | |
4842 | ||
4843 | /* | |
4844 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4845 | * leaves 0 and 1 in the loop below. | |
4846 | */ | |
4847 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
4848 | ||
4849 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 4850 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 4851 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 4852 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
4853 | |
4854 | /* | |
4855 | * Copy each region from the non-compacted offset to the | |
4856 | * possibly compacted offset. | |
4857 | */ | |
d91cab78 | 4858 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4859 | while (valid) { |
71ef4533 | 4860 | u32 size, offset, ecx, edx; |
abd16d68 SAS |
4861 | u64 xfeature_mask = valid & -valid; |
4862 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
71ef4533 DH |
4863 | |
4864 | cpuid_count(XSTATE_CPUID, xfeature_nr, | |
4865 | &size, &offset, &ecx, &edx); | |
4866 | ||
4867 | if (xfeature_nr == XFEATURE_PKRU) { | |
4868 | memcpy(&vcpu->arch.pkru, src + offset, | |
4869 | sizeof(vcpu->arch.pkru)); | |
4870 | } else { | |
4871 | void *dest = get_xsave_addr(xsave, xfeature_nr); | |
4872 | ||
4873 | if (dest) | |
38cfd5e3 | 4874 | memcpy(dest, src + offset, size); |
ee4100da | 4875 | } |
df1daba7 | 4876 | |
abd16d68 | 4877 | valid -= xfeature_mask; |
df1daba7 PB |
4878 | } |
4879 | } | |
4880 | ||
2d5b5a66 SY |
4881 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
4882 | struct kvm_xsave *guest_xsave) | |
4883 | { | |
ed02b213 TL |
4884 | if (!vcpu->arch.guest_fpu) |
4885 | return; | |
4886 | ||
d366bf7e | 4887 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
4888 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
4889 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 4890 | } else { |
2d5b5a66 | 4891 | memcpy(guest_xsave->region, |
b666a4b6 | 4892 | &vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4893 | sizeof(struct fxregs_state)); |
2d5b5a66 | 4894 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 4895 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
4896 | } |
4897 | } | |
4898 | ||
a575813b WL |
4899 | #define XSAVE_MXCSR_OFFSET 24 |
4900 | ||
2d5b5a66 SY |
4901 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
4902 | struct kvm_xsave *guest_xsave) | |
4903 | { | |
ed02b213 TL |
4904 | u64 xstate_bv; |
4905 | u32 mxcsr; | |
4906 | ||
4907 | if (!vcpu->arch.guest_fpu) | |
4908 | return 0; | |
4909 | ||
4910 | xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
4911 | mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; | |
2d5b5a66 | 4912 | |
d366bf7e | 4913 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
4914 | /* |
4915 | * Here we allow setting states that are not present in | |
4916 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
4917 | * with old userspace. | |
4918 | */ | |
cfc48181 | 4919 | if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) |
d7876f1b | 4920 | return -EINVAL; |
df1daba7 | 4921 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 4922 | } else { |
a575813b WL |
4923 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
4924 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 4925 | return -EINVAL; |
b666a4b6 | 4926 | memcpy(&vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4927 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
4928 | } |
4929 | return 0; | |
4930 | } | |
4931 | ||
4932 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
4933 | struct kvm_xcrs *guest_xcrs) | |
4934 | { | |
d366bf7e | 4935 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
4936 | guest_xcrs->nr_xcrs = 0; |
4937 | return; | |
4938 | } | |
4939 | ||
4940 | guest_xcrs->nr_xcrs = 1; | |
4941 | guest_xcrs->flags = 0; | |
4942 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
4943 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
4944 | } | |
4945 | ||
4946 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
4947 | struct kvm_xcrs *guest_xcrs) | |
4948 | { | |
4949 | int i, r = 0; | |
4950 | ||
d366bf7e | 4951 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
4952 | return -EINVAL; |
4953 | ||
4954 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
4955 | return -EINVAL; | |
4956 | ||
4957 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
4958 | /* Only support XCR0 currently */ | |
c67a04cb | 4959 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 4960 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 4961 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
4962 | break; |
4963 | } | |
4964 | if (r) | |
4965 | r = -EINVAL; | |
4966 | return r; | |
4967 | } | |
4968 | ||
1c0b28c2 EM |
4969 | /* |
4970 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
4971 | * stopped by the hypervisor. This function will be called from the host only. | |
4972 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
4973 | * does not support pv clocks. | |
4974 | */ | |
4975 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
4976 | { | |
0b79459b | 4977 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 4978 | return -EINVAL; |
51d59c6b | 4979 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
4980 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
4981 | return 0; | |
4982 | } | |
4983 | ||
5c919412 AS |
4984 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
4985 | struct kvm_enable_cap *cap) | |
4986 | { | |
57b119da VK |
4987 | int r; |
4988 | uint16_t vmcs_version; | |
4989 | void __user *user_ptr; | |
4990 | ||
5c919412 AS |
4991 | if (cap->flags) |
4992 | return -EINVAL; | |
4993 | ||
4994 | switch (cap->cap) { | |
efc479e6 RK |
4995 | case KVM_CAP_HYPERV_SYNIC2: |
4996 | if (cap->args[0]) | |
4997 | return -EINVAL; | |
df561f66 | 4998 | fallthrough; |
b2869f28 | 4999 | |
5c919412 | 5000 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
5001 | if (!irqchip_in_kernel(vcpu->kvm)) |
5002 | return -EINVAL; | |
efc479e6 RK |
5003 | return kvm_hv_activate_synic(vcpu, cap->cap == |
5004 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 5005 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
33b22172 | 5006 | if (!kvm_x86_ops.nested_ops->enable_evmcs) |
5158917c | 5007 | return -ENOTTY; |
33b22172 | 5008 | r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); |
57b119da VK |
5009 | if (!r) { |
5010 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
5011 | if (copy_to_user(user_ptr, &vmcs_version, | |
5012 | sizeof(vmcs_version))) | |
5013 | r = -EFAULT; | |
5014 | } | |
5015 | return r; | |
344c6c80 | 5016 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 5017 | if (!kvm_x86_ops.enable_direct_tlbflush) |
344c6c80 TL |
5018 | return -ENOTTY; |
5019 | ||
b3646477 | 5020 | return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); |
57b119da | 5021 | |
644f7067 VK |
5022 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
5023 | return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); | |
5024 | ||
66570e96 OU |
5025 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
5026 | vcpu->arch.pv_cpuid.enforce = cap->args[0]; | |
01b4f510 OU |
5027 | if (vcpu->arch.pv_cpuid.enforce) |
5028 | kvm_update_pv_runtime(vcpu); | |
66570e96 OU |
5029 | |
5030 | return 0; | |
5c919412 AS |
5031 | default: |
5032 | return -EINVAL; | |
5033 | } | |
5034 | } | |
5035 | ||
313a3dc7 CO |
5036 | long kvm_arch_vcpu_ioctl(struct file *filp, |
5037 | unsigned int ioctl, unsigned long arg) | |
5038 | { | |
5039 | struct kvm_vcpu *vcpu = filp->private_data; | |
5040 | void __user *argp = (void __user *)arg; | |
5041 | int r; | |
d1ac91d8 | 5042 | union { |
6dba9403 | 5043 | struct kvm_sregs2 *sregs2; |
d1ac91d8 AK |
5044 | struct kvm_lapic_state *lapic; |
5045 | struct kvm_xsave *xsave; | |
5046 | struct kvm_xcrs *xcrs; | |
5047 | void *buffer; | |
5048 | } u; | |
5049 | ||
9b062471 CD |
5050 | vcpu_load(vcpu); |
5051 | ||
d1ac91d8 | 5052 | u.buffer = NULL; |
313a3dc7 CO |
5053 | switch (ioctl) { |
5054 | case KVM_GET_LAPIC: { | |
2204ae3c | 5055 | r = -EINVAL; |
bce87cce | 5056 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 5057 | goto out; |
254272ce BG |
5058 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
5059 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 5060 | |
b772ff36 | 5061 | r = -ENOMEM; |
d1ac91d8 | 5062 | if (!u.lapic) |
b772ff36 | 5063 | goto out; |
d1ac91d8 | 5064 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
5065 | if (r) |
5066 | goto out; | |
5067 | r = -EFAULT; | |
d1ac91d8 | 5068 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
5069 | goto out; |
5070 | r = 0; | |
5071 | break; | |
5072 | } | |
5073 | case KVM_SET_LAPIC: { | |
2204ae3c | 5074 | r = -EINVAL; |
bce87cce | 5075 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 5076 | goto out; |
ff5c2c03 | 5077 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
5078 | if (IS_ERR(u.lapic)) { |
5079 | r = PTR_ERR(u.lapic); | |
5080 | goto out_nofree; | |
5081 | } | |
ff5c2c03 | 5082 | |
d1ac91d8 | 5083 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
5084 | break; |
5085 | } | |
f77bc6a4 ZX |
5086 | case KVM_INTERRUPT: { |
5087 | struct kvm_interrupt irq; | |
5088 | ||
5089 | r = -EFAULT; | |
0e96f31e | 5090 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
5091 | goto out; |
5092 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
5093 | break; |
5094 | } | |
c4abb7c9 JK |
5095 | case KVM_NMI: { |
5096 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
5097 | break; |
5098 | } | |
f077825a PB |
5099 | case KVM_SMI: { |
5100 | r = kvm_vcpu_ioctl_smi(vcpu); | |
5101 | break; | |
5102 | } | |
313a3dc7 CO |
5103 | case KVM_SET_CPUID: { |
5104 | struct kvm_cpuid __user *cpuid_arg = argp; | |
5105 | struct kvm_cpuid cpuid; | |
5106 | ||
5107 | r = -EFAULT; | |
0e96f31e | 5108 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
5109 | goto out; |
5110 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
5111 | break; |
5112 | } | |
07716717 DK |
5113 | case KVM_SET_CPUID2: { |
5114 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
5115 | struct kvm_cpuid2 cpuid; | |
5116 | ||
5117 | r = -EFAULT; | |
0e96f31e | 5118 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
5119 | goto out; |
5120 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 5121 | cpuid_arg->entries); |
07716717 DK |
5122 | break; |
5123 | } | |
5124 | case KVM_GET_CPUID2: { | |
5125 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
5126 | struct kvm_cpuid2 cpuid; | |
5127 | ||
5128 | r = -EFAULT; | |
0e96f31e | 5129 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
5130 | goto out; |
5131 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 5132 | cpuid_arg->entries); |
07716717 DK |
5133 | if (r) |
5134 | goto out; | |
5135 | r = -EFAULT; | |
0e96f31e | 5136 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
5137 | goto out; |
5138 | r = 0; | |
5139 | break; | |
5140 | } | |
801e459a TL |
5141 | case KVM_GET_MSRS: { |
5142 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 5143 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 5144 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 5145 | break; |
801e459a TL |
5146 | } |
5147 | case KVM_SET_MSRS: { | |
5148 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 5149 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 5150 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 5151 | break; |
801e459a | 5152 | } |
b209749f AK |
5153 | case KVM_TPR_ACCESS_REPORTING: { |
5154 | struct kvm_tpr_access_ctl tac; | |
5155 | ||
5156 | r = -EFAULT; | |
0e96f31e | 5157 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
5158 | goto out; |
5159 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
5160 | if (r) | |
5161 | goto out; | |
5162 | r = -EFAULT; | |
0e96f31e | 5163 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
5164 | goto out; |
5165 | r = 0; | |
5166 | break; | |
5167 | }; | |
b93463aa AK |
5168 | case KVM_SET_VAPIC_ADDR: { |
5169 | struct kvm_vapic_addr va; | |
7301d6ab | 5170 | int idx; |
b93463aa AK |
5171 | |
5172 | r = -EINVAL; | |
35754c98 | 5173 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
5174 | goto out; |
5175 | r = -EFAULT; | |
0e96f31e | 5176 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 5177 | goto out; |
7301d6ab | 5178 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 5179 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 5180 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
5181 | break; |
5182 | } | |
890ca9ae HY |
5183 | case KVM_X86_SETUP_MCE: { |
5184 | u64 mcg_cap; | |
5185 | ||
5186 | r = -EFAULT; | |
0e96f31e | 5187 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
5188 | goto out; |
5189 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
5190 | break; | |
5191 | } | |
5192 | case KVM_X86_SET_MCE: { | |
5193 | struct kvm_x86_mce mce; | |
5194 | ||
5195 | r = -EFAULT; | |
0e96f31e | 5196 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
5197 | goto out; |
5198 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
5199 | break; | |
5200 | } | |
3cfc3092 JK |
5201 | case KVM_GET_VCPU_EVENTS: { |
5202 | struct kvm_vcpu_events events; | |
5203 | ||
5204 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
5205 | ||
5206 | r = -EFAULT; | |
5207 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
5208 | break; | |
5209 | r = 0; | |
5210 | break; | |
5211 | } | |
5212 | case KVM_SET_VCPU_EVENTS: { | |
5213 | struct kvm_vcpu_events events; | |
5214 | ||
5215 | r = -EFAULT; | |
5216 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
5217 | break; | |
5218 | ||
5219 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
5220 | break; | |
5221 | } | |
a1efbe77 JK |
5222 | case KVM_GET_DEBUGREGS: { |
5223 | struct kvm_debugregs dbgregs; | |
5224 | ||
5225 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
5226 | ||
5227 | r = -EFAULT; | |
5228 | if (copy_to_user(argp, &dbgregs, | |
5229 | sizeof(struct kvm_debugregs))) | |
5230 | break; | |
5231 | r = 0; | |
5232 | break; | |
5233 | } | |
5234 | case KVM_SET_DEBUGREGS: { | |
5235 | struct kvm_debugregs dbgregs; | |
5236 | ||
5237 | r = -EFAULT; | |
5238 | if (copy_from_user(&dbgregs, argp, | |
5239 | sizeof(struct kvm_debugregs))) | |
5240 | break; | |
5241 | ||
5242 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
5243 | break; | |
5244 | } | |
2d5b5a66 | 5245 | case KVM_GET_XSAVE: { |
254272ce | 5246 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5247 | r = -ENOMEM; |
d1ac91d8 | 5248 | if (!u.xsave) |
2d5b5a66 SY |
5249 | break; |
5250 | ||
d1ac91d8 | 5251 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5252 | |
5253 | r = -EFAULT; | |
d1ac91d8 | 5254 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
5255 | break; |
5256 | r = 0; | |
5257 | break; | |
5258 | } | |
5259 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 5260 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
5261 | if (IS_ERR(u.xsave)) { |
5262 | r = PTR_ERR(u.xsave); | |
5263 | goto out_nofree; | |
5264 | } | |
2d5b5a66 | 5265 | |
d1ac91d8 | 5266 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5267 | break; |
5268 | } | |
5269 | case KVM_GET_XCRS: { | |
254272ce | 5270 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5271 | r = -ENOMEM; |
d1ac91d8 | 5272 | if (!u.xcrs) |
2d5b5a66 SY |
5273 | break; |
5274 | ||
d1ac91d8 | 5275 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5276 | |
5277 | r = -EFAULT; | |
d1ac91d8 | 5278 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
5279 | sizeof(struct kvm_xcrs))) |
5280 | break; | |
5281 | r = 0; | |
5282 | break; | |
5283 | } | |
5284 | case KVM_SET_XCRS: { | |
ff5c2c03 | 5285 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
5286 | if (IS_ERR(u.xcrs)) { |
5287 | r = PTR_ERR(u.xcrs); | |
5288 | goto out_nofree; | |
5289 | } | |
2d5b5a66 | 5290 | |
d1ac91d8 | 5291 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5292 | break; |
5293 | } | |
92a1f12d JR |
5294 | case KVM_SET_TSC_KHZ: { |
5295 | u32 user_tsc_khz; | |
5296 | ||
5297 | r = -EINVAL; | |
92a1f12d JR |
5298 | user_tsc_khz = (u32)arg; |
5299 | ||
26769f96 MT |
5300 | if (kvm_has_tsc_control && |
5301 | user_tsc_khz >= kvm_max_guest_tsc_khz) | |
92a1f12d JR |
5302 | goto out; |
5303 | ||
cc578287 ZA |
5304 | if (user_tsc_khz == 0) |
5305 | user_tsc_khz = tsc_khz; | |
5306 | ||
381d585c HZ |
5307 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
5308 | r = 0; | |
92a1f12d | 5309 | |
92a1f12d JR |
5310 | goto out; |
5311 | } | |
5312 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 5313 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
5314 | goto out; |
5315 | } | |
1c0b28c2 EM |
5316 | case KVM_KVMCLOCK_CTRL: { |
5317 | r = kvm_set_guest_paused(vcpu); | |
5318 | goto out; | |
5319 | } | |
5c919412 AS |
5320 | case KVM_ENABLE_CAP: { |
5321 | struct kvm_enable_cap cap; | |
5322 | ||
5323 | r = -EFAULT; | |
5324 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
5325 | goto out; | |
5326 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
5327 | break; | |
5328 | } | |
8fcc4b59 JM |
5329 | case KVM_GET_NESTED_STATE: { |
5330 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5331 | u32 user_data_size; | |
5332 | ||
5333 | r = -EINVAL; | |
33b22172 | 5334 | if (!kvm_x86_ops.nested_ops->get_state) |
8fcc4b59 JM |
5335 | break; |
5336 | ||
5337 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 5338 | r = -EFAULT; |
8fcc4b59 | 5339 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 5340 | break; |
8fcc4b59 | 5341 | |
33b22172 PB |
5342 | r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, |
5343 | user_data_size); | |
8fcc4b59 | 5344 | if (r < 0) |
26b471c7 | 5345 | break; |
8fcc4b59 JM |
5346 | |
5347 | if (r > user_data_size) { | |
5348 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
5349 | r = -EFAULT; |
5350 | else | |
5351 | r = -E2BIG; | |
5352 | break; | |
8fcc4b59 | 5353 | } |
26b471c7 | 5354 | |
8fcc4b59 JM |
5355 | r = 0; |
5356 | break; | |
5357 | } | |
5358 | case KVM_SET_NESTED_STATE: { | |
5359 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5360 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 5361 | int idx; |
8fcc4b59 JM |
5362 | |
5363 | r = -EINVAL; | |
33b22172 | 5364 | if (!kvm_x86_ops.nested_ops->set_state) |
8fcc4b59 JM |
5365 | break; |
5366 | ||
26b471c7 | 5367 | r = -EFAULT; |
8fcc4b59 | 5368 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 5369 | break; |
8fcc4b59 | 5370 | |
26b471c7 | 5371 | r = -EINVAL; |
8fcc4b59 | 5372 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 5373 | break; |
8fcc4b59 JM |
5374 | |
5375 | if (kvm_state.flags & | |
8cab6507 | 5376 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
cc440cda PB |
5377 | | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING |
5378 | | KVM_STATE_NESTED_GIF_SET)) | |
26b471c7 | 5379 | break; |
8fcc4b59 JM |
5380 | |
5381 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
5382 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
5383 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 5384 | break; |
8fcc4b59 | 5385 | |
ad5996d9 | 5386 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
33b22172 | 5387 | r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 5388 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
5389 | break; |
5390 | } | |
c21d54f0 VK |
5391 | case KVM_GET_SUPPORTED_HV_CPUID: |
5392 | r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); | |
2bc39970 | 5393 | break; |
b59b153d | 5394 | #ifdef CONFIG_KVM_XEN |
3e324615 DW |
5395 | case KVM_XEN_VCPU_GET_ATTR: { |
5396 | struct kvm_xen_vcpu_attr xva; | |
5397 | ||
5398 | r = -EFAULT; | |
5399 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
5400 | goto out; | |
5401 | r = kvm_xen_vcpu_get_attr(vcpu, &xva); | |
5402 | if (!r && copy_to_user(argp, &xva, sizeof(xva))) | |
5403 | r = -EFAULT; | |
5404 | break; | |
5405 | } | |
5406 | case KVM_XEN_VCPU_SET_ATTR: { | |
5407 | struct kvm_xen_vcpu_attr xva; | |
5408 | ||
5409 | r = -EFAULT; | |
5410 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
5411 | goto out; | |
5412 | r = kvm_xen_vcpu_set_attr(vcpu, &xva); | |
5413 | break; | |
5414 | } | |
b59b153d | 5415 | #endif |
6dba9403 ML |
5416 | case KVM_GET_SREGS2: { |
5417 | u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); | |
5418 | r = -ENOMEM; | |
5419 | if (!u.sregs2) | |
5420 | goto out; | |
5421 | __get_sregs2(vcpu, u.sregs2); | |
5422 | r = -EFAULT; | |
5423 | if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) | |
5424 | goto out; | |
5425 | r = 0; | |
5426 | break; | |
5427 | } | |
5428 | case KVM_SET_SREGS2: { | |
5429 | u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); | |
5430 | if (IS_ERR(u.sregs2)) { | |
5431 | r = PTR_ERR(u.sregs2); | |
5432 | u.sregs2 = NULL; | |
5433 | goto out; | |
5434 | } | |
5435 | r = __set_sregs2(vcpu, u.sregs2); | |
5436 | break; | |
5437 | } | |
313a3dc7 CO |
5438 | default: |
5439 | r = -EINVAL; | |
5440 | } | |
5441 | out: | |
d1ac91d8 | 5442 | kfree(u.buffer); |
9b062471 CD |
5443 | out_nofree: |
5444 | vcpu_put(vcpu); | |
313a3dc7 CO |
5445 | return r; |
5446 | } | |
5447 | ||
1499fa80 | 5448 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
5449 | { |
5450 | return VM_FAULT_SIGBUS; | |
5451 | } | |
5452 | ||
1fe779f8 CO |
5453 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
5454 | { | |
5455 | int ret; | |
5456 | ||
5457 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 5458 | return -EINVAL; |
b3646477 | 5459 | ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); |
1fe779f8 CO |
5460 | return ret; |
5461 | } | |
5462 | ||
b927a3ce SY |
5463 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
5464 | u64 ident_addr) | |
5465 | { | |
b3646477 | 5466 | return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); |
b927a3ce SY |
5467 | } |
5468 | ||
1fe779f8 | 5469 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 5470 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
5471 | { |
5472 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
5473 | return -EINVAL; | |
5474 | ||
79fac95e | 5475 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
5476 | |
5477 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 5478 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 5479 | |
79fac95e | 5480 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
5481 | return 0; |
5482 | } | |
5483 | ||
bc8a3d89 | 5484 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 5485 | { |
39de71ec | 5486 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
5487 | } |
5488 | ||
1fe779f8 CO |
5489 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
5490 | { | |
90bca052 | 5491 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5492 | int r; |
5493 | ||
5494 | r = 0; | |
5495 | switch (chip->chip_id) { | |
5496 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 5497 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
5498 | sizeof(struct kvm_pic_state)); |
5499 | break; | |
5500 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 5501 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
5502 | sizeof(struct kvm_pic_state)); |
5503 | break; | |
5504 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5505 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5506 | break; |
5507 | default: | |
5508 | r = -EINVAL; | |
5509 | break; | |
5510 | } | |
5511 | return r; | |
5512 | } | |
5513 | ||
5514 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
5515 | { | |
90bca052 | 5516 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5517 | int r; |
5518 | ||
5519 | r = 0; | |
5520 | switch (chip->chip_id) { | |
5521 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
5522 | spin_lock(&pic->lock); |
5523 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 5524 | sizeof(struct kvm_pic_state)); |
90bca052 | 5525 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5526 | break; |
5527 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
5528 | spin_lock(&pic->lock); |
5529 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 5530 | sizeof(struct kvm_pic_state)); |
90bca052 | 5531 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5532 | break; |
5533 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5534 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5535 | break; |
5536 | default: | |
5537 | r = -EINVAL; | |
5538 | break; | |
5539 | } | |
90bca052 | 5540 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
5541 | return r; |
5542 | } | |
5543 | ||
e0f63cb9 SY |
5544 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
5545 | { | |
34f3941c RK |
5546 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
5547 | ||
5548 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
5549 | ||
5550 | mutex_lock(&kps->lock); | |
5551 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
5552 | mutex_unlock(&kps->lock); | |
2da29bcc | 5553 | return 0; |
e0f63cb9 SY |
5554 | } |
5555 | ||
5556 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
5557 | { | |
0185604c | 5558 | int i; |
09edea72 RK |
5559 | struct kvm_pit *pit = kvm->arch.vpit; |
5560 | ||
5561 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 5562 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 5563 | for (i = 0; i < 3; i++) |
09edea72 RK |
5564 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
5565 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 5566 | return 0; |
e9f42757 BK |
5567 | } |
5568 | ||
5569 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5570 | { | |
e9f42757 BK |
5571 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
5572 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
5573 | sizeof(ps->channels)); | |
5574 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
5575 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 5576 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 5577 | return 0; |
e9f42757 BK |
5578 | } |
5579 | ||
5580 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5581 | { | |
2da29bcc | 5582 | int start = 0; |
0185604c | 5583 | int i; |
e9f42757 | 5584 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
5585 | struct kvm_pit *pit = kvm->arch.vpit; |
5586 | ||
5587 | mutex_lock(&pit->pit_state.lock); | |
5588 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
5589 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
5590 | if (!prev_legacy && cur_legacy) | |
5591 | start = 1; | |
09edea72 RK |
5592 | memcpy(&pit->pit_state.channels, &ps->channels, |
5593 | sizeof(pit->pit_state.channels)); | |
5594 | pit->pit_state.flags = ps->flags; | |
0185604c | 5595 | for (i = 0; i < 3; i++) |
09edea72 | 5596 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 5597 | start && i == 0); |
09edea72 | 5598 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 5599 | return 0; |
e0f63cb9 SY |
5600 | } |
5601 | ||
52d939a0 MT |
5602 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
5603 | struct kvm_reinject_control *control) | |
5604 | { | |
71474e2f RK |
5605 | struct kvm_pit *pit = kvm->arch.vpit; |
5606 | ||
71474e2f RK |
5607 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
5608 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
5609 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
5610 | */ | |
5611 | mutex_lock(&pit->pit_state.lock); | |
5612 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
5613 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 5614 | |
52d939a0 MT |
5615 | return 0; |
5616 | } | |
5617 | ||
0dff0846 | 5618 | void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) |
5bb064dc | 5619 | { |
a018eba5 | 5620 | |
88178fd4 | 5621 | /* |
a018eba5 SC |
5622 | * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called |
5623 | * before reporting dirty_bitmap to userspace. KVM flushes the buffers | |
5624 | * on all VM-Exits, thus we only need to kick running vCPUs to force a | |
5625 | * VM-Exit. | |
88178fd4 | 5626 | */ |
a018eba5 SC |
5627 | struct kvm_vcpu *vcpu; |
5628 | int i; | |
5629 | ||
5630 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5631 | kvm_vcpu_kick(vcpu); | |
5bb064dc ZX |
5632 | } |
5633 | ||
aa2fbe6d YZ |
5634 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
5635 | bool line_status) | |
23d43cf9 CD |
5636 | { |
5637 | if (!irqchip_in_kernel(kvm)) | |
5638 | return -ENXIO; | |
5639 | ||
5640 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
5641 | irq_event->irq, irq_event->level, |
5642 | line_status); | |
23d43cf9 CD |
5643 | return 0; |
5644 | } | |
5645 | ||
e5d83c74 PB |
5646 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
5647 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
5648 | { |
5649 | int r; | |
5650 | ||
5651 | if (cap->flags) | |
5652 | return -EINVAL; | |
5653 | ||
5654 | switch (cap->cap) { | |
5655 | case KVM_CAP_DISABLE_QUIRKS: | |
5656 | kvm->arch.disabled_quirks = cap->args[0]; | |
5657 | r = 0; | |
5658 | break; | |
49df6397 SR |
5659 | case KVM_CAP_SPLIT_IRQCHIP: { |
5660 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
5661 | r = -EINVAL; |
5662 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
5663 | goto split_irqchip_unlock; | |
49df6397 SR |
5664 | r = -EEXIST; |
5665 | if (irqchip_in_kernel(kvm)) | |
5666 | goto split_irqchip_unlock; | |
557abc40 | 5667 | if (kvm->created_vcpus) |
49df6397 SR |
5668 | goto split_irqchip_unlock; |
5669 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 5670 | if (r) |
49df6397 SR |
5671 | goto split_irqchip_unlock; |
5672 | /* Pairs with irqchip_in_kernel. */ | |
5673 | smp_wmb(); | |
49776faf | 5674 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 5675 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
5676 | r = 0; |
5677 | split_irqchip_unlock: | |
5678 | mutex_unlock(&kvm->lock); | |
5679 | break; | |
5680 | } | |
37131313 RK |
5681 | case KVM_CAP_X2APIC_API: |
5682 | r = -EINVAL; | |
5683 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
5684 | break; | |
5685 | ||
5686 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
5687 | kvm->arch.x2apic_format = true; | |
c519265f RK |
5688 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
5689 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
5690 | |
5691 | r = 0; | |
5692 | break; | |
4d5422ce WL |
5693 | case KVM_CAP_X86_DISABLE_EXITS: |
5694 | r = -EINVAL; | |
5695 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
5696 | break; | |
5697 | ||
5698 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
5699 | kvm_can_mwait_in_guest()) | |
5700 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 5701 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 5702 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
5703 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
5704 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
5705 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
5706 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
5707 | r = 0; |
5708 | break; | |
6fbbde9a DS |
5709 | case KVM_CAP_MSR_PLATFORM_INFO: |
5710 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
5711 | r = 0; | |
c4f55198 JM |
5712 | break; |
5713 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
5714 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
5715 | r = 0; | |
6fbbde9a | 5716 | break; |
1ae09954 AG |
5717 | case KVM_CAP_X86_USER_SPACE_MSR: |
5718 | kvm->arch.user_space_msr_mask = cap->args[0]; | |
5719 | r = 0; | |
5720 | break; | |
fe6b6bc8 CQ |
5721 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
5722 | r = -EINVAL; | |
5723 | if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) | |
5724 | break; | |
5725 | ||
5726 | if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && | |
5727 | (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) | |
5728 | break; | |
5729 | ||
5730 | if (kvm_has_bus_lock_exit && | |
5731 | cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) | |
5732 | kvm->arch.bus_lock_detection_enabled = true; | |
5733 | r = 0; | |
5734 | break; | |
fe7e9488 SC |
5735 | #ifdef CONFIG_X86_SGX_KVM |
5736 | case KVM_CAP_SGX_ATTRIBUTE: { | |
5737 | unsigned long allowed_attributes = 0; | |
5738 | ||
5739 | r = sgx_set_attribute(&allowed_attributes, cap->args[0]); | |
5740 | if (r) | |
5741 | break; | |
5742 | ||
5743 | /* KVM only supports the PROVISIONKEY privileged attribute. */ | |
5744 | if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && | |
5745 | !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) | |
5746 | kvm->arch.sgx_provisioning_allowed = true; | |
5747 | else | |
5748 | r = -EINVAL; | |
5749 | break; | |
5750 | } | |
5751 | #endif | |
54526d1f NT |
5752 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
5753 | r = -EINVAL; | |
5754 | if (kvm_x86_ops.vm_copy_enc_context_from) | |
5755 | r = kvm_x86_ops.vm_copy_enc_context_from(kvm, cap->args[0]); | |
5756 | return r; | |
0dbb1123 AK |
5757 | case KVM_CAP_EXIT_HYPERCALL: |
5758 | if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { | |
5759 | r = -EINVAL; | |
5760 | break; | |
5761 | } | |
5762 | kvm->arch.hypercall_exit_enabled = cap->args[0]; | |
5763 | r = 0; | |
5764 | break; | |
19238e75 AL |
5765 | case KVM_CAP_EXIT_ON_EMULATION_FAILURE: |
5766 | r = -EINVAL; | |
5767 | if (cap->args[0] & ~1) | |
5768 | break; | |
5769 | kvm->arch.exit_on_emulation_error = cap->args[0]; | |
5770 | r = 0; | |
5771 | break; | |
90de4a18 NA |
5772 | default: |
5773 | r = -EINVAL; | |
5774 | break; | |
5775 | } | |
5776 | return r; | |
5777 | } | |
5778 | ||
b318e8de SC |
5779 | static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) |
5780 | { | |
5781 | struct kvm_x86_msr_filter *msr_filter; | |
5782 | ||
5783 | msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); | |
5784 | if (!msr_filter) | |
5785 | return NULL; | |
5786 | ||
5787 | msr_filter->default_allow = default_allow; | |
5788 | return msr_filter; | |
5789 | } | |
5790 | ||
5791 | static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) | |
1a155254 AG |
5792 | { |
5793 | u32 i; | |
1a155254 | 5794 | |
b318e8de SC |
5795 | if (!msr_filter) |
5796 | return; | |
5797 | ||
5798 | for (i = 0; i < msr_filter->count; i++) | |
5799 | kfree(msr_filter->ranges[i].bitmap); | |
1a155254 | 5800 | |
b318e8de | 5801 | kfree(msr_filter); |
1a155254 AG |
5802 | } |
5803 | ||
b318e8de SC |
5804 | static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, |
5805 | struct kvm_msr_filter_range *user_range) | |
1a155254 | 5806 | { |
1a155254 AG |
5807 | unsigned long *bitmap = NULL; |
5808 | size_t bitmap_size; | |
1a155254 AG |
5809 | |
5810 | if (!user_range->nmsrs) | |
5811 | return 0; | |
5812 | ||
aca35288 SC |
5813 | if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) |
5814 | return -EINVAL; | |
5815 | ||
5816 | if (!user_range->flags) | |
5817 | return -EINVAL; | |
5818 | ||
1a155254 AG |
5819 | bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); |
5820 | if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) | |
5821 | return -EINVAL; | |
5822 | ||
5823 | bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); | |
5824 | if (IS_ERR(bitmap)) | |
5825 | return PTR_ERR(bitmap); | |
5826 | ||
aca35288 | 5827 | msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { |
1a155254 AG |
5828 | .flags = user_range->flags, |
5829 | .base = user_range->base, | |
5830 | .nmsrs = user_range->nmsrs, | |
5831 | .bitmap = bitmap, | |
5832 | }; | |
5833 | ||
b318e8de | 5834 | msr_filter->count++; |
1a155254 | 5835 | return 0; |
1a155254 AG |
5836 | } |
5837 | ||
5838 | static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) | |
5839 | { | |
5840 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
b318e8de | 5841 | struct kvm_x86_msr_filter *new_filter, *old_filter; |
1a155254 AG |
5842 | struct kvm_msr_filter filter; |
5843 | bool default_allow; | |
043248b3 | 5844 | bool empty = true; |
b318e8de | 5845 | int r = 0; |
1a155254 AG |
5846 | u32 i; |
5847 | ||
5848 | if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) | |
5849 | return -EFAULT; | |
5850 | ||
043248b3 PB |
5851 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) |
5852 | empty &= !filter.ranges[i].nmsrs; | |
1a155254 AG |
5853 | |
5854 | default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); | |
043248b3 PB |
5855 | if (empty && !default_allow) |
5856 | return -EINVAL; | |
5857 | ||
b318e8de SC |
5858 | new_filter = kvm_alloc_msr_filter(default_allow); |
5859 | if (!new_filter) | |
5860 | return -ENOMEM; | |
1a155254 | 5861 | |
1a155254 | 5862 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { |
b318e8de SC |
5863 | r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); |
5864 | if (r) { | |
5865 | kvm_free_msr_filter(new_filter); | |
5866 | return r; | |
5867 | } | |
1a155254 AG |
5868 | } |
5869 | ||
b318e8de SC |
5870 | mutex_lock(&kvm->lock); |
5871 | ||
5872 | /* The per-VM filter is protected by kvm->lock... */ | |
5873 | old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); | |
5874 | ||
5875 | rcu_assign_pointer(kvm->arch.msr_filter, new_filter); | |
5876 | synchronize_srcu(&kvm->srcu); | |
5877 | ||
5878 | kvm_free_msr_filter(old_filter); | |
5879 | ||
1a155254 AG |
5880 | kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); |
5881 | mutex_unlock(&kvm->lock); | |
5882 | ||
b318e8de | 5883 | return 0; |
1a155254 AG |
5884 | } |
5885 | ||
7d62874f SS |
5886 | #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER |
5887 | static int kvm_arch_suspend_notifier(struct kvm *kvm) | |
5888 | { | |
5889 | struct kvm_vcpu *vcpu; | |
5890 | int i, ret = 0; | |
5891 | ||
5892 | mutex_lock(&kvm->lock); | |
5893 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
5894 | if (!vcpu->arch.pv_time_enabled) | |
5895 | continue; | |
5896 | ||
5897 | ret = kvm_set_guest_paused(vcpu); | |
5898 | if (ret) { | |
5899 | kvm_err("Failed to pause guest VCPU%d: %d\n", | |
5900 | vcpu->vcpu_id, ret); | |
5901 | break; | |
5902 | } | |
5903 | } | |
5904 | mutex_unlock(&kvm->lock); | |
5905 | ||
5906 | return ret ? NOTIFY_BAD : NOTIFY_DONE; | |
5907 | } | |
5908 | ||
5909 | int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) | |
5910 | { | |
5911 | switch (state) { | |
5912 | case PM_HIBERNATION_PREPARE: | |
5913 | case PM_SUSPEND_PREPARE: | |
5914 | return kvm_arch_suspend_notifier(kvm); | |
5915 | } | |
5916 | ||
5917 | return NOTIFY_DONE; | |
5918 | } | |
5919 | #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ | |
5920 | ||
1fe779f8 CO |
5921 | long kvm_arch_vm_ioctl(struct file *filp, |
5922 | unsigned int ioctl, unsigned long arg) | |
5923 | { | |
5924 | struct kvm *kvm = filp->private_data; | |
5925 | void __user *argp = (void __user *)arg; | |
367e1319 | 5926 | int r = -ENOTTY; |
f0d66275 DH |
5927 | /* |
5928 | * This union makes it completely explicit to gcc-3.x | |
5929 | * that these two variables' stack usage should be | |
5930 | * combined, not added together. | |
5931 | */ | |
5932 | union { | |
5933 | struct kvm_pit_state ps; | |
e9f42757 | 5934 | struct kvm_pit_state2 ps2; |
c5ff41ce | 5935 | struct kvm_pit_config pit_config; |
f0d66275 | 5936 | } u; |
1fe779f8 CO |
5937 | |
5938 | switch (ioctl) { | |
5939 | case KVM_SET_TSS_ADDR: | |
5940 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 5941 | break; |
b927a3ce SY |
5942 | case KVM_SET_IDENTITY_MAP_ADDR: { |
5943 | u64 ident_addr; | |
5944 | ||
1af1ac91 DH |
5945 | mutex_lock(&kvm->lock); |
5946 | r = -EINVAL; | |
5947 | if (kvm->created_vcpus) | |
5948 | goto set_identity_unlock; | |
b927a3ce | 5949 | r = -EFAULT; |
0e96f31e | 5950 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 5951 | goto set_identity_unlock; |
b927a3ce | 5952 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
5953 | set_identity_unlock: |
5954 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
5955 | break; |
5956 | } | |
1fe779f8 CO |
5957 | case KVM_SET_NR_MMU_PAGES: |
5958 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
5959 | break; |
5960 | case KVM_GET_NR_MMU_PAGES: | |
5961 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
5962 | break; | |
3ddea128 | 5963 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 5964 | mutex_lock(&kvm->lock); |
09941366 | 5965 | |
3ddea128 | 5966 | r = -EEXIST; |
35e6eaa3 | 5967 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 5968 | goto create_irqchip_unlock; |
09941366 | 5969 | |
3e515705 | 5970 | r = -EINVAL; |
557abc40 | 5971 | if (kvm->created_vcpus) |
3e515705 | 5972 | goto create_irqchip_unlock; |
09941366 RK |
5973 | |
5974 | r = kvm_pic_init(kvm); | |
5975 | if (r) | |
3ddea128 | 5976 | goto create_irqchip_unlock; |
09941366 RK |
5977 | |
5978 | r = kvm_ioapic_init(kvm); | |
5979 | if (r) { | |
09941366 | 5980 | kvm_pic_destroy(kvm); |
3ddea128 | 5981 | goto create_irqchip_unlock; |
09941366 RK |
5982 | } |
5983 | ||
399ec807 AK |
5984 | r = kvm_setup_default_irq_routing(kvm); |
5985 | if (r) { | |
72bb2fcd | 5986 | kvm_ioapic_destroy(kvm); |
09941366 | 5987 | kvm_pic_destroy(kvm); |
71ba994c | 5988 | goto create_irqchip_unlock; |
399ec807 | 5989 | } |
49776faf | 5990 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 5991 | smp_wmb(); |
49776faf | 5992 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
5993 | create_irqchip_unlock: |
5994 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 5995 | break; |
3ddea128 | 5996 | } |
7837699f | 5997 | case KVM_CREATE_PIT: |
c5ff41ce JK |
5998 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
5999 | goto create_pit; | |
6000 | case KVM_CREATE_PIT2: | |
6001 | r = -EFAULT; | |
6002 | if (copy_from_user(&u.pit_config, argp, | |
6003 | sizeof(struct kvm_pit_config))) | |
6004 | goto out; | |
6005 | create_pit: | |
250715a6 | 6006 | mutex_lock(&kvm->lock); |
269e05e4 AK |
6007 | r = -EEXIST; |
6008 | if (kvm->arch.vpit) | |
6009 | goto create_pit_unlock; | |
7837699f | 6010 | r = -ENOMEM; |
c5ff41ce | 6011 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
6012 | if (kvm->arch.vpit) |
6013 | r = 0; | |
269e05e4 | 6014 | create_pit_unlock: |
250715a6 | 6015 | mutex_unlock(&kvm->lock); |
7837699f | 6016 | break; |
1fe779f8 CO |
6017 | case KVM_GET_IRQCHIP: { |
6018 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 6019 | struct kvm_irqchip *chip; |
1fe779f8 | 6020 | |
ff5c2c03 SL |
6021 | chip = memdup_user(argp, sizeof(*chip)); |
6022 | if (IS_ERR(chip)) { | |
6023 | r = PTR_ERR(chip); | |
1fe779f8 | 6024 | goto out; |
ff5c2c03 SL |
6025 | } |
6026 | ||
1fe779f8 | 6027 | r = -ENXIO; |
826da321 | 6028 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
6029 | goto get_irqchip_out; |
6030 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 6031 | if (r) |
f0d66275 | 6032 | goto get_irqchip_out; |
1fe779f8 | 6033 | r = -EFAULT; |
0e96f31e | 6034 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 6035 | goto get_irqchip_out; |
1fe779f8 | 6036 | r = 0; |
f0d66275 DH |
6037 | get_irqchip_out: |
6038 | kfree(chip); | |
1fe779f8 CO |
6039 | break; |
6040 | } | |
6041 | case KVM_SET_IRQCHIP: { | |
6042 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 6043 | struct kvm_irqchip *chip; |
1fe779f8 | 6044 | |
ff5c2c03 SL |
6045 | chip = memdup_user(argp, sizeof(*chip)); |
6046 | if (IS_ERR(chip)) { | |
6047 | r = PTR_ERR(chip); | |
1fe779f8 | 6048 | goto out; |
ff5c2c03 SL |
6049 | } |
6050 | ||
1fe779f8 | 6051 | r = -ENXIO; |
826da321 | 6052 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
6053 | goto set_irqchip_out; |
6054 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
6055 | set_irqchip_out: |
6056 | kfree(chip); | |
1fe779f8 CO |
6057 | break; |
6058 | } | |
e0f63cb9 | 6059 | case KVM_GET_PIT: { |
e0f63cb9 | 6060 | r = -EFAULT; |
f0d66275 | 6061 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
6062 | goto out; |
6063 | r = -ENXIO; | |
6064 | if (!kvm->arch.vpit) | |
6065 | goto out; | |
f0d66275 | 6066 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
6067 | if (r) |
6068 | goto out; | |
6069 | r = -EFAULT; | |
f0d66275 | 6070 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
6071 | goto out; |
6072 | r = 0; | |
6073 | break; | |
6074 | } | |
6075 | case KVM_SET_PIT: { | |
e0f63cb9 | 6076 | r = -EFAULT; |
0e96f31e | 6077 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 | 6078 | goto out; |
7289fdb5 | 6079 | mutex_lock(&kvm->lock); |
e0f63cb9 SY |
6080 | r = -ENXIO; |
6081 | if (!kvm->arch.vpit) | |
7289fdb5 | 6082 | goto set_pit_out; |
f0d66275 | 6083 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
7289fdb5 SR |
6084 | set_pit_out: |
6085 | mutex_unlock(&kvm->lock); | |
e0f63cb9 SY |
6086 | break; |
6087 | } | |
e9f42757 BK |
6088 | case KVM_GET_PIT2: { |
6089 | r = -ENXIO; | |
6090 | if (!kvm->arch.vpit) | |
6091 | goto out; | |
6092 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
6093 | if (r) | |
6094 | goto out; | |
6095 | r = -EFAULT; | |
6096 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
6097 | goto out; | |
6098 | r = 0; | |
6099 | break; | |
6100 | } | |
6101 | case KVM_SET_PIT2: { | |
6102 | r = -EFAULT; | |
6103 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
6104 | goto out; | |
7289fdb5 | 6105 | mutex_lock(&kvm->lock); |
e9f42757 BK |
6106 | r = -ENXIO; |
6107 | if (!kvm->arch.vpit) | |
7289fdb5 | 6108 | goto set_pit2_out; |
e9f42757 | 6109 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); |
7289fdb5 SR |
6110 | set_pit2_out: |
6111 | mutex_unlock(&kvm->lock); | |
e9f42757 BK |
6112 | break; |
6113 | } | |
52d939a0 MT |
6114 | case KVM_REINJECT_CONTROL: { |
6115 | struct kvm_reinject_control control; | |
6116 | r = -EFAULT; | |
6117 | if (copy_from_user(&control, argp, sizeof(control))) | |
6118 | goto out; | |
cad23e72 ML |
6119 | r = -ENXIO; |
6120 | if (!kvm->arch.vpit) | |
6121 | goto out; | |
52d939a0 | 6122 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
6123 | break; |
6124 | } | |
d71ba788 PB |
6125 | case KVM_SET_BOOT_CPU_ID: |
6126 | r = 0; | |
6127 | mutex_lock(&kvm->lock); | |
557abc40 | 6128 | if (kvm->created_vcpus) |
d71ba788 PB |
6129 | r = -EBUSY; |
6130 | else | |
6131 | kvm->arch.bsp_vcpu_id = arg; | |
6132 | mutex_unlock(&kvm->lock); | |
6133 | break; | |
b59b153d | 6134 | #ifdef CONFIG_KVM_XEN |
ffde22ac | 6135 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 6136 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 6137 | r = -EFAULT; |
51776043 | 6138 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac | 6139 | goto out; |
78e9878c | 6140 | r = kvm_xen_hvm_config(kvm, &xhc); |
ffde22ac ES |
6141 | break; |
6142 | } | |
a76b9641 JM |
6143 | case KVM_XEN_HVM_GET_ATTR: { |
6144 | struct kvm_xen_hvm_attr xha; | |
6145 | ||
6146 | r = -EFAULT; | |
6147 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
ffde22ac | 6148 | goto out; |
a76b9641 JM |
6149 | r = kvm_xen_hvm_get_attr(kvm, &xha); |
6150 | if (!r && copy_to_user(argp, &xha, sizeof(xha))) | |
6151 | r = -EFAULT; | |
6152 | break; | |
6153 | } | |
6154 | case KVM_XEN_HVM_SET_ATTR: { | |
6155 | struct kvm_xen_hvm_attr xha; | |
6156 | ||
6157 | r = -EFAULT; | |
6158 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
6159 | goto out; | |
6160 | r = kvm_xen_hvm_set_attr(kvm, &xha); | |
ffde22ac ES |
6161 | break; |
6162 | } | |
b59b153d | 6163 | #endif |
afbcf7ab | 6164 | case KVM_SET_CLOCK: { |
77fcbe82 | 6165 | struct kvm_arch *ka = &kvm->arch; |
afbcf7ab GC |
6166 | struct kvm_clock_data user_ns; |
6167 | u64 now_ns; | |
afbcf7ab GC |
6168 | |
6169 | r = -EFAULT; | |
6170 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
6171 | goto out; | |
6172 | ||
6173 | r = -EINVAL; | |
6174 | if (user_ns.flags) | |
6175 | goto out; | |
6176 | ||
6177 | r = 0; | |
0bc48bea RK |
6178 | /* |
6179 | * TODO: userspace has to take care of races with VCPU_RUN, so | |
6180 | * kvm_gen_update_masterclock() can be cut down to locked | |
6181 | * pvclock_update_vm_gtod_copy(). | |
6182 | */ | |
6183 | kvm_gen_update_masterclock(kvm); | |
77fcbe82 VK |
6184 | |
6185 | /* | |
6186 | * This pairs with kvm_guest_time_update(): when masterclock is | |
6187 | * in use, we use master_kernel_ns + kvmclock_offset to set | |
6188 | * unsigned 'system_time' so if we use get_kvmclock_ns() (which | |
6189 | * is slightly ahead) here we risk going negative on unsigned | |
6190 | * 'system_time' when 'user_ns.clock' is very small. | |
6191 | */ | |
8228c77d | 6192 | raw_spin_lock_irq(&ka->pvclock_gtod_sync_lock); |
77fcbe82 VK |
6193 | if (kvm->arch.use_master_clock) |
6194 | now_ns = ka->master_kernel_ns; | |
6195 | else | |
6196 | now_ns = get_kvmclock_base_ns(); | |
6197 | ka->kvmclock_offset = user_ns.clock - now_ns; | |
8228c77d | 6198 | raw_spin_unlock_irq(&ka->pvclock_gtod_sync_lock); |
77fcbe82 | 6199 | |
0bc48bea | 6200 | kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); |
afbcf7ab GC |
6201 | break; |
6202 | } | |
6203 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
6204 | struct kvm_clock_data user_ns; |
6205 | u64 now_ns; | |
6206 | ||
e891a32e | 6207 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 6208 | user_ns.clock = now_ns; |
e3fd9a93 | 6209 | user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; |
97e69aa6 | 6210 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
6211 | |
6212 | r = -EFAULT; | |
6213 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
6214 | goto out; | |
6215 | r = 0; | |
6216 | break; | |
6217 | } | |
5acc5c06 BS |
6218 | case KVM_MEMORY_ENCRYPT_OP: { |
6219 | r = -ENOTTY; | |
afaf0b2f | 6220 | if (kvm_x86_ops.mem_enc_op) |
b3646477 | 6221 | r = static_call(kvm_x86_mem_enc_op)(kvm, argp); |
5acc5c06 BS |
6222 | break; |
6223 | } | |
69eaedee BS |
6224 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
6225 | struct kvm_enc_region region; | |
6226 | ||
6227 | r = -EFAULT; | |
6228 | if (copy_from_user(®ion, argp, sizeof(region))) | |
6229 | goto out; | |
6230 | ||
6231 | r = -ENOTTY; | |
afaf0b2f | 6232 | if (kvm_x86_ops.mem_enc_reg_region) |
b3646477 | 6233 | r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); |
69eaedee BS |
6234 | break; |
6235 | } | |
6236 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
6237 | struct kvm_enc_region region; | |
6238 | ||
6239 | r = -EFAULT; | |
6240 | if (copy_from_user(®ion, argp, sizeof(region))) | |
6241 | goto out; | |
6242 | ||
6243 | r = -ENOTTY; | |
afaf0b2f | 6244 | if (kvm_x86_ops.mem_enc_unreg_region) |
b3646477 | 6245 | r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); |
69eaedee BS |
6246 | break; |
6247 | } | |
faeb7833 RK |
6248 | case KVM_HYPERV_EVENTFD: { |
6249 | struct kvm_hyperv_eventfd hvevfd; | |
6250 | ||
6251 | r = -EFAULT; | |
6252 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
6253 | goto out; | |
6254 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
6255 | break; | |
6256 | } | |
66bb8a06 EH |
6257 | case KVM_SET_PMU_EVENT_FILTER: |
6258 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
6259 | break; | |
1a155254 AG |
6260 | case KVM_X86_SET_MSR_FILTER: |
6261 | r = kvm_vm_ioctl_set_msr_filter(kvm, argp); | |
6262 | break; | |
1fe779f8 | 6263 | default: |
ad6260da | 6264 | r = -ENOTTY; |
1fe779f8 CO |
6265 | } |
6266 | out: | |
6267 | return r; | |
6268 | } | |
6269 | ||
a16b043c | 6270 | static void kvm_init_msr_list(void) |
043405e1 | 6271 | { |
24c29b7a | 6272 | struct x86_pmu_capability x86_pmu; |
043405e1 | 6273 | u32 dummy[2]; |
7a5ee6ed | 6274 | unsigned i; |
043405e1 | 6275 | |
e2ada66e | 6276 | BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, |
7a5ee6ed | 6277 | "Please update the fixed PMCs in msrs_to_saved_all[]"); |
24c29b7a PB |
6278 | |
6279 | perf_get_x86_pmu_capability(&x86_pmu); | |
e2ada66e | 6280 | |
6cbee2b9 XL |
6281 | num_msrs_to_save = 0; |
6282 | num_emulated_msrs = 0; | |
6283 | num_msr_based_features = 0; | |
6284 | ||
7a5ee6ed CQ |
6285 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { |
6286 | if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) | |
043405e1 | 6287 | continue; |
93c4adc7 PB |
6288 | |
6289 | /* | |
6290 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 6291 | * to the guests in some cases. |
93c4adc7 | 6292 | */ |
7a5ee6ed | 6293 | switch (msrs_to_save_all[i]) { |
93c4adc7 | 6294 | case MSR_IA32_BNDCFGS: |
503234b3 | 6295 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
6296 | continue; |
6297 | break; | |
9dbe6cf9 | 6298 | case MSR_TSC_AUX: |
36fa06f9 SC |
6299 | if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && |
6300 | !kvm_cpu_cap_has(X86_FEATURE_RDPID)) | |
9dbe6cf9 PB |
6301 | continue; |
6302 | break; | |
f4cfcd2d ML |
6303 | case MSR_IA32_UMWAIT_CONTROL: |
6304 | if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) | |
6305 | continue; | |
6306 | break; | |
bf8c55d8 CP |
6307 | case MSR_IA32_RTIT_CTL: |
6308 | case MSR_IA32_RTIT_STATUS: | |
7b874c26 | 6309 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) |
bf8c55d8 CP |
6310 | continue; |
6311 | break; | |
6312 | case MSR_IA32_RTIT_CR3_MATCH: | |
7b874c26 | 6313 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
6314 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) |
6315 | continue; | |
6316 | break; | |
6317 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
6318 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
7b874c26 | 6319 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
6320 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && |
6321 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
6322 | continue; | |
6323 | break; | |
7cb85fc4 | 6324 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: |
7b874c26 | 6325 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
7a5ee6ed | 6326 | msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= |
bf8c55d8 CP |
6327 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) |
6328 | continue; | |
6329 | break; | |
cf05a67b | 6330 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: |
7a5ee6ed | 6331 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= |
24c29b7a PB |
6332 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
6333 | continue; | |
6334 | break; | |
cf05a67b | 6335 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: |
7a5ee6ed | 6336 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= |
24c29b7a PB |
6337 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
6338 | continue; | |
7cb85fc4 | 6339 | break; |
93c4adc7 PB |
6340 | default: |
6341 | break; | |
6342 | } | |
6343 | ||
7a5ee6ed | 6344 | msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; |
043405e1 | 6345 | } |
62ef68bb | 6346 | |
7a5ee6ed | 6347 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
b3646477 | 6348 | if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) |
bc226f07 | 6349 | continue; |
62ef68bb | 6350 | |
7a5ee6ed | 6351 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 6352 | } |
801e459a | 6353 | |
7a5ee6ed | 6354 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { |
801e459a TL |
6355 | struct kvm_msr_entry msr; |
6356 | ||
7a5ee6ed | 6357 | msr.index = msr_based_features_all[i]; |
66421c1e | 6358 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
6359 | continue; |
6360 | ||
7a5ee6ed | 6361 | msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; |
801e459a | 6362 | } |
043405e1 CO |
6363 | } |
6364 | ||
bda9020e MT |
6365 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
6366 | const void *v) | |
bbd9b64e | 6367 | { |
70252a10 AK |
6368 | int handled = 0; |
6369 | int n; | |
6370 | ||
6371 | do { | |
6372 | n = min(len, 8); | |
bce87cce | 6373 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
6374 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
6375 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
6376 | break; |
6377 | handled += n; | |
6378 | addr += n; | |
6379 | len -= n; | |
6380 | v += n; | |
6381 | } while (len); | |
bbd9b64e | 6382 | |
70252a10 | 6383 | return handled; |
bbd9b64e CO |
6384 | } |
6385 | ||
bda9020e | 6386 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 6387 | { |
70252a10 AK |
6388 | int handled = 0; |
6389 | int n; | |
6390 | ||
6391 | do { | |
6392 | n = min(len, 8); | |
bce87cce | 6393 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
6394 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
6395 | addr, n, v)) | |
6396 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 6397 | break; |
e39d200f | 6398 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
6399 | handled += n; |
6400 | addr += n; | |
6401 | len -= n; | |
6402 | v += n; | |
6403 | } while (len); | |
bbd9b64e | 6404 | |
70252a10 | 6405 | return handled; |
bbd9b64e CO |
6406 | } |
6407 | ||
2dafc6c2 GN |
6408 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
6409 | struct kvm_segment *var, int seg) | |
6410 | { | |
b3646477 | 6411 | static_call(kvm_x86_set_segment)(vcpu, var, seg); |
2dafc6c2 GN |
6412 | } |
6413 | ||
6414 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
6415 | struct kvm_segment *var, int seg) | |
6416 | { | |
b3646477 | 6417 | static_call(kvm_x86_get_segment)(vcpu, var, seg); |
2dafc6c2 GN |
6418 | } |
6419 | ||
54987b7a PB |
6420 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
6421 | struct x86_exception *exception) | |
02f59dc9 JR |
6422 | { |
6423 | gpa_t t_gpa; | |
02f59dc9 JR |
6424 | |
6425 | BUG_ON(!mmu_is_nested(vcpu)); | |
6426 | ||
6427 | /* NPT walks are always user-walks */ | |
6428 | access |= PFERR_USER_MASK; | |
44dd3ffa | 6429 | t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
6430 | |
6431 | return t_gpa; | |
6432 | } | |
6433 | ||
ab9ae313 AK |
6434 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
6435 | struct x86_exception *exception) | |
1871c602 | 6436 | { |
b3646477 | 6437 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
ab9ae313 | 6438 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 | 6439 | } |
54f958cd | 6440 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); |
1871c602 | 6441 | |
ab9ae313 AK |
6442 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
6443 | struct x86_exception *exception) | |
1871c602 | 6444 | { |
b3646477 | 6445 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 6446 | access |= PFERR_FETCH_MASK; |
ab9ae313 | 6447 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
6448 | } |
6449 | ||
ab9ae313 AK |
6450 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
6451 | struct x86_exception *exception) | |
1871c602 | 6452 | { |
b3646477 | 6453 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 6454 | access |= PFERR_WRITE_MASK; |
ab9ae313 | 6455 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 | 6456 | } |
54f958cd | 6457 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); |
1871c602 GN |
6458 | |
6459 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
6460 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
6461 | struct x86_exception *exception) | |
1871c602 | 6462 | { |
ab9ae313 | 6463 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
6464 | } |
6465 | ||
6466 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
6467 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 6468 | struct x86_exception *exception) |
bbd9b64e CO |
6469 | { |
6470 | void *data = val; | |
10589a46 | 6471 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
6472 | |
6473 | while (bytes) { | |
14dfe855 | 6474 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 6475 | exception); |
bbd9b64e | 6476 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 6477 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
6478 | int ret; |
6479 | ||
bcc55cba | 6480 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6481 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
6482 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
6483 | offset, toread); | |
10589a46 | 6484 | if (ret < 0) { |
c3cd7ffa | 6485 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
6486 | goto out; |
6487 | } | |
bbd9b64e | 6488 | |
77c2002e IE |
6489 | bytes -= toread; |
6490 | data += toread; | |
6491 | addr += toread; | |
bbd9b64e | 6492 | } |
10589a46 | 6493 | out: |
10589a46 | 6494 | return r; |
bbd9b64e | 6495 | } |
77c2002e | 6496 | |
1871c602 | 6497 | /* used for instruction fetching */ |
0f65dd70 AK |
6498 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
6499 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 6500 | struct x86_exception *exception) |
1871c602 | 6501 | { |
0f65dd70 | 6502 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
b3646477 | 6503 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
6504 | unsigned offset; |
6505 | int ret; | |
0f65dd70 | 6506 | |
44583cba PB |
6507 | /* Inline kvm_read_guest_virt_helper for speed. */ |
6508 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
6509 | exception); | |
6510 | if (unlikely(gpa == UNMAPPED_GVA)) | |
6511 | return X86EMUL_PROPAGATE_FAULT; | |
6512 | ||
6513 | offset = addr & (PAGE_SIZE-1); | |
6514 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
6515 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
6516 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
6517 | offset, bytes); | |
44583cba PB |
6518 | if (unlikely(ret < 0)) |
6519 | return X86EMUL_IO_NEEDED; | |
6520 | ||
6521 | return X86EMUL_CONTINUE; | |
1871c602 GN |
6522 | } |
6523 | ||
ce14e868 | 6524 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 6525 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 6526 | struct x86_exception *exception) |
1871c602 | 6527 | { |
b3646477 | 6528 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 6529 | |
353c0956 PB |
6530 | /* |
6531 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
6532 | * is returned, but our callers are not ready for that and they blindly | |
6533 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
6534 | * uninitialized kernel stack memory into cr2 and error code. | |
6535 | */ | |
6536 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 6537 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 6538 | exception); |
1871c602 | 6539 | } |
064aea77 | 6540 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 6541 | |
ce14e868 PB |
6542 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
6543 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 6544 | struct x86_exception *exception, bool system) |
1871c602 | 6545 | { |
0f65dd70 | 6546 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3c9fa24c PB |
6547 | u32 access = 0; |
6548 | ||
b3646477 | 6549 | if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) |
3c9fa24c PB |
6550 | access |= PFERR_USER_MASK; |
6551 | ||
6552 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
6553 | } |
6554 | ||
7a036a6f RK |
6555 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
6556 | unsigned long addr, void *val, unsigned int bytes) | |
6557 | { | |
6558 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6559 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
6560 | ||
6561 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
6562 | } | |
6563 | ||
ce14e868 PB |
6564 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
6565 | struct kvm_vcpu *vcpu, u32 access, | |
6566 | struct x86_exception *exception) | |
77c2002e IE |
6567 | { |
6568 | void *data = val; | |
6569 | int r = X86EMUL_CONTINUE; | |
6570 | ||
6571 | while (bytes) { | |
14dfe855 | 6572 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
ce14e868 | 6573 | access, |
ab9ae313 | 6574 | exception); |
77c2002e IE |
6575 | unsigned offset = addr & (PAGE_SIZE-1); |
6576 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
6577 | int ret; | |
6578 | ||
bcc55cba | 6579 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6580 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 6581 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 6582 | if (ret < 0) { |
c3cd7ffa | 6583 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
6584 | goto out; |
6585 | } | |
6586 | ||
6587 | bytes -= towrite; | |
6588 | data += towrite; | |
6589 | addr += towrite; | |
6590 | } | |
6591 | out: | |
6592 | return r; | |
6593 | } | |
ce14e868 PB |
6594 | |
6595 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
6596 | unsigned int bytes, struct x86_exception *exception, |
6597 | bool system) | |
ce14e868 PB |
6598 | { |
6599 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
3c9fa24c PB |
6600 | u32 access = PFERR_WRITE_MASK; |
6601 | ||
b3646477 | 6602 | if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) |
3c9fa24c | 6603 | access |= PFERR_USER_MASK; |
ce14e868 PB |
6604 | |
6605 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 6606 | access, exception); |
ce14e868 PB |
6607 | } |
6608 | ||
6609 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
6610 | unsigned int bytes, struct x86_exception *exception) | |
6611 | { | |
c595ceee PB |
6612 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
6613 | vcpu->arch.l1tf_flush_l1d = true; | |
6614 | ||
ce14e868 PB |
6615 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
6616 | PFERR_WRITE_MASK, exception); | |
6617 | } | |
6a4d7550 | 6618 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 6619 | |
082d06ed WL |
6620 | int handle_ud(struct kvm_vcpu *vcpu) |
6621 | { | |
b3dc0695 | 6622 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
6c86eedc | 6623 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
6624 | char sig[5]; /* ud2; .ascii "kvm" */ |
6625 | struct x86_exception e; | |
6626 | ||
b3646477 | 6627 | if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) |
09e3e2a1 SC |
6628 | return 1; |
6629 | ||
6c86eedc | 6630 | if (force_emulation_prefix && |
3c9fa24c PB |
6631 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
6632 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 6633 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
6c86eedc | 6634 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 6635 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 6636 | } |
082d06ed | 6637 | |
60fc3d02 | 6638 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
6639 | } |
6640 | EXPORT_SYMBOL_GPL(handle_ud); | |
6641 | ||
0f89b207 TL |
6642 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6643 | gpa_t gpa, bool write) | |
6644 | { | |
6645 | /* For APIC access vmexit */ | |
6646 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6647 | return 1; | |
6648 | ||
6649 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
6650 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
6651 | return 1; | |
6652 | } | |
6653 | ||
6654 | return 0; | |
6655 | } | |
6656 | ||
af7cc7d1 XG |
6657 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6658 | gpa_t *gpa, struct x86_exception *exception, | |
6659 | bool write) | |
6660 | { | |
b3646477 | 6661 | u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) |
97d64b78 | 6662 | | (write ? PFERR_WRITE_MASK : 0); |
af7cc7d1 | 6663 | |
be94f6b7 HH |
6664 | /* |
6665 | * currently PKRU is only applied to ept enabled guest so | |
6666 | * there is no pkey in EPT page table for L1 guest or EPT | |
6667 | * shadow page table for L2 guest. | |
6668 | */ | |
908b7d43 SC |
6669 | if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || |
6670 | !permission_fault(vcpu, vcpu->arch.walk_mmu, | |
6671 | vcpu->arch.mmio_access, 0, access))) { | |
bebb106a XG |
6672 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
6673 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 6674 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
6675 | return 1; |
6676 | } | |
6677 | ||
af7cc7d1 XG |
6678 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
6679 | ||
6680 | if (*gpa == UNMAPPED_GVA) | |
6681 | return -1; | |
6682 | ||
0f89b207 | 6683 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
6684 | } |
6685 | ||
3200f405 | 6686 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 6687 | const void *val, int bytes) |
bbd9b64e CO |
6688 | { |
6689 | int ret; | |
6690 | ||
54bf36aa | 6691 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 6692 | if (ret < 0) |
bbd9b64e | 6693 | return 0; |
0eb05bf2 | 6694 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
6695 | return 1; |
6696 | } | |
6697 | ||
77d197b2 XG |
6698 | struct read_write_emulator_ops { |
6699 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
6700 | int bytes); | |
6701 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6702 | void *val, int bytes); | |
6703 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6704 | int bytes, void *val); | |
6705 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6706 | void *val, int bytes); | |
6707 | bool write; | |
6708 | }; | |
6709 | ||
6710 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
6711 | { | |
6712 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 6713 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 6714 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
6715 | vcpu->mmio_read_completed = 0; |
6716 | return 1; | |
6717 | } | |
6718 | ||
6719 | return 0; | |
6720 | } | |
6721 | ||
6722 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6723 | void *val, int bytes) | |
6724 | { | |
54bf36aa | 6725 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
6726 | } |
6727 | ||
6728 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6729 | void *val, int bytes) | |
6730 | { | |
6731 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
6732 | } | |
6733 | ||
6734 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
6735 | { | |
e39d200f | 6736 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
6737 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
6738 | } | |
6739 | ||
6740 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6741 | void *val, int bytes) | |
6742 | { | |
e39d200f | 6743 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
6744 | return X86EMUL_IO_NEEDED; |
6745 | } | |
6746 | ||
6747 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6748 | void *val, int bytes) | |
6749 | { | |
f78146b0 AK |
6750 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
6751 | ||
87da7e66 | 6752 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
6753 | return X86EMUL_CONTINUE; |
6754 | } | |
6755 | ||
0fbe9b0b | 6756 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
6757 | .read_write_prepare = read_prepare, |
6758 | .read_write_emulate = read_emulate, | |
6759 | .read_write_mmio = vcpu_mmio_read, | |
6760 | .read_write_exit_mmio = read_exit_mmio, | |
6761 | }; | |
6762 | ||
0fbe9b0b | 6763 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
6764 | .read_write_emulate = write_emulate, |
6765 | .read_write_mmio = write_mmio, | |
6766 | .read_write_exit_mmio = write_exit_mmio, | |
6767 | .write = true, | |
6768 | }; | |
6769 | ||
22388a3c XG |
6770 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
6771 | unsigned int bytes, | |
6772 | struct x86_exception *exception, | |
6773 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 6774 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6775 | { |
af7cc7d1 XG |
6776 | gpa_t gpa; |
6777 | int handled, ret; | |
22388a3c | 6778 | bool write = ops->write; |
f78146b0 | 6779 | struct kvm_mmio_fragment *frag; |
c9b8b07c | 6780 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
0f89b207 TL |
6781 | |
6782 | /* | |
6783 | * If the exit was due to a NPF we may already have a GPA. | |
6784 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
6785 | * Note, this cannot be used on string operations since string | |
6786 | * operation using rep will only have the initial GPA from the NPF | |
6787 | * occurred. | |
6788 | */ | |
744e699c SC |
6789 | if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && |
6790 | (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { | |
6791 | gpa = ctxt->gpa_val; | |
618232e2 BS |
6792 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); |
6793 | } else { | |
6794 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
6795 | if (ret < 0) | |
6796 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 6797 | } |
10589a46 | 6798 | |
618232e2 | 6799 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
6800 | return X86EMUL_CONTINUE; |
6801 | ||
bbd9b64e CO |
6802 | /* |
6803 | * Is this MMIO handled locally? | |
6804 | */ | |
22388a3c | 6805 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 6806 | if (handled == bytes) |
bbd9b64e | 6807 | return X86EMUL_CONTINUE; |
bbd9b64e | 6808 | |
70252a10 AK |
6809 | gpa += handled; |
6810 | bytes -= handled; | |
6811 | val += handled; | |
6812 | ||
87da7e66 XG |
6813 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
6814 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
6815 | frag->gpa = gpa; | |
6816 | frag->data = val; | |
6817 | frag->len = bytes; | |
f78146b0 | 6818 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
6819 | } |
6820 | ||
52eb5a6d XL |
6821 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
6822 | unsigned long addr, | |
22388a3c XG |
6823 | void *val, unsigned int bytes, |
6824 | struct x86_exception *exception, | |
0fbe9b0b | 6825 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6826 | { |
0f65dd70 | 6827 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
6828 | gpa_t gpa; |
6829 | int rc; | |
6830 | ||
6831 | if (ops->read_write_prepare && | |
6832 | ops->read_write_prepare(vcpu, val, bytes)) | |
6833 | return X86EMUL_CONTINUE; | |
6834 | ||
6835 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 6836 | |
bbd9b64e CO |
6837 | /* Crossing a page boundary? */ |
6838 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 6839 | int now; |
bbd9b64e CO |
6840 | |
6841 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
6842 | rc = emulator_read_write_onepage(addr, val, now, exception, |
6843 | vcpu, ops); | |
6844 | ||
bbd9b64e CO |
6845 | if (rc != X86EMUL_CONTINUE) |
6846 | return rc; | |
6847 | addr += now; | |
bac15531 NA |
6848 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6849 | addr = (u32)addr; | |
bbd9b64e CO |
6850 | val += now; |
6851 | bytes -= now; | |
6852 | } | |
22388a3c | 6853 | |
f78146b0 AK |
6854 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
6855 | vcpu, ops); | |
6856 | if (rc != X86EMUL_CONTINUE) | |
6857 | return rc; | |
6858 | ||
6859 | if (!vcpu->mmio_nr_fragments) | |
6860 | return rc; | |
6861 | ||
6862 | gpa = vcpu->mmio_fragments[0].gpa; | |
6863 | ||
6864 | vcpu->mmio_needed = 1; | |
6865 | vcpu->mmio_cur_fragment = 0; | |
6866 | ||
87da7e66 | 6867 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
6868 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
6869 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
6870 | vcpu->run->mmio.phys_addr = gpa; | |
6871 | ||
6872 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
6873 | } |
6874 | ||
6875 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
6876 | unsigned long addr, | |
6877 | void *val, | |
6878 | unsigned int bytes, | |
6879 | struct x86_exception *exception) | |
6880 | { | |
6881 | return emulator_read_write(ctxt, addr, val, bytes, | |
6882 | exception, &read_emultor); | |
6883 | } | |
6884 | ||
52eb5a6d | 6885 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
6886 | unsigned long addr, |
6887 | const void *val, | |
6888 | unsigned int bytes, | |
6889 | struct x86_exception *exception) | |
6890 | { | |
6891 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
6892 | exception, &write_emultor); | |
bbd9b64e | 6893 | } |
bbd9b64e | 6894 | |
daea3e73 AK |
6895 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
6896 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
6897 | ||
6898 | #ifdef CONFIG_X86_64 | |
6899 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
6900 | #else | |
6901 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 6902 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
6903 | #endif |
6904 | ||
0f65dd70 AK |
6905 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
6906 | unsigned long addr, | |
bbd9b64e CO |
6907 | const void *old, |
6908 | const void *new, | |
6909 | unsigned int bytes, | |
0f65dd70 | 6910 | struct x86_exception *exception) |
bbd9b64e | 6911 | { |
42e35f80 | 6912 | struct kvm_host_map map; |
0f65dd70 | 6913 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
9de6fe3c | 6914 | u64 page_line_mask; |
daea3e73 | 6915 | gpa_t gpa; |
daea3e73 AK |
6916 | char *kaddr; |
6917 | bool exchanged; | |
2bacc55c | 6918 | |
daea3e73 AK |
6919 | /* guests cmpxchg8b have to be emulated atomically */ |
6920 | if (bytes > 8 || (bytes & (bytes - 1))) | |
6921 | goto emul_write; | |
10589a46 | 6922 | |
daea3e73 | 6923 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 6924 | |
daea3e73 AK |
6925 | if (gpa == UNMAPPED_GVA || |
6926 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6927 | goto emul_write; | |
2bacc55c | 6928 | |
9de6fe3c XL |
6929 | /* |
6930 | * Emulate the atomic as a straight write to avoid #AC if SLD is | |
6931 | * enabled in the host and the access splits a cache line. | |
6932 | */ | |
6933 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
6934 | page_line_mask = ~(cache_line_size() - 1); | |
6935 | else | |
6936 | page_line_mask = PAGE_MASK; | |
6937 | ||
6938 | if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) | |
daea3e73 | 6939 | goto emul_write; |
72dc67a6 | 6940 | |
42e35f80 | 6941 | if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) |
c19b8bd6 | 6942 | goto emul_write; |
72dc67a6 | 6943 | |
42e35f80 KA |
6944 | kaddr = map.hva + offset_in_page(gpa); |
6945 | ||
daea3e73 AK |
6946 | switch (bytes) { |
6947 | case 1: | |
6948 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
6949 | break; | |
6950 | case 2: | |
6951 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
6952 | break; | |
6953 | case 4: | |
6954 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
6955 | break; | |
6956 | case 8: | |
6957 | exchanged = CMPXCHG64(kaddr, old, new); | |
6958 | break; | |
6959 | default: | |
6960 | BUG(); | |
2bacc55c | 6961 | } |
42e35f80 KA |
6962 | |
6963 | kvm_vcpu_unmap(vcpu, &map, true); | |
daea3e73 AK |
6964 | |
6965 | if (!exchanged) | |
6966 | return X86EMUL_CMPXCHG_FAILED; | |
6967 | ||
0eb05bf2 | 6968 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
6969 | |
6970 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 6971 | |
3200f405 | 6972 | emul_write: |
daea3e73 | 6973 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 6974 | |
0f65dd70 | 6975 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
6976 | } |
6977 | ||
cf8f70bf GN |
6978 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
6979 | { | |
cbfc6c91 | 6980 | int r = 0, i; |
cf8f70bf | 6981 | |
cbfc6c91 WL |
6982 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
6983 | if (vcpu->arch.pio.in) | |
6984 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
6985 | vcpu->arch.pio.size, pd); | |
6986 | else | |
6987 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
6988 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
6989 | pd); | |
6990 | if (r) | |
6991 | break; | |
6992 | pd += vcpu->arch.pio.size; | |
6993 | } | |
cf8f70bf GN |
6994 | return r; |
6995 | } | |
6996 | ||
6f6fbe98 | 6997 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
3b27de27 | 6998 | unsigned short port, |
6f6fbe98 | 6999 | unsigned int count, bool in) |
cf8f70bf | 7000 | { |
cf8f70bf | 7001 | vcpu->arch.pio.port = port; |
6f6fbe98 | 7002 | vcpu->arch.pio.in = in; |
7972995b | 7003 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
7004 | vcpu->arch.pio.size = size; |
7005 | ||
0d33b1ba | 7006 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) |
cf8f70bf | 7007 | return 1; |
cf8f70bf GN |
7008 | |
7009 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 7010 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
7011 | vcpu->run->io.size = size; |
7012 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
7013 | vcpu->run->io.count = count; | |
7014 | vcpu->run->io.port = port; | |
7015 | ||
7016 | return 0; | |
7017 | } | |
7018 | ||
3b27de27 PB |
7019 | static int __emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
7020 | unsigned short port, unsigned int count) | |
cf8f70bf | 7021 | { |
3b27de27 PB |
7022 | WARN_ON(vcpu->arch.pio.count); |
7023 | memset(vcpu->arch.pio_data, 0, size * count); | |
7024 | return emulator_pio_in_out(vcpu, size, port, count, true); | |
7025 | } | |
ca1d4a9e | 7026 | |
6b5efc93 | 7027 | static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val) |
3b27de27 | 7028 | { |
6b5efc93 PB |
7029 | int size = vcpu->arch.pio.size; |
7030 | unsigned count = vcpu->arch.pio.count; | |
7031 | memcpy(val, vcpu->arch.pio_data, size * count); | |
7032 | trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data); | |
3b27de27 PB |
7033 | vcpu->arch.pio.count = 0; |
7034 | } | |
cf8f70bf | 7035 | |
3b27de27 PB |
7036 | static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
7037 | unsigned short port, void *val, unsigned int count) | |
7038 | { | |
7039 | if (vcpu->arch.pio.count) { | |
5be53d5f SC |
7040 | /* |
7041 | * Complete a previous iteration that required userspace I/O. | |
7042 | * Note, @count isn't guaranteed to match pio.count as userspace | |
7043 | * can modify ECX before rerunning the vCPU. Ignore any such | |
7044 | * shenanigans as KVM doesn't support modifying the rep count, | |
7045 | * and the emulator ensures @count doesn't overflow the buffer. | |
7046 | */ | |
3b27de27 PB |
7047 | } else { |
7048 | int r = __emulator_pio_in(vcpu, size, port, count); | |
7049 | if (!r) | |
7050 | return r; | |
cbfc6c91 | 7051 | |
3b27de27 | 7052 | /* Results already available, fall through. */ |
cf8f70bf GN |
7053 | } |
7054 | ||
6b5efc93 | 7055 | complete_emulator_pio_in(vcpu, val); |
3b27de27 | 7056 | return 1; |
cf8f70bf GN |
7057 | } |
7058 | ||
2e3bb4d8 SC |
7059 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
7060 | int size, unsigned short port, void *val, | |
7061 | unsigned int count) | |
6f6fbe98 | 7062 | { |
2e3bb4d8 | 7063 | return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); |
6f6fbe98 | 7064 | |
2e3bb4d8 | 7065 | } |
6f6fbe98 | 7066 | |
2e3bb4d8 SC |
7067 | static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, |
7068 | unsigned short port, const void *val, | |
7069 | unsigned int count) | |
7070 | { | |
0d33b1ba PB |
7071 | int ret; |
7072 | ||
6f6fbe98 | 7073 | memcpy(vcpu->arch.pio_data, val, size * count); |
1171903d | 7074 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
3b27de27 | 7075 | ret = emulator_pio_in_out(vcpu, size, port, count, false); |
0d33b1ba PB |
7076 | if (ret) |
7077 | vcpu->arch.pio.count = 0; | |
7078 | ||
7079 | return ret; | |
6f6fbe98 XG |
7080 | } |
7081 | ||
2e3bb4d8 SC |
7082 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
7083 | int size, unsigned short port, | |
7084 | const void *val, unsigned int count) | |
7085 | { | |
7086 | return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); | |
7087 | } | |
7088 | ||
bbd9b64e CO |
7089 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
7090 | { | |
b3646477 | 7091 | return static_call(kvm_x86_get_segment_base)(vcpu, seg); |
bbd9b64e CO |
7092 | } |
7093 | ||
3cb16fe7 | 7094 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 7095 | { |
3cb16fe7 | 7096 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
7097 | } |
7098 | ||
ae6a2375 | 7099 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
7100 | { |
7101 | if (!need_emulate_wbinvd(vcpu)) | |
7102 | return X86EMUL_CONTINUE; | |
7103 | ||
b3646477 | 7104 | if (static_call(kvm_x86_has_wbinvd_exit)()) { |
2eec7343 JK |
7105 | int cpu = get_cpu(); |
7106 | ||
7107 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
c2162e13 | 7108 | on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, |
f5f48ee1 | 7109 | wbinvd_ipi, NULL, 1); |
2eec7343 | 7110 | put_cpu(); |
f5f48ee1 | 7111 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
7112 | } else |
7113 | wbinvd(); | |
f5f48ee1 SY |
7114 | return X86EMUL_CONTINUE; |
7115 | } | |
5cb56059 JS |
7116 | |
7117 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
7118 | { | |
6affcbed KH |
7119 | kvm_emulate_wbinvd_noskip(vcpu); |
7120 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 7121 | } |
f5f48ee1 SY |
7122 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
7123 | ||
5cb56059 JS |
7124 | |
7125 | ||
bcaf5cc5 AK |
7126 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
7127 | { | |
5cb56059 | 7128 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
7129 | } |
7130 | ||
29d6ca41 PB |
7131 | static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
7132 | unsigned long *dest) | |
bbd9b64e | 7133 | { |
29d6ca41 | 7134 | kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
7135 | } |
7136 | ||
52eb5a6d XL |
7137 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
7138 | unsigned long value) | |
bbd9b64e | 7139 | { |
338dbc97 | 7140 | |
996ff542 | 7141 | return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
7142 | } |
7143 | ||
52a46617 | 7144 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 7145 | { |
52a46617 | 7146 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
7147 | } |
7148 | ||
717746e3 | 7149 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 7150 | { |
717746e3 | 7151 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
7152 | unsigned long value; |
7153 | ||
7154 | switch (cr) { | |
7155 | case 0: | |
7156 | value = kvm_read_cr0(vcpu); | |
7157 | break; | |
7158 | case 2: | |
7159 | value = vcpu->arch.cr2; | |
7160 | break; | |
7161 | case 3: | |
9f8fe504 | 7162 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
7163 | break; |
7164 | case 4: | |
7165 | value = kvm_read_cr4(vcpu); | |
7166 | break; | |
7167 | case 8: | |
7168 | value = kvm_get_cr8(vcpu); | |
7169 | break; | |
7170 | default: | |
a737f256 | 7171 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
7172 | return 0; |
7173 | } | |
7174 | ||
7175 | return value; | |
7176 | } | |
7177 | ||
717746e3 | 7178 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 7179 | { |
717746e3 | 7180 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
7181 | int res = 0; |
7182 | ||
52a46617 GN |
7183 | switch (cr) { |
7184 | case 0: | |
49a9b07e | 7185 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
7186 | break; |
7187 | case 2: | |
7188 | vcpu->arch.cr2 = val; | |
7189 | break; | |
7190 | case 3: | |
2390218b | 7191 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
7192 | break; |
7193 | case 4: | |
a83b29c6 | 7194 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
7195 | break; |
7196 | case 8: | |
eea1cff9 | 7197 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
7198 | break; |
7199 | default: | |
a737f256 | 7200 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 7201 | res = -1; |
52a46617 | 7202 | } |
0f12244f GN |
7203 | |
7204 | return res; | |
52a46617 GN |
7205 | } |
7206 | ||
717746e3 | 7207 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 7208 | { |
b3646477 | 7209 | return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); |
9c537244 GN |
7210 | } |
7211 | ||
4bff1e86 | 7212 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 7213 | { |
b3646477 | 7214 | static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
7215 | } |
7216 | ||
4bff1e86 | 7217 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 7218 | { |
b3646477 | 7219 | static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
7220 | } |
7221 | ||
1ac9d0cf AK |
7222 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
7223 | { | |
b3646477 | 7224 | static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
7225 | } |
7226 | ||
7227 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
7228 | { | |
b3646477 | 7229 | static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
7230 | } |
7231 | ||
4bff1e86 AK |
7232 | static unsigned long emulator_get_cached_segment_base( |
7233 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 7234 | { |
4bff1e86 | 7235 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
7236 | } |
7237 | ||
1aa36616 AK |
7238 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
7239 | struct desc_struct *desc, u32 *base3, | |
7240 | int seg) | |
2dafc6c2 GN |
7241 | { |
7242 | struct kvm_segment var; | |
7243 | ||
4bff1e86 | 7244 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 7245 | *selector = var.selector; |
2dafc6c2 | 7246 | |
378a8b09 GN |
7247 | if (var.unusable) { |
7248 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
7249 | if (base3) |
7250 | *base3 = 0; | |
2dafc6c2 | 7251 | return false; |
378a8b09 | 7252 | } |
2dafc6c2 GN |
7253 | |
7254 | if (var.g) | |
7255 | var.limit >>= 12; | |
7256 | set_desc_limit(desc, var.limit); | |
7257 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
7258 | #ifdef CONFIG_X86_64 |
7259 | if (base3) | |
7260 | *base3 = var.base >> 32; | |
7261 | #endif | |
2dafc6c2 GN |
7262 | desc->type = var.type; |
7263 | desc->s = var.s; | |
7264 | desc->dpl = var.dpl; | |
7265 | desc->p = var.present; | |
7266 | desc->avl = var.avl; | |
7267 | desc->l = var.l; | |
7268 | desc->d = var.db; | |
7269 | desc->g = var.g; | |
7270 | ||
7271 | return true; | |
7272 | } | |
7273 | ||
1aa36616 AK |
7274 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
7275 | struct desc_struct *desc, u32 base3, | |
7276 | int seg) | |
2dafc6c2 | 7277 | { |
4bff1e86 | 7278 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
7279 | struct kvm_segment var; |
7280 | ||
1aa36616 | 7281 | var.selector = selector; |
2dafc6c2 | 7282 | var.base = get_desc_base(desc); |
5601d05b GN |
7283 | #ifdef CONFIG_X86_64 |
7284 | var.base |= ((u64)base3) << 32; | |
7285 | #endif | |
2dafc6c2 GN |
7286 | var.limit = get_desc_limit(desc); |
7287 | if (desc->g) | |
7288 | var.limit = (var.limit << 12) | 0xfff; | |
7289 | var.type = desc->type; | |
2dafc6c2 GN |
7290 | var.dpl = desc->dpl; |
7291 | var.db = desc->d; | |
7292 | var.s = desc->s; | |
7293 | var.l = desc->l; | |
7294 | var.g = desc->g; | |
7295 | var.avl = desc->avl; | |
7296 | var.present = desc->p; | |
7297 | var.unusable = !var.present; | |
7298 | var.padding = 0; | |
7299 | ||
7300 | kvm_set_segment(vcpu, &var, seg); | |
7301 | return; | |
7302 | } | |
7303 | ||
717746e3 AK |
7304 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
7305 | u32 msr_index, u64 *pdata) | |
7306 | { | |
1ae09954 AG |
7307 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7308 | int r; | |
7309 | ||
7310 | r = kvm_get_msr(vcpu, msr_index, pdata); | |
7311 | ||
7312 | if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { | |
7313 | /* Bounce to user space */ | |
7314 | return X86EMUL_IO_NEEDED; | |
7315 | } | |
7316 | ||
7317 | return r; | |
717746e3 AK |
7318 | } |
7319 | ||
7320 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
7321 | u32 msr_index, u64 data) | |
7322 | { | |
1ae09954 AG |
7323 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7324 | int r; | |
7325 | ||
7326 | r = kvm_set_msr(vcpu, msr_index, data); | |
7327 | ||
7328 | if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { | |
7329 | /* Bounce to user space */ | |
7330 | return X86EMUL_IO_NEEDED; | |
7331 | } | |
7332 | ||
7333 | return r; | |
717746e3 AK |
7334 | } |
7335 | ||
64d60670 PB |
7336 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
7337 | { | |
7338 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7339 | ||
7340 | return vcpu->arch.smbase; | |
7341 | } | |
7342 | ||
7343 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
7344 | { | |
7345 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7346 | ||
7347 | vcpu->arch.smbase = smbase; | |
7348 | } | |
7349 | ||
67f4d428 NA |
7350 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
7351 | u32 pmc) | |
7352 | { | |
98ff80f5 | 7353 | return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
7354 | } |
7355 | ||
222d21aa AK |
7356 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
7357 | u32 pmc, u64 *pdata) | |
7358 | { | |
c6702c9d | 7359 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
7360 | } |
7361 | ||
6c3287f7 AK |
7362 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
7363 | { | |
7364 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
7365 | } | |
7366 | ||
2953538e | 7367 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 7368 | struct x86_instruction_info *info, |
c4f035c6 AK |
7369 | enum x86_intercept_stage stage) |
7370 | { | |
b3646477 | 7371 | return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, |
21f1b8f2 | 7372 | &ctxt->exception); |
c4f035c6 AK |
7373 | } |
7374 | ||
e911eb3b | 7375 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
f91af517 SC |
7376 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, |
7377 | bool exact_only) | |
bdb42f5a | 7378 | { |
f91af517 | 7379 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); |
bdb42f5a SB |
7380 | } |
7381 | ||
5ae78e95 SC |
7382 | static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) |
7383 | { | |
7384 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); | |
7385 | } | |
7386 | ||
7387 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) | |
7388 | { | |
7389 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
7390 | } | |
7391 | ||
7392 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
7393 | { | |
7394 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
7395 | } | |
7396 | ||
dd856efa AK |
7397 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
7398 | { | |
27b4a9c4 | 7399 | return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); |
dd856efa AK |
7400 | } |
7401 | ||
7402 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
7403 | { | |
27b4a9c4 | 7404 | kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); |
dd856efa AK |
7405 | } |
7406 | ||
801806d9 NA |
7407 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
7408 | { | |
b3646477 | 7409 | static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); |
801806d9 NA |
7410 | } |
7411 | ||
6ed071f0 LP |
7412 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
7413 | { | |
7414 | return emul_to_vcpu(ctxt)->arch.hflags; | |
7415 | } | |
7416 | ||
edce4654 | 7417 | static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) |
6ed071f0 | 7418 | { |
78fcb2c9 SC |
7419 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7420 | ||
dc87275f | 7421 | kvm_smm_changed(vcpu, false); |
6ed071f0 LP |
7422 | } |
7423 | ||
ecc513e5 | 7424 | static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, |
ed19321f | 7425 | const char *smstate) |
0234bf88 | 7426 | { |
ecc513e5 | 7427 | return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
7428 | } |
7429 | ||
25b17226 SC |
7430 | static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) |
7431 | { | |
7432 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); | |
7433 | } | |
7434 | ||
02d4160f VK |
7435 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
7436 | { | |
7437 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
7438 | } | |
7439 | ||
0225fb50 | 7440 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
7441 | .read_gpr = emulator_read_gpr, |
7442 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
7443 | .read_std = emulator_read_std, |
7444 | .write_std = emulator_write_std, | |
7a036a6f | 7445 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 7446 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
7447 | .read_emulated = emulator_read_emulated, |
7448 | .write_emulated = emulator_write_emulated, | |
7449 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 7450 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
7451 | .pio_in_emulated = emulator_pio_in_emulated, |
7452 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
7453 | .get_segment = emulator_get_segment, |
7454 | .set_segment = emulator_set_segment, | |
5951c442 | 7455 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 7456 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 7457 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
7458 | .set_gdt = emulator_set_gdt, |
7459 | .set_idt = emulator_set_idt, | |
52a46617 GN |
7460 | .get_cr = emulator_get_cr, |
7461 | .set_cr = emulator_set_cr, | |
9c537244 | 7462 | .cpl = emulator_get_cpl, |
35aa5375 GN |
7463 | .get_dr = emulator_get_dr, |
7464 | .set_dr = emulator_set_dr, | |
64d60670 PB |
7465 | .get_smbase = emulator_get_smbase, |
7466 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
7467 | .set_msr = emulator_set_msr, |
7468 | .get_msr = emulator_get_msr, | |
67f4d428 | 7469 | .check_pmc = emulator_check_pmc, |
222d21aa | 7470 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 7471 | .halt = emulator_halt, |
bcaf5cc5 | 7472 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 7473 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 7474 | .intercept = emulator_intercept, |
bdb42f5a | 7475 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
7476 | .guest_has_long_mode = emulator_guest_has_long_mode, |
7477 | .guest_has_movbe = emulator_guest_has_movbe, | |
7478 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
801806d9 | 7479 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 | 7480 | .get_hflags = emulator_get_hflags, |
edce4654 | 7481 | .exiting_smm = emulator_exiting_smm, |
ecc513e5 | 7482 | .leave_smm = emulator_leave_smm, |
25b17226 | 7483 | .triple_fault = emulator_triple_fault, |
02d4160f | 7484 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
7485 | }; |
7486 | ||
95cb2295 GN |
7487 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
7488 | { | |
b3646477 | 7489 | u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
95cb2295 GN |
7490 | /* |
7491 | * an sti; sti; sequence only disable interrupts for the first | |
7492 | * instruction. So, if the last instruction, be it emulated or | |
7493 | * not, left the system with the INT_STI flag enabled, it | |
7494 | * means that the last instruction is an sti. We should not | |
7495 | * leave the flag on in this case. The same goes for mov ss | |
7496 | */ | |
37ccdcbe PB |
7497 | if (int_shadow & mask) |
7498 | mask = 0; | |
6addfc42 | 7499 | if (unlikely(int_shadow || mask)) { |
b3646477 | 7500 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); |
6addfc42 PB |
7501 | if (!mask) |
7502 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7503 | } | |
95cb2295 GN |
7504 | } |
7505 | ||
ef54bcfe | 7506 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f | 7507 | { |
c9b8b07c | 7508 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
da9cb575 | 7509 | if (ctxt->exception.vector == PF_VECTOR) |
53b3d8e9 | 7510 | return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); |
ef54bcfe PB |
7511 | |
7512 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
7513 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
7514 | ctxt->exception.error_code); | |
54b8486f | 7515 | else |
da9cb575 | 7516 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 7517 | return false; |
54b8486f GN |
7518 | } |
7519 | ||
c9b8b07c SC |
7520 | static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) |
7521 | { | |
7522 | struct x86_emulate_ctxt *ctxt; | |
7523 | ||
7524 | ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); | |
7525 | if (!ctxt) { | |
7526 | pr_err("kvm: failed to allocate vcpu's emulator\n"); | |
7527 | return NULL; | |
7528 | } | |
7529 | ||
7530 | ctxt->vcpu = vcpu; | |
7531 | ctxt->ops = &emulate_ops; | |
7532 | vcpu->arch.emulate_ctxt = ctxt; | |
7533 | ||
7534 | return ctxt; | |
7535 | } | |
7536 | ||
8ec4722d MG |
7537 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
7538 | { | |
c9b8b07c | 7539 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d MG |
7540 | int cs_db, cs_l; |
7541 | ||
b3646477 | 7542 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
8ec4722d | 7543 | |
744e699c | 7544 | ctxt->gpa_available = false; |
adf52235 | 7545 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
7546 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
7547 | ||
adf52235 TY |
7548 | ctxt->eip = kvm_rip_read(vcpu); |
7549 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
7550 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 7551 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
7552 | cs_db ? X86EMUL_MODE_PROT32 : |
7553 | X86EMUL_MODE_PROT16; | |
a584539b | 7554 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
7555 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
7556 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 7557 | |
da6393cd WL |
7558 | ctxt->interruptibility = 0; |
7559 | ctxt->have_exception = false; | |
7560 | ctxt->exception.vector = -1; | |
7561 | ctxt->perm_ok = false; | |
7562 | ||
dd856efa | 7563 | init_decode_cache(ctxt); |
7ae441ea | 7564 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
7565 | } |
7566 | ||
9497e1f2 | 7567 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 7568 | { |
c9b8b07c | 7569 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
63995653 MG |
7570 | int ret; |
7571 | ||
7572 | init_emulate_ctxt(vcpu); | |
7573 | ||
9dac77fa AK |
7574 | ctxt->op_bytes = 2; |
7575 | ctxt->ad_bytes = 2; | |
7576 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 7577 | ret = emulate_int_real(ctxt, irq); |
63995653 | 7578 | |
9497e1f2 SC |
7579 | if (ret != X86EMUL_CONTINUE) { |
7580 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
7581 | } else { | |
7582 | ctxt->eip = ctxt->_eip; | |
7583 | kvm_rip_write(vcpu, ctxt->eip); | |
7584 | kvm_set_rflags(vcpu, ctxt->eflags); | |
7585 | } | |
63995653 MG |
7586 | } |
7587 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
7588 | ||
19238e75 AL |
7589 | static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) |
7590 | { | |
7591 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; | |
7592 | u32 insn_size = ctxt->fetch.end - ctxt->fetch.data; | |
7593 | struct kvm_run *run = vcpu->run; | |
7594 | ||
7595 | run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7596 | run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7597 | run->emulation_failure.ndata = 0; | |
7598 | run->emulation_failure.flags = 0; | |
7599 | ||
7600 | if (insn_size) { | |
7601 | run->emulation_failure.ndata = 3; | |
7602 | run->emulation_failure.flags |= | |
7603 | KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; | |
7604 | run->emulation_failure.insn_size = insn_size; | |
7605 | memset(run->emulation_failure.insn_bytes, 0x90, | |
7606 | sizeof(run->emulation_failure.insn_bytes)); | |
7607 | memcpy(run->emulation_failure.insn_bytes, | |
7608 | ctxt->fetch.data, insn_size); | |
7609 | } | |
7610 | } | |
7611 | ||
e2366171 | 7612 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 7613 | { |
19238e75 AL |
7614 | struct kvm *kvm = vcpu->kvm; |
7615 | ||
6d77dbfc GN |
7616 | ++vcpu->stat.insn_emulation_fail; |
7617 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 7618 | |
42cbf068 SC |
7619 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
7620 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7621 | return 1; |
42cbf068 | 7622 | } |
e2366171 | 7623 | |
19238e75 AL |
7624 | if (kvm->arch.exit_on_emulation_error || |
7625 | (emulation_type & EMULTYPE_SKIP)) { | |
7626 | prepare_emulation_failure_exit(vcpu); | |
60fc3d02 | 7627 | return 0; |
738fece4 SC |
7628 | } |
7629 | ||
22da61c9 SC |
7630 | kvm_queue_exception(vcpu, UD_VECTOR); |
7631 | ||
b3646477 | 7632 | if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { |
fc3a9157 JR |
7633 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
7634 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7635 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7636 | return 0; |
fc3a9157 | 7637 | } |
e2366171 | 7638 | |
60fc3d02 | 7639 | return 1; |
6d77dbfc GN |
7640 | } |
7641 | ||
736c291c | 7642 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 GN |
7643 | bool write_fault_to_shadow_pgtable, |
7644 | int emulation_type) | |
a6f177ef | 7645 | { |
736c291c | 7646 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 7647 | kvm_pfn_t pfn; |
a6f177ef | 7648 | |
92daa48b | 7649 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
991eebf9 GN |
7650 | return false; |
7651 | ||
92daa48b SC |
7652 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7653 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7654 | return false; |
7655 | ||
44dd3ffa | 7656 | if (!vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7657 | /* |
7658 | * Write permission should be allowed since only | |
7659 | * write access need to be emulated. | |
7660 | */ | |
736c291c | 7661 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 7662 | |
95b3cf69 XG |
7663 | /* |
7664 | * If the mapping is invalid in guest, let cpu retry | |
7665 | * it to generate fault. | |
7666 | */ | |
7667 | if (gpa == UNMAPPED_GVA) | |
7668 | return true; | |
7669 | } | |
a6f177ef | 7670 | |
8e3d9d06 XG |
7671 | /* |
7672 | * Do not retry the unhandleable instruction if it faults on the | |
7673 | * readonly host memory, otherwise it will goto a infinite loop: | |
7674 | * retry instruction -> write #PF -> emulation fail -> retry | |
7675 | * instruction -> ... | |
7676 | */ | |
7677 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
7678 | |
7679 | /* | |
7680 | * If the instruction failed on the error pfn, it can not be fixed, | |
7681 | * report the error to userspace. | |
7682 | */ | |
7683 | if (is_error_noslot_pfn(pfn)) | |
7684 | return false; | |
7685 | ||
7686 | kvm_release_pfn_clean(pfn); | |
7687 | ||
7688 | /* The instructions are well-emulated on direct mmu. */ | |
44dd3ffa | 7689 | if (vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7690 | unsigned int indirect_shadow_pages; |
7691 | ||
531810ca | 7692 | write_lock(&vcpu->kvm->mmu_lock); |
95b3cf69 | 7693 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; |
531810ca | 7694 | write_unlock(&vcpu->kvm->mmu_lock); |
95b3cf69 XG |
7695 | |
7696 | if (indirect_shadow_pages) | |
7697 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
7698 | ||
a6f177ef | 7699 | return true; |
8e3d9d06 | 7700 | } |
a6f177ef | 7701 | |
95b3cf69 XG |
7702 | /* |
7703 | * if emulation was due to access to shadowed page table | |
7704 | * and it failed try to unshadow page and re-enter the | |
7705 | * guest to let CPU execute the instruction. | |
7706 | */ | |
7707 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
7708 | |
7709 | /* | |
7710 | * If the access faults on its page table, it can not | |
7711 | * be fixed by unprotecting shadow page and it should | |
7712 | * be reported to userspace. | |
7713 | */ | |
7714 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
7715 | } |
7716 | ||
1cb3f3ae | 7717 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 7718 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
7719 | { |
7720 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 7721 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
7722 | |
7723 | last_retry_eip = vcpu->arch.last_retry_eip; | |
7724 | last_retry_addr = vcpu->arch.last_retry_addr; | |
7725 | ||
7726 | /* | |
7727 | * If the emulation is caused by #PF and it is non-page_table | |
7728 | * writing instruction, it means the VM-EXIT is caused by shadow | |
7729 | * page protected, we can zap the shadow page and retry this | |
7730 | * instruction directly. | |
7731 | * | |
7732 | * Note: if the guest uses a non-page-table modifying instruction | |
7733 | * on the PDE that points to the instruction, then we will unmap | |
7734 | * the instruction and go to an infinite loop. So, we cache the | |
7735 | * last retried eip and the last fault address, if we meet the eip | |
7736 | * and the address again, we can break out of the potential infinite | |
7737 | * loop. | |
7738 | */ | |
7739 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
7740 | ||
92daa48b | 7741 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
1cb3f3ae XG |
7742 | return false; |
7743 | ||
92daa48b SC |
7744 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7745 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7746 | return false; |
7747 | ||
1cb3f3ae XG |
7748 | if (x86_page_table_writing_insn(ctxt)) |
7749 | return false; | |
7750 | ||
736c291c | 7751 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
7752 | return false; |
7753 | ||
7754 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 7755 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 7756 | |
44dd3ffa | 7757 | if (!vcpu->arch.mmu->direct_map) |
736c291c | 7758 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 7759 | |
22368028 | 7760 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
7761 | |
7762 | return true; | |
7763 | } | |
7764 | ||
716d51ab GN |
7765 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
7766 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
7767 | ||
dc87275f | 7768 | static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) |
a584539b | 7769 | { |
1270e647 | 7770 | trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); |
0d7ee6f4 | 7771 | |
dc87275f SC |
7772 | if (entering_smm) { |
7773 | vcpu->arch.hflags |= HF_SMM_MASK; | |
7774 | } else { | |
7775 | vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); | |
7776 | ||
c43203ca PB |
7777 | /* Process a latched INIT or SMI, if any. */ |
7778 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
37687c40 ML |
7779 | |
7780 | /* | |
7781 | * Even if KVM_SET_SREGS2 loaded PDPTRs out of band, | |
7782 | * on SMM exit we still need to reload them from | |
7783 | * guest memory | |
7784 | */ | |
7785 | vcpu->arch.pdptrs_from_userspace = false; | |
64d60670 | 7786 | } |
699023e2 PB |
7787 | |
7788 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
7789 | } |
7790 | ||
4a1e10d5 PB |
7791 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
7792 | unsigned long *db) | |
7793 | { | |
7794 | u32 dr6 = 0; | |
7795 | int i; | |
7796 | u32 enable, rwlen; | |
7797 | ||
7798 | enable = dr7; | |
7799 | rwlen = dr7 >> 16; | |
7800 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
7801 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
7802 | dr6 |= (1 << i); | |
7803 | return dr6; | |
7804 | } | |
7805 | ||
120c2c4f | 7806 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
7807 | { |
7808 | struct kvm_run *kvm_run = vcpu->run; | |
7809 | ||
c8401dda | 7810 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
9a3ecd5e | 7811 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; |
d5d260c5 | 7812 | kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
c8401dda PB |
7813 | kvm_run->debug.arch.exception = DB_VECTOR; |
7814 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7815 | return 0; |
663f4c61 | 7816 | } |
120c2c4f | 7817 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 7818 | return 1; |
663f4c61 PB |
7819 | } |
7820 | ||
6affcbed KH |
7821 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
7822 | { | |
b3646477 | 7823 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
f8ea7c60 | 7824 | int r; |
6affcbed | 7825 | |
b3646477 | 7826 | r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); |
60fc3d02 | 7827 | if (unlikely(!r)) |
f8ea7c60 | 7828 | return 0; |
c8401dda PB |
7829 | |
7830 | /* | |
7831 | * rflags is the old, "raw" value of the flags. The new value has | |
7832 | * not been saved yet. | |
7833 | * | |
7834 | * This is correct even for TF set by the guest, because "the | |
7835 | * processor will not generate this exception after the instruction | |
7836 | * that sets the TF flag". | |
7837 | */ | |
7838 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 7839 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 7840 | return r; |
6affcbed KH |
7841 | } |
7842 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
7843 | ||
4a1e10d5 PB |
7844 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
7845 | { | |
4a1e10d5 PB |
7846 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
7847 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
7848 | struct kvm_run *kvm_run = vcpu->run; |
7849 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
7850 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7851 | vcpu->arch.guest_debug_dr7, |
7852 | vcpu->arch.eff_db); | |
7853 | ||
7854 | if (dr6 != 0) { | |
9a3ecd5e | 7855 | kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; |
82b32774 | 7856 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
7857 | kvm_run->debug.arch.exception = DB_VECTOR; |
7858 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7859 | *r = 0; |
4a1e10d5 PB |
7860 | return true; |
7861 | } | |
7862 | } | |
7863 | ||
4161a569 NA |
7864 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
7865 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
7866 | unsigned long eip = kvm_get_linear_rip(vcpu); |
7867 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7868 | vcpu->arch.dr7, |
7869 | vcpu->arch.db); | |
7870 | ||
7871 | if (dr6 != 0) { | |
4d5523cf | 7872 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
60fc3d02 | 7873 | *r = 1; |
4a1e10d5 PB |
7874 | return true; |
7875 | } | |
7876 | } | |
7877 | ||
7878 | return false; | |
7879 | } | |
7880 | ||
04789b66 LA |
7881 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
7882 | { | |
2d7921c4 AM |
7883 | switch (ctxt->opcode_len) { |
7884 | case 1: | |
7885 | switch (ctxt->b) { | |
7886 | case 0xe4: /* IN */ | |
7887 | case 0xe5: | |
7888 | case 0xec: | |
7889 | case 0xed: | |
7890 | case 0xe6: /* OUT */ | |
7891 | case 0xe7: | |
7892 | case 0xee: | |
7893 | case 0xef: | |
7894 | case 0x6c: /* INS */ | |
7895 | case 0x6d: | |
7896 | case 0x6e: /* OUTS */ | |
7897 | case 0x6f: | |
7898 | return true; | |
7899 | } | |
7900 | break; | |
7901 | case 2: | |
7902 | switch (ctxt->b) { | |
7903 | case 0x33: /* RDPMC */ | |
7904 | return true; | |
7905 | } | |
7906 | break; | |
04789b66 LA |
7907 | } |
7908 | ||
7909 | return false; | |
7910 | } | |
7911 | ||
4aa2691d WH |
7912 | /* |
7913 | * Decode to be emulated instruction. Return EMULATION_OK if success. | |
7914 | */ | |
7915 | int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, | |
7916 | void *insn, int insn_len) | |
7917 | { | |
7918 | int r = EMULATION_OK; | |
7919 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; | |
7920 | ||
7921 | init_emulate_ctxt(vcpu); | |
7922 | ||
7923 | /* | |
7924 | * We will reenter on the same instruction since we do not set | |
7925 | * complete_userspace_io. This does not handle watchpoints yet, | |
7926 | * those would be handled in the emulate_ops. | |
7927 | */ | |
7928 | if (!(emulation_type & EMULTYPE_SKIP) && | |
7929 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
7930 | return r; | |
7931 | ||
b35491e6 | 7932 | r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); |
4aa2691d WH |
7933 | |
7934 | trace_kvm_emulate_insn_start(vcpu); | |
7935 | ++vcpu->stat.insn_emulation; | |
7936 | ||
7937 | return r; | |
7938 | } | |
7939 | EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); | |
7940 | ||
736c291c SC |
7941 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
7942 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 7943 | { |
95cb2295 | 7944 | int r; |
c9b8b07c | 7945 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
7ae441ea | 7946 | bool writeback = true; |
09e3e2a1 SC |
7947 | bool write_fault_to_spt; |
7948 | ||
b3646477 | 7949 | if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) |
09e3e2a1 | 7950 | return 1; |
bbd9b64e | 7951 | |
c595ceee PB |
7952 | vcpu->arch.l1tf_flush_l1d = true; |
7953 | ||
93c05d3e XG |
7954 | /* |
7955 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
7956 | * never reused. | |
7957 | */ | |
09e3e2a1 | 7958 | write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
93c05d3e | 7959 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
8d7d8102 | 7960 | |
571008da | 7961 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
4aa2691d | 7962 | kvm_clear_exception_queue(vcpu); |
4a1e10d5 | 7963 | |
4aa2691d WH |
7964 | r = x86_decode_emulated_instruction(vcpu, emulation_type, |
7965 | insn, insn_len); | |
1d2887e2 | 7966 | if (r != EMULATION_OK) { |
b4000606 | 7967 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
7968 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
7969 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 7970 | return 1; |
c83fad65 | 7971 | } |
736c291c SC |
7972 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
7973 | write_fault_to_spt, | |
7974 | emulation_type)) | |
60fc3d02 | 7975 | return 1; |
8530a79c | 7976 | if (ctxt->have_exception) { |
c8848cee JD |
7977 | /* |
7978 | * #UD should result in just EMULATION_FAILED, and trap-like | |
7979 | * exception should not be encountered during decode. | |
7980 | */ | |
7981 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
7982 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 7983 | inject_emulated_exception(vcpu); |
60fc3d02 | 7984 | return 1; |
8530a79c | 7985 | } |
e2366171 | 7986 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7987 | } |
7988 | } | |
7989 | ||
42cbf068 SC |
7990 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
7991 | !is_vmware_backdoor_opcode(ctxt)) { | |
7992 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7993 | return 1; |
42cbf068 | 7994 | } |
04789b66 | 7995 | |
1957aa63 SC |
7996 | /* |
7997 | * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks | |
7998 | * for kvm_skip_emulated_instruction(). The caller is responsible for | |
7999 | * updating interruptibility state and injecting single-step #DBs. | |
8000 | */ | |
ba8afb6b | 8001 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 8002 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
8003 | if (ctxt->eflags & X86_EFLAGS_RF) |
8004 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 8005 | return 1; |
ba8afb6b GN |
8006 | } |
8007 | ||
736c291c | 8008 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 8009 | return 1; |
1cb3f3ae | 8010 | |
7ae441ea | 8011 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 8012 | changes registers values during IO operation */ |
7ae441ea GN |
8013 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
8014 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 8015 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 8016 | } |
4d2179e1 | 8017 | |
5cd21917 | 8018 | restart: |
92daa48b SC |
8019 | if (emulation_type & EMULTYPE_PF) { |
8020 | /* Save the faulting GPA (cr2) in the address field */ | |
8021 | ctxt->exception.address = cr2_or_gpa; | |
8022 | ||
8023 | /* With shadow page tables, cr2 contains a GVA or nGPA. */ | |
8024 | if (vcpu->arch.mmu->direct_map) { | |
744e699c SC |
8025 | ctxt->gpa_available = true; |
8026 | ctxt->gpa_val = cr2_or_gpa; | |
92daa48b SC |
8027 | } |
8028 | } else { | |
8029 | /* Sanitize the address out of an abundance of paranoia. */ | |
8030 | ctxt->exception.address = 0; | |
8031 | } | |
0f89b207 | 8032 | |
9d74191a | 8033 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 8034 | |
775fde86 | 8035 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 8036 | return 1; |
775fde86 | 8037 | |
d2ddd1c4 | 8038 | if (r == EMULATION_FAILED) { |
736c291c | 8039 | if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, |
991eebf9 | 8040 | emulation_type)) |
60fc3d02 | 8041 | return 1; |
c3cd7ffa | 8042 | |
e2366171 | 8043 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
8044 | } |
8045 | ||
9d74191a | 8046 | if (ctxt->have_exception) { |
60fc3d02 | 8047 | r = 1; |
ef54bcfe PB |
8048 | if (inject_emulated_exception(vcpu)) |
8049 | return r; | |
d2ddd1c4 | 8050 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
8051 | if (!vcpu->arch.pio.in) { |
8052 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 8053 | vcpu->arch.pio.count = 0; |
0912c977 | 8054 | } else { |
7ae441ea | 8055 | writeback = false; |
716d51ab GN |
8056 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
8057 | } | |
60fc3d02 | 8058 | r = 0; |
7ae441ea | 8059 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
8060 | ++vcpu->stat.mmio_exits; |
8061 | ||
7ae441ea GN |
8062 | if (!vcpu->mmio_is_write) |
8063 | writeback = false; | |
60fc3d02 | 8064 | r = 0; |
716d51ab | 8065 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 8066 | } else if (r == EMULATION_RESTART) |
5cd21917 | 8067 | goto restart; |
d2ddd1c4 | 8068 | else |
60fc3d02 | 8069 | r = 1; |
f850e2e6 | 8070 | |
7ae441ea | 8071 | if (writeback) { |
b3646477 | 8072 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
9d74191a | 8073 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 8074 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
38827dbd | 8075 | if (!ctxt->have_exception || |
75ee23b3 SC |
8076 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
8077 | kvm_rip_write(vcpu, ctxt->eip); | |
384dea1c | 8078 | if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) |
120c2c4f | 8079 | r = kvm_vcpu_do_singlestep(vcpu); |
afaf0b2f | 8080 | if (kvm_x86_ops.update_emulated_instruction) |
b3646477 | 8081 | static_call(kvm_x86_update_emulated_instruction)(vcpu); |
38827dbd | 8082 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 8083 | } |
6addfc42 PB |
8084 | |
8085 | /* | |
8086 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
8087 | * do nothing, and it will be requested again as soon as | |
8088 | * the shadow expires. But we still need to check here, | |
8089 | * because POPF has no interrupt shadow. | |
8090 | */ | |
8091 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
8092 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
8093 | } else |
8094 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
8095 | |
8096 | return r; | |
de7d789a | 8097 | } |
c60658d1 SC |
8098 | |
8099 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
8100 | { | |
8101 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
8102 | } | |
8103 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
8104 | ||
8105 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
8106 | void *insn, int insn_len) | |
8107 | { | |
8108 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
8109 | } | |
8110 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 8111 | |
8764ed55 SC |
8112 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
8113 | { | |
8114 | vcpu->arch.pio.count = 0; | |
8115 | return 1; | |
8116 | } | |
8117 | ||
45def77e SC |
8118 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
8119 | { | |
8120 | vcpu->arch.pio.count = 0; | |
8121 | ||
8122 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
8123 | return 1; | |
8124 | ||
8125 | return kvm_skip_emulated_instruction(vcpu); | |
8126 | } | |
8127 | ||
dca7f128 SC |
8128 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
8129 | unsigned short port) | |
de7d789a | 8130 | { |
de3cd117 | 8131 | unsigned long val = kvm_rax_read(vcpu); |
2e3bb4d8 SC |
8132 | int ret = emulator_pio_out(vcpu, size, port, &val, 1); |
8133 | ||
8764ed55 SC |
8134 | if (ret) |
8135 | return ret; | |
45def77e | 8136 | |
8764ed55 SC |
8137 | /* |
8138 | * Workaround userspace that relies on old KVM behavior of %rip being | |
8139 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
8140 | */ | |
8141 | if (port == 0x7e && | |
8142 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
8143 | vcpu->arch.complete_userspace_io = | |
8144 | complete_fast_pio_out_port_0x7e; | |
8145 | kvm_skip_emulated_instruction(vcpu); | |
8146 | } else { | |
45def77e SC |
8147 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8148 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
8149 | } | |
8764ed55 | 8150 | return 0; |
de7d789a | 8151 | } |
de7d789a | 8152 | |
8370c3d0 TL |
8153 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
8154 | { | |
8155 | unsigned long val; | |
8156 | ||
8157 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
8158 | BUG_ON(vcpu->arch.pio.count != 1); | |
8159 | ||
45def77e SC |
8160 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
8161 | vcpu->arch.pio.count = 0; | |
8162 | return 1; | |
8163 | } | |
8164 | ||
8370c3d0 | 8165 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 8166 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
8167 | |
8168 | /* | |
2e3bb4d8 | 8169 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform |
8370c3d0 TL |
8170 | * the copy and tracing |
8171 | */ | |
2e3bb4d8 | 8172 | emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); |
de3cd117 | 8173 | kvm_rax_write(vcpu, val); |
8370c3d0 | 8174 | |
45def77e | 8175 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
8176 | } |
8177 | ||
dca7f128 SC |
8178 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
8179 | unsigned short port) | |
8370c3d0 TL |
8180 | { |
8181 | unsigned long val; | |
8182 | int ret; | |
8183 | ||
8184 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 8185 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 8186 | |
2e3bb4d8 | 8187 | ret = emulator_pio_in(vcpu, size, port, &val, 1); |
8370c3d0 | 8188 | if (ret) { |
de3cd117 | 8189 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
8190 | return ret; |
8191 | } | |
8192 | ||
45def77e | 8193 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
8194 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
8195 | ||
8196 | return 0; | |
8197 | } | |
dca7f128 SC |
8198 | |
8199 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
8200 | { | |
45def77e | 8201 | int ret; |
dca7f128 | 8202 | |
dca7f128 | 8203 | if (in) |
45def77e | 8204 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 8205 | else |
45def77e SC |
8206 | ret = kvm_fast_pio_out(vcpu, size, port); |
8207 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
8208 | } |
8209 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 8210 | |
251a5fd6 | 8211 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 8212 | { |
0a3aee0d | 8213 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 8214 | return 0; |
8cfdc000 ZA |
8215 | } |
8216 | ||
8217 | static void tsc_khz_changed(void *data) | |
c8076604 | 8218 | { |
8cfdc000 ZA |
8219 | struct cpufreq_freqs *freq = data; |
8220 | unsigned long khz = 0; | |
8221 | ||
8222 | if (data) | |
8223 | khz = freq->new; | |
8224 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
8225 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
8226 | if (!khz) | |
8227 | khz = tsc_khz; | |
0a3aee0d | 8228 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
8229 | } |
8230 | ||
5fa4ec9c | 8231 | #ifdef CONFIG_X86_64 |
0092e434 VK |
8232 | static void kvm_hyperv_tsc_notifier(void) |
8233 | { | |
0092e434 VK |
8234 | struct kvm *kvm; |
8235 | struct kvm_vcpu *vcpu; | |
8236 | int cpu; | |
a83829f5 | 8237 | unsigned long flags; |
0092e434 | 8238 | |
0d9ce162 | 8239 | mutex_lock(&kvm_lock); |
0092e434 VK |
8240 | list_for_each_entry(kvm, &vm_list, vm_list) |
8241 | kvm_make_mclock_inprogress_request(kvm); | |
8242 | ||
8243 | hyperv_stop_tsc_emulation(); | |
8244 | ||
8245 | /* TSC frequency always matches when on Hyper-V */ | |
8246 | for_each_present_cpu(cpu) | |
8247 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
8248 | kvm_max_guest_tsc_khz = tsc_khz; | |
8249 | ||
8250 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
8251 | struct kvm_arch *ka = &kvm->arch; | |
8252 | ||
8228c77d | 8253 | raw_spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
0092e434 | 8254 | pvclock_update_vm_gtod_copy(kvm); |
8228c77d | 8255 | raw_spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
0092e434 VK |
8256 | |
8257 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
8258 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
8259 | ||
8260 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
8261 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); | |
0092e434 | 8262 | } |
0d9ce162 | 8263 | mutex_unlock(&kvm_lock); |
0092e434 | 8264 | } |
5fa4ec9c | 8265 | #endif |
0092e434 | 8266 | |
df24014a | 8267 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 8268 | { |
c8076604 GH |
8269 | struct kvm *kvm; |
8270 | struct kvm_vcpu *vcpu; | |
8271 | int i, send_ipi = 0; | |
8272 | ||
8cfdc000 ZA |
8273 | /* |
8274 | * We allow guests to temporarily run on slowing clocks, | |
8275 | * provided we notify them after, or to run on accelerating | |
8276 | * clocks, provided we notify them before. Thus time never | |
8277 | * goes backwards. | |
8278 | * | |
8279 | * However, we have a problem. We can't atomically update | |
8280 | * the frequency of a given CPU from this function; it is | |
8281 | * merely a notifier, which can be called from any CPU. | |
8282 | * Changing the TSC frequency at arbitrary points in time | |
8283 | * requires a recomputation of local variables related to | |
8284 | * the TSC for each VCPU. We must flag these local variables | |
8285 | * to be updated and be sure the update takes place with the | |
8286 | * new frequency before any guests proceed. | |
8287 | * | |
8288 | * Unfortunately, the combination of hotplug CPU and frequency | |
8289 | * change creates an intractable locking scenario; the order | |
8290 | * of when these callouts happen is undefined with respect to | |
8291 | * CPU hotplug, and they can race with each other. As such, | |
8292 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
8293 | * undefined; you can actually have a CPU frequency change take | |
8294 | * place in between the computation of X and the setting of the | |
8295 | * variable. To protect against this problem, all updates of | |
8296 | * the per_cpu tsc_khz variable are done in an interrupt | |
8297 | * protected IPI, and all callers wishing to update the value | |
8298 | * must wait for a synchronous IPI to complete (which is trivial | |
8299 | * if the caller is on the CPU already). This establishes the | |
8300 | * necessary total order on variable updates. | |
8301 | * | |
8302 | * Note that because a guest time update may take place | |
8303 | * anytime after the setting of the VCPU's request bit, the | |
8304 | * correct TSC value must be set before the request. However, | |
8305 | * to ensure the update actually makes it to any guest which | |
8306 | * starts running in hardware virtualization between the set | |
8307 | * and the acquisition of the spinlock, we must also ping the | |
8308 | * CPU after setting the request bit. | |
8309 | * | |
8310 | */ | |
8311 | ||
df24014a | 8312 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 8313 | |
0d9ce162 | 8314 | mutex_lock(&kvm_lock); |
c8076604 | 8315 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 8316 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 8317 | if (vcpu->cpu != cpu) |
c8076604 | 8318 | continue; |
c285545f | 8319 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 8320 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 8321 | send_ipi = 1; |
c8076604 GH |
8322 | } |
8323 | } | |
0d9ce162 | 8324 | mutex_unlock(&kvm_lock); |
c8076604 GH |
8325 | |
8326 | if (freq->old < freq->new && send_ipi) { | |
8327 | /* | |
8328 | * We upscale the frequency. Must make the guest | |
8329 | * doesn't see old kvmclock values while running with | |
8330 | * the new frequency, otherwise we risk the guest sees | |
8331 | * time go backwards. | |
8332 | * | |
8333 | * In case we update the frequency for another cpu | |
8334 | * (which might be in guest context) send an interrupt | |
8335 | * to kick the cpu out of guest context. Next time | |
8336 | * guest context is entered kvmclock will be updated, | |
8337 | * so the guest will not see stale values. | |
8338 | */ | |
df24014a | 8339 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 8340 | } |
df24014a VK |
8341 | } |
8342 | ||
8343 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
8344 | void *data) | |
8345 | { | |
8346 | struct cpufreq_freqs *freq = data; | |
8347 | int cpu; | |
8348 | ||
8349 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
8350 | return 0; | |
8351 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
8352 | return 0; | |
8353 | ||
8354 | for_each_cpu(cpu, freq->policy->cpus) | |
8355 | __kvmclock_cpufreq_notifier(freq, cpu); | |
8356 | ||
c8076604 GH |
8357 | return 0; |
8358 | } | |
8359 | ||
8360 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
8361 | .notifier_call = kvmclock_cpufreq_notifier |
8362 | }; | |
8363 | ||
251a5fd6 | 8364 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 8365 | { |
251a5fd6 SAS |
8366 | tsc_khz_changed(NULL); |
8367 | return 0; | |
8cfdc000 ZA |
8368 | } |
8369 | ||
b820cc0c ZA |
8370 | static void kvm_timer_init(void) |
8371 | { | |
c285545f | 8372 | max_tsc_khz = tsc_khz; |
460dd42e | 8373 | |
b820cc0c | 8374 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f | 8375 | #ifdef CONFIG_CPU_FREQ |
aaec7c03 | 8376 | struct cpufreq_policy *policy; |
758f588d BP |
8377 | int cpu; |
8378 | ||
3e26f230 | 8379 | cpu = get_cpu(); |
aaec7c03 | 8380 | policy = cpufreq_cpu_get(cpu); |
9a11997e WL |
8381 | if (policy) { |
8382 | if (policy->cpuinfo.max_freq) | |
8383 | max_tsc_khz = policy->cpuinfo.max_freq; | |
8384 | cpufreq_cpu_put(policy); | |
8385 | } | |
3e26f230 | 8386 | put_cpu(); |
c285545f | 8387 | #endif |
b820cc0c ZA |
8388 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
8389 | CPUFREQ_TRANSITION_NOTIFIER); | |
8390 | } | |
460dd42e | 8391 | |
73c1b41e | 8392 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 8393 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
8394 | } |
8395 | ||
dd60d217 AK |
8396 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
8397 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 8398 | |
f5132b01 | 8399 | int kvm_is_in_guest(void) |
ff9d07a0 | 8400 | { |
086c9855 | 8401 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
8402 | } |
8403 | ||
8404 | static int kvm_is_user_mode(void) | |
8405 | { | |
8406 | int user_mode = 3; | |
dcf46b94 | 8407 | |
086c9855 | 8408 | if (__this_cpu_read(current_vcpu)) |
b3646477 | 8409 | user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu)); |
dcf46b94 | 8410 | |
ff9d07a0 ZY |
8411 | return user_mode != 0; |
8412 | } | |
8413 | ||
8414 | static unsigned long kvm_get_guest_ip(void) | |
8415 | { | |
8416 | unsigned long ip = 0; | |
dcf46b94 | 8417 | |
086c9855 AS |
8418 | if (__this_cpu_read(current_vcpu)) |
8419 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 8420 | |
ff9d07a0 ZY |
8421 | return ip; |
8422 | } | |
8423 | ||
8479e04e LK |
8424 | static void kvm_handle_intel_pt_intr(void) |
8425 | { | |
8426 | struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); | |
8427 | ||
8428 | kvm_make_request(KVM_REQ_PMI, vcpu); | |
8429 | __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, | |
8430 | (unsigned long *)&vcpu->arch.pmu.global_status); | |
8431 | } | |
8432 | ||
ff9d07a0 ZY |
8433 | static struct perf_guest_info_callbacks kvm_guest_cbs = { |
8434 | .is_in_guest = kvm_is_in_guest, | |
8435 | .is_user_mode = kvm_is_user_mode, | |
8436 | .get_guest_ip = kvm_get_guest_ip, | |
f2b7891e | 8437 | .handle_intel_pt_intr = NULL, |
ff9d07a0 ZY |
8438 | }; |
8439 | ||
16e8d74d MT |
8440 | #ifdef CONFIG_X86_64 |
8441 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
8442 | { | |
d828199e MT |
8443 | struct kvm *kvm; |
8444 | ||
8445 | struct kvm_vcpu *vcpu; | |
8446 | int i; | |
8447 | ||
0d9ce162 | 8448 | mutex_lock(&kvm_lock); |
d828199e MT |
8449 | list_for_each_entry(kvm, &vm_list, vm_list) |
8450 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 8451 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 8452 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 8453 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
8454 | } |
8455 | ||
8456 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
8457 | ||
3f804f6d TG |
8458 | /* |
8459 | * Indirection to move queue_work() out of the tk_core.seq write held | |
8460 | * region to prevent possible deadlocks against time accessors which | |
8461 | * are invoked with work related locks held. | |
8462 | */ | |
8463 | static void pvclock_irq_work_fn(struct irq_work *w) | |
8464 | { | |
8465 | queue_work(system_long_wq, &pvclock_gtod_work); | |
8466 | } | |
8467 | ||
8468 | static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); | |
8469 | ||
16e8d74d MT |
8470 | /* |
8471 | * Notification about pvclock gtod data update. | |
8472 | */ | |
8473 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
8474 | void *priv) | |
8475 | { | |
8476 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
8477 | struct timekeeper *tk = priv; | |
8478 | ||
8479 | update_pvclock_gtod(tk); | |
8480 | ||
3f804f6d TG |
8481 | /* |
8482 | * Disable master clock if host does not trust, or does not use, | |
8483 | * TSC based clocksource. Delegate queue_work() to irq_work as | |
8484 | * this is invoked with tk_core.seq write held. | |
16e8d74d | 8485 | */ |
b0c39dc6 | 8486 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d | 8487 | atomic_read(&kvm_guest_has_master_clock) != 0) |
3f804f6d | 8488 | irq_work_queue(&pvclock_irq_work); |
16e8d74d MT |
8489 | return 0; |
8490 | } | |
8491 | ||
8492 | static struct notifier_block pvclock_gtod_notifier = { | |
8493 | .notifier_call = pvclock_gtod_notify, | |
8494 | }; | |
8495 | #endif | |
8496 | ||
f8c16bba | 8497 | int kvm_arch_init(void *opaque) |
043405e1 | 8498 | { |
d008dfdb | 8499 | struct kvm_x86_init_ops *ops = opaque; |
b820cc0c | 8500 | int r; |
f8c16bba | 8501 | |
afaf0b2f | 8502 | if (kvm_x86_ops.hardware_enable) { |
f8c16bba | 8503 | printk(KERN_ERR "kvm: already loaded the other module\n"); |
56c6d28a ZX |
8504 | r = -EEXIST; |
8505 | goto out; | |
f8c16bba ZX |
8506 | } |
8507 | ||
8508 | if (!ops->cpu_has_kvm_support()) { | |
ef935c25 | 8509 | pr_err_ratelimited("kvm: no hardware support\n"); |
56c6d28a ZX |
8510 | r = -EOPNOTSUPP; |
8511 | goto out; | |
f8c16bba ZX |
8512 | } |
8513 | if (ops->disabled_by_bios()) { | |
5a4d224d | 8514 | pr_warn_ratelimited("kvm: disabled by bios\n"); |
56c6d28a ZX |
8515 | r = -EOPNOTSUPP; |
8516 | goto out; | |
f8c16bba ZX |
8517 | } |
8518 | ||
b666a4b6 MO |
8519 | /* |
8520 | * KVM explicitly assumes that the guest has an FPU and | |
8521 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
8522 | * vCPU's FPU state as a fxregs_state struct. | |
8523 | */ | |
8524 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
8525 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
8526 | r = -EOPNOTSUPP; | |
8527 | goto out; | |
8528 | } | |
8529 | ||
013f6a5d | 8530 | r = -ENOMEM; |
ed8e4812 | 8531 | x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), |
b666a4b6 MO |
8532 | __alignof__(struct fpu), SLAB_ACCOUNT, |
8533 | NULL); | |
8534 | if (!x86_fpu_cache) { | |
8535 | printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); | |
8536 | goto out; | |
8537 | } | |
8538 | ||
c9b8b07c SC |
8539 | x86_emulator_cache = kvm_alloc_emulator_cache(); |
8540 | if (!x86_emulator_cache) { | |
8541 | pr_err("kvm: failed to allocate cache for x86 emulator\n"); | |
8542 | goto out_free_x86_fpu_cache; | |
8543 | } | |
8544 | ||
7e34fbd0 SC |
8545 | user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); |
8546 | if (!user_return_msrs) { | |
8547 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); | |
c9b8b07c | 8548 | goto out_free_x86_emulator_cache; |
013f6a5d | 8549 | } |
e5fda4bb | 8550 | kvm_nr_uret_msrs = 0; |
013f6a5d | 8551 | |
97db56ce AK |
8552 | r = kvm_mmu_module_init(); |
8553 | if (r) | |
013f6a5d | 8554 | goto out_free_percpu; |
97db56ce | 8555 | |
b820cc0c | 8556 | kvm_timer_init(); |
c8076604 | 8557 | |
cfc48181 | 8558 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
2acf923e | 8559 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
cfc48181 SC |
8560 | supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; |
8561 | } | |
2acf923e | 8562 | |
0c5f81da WL |
8563 | if (pi_inject_timer == -1) |
8564 | pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); | |
16e8d74d MT |
8565 | #ifdef CONFIG_X86_64 |
8566 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 8567 | |
5fa4ec9c | 8568 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 8569 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
8570 | #endif |
8571 | ||
f8c16bba | 8572 | return 0; |
56c6d28a | 8573 | |
013f6a5d | 8574 | out_free_percpu: |
7e34fbd0 | 8575 | free_percpu(user_return_msrs); |
c9b8b07c SC |
8576 | out_free_x86_emulator_cache: |
8577 | kmem_cache_destroy(x86_emulator_cache); | |
b666a4b6 MO |
8578 | out_free_x86_fpu_cache: |
8579 | kmem_cache_destroy(x86_fpu_cache); | |
56c6d28a | 8580 | out: |
56c6d28a | 8581 | return r; |
043405e1 | 8582 | } |
8776e519 | 8583 | |
f8c16bba ZX |
8584 | void kvm_arch_exit(void) |
8585 | { | |
0092e434 | 8586 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 8587 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
8588 | clear_hv_tscchange_cb(); |
8589 | #endif | |
cef84c30 | 8590 | kvm_lapic_exit(); |
ff9d07a0 | 8591 | |
888d256e JK |
8592 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
8593 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
8594 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 8595 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
8596 | #ifdef CONFIG_X86_64 |
8597 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
3f804f6d | 8598 | irq_work_sync(&pvclock_irq_work); |
594b27e6 | 8599 | cancel_work_sync(&pvclock_gtod_work); |
16e8d74d | 8600 | #endif |
afaf0b2f | 8601 | kvm_x86_ops.hardware_enable = NULL; |
56c6d28a | 8602 | kvm_mmu_module_exit(); |
7e34fbd0 | 8603 | free_percpu(user_return_msrs); |
dfdc0a71 | 8604 | kmem_cache_destroy(x86_emulator_cache); |
b666a4b6 | 8605 | kmem_cache_destroy(x86_fpu_cache); |
b59b153d | 8606 | #ifdef CONFIG_KVM_XEN |
c462f859 | 8607 | static_key_deferred_flush(&kvm_xen_enabled); |
7d6bbebb | 8608 | WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); |
b59b153d | 8609 | #endif |
56c6d28a | 8610 | } |
f8c16bba | 8611 | |
872f36eb | 8612 | static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) |
8776e519 HB |
8613 | { |
8614 | ++vcpu->stat.halt_exits; | |
35754c98 | 8615 | if (lapic_in_kernel(vcpu)) { |
647daca2 | 8616 | vcpu->arch.mp_state = state; |
8776e519 HB |
8617 | return 1; |
8618 | } else { | |
647daca2 | 8619 | vcpu->run->exit_reason = reason; |
8776e519 HB |
8620 | return 0; |
8621 | } | |
8622 | } | |
647daca2 TL |
8623 | |
8624 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) | |
8625 | { | |
8626 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); | |
8627 | } | |
5cb56059 JS |
8628 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
8629 | ||
8630 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
8631 | { | |
6affcbed KH |
8632 | int ret = kvm_skip_emulated_instruction(vcpu); |
8633 | /* | |
8634 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
8635 | * KVM_EXIT_DEBUG here. | |
8636 | */ | |
8637 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 8638 | } |
8776e519 HB |
8639 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
8640 | ||
647daca2 TL |
8641 | int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) |
8642 | { | |
8643 | int ret = kvm_skip_emulated_instruction(vcpu); | |
8644 | ||
8645 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; | |
8646 | } | |
8647 | EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); | |
8648 | ||
8ef81a9a | 8649 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8650 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
8651 | unsigned long clock_type) | |
8652 | { | |
8653 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 8654 | struct timespec64 ts; |
80fbd89c | 8655 | u64 cycle; |
55dd00a7 MT |
8656 | int ret; |
8657 | ||
8658 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
8659 | return -KVM_EOPNOTSUPP; | |
8660 | ||
7ca7f3b9 | 8661 | if (!kvm_get_walltime_and_clockread(&ts, &cycle)) |
55dd00a7 MT |
8662 | return -KVM_EOPNOTSUPP; |
8663 | ||
8664 | clock_pairing.sec = ts.tv_sec; | |
8665 | clock_pairing.nsec = ts.tv_nsec; | |
8666 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
8667 | clock_pairing.flags = 0; | |
bcbfbd8e | 8668 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
8669 | |
8670 | ret = 0; | |
8671 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
8672 | sizeof(struct kvm_clock_pairing))) | |
8673 | ret = -KVM_EFAULT; | |
8674 | ||
8675 | return ret; | |
8676 | } | |
8ef81a9a | 8677 | #endif |
55dd00a7 | 8678 | |
6aef266c SV |
8679 | /* |
8680 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
8681 | * | |
8682 | * @apicid - apicid of vcpu to be kicked. | |
8683 | */ | |
8684 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
8685 | { | |
24d2166b | 8686 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 8687 | |
150a84fe | 8688 | lapic_irq.shorthand = APIC_DEST_NOSHORT; |
c96001c5 | 8689 | lapic_irq.dest_mode = APIC_DEST_PHYSICAL; |
ebd28fcb | 8690 | lapic_irq.level = 0; |
24d2166b | 8691 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 8692 | lapic_irq.msi_redir_hint = false; |
6aef266c | 8693 | |
24d2166b | 8694 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 8695 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
8696 | } |
8697 | ||
4e19c36f SS |
8698 | bool kvm_apicv_activated(struct kvm *kvm) |
8699 | { | |
8700 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
8701 | } | |
8702 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
8703 | ||
4651fc56 | 8704 | static void kvm_apicv_init(struct kvm *kvm) |
4e19c36f | 8705 | { |
b0a1637f ML |
8706 | mutex_init(&kvm->arch.apicv_update_lock); |
8707 | ||
4651fc56 | 8708 | if (enable_apicv) |
4e19c36f SS |
8709 | clear_bit(APICV_INHIBIT_REASON_DISABLE, |
8710 | &kvm->arch.apicv_inhibit_reasons); | |
8711 | else | |
8712 | set_bit(APICV_INHIBIT_REASON_DISABLE, | |
8713 | &kvm->arch.apicv_inhibit_reasons); | |
8714 | } | |
4e19c36f | 8715 | |
4a7132ef | 8716 | static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) |
71506297 WL |
8717 | { |
8718 | struct kvm_vcpu *target = NULL; | |
8719 | struct kvm_apic_map *map; | |
8720 | ||
4a7132ef WL |
8721 | vcpu->stat.directed_yield_attempted++; |
8722 | ||
72b268a8 WL |
8723 | if (single_task_running()) |
8724 | goto no_yield; | |
8725 | ||
71506297 | 8726 | rcu_read_lock(); |
4a7132ef | 8727 | map = rcu_dereference(vcpu->kvm->arch.apic_map); |
71506297 WL |
8728 | |
8729 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
8730 | target = map->phys_map[dest_id]->vcpu; | |
8731 | ||
8732 | rcu_read_unlock(); | |
8733 | ||
4a7132ef WL |
8734 | if (!target || !READ_ONCE(target->ready)) |
8735 | goto no_yield; | |
8736 | ||
a1fa4cbd WL |
8737 | /* Ignore requests to yield to self */ |
8738 | if (vcpu == target) | |
8739 | goto no_yield; | |
8740 | ||
4a7132ef WL |
8741 | if (kvm_vcpu_yield_to(target) <= 0) |
8742 | goto no_yield; | |
8743 | ||
8744 | vcpu->stat.directed_yield_successful++; | |
8745 | ||
8746 | no_yield: | |
8747 | return; | |
71506297 WL |
8748 | } |
8749 | ||
0dbb1123 AK |
8750 | static int complete_hypercall_exit(struct kvm_vcpu *vcpu) |
8751 | { | |
8752 | u64 ret = vcpu->run->hypercall.ret; | |
8753 | ||
8754 | if (!is_64_bit_mode(vcpu)) | |
8755 | ret = (u32)ret; | |
8756 | kvm_rax_write(vcpu, ret); | |
8757 | ++vcpu->stat.hypercalls; | |
8758 | return kvm_skip_emulated_instruction(vcpu); | |
8759 | } | |
8760 | ||
8776e519 HB |
8761 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
8762 | { | |
8763 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 8764 | int op_64_bit; |
8776e519 | 8765 | |
23200b7a JM |
8766 | if (kvm_xen_hypercall_enabled(vcpu->kvm)) |
8767 | return kvm_xen_hypercall(vcpu); | |
8768 | ||
8f014550 | 8769 | if (kvm_hv_hypercall_enabled(vcpu)) |
696ca779 | 8770 | return kvm_hv_hypercall(vcpu); |
55cd8e5a | 8771 | |
de3cd117 SC |
8772 | nr = kvm_rax_read(vcpu); |
8773 | a0 = kvm_rbx_read(vcpu); | |
8774 | a1 = kvm_rcx_read(vcpu); | |
8775 | a2 = kvm_rdx_read(vcpu); | |
8776 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 8777 | |
229456fc | 8778 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 8779 | |
c04c7501 | 8780 | op_64_bit = is_64_bit_hypercall(vcpu); |
a449c7aa | 8781 | if (!op_64_bit) { |
8776e519 HB |
8782 | nr &= 0xFFFFFFFF; |
8783 | a0 &= 0xFFFFFFFF; | |
8784 | a1 &= 0xFFFFFFFF; | |
8785 | a2 &= 0xFFFFFFFF; | |
8786 | a3 &= 0xFFFFFFFF; | |
8787 | } | |
8788 | ||
b3646477 | 8789 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { |
07708c4a | 8790 | ret = -KVM_EPERM; |
696ca779 | 8791 | goto out; |
07708c4a JK |
8792 | } |
8793 | ||
66570e96 OU |
8794 | ret = -KVM_ENOSYS; |
8795 | ||
8776e519 | 8796 | switch (nr) { |
b93463aa AK |
8797 | case KVM_HC_VAPIC_POLL_IRQ: |
8798 | ret = 0; | |
8799 | break; | |
6aef266c | 8800 | case KVM_HC_KICK_CPU: |
66570e96 OU |
8801 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) |
8802 | break; | |
8803 | ||
6aef266c | 8804 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); |
4a7132ef | 8805 | kvm_sched_yield(vcpu, a1); |
6aef266c SV |
8806 | ret = 0; |
8807 | break; | |
8ef81a9a | 8808 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8809 | case KVM_HC_CLOCK_PAIRING: |
8810 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
8811 | break; | |
1ed199a4 | 8812 | #endif |
4180bf1b | 8813 | case KVM_HC_SEND_IPI: |
66570e96 OU |
8814 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) |
8815 | break; | |
8816 | ||
4180bf1b WL |
8817 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); |
8818 | break; | |
71506297 | 8819 | case KVM_HC_SCHED_YIELD: |
66570e96 OU |
8820 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) |
8821 | break; | |
8822 | ||
4a7132ef | 8823 | kvm_sched_yield(vcpu, a0); |
71506297 WL |
8824 | ret = 0; |
8825 | break; | |
0dbb1123 AK |
8826 | case KVM_HC_MAP_GPA_RANGE: { |
8827 | u64 gpa = a0, npages = a1, attrs = a2; | |
8828 | ||
8829 | ret = -KVM_ENOSYS; | |
8830 | if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) | |
8831 | break; | |
8832 | ||
8833 | if (!PAGE_ALIGNED(gpa) || !npages || | |
8834 | gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { | |
8835 | ret = -KVM_EINVAL; | |
8836 | break; | |
8837 | } | |
8838 | ||
8839 | vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; | |
8840 | vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; | |
8841 | vcpu->run->hypercall.args[0] = gpa; | |
8842 | vcpu->run->hypercall.args[1] = npages; | |
8843 | vcpu->run->hypercall.args[2] = attrs; | |
8844 | vcpu->run->hypercall.longmode = op_64_bit; | |
8845 | vcpu->arch.complete_userspace_io = complete_hypercall_exit; | |
8846 | return 0; | |
8847 | } | |
8776e519 HB |
8848 | default: |
8849 | ret = -KVM_ENOSYS; | |
8850 | break; | |
8851 | } | |
696ca779 | 8852 | out: |
a449c7aa NA |
8853 | if (!op_64_bit) |
8854 | ret = (u32)ret; | |
de3cd117 | 8855 | kvm_rax_write(vcpu, ret); |
6356ee0c | 8856 | |
f11c3a8d | 8857 | ++vcpu->stat.hypercalls; |
6356ee0c | 8858 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
8859 | } |
8860 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
8861 | ||
b6785def | 8862 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 8863 | { |
d6aa1000 | 8864 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 8865 | char instruction[3]; |
5fdbf976 | 8866 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 8867 | |
b3646477 | 8868 | static_call(kvm_x86_patch_hypercall)(vcpu, instruction); |
8776e519 | 8869 | |
ce2e852e DV |
8870 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
8871 | &ctxt->exception); | |
8776e519 HB |
8872 | } |
8873 | ||
851ba692 | 8874 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8875 | { |
782d422b MG |
8876 | return vcpu->run->request_interrupt_window && |
8877 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
8878 | } |
8879 | ||
851ba692 | 8880 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8881 | { |
851ba692 AK |
8882 | struct kvm_run *kvm_run = vcpu->run; |
8883 | ||
82d6dbe9 | 8884 | kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu); |
2d3ad1f4 | 8885 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 8886 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
f3d1436d DW |
8887 | |
8888 | /* | |
8889 | * The call to kvm_ready_for_interrupt_injection() may end up in | |
8890 | * kvm_xen_has_interrupt() which may require the srcu lock to be | |
8891 | * held, to protect against changes in the vcpu_info address. | |
8892 | */ | |
8893 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
127a457a MG |
8894 | kvm_run->ready_for_interrupt_injection = |
8895 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 8896 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
f3d1436d | 8897 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
15aad3be CQ |
8898 | |
8899 | if (is_smm(vcpu)) | |
8900 | kvm_run->flags |= KVM_RUN_X86_SMM; | |
b6c7a5dc HB |
8901 | } |
8902 | ||
95ba8273 GN |
8903 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
8904 | { | |
8905 | int max_irr, tpr; | |
8906 | ||
afaf0b2f | 8907 | if (!kvm_x86_ops.update_cr8_intercept) |
95ba8273 GN |
8908 | return; |
8909 | ||
bce87cce | 8910 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
8911 | return; |
8912 | ||
d62caabb AS |
8913 | if (vcpu->arch.apicv_active) |
8914 | return; | |
8915 | ||
8db3baa2 GN |
8916 | if (!vcpu->arch.apic->vapic_addr) |
8917 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
8918 | else | |
8919 | max_irr = -1; | |
95ba8273 GN |
8920 | |
8921 | if (max_irr != -1) | |
8922 | max_irr >>= 4; | |
8923 | ||
8924 | tpr = kvm_lapic_get_cr8(vcpu); | |
8925 | ||
b3646477 | 8926 | static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); |
95ba8273 GN |
8927 | } |
8928 | ||
b97f0745 | 8929 | |
cb6a32c2 SC |
8930 | int kvm_check_nested_events(struct kvm_vcpu *vcpu) |
8931 | { | |
cb6a32c2 SC |
8932 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
8933 | kvm_x86_ops.nested_ops->triple_fault(vcpu); | |
8934 | return 1; | |
8935 | } | |
8936 | ||
8937 | return kvm_x86_ops.nested_ops->check_events(vcpu); | |
8938 | } | |
8939 | ||
b97f0745 ML |
8940 | static void kvm_inject_exception(struct kvm_vcpu *vcpu) |
8941 | { | |
8942 | if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) | |
8943 | vcpu->arch.exception.error_code = false; | |
8944 | static_call(kvm_x86_queue_exception)(vcpu); | |
8945 | } | |
8946 | ||
a5f6909a | 8947 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) |
95ba8273 | 8948 | { |
b6b8a145 | 8949 | int r; |
c6b22f59 | 8950 | bool can_inject = true; |
b6b8a145 | 8951 | |
95ba8273 | 8952 | /* try to reinject previous events if any */ |
664f8e26 | 8953 | |
c6b22f59 | 8954 | if (vcpu->arch.exception.injected) { |
b97f0745 | 8955 | kvm_inject_exception(vcpu); |
c6b22f59 PB |
8956 | can_inject = false; |
8957 | } | |
664f8e26 | 8958 | /* |
a042c26f LA |
8959 | * Do not inject an NMI or interrupt if there is a pending |
8960 | * exception. Exceptions and interrupts are recognized at | |
8961 | * instruction boundaries, i.e. the start of an instruction. | |
8962 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
8963 | * NMIs and interrupts, i.e. traps are recognized before an | |
8964 | * NMI/interrupt that's pending on the same instruction. | |
8965 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
8966 | * priority, but are only generated (pended) during instruction | |
8967 | * execution, i.e. a pending fault-like exception means the | |
8968 | * fault occurred on the *previous* instruction and must be | |
8969 | * serviced prior to recognizing any new events in order to | |
8970 | * fully complete the previous instruction. | |
664f8e26 | 8971 | */ |
1a680e35 | 8972 | else if (!vcpu->arch.exception.pending) { |
c6b22f59 | 8973 | if (vcpu->arch.nmi_injected) { |
b3646477 | 8974 | static_call(kvm_x86_set_nmi)(vcpu); |
c6b22f59 PB |
8975 | can_inject = false; |
8976 | } else if (vcpu->arch.interrupt.injected) { | |
b3646477 | 8977 | static_call(kvm_x86_set_irq)(vcpu); |
c6b22f59 PB |
8978 | can_inject = false; |
8979 | } | |
664f8e26 WL |
8980 | } |
8981 | ||
3b82b8d7 SC |
8982 | WARN_ON_ONCE(vcpu->arch.exception.injected && |
8983 | vcpu->arch.exception.pending); | |
8984 | ||
1a680e35 LA |
8985 | /* |
8986 | * Call check_nested_events() even if we reinjected a previous event | |
8987 | * in order for caller to determine if it should require immediate-exit | |
8988 | * from L2 to L1 due to pending L1 events which require exit | |
8989 | * from L2 to L1. | |
8990 | */ | |
56083bdf | 8991 | if (is_guest_mode(vcpu)) { |
cb6a32c2 | 8992 | r = kvm_check_nested_events(vcpu); |
c9d40913 | 8993 | if (r < 0) |
a5f6909a | 8994 | goto out; |
664f8e26 WL |
8995 | } |
8996 | ||
8997 | /* try to inject new event if pending */ | |
b59bb7bd | 8998 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
8999 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
9000 | vcpu->arch.exception.has_error_code, | |
9001 | vcpu->arch.exception.error_code); | |
d6e8c854 | 9002 | |
664f8e26 WL |
9003 | vcpu->arch.exception.pending = false; |
9004 | vcpu->arch.exception.injected = true; | |
9005 | ||
d6e8c854 NA |
9006 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
9007 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
9008 | X86_EFLAGS_RF); | |
9009 | ||
f10c729f | 9010 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
f10c729f JM |
9011 | kvm_deliver_exception_payload(vcpu); |
9012 | if (vcpu->arch.dr7 & DR7_GD) { | |
9013 | vcpu->arch.dr7 &= ~DR7_GD; | |
9014 | kvm_update_dr7(vcpu); | |
9015 | } | |
6bdf0662 NA |
9016 | } |
9017 | ||
b97f0745 | 9018 | kvm_inject_exception(vcpu); |
c6b22f59 | 9019 | can_inject = false; |
1a680e35 LA |
9020 | } |
9021 | ||
61e5f69e ML |
9022 | /* Don't inject interrupts if the user asked to avoid doing so */ |
9023 | if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) | |
9024 | return 0; | |
9025 | ||
c9d40913 PB |
9026 | /* |
9027 | * Finally, inject interrupt events. If an event cannot be injected | |
9028 | * due to architectural conditions (e.g. IF=0) a window-open exit | |
9029 | * will re-request KVM_REQ_EVENT. Sometimes however an event is pending | |
9030 | * and can architecturally be injected, but we cannot do it right now: | |
9031 | * an interrupt could have arrived just now and we have to inject it | |
9032 | * as a vmexit, or there could already an event in the queue, which is | |
9033 | * indicated by can_inject. In that case we request an immediate exit | |
9034 | * in order to make progress and get back here for another iteration. | |
9035 | * The kvm_x86_ops hooks communicate this by returning -EBUSY. | |
9036 | */ | |
9037 | if (vcpu->arch.smi_pending) { | |
b3646477 | 9038 | r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 9039 | if (r < 0) |
a5f6909a | 9040 | goto out; |
c9d40913 PB |
9041 | if (r) { |
9042 | vcpu->arch.smi_pending = false; | |
9043 | ++vcpu->arch.smi_count; | |
9044 | enter_smm(vcpu); | |
9045 | can_inject = false; | |
9046 | } else | |
b3646477 | 9047 | static_call(kvm_x86_enable_smi_window)(vcpu); |
c9d40913 PB |
9048 | } |
9049 | ||
9050 | if (vcpu->arch.nmi_pending) { | |
b3646477 | 9051 | r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 9052 | if (r < 0) |
a5f6909a | 9053 | goto out; |
c9d40913 PB |
9054 | if (r) { |
9055 | --vcpu->arch.nmi_pending; | |
9056 | vcpu->arch.nmi_injected = true; | |
b3646477 | 9057 | static_call(kvm_x86_set_nmi)(vcpu); |
c9d40913 | 9058 | can_inject = false; |
b3646477 | 9059 | WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); |
c9d40913 PB |
9060 | } |
9061 | if (vcpu->arch.nmi_pending) | |
b3646477 | 9062 | static_call(kvm_x86_enable_nmi_window)(vcpu); |
c9d40913 | 9063 | } |
1a680e35 | 9064 | |
c9d40913 | 9065 | if (kvm_cpu_has_injectable_intr(vcpu)) { |
b3646477 | 9066 | r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 9067 | if (r < 0) |
a5f6909a | 9068 | goto out; |
c9d40913 PB |
9069 | if (r) { |
9070 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); | |
b3646477 JB |
9071 | static_call(kvm_x86_set_irq)(vcpu); |
9072 | WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); | |
c9d40913 PB |
9073 | } |
9074 | if (kvm_cpu_has_injectable_intr(vcpu)) | |
b3646477 | 9075 | static_call(kvm_x86_enable_irq_window)(vcpu); |
95ba8273 | 9076 | } |
ee2cd4b7 | 9077 | |
c9d40913 PB |
9078 | if (is_guest_mode(vcpu) && |
9079 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
9080 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
9081 | *req_immediate_exit = true; | |
9082 | ||
9083 | WARN_ON(vcpu->arch.exception.pending); | |
a5f6909a | 9084 | return 0; |
c9d40913 | 9085 | |
a5f6909a JM |
9086 | out: |
9087 | if (r == -EBUSY) { | |
9088 | *req_immediate_exit = true; | |
9089 | r = 0; | |
9090 | } | |
9091 | return r; | |
95ba8273 GN |
9092 | } |
9093 | ||
7460fb4a AK |
9094 | static void process_nmi(struct kvm_vcpu *vcpu) |
9095 | { | |
9096 | unsigned limit = 2; | |
9097 | ||
9098 | /* | |
9099 | * x86 is limited to one NMI running, and one NMI pending after it. | |
9100 | * If an NMI is already in progress, limit further NMIs to just one. | |
9101 | * Otherwise, allow two (and we'll inject the first one immediately). | |
9102 | */ | |
b3646477 | 9103 | if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) |
7460fb4a AK |
9104 | limit = 1; |
9105 | ||
9106 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
9107 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
9108 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9109 | } | |
9110 | ||
ee2cd4b7 | 9111 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
9112 | { |
9113 | u32 flags = 0; | |
9114 | flags |= seg->g << 23; | |
9115 | flags |= seg->db << 22; | |
9116 | flags |= seg->l << 21; | |
9117 | flags |= seg->avl << 20; | |
9118 | flags |= seg->present << 15; | |
9119 | flags |= seg->dpl << 13; | |
9120 | flags |= seg->s << 12; | |
9121 | flags |= seg->type << 8; | |
9122 | return flags; | |
9123 | } | |
9124 | ||
ee2cd4b7 | 9125 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
9126 | { |
9127 | struct kvm_segment seg; | |
9128 | int offset; | |
9129 | ||
9130 | kvm_get_segment(vcpu, &seg, n); | |
9131 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
9132 | ||
9133 | if (n < 3) | |
9134 | offset = 0x7f84 + n * 12; | |
9135 | else | |
9136 | offset = 0x7f2c + (n - 3) * 12; | |
9137 | ||
9138 | put_smstate(u32, buf, offset + 8, seg.base); | |
9139 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 9140 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
9141 | } |
9142 | ||
efbb288a | 9143 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 9144 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
9145 | { |
9146 | struct kvm_segment seg; | |
9147 | int offset; | |
9148 | u16 flags; | |
9149 | ||
9150 | kvm_get_segment(vcpu, &seg, n); | |
9151 | offset = 0x7e00 + n * 16; | |
9152 | ||
ee2cd4b7 | 9153 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
9154 | put_smstate(u16, buf, offset, seg.selector); |
9155 | put_smstate(u16, buf, offset + 2, flags); | |
9156 | put_smstate(u32, buf, offset + 4, seg.limit); | |
9157 | put_smstate(u64, buf, offset + 8, seg.base); | |
9158 | } | |
efbb288a | 9159 | #endif |
660a5d51 | 9160 | |
ee2cd4b7 | 9161 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
9162 | { |
9163 | struct desc_ptr dt; | |
9164 | struct kvm_segment seg; | |
9165 | unsigned long val; | |
9166 | int i; | |
9167 | ||
9168 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
9169 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
9170 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
9171 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
9172 | ||
9173 | for (i = 0; i < 8; i++) | |
27b4a9c4 | 9174 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); |
660a5d51 PB |
9175 | |
9176 | kvm_get_dr(vcpu, 6, &val); | |
9177 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
9178 | kvm_get_dr(vcpu, 7, &val); | |
9179 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
9180 | ||
9181 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
9182 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
9183 | put_smstate(u32, buf, 0x7f64, seg.base); | |
9184 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 9185 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
9186 | |
9187 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
9188 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
9189 | put_smstate(u32, buf, 0x7f80, seg.base); | |
9190 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 9191 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 | 9192 | |
b3646477 | 9193 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
660a5d51 PB |
9194 | put_smstate(u32, buf, 0x7f74, dt.address); |
9195 | put_smstate(u32, buf, 0x7f70, dt.size); | |
9196 | ||
b3646477 | 9197 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
660a5d51 PB |
9198 | put_smstate(u32, buf, 0x7f58, dt.address); |
9199 | put_smstate(u32, buf, 0x7f54, dt.size); | |
9200 | ||
9201 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 9202 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
9203 | |
9204 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
9205 | ||
9206 | /* revision id */ | |
9207 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
9208 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
9209 | } | |
9210 | ||
b68f3cc7 | 9211 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 9212 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 9213 | { |
660a5d51 PB |
9214 | struct desc_ptr dt; |
9215 | struct kvm_segment seg; | |
9216 | unsigned long val; | |
9217 | int i; | |
9218 | ||
9219 | for (i = 0; i < 16; i++) | |
27b4a9c4 | 9220 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); |
660a5d51 PB |
9221 | |
9222 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
9223 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
9224 | ||
9225 | kvm_get_dr(vcpu, 6, &val); | |
9226 | put_smstate(u64, buf, 0x7f68, val); | |
9227 | kvm_get_dr(vcpu, 7, &val); | |
9228 | put_smstate(u64, buf, 0x7f60, val); | |
9229 | ||
9230 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
9231 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
9232 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
9233 | ||
9234 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
9235 | ||
9236 | /* revision id */ | |
9237 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
9238 | ||
9239 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
9240 | ||
9241 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
9242 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 9243 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
9244 | put_smstate(u32, buf, 0x7e94, seg.limit); |
9245 | put_smstate(u64, buf, 0x7e98, seg.base); | |
9246 | ||
b3646477 | 9247 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
660a5d51 PB |
9248 | put_smstate(u32, buf, 0x7e84, dt.size); |
9249 | put_smstate(u64, buf, 0x7e88, dt.address); | |
9250 | ||
9251 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
9252 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 9253 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
9254 | put_smstate(u32, buf, 0x7e74, seg.limit); |
9255 | put_smstate(u64, buf, 0x7e78, seg.base); | |
9256 | ||
b3646477 | 9257 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
660a5d51 PB |
9258 | put_smstate(u32, buf, 0x7e64, dt.size); |
9259 | put_smstate(u64, buf, 0x7e68, dt.address); | |
9260 | ||
9261 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 9262 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 9263 | } |
b68f3cc7 | 9264 | #endif |
660a5d51 | 9265 | |
ee2cd4b7 | 9266 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 9267 | { |
660a5d51 | 9268 | struct kvm_segment cs, ds; |
18c3626e | 9269 | struct desc_ptr dt; |
dbc4739b | 9270 | unsigned long cr0; |
660a5d51 | 9271 | char buf[512]; |
660a5d51 | 9272 | |
660a5d51 | 9273 | memset(buf, 0, 512); |
b68f3cc7 | 9274 | #ifdef CONFIG_X86_64 |
d6321d49 | 9275 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 9276 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 9277 | else |
b68f3cc7 | 9278 | #endif |
ee2cd4b7 | 9279 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 9280 | |
0234bf88 | 9281 | /* |
ecc513e5 SC |
9282 | * Give enter_smm() a chance to make ISA-specific changes to the vCPU |
9283 | * state (e.g. leave guest mode) after we've saved the state into the | |
9284 | * SMM state-save area. | |
0234bf88 | 9285 | */ |
ecc513e5 | 9286 | static_call(kvm_x86_enter_smm)(vcpu, buf); |
0234bf88 | 9287 | |
dc87275f | 9288 | kvm_smm_changed(vcpu, true); |
54bf36aa | 9289 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 | 9290 | |
b3646477 | 9291 | if (static_call(kvm_x86_get_nmi_mask)(vcpu)) |
660a5d51 PB |
9292 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; |
9293 | else | |
b3646477 | 9294 | static_call(kvm_x86_set_nmi_mask)(vcpu, true); |
660a5d51 PB |
9295 | |
9296 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
9297 | kvm_rip_write(vcpu, 0x8000); | |
9298 | ||
9299 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
b3646477 | 9300 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
660a5d51 PB |
9301 | vcpu->arch.cr0 = cr0; |
9302 | ||
b3646477 | 9303 | static_call(kvm_x86_set_cr4)(vcpu, 0); |
660a5d51 | 9304 | |
18c3626e PB |
9305 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
9306 | dt.address = dt.size = 0; | |
b3646477 | 9307 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
18c3626e | 9308 | |
996ff542 | 9309 | kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
660a5d51 PB |
9310 | |
9311 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
9312 | cs.base = vcpu->arch.smbase; | |
9313 | ||
9314 | ds.selector = 0; | |
9315 | ds.base = 0; | |
9316 | ||
9317 | cs.limit = ds.limit = 0xffffffff; | |
9318 | cs.type = ds.type = 0x3; | |
9319 | cs.dpl = ds.dpl = 0; | |
9320 | cs.db = ds.db = 0; | |
9321 | cs.s = ds.s = 1; | |
9322 | cs.l = ds.l = 0; | |
9323 | cs.g = ds.g = 1; | |
9324 | cs.avl = ds.avl = 0; | |
9325 | cs.present = ds.present = 1; | |
9326 | cs.unusable = ds.unusable = 0; | |
9327 | cs.padding = ds.padding = 0; | |
9328 | ||
9329 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
9330 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
9331 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
9332 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
9333 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
9334 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
9335 | ||
b68f3cc7 | 9336 | #ifdef CONFIG_X86_64 |
d6321d49 | 9337 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
b3646477 | 9338 | static_call(kvm_x86_set_efer)(vcpu, 0); |
b68f3cc7 | 9339 | #endif |
660a5d51 | 9340 | |
aedbaf4f | 9341 | kvm_update_cpuid_runtime(vcpu); |
660a5d51 | 9342 | kvm_mmu_reset_context(vcpu); |
64d60670 PB |
9343 | } |
9344 | ||
ee2cd4b7 | 9345 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
9346 | { |
9347 | vcpu->arch.smi_pending = true; | |
9348 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9349 | } | |
9350 | ||
7ee30bc1 NNL |
9351 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
9352 | unsigned long *vcpu_bitmap) | |
9353 | { | |
9354 | cpumask_var_t cpus; | |
7ee30bc1 NNL |
9355 | |
9356 | zalloc_cpumask_var(&cpus, GFP_ATOMIC); | |
9357 | ||
db5a95ec | 9358 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, |
54163a34 | 9359 | NULL, vcpu_bitmap, cpus); |
7ee30bc1 NNL |
9360 | |
9361 | free_cpumask_var(cpus); | |
9362 | } | |
9363 | ||
2860c4b1 PB |
9364 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
9365 | { | |
9366 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
9367 | } | |
9368 | ||
8df14af4 SS |
9369 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
9370 | { | |
06ef8134 ML |
9371 | bool activate; |
9372 | ||
8df14af4 SS |
9373 | if (!lapic_in_kernel(vcpu)) |
9374 | return; | |
9375 | ||
b0a1637f ML |
9376 | mutex_lock(&vcpu->kvm->arch.apicv_update_lock); |
9377 | ||
06ef8134 ML |
9378 | activate = kvm_apicv_activated(vcpu->kvm); |
9379 | if (vcpu->arch.apicv_active == activate) | |
9380 | goto out; | |
9381 | ||
9382 | vcpu->arch.apicv_active = activate; | |
8df14af4 | 9383 | kvm_apic_update_apicv(vcpu); |
b3646477 | 9384 | static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); |
bca66dbc VK |
9385 | |
9386 | /* | |
9387 | * When APICv gets disabled, we may still have injected interrupts | |
9388 | * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was | |
9389 | * still active when the interrupt got accepted. Make sure | |
9390 | * inject_pending_event() is called to check for that. | |
9391 | */ | |
9392 | if (!vcpu->arch.apicv_active) | |
9393 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b0a1637f | 9394 | |
06ef8134 | 9395 | out: |
b0a1637f | 9396 | mutex_unlock(&vcpu->kvm->arch.apicv_update_lock); |
8df14af4 SS |
9397 | } |
9398 | EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); | |
9399 | ||
b0a1637f | 9400 | void __kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) |
8df14af4 | 9401 | { |
b0a1637f | 9402 | unsigned long old, new; |
8e205a6b | 9403 | |
afaf0b2f | 9404 | if (!kvm_x86_ops.check_apicv_inhibit_reasons || |
b3646477 | 9405 | !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) |
ef8efd7a SS |
9406 | return; |
9407 | ||
b0a1637f ML |
9408 | old = new = kvm->arch.apicv_inhibit_reasons; |
9409 | ||
9410 | if (activate) | |
9411 | __clear_bit(bit, &new); | |
9412 | else | |
9413 | __set_bit(bit, &new); | |
8e205a6b | 9414 | |
36222b11 ML |
9415 | if (!!old != !!new) { |
9416 | trace_kvm_apicv_update_request(activate, bit); | |
9417 | kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); | |
b0a1637f | 9418 | kvm->arch.apicv_inhibit_reasons = new; |
36222b11 ML |
9419 | if (new) { |
9420 | unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); | |
36222b11 ML |
9421 | kvm_zap_gfn_range(kvm, gfn, gfn+1); |
9422 | } | |
b0a1637f ML |
9423 | } else |
9424 | kvm->arch.apicv_inhibit_reasons = new; | |
9425 | } | |
9426 | EXPORT_SYMBOL_GPL(__kvm_request_apicv_update); | |
7d611233 | 9427 | |
b0a1637f ML |
9428 | void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) |
9429 | { | |
9430 | mutex_lock(&kvm->arch.apicv_update_lock); | |
9431 | __kvm_request_apicv_update(kvm, activate, bit); | |
9432 | mutex_unlock(&kvm->arch.apicv_update_lock); | |
8df14af4 SS |
9433 | } |
9434 | EXPORT_SYMBOL_GPL(kvm_request_apicv_update); | |
9435 | ||
3d81bc7e | 9436 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 9437 | { |
dcbd3e49 | 9438 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 9439 | return; |
c7c9c56c | 9440 | |
6308630b | 9441 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 9442 | |
b053b2ae | 9443 | if (irqchip_split(vcpu->kvm)) |
6308630b | 9444 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 9445 | else { |
6a849d3d | 9446 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); |
e97f852f WL |
9447 | if (ioapic_in_kernel(vcpu->kvm)) |
9448 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 9449 | } |
e40ff1d6 LA |
9450 | |
9451 | if (is_guest_mode(vcpu)) | |
9452 | vcpu->arch.load_eoi_exitmap_pending = true; | |
9453 | else | |
9454 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
9455 | } | |
9456 | ||
9457 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
9458 | { | |
9459 | u64 eoi_exit_bitmap[4]; | |
9460 | ||
9461 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
9462 | return; | |
9463 | ||
e1a4b3b3 | 9464 | if (to_hv_vcpu(vcpu)) { |
f2bc14b6 VK |
9465 | bitmap_or((ulong *)eoi_exit_bitmap, |
9466 | vcpu->arch.ioapic_handled_vectors, | |
9467 | to_hv_synic(vcpu)->vec_bitmap, 256); | |
e1a4b3b3 | 9468 | static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); |
9469 | return; | |
9470 | } | |
f2bc14b6 | 9471 | |
e1a4b3b3 | 9472 | static_call(kvm_x86_load_eoi_exitmap)( |
9473 | vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors); | |
c7c9c56c YZ |
9474 | } |
9475 | ||
e649b3f0 ET |
9476 | void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
9477 | unsigned long start, unsigned long end) | |
b1394e74 RK |
9478 | { |
9479 | unsigned long apic_address; | |
9480 | ||
9481 | /* | |
9482 | * The physical address of apic access page is stored in the VMCS. | |
9483 | * Update it when it becomes invalid. | |
9484 | */ | |
9485 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
9486 | if (start <= apic_address && apic_address < end) | |
9487 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
9488 | } | |
9489 | ||
4256f43f TC |
9490 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
9491 | { | |
35754c98 | 9492 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
9493 | return; |
9494 | ||
afaf0b2f | 9495 | if (!kvm_x86_ops.set_apic_access_page_addr) |
4256f43f TC |
9496 | return; |
9497 | ||
b3646477 | 9498 | static_call(kvm_x86_set_apic_access_page_addr)(vcpu); |
4256f43f | 9499 | } |
4256f43f | 9500 | |
d264ee0c SC |
9501 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
9502 | { | |
9503 | smp_send_reschedule(vcpu->cpu); | |
9504 | } | |
9505 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
9506 | ||
9357d939 | 9507 | /* |
362c698f | 9508 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
9509 | * exiting to the userspace. Otherwise, the value will be returned to the |
9510 | * userspace. | |
9511 | */ | |
851ba692 | 9512 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
9513 | { |
9514 | int r; | |
62a193ed MG |
9515 | bool req_int_win = |
9516 | dm_request_for_irq_injection(vcpu) && | |
9517 | kvm_cpu_accept_dm_intr(vcpu); | |
404d5d7b | 9518 | fastpath_t exit_fastpath; |
62a193ed | 9519 | |
730dca42 | 9520 | bool req_immediate_exit = false; |
b6c7a5dc | 9521 | |
fb04a1ed PX |
9522 | /* Forbid vmenter if vcpu dirty ring is soft-full */ |
9523 | if (unlikely(vcpu->kvm->dirty_ring_size && | |
9524 | kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { | |
9525 | vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; | |
9526 | trace_kvm_dirty_ring_exit(vcpu); | |
9527 | r = 0; | |
9528 | goto out; | |
9529 | } | |
9530 | ||
2fa6e1e1 | 9531 | if (kvm_request_pending(vcpu)) { |
67369273 SC |
9532 | if (kvm_check_request(KVM_REQ_VM_BUGGED, vcpu)) { |
9533 | r = -EIO; | |
9534 | goto out; | |
9535 | } | |
729c15c2 | 9536 | if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { |
9a78e158 | 9537 | if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { |
671ddc70 JM |
9538 | r = 0; |
9539 | goto out; | |
9540 | } | |
9541 | } | |
a8eeb04a | 9542 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 9543 | kvm_mmu_unload(vcpu); |
a8eeb04a | 9544 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 9545 | __kvm_migrate_timers(vcpu); |
d828199e MT |
9546 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
9547 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
9548 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
9549 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
9550 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
9551 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
9552 | if (unlikely(r)) |
9553 | goto out; | |
9554 | } | |
a8eeb04a | 9555 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 9556 | kvm_mmu_sync_roots(vcpu); |
727a7e27 PB |
9557 | if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) |
9558 | kvm_mmu_load_pgd(vcpu); | |
eeeb4f67 | 9559 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { |
7780938c | 9560 | kvm_vcpu_flush_tlb_all(vcpu); |
eeeb4f67 SC |
9561 | |
9562 | /* Flushing all ASIDs flushes the current ASID... */ | |
9563 | kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
9564 | } | |
8eb2fc7c | 9565 | kvm_service_local_tlb_flush_requests(vcpu); |
eeeb4f67 | 9566 | |
a8eeb04a | 9567 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 9568 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
9569 | r = 0; |
9570 | goto out; | |
9571 | } | |
a8eeb04a | 9572 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
cb6a32c2 SC |
9573 | if (is_guest_mode(vcpu)) { |
9574 | kvm_x86_ops.nested_ops->triple_fault(vcpu); | |
9575 | } else { | |
9576 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; | |
9577 | vcpu->mmio_needed = 0; | |
9578 | r = 0; | |
9579 | goto out; | |
9580 | } | |
71c4dfaf | 9581 | } |
af585b92 GN |
9582 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
9583 | /* Page is swapped out. Do synthetic halt */ | |
9584 | vcpu->arch.apf.halted = true; | |
9585 | r = 1; | |
9586 | goto out; | |
9587 | } | |
c9aaa895 GC |
9588 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
9589 | record_steal_time(vcpu); | |
64d60670 PB |
9590 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
9591 | process_smi(vcpu); | |
7460fb4a AK |
9592 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
9593 | process_nmi(vcpu); | |
f5132b01 | 9594 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 9595 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 9596 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 9597 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
9598 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
9599 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
9600 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 9601 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
9602 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
9603 | vcpu->run->eoi.vector = | |
9604 | vcpu->arch.pending_ioapic_eoi; | |
9605 | r = 0; | |
9606 | goto out; | |
9607 | } | |
9608 | } | |
3d81bc7e YZ |
9609 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
9610 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
9611 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
9612 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
9613 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
9614 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
9615 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
9616 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
9617 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
9618 | r = 0; | |
9619 | goto out; | |
9620 | } | |
e516cebb AS |
9621 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
9622 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
9623 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
9624 | r = 0; | |
9625 | goto out; | |
9626 | } | |
db397571 | 9627 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
9ff5e030 VK |
9628 | struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); |
9629 | ||
db397571 | 9630 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; |
9ff5e030 | 9631 | vcpu->run->hyperv = hv_vcpu->exit; |
db397571 AS |
9632 | r = 0; |
9633 | goto out; | |
9634 | } | |
f3b138c5 AS |
9635 | |
9636 | /* | |
9637 | * KVM_REQ_HV_STIMER has to be processed after | |
9638 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
9639 | * depend on the guest clock being up-to-date | |
9640 | */ | |
1f4b34f8 AS |
9641 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
9642 | kvm_hv_process_stimers(vcpu); | |
8df14af4 SS |
9643 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
9644 | kvm_vcpu_update_apicv(vcpu); | |
557a961a VK |
9645 | if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) |
9646 | kvm_check_async_pf_completion(vcpu); | |
1a155254 | 9647 | if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) |
b3646477 | 9648 | static_call(kvm_x86_msr_filter_changed)(vcpu); |
a85863c2 MS |
9649 | |
9650 | if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) | |
9651 | static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); | |
2f52d58c | 9652 | } |
b93463aa | 9653 | |
40da8ccd DW |
9654 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || |
9655 | kvm_xen_has_interrupt(vcpu)) { | |
0f1e261e | 9656 | ++vcpu->stat.req_event; |
4fe09bcf JM |
9657 | r = kvm_apic_accept_events(vcpu); |
9658 | if (r < 0) { | |
9659 | r = 0; | |
9660 | goto out; | |
9661 | } | |
66450a21 JK |
9662 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
9663 | r = 1; | |
9664 | goto out; | |
9665 | } | |
9666 | ||
a5f6909a JM |
9667 | r = inject_pending_event(vcpu, &req_immediate_exit); |
9668 | if (r < 0) { | |
9669 | r = 0; | |
9670 | goto out; | |
9671 | } | |
c9d40913 | 9672 | if (req_int_win) |
b3646477 | 9673 | static_call(kvm_x86_enable_irq_window)(vcpu); |
b463a6f7 AK |
9674 | |
9675 | if (kvm_lapic_enabled(vcpu)) { | |
9676 | update_cr8_intercept(vcpu); | |
9677 | kvm_lapic_sync_to_vapic(vcpu); | |
9678 | } | |
9679 | } | |
9680 | ||
d8368af8 AK |
9681 | r = kvm_mmu_reload(vcpu); |
9682 | if (unlikely(r)) { | |
d905c069 | 9683 | goto cancel_injection; |
d8368af8 AK |
9684 | } |
9685 | ||
b6c7a5dc HB |
9686 | preempt_disable(); |
9687 | ||
b3646477 | 9688 | static_call(kvm_x86_prepare_guest_switch)(vcpu); |
b95234c8 PB |
9689 | |
9690 | /* | |
9691 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
9692 | * IPI are then delayed after guest entry, which ensures that they | |
9693 | * result in virtual interrupt delivery. | |
9694 | */ | |
9695 | local_irq_disable(); | |
6b7e2d09 XG |
9696 | vcpu->mode = IN_GUEST_MODE; |
9697 | ||
01b71917 MT |
9698 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
9699 | ||
0f127d12 | 9700 | /* |
b95234c8 | 9701 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 9702 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 9703 | * |
81b01667 | 9704 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
9705 | * pairs with the memory barrier implicit in pi_test_and_set_on |
9706 | * (see vmx_deliver_posted_interrupt). | |
9707 | * | |
9708 | * 3) This also orders the write to mode from any reads to the page | |
9709 | * tables done while the VCPU is running. Please see the comment | |
9710 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 9711 | */ |
01b71917 | 9712 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 9713 | |
b95234c8 PB |
9714 | /* |
9715 | * This handles the case where a posted interrupt was | |
6a849d3d PB |
9716 | * notified with kvm_vcpu_kick. Assigned devices can |
9717 | * use the POSTED_INTR_VECTOR even if APICv is disabled, | |
9718 | * so do it even if APICv is disabled on this vCPU. | |
b95234c8 | 9719 | */ |
6a849d3d PB |
9720 | if (kvm_lapic_enabled(vcpu)) |
9721 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); | |
32f88400 | 9722 | |
5a9f5443 | 9723 | if (kvm_vcpu_exit_request(vcpu)) { |
6b7e2d09 | 9724 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9725 | smp_wmb(); |
6c142801 AK |
9726 | local_irq_enable(); |
9727 | preempt_enable(); | |
01b71917 | 9728 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 9729 | r = 1; |
d905c069 | 9730 | goto cancel_injection; |
6c142801 AK |
9731 | } |
9732 | ||
c43203ca PB |
9733 | if (req_immediate_exit) { |
9734 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 9735 | static_call(kvm_x86_request_immediate_exit)(vcpu); |
c43203ca | 9736 | } |
d6185f20 | 9737 | |
2620fe26 SC |
9738 | fpregs_assert_state_consistent(); |
9739 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9740 | switch_fpu_return(); | |
5f409e20 | 9741 | |
42dbaa5a | 9742 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
9743 | set_debugreg(0, 7); |
9744 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
9745 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
9746 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
9747 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
f85d4016 LJ |
9748 | } else if (unlikely(hw_breakpoint_active())) { |
9749 | set_debugreg(0, 7); | |
42dbaa5a | 9750 | } |
b6c7a5dc | 9751 | |
d89d04ab PB |
9752 | for (;;) { |
9753 | exit_fastpath = static_call(kvm_x86_run)(vcpu); | |
9754 | if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) | |
9755 | break; | |
9756 | ||
6a849d3d PB |
9757 | if (kvm_lapic_enabled(vcpu)) |
9758 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); | |
de7cd3f6 PB |
9759 | |
9760 | if (unlikely(kvm_vcpu_exit_request(vcpu))) { | |
d89d04ab PB |
9761 | exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; |
9762 | break; | |
9763 | } | |
de7cd3f6 | 9764 | } |
b6c7a5dc | 9765 | |
c77fb5fe PB |
9766 | /* |
9767 | * Do this here before restoring debug registers on the host. And | |
9768 | * since we do this before handling the vmexit, a DR access vmexit | |
9769 | * can (a) read the correct value of the debug registers, (b) set | |
9770 | * KVM_DEBUGREG_WONT_EXIT again. | |
9771 | */ | |
9772 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe | 9773 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
b3646477 | 9774 | static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); |
70e4da7a | 9775 | kvm_update_dr0123(vcpu); |
70e4da7a | 9776 | kvm_update_dr7(vcpu); |
c77fb5fe PB |
9777 | } |
9778 | ||
24f1e32c FW |
9779 | /* |
9780 | * If the guest has used debug registers, at least dr7 | |
9781 | * will be disabled while returning to the host. | |
9782 | * If we don't have active breakpoints in the host, we don't | |
9783 | * care about the messed up debug address registers. But if | |
9784 | * we have some of them active, restore the old state. | |
9785 | */ | |
59d8eb53 | 9786 | if (hw_breakpoint_active()) |
24f1e32c | 9787 | hw_breakpoint_restore(); |
42dbaa5a | 9788 | |
c967118d | 9789 | vcpu->arch.last_vmentry_cpu = vcpu->cpu; |
4ba76538 | 9790 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 9791 | |
6b7e2d09 | 9792 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9793 | smp_wmb(); |
a547c6db | 9794 | |
b3646477 | 9795 | static_call(kvm_x86_handle_exit_irqoff)(vcpu); |
b6c7a5dc | 9796 | |
d7a08882 SC |
9797 | /* |
9798 | * Consume any pending interrupts, including the possible source of | |
9799 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
9800 | * An instruction is required after local_irq_enable() to fully unblock | |
9801 | * interrupts on processors that implement an interrupt shadow, the | |
9802 | * stat.exits increment will do nicely. | |
9803 | */ | |
9804 | kvm_before_interrupt(vcpu); | |
9805 | local_irq_enable(); | |
b6c7a5dc | 9806 | ++vcpu->stat.exits; |
d7a08882 SC |
9807 | local_irq_disable(); |
9808 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 9809 | |
16045714 WL |
9810 | /* |
9811 | * Wait until after servicing IRQs to account guest time so that any | |
9812 | * ticks that occurred while running the guest are properly accounted | |
9813 | * to the guest. Waiting until IRQs are enabled degrades the accuracy | |
9814 | * of accounting via context tracking, but the loss of accuracy is | |
9815 | * acceptable for all known use cases. | |
9816 | */ | |
9817 | vtime_account_guest_exit(); | |
9818 | ||
ec0671d5 WL |
9819 | if (lapic_in_kernel(vcpu)) { |
9820 | s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; | |
9821 | if (delta != S64_MIN) { | |
9822 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); | |
9823 | vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; | |
9824 | } | |
9825 | } | |
b6c7a5dc | 9826 | |
f2485b3e | 9827 | local_irq_enable(); |
b6c7a5dc HB |
9828 | preempt_enable(); |
9829 | ||
f656ce01 | 9830 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 9831 | |
b6c7a5dc HB |
9832 | /* |
9833 | * Profile KVM exit RIPs: | |
9834 | */ | |
9835 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
9836 | unsigned long rip = kvm_rip_read(vcpu); |
9837 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
9838 | } |
9839 | ||
cc578287 ZA |
9840 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
9841 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 9842 | |
5cfb1d5a MT |
9843 | if (vcpu->arch.apic_attention) |
9844 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 9845 | |
b3646477 | 9846 | r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); |
d905c069 MT |
9847 | return r; |
9848 | ||
9849 | cancel_injection: | |
8081ad06 SC |
9850 | if (req_immediate_exit) |
9851 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 9852 | static_call(kvm_x86_cancel_injection)(vcpu); |
ae7a2a3f MT |
9853 | if (unlikely(vcpu->arch.apic_attention)) |
9854 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
9855 | out: |
9856 | return r; | |
9857 | } | |
b6c7a5dc | 9858 | |
362c698f PB |
9859 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
9860 | { | |
bf9f6ac8 | 9861 | if (!kvm_arch_vcpu_runnable(vcpu) && |
b3646477 | 9862 | (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { |
9c8fd1ba PB |
9863 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
9864 | kvm_vcpu_block(vcpu); | |
9865 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 | 9866 | |
afaf0b2f | 9867 | if (kvm_x86_ops.post_block) |
b3646477 | 9868 | static_call(kvm_x86_post_block)(vcpu); |
bf9f6ac8 | 9869 | |
9c8fd1ba PB |
9870 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
9871 | return 1; | |
9872 | } | |
362c698f | 9873 | |
4fe09bcf JM |
9874 | if (kvm_apic_accept_events(vcpu) < 0) |
9875 | return 0; | |
362c698f PB |
9876 | switch(vcpu->arch.mp_state) { |
9877 | case KVM_MP_STATE_HALTED: | |
647daca2 | 9878 | case KVM_MP_STATE_AP_RESET_HOLD: |
362c698f PB |
9879 | vcpu->arch.pv.pv_unhalted = false; |
9880 | vcpu->arch.mp_state = | |
9881 | KVM_MP_STATE_RUNNABLE; | |
df561f66 | 9882 | fallthrough; |
362c698f PB |
9883 | case KVM_MP_STATE_RUNNABLE: |
9884 | vcpu->arch.apf.halted = false; | |
9885 | break; | |
9886 | case KVM_MP_STATE_INIT_RECEIVED: | |
9887 | break; | |
9888 | default: | |
9889 | return -EINTR; | |
362c698f PB |
9890 | } |
9891 | return 1; | |
9892 | } | |
09cec754 | 9893 | |
5d9bc648 PB |
9894 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
9895 | { | |
56083bdf | 9896 | if (is_guest_mode(vcpu)) |
cb6a32c2 | 9897 | kvm_check_nested_events(vcpu); |
0ad3bed6 | 9898 | |
5d9bc648 PB |
9899 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
9900 | !vcpu->arch.apf.halted); | |
9901 | } | |
9902 | ||
362c698f | 9903 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
9904 | { |
9905 | int r; | |
f656ce01 | 9906 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 9907 | |
f656ce01 | 9908 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
c595ceee | 9909 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 9910 | |
362c698f | 9911 | for (;;) { |
58f800d5 | 9912 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 9913 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 9914 | } else { |
362c698f | 9915 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
9916 | } |
9917 | ||
09cec754 GN |
9918 | if (r <= 0) |
9919 | break; | |
9920 | ||
084071d5 | 9921 | kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); |
09cec754 GN |
9922 | if (kvm_cpu_has_pending_timer(vcpu)) |
9923 | kvm_inject_pending_timer_irqs(vcpu); | |
9924 | ||
782d422b MG |
9925 | if (dm_request_for_irq_injection(vcpu) && |
9926 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
9927 | r = 0; |
9928 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 9929 | ++vcpu->stat.request_irq_exits; |
362c698f | 9930 | break; |
09cec754 | 9931 | } |
af585b92 | 9932 | |
f3020b88 | 9933 | if (__xfer_to_guest_mode_work_pending()) { |
f656ce01 | 9934 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
72c3c0fe TG |
9935 | r = xfer_to_guest_mode_handle_work(vcpu); |
9936 | if (r) | |
9937 | return r; | |
f656ce01 | 9938 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 9939 | } |
b6c7a5dc HB |
9940 | } |
9941 | ||
f656ce01 | 9942 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
9943 | |
9944 | return r; | |
9945 | } | |
9946 | ||
716d51ab GN |
9947 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
9948 | { | |
9949 | int r; | |
60fc3d02 | 9950 | |
716d51ab | 9951 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
0ce97a2b | 9952 | r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab | 9953 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
60fc3d02 | 9954 | return r; |
716d51ab GN |
9955 | } |
9956 | ||
9957 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
9958 | { | |
9959 | BUG_ON(!vcpu->arch.pio.count); | |
9960 | ||
9961 | return complete_emulated_io(vcpu); | |
9962 | } | |
9963 | ||
f78146b0 AK |
9964 | /* |
9965 | * Implements the following, as a state machine: | |
9966 | * | |
9967 | * read: | |
9968 | * for each fragment | |
87da7e66 XG |
9969 | * for each mmio piece in the fragment |
9970 | * write gpa, len | |
9971 | * exit | |
9972 | * copy data | |
f78146b0 AK |
9973 | * execute insn |
9974 | * | |
9975 | * write: | |
9976 | * for each fragment | |
87da7e66 XG |
9977 | * for each mmio piece in the fragment |
9978 | * write gpa, len | |
9979 | * copy data | |
9980 | * exit | |
f78146b0 | 9981 | */ |
716d51ab | 9982 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
9983 | { |
9984 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 9985 | struct kvm_mmio_fragment *frag; |
87da7e66 | 9986 | unsigned len; |
5287f194 | 9987 | |
716d51ab | 9988 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 9989 | |
716d51ab | 9990 | /* Complete previous fragment */ |
87da7e66 XG |
9991 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
9992 | len = min(8u, frag->len); | |
716d51ab | 9993 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
9994 | memcpy(frag->data, run->mmio.data, len); |
9995 | ||
9996 | if (frag->len <= 8) { | |
9997 | /* Switch to the next fragment. */ | |
9998 | frag++; | |
9999 | vcpu->mmio_cur_fragment++; | |
10000 | } else { | |
10001 | /* Go forward to the next mmio piece. */ | |
10002 | frag->data += len; | |
10003 | frag->gpa += len; | |
10004 | frag->len -= len; | |
10005 | } | |
10006 | ||
a08d3b3b | 10007 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 10008 | vcpu->mmio_needed = 0; |
0912c977 PB |
10009 | |
10010 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 10011 | if (vcpu->mmio_is_write) |
716d51ab GN |
10012 | return 1; |
10013 | vcpu->mmio_read_completed = 1; | |
10014 | return complete_emulated_io(vcpu); | |
10015 | } | |
87da7e66 | 10016 | |
716d51ab GN |
10017 | run->exit_reason = KVM_EXIT_MMIO; |
10018 | run->mmio.phys_addr = frag->gpa; | |
10019 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
10020 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
10021 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
10022 | run->mmio.is_write = vcpu->mmio_is_write; |
10023 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
10024 | return 0; | |
5287f194 AK |
10025 | } |
10026 | ||
c9aef3b8 SC |
10027 | static void kvm_save_current_fpu(struct fpu *fpu) |
10028 | { | |
10029 | /* | |
10030 | * If the target FPU state is not resident in the CPU registers, just | |
10031 | * memcpy() from current, else save CPU state directly to the target. | |
10032 | */ | |
10033 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
10034 | memcpy(&fpu->state, ¤t->thread.fpu.state, | |
10035 | fpu_kernel_xstate_size); | |
10036 | else | |
ebe7234b | 10037 | save_fpregs_to_fpstate(fpu); |
c9aef3b8 SC |
10038 | } |
10039 | ||
822f312d SAS |
10040 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
10041 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
10042 | { | |
5f409e20 RR |
10043 | fpregs_lock(); |
10044 | ||
c9aef3b8 SC |
10045 | kvm_save_current_fpu(vcpu->arch.user_fpu); |
10046 | ||
ed02b213 TL |
10047 | /* |
10048 | * Guests with protected state can't have it set by the hypervisor, | |
10049 | * so skip trying to set it. | |
10050 | */ | |
10051 | if (vcpu->arch.guest_fpu) | |
10052 | /* PKRU is separately restored in kvm_x86_ops.run. */ | |
1c61fada | 10053 | __restore_fpregs_from_fpstate(&vcpu->arch.guest_fpu->state, |
ed02b213 | 10054 | ~XFEATURE_MASK_PKRU); |
5f409e20 RR |
10055 | |
10056 | fpregs_mark_activate(); | |
10057 | fpregs_unlock(); | |
10058 | ||
822f312d SAS |
10059 | trace_kvm_fpu(1); |
10060 | } | |
10061 | ||
10062 | /* When vcpu_run ends, restore user space FPU context. */ | |
10063 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
10064 | { | |
5f409e20 RR |
10065 | fpregs_lock(); |
10066 | ||
ed02b213 TL |
10067 | /* |
10068 | * Guests with protected state can't have it read by the hypervisor, | |
10069 | * so skip trying to save it. | |
10070 | */ | |
10071 | if (vcpu->arch.guest_fpu) | |
10072 | kvm_save_current_fpu(vcpu->arch.guest_fpu); | |
c9aef3b8 | 10073 | |
1c61fada | 10074 | restore_fpregs_from_fpstate(&vcpu->arch.user_fpu->state); |
5f409e20 RR |
10075 | |
10076 | fpregs_mark_activate(); | |
10077 | fpregs_unlock(); | |
10078 | ||
822f312d SAS |
10079 | ++vcpu->stat.fpu_reload; |
10080 | trace_kvm_fpu(0); | |
10081 | } | |
10082 | ||
1b94f6f8 | 10083 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) |
b6c7a5dc | 10084 | { |
1b94f6f8 | 10085 | struct kvm_run *kvm_run = vcpu->run; |
b6c7a5dc | 10086 | int r; |
b6c7a5dc | 10087 | |
accb757d | 10088 | vcpu_load(vcpu); |
20b7035c | 10089 | kvm_sigset_activate(vcpu); |
15aad3be | 10090 | kvm_run->flags = 0; |
5663d8f9 PX |
10091 | kvm_load_guest_fpu(vcpu); |
10092 | ||
a4535290 | 10093 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
10094 | if (kvm_run->immediate_exit) { |
10095 | r = -EINTR; | |
10096 | goto out; | |
10097 | } | |
b6c7a5dc | 10098 | kvm_vcpu_block(vcpu); |
4fe09bcf JM |
10099 | if (kvm_apic_accept_events(vcpu) < 0) { |
10100 | r = 0; | |
10101 | goto out; | |
10102 | } | |
72875d8a | 10103 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 10104 | r = -EAGAIN; |
a0595000 JS |
10105 | if (signal_pending(current)) { |
10106 | r = -EINTR; | |
1b94f6f8 | 10107 | kvm_run->exit_reason = KVM_EXIT_INTR; |
a0595000 JS |
10108 | ++vcpu->stat.signal_exits; |
10109 | } | |
ac9f6dc0 | 10110 | goto out; |
b6c7a5dc HB |
10111 | } |
10112 | ||
e489a4a6 SC |
10113 | if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || |
10114 | (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { | |
01643c51 KH |
10115 | r = -EINVAL; |
10116 | goto out; | |
10117 | } | |
10118 | ||
1b94f6f8 | 10119 | if (kvm_run->kvm_dirty_regs) { |
01643c51 KH |
10120 | r = sync_regs(vcpu); |
10121 | if (r != 0) | |
10122 | goto out; | |
10123 | } | |
10124 | ||
b6c7a5dc | 10125 | /* re-sync apic's tpr */ |
35754c98 | 10126 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
10127 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
10128 | r = -EINVAL; | |
10129 | goto out; | |
10130 | } | |
10131 | } | |
b6c7a5dc | 10132 | |
716d51ab GN |
10133 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
10134 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
10135 | vcpu->arch.complete_userspace_io = NULL; | |
10136 | r = cui(vcpu); | |
10137 | if (r <= 0) | |
5663d8f9 | 10138 | goto out; |
716d51ab GN |
10139 | } else |
10140 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 10141 | |
460df4c1 PB |
10142 | if (kvm_run->immediate_exit) |
10143 | r = -EINTR; | |
10144 | else | |
10145 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
10146 | |
10147 | out: | |
5663d8f9 | 10148 | kvm_put_guest_fpu(vcpu); |
1b94f6f8 | 10149 | if (kvm_run->kvm_valid_regs) |
01643c51 | 10150 | store_regs(vcpu); |
f1d86e46 | 10151 | post_kvm_run_save(vcpu); |
20b7035c | 10152 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 10153 | |
accb757d | 10154 | vcpu_put(vcpu); |
b6c7a5dc HB |
10155 | return r; |
10156 | } | |
10157 | ||
01643c51 | 10158 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 10159 | { |
7ae441ea GN |
10160 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
10161 | /* | |
10162 | * We are here if userspace calls get_regs() in the middle of | |
10163 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 10164 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
10165 | * that usually, but some bad designed PV devices (vmware |
10166 | * backdoor interface) need this to work | |
10167 | */ | |
c9b8b07c | 10168 | emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); |
7ae441ea GN |
10169 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
10170 | } | |
de3cd117 SC |
10171 | regs->rax = kvm_rax_read(vcpu); |
10172 | regs->rbx = kvm_rbx_read(vcpu); | |
10173 | regs->rcx = kvm_rcx_read(vcpu); | |
10174 | regs->rdx = kvm_rdx_read(vcpu); | |
10175 | regs->rsi = kvm_rsi_read(vcpu); | |
10176 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 10177 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 10178 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 10179 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
10180 | regs->r8 = kvm_r8_read(vcpu); |
10181 | regs->r9 = kvm_r9_read(vcpu); | |
10182 | regs->r10 = kvm_r10_read(vcpu); | |
10183 | regs->r11 = kvm_r11_read(vcpu); | |
10184 | regs->r12 = kvm_r12_read(vcpu); | |
10185 | regs->r13 = kvm_r13_read(vcpu); | |
10186 | regs->r14 = kvm_r14_read(vcpu); | |
10187 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
10188 | #endif |
10189 | ||
5fdbf976 | 10190 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 10191 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 10192 | } |
b6c7a5dc | 10193 | |
01643c51 KH |
10194 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
10195 | { | |
10196 | vcpu_load(vcpu); | |
10197 | __get_regs(vcpu, regs); | |
1fc9b76b | 10198 | vcpu_put(vcpu); |
b6c7a5dc HB |
10199 | return 0; |
10200 | } | |
10201 | ||
01643c51 | 10202 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 10203 | { |
7ae441ea GN |
10204 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
10205 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
10206 | ||
de3cd117 SC |
10207 | kvm_rax_write(vcpu, regs->rax); |
10208 | kvm_rbx_write(vcpu, regs->rbx); | |
10209 | kvm_rcx_write(vcpu, regs->rcx); | |
10210 | kvm_rdx_write(vcpu, regs->rdx); | |
10211 | kvm_rsi_write(vcpu, regs->rsi); | |
10212 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 10213 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 10214 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 10215 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
10216 | kvm_r8_write(vcpu, regs->r8); |
10217 | kvm_r9_write(vcpu, regs->r9); | |
10218 | kvm_r10_write(vcpu, regs->r10); | |
10219 | kvm_r11_write(vcpu, regs->r11); | |
10220 | kvm_r12_write(vcpu, regs->r12); | |
10221 | kvm_r13_write(vcpu, regs->r13); | |
10222 | kvm_r14_write(vcpu, regs->r14); | |
10223 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
10224 | #endif |
10225 | ||
5fdbf976 | 10226 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 10227 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 10228 | |
b4f14abd JK |
10229 | vcpu->arch.exception.pending = false; |
10230 | ||
3842d135 | 10231 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 10232 | } |
3842d135 | 10233 | |
01643c51 KH |
10234 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
10235 | { | |
10236 | vcpu_load(vcpu); | |
10237 | __set_regs(vcpu, regs); | |
875656fe | 10238 | vcpu_put(vcpu); |
b6c7a5dc HB |
10239 | return 0; |
10240 | } | |
10241 | ||
b6c7a5dc HB |
10242 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
10243 | { | |
10244 | struct kvm_segment cs; | |
10245 | ||
3e6e0aab | 10246 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
10247 | *db = cs.db; |
10248 | *l = cs.l; | |
10249 | } | |
10250 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
10251 | ||
6dba9403 | 10252 | static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 10253 | { |
89a27f4d | 10254 | struct desc_ptr dt; |
b6c7a5dc | 10255 | |
5265713a TL |
10256 | if (vcpu->arch.guest_state_protected) |
10257 | goto skip_protected_regs; | |
10258 | ||
3e6e0aab GT |
10259 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
10260 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
10261 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
10262 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
10263 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
10264 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 10265 | |
3e6e0aab GT |
10266 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
10267 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 10268 | |
b3646477 | 10269 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
89a27f4d GN |
10270 | sregs->idt.limit = dt.size; |
10271 | sregs->idt.base = dt.address; | |
b3646477 | 10272 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
89a27f4d GN |
10273 | sregs->gdt.limit = dt.size; |
10274 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 10275 | |
ad312c7c | 10276 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 10277 | sregs->cr3 = kvm_read_cr3(vcpu); |
5265713a TL |
10278 | |
10279 | skip_protected_regs: | |
10280 | sregs->cr0 = kvm_read_cr0(vcpu); | |
fc78f519 | 10281 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 10282 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 10283 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc | 10284 | sregs->apic_base = kvm_get_apic_base(vcpu); |
6dba9403 | 10285 | } |
b6c7a5dc | 10286 | |
6dba9403 ML |
10287 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
10288 | { | |
10289 | __get_sregs_common(vcpu, sregs); | |
10290 | ||
10291 | if (vcpu->arch.guest_state_protected) | |
10292 | return; | |
b6c7a5dc | 10293 | |
04140b41 | 10294 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
10295 | set_bit(vcpu->arch.interrupt.nr, |
10296 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 10297 | } |
16d7a191 | 10298 | |
6dba9403 ML |
10299 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
10300 | { | |
10301 | int i; | |
10302 | ||
10303 | __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); | |
10304 | ||
10305 | if (vcpu->arch.guest_state_protected) | |
10306 | return; | |
10307 | ||
10308 | if (is_pae_paging(vcpu)) { | |
10309 | for (i = 0 ; i < 4 ; i++) | |
10310 | sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); | |
10311 | sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
10312 | } | |
10313 | } | |
10314 | ||
01643c51 KH |
10315 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
10316 | struct kvm_sregs *sregs) | |
10317 | { | |
10318 | vcpu_load(vcpu); | |
10319 | __get_sregs(vcpu, sregs); | |
bcdec41c | 10320 | vcpu_put(vcpu); |
b6c7a5dc HB |
10321 | return 0; |
10322 | } | |
10323 | ||
62d9f0db MT |
10324 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
10325 | struct kvm_mp_state *mp_state) | |
10326 | { | |
4fe09bcf JM |
10327 | int r; |
10328 | ||
fd232561 | 10329 | vcpu_load(vcpu); |
f958bd23 SC |
10330 | if (kvm_mpx_supported()) |
10331 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 10332 | |
4fe09bcf JM |
10333 | r = kvm_apic_accept_events(vcpu); |
10334 | if (r < 0) | |
10335 | goto out; | |
10336 | r = 0; | |
10337 | ||
647daca2 TL |
10338 | if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || |
10339 | vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && | |
10340 | vcpu->arch.pv.pv_unhalted) | |
6aef266c SV |
10341 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; |
10342 | else | |
10343 | mp_state->mp_state = vcpu->arch.mp_state; | |
10344 | ||
4fe09bcf | 10345 | out: |
f958bd23 SC |
10346 | if (kvm_mpx_supported()) |
10347 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 10348 | vcpu_put(vcpu); |
4fe09bcf | 10349 | return r; |
62d9f0db MT |
10350 | } |
10351 | ||
10352 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
10353 | struct kvm_mp_state *mp_state) | |
10354 | { | |
e83dff5e CD |
10355 | int ret = -EINVAL; |
10356 | ||
10357 | vcpu_load(vcpu); | |
10358 | ||
bce87cce | 10359 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 10360 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 10361 | goto out; |
66450a21 | 10362 | |
27cbe7d6 LA |
10363 | /* |
10364 | * KVM_MP_STATE_INIT_RECEIVED means the processor is in | |
10365 | * INIT state; latched init should be reported using | |
10366 | * KVM_SET_VCPU_EVENTS, so reject it here. | |
10367 | */ | |
10368 | if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && | |
28bf2888 DH |
10369 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
10370 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 10371 | goto out; |
28bf2888 | 10372 | |
66450a21 JK |
10373 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
10374 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
10375 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
10376 | } else | |
10377 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 10378 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
10379 | |
10380 | ret = 0; | |
10381 | out: | |
10382 | vcpu_put(vcpu); | |
10383 | return ret; | |
62d9f0db MT |
10384 | } |
10385 | ||
7f3d35fd KW |
10386 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
10387 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 10388 | { |
c9b8b07c | 10389 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d | 10390 | int ret; |
e01c2426 | 10391 | |
8ec4722d | 10392 | init_emulate_ctxt(vcpu); |
c697518a | 10393 | |
7f3d35fd | 10394 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 10395 | has_error_code, error_code); |
1051778f SC |
10396 | if (ret) { |
10397 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
10398 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
10399 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 10400 | return 0; |
1051778f | 10401 | } |
37817f29 | 10402 | |
9d74191a TY |
10403 | kvm_rip_write(vcpu, ctxt->eip); |
10404 | kvm_set_rflags(vcpu, ctxt->eflags); | |
60fc3d02 | 10405 | return 1; |
37817f29 IE |
10406 | } |
10407 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
10408 | ||
ee69c92b | 10409 | static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 10410 | { |
37b95951 | 10411 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
10412 | /* |
10413 | * When EFER.LME and CR0.PG are set, the processor is in | |
10414 | * 64-bit mode (though maybe in a 32-bit code segment). | |
10415 | * CR4.PAE and EFER.LMA must be set. | |
10416 | */ | |
ee69c92b SC |
10417 | if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) |
10418 | return false; | |
ca29e145 | 10419 | if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) |
c1c35cf7 | 10420 | return false; |
f2981033 LT |
10421 | } else { |
10422 | /* | |
10423 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
10424 | * segment cannot be 64-bit. | |
10425 | */ | |
10426 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
ee69c92b | 10427 | return false; |
f2981033 LT |
10428 | } |
10429 | ||
ee69c92b | 10430 | return kvm_is_valid_cr4(vcpu, sregs->cr4); |
f2981033 LT |
10431 | } |
10432 | ||
6dba9403 ML |
10433 | static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, |
10434 | int *mmu_reset_needed, bool update_pdptrs) | |
b6c7a5dc | 10435 | { |
58cb628d | 10436 | struct msr_data apic_base_msr; |
6dba9403 | 10437 | int idx; |
89a27f4d | 10438 | struct desc_ptr dt; |
b4ef9d4e | 10439 | |
ee69c92b | 10440 | if (!kvm_is_valid_sregs(vcpu, sregs)) |
6dba9403 | 10441 | return -EINVAL; |
f2981033 | 10442 | |
d3802286 JM |
10443 | apic_base_msr.data = sregs->apic_base; |
10444 | apic_base_msr.host_initiated = true; | |
10445 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
6dba9403 | 10446 | return -EINVAL; |
6d1068b3 | 10447 | |
5265713a | 10448 | if (vcpu->arch.guest_state_protected) |
6dba9403 | 10449 | return 0; |
5265713a | 10450 | |
89a27f4d GN |
10451 | dt.size = sregs->idt.limit; |
10452 | dt.address = sregs->idt.base; | |
b3646477 | 10453 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
89a27f4d GN |
10454 | dt.size = sregs->gdt.limit; |
10455 | dt.address = sregs->gdt.base; | |
b3646477 | 10456 | static_call(kvm_x86_set_gdt)(vcpu, &dt); |
b6c7a5dc | 10457 | |
ad312c7c | 10458 | vcpu->arch.cr2 = sregs->cr2; |
6dba9403 | 10459 | *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 10460 | vcpu->arch.cr3 = sregs->cr3; |
cb3c1e2f | 10461 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
b6c7a5dc | 10462 | |
2d3ad1f4 | 10463 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 10464 | |
6dba9403 | 10465 | *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b3646477 | 10466 | static_call(kvm_x86_set_efer)(vcpu, sregs->efer); |
b6c7a5dc | 10467 | |
6dba9403 | 10468 | *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b3646477 | 10469 | static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); |
d7306163 | 10470 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 10471 | |
6dba9403 | 10472 | *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b3646477 | 10473 | static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); |
63f42e02 | 10474 | |
6dba9403 ML |
10475 | if (update_pdptrs) { |
10476 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
10477 | if (is_pae_paging(vcpu)) { | |
10478 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); | |
10479 | *mmu_reset_needed = 1; | |
10480 | } | |
10481 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
7c93be44 | 10482 | } |
b6c7a5dc | 10483 | |
3e6e0aab GT |
10484 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
10485 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
10486 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
10487 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
10488 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
10489 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 10490 | |
3e6e0aab GT |
10491 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
10492 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 10493 | |
5f0269f5 ME |
10494 | update_cr8_intercept(vcpu); |
10495 | ||
9c3e4aab | 10496 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 10497 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 10498 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 10499 | !is_protmode(vcpu)) |
9c3e4aab MT |
10500 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
10501 | ||
6dba9403 ML |
10502 | return 0; |
10503 | } | |
10504 | ||
10505 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
10506 | { | |
10507 | int pending_vec, max_bits; | |
10508 | int mmu_reset_needed = 0; | |
10509 | int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); | |
10510 | ||
10511 | if (ret) | |
10512 | return ret; | |
10513 | ||
10514 | if (mmu_reset_needed) | |
10515 | kvm_mmu_reset_context(vcpu); | |
10516 | ||
5265713a TL |
10517 | max_bits = KVM_NR_INTERRUPTS; |
10518 | pending_vec = find_first_bit( | |
10519 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
6dba9403 | 10520 | |
5265713a TL |
10521 | if (pending_vec < max_bits) { |
10522 | kvm_queue_interrupt(vcpu, pending_vec, false); | |
10523 | pr_debug("Set back pending irq %d\n", pending_vec); | |
6dba9403 | 10524 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5265713a | 10525 | } |
6dba9403 ML |
10526 | return 0; |
10527 | } | |
5265713a | 10528 | |
6dba9403 ML |
10529 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
10530 | { | |
10531 | int mmu_reset_needed = 0; | |
10532 | bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
10533 | bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && | |
10534 | !(sregs2->efer & EFER_LMA); | |
10535 | int i, ret; | |
3842d135 | 10536 | |
6dba9403 ML |
10537 | if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) |
10538 | return -EINVAL; | |
10539 | ||
10540 | if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) | |
10541 | return -EINVAL; | |
10542 | ||
10543 | ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, | |
10544 | &mmu_reset_needed, !valid_pdptrs); | |
10545 | if (ret) | |
10546 | return ret; | |
10547 | ||
10548 | if (valid_pdptrs) { | |
10549 | for (i = 0; i < 4 ; i++) | |
10550 | kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); | |
10551 | ||
10552 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); | |
10553 | mmu_reset_needed = 1; | |
158a48ec | 10554 | vcpu->arch.pdptrs_from_userspace = true; |
6dba9403 ML |
10555 | } |
10556 | if (mmu_reset_needed) | |
10557 | kvm_mmu_reset_context(vcpu); | |
10558 | return 0; | |
01643c51 KH |
10559 | } |
10560 | ||
10561 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
10562 | struct kvm_sregs *sregs) | |
10563 | { | |
10564 | int ret; | |
10565 | ||
10566 | vcpu_load(vcpu); | |
10567 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
10568 | vcpu_put(vcpu); |
10569 | return ret; | |
b6c7a5dc HB |
10570 | } |
10571 | ||
d0bfb940 JK |
10572 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
10573 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 10574 | { |
355be0b9 | 10575 | unsigned long rflags; |
ae675ef0 | 10576 | int i, r; |
b6c7a5dc | 10577 | |
8d4846b9 TL |
10578 | if (vcpu->arch.guest_state_protected) |
10579 | return -EINVAL; | |
10580 | ||
66b56562 CD |
10581 | vcpu_load(vcpu); |
10582 | ||
4f926bf2 JK |
10583 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
10584 | r = -EBUSY; | |
10585 | if (vcpu->arch.exception.pending) | |
2122ff5e | 10586 | goto out; |
4f926bf2 JK |
10587 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
10588 | kvm_queue_exception(vcpu, DB_VECTOR); | |
10589 | else | |
10590 | kvm_queue_exception(vcpu, BP_VECTOR); | |
10591 | } | |
10592 | ||
91586a3b JK |
10593 | /* |
10594 | * Read rflags as long as potentially injected trace flags are still | |
10595 | * filtered out. | |
10596 | */ | |
10597 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
10598 | |
10599 | vcpu->guest_debug = dbg->control; | |
10600 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
10601 | vcpu->guest_debug = 0; | |
10602 | ||
10603 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
10604 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
10605 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 10606 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
10607 | } else { |
10608 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
10609 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 10610 | } |
c8639010 | 10611 | kvm_update_dr7(vcpu); |
ae675ef0 | 10612 | |
f92653ee | 10613 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
e87e46d5 | 10614 | vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); |
94fe45da | 10615 | |
91586a3b JK |
10616 | /* |
10617 | * Trigger an rflags update that will inject or remove the trace | |
10618 | * flags. | |
10619 | */ | |
10620 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 10621 | |
b3646477 | 10622 | static_call(kvm_x86_update_exception_bitmap)(vcpu); |
b6c7a5dc | 10623 | |
4f926bf2 | 10624 | r = 0; |
d0bfb940 | 10625 | |
2122ff5e | 10626 | out: |
66b56562 | 10627 | vcpu_put(vcpu); |
b6c7a5dc HB |
10628 | return r; |
10629 | } | |
10630 | ||
8b006791 ZX |
10631 | /* |
10632 | * Translate a guest virtual address to a guest physical address. | |
10633 | */ | |
10634 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
10635 | struct kvm_translation *tr) | |
10636 | { | |
10637 | unsigned long vaddr = tr->linear_address; | |
10638 | gpa_t gpa; | |
f656ce01 | 10639 | int idx; |
8b006791 | 10640 | |
1da5b61d CD |
10641 | vcpu_load(vcpu); |
10642 | ||
f656ce01 | 10643 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 10644 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 10645 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
10646 | tr->physical_address = gpa; |
10647 | tr->valid = gpa != UNMAPPED_GVA; | |
10648 | tr->writeable = 1; | |
10649 | tr->usermode = 0; | |
8b006791 | 10650 | |
1da5b61d | 10651 | vcpu_put(vcpu); |
8b006791 ZX |
10652 | return 0; |
10653 | } | |
10654 | ||
d0752060 HB |
10655 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
10656 | { | |
1393123e | 10657 | struct fxregs_state *fxsave; |
d0752060 | 10658 | |
ed02b213 TL |
10659 | if (!vcpu->arch.guest_fpu) |
10660 | return 0; | |
10661 | ||
1393123e | 10662 | vcpu_load(vcpu); |
d0752060 | 10663 | |
b666a4b6 | 10664 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 HB |
10665 | memcpy(fpu->fpr, fxsave->st_space, 128); |
10666 | fpu->fcw = fxsave->cwd; | |
10667 | fpu->fsw = fxsave->swd; | |
10668 | fpu->ftwx = fxsave->twd; | |
10669 | fpu->last_opcode = fxsave->fop; | |
10670 | fpu->last_ip = fxsave->rip; | |
10671 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 10672 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 10673 | |
1393123e | 10674 | vcpu_put(vcpu); |
d0752060 HB |
10675 | return 0; |
10676 | } | |
10677 | ||
10678 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
10679 | { | |
6a96bc7f CD |
10680 | struct fxregs_state *fxsave; |
10681 | ||
ed02b213 TL |
10682 | if (!vcpu->arch.guest_fpu) |
10683 | return 0; | |
10684 | ||
6a96bc7f CD |
10685 | vcpu_load(vcpu); |
10686 | ||
b666a4b6 | 10687 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 | 10688 | |
d0752060 HB |
10689 | memcpy(fxsave->st_space, fpu->fpr, 128); |
10690 | fxsave->cwd = fpu->fcw; | |
10691 | fxsave->swd = fpu->fsw; | |
10692 | fxsave->twd = fpu->ftwx; | |
10693 | fxsave->fop = fpu->last_opcode; | |
10694 | fxsave->rip = fpu->last_ip; | |
10695 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 10696 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 10697 | |
6a96bc7f | 10698 | vcpu_put(vcpu); |
d0752060 HB |
10699 | return 0; |
10700 | } | |
10701 | ||
01643c51 KH |
10702 | static void store_regs(struct kvm_vcpu *vcpu) |
10703 | { | |
10704 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
10705 | ||
10706 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
10707 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
10708 | ||
10709 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
10710 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
10711 | ||
10712 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
10713 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
10714 | vcpu, &vcpu->run->s.regs.events); | |
10715 | } | |
10716 | ||
10717 | static int sync_regs(struct kvm_vcpu *vcpu) | |
10718 | { | |
01643c51 KH |
10719 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { |
10720 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
10721 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
10722 | } | |
10723 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
10724 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
10725 | return -EINVAL; | |
10726 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
10727 | } | |
10728 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
10729 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
10730 | vcpu, &vcpu->run->s.regs.events)) | |
10731 | return -EINVAL; | |
10732 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
10733 | } | |
10734 | ||
10735 | return 0; | |
10736 | } | |
10737 | ||
0ee6a517 | 10738 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 10739 | { |
ed02b213 TL |
10740 | if (!vcpu->arch.guest_fpu) |
10741 | return; | |
10742 | ||
b666a4b6 | 10743 | fpstate_init(&vcpu->arch.guest_fpu->state); |
782511b0 | 10744 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
b666a4b6 | 10745 | vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = |
df1daba7 | 10746 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 10747 | |
2acf923e DC |
10748 | /* |
10749 | * Ensure guest xcr0 is valid for loading | |
10750 | */ | |
d91cab78 | 10751 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 10752 | |
ad312c7c | 10753 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 10754 | } |
d0752060 | 10755 | |
ed02b213 TL |
10756 | void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) |
10757 | { | |
10758 | if (vcpu->arch.guest_fpu) { | |
10759 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
10760 | vcpu->arch.guest_fpu = NULL; | |
10761 | } | |
10762 | } | |
10763 | EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); | |
10764 | ||
897cc38e | 10765 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 10766 | { |
897cc38e SC |
10767 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
10768 | pr_warn_once("kvm: SMP vm created on host with unstable TSC; " | |
10769 | "guest TSC will not be reliable\n"); | |
7f1ea208 | 10770 | |
897cc38e | 10771 | return 0; |
e9b11c17 ZX |
10772 | } |
10773 | ||
e529ef66 | 10774 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 10775 | { |
95a0d01e SC |
10776 | struct page *page; |
10777 | int r; | |
c447e76b | 10778 | |
63f5a190 | 10779 | vcpu->arch.last_vmentry_cpu = -1; |
7117003f SC |
10780 | vcpu->arch.regs_avail = ~0; |
10781 | vcpu->arch.regs_dirty = ~0; | |
63f5a190 | 10782 | |
95a0d01e SC |
10783 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
10784 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
10785 | else | |
10786 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 10787 | |
95a0d01e SC |
10788 | r = kvm_mmu_create(vcpu); |
10789 | if (r < 0) | |
10790 | return r; | |
10791 | ||
10792 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
10793 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
10794 | if (r < 0) | |
10795 | goto fail_mmu_destroy; | |
4e19c36f SS |
10796 | if (kvm_apicv_activated(vcpu->kvm)) |
10797 | vcpu->arch.apicv_active = true; | |
95a0d01e | 10798 | } else |
6e4e3b4d | 10799 | static_branch_inc(&kvm_has_noapic_vcpu); |
95a0d01e SC |
10800 | |
10801 | r = -ENOMEM; | |
10802 | ||
93bb59ca | 10803 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); |
95a0d01e SC |
10804 | if (!page) |
10805 | goto fail_free_lapic; | |
10806 | vcpu->arch.pio_data = page_address(page); | |
10807 | ||
10808 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, | |
10809 | GFP_KERNEL_ACCOUNT); | |
10810 | if (!vcpu->arch.mce_banks) | |
10811 | goto fail_free_pio_data; | |
10812 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
10813 | ||
10814 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
10815 | GFP_KERNEL_ACCOUNT)) | |
10816 | goto fail_free_mce_banks; | |
10817 | ||
c9b8b07c SC |
10818 | if (!alloc_emulate_ctxt(vcpu)) |
10819 | goto free_wbinvd_dirty_mask; | |
10820 | ||
95a0d01e SC |
10821 | vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, |
10822 | GFP_KERNEL_ACCOUNT); | |
10823 | if (!vcpu->arch.user_fpu) { | |
10824 | pr_err("kvm: failed to allocate userspace's fpu\n"); | |
c9b8b07c | 10825 | goto free_emulate_ctxt; |
95a0d01e SC |
10826 | } |
10827 | ||
10828 | vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, | |
10829 | GFP_KERNEL_ACCOUNT); | |
10830 | if (!vcpu->arch.guest_fpu) { | |
10831 | pr_err("kvm: failed to allocate vcpu's fpu\n"); | |
10832 | goto free_user_fpu; | |
10833 | } | |
10834 | fx_init(vcpu); | |
10835 | ||
95a0d01e | 10836 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
a8ac864a | 10837 | vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); |
95a0d01e SC |
10838 | |
10839 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
10840 | ||
10841 | kvm_async_pf_hash_reset(vcpu); | |
10842 | kvm_pmu_init(vcpu); | |
10843 | ||
10844 | vcpu->arch.pending_external_vector = -1; | |
10845 | vcpu->arch.preempted_in_kernel = false; | |
10846 | ||
3c86c0d3 VP |
10847 | #if IS_ENABLED(CONFIG_HYPERV) |
10848 | vcpu->arch.hv_root_tdp = INVALID_PAGE; | |
10849 | #endif | |
10850 | ||
b3646477 | 10851 | r = static_call(kvm_x86_vcpu_create)(vcpu); |
95a0d01e SC |
10852 | if (r) |
10853 | goto free_guest_fpu; | |
e9b11c17 | 10854 | |
0cf9135b | 10855 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 10856 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
19efffa2 | 10857 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 10858 | vcpu_load(vcpu); |
1ab9287a | 10859 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
d28bc9dd | 10860 | kvm_vcpu_reset(vcpu, false); |
c9060662 | 10861 | kvm_init_mmu(vcpu); |
e9b11c17 | 10862 | vcpu_put(vcpu); |
ec7660cc | 10863 | return 0; |
95a0d01e SC |
10864 | |
10865 | free_guest_fpu: | |
ed02b213 | 10866 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10867 | free_user_fpu: |
10868 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
c9b8b07c SC |
10869 | free_emulate_ctxt: |
10870 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); | |
95a0d01e SC |
10871 | free_wbinvd_dirty_mask: |
10872 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
10873 | fail_free_mce_banks: | |
10874 | kfree(vcpu->arch.mce_banks); | |
10875 | fail_free_pio_data: | |
10876 | free_page((unsigned long)vcpu->arch.pio_data); | |
10877 | fail_free_lapic: | |
10878 | kvm_free_lapic(vcpu); | |
10879 | fail_mmu_destroy: | |
10880 | kvm_mmu_destroy(vcpu); | |
10881 | return r; | |
e9b11c17 ZX |
10882 | } |
10883 | ||
31928aa5 | 10884 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 10885 | { |
332967a3 | 10886 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 10887 | |
ec7660cc | 10888 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 10889 | return; |
ec7660cc | 10890 | vcpu_load(vcpu); |
0c899c25 | 10891 | kvm_synchronize_tsc(vcpu, 0); |
42897d86 | 10892 | vcpu_put(vcpu); |
2d5ba19b MT |
10893 | |
10894 | /* poll control enabled by default */ | |
10895 | vcpu->arch.msr_kvm_poll_control = 1; | |
10896 | ||
ec7660cc | 10897 | mutex_unlock(&vcpu->mutex); |
42897d86 | 10898 | |
b34de572 WL |
10899 | if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) |
10900 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
10901 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
10902 | } |
10903 | ||
d40ccc62 | 10904 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 10905 | { |
95a0d01e | 10906 | int idx; |
344d9588 | 10907 | |
50b143e1 | 10908 | kvmclock_reset(vcpu); |
e9b11c17 | 10909 | |
b3646477 | 10910 | static_call(kvm_x86_vcpu_free)(vcpu); |
50b143e1 | 10911 | |
c9b8b07c | 10912 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); |
50b143e1 SC |
10913 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
10914 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
ed02b213 | 10915 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10916 | |
10917 | kvm_hv_vcpu_uninit(vcpu); | |
10918 | kvm_pmu_destroy(vcpu); | |
10919 | kfree(vcpu->arch.mce_banks); | |
10920 | kvm_free_lapic(vcpu); | |
10921 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
10922 | kvm_mmu_destroy(vcpu); | |
10923 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
10924 | free_page((unsigned long)vcpu->arch.pio_data); | |
255cbecf | 10925 | kvfree(vcpu->arch.cpuid_entries); |
95a0d01e | 10926 | if (!lapic_in_kernel(vcpu)) |
6e4e3b4d | 10927 | static_branch_dec(&kvm_has_noapic_vcpu); |
e9b11c17 ZX |
10928 | } |
10929 | ||
d28bc9dd | 10930 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 10931 | { |
0aa18375 | 10932 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
4c72ab5a | 10933 | unsigned long new_cr0; |
49d8665c | 10934 | u32 eax, dummy; |
0aa18375 | 10935 | |
b7e31be3 RK |
10936 | kvm_lapic_reset(vcpu, init_event); |
10937 | ||
e69fab5d PB |
10938 | vcpu->arch.hflags = 0; |
10939 | ||
c43203ca | 10940 | vcpu->arch.smi_pending = 0; |
52797bf9 | 10941 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
10942 | atomic_set(&vcpu->arch.nmi_queued, 0); |
10943 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 10944 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
10945 | kvm_clear_interrupt_queue(vcpu); |
10946 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 10947 | |
42dbaa5a | 10948 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 10949 | kvm_update_dr0123(vcpu); |
9a3ecd5e | 10950 | vcpu->arch.dr6 = DR6_ACTIVE_LOW; |
42dbaa5a | 10951 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 10952 | kvm_update_dr7(vcpu); |
42dbaa5a | 10953 | |
1119022c NA |
10954 | vcpu->arch.cr2 = 0; |
10955 | ||
3842d135 | 10956 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2635b5c4 VK |
10957 | vcpu->arch.apf.msr_en_val = 0; |
10958 | vcpu->arch.apf.msr_int_val = 0; | |
c9aaa895 | 10959 | vcpu->arch.st.msr_val = 0; |
3842d135 | 10960 | |
12f9a48f GC |
10961 | kvmclock_reset(vcpu); |
10962 | ||
af585b92 GN |
10963 | kvm_clear_async_pf_completion_queue(vcpu); |
10964 | kvm_async_pf_hash_reset(vcpu); | |
10965 | vcpu->arch.apf.halted = false; | |
3842d135 | 10966 | |
ed02b213 | 10967 | if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { |
a554d207 WL |
10968 | void *mpx_state_buffer; |
10969 | ||
10970 | /* | |
10971 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
10972 | * called with loaded FPU and does not let userspace fix the state. | |
10973 | */ | |
f775b13e RR |
10974 | if (init_event) |
10975 | kvm_put_guest_fpu(vcpu); | |
b666a4b6 | 10976 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10977 | XFEATURE_BNDREGS); |
a554d207 WL |
10978 | if (mpx_state_buffer) |
10979 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
b666a4b6 | 10980 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10981 | XFEATURE_BNDCSR); |
a554d207 WL |
10982 | if (mpx_state_buffer) |
10983 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
10984 | if (init_event) |
10985 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
10986 | } |
10987 | ||
64d60670 | 10988 | if (!init_event) { |
d28bc9dd | 10989 | kvm_pmu_reset(vcpu); |
64d60670 | 10990 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 10991 | |
db2336a8 | 10992 | vcpu->arch.msr_misc_features_enables = 0; |
a554d207 | 10993 | |
49624fd7 LX |
10994 | __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP); |
10995 | __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true); | |
64d60670 | 10996 | } |
f5132b01 | 10997 | |
66f7b72e JS |
10998 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
10999 | vcpu->arch.regs_avail = ~0; | |
11000 | vcpu->arch.regs_dirty = ~0; | |
11001 | ||
49d8665c SC |
11002 | /* |
11003 | * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) | |
11004 | * if no CPUID match is found. Note, it's impossible to get a match at | |
11005 | * RESET since KVM emulates RESET before exposing the vCPU to userspace, | |
11006 | * i.e. it'simpossible for kvm_cpuid() to find a valid entry on RESET. | |
11007 | * But, go through the motions in case that's ever remedied. | |
11008 | */ | |
11009 | eax = 1; | |
11010 | if (!kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true)) | |
11011 | eax = 0x600; | |
11012 | kvm_rdx_write(vcpu, eax); | |
11013 | ||
b3646477 | 11014 | static_call(kvm_x86_vcpu_reset)(vcpu, init_event); |
0aa18375 | 11015 | |
f39e805e SC |
11016 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); |
11017 | kvm_rip_write(vcpu, 0xfff0); | |
11018 | ||
03a6e840 SC |
11019 | vcpu->arch.cr3 = 0; |
11020 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); | |
11021 | ||
4c72ab5a SC |
11022 | /* |
11023 | * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions | |
11024 | * of Intel's SDM list CD/NW as being set on INIT, but they contradict | |
11025 | * (or qualify) that with a footnote stating that CD/NW are preserved. | |
11026 | */ | |
11027 | new_cr0 = X86_CR0_ET; | |
11028 | if (init_event) | |
11029 | new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); | |
11030 | else | |
11031 | new_cr0 |= X86_CR0_NW | X86_CR0_CD; | |
11032 | ||
11033 | static_call(kvm_x86_set_cr0)(vcpu, new_cr0); | |
f39e805e SC |
11034 | static_call(kvm_x86_set_cr4)(vcpu, 0); |
11035 | static_call(kvm_x86_set_efer)(vcpu, 0); | |
11036 | static_call(kvm_x86_update_exception_bitmap)(vcpu); | |
11037 | ||
0aa18375 SC |
11038 | /* |
11039 | * Reset the MMU context if paging was enabled prior to INIT (which is | |
11040 | * implied if CR0.PG=1 as CR0 will be '0' prior to RESET). Unlike the | |
11041 | * standard CR0/CR4/EFER modification paths, only CR0.PG needs to be | |
11042 | * checked because it is unconditionally cleared on INIT and all other | |
11043 | * paging related bits are ignored if paging is disabled, i.e. CR0.WP, | |
11044 | * CR4, and EFER changes are all irrelevant if CR0.PG was '0'. | |
11045 | */ | |
11046 | if (old_cr0 & X86_CR0_PG) | |
11047 | kvm_mmu_reset_context(vcpu); | |
df37ed38 SC |
11048 | |
11049 | /* | |
11050 | * Intel's SDM states that all TLB entries are flushed on INIT. AMD's | |
11051 | * APM states the TLBs are untouched by INIT, but it also states that | |
11052 | * the TLBs are flushed on "External initialization of the processor." | |
11053 | * Flush the guest TLB regardless of vendor, there is no meaningful | |
11054 | * benefit in relying on the guest to flush the TLB immediately after | |
11055 | * INIT. A spurious TLB flush is benign and likely negligible from a | |
11056 | * performance perspective. | |
11057 | */ | |
11058 | if (init_event) | |
11059 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
e9b11c17 | 11060 | } |
265e4353 | 11061 | EXPORT_SYMBOL_GPL(kvm_vcpu_reset); |
e9b11c17 | 11062 | |
2b4a273b | 11063 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
11064 | { |
11065 | struct kvm_segment cs; | |
11066 | ||
11067 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
11068 | cs.selector = vector << 8; | |
11069 | cs.base = vector << 12; | |
11070 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
11071 | kvm_rip_write(vcpu, 0); | |
e9b11c17 | 11072 | } |
647daca2 | 11073 | EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); |
e9b11c17 | 11074 | |
13a34e06 | 11075 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 11076 | { |
ca84d1a2 ZA |
11077 | struct kvm *kvm; |
11078 | struct kvm_vcpu *vcpu; | |
11079 | int i; | |
0dd6a6ed ZA |
11080 | int ret; |
11081 | u64 local_tsc; | |
11082 | u64 max_tsc = 0; | |
11083 | bool stable, backwards_tsc = false; | |
18863bdd | 11084 | |
7e34fbd0 | 11085 | kvm_user_return_msr_cpu_online(); |
b3646477 | 11086 | ret = static_call(kvm_x86_hardware_enable)(); |
0dd6a6ed ZA |
11087 | if (ret != 0) |
11088 | return ret; | |
11089 | ||
4ea1636b | 11090 | local_tsc = rdtsc(); |
b0c39dc6 | 11091 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
11092 | list_for_each_entry(kvm, &vm_list, vm_list) { |
11093 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
11094 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 11095 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
11096 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
11097 | backwards_tsc = true; | |
11098 | if (vcpu->arch.last_host_tsc > max_tsc) | |
11099 | max_tsc = vcpu->arch.last_host_tsc; | |
11100 | } | |
11101 | } | |
11102 | } | |
11103 | ||
11104 | /* | |
11105 | * Sometimes, even reliable TSCs go backwards. This happens on | |
11106 | * platforms that reset TSC during suspend or hibernate actions, but | |
11107 | * maintain synchronization. We must compensate. Fortunately, we can | |
11108 | * detect that condition here, which happens early in CPU bringup, | |
11109 | * before any KVM threads can be running. Unfortunately, we can't | |
11110 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
11111 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 11112 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
11113 | * variables that haven't been updated yet. |
11114 | * | |
11115 | * So we simply find the maximum observed TSC above, then record the | |
11116 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
11117 | * the adjustment will be applied. Note that we accumulate | |
11118 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
11119 | * gets a chance to run again. In the event that no KVM threads get a | |
11120 | * chance to run, we will miss the entire elapsed period, as we'll have | |
11121 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
11122 | * loose cycle time. This isn't too big a deal, since the loss will be | |
11123 | * uniform across all VCPUs (not to mention the scenario is extremely | |
11124 | * unlikely). It is possible that a second hibernate recovery happens | |
11125 | * much faster than a first, causing the observed TSC here to be | |
11126 | * smaller; this would require additional padding adjustment, which is | |
11127 | * why we set last_host_tsc to the local tsc observed here. | |
11128 | * | |
11129 | * N.B. - this code below runs only on platforms with reliable TSC, | |
11130 | * as that is the only way backwards_tsc is set above. Also note | |
11131 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
11132 | * have the same delta_cyc adjustment applied if backwards_tsc | |
11133 | * is detected. Note further, this adjustment is only done once, | |
11134 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
11135 | * called multiple times (one for each physical CPU bringup). | |
11136 | * | |
4a969980 | 11137 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
11138 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
11139 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
11140 | * guarantee that they stay in perfect synchronization. | |
11141 | */ | |
11142 | if (backwards_tsc) { | |
11143 | u64 delta_cyc = max_tsc - local_tsc; | |
11144 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 11145 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
11146 | kvm_for_each_vcpu(i, vcpu, kvm) { |
11147 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
11148 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 11149 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
11150 | } |
11151 | ||
11152 | /* | |
11153 | * We have to disable TSC offset matching.. if you were | |
11154 | * booting a VM while issuing an S4 host suspend.... | |
11155 | * you may have some problem. Solving this issue is | |
11156 | * left as an exercise to the reader. | |
11157 | */ | |
11158 | kvm->arch.last_tsc_nsec = 0; | |
11159 | kvm->arch.last_tsc_write = 0; | |
11160 | } | |
11161 | ||
11162 | } | |
11163 | return 0; | |
e9b11c17 ZX |
11164 | } |
11165 | ||
13a34e06 | 11166 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 11167 | { |
b3646477 | 11168 | static_call(kvm_x86_hardware_disable)(); |
13a34e06 | 11169 | drop_user_return_notifiers(); |
e9b11c17 ZX |
11170 | } |
11171 | ||
b9904085 | 11172 | int kvm_arch_hardware_setup(void *opaque) |
e9b11c17 | 11173 | { |
d008dfdb | 11174 | struct kvm_x86_init_ops *ops = opaque; |
9e9c3fe4 NA |
11175 | int r; |
11176 | ||
91661989 SC |
11177 | rdmsrl_safe(MSR_EFER, &host_efer); |
11178 | ||
408e9a31 PB |
11179 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
11180 | rdmsrl(MSR_IA32_XSS, host_xss); | |
11181 | ||
d008dfdb | 11182 | r = ops->hardware_setup(); |
9e9c3fe4 NA |
11183 | if (r != 0) |
11184 | return r; | |
11185 | ||
afaf0b2f | 11186 | memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); |
b3646477 | 11187 | kvm_ops_static_call_update(); |
69c6f69a | 11188 | |
f2b7891e SC |
11189 | if (ops->intel_pt_intr_in_guest && ops->intel_pt_intr_in_guest()) |
11190 | kvm_guest_cbs.handle_intel_pt_intr = kvm_handle_intel_pt_intr; | |
a9140706 SC |
11191 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
11192 | ||
408e9a31 PB |
11193 | if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) |
11194 | supported_xss = 0; | |
11195 | ||
139f7425 PB |
11196 | #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) |
11197 | cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); | |
11198 | #undef __kvm_cpu_cap_has | |
b11306b5 | 11199 | |
35181e86 HZ |
11200 | if (kvm_has_tsc_control) { |
11201 | /* | |
11202 | * Make sure the user can only configure tsc_khz values that | |
11203 | * fit into a signed integer. | |
273ba457 | 11204 | * A min value is not calculated because it will always |
35181e86 HZ |
11205 | * be 1 on all machines. |
11206 | */ | |
11207 | u64 max = min(0x7fffffffULL, | |
11208 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
11209 | kvm_max_guest_tsc_khz = max; | |
11210 | ||
ad721883 | 11211 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 11212 | } |
ad721883 | 11213 | |
9e9c3fe4 NA |
11214 | kvm_init_msr_list(); |
11215 | return 0; | |
e9b11c17 ZX |
11216 | } |
11217 | ||
11218 | void kvm_arch_hardware_unsetup(void) | |
11219 | { | |
a9140706 | 11220 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
f2b7891e | 11221 | kvm_guest_cbs.handle_intel_pt_intr = NULL; |
a9140706 | 11222 | |
b3646477 | 11223 | static_call(kvm_x86_hardware_unsetup)(); |
e9b11c17 ZX |
11224 | } |
11225 | ||
b9904085 | 11226 | int kvm_arch_check_processor_compat(void *opaque) |
e9b11c17 | 11227 | { |
f1cdecf5 | 11228 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); |
d008dfdb | 11229 | struct kvm_x86_init_ops *ops = opaque; |
f1cdecf5 SC |
11230 | |
11231 | WARN_ON(!irqs_disabled()); | |
11232 | ||
139f7425 PB |
11233 | if (__cr4_reserved_bits(cpu_has, c) != |
11234 | __cr4_reserved_bits(cpu_has, &boot_cpu_data)) | |
f1cdecf5 SC |
11235 | return -EIO; |
11236 | ||
d008dfdb | 11237 | return ops->check_processor_compatibility(); |
d71ba788 PB |
11238 | } |
11239 | ||
11240 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
11241 | { | |
11242 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
11243 | } | |
11244 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
11245 | ||
11246 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
11247 | { | |
11248 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
11249 | } |
11250 | ||
6e4e3b4d CL |
11251 | __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); |
11252 | EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); | |
54e9818f | 11253 | |
e790d9ef RK |
11254 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
11255 | { | |
b35e5548 LX |
11256 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
11257 | ||
c595ceee | 11258 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
11259 | if (pmu->version && unlikely(pmu->event_count)) { |
11260 | pmu->need_cleanup = true; | |
11261 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
11262 | } | |
b3646477 | 11263 | static_call(kvm_x86_sched_in)(vcpu, cpu); |
e790d9ef RK |
11264 | } |
11265 | ||
562b6b08 SC |
11266 | void kvm_arch_free_vm(struct kvm *kvm) |
11267 | { | |
05f04ae4 | 11268 | kfree(to_kvm_hv(kvm)->hv_pa_pg); |
562b6b08 | 11269 | vfree(kvm); |
e790d9ef RK |
11270 | } |
11271 | ||
562b6b08 | 11272 | |
e08b9637 | 11273 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 11274 | { |
eb7511bf HZ |
11275 | int ret; |
11276 | ||
e08b9637 CO |
11277 | if (type) |
11278 | return -EINVAL; | |
11279 | ||
eb7511bf HZ |
11280 | ret = kvm_page_track_init(kvm); |
11281 | if (ret) | |
11282 | return ret; | |
11283 | ||
6ef768fa | 11284 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 11285 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
10605204 | 11286 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
1aa9b957 | 11287 | INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); |
4d5c5d0f | 11288 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 11289 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 11290 | |
5550af4d SY |
11291 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
11292 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
11293 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
11294 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
11295 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 11296 | |
038f8c11 | 11297 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 11298 | mutex_init(&kvm->arch.apic_map_lock); |
8228c77d | 11299 | raw_spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
d828199e | 11300 | |
8171cd68 | 11301 | kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); |
d828199e | 11302 | pvclock_update_vm_gtod_copy(kvm); |
53f658b3 | 11303 | |
6fbbde9a DS |
11304 | kvm->arch.guest_can_read_msr_platform_info = true; |
11305 | ||
3c86c0d3 VP |
11306 | #if IS_ENABLED(CONFIG_HYPERV) |
11307 | spin_lock_init(&kvm->arch.hv_root_tdp_lock); | |
11308 | kvm->arch.hv_root_tdp = INVALID_PAGE; | |
11309 | #endif | |
11310 | ||
7e44e449 | 11311 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 11312 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 11313 | |
4651fc56 | 11314 | kvm_apicv_init(kvm); |
cbc0236a | 11315 | kvm_hv_init_vm(kvm); |
13d268ca | 11316 | kvm_mmu_init_vm(kvm); |
319afe68 | 11317 | kvm_xen_init_vm(kvm); |
0eb05bf2 | 11318 | |
b3646477 | 11319 | return static_call(kvm_x86_vm_init)(kvm); |
d19a9cd2 ZX |
11320 | } |
11321 | ||
1aa9b957 JS |
11322 | int kvm_arch_post_init_vm(struct kvm *kvm) |
11323 | { | |
11324 | return kvm_mmu_post_init_vm(kvm); | |
11325 | } | |
11326 | ||
d19a9cd2 ZX |
11327 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
11328 | { | |
ec7660cc | 11329 | vcpu_load(vcpu); |
d19a9cd2 ZX |
11330 | kvm_mmu_unload(vcpu); |
11331 | vcpu_put(vcpu); | |
11332 | } | |
11333 | ||
11334 | static void kvm_free_vcpus(struct kvm *kvm) | |
11335 | { | |
11336 | unsigned int i; | |
988a2cae | 11337 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
11338 | |
11339 | /* | |
11340 | * Unpin any mmu pages first. | |
11341 | */ | |
af585b92 GN |
11342 | kvm_for_each_vcpu(i, vcpu, kvm) { |
11343 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 11344 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 11345 | } |
988a2cae | 11346 | kvm_for_each_vcpu(i, vcpu, kvm) |
4543bdc0 | 11347 | kvm_vcpu_destroy(vcpu); |
988a2cae GN |
11348 | |
11349 | mutex_lock(&kvm->lock); | |
11350 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
11351 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 11352 | |
988a2cae GN |
11353 | atomic_set(&kvm->online_vcpus, 0); |
11354 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
11355 | } |
11356 | ||
ad8ba2cd SY |
11357 | void kvm_arch_sync_events(struct kvm *kvm) |
11358 | { | |
332967a3 | 11359 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 11360 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 11361 | kvm_free_pit(kvm); |
ad8ba2cd SY |
11362 | } |
11363 | ||
ff5a983c PX |
11364 | #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) |
11365 | ||
11366 | /** | |
11367 | * __x86_set_memory_region: Setup KVM internal memory slot | |
11368 | * | |
11369 | * @kvm: the kvm pointer to the VM. | |
11370 | * @id: the slot ID to setup. | |
11371 | * @gpa: the GPA to install the slot (unused when @size == 0). | |
11372 | * @size: the size of the slot. Set to zero to uninstall a slot. | |
11373 | * | |
11374 | * This function helps to setup a KVM internal memory slot. Specify | |
11375 | * @size > 0 to install a new slot, while @size == 0 to uninstall a | |
11376 | * slot. The return code can be one of the following: | |
11377 | * | |
11378 | * HVA: on success (uninstall will return a bogus HVA) | |
11379 | * -errno: on error | |
11380 | * | |
11381 | * The caller should always use IS_ERR() to check the return value | |
11382 | * before use. Note, the KVM internal memory slots are guaranteed to | |
11383 | * remain valid and unchanged until the VM is destroyed, i.e., the | |
11384 | * GPA->HVA translation will not change. However, the HVA is a user | |
11385 | * address, i.e. its accessibility is not guaranteed, and must be | |
11386 | * accessed via __copy_{to,from}_user(). | |
11387 | */ | |
11388 | void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, | |
11389 | u32 size) | |
9da0e4d5 PB |
11390 | { |
11391 | int i, r; | |
3f649ab7 | 11392 | unsigned long hva, old_npages; |
f0d648bd | 11393 | struct kvm_memslots *slots = kvm_memslots(kvm); |
0577d1ab | 11394 | struct kvm_memory_slot *slot; |
9da0e4d5 PB |
11395 | |
11396 | /* Called with kvm->slots_lock held. */ | |
1d8007bd | 11397 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
ff5a983c | 11398 | return ERR_PTR_USR(-EINVAL); |
9da0e4d5 | 11399 | |
f0d648bd PB |
11400 | slot = id_to_memslot(slots, id); |
11401 | if (size) { | |
0577d1ab | 11402 | if (slot && slot->npages) |
ff5a983c | 11403 | return ERR_PTR_USR(-EEXIST); |
f0d648bd PB |
11404 | |
11405 | /* | |
11406 | * MAP_SHARED to prevent internal slot pages from being moved | |
11407 | * by fork()/COW. | |
11408 | */ | |
11409 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
11410 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
11411 | if (IS_ERR((void *)hva)) | |
ff5a983c | 11412 | return (void __user *)hva; |
f0d648bd | 11413 | } else { |
0577d1ab | 11414 | if (!slot || !slot->npages) |
46914534 | 11415 | return NULL; |
f0d648bd | 11416 | |
0577d1ab | 11417 | old_npages = slot->npages; |
b66f9bab | 11418 | hva = slot->userspace_addr; |
f0d648bd PB |
11419 | } |
11420 | ||
9da0e4d5 | 11421 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 11422 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 11423 | |
1d8007bd PB |
11424 | m.slot = id | (i << 16); |
11425 | m.flags = 0; | |
11426 | m.guest_phys_addr = gpa; | |
f0d648bd | 11427 | m.userspace_addr = hva; |
1d8007bd | 11428 | m.memory_size = size; |
9da0e4d5 PB |
11429 | r = __kvm_set_memory_region(kvm, &m); |
11430 | if (r < 0) | |
ff5a983c | 11431 | return ERR_PTR_USR(r); |
9da0e4d5 PB |
11432 | } |
11433 | ||
103c763c | 11434 | if (!size) |
0577d1ab | 11435 | vm_munmap(hva, old_npages * PAGE_SIZE); |
f0d648bd | 11436 | |
ff5a983c | 11437 | return (void __user *)hva; |
9da0e4d5 PB |
11438 | } |
11439 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
11440 | ||
1aa9b957 JS |
11441 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
11442 | { | |
11443 | kvm_mmu_pre_destroy_vm(kvm); | |
11444 | } | |
11445 | ||
d19a9cd2 ZX |
11446 | void kvm_arch_destroy_vm(struct kvm *kvm) |
11447 | { | |
27469d29 AH |
11448 | if (current->mm == kvm->mm) { |
11449 | /* | |
11450 | * Free memory regions allocated on behalf of userspace, | |
11451 | * unless the the memory map has changed due to process exit | |
11452 | * or fd copying. | |
11453 | */ | |
6a3c623b PX |
11454 | mutex_lock(&kvm->slots_lock); |
11455 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
11456 | 0, 0); | |
11457 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
11458 | 0, 0); | |
11459 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
11460 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 11461 | } |
b3646477 | 11462 | static_call_cond(kvm_x86_vm_destroy)(kvm); |
b318e8de | 11463 | kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); |
c761159c PX |
11464 | kvm_pic_destroy(kvm); |
11465 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 11466 | kvm_free_vcpus(kvm); |
af1bae54 | 11467 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 11468 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 11469 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 11470 | kvm_page_track_cleanup(kvm); |
7d6bbebb | 11471 | kvm_xen_destroy_vm(kvm); |
cbc0236a | 11472 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 11473 | } |
0de10343 | 11474 | |
c9b929b3 | 11475 | static void memslot_rmap_free(struct kvm_memory_slot *slot) |
db3fe4eb TY |
11476 | { |
11477 | int i; | |
11478 | ||
d89cc617 | 11479 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
11480 | kvfree(slot->arch.rmap[i]); |
11481 | slot->arch.rmap[i] = NULL; | |
c9b929b3 BG |
11482 | } |
11483 | } | |
e96c81ee | 11484 | |
c9b929b3 BG |
11485 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
11486 | { | |
11487 | int i; | |
11488 | ||
11489 | memslot_rmap_free(slot); | |
d89cc617 | 11490 | |
c9b929b3 | 11491 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
11492 | kvfree(slot->arch.lpage_info[i - 1]); |
11493 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb | 11494 | } |
21ebbeda | 11495 | |
e96c81ee | 11496 | kvm_page_track_free_memslot(slot); |
db3fe4eb TY |
11497 | } |
11498 | ||
56dd1019 BG |
11499 | static int memslot_rmap_alloc(struct kvm_memory_slot *slot, |
11500 | unsigned long npages) | |
11501 | { | |
11502 | const int sz = sizeof(*slot->arch.rmap[0]); | |
11503 | int i; | |
11504 | ||
11505 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { | |
11506 | int level = i + 1; | |
4139b197 | 11507 | int lpages = __kvm_mmu_slot_lpages(slot, npages, level); |
56dd1019 | 11508 | |
fa13843d PB |
11509 | if (slot->arch.rmap[i]) |
11510 | continue; | |
d501f747 | 11511 | |
56dd1019 BG |
11512 | slot->arch.rmap[i] = kvcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); |
11513 | if (!slot->arch.rmap[i]) { | |
11514 | memslot_rmap_free(slot); | |
11515 | return -ENOMEM; | |
11516 | } | |
11517 | } | |
11518 | ||
11519 | return 0; | |
11520 | } | |
11521 | ||
d501f747 BG |
11522 | int alloc_all_memslots_rmaps(struct kvm *kvm) |
11523 | { | |
11524 | struct kvm_memslots *slots; | |
11525 | struct kvm_memory_slot *slot; | |
11526 | int r, i; | |
11527 | ||
11528 | /* | |
11529 | * Check if memslots alreday have rmaps early before acquiring | |
11530 | * the slots_arch_lock below. | |
11531 | */ | |
11532 | if (kvm_memslots_have_rmaps(kvm)) | |
11533 | return 0; | |
11534 | ||
11535 | mutex_lock(&kvm->slots_arch_lock); | |
11536 | ||
11537 | /* | |
11538 | * Read memslots_have_rmaps again, under the slots arch lock, | |
11539 | * before allocating the rmaps | |
11540 | */ | |
11541 | if (kvm_memslots_have_rmaps(kvm)) { | |
11542 | mutex_unlock(&kvm->slots_arch_lock); | |
11543 | return 0; | |
11544 | } | |
11545 | ||
11546 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { | |
11547 | slots = __kvm_memslots(kvm, i); | |
11548 | kvm_for_each_memslot(slot, slots) { | |
11549 | r = memslot_rmap_alloc(slot, slot->npages); | |
11550 | if (r) { | |
11551 | mutex_unlock(&kvm->slots_arch_lock); | |
11552 | return r; | |
11553 | } | |
11554 | } | |
11555 | } | |
11556 | ||
11557 | /* | |
11558 | * Ensure that memslots_have_rmaps becomes true strictly after | |
11559 | * all the rmap pointers are set. | |
11560 | */ | |
11561 | smp_store_release(&kvm->arch.memslots_have_rmaps, true); | |
11562 | mutex_unlock(&kvm->slots_arch_lock); | |
11563 | return 0; | |
11564 | } | |
11565 | ||
a2557408 BG |
11566 | static int kvm_alloc_memslot_metadata(struct kvm *kvm, |
11567 | struct kvm_memory_slot *slot, | |
0dab98b7 | 11568 | unsigned long npages) |
db3fe4eb | 11569 | { |
56dd1019 | 11570 | int i, r; |
db3fe4eb | 11571 | |
edd4fa37 SC |
11572 | /* |
11573 | * Clear out the previous array pointers for the KVM_MR_MOVE case. The | |
11574 | * old arrays will be freed by __kvm_set_memory_region() if installing | |
11575 | * the new memslot is successful. | |
11576 | */ | |
11577 | memset(&slot->arch, 0, sizeof(slot->arch)); | |
11578 | ||
e2209710 | 11579 | if (kvm_memslots_have_rmaps(kvm)) { |
a2557408 BG |
11580 | r = memslot_rmap_alloc(slot, npages); |
11581 | if (r) | |
11582 | return r; | |
11583 | } | |
56dd1019 BG |
11584 | |
11585 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { | |
92f94f1e | 11586 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
11587 | unsigned long ugfn; |
11588 | int lpages; | |
d89cc617 | 11589 | int level = i + 1; |
db3fe4eb | 11590 | |
4139b197 | 11591 | lpages = __kvm_mmu_slot_lpages(slot, npages, level); |
db3fe4eb | 11592 | |
254272ce | 11593 | linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 11594 | if (!linfo) |
db3fe4eb TY |
11595 | goto out_free; |
11596 | ||
92f94f1e XG |
11597 | slot->arch.lpage_info[i - 1] = linfo; |
11598 | ||
db3fe4eb | 11599 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 11600 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 11601 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 11602 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
11603 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
11604 | /* | |
11605 | * If the gfn and userspace address are not aligned wrt each | |
600087b6 | 11606 | * other, disable large page support for this slot. |
db3fe4eb | 11607 | */ |
600087b6 | 11608 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { |
db3fe4eb TY |
11609 | unsigned long j; |
11610 | ||
11611 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 11612 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
11613 | } |
11614 | } | |
11615 | ||
21ebbeda XG |
11616 | if (kvm_page_track_create_memslot(slot, npages)) |
11617 | goto out_free; | |
11618 | ||
db3fe4eb TY |
11619 | return 0; |
11620 | ||
11621 | out_free: | |
c9b929b3 | 11622 | memslot_rmap_free(slot); |
d89cc617 | 11623 | |
c9b929b3 | 11624 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 11625 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 11626 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
11627 | } |
11628 | return -ENOMEM; | |
11629 | } | |
11630 | ||
15248258 | 11631 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 11632 | { |
91724814 BO |
11633 | struct kvm_vcpu *vcpu; |
11634 | int i; | |
11635 | ||
e6dff7d1 TY |
11636 | /* |
11637 | * memslots->generation has been incremented. | |
11638 | * mmio generation may have reached its maximum value. | |
11639 | */ | |
15248258 | 11640 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
11641 | |
11642 | /* Force re-initialization of steal_time cache */ | |
11643 | kvm_for_each_vcpu(i, vcpu, kvm) | |
11644 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
11645 | } |
11646 | ||
f7784b8e MT |
11647 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
11648 | struct kvm_memory_slot *memslot, | |
09170a49 | 11649 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 11650 | enum kvm_mr_change change) |
0de10343 | 11651 | { |
0dab98b7 | 11652 | if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) |
a2557408 | 11653 | return kvm_alloc_memslot_metadata(kvm, memslot, |
0dab98b7 | 11654 | mem->memory_size >> PAGE_SHIFT); |
f7784b8e MT |
11655 | return 0; |
11656 | } | |
11657 | ||
a85863c2 MS |
11658 | |
11659 | static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) | |
11660 | { | |
11661 | struct kvm_arch *ka = &kvm->arch; | |
11662 | ||
11663 | if (!kvm_x86_ops.cpu_dirty_log_size) | |
11664 | return; | |
11665 | ||
11666 | if ((enable && ++ka->cpu_dirty_logging_count == 1) || | |
11667 | (!enable && --ka->cpu_dirty_logging_count == 0)) | |
11668 | kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); | |
11669 | ||
11670 | WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); | |
11671 | } | |
11672 | ||
88178fd4 | 11673 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
3741679b | 11674 | struct kvm_memory_slot *old, |
269e9552 | 11675 | const struct kvm_memory_slot *new, |
3741679b | 11676 | enum kvm_mr_change change) |
88178fd4 | 11677 | { |
a85863c2 MS |
11678 | bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES; |
11679 | ||
3741679b | 11680 | /* |
a85863c2 MS |
11681 | * Update CPU dirty logging if dirty logging is being toggled. This |
11682 | * applies to all operations. | |
3741679b | 11683 | */ |
a85863c2 MS |
11684 | if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES) |
11685 | kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); | |
88178fd4 KH |
11686 | |
11687 | /* | |
a85863c2 | 11688 | * Nothing more to do for RO slots (which can't be dirtied and can't be |
b6e16ae5 | 11689 | * made writable) or CREATE/MOVE/DELETE of a slot. |
88178fd4 | 11690 | * |
b6e16ae5 | 11691 | * For a memslot with dirty logging disabled: |
3741679b AY |
11692 | * CREATE: No dirty mappings will already exist. |
11693 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
11694 | * kvm_arch_flush_shadow_memslot() | |
b6e16ae5 SC |
11695 | * |
11696 | * For a memslot with dirty logging enabled: | |
11697 | * CREATE: No shadow pages exist, thus nothing to write-protect | |
11698 | * and no dirty bits to clear. | |
11699 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
11700 | * kvm_arch_flush_shadow_memslot(). | |
3741679b | 11701 | */ |
3741679b | 11702 | if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) |
88178fd4 | 11703 | return; |
3741679b AY |
11704 | |
11705 | /* | |
52f46079 SC |
11706 | * READONLY and non-flags changes were filtered out above, and the only |
11707 | * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty | |
11708 | * logging isn't being toggled on or off. | |
88178fd4 | 11709 | */ |
52f46079 SC |
11710 | if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES))) |
11711 | return; | |
11712 | ||
b6e16ae5 SC |
11713 | if (!log_dirty_pages) { |
11714 | /* | |
11715 | * Dirty logging tracks sptes in 4k granularity, meaning that | |
11716 | * large sptes have to be split. If live migration succeeds, | |
11717 | * the guest in the source machine will be destroyed and large | |
11718 | * sptes will be created in the destination. However, if the | |
11719 | * guest continues to run in the source machine (for example if | |
11720 | * live migration fails), small sptes will remain around and | |
11721 | * cause bad performance. | |
11722 | * | |
11723 | * Scan sptes if dirty logging has been stopped, dropping those | |
11724 | * which can be collapsed into a single large-page spte. Later | |
11725 | * page faults will create the large-page sptes. | |
11726 | */ | |
3741679b | 11727 | kvm_mmu_zap_collapsible_sptes(kvm, new); |
b6e16ae5 | 11728 | } else { |
89212919 KZ |
11729 | /* |
11730 | * Initially-all-set does not require write protecting any page, | |
11731 | * because they're all assumed to be dirty. | |
11732 | */ | |
11733 | if (kvm_dirty_log_manual_protect_and_init_set(kvm)) | |
11734 | return; | |
a1419f8b | 11735 | |
a018eba5 | 11736 | if (kvm_x86_ops.cpu_dirty_log_size) { |
89212919 KZ |
11737 | kvm_mmu_slot_leaf_clear_dirty(kvm, new); |
11738 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); | |
11739 | } else { | |
11740 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); | |
3c9bd400 | 11741 | } |
88178fd4 KH |
11742 | } |
11743 | } | |
11744 | ||
f7784b8e | 11745 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 11746 | const struct kvm_userspace_memory_region *mem, |
9d4c197c | 11747 | struct kvm_memory_slot *old, |
f36f3f28 | 11748 | const struct kvm_memory_slot *new, |
8482644a | 11749 | enum kvm_mr_change change) |
f7784b8e | 11750 | { |
48c0e4e9 | 11751 | if (!kvm->arch.n_requested_mmu_pages) |
4d66623c WY |
11752 | kvm_mmu_change_mmu_pages(kvm, |
11753 | kvm_mmu_calculate_default_mmu_pages(kvm)); | |
1c91cad4 | 11754 | |
269e9552 | 11755 | kvm_mmu_slot_apply_flags(kvm, old, new, change); |
21198846 SC |
11756 | |
11757 | /* Free the arrays associated with the old memslot. */ | |
11758 | if (change == KVM_MR_MOVE) | |
e96c81ee | 11759 | kvm_arch_free_memslot(kvm, old); |
0de10343 | 11760 | } |
1d737c8a | 11761 | |
2df72e9b | 11762 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 11763 | { |
7390de1e | 11764 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
11765 | } |
11766 | ||
2df72e9b MT |
11767 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
11768 | struct kvm_memory_slot *slot) | |
11769 | { | |
ae7cd873 | 11770 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
11771 | } |
11772 | ||
e6c67d8c LA |
11773 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
11774 | { | |
11775 | return (is_guest_mode(vcpu) && | |
afaf0b2f | 11776 | kvm_x86_ops.guest_apic_has_interrupt && |
b3646477 | 11777 | static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); |
e6c67d8c LA |
11778 | } |
11779 | ||
5d9bc648 PB |
11780 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
11781 | { | |
11782 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
11783 | return true; | |
11784 | ||
11785 | if (kvm_apic_has_events(vcpu)) | |
11786 | return true; | |
11787 | ||
11788 | if (vcpu->arch.pv.pv_unhalted) | |
11789 | return true; | |
11790 | ||
a5f01f8e WL |
11791 | if (vcpu->arch.exception.pending) |
11792 | return true; | |
11793 | ||
47a66eed Z |
11794 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
11795 | (vcpu->arch.nmi_pending && | |
b3646477 | 11796 | static_call(kvm_x86_nmi_allowed)(vcpu, false))) |
5d9bc648 PB |
11797 | return true; |
11798 | ||
47a66eed | 11799 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
a9fa7cb6 | 11800 | (vcpu->arch.smi_pending && |
b3646477 | 11801 | static_call(kvm_x86_smi_allowed)(vcpu, false))) |
73917739 PB |
11802 | return true; |
11803 | ||
5d9bc648 | 11804 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
11805 | (kvm_cpu_has_interrupt(vcpu) || |
11806 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
11807 | return true; |
11808 | ||
1f4b34f8 AS |
11809 | if (kvm_hv_has_stimer_pending(vcpu)) |
11810 | return true; | |
11811 | ||
d2060bd4 SC |
11812 | if (is_guest_mode(vcpu) && |
11813 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
11814 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
11815 | return true; | |
11816 | ||
5d9bc648 PB |
11817 | return false; |
11818 | } | |
11819 | ||
1d737c8a ZX |
11820 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
11821 | { | |
5d9bc648 | 11822 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 11823 | } |
5736199a | 11824 | |
10dbdf98 | 11825 | bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) |
17e433b5 | 11826 | { |
b3646477 | 11827 | if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) |
52acd22f WL |
11828 | return true; |
11829 | ||
11830 | return false; | |
11831 | } | |
11832 | ||
17e433b5 WL |
11833 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
11834 | { | |
11835 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
11836 | return true; | |
11837 | ||
11838 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
11839 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
11840 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
11841 | return true; | |
11842 | ||
10dbdf98 | 11843 | return kvm_arch_dy_has_pending_interrupt(vcpu); |
17e433b5 WL |
11844 | } |
11845 | ||
199b5763 LM |
11846 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
11847 | { | |
b86bb11e WL |
11848 | if (vcpu->arch.guest_state_protected) |
11849 | return true; | |
11850 | ||
de63ad4c | 11851 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
11852 | } |
11853 | ||
b6d33834 | 11854 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 11855 | { |
b6d33834 | 11856 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 11857 | } |
78646121 GN |
11858 | |
11859 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
11860 | { | |
b3646477 | 11861 | return static_call(kvm_x86_interrupt_allowed)(vcpu, false); |
78646121 | 11862 | } |
229456fc | 11863 | |
82b32774 | 11864 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 11865 | { |
7ed9abfe TL |
11866 | /* Can't read the RIP when guest state is protected, just return 0 */ |
11867 | if (vcpu->arch.guest_state_protected) | |
11868 | return 0; | |
11869 | ||
82b32774 NA |
11870 | if (is_64_bit_mode(vcpu)) |
11871 | return kvm_rip_read(vcpu); | |
11872 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
11873 | kvm_rip_read(vcpu)); | |
11874 | } | |
11875 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 11876 | |
82b32774 NA |
11877 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
11878 | { | |
11879 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
11880 | } |
11881 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
11882 | ||
94fe45da JK |
11883 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
11884 | { | |
11885 | unsigned long rflags; | |
11886 | ||
b3646477 | 11887 | rflags = static_call(kvm_x86_get_rflags)(vcpu); |
94fe45da | 11888 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
c310bac5 | 11889 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
11890 | return rflags; |
11891 | } | |
11892 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
11893 | ||
6addfc42 | 11894 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
11895 | { |
11896 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 11897 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 11898 | rflags |= X86_EFLAGS_TF; |
b3646477 | 11899 | static_call(kvm_x86_set_rflags)(vcpu, rflags); |
6addfc42 PB |
11900 | } |
11901 | ||
11902 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
11903 | { | |
11904 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 11905 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
11906 | } |
11907 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
11908 | ||
56028d08 GN |
11909 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
11910 | { | |
11911 | int r; | |
11912 | ||
44dd3ffa | 11913 | if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || |
f2e10669 | 11914 | work->wakeup_all) |
56028d08 GN |
11915 | return; |
11916 | ||
11917 | r = kvm_mmu_reload(vcpu); | |
11918 | if (unlikely(r)) | |
11919 | return; | |
11920 | ||
44dd3ffa | 11921 | if (!vcpu->arch.mmu->direct_map && |
d8dd54e0 | 11922 | work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) |
fb67e14f XG |
11923 | return; |
11924 | ||
7a02674d | 11925 | kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); |
56028d08 GN |
11926 | } |
11927 | ||
af585b92 GN |
11928 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
11929 | { | |
dd03bcaa PX |
11930 | BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); |
11931 | ||
af585b92 GN |
11932 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); |
11933 | } | |
11934 | ||
11935 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
11936 | { | |
dd03bcaa | 11937 | return (key + 1) & (ASYNC_PF_PER_VCPU - 1); |
af585b92 GN |
11938 | } |
11939 | ||
11940 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11941 | { | |
11942 | u32 key = kvm_async_pf_hash_fn(gfn); | |
11943 | ||
11944 | while (vcpu->arch.apf.gfns[key] != ~0) | |
11945 | key = kvm_async_pf_next_probe(key); | |
11946 | ||
11947 | vcpu->arch.apf.gfns[key] = gfn; | |
11948 | } | |
11949 | ||
11950 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11951 | { | |
11952 | int i; | |
11953 | u32 key = kvm_async_pf_hash_fn(gfn); | |
11954 | ||
dd03bcaa | 11955 | for (i = 0; i < ASYNC_PF_PER_VCPU && |
c7d28c24 XG |
11956 | (vcpu->arch.apf.gfns[key] != gfn && |
11957 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
11958 | key = kvm_async_pf_next_probe(key); |
11959 | ||
11960 | return key; | |
11961 | } | |
11962 | ||
11963 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11964 | { | |
11965 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
11966 | } | |
11967 | ||
11968 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11969 | { | |
11970 | u32 i, j, k; | |
11971 | ||
11972 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
0fd46044 PX |
11973 | |
11974 | if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) | |
11975 | return; | |
11976 | ||
af585b92 GN |
11977 | while (true) { |
11978 | vcpu->arch.apf.gfns[i] = ~0; | |
11979 | do { | |
11980 | j = kvm_async_pf_next_probe(j); | |
11981 | if (vcpu->arch.apf.gfns[j] == ~0) | |
11982 | return; | |
11983 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
11984 | /* | |
11985 | * k lies cyclically in ]i,j] | |
11986 | * | i.k.j | | |
11987 | * |....j i.k.| or |.k..j i...| | |
11988 | */ | |
11989 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
11990 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
11991 | i = j; | |
11992 | } | |
11993 | } | |
11994 | ||
68fd66f1 | 11995 | static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) |
7c90705b | 11996 | { |
68fd66f1 VK |
11997 | u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; |
11998 | ||
11999 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, | |
12000 | sizeof(reason)); | |
12001 | } | |
12002 | ||
12003 | static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) | |
12004 | { | |
2635b5c4 | 12005 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); |
4e335d9e | 12006 | |
2635b5c4 VK |
12007 | return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, |
12008 | &token, offset, sizeof(token)); | |
12009 | } | |
12010 | ||
12011 | static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) | |
12012 | { | |
12013 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); | |
12014 | u32 val; | |
12015 | ||
12016 | if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, | |
12017 | &val, offset, sizeof(val))) | |
12018 | return false; | |
12019 | ||
12020 | return !val; | |
7c90705b GN |
12021 | } |
12022 | ||
1dfdb45e PB |
12023 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
12024 | { | |
12025 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) | |
12026 | return false; | |
12027 | ||
2635b5c4 | 12028 | if (!kvm_pv_async_pf_enabled(vcpu) || |
b3646477 | 12029 | (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) |
1dfdb45e PB |
12030 | return false; |
12031 | ||
12032 | return true; | |
12033 | } | |
12034 | ||
12035 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
12036 | { | |
12037 | if (unlikely(!lapic_in_kernel(vcpu) || | |
12038 | kvm_event_needs_reinjection(vcpu) || | |
12039 | vcpu->arch.exception.pending)) | |
12040 | return false; | |
12041 | ||
12042 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
12043 | return false; | |
12044 | ||
12045 | /* | |
12046 | * If interrupts are off we cannot even use an artificial | |
12047 | * halt state. | |
12048 | */ | |
c300ab9f | 12049 | return kvm_arch_interrupt_allowed(vcpu); |
1dfdb45e PB |
12050 | } |
12051 | ||
2a18b7e7 | 12052 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
12053 | struct kvm_async_pf *work) |
12054 | { | |
6389ee94 AK |
12055 | struct x86_exception fault; |
12056 | ||
736c291c | 12057 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 12058 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 12059 | |
1dfdb45e | 12060 | if (kvm_can_deliver_async_pf(vcpu) && |
68fd66f1 | 12061 | !apf_put_user_notpresent(vcpu)) { |
6389ee94 AK |
12062 | fault.vector = PF_VECTOR; |
12063 | fault.error_code_valid = true; | |
12064 | fault.error_code = 0; | |
12065 | fault.nested_page_fault = false; | |
12066 | fault.address = work->arch.token; | |
adfe20fb | 12067 | fault.async_page_fault = true; |
6389ee94 | 12068 | kvm_inject_page_fault(vcpu, &fault); |
2a18b7e7 | 12069 | return true; |
1dfdb45e PB |
12070 | } else { |
12071 | /* | |
12072 | * It is not possible to deliver a paravirtualized asynchronous | |
12073 | * page fault, but putting the guest in an artificial halt state | |
12074 | * can be beneficial nevertheless: if an interrupt arrives, we | |
12075 | * can deliver it timely and perhaps the guest will schedule | |
12076 | * another process. When the instruction that triggered a page | |
12077 | * fault is retried, hopefully the page will be ready in the host. | |
12078 | */ | |
12079 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2a18b7e7 | 12080 | return false; |
7c90705b | 12081 | } |
af585b92 GN |
12082 | } |
12083 | ||
12084 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
12085 | struct kvm_async_pf *work) | |
12086 | { | |
2635b5c4 VK |
12087 | struct kvm_lapic_irq irq = { |
12088 | .delivery_mode = APIC_DM_FIXED, | |
12089 | .vector = vcpu->arch.apf.vec | |
12090 | }; | |
6389ee94 | 12091 | |
f2e10669 | 12092 | if (work->wakeup_all) |
7c90705b GN |
12093 | work->arch.token = ~0; /* broadcast wakeup */ |
12094 | else | |
12095 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 12096 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 12097 | |
2a18b7e7 VK |
12098 | if ((work->wakeup_all || work->notpresent_injected) && |
12099 | kvm_pv_async_pf_enabled(vcpu) && | |
557a961a VK |
12100 | !apf_put_user_ready(vcpu, work->arch.token)) { |
12101 | vcpu->arch.apf.pageready_pending = true; | |
2635b5c4 | 12102 | kvm_apic_set_irq(vcpu, &irq, NULL); |
557a961a | 12103 | } |
2635b5c4 | 12104 | |
e6d53e3b | 12105 | vcpu->arch.apf.halted = false; |
a4fa1635 | 12106 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
12107 | } |
12108 | ||
557a961a VK |
12109 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) |
12110 | { | |
12111 | kvm_make_request(KVM_REQ_APF_READY, vcpu); | |
12112 | if (!vcpu->arch.apf.pageready_pending) | |
12113 | kvm_vcpu_kick(vcpu); | |
12114 | } | |
12115 | ||
7c0ade6c | 12116 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) |
7c90705b | 12117 | { |
2635b5c4 | 12118 | if (!kvm_pv_async_pf_enabled(vcpu)) |
7c90705b GN |
12119 | return true; |
12120 | else | |
2f15d027 | 12121 | return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); |
af585b92 GN |
12122 | } |
12123 | ||
5544eb9b PB |
12124 | void kvm_arch_start_assignment(struct kvm *kvm) |
12125 | { | |
57ab8794 MT |
12126 | if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) |
12127 | static_call_cond(kvm_x86_start_assignment)(kvm); | |
5544eb9b PB |
12128 | } |
12129 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
12130 | ||
12131 | void kvm_arch_end_assignment(struct kvm *kvm) | |
12132 | { | |
12133 | atomic_dec(&kvm->arch.assigned_device_count); | |
12134 | } | |
12135 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
12136 | ||
12137 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
12138 | { | |
12139 | return atomic_read(&kvm->arch.assigned_device_count); | |
12140 | } | |
12141 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
12142 | ||
e0f0bbc5 AW |
12143 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
12144 | { | |
12145 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
12146 | } | |
12147 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
12148 | ||
12149 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
12150 | { | |
12151 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
12152 | } | |
12153 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
12154 | ||
12155 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
12156 | { | |
12157 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
12158 | } | |
12159 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
12160 | ||
14717e20 AW |
12161 | bool kvm_arch_has_irq_bypass(void) |
12162 | { | |
92735b1b | 12163 | return true; |
14717e20 AW |
12164 | } |
12165 | ||
87276880 FW |
12166 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
12167 | struct irq_bypass_producer *prod) | |
12168 | { | |
12169 | struct kvm_kernel_irqfd *irqfd = | |
12170 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
2edd9cb7 | 12171 | int ret; |
87276880 | 12172 | |
14717e20 | 12173 | irqfd->producer = prod; |
2edd9cb7 | 12174 | kvm_arch_start_assignment(irqfd->kvm); |
b3646477 | 12175 | ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, |
2edd9cb7 ZL |
12176 | prod->irq, irqfd->gsi, 1); |
12177 | ||
12178 | if (ret) | |
12179 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 | 12180 | |
2edd9cb7 | 12181 | return ret; |
87276880 FW |
12182 | } |
12183 | ||
12184 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
12185 | struct irq_bypass_producer *prod) | |
12186 | { | |
12187 | int ret; | |
12188 | struct kvm_kernel_irqfd *irqfd = | |
12189 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
12190 | ||
87276880 FW |
12191 | WARN_ON(irqfd->producer != prod); |
12192 | irqfd->producer = NULL; | |
12193 | ||
12194 | /* | |
12195 | * When producer of consumer is unregistered, we change back to | |
12196 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 12197 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
12198 | * int this case doesn't want to receive the interrupts. |
12199 | */ | |
b3646477 | 12200 | ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); |
87276880 FW |
12201 | if (ret) |
12202 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
12203 | " fails: %d\n", irqfd->consumer.token, ret); | |
2edd9cb7 ZL |
12204 | |
12205 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 FW |
12206 | } |
12207 | ||
12208 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
12209 | uint32_t guest_irq, bool set) | |
12210 | { | |
b3646477 | 12211 | return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); |
87276880 FW |
12212 | } |
12213 | ||
52004014 FW |
12214 | bool kvm_vector_hashing_enabled(void) |
12215 | { | |
12216 | return vector_hashing; | |
12217 | } | |
52004014 | 12218 | |
2d5ba19b MT |
12219 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
12220 | { | |
12221 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
12222 | } | |
12223 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
12224 | ||
841c2be0 ML |
12225 | |
12226 | int kvm_spec_ctrl_test_value(u64 value) | |
6441fa61 | 12227 | { |
841c2be0 ML |
12228 | /* |
12229 | * test that setting IA32_SPEC_CTRL to given value | |
12230 | * is allowed by the host processor | |
12231 | */ | |
6441fa61 | 12232 | |
841c2be0 ML |
12233 | u64 saved_value; |
12234 | unsigned long flags; | |
12235 | int ret = 0; | |
6441fa61 | 12236 | |
841c2be0 | 12237 | local_irq_save(flags); |
6441fa61 | 12238 | |
841c2be0 ML |
12239 | if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) |
12240 | ret = 1; | |
12241 | else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) | |
12242 | ret = 1; | |
12243 | else | |
12244 | wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); | |
6441fa61 | 12245 | |
841c2be0 | 12246 | local_irq_restore(flags); |
6441fa61 | 12247 | |
841c2be0 | 12248 | return ret; |
6441fa61 | 12249 | } |
841c2be0 | 12250 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); |
2d5ba19b | 12251 | |
89786147 MG |
12252 | void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) |
12253 | { | |
12254 | struct x86_exception fault; | |
19cf4b7e PB |
12255 | u32 access = error_code & |
12256 | (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); | |
89786147 MG |
12257 | |
12258 | if (!(error_code & PFERR_PRESENT_MASK) || | |
19cf4b7e | 12259 | vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { |
89786147 MG |
12260 | /* |
12261 | * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page | |
12262 | * tables probably do not match the TLB. Just proceed | |
12263 | * with the error code that the processor gave. | |
12264 | */ | |
12265 | fault.vector = PF_VECTOR; | |
12266 | fault.error_code_valid = true; | |
12267 | fault.error_code = error_code; | |
12268 | fault.nested_page_fault = false; | |
12269 | fault.address = gva; | |
12270 | } | |
12271 | vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); | |
6441fa61 | 12272 | } |
89786147 | 12273 | EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); |
2d5ba19b | 12274 | |
3f3393b3 BM |
12275 | /* |
12276 | * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns | |
12277 | * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value | |
12278 | * indicates whether exit to userspace is needed. | |
12279 | */ | |
12280 | int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, | |
12281 | struct x86_exception *e) | |
12282 | { | |
12283 | if (r == X86EMUL_PROPAGATE_FAULT) { | |
12284 | kvm_inject_emulated_page_fault(vcpu, e); | |
12285 | return 1; | |
12286 | } | |
12287 | ||
12288 | /* | |
12289 | * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED | |
12290 | * while handling a VMX instruction KVM could've handled the request | |
12291 | * correctly by exiting to userspace and performing I/O but there | |
12292 | * doesn't seem to be a real use-case behind such requests, just return | |
12293 | * KVM_EXIT_INTERNAL_ERROR for now. | |
12294 | */ | |
12295 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
12296 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
12297 | vcpu->run->internal.ndata = 0; | |
12298 | ||
12299 | return 0; | |
12300 | } | |
12301 | EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); | |
12302 | ||
9715092f BM |
12303 | int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) |
12304 | { | |
12305 | bool pcid_enabled; | |
12306 | struct x86_exception e; | |
9715092f BM |
12307 | struct { |
12308 | u64 pcid; | |
12309 | u64 gla; | |
12310 | } operand; | |
12311 | int r; | |
12312 | ||
12313 | r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); | |
12314 | if (r != X86EMUL_CONTINUE) | |
12315 | return kvm_handle_memory_failure(vcpu, r, &e); | |
12316 | ||
12317 | if (operand.pcid >> 12 != 0) { | |
12318 | kvm_inject_gp(vcpu, 0); | |
12319 | return 1; | |
12320 | } | |
12321 | ||
12322 | pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); | |
12323 | ||
12324 | switch (type) { | |
12325 | case INVPCID_TYPE_INDIV_ADDR: | |
12326 | if ((!pcid_enabled && (operand.pcid != 0)) || | |
12327 | is_noncanonical_address(operand.gla, vcpu)) { | |
12328 | kvm_inject_gp(vcpu, 0); | |
12329 | return 1; | |
12330 | } | |
12331 | kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); | |
12332 | return kvm_skip_emulated_instruction(vcpu); | |
12333 | ||
12334 | case INVPCID_TYPE_SINGLE_CTXT: | |
12335 | if (!pcid_enabled && (operand.pcid != 0)) { | |
12336 | kvm_inject_gp(vcpu, 0); | |
12337 | return 1; | |
12338 | } | |
12339 | ||
21823fbd | 12340 | kvm_invalidate_pcid(vcpu, operand.pcid); |
9715092f BM |
12341 | return kvm_skip_emulated_instruction(vcpu); |
12342 | ||
12343 | case INVPCID_TYPE_ALL_NON_GLOBAL: | |
12344 | /* | |
12345 | * Currently, KVM doesn't mark global entries in the shadow | |
12346 | * page tables, so a non-global flush just degenerates to a | |
12347 | * global flush. If needed, we could optimize this later by | |
12348 | * keeping track of global entries in shadow page tables. | |
12349 | */ | |
12350 | ||
12351 | fallthrough; | |
12352 | case INVPCID_TYPE_ALL_INCL_GLOBAL: | |
28f28d45 | 12353 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); |
9715092f BM |
12354 | return kvm_skip_emulated_instruction(vcpu); |
12355 | ||
12356 | default: | |
12357 | BUG(); /* We have already checked above that type <= 3 */ | |
12358 | } | |
12359 | } | |
12360 | EXPORT_SYMBOL_GPL(kvm_handle_invpcid); | |
12361 | ||
8f423a80 TL |
12362 | static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) |
12363 | { | |
12364 | struct kvm_run *run = vcpu->run; | |
12365 | struct kvm_mmio_fragment *frag; | |
12366 | unsigned int len; | |
12367 | ||
12368 | BUG_ON(!vcpu->mmio_needed); | |
12369 | ||
12370 | /* Complete previous fragment */ | |
12371 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; | |
12372 | len = min(8u, frag->len); | |
12373 | if (!vcpu->mmio_is_write) | |
12374 | memcpy(frag->data, run->mmio.data, len); | |
12375 | ||
12376 | if (frag->len <= 8) { | |
12377 | /* Switch to the next fragment. */ | |
12378 | frag++; | |
12379 | vcpu->mmio_cur_fragment++; | |
12380 | } else { | |
12381 | /* Go forward to the next mmio piece. */ | |
12382 | frag->data += len; | |
12383 | frag->gpa += len; | |
12384 | frag->len -= len; | |
12385 | } | |
12386 | ||
12387 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { | |
12388 | vcpu->mmio_needed = 0; | |
12389 | ||
12390 | // VMG change, at this point, we're always done | |
12391 | // RIP has already been advanced | |
12392 | return 1; | |
12393 | } | |
12394 | ||
12395 | // More MMIO is needed | |
12396 | run->mmio.phys_addr = frag->gpa; | |
12397 | run->mmio.len = min(8u, frag->len); | |
12398 | run->mmio.is_write = vcpu->mmio_is_write; | |
12399 | if (run->mmio.is_write) | |
12400 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); | |
12401 | run->exit_reason = KVM_EXIT_MMIO; | |
12402 | ||
12403 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12404 | ||
12405 | return 0; | |
12406 | } | |
12407 | ||
12408 | int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
12409 | void *data) | |
12410 | { | |
12411 | int handled; | |
12412 | struct kvm_mmio_fragment *frag; | |
12413 | ||
12414 | if (!data) | |
12415 | return -EINVAL; | |
12416 | ||
12417 | handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
12418 | if (handled == bytes) | |
12419 | return 1; | |
12420 | ||
12421 | bytes -= handled; | |
12422 | gpa += handled; | |
12423 | data += handled; | |
12424 | ||
12425 | /*TODO: Check if need to increment number of frags */ | |
12426 | frag = vcpu->mmio_fragments; | |
12427 | vcpu->mmio_nr_fragments = 1; | |
12428 | frag->len = bytes; | |
12429 | frag->gpa = gpa; | |
12430 | frag->data = data; | |
12431 | ||
12432 | vcpu->mmio_needed = 1; | |
12433 | vcpu->mmio_cur_fragment = 0; | |
12434 | ||
12435 | vcpu->run->mmio.phys_addr = gpa; | |
12436 | vcpu->run->mmio.len = min(8u, frag->len); | |
12437 | vcpu->run->mmio.is_write = 1; | |
12438 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); | |
12439 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
12440 | ||
12441 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12442 | ||
12443 | return 0; | |
12444 | } | |
12445 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); | |
12446 | ||
12447 | int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
12448 | void *data) | |
12449 | { | |
12450 | int handled; | |
12451 | struct kvm_mmio_fragment *frag; | |
12452 | ||
12453 | if (!data) | |
12454 | return -EINVAL; | |
12455 | ||
12456 | handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
12457 | if (handled == bytes) | |
12458 | return 1; | |
12459 | ||
12460 | bytes -= handled; | |
12461 | gpa += handled; | |
12462 | data += handled; | |
12463 | ||
12464 | /*TODO: Check if need to increment number of frags */ | |
12465 | frag = vcpu->mmio_fragments; | |
12466 | vcpu->mmio_nr_fragments = 1; | |
12467 | frag->len = bytes; | |
12468 | frag->gpa = gpa; | |
12469 | frag->data = data; | |
12470 | ||
12471 | vcpu->mmio_needed = 1; | |
12472 | vcpu->mmio_cur_fragment = 0; | |
12473 | ||
12474 | vcpu->run->mmio.phys_addr = gpa; | |
12475 | vcpu->run->mmio.len = min(8u, frag->len); | |
12476 | vcpu->run->mmio.is_write = 0; | |
12477 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
12478 | ||
12479 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12480 | ||
12481 | return 0; | |
12482 | } | |
12483 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); | |
12484 | ||
7ed9abfe | 12485 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, |
95e16b47 PB |
12486 | unsigned int port); |
12487 | ||
12488 | static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu) | |
7ed9abfe | 12489 | { |
95e16b47 PB |
12490 | int size = vcpu->arch.pio.size; |
12491 | int port = vcpu->arch.pio.port; | |
12492 | ||
12493 | vcpu->arch.pio.count = 0; | |
12494 | if (vcpu->arch.sev_pio_count) | |
12495 | return kvm_sev_es_outs(vcpu, size, port); | |
12496 | return 1; | |
12497 | } | |
12498 | ||
12499 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, | |
12500 | unsigned int port) | |
12501 | { | |
12502 | for (;;) { | |
12503 | unsigned int count = | |
12504 | min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); | |
12505 | int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count); | |
12506 | ||
12507 | /* memcpy done already by emulator_pio_out. */ | |
12508 | vcpu->arch.sev_pio_count -= count; | |
12509 | vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; | |
12510 | if (!ret) | |
12511 | break; | |
7ed9abfe | 12512 | |
ea724ea4 | 12513 | /* Emulation done by the kernel. */ |
95e16b47 PB |
12514 | if (!vcpu->arch.sev_pio_count) |
12515 | return 1; | |
ea724ea4 | 12516 | } |
7ed9abfe | 12517 | |
95e16b47 | 12518 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs; |
7ed9abfe TL |
12519 | return 0; |
12520 | } | |
12521 | ||
95e16b47 PB |
12522 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, |
12523 | unsigned int port); | |
12524 | ||
12525 | static void advance_sev_es_emulated_ins(struct kvm_vcpu *vcpu) | |
12526 | { | |
12527 | unsigned count = vcpu->arch.pio.count; | |
12528 | complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data); | |
12529 | vcpu->arch.sev_pio_count -= count; | |
12530 | vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; | |
12531 | } | |
12532 | ||
4fa4b38d PB |
12533 | static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) |
12534 | { | |
95e16b47 PB |
12535 | int size = vcpu->arch.pio.size; |
12536 | int port = vcpu->arch.pio.port; | |
4fa4b38d | 12537 | |
95e16b47 PB |
12538 | advance_sev_es_emulated_ins(vcpu); |
12539 | if (vcpu->arch.sev_pio_count) | |
12540 | return kvm_sev_es_ins(vcpu, size, port); | |
4fa4b38d PB |
12541 | return 1; |
12542 | } | |
12543 | ||
7ed9abfe | 12544 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, |
95e16b47 | 12545 | unsigned int port) |
7ed9abfe | 12546 | { |
95e16b47 PB |
12547 | for (;;) { |
12548 | unsigned int count = | |
12549 | min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); | |
12550 | if (!__emulator_pio_in(vcpu, size, port, count)) | |
12551 | break; | |
7ed9abfe | 12552 | |
ea724ea4 | 12553 | /* Emulation done by the kernel. */ |
95e16b47 PB |
12554 | advance_sev_es_emulated_ins(vcpu); |
12555 | if (!vcpu->arch.sev_pio_count) | |
12556 | return 1; | |
7ed9abfe TL |
12557 | } |
12558 | ||
ea724ea4 | 12559 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; |
7ed9abfe TL |
12560 | return 0; |
12561 | } | |
12562 | ||
12563 | int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, | |
12564 | unsigned int port, void *data, unsigned int count, | |
12565 | int in) | |
12566 | { | |
ea724ea4 | 12567 | vcpu->arch.sev_pio_data = data; |
95e16b47 PB |
12568 | vcpu->arch.sev_pio_count = count; |
12569 | return in ? kvm_sev_es_ins(vcpu, size, port) | |
12570 | : kvm_sev_es_outs(vcpu, size, port); | |
7ed9abfe TL |
12571 | } |
12572 | EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); | |
12573 | ||
d95df951 | 12574 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); |
229456fc | 12575 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 12576 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
12577 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
12578 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
12579 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
12580 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 12581 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 12582 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 12583 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 12584 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 12585 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 12586 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 12587 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 12588 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 12589 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 12590 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 12591 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 12592 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
12593 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
12594 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
ab56f8e6 | 12595 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); |
24bbf74c | 12596 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); |
d523ab6b TL |
12597 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); |
12598 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); | |
59e38b58 TL |
12599 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); |
12600 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); |