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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
88197e6a | 21 | #include "ioapic.h" |
1d737c8a | 22 | #include "mmu.h" |
7837699f | 23 | #include "i8254.h" |
37817f29 | 24 | #include "tss.h" |
5fdbf976 | 25 | #include "kvm_cache_regs.h" |
2f728d66 | 26 | #include "kvm_emulate.h" |
26eef70c | 27 | #include "x86.h" |
00b27a3e | 28 | #include "cpuid.h" |
474a5bb9 | 29 | #include "pmu.h" |
e83d5887 | 30 | #include "hyperv.h" |
8df14af4 | 31 | #include "lapic.h" |
23200b7a | 32 | #include "xen.h" |
313a3dc7 | 33 | |
18068523 | 34 | #include <linux/clocksource.h> |
4d5c5d0f | 35 | #include <linux/interrupt.h> |
313a3dc7 CO |
36 | #include <linux/kvm.h> |
37 | #include <linux/fs.h> | |
38 | #include <linux/vmalloc.h> | |
1767e931 PG |
39 | #include <linux/export.h> |
40 | #include <linux/moduleparam.h> | |
0de10343 | 41 | #include <linux/mman.h> |
2bacc55c | 42 | #include <linux/highmem.h> |
19de40a8 | 43 | #include <linux/iommu.h> |
62c476c7 | 44 | #include <linux/intel-iommu.h> |
c8076604 | 45 | #include <linux/cpufreq.h> |
18863bdd | 46 | #include <linux/user-return-notifier.h> |
a983fb23 | 47 | #include <linux/srcu.h> |
5a0e3ad6 | 48 | #include <linux/slab.h> |
ff9d07a0 | 49 | #include <linux/perf_event.h> |
7bee342a | 50 | #include <linux/uaccess.h> |
af585b92 | 51 | #include <linux/hash.h> |
a1b60c1c | 52 | #include <linux/pci.h> |
16e8d74d MT |
53 | #include <linux/timekeeper_internal.h> |
54 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
55 | #include <linux/kvm_irqfd.h> |
56 | #include <linux/irqbypass.h> | |
3905f9ad | 57 | #include <linux/sched/stat.h> |
0c5f81da | 58 | #include <linux/sched/isolation.h> |
d0ec49d4 | 59 | #include <linux/mem_encrypt.h> |
72c3c0fe | 60 | #include <linux/entry-kvm.h> |
7d62874f | 61 | #include <linux/suspend.h> |
3905f9ad | 62 | |
aec51dc4 | 63 | #include <trace/events/kvm.h> |
2ed152af | 64 | |
24f1e32c | 65 | #include <asm/debugreg.h> |
d825ed0a | 66 | #include <asm/msr.h> |
a5f61300 | 67 | #include <asm/desc.h> |
890ca9ae | 68 | #include <asm/mce.h> |
f89e32e0 | 69 | #include <linux/kernel_stat.h> |
78f7f1e5 | 70 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 71 | #include <asm/pvclock.h> |
217fc9cf | 72 | #include <asm/div64.h> |
efc64404 | 73 | #include <asm/irq_remapping.h> |
b0c39dc6 | 74 | #include <asm/mshyperv.h> |
0092e434 | 75 | #include <asm/hypervisor.h> |
9715092f | 76 | #include <asm/tlbflush.h> |
bf8c55d8 | 77 | #include <asm/intel_pt.h> |
b3dc0695 | 78 | #include <asm/emulate_prefix.h> |
fe7e9488 | 79 | #include <asm/sgx.h> |
dd2cb348 | 80 | #include <clocksource/hyperv_timer.h> |
043405e1 | 81 | |
d1898b73 DH |
82 | #define CREATE_TRACE_POINTS |
83 | #include "trace.h" | |
84 | ||
313a3dc7 | 85 | #define MAX_IO_MSRS 256 |
890ca9ae | 86 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
87 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
88 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 89 | |
0f65dd70 | 90 | #define emul_to_vcpu(ctxt) \ |
c9b8b07c | 91 | ((struct kvm_vcpu *)(ctxt)->vcpu) |
0f65dd70 | 92 | |
50a37eb4 JR |
93 | /* EFER defaults: |
94 | * - enable syscall per default because its emulated by KVM | |
95 | * - enable LME and LMA per default on 64 bit KVM | |
96 | */ | |
97 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
98 | static |
99 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 100 | #else |
1260edbe | 101 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 102 | #endif |
313a3dc7 | 103 | |
b11306b5 SC |
104 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
105 | ||
c519265f RK |
106 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
107 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 108 | |
cb142eb7 | 109 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 110 | static void process_nmi(struct kvm_vcpu *vcpu); |
1f7becf1 | 111 | static void process_smi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 112 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 113 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
114 | static void store_regs(struct kvm_vcpu *vcpu); |
115 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 116 | |
6dba9403 ML |
117 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); |
118 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); | |
119 | ||
afaf0b2f | 120 | struct kvm_x86_ops kvm_x86_ops __read_mostly; |
5fdbf976 | 121 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 122 | |
9af5471b JB |
123 | #define KVM_X86_OP(func) \ |
124 | DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ | |
125 | *(((struct kvm_x86_ops *)0)->func)); | |
126 | #define KVM_X86_OP_NULL KVM_X86_OP | |
127 | #include <asm/kvm-x86-ops.h> | |
128 | EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); | |
129 | EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); | |
130 | EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); | |
131 | ||
893590c7 | 132 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 133 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 134 | |
d855066f | 135 | bool __read_mostly report_ignored_msrs = true; |
fab0aa3b | 136 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); |
d855066f | 137 | EXPORT_SYMBOL_GPL(report_ignored_msrs); |
fab0aa3b | 138 | |
4c27625b | 139 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
140 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
141 | ||
630994b3 MT |
142 | static bool __read_mostly kvmclock_periodic_sync = true; |
143 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
144 | ||
893590c7 | 145 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 146 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 147 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 148 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
149 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
150 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
151 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
152 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
153 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
154 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
fe6b6bc8 CQ |
155 | bool __read_mostly kvm_has_bus_lock_exit; |
156 | EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); | |
92a1f12d | 157 | |
cc578287 | 158 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 159 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
160 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
161 | ||
c3941d9e SC |
162 | /* |
163 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
d9f6e12f | 164 | * adaptive tuning starting from default advancement of 1000ns. '0' disables |
c3941d9e | 165 | * advancement entirely. Any other value is used as-is and disables adaptive |
d9f6e12f | 166 | * tuning, i.e. allows privileged userspace to set an exact advancement time. |
c3941d9e SC |
167 | */ |
168 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 169 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 170 | |
52004014 FW |
171 | static bool __read_mostly vector_hashing = true; |
172 | module_param(vector_hashing, bool, S_IRUGO); | |
173 | ||
c4ae60e4 LA |
174 | bool __read_mostly enable_vmware_backdoor = false; |
175 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
176 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
177 | ||
6c86eedc WL |
178 | static bool __read_mostly force_emulation_prefix = false; |
179 | module_param(force_emulation_prefix, bool, S_IRUGO); | |
180 | ||
0c5f81da WL |
181 | int __read_mostly pi_inject_timer = -1; |
182 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
183 | ||
7e34fbd0 SC |
184 | /* |
185 | * Restoring the host value for MSRs that are only consumed when running in | |
186 | * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU | |
187 | * returns to userspace, i.e. the kernel can run with the guest's value. | |
188 | */ | |
189 | #define KVM_MAX_NR_USER_RETURN_MSRS 16 | |
18863bdd | 190 | |
7e34fbd0 | 191 | struct kvm_user_return_msrs { |
18863bdd AK |
192 | struct user_return_notifier urn; |
193 | bool registered; | |
7e34fbd0 | 194 | struct kvm_user_return_msr_values { |
2bf78fa7 SY |
195 | u64 host; |
196 | u64 curr; | |
7e34fbd0 | 197 | } values[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
198 | }; |
199 | ||
9cc39a5a SC |
200 | u32 __read_mostly kvm_nr_uret_msrs; |
201 | EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); | |
202 | static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; | |
7e34fbd0 | 203 | static struct kvm_user_return_msrs __percpu *user_return_msrs; |
18863bdd | 204 | |
cfc48181 SC |
205 | #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ |
206 | | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | |
207 | | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | |
208 | | XFEATURE_MASK_PKRU) | |
209 | ||
91661989 SC |
210 | u64 __read_mostly host_efer; |
211 | EXPORT_SYMBOL_GPL(host_efer); | |
212 | ||
b96e6506 | 213 | bool __read_mostly allow_smaller_maxphyaddr = 0; |
3edd6839 MG |
214 | EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); |
215 | ||
fdf513e3 VK |
216 | bool __read_mostly enable_apicv = true; |
217 | EXPORT_SYMBOL_GPL(enable_apicv); | |
218 | ||
86137773 TL |
219 | u64 __read_mostly host_xss; |
220 | EXPORT_SYMBOL_GPL(host_xss); | |
408e9a31 PB |
221 | u64 __read_mostly supported_xss; |
222 | EXPORT_SYMBOL_GPL(supported_xss); | |
139a12cf | 223 | |
417bc304 | 224 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
812756a8 EGE |
225 | VCPU_STAT("pf_fixed", pf_fixed), |
226 | VCPU_STAT("pf_guest", pf_guest), | |
227 | VCPU_STAT("tlb_flush", tlb_flush), | |
228 | VCPU_STAT("invlpg", invlpg), | |
229 | VCPU_STAT("exits", exits), | |
230 | VCPU_STAT("io_exits", io_exits), | |
231 | VCPU_STAT("mmio_exits", mmio_exits), | |
232 | VCPU_STAT("signal_exits", signal_exits), | |
233 | VCPU_STAT("irq_window", irq_window_exits), | |
234 | VCPU_STAT("nmi_window", nmi_window_exits), | |
235 | VCPU_STAT("halt_exits", halt_exits), | |
236 | VCPU_STAT("halt_successful_poll", halt_successful_poll), | |
237 | VCPU_STAT("halt_attempted_poll", halt_attempted_poll), | |
238 | VCPU_STAT("halt_poll_invalid", halt_poll_invalid), | |
239 | VCPU_STAT("halt_wakeup", halt_wakeup), | |
240 | VCPU_STAT("hypercalls", hypercalls), | |
241 | VCPU_STAT("request_irq", request_irq_exits), | |
242 | VCPU_STAT("irq_exits", irq_exits), | |
243 | VCPU_STAT("host_state_reload", host_state_reload), | |
244 | VCPU_STAT("fpu_reload", fpu_reload), | |
245 | VCPU_STAT("insn_emulation", insn_emulation), | |
246 | VCPU_STAT("insn_emulation_fail", insn_emulation_fail), | |
247 | VCPU_STAT("irq_injections", irq_injections), | |
248 | VCPU_STAT("nmi_injections", nmi_injections), | |
249 | VCPU_STAT("req_event", req_event), | |
250 | VCPU_STAT("l1d_flush", l1d_flush), | |
cb953129 DM |
251 | VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns), |
252 | VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns), | |
43c11d91 | 253 | VCPU_STAT("nested_run", nested_run), |
4a7132ef WL |
254 | VCPU_STAT("directed_yield_attempted", directed_yield_attempted), |
255 | VCPU_STAT("directed_yield_successful", directed_yield_successful), | |
d5a0483f | 256 | VCPU_STAT("guest_mode", guest_mode), |
812756a8 EGE |
257 | VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped), |
258 | VM_STAT("mmu_pte_write", mmu_pte_write), | |
812756a8 EGE |
259 | VM_STAT("mmu_pde_zapped", mmu_pde_zapped), |
260 | VM_STAT("mmu_flooded", mmu_flooded), | |
261 | VM_STAT("mmu_recycled", mmu_recycled), | |
262 | VM_STAT("mmu_cache_miss", mmu_cache_miss), | |
263 | VM_STAT("mmu_unsync", mmu_unsync), | |
264 | VM_STAT("remote_tlb_flush", remote_tlb_flush), | |
265 | VM_STAT("largepages", lpages, .mode = 0444), | |
266 | VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444), | |
267 | VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions), | |
417bc304 HB |
268 | { NULL } |
269 | }; | |
270 | ||
2acf923e | 271 | u64 __read_mostly host_xcr0; |
cfc48181 SC |
272 | u64 __read_mostly supported_xcr0; |
273 | EXPORT_SYMBOL_GPL(supported_xcr0); | |
2acf923e | 274 | |
80fbd280 | 275 | static struct kmem_cache *x86_fpu_cache; |
b666a4b6 | 276 | |
c9b8b07c SC |
277 | static struct kmem_cache *x86_emulator_cache; |
278 | ||
6abe9c13 PX |
279 | /* |
280 | * When called, it means the previous get/set msr reached an invalid msr. | |
cc4cb017 | 281 | * Return true if we want to ignore/silent this failed msr access. |
6abe9c13 | 282 | */ |
d632826f | 283 | static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) |
6abe9c13 PX |
284 | { |
285 | const char *op = write ? "wrmsr" : "rdmsr"; | |
286 | ||
287 | if (ignore_msrs) { | |
288 | if (report_ignored_msrs) | |
d383b314 TI |
289 | kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", |
290 | op, msr, data); | |
6abe9c13 | 291 | /* Mask the error */ |
cc4cb017 | 292 | return true; |
6abe9c13 | 293 | } else { |
d383b314 TI |
294 | kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", |
295 | op, msr, data); | |
cc4cb017 | 296 | return false; |
6abe9c13 PX |
297 | } |
298 | } | |
299 | ||
c9b8b07c SC |
300 | static struct kmem_cache *kvm_alloc_emulator_cache(void) |
301 | { | |
06add254 SC |
302 | unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); |
303 | unsigned int size = sizeof(struct x86_emulate_ctxt); | |
304 | ||
305 | return kmem_cache_create_usercopy("x86_emulator", size, | |
c9b8b07c | 306 | __alignof__(struct x86_emulate_ctxt), |
06add254 SC |
307 | SLAB_ACCOUNT, useroffset, |
308 | size - useroffset, NULL); | |
c9b8b07c SC |
309 | } |
310 | ||
b6785def | 311 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 312 | |
af585b92 GN |
313 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
314 | { | |
315 | int i; | |
dd03bcaa | 316 | for (i = 0; i < ASYNC_PF_PER_VCPU; i++) |
af585b92 GN |
317 | vcpu->arch.apf.gfns[i] = ~0; |
318 | } | |
319 | ||
18863bdd AK |
320 | static void kvm_on_user_return(struct user_return_notifier *urn) |
321 | { | |
322 | unsigned slot; | |
7e34fbd0 SC |
323 | struct kvm_user_return_msrs *msrs |
324 | = container_of(urn, struct kvm_user_return_msrs, urn); | |
325 | struct kvm_user_return_msr_values *values; | |
1650b4eb IA |
326 | unsigned long flags; |
327 | ||
328 | /* | |
329 | * Disabling irqs at this point since the following code could be | |
330 | * interrupted and executed through kvm_arch_hardware_disable() | |
331 | */ | |
332 | local_irq_save(flags); | |
7e34fbd0 SC |
333 | if (msrs->registered) { |
334 | msrs->registered = false; | |
1650b4eb IA |
335 | user_return_notifier_unregister(urn); |
336 | } | |
337 | local_irq_restore(flags); | |
9cc39a5a | 338 | for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { |
7e34fbd0 | 339 | values = &msrs->values[slot]; |
2bf78fa7 | 340 | if (values->host != values->curr) { |
9cc39a5a | 341 | wrmsrl(kvm_uret_msrs_list[slot], values->host); |
2bf78fa7 | 342 | values->curr = values->host; |
18863bdd AK |
343 | } |
344 | } | |
18863bdd AK |
345 | } |
346 | ||
e5fda4bb | 347 | static int kvm_probe_user_return_msr(u32 msr) |
5104d7ff SC |
348 | { |
349 | u64 val; | |
350 | int ret; | |
351 | ||
352 | preempt_disable(); | |
353 | ret = rdmsrl_safe(msr, &val); | |
354 | if (ret) | |
355 | goto out; | |
356 | ret = wrmsrl_safe(msr, val); | |
357 | out: | |
358 | preempt_enable(); | |
359 | return ret; | |
360 | } | |
5104d7ff | 361 | |
e5fda4bb | 362 | int kvm_add_user_return_msr(u32 msr) |
2bf78fa7 | 363 | { |
e5fda4bb SC |
364 | BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); |
365 | ||
366 | if (kvm_probe_user_return_msr(msr)) | |
367 | return -1; | |
368 | ||
369 | kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; | |
370 | return kvm_nr_uret_msrs++; | |
18863bdd | 371 | } |
e5fda4bb | 372 | EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); |
18863bdd | 373 | |
8ea8b8d6 SC |
374 | int kvm_find_user_return_msr(u32 msr) |
375 | { | |
376 | int i; | |
377 | ||
9cc39a5a SC |
378 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
379 | if (kvm_uret_msrs_list[i] == msr) | |
8ea8b8d6 SC |
380 | return i; |
381 | } | |
382 | return -1; | |
383 | } | |
384 | EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); | |
385 | ||
7e34fbd0 | 386 | static void kvm_user_return_msr_cpu_online(void) |
18863bdd | 387 | { |
05c19c2f | 388 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 389 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
05c19c2f SC |
390 | u64 value; |
391 | int i; | |
18863bdd | 392 | |
9cc39a5a SC |
393 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
394 | rdmsrl_safe(kvm_uret_msrs_list[i], &value); | |
7e34fbd0 SC |
395 | msrs->values[i].host = value; |
396 | msrs->values[i].curr = value; | |
05c19c2f | 397 | } |
18863bdd AK |
398 | } |
399 | ||
7e34fbd0 | 400 | int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 401 | { |
013f6a5d | 402 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 403 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
8b3c3104 | 404 | int err; |
18863bdd | 405 | |
7e34fbd0 SC |
406 | value = (value & mask) | (msrs->values[slot].host & ~mask); |
407 | if (value == msrs->values[slot].curr) | |
8b3c3104 | 408 | return 0; |
9cc39a5a | 409 | err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); |
8b3c3104 AH |
410 | if (err) |
411 | return 1; | |
412 | ||
7e34fbd0 SC |
413 | msrs->values[slot].curr = value; |
414 | if (!msrs->registered) { | |
415 | msrs->urn.on_user_return = kvm_on_user_return; | |
416 | user_return_notifier_register(&msrs->urn); | |
417 | msrs->registered = true; | |
18863bdd | 418 | } |
8b3c3104 | 419 | return 0; |
18863bdd | 420 | } |
7e34fbd0 | 421 | EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); |
18863bdd | 422 | |
13a34e06 | 423 | static void drop_user_return_notifiers(void) |
3548bab5 | 424 | { |
013f6a5d | 425 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 426 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
3548bab5 | 427 | |
7e34fbd0 SC |
428 | if (msrs->registered) |
429 | kvm_on_user_return(&msrs->urn); | |
3548bab5 AK |
430 | } |
431 | ||
6866b83e CO |
432 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
433 | { | |
8a5a87d9 | 434 | return vcpu->arch.apic_base; |
6866b83e CO |
435 | } |
436 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
437 | ||
58871649 JM |
438 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
439 | { | |
440 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
441 | } | |
442 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
443 | ||
58cb628d JK |
444 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
445 | { | |
58871649 JM |
446 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
447 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
a8ac864a | 448 | u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | |
d6321d49 | 449 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); |
58cb628d | 450 | |
58871649 | 451 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 452 | return 1; |
58871649 JM |
453 | if (!msr_info->host_initiated) { |
454 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
455 | return 1; | |
456 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
457 | return 1; | |
458 | } | |
58cb628d JK |
459 | |
460 | kvm_lapic_set_base(vcpu, msr_info->data); | |
4abaffce | 461 | kvm_recalculate_apic_map(vcpu->kvm); |
58cb628d | 462 | return 0; |
6866b83e CO |
463 | } |
464 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
465 | ||
3ebccdf3 | 466 | asmlinkage __visible noinstr void kvm_spurious_fault(void) |
e3ba45b8 GL |
467 | { |
468 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 469 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
470 | } |
471 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
472 | ||
3fd28fce ED |
473 | #define EXCPT_BENIGN 0 |
474 | #define EXCPT_CONTRIBUTORY 1 | |
475 | #define EXCPT_PF 2 | |
476 | ||
477 | static int exception_class(int vector) | |
478 | { | |
479 | switch (vector) { | |
480 | case PF_VECTOR: | |
481 | return EXCPT_PF; | |
482 | case DE_VECTOR: | |
483 | case TS_VECTOR: | |
484 | case NP_VECTOR: | |
485 | case SS_VECTOR: | |
486 | case GP_VECTOR: | |
487 | return EXCPT_CONTRIBUTORY; | |
488 | default: | |
489 | break; | |
490 | } | |
491 | return EXCPT_BENIGN; | |
492 | } | |
493 | ||
d6e8c854 NA |
494 | #define EXCPT_FAULT 0 |
495 | #define EXCPT_TRAP 1 | |
496 | #define EXCPT_ABORT 2 | |
497 | #define EXCPT_INTERRUPT 3 | |
498 | ||
499 | static int exception_type(int vector) | |
500 | { | |
501 | unsigned int mask; | |
502 | ||
503 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
504 | return EXCPT_INTERRUPT; | |
505 | ||
506 | mask = 1 << vector; | |
507 | ||
508 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
509 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
510 | return EXCPT_TRAP; | |
511 | ||
512 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
513 | return EXCPT_ABORT; | |
514 | ||
515 | /* Reserved exceptions will result in fault */ | |
516 | return EXCPT_FAULT; | |
517 | } | |
518 | ||
da998b46 JM |
519 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
520 | { | |
521 | unsigned nr = vcpu->arch.exception.nr; | |
522 | bool has_payload = vcpu->arch.exception.has_payload; | |
523 | unsigned long payload = vcpu->arch.exception.payload; | |
524 | ||
525 | if (!has_payload) | |
526 | return; | |
527 | ||
528 | switch (nr) { | |
f10c729f JM |
529 | case DB_VECTOR: |
530 | /* | |
531 | * "Certain debug exceptions may clear bit 0-3. The | |
532 | * remaining contents of the DR6 register are never | |
533 | * cleared by the processor". | |
534 | */ | |
535 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
536 | /* | |
9a3ecd5e CQ |
537 | * In order to reflect the #DB exception payload in guest |
538 | * dr6, three components need to be considered: active low | |
539 | * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, | |
540 | * DR6_BS and DR6_BT) | |
541 | * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. | |
542 | * In the target guest dr6: | |
543 | * FIXED_1 bits should always be set. | |
544 | * Active low bits should be cleared if 1-setting in payload. | |
545 | * Active high bits should be set if 1-setting in payload. | |
546 | * | |
547 | * Note, the payload is compatible with the pending debug | |
548 | * exceptions/exit qualification under VMX, that active_low bits | |
549 | * are active high in payload. | |
550 | * So they need to be flipped for DR6. | |
f10c729f | 551 | */ |
9a3ecd5e | 552 | vcpu->arch.dr6 |= DR6_ACTIVE_LOW; |
f10c729f | 553 | vcpu->arch.dr6 |= payload; |
9a3ecd5e | 554 | vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; |
307f1cfa OU |
555 | |
556 | /* | |
557 | * The #DB payload is defined as compatible with the 'pending | |
558 | * debug exceptions' field under VMX, not DR6. While bit 12 is | |
559 | * defined in the 'pending debug exceptions' field (enabled | |
560 | * breakpoint), it is reserved and must be zero in DR6. | |
561 | */ | |
562 | vcpu->arch.dr6 &= ~BIT(12); | |
f10c729f | 563 | break; |
da998b46 JM |
564 | case PF_VECTOR: |
565 | vcpu->arch.cr2 = payload; | |
566 | break; | |
567 | } | |
568 | ||
569 | vcpu->arch.exception.has_payload = false; | |
570 | vcpu->arch.exception.payload = 0; | |
571 | } | |
572 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
573 | ||
3fd28fce | 574 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 575 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 576 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
577 | { |
578 | u32 prev_nr; | |
579 | int class1, class2; | |
580 | ||
3842d135 AK |
581 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
582 | ||
664f8e26 | 583 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 584 | queue: |
664f8e26 WL |
585 | if (reinject) { |
586 | /* | |
587 | * On vmentry, vcpu->arch.exception.pending is only | |
588 | * true if an event injection was blocked by | |
589 | * nested_run_pending. In that case, however, | |
590 | * vcpu_enter_guest requests an immediate exit, | |
591 | * and the guest shouldn't proceed far enough to | |
592 | * need reinjection. | |
593 | */ | |
594 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
595 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
596 | if (WARN_ON_ONCE(has_payload)) { |
597 | /* | |
598 | * A reinjected event has already | |
599 | * delivered its payload. | |
600 | */ | |
601 | has_payload = false; | |
602 | payload = 0; | |
603 | } | |
664f8e26 WL |
604 | } else { |
605 | vcpu->arch.exception.pending = true; | |
606 | vcpu->arch.exception.injected = false; | |
607 | } | |
3fd28fce ED |
608 | vcpu->arch.exception.has_error_code = has_error; |
609 | vcpu->arch.exception.nr = nr; | |
610 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
611 | vcpu->arch.exception.has_payload = has_payload; |
612 | vcpu->arch.exception.payload = payload; | |
a06230b6 | 613 | if (!is_guest_mode(vcpu)) |
da998b46 | 614 | kvm_deliver_exception_payload(vcpu); |
3fd28fce ED |
615 | return; |
616 | } | |
617 | ||
618 | /* to check exception */ | |
619 | prev_nr = vcpu->arch.exception.nr; | |
620 | if (prev_nr == DF_VECTOR) { | |
621 | /* triple fault -> shutdown */ | |
a8eeb04a | 622 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
623 | return; |
624 | } | |
625 | class1 = exception_class(prev_nr); | |
626 | class2 = exception_class(nr); | |
627 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
628 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
629 | /* |
630 | * Generate double fault per SDM Table 5-5. Set | |
631 | * exception.pending = true so that the double fault | |
632 | * can trigger a nested vmexit. | |
633 | */ | |
3fd28fce | 634 | vcpu->arch.exception.pending = true; |
664f8e26 | 635 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
636 | vcpu->arch.exception.has_error_code = true; |
637 | vcpu->arch.exception.nr = DF_VECTOR; | |
638 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
639 | vcpu->arch.exception.has_payload = false; |
640 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
641 | } else |
642 | /* replace previous exception with a new one in a hope | |
643 | that instruction re-execution will regenerate lost | |
644 | exception */ | |
645 | goto queue; | |
646 | } | |
647 | ||
298101da AK |
648 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
649 | { | |
91e86d22 | 650 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
651 | } |
652 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
653 | ||
ce7ddec4 JR |
654 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
655 | { | |
91e86d22 | 656 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
657 | } |
658 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
659 | ||
4d5523cf PB |
660 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
661 | unsigned long payload) | |
f10c729f JM |
662 | { |
663 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
664 | } | |
4d5523cf | 665 | EXPORT_SYMBOL_GPL(kvm_queue_exception_p); |
f10c729f | 666 | |
da998b46 JM |
667 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
668 | u32 error_code, unsigned long payload) | |
669 | { | |
670 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
671 | true, payload, false); | |
672 | } | |
673 | ||
6affcbed | 674 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 675 | { |
db8fcefa AP |
676 | if (err) |
677 | kvm_inject_gp(vcpu, 0); | |
678 | else | |
6affcbed KH |
679 | return kvm_skip_emulated_instruction(vcpu); |
680 | ||
681 | return 1; | |
db8fcefa AP |
682 | } |
683 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 684 | |
6389ee94 | 685 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
686 | { |
687 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
688 | vcpu->arch.exception.nested_apf = |
689 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 690 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 691 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
692 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
693 | } else { | |
694 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
695 | fault->address); | |
696 | } | |
c3c91fee | 697 | } |
27d6c865 | 698 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 699 | |
53b3d8e9 SC |
700 | bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
701 | struct x86_exception *fault) | |
d4f8cf66 | 702 | { |
0cd665bd | 703 | struct kvm_mmu *fault_mmu; |
53b3d8e9 SC |
704 | WARN_ON_ONCE(fault->vector != PF_VECTOR); |
705 | ||
0cd665bd PB |
706 | fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : |
707 | vcpu->arch.walk_mmu; | |
ef54bcfe | 708 | |
ee1fa209 JS |
709 | /* |
710 | * Invalidate the TLB entry for the faulting address, if it exists, | |
711 | * else the access will fault indefinitely (and to emulate hardware). | |
712 | */ | |
713 | if ((fault->error_code & PFERR_PRESENT_MASK) && | |
714 | !(fault->error_code & PFERR_RSVD_MASK)) | |
715 | kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, | |
716 | fault_mmu->root_hpa); | |
717 | ||
718 | fault_mmu->inject_page_fault(vcpu, fault); | |
ef54bcfe | 719 | return fault->nested_page_fault; |
d4f8cf66 | 720 | } |
53b3d8e9 | 721 | EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); |
d4f8cf66 | 722 | |
3419ffc8 SY |
723 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
724 | { | |
7460fb4a AK |
725 | atomic_inc(&vcpu->arch.nmi_queued); |
726 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
727 | } |
728 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
729 | ||
298101da AK |
730 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
731 | { | |
91e86d22 | 732 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
733 | } |
734 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
735 | ||
ce7ddec4 JR |
736 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
737 | { | |
91e86d22 | 738 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
739 | } |
740 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
741 | ||
0a79b009 AK |
742 | /* |
743 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
744 | * a #GP and return false. | |
745 | */ | |
746 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 747 | { |
b3646477 | 748 | if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) |
0a79b009 AK |
749 | return true; |
750 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
751 | return false; | |
298101da | 752 | } |
0a79b009 | 753 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 754 | |
16f8a6f9 NA |
755 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
756 | { | |
757 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
758 | return true; | |
759 | ||
760 | kvm_queue_exception(vcpu, UD_VECTOR); | |
761 | return false; | |
762 | } | |
763 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
764 | ||
ec92fe44 JR |
765 | /* |
766 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 767 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
768 | * can read from guest physical or from the guest's guest physical memory. |
769 | */ | |
770 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
771 | gfn_t ngfn, void *data, int offset, int len, | |
772 | u32 access) | |
773 | { | |
54987b7a | 774 | struct x86_exception exception; |
ec92fe44 JR |
775 | gfn_t real_gfn; |
776 | gpa_t ngpa; | |
777 | ||
778 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 779 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
780 | if (real_gfn == UNMAPPED_GVA) |
781 | return -EFAULT; | |
782 | ||
783 | real_gfn = gpa_to_gfn(real_gfn); | |
784 | ||
54bf36aa | 785 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
786 | } |
787 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
788 | ||
16cfacc8 SC |
789 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
790 | { | |
5b7f575c | 791 | return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); |
16cfacc8 SC |
792 | } |
793 | ||
a03490ed | 794 | /* |
16cfacc8 | 795 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 796 | */ |
ff03a073 | 797 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
798 | { |
799 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
800 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
801 | int i; | |
802 | int ret; | |
ff03a073 | 803 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 804 | |
ff03a073 JR |
805 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
806 | offset * sizeof(u64), sizeof(pdpte), | |
807 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
808 | if (ret < 0) { |
809 | ret = 0; | |
810 | goto out; | |
811 | } | |
812 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
812f30b2 | 813 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 814 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
a03490ed CO |
815 | ret = 0; |
816 | goto out; | |
817 | } | |
818 | } | |
819 | ret = 1; | |
820 | ||
ff03a073 | 821 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
cb3c1e2f | 822 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); |
a03490ed | 823 | out: |
a03490ed CO |
824 | |
825 | return ret; | |
826 | } | |
cc4b6871 | 827 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 828 | |
f27ad38a TL |
829 | void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) |
830 | { | |
831 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; | |
832 | ||
833 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { | |
834 | kvm_clear_async_pf_completion_queue(vcpu); | |
835 | kvm_async_pf_hash_reset(vcpu); | |
836 | } | |
837 | ||
838 | if ((cr0 ^ old_cr0) & update_bits) | |
839 | kvm_mmu_reset_context(vcpu); | |
840 | ||
841 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && | |
842 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
843 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
844 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); | |
845 | } | |
846 | EXPORT_SYMBOL_GPL(kvm_post_set_cr0); | |
847 | ||
49a9b07e | 848 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 849 | { |
aad82703 | 850 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d42e3fae | 851 | unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; |
aad82703 | 852 | |
f9a48e6a AK |
853 | cr0 |= X86_CR0_ET; |
854 | ||
ab344828 | 855 | #ifdef CONFIG_X86_64 |
0f12244f GN |
856 | if (cr0 & 0xffffffff00000000UL) |
857 | return 1; | |
ab344828 GN |
858 | #endif |
859 | ||
860 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 861 | |
0f12244f GN |
862 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
863 | return 1; | |
a03490ed | 864 | |
0f12244f GN |
865 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
866 | return 1; | |
a03490ed | 867 | |
a03490ed | 868 | #ifdef CONFIG_X86_64 |
05487215 SC |
869 | if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && |
870 | (cr0 & X86_CR0_PG)) { | |
871 | int cs_db, cs_l; | |
872 | ||
873 | if (!is_pae(vcpu)) | |
874 | return 1; | |
b3646477 | 875 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
05487215 | 876 | if (cs_l) |
0f12244f | 877 | return 1; |
a03490ed | 878 | } |
05487215 SC |
879 | #endif |
880 | if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && | |
881 | is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && | |
882 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) | |
883 | return 1; | |
a03490ed | 884 | |
ad756a16 MJ |
885 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
886 | return 1; | |
887 | ||
b3646477 | 888 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
a03490ed | 889 | |
f27ad38a | 890 | kvm_post_set_cr0(vcpu, old_cr0, cr0); |
b18d5431 | 891 | |
0f12244f GN |
892 | return 0; |
893 | } | |
2d3ad1f4 | 894 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 895 | |
2d3ad1f4 | 896 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 897 | { |
49a9b07e | 898 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 899 | } |
2d3ad1f4 | 900 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 901 | |
139a12cf | 902 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 903 | { |
16809ecd TL |
904 | if (vcpu->arch.guest_state_protected) |
905 | return; | |
906 | ||
139a12cf AL |
907 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
908 | ||
909 | if (vcpu->arch.xcr0 != host_xcr0) | |
910 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
911 | ||
912 | if (vcpu->arch.xsaves_enabled && | |
913 | vcpu->arch.ia32_xss != host_xss) | |
914 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
915 | } | |
37486135 BM |
916 | |
917 | if (static_cpu_has(X86_FEATURE_PKU) && | |
918 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
919 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && | |
920 | vcpu->arch.pkru != vcpu->arch.host_pkru) | |
921 | __write_pkru(vcpu->arch.pkru); | |
42bdf991 | 922 | } |
139a12cf | 923 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 924 | |
139a12cf | 925 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 926 | { |
16809ecd TL |
927 | if (vcpu->arch.guest_state_protected) |
928 | return; | |
929 | ||
37486135 BM |
930 | if (static_cpu_has(X86_FEATURE_PKU) && |
931 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
932 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { | |
933 | vcpu->arch.pkru = rdpkru(); | |
934 | if (vcpu->arch.pkru != vcpu->arch.host_pkru) | |
935 | __write_pkru(vcpu->arch.host_pkru); | |
936 | } | |
937 | ||
139a12cf AL |
938 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
939 | ||
940 | if (vcpu->arch.xcr0 != host_xcr0) | |
941 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
942 | ||
943 | if (vcpu->arch.xsaves_enabled && | |
944 | vcpu->arch.ia32_xss != host_xss) | |
945 | wrmsrl(MSR_IA32_XSS, host_xss); | |
946 | } | |
947 | ||
42bdf991 | 948 | } |
139a12cf | 949 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 950 | |
69b0049a | 951 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 952 | { |
56c103ec LJ |
953 | u64 xcr0 = xcr; |
954 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 955 | u64 valid_bits; |
2acf923e DC |
956 | |
957 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
958 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
959 | return 1; | |
d91cab78 | 960 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 961 | return 1; |
d91cab78 | 962 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 963 | return 1; |
46c34cb0 PB |
964 | |
965 | /* | |
966 | * Do not allow the guest to set bits that we do not support | |
967 | * saving. However, xcr0 bit 0 is always set, even if the | |
968 | * emulated CPU does not support XSAVE (see fx_init). | |
969 | */ | |
d91cab78 | 970 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 971 | if (xcr0 & ~valid_bits) |
2acf923e | 972 | return 1; |
46c34cb0 | 973 | |
d91cab78 DH |
974 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
975 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
976 | return 1; |
977 | ||
d91cab78 DH |
978 | if (xcr0 & XFEATURE_MASK_AVX512) { |
979 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 980 | return 1; |
d91cab78 | 981 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
982 | return 1; |
983 | } | |
2acf923e | 984 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 985 | |
d91cab78 | 986 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
aedbaf4f | 987 | kvm_update_cpuid_runtime(vcpu); |
2acf923e DC |
988 | return 0; |
989 | } | |
990 | ||
92f9895c | 991 | int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) |
2acf923e | 992 | { |
92f9895c SC |
993 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || |
994 | __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { | |
995 | kvm_inject_gp(vcpu, 0); | |
996 | return 1; | |
997 | } | |
bbefd4fc | 998 | |
92f9895c | 999 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e | 1000 | } |
92f9895c | 1001 | EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); |
2acf923e | 1002 | |
ee69c92b | 1003 | bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 1004 | { |
b11306b5 | 1005 | if (cr4 & cr4_reserved_bits) |
ee69c92b | 1006 | return false; |
b9baba86 | 1007 | |
b899c132 | 1008 | if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) |
ee69c92b | 1009 | return false; |
3ca94192 | 1010 | |
b3646477 | 1011 | return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); |
3ca94192 | 1012 | } |
ee69c92b | 1013 | EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); |
3ca94192 | 1014 | |
5b51cb13 TL |
1015 | void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) |
1016 | { | |
1017 | unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
1018 | X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; | |
1019 | ||
1020 | if (((cr4 ^ old_cr4) & mmu_role_bits) || | |
1021 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
1022 | kvm_mmu_reset_context(vcpu); | |
3ca94192 | 1023 | } |
5b51cb13 | 1024 | EXPORT_SYMBOL_GPL(kvm_post_set_cr4); |
3ca94192 WL |
1025 | |
1026 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1027 | { | |
1028 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
1029 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
cb957adb | 1030 | X86_CR4_SMEP; |
3ca94192 | 1031 | |
ee69c92b | 1032 | if (!kvm_is_valid_cr4(vcpu, cr4)) |
ae3e61e1 PB |
1033 | return 1; |
1034 | ||
a03490ed | 1035 | if (is_long_mode(vcpu)) { |
0f12244f GN |
1036 | if (!(cr4 & X86_CR4_PAE)) |
1037 | return 1; | |
d74fcfc1 SC |
1038 | if ((cr4 ^ old_cr4) & X86_CR4_LA57) |
1039 | return 1; | |
a2edf57f AK |
1040 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
1041 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
1042 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
1043 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
1044 | return 1; |
1045 | ||
ad756a16 | 1046 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 1047 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
1048 | return 1; |
1049 | ||
1050 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
1051 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
1052 | return 1; | |
1053 | } | |
1054 | ||
b3646477 | 1055 | static_call(kvm_x86_set_cr4)(vcpu, cr4); |
a03490ed | 1056 | |
5b51cb13 | 1057 | kvm_post_set_cr4(vcpu, old_cr4, cr4); |
2acf923e | 1058 | |
0f12244f GN |
1059 | return 0; |
1060 | } | |
2d3ad1f4 | 1061 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 1062 | |
2390218b | 1063 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 1064 | { |
ade61e28 | 1065 | bool skip_tlb_flush = false; |
ac146235 | 1066 | #ifdef CONFIG_X86_64 |
c19986fe JS |
1067 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
1068 | ||
ade61e28 | 1069 | if (pcid_enabled) { |
208320ba JS |
1070 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
1071 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
ade61e28 | 1072 | } |
ac146235 | 1073 | #endif |
9d88fca7 | 1074 | |
c7313155 SC |
1075 | /* PDPTRs are always reloaded for PAE paging. */ |
1076 | if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) { | |
956bf353 JS |
1077 | if (!skip_tlb_flush) { |
1078 | kvm_mmu_sync_roots(vcpu); | |
eeeb4f67 | 1079 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
956bf353 | 1080 | } |
0f12244f | 1081 | return 0; |
d835dfec AK |
1082 | } |
1083 | ||
886bbcc7 SC |
1084 | /* |
1085 | * Do not condition the GPA check on long mode, this helper is used to | |
1086 | * stuff CR3, e.g. for RSM emulation, and there is no guarantee that | |
1087 | * the current vCPU mode is accurate. | |
1088 | */ | |
1089 | if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) | |
d1cd3ce9 | 1090 | return 1; |
886bbcc7 SC |
1091 | |
1092 | if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 1093 | return 1; |
a03490ed | 1094 | |
be01e8e2 | 1095 | kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush); |
0f12244f | 1096 | vcpu->arch.cr3 = cr3; |
cb3c1e2f | 1097 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
7c390d35 | 1098 | |
0f12244f GN |
1099 | return 0; |
1100 | } | |
2d3ad1f4 | 1101 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1102 | |
eea1cff9 | 1103 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1104 | { |
0f12244f GN |
1105 | if (cr8 & CR8_RESERVED_BITS) |
1106 | return 1; | |
35754c98 | 1107 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1108 | kvm_lapic_set_tpr(vcpu, cr8); |
1109 | else | |
ad312c7c | 1110 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1111 | return 0; |
1112 | } | |
2d3ad1f4 | 1113 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1114 | |
2d3ad1f4 | 1115 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1116 | { |
35754c98 | 1117 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1118 | return kvm_lapic_get_cr8(vcpu); |
1119 | else | |
ad312c7c | 1120 | return vcpu->arch.cr8; |
a03490ed | 1121 | } |
2d3ad1f4 | 1122 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1123 | |
ae561ede NA |
1124 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1125 | { | |
1126 | int i; | |
1127 | ||
1128 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1129 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1130 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
1131 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
1132 | } | |
1133 | } | |
1134 | ||
7c86663b | 1135 | void kvm_update_dr7(struct kvm_vcpu *vcpu) |
c8639010 JK |
1136 | { |
1137 | unsigned long dr7; | |
1138 | ||
1139 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1140 | dr7 = vcpu->arch.guest_debug_dr7; | |
1141 | else | |
1142 | dr7 = vcpu->arch.dr7; | |
b3646477 | 1143 | static_call(kvm_x86_set_dr7)(vcpu, dr7); |
360b948d PB |
1144 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1145 | if (dr7 & DR7_BP_EN_MASK) | |
1146 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 | 1147 | } |
7c86663b | 1148 | EXPORT_SYMBOL_GPL(kvm_update_dr7); |
c8639010 | 1149 | |
6f43ed01 NA |
1150 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1151 | { | |
1152 | u64 fixed = DR6_FIXED_1; | |
1153 | ||
d6321d49 | 1154 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 | 1155 | fixed |= DR6_RTM; |
e8ea85fb CQ |
1156 | |
1157 | if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) | |
1158 | fixed |= DR6_BUS_LOCK; | |
6f43ed01 NA |
1159 | return fixed; |
1160 | } | |
1161 | ||
996ff542 | 1162 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1163 | { |
ea740059 MP |
1164 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1165 | ||
020df079 GN |
1166 | switch (dr) { |
1167 | case 0 ... 3: | |
ea740059 | 1168 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1169 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1170 | vcpu->arch.eff_db[dr] = val; | |
1171 | break; | |
1172 | case 4: | |
020df079 | 1173 | case 6: |
f5f6145e | 1174 | if (!kvm_dr6_valid(val)) |
996ff542 | 1175 | return 1; /* #GP */ |
6f43ed01 | 1176 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
020df079 GN |
1177 | break; |
1178 | case 5: | |
020df079 | 1179 | default: /* 7 */ |
b91991bf | 1180 | if (!kvm_dr7_valid(val)) |
996ff542 | 1181 | return 1; /* #GP */ |
020df079 | 1182 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1183 | kvm_update_dr7(vcpu); |
020df079 GN |
1184 | break; |
1185 | } | |
1186 | ||
1187 | return 0; | |
1188 | } | |
1189 | EXPORT_SYMBOL_GPL(kvm_set_dr); | |
1190 | ||
29d6ca41 | 1191 | void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1192 | { |
ea740059 MP |
1193 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1194 | ||
020df079 GN |
1195 | switch (dr) { |
1196 | case 0 ... 3: | |
ea740059 | 1197 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1198 | break; |
1199 | case 4: | |
020df079 | 1200 | case 6: |
5679b803 | 1201 | *val = vcpu->arch.dr6; |
020df079 GN |
1202 | break; |
1203 | case 5: | |
020df079 GN |
1204 | default: /* 7 */ |
1205 | *val = vcpu->arch.dr7; | |
1206 | break; | |
1207 | } | |
338dbc97 | 1208 | } |
020df079 GN |
1209 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1210 | ||
c483c454 | 1211 | int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) |
022cd0e8 | 1212 | { |
de3cd117 | 1213 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 | 1214 | u64 data; |
022cd0e8 | 1215 | |
c483c454 SC |
1216 | if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { |
1217 | kvm_inject_gp(vcpu, 0); | |
1218 | return 1; | |
1219 | } | |
1220 | ||
de3cd117 SC |
1221 | kvm_rax_write(vcpu, (u32)data); |
1222 | kvm_rdx_write(vcpu, data >> 32); | |
c483c454 | 1223 | return kvm_skip_emulated_instruction(vcpu); |
022cd0e8 | 1224 | } |
c483c454 | 1225 | EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); |
022cd0e8 | 1226 | |
043405e1 CO |
1227 | /* |
1228 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1229 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1230 | * | |
7a5ee6ed CQ |
1231 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) |
1232 | * extract the supported MSRs from the related const lists. | |
1233 | * msrs_to_save is selected from the msrs_to_save_all to reflect the | |
e3267cbb | 1234 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
7a5ee6ed | 1235 | * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs |
62ef68bb | 1236 | * may depend on host virtualization features rather than host cpu features. |
043405e1 | 1237 | */ |
e3267cbb | 1238 | |
7a5ee6ed | 1239 | static const u32 msrs_to_save_all[] = { |
043405e1 | 1240 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1241 | MSR_STAR, |
043405e1 CO |
1242 | #ifdef CONFIG_X86_64 |
1243 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1244 | #endif | |
b3897a49 | 1245 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1246 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1247 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1248 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1249 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1250 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1251 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1252 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1253 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1254 | MSR_IA32_UMWAIT_CONTROL, |
1255 | ||
e2ada66e JM |
1256 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
1257 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, | |
1258 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, | |
1259 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1260 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, | |
1261 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1262 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1263 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
1264 | MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, | |
1265 | MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, | |
1266 | MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, | |
1267 | MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, | |
1268 | MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, | |
e2ada66e JM |
1269 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1270 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1271 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1272 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
1273 | MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, | |
1274 | MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, | |
1275 | MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, | |
1276 | MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, | |
1277 | MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, | |
043405e1 CO |
1278 | }; |
1279 | ||
7a5ee6ed | 1280 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; |
043405e1 CO |
1281 | static unsigned num_msrs_to_save; |
1282 | ||
7a5ee6ed | 1283 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1284 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1285 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1286 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1287 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1288 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1289 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1290 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1291 | HV_X64_MSR_RESET, |
11c4b1ca | 1292 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1293 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1294 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1295 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1296 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1297 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1298 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
f97f5a56 JD |
1299 | HV_X64_MSR_SYNDBG_OPTIONS, |
1300 | HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, | |
1301 | HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, | |
1302 | HV_X64_MSR_SYNDBG_PENDING_BUFFER, | |
a2e164e7 VK |
1303 | |
1304 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
557a961a | 1305 | MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, |
62ef68bb | 1306 | |
ba904635 | 1307 | MSR_IA32_TSC_ADJUST, |
09141ec0 | 1308 | MSR_IA32_TSC_DEADLINE, |
2bdb76c0 | 1309 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1310 | MSR_IA32_PERF_CAPABILITIES, |
043405e1 | 1311 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1312 | MSR_IA32_MCG_STATUS, |
1313 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1314 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1315 | MSR_IA32_SMBASE, |
52797bf9 | 1316 | MSR_SMI_COUNT, |
db2336a8 KH |
1317 | MSR_PLATFORM_INFO, |
1318 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1319 | MSR_AMD64_VIRT_SPEC_CTRL, |
6c6a2ab9 | 1320 | MSR_IA32_POWER_CTL, |
99634e3e | 1321 | MSR_IA32_UCODE_REV, |
191c8137 | 1322 | |
95c5c7c7 PB |
1323 | /* |
1324 | * The following list leaves out MSRs whose values are determined | |
1325 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1326 | * We always support the "true" VMX control MSRs, even if the host | |
1327 | * processor does not, so I am putting these registers here rather | |
7a5ee6ed | 1328 | * than in msrs_to_save_all. |
95c5c7c7 PB |
1329 | */ |
1330 | MSR_IA32_VMX_BASIC, | |
1331 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1332 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1333 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1334 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1335 | MSR_IA32_VMX_MISC, | |
1336 | MSR_IA32_VMX_CR0_FIXED0, | |
1337 | MSR_IA32_VMX_CR4_FIXED0, | |
1338 | MSR_IA32_VMX_VMCS_ENUM, | |
1339 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1340 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1341 | MSR_IA32_VMX_VMFUNC, | |
1342 | ||
191c8137 | 1343 | MSR_K7_HWCR, |
2d5ba19b | 1344 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1345 | }; |
1346 | ||
7a5ee6ed | 1347 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1348 | static unsigned num_emulated_msrs; |
1349 | ||
801e459a TL |
1350 | /* |
1351 | * List of msr numbers which are used to expose MSR-based features that | |
1352 | * can be used by a hypervisor to validate requested CPU features. | |
1353 | */ | |
7a5ee6ed | 1354 | static const u32 msr_based_features_all[] = { |
1389309c PB |
1355 | MSR_IA32_VMX_BASIC, |
1356 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1357 | MSR_IA32_VMX_PINBASED_CTLS, | |
1358 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1359 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1360 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1361 | MSR_IA32_VMX_EXIT_CTLS, | |
1362 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1363 | MSR_IA32_VMX_ENTRY_CTLS, | |
1364 | MSR_IA32_VMX_MISC, | |
1365 | MSR_IA32_VMX_CR0_FIXED0, | |
1366 | MSR_IA32_VMX_CR0_FIXED1, | |
1367 | MSR_IA32_VMX_CR4_FIXED0, | |
1368 | MSR_IA32_VMX_CR4_FIXED1, | |
1369 | MSR_IA32_VMX_VMCS_ENUM, | |
1370 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1371 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1372 | MSR_IA32_VMX_VMFUNC, | |
1373 | ||
d1d93fa9 | 1374 | MSR_F10H_DECFG, |
518e7b94 | 1375 | MSR_IA32_UCODE_REV, |
cd283252 | 1376 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1377 | MSR_IA32_PERF_CAPABILITIES, |
801e459a TL |
1378 | }; |
1379 | ||
7a5ee6ed | 1380 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; |
801e459a TL |
1381 | static unsigned int num_msr_based_features; |
1382 | ||
4d22c17c | 1383 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1384 | { |
4d22c17c | 1385 | u64 data = 0; |
5b76a3cf | 1386 | |
4d22c17c XL |
1387 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1388 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf | 1389 | |
b8e8c830 PB |
1390 | /* |
1391 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1392 | * the nested hypervisor runs with NX huge pages. If it is not, | |
d9f6e12f | 1393 | * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other |
b8e8c830 PB |
1394 | * L1 guests, so it need not worry about its own (L2) guests. |
1395 | */ | |
1396 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1397 | ||
5b76a3cf PB |
1398 | /* |
1399 | * If we're doing cache flushes (either "always" or "cond") | |
1400 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1401 | * If an outer hypervisor is doing the cache flush for us | |
1402 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1403 | * capability to the guest too, and if EPT is disabled we're not | |
1404 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1405 | * require a nested hypervisor to do a flush of its own. | |
1406 | */ | |
1407 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1408 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1409 | ||
0c54914d PB |
1410 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1411 | data |= ARCH_CAP_RDCL_NO; | |
1412 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1413 | data |= ARCH_CAP_SSB_NO; | |
1414 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1415 | data |= ARCH_CAP_MDS_NO; | |
1416 | ||
7131636e PB |
1417 | if (!boot_cpu_has(X86_FEATURE_RTM)) { |
1418 | /* | |
1419 | * If RTM=0 because the kernel has disabled TSX, the host might | |
1420 | * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 | |
1421 | * and therefore knows that there cannot be TAA) but keep | |
1422 | * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, | |
1423 | * and we want to allow migrating those guests to tsx=off hosts. | |
1424 | */ | |
1425 | data &= ~ARCH_CAP_TAA_NO; | |
1426 | } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { | |
cbbaa272 | 1427 | data |= ARCH_CAP_TAA_NO; |
7131636e PB |
1428 | } else { |
1429 | /* | |
1430 | * Nothing to do here; we emulate TSX_CTRL if present on the | |
1431 | * host so the guest can choose between disabling TSX or | |
1432 | * using VERW to clear CPU buffers. | |
1433 | */ | |
1434 | } | |
e1d38b63 | 1435 | |
5b76a3cf PB |
1436 | return data; |
1437 | } | |
5b76a3cf | 1438 | |
66421c1e WL |
1439 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1440 | { | |
1441 | switch (msr->index) { | |
cd283252 | 1442 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1443 | msr->data = kvm_get_arch_capabilities(); |
1444 | break; | |
1445 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1446 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1447 | break; |
66421c1e | 1448 | default: |
b3646477 | 1449 | return static_call(kvm_x86_get_msr_feature)(msr); |
66421c1e WL |
1450 | } |
1451 | return 0; | |
1452 | } | |
1453 | ||
801e459a TL |
1454 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1455 | { | |
1456 | struct kvm_msr_entry msr; | |
66421c1e | 1457 | int r; |
801e459a TL |
1458 | |
1459 | msr.index = index; | |
66421c1e | 1460 | r = kvm_get_msr_feature(&msr); |
12bc2132 PX |
1461 | |
1462 | if (r == KVM_MSR_RET_INVALID) { | |
1463 | /* Unconditionally clear the output for simplicity */ | |
1464 | *data = 0; | |
d632826f | 1465 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1466 | r = 0; |
12bc2132 PX |
1467 | } |
1468 | ||
66421c1e WL |
1469 | if (r) |
1470 | return r; | |
801e459a TL |
1471 | |
1472 | *data = msr.data; | |
1473 | ||
1474 | return 0; | |
1475 | } | |
1476 | ||
11988499 | 1477 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1478 | { |
1b4d56b8 | 1479 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1480 | return false; |
1b2fd70c | 1481 | |
1b4d56b8 | 1482 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1483 | return false; |
d8017474 | 1484 | |
0a629563 SC |
1485 | if (efer & (EFER_LME | EFER_LMA) && |
1486 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1487 | return false; | |
1488 | ||
1489 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1490 | return false; | |
d8017474 | 1491 | |
384bb783 | 1492 | return true; |
11988499 SC |
1493 | |
1494 | } | |
1495 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1496 | { | |
1497 | if (efer & efer_reserved_bits) | |
1498 | return false; | |
1499 | ||
1500 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1501 | } |
1502 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1503 | ||
11988499 | 1504 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1505 | { |
1506 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1507 | u64 efer = msr_info->data; |
72f211ec | 1508 | int r; |
384bb783 | 1509 | |
11988499 | 1510 | if (efer & efer_reserved_bits) |
66f61c92 | 1511 | return 1; |
384bb783 | 1512 | |
11988499 SC |
1513 | if (!msr_info->host_initiated) { |
1514 | if (!__kvm_valid_efer(vcpu, efer)) | |
1515 | return 1; | |
1516 | ||
1517 | if (is_paging(vcpu) && | |
1518 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1519 | return 1; | |
1520 | } | |
384bb783 | 1521 | |
15c4a640 | 1522 | efer &= ~EFER_LMA; |
f6801dff | 1523 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1524 | |
b3646477 | 1525 | r = static_call(kvm_x86_set_efer)(vcpu, efer); |
72f211ec ML |
1526 | if (r) { |
1527 | WARN_ON(r > 0); | |
1528 | return r; | |
1529 | } | |
a3d204e2 | 1530 | |
aad82703 SY |
1531 | /* Update reserved bits */ |
1532 | if ((efer ^ old_efer) & EFER_NX) | |
1533 | kvm_mmu_reset_context(vcpu); | |
1534 | ||
b69e8cae | 1535 | return 0; |
15c4a640 CO |
1536 | } |
1537 | ||
f2b4b7dd JR |
1538 | void kvm_enable_efer_bits(u64 mask) |
1539 | { | |
1540 | efer_reserved_bits &= ~mask; | |
1541 | } | |
1542 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1543 | ||
51de8151 AG |
1544 | bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) |
1545 | { | |
b318e8de SC |
1546 | struct kvm_x86_msr_filter *msr_filter; |
1547 | struct msr_bitmap_range *ranges; | |
1a155254 | 1548 | struct kvm *kvm = vcpu->kvm; |
b318e8de | 1549 | bool allowed; |
1a155254 | 1550 | int idx; |
b318e8de | 1551 | u32 i; |
1a155254 | 1552 | |
b318e8de SC |
1553 | /* x2APIC MSRs do not support filtering. */ |
1554 | if (index >= 0x800 && index <= 0x8ff) | |
1a155254 AG |
1555 | return true; |
1556 | ||
1a155254 AG |
1557 | idx = srcu_read_lock(&kvm->srcu); |
1558 | ||
b318e8de SC |
1559 | msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); |
1560 | if (!msr_filter) { | |
1561 | allowed = true; | |
1562 | goto out; | |
1563 | } | |
1564 | ||
1565 | allowed = msr_filter->default_allow; | |
1566 | ranges = msr_filter->ranges; | |
1567 | ||
1568 | for (i = 0; i < msr_filter->count; i++) { | |
1a155254 AG |
1569 | u32 start = ranges[i].base; |
1570 | u32 end = start + ranges[i].nmsrs; | |
1571 | u32 flags = ranges[i].flags; | |
1572 | unsigned long *bitmap = ranges[i].bitmap; | |
1573 | ||
1574 | if ((index >= start) && (index < end) && (flags & type)) { | |
b318e8de | 1575 | allowed = !!test_bit(index - start, bitmap); |
1a155254 AG |
1576 | break; |
1577 | } | |
1578 | } | |
1579 | ||
b318e8de | 1580 | out: |
1a155254 AG |
1581 | srcu_read_unlock(&kvm->srcu, idx); |
1582 | ||
b318e8de | 1583 | return allowed; |
51de8151 AG |
1584 | } |
1585 | EXPORT_SYMBOL_GPL(kvm_msr_allowed); | |
1586 | ||
15c4a640 | 1587 | /* |
f20935d8 SC |
1588 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1589 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1590 | * Returns 0 on success, non-0 otherwise. |
1591 | * Assumes vcpu_load() was already called. | |
1592 | */ | |
f20935d8 SC |
1593 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1594 | bool host_initiated) | |
15c4a640 | 1595 | { |
f20935d8 SC |
1596 | struct msr_data msr; |
1597 | ||
1a155254 | 1598 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) |
cc4cb017 | 1599 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1600 | |
f20935d8 | 1601 | switch (index) { |
854e8bb1 NA |
1602 | case MSR_FS_BASE: |
1603 | case MSR_GS_BASE: | |
1604 | case MSR_KERNEL_GS_BASE: | |
1605 | case MSR_CSTAR: | |
1606 | case MSR_LSTAR: | |
f20935d8 | 1607 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1608 | return 1; |
1609 | break; | |
1610 | case MSR_IA32_SYSENTER_EIP: | |
1611 | case MSR_IA32_SYSENTER_ESP: | |
1612 | /* | |
1613 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1614 | * non-canonical address is written on Intel but not on | |
1615 | * AMD (which ignores the top 32-bits, because it does | |
1616 | * not implement 64-bit SYSENTER). | |
1617 | * | |
1618 | * 64-bit code should hence be able to write a non-canonical | |
1619 | * value on AMD. Making the address canonical ensures that | |
1620 | * vmentry does not fail on Intel after writing a non-canonical | |
1621 | * value, and that something deterministic happens if the guest | |
1622 | * invokes 64-bit SYSENTER. | |
1623 | */ | |
f20935d8 | 1624 | data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); |
61a05d44 SC |
1625 | break; |
1626 | case MSR_TSC_AUX: | |
1627 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1628 | return 1; | |
1629 | ||
1630 | if (!host_initiated && | |
1631 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1632 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1633 | return 1; | |
1634 | ||
1635 | /* | |
1636 | * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has | |
1637 | * incomplete and conflicting architectural behavior. Current | |
1638 | * AMD CPUs completely ignore bits 63:32, i.e. they aren't | |
1639 | * reserved and always read as zeros. Enforce Intel's reserved | |
1640 | * bits check if and only if the guest CPU is Intel, and clear | |
1641 | * the bits in all other cases. This ensures cross-vendor | |
1642 | * migration will provide consistent behavior for the guest. | |
1643 | */ | |
1644 | if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) | |
1645 | return 1; | |
1646 | ||
1647 | data = (u32)data; | |
1648 | break; | |
854e8bb1 | 1649 | } |
f20935d8 SC |
1650 | |
1651 | msr.data = data; | |
1652 | msr.index = index; | |
1653 | msr.host_initiated = host_initiated; | |
1654 | ||
b3646477 | 1655 | return static_call(kvm_x86_set_msr)(vcpu, &msr); |
15c4a640 CO |
1656 | } |
1657 | ||
6abe9c13 PX |
1658 | static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, |
1659 | u32 index, u64 data, bool host_initiated) | |
1660 | { | |
1661 | int ret = __kvm_set_msr(vcpu, index, data, host_initiated); | |
1662 | ||
1663 | if (ret == KVM_MSR_RET_INVALID) | |
d632826f | 1664 | if (kvm_msr_ignored_check(index, data, true)) |
cc4cb017 | 1665 | ret = 0; |
6abe9c13 PX |
1666 | |
1667 | return ret; | |
1668 | } | |
1669 | ||
313a3dc7 | 1670 | /* |
f20935d8 SC |
1671 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1672 | * checks are bypassed if @host_initiated is %true. | |
1673 | * Returns 0 on success, non-0 otherwise. | |
1674 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1675 | */ |
edef5c36 PB |
1676 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1677 | bool host_initiated) | |
609e36d3 PB |
1678 | { |
1679 | struct msr_data msr; | |
f20935d8 | 1680 | int ret; |
609e36d3 | 1681 | |
1a155254 | 1682 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) |
cc4cb017 | 1683 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1684 | |
61a05d44 SC |
1685 | switch (index) { |
1686 | case MSR_TSC_AUX: | |
1687 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1688 | return 1; | |
1689 | ||
1690 | if (!host_initiated && | |
1691 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1692 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1693 | return 1; | |
1694 | break; | |
1695 | } | |
1696 | ||
609e36d3 | 1697 | msr.index = index; |
f20935d8 | 1698 | msr.host_initiated = host_initiated; |
609e36d3 | 1699 | |
b3646477 | 1700 | ret = static_call(kvm_x86_get_msr)(vcpu, &msr); |
f20935d8 SC |
1701 | if (!ret) |
1702 | *data = msr.data; | |
1703 | return ret; | |
609e36d3 PB |
1704 | } |
1705 | ||
6abe9c13 PX |
1706 | static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, |
1707 | u32 index, u64 *data, bool host_initiated) | |
1708 | { | |
1709 | int ret = __kvm_get_msr(vcpu, index, data, host_initiated); | |
1710 | ||
1711 | if (ret == KVM_MSR_RET_INVALID) { | |
1712 | /* Unconditionally clear *data for simplicity */ | |
1713 | *data = 0; | |
d632826f | 1714 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1715 | ret = 0; |
6abe9c13 PX |
1716 | } |
1717 | ||
1718 | return ret; | |
1719 | } | |
1720 | ||
f20935d8 | 1721 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1722 | { |
6abe9c13 | 1723 | return kvm_get_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1724 | } |
1725 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1726 | |
f20935d8 SC |
1727 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1728 | { | |
6abe9c13 | 1729 | return kvm_set_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1730 | } |
1731 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1732 | ||
8b474427 | 1733 | static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) |
1ae09954 | 1734 | { |
8b474427 PB |
1735 | int err = vcpu->run->msr.error; |
1736 | if (!err) { | |
1ae09954 AG |
1737 | kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); |
1738 | kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); | |
1739 | } | |
1740 | ||
b3646477 | 1741 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, err); |
1ae09954 AG |
1742 | } |
1743 | ||
1744 | static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) | |
1745 | { | |
b3646477 | 1746 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); |
1ae09954 AG |
1747 | } |
1748 | ||
1749 | static u64 kvm_msr_reason(int r) | |
1750 | { | |
1751 | switch (r) { | |
cc4cb017 | 1752 | case KVM_MSR_RET_INVALID: |
1ae09954 | 1753 | return KVM_MSR_EXIT_REASON_UNKNOWN; |
cc4cb017 | 1754 | case KVM_MSR_RET_FILTERED: |
1a155254 | 1755 | return KVM_MSR_EXIT_REASON_FILTER; |
1ae09954 AG |
1756 | default: |
1757 | return KVM_MSR_EXIT_REASON_INVAL; | |
1758 | } | |
1759 | } | |
1760 | ||
1761 | static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, | |
1762 | u32 exit_reason, u64 data, | |
1763 | int (*completion)(struct kvm_vcpu *vcpu), | |
1764 | int r) | |
1765 | { | |
1766 | u64 msr_reason = kvm_msr_reason(r); | |
1767 | ||
1768 | /* Check if the user wanted to know about this MSR fault */ | |
1769 | if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) | |
1770 | return 0; | |
1771 | ||
1772 | vcpu->run->exit_reason = exit_reason; | |
1773 | vcpu->run->msr.error = 0; | |
1774 | memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); | |
1775 | vcpu->run->msr.reason = msr_reason; | |
1776 | vcpu->run->msr.index = index; | |
1777 | vcpu->run->msr.data = data; | |
1778 | vcpu->arch.complete_userspace_io = completion; | |
1779 | ||
1780 | return 1; | |
1781 | } | |
1782 | ||
1783 | static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) | |
1784 | { | |
1785 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, | |
1786 | complete_emulated_rdmsr, r); | |
1787 | } | |
1788 | ||
1789 | static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) | |
1790 | { | |
1791 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, | |
1792 | complete_emulated_wrmsr, r); | |
1793 | } | |
1794 | ||
1edce0a9 SC |
1795 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
1796 | { | |
1797 | u32 ecx = kvm_rcx_read(vcpu); | |
1798 | u64 data; | |
1ae09954 AG |
1799 | int r; |
1800 | ||
1801 | r = kvm_get_msr(vcpu, ecx, &data); | |
1edce0a9 | 1802 | |
1ae09954 AG |
1803 | /* MSR read failed? See if we should ask user space */ |
1804 | if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { | |
1805 | /* Bounce to user space */ | |
1806 | return 0; | |
1807 | } | |
1808 | ||
8b474427 PB |
1809 | if (!r) { |
1810 | trace_kvm_msr_read(ecx, data); | |
1811 | ||
1812 | kvm_rax_write(vcpu, data & -1u); | |
1813 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
1814 | } else { | |
1edce0a9 | 1815 | trace_kvm_msr_read_ex(ecx); |
1edce0a9 SC |
1816 | } |
1817 | ||
b3646477 | 1818 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
1819 | } |
1820 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
1821 | ||
1822 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
1823 | { | |
1824 | u32 ecx = kvm_rcx_read(vcpu); | |
1825 | u64 data = kvm_read_edx_eax(vcpu); | |
1ae09954 | 1826 | int r; |
1edce0a9 | 1827 | |
1ae09954 AG |
1828 | r = kvm_set_msr(vcpu, ecx, data); |
1829 | ||
1830 | /* MSR write failed? See if we should ask user space */ | |
7dffecaf | 1831 | if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) |
1ae09954 AG |
1832 | /* Bounce to user space */ |
1833 | return 0; | |
7dffecaf ML |
1834 | |
1835 | /* Signal all other negative errors to userspace */ | |
1836 | if (r < 0) | |
1837 | return r; | |
1ae09954 | 1838 | |
8b474427 PB |
1839 | if (!r) |
1840 | trace_kvm_msr_write(ecx, data); | |
1841 | else | |
1edce0a9 | 1842 | trace_kvm_msr_write_ex(ecx, data); |
1edce0a9 | 1843 | |
b3646477 | 1844 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
1845 | } |
1846 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
1847 | ||
5ff3a351 SC |
1848 | int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) |
1849 | { | |
1850 | return kvm_skip_emulated_instruction(vcpu); | |
1851 | } | |
1852 | EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); | |
1853 | ||
1854 | int kvm_emulate_invd(struct kvm_vcpu *vcpu) | |
1855 | { | |
1856 | /* Treat an INVD instruction as a NOP and just skip it. */ | |
1857 | return kvm_emulate_as_nop(vcpu); | |
1858 | } | |
1859 | EXPORT_SYMBOL_GPL(kvm_emulate_invd); | |
1860 | ||
1861 | int kvm_emulate_mwait(struct kvm_vcpu *vcpu) | |
1862 | { | |
1863 | pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); | |
1864 | return kvm_emulate_as_nop(vcpu); | |
1865 | } | |
1866 | EXPORT_SYMBOL_GPL(kvm_emulate_mwait); | |
1867 | ||
1868 | int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) | |
1869 | { | |
1870 | kvm_queue_exception(vcpu, UD_VECTOR); | |
1871 | return 1; | |
1872 | } | |
1873 | EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); | |
1874 | ||
1875 | int kvm_emulate_monitor(struct kvm_vcpu *vcpu) | |
1876 | { | |
1877 | pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); | |
1878 | return kvm_emulate_as_nop(vcpu); | |
1879 | } | |
1880 | EXPORT_SYMBOL_GPL(kvm_emulate_monitor); | |
1881 | ||
d89d04ab | 1882 | static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) |
5a9f5443 | 1883 | { |
4ae7dc97 | 1884 | xfer_to_guest_mode_prepare(); |
5a9f5443 | 1885 | return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || |
72c3c0fe | 1886 | xfer_to_guest_mode_work_pending(); |
5a9f5443 | 1887 | } |
5a9f5443 | 1888 | |
1e9e2622 WL |
1889 | /* |
1890 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
1891 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
1892 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
1893 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
1894 | * other cases which must be called after interrupts are enabled on the host. | |
1895 | */ | |
1896 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
1897 | { | |
e1be9ac8 WL |
1898 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) |
1899 | return 1; | |
1900 | ||
1901 | if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && | |
1e9e2622 | 1902 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && |
4064a4c6 WL |
1903 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && |
1904 | ((u32)(data >> 32) != X2APIC_BROADCAST)) { | |
1e9e2622 | 1905 | |
d5361678 WL |
1906 | data &= ~(1 << 12); |
1907 | kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); | |
1e9e2622 | 1908 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); |
d5361678 WL |
1909 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); |
1910 | trace_kvm_apic_write(APIC_ICR, (u32)data); | |
1911 | return 0; | |
1e9e2622 WL |
1912 | } |
1913 | ||
1914 | return 1; | |
1915 | } | |
1916 | ||
ae95f566 WL |
1917 | static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) |
1918 | { | |
1919 | if (!kvm_can_use_hv_timer(vcpu)) | |
1920 | return 1; | |
1921 | ||
1922 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
1923 | return 0; | |
1924 | } | |
1925 | ||
404d5d7b | 1926 | fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) |
1e9e2622 WL |
1927 | { |
1928 | u32 msr = kvm_rcx_read(vcpu); | |
8a1038de | 1929 | u64 data; |
404d5d7b | 1930 | fastpath_t ret = EXIT_FASTPATH_NONE; |
1e9e2622 WL |
1931 | |
1932 | switch (msr) { | |
1933 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
8a1038de | 1934 | data = kvm_read_edx_eax(vcpu); |
404d5d7b WL |
1935 | if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { |
1936 | kvm_skip_emulated_instruction(vcpu); | |
1937 | ret = EXIT_FASTPATH_EXIT_HANDLED; | |
80bc97f2 | 1938 | } |
1e9e2622 | 1939 | break; |
09141ec0 | 1940 | case MSR_IA32_TSC_DEADLINE: |
ae95f566 WL |
1941 | data = kvm_read_edx_eax(vcpu); |
1942 | if (!handle_fastpath_set_tscdeadline(vcpu, data)) { | |
1943 | kvm_skip_emulated_instruction(vcpu); | |
1944 | ret = EXIT_FASTPATH_REENTER_GUEST; | |
1945 | } | |
1946 | break; | |
1e9e2622 | 1947 | default: |
404d5d7b | 1948 | break; |
1e9e2622 WL |
1949 | } |
1950 | ||
404d5d7b | 1951 | if (ret != EXIT_FASTPATH_NONE) |
1e9e2622 | 1952 | trace_kvm_msr_write(msr, data); |
1e9e2622 | 1953 | |
404d5d7b | 1954 | return ret; |
1e9e2622 WL |
1955 | } |
1956 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
1957 | ||
f20935d8 SC |
1958 | /* |
1959 | * Adapt set_msr() to msr_io()'s calling convention | |
1960 | */ | |
1961 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1962 | { | |
6abe9c13 | 1963 | return kvm_get_msr_ignored_check(vcpu, index, data, true); |
f20935d8 SC |
1964 | } |
1965 | ||
1966 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1967 | { | |
6abe9c13 | 1968 | return kvm_set_msr_ignored_check(vcpu, index, *data, true); |
313a3dc7 CO |
1969 | } |
1970 | ||
16e8d74d | 1971 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
1972 | struct pvclock_clock { |
1973 | int vclock_mode; | |
1974 | u64 cycle_last; | |
1975 | u64 mask; | |
1976 | u32 mult; | |
1977 | u32 shift; | |
917f9475 PB |
1978 | u64 base_cycles; |
1979 | u64 offset; | |
53fafdbb MT |
1980 | }; |
1981 | ||
16e8d74d MT |
1982 | struct pvclock_gtod_data { |
1983 | seqcount_t seq; | |
1984 | ||
53fafdbb MT |
1985 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
1986 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 1987 | |
917f9475 | 1988 | ktime_t offs_boot; |
55dd00a7 | 1989 | u64 wall_time_sec; |
16e8d74d MT |
1990 | }; |
1991 | ||
1992 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1993 | ||
1994 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1995 | { | |
1996 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
1997 | ||
1998 | write_seqcount_begin(&vdata->seq); | |
1999 | ||
2000 | /* copy pvclock gtod data */ | |
b95a8a27 | 2001 | vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; |
876e7881 PZ |
2002 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; |
2003 | vdata->clock.mask = tk->tkr_mono.mask; | |
2004 | vdata->clock.mult = tk->tkr_mono.mult; | |
2005 | vdata->clock.shift = tk->tkr_mono.shift; | |
917f9475 PB |
2006 | vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; |
2007 | vdata->clock.offset = tk->tkr_mono.base; | |
16e8d74d | 2008 | |
b95a8a27 | 2009 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; |
53fafdbb MT |
2010 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; |
2011 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
2012 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
2013 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
917f9475 PB |
2014 | vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; |
2015 | vdata->raw_clock.offset = tk->tkr_raw.base; | |
16e8d74d | 2016 | |
55dd00a7 MT |
2017 | vdata->wall_time_sec = tk->xtime_sec; |
2018 | ||
917f9475 | 2019 | vdata->offs_boot = tk->offs_boot; |
53fafdbb | 2020 | |
16e8d74d MT |
2021 | write_seqcount_end(&vdata->seq); |
2022 | } | |
8171cd68 PB |
2023 | |
2024 | static s64 get_kvmclock_base_ns(void) | |
2025 | { | |
2026 | /* Count up from boot time, but with the frequency of the raw clock. */ | |
2027 | return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); | |
2028 | } | |
2029 | #else | |
2030 | static s64 get_kvmclock_base_ns(void) | |
2031 | { | |
2032 | /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ | |
2033 | return ktime_get_boottime_ns(); | |
2034 | } | |
16e8d74d MT |
2035 | #endif |
2036 | ||
629b5348 | 2037 | void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) |
18068523 | 2038 | { |
9ed3c444 AK |
2039 | int version; |
2040 | int r; | |
50d0a0f9 | 2041 | struct pvclock_wall_clock wc; |
629b5348 | 2042 | u32 wc_sec_hi; |
8171cd68 | 2043 | u64 wall_nsec; |
18068523 GOC |
2044 | |
2045 | if (!wall_clock) | |
2046 | return; | |
2047 | ||
9ed3c444 AK |
2048 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
2049 | if (r) | |
2050 | return; | |
2051 | ||
2052 | if (version & 1) | |
2053 | ++version; /* first time write, random junk */ | |
2054 | ||
2055 | ++version; | |
18068523 | 2056 | |
1dab1345 NK |
2057 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
2058 | return; | |
18068523 | 2059 | |
50d0a0f9 GH |
2060 | /* |
2061 | * The guest calculates current wall clock time by adding | |
34c238a1 | 2062 | * system time (updated by kvm_guest_time_update below) to the |
8171cd68 | 2063 | * wall clock specified here. We do the reverse here. |
50d0a0f9 | 2064 | */ |
8171cd68 | 2065 | wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); |
50d0a0f9 | 2066 | |
8171cd68 PB |
2067 | wc.nsec = do_div(wall_nsec, 1000000000); |
2068 | wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ | |
50d0a0f9 | 2069 | wc.version = version; |
18068523 GOC |
2070 | |
2071 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
2072 | ||
629b5348 JM |
2073 | if (sec_hi_ofs) { |
2074 | wc_sec_hi = wall_nsec >> 32; | |
2075 | kvm_write_guest(kvm, wall_clock + sec_hi_ofs, | |
2076 | &wc_sec_hi, sizeof(wc_sec_hi)); | |
2077 | } | |
2078 | ||
18068523 GOC |
2079 | version++; |
2080 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
2081 | } |
2082 | ||
5b9bb0eb OU |
2083 | static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, |
2084 | bool old_msr, bool host_initiated) | |
2085 | { | |
2086 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
2087 | ||
2088 | if (vcpu->vcpu_id == 0 && !host_initiated) { | |
1e293d1a | 2089 | if (ka->boot_vcpu_runs_old_kvmclock != old_msr) |
5b9bb0eb OU |
2090 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2091 | ||
2092 | ka->boot_vcpu_runs_old_kvmclock = old_msr; | |
2093 | } | |
2094 | ||
2095 | vcpu->arch.time = system_time; | |
2096 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
2097 | ||
2098 | /* we verify if the enable bit is set... */ | |
2099 | vcpu->arch.pv_time_enabled = false; | |
2100 | if (!(system_time & 1)) | |
2101 | return; | |
2102 | ||
2103 | if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
2104 | &vcpu->arch.pv_time, system_time & ~1ULL, | |
2105 | sizeof(struct pvclock_vcpu_time_info))) | |
2106 | vcpu->arch.pv_time_enabled = true; | |
2107 | ||
2108 | return; | |
2109 | } | |
2110 | ||
50d0a0f9 GH |
2111 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
2112 | { | |
b51012de PB |
2113 | do_shl32_div32(dividend, divisor); |
2114 | return dividend; | |
50d0a0f9 GH |
2115 | } |
2116 | ||
3ae13faa | 2117 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 2118 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 2119 | { |
5f4e3f88 | 2120 | uint64_t scaled64; |
50d0a0f9 GH |
2121 | int32_t shift = 0; |
2122 | uint64_t tps64; | |
2123 | uint32_t tps32; | |
2124 | ||
3ae13faa PB |
2125 | tps64 = base_hz; |
2126 | scaled64 = scaled_hz; | |
50933623 | 2127 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
2128 | tps64 >>= 1; |
2129 | shift--; | |
2130 | } | |
2131 | ||
2132 | tps32 = (uint32_t)tps64; | |
50933623 JK |
2133 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
2134 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
2135 | scaled64 >>= 1; |
2136 | else | |
2137 | tps32 <<= 1; | |
50d0a0f9 GH |
2138 | shift++; |
2139 | } | |
2140 | ||
5f4e3f88 ZA |
2141 | *pshift = shift; |
2142 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
2143 | } |
2144 | ||
d828199e | 2145 | #ifdef CONFIG_X86_64 |
16e8d74d | 2146 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 2147 | #endif |
16e8d74d | 2148 | |
c8076604 | 2149 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 2150 | static unsigned long max_tsc_khz; |
c8076604 | 2151 | |
cc578287 | 2152 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 2153 | { |
cc578287 ZA |
2154 | u64 v = (u64)khz * (1000000 + ppm); |
2155 | do_div(v, 1000000); | |
2156 | return v; | |
1e993611 JR |
2157 | } |
2158 | ||
1ab9287a IS |
2159 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); |
2160 | ||
381d585c HZ |
2161 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
2162 | { | |
2163 | u64 ratio; | |
2164 | ||
2165 | /* Guest TSC same frequency as host TSC? */ | |
2166 | if (!scale) { | |
1ab9287a | 2167 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); |
381d585c HZ |
2168 | return 0; |
2169 | } | |
2170 | ||
2171 | /* TSC scaling supported? */ | |
2172 | if (!kvm_has_tsc_control) { | |
2173 | if (user_tsc_khz > tsc_khz) { | |
2174 | vcpu->arch.tsc_catchup = 1; | |
2175 | vcpu->arch.tsc_always_catchup = 1; | |
2176 | return 0; | |
2177 | } else { | |
3f16a5c3 | 2178 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
2179 | return -1; |
2180 | } | |
2181 | } | |
2182 | ||
2183 | /* TSC scaling required - calculate ratio */ | |
2184 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
2185 | user_tsc_khz, tsc_khz); | |
2186 | ||
2187 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
3f16a5c3 PB |
2188 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
2189 | user_tsc_khz); | |
381d585c HZ |
2190 | return -1; |
2191 | } | |
2192 | ||
1ab9287a | 2193 | kvm_vcpu_write_tsc_multiplier(vcpu, ratio); |
381d585c HZ |
2194 | return 0; |
2195 | } | |
2196 | ||
4941b8cb | 2197 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 2198 | { |
cc578287 ZA |
2199 | u32 thresh_lo, thresh_hi; |
2200 | int use_scaling = 0; | |
217fc9cf | 2201 | |
03ba32ca | 2202 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 2203 | if (user_tsc_khz == 0) { |
ad721883 | 2204 | /* set tsc_scaling_ratio to a safe value */ |
1ab9287a | 2205 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); |
381d585c | 2206 | return -1; |
ad721883 | 2207 | } |
03ba32ca | 2208 | |
c285545f | 2209 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 2210 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
2211 | &vcpu->arch.virtual_tsc_shift, |
2212 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 2213 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
2214 | |
2215 | /* | |
2216 | * Compute the variation in TSC rate which is acceptable | |
2217 | * within the range of tolerance and decide if the | |
2218 | * rate being applied is within that bounds of the hardware | |
2219 | * rate. If so, no scaling or compensation need be done. | |
2220 | */ | |
2221 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
2222 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
2223 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
2224 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
2225 | use_scaling = 1; |
2226 | } | |
4941b8cb | 2227 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
2228 | } |
2229 | ||
2230 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
2231 | { | |
e26101b1 | 2232 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
2233 | vcpu->arch.virtual_tsc_mult, |
2234 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 2235 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
2236 | return tsc; |
2237 | } | |
2238 | ||
b0c39dc6 VK |
2239 | static inline int gtod_is_based_on_tsc(int mode) |
2240 | { | |
b95a8a27 | 2241 | return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; |
b0c39dc6 VK |
2242 | } |
2243 | ||
69b0049a | 2244 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
2245 | { |
2246 | #ifdef CONFIG_X86_64 | |
2247 | bool vcpus_matched; | |
b48aa97e MT |
2248 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2249 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2250 | ||
2251 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2252 | atomic_read(&vcpu->kvm->online_vcpus)); | |
2253 | ||
7f187922 MT |
2254 | /* |
2255 | * Once the masterclock is enabled, always perform request in | |
2256 | * order to update it. | |
2257 | * | |
2258 | * In order to enable masterclock, the host clocksource must be TSC | |
2259 | * and the vcpus need to have matched TSCs. When that happens, | |
2260 | * perform request to enable masterclock. | |
2261 | */ | |
2262 | if (ka->use_master_clock || | |
b0c39dc6 | 2263 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
2264 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2265 | ||
2266 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
2267 | atomic_read(&vcpu->kvm->online_vcpus), | |
2268 | ka->use_master_clock, gtod->clock.vclock_mode); | |
2269 | #endif | |
2270 | } | |
2271 | ||
35181e86 HZ |
2272 | /* |
2273 | * Multiply tsc by a fixed point number represented by ratio. | |
2274 | * | |
2275 | * The most significant 64-N bits (mult) of ratio represent the | |
2276 | * integral part of the fixed point number; the remaining N bits | |
2277 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
2278 | * point number (mult + frac * 2^(-N)). | |
2279 | * | |
2280 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
2281 | */ | |
2282 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
2283 | { | |
2284 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
2285 | } | |
2286 | ||
fe3eb504 | 2287 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc, u64 ratio) |
35181e86 HZ |
2288 | { |
2289 | u64 _tsc = tsc; | |
35181e86 HZ |
2290 | |
2291 | if (ratio != kvm_default_tsc_scaling_ratio) | |
2292 | _tsc = __scale_tsc(ratio, tsc); | |
2293 | ||
2294 | return _tsc; | |
2295 | } | |
2296 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
2297 | ||
9b399dfd | 2298 | static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
07c1419a HZ |
2299 | { |
2300 | u64 tsc; | |
2301 | ||
fe3eb504 | 2302 | tsc = kvm_scale_tsc(vcpu, rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); |
07c1419a HZ |
2303 | |
2304 | return target_tsc - tsc; | |
2305 | } | |
2306 | ||
4ba76538 HZ |
2307 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
2308 | { | |
fe3eb504 IS |
2309 | return vcpu->arch.l1_tsc_offset + |
2310 | kvm_scale_tsc(vcpu, host_tsc, vcpu->arch.l1_tsc_scaling_ratio); | |
4ba76538 HZ |
2311 | } |
2312 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
2313 | ||
83150f29 IS |
2314 | u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) |
2315 | { | |
2316 | u64 nested_offset; | |
2317 | ||
2318 | if (l2_multiplier == kvm_default_tsc_scaling_ratio) | |
2319 | nested_offset = l1_offset; | |
2320 | else | |
2321 | nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, | |
2322 | kvm_tsc_scaling_ratio_frac_bits); | |
2323 | ||
2324 | nested_offset += l2_offset; | |
2325 | return nested_offset; | |
2326 | } | |
2327 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); | |
2328 | ||
2329 | u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) | |
2330 | { | |
2331 | if (l2_multiplier != kvm_default_tsc_scaling_ratio) | |
2332 | return mul_u64_u64_shr(l1_multiplier, l2_multiplier, | |
2333 | kvm_tsc_scaling_ratio_frac_bits); | |
2334 | ||
2335 | return l1_multiplier; | |
2336 | } | |
2337 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); | |
2338 | ||
edcfe540 | 2339 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) |
a545ab6a | 2340 | { |
edcfe540 IS |
2341 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2342 | vcpu->arch.l1_tsc_offset, | |
2343 | l1_offset); | |
2344 | ||
2345 | vcpu->arch.l1_tsc_offset = l1_offset; | |
2346 | ||
2347 | /* | |
2348 | * If we are here because L1 chose not to trap WRMSR to TSC then | |
2349 | * according to the spec this should set L1's TSC (as opposed to | |
2350 | * setting L1's offset for L2). | |
2351 | */ | |
2352 | if (is_guest_mode(vcpu)) | |
2353 | vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( | |
2354 | l1_offset, | |
2355 | static_call(kvm_x86_get_l2_tsc_offset)(vcpu), | |
2356 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2357 | else | |
2358 | vcpu->arch.tsc_offset = l1_offset; | |
2359 | ||
2360 | static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); | |
a545ab6a LC |
2361 | } |
2362 | ||
1ab9287a IS |
2363 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) |
2364 | { | |
2365 | vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; | |
2366 | ||
2367 | /* Userspace is changing the multiplier while L2 is active */ | |
2368 | if (is_guest_mode(vcpu)) | |
2369 | vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( | |
2370 | l1_multiplier, | |
2371 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2372 | else | |
2373 | vcpu->arch.tsc_scaling_ratio = l1_multiplier; | |
2374 | ||
2375 | if (kvm_has_tsc_control) | |
2376 | static_call(kvm_x86_write_tsc_multiplier)( | |
2377 | vcpu, vcpu->arch.tsc_scaling_ratio); | |
2378 | } | |
2379 | ||
b0c39dc6 VK |
2380 | static inline bool kvm_check_tsc_unstable(void) |
2381 | { | |
2382 | #ifdef CONFIG_X86_64 | |
2383 | /* | |
2384 | * TSC is marked unstable when we're running on Hyper-V, | |
2385 | * 'TSC page' clocksource is good. | |
2386 | */ | |
b95a8a27 | 2387 | if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) |
b0c39dc6 VK |
2388 | return false; |
2389 | #endif | |
2390 | return check_tsc_unstable(); | |
2391 | } | |
2392 | ||
0c899c25 | 2393 | static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) |
99e3e30a ZA |
2394 | { |
2395 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 2396 | u64 offset, ns, elapsed; |
99e3e30a | 2397 | unsigned long flags; |
b48aa97e | 2398 | bool matched; |
0d3da0d2 | 2399 | bool already_matched; |
c5e8ec8e | 2400 | bool synchronizing = false; |
99e3e30a | 2401 | |
038f8c11 | 2402 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
9b399dfd | 2403 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
8171cd68 | 2404 | ns = get_kvmclock_base_ns(); |
f38e098f | 2405 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 2406 | |
03ba32ca | 2407 | if (vcpu->arch.virtual_tsc_khz) { |
0c899c25 | 2408 | if (data == 0) { |
bd8fab39 DP |
2409 | /* |
2410 | * detection of vcpu initialization -- need to sync | |
2411 | * with other vCPUs. This particularly helps to keep | |
2412 | * kvm_clock stable after CPU hotplug | |
2413 | */ | |
2414 | synchronizing = true; | |
2415 | } else { | |
2416 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
2417 | nsec_to_cycles(vcpu, elapsed); | |
2418 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
2419 | /* | |
2420 | * Special case: TSC write with a small delta (1 second) | |
2421 | * of virtual cycle time against real time is | |
2422 | * interpreted as an attempt to synchronize the CPU. | |
2423 | */ | |
2424 | synchronizing = data < tsc_exp + tsc_hz && | |
2425 | data + tsc_hz > tsc_exp; | |
2426 | } | |
c5e8ec8e | 2427 | } |
f38e098f ZA |
2428 | |
2429 | /* | |
5d3cb0f6 ZA |
2430 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
2431 | * TSC, we add elapsed time in this computation. We could let the | |
2432 | * compensation code attempt to catch up if we fall behind, but | |
2433 | * it's better to try to match offsets from the beginning. | |
2434 | */ | |
c5e8ec8e | 2435 | if (synchronizing && |
5d3cb0f6 | 2436 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 2437 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 2438 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 2439 | } else { |
857e4099 | 2440 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 2441 | data += delta; |
9b399dfd | 2442 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
f38e098f | 2443 | } |
b48aa97e | 2444 | matched = true; |
0d3da0d2 | 2445 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
2446 | } else { |
2447 | /* | |
2448 | * We split periods of matched TSC writes into generations. | |
2449 | * For each generation, we track the original measured | |
2450 | * nanosecond time, offset, and write, so if TSCs are in | |
2451 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 2452 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
2453 | * |
2454 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2455 | */ | |
2456 | kvm->arch.cur_tsc_generation++; | |
2457 | kvm->arch.cur_tsc_nsec = ns; | |
2458 | kvm->arch.cur_tsc_write = data; | |
2459 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 2460 | matched = false; |
f38e098f | 2461 | } |
e26101b1 ZA |
2462 | |
2463 | /* | |
2464 | * We also track th most recent recorded KHZ, write and time to | |
2465 | * allow the matching interval to be extended at each write. | |
2466 | */ | |
f38e098f ZA |
2467 | kvm->arch.last_tsc_nsec = ns; |
2468 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 2469 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 2470 | |
b183aa58 | 2471 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
2472 | |
2473 | /* Keep track of which generation this VCPU has synchronized to */ | |
2474 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2475 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2476 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2477 | ||
a545ab6a | 2478 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
e26101b1 | 2479 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
b48aa97e | 2480 | |
a83829f5 | 2481 | spin_lock_irqsave(&kvm->arch.pvclock_gtod_sync_lock, flags); |
0d3da0d2 | 2482 | if (!matched) { |
b48aa97e | 2483 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
2484 | } else if (!already_matched) { |
2485 | kvm->arch.nr_vcpus_matched_tsc++; | |
2486 | } | |
b48aa97e MT |
2487 | |
2488 | kvm_track_tsc_matching(vcpu); | |
a83829f5 | 2489 | spin_unlock_irqrestore(&kvm->arch.pvclock_gtod_sync_lock, flags); |
99e3e30a | 2490 | } |
e26101b1 | 2491 | |
58ea6767 HZ |
2492 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2493 | s64 adjustment) | |
2494 | { | |
56ba77a4 | 2495 | u64 tsc_offset = vcpu->arch.l1_tsc_offset; |
326e7425 | 2496 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); |
58ea6767 HZ |
2497 | } |
2498 | ||
2499 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2500 | { | |
805d705f | 2501 | if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) |
58ea6767 | 2502 | WARN_ON(adjustment < 0); |
fe3eb504 IS |
2503 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment, |
2504 | vcpu->arch.l1_tsc_scaling_ratio); | |
ea26e4ec | 2505 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2506 | } |
2507 | ||
d828199e MT |
2508 | #ifdef CONFIG_X86_64 |
2509 | ||
a5a1d1c2 | 2510 | static u64 read_tsc(void) |
d828199e | 2511 | { |
a5a1d1c2 | 2512 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2513 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2514 | |
2515 | if (likely(ret >= last)) | |
2516 | return ret; | |
2517 | ||
2518 | /* | |
2519 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2520 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2521 | * very likely) and there's a data dependence, so force GCC |
2522 | * to generate a branch instead. I don't barrier() because | |
2523 | * we don't actually need a barrier, and if this function | |
2524 | * ever gets inlined it will generate worse code. | |
2525 | */ | |
2526 | asm volatile (""); | |
2527 | return last; | |
2528 | } | |
2529 | ||
53fafdbb MT |
2530 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2531 | int *mode) | |
d828199e MT |
2532 | { |
2533 | long v; | |
b0c39dc6 VK |
2534 | u64 tsc_pg_val; |
2535 | ||
53fafdbb | 2536 | switch (clock->vclock_mode) { |
b95a8a27 | 2537 | case VDSO_CLOCKMODE_HVCLOCK: |
b0c39dc6 VK |
2538 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), |
2539 | tsc_timestamp); | |
2540 | if (tsc_pg_val != U64_MAX) { | |
2541 | /* TSC page valid */ | |
b95a8a27 | 2542 | *mode = VDSO_CLOCKMODE_HVCLOCK; |
53fafdbb MT |
2543 | v = (tsc_pg_val - clock->cycle_last) & |
2544 | clock->mask; | |
b0c39dc6 VK |
2545 | } else { |
2546 | /* TSC page invalid */ | |
b95a8a27 | 2547 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 VK |
2548 | } |
2549 | break; | |
b95a8a27 TG |
2550 | case VDSO_CLOCKMODE_TSC: |
2551 | *mode = VDSO_CLOCKMODE_TSC; | |
b0c39dc6 | 2552 | *tsc_timestamp = read_tsc(); |
53fafdbb MT |
2553 | v = (*tsc_timestamp - clock->cycle_last) & |
2554 | clock->mask; | |
b0c39dc6 VK |
2555 | break; |
2556 | default: | |
b95a8a27 | 2557 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 | 2558 | } |
d828199e | 2559 | |
b95a8a27 | 2560 | if (*mode == VDSO_CLOCKMODE_NONE) |
b0c39dc6 | 2561 | *tsc_timestamp = v = 0; |
d828199e | 2562 | |
53fafdbb | 2563 | return v * clock->mult; |
d828199e MT |
2564 | } |
2565 | ||
53fafdbb | 2566 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2567 | { |
cbcf2dd3 | 2568 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2569 | unsigned long seq; |
d828199e | 2570 | int mode; |
cbcf2dd3 | 2571 | u64 ns; |
d828199e | 2572 | |
d828199e MT |
2573 | do { |
2574 | seq = read_seqcount_begin(>od->seq); | |
917f9475 | 2575 | ns = gtod->raw_clock.base_cycles; |
53fafdbb | 2576 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); |
917f9475 PB |
2577 | ns >>= gtod->raw_clock.shift; |
2578 | ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); | |
d828199e | 2579 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2580 | *t = ns; |
d828199e MT |
2581 | |
2582 | return mode; | |
2583 | } | |
2584 | ||
899a31f5 | 2585 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2586 | { |
2587 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2588 | unsigned long seq; | |
2589 | int mode; | |
2590 | u64 ns; | |
2591 | ||
2592 | do { | |
2593 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 | 2594 | ts->tv_sec = gtod->wall_time_sec; |
917f9475 | 2595 | ns = gtod->clock.base_cycles; |
53fafdbb | 2596 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2597 | ns >>= gtod->clock.shift; |
2598 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2599 | ||
2600 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2601 | ts->tv_nsec = ns; | |
2602 | ||
2603 | return mode; | |
2604 | } | |
2605 | ||
b0c39dc6 VK |
2606 | /* returns true if host is using TSC based clocksource */ |
2607 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2608 | { |
d828199e | 2609 | /* checked again under seqlock below */ |
b0c39dc6 | 2610 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2611 | return false; |
2612 | ||
53fafdbb | 2613 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2614 | tsc_timestamp)); |
d828199e | 2615 | } |
55dd00a7 | 2616 | |
b0c39dc6 | 2617 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2618 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2619 | u64 *tsc_timestamp) |
55dd00a7 MT |
2620 | { |
2621 | /* checked again under seqlock below */ | |
b0c39dc6 | 2622 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2623 | return false; |
2624 | ||
b0c39dc6 | 2625 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2626 | } |
d828199e MT |
2627 | #endif |
2628 | ||
2629 | /* | |
2630 | * | |
b48aa97e MT |
2631 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2632 | * across virtual CPUs, the following condition is possible. | |
2633 | * Each numbered line represents an event visible to both | |
d828199e MT |
2634 | * CPUs at the next numbered event. |
2635 | * | |
2636 | * "timespecX" represents host monotonic time. "tscX" represents | |
2637 | * RDTSC value. | |
2638 | * | |
2639 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2640 | * | |
2641 | * 1. read timespec0,tsc0 | |
2642 | * 2. | timespec1 = timespec0 + N | |
2643 | * | tsc1 = tsc0 + M | |
2644 | * 3. transition to guest | transition to guest | |
2645 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2646 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2647 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2648 | * | |
2649 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2650 | * | |
2651 | * - ret0 < ret1 | |
2652 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2653 | * ... | |
2654 | * - 0 < N - M => M < N | |
2655 | * | |
2656 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2657 | * always the case (the difference between two distinct xtime instances | |
2658 | * might be smaller then the difference between corresponding TSC reads, | |
2659 | * when updating guest vcpus pvclock areas). | |
2660 | * | |
2661 | * To avoid that problem, do not allow visibility of distinct | |
2662 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2663 | * copy of host monotonic time values. Update that master copy | |
2664 | * in lockstep. | |
2665 | * | |
b48aa97e | 2666 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2667 | * |
2668 | */ | |
2669 | ||
2670 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2671 | { | |
2672 | #ifdef CONFIG_X86_64 | |
2673 | struct kvm_arch *ka = &kvm->arch; | |
2674 | int vclock_mode; | |
b48aa97e MT |
2675 | bool host_tsc_clocksource, vcpus_matched; |
2676 | ||
2677 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2678 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2679 | |
2680 | /* | |
2681 | * If the host uses TSC clock, then passthrough TSC as stable | |
2682 | * to the guest. | |
2683 | */ | |
b48aa97e | 2684 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2685 | &ka->master_kernel_ns, |
2686 | &ka->master_cycle_now); | |
2687 | ||
16a96021 | 2688 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2689 | && !ka->backwards_tsc_observed |
54750f2c | 2690 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2691 | |
d828199e MT |
2692 | if (ka->use_master_clock) |
2693 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2694 | ||
2695 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2696 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2697 | vcpus_matched); | |
d828199e MT |
2698 | #endif |
2699 | } | |
2700 | ||
2860c4b1 PB |
2701 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2702 | { | |
2703 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2704 | } | |
2705 | ||
2e762ff7 MT |
2706 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
2707 | { | |
2708 | #ifdef CONFIG_X86_64 | |
2709 | int i; | |
2710 | struct kvm_vcpu *vcpu; | |
2711 | struct kvm_arch *ka = &kvm->arch; | |
a83829f5 | 2712 | unsigned long flags; |
2e762ff7 | 2713 | |
e880c6ea VK |
2714 | kvm_hv_invalidate_tsc_page(kvm); |
2715 | ||
2e762ff7 | 2716 | kvm_make_mclock_inprogress_request(kvm); |
c2c647f9 | 2717 | |
2e762ff7 | 2718 | /* no guest entries from this point */ |
a83829f5 | 2719 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
2e762ff7 | 2720 | pvclock_update_vm_gtod_copy(kvm); |
a83829f5 | 2721 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
2e762ff7 MT |
2722 | |
2723 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 2724 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2725 | |
2726 | /* guest entries allowed */ | |
2727 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2728 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
2729 | #endif |
2730 | } | |
2731 | ||
e891a32e | 2732 | u64 get_kvmclock_ns(struct kvm *kvm) |
108b249c | 2733 | { |
108b249c | 2734 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2735 | struct pvclock_vcpu_time_info hv_clock; |
a83829f5 | 2736 | unsigned long flags; |
e2c2206a | 2737 | u64 ret; |
108b249c | 2738 | |
a83829f5 | 2739 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
8b953440 | 2740 | if (!ka->use_master_clock) { |
a83829f5 | 2741 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
8171cd68 | 2742 | return get_kvmclock_base_ns() + ka->kvmclock_offset; |
108b249c PB |
2743 | } |
2744 | ||
8b953440 PB |
2745 | hv_clock.tsc_timestamp = ka->master_cycle_now; |
2746 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
a83829f5 | 2747 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
8b953440 | 2748 | |
e2c2206a WL |
2749 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2750 | get_cpu(); | |
2751 | ||
e70b57a6 WL |
2752 | if (__this_cpu_read(cpu_tsc_khz)) { |
2753 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, | |
2754 | &hv_clock.tsc_shift, | |
2755 | &hv_clock.tsc_to_system_mul); | |
2756 | ret = __pvclock_read_cycles(&hv_clock, rdtsc()); | |
2757 | } else | |
8171cd68 | 2758 | ret = get_kvmclock_base_ns() + ka->kvmclock_offset; |
e2c2206a WL |
2759 | |
2760 | put_cpu(); | |
2761 | ||
2762 | return ret; | |
108b249c PB |
2763 | } |
2764 | ||
aa096aa0 JM |
2765 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v, |
2766 | struct gfn_to_hva_cache *cache, | |
2767 | unsigned int offset) | |
0d6dd2ff PB |
2768 | { |
2769 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
2770 | struct pvclock_vcpu_time_info guest_hv_clock; | |
2771 | ||
aa096aa0 JM |
2772 | if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, |
2773 | &guest_hv_clock, offset, sizeof(guest_hv_clock)))) | |
0d6dd2ff PB |
2774 | return; |
2775 | ||
2776 | /* This VCPU is paused, but it's legal for a guest to read another | |
2777 | * VCPU's kvmclock, so we really have to follow the specification where | |
2778 | * it says that version is odd if data is being modified, and even after | |
2779 | * it is consistent. | |
2780 | * | |
2781 | * Version field updates must be kept separate. This is because | |
2782 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
2783 | * writes within a string instruction are weakly ordered. So there | |
2784 | * are three writes overall. | |
2785 | * | |
2786 | * As a small optimization, only write the version field in the first | |
2787 | * and third write. The vcpu->pv_time cache is still valid, because the | |
2788 | * version field is the first in the struct. | |
2789 | */ | |
2790 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
2791 | ||
51c4b8bb LA |
2792 | if (guest_hv_clock.version & 1) |
2793 | ++guest_hv_clock.version; /* first time write, random junk */ | |
2794 | ||
0d6dd2ff | 2795 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
aa096aa0 JM |
2796 | kvm_write_guest_offset_cached(v->kvm, cache, |
2797 | &vcpu->hv_clock, offset, | |
2798 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2799 | |
2800 | smp_wmb(); | |
2801 | ||
2802 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
2803 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
2804 | ||
2805 | if (vcpu->pvclock_set_guest_stopped_request) { | |
2806 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
2807 | vcpu->pvclock_set_guest_stopped_request = false; | |
2808 | } | |
2809 | ||
2810 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
2811 | ||
aa096aa0 JM |
2812 | kvm_write_guest_offset_cached(v->kvm, cache, |
2813 | &vcpu->hv_clock, offset, | |
2814 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
2815 | |
2816 | smp_wmb(); | |
2817 | ||
2818 | vcpu->hv_clock.version++; | |
aa096aa0 JM |
2819 | kvm_write_guest_offset_cached(v->kvm, cache, |
2820 | &vcpu->hv_clock, offset, | |
2821 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2822 | } |
2823 | ||
34c238a1 | 2824 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 2825 | { |
78db6a50 | 2826 | unsigned long flags, tgt_tsc_khz; |
18068523 | 2827 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 2828 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 2829 | s64 kernel_ns; |
d828199e | 2830 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 2831 | u8 pvclock_flags; |
d828199e MT |
2832 | bool use_master_clock; |
2833 | ||
2834 | kernel_ns = 0; | |
2835 | host_tsc = 0; | |
18068523 | 2836 | |
d828199e MT |
2837 | /* |
2838 | * If the host uses TSC clock, then passthrough TSC as stable | |
2839 | * to the guest. | |
2840 | */ | |
a83829f5 | 2841 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
d828199e MT |
2842 | use_master_clock = ka->use_master_clock; |
2843 | if (use_master_clock) { | |
2844 | host_tsc = ka->master_cycle_now; | |
2845 | kernel_ns = ka->master_kernel_ns; | |
2846 | } | |
a83829f5 | 2847 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
c09664bb MT |
2848 | |
2849 | /* Keep irq disabled to prevent changes to the clock */ | |
2850 | local_irq_save(flags); | |
78db6a50 PB |
2851 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2852 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2853 | local_irq_restore(flags); |
2854 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2855 | return 1; | |
2856 | } | |
d828199e | 2857 | if (!use_master_clock) { |
4ea1636b | 2858 | host_tsc = rdtsc(); |
8171cd68 | 2859 | kernel_ns = get_kvmclock_base_ns(); |
d828199e MT |
2860 | } |
2861 | ||
4ba76538 | 2862 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2863 | |
c285545f ZA |
2864 | /* |
2865 | * We may have to catch up the TSC to match elapsed wall clock | |
2866 | * time for two reasons, even if kvmclock is used. | |
2867 | * 1) CPU could have been running below the maximum TSC rate | |
2868 | * 2) Broken TSC compensation resets the base at each VCPU | |
2869 | * entry to avoid unknown leaps of TSC even when running | |
2870 | * again on the same CPU. This may cause apparent elapsed | |
2871 | * time to disappear, and the guest to stand still or run | |
2872 | * very slowly. | |
2873 | */ | |
2874 | if (vcpu->tsc_catchup) { | |
2875 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
2876 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 2877 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
2878 | tsc_timestamp = tsc; |
2879 | } | |
50d0a0f9 GH |
2880 | } |
2881 | ||
18068523 GOC |
2882 | local_irq_restore(flags); |
2883 | ||
0d6dd2ff | 2884 | /* With all the info we got, fill in the values */ |
18068523 | 2885 | |
78db6a50 | 2886 | if (kvm_has_tsc_control) |
fe3eb504 IS |
2887 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz, |
2888 | v->arch.l1_tsc_scaling_ratio); | |
78db6a50 PB |
2889 | |
2890 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 2891 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
2892 | &vcpu->hv_clock.tsc_shift, |
2893 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 2894 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
2895 | } |
2896 | ||
1d5f066e | 2897 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 2898 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 2899 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 2900 | |
d828199e | 2901 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 2902 | pvclock_flags = 0; |
d828199e MT |
2903 | if (use_master_clock) |
2904 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
2905 | ||
78c0337a MT |
2906 | vcpu->hv_clock.flags = pvclock_flags; |
2907 | ||
095cf55d | 2908 | if (vcpu->pv_time_enabled) |
aa096aa0 JM |
2909 | kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); |
2910 | if (vcpu->xen.vcpu_info_set) | |
2911 | kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, | |
2912 | offsetof(struct compat_vcpu_info, time)); | |
f2340cd9 JM |
2913 | if (vcpu->xen.vcpu_time_info_set) |
2914 | kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); | |
095cf55d PB |
2915 | if (v == kvm_get_vcpu(v->kvm, 0)) |
2916 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); | |
8cfdc000 | 2917 | return 0; |
c8076604 GH |
2918 | } |
2919 | ||
0061d53d MT |
2920 | /* |
2921 | * kvmclock updates which are isolated to a given vcpu, such as | |
2922 | * vcpu->cpu migration, should not allow system_timestamp from | |
2923 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
2924 | * correction applies to one vcpu's system_timestamp but not | |
2925 | * the others. | |
2926 | * | |
2927 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
2928 | * We need to rate-limit these requests though, as they can |
2929 | * considerably slow guests that have a large number of vcpus. | |
2930 | * The time for a remote vcpu to update its kvmclock is bound | |
2931 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
2932 | */ |
2933 | ||
7e44e449 AJ |
2934 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
2935 | ||
2936 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
2937 | { |
2938 | int i; | |
7e44e449 AJ |
2939 | struct delayed_work *dwork = to_delayed_work(work); |
2940 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2941 | kvmclock_update_work); | |
2942 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
2943 | struct kvm_vcpu *vcpu; |
2944 | ||
2945 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 2946 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
2947 | kvm_vcpu_kick(vcpu); |
2948 | } | |
2949 | } | |
2950 | ||
7e44e449 AJ |
2951 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
2952 | { | |
2953 | struct kvm *kvm = v->kvm; | |
2954 | ||
105b21bb | 2955 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
2956 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
2957 | KVMCLOCK_UPDATE_DELAY); | |
2958 | } | |
2959 | ||
332967a3 AJ |
2960 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
2961 | ||
2962 | static void kvmclock_sync_fn(struct work_struct *work) | |
2963 | { | |
2964 | struct delayed_work *dwork = to_delayed_work(work); | |
2965 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2966 | kvmclock_sync_work); | |
2967 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
2968 | ||
630994b3 MT |
2969 | if (!kvmclock_periodic_sync) |
2970 | return; | |
2971 | ||
332967a3 AJ |
2972 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
2973 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
2974 | KVMCLOCK_SYNC_PERIOD); | |
2975 | } | |
2976 | ||
191c8137 BP |
2977 | /* |
2978 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
2979 | */ | |
2980 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
2981 | { | |
2982 | /* McStatusWrEn enabled? */ | |
23493d0a | 2983 | if (guest_cpuid_is_amd_or_hygon(vcpu)) |
191c8137 BP |
2984 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); |
2985 | ||
2986 | return false; | |
2987 | } | |
2988 | ||
9ffd986c | 2989 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2990 | { |
890ca9ae HY |
2991 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2992 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
2993 | u32 msr = msr_info->index; |
2994 | u64 data = msr_info->data; | |
890ca9ae | 2995 | |
15c4a640 | 2996 | switch (msr) { |
15c4a640 | 2997 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 2998 | vcpu->arch.mcg_status = data; |
15c4a640 | 2999 | break; |
c7ac679c | 3000 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
3001 | if (!(mcg_cap & MCG_CTL_P) && |
3002 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
3003 | return 1; |
3004 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 3005 | return 1; |
890ca9ae HY |
3006 | vcpu->arch.mcg_ctl = data; |
3007 | break; | |
3008 | default: | |
3009 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3010 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3011 | u32 offset = array_index_nospec( |
3012 | msr - MSR_IA32_MC0_CTL, | |
3013 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3014 | ||
114be429 AP |
3015 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
3016 | * some Linux kernels though clear bit 10 in bank 4 to | |
3017 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
3018 | * this to avoid an uncatched #GP in the guest | |
3019 | */ | |
890ca9ae | 3020 | if ((offset & 0x3) == 0 && |
114be429 | 3021 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 3022 | return -1; |
191c8137 BP |
3023 | |
3024 | /* MCi_STATUS */ | |
9ffd986c | 3025 | if (!msr_info->host_initiated && |
191c8137 BP |
3026 | (offset & 0x3) == 1 && data != 0) { |
3027 | if (!can_set_mci_status(vcpu)) | |
3028 | return -1; | |
3029 | } | |
3030 | ||
890ca9ae HY |
3031 | vcpu->arch.mce_banks[offset] = data; |
3032 | break; | |
3033 | } | |
3034 | return 1; | |
3035 | } | |
3036 | return 0; | |
3037 | } | |
3038 | ||
2635b5c4 VK |
3039 | static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) |
3040 | { | |
3041 | u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; | |
3042 | ||
3043 | return (vcpu->arch.apf.msr_en_val & mask) == mask; | |
3044 | } | |
3045 | ||
344d9588 GN |
3046 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
3047 | { | |
3048 | gpa_t gpa = data & ~0x3f; | |
3049 | ||
2635b5c4 VK |
3050 | /* Bits 4:5 are reserved, Should be zero */ |
3051 | if (data & 0x30) | |
344d9588 GN |
3052 | return 1; |
3053 | ||
66570e96 OU |
3054 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && |
3055 | (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) | |
3056 | return 1; | |
3057 | ||
3058 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && | |
3059 | (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) | |
3060 | return 1; | |
3061 | ||
9d3c447c | 3062 | if (!lapic_in_kernel(vcpu)) |
d831de17 | 3063 | return data ? 1 : 0; |
9d3c447c | 3064 | |
2635b5c4 | 3065 | vcpu->arch.apf.msr_en_val = data; |
344d9588 | 3066 | |
2635b5c4 | 3067 | if (!kvm_pv_async_pf_enabled(vcpu)) { |
344d9588 GN |
3068 | kvm_clear_async_pf_completion_queue(vcpu); |
3069 | kvm_async_pf_hash_reset(vcpu); | |
3070 | return 0; | |
3071 | } | |
3072 | ||
4e335d9e | 3073 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
68fd66f1 | 3074 | sizeof(u64))) |
344d9588 GN |
3075 | return 1; |
3076 | ||
6adba527 | 3077 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 3078 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
2635b5c4 | 3079 | |
344d9588 | 3080 | kvm_async_pf_wakeup_all(vcpu); |
2635b5c4 VK |
3081 | |
3082 | return 0; | |
3083 | } | |
3084 | ||
3085 | static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) | |
3086 | { | |
3087 | /* Bits 8-63 are reserved */ | |
3088 | if (data >> 8) | |
3089 | return 1; | |
3090 | ||
3091 | if (!lapic_in_kernel(vcpu)) | |
3092 | return 1; | |
3093 | ||
3094 | vcpu->arch.apf.msr_int_val = data; | |
3095 | ||
3096 | vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; | |
3097 | ||
344d9588 GN |
3098 | return 0; |
3099 | } | |
3100 | ||
12f9a48f GC |
3101 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
3102 | { | |
0b79459b | 3103 | vcpu->arch.pv_time_enabled = false; |
49dedf0d | 3104 | vcpu->arch.time = 0; |
12f9a48f GC |
3105 | } |
3106 | ||
7780938c | 3107 | static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) |
f38a7b75 WL |
3108 | { |
3109 | ++vcpu->stat.tlb_flush; | |
b3646477 | 3110 | static_call(kvm_x86_tlb_flush_all)(vcpu); |
f38a7b75 WL |
3111 | } |
3112 | ||
0baedd79 VK |
3113 | static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) |
3114 | { | |
3115 | ++vcpu->stat.tlb_flush; | |
b53e84ee LJ |
3116 | |
3117 | if (!tdp_enabled) { | |
3118 | /* | |
3119 | * A TLB flush on behalf of the guest is equivalent to | |
3120 | * INVPCID(all), toggling CR4.PGE, etc., which requires | |
3121 | * a forced sync of the shadow page tables. Unload the | |
3122 | * entire MMU here and the subsequent load will sync the | |
3123 | * shadow page tables, and also flush the TLB. | |
3124 | */ | |
3125 | kvm_mmu_unload(vcpu); | |
3126 | return; | |
3127 | } | |
3128 | ||
b3646477 | 3129 | static_call(kvm_x86_tlb_flush_guest)(vcpu); |
0baedd79 VK |
3130 | } |
3131 | ||
c9aaa895 GC |
3132 | static void record_steal_time(struct kvm_vcpu *vcpu) |
3133 | { | |
b0431382 BO |
3134 | struct kvm_host_map map; |
3135 | struct kvm_steal_time *st; | |
3136 | ||
30b5c851 DW |
3137 | if (kvm_xen_msr_enabled(vcpu->kvm)) { |
3138 | kvm_xen_runstate_set_running(vcpu); | |
3139 | return; | |
3140 | } | |
3141 | ||
c9aaa895 GC |
3142 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
3143 | return; | |
3144 | ||
b0431382 BO |
3145 | /* -EAGAIN is returned in atomic context so we can just return. */ |
3146 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, | |
3147 | &map, &vcpu->arch.st.cache, false)) | |
c9aaa895 GC |
3148 | return; |
3149 | ||
b0431382 BO |
3150 | st = map.hva + |
3151 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
3152 | ||
f38a7b75 WL |
3153 | /* |
3154 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
3155 | * expensive IPIs. | |
3156 | */ | |
66570e96 | 3157 | if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { |
af3511ff LJ |
3158 | u8 st_preempted = xchg(&st->preempted, 0); |
3159 | ||
66570e96 | 3160 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, |
af3511ff LJ |
3161 | st_preempted & KVM_VCPU_FLUSH_TLB); |
3162 | if (st_preempted & KVM_VCPU_FLUSH_TLB) | |
66570e96 | 3163 | kvm_vcpu_flush_tlb_guest(vcpu); |
1eff0ada WL |
3164 | } else { |
3165 | st->preempted = 0; | |
66570e96 | 3166 | } |
0b9f6c46 | 3167 | |
a6bd811f | 3168 | vcpu->arch.st.preempted = 0; |
35f3fae1 | 3169 | |
b0431382 BO |
3170 | if (st->version & 1) |
3171 | st->version += 1; /* first time write, random junk */ | |
35f3fae1 | 3172 | |
b0431382 | 3173 | st->version += 1; |
35f3fae1 WL |
3174 | |
3175 | smp_wmb(); | |
3176 | ||
b0431382 | 3177 | st->steal += current->sched_info.run_delay - |
c54cdf14 LC |
3178 | vcpu->arch.st.last_steal; |
3179 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
35f3fae1 | 3180 | |
35f3fae1 WL |
3181 | smp_wmb(); |
3182 | ||
b0431382 | 3183 | st->version += 1; |
c9aaa895 | 3184 | |
b0431382 | 3185 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); |
c9aaa895 GC |
3186 | } |
3187 | ||
8fe8ab46 | 3188 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3189 | { |
5753785f | 3190 | bool pr = false; |
8fe8ab46 WA |
3191 | u32 msr = msr_info->index; |
3192 | u64 data = msr_info->data; | |
5753785f | 3193 | |
1232f8e6 | 3194 | if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) |
23200b7a | 3195 | return kvm_xen_write_hypercall_page(vcpu, data); |
1232f8e6 | 3196 | |
15c4a640 | 3197 | switch (msr) { |
2e32b719 | 3198 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
3199 | case MSR_IA32_UCODE_WRITE: |
3200 | case MSR_VM_HSAVE_PA: | |
3201 | case MSR_AMD64_PATCH_LOADER: | |
3202 | case MSR_AMD64_BU_CFG2: | |
405a353a | 3203 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3204 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
3205 | break; |
3206 | ||
518e7b94 WL |
3207 | case MSR_IA32_UCODE_REV: |
3208 | if (msr_info->host_initiated) | |
3209 | vcpu->arch.microcode_version = data; | |
3210 | break; | |
0cf9135b SC |
3211 | case MSR_IA32_ARCH_CAPABILITIES: |
3212 | if (!msr_info->host_initiated) | |
3213 | return 1; | |
3214 | vcpu->arch.arch_capabilities = data; | |
3215 | break; | |
d574c539 VK |
3216 | case MSR_IA32_PERF_CAPABILITIES: { |
3217 | struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; | |
3218 | ||
3219 | if (!msr_info->host_initiated) | |
3220 | return 1; | |
3221 | if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) | |
3222 | return 1; | |
3223 | if (data & ~msr_ent.data) | |
3224 | return 1; | |
3225 | ||
3226 | vcpu->arch.perf_capabilities = data; | |
3227 | ||
3228 | return 0; | |
3229 | } | |
15c4a640 | 3230 | case MSR_EFER: |
11988499 | 3231 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
3232 | case MSR_K7_HWCR: |
3233 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 3234 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 3235 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
3236 | |
3237 | /* Handle McStatusWrEn */ | |
3238 | if (data == BIT_ULL(18)) { | |
3239 | vcpu->arch.msr_hwcr = data; | |
3240 | } else if (data != 0) { | |
a737f256 CD |
3241 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
3242 | data); | |
8f1589d9 AP |
3243 | return 1; |
3244 | } | |
15c4a640 | 3245 | break; |
f7c6d140 AP |
3246 | case MSR_FAM10H_MMIO_CONF_BASE: |
3247 | if (data != 0) { | |
a737f256 CD |
3248 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
3249 | "0x%llx\n", data); | |
f7c6d140 AP |
3250 | return 1; |
3251 | } | |
15c4a640 | 3252 | break; |
9ba075a6 | 3253 | case 0x200 ... 0x2ff: |
ff53604b | 3254 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 3255 | case MSR_IA32_APICBASE: |
58cb628d | 3256 | return kvm_set_apic_base(vcpu, msr_info); |
bf10bd0b | 3257 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
0105d1a5 | 3258 | return kvm_x2apic_msr_write(vcpu, msr, data); |
09141ec0 | 3259 | case MSR_IA32_TSC_DEADLINE: |
a3e06bbe LJ |
3260 | kvm_set_lapic_tscdeadline_msr(vcpu, data); |
3261 | break; | |
ba904635 | 3262 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 3263 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 3264 | if (!msr_info->host_initiated) { |
d913b904 | 3265 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 3266 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
3267 | } |
3268 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
3269 | } | |
3270 | break; | |
15c4a640 | 3271 | case MSR_IA32_MISC_ENABLE: |
511a8556 WL |
3272 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
3273 | ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { | |
3274 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) | |
3275 | return 1; | |
3276 | vcpu->arch.ia32_misc_enable_msr = data; | |
aedbaf4f | 3277 | kvm_update_cpuid_runtime(vcpu); |
511a8556 WL |
3278 | } else { |
3279 | vcpu->arch.ia32_misc_enable_msr = data; | |
3280 | } | |
15c4a640 | 3281 | break; |
64d60670 PB |
3282 | case MSR_IA32_SMBASE: |
3283 | if (!msr_info->host_initiated) | |
3284 | return 1; | |
3285 | vcpu->arch.smbase = data; | |
3286 | break; | |
73f624f4 PB |
3287 | case MSR_IA32_POWER_CTL: |
3288 | vcpu->arch.msr_ia32_power_ctl = data; | |
3289 | break; | |
dd259935 | 3290 | case MSR_IA32_TSC: |
0c899c25 PB |
3291 | if (msr_info->host_initiated) { |
3292 | kvm_synchronize_tsc(vcpu, data); | |
3293 | } else { | |
9b399dfd | 3294 | u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; |
0c899c25 PB |
3295 | adjust_tsc_offset_guest(vcpu, adj); |
3296 | vcpu->arch.ia32_tsc_adjust_msr += adj; | |
3297 | } | |
dd259935 | 3298 | break; |
864e2ab2 AL |
3299 | case MSR_IA32_XSS: |
3300 | if (!msr_info->host_initiated && | |
3301 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3302 | return 1; | |
3303 | /* | |
a1bead2a SC |
3304 | * KVM supports exposing PT to the guest, but does not support |
3305 | * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than | |
3306 | * XSAVES/XRSTORS to save/restore PT MSRs. | |
864e2ab2 | 3307 | */ |
408e9a31 | 3308 | if (data & ~supported_xss) |
864e2ab2 AL |
3309 | return 1; |
3310 | vcpu->arch.ia32_xss = data; | |
3311 | break; | |
52797bf9 LA |
3312 | case MSR_SMI_COUNT: |
3313 | if (!msr_info->host_initiated) | |
3314 | return 1; | |
3315 | vcpu->arch.smi_count = data; | |
3316 | break; | |
11c6bffa | 3317 | case MSR_KVM_WALL_CLOCK_NEW: |
66570e96 OU |
3318 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3319 | return 1; | |
3320 | ||
629b5348 JM |
3321 | vcpu->kvm->arch.wall_clock = data; |
3322 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
66570e96 | 3323 | break; |
18068523 | 3324 | case MSR_KVM_WALL_CLOCK: |
66570e96 OU |
3325 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3326 | return 1; | |
3327 | ||
629b5348 JM |
3328 | vcpu->kvm->arch.wall_clock = data; |
3329 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
18068523 | 3330 | break; |
11c6bffa | 3331 | case MSR_KVM_SYSTEM_TIME_NEW: |
66570e96 OU |
3332 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3333 | return 1; | |
3334 | ||
5b9bb0eb OU |
3335 | kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); |
3336 | break; | |
3337 | case MSR_KVM_SYSTEM_TIME: | |
66570e96 OU |
3338 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3339 | return 1; | |
3340 | ||
3341 | kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); | |
18068523 | 3342 | break; |
344d9588 | 3343 | case MSR_KVM_ASYNC_PF_EN: |
66570e96 OU |
3344 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3345 | return 1; | |
3346 | ||
344d9588 GN |
3347 | if (kvm_pv_enable_async_pf(vcpu, data)) |
3348 | return 1; | |
3349 | break; | |
2635b5c4 | 3350 | case MSR_KVM_ASYNC_PF_INT: |
66570e96 OU |
3351 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3352 | return 1; | |
3353 | ||
2635b5c4 VK |
3354 | if (kvm_pv_enable_async_pf_int(vcpu, data)) |
3355 | return 1; | |
3356 | break; | |
557a961a | 3357 | case MSR_KVM_ASYNC_PF_ACK: |
66570e96 OU |
3358 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3359 | return 1; | |
557a961a VK |
3360 | if (data & 0x1) { |
3361 | vcpu->arch.apf.pageready_pending = false; | |
3362 | kvm_check_async_pf_completion(vcpu); | |
3363 | } | |
3364 | break; | |
c9aaa895 | 3365 | case MSR_KVM_STEAL_TIME: |
66570e96 OU |
3366 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3367 | return 1; | |
c9aaa895 GC |
3368 | |
3369 | if (unlikely(!sched_info_on())) | |
3370 | return 1; | |
3371 | ||
3372 | if (data & KVM_STEAL_RESERVED_MASK) | |
3373 | return 1; | |
3374 | ||
c9aaa895 GC |
3375 | vcpu->arch.st.msr_val = data; |
3376 | ||
3377 | if (!(data & KVM_MSR_ENABLED)) | |
3378 | break; | |
3379 | ||
c9aaa895 GC |
3380 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
3381 | ||
3382 | break; | |
ae7a2a3f | 3383 | case MSR_KVM_PV_EOI_EN: |
66570e96 OU |
3384 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3385 | return 1; | |
3386 | ||
72bbf935 | 3387 | if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
3388 | return 1; |
3389 | break; | |
c9aaa895 | 3390 | |
2d5ba19b | 3391 | case MSR_KVM_POLL_CONTROL: |
66570e96 OU |
3392 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3393 | return 1; | |
3394 | ||
2d5ba19b MT |
3395 | /* only enable bit supported */ |
3396 | if (data & (-1ULL << 1)) | |
3397 | return 1; | |
3398 | ||
3399 | vcpu->arch.msr_kvm_poll_control = data; | |
3400 | break; | |
3401 | ||
890ca9ae HY |
3402 | case MSR_IA32_MCG_CTL: |
3403 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3404 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 3405 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 3406 | |
6912ac32 WH |
3407 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
3408 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
df561f66 GS |
3409 | pr = true; |
3410 | fallthrough; | |
6912ac32 WH |
3411 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3412 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3413 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3414 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
3415 | |
3416 | if (pr || data != 0) | |
a737f256 CD |
3417 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
3418 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 3419 | break; |
84e0cefa JS |
3420 | case MSR_K7_CLK_CTL: |
3421 | /* | |
3422 | * Ignore all writes to this no longer documented MSR. | |
3423 | * Writes are only relevant for old K7 processors, | |
3424 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 3425 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
3426 | * affected processor models on the command line, hence |
3427 | * the need to ignore the workaround. | |
3428 | */ | |
3429 | break; | |
55cd8e5a | 3430 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3431 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3432 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3433 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3434 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3435 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3436 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3437 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3438 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
3439 | return kvm_hv_set_msr_common(vcpu, msr, data, |
3440 | msr_info->host_initiated); | |
91c9c3ed | 3441 | case MSR_IA32_BBL_CR_CTL3: |
3442 | /* Drop writes to this legacy MSR -- see rdmsr | |
3443 | * counterpart for further detail. | |
3444 | */ | |
fab0aa3b EM |
3445 | if (report_ignored_msrs) |
3446 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
3447 | msr, data); | |
91c9c3ed | 3448 | break; |
2b036c6b | 3449 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3450 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3451 | return 1; |
3452 | vcpu->arch.osvw.length = data; | |
3453 | break; | |
3454 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3455 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3456 | return 1; |
3457 | vcpu->arch.osvw.status = data; | |
3458 | break; | |
db2336a8 KH |
3459 | case MSR_PLATFORM_INFO: |
3460 | if (!msr_info->host_initiated || | |
db2336a8 KH |
3461 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
3462 | cpuid_fault_enabled(vcpu))) | |
3463 | return 1; | |
3464 | vcpu->arch.msr_platform_info = data; | |
3465 | break; | |
3466 | case MSR_MISC_FEATURES_ENABLES: | |
3467 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
3468 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
3469 | !supports_cpuid_fault(vcpu))) | |
3470 | return 1; | |
3471 | vcpu->arch.msr_misc_features_enables = data; | |
3472 | break; | |
15c4a640 | 3473 | default: |
c6702c9d | 3474 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3475 | return kvm_pmu_set_msr(vcpu, msr_info); |
6abe9c13 | 3476 | return KVM_MSR_RET_INVALID; |
15c4a640 CO |
3477 | } |
3478 | return 0; | |
3479 | } | |
3480 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
3481 | ||
44883f01 | 3482 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
3483 | { |
3484 | u64 data; | |
890ca9ae HY |
3485 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3486 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
3487 | |
3488 | switch (msr) { | |
15c4a640 CO |
3489 | case MSR_IA32_P5_MC_ADDR: |
3490 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
3491 | data = 0; |
3492 | break; | |
15c4a640 | 3493 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
3494 | data = vcpu->arch.mcg_cap; |
3495 | break; | |
c7ac679c | 3496 | case MSR_IA32_MCG_CTL: |
44883f01 | 3497 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
3498 | return 1; |
3499 | data = vcpu->arch.mcg_ctl; | |
3500 | break; | |
3501 | case MSR_IA32_MCG_STATUS: | |
3502 | data = vcpu->arch.mcg_status; | |
3503 | break; | |
3504 | default: | |
3505 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3506 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3507 | u32 offset = array_index_nospec( |
3508 | msr - MSR_IA32_MC0_CTL, | |
3509 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3510 | ||
890ca9ae HY |
3511 | data = vcpu->arch.mce_banks[offset]; |
3512 | break; | |
3513 | } | |
3514 | return 1; | |
3515 | } | |
3516 | *pdata = data; | |
3517 | return 0; | |
3518 | } | |
3519 | ||
609e36d3 | 3520 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 3521 | { |
609e36d3 | 3522 | switch (msr_info->index) { |
890ca9ae | 3523 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 3524 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
3525 | case MSR_IA32_LASTBRANCHFROMIP: |
3526 | case MSR_IA32_LASTBRANCHTOIP: | |
3527 | case MSR_IA32_LASTINTFROMIP: | |
3528 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd | 3529 | case MSR_K8_SYSCFG: |
3afb1121 PB |
3530 | case MSR_K8_TSEG_ADDR: |
3531 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 3532 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 3533 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 3534 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 3535 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 3536 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 3537 | case MSR_IA32_PERF_CTL: |
405a353a | 3538 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3539 | case MSR_F15H_EX_CFG: |
2ca1a06a VS |
3540 | /* |
3541 | * Intel Sandy Bridge CPUs must support the RAPL (running average power | |
3542 | * limit) MSRs. Just return 0, as we do not want to expose the host | |
3543 | * data here. Do not conditionalize this on CPUID, as KVM does not do | |
3544 | * so for existing CPU-specific MSRs. | |
3545 | */ | |
3546 | case MSR_RAPL_POWER_UNIT: | |
3547 | case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ | |
3548 | case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ | |
3549 | case MSR_PKG_ENERGY_STATUS: /* Total package */ | |
3550 | case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ | |
609e36d3 | 3551 | msr_info->data = 0; |
15c4a640 | 3552 | break; |
c51eb52b | 3553 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
c28fa560 VK |
3554 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
3555 | return kvm_pmu_get_msr(vcpu, msr_info); | |
3556 | if (!msr_info->host_initiated) | |
3557 | return 1; | |
3558 | msr_info->data = 0; | |
3559 | break; | |
6912ac32 WH |
3560 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3561 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
3562 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
3563 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3564 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3565 | return kvm_pmu_get_msr(vcpu, msr_info); |
609e36d3 | 3566 | msr_info->data = 0; |
5753785f | 3567 | break; |
742bc670 | 3568 | case MSR_IA32_UCODE_REV: |
518e7b94 | 3569 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 3570 | break; |
0cf9135b SC |
3571 | case MSR_IA32_ARCH_CAPABILITIES: |
3572 | if (!msr_info->host_initiated && | |
3573 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3574 | return 1; | |
3575 | msr_info->data = vcpu->arch.arch_capabilities; | |
3576 | break; | |
d574c539 VK |
3577 | case MSR_IA32_PERF_CAPABILITIES: |
3578 | if (!msr_info->host_initiated && | |
3579 | !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) | |
3580 | return 1; | |
3581 | msr_info->data = vcpu->arch.perf_capabilities; | |
3582 | break; | |
73f624f4 PB |
3583 | case MSR_IA32_POWER_CTL: |
3584 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
3585 | break; | |
cc5b54dd ML |
3586 | case MSR_IA32_TSC: { |
3587 | /* | |
3588 | * Intel SDM states that MSR_IA32_TSC read adds the TSC offset | |
3589 | * even when not intercepted. AMD manual doesn't explicitly | |
3590 | * state this but appears to behave the same. | |
3591 | * | |
ee6fa053 | 3592 | * On userspace reads and writes, however, we unconditionally |
c0623f5e | 3593 | * return L1's TSC value to ensure backwards-compatible |
ee6fa053 | 3594 | * behavior for migration. |
cc5b54dd | 3595 | */ |
fe3eb504 | 3596 | u64 offset, ratio; |
cc5b54dd | 3597 | |
fe3eb504 IS |
3598 | if (msr_info->host_initiated) { |
3599 | offset = vcpu->arch.l1_tsc_offset; | |
3600 | ratio = vcpu->arch.l1_tsc_scaling_ratio; | |
3601 | } else { | |
3602 | offset = vcpu->arch.tsc_offset; | |
3603 | ratio = vcpu->arch.tsc_scaling_ratio; | |
3604 | } | |
3605 | ||
3606 | msr_info->data = kvm_scale_tsc(vcpu, rdtsc(), ratio) + offset; | |
dd259935 | 3607 | break; |
cc5b54dd | 3608 | } |
9ba075a6 | 3609 | case MSR_MTRRcap: |
9ba075a6 | 3610 | case 0x200 ... 0x2ff: |
ff53604b | 3611 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 3612 | case 0xcd: /* fsb frequency */ |
609e36d3 | 3613 | msr_info->data = 3; |
15c4a640 | 3614 | break; |
7b914098 JS |
3615 | /* |
3616 | * MSR_EBC_FREQUENCY_ID | |
3617 | * Conservative value valid for even the basic CPU models. | |
3618 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
3619 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
3620 | * and 266MHz for model 3, or 4. Set Core Clock | |
3621 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
3622 | * 31:24) even though these are only valid for CPU | |
3623 | * models > 2, however guests may end up dividing or | |
3624 | * multiplying by zero otherwise. | |
3625 | */ | |
3626 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 3627 | msr_info->data = 1 << 24; |
7b914098 | 3628 | break; |
15c4a640 | 3629 | case MSR_IA32_APICBASE: |
609e36d3 | 3630 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 3631 | break; |
bf10bd0b | 3632 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
609e36d3 | 3633 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
09141ec0 | 3634 | case MSR_IA32_TSC_DEADLINE: |
609e36d3 | 3635 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 3636 | break; |
ba904635 | 3637 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 3638 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 3639 | break; |
15c4a640 | 3640 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 3641 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 3642 | break; |
64d60670 PB |
3643 | case MSR_IA32_SMBASE: |
3644 | if (!msr_info->host_initiated) | |
3645 | return 1; | |
3646 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 3647 | break; |
52797bf9 LA |
3648 | case MSR_SMI_COUNT: |
3649 | msr_info->data = vcpu->arch.smi_count; | |
3650 | break; | |
847f0ad8 AG |
3651 | case MSR_IA32_PERF_STATUS: |
3652 | /* TSC increment by tick */ | |
609e36d3 | 3653 | msr_info->data = 1000ULL; |
847f0ad8 | 3654 | /* CPU multiplier */ |
b0996ae4 | 3655 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 3656 | break; |
15c4a640 | 3657 | case MSR_EFER: |
609e36d3 | 3658 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 3659 | break; |
18068523 | 3660 | case MSR_KVM_WALL_CLOCK: |
1930e5dd OU |
3661 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3662 | return 1; | |
3663 | ||
3664 | msr_info->data = vcpu->kvm->arch.wall_clock; | |
3665 | break; | |
11c6bffa | 3666 | case MSR_KVM_WALL_CLOCK_NEW: |
1930e5dd OU |
3667 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3668 | return 1; | |
3669 | ||
609e36d3 | 3670 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
3671 | break; |
3672 | case MSR_KVM_SYSTEM_TIME: | |
1930e5dd OU |
3673 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3674 | return 1; | |
3675 | ||
3676 | msr_info->data = vcpu->arch.time; | |
3677 | break; | |
11c6bffa | 3678 | case MSR_KVM_SYSTEM_TIME_NEW: |
1930e5dd OU |
3679 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3680 | return 1; | |
3681 | ||
609e36d3 | 3682 | msr_info->data = vcpu->arch.time; |
18068523 | 3683 | break; |
344d9588 | 3684 | case MSR_KVM_ASYNC_PF_EN: |
1930e5dd OU |
3685 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3686 | return 1; | |
3687 | ||
2635b5c4 VK |
3688 | msr_info->data = vcpu->arch.apf.msr_en_val; |
3689 | break; | |
3690 | case MSR_KVM_ASYNC_PF_INT: | |
1930e5dd OU |
3691 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3692 | return 1; | |
3693 | ||
2635b5c4 | 3694 | msr_info->data = vcpu->arch.apf.msr_int_val; |
344d9588 | 3695 | break; |
557a961a | 3696 | case MSR_KVM_ASYNC_PF_ACK: |
1930e5dd OU |
3697 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3698 | return 1; | |
3699 | ||
557a961a VK |
3700 | msr_info->data = 0; |
3701 | break; | |
c9aaa895 | 3702 | case MSR_KVM_STEAL_TIME: |
1930e5dd OU |
3703 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3704 | return 1; | |
3705 | ||
609e36d3 | 3706 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 3707 | break; |
1d92128f | 3708 | case MSR_KVM_PV_EOI_EN: |
1930e5dd OU |
3709 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3710 | return 1; | |
3711 | ||
609e36d3 | 3712 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 3713 | break; |
2d5ba19b | 3714 | case MSR_KVM_POLL_CONTROL: |
1930e5dd OU |
3715 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3716 | return 1; | |
3717 | ||
2d5ba19b MT |
3718 | msr_info->data = vcpu->arch.msr_kvm_poll_control; |
3719 | break; | |
890ca9ae HY |
3720 | case MSR_IA32_P5_MC_ADDR: |
3721 | case MSR_IA32_P5_MC_TYPE: | |
3722 | case MSR_IA32_MCG_CAP: | |
3723 | case MSR_IA32_MCG_CTL: | |
3724 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3725 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
3726 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
3727 | msr_info->host_initiated); | |
864e2ab2 AL |
3728 | case MSR_IA32_XSS: |
3729 | if (!msr_info->host_initiated && | |
3730 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3731 | return 1; | |
3732 | msr_info->data = vcpu->arch.ia32_xss; | |
3733 | break; | |
84e0cefa JS |
3734 | case MSR_K7_CLK_CTL: |
3735 | /* | |
3736 | * Provide expected ramp-up count for K7. All other | |
3737 | * are set to zero, indicating minimum divisors for | |
3738 | * every field. | |
3739 | * | |
3740 | * This prevents guest kernels on AMD host with CPU | |
3741 | * type 6, model 8 and higher from exploding due to | |
3742 | * the rdmsr failing. | |
3743 | */ | |
609e36d3 | 3744 | msr_info->data = 0x20000000; |
84e0cefa | 3745 | break; |
55cd8e5a | 3746 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3747 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3748 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3749 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3750 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3751 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3752 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3753 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3754 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 3755 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
3756 | msr_info->index, &msr_info->data, |
3757 | msr_info->host_initiated); | |
91c9c3ed | 3758 | case MSR_IA32_BBL_CR_CTL3: |
3759 | /* This legacy MSR exists but isn't fully documented in current | |
3760 | * silicon. It is however accessed by winxp in very narrow | |
3761 | * scenarios where it sets bit #19, itself documented as | |
3762 | * a "reserved" bit. Best effort attempt to source coherent | |
3763 | * read data here should the balance of the register be | |
3764 | * interpreted by the guest: | |
3765 | * | |
3766 | * L2 cache control register 3: 64GB range, 256KB size, | |
3767 | * enabled, latency 0x1, configured | |
3768 | */ | |
609e36d3 | 3769 | msr_info->data = 0xbe702111; |
91c9c3ed | 3770 | break; |
2b036c6b | 3771 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3772 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3773 | return 1; |
609e36d3 | 3774 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
3775 | break; |
3776 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3777 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3778 | return 1; |
609e36d3 | 3779 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 3780 | break; |
db2336a8 | 3781 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
3782 | if (!msr_info->host_initiated && |
3783 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
3784 | return 1; | |
db2336a8 KH |
3785 | msr_info->data = vcpu->arch.msr_platform_info; |
3786 | break; | |
3787 | case MSR_MISC_FEATURES_ENABLES: | |
3788 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
3789 | break; | |
191c8137 BP |
3790 | case MSR_K7_HWCR: |
3791 | msr_info->data = vcpu->arch.msr_hwcr; | |
3792 | break; | |
15c4a640 | 3793 | default: |
c6702c9d | 3794 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3795 | return kvm_pmu_get_msr(vcpu, msr_info); |
6abe9c13 | 3796 | return KVM_MSR_RET_INVALID; |
15c4a640 | 3797 | } |
15c4a640 CO |
3798 | return 0; |
3799 | } | |
3800 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
3801 | ||
313a3dc7 CO |
3802 | /* |
3803 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
3804 | * | |
3805 | * @return number of msrs set successfully. | |
3806 | */ | |
3807 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
3808 | struct kvm_msr_entry *entries, | |
3809 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3810 | unsigned index, u64 *data)) | |
3811 | { | |
801e459a | 3812 | int i; |
313a3dc7 | 3813 | |
313a3dc7 CO |
3814 | for (i = 0; i < msrs->nmsrs; ++i) |
3815 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
3816 | break; | |
3817 | ||
313a3dc7 CO |
3818 | return i; |
3819 | } | |
3820 | ||
3821 | /* | |
3822 | * Read or write a bunch of msrs. Parameters are user addresses. | |
3823 | * | |
3824 | * @return number of msrs set successfully. | |
3825 | */ | |
3826 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
3827 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3828 | unsigned index, u64 *data), | |
3829 | int writeback) | |
3830 | { | |
3831 | struct kvm_msrs msrs; | |
3832 | struct kvm_msr_entry *entries; | |
3833 | int r, n; | |
3834 | unsigned size; | |
3835 | ||
3836 | r = -EFAULT; | |
0e96f31e | 3837 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
3838 | goto out; |
3839 | ||
3840 | r = -E2BIG; | |
3841 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
3842 | goto out; | |
3843 | ||
313a3dc7 | 3844 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
3845 | entries = memdup_user(user_msrs->entries, size); |
3846 | if (IS_ERR(entries)) { | |
3847 | r = PTR_ERR(entries); | |
313a3dc7 | 3848 | goto out; |
ff5c2c03 | 3849 | } |
313a3dc7 CO |
3850 | |
3851 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
3852 | if (r < 0) | |
3853 | goto out_free; | |
3854 | ||
3855 | r = -EFAULT; | |
3856 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
3857 | goto out_free; | |
3858 | ||
3859 | r = n; | |
3860 | ||
3861 | out_free: | |
7a73c028 | 3862 | kfree(entries); |
313a3dc7 CO |
3863 | out: |
3864 | return r; | |
3865 | } | |
3866 | ||
4d5422ce WL |
3867 | static inline bool kvm_can_mwait_in_guest(void) |
3868 | { | |
3869 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
3870 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
3871 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
3872 | } |
3873 | ||
c21d54f0 VK |
3874 | static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, |
3875 | struct kvm_cpuid2 __user *cpuid_arg) | |
3876 | { | |
3877 | struct kvm_cpuid2 cpuid; | |
3878 | int r; | |
3879 | ||
3880 | r = -EFAULT; | |
3881 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
3882 | return r; | |
3883 | ||
3884 | r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
3885 | if (r) | |
3886 | return r; | |
3887 | ||
3888 | r = -EFAULT; | |
3889 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
3890 | return r; | |
3891 | ||
3892 | return 0; | |
3893 | } | |
3894 | ||
784aa3d7 | 3895 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 3896 | { |
4d5422ce | 3897 | int r = 0; |
018d00d2 ZX |
3898 | |
3899 | switch (ext) { | |
3900 | case KVM_CAP_IRQCHIP: | |
3901 | case KVM_CAP_HLT: | |
3902 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 3903 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 3904 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 3905 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 3906 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 3907 | case KVM_CAP_PIT: |
a28e4f5a | 3908 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 3909 | case KVM_CAP_MP_STATE: |
ed848624 | 3910 | case KVM_CAP_SYNC_MMU: |
a355c85c | 3911 | case KVM_CAP_USER_NMI: |
52d939a0 | 3912 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 3913 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 3914 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 3915 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 3916 | case KVM_CAP_PIT2: |
e9f42757 | 3917 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 3918 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
3cfc3092 | 3919 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 3920 | case KVM_CAP_HYPERV: |
10388a07 | 3921 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 3922 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 3923 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 3924 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 3925 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 3926 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 3927 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 3928 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 3929 | case KVM_CAP_HYPERV_CPUID: |
644f7067 | 3930 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
c21d54f0 | 3931 | case KVM_CAP_SYS_HYPERV_CPUID: |
ab9f4ecb | 3932 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 3933 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 3934 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 3935 | case KVM_CAP_XSAVE: |
344d9588 | 3936 | case KVM_CAP_ASYNC_PF: |
72de5fa4 | 3937 | case KVM_CAP_ASYNC_PF_INT: |
92a1f12d | 3938 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 3939 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 3940 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 3941 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 3942 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 3943 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 3944 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 3945 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 3946 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 3947 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 3948 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 3949 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 3950 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 3951 | case KVM_CAP_EXCEPTION_PAYLOAD: |
b9b2782c | 3952 | case KVM_CAP_SET_GUEST_DEBUG: |
1aa561b1 | 3953 | case KVM_CAP_LAST_CPU: |
1ae09954 | 3954 | case KVM_CAP_X86_USER_SPACE_MSR: |
1a155254 | 3955 | case KVM_CAP_X86_MSR_FILTER: |
66570e96 | 3956 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
fe7e9488 SC |
3957 | #ifdef CONFIG_X86_SGX_KVM |
3958 | case KVM_CAP_SGX_ATTRIBUTE: | |
3959 | #endif | |
54526d1f | 3960 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
6dba9403 | 3961 | case KVM_CAP_SREGS2: |
018d00d2 ZX |
3962 | r = 1; |
3963 | break; | |
7e582ccb ML |
3964 | case KVM_CAP_SET_GUEST_DEBUG2: |
3965 | return KVM_GUESTDBG_VALID_MASK; | |
b59b153d | 3966 | #ifdef CONFIG_KVM_XEN |
23200b7a JM |
3967 | case KVM_CAP_XEN_HVM: |
3968 | r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | | |
8d4e7e80 DW |
3969 | KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | |
3970 | KVM_XEN_HVM_CONFIG_SHARED_INFO; | |
30b5c851 DW |
3971 | if (sched_info_on()) |
3972 | r |= KVM_XEN_HVM_CONFIG_RUNSTATE; | |
23200b7a | 3973 | break; |
b59b153d | 3974 | #endif |
01643c51 KH |
3975 | case KVM_CAP_SYNC_REGS: |
3976 | r = KVM_SYNC_X86_VALID_FIELDS; | |
3977 | break; | |
e3fd9a93 PB |
3978 | case KVM_CAP_ADJUST_CLOCK: |
3979 | r = KVM_CLOCK_TSC_STABLE; | |
3980 | break; | |
4d5422ce | 3981 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
3982 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
3983 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
3984 | if(kvm_can_mwait_in_guest()) |
3985 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 3986 | break; |
6d396b55 PB |
3987 | case KVM_CAP_X86_SMM: |
3988 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
3989 | * and SMM handlers might indeed rely on 4G segment limits, | |
3990 | * so do not report SMM to be available if real mode is | |
3991 | * emulated via vm86 mode. Still, do not go to great lengths | |
3992 | * to avoid userspace's usage of the feature, because it is a | |
3993 | * fringe case that is not enabled except via specific settings | |
3994 | * of the module parameters. | |
3995 | */ | |
b3646477 | 3996 | r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); |
6d396b55 | 3997 | break; |
774ead3a | 3998 | case KVM_CAP_VAPIC: |
b3646477 | 3999 | r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); |
774ead3a | 4000 | break; |
f725230a | 4001 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
4002 | r = KVM_SOFT_MAX_VCPUS; |
4003 | break; | |
4004 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
4005 | r = KVM_MAX_VCPUS; |
4006 | break; | |
a86cb413 TH |
4007 | case KVM_CAP_MAX_VCPU_ID: |
4008 | r = KVM_MAX_VCPU_ID; | |
4009 | break; | |
a68a6a72 MT |
4010 | case KVM_CAP_PV_MMU: /* obsolete */ |
4011 | r = 0; | |
2f333bcb | 4012 | break; |
890ca9ae HY |
4013 | case KVM_CAP_MCE: |
4014 | r = KVM_MAX_MCE_BANKS; | |
4015 | break; | |
2d5b5a66 | 4016 | case KVM_CAP_XCRS: |
d366bf7e | 4017 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 4018 | break; |
92a1f12d JR |
4019 | case KVM_CAP_TSC_CONTROL: |
4020 | r = kvm_has_tsc_control; | |
4021 | break; | |
37131313 RK |
4022 | case KVM_CAP_X2APIC_API: |
4023 | r = KVM_X2APIC_API_VALID_FLAGS; | |
4024 | break; | |
8fcc4b59 | 4025 | case KVM_CAP_NESTED_STATE: |
33b22172 PB |
4026 | r = kvm_x86_ops.nested_ops->get_state ? |
4027 | kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; | |
8fcc4b59 | 4028 | break; |
344c6c80 | 4029 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4030 | r = kvm_x86_ops.enable_direct_tlbflush != NULL; |
5a0165f6 VK |
4031 | break; |
4032 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
33b22172 | 4033 | r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; |
344c6c80 | 4034 | break; |
3edd6839 MG |
4035 | case KVM_CAP_SMALLER_MAXPHYADDR: |
4036 | r = (int) allow_smaller_maxphyaddr; | |
4037 | break; | |
004a0124 AJ |
4038 | case KVM_CAP_STEAL_TIME: |
4039 | r = sched_info_on(); | |
4040 | break; | |
fe6b6bc8 CQ |
4041 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
4042 | if (kvm_has_bus_lock_exit) | |
4043 | r = KVM_BUS_LOCK_DETECTION_OFF | | |
4044 | KVM_BUS_LOCK_DETECTION_EXIT; | |
4045 | else | |
4046 | r = 0; | |
4047 | break; | |
018d00d2 | 4048 | default: |
018d00d2 ZX |
4049 | break; |
4050 | } | |
4051 | return r; | |
4052 | ||
4053 | } | |
4054 | ||
043405e1 CO |
4055 | long kvm_arch_dev_ioctl(struct file *filp, |
4056 | unsigned int ioctl, unsigned long arg) | |
4057 | { | |
4058 | void __user *argp = (void __user *)arg; | |
4059 | long r; | |
4060 | ||
4061 | switch (ioctl) { | |
4062 | case KVM_GET_MSR_INDEX_LIST: { | |
4063 | struct kvm_msr_list __user *user_msr_list = argp; | |
4064 | struct kvm_msr_list msr_list; | |
4065 | unsigned n; | |
4066 | ||
4067 | r = -EFAULT; | |
0e96f31e | 4068 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
4069 | goto out; |
4070 | n = msr_list.nmsrs; | |
62ef68bb | 4071 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 4072 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
4073 | goto out; |
4074 | r = -E2BIG; | |
e125e7b6 | 4075 | if (n < msr_list.nmsrs) |
043405e1 CO |
4076 | goto out; |
4077 | r = -EFAULT; | |
4078 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
4079 | num_msrs_to_save * sizeof(u32))) | |
4080 | goto out; | |
e125e7b6 | 4081 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 4082 | &emulated_msrs, |
62ef68bb | 4083 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
4084 | goto out; |
4085 | r = 0; | |
4086 | break; | |
4087 | } | |
9c15bb1d BP |
4088 | case KVM_GET_SUPPORTED_CPUID: |
4089 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
4090 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
4091 | struct kvm_cpuid2 cpuid; | |
4092 | ||
4093 | r = -EFAULT; | |
0e96f31e | 4094 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 4095 | goto out; |
9c15bb1d BP |
4096 | |
4097 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
4098 | ioctl); | |
674eea0f AK |
4099 | if (r) |
4100 | goto out; | |
4101 | ||
4102 | r = -EFAULT; | |
0e96f31e | 4103 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
4104 | goto out; |
4105 | r = 0; | |
4106 | break; | |
4107 | } | |
cf6c26ec | 4108 | case KVM_X86_GET_MCE_CAP_SUPPORTED: |
890ca9ae | 4109 | r = -EFAULT; |
c45dcc71 AR |
4110 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
4111 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
4112 | goto out; |
4113 | r = 0; | |
4114 | break; | |
801e459a TL |
4115 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
4116 | struct kvm_msr_list __user *user_msr_list = argp; | |
4117 | struct kvm_msr_list msr_list; | |
4118 | unsigned int n; | |
4119 | ||
4120 | r = -EFAULT; | |
4121 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
4122 | goto out; | |
4123 | n = msr_list.nmsrs; | |
4124 | msr_list.nmsrs = num_msr_based_features; | |
4125 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
4126 | goto out; | |
4127 | r = -E2BIG; | |
4128 | if (n < msr_list.nmsrs) | |
4129 | goto out; | |
4130 | r = -EFAULT; | |
4131 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
4132 | num_msr_based_features * sizeof(u32))) | |
4133 | goto out; | |
4134 | r = 0; | |
4135 | break; | |
4136 | } | |
4137 | case KVM_GET_MSRS: | |
4138 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
4139 | break; | |
c21d54f0 VK |
4140 | case KVM_GET_SUPPORTED_HV_CPUID: |
4141 | r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); | |
4142 | break; | |
043405e1 CO |
4143 | default: |
4144 | r = -EINVAL; | |
cf6c26ec | 4145 | break; |
043405e1 CO |
4146 | } |
4147 | out: | |
4148 | return r; | |
4149 | } | |
4150 | ||
f5f48ee1 SY |
4151 | static void wbinvd_ipi(void *garbage) |
4152 | { | |
4153 | wbinvd(); | |
4154 | } | |
4155 | ||
4156 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4157 | { | |
e0f0bbc5 | 4158 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
4159 | } |
4160 | ||
313a3dc7 CO |
4161 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
4162 | { | |
f5f48ee1 SY |
4163 | /* Address WBINVD may be executed by guest */ |
4164 | if (need_emulate_wbinvd(vcpu)) { | |
b3646477 | 4165 | if (static_call(kvm_x86_has_wbinvd_exit)()) |
f5f48ee1 SY |
4166 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); |
4167 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
4168 | smp_call_function_single(vcpu->cpu, | |
4169 | wbinvd_ipi, NULL, 1); | |
4170 | } | |
4171 | ||
b3646477 | 4172 | static_call(kvm_x86_vcpu_load)(vcpu, cpu); |
8f6055cb | 4173 | |
37486135 BM |
4174 | /* Save host pkru register if supported */ |
4175 | vcpu->arch.host_pkru = read_pkru(); | |
4176 | ||
0dd6a6ed ZA |
4177 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
4178 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
4179 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
4180 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 4181 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 4182 | } |
8f6055cb | 4183 | |
b0c39dc6 | 4184 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 4185 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 4186 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
4187 | if (tsc_delta < 0) |
4188 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 4189 | |
b0c39dc6 | 4190 | if (kvm_check_tsc_unstable()) { |
9b399dfd | 4191 | u64 offset = kvm_compute_l1_tsc_offset(vcpu, |
b183aa58 | 4192 | vcpu->arch.last_guest_tsc); |
a545ab6a | 4193 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 4194 | vcpu->arch.tsc_catchup = 1; |
c285545f | 4195 | } |
a749e247 PB |
4196 | |
4197 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
4198 | kvm_lapic_restart_hv_timer(vcpu); | |
4199 | ||
d98d07ca MT |
4200 | /* |
4201 | * On a host with synchronized TSC, there is no need to update | |
4202 | * kvmclock on vcpu->cpu migration | |
4203 | */ | |
4204 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 4205 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 4206 | if (vcpu->cpu != cpu) |
1bd2009e | 4207 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 4208 | vcpu->cpu = cpu; |
6b7d7e76 | 4209 | } |
c9aaa895 | 4210 | |
c9aaa895 | 4211 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
4212 | } |
4213 | ||
0b9f6c46 PX |
4214 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
4215 | { | |
b0431382 BO |
4216 | struct kvm_host_map map; |
4217 | struct kvm_steal_time *st; | |
4218 | ||
0b9f6c46 PX |
4219 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
4220 | return; | |
4221 | ||
a6bd811f | 4222 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
4223 | return; |
4224 | ||
b0431382 BO |
4225 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, |
4226 | &vcpu->arch.st.cache, true)) | |
9c1a0744 | 4227 | return; |
b0431382 BO |
4228 | |
4229 | st = map.hva + | |
4230 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
0b9f6c46 | 4231 | |
a6bd811f | 4232 | st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; |
0b9f6c46 | 4233 | |
b0431382 | 4234 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); |
0b9f6c46 PX |
4235 | } |
4236 | ||
313a3dc7 CO |
4237 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
4238 | { | |
9c1a0744 WL |
4239 | int idx; |
4240 | ||
f1c6366e | 4241 | if (vcpu->preempted && !vcpu->arch.guest_state_protected) |
b3646477 | 4242 | vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); |
de63ad4c | 4243 | |
9c1a0744 WL |
4244 | /* |
4245 | * Take the srcu lock as memslots will be accessed to check the gfn | |
4246 | * cache generation against the memslots generation. | |
4247 | */ | |
4248 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
30b5c851 DW |
4249 | if (kvm_xen_msr_enabled(vcpu->kvm)) |
4250 | kvm_xen_runstate_set_preempted(vcpu); | |
4251 | else | |
4252 | kvm_steal_time_set_preempted(vcpu); | |
9c1a0744 | 4253 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
30b5c851 | 4254 | |
b3646477 | 4255 | static_call(kvm_x86_vcpu_put)(vcpu); |
4ea1636b | 4256 | vcpu->arch.last_host_tsc = rdtsc(); |
efdab992 | 4257 | /* |
f9dcf08e RK |
4258 | * If userspace has set any breakpoints or watchpoints, dr6 is restored |
4259 | * on every vmexit, but if not, we might have a stale dr6 from the | |
4260 | * guest. do_debug expects dr6 to be cleared after it runs, do the same. | |
efdab992 | 4261 | */ |
f9dcf08e | 4262 | set_debugreg(0, 6); |
313a3dc7 CO |
4263 | } |
4264 | ||
313a3dc7 CO |
4265 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
4266 | struct kvm_lapic_state *s) | |
4267 | { | |
fa59cc00 | 4268 | if (vcpu->arch.apicv_active) |
b3646477 | 4269 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
d62caabb | 4270 | |
a92e2543 | 4271 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
4272 | } |
4273 | ||
4274 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
4275 | struct kvm_lapic_state *s) | |
4276 | { | |
a92e2543 RK |
4277 | int r; |
4278 | ||
4279 | r = kvm_apic_set_state(vcpu, s); | |
4280 | if (r) | |
4281 | return r; | |
cb142eb7 | 4282 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
4283 | |
4284 | return 0; | |
4285 | } | |
4286 | ||
127a457a MG |
4287 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
4288 | { | |
71cc849b PB |
4289 | /* |
4290 | * We can accept userspace's request for interrupt injection | |
4291 | * as long as we have a place to store the interrupt number. | |
4292 | * The actual injection will happen when the CPU is able to | |
4293 | * deliver the interrupt. | |
4294 | */ | |
4295 | if (kvm_cpu_has_extint(vcpu)) | |
4296 | return false; | |
4297 | ||
4298 | /* Acknowledging ExtINT does not happen if LINT0 is masked. */ | |
127a457a MG |
4299 | return (!lapic_in_kernel(vcpu) || |
4300 | kvm_apic_accept_pic_intr(vcpu)); | |
4301 | } | |
4302 | ||
782d422b MG |
4303 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) |
4304 | { | |
4305 | return kvm_arch_interrupt_allowed(vcpu) && | |
782d422b MG |
4306 | kvm_cpu_accept_dm_intr(vcpu); |
4307 | } | |
4308 | ||
f77bc6a4 ZX |
4309 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
4310 | struct kvm_interrupt *irq) | |
4311 | { | |
02cdb50f | 4312 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 4313 | return -EINVAL; |
1c1a9ce9 SR |
4314 | |
4315 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
4316 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
4317 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4318 | return 0; | |
4319 | } | |
4320 | ||
4321 | /* | |
4322 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
4323 | * fail for in-kernel 8259. | |
4324 | */ | |
4325 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 4326 | return -ENXIO; |
f77bc6a4 | 4327 | |
1c1a9ce9 SR |
4328 | if (vcpu->arch.pending_external_vector != -1) |
4329 | return -EEXIST; | |
f77bc6a4 | 4330 | |
1c1a9ce9 | 4331 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 4332 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
4333 | return 0; |
4334 | } | |
4335 | ||
c4abb7c9 JK |
4336 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
4337 | { | |
c4abb7c9 | 4338 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
4339 | |
4340 | return 0; | |
4341 | } | |
4342 | ||
f077825a PB |
4343 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
4344 | { | |
64d60670 PB |
4345 | kvm_make_request(KVM_REQ_SMI, vcpu); |
4346 | ||
f077825a PB |
4347 | return 0; |
4348 | } | |
4349 | ||
b209749f AK |
4350 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
4351 | struct kvm_tpr_access_ctl *tac) | |
4352 | { | |
4353 | if (tac->flags) | |
4354 | return -EINVAL; | |
4355 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
4356 | return 0; | |
4357 | } | |
4358 | ||
890ca9ae HY |
4359 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
4360 | u64 mcg_cap) | |
4361 | { | |
4362 | int r; | |
4363 | unsigned bank_num = mcg_cap & 0xff, bank; | |
4364 | ||
4365 | r = -EINVAL; | |
c4e0e4ab | 4366 | if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) |
890ca9ae | 4367 | goto out; |
c45dcc71 | 4368 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
4369 | goto out; |
4370 | r = 0; | |
4371 | vcpu->arch.mcg_cap = mcg_cap; | |
4372 | /* Init IA32_MCG_CTL to all 1s */ | |
4373 | if (mcg_cap & MCG_CTL_P) | |
4374 | vcpu->arch.mcg_ctl = ~(u64)0; | |
4375 | /* Init IA32_MCi_CTL to all 1s */ | |
4376 | for (bank = 0; bank < bank_num; bank++) | |
4377 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 | 4378 | |
b3646477 | 4379 | static_call(kvm_x86_setup_mce)(vcpu); |
890ca9ae HY |
4380 | out: |
4381 | return r; | |
4382 | } | |
4383 | ||
4384 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
4385 | struct kvm_x86_mce *mce) | |
4386 | { | |
4387 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
4388 | unsigned bank_num = mcg_cap & 0xff; | |
4389 | u64 *banks = vcpu->arch.mce_banks; | |
4390 | ||
4391 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
4392 | return -EINVAL; | |
4393 | /* | |
4394 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
4395 | * reporting is disabled | |
4396 | */ | |
4397 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
4398 | vcpu->arch.mcg_ctl != ~(u64)0) | |
4399 | return 0; | |
4400 | banks += 4 * mce->bank; | |
4401 | /* | |
4402 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
4403 | * reporting is disabled for the bank | |
4404 | */ | |
4405 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
4406 | return 0; | |
4407 | if (mce->status & MCI_STATUS_UC) { | |
4408 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 4409 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 4410 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
4411 | return 0; |
4412 | } | |
4413 | if (banks[1] & MCI_STATUS_VAL) | |
4414 | mce->status |= MCI_STATUS_OVER; | |
4415 | banks[2] = mce->addr; | |
4416 | banks[3] = mce->misc; | |
4417 | vcpu->arch.mcg_status = mce->mcg_status; | |
4418 | banks[1] = mce->status; | |
4419 | kvm_queue_exception(vcpu, MC_VECTOR); | |
4420 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
4421 | || !(banks[1] & MCI_STATUS_UC)) { | |
4422 | if (banks[1] & MCI_STATUS_VAL) | |
4423 | mce->status |= MCI_STATUS_OVER; | |
4424 | banks[2] = mce->addr; | |
4425 | banks[3] = mce->misc; | |
4426 | banks[1] = mce->status; | |
4427 | } else | |
4428 | banks[1] |= MCI_STATUS_OVER; | |
4429 | return 0; | |
4430 | } | |
4431 | ||
3cfc3092 JK |
4432 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
4433 | struct kvm_vcpu_events *events) | |
4434 | { | |
7460fb4a | 4435 | process_nmi(vcpu); |
59073aaf | 4436 | |
1f7becf1 JZ |
4437 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
4438 | process_smi(vcpu); | |
4439 | ||
a06230b6 OU |
4440 | /* |
4441 | * In guest mode, payload delivery should be deferred, | |
4442 | * so that the L1 hypervisor can intercept #PF before | |
4443 | * CR2 is modified (or intercept #DB before DR6 is | |
4444 | * modified under nVMX). Unless the per-VM capability, | |
4445 | * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of | |
4446 | * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we | |
4447 | * opportunistically defer the exception payload, deliver it if the | |
4448 | * capability hasn't been requested before processing a | |
4449 | * KVM_GET_VCPU_EVENTS. | |
4450 | */ | |
4451 | if (!vcpu->kvm->arch.exception_payload_enabled && | |
4452 | vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) | |
4453 | kvm_deliver_exception_payload(vcpu); | |
4454 | ||
664f8e26 | 4455 | /* |
59073aaf JM |
4456 | * The API doesn't provide the instruction length for software |
4457 | * exceptions, so don't report them. As long as the guest RIP | |
4458 | * isn't advanced, we should expect to encounter the exception | |
4459 | * again. | |
664f8e26 | 4460 | */ |
59073aaf JM |
4461 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
4462 | events->exception.injected = 0; | |
4463 | events->exception.pending = 0; | |
4464 | } else { | |
4465 | events->exception.injected = vcpu->arch.exception.injected; | |
4466 | events->exception.pending = vcpu->arch.exception.pending; | |
4467 | /* | |
4468 | * For ABI compatibility, deliberately conflate | |
4469 | * pending and injected exceptions when | |
4470 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
4471 | */ | |
4472 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4473 | events->exception.injected |= | |
4474 | vcpu->arch.exception.pending; | |
4475 | } | |
3cfc3092 JK |
4476 | events->exception.nr = vcpu->arch.exception.nr; |
4477 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
4478 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
4479 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
4480 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 4481 | |
03b82a30 | 4482 | events->interrupt.injected = |
04140b41 | 4483 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 4484 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 4485 | events->interrupt.soft = 0; |
b3646477 | 4486 | events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
3cfc3092 JK |
4487 | |
4488 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 4489 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
b3646477 | 4490 | events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); |
97e69aa6 | 4491 | events->nmi.pad = 0; |
3cfc3092 | 4492 | |
66450a21 | 4493 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 4494 | |
f077825a PB |
4495 | events->smi.smm = is_smm(vcpu); |
4496 | events->smi.pending = vcpu->arch.smi_pending; | |
4497 | events->smi.smm_inside_nmi = | |
4498 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
4499 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
4500 | ||
dab4b911 | 4501 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
4502 | | KVM_VCPUEVENT_VALID_SHADOW |
4503 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
4504 | if (vcpu->kvm->arch.exception_payload_enabled) |
4505 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
4506 | ||
97e69aa6 | 4507 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
4508 | } |
4509 | ||
dc87275f | 4510 | static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); |
6ef4e07e | 4511 | |
3cfc3092 JK |
4512 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
4513 | struct kvm_vcpu_events *events) | |
4514 | { | |
dab4b911 | 4515 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 4516 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 4517 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf JM |
4518 | | KVM_VCPUEVENT_VALID_SMM |
4519 | | KVM_VCPUEVENT_VALID_PAYLOAD)) | |
3cfc3092 JK |
4520 | return -EINVAL; |
4521 | ||
59073aaf JM |
4522 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
4523 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4524 | return -EINVAL; | |
4525 | if (events->exception.pending) | |
4526 | events->exception.injected = 0; | |
4527 | else | |
4528 | events->exception_has_payload = 0; | |
4529 | } else { | |
4530 | events->exception.pending = 0; | |
4531 | events->exception_has_payload = 0; | |
4532 | } | |
4533 | ||
4534 | if ((events->exception.injected || events->exception.pending) && | |
4535 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
4536 | return -EINVAL; |
4537 | ||
28bf2888 DH |
4538 | /* INITs are latched while in SMM */ |
4539 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
4540 | (events->smi.smm || events->smi.pending) && | |
4541 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
4542 | return -EINVAL; | |
4543 | ||
7460fb4a | 4544 | process_nmi(vcpu); |
59073aaf JM |
4545 | vcpu->arch.exception.injected = events->exception.injected; |
4546 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
4547 | vcpu->arch.exception.nr = events->exception.nr; |
4548 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
4549 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
4550 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
4551 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 4552 | |
04140b41 | 4553 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
4554 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
4555 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 | 4556 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
b3646477 JB |
4557 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, |
4558 | events->interrupt.shadow); | |
3cfc3092 JK |
4559 | |
4560 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
4561 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
4562 | vcpu->arch.nmi_pending = events->nmi.pending; | |
b3646477 | 4563 | static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); |
3cfc3092 | 4564 | |
66450a21 | 4565 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 4566 | lapic_in_kernel(vcpu)) |
66450a21 | 4567 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 4568 | |
f077825a | 4569 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
dc87275f SC |
4570 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) |
4571 | kvm_smm_changed(vcpu, events->smi.smm); | |
6ef4e07e | 4572 | |
f077825a | 4573 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
4574 | |
4575 | if (events->smi.smm) { | |
4576 | if (events->smi.smm_inside_nmi) | |
4577 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 4578 | else |
f4ef1910 | 4579 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
4580 | } |
4581 | ||
4582 | if (lapic_in_kernel(vcpu)) { | |
4583 | if (events->smi.latched_init) | |
4584 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
4585 | else | |
4586 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
4587 | } |
4588 | } | |
4589 | ||
3842d135 AK |
4590 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
4591 | ||
3cfc3092 JK |
4592 | return 0; |
4593 | } | |
4594 | ||
a1efbe77 JK |
4595 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
4596 | struct kvm_debugregs *dbgregs) | |
4597 | { | |
73aaf249 JK |
4598 | unsigned long val; |
4599 | ||
a1efbe77 | 4600 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 4601 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 4602 | dbgregs->dr6 = val; |
a1efbe77 JK |
4603 | dbgregs->dr7 = vcpu->arch.dr7; |
4604 | dbgregs->flags = 0; | |
97e69aa6 | 4605 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
4606 | } |
4607 | ||
4608 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
4609 | struct kvm_debugregs *dbgregs) | |
4610 | { | |
4611 | if (dbgregs->flags) | |
4612 | return -EINVAL; | |
4613 | ||
fd238002 | 4614 | if (!kvm_dr6_valid(dbgregs->dr6)) |
d14bdb55 | 4615 | return -EINVAL; |
fd238002 | 4616 | if (!kvm_dr7_valid(dbgregs->dr7)) |
d14bdb55 PB |
4617 | return -EINVAL; |
4618 | ||
a1efbe77 | 4619 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 4620 | kvm_update_dr0123(vcpu); |
a1efbe77 JK |
4621 | vcpu->arch.dr6 = dbgregs->dr6; |
4622 | vcpu->arch.dr7 = dbgregs->dr7; | |
9926c9fd | 4623 | kvm_update_dr7(vcpu); |
a1efbe77 | 4624 | |
a1efbe77 JK |
4625 | return 0; |
4626 | } | |
4627 | ||
df1daba7 PB |
4628 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
4629 | ||
4630 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
4631 | { | |
b666a4b6 | 4632 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
400e4b20 | 4633 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
4634 | u64 valid; |
4635 | ||
4636 | /* | |
4637 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4638 | * leaves 0 and 1 in the loop below. | |
4639 | */ | |
4640 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
4641 | ||
4642 | /* Set XSTATE_BV */ | |
00c87e9a | 4643 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
4644 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
4645 | ||
4646 | /* | |
4647 | * Copy each region from the possibly compacted offset to the | |
4648 | * non-compacted offset. | |
4649 | */ | |
d91cab78 | 4650 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4651 | while (valid) { |
abd16d68 SAS |
4652 | u64 xfeature_mask = valid & -valid; |
4653 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
4654 | void *src = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
4655 | |
4656 | if (src) { | |
4657 | u32 size, offset, ecx, edx; | |
abd16d68 | 4658 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 4659 | &size, &offset, &ecx, &edx); |
abd16d68 | 4660 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
4661 | memcpy(dest + offset, &vcpu->arch.pkru, |
4662 | sizeof(vcpu->arch.pkru)); | |
4663 | else | |
4664 | memcpy(dest + offset, src, size); | |
4665 | ||
df1daba7 PB |
4666 | } |
4667 | ||
abd16d68 | 4668 | valid -= xfeature_mask; |
df1daba7 PB |
4669 | } |
4670 | } | |
4671 | ||
4672 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
4673 | { | |
b666a4b6 | 4674 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
df1daba7 PB |
4675 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
4676 | u64 valid; | |
4677 | ||
4678 | /* | |
4679 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4680 | * leaves 0 and 1 in the loop below. | |
4681 | */ | |
4682 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
4683 | ||
4684 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 4685 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 4686 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 4687 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
4688 | |
4689 | /* | |
4690 | * Copy each region from the non-compacted offset to the | |
4691 | * possibly compacted offset. | |
4692 | */ | |
d91cab78 | 4693 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4694 | while (valid) { |
abd16d68 SAS |
4695 | u64 xfeature_mask = valid & -valid; |
4696 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
4697 | void *dest = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
4698 | |
4699 | if (dest) { | |
4700 | u32 size, offset, ecx, edx; | |
abd16d68 | 4701 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 4702 | &size, &offset, &ecx, &edx); |
abd16d68 | 4703 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
4704 | memcpy(&vcpu->arch.pkru, src + offset, |
4705 | sizeof(vcpu->arch.pkru)); | |
4706 | else | |
4707 | memcpy(dest, src + offset, size); | |
ee4100da | 4708 | } |
df1daba7 | 4709 | |
abd16d68 | 4710 | valid -= xfeature_mask; |
df1daba7 PB |
4711 | } |
4712 | } | |
4713 | ||
2d5b5a66 SY |
4714 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
4715 | struct kvm_xsave *guest_xsave) | |
4716 | { | |
ed02b213 TL |
4717 | if (!vcpu->arch.guest_fpu) |
4718 | return; | |
4719 | ||
d366bf7e | 4720 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
4721 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
4722 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 4723 | } else { |
2d5b5a66 | 4724 | memcpy(guest_xsave->region, |
b666a4b6 | 4725 | &vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4726 | sizeof(struct fxregs_state)); |
2d5b5a66 | 4727 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 4728 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
4729 | } |
4730 | } | |
4731 | ||
a575813b WL |
4732 | #define XSAVE_MXCSR_OFFSET 24 |
4733 | ||
2d5b5a66 SY |
4734 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
4735 | struct kvm_xsave *guest_xsave) | |
4736 | { | |
ed02b213 TL |
4737 | u64 xstate_bv; |
4738 | u32 mxcsr; | |
4739 | ||
4740 | if (!vcpu->arch.guest_fpu) | |
4741 | return 0; | |
4742 | ||
4743 | xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
4744 | mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; | |
2d5b5a66 | 4745 | |
d366bf7e | 4746 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
4747 | /* |
4748 | * Here we allow setting states that are not present in | |
4749 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
4750 | * with old userspace. | |
4751 | */ | |
cfc48181 | 4752 | if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) |
d7876f1b | 4753 | return -EINVAL; |
df1daba7 | 4754 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 4755 | } else { |
a575813b WL |
4756 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
4757 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 4758 | return -EINVAL; |
b666a4b6 | 4759 | memcpy(&vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4760 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
4761 | } |
4762 | return 0; | |
4763 | } | |
4764 | ||
4765 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
4766 | struct kvm_xcrs *guest_xcrs) | |
4767 | { | |
d366bf7e | 4768 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
4769 | guest_xcrs->nr_xcrs = 0; |
4770 | return; | |
4771 | } | |
4772 | ||
4773 | guest_xcrs->nr_xcrs = 1; | |
4774 | guest_xcrs->flags = 0; | |
4775 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
4776 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
4777 | } | |
4778 | ||
4779 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
4780 | struct kvm_xcrs *guest_xcrs) | |
4781 | { | |
4782 | int i, r = 0; | |
4783 | ||
d366bf7e | 4784 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
4785 | return -EINVAL; |
4786 | ||
4787 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
4788 | return -EINVAL; | |
4789 | ||
4790 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
4791 | /* Only support XCR0 currently */ | |
c67a04cb | 4792 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 4793 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 4794 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
4795 | break; |
4796 | } | |
4797 | if (r) | |
4798 | r = -EINVAL; | |
4799 | return r; | |
4800 | } | |
4801 | ||
1c0b28c2 EM |
4802 | /* |
4803 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
4804 | * stopped by the hypervisor. This function will be called from the host only. | |
4805 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
4806 | * does not support pv clocks. | |
4807 | */ | |
4808 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
4809 | { | |
0b79459b | 4810 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 4811 | return -EINVAL; |
51d59c6b | 4812 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
4813 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
4814 | return 0; | |
4815 | } | |
4816 | ||
5c919412 AS |
4817 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
4818 | struct kvm_enable_cap *cap) | |
4819 | { | |
57b119da VK |
4820 | int r; |
4821 | uint16_t vmcs_version; | |
4822 | void __user *user_ptr; | |
4823 | ||
5c919412 AS |
4824 | if (cap->flags) |
4825 | return -EINVAL; | |
4826 | ||
4827 | switch (cap->cap) { | |
efc479e6 RK |
4828 | case KVM_CAP_HYPERV_SYNIC2: |
4829 | if (cap->args[0]) | |
4830 | return -EINVAL; | |
df561f66 | 4831 | fallthrough; |
b2869f28 | 4832 | |
5c919412 | 4833 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
4834 | if (!irqchip_in_kernel(vcpu->kvm)) |
4835 | return -EINVAL; | |
efc479e6 RK |
4836 | return kvm_hv_activate_synic(vcpu, cap->cap == |
4837 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 4838 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
33b22172 | 4839 | if (!kvm_x86_ops.nested_ops->enable_evmcs) |
5158917c | 4840 | return -ENOTTY; |
33b22172 | 4841 | r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); |
57b119da VK |
4842 | if (!r) { |
4843 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
4844 | if (copy_to_user(user_ptr, &vmcs_version, | |
4845 | sizeof(vmcs_version))) | |
4846 | r = -EFAULT; | |
4847 | } | |
4848 | return r; | |
344c6c80 | 4849 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4850 | if (!kvm_x86_ops.enable_direct_tlbflush) |
344c6c80 TL |
4851 | return -ENOTTY; |
4852 | ||
b3646477 | 4853 | return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); |
57b119da | 4854 | |
644f7067 VK |
4855 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
4856 | return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); | |
4857 | ||
66570e96 OU |
4858 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
4859 | vcpu->arch.pv_cpuid.enforce = cap->args[0]; | |
01b4f510 OU |
4860 | if (vcpu->arch.pv_cpuid.enforce) |
4861 | kvm_update_pv_runtime(vcpu); | |
66570e96 OU |
4862 | |
4863 | return 0; | |
5c919412 AS |
4864 | default: |
4865 | return -EINVAL; | |
4866 | } | |
4867 | } | |
4868 | ||
313a3dc7 CO |
4869 | long kvm_arch_vcpu_ioctl(struct file *filp, |
4870 | unsigned int ioctl, unsigned long arg) | |
4871 | { | |
4872 | struct kvm_vcpu *vcpu = filp->private_data; | |
4873 | void __user *argp = (void __user *)arg; | |
4874 | int r; | |
d1ac91d8 | 4875 | union { |
6dba9403 | 4876 | struct kvm_sregs2 *sregs2; |
d1ac91d8 AK |
4877 | struct kvm_lapic_state *lapic; |
4878 | struct kvm_xsave *xsave; | |
4879 | struct kvm_xcrs *xcrs; | |
4880 | void *buffer; | |
4881 | } u; | |
4882 | ||
9b062471 CD |
4883 | vcpu_load(vcpu); |
4884 | ||
d1ac91d8 | 4885 | u.buffer = NULL; |
313a3dc7 CO |
4886 | switch (ioctl) { |
4887 | case KVM_GET_LAPIC: { | |
2204ae3c | 4888 | r = -EINVAL; |
bce87cce | 4889 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4890 | goto out; |
254272ce BG |
4891 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
4892 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 4893 | |
b772ff36 | 4894 | r = -ENOMEM; |
d1ac91d8 | 4895 | if (!u.lapic) |
b772ff36 | 4896 | goto out; |
d1ac91d8 | 4897 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4898 | if (r) |
4899 | goto out; | |
4900 | r = -EFAULT; | |
d1ac91d8 | 4901 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
4902 | goto out; |
4903 | r = 0; | |
4904 | break; | |
4905 | } | |
4906 | case KVM_SET_LAPIC: { | |
2204ae3c | 4907 | r = -EINVAL; |
bce87cce | 4908 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4909 | goto out; |
ff5c2c03 | 4910 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
4911 | if (IS_ERR(u.lapic)) { |
4912 | r = PTR_ERR(u.lapic); | |
4913 | goto out_nofree; | |
4914 | } | |
ff5c2c03 | 4915 | |
d1ac91d8 | 4916 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4917 | break; |
4918 | } | |
f77bc6a4 ZX |
4919 | case KVM_INTERRUPT: { |
4920 | struct kvm_interrupt irq; | |
4921 | ||
4922 | r = -EFAULT; | |
0e96f31e | 4923 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
4924 | goto out; |
4925 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
4926 | break; |
4927 | } | |
c4abb7c9 JK |
4928 | case KVM_NMI: { |
4929 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
4930 | break; |
4931 | } | |
f077825a PB |
4932 | case KVM_SMI: { |
4933 | r = kvm_vcpu_ioctl_smi(vcpu); | |
4934 | break; | |
4935 | } | |
313a3dc7 CO |
4936 | case KVM_SET_CPUID: { |
4937 | struct kvm_cpuid __user *cpuid_arg = argp; | |
4938 | struct kvm_cpuid cpuid; | |
4939 | ||
4940 | r = -EFAULT; | |
0e96f31e | 4941 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
4942 | goto out; |
4943 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
4944 | break; |
4945 | } | |
07716717 DK |
4946 | case KVM_SET_CPUID2: { |
4947 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4948 | struct kvm_cpuid2 cpuid; | |
4949 | ||
4950 | r = -EFAULT; | |
0e96f31e | 4951 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4952 | goto out; |
4953 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 4954 | cpuid_arg->entries); |
07716717 DK |
4955 | break; |
4956 | } | |
4957 | case KVM_GET_CPUID2: { | |
4958 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4959 | struct kvm_cpuid2 cpuid; | |
4960 | ||
4961 | r = -EFAULT; | |
0e96f31e | 4962 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4963 | goto out; |
4964 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 4965 | cpuid_arg->entries); |
07716717 DK |
4966 | if (r) |
4967 | goto out; | |
4968 | r = -EFAULT; | |
0e96f31e | 4969 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
4970 | goto out; |
4971 | r = 0; | |
4972 | break; | |
4973 | } | |
801e459a TL |
4974 | case KVM_GET_MSRS: { |
4975 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 4976 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 4977 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4978 | break; |
801e459a TL |
4979 | } |
4980 | case KVM_SET_MSRS: { | |
4981 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 4982 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 4983 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4984 | break; |
801e459a | 4985 | } |
b209749f AK |
4986 | case KVM_TPR_ACCESS_REPORTING: { |
4987 | struct kvm_tpr_access_ctl tac; | |
4988 | ||
4989 | r = -EFAULT; | |
0e96f31e | 4990 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
4991 | goto out; |
4992 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
4993 | if (r) | |
4994 | goto out; | |
4995 | r = -EFAULT; | |
0e96f31e | 4996 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
4997 | goto out; |
4998 | r = 0; | |
4999 | break; | |
5000 | }; | |
b93463aa AK |
5001 | case KVM_SET_VAPIC_ADDR: { |
5002 | struct kvm_vapic_addr va; | |
7301d6ab | 5003 | int idx; |
b93463aa AK |
5004 | |
5005 | r = -EINVAL; | |
35754c98 | 5006 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
5007 | goto out; |
5008 | r = -EFAULT; | |
0e96f31e | 5009 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 5010 | goto out; |
7301d6ab | 5011 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 5012 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 5013 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
5014 | break; |
5015 | } | |
890ca9ae HY |
5016 | case KVM_X86_SETUP_MCE: { |
5017 | u64 mcg_cap; | |
5018 | ||
5019 | r = -EFAULT; | |
0e96f31e | 5020 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
5021 | goto out; |
5022 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
5023 | break; | |
5024 | } | |
5025 | case KVM_X86_SET_MCE: { | |
5026 | struct kvm_x86_mce mce; | |
5027 | ||
5028 | r = -EFAULT; | |
0e96f31e | 5029 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
5030 | goto out; |
5031 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
5032 | break; | |
5033 | } | |
3cfc3092 JK |
5034 | case KVM_GET_VCPU_EVENTS: { |
5035 | struct kvm_vcpu_events events; | |
5036 | ||
5037 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
5038 | ||
5039 | r = -EFAULT; | |
5040 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
5041 | break; | |
5042 | r = 0; | |
5043 | break; | |
5044 | } | |
5045 | case KVM_SET_VCPU_EVENTS: { | |
5046 | struct kvm_vcpu_events events; | |
5047 | ||
5048 | r = -EFAULT; | |
5049 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
5050 | break; | |
5051 | ||
5052 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
5053 | break; | |
5054 | } | |
a1efbe77 JK |
5055 | case KVM_GET_DEBUGREGS: { |
5056 | struct kvm_debugregs dbgregs; | |
5057 | ||
5058 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
5059 | ||
5060 | r = -EFAULT; | |
5061 | if (copy_to_user(argp, &dbgregs, | |
5062 | sizeof(struct kvm_debugregs))) | |
5063 | break; | |
5064 | r = 0; | |
5065 | break; | |
5066 | } | |
5067 | case KVM_SET_DEBUGREGS: { | |
5068 | struct kvm_debugregs dbgregs; | |
5069 | ||
5070 | r = -EFAULT; | |
5071 | if (copy_from_user(&dbgregs, argp, | |
5072 | sizeof(struct kvm_debugregs))) | |
5073 | break; | |
5074 | ||
5075 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
5076 | break; | |
5077 | } | |
2d5b5a66 | 5078 | case KVM_GET_XSAVE: { |
254272ce | 5079 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5080 | r = -ENOMEM; |
d1ac91d8 | 5081 | if (!u.xsave) |
2d5b5a66 SY |
5082 | break; |
5083 | ||
d1ac91d8 | 5084 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5085 | |
5086 | r = -EFAULT; | |
d1ac91d8 | 5087 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
5088 | break; |
5089 | r = 0; | |
5090 | break; | |
5091 | } | |
5092 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 5093 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
5094 | if (IS_ERR(u.xsave)) { |
5095 | r = PTR_ERR(u.xsave); | |
5096 | goto out_nofree; | |
5097 | } | |
2d5b5a66 | 5098 | |
d1ac91d8 | 5099 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5100 | break; |
5101 | } | |
5102 | case KVM_GET_XCRS: { | |
254272ce | 5103 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5104 | r = -ENOMEM; |
d1ac91d8 | 5105 | if (!u.xcrs) |
2d5b5a66 SY |
5106 | break; |
5107 | ||
d1ac91d8 | 5108 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5109 | |
5110 | r = -EFAULT; | |
d1ac91d8 | 5111 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
5112 | sizeof(struct kvm_xcrs))) |
5113 | break; | |
5114 | r = 0; | |
5115 | break; | |
5116 | } | |
5117 | case KVM_SET_XCRS: { | |
ff5c2c03 | 5118 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
5119 | if (IS_ERR(u.xcrs)) { |
5120 | r = PTR_ERR(u.xcrs); | |
5121 | goto out_nofree; | |
5122 | } | |
2d5b5a66 | 5123 | |
d1ac91d8 | 5124 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5125 | break; |
5126 | } | |
92a1f12d JR |
5127 | case KVM_SET_TSC_KHZ: { |
5128 | u32 user_tsc_khz; | |
5129 | ||
5130 | r = -EINVAL; | |
92a1f12d JR |
5131 | user_tsc_khz = (u32)arg; |
5132 | ||
26769f96 MT |
5133 | if (kvm_has_tsc_control && |
5134 | user_tsc_khz >= kvm_max_guest_tsc_khz) | |
92a1f12d JR |
5135 | goto out; |
5136 | ||
cc578287 ZA |
5137 | if (user_tsc_khz == 0) |
5138 | user_tsc_khz = tsc_khz; | |
5139 | ||
381d585c HZ |
5140 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
5141 | r = 0; | |
92a1f12d | 5142 | |
92a1f12d JR |
5143 | goto out; |
5144 | } | |
5145 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 5146 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
5147 | goto out; |
5148 | } | |
1c0b28c2 EM |
5149 | case KVM_KVMCLOCK_CTRL: { |
5150 | r = kvm_set_guest_paused(vcpu); | |
5151 | goto out; | |
5152 | } | |
5c919412 AS |
5153 | case KVM_ENABLE_CAP: { |
5154 | struct kvm_enable_cap cap; | |
5155 | ||
5156 | r = -EFAULT; | |
5157 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
5158 | goto out; | |
5159 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
5160 | break; | |
5161 | } | |
8fcc4b59 JM |
5162 | case KVM_GET_NESTED_STATE: { |
5163 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5164 | u32 user_data_size; | |
5165 | ||
5166 | r = -EINVAL; | |
33b22172 | 5167 | if (!kvm_x86_ops.nested_ops->get_state) |
8fcc4b59 JM |
5168 | break; |
5169 | ||
5170 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 5171 | r = -EFAULT; |
8fcc4b59 | 5172 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 5173 | break; |
8fcc4b59 | 5174 | |
33b22172 PB |
5175 | r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, |
5176 | user_data_size); | |
8fcc4b59 | 5177 | if (r < 0) |
26b471c7 | 5178 | break; |
8fcc4b59 JM |
5179 | |
5180 | if (r > user_data_size) { | |
5181 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
5182 | r = -EFAULT; |
5183 | else | |
5184 | r = -E2BIG; | |
5185 | break; | |
8fcc4b59 | 5186 | } |
26b471c7 | 5187 | |
8fcc4b59 JM |
5188 | r = 0; |
5189 | break; | |
5190 | } | |
5191 | case KVM_SET_NESTED_STATE: { | |
5192 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5193 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 5194 | int idx; |
8fcc4b59 JM |
5195 | |
5196 | r = -EINVAL; | |
33b22172 | 5197 | if (!kvm_x86_ops.nested_ops->set_state) |
8fcc4b59 JM |
5198 | break; |
5199 | ||
26b471c7 | 5200 | r = -EFAULT; |
8fcc4b59 | 5201 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 5202 | break; |
8fcc4b59 | 5203 | |
26b471c7 | 5204 | r = -EINVAL; |
8fcc4b59 | 5205 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 5206 | break; |
8fcc4b59 JM |
5207 | |
5208 | if (kvm_state.flags & | |
8cab6507 | 5209 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
cc440cda PB |
5210 | | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING |
5211 | | KVM_STATE_NESTED_GIF_SET)) | |
26b471c7 | 5212 | break; |
8fcc4b59 JM |
5213 | |
5214 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
5215 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
5216 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 5217 | break; |
8fcc4b59 | 5218 | |
ad5996d9 | 5219 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
33b22172 | 5220 | r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 5221 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
5222 | break; |
5223 | } | |
c21d54f0 VK |
5224 | case KVM_GET_SUPPORTED_HV_CPUID: |
5225 | r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); | |
2bc39970 | 5226 | break; |
b59b153d | 5227 | #ifdef CONFIG_KVM_XEN |
3e324615 DW |
5228 | case KVM_XEN_VCPU_GET_ATTR: { |
5229 | struct kvm_xen_vcpu_attr xva; | |
5230 | ||
5231 | r = -EFAULT; | |
5232 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
5233 | goto out; | |
5234 | r = kvm_xen_vcpu_get_attr(vcpu, &xva); | |
5235 | if (!r && copy_to_user(argp, &xva, sizeof(xva))) | |
5236 | r = -EFAULT; | |
5237 | break; | |
5238 | } | |
5239 | case KVM_XEN_VCPU_SET_ATTR: { | |
5240 | struct kvm_xen_vcpu_attr xva; | |
5241 | ||
5242 | r = -EFAULT; | |
5243 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
5244 | goto out; | |
5245 | r = kvm_xen_vcpu_set_attr(vcpu, &xva); | |
5246 | break; | |
5247 | } | |
b59b153d | 5248 | #endif |
6dba9403 ML |
5249 | case KVM_GET_SREGS2: { |
5250 | u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); | |
5251 | r = -ENOMEM; | |
5252 | if (!u.sregs2) | |
5253 | goto out; | |
5254 | __get_sregs2(vcpu, u.sregs2); | |
5255 | r = -EFAULT; | |
5256 | if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) | |
5257 | goto out; | |
5258 | r = 0; | |
5259 | break; | |
5260 | } | |
5261 | case KVM_SET_SREGS2: { | |
5262 | u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); | |
5263 | if (IS_ERR(u.sregs2)) { | |
5264 | r = PTR_ERR(u.sregs2); | |
5265 | u.sregs2 = NULL; | |
5266 | goto out; | |
5267 | } | |
5268 | r = __set_sregs2(vcpu, u.sregs2); | |
5269 | break; | |
5270 | } | |
313a3dc7 CO |
5271 | default: |
5272 | r = -EINVAL; | |
5273 | } | |
5274 | out: | |
d1ac91d8 | 5275 | kfree(u.buffer); |
9b062471 CD |
5276 | out_nofree: |
5277 | vcpu_put(vcpu); | |
313a3dc7 CO |
5278 | return r; |
5279 | } | |
5280 | ||
1499fa80 | 5281 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
5282 | { |
5283 | return VM_FAULT_SIGBUS; | |
5284 | } | |
5285 | ||
1fe779f8 CO |
5286 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
5287 | { | |
5288 | int ret; | |
5289 | ||
5290 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 5291 | return -EINVAL; |
b3646477 | 5292 | ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); |
1fe779f8 CO |
5293 | return ret; |
5294 | } | |
5295 | ||
b927a3ce SY |
5296 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
5297 | u64 ident_addr) | |
5298 | { | |
b3646477 | 5299 | return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); |
b927a3ce SY |
5300 | } |
5301 | ||
1fe779f8 | 5302 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 5303 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
5304 | { |
5305 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
5306 | return -EINVAL; | |
5307 | ||
79fac95e | 5308 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
5309 | |
5310 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 5311 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 5312 | |
79fac95e | 5313 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
5314 | return 0; |
5315 | } | |
5316 | ||
bc8a3d89 | 5317 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 5318 | { |
39de71ec | 5319 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
5320 | } |
5321 | ||
1fe779f8 CO |
5322 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
5323 | { | |
90bca052 | 5324 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5325 | int r; |
5326 | ||
5327 | r = 0; | |
5328 | switch (chip->chip_id) { | |
5329 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 5330 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
5331 | sizeof(struct kvm_pic_state)); |
5332 | break; | |
5333 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 5334 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
5335 | sizeof(struct kvm_pic_state)); |
5336 | break; | |
5337 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5338 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5339 | break; |
5340 | default: | |
5341 | r = -EINVAL; | |
5342 | break; | |
5343 | } | |
5344 | return r; | |
5345 | } | |
5346 | ||
5347 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
5348 | { | |
90bca052 | 5349 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5350 | int r; |
5351 | ||
5352 | r = 0; | |
5353 | switch (chip->chip_id) { | |
5354 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
5355 | spin_lock(&pic->lock); |
5356 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 5357 | sizeof(struct kvm_pic_state)); |
90bca052 | 5358 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5359 | break; |
5360 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
5361 | spin_lock(&pic->lock); |
5362 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 5363 | sizeof(struct kvm_pic_state)); |
90bca052 | 5364 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5365 | break; |
5366 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5367 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5368 | break; |
5369 | default: | |
5370 | r = -EINVAL; | |
5371 | break; | |
5372 | } | |
90bca052 | 5373 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
5374 | return r; |
5375 | } | |
5376 | ||
e0f63cb9 SY |
5377 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
5378 | { | |
34f3941c RK |
5379 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
5380 | ||
5381 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
5382 | ||
5383 | mutex_lock(&kps->lock); | |
5384 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
5385 | mutex_unlock(&kps->lock); | |
2da29bcc | 5386 | return 0; |
e0f63cb9 SY |
5387 | } |
5388 | ||
5389 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
5390 | { | |
0185604c | 5391 | int i; |
09edea72 RK |
5392 | struct kvm_pit *pit = kvm->arch.vpit; |
5393 | ||
5394 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 5395 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 5396 | for (i = 0; i < 3; i++) |
09edea72 RK |
5397 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
5398 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 5399 | return 0; |
e9f42757 BK |
5400 | } |
5401 | ||
5402 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5403 | { | |
e9f42757 BK |
5404 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
5405 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
5406 | sizeof(ps->channels)); | |
5407 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
5408 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 5409 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 5410 | return 0; |
e9f42757 BK |
5411 | } |
5412 | ||
5413 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5414 | { | |
2da29bcc | 5415 | int start = 0; |
0185604c | 5416 | int i; |
e9f42757 | 5417 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
5418 | struct kvm_pit *pit = kvm->arch.vpit; |
5419 | ||
5420 | mutex_lock(&pit->pit_state.lock); | |
5421 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
5422 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
5423 | if (!prev_legacy && cur_legacy) | |
5424 | start = 1; | |
09edea72 RK |
5425 | memcpy(&pit->pit_state.channels, &ps->channels, |
5426 | sizeof(pit->pit_state.channels)); | |
5427 | pit->pit_state.flags = ps->flags; | |
0185604c | 5428 | for (i = 0; i < 3; i++) |
09edea72 | 5429 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 5430 | start && i == 0); |
09edea72 | 5431 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 5432 | return 0; |
e0f63cb9 SY |
5433 | } |
5434 | ||
52d939a0 MT |
5435 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
5436 | struct kvm_reinject_control *control) | |
5437 | { | |
71474e2f RK |
5438 | struct kvm_pit *pit = kvm->arch.vpit; |
5439 | ||
71474e2f RK |
5440 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
5441 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
5442 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
5443 | */ | |
5444 | mutex_lock(&pit->pit_state.lock); | |
5445 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
5446 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 5447 | |
52d939a0 MT |
5448 | return 0; |
5449 | } | |
5450 | ||
0dff0846 | 5451 | void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) |
5bb064dc | 5452 | { |
a018eba5 | 5453 | |
88178fd4 | 5454 | /* |
a018eba5 SC |
5455 | * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called |
5456 | * before reporting dirty_bitmap to userspace. KVM flushes the buffers | |
5457 | * on all VM-Exits, thus we only need to kick running vCPUs to force a | |
5458 | * VM-Exit. | |
88178fd4 | 5459 | */ |
a018eba5 SC |
5460 | struct kvm_vcpu *vcpu; |
5461 | int i; | |
5462 | ||
5463 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5464 | kvm_vcpu_kick(vcpu); | |
5bb064dc ZX |
5465 | } |
5466 | ||
aa2fbe6d YZ |
5467 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
5468 | bool line_status) | |
23d43cf9 CD |
5469 | { |
5470 | if (!irqchip_in_kernel(kvm)) | |
5471 | return -ENXIO; | |
5472 | ||
5473 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
5474 | irq_event->irq, irq_event->level, |
5475 | line_status); | |
23d43cf9 CD |
5476 | return 0; |
5477 | } | |
5478 | ||
e5d83c74 PB |
5479 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
5480 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
5481 | { |
5482 | int r; | |
5483 | ||
5484 | if (cap->flags) | |
5485 | return -EINVAL; | |
5486 | ||
5487 | switch (cap->cap) { | |
5488 | case KVM_CAP_DISABLE_QUIRKS: | |
5489 | kvm->arch.disabled_quirks = cap->args[0]; | |
5490 | r = 0; | |
5491 | break; | |
49df6397 SR |
5492 | case KVM_CAP_SPLIT_IRQCHIP: { |
5493 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
5494 | r = -EINVAL; |
5495 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
5496 | goto split_irqchip_unlock; | |
49df6397 SR |
5497 | r = -EEXIST; |
5498 | if (irqchip_in_kernel(kvm)) | |
5499 | goto split_irqchip_unlock; | |
557abc40 | 5500 | if (kvm->created_vcpus) |
49df6397 SR |
5501 | goto split_irqchip_unlock; |
5502 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 5503 | if (r) |
49df6397 SR |
5504 | goto split_irqchip_unlock; |
5505 | /* Pairs with irqchip_in_kernel. */ | |
5506 | smp_wmb(); | |
49776faf | 5507 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 5508 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
5509 | r = 0; |
5510 | split_irqchip_unlock: | |
5511 | mutex_unlock(&kvm->lock); | |
5512 | break; | |
5513 | } | |
37131313 RK |
5514 | case KVM_CAP_X2APIC_API: |
5515 | r = -EINVAL; | |
5516 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
5517 | break; | |
5518 | ||
5519 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
5520 | kvm->arch.x2apic_format = true; | |
c519265f RK |
5521 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
5522 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
5523 | |
5524 | r = 0; | |
5525 | break; | |
4d5422ce WL |
5526 | case KVM_CAP_X86_DISABLE_EXITS: |
5527 | r = -EINVAL; | |
5528 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
5529 | break; | |
5530 | ||
5531 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
5532 | kvm_can_mwait_in_guest()) | |
5533 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 5534 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 5535 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
5536 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
5537 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
5538 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
5539 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
5540 | r = 0; |
5541 | break; | |
6fbbde9a DS |
5542 | case KVM_CAP_MSR_PLATFORM_INFO: |
5543 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
5544 | r = 0; | |
c4f55198 JM |
5545 | break; |
5546 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
5547 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
5548 | r = 0; | |
6fbbde9a | 5549 | break; |
1ae09954 AG |
5550 | case KVM_CAP_X86_USER_SPACE_MSR: |
5551 | kvm->arch.user_space_msr_mask = cap->args[0]; | |
5552 | r = 0; | |
5553 | break; | |
fe6b6bc8 CQ |
5554 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
5555 | r = -EINVAL; | |
5556 | if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) | |
5557 | break; | |
5558 | ||
5559 | if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && | |
5560 | (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) | |
5561 | break; | |
5562 | ||
5563 | if (kvm_has_bus_lock_exit && | |
5564 | cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) | |
5565 | kvm->arch.bus_lock_detection_enabled = true; | |
5566 | r = 0; | |
5567 | break; | |
fe7e9488 SC |
5568 | #ifdef CONFIG_X86_SGX_KVM |
5569 | case KVM_CAP_SGX_ATTRIBUTE: { | |
5570 | unsigned long allowed_attributes = 0; | |
5571 | ||
5572 | r = sgx_set_attribute(&allowed_attributes, cap->args[0]); | |
5573 | if (r) | |
5574 | break; | |
5575 | ||
5576 | /* KVM only supports the PROVISIONKEY privileged attribute. */ | |
5577 | if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && | |
5578 | !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) | |
5579 | kvm->arch.sgx_provisioning_allowed = true; | |
5580 | else | |
5581 | r = -EINVAL; | |
5582 | break; | |
5583 | } | |
5584 | #endif | |
54526d1f NT |
5585 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
5586 | r = -EINVAL; | |
5587 | if (kvm_x86_ops.vm_copy_enc_context_from) | |
5588 | r = kvm_x86_ops.vm_copy_enc_context_from(kvm, cap->args[0]); | |
5589 | return r; | |
90de4a18 NA |
5590 | default: |
5591 | r = -EINVAL; | |
5592 | break; | |
5593 | } | |
5594 | return r; | |
5595 | } | |
5596 | ||
b318e8de SC |
5597 | static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) |
5598 | { | |
5599 | struct kvm_x86_msr_filter *msr_filter; | |
5600 | ||
5601 | msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); | |
5602 | if (!msr_filter) | |
5603 | return NULL; | |
5604 | ||
5605 | msr_filter->default_allow = default_allow; | |
5606 | return msr_filter; | |
5607 | } | |
5608 | ||
5609 | static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) | |
1a155254 AG |
5610 | { |
5611 | u32 i; | |
1a155254 | 5612 | |
b318e8de SC |
5613 | if (!msr_filter) |
5614 | return; | |
5615 | ||
5616 | for (i = 0; i < msr_filter->count; i++) | |
5617 | kfree(msr_filter->ranges[i].bitmap); | |
1a155254 | 5618 | |
b318e8de | 5619 | kfree(msr_filter); |
1a155254 AG |
5620 | } |
5621 | ||
b318e8de SC |
5622 | static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, |
5623 | struct kvm_msr_filter_range *user_range) | |
1a155254 | 5624 | { |
1a155254 AG |
5625 | unsigned long *bitmap = NULL; |
5626 | size_t bitmap_size; | |
1a155254 AG |
5627 | |
5628 | if (!user_range->nmsrs) | |
5629 | return 0; | |
5630 | ||
aca35288 SC |
5631 | if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) |
5632 | return -EINVAL; | |
5633 | ||
5634 | if (!user_range->flags) | |
5635 | return -EINVAL; | |
5636 | ||
1a155254 AG |
5637 | bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); |
5638 | if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) | |
5639 | return -EINVAL; | |
5640 | ||
5641 | bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); | |
5642 | if (IS_ERR(bitmap)) | |
5643 | return PTR_ERR(bitmap); | |
5644 | ||
aca35288 | 5645 | msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { |
1a155254 AG |
5646 | .flags = user_range->flags, |
5647 | .base = user_range->base, | |
5648 | .nmsrs = user_range->nmsrs, | |
5649 | .bitmap = bitmap, | |
5650 | }; | |
5651 | ||
b318e8de | 5652 | msr_filter->count++; |
1a155254 | 5653 | return 0; |
1a155254 AG |
5654 | } |
5655 | ||
5656 | static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) | |
5657 | { | |
5658 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
b318e8de | 5659 | struct kvm_x86_msr_filter *new_filter, *old_filter; |
1a155254 AG |
5660 | struct kvm_msr_filter filter; |
5661 | bool default_allow; | |
043248b3 | 5662 | bool empty = true; |
b318e8de | 5663 | int r = 0; |
1a155254 AG |
5664 | u32 i; |
5665 | ||
5666 | if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) | |
5667 | return -EFAULT; | |
5668 | ||
043248b3 PB |
5669 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) |
5670 | empty &= !filter.ranges[i].nmsrs; | |
1a155254 AG |
5671 | |
5672 | default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); | |
043248b3 PB |
5673 | if (empty && !default_allow) |
5674 | return -EINVAL; | |
5675 | ||
b318e8de SC |
5676 | new_filter = kvm_alloc_msr_filter(default_allow); |
5677 | if (!new_filter) | |
5678 | return -ENOMEM; | |
1a155254 | 5679 | |
1a155254 | 5680 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { |
b318e8de SC |
5681 | r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); |
5682 | if (r) { | |
5683 | kvm_free_msr_filter(new_filter); | |
5684 | return r; | |
5685 | } | |
1a155254 AG |
5686 | } |
5687 | ||
b318e8de SC |
5688 | mutex_lock(&kvm->lock); |
5689 | ||
5690 | /* The per-VM filter is protected by kvm->lock... */ | |
5691 | old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); | |
5692 | ||
5693 | rcu_assign_pointer(kvm->arch.msr_filter, new_filter); | |
5694 | synchronize_srcu(&kvm->srcu); | |
5695 | ||
5696 | kvm_free_msr_filter(old_filter); | |
5697 | ||
1a155254 AG |
5698 | kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); |
5699 | mutex_unlock(&kvm->lock); | |
5700 | ||
b318e8de | 5701 | return 0; |
1a155254 AG |
5702 | } |
5703 | ||
7d62874f SS |
5704 | #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER |
5705 | static int kvm_arch_suspend_notifier(struct kvm *kvm) | |
5706 | { | |
5707 | struct kvm_vcpu *vcpu; | |
5708 | int i, ret = 0; | |
5709 | ||
5710 | mutex_lock(&kvm->lock); | |
5711 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
5712 | if (!vcpu->arch.pv_time_enabled) | |
5713 | continue; | |
5714 | ||
5715 | ret = kvm_set_guest_paused(vcpu); | |
5716 | if (ret) { | |
5717 | kvm_err("Failed to pause guest VCPU%d: %d\n", | |
5718 | vcpu->vcpu_id, ret); | |
5719 | break; | |
5720 | } | |
5721 | } | |
5722 | mutex_unlock(&kvm->lock); | |
5723 | ||
5724 | return ret ? NOTIFY_BAD : NOTIFY_DONE; | |
5725 | } | |
5726 | ||
5727 | int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) | |
5728 | { | |
5729 | switch (state) { | |
5730 | case PM_HIBERNATION_PREPARE: | |
5731 | case PM_SUSPEND_PREPARE: | |
5732 | return kvm_arch_suspend_notifier(kvm); | |
5733 | } | |
5734 | ||
5735 | return NOTIFY_DONE; | |
5736 | } | |
5737 | #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ | |
5738 | ||
1fe779f8 CO |
5739 | long kvm_arch_vm_ioctl(struct file *filp, |
5740 | unsigned int ioctl, unsigned long arg) | |
5741 | { | |
5742 | struct kvm *kvm = filp->private_data; | |
5743 | void __user *argp = (void __user *)arg; | |
367e1319 | 5744 | int r = -ENOTTY; |
f0d66275 DH |
5745 | /* |
5746 | * This union makes it completely explicit to gcc-3.x | |
5747 | * that these two variables' stack usage should be | |
5748 | * combined, not added together. | |
5749 | */ | |
5750 | union { | |
5751 | struct kvm_pit_state ps; | |
e9f42757 | 5752 | struct kvm_pit_state2 ps2; |
c5ff41ce | 5753 | struct kvm_pit_config pit_config; |
f0d66275 | 5754 | } u; |
1fe779f8 CO |
5755 | |
5756 | switch (ioctl) { | |
5757 | case KVM_SET_TSS_ADDR: | |
5758 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 5759 | break; |
b927a3ce SY |
5760 | case KVM_SET_IDENTITY_MAP_ADDR: { |
5761 | u64 ident_addr; | |
5762 | ||
1af1ac91 DH |
5763 | mutex_lock(&kvm->lock); |
5764 | r = -EINVAL; | |
5765 | if (kvm->created_vcpus) | |
5766 | goto set_identity_unlock; | |
b927a3ce | 5767 | r = -EFAULT; |
0e96f31e | 5768 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 5769 | goto set_identity_unlock; |
b927a3ce | 5770 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
5771 | set_identity_unlock: |
5772 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
5773 | break; |
5774 | } | |
1fe779f8 CO |
5775 | case KVM_SET_NR_MMU_PAGES: |
5776 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
5777 | break; |
5778 | case KVM_GET_NR_MMU_PAGES: | |
5779 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
5780 | break; | |
3ddea128 | 5781 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 5782 | mutex_lock(&kvm->lock); |
09941366 | 5783 | |
3ddea128 | 5784 | r = -EEXIST; |
35e6eaa3 | 5785 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 5786 | goto create_irqchip_unlock; |
09941366 | 5787 | |
3e515705 | 5788 | r = -EINVAL; |
557abc40 | 5789 | if (kvm->created_vcpus) |
3e515705 | 5790 | goto create_irqchip_unlock; |
09941366 RK |
5791 | |
5792 | r = kvm_pic_init(kvm); | |
5793 | if (r) | |
3ddea128 | 5794 | goto create_irqchip_unlock; |
09941366 RK |
5795 | |
5796 | r = kvm_ioapic_init(kvm); | |
5797 | if (r) { | |
09941366 | 5798 | kvm_pic_destroy(kvm); |
3ddea128 | 5799 | goto create_irqchip_unlock; |
09941366 RK |
5800 | } |
5801 | ||
399ec807 AK |
5802 | r = kvm_setup_default_irq_routing(kvm); |
5803 | if (r) { | |
72bb2fcd | 5804 | kvm_ioapic_destroy(kvm); |
09941366 | 5805 | kvm_pic_destroy(kvm); |
71ba994c | 5806 | goto create_irqchip_unlock; |
399ec807 | 5807 | } |
49776faf | 5808 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 5809 | smp_wmb(); |
49776faf | 5810 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
5811 | create_irqchip_unlock: |
5812 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 5813 | break; |
3ddea128 | 5814 | } |
7837699f | 5815 | case KVM_CREATE_PIT: |
c5ff41ce JK |
5816 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
5817 | goto create_pit; | |
5818 | case KVM_CREATE_PIT2: | |
5819 | r = -EFAULT; | |
5820 | if (copy_from_user(&u.pit_config, argp, | |
5821 | sizeof(struct kvm_pit_config))) | |
5822 | goto out; | |
5823 | create_pit: | |
250715a6 | 5824 | mutex_lock(&kvm->lock); |
269e05e4 AK |
5825 | r = -EEXIST; |
5826 | if (kvm->arch.vpit) | |
5827 | goto create_pit_unlock; | |
7837699f | 5828 | r = -ENOMEM; |
c5ff41ce | 5829 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
5830 | if (kvm->arch.vpit) |
5831 | r = 0; | |
269e05e4 | 5832 | create_pit_unlock: |
250715a6 | 5833 | mutex_unlock(&kvm->lock); |
7837699f | 5834 | break; |
1fe779f8 CO |
5835 | case KVM_GET_IRQCHIP: { |
5836 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5837 | struct kvm_irqchip *chip; |
1fe779f8 | 5838 | |
ff5c2c03 SL |
5839 | chip = memdup_user(argp, sizeof(*chip)); |
5840 | if (IS_ERR(chip)) { | |
5841 | r = PTR_ERR(chip); | |
1fe779f8 | 5842 | goto out; |
ff5c2c03 SL |
5843 | } |
5844 | ||
1fe779f8 | 5845 | r = -ENXIO; |
826da321 | 5846 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5847 | goto get_irqchip_out; |
5848 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 5849 | if (r) |
f0d66275 | 5850 | goto get_irqchip_out; |
1fe779f8 | 5851 | r = -EFAULT; |
0e96f31e | 5852 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 5853 | goto get_irqchip_out; |
1fe779f8 | 5854 | r = 0; |
f0d66275 DH |
5855 | get_irqchip_out: |
5856 | kfree(chip); | |
1fe779f8 CO |
5857 | break; |
5858 | } | |
5859 | case KVM_SET_IRQCHIP: { | |
5860 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5861 | struct kvm_irqchip *chip; |
1fe779f8 | 5862 | |
ff5c2c03 SL |
5863 | chip = memdup_user(argp, sizeof(*chip)); |
5864 | if (IS_ERR(chip)) { | |
5865 | r = PTR_ERR(chip); | |
1fe779f8 | 5866 | goto out; |
ff5c2c03 SL |
5867 | } |
5868 | ||
1fe779f8 | 5869 | r = -ENXIO; |
826da321 | 5870 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5871 | goto set_irqchip_out; |
5872 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
5873 | set_irqchip_out: |
5874 | kfree(chip); | |
1fe779f8 CO |
5875 | break; |
5876 | } | |
e0f63cb9 | 5877 | case KVM_GET_PIT: { |
e0f63cb9 | 5878 | r = -EFAULT; |
f0d66275 | 5879 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5880 | goto out; |
5881 | r = -ENXIO; | |
5882 | if (!kvm->arch.vpit) | |
5883 | goto out; | |
f0d66275 | 5884 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
5885 | if (r) |
5886 | goto out; | |
5887 | r = -EFAULT; | |
f0d66275 | 5888 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5889 | goto out; |
5890 | r = 0; | |
5891 | break; | |
5892 | } | |
5893 | case KVM_SET_PIT: { | |
e0f63cb9 | 5894 | r = -EFAULT; |
0e96f31e | 5895 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 | 5896 | goto out; |
7289fdb5 | 5897 | mutex_lock(&kvm->lock); |
e0f63cb9 SY |
5898 | r = -ENXIO; |
5899 | if (!kvm->arch.vpit) | |
7289fdb5 | 5900 | goto set_pit_out; |
f0d66275 | 5901 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
7289fdb5 SR |
5902 | set_pit_out: |
5903 | mutex_unlock(&kvm->lock); | |
e0f63cb9 SY |
5904 | break; |
5905 | } | |
e9f42757 BK |
5906 | case KVM_GET_PIT2: { |
5907 | r = -ENXIO; | |
5908 | if (!kvm->arch.vpit) | |
5909 | goto out; | |
5910 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
5911 | if (r) | |
5912 | goto out; | |
5913 | r = -EFAULT; | |
5914 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
5915 | goto out; | |
5916 | r = 0; | |
5917 | break; | |
5918 | } | |
5919 | case KVM_SET_PIT2: { | |
5920 | r = -EFAULT; | |
5921 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
5922 | goto out; | |
7289fdb5 | 5923 | mutex_lock(&kvm->lock); |
e9f42757 BK |
5924 | r = -ENXIO; |
5925 | if (!kvm->arch.vpit) | |
7289fdb5 | 5926 | goto set_pit2_out; |
e9f42757 | 5927 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); |
7289fdb5 SR |
5928 | set_pit2_out: |
5929 | mutex_unlock(&kvm->lock); | |
e9f42757 BK |
5930 | break; |
5931 | } | |
52d939a0 MT |
5932 | case KVM_REINJECT_CONTROL: { |
5933 | struct kvm_reinject_control control; | |
5934 | r = -EFAULT; | |
5935 | if (copy_from_user(&control, argp, sizeof(control))) | |
5936 | goto out; | |
cad23e72 ML |
5937 | r = -ENXIO; |
5938 | if (!kvm->arch.vpit) | |
5939 | goto out; | |
52d939a0 | 5940 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
5941 | break; |
5942 | } | |
d71ba788 PB |
5943 | case KVM_SET_BOOT_CPU_ID: |
5944 | r = 0; | |
5945 | mutex_lock(&kvm->lock); | |
557abc40 | 5946 | if (kvm->created_vcpus) |
d71ba788 PB |
5947 | r = -EBUSY; |
5948 | else | |
5949 | kvm->arch.bsp_vcpu_id = arg; | |
5950 | mutex_unlock(&kvm->lock); | |
5951 | break; | |
b59b153d | 5952 | #ifdef CONFIG_KVM_XEN |
ffde22ac | 5953 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 5954 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 5955 | r = -EFAULT; |
51776043 | 5956 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac | 5957 | goto out; |
78e9878c | 5958 | r = kvm_xen_hvm_config(kvm, &xhc); |
ffde22ac ES |
5959 | break; |
5960 | } | |
a76b9641 JM |
5961 | case KVM_XEN_HVM_GET_ATTR: { |
5962 | struct kvm_xen_hvm_attr xha; | |
5963 | ||
5964 | r = -EFAULT; | |
5965 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
ffde22ac | 5966 | goto out; |
a76b9641 JM |
5967 | r = kvm_xen_hvm_get_attr(kvm, &xha); |
5968 | if (!r && copy_to_user(argp, &xha, sizeof(xha))) | |
5969 | r = -EFAULT; | |
5970 | break; | |
5971 | } | |
5972 | case KVM_XEN_HVM_SET_ATTR: { | |
5973 | struct kvm_xen_hvm_attr xha; | |
5974 | ||
5975 | r = -EFAULT; | |
5976 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
5977 | goto out; | |
5978 | r = kvm_xen_hvm_set_attr(kvm, &xha); | |
ffde22ac ES |
5979 | break; |
5980 | } | |
b59b153d | 5981 | #endif |
afbcf7ab | 5982 | case KVM_SET_CLOCK: { |
77fcbe82 | 5983 | struct kvm_arch *ka = &kvm->arch; |
afbcf7ab GC |
5984 | struct kvm_clock_data user_ns; |
5985 | u64 now_ns; | |
afbcf7ab GC |
5986 | |
5987 | r = -EFAULT; | |
5988 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
5989 | goto out; | |
5990 | ||
5991 | r = -EINVAL; | |
5992 | if (user_ns.flags) | |
5993 | goto out; | |
5994 | ||
5995 | r = 0; | |
0bc48bea RK |
5996 | /* |
5997 | * TODO: userspace has to take care of races with VCPU_RUN, so | |
5998 | * kvm_gen_update_masterclock() can be cut down to locked | |
5999 | * pvclock_update_vm_gtod_copy(). | |
6000 | */ | |
6001 | kvm_gen_update_masterclock(kvm); | |
77fcbe82 VK |
6002 | |
6003 | /* | |
6004 | * This pairs with kvm_guest_time_update(): when masterclock is | |
6005 | * in use, we use master_kernel_ns + kvmclock_offset to set | |
6006 | * unsigned 'system_time' so if we use get_kvmclock_ns() (which | |
6007 | * is slightly ahead) here we risk going negative on unsigned | |
6008 | * 'system_time' when 'user_ns.clock' is very small. | |
6009 | */ | |
6010 | spin_lock_irq(&ka->pvclock_gtod_sync_lock); | |
6011 | if (kvm->arch.use_master_clock) | |
6012 | now_ns = ka->master_kernel_ns; | |
6013 | else | |
6014 | now_ns = get_kvmclock_base_ns(); | |
6015 | ka->kvmclock_offset = user_ns.clock - now_ns; | |
6016 | spin_unlock_irq(&ka->pvclock_gtod_sync_lock); | |
6017 | ||
0bc48bea | 6018 | kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); |
afbcf7ab GC |
6019 | break; |
6020 | } | |
6021 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
6022 | struct kvm_clock_data user_ns; |
6023 | u64 now_ns; | |
6024 | ||
e891a32e | 6025 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 6026 | user_ns.clock = now_ns; |
e3fd9a93 | 6027 | user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; |
97e69aa6 | 6028 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
6029 | |
6030 | r = -EFAULT; | |
6031 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
6032 | goto out; | |
6033 | r = 0; | |
6034 | break; | |
6035 | } | |
5acc5c06 BS |
6036 | case KVM_MEMORY_ENCRYPT_OP: { |
6037 | r = -ENOTTY; | |
afaf0b2f | 6038 | if (kvm_x86_ops.mem_enc_op) |
b3646477 | 6039 | r = static_call(kvm_x86_mem_enc_op)(kvm, argp); |
5acc5c06 BS |
6040 | break; |
6041 | } | |
69eaedee BS |
6042 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
6043 | struct kvm_enc_region region; | |
6044 | ||
6045 | r = -EFAULT; | |
6046 | if (copy_from_user(®ion, argp, sizeof(region))) | |
6047 | goto out; | |
6048 | ||
6049 | r = -ENOTTY; | |
afaf0b2f | 6050 | if (kvm_x86_ops.mem_enc_reg_region) |
b3646477 | 6051 | r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); |
69eaedee BS |
6052 | break; |
6053 | } | |
6054 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
6055 | struct kvm_enc_region region; | |
6056 | ||
6057 | r = -EFAULT; | |
6058 | if (copy_from_user(®ion, argp, sizeof(region))) | |
6059 | goto out; | |
6060 | ||
6061 | r = -ENOTTY; | |
afaf0b2f | 6062 | if (kvm_x86_ops.mem_enc_unreg_region) |
b3646477 | 6063 | r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); |
69eaedee BS |
6064 | break; |
6065 | } | |
faeb7833 RK |
6066 | case KVM_HYPERV_EVENTFD: { |
6067 | struct kvm_hyperv_eventfd hvevfd; | |
6068 | ||
6069 | r = -EFAULT; | |
6070 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
6071 | goto out; | |
6072 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
6073 | break; | |
6074 | } | |
66bb8a06 EH |
6075 | case KVM_SET_PMU_EVENT_FILTER: |
6076 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
6077 | break; | |
1a155254 AG |
6078 | case KVM_X86_SET_MSR_FILTER: |
6079 | r = kvm_vm_ioctl_set_msr_filter(kvm, argp); | |
6080 | break; | |
1fe779f8 | 6081 | default: |
ad6260da | 6082 | r = -ENOTTY; |
1fe779f8 CO |
6083 | } |
6084 | out: | |
6085 | return r; | |
6086 | } | |
6087 | ||
a16b043c | 6088 | static void kvm_init_msr_list(void) |
043405e1 | 6089 | { |
24c29b7a | 6090 | struct x86_pmu_capability x86_pmu; |
043405e1 | 6091 | u32 dummy[2]; |
7a5ee6ed | 6092 | unsigned i; |
043405e1 | 6093 | |
e2ada66e | 6094 | BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, |
7a5ee6ed | 6095 | "Please update the fixed PMCs in msrs_to_saved_all[]"); |
24c29b7a PB |
6096 | |
6097 | perf_get_x86_pmu_capability(&x86_pmu); | |
e2ada66e | 6098 | |
6cbee2b9 XL |
6099 | num_msrs_to_save = 0; |
6100 | num_emulated_msrs = 0; | |
6101 | num_msr_based_features = 0; | |
6102 | ||
7a5ee6ed CQ |
6103 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { |
6104 | if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) | |
043405e1 | 6105 | continue; |
93c4adc7 PB |
6106 | |
6107 | /* | |
6108 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 6109 | * to the guests in some cases. |
93c4adc7 | 6110 | */ |
7a5ee6ed | 6111 | switch (msrs_to_save_all[i]) { |
93c4adc7 | 6112 | case MSR_IA32_BNDCFGS: |
503234b3 | 6113 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
6114 | continue; |
6115 | break; | |
9dbe6cf9 | 6116 | case MSR_TSC_AUX: |
36fa06f9 SC |
6117 | if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && |
6118 | !kvm_cpu_cap_has(X86_FEATURE_RDPID)) | |
9dbe6cf9 PB |
6119 | continue; |
6120 | break; | |
f4cfcd2d ML |
6121 | case MSR_IA32_UMWAIT_CONTROL: |
6122 | if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) | |
6123 | continue; | |
6124 | break; | |
bf8c55d8 CP |
6125 | case MSR_IA32_RTIT_CTL: |
6126 | case MSR_IA32_RTIT_STATUS: | |
7b874c26 | 6127 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) |
bf8c55d8 CP |
6128 | continue; |
6129 | break; | |
6130 | case MSR_IA32_RTIT_CR3_MATCH: | |
7b874c26 | 6131 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
6132 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) |
6133 | continue; | |
6134 | break; | |
6135 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
6136 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
7b874c26 | 6137 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
6138 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && |
6139 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
6140 | continue; | |
6141 | break; | |
7cb85fc4 | 6142 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: |
7b874c26 | 6143 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
7a5ee6ed | 6144 | msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= |
bf8c55d8 CP |
6145 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) |
6146 | continue; | |
6147 | break; | |
cf05a67b | 6148 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: |
7a5ee6ed | 6149 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= |
24c29b7a PB |
6150 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
6151 | continue; | |
6152 | break; | |
cf05a67b | 6153 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: |
7a5ee6ed | 6154 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= |
24c29b7a PB |
6155 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
6156 | continue; | |
7cb85fc4 | 6157 | break; |
93c4adc7 PB |
6158 | default: |
6159 | break; | |
6160 | } | |
6161 | ||
7a5ee6ed | 6162 | msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; |
043405e1 | 6163 | } |
62ef68bb | 6164 | |
7a5ee6ed | 6165 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
b3646477 | 6166 | if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) |
bc226f07 | 6167 | continue; |
62ef68bb | 6168 | |
7a5ee6ed | 6169 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 6170 | } |
801e459a | 6171 | |
7a5ee6ed | 6172 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { |
801e459a TL |
6173 | struct kvm_msr_entry msr; |
6174 | ||
7a5ee6ed | 6175 | msr.index = msr_based_features_all[i]; |
66421c1e | 6176 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
6177 | continue; |
6178 | ||
7a5ee6ed | 6179 | msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; |
801e459a | 6180 | } |
043405e1 CO |
6181 | } |
6182 | ||
bda9020e MT |
6183 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
6184 | const void *v) | |
bbd9b64e | 6185 | { |
70252a10 AK |
6186 | int handled = 0; |
6187 | int n; | |
6188 | ||
6189 | do { | |
6190 | n = min(len, 8); | |
bce87cce | 6191 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
6192 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
6193 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
6194 | break; |
6195 | handled += n; | |
6196 | addr += n; | |
6197 | len -= n; | |
6198 | v += n; | |
6199 | } while (len); | |
bbd9b64e | 6200 | |
70252a10 | 6201 | return handled; |
bbd9b64e CO |
6202 | } |
6203 | ||
bda9020e | 6204 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 6205 | { |
70252a10 AK |
6206 | int handled = 0; |
6207 | int n; | |
6208 | ||
6209 | do { | |
6210 | n = min(len, 8); | |
bce87cce | 6211 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
6212 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
6213 | addr, n, v)) | |
6214 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 6215 | break; |
e39d200f | 6216 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
6217 | handled += n; |
6218 | addr += n; | |
6219 | len -= n; | |
6220 | v += n; | |
6221 | } while (len); | |
bbd9b64e | 6222 | |
70252a10 | 6223 | return handled; |
bbd9b64e CO |
6224 | } |
6225 | ||
2dafc6c2 GN |
6226 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
6227 | struct kvm_segment *var, int seg) | |
6228 | { | |
b3646477 | 6229 | static_call(kvm_x86_set_segment)(vcpu, var, seg); |
2dafc6c2 GN |
6230 | } |
6231 | ||
6232 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
6233 | struct kvm_segment *var, int seg) | |
6234 | { | |
b3646477 | 6235 | static_call(kvm_x86_get_segment)(vcpu, var, seg); |
2dafc6c2 GN |
6236 | } |
6237 | ||
54987b7a PB |
6238 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
6239 | struct x86_exception *exception) | |
02f59dc9 JR |
6240 | { |
6241 | gpa_t t_gpa; | |
02f59dc9 JR |
6242 | |
6243 | BUG_ON(!mmu_is_nested(vcpu)); | |
6244 | ||
6245 | /* NPT walks are always user-walks */ | |
6246 | access |= PFERR_USER_MASK; | |
44dd3ffa | 6247 | t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
6248 | |
6249 | return t_gpa; | |
6250 | } | |
6251 | ||
ab9ae313 AK |
6252 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
6253 | struct x86_exception *exception) | |
1871c602 | 6254 | { |
b3646477 | 6255 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
ab9ae313 | 6256 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 | 6257 | } |
54f958cd | 6258 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); |
1871c602 | 6259 | |
ab9ae313 AK |
6260 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
6261 | struct x86_exception *exception) | |
1871c602 | 6262 | { |
b3646477 | 6263 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 6264 | access |= PFERR_FETCH_MASK; |
ab9ae313 | 6265 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
6266 | } |
6267 | ||
ab9ae313 AK |
6268 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
6269 | struct x86_exception *exception) | |
1871c602 | 6270 | { |
b3646477 | 6271 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 6272 | access |= PFERR_WRITE_MASK; |
ab9ae313 | 6273 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 | 6274 | } |
54f958cd | 6275 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); |
1871c602 GN |
6276 | |
6277 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
6278 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
6279 | struct x86_exception *exception) | |
1871c602 | 6280 | { |
ab9ae313 | 6281 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
6282 | } |
6283 | ||
6284 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
6285 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 6286 | struct x86_exception *exception) |
bbd9b64e CO |
6287 | { |
6288 | void *data = val; | |
10589a46 | 6289 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
6290 | |
6291 | while (bytes) { | |
14dfe855 | 6292 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 6293 | exception); |
bbd9b64e | 6294 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 6295 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
6296 | int ret; |
6297 | ||
bcc55cba | 6298 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6299 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
6300 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
6301 | offset, toread); | |
10589a46 | 6302 | if (ret < 0) { |
c3cd7ffa | 6303 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
6304 | goto out; |
6305 | } | |
bbd9b64e | 6306 | |
77c2002e IE |
6307 | bytes -= toread; |
6308 | data += toread; | |
6309 | addr += toread; | |
bbd9b64e | 6310 | } |
10589a46 | 6311 | out: |
10589a46 | 6312 | return r; |
bbd9b64e | 6313 | } |
77c2002e | 6314 | |
1871c602 | 6315 | /* used for instruction fetching */ |
0f65dd70 AK |
6316 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
6317 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 6318 | struct x86_exception *exception) |
1871c602 | 6319 | { |
0f65dd70 | 6320 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
b3646477 | 6321 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
6322 | unsigned offset; |
6323 | int ret; | |
0f65dd70 | 6324 | |
44583cba PB |
6325 | /* Inline kvm_read_guest_virt_helper for speed. */ |
6326 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
6327 | exception); | |
6328 | if (unlikely(gpa == UNMAPPED_GVA)) | |
6329 | return X86EMUL_PROPAGATE_FAULT; | |
6330 | ||
6331 | offset = addr & (PAGE_SIZE-1); | |
6332 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
6333 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
6334 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
6335 | offset, bytes); | |
44583cba PB |
6336 | if (unlikely(ret < 0)) |
6337 | return X86EMUL_IO_NEEDED; | |
6338 | ||
6339 | return X86EMUL_CONTINUE; | |
1871c602 GN |
6340 | } |
6341 | ||
ce14e868 | 6342 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 6343 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 6344 | struct x86_exception *exception) |
1871c602 | 6345 | { |
b3646477 | 6346 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 6347 | |
353c0956 PB |
6348 | /* |
6349 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
6350 | * is returned, but our callers are not ready for that and they blindly | |
6351 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
6352 | * uninitialized kernel stack memory into cr2 and error code. | |
6353 | */ | |
6354 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 6355 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 6356 | exception); |
1871c602 | 6357 | } |
064aea77 | 6358 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 6359 | |
ce14e868 PB |
6360 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
6361 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 6362 | struct x86_exception *exception, bool system) |
1871c602 | 6363 | { |
0f65dd70 | 6364 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3c9fa24c PB |
6365 | u32 access = 0; |
6366 | ||
b3646477 | 6367 | if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) |
3c9fa24c PB |
6368 | access |= PFERR_USER_MASK; |
6369 | ||
6370 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
6371 | } |
6372 | ||
7a036a6f RK |
6373 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
6374 | unsigned long addr, void *val, unsigned int bytes) | |
6375 | { | |
6376 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6377 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
6378 | ||
6379 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
6380 | } | |
6381 | ||
ce14e868 PB |
6382 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
6383 | struct kvm_vcpu *vcpu, u32 access, | |
6384 | struct x86_exception *exception) | |
77c2002e IE |
6385 | { |
6386 | void *data = val; | |
6387 | int r = X86EMUL_CONTINUE; | |
6388 | ||
6389 | while (bytes) { | |
14dfe855 | 6390 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
ce14e868 | 6391 | access, |
ab9ae313 | 6392 | exception); |
77c2002e IE |
6393 | unsigned offset = addr & (PAGE_SIZE-1); |
6394 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
6395 | int ret; | |
6396 | ||
bcc55cba | 6397 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6398 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 6399 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 6400 | if (ret < 0) { |
c3cd7ffa | 6401 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
6402 | goto out; |
6403 | } | |
6404 | ||
6405 | bytes -= towrite; | |
6406 | data += towrite; | |
6407 | addr += towrite; | |
6408 | } | |
6409 | out: | |
6410 | return r; | |
6411 | } | |
ce14e868 PB |
6412 | |
6413 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
6414 | unsigned int bytes, struct x86_exception *exception, |
6415 | bool system) | |
ce14e868 PB |
6416 | { |
6417 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
3c9fa24c PB |
6418 | u32 access = PFERR_WRITE_MASK; |
6419 | ||
b3646477 | 6420 | if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) |
3c9fa24c | 6421 | access |= PFERR_USER_MASK; |
ce14e868 PB |
6422 | |
6423 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 6424 | access, exception); |
ce14e868 PB |
6425 | } |
6426 | ||
6427 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
6428 | unsigned int bytes, struct x86_exception *exception) | |
6429 | { | |
c595ceee PB |
6430 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
6431 | vcpu->arch.l1tf_flush_l1d = true; | |
6432 | ||
ce14e868 PB |
6433 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
6434 | PFERR_WRITE_MASK, exception); | |
6435 | } | |
6a4d7550 | 6436 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 6437 | |
082d06ed WL |
6438 | int handle_ud(struct kvm_vcpu *vcpu) |
6439 | { | |
b3dc0695 | 6440 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
6c86eedc | 6441 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
6442 | char sig[5]; /* ud2; .ascii "kvm" */ |
6443 | struct x86_exception e; | |
6444 | ||
b3646477 | 6445 | if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) |
09e3e2a1 SC |
6446 | return 1; |
6447 | ||
6c86eedc | 6448 | if (force_emulation_prefix && |
3c9fa24c PB |
6449 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
6450 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 6451 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
6c86eedc | 6452 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 6453 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 6454 | } |
082d06ed | 6455 | |
60fc3d02 | 6456 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
6457 | } |
6458 | EXPORT_SYMBOL_GPL(handle_ud); | |
6459 | ||
0f89b207 TL |
6460 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6461 | gpa_t gpa, bool write) | |
6462 | { | |
6463 | /* For APIC access vmexit */ | |
6464 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6465 | return 1; | |
6466 | ||
6467 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
6468 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
6469 | return 1; | |
6470 | } | |
6471 | ||
6472 | return 0; | |
6473 | } | |
6474 | ||
af7cc7d1 XG |
6475 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6476 | gpa_t *gpa, struct x86_exception *exception, | |
6477 | bool write) | |
6478 | { | |
b3646477 | 6479 | u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) |
97d64b78 | 6480 | | (write ? PFERR_WRITE_MASK : 0); |
af7cc7d1 | 6481 | |
be94f6b7 HH |
6482 | /* |
6483 | * currently PKRU is only applied to ept enabled guest so | |
6484 | * there is no pkey in EPT page table for L1 guest or EPT | |
6485 | * shadow page table for L2 guest. | |
6486 | */ | |
97d64b78 | 6487 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 | 6488 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
871bd034 | 6489 | vcpu->arch.mmio_access, 0, access)) { |
bebb106a XG |
6490 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
6491 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 6492 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
6493 | return 1; |
6494 | } | |
6495 | ||
af7cc7d1 XG |
6496 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
6497 | ||
6498 | if (*gpa == UNMAPPED_GVA) | |
6499 | return -1; | |
6500 | ||
0f89b207 | 6501 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
6502 | } |
6503 | ||
3200f405 | 6504 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 6505 | const void *val, int bytes) |
bbd9b64e CO |
6506 | { |
6507 | int ret; | |
6508 | ||
54bf36aa | 6509 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 6510 | if (ret < 0) |
bbd9b64e | 6511 | return 0; |
0eb05bf2 | 6512 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
6513 | return 1; |
6514 | } | |
6515 | ||
77d197b2 XG |
6516 | struct read_write_emulator_ops { |
6517 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
6518 | int bytes); | |
6519 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6520 | void *val, int bytes); | |
6521 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6522 | int bytes, void *val); | |
6523 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6524 | void *val, int bytes); | |
6525 | bool write; | |
6526 | }; | |
6527 | ||
6528 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
6529 | { | |
6530 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 6531 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 6532 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
6533 | vcpu->mmio_read_completed = 0; |
6534 | return 1; | |
6535 | } | |
6536 | ||
6537 | return 0; | |
6538 | } | |
6539 | ||
6540 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6541 | void *val, int bytes) | |
6542 | { | |
54bf36aa | 6543 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
6544 | } |
6545 | ||
6546 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6547 | void *val, int bytes) | |
6548 | { | |
6549 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
6550 | } | |
6551 | ||
6552 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
6553 | { | |
e39d200f | 6554 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
6555 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
6556 | } | |
6557 | ||
6558 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6559 | void *val, int bytes) | |
6560 | { | |
e39d200f | 6561 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
6562 | return X86EMUL_IO_NEEDED; |
6563 | } | |
6564 | ||
6565 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6566 | void *val, int bytes) | |
6567 | { | |
f78146b0 AK |
6568 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
6569 | ||
87da7e66 | 6570 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
6571 | return X86EMUL_CONTINUE; |
6572 | } | |
6573 | ||
0fbe9b0b | 6574 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
6575 | .read_write_prepare = read_prepare, |
6576 | .read_write_emulate = read_emulate, | |
6577 | .read_write_mmio = vcpu_mmio_read, | |
6578 | .read_write_exit_mmio = read_exit_mmio, | |
6579 | }; | |
6580 | ||
0fbe9b0b | 6581 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
6582 | .read_write_emulate = write_emulate, |
6583 | .read_write_mmio = write_mmio, | |
6584 | .read_write_exit_mmio = write_exit_mmio, | |
6585 | .write = true, | |
6586 | }; | |
6587 | ||
22388a3c XG |
6588 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
6589 | unsigned int bytes, | |
6590 | struct x86_exception *exception, | |
6591 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 6592 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6593 | { |
af7cc7d1 XG |
6594 | gpa_t gpa; |
6595 | int handled, ret; | |
22388a3c | 6596 | bool write = ops->write; |
f78146b0 | 6597 | struct kvm_mmio_fragment *frag; |
c9b8b07c | 6598 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
0f89b207 TL |
6599 | |
6600 | /* | |
6601 | * If the exit was due to a NPF we may already have a GPA. | |
6602 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
6603 | * Note, this cannot be used on string operations since string | |
6604 | * operation using rep will only have the initial GPA from the NPF | |
6605 | * occurred. | |
6606 | */ | |
744e699c SC |
6607 | if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && |
6608 | (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { | |
6609 | gpa = ctxt->gpa_val; | |
618232e2 BS |
6610 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); |
6611 | } else { | |
6612 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
6613 | if (ret < 0) | |
6614 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 6615 | } |
10589a46 | 6616 | |
618232e2 | 6617 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
6618 | return X86EMUL_CONTINUE; |
6619 | ||
bbd9b64e CO |
6620 | /* |
6621 | * Is this MMIO handled locally? | |
6622 | */ | |
22388a3c | 6623 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 6624 | if (handled == bytes) |
bbd9b64e | 6625 | return X86EMUL_CONTINUE; |
bbd9b64e | 6626 | |
70252a10 AK |
6627 | gpa += handled; |
6628 | bytes -= handled; | |
6629 | val += handled; | |
6630 | ||
87da7e66 XG |
6631 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
6632 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
6633 | frag->gpa = gpa; | |
6634 | frag->data = val; | |
6635 | frag->len = bytes; | |
f78146b0 | 6636 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
6637 | } |
6638 | ||
52eb5a6d XL |
6639 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
6640 | unsigned long addr, | |
22388a3c XG |
6641 | void *val, unsigned int bytes, |
6642 | struct x86_exception *exception, | |
0fbe9b0b | 6643 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6644 | { |
0f65dd70 | 6645 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
6646 | gpa_t gpa; |
6647 | int rc; | |
6648 | ||
6649 | if (ops->read_write_prepare && | |
6650 | ops->read_write_prepare(vcpu, val, bytes)) | |
6651 | return X86EMUL_CONTINUE; | |
6652 | ||
6653 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 6654 | |
bbd9b64e CO |
6655 | /* Crossing a page boundary? */ |
6656 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 6657 | int now; |
bbd9b64e CO |
6658 | |
6659 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
6660 | rc = emulator_read_write_onepage(addr, val, now, exception, |
6661 | vcpu, ops); | |
6662 | ||
bbd9b64e CO |
6663 | if (rc != X86EMUL_CONTINUE) |
6664 | return rc; | |
6665 | addr += now; | |
bac15531 NA |
6666 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6667 | addr = (u32)addr; | |
bbd9b64e CO |
6668 | val += now; |
6669 | bytes -= now; | |
6670 | } | |
22388a3c | 6671 | |
f78146b0 AK |
6672 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
6673 | vcpu, ops); | |
6674 | if (rc != X86EMUL_CONTINUE) | |
6675 | return rc; | |
6676 | ||
6677 | if (!vcpu->mmio_nr_fragments) | |
6678 | return rc; | |
6679 | ||
6680 | gpa = vcpu->mmio_fragments[0].gpa; | |
6681 | ||
6682 | vcpu->mmio_needed = 1; | |
6683 | vcpu->mmio_cur_fragment = 0; | |
6684 | ||
87da7e66 | 6685 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
6686 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
6687 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
6688 | vcpu->run->mmio.phys_addr = gpa; | |
6689 | ||
6690 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
6691 | } |
6692 | ||
6693 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
6694 | unsigned long addr, | |
6695 | void *val, | |
6696 | unsigned int bytes, | |
6697 | struct x86_exception *exception) | |
6698 | { | |
6699 | return emulator_read_write(ctxt, addr, val, bytes, | |
6700 | exception, &read_emultor); | |
6701 | } | |
6702 | ||
52eb5a6d | 6703 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
6704 | unsigned long addr, |
6705 | const void *val, | |
6706 | unsigned int bytes, | |
6707 | struct x86_exception *exception) | |
6708 | { | |
6709 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
6710 | exception, &write_emultor); | |
bbd9b64e | 6711 | } |
bbd9b64e | 6712 | |
daea3e73 AK |
6713 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
6714 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
6715 | ||
6716 | #ifdef CONFIG_X86_64 | |
6717 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
6718 | #else | |
6719 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 6720 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
6721 | #endif |
6722 | ||
0f65dd70 AK |
6723 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
6724 | unsigned long addr, | |
bbd9b64e CO |
6725 | const void *old, |
6726 | const void *new, | |
6727 | unsigned int bytes, | |
0f65dd70 | 6728 | struct x86_exception *exception) |
bbd9b64e | 6729 | { |
42e35f80 | 6730 | struct kvm_host_map map; |
0f65dd70 | 6731 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
9de6fe3c | 6732 | u64 page_line_mask; |
daea3e73 | 6733 | gpa_t gpa; |
daea3e73 AK |
6734 | char *kaddr; |
6735 | bool exchanged; | |
2bacc55c | 6736 | |
daea3e73 AK |
6737 | /* guests cmpxchg8b have to be emulated atomically */ |
6738 | if (bytes > 8 || (bytes & (bytes - 1))) | |
6739 | goto emul_write; | |
10589a46 | 6740 | |
daea3e73 | 6741 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 6742 | |
daea3e73 AK |
6743 | if (gpa == UNMAPPED_GVA || |
6744 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6745 | goto emul_write; | |
2bacc55c | 6746 | |
9de6fe3c XL |
6747 | /* |
6748 | * Emulate the atomic as a straight write to avoid #AC if SLD is | |
6749 | * enabled in the host and the access splits a cache line. | |
6750 | */ | |
6751 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
6752 | page_line_mask = ~(cache_line_size() - 1); | |
6753 | else | |
6754 | page_line_mask = PAGE_MASK; | |
6755 | ||
6756 | if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) | |
daea3e73 | 6757 | goto emul_write; |
72dc67a6 | 6758 | |
42e35f80 | 6759 | if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) |
c19b8bd6 | 6760 | goto emul_write; |
72dc67a6 | 6761 | |
42e35f80 KA |
6762 | kaddr = map.hva + offset_in_page(gpa); |
6763 | ||
daea3e73 AK |
6764 | switch (bytes) { |
6765 | case 1: | |
6766 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
6767 | break; | |
6768 | case 2: | |
6769 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
6770 | break; | |
6771 | case 4: | |
6772 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
6773 | break; | |
6774 | case 8: | |
6775 | exchanged = CMPXCHG64(kaddr, old, new); | |
6776 | break; | |
6777 | default: | |
6778 | BUG(); | |
2bacc55c | 6779 | } |
42e35f80 KA |
6780 | |
6781 | kvm_vcpu_unmap(vcpu, &map, true); | |
daea3e73 AK |
6782 | |
6783 | if (!exchanged) | |
6784 | return X86EMUL_CMPXCHG_FAILED; | |
6785 | ||
0eb05bf2 | 6786 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
6787 | |
6788 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 6789 | |
3200f405 | 6790 | emul_write: |
daea3e73 | 6791 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 6792 | |
0f65dd70 | 6793 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
6794 | } |
6795 | ||
cf8f70bf GN |
6796 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
6797 | { | |
cbfc6c91 | 6798 | int r = 0, i; |
cf8f70bf | 6799 | |
cbfc6c91 WL |
6800 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
6801 | if (vcpu->arch.pio.in) | |
6802 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
6803 | vcpu->arch.pio.size, pd); | |
6804 | else | |
6805 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
6806 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
6807 | pd); | |
6808 | if (r) | |
6809 | break; | |
6810 | pd += vcpu->arch.pio.size; | |
6811 | } | |
cf8f70bf GN |
6812 | return r; |
6813 | } | |
6814 | ||
6f6fbe98 XG |
6815 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
6816 | unsigned short port, void *val, | |
6817 | unsigned int count, bool in) | |
cf8f70bf | 6818 | { |
cf8f70bf | 6819 | vcpu->arch.pio.port = port; |
6f6fbe98 | 6820 | vcpu->arch.pio.in = in; |
7972995b | 6821 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
6822 | vcpu->arch.pio.size = size; |
6823 | ||
6824 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 6825 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6826 | return 1; |
6827 | } | |
6828 | ||
6829 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 6830 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
6831 | vcpu->run->io.size = size; |
6832 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
6833 | vcpu->run->io.count = count; | |
6834 | vcpu->run->io.port = port; | |
6835 | ||
6836 | return 0; | |
6837 | } | |
6838 | ||
2e3bb4d8 SC |
6839 | static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
6840 | unsigned short port, void *val, unsigned int count) | |
cf8f70bf | 6841 | { |
6f6fbe98 | 6842 | int ret; |
ca1d4a9e | 6843 | |
6f6fbe98 XG |
6844 | if (vcpu->arch.pio.count) |
6845 | goto data_avail; | |
cf8f70bf | 6846 | |
cbfc6c91 WL |
6847 | memset(vcpu->arch.pio_data, 0, size * count); |
6848 | ||
6f6fbe98 XG |
6849 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
6850 | if (ret) { | |
6851 | data_avail: | |
6852 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 6853 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 6854 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6855 | return 1; |
6856 | } | |
6857 | ||
cf8f70bf GN |
6858 | return 0; |
6859 | } | |
6860 | ||
2e3bb4d8 SC |
6861 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
6862 | int size, unsigned short port, void *val, | |
6863 | unsigned int count) | |
6f6fbe98 | 6864 | { |
2e3bb4d8 | 6865 | return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); |
6f6fbe98 | 6866 | |
2e3bb4d8 | 6867 | } |
6f6fbe98 | 6868 | |
2e3bb4d8 SC |
6869 | static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, |
6870 | unsigned short port, const void *val, | |
6871 | unsigned int count) | |
6872 | { | |
6f6fbe98 | 6873 | memcpy(vcpu->arch.pio_data, val, size * count); |
1171903d | 6874 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
6875 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
6876 | } | |
6877 | ||
2e3bb4d8 SC |
6878 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
6879 | int size, unsigned short port, | |
6880 | const void *val, unsigned int count) | |
6881 | { | |
6882 | return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); | |
6883 | } | |
6884 | ||
bbd9b64e CO |
6885 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
6886 | { | |
b3646477 | 6887 | return static_call(kvm_x86_get_segment_base)(vcpu, seg); |
bbd9b64e CO |
6888 | } |
6889 | ||
3cb16fe7 | 6890 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 6891 | { |
3cb16fe7 | 6892 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
6893 | } |
6894 | ||
ae6a2375 | 6895 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
6896 | { |
6897 | if (!need_emulate_wbinvd(vcpu)) | |
6898 | return X86EMUL_CONTINUE; | |
6899 | ||
b3646477 | 6900 | if (static_call(kvm_x86_has_wbinvd_exit)()) { |
2eec7343 JK |
6901 | int cpu = get_cpu(); |
6902 | ||
6903 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
c2162e13 | 6904 | on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, |
f5f48ee1 | 6905 | wbinvd_ipi, NULL, 1); |
2eec7343 | 6906 | put_cpu(); |
f5f48ee1 | 6907 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
6908 | } else |
6909 | wbinvd(); | |
f5f48ee1 SY |
6910 | return X86EMUL_CONTINUE; |
6911 | } | |
5cb56059 JS |
6912 | |
6913 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
6914 | { | |
6affcbed KH |
6915 | kvm_emulate_wbinvd_noskip(vcpu); |
6916 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 6917 | } |
f5f48ee1 SY |
6918 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
6919 | ||
5cb56059 JS |
6920 | |
6921 | ||
bcaf5cc5 AK |
6922 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
6923 | { | |
5cb56059 | 6924 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
6925 | } |
6926 | ||
29d6ca41 PB |
6927 | static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6928 | unsigned long *dest) | |
bbd9b64e | 6929 | { |
29d6ca41 | 6930 | kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
6931 | } |
6932 | ||
52eb5a6d XL |
6933 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6934 | unsigned long value) | |
bbd9b64e | 6935 | { |
338dbc97 | 6936 | |
996ff542 | 6937 | return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
6938 | } |
6939 | ||
52a46617 | 6940 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 6941 | { |
52a46617 | 6942 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
6943 | } |
6944 | ||
717746e3 | 6945 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 6946 | { |
717746e3 | 6947 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
6948 | unsigned long value; |
6949 | ||
6950 | switch (cr) { | |
6951 | case 0: | |
6952 | value = kvm_read_cr0(vcpu); | |
6953 | break; | |
6954 | case 2: | |
6955 | value = vcpu->arch.cr2; | |
6956 | break; | |
6957 | case 3: | |
9f8fe504 | 6958 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
6959 | break; |
6960 | case 4: | |
6961 | value = kvm_read_cr4(vcpu); | |
6962 | break; | |
6963 | case 8: | |
6964 | value = kvm_get_cr8(vcpu); | |
6965 | break; | |
6966 | default: | |
a737f256 | 6967 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
6968 | return 0; |
6969 | } | |
6970 | ||
6971 | return value; | |
6972 | } | |
6973 | ||
717746e3 | 6974 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 6975 | { |
717746e3 | 6976 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
6977 | int res = 0; |
6978 | ||
52a46617 GN |
6979 | switch (cr) { |
6980 | case 0: | |
49a9b07e | 6981 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
6982 | break; |
6983 | case 2: | |
6984 | vcpu->arch.cr2 = val; | |
6985 | break; | |
6986 | case 3: | |
2390218b | 6987 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
6988 | break; |
6989 | case 4: | |
a83b29c6 | 6990 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
6991 | break; |
6992 | case 8: | |
eea1cff9 | 6993 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
6994 | break; |
6995 | default: | |
a737f256 | 6996 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 6997 | res = -1; |
52a46617 | 6998 | } |
0f12244f GN |
6999 | |
7000 | return res; | |
52a46617 GN |
7001 | } |
7002 | ||
717746e3 | 7003 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 7004 | { |
b3646477 | 7005 | return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); |
9c537244 GN |
7006 | } |
7007 | ||
4bff1e86 | 7008 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 7009 | { |
b3646477 | 7010 | static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
7011 | } |
7012 | ||
4bff1e86 | 7013 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 7014 | { |
b3646477 | 7015 | static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
7016 | } |
7017 | ||
1ac9d0cf AK |
7018 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
7019 | { | |
b3646477 | 7020 | static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
7021 | } |
7022 | ||
7023 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
7024 | { | |
b3646477 | 7025 | static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
7026 | } |
7027 | ||
4bff1e86 AK |
7028 | static unsigned long emulator_get_cached_segment_base( |
7029 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 7030 | { |
4bff1e86 | 7031 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
7032 | } |
7033 | ||
1aa36616 AK |
7034 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
7035 | struct desc_struct *desc, u32 *base3, | |
7036 | int seg) | |
2dafc6c2 GN |
7037 | { |
7038 | struct kvm_segment var; | |
7039 | ||
4bff1e86 | 7040 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 7041 | *selector = var.selector; |
2dafc6c2 | 7042 | |
378a8b09 GN |
7043 | if (var.unusable) { |
7044 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
7045 | if (base3) |
7046 | *base3 = 0; | |
2dafc6c2 | 7047 | return false; |
378a8b09 | 7048 | } |
2dafc6c2 GN |
7049 | |
7050 | if (var.g) | |
7051 | var.limit >>= 12; | |
7052 | set_desc_limit(desc, var.limit); | |
7053 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
7054 | #ifdef CONFIG_X86_64 |
7055 | if (base3) | |
7056 | *base3 = var.base >> 32; | |
7057 | #endif | |
2dafc6c2 GN |
7058 | desc->type = var.type; |
7059 | desc->s = var.s; | |
7060 | desc->dpl = var.dpl; | |
7061 | desc->p = var.present; | |
7062 | desc->avl = var.avl; | |
7063 | desc->l = var.l; | |
7064 | desc->d = var.db; | |
7065 | desc->g = var.g; | |
7066 | ||
7067 | return true; | |
7068 | } | |
7069 | ||
1aa36616 AK |
7070 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
7071 | struct desc_struct *desc, u32 base3, | |
7072 | int seg) | |
2dafc6c2 | 7073 | { |
4bff1e86 | 7074 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
7075 | struct kvm_segment var; |
7076 | ||
1aa36616 | 7077 | var.selector = selector; |
2dafc6c2 | 7078 | var.base = get_desc_base(desc); |
5601d05b GN |
7079 | #ifdef CONFIG_X86_64 |
7080 | var.base |= ((u64)base3) << 32; | |
7081 | #endif | |
2dafc6c2 GN |
7082 | var.limit = get_desc_limit(desc); |
7083 | if (desc->g) | |
7084 | var.limit = (var.limit << 12) | 0xfff; | |
7085 | var.type = desc->type; | |
2dafc6c2 GN |
7086 | var.dpl = desc->dpl; |
7087 | var.db = desc->d; | |
7088 | var.s = desc->s; | |
7089 | var.l = desc->l; | |
7090 | var.g = desc->g; | |
7091 | var.avl = desc->avl; | |
7092 | var.present = desc->p; | |
7093 | var.unusable = !var.present; | |
7094 | var.padding = 0; | |
7095 | ||
7096 | kvm_set_segment(vcpu, &var, seg); | |
7097 | return; | |
7098 | } | |
7099 | ||
717746e3 AK |
7100 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
7101 | u32 msr_index, u64 *pdata) | |
7102 | { | |
1ae09954 AG |
7103 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7104 | int r; | |
7105 | ||
7106 | r = kvm_get_msr(vcpu, msr_index, pdata); | |
7107 | ||
7108 | if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { | |
7109 | /* Bounce to user space */ | |
7110 | return X86EMUL_IO_NEEDED; | |
7111 | } | |
7112 | ||
7113 | return r; | |
717746e3 AK |
7114 | } |
7115 | ||
7116 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
7117 | u32 msr_index, u64 data) | |
7118 | { | |
1ae09954 AG |
7119 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7120 | int r; | |
7121 | ||
7122 | r = kvm_set_msr(vcpu, msr_index, data); | |
7123 | ||
7124 | if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { | |
7125 | /* Bounce to user space */ | |
7126 | return X86EMUL_IO_NEEDED; | |
7127 | } | |
7128 | ||
7129 | return r; | |
717746e3 AK |
7130 | } |
7131 | ||
64d60670 PB |
7132 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
7133 | { | |
7134 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7135 | ||
7136 | return vcpu->arch.smbase; | |
7137 | } | |
7138 | ||
7139 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
7140 | { | |
7141 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7142 | ||
7143 | vcpu->arch.smbase = smbase; | |
7144 | } | |
7145 | ||
67f4d428 NA |
7146 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
7147 | u32 pmc) | |
7148 | { | |
98ff80f5 | 7149 | return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
7150 | } |
7151 | ||
222d21aa AK |
7152 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
7153 | u32 pmc, u64 *pdata) | |
7154 | { | |
c6702c9d | 7155 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
7156 | } |
7157 | ||
6c3287f7 AK |
7158 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
7159 | { | |
7160 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
7161 | } | |
7162 | ||
2953538e | 7163 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 7164 | struct x86_instruction_info *info, |
c4f035c6 AK |
7165 | enum x86_intercept_stage stage) |
7166 | { | |
b3646477 | 7167 | return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, |
21f1b8f2 | 7168 | &ctxt->exception); |
c4f035c6 AK |
7169 | } |
7170 | ||
e911eb3b | 7171 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
f91af517 SC |
7172 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, |
7173 | bool exact_only) | |
bdb42f5a | 7174 | { |
f91af517 | 7175 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); |
bdb42f5a SB |
7176 | } |
7177 | ||
5ae78e95 SC |
7178 | static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) |
7179 | { | |
7180 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); | |
7181 | } | |
7182 | ||
7183 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) | |
7184 | { | |
7185 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
7186 | } | |
7187 | ||
7188 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
7189 | { | |
7190 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
7191 | } | |
7192 | ||
dd856efa AK |
7193 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
7194 | { | |
27b4a9c4 | 7195 | return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); |
dd856efa AK |
7196 | } |
7197 | ||
7198 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
7199 | { | |
27b4a9c4 | 7200 | kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); |
dd856efa AK |
7201 | } |
7202 | ||
801806d9 NA |
7203 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
7204 | { | |
b3646477 | 7205 | static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); |
801806d9 NA |
7206 | } |
7207 | ||
6ed071f0 LP |
7208 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
7209 | { | |
7210 | return emul_to_vcpu(ctxt)->arch.hflags; | |
7211 | } | |
7212 | ||
edce4654 | 7213 | static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) |
6ed071f0 | 7214 | { |
78fcb2c9 SC |
7215 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7216 | ||
dc87275f | 7217 | kvm_smm_changed(vcpu, false); |
6ed071f0 LP |
7218 | } |
7219 | ||
ecc513e5 | 7220 | static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, |
ed19321f | 7221 | const char *smstate) |
0234bf88 | 7222 | { |
ecc513e5 | 7223 | return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
7224 | } |
7225 | ||
25b17226 SC |
7226 | static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) |
7227 | { | |
7228 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); | |
7229 | } | |
7230 | ||
02d4160f VK |
7231 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
7232 | { | |
7233 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
7234 | } | |
7235 | ||
0225fb50 | 7236 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
7237 | .read_gpr = emulator_read_gpr, |
7238 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
7239 | .read_std = emulator_read_std, |
7240 | .write_std = emulator_write_std, | |
7a036a6f | 7241 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 7242 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
7243 | .read_emulated = emulator_read_emulated, |
7244 | .write_emulated = emulator_write_emulated, | |
7245 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 7246 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
7247 | .pio_in_emulated = emulator_pio_in_emulated, |
7248 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
7249 | .get_segment = emulator_get_segment, |
7250 | .set_segment = emulator_set_segment, | |
5951c442 | 7251 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 7252 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 7253 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
7254 | .set_gdt = emulator_set_gdt, |
7255 | .set_idt = emulator_set_idt, | |
52a46617 GN |
7256 | .get_cr = emulator_get_cr, |
7257 | .set_cr = emulator_set_cr, | |
9c537244 | 7258 | .cpl = emulator_get_cpl, |
35aa5375 GN |
7259 | .get_dr = emulator_get_dr, |
7260 | .set_dr = emulator_set_dr, | |
64d60670 PB |
7261 | .get_smbase = emulator_get_smbase, |
7262 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
7263 | .set_msr = emulator_set_msr, |
7264 | .get_msr = emulator_get_msr, | |
67f4d428 | 7265 | .check_pmc = emulator_check_pmc, |
222d21aa | 7266 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 7267 | .halt = emulator_halt, |
bcaf5cc5 | 7268 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 7269 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 7270 | .intercept = emulator_intercept, |
bdb42f5a | 7271 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
7272 | .guest_has_long_mode = emulator_guest_has_long_mode, |
7273 | .guest_has_movbe = emulator_guest_has_movbe, | |
7274 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
801806d9 | 7275 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 | 7276 | .get_hflags = emulator_get_hflags, |
edce4654 | 7277 | .exiting_smm = emulator_exiting_smm, |
ecc513e5 | 7278 | .leave_smm = emulator_leave_smm, |
25b17226 | 7279 | .triple_fault = emulator_triple_fault, |
02d4160f | 7280 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
7281 | }; |
7282 | ||
95cb2295 GN |
7283 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
7284 | { | |
b3646477 | 7285 | u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
95cb2295 GN |
7286 | /* |
7287 | * an sti; sti; sequence only disable interrupts for the first | |
7288 | * instruction. So, if the last instruction, be it emulated or | |
7289 | * not, left the system with the INT_STI flag enabled, it | |
7290 | * means that the last instruction is an sti. We should not | |
7291 | * leave the flag on in this case. The same goes for mov ss | |
7292 | */ | |
37ccdcbe PB |
7293 | if (int_shadow & mask) |
7294 | mask = 0; | |
6addfc42 | 7295 | if (unlikely(int_shadow || mask)) { |
b3646477 | 7296 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); |
6addfc42 PB |
7297 | if (!mask) |
7298 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7299 | } | |
95cb2295 GN |
7300 | } |
7301 | ||
ef54bcfe | 7302 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f | 7303 | { |
c9b8b07c | 7304 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
da9cb575 | 7305 | if (ctxt->exception.vector == PF_VECTOR) |
53b3d8e9 | 7306 | return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); |
ef54bcfe PB |
7307 | |
7308 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
7309 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
7310 | ctxt->exception.error_code); | |
54b8486f | 7311 | else |
da9cb575 | 7312 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 7313 | return false; |
54b8486f GN |
7314 | } |
7315 | ||
c9b8b07c SC |
7316 | static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) |
7317 | { | |
7318 | struct x86_emulate_ctxt *ctxt; | |
7319 | ||
7320 | ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); | |
7321 | if (!ctxt) { | |
7322 | pr_err("kvm: failed to allocate vcpu's emulator\n"); | |
7323 | return NULL; | |
7324 | } | |
7325 | ||
7326 | ctxt->vcpu = vcpu; | |
7327 | ctxt->ops = &emulate_ops; | |
7328 | vcpu->arch.emulate_ctxt = ctxt; | |
7329 | ||
7330 | return ctxt; | |
7331 | } | |
7332 | ||
8ec4722d MG |
7333 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
7334 | { | |
c9b8b07c | 7335 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d MG |
7336 | int cs_db, cs_l; |
7337 | ||
b3646477 | 7338 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
8ec4722d | 7339 | |
744e699c | 7340 | ctxt->gpa_available = false; |
adf52235 | 7341 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
7342 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
7343 | ||
adf52235 TY |
7344 | ctxt->eip = kvm_rip_read(vcpu); |
7345 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
7346 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 7347 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
7348 | cs_db ? X86EMUL_MODE_PROT32 : |
7349 | X86EMUL_MODE_PROT16; | |
a584539b | 7350 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
7351 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
7352 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 7353 | |
da6393cd WL |
7354 | ctxt->interruptibility = 0; |
7355 | ctxt->have_exception = false; | |
7356 | ctxt->exception.vector = -1; | |
7357 | ctxt->perm_ok = false; | |
7358 | ||
dd856efa | 7359 | init_decode_cache(ctxt); |
7ae441ea | 7360 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
7361 | } |
7362 | ||
9497e1f2 | 7363 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 7364 | { |
c9b8b07c | 7365 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
63995653 MG |
7366 | int ret; |
7367 | ||
7368 | init_emulate_ctxt(vcpu); | |
7369 | ||
9dac77fa AK |
7370 | ctxt->op_bytes = 2; |
7371 | ctxt->ad_bytes = 2; | |
7372 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 7373 | ret = emulate_int_real(ctxt, irq); |
63995653 | 7374 | |
9497e1f2 SC |
7375 | if (ret != X86EMUL_CONTINUE) { |
7376 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
7377 | } else { | |
7378 | ctxt->eip = ctxt->_eip; | |
7379 | kvm_rip_write(vcpu, ctxt->eip); | |
7380 | kvm_set_rflags(vcpu, ctxt->eflags); | |
7381 | } | |
63995653 MG |
7382 | } |
7383 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
7384 | ||
e2366171 | 7385 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 7386 | { |
6d77dbfc GN |
7387 | ++vcpu->stat.insn_emulation_fail; |
7388 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 7389 | |
42cbf068 SC |
7390 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
7391 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7392 | return 1; |
42cbf068 | 7393 | } |
e2366171 | 7394 | |
738fece4 SC |
7395 | if (emulation_type & EMULTYPE_SKIP) { |
7396 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7397 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7398 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7399 | return 0; |
738fece4 SC |
7400 | } |
7401 | ||
22da61c9 SC |
7402 | kvm_queue_exception(vcpu, UD_VECTOR); |
7403 | ||
b3646477 | 7404 | if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { |
fc3a9157 JR |
7405 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
7406 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7407 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7408 | return 0; |
fc3a9157 | 7409 | } |
e2366171 | 7410 | |
60fc3d02 | 7411 | return 1; |
6d77dbfc GN |
7412 | } |
7413 | ||
736c291c | 7414 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 GN |
7415 | bool write_fault_to_shadow_pgtable, |
7416 | int emulation_type) | |
a6f177ef | 7417 | { |
736c291c | 7418 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 7419 | kvm_pfn_t pfn; |
a6f177ef | 7420 | |
92daa48b | 7421 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
991eebf9 GN |
7422 | return false; |
7423 | ||
92daa48b SC |
7424 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7425 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7426 | return false; |
7427 | ||
44dd3ffa | 7428 | if (!vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7429 | /* |
7430 | * Write permission should be allowed since only | |
7431 | * write access need to be emulated. | |
7432 | */ | |
736c291c | 7433 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 7434 | |
95b3cf69 XG |
7435 | /* |
7436 | * If the mapping is invalid in guest, let cpu retry | |
7437 | * it to generate fault. | |
7438 | */ | |
7439 | if (gpa == UNMAPPED_GVA) | |
7440 | return true; | |
7441 | } | |
a6f177ef | 7442 | |
8e3d9d06 XG |
7443 | /* |
7444 | * Do not retry the unhandleable instruction if it faults on the | |
7445 | * readonly host memory, otherwise it will goto a infinite loop: | |
7446 | * retry instruction -> write #PF -> emulation fail -> retry | |
7447 | * instruction -> ... | |
7448 | */ | |
7449 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
7450 | |
7451 | /* | |
7452 | * If the instruction failed on the error pfn, it can not be fixed, | |
7453 | * report the error to userspace. | |
7454 | */ | |
7455 | if (is_error_noslot_pfn(pfn)) | |
7456 | return false; | |
7457 | ||
7458 | kvm_release_pfn_clean(pfn); | |
7459 | ||
7460 | /* The instructions are well-emulated on direct mmu. */ | |
44dd3ffa | 7461 | if (vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7462 | unsigned int indirect_shadow_pages; |
7463 | ||
531810ca | 7464 | write_lock(&vcpu->kvm->mmu_lock); |
95b3cf69 | 7465 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; |
531810ca | 7466 | write_unlock(&vcpu->kvm->mmu_lock); |
95b3cf69 XG |
7467 | |
7468 | if (indirect_shadow_pages) | |
7469 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
7470 | ||
a6f177ef | 7471 | return true; |
8e3d9d06 | 7472 | } |
a6f177ef | 7473 | |
95b3cf69 XG |
7474 | /* |
7475 | * if emulation was due to access to shadowed page table | |
7476 | * and it failed try to unshadow page and re-enter the | |
7477 | * guest to let CPU execute the instruction. | |
7478 | */ | |
7479 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
7480 | |
7481 | /* | |
7482 | * If the access faults on its page table, it can not | |
7483 | * be fixed by unprotecting shadow page and it should | |
7484 | * be reported to userspace. | |
7485 | */ | |
7486 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
7487 | } |
7488 | ||
1cb3f3ae | 7489 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 7490 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
7491 | { |
7492 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 7493 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
7494 | |
7495 | last_retry_eip = vcpu->arch.last_retry_eip; | |
7496 | last_retry_addr = vcpu->arch.last_retry_addr; | |
7497 | ||
7498 | /* | |
7499 | * If the emulation is caused by #PF and it is non-page_table | |
7500 | * writing instruction, it means the VM-EXIT is caused by shadow | |
7501 | * page protected, we can zap the shadow page and retry this | |
7502 | * instruction directly. | |
7503 | * | |
7504 | * Note: if the guest uses a non-page-table modifying instruction | |
7505 | * on the PDE that points to the instruction, then we will unmap | |
7506 | * the instruction and go to an infinite loop. So, we cache the | |
7507 | * last retried eip and the last fault address, if we meet the eip | |
7508 | * and the address again, we can break out of the potential infinite | |
7509 | * loop. | |
7510 | */ | |
7511 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
7512 | ||
92daa48b | 7513 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
1cb3f3ae XG |
7514 | return false; |
7515 | ||
92daa48b SC |
7516 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7517 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7518 | return false; |
7519 | ||
1cb3f3ae XG |
7520 | if (x86_page_table_writing_insn(ctxt)) |
7521 | return false; | |
7522 | ||
736c291c | 7523 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
7524 | return false; |
7525 | ||
7526 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 7527 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 7528 | |
44dd3ffa | 7529 | if (!vcpu->arch.mmu->direct_map) |
736c291c | 7530 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 7531 | |
22368028 | 7532 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
7533 | |
7534 | return true; | |
7535 | } | |
7536 | ||
716d51ab GN |
7537 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
7538 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
7539 | ||
dc87275f | 7540 | static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) |
a584539b | 7541 | { |
1270e647 | 7542 | trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); |
0d7ee6f4 | 7543 | |
dc87275f SC |
7544 | if (entering_smm) { |
7545 | vcpu->arch.hflags |= HF_SMM_MASK; | |
7546 | } else { | |
7547 | vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); | |
7548 | ||
c43203ca PB |
7549 | /* Process a latched INIT or SMI, if any. */ |
7550 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 | 7551 | } |
699023e2 PB |
7552 | |
7553 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
7554 | } |
7555 | ||
4a1e10d5 PB |
7556 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
7557 | unsigned long *db) | |
7558 | { | |
7559 | u32 dr6 = 0; | |
7560 | int i; | |
7561 | u32 enable, rwlen; | |
7562 | ||
7563 | enable = dr7; | |
7564 | rwlen = dr7 >> 16; | |
7565 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
7566 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
7567 | dr6 |= (1 << i); | |
7568 | return dr6; | |
7569 | } | |
7570 | ||
120c2c4f | 7571 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
7572 | { |
7573 | struct kvm_run *kvm_run = vcpu->run; | |
7574 | ||
c8401dda | 7575 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
9a3ecd5e | 7576 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; |
d5d260c5 | 7577 | kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
c8401dda PB |
7578 | kvm_run->debug.arch.exception = DB_VECTOR; |
7579 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7580 | return 0; |
663f4c61 | 7581 | } |
120c2c4f | 7582 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 7583 | return 1; |
663f4c61 PB |
7584 | } |
7585 | ||
6affcbed KH |
7586 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
7587 | { | |
b3646477 | 7588 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
f8ea7c60 | 7589 | int r; |
6affcbed | 7590 | |
b3646477 | 7591 | r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); |
60fc3d02 | 7592 | if (unlikely(!r)) |
f8ea7c60 | 7593 | return 0; |
c8401dda PB |
7594 | |
7595 | /* | |
7596 | * rflags is the old, "raw" value of the flags. The new value has | |
7597 | * not been saved yet. | |
7598 | * | |
7599 | * This is correct even for TF set by the guest, because "the | |
7600 | * processor will not generate this exception after the instruction | |
7601 | * that sets the TF flag". | |
7602 | */ | |
7603 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 7604 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 7605 | return r; |
6affcbed KH |
7606 | } |
7607 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
7608 | ||
4a1e10d5 PB |
7609 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
7610 | { | |
4a1e10d5 PB |
7611 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
7612 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
7613 | struct kvm_run *kvm_run = vcpu->run; |
7614 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
7615 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7616 | vcpu->arch.guest_debug_dr7, |
7617 | vcpu->arch.eff_db); | |
7618 | ||
7619 | if (dr6 != 0) { | |
9a3ecd5e | 7620 | kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; |
82b32774 | 7621 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
7622 | kvm_run->debug.arch.exception = DB_VECTOR; |
7623 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7624 | *r = 0; |
4a1e10d5 PB |
7625 | return true; |
7626 | } | |
7627 | } | |
7628 | ||
4161a569 NA |
7629 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
7630 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
7631 | unsigned long eip = kvm_get_linear_rip(vcpu); |
7632 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7633 | vcpu->arch.dr7, |
7634 | vcpu->arch.db); | |
7635 | ||
7636 | if (dr6 != 0) { | |
4d5523cf | 7637 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
60fc3d02 | 7638 | *r = 1; |
4a1e10d5 PB |
7639 | return true; |
7640 | } | |
7641 | } | |
7642 | ||
7643 | return false; | |
7644 | } | |
7645 | ||
04789b66 LA |
7646 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
7647 | { | |
2d7921c4 AM |
7648 | switch (ctxt->opcode_len) { |
7649 | case 1: | |
7650 | switch (ctxt->b) { | |
7651 | case 0xe4: /* IN */ | |
7652 | case 0xe5: | |
7653 | case 0xec: | |
7654 | case 0xed: | |
7655 | case 0xe6: /* OUT */ | |
7656 | case 0xe7: | |
7657 | case 0xee: | |
7658 | case 0xef: | |
7659 | case 0x6c: /* INS */ | |
7660 | case 0x6d: | |
7661 | case 0x6e: /* OUTS */ | |
7662 | case 0x6f: | |
7663 | return true; | |
7664 | } | |
7665 | break; | |
7666 | case 2: | |
7667 | switch (ctxt->b) { | |
7668 | case 0x33: /* RDPMC */ | |
7669 | return true; | |
7670 | } | |
7671 | break; | |
04789b66 LA |
7672 | } |
7673 | ||
7674 | return false; | |
7675 | } | |
7676 | ||
4aa2691d WH |
7677 | /* |
7678 | * Decode to be emulated instruction. Return EMULATION_OK if success. | |
7679 | */ | |
7680 | int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, | |
7681 | void *insn, int insn_len) | |
7682 | { | |
7683 | int r = EMULATION_OK; | |
7684 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; | |
7685 | ||
7686 | init_emulate_ctxt(vcpu); | |
7687 | ||
7688 | /* | |
7689 | * We will reenter on the same instruction since we do not set | |
7690 | * complete_userspace_io. This does not handle watchpoints yet, | |
7691 | * those would be handled in the emulate_ops. | |
7692 | */ | |
7693 | if (!(emulation_type & EMULTYPE_SKIP) && | |
7694 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
7695 | return r; | |
7696 | ||
b35491e6 | 7697 | r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); |
4aa2691d WH |
7698 | |
7699 | trace_kvm_emulate_insn_start(vcpu); | |
7700 | ++vcpu->stat.insn_emulation; | |
7701 | ||
7702 | return r; | |
7703 | } | |
7704 | EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); | |
7705 | ||
736c291c SC |
7706 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
7707 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 7708 | { |
95cb2295 | 7709 | int r; |
c9b8b07c | 7710 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
7ae441ea | 7711 | bool writeback = true; |
09e3e2a1 SC |
7712 | bool write_fault_to_spt; |
7713 | ||
b3646477 | 7714 | if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) |
09e3e2a1 | 7715 | return 1; |
bbd9b64e | 7716 | |
c595ceee PB |
7717 | vcpu->arch.l1tf_flush_l1d = true; |
7718 | ||
93c05d3e XG |
7719 | /* |
7720 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
7721 | * never reused. | |
7722 | */ | |
09e3e2a1 | 7723 | write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
93c05d3e | 7724 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
8d7d8102 | 7725 | |
571008da | 7726 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
4aa2691d | 7727 | kvm_clear_exception_queue(vcpu); |
4a1e10d5 | 7728 | |
4aa2691d WH |
7729 | r = x86_decode_emulated_instruction(vcpu, emulation_type, |
7730 | insn, insn_len); | |
1d2887e2 | 7731 | if (r != EMULATION_OK) { |
b4000606 | 7732 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
7733 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
7734 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 7735 | return 1; |
c83fad65 | 7736 | } |
736c291c SC |
7737 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
7738 | write_fault_to_spt, | |
7739 | emulation_type)) | |
60fc3d02 | 7740 | return 1; |
8530a79c | 7741 | if (ctxt->have_exception) { |
c8848cee JD |
7742 | /* |
7743 | * #UD should result in just EMULATION_FAILED, and trap-like | |
7744 | * exception should not be encountered during decode. | |
7745 | */ | |
7746 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
7747 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 7748 | inject_emulated_exception(vcpu); |
60fc3d02 | 7749 | return 1; |
8530a79c | 7750 | } |
e2366171 | 7751 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7752 | } |
7753 | } | |
7754 | ||
42cbf068 SC |
7755 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
7756 | !is_vmware_backdoor_opcode(ctxt)) { | |
7757 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7758 | return 1; |
42cbf068 | 7759 | } |
04789b66 | 7760 | |
1957aa63 SC |
7761 | /* |
7762 | * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks | |
7763 | * for kvm_skip_emulated_instruction(). The caller is responsible for | |
7764 | * updating interruptibility state and injecting single-step #DBs. | |
7765 | */ | |
ba8afb6b | 7766 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 7767 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
7768 | if (ctxt->eflags & X86_EFLAGS_RF) |
7769 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 7770 | return 1; |
ba8afb6b GN |
7771 | } |
7772 | ||
736c291c | 7773 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 7774 | return 1; |
1cb3f3ae | 7775 | |
7ae441ea | 7776 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 7777 | changes registers values during IO operation */ |
7ae441ea GN |
7778 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
7779 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 7780 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 7781 | } |
4d2179e1 | 7782 | |
5cd21917 | 7783 | restart: |
92daa48b SC |
7784 | if (emulation_type & EMULTYPE_PF) { |
7785 | /* Save the faulting GPA (cr2) in the address field */ | |
7786 | ctxt->exception.address = cr2_or_gpa; | |
7787 | ||
7788 | /* With shadow page tables, cr2 contains a GVA or nGPA. */ | |
7789 | if (vcpu->arch.mmu->direct_map) { | |
744e699c SC |
7790 | ctxt->gpa_available = true; |
7791 | ctxt->gpa_val = cr2_or_gpa; | |
92daa48b SC |
7792 | } |
7793 | } else { | |
7794 | /* Sanitize the address out of an abundance of paranoia. */ | |
7795 | ctxt->exception.address = 0; | |
7796 | } | |
0f89b207 | 7797 | |
9d74191a | 7798 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 7799 | |
775fde86 | 7800 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 7801 | return 1; |
775fde86 | 7802 | |
d2ddd1c4 | 7803 | if (r == EMULATION_FAILED) { |
736c291c | 7804 | if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, |
991eebf9 | 7805 | emulation_type)) |
60fc3d02 | 7806 | return 1; |
c3cd7ffa | 7807 | |
e2366171 | 7808 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7809 | } |
7810 | ||
9d74191a | 7811 | if (ctxt->have_exception) { |
60fc3d02 | 7812 | r = 1; |
ef54bcfe PB |
7813 | if (inject_emulated_exception(vcpu)) |
7814 | return r; | |
d2ddd1c4 | 7815 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
7816 | if (!vcpu->arch.pio.in) { |
7817 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 7818 | vcpu->arch.pio.count = 0; |
0912c977 | 7819 | } else { |
7ae441ea | 7820 | writeback = false; |
716d51ab GN |
7821 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
7822 | } | |
60fc3d02 | 7823 | r = 0; |
7ae441ea | 7824 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
7825 | ++vcpu->stat.mmio_exits; |
7826 | ||
7ae441ea GN |
7827 | if (!vcpu->mmio_is_write) |
7828 | writeback = false; | |
60fc3d02 | 7829 | r = 0; |
716d51ab | 7830 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 7831 | } else if (r == EMULATION_RESTART) |
5cd21917 | 7832 | goto restart; |
d2ddd1c4 | 7833 | else |
60fc3d02 | 7834 | r = 1; |
f850e2e6 | 7835 | |
7ae441ea | 7836 | if (writeback) { |
b3646477 | 7837 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
9d74191a | 7838 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 7839 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
38827dbd | 7840 | if (!ctxt->have_exception || |
75ee23b3 SC |
7841 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
7842 | kvm_rip_write(vcpu, ctxt->eip); | |
384dea1c | 7843 | if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) |
120c2c4f | 7844 | r = kvm_vcpu_do_singlestep(vcpu); |
afaf0b2f | 7845 | if (kvm_x86_ops.update_emulated_instruction) |
b3646477 | 7846 | static_call(kvm_x86_update_emulated_instruction)(vcpu); |
38827dbd | 7847 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 7848 | } |
6addfc42 PB |
7849 | |
7850 | /* | |
7851 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
7852 | * do nothing, and it will be requested again as soon as | |
7853 | * the shadow expires. But we still need to check here, | |
7854 | * because POPF has no interrupt shadow. | |
7855 | */ | |
7856 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
7857 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
7858 | } else |
7859 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
7860 | |
7861 | return r; | |
de7d789a | 7862 | } |
c60658d1 SC |
7863 | |
7864 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
7865 | { | |
7866 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
7867 | } | |
7868 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
7869 | ||
7870 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
7871 | void *insn, int insn_len) | |
7872 | { | |
7873 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
7874 | } | |
7875 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 7876 | |
8764ed55 SC |
7877 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
7878 | { | |
7879 | vcpu->arch.pio.count = 0; | |
7880 | return 1; | |
7881 | } | |
7882 | ||
45def77e SC |
7883 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
7884 | { | |
7885 | vcpu->arch.pio.count = 0; | |
7886 | ||
7887 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
7888 | return 1; | |
7889 | ||
7890 | return kvm_skip_emulated_instruction(vcpu); | |
7891 | } | |
7892 | ||
dca7f128 SC |
7893 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
7894 | unsigned short port) | |
de7d789a | 7895 | { |
de3cd117 | 7896 | unsigned long val = kvm_rax_read(vcpu); |
2e3bb4d8 SC |
7897 | int ret = emulator_pio_out(vcpu, size, port, &val, 1); |
7898 | ||
8764ed55 SC |
7899 | if (ret) |
7900 | return ret; | |
45def77e | 7901 | |
8764ed55 SC |
7902 | /* |
7903 | * Workaround userspace that relies on old KVM behavior of %rip being | |
7904 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
7905 | */ | |
7906 | if (port == 0x7e && | |
7907 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
7908 | vcpu->arch.complete_userspace_io = | |
7909 | complete_fast_pio_out_port_0x7e; | |
7910 | kvm_skip_emulated_instruction(vcpu); | |
7911 | } else { | |
45def77e SC |
7912 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
7913 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
7914 | } | |
8764ed55 | 7915 | return 0; |
de7d789a | 7916 | } |
de7d789a | 7917 | |
8370c3d0 TL |
7918 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
7919 | { | |
7920 | unsigned long val; | |
7921 | ||
7922 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
7923 | BUG_ON(vcpu->arch.pio.count != 1); | |
7924 | ||
45def77e SC |
7925 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
7926 | vcpu->arch.pio.count = 0; | |
7927 | return 1; | |
7928 | } | |
7929 | ||
8370c3d0 | 7930 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 7931 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
7932 | |
7933 | /* | |
2e3bb4d8 | 7934 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform |
8370c3d0 TL |
7935 | * the copy and tracing |
7936 | */ | |
2e3bb4d8 | 7937 | emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); |
de3cd117 | 7938 | kvm_rax_write(vcpu, val); |
8370c3d0 | 7939 | |
45def77e | 7940 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
7941 | } |
7942 | ||
dca7f128 SC |
7943 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
7944 | unsigned short port) | |
8370c3d0 TL |
7945 | { |
7946 | unsigned long val; | |
7947 | int ret; | |
7948 | ||
7949 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 7950 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 7951 | |
2e3bb4d8 | 7952 | ret = emulator_pio_in(vcpu, size, port, &val, 1); |
8370c3d0 | 7953 | if (ret) { |
de3cd117 | 7954 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
7955 | return ret; |
7956 | } | |
7957 | ||
45def77e | 7958 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
7959 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
7960 | ||
7961 | return 0; | |
7962 | } | |
dca7f128 SC |
7963 | |
7964 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
7965 | { | |
45def77e | 7966 | int ret; |
dca7f128 | 7967 | |
dca7f128 | 7968 | if (in) |
45def77e | 7969 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 7970 | else |
45def77e SC |
7971 | ret = kvm_fast_pio_out(vcpu, size, port); |
7972 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
7973 | } |
7974 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 7975 | |
251a5fd6 | 7976 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 7977 | { |
0a3aee0d | 7978 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 7979 | return 0; |
8cfdc000 ZA |
7980 | } |
7981 | ||
7982 | static void tsc_khz_changed(void *data) | |
c8076604 | 7983 | { |
8cfdc000 ZA |
7984 | struct cpufreq_freqs *freq = data; |
7985 | unsigned long khz = 0; | |
7986 | ||
7987 | if (data) | |
7988 | khz = freq->new; | |
7989 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
7990 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
7991 | if (!khz) | |
7992 | khz = tsc_khz; | |
0a3aee0d | 7993 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
7994 | } |
7995 | ||
5fa4ec9c | 7996 | #ifdef CONFIG_X86_64 |
0092e434 VK |
7997 | static void kvm_hyperv_tsc_notifier(void) |
7998 | { | |
0092e434 VK |
7999 | struct kvm *kvm; |
8000 | struct kvm_vcpu *vcpu; | |
8001 | int cpu; | |
a83829f5 | 8002 | unsigned long flags; |
0092e434 | 8003 | |
0d9ce162 | 8004 | mutex_lock(&kvm_lock); |
0092e434 VK |
8005 | list_for_each_entry(kvm, &vm_list, vm_list) |
8006 | kvm_make_mclock_inprogress_request(kvm); | |
8007 | ||
8008 | hyperv_stop_tsc_emulation(); | |
8009 | ||
8010 | /* TSC frequency always matches when on Hyper-V */ | |
8011 | for_each_present_cpu(cpu) | |
8012 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
8013 | kvm_max_guest_tsc_khz = tsc_khz; | |
8014 | ||
8015 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
8016 | struct kvm_arch *ka = &kvm->arch; | |
8017 | ||
a83829f5 | 8018 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
0092e434 | 8019 | pvclock_update_vm_gtod_copy(kvm); |
a83829f5 | 8020 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
0092e434 VK |
8021 | |
8022 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
8023 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
8024 | ||
8025 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
8026 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); | |
0092e434 | 8027 | } |
0d9ce162 | 8028 | mutex_unlock(&kvm_lock); |
0092e434 | 8029 | } |
5fa4ec9c | 8030 | #endif |
0092e434 | 8031 | |
df24014a | 8032 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 8033 | { |
c8076604 GH |
8034 | struct kvm *kvm; |
8035 | struct kvm_vcpu *vcpu; | |
8036 | int i, send_ipi = 0; | |
8037 | ||
8cfdc000 ZA |
8038 | /* |
8039 | * We allow guests to temporarily run on slowing clocks, | |
8040 | * provided we notify them after, or to run on accelerating | |
8041 | * clocks, provided we notify them before. Thus time never | |
8042 | * goes backwards. | |
8043 | * | |
8044 | * However, we have a problem. We can't atomically update | |
8045 | * the frequency of a given CPU from this function; it is | |
8046 | * merely a notifier, which can be called from any CPU. | |
8047 | * Changing the TSC frequency at arbitrary points in time | |
8048 | * requires a recomputation of local variables related to | |
8049 | * the TSC for each VCPU. We must flag these local variables | |
8050 | * to be updated and be sure the update takes place with the | |
8051 | * new frequency before any guests proceed. | |
8052 | * | |
8053 | * Unfortunately, the combination of hotplug CPU and frequency | |
8054 | * change creates an intractable locking scenario; the order | |
8055 | * of when these callouts happen is undefined with respect to | |
8056 | * CPU hotplug, and they can race with each other. As such, | |
8057 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
8058 | * undefined; you can actually have a CPU frequency change take | |
8059 | * place in between the computation of X and the setting of the | |
8060 | * variable. To protect against this problem, all updates of | |
8061 | * the per_cpu tsc_khz variable are done in an interrupt | |
8062 | * protected IPI, and all callers wishing to update the value | |
8063 | * must wait for a synchronous IPI to complete (which is trivial | |
8064 | * if the caller is on the CPU already). This establishes the | |
8065 | * necessary total order on variable updates. | |
8066 | * | |
8067 | * Note that because a guest time update may take place | |
8068 | * anytime after the setting of the VCPU's request bit, the | |
8069 | * correct TSC value must be set before the request. However, | |
8070 | * to ensure the update actually makes it to any guest which | |
8071 | * starts running in hardware virtualization between the set | |
8072 | * and the acquisition of the spinlock, we must also ping the | |
8073 | * CPU after setting the request bit. | |
8074 | * | |
8075 | */ | |
8076 | ||
df24014a | 8077 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 8078 | |
0d9ce162 | 8079 | mutex_lock(&kvm_lock); |
c8076604 | 8080 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 8081 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 8082 | if (vcpu->cpu != cpu) |
c8076604 | 8083 | continue; |
c285545f | 8084 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 8085 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 8086 | send_ipi = 1; |
c8076604 GH |
8087 | } |
8088 | } | |
0d9ce162 | 8089 | mutex_unlock(&kvm_lock); |
c8076604 GH |
8090 | |
8091 | if (freq->old < freq->new && send_ipi) { | |
8092 | /* | |
8093 | * We upscale the frequency. Must make the guest | |
8094 | * doesn't see old kvmclock values while running with | |
8095 | * the new frequency, otherwise we risk the guest sees | |
8096 | * time go backwards. | |
8097 | * | |
8098 | * In case we update the frequency for another cpu | |
8099 | * (which might be in guest context) send an interrupt | |
8100 | * to kick the cpu out of guest context. Next time | |
8101 | * guest context is entered kvmclock will be updated, | |
8102 | * so the guest will not see stale values. | |
8103 | */ | |
df24014a | 8104 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 8105 | } |
df24014a VK |
8106 | } |
8107 | ||
8108 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
8109 | void *data) | |
8110 | { | |
8111 | struct cpufreq_freqs *freq = data; | |
8112 | int cpu; | |
8113 | ||
8114 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
8115 | return 0; | |
8116 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
8117 | return 0; | |
8118 | ||
8119 | for_each_cpu(cpu, freq->policy->cpus) | |
8120 | __kvmclock_cpufreq_notifier(freq, cpu); | |
8121 | ||
c8076604 GH |
8122 | return 0; |
8123 | } | |
8124 | ||
8125 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
8126 | .notifier_call = kvmclock_cpufreq_notifier |
8127 | }; | |
8128 | ||
251a5fd6 | 8129 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 8130 | { |
251a5fd6 SAS |
8131 | tsc_khz_changed(NULL); |
8132 | return 0; | |
8cfdc000 ZA |
8133 | } |
8134 | ||
b820cc0c ZA |
8135 | static void kvm_timer_init(void) |
8136 | { | |
c285545f | 8137 | max_tsc_khz = tsc_khz; |
460dd42e | 8138 | |
b820cc0c | 8139 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f | 8140 | #ifdef CONFIG_CPU_FREQ |
aaec7c03 | 8141 | struct cpufreq_policy *policy; |
758f588d BP |
8142 | int cpu; |
8143 | ||
3e26f230 | 8144 | cpu = get_cpu(); |
aaec7c03 | 8145 | policy = cpufreq_cpu_get(cpu); |
9a11997e WL |
8146 | if (policy) { |
8147 | if (policy->cpuinfo.max_freq) | |
8148 | max_tsc_khz = policy->cpuinfo.max_freq; | |
8149 | cpufreq_cpu_put(policy); | |
8150 | } | |
3e26f230 | 8151 | put_cpu(); |
c285545f | 8152 | #endif |
b820cc0c ZA |
8153 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
8154 | CPUFREQ_TRANSITION_NOTIFIER); | |
8155 | } | |
460dd42e | 8156 | |
73c1b41e | 8157 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 8158 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
8159 | } |
8160 | ||
dd60d217 AK |
8161 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
8162 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 8163 | |
f5132b01 | 8164 | int kvm_is_in_guest(void) |
ff9d07a0 | 8165 | { |
086c9855 | 8166 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
8167 | } |
8168 | ||
8169 | static int kvm_is_user_mode(void) | |
8170 | { | |
8171 | int user_mode = 3; | |
dcf46b94 | 8172 | |
086c9855 | 8173 | if (__this_cpu_read(current_vcpu)) |
b3646477 | 8174 | user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu)); |
dcf46b94 | 8175 | |
ff9d07a0 ZY |
8176 | return user_mode != 0; |
8177 | } | |
8178 | ||
8179 | static unsigned long kvm_get_guest_ip(void) | |
8180 | { | |
8181 | unsigned long ip = 0; | |
dcf46b94 | 8182 | |
086c9855 AS |
8183 | if (__this_cpu_read(current_vcpu)) |
8184 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 8185 | |
ff9d07a0 ZY |
8186 | return ip; |
8187 | } | |
8188 | ||
8479e04e LK |
8189 | static void kvm_handle_intel_pt_intr(void) |
8190 | { | |
8191 | struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); | |
8192 | ||
8193 | kvm_make_request(KVM_REQ_PMI, vcpu); | |
8194 | __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, | |
8195 | (unsigned long *)&vcpu->arch.pmu.global_status); | |
8196 | } | |
8197 | ||
ff9d07a0 ZY |
8198 | static struct perf_guest_info_callbacks kvm_guest_cbs = { |
8199 | .is_in_guest = kvm_is_in_guest, | |
8200 | .is_user_mode = kvm_is_user_mode, | |
8201 | .get_guest_ip = kvm_get_guest_ip, | |
8479e04e | 8202 | .handle_intel_pt_intr = kvm_handle_intel_pt_intr, |
ff9d07a0 ZY |
8203 | }; |
8204 | ||
16e8d74d MT |
8205 | #ifdef CONFIG_X86_64 |
8206 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
8207 | { | |
d828199e MT |
8208 | struct kvm *kvm; |
8209 | ||
8210 | struct kvm_vcpu *vcpu; | |
8211 | int i; | |
8212 | ||
0d9ce162 | 8213 | mutex_lock(&kvm_lock); |
d828199e MT |
8214 | list_for_each_entry(kvm, &vm_list, vm_list) |
8215 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 8216 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 8217 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 8218 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
8219 | } |
8220 | ||
8221 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
8222 | ||
3f804f6d TG |
8223 | /* |
8224 | * Indirection to move queue_work() out of the tk_core.seq write held | |
8225 | * region to prevent possible deadlocks against time accessors which | |
8226 | * are invoked with work related locks held. | |
8227 | */ | |
8228 | static void pvclock_irq_work_fn(struct irq_work *w) | |
8229 | { | |
8230 | queue_work(system_long_wq, &pvclock_gtod_work); | |
8231 | } | |
8232 | ||
8233 | static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); | |
8234 | ||
16e8d74d MT |
8235 | /* |
8236 | * Notification about pvclock gtod data update. | |
8237 | */ | |
8238 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
8239 | void *priv) | |
8240 | { | |
8241 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
8242 | struct timekeeper *tk = priv; | |
8243 | ||
8244 | update_pvclock_gtod(tk); | |
8245 | ||
3f804f6d TG |
8246 | /* |
8247 | * Disable master clock if host does not trust, or does not use, | |
8248 | * TSC based clocksource. Delegate queue_work() to irq_work as | |
8249 | * this is invoked with tk_core.seq write held. | |
16e8d74d | 8250 | */ |
b0c39dc6 | 8251 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d | 8252 | atomic_read(&kvm_guest_has_master_clock) != 0) |
3f804f6d | 8253 | irq_work_queue(&pvclock_irq_work); |
16e8d74d MT |
8254 | return 0; |
8255 | } | |
8256 | ||
8257 | static struct notifier_block pvclock_gtod_notifier = { | |
8258 | .notifier_call = pvclock_gtod_notify, | |
8259 | }; | |
8260 | #endif | |
8261 | ||
f8c16bba | 8262 | int kvm_arch_init(void *opaque) |
043405e1 | 8263 | { |
d008dfdb | 8264 | struct kvm_x86_init_ops *ops = opaque; |
b820cc0c | 8265 | int r; |
f8c16bba | 8266 | |
afaf0b2f | 8267 | if (kvm_x86_ops.hardware_enable) { |
f8c16bba | 8268 | printk(KERN_ERR "kvm: already loaded the other module\n"); |
56c6d28a ZX |
8269 | r = -EEXIST; |
8270 | goto out; | |
f8c16bba ZX |
8271 | } |
8272 | ||
8273 | if (!ops->cpu_has_kvm_support()) { | |
ef935c25 | 8274 | pr_err_ratelimited("kvm: no hardware support\n"); |
56c6d28a ZX |
8275 | r = -EOPNOTSUPP; |
8276 | goto out; | |
f8c16bba ZX |
8277 | } |
8278 | if (ops->disabled_by_bios()) { | |
ef935c25 | 8279 | pr_err_ratelimited("kvm: disabled by bios\n"); |
56c6d28a ZX |
8280 | r = -EOPNOTSUPP; |
8281 | goto out; | |
f8c16bba ZX |
8282 | } |
8283 | ||
b666a4b6 MO |
8284 | /* |
8285 | * KVM explicitly assumes that the guest has an FPU and | |
8286 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
8287 | * vCPU's FPU state as a fxregs_state struct. | |
8288 | */ | |
8289 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
8290 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
8291 | r = -EOPNOTSUPP; | |
8292 | goto out; | |
8293 | } | |
8294 | ||
013f6a5d | 8295 | r = -ENOMEM; |
ed8e4812 | 8296 | x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), |
b666a4b6 MO |
8297 | __alignof__(struct fpu), SLAB_ACCOUNT, |
8298 | NULL); | |
8299 | if (!x86_fpu_cache) { | |
8300 | printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); | |
8301 | goto out; | |
8302 | } | |
8303 | ||
c9b8b07c SC |
8304 | x86_emulator_cache = kvm_alloc_emulator_cache(); |
8305 | if (!x86_emulator_cache) { | |
8306 | pr_err("kvm: failed to allocate cache for x86 emulator\n"); | |
8307 | goto out_free_x86_fpu_cache; | |
8308 | } | |
8309 | ||
7e34fbd0 SC |
8310 | user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); |
8311 | if (!user_return_msrs) { | |
8312 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); | |
c9b8b07c | 8313 | goto out_free_x86_emulator_cache; |
013f6a5d | 8314 | } |
e5fda4bb | 8315 | kvm_nr_uret_msrs = 0; |
013f6a5d | 8316 | |
97db56ce AK |
8317 | r = kvm_mmu_module_init(); |
8318 | if (r) | |
013f6a5d | 8319 | goto out_free_percpu; |
97db56ce | 8320 | |
b820cc0c | 8321 | kvm_timer_init(); |
c8076604 | 8322 | |
ff9d07a0 ZY |
8323 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
8324 | ||
cfc48181 | 8325 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
2acf923e | 8326 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
cfc48181 SC |
8327 | supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; |
8328 | } | |
2acf923e | 8329 | |
0c5f81da WL |
8330 | if (pi_inject_timer == -1) |
8331 | pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); | |
16e8d74d MT |
8332 | #ifdef CONFIG_X86_64 |
8333 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 8334 | |
5fa4ec9c | 8335 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 8336 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
8337 | #endif |
8338 | ||
f8c16bba | 8339 | return 0; |
56c6d28a | 8340 | |
013f6a5d | 8341 | out_free_percpu: |
7e34fbd0 | 8342 | free_percpu(user_return_msrs); |
c9b8b07c SC |
8343 | out_free_x86_emulator_cache: |
8344 | kmem_cache_destroy(x86_emulator_cache); | |
b666a4b6 MO |
8345 | out_free_x86_fpu_cache: |
8346 | kmem_cache_destroy(x86_fpu_cache); | |
56c6d28a | 8347 | out: |
56c6d28a | 8348 | return r; |
043405e1 | 8349 | } |
8776e519 | 8350 | |
f8c16bba ZX |
8351 | void kvm_arch_exit(void) |
8352 | { | |
0092e434 | 8353 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 8354 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
8355 | clear_hv_tscchange_cb(); |
8356 | #endif | |
cef84c30 | 8357 | kvm_lapic_exit(); |
ff9d07a0 ZY |
8358 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
8359 | ||
888d256e JK |
8360 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
8361 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
8362 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 8363 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
8364 | #ifdef CONFIG_X86_64 |
8365 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
3f804f6d | 8366 | irq_work_sync(&pvclock_irq_work); |
594b27e6 | 8367 | cancel_work_sync(&pvclock_gtod_work); |
16e8d74d | 8368 | #endif |
afaf0b2f | 8369 | kvm_x86_ops.hardware_enable = NULL; |
56c6d28a | 8370 | kvm_mmu_module_exit(); |
7e34fbd0 | 8371 | free_percpu(user_return_msrs); |
dfdc0a71 | 8372 | kmem_cache_destroy(x86_emulator_cache); |
b666a4b6 | 8373 | kmem_cache_destroy(x86_fpu_cache); |
b59b153d | 8374 | #ifdef CONFIG_KVM_XEN |
c462f859 | 8375 | static_key_deferred_flush(&kvm_xen_enabled); |
7d6bbebb | 8376 | WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); |
b59b153d | 8377 | #endif |
56c6d28a | 8378 | } |
f8c16bba | 8379 | |
872f36eb | 8380 | static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) |
8776e519 HB |
8381 | { |
8382 | ++vcpu->stat.halt_exits; | |
35754c98 | 8383 | if (lapic_in_kernel(vcpu)) { |
647daca2 | 8384 | vcpu->arch.mp_state = state; |
8776e519 HB |
8385 | return 1; |
8386 | } else { | |
647daca2 | 8387 | vcpu->run->exit_reason = reason; |
8776e519 HB |
8388 | return 0; |
8389 | } | |
8390 | } | |
647daca2 TL |
8391 | |
8392 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) | |
8393 | { | |
8394 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); | |
8395 | } | |
5cb56059 JS |
8396 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
8397 | ||
8398 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
8399 | { | |
6affcbed KH |
8400 | int ret = kvm_skip_emulated_instruction(vcpu); |
8401 | /* | |
8402 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
8403 | * KVM_EXIT_DEBUG here. | |
8404 | */ | |
8405 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 8406 | } |
8776e519 HB |
8407 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
8408 | ||
647daca2 TL |
8409 | int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) |
8410 | { | |
8411 | int ret = kvm_skip_emulated_instruction(vcpu); | |
8412 | ||
8413 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; | |
8414 | } | |
8415 | EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); | |
8416 | ||
8ef81a9a | 8417 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8418 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
8419 | unsigned long clock_type) | |
8420 | { | |
8421 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 8422 | struct timespec64 ts; |
80fbd89c | 8423 | u64 cycle; |
55dd00a7 MT |
8424 | int ret; |
8425 | ||
8426 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
8427 | return -KVM_EOPNOTSUPP; | |
8428 | ||
7ca7f3b9 | 8429 | if (!kvm_get_walltime_and_clockread(&ts, &cycle)) |
55dd00a7 MT |
8430 | return -KVM_EOPNOTSUPP; |
8431 | ||
8432 | clock_pairing.sec = ts.tv_sec; | |
8433 | clock_pairing.nsec = ts.tv_nsec; | |
8434 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
8435 | clock_pairing.flags = 0; | |
bcbfbd8e | 8436 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
8437 | |
8438 | ret = 0; | |
8439 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
8440 | sizeof(struct kvm_clock_pairing))) | |
8441 | ret = -KVM_EFAULT; | |
8442 | ||
8443 | return ret; | |
8444 | } | |
8ef81a9a | 8445 | #endif |
55dd00a7 | 8446 | |
6aef266c SV |
8447 | /* |
8448 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
8449 | * | |
8450 | * @apicid - apicid of vcpu to be kicked. | |
8451 | */ | |
8452 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
8453 | { | |
24d2166b | 8454 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 8455 | |
150a84fe | 8456 | lapic_irq.shorthand = APIC_DEST_NOSHORT; |
c96001c5 | 8457 | lapic_irq.dest_mode = APIC_DEST_PHYSICAL; |
ebd28fcb | 8458 | lapic_irq.level = 0; |
24d2166b | 8459 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 8460 | lapic_irq.msi_redir_hint = false; |
6aef266c | 8461 | |
24d2166b | 8462 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 8463 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
8464 | } |
8465 | ||
4e19c36f SS |
8466 | bool kvm_apicv_activated(struct kvm *kvm) |
8467 | { | |
8468 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
8469 | } | |
8470 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
8471 | ||
4651fc56 | 8472 | static void kvm_apicv_init(struct kvm *kvm) |
4e19c36f | 8473 | { |
4651fc56 | 8474 | if (enable_apicv) |
4e19c36f SS |
8475 | clear_bit(APICV_INHIBIT_REASON_DISABLE, |
8476 | &kvm->arch.apicv_inhibit_reasons); | |
8477 | else | |
8478 | set_bit(APICV_INHIBIT_REASON_DISABLE, | |
8479 | &kvm->arch.apicv_inhibit_reasons); | |
8480 | } | |
4e19c36f | 8481 | |
4a7132ef | 8482 | static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) |
71506297 WL |
8483 | { |
8484 | struct kvm_vcpu *target = NULL; | |
8485 | struct kvm_apic_map *map; | |
8486 | ||
4a7132ef WL |
8487 | vcpu->stat.directed_yield_attempted++; |
8488 | ||
72b268a8 WL |
8489 | if (single_task_running()) |
8490 | goto no_yield; | |
8491 | ||
71506297 | 8492 | rcu_read_lock(); |
4a7132ef | 8493 | map = rcu_dereference(vcpu->kvm->arch.apic_map); |
71506297 WL |
8494 | |
8495 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
8496 | target = map->phys_map[dest_id]->vcpu; | |
8497 | ||
8498 | rcu_read_unlock(); | |
8499 | ||
4a7132ef WL |
8500 | if (!target || !READ_ONCE(target->ready)) |
8501 | goto no_yield; | |
8502 | ||
a1fa4cbd WL |
8503 | /* Ignore requests to yield to self */ |
8504 | if (vcpu == target) | |
8505 | goto no_yield; | |
8506 | ||
4a7132ef WL |
8507 | if (kvm_vcpu_yield_to(target) <= 0) |
8508 | goto no_yield; | |
8509 | ||
8510 | vcpu->stat.directed_yield_successful++; | |
8511 | ||
8512 | no_yield: | |
8513 | return; | |
71506297 WL |
8514 | } |
8515 | ||
8776e519 HB |
8516 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
8517 | { | |
8518 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 8519 | int op_64_bit; |
8776e519 | 8520 | |
23200b7a JM |
8521 | if (kvm_xen_hypercall_enabled(vcpu->kvm)) |
8522 | return kvm_xen_hypercall(vcpu); | |
8523 | ||
8f014550 | 8524 | if (kvm_hv_hypercall_enabled(vcpu)) |
696ca779 | 8525 | return kvm_hv_hypercall(vcpu); |
55cd8e5a | 8526 | |
de3cd117 SC |
8527 | nr = kvm_rax_read(vcpu); |
8528 | a0 = kvm_rbx_read(vcpu); | |
8529 | a1 = kvm_rcx_read(vcpu); | |
8530 | a2 = kvm_rdx_read(vcpu); | |
8531 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 8532 | |
229456fc | 8533 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 8534 | |
a449c7aa NA |
8535 | op_64_bit = is_64_bit_mode(vcpu); |
8536 | if (!op_64_bit) { | |
8776e519 HB |
8537 | nr &= 0xFFFFFFFF; |
8538 | a0 &= 0xFFFFFFFF; | |
8539 | a1 &= 0xFFFFFFFF; | |
8540 | a2 &= 0xFFFFFFFF; | |
8541 | a3 &= 0xFFFFFFFF; | |
8542 | } | |
8543 | ||
b3646477 | 8544 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { |
07708c4a | 8545 | ret = -KVM_EPERM; |
696ca779 | 8546 | goto out; |
07708c4a JK |
8547 | } |
8548 | ||
66570e96 OU |
8549 | ret = -KVM_ENOSYS; |
8550 | ||
8776e519 | 8551 | switch (nr) { |
b93463aa AK |
8552 | case KVM_HC_VAPIC_POLL_IRQ: |
8553 | ret = 0; | |
8554 | break; | |
6aef266c | 8555 | case KVM_HC_KICK_CPU: |
66570e96 OU |
8556 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) |
8557 | break; | |
8558 | ||
6aef266c | 8559 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); |
4a7132ef | 8560 | kvm_sched_yield(vcpu, a1); |
6aef266c SV |
8561 | ret = 0; |
8562 | break; | |
8ef81a9a | 8563 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8564 | case KVM_HC_CLOCK_PAIRING: |
8565 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
8566 | break; | |
1ed199a4 | 8567 | #endif |
4180bf1b | 8568 | case KVM_HC_SEND_IPI: |
66570e96 OU |
8569 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) |
8570 | break; | |
8571 | ||
4180bf1b WL |
8572 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); |
8573 | break; | |
71506297 | 8574 | case KVM_HC_SCHED_YIELD: |
66570e96 OU |
8575 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) |
8576 | break; | |
8577 | ||
4a7132ef | 8578 | kvm_sched_yield(vcpu, a0); |
71506297 WL |
8579 | ret = 0; |
8580 | break; | |
8776e519 HB |
8581 | default: |
8582 | ret = -KVM_ENOSYS; | |
8583 | break; | |
8584 | } | |
696ca779 | 8585 | out: |
a449c7aa NA |
8586 | if (!op_64_bit) |
8587 | ret = (u32)ret; | |
de3cd117 | 8588 | kvm_rax_write(vcpu, ret); |
6356ee0c | 8589 | |
f11c3a8d | 8590 | ++vcpu->stat.hypercalls; |
6356ee0c | 8591 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
8592 | } |
8593 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
8594 | ||
b6785def | 8595 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 8596 | { |
d6aa1000 | 8597 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 8598 | char instruction[3]; |
5fdbf976 | 8599 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 8600 | |
b3646477 | 8601 | static_call(kvm_x86_patch_hypercall)(vcpu, instruction); |
8776e519 | 8602 | |
ce2e852e DV |
8603 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
8604 | &ctxt->exception); | |
8776e519 HB |
8605 | } |
8606 | ||
851ba692 | 8607 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8608 | { |
782d422b MG |
8609 | return vcpu->run->request_interrupt_window && |
8610 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
8611 | } |
8612 | ||
851ba692 | 8613 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8614 | { |
851ba692 AK |
8615 | struct kvm_run *kvm_run = vcpu->run; |
8616 | ||
f1c6366e TL |
8617 | /* |
8618 | * if_flag is obsolete and useless, so do not bother | |
8619 | * setting it for SEV-ES guests. Userspace can just | |
8620 | * use kvm_run->ready_for_interrupt_injection. | |
8621 | */ | |
8622 | kvm_run->if_flag = !vcpu->arch.guest_state_protected | |
8623 | && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; | |
8624 | ||
2d3ad1f4 | 8625 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 8626 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
8627 | kvm_run->ready_for_interrupt_injection = |
8628 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 8629 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
15aad3be CQ |
8630 | |
8631 | if (is_smm(vcpu)) | |
8632 | kvm_run->flags |= KVM_RUN_X86_SMM; | |
b6c7a5dc HB |
8633 | } |
8634 | ||
95ba8273 GN |
8635 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
8636 | { | |
8637 | int max_irr, tpr; | |
8638 | ||
afaf0b2f | 8639 | if (!kvm_x86_ops.update_cr8_intercept) |
95ba8273 GN |
8640 | return; |
8641 | ||
bce87cce | 8642 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
8643 | return; |
8644 | ||
d62caabb AS |
8645 | if (vcpu->arch.apicv_active) |
8646 | return; | |
8647 | ||
8db3baa2 GN |
8648 | if (!vcpu->arch.apic->vapic_addr) |
8649 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
8650 | else | |
8651 | max_irr = -1; | |
95ba8273 GN |
8652 | |
8653 | if (max_irr != -1) | |
8654 | max_irr >>= 4; | |
8655 | ||
8656 | tpr = kvm_lapic_get_cr8(vcpu); | |
8657 | ||
b3646477 | 8658 | static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); |
95ba8273 GN |
8659 | } |
8660 | ||
b97f0745 | 8661 | |
cb6a32c2 SC |
8662 | int kvm_check_nested_events(struct kvm_vcpu *vcpu) |
8663 | { | |
cb6a32c2 SC |
8664 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
8665 | kvm_x86_ops.nested_ops->triple_fault(vcpu); | |
8666 | return 1; | |
8667 | } | |
8668 | ||
8669 | return kvm_x86_ops.nested_ops->check_events(vcpu); | |
8670 | } | |
8671 | ||
b97f0745 ML |
8672 | static void kvm_inject_exception(struct kvm_vcpu *vcpu) |
8673 | { | |
8674 | if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) | |
8675 | vcpu->arch.exception.error_code = false; | |
8676 | static_call(kvm_x86_queue_exception)(vcpu); | |
8677 | } | |
8678 | ||
a5f6909a | 8679 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) |
95ba8273 | 8680 | { |
b6b8a145 | 8681 | int r; |
c6b22f59 | 8682 | bool can_inject = true; |
b6b8a145 | 8683 | |
95ba8273 | 8684 | /* try to reinject previous events if any */ |
664f8e26 | 8685 | |
c6b22f59 | 8686 | if (vcpu->arch.exception.injected) { |
b97f0745 | 8687 | kvm_inject_exception(vcpu); |
c6b22f59 PB |
8688 | can_inject = false; |
8689 | } | |
664f8e26 | 8690 | /* |
a042c26f LA |
8691 | * Do not inject an NMI or interrupt if there is a pending |
8692 | * exception. Exceptions and interrupts are recognized at | |
8693 | * instruction boundaries, i.e. the start of an instruction. | |
8694 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
8695 | * NMIs and interrupts, i.e. traps are recognized before an | |
8696 | * NMI/interrupt that's pending on the same instruction. | |
8697 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
8698 | * priority, but are only generated (pended) during instruction | |
8699 | * execution, i.e. a pending fault-like exception means the | |
8700 | * fault occurred on the *previous* instruction and must be | |
8701 | * serviced prior to recognizing any new events in order to | |
8702 | * fully complete the previous instruction. | |
664f8e26 | 8703 | */ |
1a680e35 | 8704 | else if (!vcpu->arch.exception.pending) { |
c6b22f59 | 8705 | if (vcpu->arch.nmi_injected) { |
b3646477 | 8706 | static_call(kvm_x86_set_nmi)(vcpu); |
c6b22f59 PB |
8707 | can_inject = false; |
8708 | } else if (vcpu->arch.interrupt.injected) { | |
b3646477 | 8709 | static_call(kvm_x86_set_irq)(vcpu); |
c6b22f59 PB |
8710 | can_inject = false; |
8711 | } | |
664f8e26 WL |
8712 | } |
8713 | ||
3b82b8d7 SC |
8714 | WARN_ON_ONCE(vcpu->arch.exception.injected && |
8715 | vcpu->arch.exception.pending); | |
8716 | ||
1a680e35 LA |
8717 | /* |
8718 | * Call check_nested_events() even if we reinjected a previous event | |
8719 | * in order for caller to determine if it should require immediate-exit | |
8720 | * from L2 to L1 due to pending L1 events which require exit | |
8721 | * from L2 to L1. | |
8722 | */ | |
56083bdf | 8723 | if (is_guest_mode(vcpu)) { |
cb6a32c2 | 8724 | r = kvm_check_nested_events(vcpu); |
c9d40913 | 8725 | if (r < 0) |
a5f6909a | 8726 | goto out; |
664f8e26 WL |
8727 | } |
8728 | ||
8729 | /* try to inject new event if pending */ | |
b59bb7bd | 8730 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
8731 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
8732 | vcpu->arch.exception.has_error_code, | |
8733 | vcpu->arch.exception.error_code); | |
d6e8c854 | 8734 | |
664f8e26 WL |
8735 | vcpu->arch.exception.pending = false; |
8736 | vcpu->arch.exception.injected = true; | |
8737 | ||
d6e8c854 NA |
8738 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
8739 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
8740 | X86_EFLAGS_RF); | |
8741 | ||
f10c729f | 8742 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
f10c729f JM |
8743 | kvm_deliver_exception_payload(vcpu); |
8744 | if (vcpu->arch.dr7 & DR7_GD) { | |
8745 | vcpu->arch.dr7 &= ~DR7_GD; | |
8746 | kvm_update_dr7(vcpu); | |
8747 | } | |
6bdf0662 NA |
8748 | } |
8749 | ||
b97f0745 | 8750 | kvm_inject_exception(vcpu); |
c6b22f59 | 8751 | can_inject = false; |
1a680e35 LA |
8752 | } |
8753 | ||
c9d40913 PB |
8754 | /* |
8755 | * Finally, inject interrupt events. If an event cannot be injected | |
8756 | * due to architectural conditions (e.g. IF=0) a window-open exit | |
8757 | * will re-request KVM_REQ_EVENT. Sometimes however an event is pending | |
8758 | * and can architecturally be injected, but we cannot do it right now: | |
8759 | * an interrupt could have arrived just now and we have to inject it | |
8760 | * as a vmexit, or there could already an event in the queue, which is | |
8761 | * indicated by can_inject. In that case we request an immediate exit | |
8762 | * in order to make progress and get back here for another iteration. | |
8763 | * The kvm_x86_ops hooks communicate this by returning -EBUSY. | |
8764 | */ | |
8765 | if (vcpu->arch.smi_pending) { | |
b3646477 | 8766 | r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 8767 | if (r < 0) |
a5f6909a | 8768 | goto out; |
c9d40913 PB |
8769 | if (r) { |
8770 | vcpu->arch.smi_pending = false; | |
8771 | ++vcpu->arch.smi_count; | |
8772 | enter_smm(vcpu); | |
8773 | can_inject = false; | |
8774 | } else | |
b3646477 | 8775 | static_call(kvm_x86_enable_smi_window)(vcpu); |
c9d40913 PB |
8776 | } |
8777 | ||
8778 | if (vcpu->arch.nmi_pending) { | |
b3646477 | 8779 | r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 8780 | if (r < 0) |
a5f6909a | 8781 | goto out; |
c9d40913 PB |
8782 | if (r) { |
8783 | --vcpu->arch.nmi_pending; | |
8784 | vcpu->arch.nmi_injected = true; | |
b3646477 | 8785 | static_call(kvm_x86_set_nmi)(vcpu); |
c9d40913 | 8786 | can_inject = false; |
b3646477 | 8787 | WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); |
c9d40913 PB |
8788 | } |
8789 | if (vcpu->arch.nmi_pending) | |
b3646477 | 8790 | static_call(kvm_x86_enable_nmi_window)(vcpu); |
c9d40913 | 8791 | } |
1a680e35 | 8792 | |
c9d40913 | 8793 | if (kvm_cpu_has_injectable_intr(vcpu)) { |
b3646477 | 8794 | r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 8795 | if (r < 0) |
a5f6909a | 8796 | goto out; |
c9d40913 PB |
8797 | if (r) { |
8798 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); | |
b3646477 JB |
8799 | static_call(kvm_x86_set_irq)(vcpu); |
8800 | WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); | |
c9d40913 PB |
8801 | } |
8802 | if (kvm_cpu_has_injectable_intr(vcpu)) | |
b3646477 | 8803 | static_call(kvm_x86_enable_irq_window)(vcpu); |
95ba8273 | 8804 | } |
ee2cd4b7 | 8805 | |
c9d40913 PB |
8806 | if (is_guest_mode(vcpu) && |
8807 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
8808 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
8809 | *req_immediate_exit = true; | |
8810 | ||
8811 | WARN_ON(vcpu->arch.exception.pending); | |
a5f6909a | 8812 | return 0; |
c9d40913 | 8813 | |
a5f6909a JM |
8814 | out: |
8815 | if (r == -EBUSY) { | |
8816 | *req_immediate_exit = true; | |
8817 | r = 0; | |
8818 | } | |
8819 | return r; | |
95ba8273 GN |
8820 | } |
8821 | ||
7460fb4a AK |
8822 | static void process_nmi(struct kvm_vcpu *vcpu) |
8823 | { | |
8824 | unsigned limit = 2; | |
8825 | ||
8826 | /* | |
8827 | * x86 is limited to one NMI running, and one NMI pending after it. | |
8828 | * If an NMI is already in progress, limit further NMIs to just one. | |
8829 | * Otherwise, allow two (and we'll inject the first one immediately). | |
8830 | */ | |
b3646477 | 8831 | if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) |
7460fb4a AK |
8832 | limit = 1; |
8833 | ||
8834 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
8835 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
8836 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8837 | } | |
8838 | ||
ee2cd4b7 | 8839 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
8840 | { |
8841 | u32 flags = 0; | |
8842 | flags |= seg->g << 23; | |
8843 | flags |= seg->db << 22; | |
8844 | flags |= seg->l << 21; | |
8845 | flags |= seg->avl << 20; | |
8846 | flags |= seg->present << 15; | |
8847 | flags |= seg->dpl << 13; | |
8848 | flags |= seg->s << 12; | |
8849 | flags |= seg->type << 8; | |
8850 | return flags; | |
8851 | } | |
8852 | ||
ee2cd4b7 | 8853 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
8854 | { |
8855 | struct kvm_segment seg; | |
8856 | int offset; | |
8857 | ||
8858 | kvm_get_segment(vcpu, &seg, n); | |
8859 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
8860 | ||
8861 | if (n < 3) | |
8862 | offset = 0x7f84 + n * 12; | |
8863 | else | |
8864 | offset = 0x7f2c + (n - 3) * 12; | |
8865 | ||
8866 | put_smstate(u32, buf, offset + 8, seg.base); | |
8867 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 8868 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
8869 | } |
8870 | ||
efbb288a | 8871 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 8872 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
8873 | { |
8874 | struct kvm_segment seg; | |
8875 | int offset; | |
8876 | u16 flags; | |
8877 | ||
8878 | kvm_get_segment(vcpu, &seg, n); | |
8879 | offset = 0x7e00 + n * 16; | |
8880 | ||
ee2cd4b7 | 8881 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
8882 | put_smstate(u16, buf, offset, seg.selector); |
8883 | put_smstate(u16, buf, offset + 2, flags); | |
8884 | put_smstate(u32, buf, offset + 4, seg.limit); | |
8885 | put_smstate(u64, buf, offset + 8, seg.base); | |
8886 | } | |
efbb288a | 8887 | #endif |
660a5d51 | 8888 | |
ee2cd4b7 | 8889 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
8890 | { |
8891 | struct desc_ptr dt; | |
8892 | struct kvm_segment seg; | |
8893 | unsigned long val; | |
8894 | int i; | |
8895 | ||
8896 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
8897 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
8898 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
8899 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
8900 | ||
8901 | for (i = 0; i < 8; i++) | |
27b4a9c4 | 8902 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); |
660a5d51 PB |
8903 | |
8904 | kvm_get_dr(vcpu, 6, &val); | |
8905 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
8906 | kvm_get_dr(vcpu, 7, &val); | |
8907 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
8908 | ||
8909 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
8910 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
8911 | put_smstate(u32, buf, 0x7f64, seg.base); | |
8912 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 8913 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
8914 | |
8915 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
8916 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
8917 | put_smstate(u32, buf, 0x7f80, seg.base); | |
8918 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 8919 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 | 8920 | |
b3646477 | 8921 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
660a5d51 PB |
8922 | put_smstate(u32, buf, 0x7f74, dt.address); |
8923 | put_smstate(u32, buf, 0x7f70, dt.size); | |
8924 | ||
b3646477 | 8925 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
660a5d51 PB |
8926 | put_smstate(u32, buf, 0x7f58, dt.address); |
8927 | put_smstate(u32, buf, 0x7f54, dt.size); | |
8928 | ||
8929 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 8930 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
8931 | |
8932 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
8933 | ||
8934 | /* revision id */ | |
8935 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
8936 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
8937 | } | |
8938 | ||
b68f3cc7 | 8939 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 8940 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 8941 | { |
660a5d51 PB |
8942 | struct desc_ptr dt; |
8943 | struct kvm_segment seg; | |
8944 | unsigned long val; | |
8945 | int i; | |
8946 | ||
8947 | for (i = 0; i < 16; i++) | |
27b4a9c4 | 8948 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); |
660a5d51 PB |
8949 | |
8950 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
8951 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
8952 | ||
8953 | kvm_get_dr(vcpu, 6, &val); | |
8954 | put_smstate(u64, buf, 0x7f68, val); | |
8955 | kvm_get_dr(vcpu, 7, &val); | |
8956 | put_smstate(u64, buf, 0x7f60, val); | |
8957 | ||
8958 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
8959 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
8960 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
8961 | ||
8962 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
8963 | ||
8964 | /* revision id */ | |
8965 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
8966 | ||
8967 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
8968 | ||
8969 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
8970 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 8971 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
8972 | put_smstate(u32, buf, 0x7e94, seg.limit); |
8973 | put_smstate(u64, buf, 0x7e98, seg.base); | |
8974 | ||
b3646477 | 8975 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
660a5d51 PB |
8976 | put_smstate(u32, buf, 0x7e84, dt.size); |
8977 | put_smstate(u64, buf, 0x7e88, dt.address); | |
8978 | ||
8979 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
8980 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 8981 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
8982 | put_smstate(u32, buf, 0x7e74, seg.limit); |
8983 | put_smstate(u64, buf, 0x7e78, seg.base); | |
8984 | ||
b3646477 | 8985 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
660a5d51 PB |
8986 | put_smstate(u32, buf, 0x7e64, dt.size); |
8987 | put_smstate(u64, buf, 0x7e68, dt.address); | |
8988 | ||
8989 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 8990 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 8991 | } |
b68f3cc7 | 8992 | #endif |
660a5d51 | 8993 | |
ee2cd4b7 | 8994 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 8995 | { |
660a5d51 | 8996 | struct kvm_segment cs, ds; |
18c3626e | 8997 | struct desc_ptr dt; |
660a5d51 PB |
8998 | char buf[512]; |
8999 | u32 cr0; | |
9000 | ||
660a5d51 | 9001 | memset(buf, 0, 512); |
b68f3cc7 | 9002 | #ifdef CONFIG_X86_64 |
d6321d49 | 9003 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 9004 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 9005 | else |
b68f3cc7 | 9006 | #endif |
ee2cd4b7 | 9007 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 9008 | |
0234bf88 | 9009 | /* |
ecc513e5 SC |
9010 | * Give enter_smm() a chance to make ISA-specific changes to the vCPU |
9011 | * state (e.g. leave guest mode) after we've saved the state into the | |
9012 | * SMM state-save area. | |
0234bf88 | 9013 | */ |
ecc513e5 | 9014 | static_call(kvm_x86_enter_smm)(vcpu, buf); |
0234bf88 | 9015 | |
dc87275f | 9016 | kvm_smm_changed(vcpu, true); |
54bf36aa | 9017 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 | 9018 | |
b3646477 | 9019 | if (static_call(kvm_x86_get_nmi_mask)(vcpu)) |
660a5d51 PB |
9020 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; |
9021 | else | |
b3646477 | 9022 | static_call(kvm_x86_set_nmi_mask)(vcpu, true); |
660a5d51 PB |
9023 | |
9024 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
9025 | kvm_rip_write(vcpu, 0x8000); | |
9026 | ||
9027 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
b3646477 | 9028 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
660a5d51 PB |
9029 | vcpu->arch.cr0 = cr0; |
9030 | ||
b3646477 | 9031 | static_call(kvm_x86_set_cr4)(vcpu, 0); |
660a5d51 | 9032 | |
18c3626e PB |
9033 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
9034 | dt.address = dt.size = 0; | |
b3646477 | 9035 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
18c3626e | 9036 | |
996ff542 | 9037 | kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
660a5d51 PB |
9038 | |
9039 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
9040 | cs.base = vcpu->arch.smbase; | |
9041 | ||
9042 | ds.selector = 0; | |
9043 | ds.base = 0; | |
9044 | ||
9045 | cs.limit = ds.limit = 0xffffffff; | |
9046 | cs.type = ds.type = 0x3; | |
9047 | cs.dpl = ds.dpl = 0; | |
9048 | cs.db = ds.db = 0; | |
9049 | cs.s = ds.s = 1; | |
9050 | cs.l = ds.l = 0; | |
9051 | cs.g = ds.g = 1; | |
9052 | cs.avl = ds.avl = 0; | |
9053 | cs.present = ds.present = 1; | |
9054 | cs.unusable = ds.unusable = 0; | |
9055 | cs.padding = ds.padding = 0; | |
9056 | ||
9057 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
9058 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
9059 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
9060 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
9061 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
9062 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
9063 | ||
b68f3cc7 | 9064 | #ifdef CONFIG_X86_64 |
d6321d49 | 9065 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
b3646477 | 9066 | static_call(kvm_x86_set_efer)(vcpu, 0); |
b68f3cc7 | 9067 | #endif |
660a5d51 | 9068 | |
aedbaf4f | 9069 | kvm_update_cpuid_runtime(vcpu); |
660a5d51 | 9070 | kvm_mmu_reset_context(vcpu); |
64d60670 PB |
9071 | } |
9072 | ||
ee2cd4b7 | 9073 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
9074 | { |
9075 | vcpu->arch.smi_pending = true; | |
9076 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9077 | } | |
9078 | ||
7ee30bc1 NNL |
9079 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
9080 | unsigned long *vcpu_bitmap) | |
9081 | { | |
9082 | cpumask_var_t cpus; | |
7ee30bc1 NNL |
9083 | |
9084 | zalloc_cpumask_var(&cpus, GFP_ATOMIC); | |
9085 | ||
db5a95ec | 9086 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, |
54163a34 | 9087 | NULL, vcpu_bitmap, cpus); |
7ee30bc1 NNL |
9088 | |
9089 | free_cpumask_var(cpus); | |
9090 | } | |
9091 | ||
2860c4b1 PB |
9092 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
9093 | { | |
9094 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
9095 | } | |
9096 | ||
8df14af4 SS |
9097 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
9098 | { | |
9099 | if (!lapic_in_kernel(vcpu)) | |
9100 | return; | |
9101 | ||
9102 | vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); | |
9103 | kvm_apic_update_apicv(vcpu); | |
b3646477 | 9104 | static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); |
8df14af4 SS |
9105 | } |
9106 | EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); | |
9107 | ||
9108 | /* | |
9109 | * NOTE: Do not hold any lock prior to calling this. | |
9110 | * | |
9111 | * In particular, kvm_request_apicv_update() expects kvm->srcu not to be | |
9112 | * locked, because it calls __x86_set_memory_region() which does | |
9113 | * synchronize_srcu(&kvm->srcu). | |
9114 | */ | |
9115 | void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) | |
9116 | { | |
7d611233 | 9117 | struct kvm_vcpu *except; |
8e205a6b PB |
9118 | unsigned long old, new, expected; |
9119 | ||
afaf0b2f | 9120 | if (!kvm_x86_ops.check_apicv_inhibit_reasons || |
b3646477 | 9121 | !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) |
ef8efd7a SS |
9122 | return; |
9123 | ||
8e205a6b PB |
9124 | old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); |
9125 | do { | |
9126 | expected = new = old; | |
9127 | if (activate) | |
9128 | __clear_bit(bit, &new); | |
9129 | else | |
9130 | __set_bit(bit, &new); | |
9131 | if (new == old) | |
9132 | break; | |
9133 | old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); | |
9134 | } while (old != expected); | |
9135 | ||
9136 | if (!!old == !!new) | |
9137 | return; | |
8df14af4 | 9138 | |
24bbf74c | 9139 | trace_kvm_apicv_update_request(activate, bit); |
afaf0b2f | 9140 | if (kvm_x86_ops.pre_update_apicv_exec_ctrl) |
b3646477 | 9141 | static_call(kvm_x86_pre_update_apicv_exec_ctrl)(kvm, activate); |
7d611233 SS |
9142 | |
9143 | /* | |
9144 | * Sending request to update APICV for all other vcpus, | |
9145 | * while update the calling vcpu immediately instead of | |
9146 | * waiting for another #VMEXIT to handle the request. | |
9147 | */ | |
9148 | except = kvm_get_running_vcpu(); | |
9149 | kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE, | |
9150 | except); | |
9151 | if (except) | |
9152 | kvm_vcpu_update_apicv(except); | |
8df14af4 SS |
9153 | } |
9154 | EXPORT_SYMBOL_GPL(kvm_request_apicv_update); | |
9155 | ||
3d81bc7e | 9156 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 9157 | { |
dcbd3e49 | 9158 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 9159 | return; |
c7c9c56c | 9160 | |
6308630b | 9161 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 9162 | |
b053b2ae | 9163 | if (irqchip_split(vcpu->kvm)) |
6308630b | 9164 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 9165 | else { |
fa59cc00 | 9166 | if (vcpu->arch.apicv_active) |
b3646477 | 9167 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
e97f852f WL |
9168 | if (ioapic_in_kernel(vcpu->kvm)) |
9169 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 9170 | } |
e40ff1d6 LA |
9171 | |
9172 | if (is_guest_mode(vcpu)) | |
9173 | vcpu->arch.load_eoi_exitmap_pending = true; | |
9174 | else | |
9175 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
9176 | } | |
9177 | ||
9178 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
9179 | { | |
9180 | u64 eoi_exit_bitmap[4]; | |
9181 | ||
9182 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
9183 | return; | |
9184 | ||
f2bc14b6 VK |
9185 | if (to_hv_vcpu(vcpu)) |
9186 | bitmap_or((ulong *)eoi_exit_bitmap, | |
9187 | vcpu->arch.ioapic_handled_vectors, | |
9188 | to_hv_synic(vcpu)->vec_bitmap, 256); | |
9189 | ||
b3646477 | 9190 | static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); |
c7c9c56c YZ |
9191 | } |
9192 | ||
e649b3f0 ET |
9193 | void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
9194 | unsigned long start, unsigned long end) | |
b1394e74 RK |
9195 | { |
9196 | unsigned long apic_address; | |
9197 | ||
9198 | /* | |
9199 | * The physical address of apic access page is stored in the VMCS. | |
9200 | * Update it when it becomes invalid. | |
9201 | */ | |
9202 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
9203 | if (start <= apic_address && apic_address < end) | |
9204 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
9205 | } | |
9206 | ||
4256f43f TC |
9207 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
9208 | { | |
35754c98 | 9209 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
9210 | return; |
9211 | ||
afaf0b2f | 9212 | if (!kvm_x86_ops.set_apic_access_page_addr) |
4256f43f TC |
9213 | return; |
9214 | ||
b3646477 | 9215 | static_call(kvm_x86_set_apic_access_page_addr)(vcpu); |
4256f43f | 9216 | } |
4256f43f | 9217 | |
d264ee0c SC |
9218 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
9219 | { | |
9220 | smp_send_reschedule(vcpu->cpu); | |
9221 | } | |
9222 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
9223 | ||
9357d939 | 9224 | /* |
362c698f | 9225 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
9226 | * exiting to the userspace. Otherwise, the value will be returned to the |
9227 | * userspace. | |
9228 | */ | |
851ba692 | 9229 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
9230 | { |
9231 | int r; | |
62a193ed MG |
9232 | bool req_int_win = |
9233 | dm_request_for_irq_injection(vcpu) && | |
9234 | kvm_cpu_accept_dm_intr(vcpu); | |
404d5d7b | 9235 | fastpath_t exit_fastpath; |
62a193ed | 9236 | |
730dca42 | 9237 | bool req_immediate_exit = false; |
b6c7a5dc | 9238 | |
fb04a1ed PX |
9239 | /* Forbid vmenter if vcpu dirty ring is soft-full */ |
9240 | if (unlikely(vcpu->kvm->dirty_ring_size && | |
9241 | kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { | |
9242 | vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; | |
9243 | trace_kvm_dirty_ring_exit(vcpu); | |
9244 | r = 0; | |
9245 | goto out; | |
9246 | } | |
9247 | ||
2fa6e1e1 | 9248 | if (kvm_request_pending(vcpu)) { |
729c15c2 | 9249 | if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { |
9a78e158 | 9250 | if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { |
671ddc70 JM |
9251 | r = 0; |
9252 | goto out; | |
9253 | } | |
9254 | } | |
a8eeb04a | 9255 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 9256 | kvm_mmu_unload(vcpu); |
a8eeb04a | 9257 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 9258 | __kvm_migrate_timers(vcpu); |
d828199e MT |
9259 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
9260 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
9261 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
9262 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
9263 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
9264 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
9265 | if (unlikely(r)) |
9266 | goto out; | |
9267 | } | |
a8eeb04a | 9268 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 9269 | kvm_mmu_sync_roots(vcpu); |
727a7e27 PB |
9270 | if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) |
9271 | kvm_mmu_load_pgd(vcpu); | |
eeeb4f67 | 9272 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { |
7780938c | 9273 | kvm_vcpu_flush_tlb_all(vcpu); |
eeeb4f67 SC |
9274 | |
9275 | /* Flushing all ASIDs flushes the current ASID... */ | |
9276 | kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
9277 | } | |
9278 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) | |
9279 | kvm_vcpu_flush_tlb_current(vcpu); | |
0baedd79 VK |
9280 | if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu)) |
9281 | kvm_vcpu_flush_tlb_guest(vcpu); | |
eeeb4f67 | 9282 | |
a8eeb04a | 9283 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 9284 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
9285 | r = 0; |
9286 | goto out; | |
9287 | } | |
a8eeb04a | 9288 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
cb6a32c2 SC |
9289 | if (is_guest_mode(vcpu)) { |
9290 | kvm_x86_ops.nested_ops->triple_fault(vcpu); | |
9291 | } else { | |
9292 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; | |
9293 | vcpu->mmio_needed = 0; | |
9294 | r = 0; | |
9295 | goto out; | |
9296 | } | |
71c4dfaf | 9297 | } |
af585b92 GN |
9298 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
9299 | /* Page is swapped out. Do synthetic halt */ | |
9300 | vcpu->arch.apf.halted = true; | |
9301 | r = 1; | |
9302 | goto out; | |
9303 | } | |
c9aaa895 GC |
9304 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
9305 | record_steal_time(vcpu); | |
64d60670 PB |
9306 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
9307 | process_smi(vcpu); | |
7460fb4a AK |
9308 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
9309 | process_nmi(vcpu); | |
f5132b01 | 9310 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 9311 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 9312 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 9313 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
9314 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
9315 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
9316 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 9317 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
9318 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
9319 | vcpu->run->eoi.vector = | |
9320 | vcpu->arch.pending_ioapic_eoi; | |
9321 | r = 0; | |
9322 | goto out; | |
9323 | } | |
9324 | } | |
3d81bc7e YZ |
9325 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
9326 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
9327 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
9328 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
9329 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
9330 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
9331 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
9332 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
9333 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
9334 | r = 0; | |
9335 | goto out; | |
9336 | } | |
e516cebb AS |
9337 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
9338 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
9339 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
9340 | r = 0; | |
9341 | goto out; | |
9342 | } | |
db397571 | 9343 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
9ff5e030 VK |
9344 | struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); |
9345 | ||
db397571 | 9346 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; |
9ff5e030 | 9347 | vcpu->run->hyperv = hv_vcpu->exit; |
db397571 AS |
9348 | r = 0; |
9349 | goto out; | |
9350 | } | |
f3b138c5 AS |
9351 | |
9352 | /* | |
9353 | * KVM_REQ_HV_STIMER has to be processed after | |
9354 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
9355 | * depend on the guest clock being up-to-date | |
9356 | */ | |
1f4b34f8 AS |
9357 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
9358 | kvm_hv_process_stimers(vcpu); | |
8df14af4 SS |
9359 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
9360 | kvm_vcpu_update_apicv(vcpu); | |
557a961a VK |
9361 | if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) |
9362 | kvm_check_async_pf_completion(vcpu); | |
1a155254 | 9363 | if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) |
b3646477 | 9364 | static_call(kvm_x86_msr_filter_changed)(vcpu); |
a85863c2 MS |
9365 | |
9366 | if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) | |
9367 | static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); | |
2f52d58c | 9368 | } |
b93463aa | 9369 | |
40da8ccd DW |
9370 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || |
9371 | kvm_xen_has_interrupt(vcpu)) { | |
0f1e261e | 9372 | ++vcpu->stat.req_event; |
4fe09bcf JM |
9373 | r = kvm_apic_accept_events(vcpu); |
9374 | if (r < 0) { | |
9375 | r = 0; | |
9376 | goto out; | |
9377 | } | |
66450a21 JK |
9378 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
9379 | r = 1; | |
9380 | goto out; | |
9381 | } | |
9382 | ||
a5f6909a JM |
9383 | r = inject_pending_event(vcpu, &req_immediate_exit); |
9384 | if (r < 0) { | |
9385 | r = 0; | |
9386 | goto out; | |
9387 | } | |
c9d40913 | 9388 | if (req_int_win) |
b3646477 | 9389 | static_call(kvm_x86_enable_irq_window)(vcpu); |
b463a6f7 AK |
9390 | |
9391 | if (kvm_lapic_enabled(vcpu)) { | |
9392 | update_cr8_intercept(vcpu); | |
9393 | kvm_lapic_sync_to_vapic(vcpu); | |
9394 | } | |
9395 | } | |
9396 | ||
d8368af8 AK |
9397 | r = kvm_mmu_reload(vcpu); |
9398 | if (unlikely(r)) { | |
d905c069 | 9399 | goto cancel_injection; |
d8368af8 AK |
9400 | } |
9401 | ||
b6c7a5dc HB |
9402 | preempt_disable(); |
9403 | ||
b3646477 | 9404 | static_call(kvm_x86_prepare_guest_switch)(vcpu); |
b95234c8 PB |
9405 | |
9406 | /* | |
9407 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
9408 | * IPI are then delayed after guest entry, which ensures that they | |
9409 | * result in virtual interrupt delivery. | |
9410 | */ | |
9411 | local_irq_disable(); | |
6b7e2d09 XG |
9412 | vcpu->mode = IN_GUEST_MODE; |
9413 | ||
01b71917 MT |
9414 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
9415 | ||
0f127d12 | 9416 | /* |
b95234c8 | 9417 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 9418 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 9419 | * |
81b01667 | 9420 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
9421 | * pairs with the memory barrier implicit in pi_test_and_set_on |
9422 | * (see vmx_deliver_posted_interrupt). | |
9423 | * | |
9424 | * 3) This also orders the write to mode from any reads to the page | |
9425 | * tables done while the VCPU is running. Please see the comment | |
9426 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 9427 | */ |
01b71917 | 9428 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 9429 | |
b95234c8 PB |
9430 | /* |
9431 | * This handles the case where a posted interrupt was | |
9432 | * notified with kvm_vcpu_kick. | |
9433 | */ | |
fa59cc00 | 9434 | if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) |
b3646477 | 9435 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
32f88400 | 9436 | |
5a9f5443 | 9437 | if (kvm_vcpu_exit_request(vcpu)) { |
6b7e2d09 | 9438 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9439 | smp_wmb(); |
6c142801 AK |
9440 | local_irq_enable(); |
9441 | preempt_enable(); | |
01b71917 | 9442 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 9443 | r = 1; |
d905c069 | 9444 | goto cancel_injection; |
6c142801 AK |
9445 | } |
9446 | ||
c43203ca PB |
9447 | if (req_immediate_exit) { |
9448 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 9449 | static_call(kvm_x86_request_immediate_exit)(vcpu); |
c43203ca | 9450 | } |
d6185f20 | 9451 | |
2620fe26 SC |
9452 | fpregs_assert_state_consistent(); |
9453 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9454 | switch_fpu_return(); | |
5f409e20 | 9455 | |
42dbaa5a | 9456 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
9457 | set_debugreg(0, 7); |
9458 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
9459 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
9460 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
9461 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 9462 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 9463 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 9464 | } |
b6c7a5dc | 9465 | |
d89d04ab PB |
9466 | for (;;) { |
9467 | exit_fastpath = static_call(kvm_x86_run)(vcpu); | |
9468 | if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) | |
9469 | break; | |
9470 | ||
9471 | if (unlikely(kvm_vcpu_exit_request(vcpu))) { | |
9472 | exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; | |
9473 | break; | |
9474 | } | |
9475 | ||
9476 | if (vcpu->arch.apicv_active) | |
9477 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); | |
9478 | } | |
b6c7a5dc | 9479 | |
c77fb5fe PB |
9480 | /* |
9481 | * Do this here before restoring debug registers on the host. And | |
9482 | * since we do this before handling the vmexit, a DR access vmexit | |
9483 | * can (a) read the correct value of the debug registers, (b) set | |
9484 | * KVM_DEBUGREG_WONT_EXIT again. | |
9485 | */ | |
9486 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe | 9487 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
b3646477 | 9488 | static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); |
70e4da7a | 9489 | kvm_update_dr0123(vcpu); |
70e4da7a PB |
9490 | kvm_update_dr7(vcpu); |
9491 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; | |
c77fb5fe PB |
9492 | } |
9493 | ||
24f1e32c FW |
9494 | /* |
9495 | * If the guest has used debug registers, at least dr7 | |
9496 | * will be disabled while returning to the host. | |
9497 | * If we don't have active breakpoints in the host, we don't | |
9498 | * care about the messed up debug address registers. But if | |
9499 | * we have some of them active, restore the old state. | |
9500 | */ | |
59d8eb53 | 9501 | if (hw_breakpoint_active()) |
24f1e32c | 9502 | hw_breakpoint_restore(); |
42dbaa5a | 9503 | |
c967118d | 9504 | vcpu->arch.last_vmentry_cpu = vcpu->cpu; |
4ba76538 | 9505 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 9506 | |
6b7e2d09 | 9507 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9508 | smp_wmb(); |
a547c6db | 9509 | |
b3646477 | 9510 | static_call(kvm_x86_handle_exit_irqoff)(vcpu); |
b6c7a5dc | 9511 | |
d7a08882 SC |
9512 | /* |
9513 | * Consume any pending interrupts, including the possible source of | |
9514 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
9515 | * An instruction is required after local_irq_enable() to fully unblock | |
9516 | * interrupts on processors that implement an interrupt shadow, the | |
9517 | * stat.exits increment will do nicely. | |
9518 | */ | |
9519 | kvm_before_interrupt(vcpu); | |
9520 | local_irq_enable(); | |
b6c7a5dc | 9521 | ++vcpu->stat.exits; |
d7a08882 SC |
9522 | local_irq_disable(); |
9523 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 9524 | |
16045714 WL |
9525 | /* |
9526 | * Wait until after servicing IRQs to account guest time so that any | |
9527 | * ticks that occurred while running the guest are properly accounted | |
9528 | * to the guest. Waiting until IRQs are enabled degrades the accuracy | |
9529 | * of accounting via context tracking, but the loss of accuracy is | |
9530 | * acceptable for all known use cases. | |
9531 | */ | |
9532 | vtime_account_guest_exit(); | |
9533 | ||
ec0671d5 WL |
9534 | if (lapic_in_kernel(vcpu)) { |
9535 | s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; | |
9536 | if (delta != S64_MIN) { | |
9537 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); | |
9538 | vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; | |
9539 | } | |
9540 | } | |
b6c7a5dc | 9541 | |
f2485b3e | 9542 | local_irq_enable(); |
b6c7a5dc HB |
9543 | preempt_enable(); |
9544 | ||
f656ce01 | 9545 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 9546 | |
b6c7a5dc HB |
9547 | /* |
9548 | * Profile KVM exit RIPs: | |
9549 | */ | |
9550 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
9551 | unsigned long rip = kvm_rip_read(vcpu); |
9552 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
9553 | } |
9554 | ||
cc578287 ZA |
9555 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
9556 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 9557 | |
5cfb1d5a MT |
9558 | if (vcpu->arch.apic_attention) |
9559 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 9560 | |
b3646477 | 9561 | r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); |
d905c069 MT |
9562 | return r; |
9563 | ||
9564 | cancel_injection: | |
8081ad06 SC |
9565 | if (req_immediate_exit) |
9566 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 9567 | static_call(kvm_x86_cancel_injection)(vcpu); |
ae7a2a3f MT |
9568 | if (unlikely(vcpu->arch.apic_attention)) |
9569 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
9570 | out: |
9571 | return r; | |
9572 | } | |
b6c7a5dc | 9573 | |
362c698f PB |
9574 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
9575 | { | |
bf9f6ac8 | 9576 | if (!kvm_arch_vcpu_runnable(vcpu) && |
b3646477 | 9577 | (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { |
9c8fd1ba PB |
9578 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
9579 | kvm_vcpu_block(vcpu); | |
9580 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 | 9581 | |
afaf0b2f | 9582 | if (kvm_x86_ops.post_block) |
b3646477 | 9583 | static_call(kvm_x86_post_block)(vcpu); |
bf9f6ac8 | 9584 | |
9c8fd1ba PB |
9585 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
9586 | return 1; | |
9587 | } | |
362c698f | 9588 | |
4fe09bcf JM |
9589 | if (kvm_apic_accept_events(vcpu) < 0) |
9590 | return 0; | |
362c698f PB |
9591 | switch(vcpu->arch.mp_state) { |
9592 | case KVM_MP_STATE_HALTED: | |
647daca2 | 9593 | case KVM_MP_STATE_AP_RESET_HOLD: |
362c698f PB |
9594 | vcpu->arch.pv.pv_unhalted = false; |
9595 | vcpu->arch.mp_state = | |
9596 | KVM_MP_STATE_RUNNABLE; | |
df561f66 | 9597 | fallthrough; |
362c698f PB |
9598 | case KVM_MP_STATE_RUNNABLE: |
9599 | vcpu->arch.apf.halted = false; | |
9600 | break; | |
9601 | case KVM_MP_STATE_INIT_RECEIVED: | |
9602 | break; | |
9603 | default: | |
9604 | return -EINTR; | |
362c698f PB |
9605 | } |
9606 | return 1; | |
9607 | } | |
09cec754 | 9608 | |
5d9bc648 PB |
9609 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
9610 | { | |
56083bdf | 9611 | if (is_guest_mode(vcpu)) |
cb6a32c2 | 9612 | kvm_check_nested_events(vcpu); |
0ad3bed6 | 9613 | |
5d9bc648 PB |
9614 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
9615 | !vcpu->arch.apf.halted); | |
9616 | } | |
9617 | ||
362c698f | 9618 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
9619 | { |
9620 | int r; | |
f656ce01 | 9621 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 9622 | |
f656ce01 | 9623 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
c595ceee | 9624 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 9625 | |
362c698f | 9626 | for (;;) { |
58f800d5 | 9627 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 9628 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 9629 | } else { |
362c698f | 9630 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
9631 | } |
9632 | ||
09cec754 GN |
9633 | if (r <= 0) |
9634 | break; | |
9635 | ||
084071d5 | 9636 | kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); |
09cec754 GN |
9637 | if (kvm_cpu_has_pending_timer(vcpu)) |
9638 | kvm_inject_pending_timer_irqs(vcpu); | |
9639 | ||
782d422b MG |
9640 | if (dm_request_for_irq_injection(vcpu) && |
9641 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
9642 | r = 0; |
9643 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 9644 | ++vcpu->stat.request_irq_exits; |
362c698f | 9645 | break; |
09cec754 | 9646 | } |
af585b92 | 9647 | |
f3020b88 | 9648 | if (__xfer_to_guest_mode_work_pending()) { |
f656ce01 | 9649 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
72c3c0fe TG |
9650 | r = xfer_to_guest_mode_handle_work(vcpu); |
9651 | if (r) | |
9652 | return r; | |
f656ce01 | 9653 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 9654 | } |
b6c7a5dc HB |
9655 | } |
9656 | ||
f656ce01 | 9657 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
9658 | |
9659 | return r; | |
9660 | } | |
9661 | ||
716d51ab GN |
9662 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
9663 | { | |
9664 | int r; | |
60fc3d02 | 9665 | |
716d51ab | 9666 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
0ce97a2b | 9667 | r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab | 9668 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
60fc3d02 | 9669 | return r; |
716d51ab GN |
9670 | } |
9671 | ||
9672 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
9673 | { | |
9674 | BUG_ON(!vcpu->arch.pio.count); | |
9675 | ||
9676 | return complete_emulated_io(vcpu); | |
9677 | } | |
9678 | ||
f78146b0 AK |
9679 | /* |
9680 | * Implements the following, as a state machine: | |
9681 | * | |
9682 | * read: | |
9683 | * for each fragment | |
87da7e66 XG |
9684 | * for each mmio piece in the fragment |
9685 | * write gpa, len | |
9686 | * exit | |
9687 | * copy data | |
f78146b0 AK |
9688 | * execute insn |
9689 | * | |
9690 | * write: | |
9691 | * for each fragment | |
87da7e66 XG |
9692 | * for each mmio piece in the fragment |
9693 | * write gpa, len | |
9694 | * copy data | |
9695 | * exit | |
f78146b0 | 9696 | */ |
716d51ab | 9697 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
9698 | { |
9699 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 9700 | struct kvm_mmio_fragment *frag; |
87da7e66 | 9701 | unsigned len; |
5287f194 | 9702 | |
716d51ab | 9703 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 9704 | |
716d51ab | 9705 | /* Complete previous fragment */ |
87da7e66 XG |
9706 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
9707 | len = min(8u, frag->len); | |
716d51ab | 9708 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
9709 | memcpy(frag->data, run->mmio.data, len); |
9710 | ||
9711 | if (frag->len <= 8) { | |
9712 | /* Switch to the next fragment. */ | |
9713 | frag++; | |
9714 | vcpu->mmio_cur_fragment++; | |
9715 | } else { | |
9716 | /* Go forward to the next mmio piece. */ | |
9717 | frag->data += len; | |
9718 | frag->gpa += len; | |
9719 | frag->len -= len; | |
9720 | } | |
9721 | ||
a08d3b3b | 9722 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 9723 | vcpu->mmio_needed = 0; |
0912c977 PB |
9724 | |
9725 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 9726 | if (vcpu->mmio_is_write) |
716d51ab GN |
9727 | return 1; |
9728 | vcpu->mmio_read_completed = 1; | |
9729 | return complete_emulated_io(vcpu); | |
9730 | } | |
87da7e66 | 9731 | |
716d51ab GN |
9732 | run->exit_reason = KVM_EXIT_MMIO; |
9733 | run->mmio.phys_addr = frag->gpa; | |
9734 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
9735 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
9736 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
9737 | run->mmio.is_write = vcpu->mmio_is_write; |
9738 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
9739 | return 0; | |
5287f194 AK |
9740 | } |
9741 | ||
c9aef3b8 SC |
9742 | static void kvm_save_current_fpu(struct fpu *fpu) |
9743 | { | |
9744 | /* | |
9745 | * If the target FPU state is not resident in the CPU registers, just | |
9746 | * memcpy() from current, else save CPU state directly to the target. | |
9747 | */ | |
9748 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9749 | memcpy(&fpu->state, ¤t->thread.fpu.state, | |
9750 | fpu_kernel_xstate_size); | |
9751 | else | |
9752 | copy_fpregs_to_fpstate(fpu); | |
9753 | } | |
9754 | ||
822f312d SAS |
9755 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
9756 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
9757 | { | |
5f409e20 RR |
9758 | fpregs_lock(); |
9759 | ||
c9aef3b8 SC |
9760 | kvm_save_current_fpu(vcpu->arch.user_fpu); |
9761 | ||
ed02b213 TL |
9762 | /* |
9763 | * Guests with protected state can't have it set by the hypervisor, | |
9764 | * so skip trying to set it. | |
9765 | */ | |
9766 | if (vcpu->arch.guest_fpu) | |
9767 | /* PKRU is separately restored in kvm_x86_ops.run. */ | |
9768 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, | |
9769 | ~XFEATURE_MASK_PKRU); | |
5f409e20 RR |
9770 | |
9771 | fpregs_mark_activate(); | |
9772 | fpregs_unlock(); | |
9773 | ||
822f312d SAS |
9774 | trace_kvm_fpu(1); |
9775 | } | |
9776 | ||
9777 | /* When vcpu_run ends, restore user space FPU context. */ | |
9778 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
9779 | { | |
5f409e20 RR |
9780 | fpregs_lock(); |
9781 | ||
ed02b213 TL |
9782 | /* |
9783 | * Guests with protected state can't have it read by the hypervisor, | |
9784 | * so skip trying to save it. | |
9785 | */ | |
9786 | if (vcpu->arch.guest_fpu) | |
9787 | kvm_save_current_fpu(vcpu->arch.guest_fpu); | |
c9aef3b8 | 9788 | |
d9a710e5 | 9789 | copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); |
5f409e20 RR |
9790 | |
9791 | fpregs_mark_activate(); | |
9792 | fpregs_unlock(); | |
9793 | ||
822f312d SAS |
9794 | ++vcpu->stat.fpu_reload; |
9795 | trace_kvm_fpu(0); | |
9796 | } | |
9797 | ||
1b94f6f8 | 9798 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) |
b6c7a5dc | 9799 | { |
1b94f6f8 | 9800 | struct kvm_run *kvm_run = vcpu->run; |
b6c7a5dc | 9801 | int r; |
b6c7a5dc | 9802 | |
accb757d | 9803 | vcpu_load(vcpu); |
20b7035c | 9804 | kvm_sigset_activate(vcpu); |
15aad3be | 9805 | kvm_run->flags = 0; |
5663d8f9 PX |
9806 | kvm_load_guest_fpu(vcpu); |
9807 | ||
a4535290 | 9808 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
9809 | if (kvm_run->immediate_exit) { |
9810 | r = -EINTR; | |
9811 | goto out; | |
9812 | } | |
b6c7a5dc | 9813 | kvm_vcpu_block(vcpu); |
4fe09bcf JM |
9814 | if (kvm_apic_accept_events(vcpu) < 0) { |
9815 | r = 0; | |
9816 | goto out; | |
9817 | } | |
72875d8a | 9818 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 9819 | r = -EAGAIN; |
a0595000 JS |
9820 | if (signal_pending(current)) { |
9821 | r = -EINTR; | |
1b94f6f8 | 9822 | kvm_run->exit_reason = KVM_EXIT_INTR; |
a0595000 JS |
9823 | ++vcpu->stat.signal_exits; |
9824 | } | |
ac9f6dc0 | 9825 | goto out; |
b6c7a5dc HB |
9826 | } |
9827 | ||
1b94f6f8 | 9828 | if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { |
01643c51 KH |
9829 | r = -EINVAL; |
9830 | goto out; | |
9831 | } | |
9832 | ||
1b94f6f8 | 9833 | if (kvm_run->kvm_dirty_regs) { |
01643c51 KH |
9834 | r = sync_regs(vcpu); |
9835 | if (r != 0) | |
9836 | goto out; | |
9837 | } | |
9838 | ||
b6c7a5dc | 9839 | /* re-sync apic's tpr */ |
35754c98 | 9840 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
9841 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
9842 | r = -EINVAL; | |
9843 | goto out; | |
9844 | } | |
9845 | } | |
b6c7a5dc | 9846 | |
716d51ab GN |
9847 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
9848 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
9849 | vcpu->arch.complete_userspace_io = NULL; | |
9850 | r = cui(vcpu); | |
9851 | if (r <= 0) | |
5663d8f9 | 9852 | goto out; |
716d51ab GN |
9853 | } else |
9854 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 9855 | |
460df4c1 PB |
9856 | if (kvm_run->immediate_exit) |
9857 | r = -EINTR; | |
9858 | else | |
9859 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
9860 | |
9861 | out: | |
5663d8f9 | 9862 | kvm_put_guest_fpu(vcpu); |
1b94f6f8 | 9863 | if (kvm_run->kvm_valid_regs) |
01643c51 | 9864 | store_regs(vcpu); |
f1d86e46 | 9865 | post_kvm_run_save(vcpu); |
20b7035c | 9866 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 9867 | |
accb757d | 9868 | vcpu_put(vcpu); |
b6c7a5dc HB |
9869 | return r; |
9870 | } | |
9871 | ||
01643c51 | 9872 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 9873 | { |
7ae441ea GN |
9874 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
9875 | /* | |
9876 | * We are here if userspace calls get_regs() in the middle of | |
9877 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 9878 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
9879 | * that usually, but some bad designed PV devices (vmware |
9880 | * backdoor interface) need this to work | |
9881 | */ | |
c9b8b07c | 9882 | emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); |
7ae441ea GN |
9883 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
9884 | } | |
de3cd117 SC |
9885 | regs->rax = kvm_rax_read(vcpu); |
9886 | regs->rbx = kvm_rbx_read(vcpu); | |
9887 | regs->rcx = kvm_rcx_read(vcpu); | |
9888 | regs->rdx = kvm_rdx_read(vcpu); | |
9889 | regs->rsi = kvm_rsi_read(vcpu); | |
9890 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 9891 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 9892 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 9893 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
9894 | regs->r8 = kvm_r8_read(vcpu); |
9895 | regs->r9 = kvm_r9_read(vcpu); | |
9896 | regs->r10 = kvm_r10_read(vcpu); | |
9897 | regs->r11 = kvm_r11_read(vcpu); | |
9898 | regs->r12 = kvm_r12_read(vcpu); | |
9899 | regs->r13 = kvm_r13_read(vcpu); | |
9900 | regs->r14 = kvm_r14_read(vcpu); | |
9901 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
9902 | #endif |
9903 | ||
5fdbf976 | 9904 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 9905 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 9906 | } |
b6c7a5dc | 9907 | |
01643c51 KH |
9908 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
9909 | { | |
9910 | vcpu_load(vcpu); | |
9911 | __get_regs(vcpu, regs); | |
1fc9b76b | 9912 | vcpu_put(vcpu); |
b6c7a5dc HB |
9913 | return 0; |
9914 | } | |
9915 | ||
01643c51 | 9916 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 9917 | { |
7ae441ea GN |
9918 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
9919 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
9920 | ||
de3cd117 SC |
9921 | kvm_rax_write(vcpu, regs->rax); |
9922 | kvm_rbx_write(vcpu, regs->rbx); | |
9923 | kvm_rcx_write(vcpu, regs->rcx); | |
9924 | kvm_rdx_write(vcpu, regs->rdx); | |
9925 | kvm_rsi_write(vcpu, regs->rsi); | |
9926 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 9927 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 9928 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 9929 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
9930 | kvm_r8_write(vcpu, regs->r8); |
9931 | kvm_r9_write(vcpu, regs->r9); | |
9932 | kvm_r10_write(vcpu, regs->r10); | |
9933 | kvm_r11_write(vcpu, regs->r11); | |
9934 | kvm_r12_write(vcpu, regs->r12); | |
9935 | kvm_r13_write(vcpu, regs->r13); | |
9936 | kvm_r14_write(vcpu, regs->r14); | |
9937 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
9938 | #endif |
9939 | ||
5fdbf976 | 9940 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 9941 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 9942 | |
b4f14abd JK |
9943 | vcpu->arch.exception.pending = false; |
9944 | ||
3842d135 | 9945 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 9946 | } |
3842d135 | 9947 | |
01643c51 KH |
9948 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
9949 | { | |
9950 | vcpu_load(vcpu); | |
9951 | __set_regs(vcpu, regs); | |
875656fe | 9952 | vcpu_put(vcpu); |
b6c7a5dc HB |
9953 | return 0; |
9954 | } | |
9955 | ||
b6c7a5dc HB |
9956 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
9957 | { | |
9958 | struct kvm_segment cs; | |
9959 | ||
3e6e0aab | 9960 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
9961 | *db = cs.db; |
9962 | *l = cs.l; | |
9963 | } | |
9964 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
9965 | ||
6dba9403 | 9966 | static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 9967 | { |
89a27f4d | 9968 | struct desc_ptr dt; |
b6c7a5dc | 9969 | |
5265713a TL |
9970 | if (vcpu->arch.guest_state_protected) |
9971 | goto skip_protected_regs; | |
9972 | ||
3e6e0aab GT |
9973 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
9974 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
9975 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
9976 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
9977 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
9978 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 9979 | |
3e6e0aab GT |
9980 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
9981 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 9982 | |
b3646477 | 9983 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
89a27f4d GN |
9984 | sregs->idt.limit = dt.size; |
9985 | sregs->idt.base = dt.address; | |
b3646477 | 9986 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
89a27f4d GN |
9987 | sregs->gdt.limit = dt.size; |
9988 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 9989 | |
ad312c7c | 9990 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 9991 | sregs->cr3 = kvm_read_cr3(vcpu); |
5265713a TL |
9992 | |
9993 | skip_protected_regs: | |
9994 | sregs->cr0 = kvm_read_cr0(vcpu); | |
fc78f519 | 9995 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 9996 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 9997 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc | 9998 | sregs->apic_base = kvm_get_apic_base(vcpu); |
6dba9403 | 9999 | } |
b6c7a5dc | 10000 | |
6dba9403 ML |
10001 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
10002 | { | |
10003 | __get_sregs_common(vcpu, sregs); | |
10004 | ||
10005 | if (vcpu->arch.guest_state_protected) | |
10006 | return; | |
b6c7a5dc | 10007 | |
04140b41 | 10008 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
10009 | set_bit(vcpu->arch.interrupt.nr, |
10010 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 10011 | } |
16d7a191 | 10012 | |
6dba9403 ML |
10013 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
10014 | { | |
10015 | int i; | |
10016 | ||
10017 | __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); | |
10018 | ||
10019 | if (vcpu->arch.guest_state_protected) | |
10020 | return; | |
10021 | ||
10022 | if (is_pae_paging(vcpu)) { | |
10023 | for (i = 0 ; i < 4 ; i++) | |
10024 | sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); | |
10025 | sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
10026 | } | |
10027 | } | |
10028 | ||
01643c51 KH |
10029 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
10030 | struct kvm_sregs *sregs) | |
10031 | { | |
10032 | vcpu_load(vcpu); | |
10033 | __get_sregs(vcpu, sregs); | |
bcdec41c | 10034 | vcpu_put(vcpu); |
b6c7a5dc HB |
10035 | return 0; |
10036 | } | |
10037 | ||
62d9f0db MT |
10038 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
10039 | struct kvm_mp_state *mp_state) | |
10040 | { | |
4fe09bcf JM |
10041 | int r; |
10042 | ||
fd232561 | 10043 | vcpu_load(vcpu); |
f958bd23 SC |
10044 | if (kvm_mpx_supported()) |
10045 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 10046 | |
4fe09bcf JM |
10047 | r = kvm_apic_accept_events(vcpu); |
10048 | if (r < 0) | |
10049 | goto out; | |
10050 | r = 0; | |
10051 | ||
647daca2 TL |
10052 | if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || |
10053 | vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && | |
10054 | vcpu->arch.pv.pv_unhalted) | |
6aef266c SV |
10055 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; |
10056 | else | |
10057 | mp_state->mp_state = vcpu->arch.mp_state; | |
10058 | ||
4fe09bcf | 10059 | out: |
f958bd23 SC |
10060 | if (kvm_mpx_supported()) |
10061 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 10062 | vcpu_put(vcpu); |
4fe09bcf | 10063 | return r; |
62d9f0db MT |
10064 | } |
10065 | ||
10066 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
10067 | struct kvm_mp_state *mp_state) | |
10068 | { | |
e83dff5e CD |
10069 | int ret = -EINVAL; |
10070 | ||
10071 | vcpu_load(vcpu); | |
10072 | ||
bce87cce | 10073 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 10074 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 10075 | goto out; |
66450a21 | 10076 | |
27cbe7d6 LA |
10077 | /* |
10078 | * KVM_MP_STATE_INIT_RECEIVED means the processor is in | |
10079 | * INIT state; latched init should be reported using | |
10080 | * KVM_SET_VCPU_EVENTS, so reject it here. | |
10081 | */ | |
10082 | if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && | |
28bf2888 DH |
10083 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
10084 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 10085 | goto out; |
28bf2888 | 10086 | |
66450a21 JK |
10087 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
10088 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
10089 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
10090 | } else | |
10091 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 10092 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
10093 | |
10094 | ret = 0; | |
10095 | out: | |
10096 | vcpu_put(vcpu); | |
10097 | return ret; | |
62d9f0db MT |
10098 | } |
10099 | ||
7f3d35fd KW |
10100 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
10101 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 10102 | { |
c9b8b07c | 10103 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d | 10104 | int ret; |
e01c2426 | 10105 | |
8ec4722d | 10106 | init_emulate_ctxt(vcpu); |
c697518a | 10107 | |
7f3d35fd | 10108 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 10109 | has_error_code, error_code); |
1051778f SC |
10110 | if (ret) { |
10111 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
10112 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
10113 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 10114 | return 0; |
1051778f | 10115 | } |
37817f29 | 10116 | |
9d74191a TY |
10117 | kvm_rip_write(vcpu, ctxt->eip); |
10118 | kvm_set_rflags(vcpu, ctxt->eflags); | |
60fc3d02 | 10119 | return 1; |
37817f29 IE |
10120 | } |
10121 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
10122 | ||
ee69c92b | 10123 | static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 10124 | { |
37b95951 | 10125 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
10126 | /* |
10127 | * When EFER.LME and CR0.PG are set, the processor is in | |
10128 | * 64-bit mode (though maybe in a 32-bit code segment). | |
10129 | * CR4.PAE and EFER.LMA must be set. | |
10130 | */ | |
ee69c92b SC |
10131 | if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) |
10132 | return false; | |
ca29e145 | 10133 | if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) |
c1c35cf7 | 10134 | return false; |
f2981033 LT |
10135 | } else { |
10136 | /* | |
10137 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
10138 | * segment cannot be 64-bit. | |
10139 | */ | |
10140 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
ee69c92b | 10141 | return false; |
f2981033 LT |
10142 | } |
10143 | ||
ee69c92b | 10144 | return kvm_is_valid_cr4(vcpu, sregs->cr4); |
f2981033 LT |
10145 | } |
10146 | ||
6dba9403 ML |
10147 | static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, |
10148 | int *mmu_reset_needed, bool update_pdptrs) | |
b6c7a5dc | 10149 | { |
58cb628d | 10150 | struct msr_data apic_base_msr; |
6dba9403 | 10151 | int idx; |
89a27f4d | 10152 | struct desc_ptr dt; |
b4ef9d4e | 10153 | |
ee69c92b | 10154 | if (!kvm_is_valid_sregs(vcpu, sregs)) |
6dba9403 | 10155 | return -EINVAL; |
f2981033 | 10156 | |
d3802286 JM |
10157 | apic_base_msr.data = sregs->apic_base; |
10158 | apic_base_msr.host_initiated = true; | |
10159 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
6dba9403 | 10160 | return -EINVAL; |
6d1068b3 | 10161 | |
5265713a | 10162 | if (vcpu->arch.guest_state_protected) |
6dba9403 | 10163 | return 0; |
5265713a | 10164 | |
89a27f4d GN |
10165 | dt.size = sregs->idt.limit; |
10166 | dt.address = sregs->idt.base; | |
b3646477 | 10167 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
89a27f4d GN |
10168 | dt.size = sregs->gdt.limit; |
10169 | dt.address = sregs->gdt.base; | |
b3646477 | 10170 | static_call(kvm_x86_set_gdt)(vcpu, &dt); |
b6c7a5dc | 10171 | |
ad312c7c | 10172 | vcpu->arch.cr2 = sregs->cr2; |
6dba9403 | 10173 | *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 10174 | vcpu->arch.cr3 = sregs->cr3; |
cb3c1e2f | 10175 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
b6c7a5dc | 10176 | |
2d3ad1f4 | 10177 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 10178 | |
6dba9403 | 10179 | *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b3646477 | 10180 | static_call(kvm_x86_set_efer)(vcpu, sregs->efer); |
b6c7a5dc | 10181 | |
6dba9403 | 10182 | *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b3646477 | 10183 | static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); |
d7306163 | 10184 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 10185 | |
6dba9403 | 10186 | *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b3646477 | 10187 | static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); |
63f42e02 | 10188 | |
6dba9403 ML |
10189 | if (update_pdptrs) { |
10190 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
10191 | if (is_pae_paging(vcpu)) { | |
10192 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); | |
10193 | *mmu_reset_needed = 1; | |
10194 | } | |
10195 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
7c93be44 | 10196 | } |
b6c7a5dc | 10197 | |
3e6e0aab GT |
10198 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
10199 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
10200 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
10201 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
10202 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
10203 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 10204 | |
3e6e0aab GT |
10205 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
10206 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 10207 | |
5f0269f5 ME |
10208 | update_cr8_intercept(vcpu); |
10209 | ||
9c3e4aab | 10210 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 10211 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 10212 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 10213 | !is_protmode(vcpu)) |
9c3e4aab MT |
10214 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
10215 | ||
6dba9403 ML |
10216 | return 0; |
10217 | } | |
10218 | ||
10219 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
10220 | { | |
10221 | int pending_vec, max_bits; | |
10222 | int mmu_reset_needed = 0; | |
10223 | int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); | |
10224 | ||
10225 | if (ret) | |
10226 | return ret; | |
10227 | ||
10228 | if (mmu_reset_needed) | |
10229 | kvm_mmu_reset_context(vcpu); | |
10230 | ||
5265713a TL |
10231 | max_bits = KVM_NR_INTERRUPTS; |
10232 | pending_vec = find_first_bit( | |
10233 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
6dba9403 | 10234 | |
5265713a TL |
10235 | if (pending_vec < max_bits) { |
10236 | kvm_queue_interrupt(vcpu, pending_vec, false); | |
10237 | pr_debug("Set back pending irq %d\n", pending_vec); | |
6dba9403 | 10238 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5265713a | 10239 | } |
6dba9403 ML |
10240 | return 0; |
10241 | } | |
5265713a | 10242 | |
6dba9403 ML |
10243 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
10244 | { | |
10245 | int mmu_reset_needed = 0; | |
10246 | bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
10247 | bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && | |
10248 | !(sregs2->efer & EFER_LMA); | |
10249 | int i, ret; | |
3842d135 | 10250 | |
6dba9403 ML |
10251 | if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) |
10252 | return -EINVAL; | |
10253 | ||
10254 | if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) | |
10255 | return -EINVAL; | |
10256 | ||
10257 | ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, | |
10258 | &mmu_reset_needed, !valid_pdptrs); | |
10259 | if (ret) | |
10260 | return ret; | |
10261 | ||
10262 | if (valid_pdptrs) { | |
10263 | for (i = 0; i < 4 ; i++) | |
10264 | kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); | |
10265 | ||
10266 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); | |
10267 | mmu_reset_needed = 1; | |
10268 | } | |
10269 | if (mmu_reset_needed) | |
10270 | kvm_mmu_reset_context(vcpu); | |
10271 | return 0; | |
01643c51 KH |
10272 | } |
10273 | ||
10274 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
10275 | struct kvm_sregs *sregs) | |
10276 | { | |
10277 | int ret; | |
10278 | ||
10279 | vcpu_load(vcpu); | |
10280 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
10281 | vcpu_put(vcpu); |
10282 | return ret; | |
b6c7a5dc HB |
10283 | } |
10284 | ||
d0bfb940 JK |
10285 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
10286 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 10287 | { |
355be0b9 | 10288 | unsigned long rflags; |
ae675ef0 | 10289 | int i, r; |
b6c7a5dc | 10290 | |
8d4846b9 TL |
10291 | if (vcpu->arch.guest_state_protected) |
10292 | return -EINVAL; | |
10293 | ||
66b56562 CD |
10294 | vcpu_load(vcpu); |
10295 | ||
4f926bf2 JK |
10296 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
10297 | r = -EBUSY; | |
10298 | if (vcpu->arch.exception.pending) | |
2122ff5e | 10299 | goto out; |
4f926bf2 JK |
10300 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
10301 | kvm_queue_exception(vcpu, DB_VECTOR); | |
10302 | else | |
10303 | kvm_queue_exception(vcpu, BP_VECTOR); | |
10304 | } | |
10305 | ||
91586a3b JK |
10306 | /* |
10307 | * Read rflags as long as potentially injected trace flags are still | |
10308 | * filtered out. | |
10309 | */ | |
10310 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
10311 | |
10312 | vcpu->guest_debug = dbg->control; | |
10313 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
10314 | vcpu->guest_debug = 0; | |
10315 | ||
10316 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
10317 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
10318 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 10319 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
10320 | } else { |
10321 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
10322 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 10323 | } |
c8639010 | 10324 | kvm_update_dr7(vcpu); |
ae675ef0 | 10325 | |
f92653ee | 10326 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
e87e46d5 | 10327 | vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); |
94fe45da | 10328 | |
91586a3b JK |
10329 | /* |
10330 | * Trigger an rflags update that will inject or remove the trace | |
10331 | * flags. | |
10332 | */ | |
10333 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 10334 | |
b3646477 | 10335 | static_call(kvm_x86_update_exception_bitmap)(vcpu); |
b6c7a5dc | 10336 | |
4f926bf2 | 10337 | r = 0; |
d0bfb940 | 10338 | |
2122ff5e | 10339 | out: |
66b56562 | 10340 | vcpu_put(vcpu); |
b6c7a5dc HB |
10341 | return r; |
10342 | } | |
10343 | ||
8b006791 ZX |
10344 | /* |
10345 | * Translate a guest virtual address to a guest physical address. | |
10346 | */ | |
10347 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
10348 | struct kvm_translation *tr) | |
10349 | { | |
10350 | unsigned long vaddr = tr->linear_address; | |
10351 | gpa_t gpa; | |
f656ce01 | 10352 | int idx; |
8b006791 | 10353 | |
1da5b61d CD |
10354 | vcpu_load(vcpu); |
10355 | ||
f656ce01 | 10356 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 10357 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 10358 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
10359 | tr->physical_address = gpa; |
10360 | tr->valid = gpa != UNMAPPED_GVA; | |
10361 | tr->writeable = 1; | |
10362 | tr->usermode = 0; | |
8b006791 | 10363 | |
1da5b61d | 10364 | vcpu_put(vcpu); |
8b006791 ZX |
10365 | return 0; |
10366 | } | |
10367 | ||
d0752060 HB |
10368 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
10369 | { | |
1393123e | 10370 | struct fxregs_state *fxsave; |
d0752060 | 10371 | |
ed02b213 TL |
10372 | if (!vcpu->arch.guest_fpu) |
10373 | return 0; | |
10374 | ||
1393123e | 10375 | vcpu_load(vcpu); |
d0752060 | 10376 | |
b666a4b6 | 10377 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 HB |
10378 | memcpy(fpu->fpr, fxsave->st_space, 128); |
10379 | fpu->fcw = fxsave->cwd; | |
10380 | fpu->fsw = fxsave->swd; | |
10381 | fpu->ftwx = fxsave->twd; | |
10382 | fpu->last_opcode = fxsave->fop; | |
10383 | fpu->last_ip = fxsave->rip; | |
10384 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 10385 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 10386 | |
1393123e | 10387 | vcpu_put(vcpu); |
d0752060 HB |
10388 | return 0; |
10389 | } | |
10390 | ||
10391 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
10392 | { | |
6a96bc7f CD |
10393 | struct fxregs_state *fxsave; |
10394 | ||
ed02b213 TL |
10395 | if (!vcpu->arch.guest_fpu) |
10396 | return 0; | |
10397 | ||
6a96bc7f CD |
10398 | vcpu_load(vcpu); |
10399 | ||
b666a4b6 | 10400 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 | 10401 | |
d0752060 HB |
10402 | memcpy(fxsave->st_space, fpu->fpr, 128); |
10403 | fxsave->cwd = fpu->fcw; | |
10404 | fxsave->swd = fpu->fsw; | |
10405 | fxsave->twd = fpu->ftwx; | |
10406 | fxsave->fop = fpu->last_opcode; | |
10407 | fxsave->rip = fpu->last_ip; | |
10408 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 10409 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 10410 | |
6a96bc7f | 10411 | vcpu_put(vcpu); |
d0752060 HB |
10412 | return 0; |
10413 | } | |
10414 | ||
01643c51 KH |
10415 | static void store_regs(struct kvm_vcpu *vcpu) |
10416 | { | |
10417 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
10418 | ||
10419 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
10420 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
10421 | ||
10422 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
10423 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
10424 | ||
10425 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
10426 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
10427 | vcpu, &vcpu->run->s.regs.events); | |
10428 | } | |
10429 | ||
10430 | static int sync_regs(struct kvm_vcpu *vcpu) | |
10431 | { | |
10432 | if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) | |
10433 | return -EINVAL; | |
10434 | ||
10435 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { | |
10436 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
10437 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
10438 | } | |
10439 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
10440 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
10441 | return -EINVAL; | |
10442 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
10443 | } | |
10444 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
10445 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
10446 | vcpu, &vcpu->run->s.regs.events)) | |
10447 | return -EINVAL; | |
10448 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
10449 | } | |
10450 | ||
10451 | return 0; | |
10452 | } | |
10453 | ||
0ee6a517 | 10454 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 10455 | { |
ed02b213 TL |
10456 | if (!vcpu->arch.guest_fpu) |
10457 | return; | |
10458 | ||
b666a4b6 | 10459 | fpstate_init(&vcpu->arch.guest_fpu->state); |
782511b0 | 10460 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
b666a4b6 | 10461 | vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = |
df1daba7 | 10462 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 10463 | |
2acf923e DC |
10464 | /* |
10465 | * Ensure guest xcr0 is valid for loading | |
10466 | */ | |
d91cab78 | 10467 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 10468 | |
ad312c7c | 10469 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 10470 | } |
d0752060 | 10471 | |
ed02b213 TL |
10472 | void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) |
10473 | { | |
10474 | if (vcpu->arch.guest_fpu) { | |
10475 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
10476 | vcpu->arch.guest_fpu = NULL; | |
10477 | } | |
10478 | } | |
10479 | EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); | |
10480 | ||
897cc38e | 10481 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 10482 | { |
897cc38e SC |
10483 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
10484 | pr_warn_once("kvm: SMP vm created on host with unstable TSC; " | |
10485 | "guest TSC will not be reliable\n"); | |
7f1ea208 | 10486 | |
897cc38e | 10487 | return 0; |
e9b11c17 ZX |
10488 | } |
10489 | ||
e529ef66 | 10490 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 10491 | { |
95a0d01e SC |
10492 | struct page *page; |
10493 | int r; | |
c447e76b | 10494 | |
95a0d01e SC |
10495 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
10496 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
10497 | else | |
10498 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 10499 | |
95a0d01e SC |
10500 | r = kvm_mmu_create(vcpu); |
10501 | if (r < 0) | |
10502 | return r; | |
10503 | ||
10504 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
10505 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
10506 | if (r < 0) | |
10507 | goto fail_mmu_destroy; | |
4e19c36f SS |
10508 | if (kvm_apicv_activated(vcpu->kvm)) |
10509 | vcpu->arch.apicv_active = true; | |
95a0d01e | 10510 | } else |
6e4e3b4d | 10511 | static_branch_inc(&kvm_has_noapic_vcpu); |
95a0d01e SC |
10512 | |
10513 | r = -ENOMEM; | |
10514 | ||
93bb59ca | 10515 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); |
95a0d01e SC |
10516 | if (!page) |
10517 | goto fail_free_lapic; | |
10518 | vcpu->arch.pio_data = page_address(page); | |
10519 | ||
10520 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, | |
10521 | GFP_KERNEL_ACCOUNT); | |
10522 | if (!vcpu->arch.mce_banks) | |
10523 | goto fail_free_pio_data; | |
10524 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
10525 | ||
10526 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
10527 | GFP_KERNEL_ACCOUNT)) | |
10528 | goto fail_free_mce_banks; | |
10529 | ||
c9b8b07c SC |
10530 | if (!alloc_emulate_ctxt(vcpu)) |
10531 | goto free_wbinvd_dirty_mask; | |
10532 | ||
95a0d01e SC |
10533 | vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, |
10534 | GFP_KERNEL_ACCOUNT); | |
10535 | if (!vcpu->arch.user_fpu) { | |
10536 | pr_err("kvm: failed to allocate userspace's fpu\n"); | |
c9b8b07c | 10537 | goto free_emulate_ctxt; |
95a0d01e SC |
10538 | } |
10539 | ||
10540 | vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, | |
10541 | GFP_KERNEL_ACCOUNT); | |
10542 | if (!vcpu->arch.guest_fpu) { | |
10543 | pr_err("kvm: failed to allocate vcpu's fpu\n"); | |
10544 | goto free_user_fpu; | |
10545 | } | |
10546 | fx_init(vcpu); | |
10547 | ||
95a0d01e | 10548 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
a8ac864a | 10549 | vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); |
95a0d01e SC |
10550 | |
10551 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
10552 | ||
10553 | kvm_async_pf_hash_reset(vcpu); | |
10554 | kvm_pmu_init(vcpu); | |
10555 | ||
10556 | vcpu->arch.pending_external_vector = -1; | |
10557 | vcpu->arch.preempted_in_kernel = false; | |
10558 | ||
3c86c0d3 VP |
10559 | #if IS_ENABLED(CONFIG_HYPERV) |
10560 | vcpu->arch.hv_root_tdp = INVALID_PAGE; | |
10561 | #endif | |
10562 | ||
b3646477 | 10563 | r = static_call(kvm_x86_vcpu_create)(vcpu); |
95a0d01e SC |
10564 | if (r) |
10565 | goto free_guest_fpu; | |
e9b11c17 | 10566 | |
0cf9135b | 10567 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 10568 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
19efffa2 | 10569 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 10570 | vcpu_load(vcpu); |
1ab9287a | 10571 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
d28bc9dd | 10572 | kvm_vcpu_reset(vcpu, false); |
e1732991 | 10573 | kvm_init_mmu(vcpu, false); |
e9b11c17 | 10574 | vcpu_put(vcpu); |
ec7660cc | 10575 | return 0; |
95a0d01e SC |
10576 | |
10577 | free_guest_fpu: | |
ed02b213 | 10578 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10579 | free_user_fpu: |
10580 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
c9b8b07c SC |
10581 | free_emulate_ctxt: |
10582 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); | |
95a0d01e SC |
10583 | free_wbinvd_dirty_mask: |
10584 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
10585 | fail_free_mce_banks: | |
10586 | kfree(vcpu->arch.mce_banks); | |
10587 | fail_free_pio_data: | |
10588 | free_page((unsigned long)vcpu->arch.pio_data); | |
10589 | fail_free_lapic: | |
10590 | kvm_free_lapic(vcpu); | |
10591 | fail_mmu_destroy: | |
10592 | kvm_mmu_destroy(vcpu); | |
10593 | return r; | |
e9b11c17 ZX |
10594 | } |
10595 | ||
31928aa5 | 10596 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 10597 | { |
332967a3 | 10598 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 10599 | |
ec7660cc | 10600 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 10601 | return; |
ec7660cc | 10602 | vcpu_load(vcpu); |
0c899c25 | 10603 | kvm_synchronize_tsc(vcpu, 0); |
42897d86 | 10604 | vcpu_put(vcpu); |
2d5ba19b MT |
10605 | |
10606 | /* poll control enabled by default */ | |
10607 | vcpu->arch.msr_kvm_poll_control = 1; | |
10608 | ||
ec7660cc | 10609 | mutex_unlock(&vcpu->mutex); |
42897d86 | 10610 | |
b34de572 WL |
10611 | if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) |
10612 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
10613 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
10614 | } |
10615 | ||
d40ccc62 | 10616 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 10617 | { |
4cbc418a | 10618 | struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; |
95a0d01e | 10619 | int idx; |
344d9588 | 10620 | |
4cbc418a PB |
10621 | kvm_release_pfn(cache->pfn, cache->dirty, cache); |
10622 | ||
50b143e1 | 10623 | kvmclock_reset(vcpu); |
e9b11c17 | 10624 | |
b3646477 | 10625 | static_call(kvm_x86_vcpu_free)(vcpu); |
50b143e1 | 10626 | |
c9b8b07c | 10627 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); |
50b143e1 SC |
10628 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
10629 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
ed02b213 | 10630 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10631 | |
10632 | kvm_hv_vcpu_uninit(vcpu); | |
10633 | kvm_pmu_destroy(vcpu); | |
10634 | kfree(vcpu->arch.mce_banks); | |
10635 | kvm_free_lapic(vcpu); | |
10636 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
10637 | kvm_mmu_destroy(vcpu); | |
10638 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
10639 | free_page((unsigned long)vcpu->arch.pio_data); | |
255cbecf | 10640 | kvfree(vcpu->arch.cpuid_entries); |
95a0d01e | 10641 | if (!lapic_in_kernel(vcpu)) |
6e4e3b4d | 10642 | static_branch_dec(&kvm_has_noapic_vcpu); |
e9b11c17 ZX |
10643 | } |
10644 | ||
d28bc9dd | 10645 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 10646 | { |
b7e31be3 RK |
10647 | kvm_lapic_reset(vcpu, init_event); |
10648 | ||
e69fab5d PB |
10649 | vcpu->arch.hflags = 0; |
10650 | ||
c43203ca | 10651 | vcpu->arch.smi_pending = 0; |
52797bf9 | 10652 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
10653 | atomic_set(&vcpu->arch.nmi_queued, 0); |
10654 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 10655 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
10656 | kvm_clear_interrupt_queue(vcpu); |
10657 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 10658 | |
42dbaa5a | 10659 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 10660 | kvm_update_dr0123(vcpu); |
9a3ecd5e | 10661 | vcpu->arch.dr6 = DR6_ACTIVE_LOW; |
42dbaa5a | 10662 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 10663 | kvm_update_dr7(vcpu); |
42dbaa5a | 10664 | |
1119022c NA |
10665 | vcpu->arch.cr2 = 0; |
10666 | ||
3842d135 | 10667 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2635b5c4 VK |
10668 | vcpu->arch.apf.msr_en_val = 0; |
10669 | vcpu->arch.apf.msr_int_val = 0; | |
c9aaa895 | 10670 | vcpu->arch.st.msr_val = 0; |
3842d135 | 10671 | |
12f9a48f GC |
10672 | kvmclock_reset(vcpu); |
10673 | ||
af585b92 GN |
10674 | kvm_clear_async_pf_completion_queue(vcpu); |
10675 | kvm_async_pf_hash_reset(vcpu); | |
10676 | vcpu->arch.apf.halted = false; | |
3842d135 | 10677 | |
ed02b213 | 10678 | if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { |
a554d207 WL |
10679 | void *mpx_state_buffer; |
10680 | ||
10681 | /* | |
10682 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
10683 | * called with loaded FPU and does not let userspace fix the state. | |
10684 | */ | |
f775b13e RR |
10685 | if (init_event) |
10686 | kvm_put_guest_fpu(vcpu); | |
b666a4b6 | 10687 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10688 | XFEATURE_BNDREGS); |
a554d207 WL |
10689 | if (mpx_state_buffer) |
10690 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
b666a4b6 | 10691 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10692 | XFEATURE_BNDCSR); |
a554d207 WL |
10693 | if (mpx_state_buffer) |
10694 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
10695 | if (init_event) |
10696 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
10697 | } |
10698 | ||
64d60670 | 10699 | if (!init_event) { |
d28bc9dd | 10700 | kvm_pmu_reset(vcpu); |
64d60670 | 10701 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 10702 | |
db2336a8 | 10703 | vcpu->arch.msr_misc_features_enables = 0; |
a554d207 WL |
10704 | |
10705 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; | |
64d60670 | 10706 | } |
f5132b01 | 10707 | |
66f7b72e JS |
10708 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
10709 | vcpu->arch.regs_avail = ~0; | |
10710 | vcpu->arch.regs_dirty = ~0; | |
10711 | ||
a554d207 WL |
10712 | vcpu->arch.ia32_xss = 0; |
10713 | ||
b3646477 | 10714 | static_call(kvm_x86_vcpu_reset)(vcpu, init_event); |
e9b11c17 ZX |
10715 | } |
10716 | ||
2b4a273b | 10717 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
10718 | { |
10719 | struct kvm_segment cs; | |
10720 | ||
10721 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
10722 | cs.selector = vector << 8; | |
10723 | cs.base = vector << 12; | |
10724 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
10725 | kvm_rip_write(vcpu, 0); | |
e9b11c17 | 10726 | } |
647daca2 | 10727 | EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); |
e9b11c17 | 10728 | |
13a34e06 | 10729 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 10730 | { |
ca84d1a2 ZA |
10731 | struct kvm *kvm; |
10732 | struct kvm_vcpu *vcpu; | |
10733 | int i; | |
0dd6a6ed ZA |
10734 | int ret; |
10735 | u64 local_tsc; | |
10736 | u64 max_tsc = 0; | |
10737 | bool stable, backwards_tsc = false; | |
18863bdd | 10738 | |
7e34fbd0 | 10739 | kvm_user_return_msr_cpu_online(); |
b3646477 | 10740 | ret = static_call(kvm_x86_hardware_enable)(); |
0dd6a6ed ZA |
10741 | if (ret != 0) |
10742 | return ret; | |
10743 | ||
4ea1636b | 10744 | local_tsc = rdtsc(); |
b0c39dc6 | 10745 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
10746 | list_for_each_entry(kvm, &vm_list, vm_list) { |
10747 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
10748 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 10749 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10750 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
10751 | backwards_tsc = true; | |
10752 | if (vcpu->arch.last_host_tsc > max_tsc) | |
10753 | max_tsc = vcpu->arch.last_host_tsc; | |
10754 | } | |
10755 | } | |
10756 | } | |
10757 | ||
10758 | /* | |
10759 | * Sometimes, even reliable TSCs go backwards. This happens on | |
10760 | * platforms that reset TSC during suspend or hibernate actions, but | |
10761 | * maintain synchronization. We must compensate. Fortunately, we can | |
10762 | * detect that condition here, which happens early in CPU bringup, | |
10763 | * before any KVM threads can be running. Unfortunately, we can't | |
10764 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
10765 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 10766 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
10767 | * variables that haven't been updated yet. |
10768 | * | |
10769 | * So we simply find the maximum observed TSC above, then record the | |
10770 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
10771 | * the adjustment will be applied. Note that we accumulate | |
10772 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
10773 | * gets a chance to run again. In the event that no KVM threads get a | |
10774 | * chance to run, we will miss the entire elapsed period, as we'll have | |
10775 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
10776 | * loose cycle time. This isn't too big a deal, since the loss will be | |
10777 | * uniform across all VCPUs (not to mention the scenario is extremely | |
10778 | * unlikely). It is possible that a second hibernate recovery happens | |
10779 | * much faster than a first, causing the observed TSC here to be | |
10780 | * smaller; this would require additional padding adjustment, which is | |
10781 | * why we set last_host_tsc to the local tsc observed here. | |
10782 | * | |
10783 | * N.B. - this code below runs only on platforms with reliable TSC, | |
10784 | * as that is the only way backwards_tsc is set above. Also note | |
10785 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
10786 | * have the same delta_cyc adjustment applied if backwards_tsc | |
10787 | * is detected. Note further, this adjustment is only done once, | |
10788 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
10789 | * called multiple times (one for each physical CPU bringup). | |
10790 | * | |
4a969980 | 10791 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
10792 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
10793 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
10794 | * guarantee that they stay in perfect synchronization. | |
10795 | */ | |
10796 | if (backwards_tsc) { | |
10797 | u64 delta_cyc = max_tsc - local_tsc; | |
10798 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 10799 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
10800 | kvm_for_each_vcpu(i, vcpu, kvm) { |
10801 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
10802 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 10803 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10804 | } |
10805 | ||
10806 | /* | |
10807 | * We have to disable TSC offset matching.. if you were | |
10808 | * booting a VM while issuing an S4 host suspend.... | |
10809 | * you may have some problem. Solving this issue is | |
10810 | * left as an exercise to the reader. | |
10811 | */ | |
10812 | kvm->arch.last_tsc_nsec = 0; | |
10813 | kvm->arch.last_tsc_write = 0; | |
10814 | } | |
10815 | ||
10816 | } | |
10817 | return 0; | |
e9b11c17 ZX |
10818 | } |
10819 | ||
13a34e06 | 10820 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 10821 | { |
b3646477 | 10822 | static_call(kvm_x86_hardware_disable)(); |
13a34e06 | 10823 | drop_user_return_notifiers(); |
e9b11c17 ZX |
10824 | } |
10825 | ||
b9904085 | 10826 | int kvm_arch_hardware_setup(void *opaque) |
e9b11c17 | 10827 | { |
d008dfdb | 10828 | struct kvm_x86_init_ops *ops = opaque; |
9e9c3fe4 NA |
10829 | int r; |
10830 | ||
91661989 SC |
10831 | rdmsrl_safe(MSR_EFER, &host_efer); |
10832 | ||
408e9a31 PB |
10833 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
10834 | rdmsrl(MSR_IA32_XSS, host_xss); | |
10835 | ||
d008dfdb | 10836 | r = ops->hardware_setup(); |
9e9c3fe4 NA |
10837 | if (r != 0) |
10838 | return r; | |
10839 | ||
afaf0b2f | 10840 | memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); |
b3646477 | 10841 | kvm_ops_static_call_update(); |
69c6f69a | 10842 | |
408e9a31 PB |
10843 | if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) |
10844 | supported_xss = 0; | |
10845 | ||
139f7425 PB |
10846 | #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) |
10847 | cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); | |
10848 | #undef __kvm_cpu_cap_has | |
b11306b5 | 10849 | |
35181e86 HZ |
10850 | if (kvm_has_tsc_control) { |
10851 | /* | |
10852 | * Make sure the user can only configure tsc_khz values that | |
10853 | * fit into a signed integer. | |
273ba457 | 10854 | * A min value is not calculated because it will always |
35181e86 HZ |
10855 | * be 1 on all machines. |
10856 | */ | |
10857 | u64 max = min(0x7fffffffULL, | |
10858 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
10859 | kvm_max_guest_tsc_khz = max; | |
10860 | ||
ad721883 | 10861 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 10862 | } |
ad721883 | 10863 | |
9e9c3fe4 NA |
10864 | kvm_init_msr_list(); |
10865 | return 0; | |
e9b11c17 ZX |
10866 | } |
10867 | ||
10868 | void kvm_arch_hardware_unsetup(void) | |
10869 | { | |
b3646477 | 10870 | static_call(kvm_x86_hardware_unsetup)(); |
e9b11c17 ZX |
10871 | } |
10872 | ||
b9904085 | 10873 | int kvm_arch_check_processor_compat(void *opaque) |
e9b11c17 | 10874 | { |
f1cdecf5 | 10875 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); |
d008dfdb | 10876 | struct kvm_x86_init_ops *ops = opaque; |
f1cdecf5 SC |
10877 | |
10878 | WARN_ON(!irqs_disabled()); | |
10879 | ||
139f7425 PB |
10880 | if (__cr4_reserved_bits(cpu_has, c) != |
10881 | __cr4_reserved_bits(cpu_has, &boot_cpu_data)) | |
f1cdecf5 SC |
10882 | return -EIO; |
10883 | ||
d008dfdb | 10884 | return ops->check_processor_compatibility(); |
d71ba788 PB |
10885 | } |
10886 | ||
10887 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
10888 | { | |
10889 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
10890 | } | |
10891 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
10892 | ||
10893 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
10894 | { | |
10895 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
10896 | } |
10897 | ||
6e4e3b4d CL |
10898 | __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); |
10899 | EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); | |
54e9818f | 10900 | |
e790d9ef RK |
10901 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
10902 | { | |
b35e5548 LX |
10903 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
10904 | ||
c595ceee | 10905 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
10906 | if (pmu->version && unlikely(pmu->event_count)) { |
10907 | pmu->need_cleanup = true; | |
10908 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
10909 | } | |
b3646477 | 10910 | static_call(kvm_x86_sched_in)(vcpu, cpu); |
e790d9ef RK |
10911 | } |
10912 | ||
562b6b08 SC |
10913 | void kvm_arch_free_vm(struct kvm *kvm) |
10914 | { | |
05f04ae4 | 10915 | kfree(to_kvm_hv(kvm)->hv_pa_pg); |
562b6b08 | 10916 | vfree(kvm); |
e790d9ef RK |
10917 | } |
10918 | ||
562b6b08 | 10919 | |
e08b9637 | 10920 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 10921 | { |
e08b9637 CO |
10922 | if (type) |
10923 | return -EINVAL; | |
10924 | ||
6ef768fa | 10925 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 10926 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
10605204 | 10927 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
1aa9b957 | 10928 | INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); |
4d5c5d0f | 10929 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 10930 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 10931 | |
5550af4d SY |
10932 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
10933 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
10934 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
10935 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
10936 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 10937 | |
038f8c11 | 10938 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 10939 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
10940 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
10941 | ||
8171cd68 | 10942 | kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); |
d828199e | 10943 | pvclock_update_vm_gtod_copy(kvm); |
53f658b3 | 10944 | |
6fbbde9a DS |
10945 | kvm->arch.guest_can_read_msr_platform_info = true; |
10946 | ||
3c86c0d3 VP |
10947 | #if IS_ENABLED(CONFIG_HYPERV) |
10948 | spin_lock_init(&kvm->arch.hv_root_tdp_lock); | |
10949 | kvm->arch.hv_root_tdp = INVALID_PAGE; | |
10950 | #endif | |
10951 | ||
7e44e449 | 10952 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 10953 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 10954 | |
4651fc56 | 10955 | kvm_apicv_init(kvm); |
cbc0236a | 10956 | kvm_hv_init_vm(kvm); |
0eb05bf2 | 10957 | kvm_page_track_init(kvm); |
13d268ca | 10958 | kvm_mmu_init_vm(kvm); |
0eb05bf2 | 10959 | |
b3646477 | 10960 | return static_call(kvm_x86_vm_init)(kvm); |
d19a9cd2 ZX |
10961 | } |
10962 | ||
1aa9b957 JS |
10963 | int kvm_arch_post_init_vm(struct kvm *kvm) |
10964 | { | |
10965 | return kvm_mmu_post_init_vm(kvm); | |
10966 | } | |
10967 | ||
d19a9cd2 ZX |
10968 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
10969 | { | |
ec7660cc | 10970 | vcpu_load(vcpu); |
d19a9cd2 ZX |
10971 | kvm_mmu_unload(vcpu); |
10972 | vcpu_put(vcpu); | |
10973 | } | |
10974 | ||
10975 | static void kvm_free_vcpus(struct kvm *kvm) | |
10976 | { | |
10977 | unsigned int i; | |
988a2cae | 10978 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
10979 | |
10980 | /* | |
10981 | * Unpin any mmu pages first. | |
10982 | */ | |
af585b92 GN |
10983 | kvm_for_each_vcpu(i, vcpu, kvm) { |
10984 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 10985 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 10986 | } |
988a2cae | 10987 | kvm_for_each_vcpu(i, vcpu, kvm) |
4543bdc0 | 10988 | kvm_vcpu_destroy(vcpu); |
988a2cae GN |
10989 | |
10990 | mutex_lock(&kvm->lock); | |
10991 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
10992 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 10993 | |
988a2cae GN |
10994 | atomic_set(&kvm->online_vcpus, 0); |
10995 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
10996 | } |
10997 | ||
ad8ba2cd SY |
10998 | void kvm_arch_sync_events(struct kvm *kvm) |
10999 | { | |
332967a3 | 11000 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 11001 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 11002 | kvm_free_pit(kvm); |
ad8ba2cd SY |
11003 | } |
11004 | ||
ff5a983c PX |
11005 | #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) |
11006 | ||
11007 | /** | |
11008 | * __x86_set_memory_region: Setup KVM internal memory slot | |
11009 | * | |
11010 | * @kvm: the kvm pointer to the VM. | |
11011 | * @id: the slot ID to setup. | |
11012 | * @gpa: the GPA to install the slot (unused when @size == 0). | |
11013 | * @size: the size of the slot. Set to zero to uninstall a slot. | |
11014 | * | |
11015 | * This function helps to setup a KVM internal memory slot. Specify | |
11016 | * @size > 0 to install a new slot, while @size == 0 to uninstall a | |
11017 | * slot. The return code can be one of the following: | |
11018 | * | |
11019 | * HVA: on success (uninstall will return a bogus HVA) | |
11020 | * -errno: on error | |
11021 | * | |
11022 | * The caller should always use IS_ERR() to check the return value | |
11023 | * before use. Note, the KVM internal memory slots are guaranteed to | |
11024 | * remain valid and unchanged until the VM is destroyed, i.e., the | |
11025 | * GPA->HVA translation will not change. However, the HVA is a user | |
11026 | * address, i.e. its accessibility is not guaranteed, and must be | |
11027 | * accessed via __copy_{to,from}_user(). | |
11028 | */ | |
11029 | void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, | |
11030 | u32 size) | |
9da0e4d5 PB |
11031 | { |
11032 | int i, r; | |
3f649ab7 | 11033 | unsigned long hva, old_npages; |
f0d648bd | 11034 | struct kvm_memslots *slots = kvm_memslots(kvm); |
0577d1ab | 11035 | struct kvm_memory_slot *slot; |
9da0e4d5 PB |
11036 | |
11037 | /* Called with kvm->slots_lock held. */ | |
1d8007bd | 11038 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
ff5a983c | 11039 | return ERR_PTR_USR(-EINVAL); |
9da0e4d5 | 11040 | |
f0d648bd PB |
11041 | slot = id_to_memslot(slots, id); |
11042 | if (size) { | |
0577d1ab | 11043 | if (slot && slot->npages) |
ff5a983c | 11044 | return ERR_PTR_USR(-EEXIST); |
f0d648bd PB |
11045 | |
11046 | /* | |
11047 | * MAP_SHARED to prevent internal slot pages from being moved | |
11048 | * by fork()/COW. | |
11049 | */ | |
11050 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
11051 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
11052 | if (IS_ERR((void *)hva)) | |
ff5a983c | 11053 | return (void __user *)hva; |
f0d648bd | 11054 | } else { |
0577d1ab | 11055 | if (!slot || !slot->npages) |
46914534 | 11056 | return NULL; |
f0d648bd | 11057 | |
0577d1ab | 11058 | old_npages = slot->npages; |
b66f9bab | 11059 | hva = slot->userspace_addr; |
f0d648bd PB |
11060 | } |
11061 | ||
9da0e4d5 | 11062 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 11063 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 11064 | |
1d8007bd PB |
11065 | m.slot = id | (i << 16); |
11066 | m.flags = 0; | |
11067 | m.guest_phys_addr = gpa; | |
f0d648bd | 11068 | m.userspace_addr = hva; |
1d8007bd | 11069 | m.memory_size = size; |
9da0e4d5 PB |
11070 | r = __kvm_set_memory_region(kvm, &m); |
11071 | if (r < 0) | |
ff5a983c | 11072 | return ERR_PTR_USR(r); |
9da0e4d5 PB |
11073 | } |
11074 | ||
103c763c | 11075 | if (!size) |
0577d1ab | 11076 | vm_munmap(hva, old_npages * PAGE_SIZE); |
f0d648bd | 11077 | |
ff5a983c | 11078 | return (void __user *)hva; |
9da0e4d5 PB |
11079 | } |
11080 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
11081 | ||
1aa9b957 JS |
11082 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
11083 | { | |
11084 | kvm_mmu_pre_destroy_vm(kvm); | |
11085 | } | |
11086 | ||
d19a9cd2 ZX |
11087 | void kvm_arch_destroy_vm(struct kvm *kvm) |
11088 | { | |
27469d29 AH |
11089 | if (current->mm == kvm->mm) { |
11090 | /* | |
11091 | * Free memory regions allocated on behalf of userspace, | |
11092 | * unless the the memory map has changed due to process exit | |
11093 | * or fd copying. | |
11094 | */ | |
6a3c623b PX |
11095 | mutex_lock(&kvm->slots_lock); |
11096 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
11097 | 0, 0); | |
11098 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
11099 | 0, 0); | |
11100 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
11101 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 11102 | } |
b3646477 | 11103 | static_call_cond(kvm_x86_vm_destroy)(kvm); |
b318e8de | 11104 | kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); |
c761159c PX |
11105 | kvm_pic_destroy(kvm); |
11106 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 11107 | kvm_free_vcpus(kvm); |
af1bae54 | 11108 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 11109 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 11110 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 11111 | kvm_page_track_cleanup(kvm); |
7d6bbebb | 11112 | kvm_xen_destroy_vm(kvm); |
cbc0236a | 11113 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 11114 | } |
0de10343 | 11115 | |
c9b929b3 | 11116 | static void memslot_rmap_free(struct kvm_memory_slot *slot) |
db3fe4eb TY |
11117 | { |
11118 | int i; | |
11119 | ||
d89cc617 | 11120 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
11121 | kvfree(slot->arch.rmap[i]); |
11122 | slot->arch.rmap[i] = NULL; | |
c9b929b3 BG |
11123 | } |
11124 | } | |
e96c81ee | 11125 | |
c9b929b3 BG |
11126 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
11127 | { | |
11128 | int i; | |
11129 | ||
11130 | memslot_rmap_free(slot); | |
d89cc617 | 11131 | |
c9b929b3 | 11132 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
11133 | kvfree(slot->arch.lpage_info[i - 1]); |
11134 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb | 11135 | } |
21ebbeda | 11136 | |
e96c81ee | 11137 | kvm_page_track_free_memslot(slot); |
db3fe4eb TY |
11138 | } |
11139 | ||
56dd1019 BG |
11140 | static int memslot_rmap_alloc(struct kvm_memory_slot *slot, |
11141 | unsigned long npages) | |
11142 | { | |
11143 | const int sz = sizeof(*slot->arch.rmap[0]); | |
11144 | int i; | |
11145 | ||
11146 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { | |
11147 | int level = i + 1; | |
11148 | int lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
11149 | slot->base_gfn, level) + 1; | |
11150 | ||
d501f747 BG |
11151 | WARN_ON(slot->arch.rmap[i]); |
11152 | ||
56dd1019 BG |
11153 | slot->arch.rmap[i] = kvcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); |
11154 | if (!slot->arch.rmap[i]) { | |
11155 | memslot_rmap_free(slot); | |
11156 | return -ENOMEM; | |
11157 | } | |
11158 | } | |
11159 | ||
11160 | return 0; | |
11161 | } | |
11162 | ||
d501f747 BG |
11163 | int alloc_all_memslots_rmaps(struct kvm *kvm) |
11164 | { | |
11165 | struct kvm_memslots *slots; | |
11166 | struct kvm_memory_slot *slot; | |
11167 | int r, i; | |
11168 | ||
11169 | /* | |
11170 | * Check if memslots alreday have rmaps early before acquiring | |
11171 | * the slots_arch_lock below. | |
11172 | */ | |
11173 | if (kvm_memslots_have_rmaps(kvm)) | |
11174 | return 0; | |
11175 | ||
11176 | mutex_lock(&kvm->slots_arch_lock); | |
11177 | ||
11178 | /* | |
11179 | * Read memslots_have_rmaps again, under the slots arch lock, | |
11180 | * before allocating the rmaps | |
11181 | */ | |
11182 | if (kvm_memslots_have_rmaps(kvm)) { | |
11183 | mutex_unlock(&kvm->slots_arch_lock); | |
11184 | return 0; | |
11185 | } | |
11186 | ||
11187 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { | |
11188 | slots = __kvm_memslots(kvm, i); | |
11189 | kvm_for_each_memslot(slot, slots) { | |
11190 | r = memslot_rmap_alloc(slot, slot->npages); | |
11191 | if (r) { | |
11192 | mutex_unlock(&kvm->slots_arch_lock); | |
11193 | return r; | |
11194 | } | |
11195 | } | |
11196 | } | |
11197 | ||
11198 | /* | |
11199 | * Ensure that memslots_have_rmaps becomes true strictly after | |
11200 | * all the rmap pointers are set. | |
11201 | */ | |
11202 | smp_store_release(&kvm->arch.memslots_have_rmaps, true); | |
11203 | mutex_unlock(&kvm->slots_arch_lock); | |
11204 | return 0; | |
11205 | } | |
11206 | ||
a2557408 BG |
11207 | static int kvm_alloc_memslot_metadata(struct kvm *kvm, |
11208 | struct kvm_memory_slot *slot, | |
0dab98b7 | 11209 | unsigned long npages) |
db3fe4eb | 11210 | { |
56dd1019 | 11211 | int i, r; |
db3fe4eb | 11212 | |
edd4fa37 SC |
11213 | /* |
11214 | * Clear out the previous array pointers for the KVM_MR_MOVE case. The | |
11215 | * old arrays will be freed by __kvm_set_memory_region() if installing | |
11216 | * the new memslot is successful. | |
11217 | */ | |
11218 | memset(&slot->arch, 0, sizeof(slot->arch)); | |
11219 | ||
e2209710 | 11220 | if (kvm_memslots_have_rmaps(kvm)) { |
a2557408 BG |
11221 | r = memslot_rmap_alloc(slot, npages); |
11222 | if (r) | |
11223 | return r; | |
11224 | } | |
56dd1019 BG |
11225 | |
11226 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { | |
92f94f1e | 11227 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
11228 | unsigned long ugfn; |
11229 | int lpages; | |
d89cc617 | 11230 | int level = i + 1; |
db3fe4eb TY |
11231 | |
11232 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
11233 | slot->base_gfn, level) + 1; | |
11234 | ||
254272ce | 11235 | linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 11236 | if (!linfo) |
db3fe4eb TY |
11237 | goto out_free; |
11238 | ||
92f94f1e XG |
11239 | slot->arch.lpage_info[i - 1] = linfo; |
11240 | ||
db3fe4eb | 11241 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 11242 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 11243 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 11244 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
11245 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
11246 | /* | |
11247 | * If the gfn and userspace address are not aligned wrt each | |
600087b6 | 11248 | * other, disable large page support for this slot. |
db3fe4eb | 11249 | */ |
600087b6 | 11250 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { |
db3fe4eb TY |
11251 | unsigned long j; |
11252 | ||
11253 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 11254 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
11255 | } |
11256 | } | |
11257 | ||
21ebbeda XG |
11258 | if (kvm_page_track_create_memslot(slot, npages)) |
11259 | goto out_free; | |
11260 | ||
db3fe4eb TY |
11261 | return 0; |
11262 | ||
11263 | out_free: | |
c9b929b3 | 11264 | memslot_rmap_free(slot); |
d89cc617 | 11265 | |
c9b929b3 | 11266 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 11267 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 11268 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
11269 | } |
11270 | return -ENOMEM; | |
11271 | } | |
11272 | ||
15248258 | 11273 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 11274 | { |
91724814 BO |
11275 | struct kvm_vcpu *vcpu; |
11276 | int i; | |
11277 | ||
e6dff7d1 TY |
11278 | /* |
11279 | * memslots->generation has been incremented. | |
11280 | * mmio generation may have reached its maximum value. | |
11281 | */ | |
15248258 | 11282 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
11283 | |
11284 | /* Force re-initialization of steal_time cache */ | |
11285 | kvm_for_each_vcpu(i, vcpu, kvm) | |
11286 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
11287 | } |
11288 | ||
f7784b8e MT |
11289 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
11290 | struct kvm_memory_slot *memslot, | |
09170a49 | 11291 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 11292 | enum kvm_mr_change change) |
0de10343 | 11293 | { |
0dab98b7 | 11294 | if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) |
a2557408 | 11295 | return kvm_alloc_memslot_metadata(kvm, memslot, |
0dab98b7 | 11296 | mem->memory_size >> PAGE_SHIFT); |
f7784b8e MT |
11297 | return 0; |
11298 | } | |
11299 | ||
a85863c2 MS |
11300 | |
11301 | static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) | |
11302 | { | |
11303 | struct kvm_arch *ka = &kvm->arch; | |
11304 | ||
11305 | if (!kvm_x86_ops.cpu_dirty_log_size) | |
11306 | return; | |
11307 | ||
11308 | if ((enable && ++ka->cpu_dirty_logging_count == 1) || | |
11309 | (!enable && --ka->cpu_dirty_logging_count == 0)) | |
11310 | kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); | |
11311 | ||
11312 | WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); | |
11313 | } | |
11314 | ||
88178fd4 | 11315 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
3741679b AY |
11316 | struct kvm_memory_slot *old, |
11317 | struct kvm_memory_slot *new, | |
11318 | enum kvm_mr_change change) | |
88178fd4 | 11319 | { |
a85863c2 MS |
11320 | bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES; |
11321 | ||
3741679b | 11322 | /* |
a85863c2 MS |
11323 | * Update CPU dirty logging if dirty logging is being toggled. This |
11324 | * applies to all operations. | |
3741679b | 11325 | */ |
a85863c2 MS |
11326 | if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES) |
11327 | kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); | |
88178fd4 KH |
11328 | |
11329 | /* | |
a85863c2 | 11330 | * Nothing more to do for RO slots (which can't be dirtied and can't be |
b6e16ae5 | 11331 | * made writable) or CREATE/MOVE/DELETE of a slot. |
88178fd4 | 11332 | * |
b6e16ae5 | 11333 | * For a memslot with dirty logging disabled: |
3741679b AY |
11334 | * CREATE: No dirty mappings will already exist. |
11335 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
11336 | * kvm_arch_flush_shadow_memslot() | |
b6e16ae5 SC |
11337 | * |
11338 | * For a memslot with dirty logging enabled: | |
11339 | * CREATE: No shadow pages exist, thus nothing to write-protect | |
11340 | * and no dirty bits to clear. | |
11341 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
11342 | * kvm_arch_flush_shadow_memslot(). | |
3741679b | 11343 | */ |
3741679b | 11344 | if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) |
88178fd4 | 11345 | return; |
3741679b AY |
11346 | |
11347 | /* | |
52f46079 SC |
11348 | * READONLY and non-flags changes were filtered out above, and the only |
11349 | * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty | |
11350 | * logging isn't being toggled on or off. | |
88178fd4 | 11351 | */ |
52f46079 SC |
11352 | if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES))) |
11353 | return; | |
11354 | ||
b6e16ae5 SC |
11355 | if (!log_dirty_pages) { |
11356 | /* | |
11357 | * Dirty logging tracks sptes in 4k granularity, meaning that | |
11358 | * large sptes have to be split. If live migration succeeds, | |
11359 | * the guest in the source machine will be destroyed and large | |
11360 | * sptes will be created in the destination. However, if the | |
11361 | * guest continues to run in the source machine (for example if | |
11362 | * live migration fails), small sptes will remain around and | |
11363 | * cause bad performance. | |
11364 | * | |
11365 | * Scan sptes if dirty logging has been stopped, dropping those | |
11366 | * which can be collapsed into a single large-page spte. Later | |
11367 | * page faults will create the large-page sptes. | |
11368 | */ | |
3741679b | 11369 | kvm_mmu_zap_collapsible_sptes(kvm, new); |
b6e16ae5 | 11370 | } else { |
89212919 KZ |
11371 | /* |
11372 | * Initially-all-set does not require write protecting any page, | |
11373 | * because they're all assumed to be dirty. | |
11374 | */ | |
11375 | if (kvm_dirty_log_manual_protect_and_init_set(kvm)) | |
11376 | return; | |
a1419f8b | 11377 | |
a018eba5 | 11378 | if (kvm_x86_ops.cpu_dirty_log_size) { |
89212919 KZ |
11379 | kvm_mmu_slot_leaf_clear_dirty(kvm, new); |
11380 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); | |
11381 | } else { | |
11382 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); | |
3c9bd400 | 11383 | } |
88178fd4 KH |
11384 | } |
11385 | } | |
11386 | ||
f7784b8e | 11387 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 11388 | const struct kvm_userspace_memory_region *mem, |
9d4c197c | 11389 | struct kvm_memory_slot *old, |
f36f3f28 | 11390 | const struct kvm_memory_slot *new, |
8482644a | 11391 | enum kvm_mr_change change) |
f7784b8e | 11392 | { |
48c0e4e9 | 11393 | if (!kvm->arch.n_requested_mmu_pages) |
4d66623c WY |
11394 | kvm_mmu_change_mmu_pages(kvm, |
11395 | kvm_mmu_calculate_default_mmu_pages(kvm)); | |
1c91cad4 | 11396 | |
3ea3b7fa | 11397 | /* |
f36f3f28 | 11398 | * FIXME: const-ify all uses of struct kvm_memory_slot. |
c972f3b1 | 11399 | */ |
3741679b | 11400 | kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change); |
21198846 SC |
11401 | |
11402 | /* Free the arrays associated with the old memslot. */ | |
11403 | if (change == KVM_MR_MOVE) | |
e96c81ee | 11404 | kvm_arch_free_memslot(kvm, old); |
0de10343 | 11405 | } |
1d737c8a | 11406 | |
2df72e9b | 11407 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 11408 | { |
7390de1e | 11409 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
11410 | } |
11411 | ||
2df72e9b MT |
11412 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
11413 | struct kvm_memory_slot *slot) | |
11414 | { | |
ae7cd873 | 11415 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
11416 | } |
11417 | ||
e6c67d8c LA |
11418 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
11419 | { | |
11420 | return (is_guest_mode(vcpu) && | |
afaf0b2f | 11421 | kvm_x86_ops.guest_apic_has_interrupt && |
b3646477 | 11422 | static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); |
e6c67d8c LA |
11423 | } |
11424 | ||
5d9bc648 PB |
11425 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
11426 | { | |
11427 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
11428 | return true; | |
11429 | ||
11430 | if (kvm_apic_has_events(vcpu)) | |
11431 | return true; | |
11432 | ||
11433 | if (vcpu->arch.pv.pv_unhalted) | |
11434 | return true; | |
11435 | ||
a5f01f8e WL |
11436 | if (vcpu->arch.exception.pending) |
11437 | return true; | |
11438 | ||
47a66eed Z |
11439 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
11440 | (vcpu->arch.nmi_pending && | |
b3646477 | 11441 | static_call(kvm_x86_nmi_allowed)(vcpu, false))) |
5d9bc648 PB |
11442 | return true; |
11443 | ||
47a66eed | 11444 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
a9fa7cb6 | 11445 | (vcpu->arch.smi_pending && |
b3646477 | 11446 | static_call(kvm_x86_smi_allowed)(vcpu, false))) |
73917739 PB |
11447 | return true; |
11448 | ||
5d9bc648 | 11449 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
11450 | (kvm_cpu_has_interrupt(vcpu) || |
11451 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
11452 | return true; |
11453 | ||
1f4b34f8 AS |
11454 | if (kvm_hv_has_stimer_pending(vcpu)) |
11455 | return true; | |
11456 | ||
d2060bd4 SC |
11457 | if (is_guest_mode(vcpu) && |
11458 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
11459 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
11460 | return true; | |
11461 | ||
5d9bc648 PB |
11462 | return false; |
11463 | } | |
11464 | ||
1d737c8a ZX |
11465 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
11466 | { | |
5d9bc648 | 11467 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 11468 | } |
5736199a | 11469 | |
10dbdf98 | 11470 | bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) |
17e433b5 | 11471 | { |
b3646477 | 11472 | if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) |
52acd22f WL |
11473 | return true; |
11474 | ||
11475 | return false; | |
11476 | } | |
11477 | ||
17e433b5 WL |
11478 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
11479 | { | |
11480 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
11481 | return true; | |
11482 | ||
11483 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
11484 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
11485 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
11486 | return true; | |
11487 | ||
10dbdf98 | 11488 | return kvm_arch_dy_has_pending_interrupt(vcpu); |
17e433b5 WL |
11489 | } |
11490 | ||
199b5763 LM |
11491 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
11492 | { | |
b86bb11e WL |
11493 | if (vcpu->arch.guest_state_protected) |
11494 | return true; | |
11495 | ||
de63ad4c | 11496 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
11497 | } |
11498 | ||
b6d33834 | 11499 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 11500 | { |
b6d33834 | 11501 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 11502 | } |
78646121 GN |
11503 | |
11504 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
11505 | { | |
b3646477 | 11506 | return static_call(kvm_x86_interrupt_allowed)(vcpu, false); |
78646121 | 11507 | } |
229456fc | 11508 | |
82b32774 | 11509 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 11510 | { |
7ed9abfe TL |
11511 | /* Can't read the RIP when guest state is protected, just return 0 */ |
11512 | if (vcpu->arch.guest_state_protected) | |
11513 | return 0; | |
11514 | ||
82b32774 NA |
11515 | if (is_64_bit_mode(vcpu)) |
11516 | return kvm_rip_read(vcpu); | |
11517 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
11518 | kvm_rip_read(vcpu)); | |
11519 | } | |
11520 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 11521 | |
82b32774 NA |
11522 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
11523 | { | |
11524 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
11525 | } |
11526 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
11527 | ||
94fe45da JK |
11528 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
11529 | { | |
11530 | unsigned long rflags; | |
11531 | ||
b3646477 | 11532 | rflags = static_call(kvm_x86_get_rflags)(vcpu); |
94fe45da | 11533 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
c310bac5 | 11534 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
11535 | return rflags; |
11536 | } | |
11537 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
11538 | ||
6addfc42 | 11539 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
11540 | { |
11541 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 11542 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 11543 | rflags |= X86_EFLAGS_TF; |
b3646477 | 11544 | static_call(kvm_x86_set_rflags)(vcpu, rflags); |
6addfc42 PB |
11545 | } |
11546 | ||
11547 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
11548 | { | |
11549 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 11550 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
11551 | } |
11552 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
11553 | ||
56028d08 GN |
11554 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
11555 | { | |
11556 | int r; | |
11557 | ||
44dd3ffa | 11558 | if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || |
f2e10669 | 11559 | work->wakeup_all) |
56028d08 GN |
11560 | return; |
11561 | ||
11562 | r = kvm_mmu_reload(vcpu); | |
11563 | if (unlikely(r)) | |
11564 | return; | |
11565 | ||
44dd3ffa | 11566 | if (!vcpu->arch.mmu->direct_map && |
d8dd54e0 | 11567 | work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) |
fb67e14f XG |
11568 | return; |
11569 | ||
7a02674d | 11570 | kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); |
56028d08 GN |
11571 | } |
11572 | ||
af585b92 GN |
11573 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
11574 | { | |
dd03bcaa PX |
11575 | BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); |
11576 | ||
af585b92 GN |
11577 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); |
11578 | } | |
11579 | ||
11580 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
11581 | { | |
dd03bcaa | 11582 | return (key + 1) & (ASYNC_PF_PER_VCPU - 1); |
af585b92 GN |
11583 | } |
11584 | ||
11585 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11586 | { | |
11587 | u32 key = kvm_async_pf_hash_fn(gfn); | |
11588 | ||
11589 | while (vcpu->arch.apf.gfns[key] != ~0) | |
11590 | key = kvm_async_pf_next_probe(key); | |
11591 | ||
11592 | vcpu->arch.apf.gfns[key] = gfn; | |
11593 | } | |
11594 | ||
11595 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11596 | { | |
11597 | int i; | |
11598 | u32 key = kvm_async_pf_hash_fn(gfn); | |
11599 | ||
dd03bcaa | 11600 | for (i = 0; i < ASYNC_PF_PER_VCPU && |
c7d28c24 XG |
11601 | (vcpu->arch.apf.gfns[key] != gfn && |
11602 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
11603 | key = kvm_async_pf_next_probe(key); |
11604 | ||
11605 | return key; | |
11606 | } | |
11607 | ||
11608 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11609 | { | |
11610 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
11611 | } | |
11612 | ||
11613 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11614 | { | |
11615 | u32 i, j, k; | |
11616 | ||
11617 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
0fd46044 PX |
11618 | |
11619 | if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) | |
11620 | return; | |
11621 | ||
af585b92 GN |
11622 | while (true) { |
11623 | vcpu->arch.apf.gfns[i] = ~0; | |
11624 | do { | |
11625 | j = kvm_async_pf_next_probe(j); | |
11626 | if (vcpu->arch.apf.gfns[j] == ~0) | |
11627 | return; | |
11628 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
11629 | /* | |
11630 | * k lies cyclically in ]i,j] | |
11631 | * | i.k.j | | |
11632 | * |....j i.k.| or |.k..j i...| | |
11633 | */ | |
11634 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
11635 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
11636 | i = j; | |
11637 | } | |
11638 | } | |
11639 | ||
68fd66f1 | 11640 | static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) |
7c90705b | 11641 | { |
68fd66f1 VK |
11642 | u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; |
11643 | ||
11644 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, | |
11645 | sizeof(reason)); | |
11646 | } | |
11647 | ||
11648 | static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) | |
11649 | { | |
2635b5c4 | 11650 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); |
4e335d9e | 11651 | |
2635b5c4 VK |
11652 | return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, |
11653 | &token, offset, sizeof(token)); | |
11654 | } | |
11655 | ||
11656 | static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) | |
11657 | { | |
11658 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); | |
11659 | u32 val; | |
11660 | ||
11661 | if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, | |
11662 | &val, offset, sizeof(val))) | |
11663 | return false; | |
11664 | ||
11665 | return !val; | |
7c90705b GN |
11666 | } |
11667 | ||
1dfdb45e PB |
11668 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
11669 | { | |
11670 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) | |
11671 | return false; | |
11672 | ||
2635b5c4 | 11673 | if (!kvm_pv_async_pf_enabled(vcpu) || |
b3646477 | 11674 | (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) |
1dfdb45e PB |
11675 | return false; |
11676 | ||
11677 | return true; | |
11678 | } | |
11679 | ||
11680 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
11681 | { | |
11682 | if (unlikely(!lapic_in_kernel(vcpu) || | |
11683 | kvm_event_needs_reinjection(vcpu) || | |
11684 | vcpu->arch.exception.pending)) | |
11685 | return false; | |
11686 | ||
11687 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
11688 | return false; | |
11689 | ||
11690 | /* | |
11691 | * If interrupts are off we cannot even use an artificial | |
11692 | * halt state. | |
11693 | */ | |
c300ab9f | 11694 | return kvm_arch_interrupt_allowed(vcpu); |
1dfdb45e PB |
11695 | } |
11696 | ||
2a18b7e7 | 11697 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
11698 | struct kvm_async_pf *work) |
11699 | { | |
6389ee94 AK |
11700 | struct x86_exception fault; |
11701 | ||
736c291c | 11702 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 11703 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 11704 | |
1dfdb45e | 11705 | if (kvm_can_deliver_async_pf(vcpu) && |
68fd66f1 | 11706 | !apf_put_user_notpresent(vcpu)) { |
6389ee94 AK |
11707 | fault.vector = PF_VECTOR; |
11708 | fault.error_code_valid = true; | |
11709 | fault.error_code = 0; | |
11710 | fault.nested_page_fault = false; | |
11711 | fault.address = work->arch.token; | |
adfe20fb | 11712 | fault.async_page_fault = true; |
6389ee94 | 11713 | kvm_inject_page_fault(vcpu, &fault); |
2a18b7e7 | 11714 | return true; |
1dfdb45e PB |
11715 | } else { |
11716 | /* | |
11717 | * It is not possible to deliver a paravirtualized asynchronous | |
11718 | * page fault, but putting the guest in an artificial halt state | |
11719 | * can be beneficial nevertheless: if an interrupt arrives, we | |
11720 | * can deliver it timely and perhaps the guest will schedule | |
11721 | * another process. When the instruction that triggered a page | |
11722 | * fault is retried, hopefully the page will be ready in the host. | |
11723 | */ | |
11724 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2a18b7e7 | 11725 | return false; |
7c90705b | 11726 | } |
af585b92 GN |
11727 | } |
11728 | ||
11729 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
11730 | struct kvm_async_pf *work) | |
11731 | { | |
2635b5c4 VK |
11732 | struct kvm_lapic_irq irq = { |
11733 | .delivery_mode = APIC_DM_FIXED, | |
11734 | .vector = vcpu->arch.apf.vec | |
11735 | }; | |
6389ee94 | 11736 | |
f2e10669 | 11737 | if (work->wakeup_all) |
7c90705b GN |
11738 | work->arch.token = ~0; /* broadcast wakeup */ |
11739 | else | |
11740 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 11741 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 11742 | |
2a18b7e7 VK |
11743 | if ((work->wakeup_all || work->notpresent_injected) && |
11744 | kvm_pv_async_pf_enabled(vcpu) && | |
557a961a VK |
11745 | !apf_put_user_ready(vcpu, work->arch.token)) { |
11746 | vcpu->arch.apf.pageready_pending = true; | |
2635b5c4 | 11747 | kvm_apic_set_irq(vcpu, &irq, NULL); |
557a961a | 11748 | } |
2635b5c4 | 11749 | |
e6d53e3b | 11750 | vcpu->arch.apf.halted = false; |
a4fa1635 | 11751 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
11752 | } |
11753 | ||
557a961a VK |
11754 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) |
11755 | { | |
11756 | kvm_make_request(KVM_REQ_APF_READY, vcpu); | |
11757 | if (!vcpu->arch.apf.pageready_pending) | |
11758 | kvm_vcpu_kick(vcpu); | |
11759 | } | |
11760 | ||
7c0ade6c | 11761 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) |
7c90705b | 11762 | { |
2635b5c4 | 11763 | if (!kvm_pv_async_pf_enabled(vcpu)) |
7c90705b GN |
11764 | return true; |
11765 | else | |
2f15d027 | 11766 | return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); |
af585b92 GN |
11767 | } |
11768 | ||
5544eb9b PB |
11769 | void kvm_arch_start_assignment(struct kvm *kvm) |
11770 | { | |
57ab8794 MT |
11771 | if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) |
11772 | static_call_cond(kvm_x86_start_assignment)(kvm); | |
5544eb9b PB |
11773 | } |
11774 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
11775 | ||
11776 | void kvm_arch_end_assignment(struct kvm *kvm) | |
11777 | { | |
11778 | atomic_dec(&kvm->arch.assigned_device_count); | |
11779 | } | |
11780 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
11781 | ||
11782 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
11783 | { | |
11784 | return atomic_read(&kvm->arch.assigned_device_count); | |
11785 | } | |
11786 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
11787 | ||
e0f0bbc5 AW |
11788 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
11789 | { | |
11790 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
11791 | } | |
11792 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
11793 | ||
11794 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
11795 | { | |
11796 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
11797 | } | |
11798 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
11799 | ||
11800 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
11801 | { | |
11802 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
11803 | } | |
11804 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
11805 | ||
14717e20 AW |
11806 | bool kvm_arch_has_irq_bypass(void) |
11807 | { | |
92735b1b | 11808 | return true; |
14717e20 AW |
11809 | } |
11810 | ||
87276880 FW |
11811 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
11812 | struct irq_bypass_producer *prod) | |
11813 | { | |
11814 | struct kvm_kernel_irqfd *irqfd = | |
11815 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
2edd9cb7 | 11816 | int ret; |
87276880 | 11817 | |
14717e20 | 11818 | irqfd->producer = prod; |
2edd9cb7 | 11819 | kvm_arch_start_assignment(irqfd->kvm); |
b3646477 | 11820 | ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, |
2edd9cb7 ZL |
11821 | prod->irq, irqfd->gsi, 1); |
11822 | ||
11823 | if (ret) | |
11824 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 | 11825 | |
2edd9cb7 | 11826 | return ret; |
87276880 FW |
11827 | } |
11828 | ||
11829 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
11830 | struct irq_bypass_producer *prod) | |
11831 | { | |
11832 | int ret; | |
11833 | struct kvm_kernel_irqfd *irqfd = | |
11834 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
11835 | ||
87276880 FW |
11836 | WARN_ON(irqfd->producer != prod); |
11837 | irqfd->producer = NULL; | |
11838 | ||
11839 | /* | |
11840 | * When producer of consumer is unregistered, we change back to | |
11841 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 11842 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
11843 | * int this case doesn't want to receive the interrupts. |
11844 | */ | |
b3646477 | 11845 | ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); |
87276880 FW |
11846 | if (ret) |
11847 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
11848 | " fails: %d\n", irqfd->consumer.token, ret); | |
2edd9cb7 ZL |
11849 | |
11850 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 FW |
11851 | } |
11852 | ||
11853 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
11854 | uint32_t guest_irq, bool set) | |
11855 | { | |
b3646477 | 11856 | return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); |
87276880 FW |
11857 | } |
11858 | ||
52004014 FW |
11859 | bool kvm_vector_hashing_enabled(void) |
11860 | { | |
11861 | return vector_hashing; | |
11862 | } | |
52004014 | 11863 | |
2d5ba19b MT |
11864 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
11865 | { | |
11866 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
11867 | } | |
11868 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
11869 | ||
841c2be0 ML |
11870 | |
11871 | int kvm_spec_ctrl_test_value(u64 value) | |
6441fa61 | 11872 | { |
841c2be0 ML |
11873 | /* |
11874 | * test that setting IA32_SPEC_CTRL to given value | |
11875 | * is allowed by the host processor | |
11876 | */ | |
6441fa61 | 11877 | |
841c2be0 ML |
11878 | u64 saved_value; |
11879 | unsigned long flags; | |
11880 | int ret = 0; | |
6441fa61 | 11881 | |
841c2be0 | 11882 | local_irq_save(flags); |
6441fa61 | 11883 | |
841c2be0 ML |
11884 | if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) |
11885 | ret = 1; | |
11886 | else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) | |
11887 | ret = 1; | |
11888 | else | |
11889 | wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); | |
6441fa61 | 11890 | |
841c2be0 | 11891 | local_irq_restore(flags); |
6441fa61 | 11892 | |
841c2be0 | 11893 | return ret; |
6441fa61 | 11894 | } |
841c2be0 | 11895 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); |
2d5ba19b | 11896 | |
89786147 MG |
11897 | void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) |
11898 | { | |
11899 | struct x86_exception fault; | |
19cf4b7e PB |
11900 | u32 access = error_code & |
11901 | (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); | |
89786147 MG |
11902 | |
11903 | if (!(error_code & PFERR_PRESENT_MASK) || | |
19cf4b7e | 11904 | vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { |
89786147 MG |
11905 | /* |
11906 | * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page | |
11907 | * tables probably do not match the TLB. Just proceed | |
11908 | * with the error code that the processor gave. | |
11909 | */ | |
11910 | fault.vector = PF_VECTOR; | |
11911 | fault.error_code_valid = true; | |
11912 | fault.error_code = error_code; | |
11913 | fault.nested_page_fault = false; | |
11914 | fault.address = gva; | |
11915 | } | |
11916 | vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); | |
6441fa61 | 11917 | } |
89786147 | 11918 | EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); |
2d5ba19b | 11919 | |
3f3393b3 BM |
11920 | /* |
11921 | * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns | |
11922 | * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value | |
11923 | * indicates whether exit to userspace is needed. | |
11924 | */ | |
11925 | int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, | |
11926 | struct x86_exception *e) | |
11927 | { | |
11928 | if (r == X86EMUL_PROPAGATE_FAULT) { | |
11929 | kvm_inject_emulated_page_fault(vcpu, e); | |
11930 | return 1; | |
11931 | } | |
11932 | ||
11933 | /* | |
11934 | * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED | |
11935 | * while handling a VMX instruction KVM could've handled the request | |
11936 | * correctly by exiting to userspace and performing I/O but there | |
11937 | * doesn't seem to be a real use-case behind such requests, just return | |
11938 | * KVM_EXIT_INTERNAL_ERROR for now. | |
11939 | */ | |
11940 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
11941 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
11942 | vcpu->run->internal.ndata = 0; | |
11943 | ||
11944 | return 0; | |
11945 | } | |
11946 | EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); | |
11947 | ||
9715092f BM |
11948 | int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) |
11949 | { | |
11950 | bool pcid_enabled; | |
11951 | struct x86_exception e; | |
11952 | unsigned i; | |
11953 | unsigned long roots_to_free = 0; | |
11954 | struct { | |
11955 | u64 pcid; | |
11956 | u64 gla; | |
11957 | } operand; | |
11958 | int r; | |
11959 | ||
11960 | r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); | |
11961 | if (r != X86EMUL_CONTINUE) | |
11962 | return kvm_handle_memory_failure(vcpu, r, &e); | |
11963 | ||
11964 | if (operand.pcid >> 12 != 0) { | |
11965 | kvm_inject_gp(vcpu, 0); | |
11966 | return 1; | |
11967 | } | |
11968 | ||
11969 | pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); | |
11970 | ||
11971 | switch (type) { | |
11972 | case INVPCID_TYPE_INDIV_ADDR: | |
11973 | if ((!pcid_enabled && (operand.pcid != 0)) || | |
11974 | is_noncanonical_address(operand.gla, vcpu)) { | |
11975 | kvm_inject_gp(vcpu, 0); | |
11976 | return 1; | |
11977 | } | |
11978 | kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); | |
11979 | return kvm_skip_emulated_instruction(vcpu); | |
11980 | ||
11981 | case INVPCID_TYPE_SINGLE_CTXT: | |
11982 | if (!pcid_enabled && (operand.pcid != 0)) { | |
11983 | kvm_inject_gp(vcpu, 0); | |
11984 | return 1; | |
11985 | } | |
11986 | ||
11987 | if (kvm_get_active_pcid(vcpu) == operand.pcid) { | |
11988 | kvm_mmu_sync_roots(vcpu); | |
11989 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
11990 | } | |
11991 | ||
11992 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
11993 | if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd) | |
11994 | == operand.pcid) | |
11995 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
11996 | ||
11997 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); | |
11998 | /* | |
11999 | * If neither the current cr3 nor any of the prev_roots use the | |
12000 | * given PCID, then nothing needs to be done here because a | |
12001 | * resync will happen anyway before switching to any other CR3. | |
12002 | */ | |
12003 | ||
12004 | return kvm_skip_emulated_instruction(vcpu); | |
12005 | ||
12006 | case INVPCID_TYPE_ALL_NON_GLOBAL: | |
12007 | /* | |
12008 | * Currently, KVM doesn't mark global entries in the shadow | |
12009 | * page tables, so a non-global flush just degenerates to a | |
12010 | * global flush. If needed, we could optimize this later by | |
12011 | * keeping track of global entries in shadow page tables. | |
12012 | */ | |
12013 | ||
12014 | fallthrough; | |
12015 | case INVPCID_TYPE_ALL_INCL_GLOBAL: | |
f66c53b3 | 12016 | kvm_make_request(KVM_REQ_MMU_RELOAD, vcpu); |
9715092f BM |
12017 | return kvm_skip_emulated_instruction(vcpu); |
12018 | ||
12019 | default: | |
12020 | BUG(); /* We have already checked above that type <= 3 */ | |
12021 | } | |
12022 | } | |
12023 | EXPORT_SYMBOL_GPL(kvm_handle_invpcid); | |
12024 | ||
8f423a80 TL |
12025 | static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) |
12026 | { | |
12027 | struct kvm_run *run = vcpu->run; | |
12028 | struct kvm_mmio_fragment *frag; | |
12029 | unsigned int len; | |
12030 | ||
12031 | BUG_ON(!vcpu->mmio_needed); | |
12032 | ||
12033 | /* Complete previous fragment */ | |
12034 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; | |
12035 | len = min(8u, frag->len); | |
12036 | if (!vcpu->mmio_is_write) | |
12037 | memcpy(frag->data, run->mmio.data, len); | |
12038 | ||
12039 | if (frag->len <= 8) { | |
12040 | /* Switch to the next fragment. */ | |
12041 | frag++; | |
12042 | vcpu->mmio_cur_fragment++; | |
12043 | } else { | |
12044 | /* Go forward to the next mmio piece. */ | |
12045 | frag->data += len; | |
12046 | frag->gpa += len; | |
12047 | frag->len -= len; | |
12048 | } | |
12049 | ||
12050 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { | |
12051 | vcpu->mmio_needed = 0; | |
12052 | ||
12053 | // VMG change, at this point, we're always done | |
12054 | // RIP has already been advanced | |
12055 | return 1; | |
12056 | } | |
12057 | ||
12058 | // More MMIO is needed | |
12059 | run->mmio.phys_addr = frag->gpa; | |
12060 | run->mmio.len = min(8u, frag->len); | |
12061 | run->mmio.is_write = vcpu->mmio_is_write; | |
12062 | if (run->mmio.is_write) | |
12063 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); | |
12064 | run->exit_reason = KVM_EXIT_MMIO; | |
12065 | ||
12066 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12067 | ||
12068 | return 0; | |
12069 | } | |
12070 | ||
12071 | int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
12072 | void *data) | |
12073 | { | |
12074 | int handled; | |
12075 | struct kvm_mmio_fragment *frag; | |
12076 | ||
12077 | if (!data) | |
12078 | return -EINVAL; | |
12079 | ||
12080 | handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
12081 | if (handled == bytes) | |
12082 | return 1; | |
12083 | ||
12084 | bytes -= handled; | |
12085 | gpa += handled; | |
12086 | data += handled; | |
12087 | ||
12088 | /*TODO: Check if need to increment number of frags */ | |
12089 | frag = vcpu->mmio_fragments; | |
12090 | vcpu->mmio_nr_fragments = 1; | |
12091 | frag->len = bytes; | |
12092 | frag->gpa = gpa; | |
12093 | frag->data = data; | |
12094 | ||
12095 | vcpu->mmio_needed = 1; | |
12096 | vcpu->mmio_cur_fragment = 0; | |
12097 | ||
12098 | vcpu->run->mmio.phys_addr = gpa; | |
12099 | vcpu->run->mmio.len = min(8u, frag->len); | |
12100 | vcpu->run->mmio.is_write = 1; | |
12101 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); | |
12102 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
12103 | ||
12104 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12105 | ||
12106 | return 0; | |
12107 | } | |
12108 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); | |
12109 | ||
12110 | int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
12111 | void *data) | |
12112 | { | |
12113 | int handled; | |
12114 | struct kvm_mmio_fragment *frag; | |
12115 | ||
12116 | if (!data) | |
12117 | return -EINVAL; | |
12118 | ||
12119 | handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
12120 | if (handled == bytes) | |
12121 | return 1; | |
12122 | ||
12123 | bytes -= handled; | |
12124 | gpa += handled; | |
12125 | data += handled; | |
12126 | ||
12127 | /*TODO: Check if need to increment number of frags */ | |
12128 | frag = vcpu->mmio_fragments; | |
12129 | vcpu->mmio_nr_fragments = 1; | |
12130 | frag->len = bytes; | |
12131 | frag->gpa = gpa; | |
12132 | frag->data = data; | |
12133 | ||
12134 | vcpu->mmio_needed = 1; | |
12135 | vcpu->mmio_cur_fragment = 0; | |
12136 | ||
12137 | vcpu->run->mmio.phys_addr = gpa; | |
12138 | vcpu->run->mmio.len = min(8u, frag->len); | |
12139 | vcpu->run->mmio.is_write = 0; | |
12140 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
12141 | ||
12142 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12143 | ||
12144 | return 0; | |
12145 | } | |
12146 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); | |
12147 | ||
7ed9abfe TL |
12148 | static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) |
12149 | { | |
12150 | memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data, | |
12151 | vcpu->arch.pio.count * vcpu->arch.pio.size); | |
12152 | vcpu->arch.pio.count = 0; | |
12153 | ||
12154 | return 1; | |
12155 | } | |
12156 | ||
12157 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, | |
12158 | unsigned int port, void *data, unsigned int count) | |
12159 | { | |
12160 | int ret; | |
12161 | ||
12162 | ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port, | |
12163 | data, count); | |
12164 | if (ret) | |
12165 | return ret; | |
12166 | ||
12167 | vcpu->arch.pio.count = 0; | |
12168 | ||
12169 | return 0; | |
12170 | } | |
12171 | ||
12172 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, | |
12173 | unsigned int port, void *data, unsigned int count) | |
12174 | { | |
12175 | int ret; | |
12176 | ||
12177 | ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port, | |
12178 | data, count); | |
12179 | if (ret) { | |
12180 | vcpu->arch.pio.count = 0; | |
12181 | } else { | |
12182 | vcpu->arch.guest_ins_data = data; | |
12183 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; | |
12184 | } | |
12185 | ||
12186 | return 0; | |
12187 | } | |
12188 | ||
12189 | int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, | |
12190 | unsigned int port, void *data, unsigned int count, | |
12191 | int in) | |
12192 | { | |
12193 | return in ? kvm_sev_es_ins(vcpu, size, port, data, count) | |
12194 | : kvm_sev_es_outs(vcpu, size, port, data, count); | |
12195 | } | |
12196 | EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); | |
12197 | ||
d95df951 | 12198 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); |
229456fc | 12199 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 12200 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
12201 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
12202 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
12203 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
12204 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 12205 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 12206 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 12207 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 12208 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 12209 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 12210 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 12211 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 12212 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 12213 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 12214 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 12215 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 12216 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
12217 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
12218 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
ab56f8e6 | 12219 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); |
24bbf74c | 12220 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); |
d523ab6b TL |
12221 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); |
12222 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); | |
59e38b58 TL |
12223 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); |
12224 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); |