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Linux 2.6.27-rc1
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Avi Kivity <avi@qumranet.com>
10 * Yaniv Kamay <yaniv@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
edf88417 17#include <linux/kvm_host.h>
313a3dc7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
7837699f 20#include "i8254.h"
37817f29 21#include "tss.h"
313a3dc7 22
18068523 23#include <linux/clocksource.h>
313a3dc7
CO		 24#include <linux/kvm.h>
25#include <linux/fs.h>
26#include <linux/vmalloc.h>
5fb76f9b 27#include <linux/module.h>
0de10343 28#include <linux/mman.h>
2bacc55c 29#include <linux/highmem.h>
043405e1
CO		 30
31#include <asm/uaccess.h>
d825ed0a 32#include <asm/msr.h>
a5f61300 33#include <asm/desc.h>
043405e1 34
313a3dc7 35#define MAX_IO_MSRS 256
a03490ed
CO		 36#define CR0_RESERVED_BITS \
37 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
38 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
39 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
40#define CR4_RESERVED_BITS \
41 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
42 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
43 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
44 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
45
46#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 47/* EFER defaults:
48 * - enable syscall per default because its emulated by KVM
49 * - enable LME and LMA per default on 64 bit KVM
50 */
51#ifdef CONFIG_X86_64
52static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
53#else
54static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
55#endif
313a3dc7 56
ba1389b7
AK		 57#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
58#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 59
674eea0f
AK		 60static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
61 struct kvm_cpuid_entry2 __user *entries);
62
97896d04
ZX		 63struct kvm_x86_ops *kvm_x86_ops;
64
417bc304 65struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 66 { "pf_fixed", VCPU_STAT(pf_fixed) },
67 { "pf_guest", VCPU_STAT(pf_guest) },
68 { "tlb_flush", VCPU_STAT(tlb_flush) },
69 { "invlpg", VCPU_STAT(invlpg) },
70 { "exits", VCPU_STAT(exits) },
71 { "io_exits", VCPU_STAT(io_exits) },
72 { "mmio_exits", VCPU_STAT(mmio_exits) },
73 { "signal_exits", VCPU_STAT(signal_exits) },
74 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 75 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 76 { "halt_exits", VCPU_STAT(halt_exits) },
77 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 78 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 79 { "request_irq", VCPU_STAT(request_irq_exits) },
80 { "irq_exits", VCPU_STAT(irq_exits) },
81 { "host_state_reload", VCPU_STAT(host_state_reload) },
82 { "efer_reload", VCPU_STAT(efer_reload) },
83 { "fpu_reload", VCPU_STAT(fpu_reload) },
84 { "insn_emulation", VCPU_STAT(insn_emulation) },
85 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
4cee5764
AK		 86 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
87 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
88 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
89 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
90 { "mmu_flooded", VM_STAT(mmu_flooded) },
91 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 92 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
0f74a24c 93 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 94 { "largepages", VM_STAT(lpages) },
417bc304
HB		 95 { NULL }
96};
97
98
5fb76f9b
CO		 99unsigned long segment_base(u16 selector)
100{
101 struct descriptor_table gdt;
a5f61300 102 struct desc_struct *d;
5fb76f9b
CO		 103 unsigned long table_base;
104 unsigned long v;
105
106 if (selector == 0)
107 return 0;
108
109 asm("sgdt %0" : "=m"(gdt));
110 table_base = gdt.base;
111
112 if (selector & 4) { /* from ldt */
113 u16 ldt_selector;
114
115 asm("sldt %0" : "=g"(ldt_selector));
116 table_base = segment_base(ldt_selector);
117 }
a5f61300
AK		 118 d = (struct desc_struct *)(table_base + (selector & ~7));
119 v = d->base0 | ((unsigned long)d->base1 << 16) |
120 ((unsigned long)d->base2 << 24);
5fb76f9b 121#ifdef CONFIG_X86_64
a5f61300
AK		 122 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
123 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 124#endif
125 return v;
126}
127EXPORT_SYMBOL_GPL(segment_base);
128
6866b83e
CO		 129u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
130{
131 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 132 return vcpu->arch.apic_base;
6866b83e 133 else
ad312c7c 134 return vcpu->arch.apic_base;
6866b83e
CO		 135}
136EXPORT_SYMBOL_GPL(kvm_get_apic_base);
137
138void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
139{
140 /* TODO: reserve bits check */
141 if (irqchip_in_kernel(vcpu->kvm))
142 kvm_lapic_set_base(vcpu, data);
143 else
ad312c7c 144 vcpu->arch.apic_base = data;
6866b83e
CO		 145}
146EXPORT_SYMBOL_GPL(kvm_set_apic_base);
147
298101da
AK		 148void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
149{
ad312c7c
ZX		 150 WARN_ON(vcpu->arch.exception.pending);
151 vcpu->arch.exception.pending = true;
152 vcpu->arch.exception.has_error_code = false;
153 vcpu->arch.exception.nr = nr;
298101da
AK		 154}
155EXPORT_SYMBOL_GPL(kvm_queue_exception);
156
c3c91fee
AK		 157void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
158 u32 error_code)
159{
160 ++vcpu->stat.pf_guest;
71c4dfaf
JR		 161 if (vcpu->arch.exception.pending) {
162 if (vcpu->arch.exception.nr == PF_VECTOR) {
163 printk(KERN_DEBUG "kvm: inject_page_fault:"
164 " double fault 0x%lx\n", addr);
165 vcpu->arch.exception.nr = DF_VECTOR;
166 vcpu->arch.exception.error_code = 0;
167 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
168 /* triple fault -> shutdown */
169 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
170 }
c3c91fee
AK		 171 return;
172 }
ad312c7c 173 vcpu->arch.cr2 = addr;
c3c91fee
AK		 174 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
175}
176
3419ffc8
SY		 177void kvm_inject_nmi(struct kvm_vcpu *vcpu)
178{
179 vcpu->arch.nmi_pending = 1;
180}
181EXPORT_SYMBOL_GPL(kvm_inject_nmi);
182
298101da
AK		 183void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
184{
ad312c7c
ZX		 185 WARN_ON(vcpu->arch.exception.pending);
186 vcpu->arch.exception.pending = true;
187 vcpu->arch.exception.has_error_code = true;
188 vcpu->arch.exception.nr = nr;
189 vcpu->arch.exception.error_code = error_code;
298101da
AK		 190}
191EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
192
193static void __queue_exception(struct kvm_vcpu *vcpu)
194{
ad312c7c
ZX		 195 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
196 vcpu->arch.exception.has_error_code,
197 vcpu->arch.exception.error_code);
298101da
AK		 198}
199
a03490ed
CO		 200/*
201 * Load the pae pdptrs. Return true is they are all valid.
202 */
203int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
204{
205 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
206 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
207 int i;
208 int ret;
ad312c7c 209 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 210
a03490ed
CO		 211 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
212 offset * sizeof(u64), sizeof(pdpte));
213 if (ret < 0) {
214 ret = 0;
215 goto out;
216 }
217 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
218 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
219 ret = 0;
220 goto out;
221 }
222 }
223 ret = 1;
224
ad312c7c 225 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 226out:
a03490ed
CO		 227
228 return ret;
229}
cc4b6871 230EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 231
d835dfec
AK		 232static bool pdptrs_changed(struct kvm_vcpu *vcpu)
233{
ad312c7c 234 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 235 bool changed = true;
236 int r;
237
238 if (is_long_mode(vcpu) || !is_pae(vcpu))
239 return false;
240
ad312c7c 241 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 242 if (r < 0)
243 goto out;
ad312c7c 244 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 245out:
d835dfec
AK		 246
247 return changed;
248}
249
2d3ad1f4 250void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 251{
252 if (cr0 & CR0_RESERVED_BITS) {
253 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 254 cr0, vcpu->arch.cr0);
c1a5d4f9 255 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 256 return;
257 }
258
259 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
260 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 261 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 262 return;
263 }
264
265 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
266 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
267 "and a clear PE flag\n");
c1a5d4f9 268 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 269 return;
270 }
271
272 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
273#ifdef CONFIG_X86_64
ad312c7c 274 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 275 int cs_db, cs_l;
276
277 if (!is_pae(vcpu)) {
278 printk(KERN_DEBUG "set_cr0: #GP, start paging "
279 "in long mode while PAE is disabled\n");
c1a5d4f9 280 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 281 return;
282 }
283 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
284 if (cs_l) {
285 printk(KERN_DEBUG "set_cr0: #GP, start paging "
286 "in long mode while CS.L == 1\n");
c1a5d4f9 287 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 288 return;
289
290 }
291 } else
292#endif
ad312c7c 293 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 294 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
295 "reserved bits\n");
c1a5d4f9 296 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 297 return;
298 }
299
300 }
301
302 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 303 vcpu->arch.cr0 = cr0;
a03490ed 304
a03490ed 305 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 306 return;
307}
2d3ad1f4 308EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 309
2d3ad1f4 310void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 311{
2d3ad1f4 312 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 313 KVMTRACE_1D(LMSW, vcpu,
314 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
315 handler);
a03490ed 316}
2d3ad1f4 317EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 318
2d3ad1f4 319void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 320{
321 if (cr4 & CR4_RESERVED_BITS) {
322 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 323 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 324 return;
325 }
326
327 if (is_long_mode(vcpu)) {
328 if (!(cr4 & X86_CR4_PAE)) {
329 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
330 "in long mode\n");
c1a5d4f9 331 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 332 return;
333 }
334 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 335 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 336 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 337 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 338 return;
339 }
340
341 if (cr4 & X86_CR4_VMXE) {
342 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 343 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 344 return;
345 }
346 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 347 vcpu->arch.cr4 = cr4;
a03490ed 348 kvm_mmu_reset_context(vcpu);
a03490ed 349}
2d3ad1f4 350EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 351
2d3ad1f4 352void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 353{
ad312c7c 354 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
d835dfec
AK		 355 kvm_mmu_flush_tlb(vcpu);
356 return;
357 }
358
a03490ed
CO		 359 if (is_long_mode(vcpu)) {
360 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
361 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 362 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 363 return;
364 }
365 } else {
366 if (is_pae(vcpu)) {
367 if (cr3 & CR3_PAE_RESERVED_BITS) {
368 printk(KERN_DEBUG
369 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 370 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 371 return;
372 }
373 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
374 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
375 "reserved bits\n");
c1a5d4f9 376 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 377 return;
378 }
379 }
380 /*
381 * We don't check reserved bits in nonpae mode, because
382 * this isn't enforced, and VMware depends on this.
383 */
384 }
385
a03490ed
CO		 386 /*
387 * Does the new cr3 value map to physical memory? (Note, we
388 * catch an invalid cr3 even in real-mode, because it would
389 * cause trouble later on when we turn on paging anyway.)
390 *
391 * A real CPU would silently accept an invalid cr3 and would
392 * attempt to use it - with largely undefined (and often hard
393 * to debug) behavior on the guest side.
394 */
395 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 396 kvm_inject_gp(vcpu, 0);
a03490ed 397 else {
ad312c7c
ZX		 398 vcpu->arch.cr3 = cr3;
399 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 400 }
a03490ed 401}
2d3ad1f4 402EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 403
2d3ad1f4 404void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 405{
406 if (cr8 & CR8_RESERVED_BITS) {
407 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 408 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 409 return;
410 }
411 if (irqchip_in_kernel(vcpu->kvm))
412 kvm_lapic_set_tpr(vcpu, cr8);
413 else
ad312c7c 414 vcpu->arch.cr8 = cr8;
a03490ed 415}
2d3ad1f4 416EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 417
2d3ad1f4 418unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 419{
420 if (irqchip_in_kernel(vcpu->kvm))
421 return kvm_lapic_get_cr8(vcpu);
422 else
ad312c7c 423 return vcpu->arch.cr8;
a03490ed 424}
2d3ad1f4 425EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 426
043405e1
CO		 427/*
428 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
429 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
430 *
431 * This list is modified at module load time to reflect the
432 * capabilities of the host cpu.
433 */
434static u32 msrs_to_save[] = {
435 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
436 MSR_K6_STAR,
437#ifdef CONFIG_X86_64
438 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
439#endif
18068523 440 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
847f0ad8 441 MSR_IA32_PERF_STATUS,
043405e1
CO		 442};
443
444static unsigned num_msrs_to_save;
445
446static u32 emulated_msrs[] = {
447 MSR_IA32_MISC_ENABLE,
448};
449
15c4a640
CO		 450static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
451{
f2b4b7dd 452 if (efer & efer_reserved_bits) {
15c4a640
CO		 453 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
454 efer);
c1a5d4f9 455 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 456 return;
457 }
458
459 if (is_paging(vcpu)
ad312c7c 460 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 461 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 462 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 463 return;
464 }
465
466 kvm_x86_ops->set_efer(vcpu, efer);
467
468 efer &= ~EFER_LMA;
ad312c7c 469 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 470
ad312c7c 471 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 472}
473
f2b4b7dd
JR		 474void kvm_enable_efer_bits(u64 mask)
475{
476 efer_reserved_bits &= ~mask;
477}
478EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
479
480
15c4a640
CO		 481/*
482 * Writes msr value into into the appropriate "register".
483 * Returns 0 on success, non-0 otherwise.
484 * Assumes vcpu_load() was already called.
485 */
486int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
487{
488 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
489}
490
313a3dc7
CO		 491/*
492 * Adapt set_msr() to msr_io()'s calling convention
493 */
494static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
495{
496 return kvm_set_msr(vcpu, index, *data);
497}
498
18068523
GOC		 499static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
500{
501 static int version;
50d0a0f9
GH		 502 struct pvclock_wall_clock wc;
503 struct timespec now, sys, boot;
18068523
GOC		 504
505 if (!wall_clock)
506 return;
507
508 version++;
509
18068523
GOC		 510 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
511
50d0a0f9
GH		 512 /*
513 * The guest calculates current wall clock time by adding
514 * system time (updated by kvm_write_guest_time below) to the
515 * wall clock specified here. guest system time equals host
516 * system time for us, thus we must fill in host boot time here.
517 */
518 now = current_kernel_time();
519 ktime_get_ts(&sys);
520 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
521
522 wc.sec = boot.tv_sec;
523 wc.nsec = boot.tv_nsec;
524 wc.version = version;
18068523
GOC		 525
526 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
527
528 version++;
529 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 530}
531
50d0a0f9
GH		 532static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
533{
534 uint32_t quotient, remainder;
535
536 /* Don't try to replace with do_div(), this one calculates
537 * "(dividend << 32) / divisor" */
538 __asm__ ( "divl %4"
539 : "=a" (quotient), "=d" (remainder)
540 : "0" (0), "1" (dividend), "r" (divisor) );
541 return quotient;
542}
543
544static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
545{
546 uint64_t nsecs = 1000000000LL;
547 int32_t shift = 0;
548 uint64_t tps64;
549 uint32_t tps32;
550
551 tps64 = tsc_khz * 1000LL;
552 while (tps64 > nsecs*2) {
553 tps64 >>= 1;
554 shift--;
555 }
556
557 tps32 = (uint32_t)tps64;
558 while (tps32 <= (uint32_t)nsecs) {
559 tps32 <<= 1;
560 shift++;
561 }
562
563 hv_clock->tsc_shift = shift;
564 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
565
566 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
567 __FUNCTION__, tsc_khz, hv_clock->tsc_shift,
568 hv_clock->tsc_to_system_mul);
569}
570
18068523
GOC		 571static void kvm_write_guest_time(struct kvm_vcpu *v)
572{
573 struct timespec ts;
574 unsigned long flags;
575 struct kvm_vcpu_arch *vcpu = &v->arch;
576 void *shared_kaddr;
577
578 if ((!vcpu->time_page))
579 return;
580
50d0a0f9
GH		 581 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
582 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
583 vcpu->hv_clock_tsc_khz = tsc_khz;
584 }
585
18068523
GOC		 586 /* Keep irq disabled to prevent changes to the clock */
587 local_irq_save(flags);
588 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
589 &vcpu->hv_clock.tsc_timestamp);
590 ktime_get_ts(&ts);
591 local_irq_restore(flags);
592
593 /* With all the info we got, fill in the values */
594
595 vcpu->hv_clock.system_time = ts.tv_nsec +
596 (NSEC_PER_SEC * (u64)ts.tv_sec);
597 /*
598 * The interface expects us to write an even number signaling that the
599 * update is finished. Since the guest won't see the intermediate
50d0a0f9 600 * state, we just increase by 2 at the end.
18068523 601 */
50d0a0f9 602 vcpu->hv_clock.version += 2;
18068523
GOC		 603
604 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
605
606 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 607 sizeof(vcpu->hv_clock));
18068523
GOC		 608
609 kunmap_atomic(shared_kaddr, KM_USER0);
610
611 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
612}
613
9ba075a6
AK		 614static bool msr_mtrr_valid(unsigned msr)
615{
616 switch (msr) {
617 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
618 case MSR_MTRRfix64K_00000:
619 case MSR_MTRRfix16K_80000:
620 case MSR_MTRRfix16K_A0000:
621 case MSR_MTRRfix4K_C0000:
622 case MSR_MTRRfix4K_C8000:
623 case MSR_MTRRfix4K_D0000:
624 case MSR_MTRRfix4K_D8000:
625 case MSR_MTRRfix4K_E0000:
626 case MSR_MTRRfix4K_E8000:
627 case MSR_MTRRfix4K_F0000:
628 case MSR_MTRRfix4K_F8000:
629 case MSR_MTRRdefType:
630 case MSR_IA32_CR_PAT:
631 return true;
632 case 0x2f8:
633 return true;
634 }
635 return false;
636}
637
638static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
639{
640 if (!msr_mtrr_valid(msr))
641 return 1;
642
643 vcpu->arch.mtrr[msr - 0x200] = data;
644 return 0;
645}
15c4a640
CO		 646
647int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
648{
649 switch (msr) {
15c4a640
CO		 650 case MSR_EFER:
651 set_efer(vcpu, data);
652 break;
15c4a640
CO		 653 case MSR_IA32_MC0_STATUS:
654 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 655 __func__, data);
15c4a640
CO		 656 break;
657 case MSR_IA32_MCG_STATUS:
658 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 659 __func__, data);
15c4a640 660 break;
c7ac679c
JR		 661 case MSR_IA32_MCG_CTL:
662 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 663 __func__, data);
c7ac679c 664 break;
15c4a640
CO		 665 case MSR_IA32_UCODE_REV:
666 case MSR_IA32_UCODE_WRITE:
15c4a640 667 break;
9ba075a6
AK		 668 case 0x200 ... 0x2ff:
669 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 670 case MSR_IA32_APICBASE:
671 kvm_set_apic_base(vcpu, data);
672 break;
673 case MSR_IA32_MISC_ENABLE:
ad312c7c 674 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 675 break;
18068523
GOC		 676 case MSR_KVM_WALL_CLOCK:
677 vcpu->kvm->arch.wall_clock = data;
678 kvm_write_wall_clock(vcpu->kvm, data);
679 break;
680 case MSR_KVM_SYSTEM_TIME: {
681 if (vcpu->arch.time_page) {
682 kvm_release_page_dirty(vcpu->arch.time_page);
683 vcpu->arch.time_page = NULL;
684 }
685
686 vcpu->arch.time = data;
687
688 /* we verify if the enable bit is set... */
689 if (!(data & 1))
690 break;
691
692 /* ...but clean it before doing the actual write */
693 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
694
18068523 695 down_read(&current->mm->mmap_sem);
18068523
GOC		 696 vcpu->arch.time_page =
697 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 698 up_read(&current->mm->mmap_sem);
699
700 if (is_error_page(vcpu->arch.time_page)) {
701 kvm_release_page_clean(vcpu->arch.time_page);
702 vcpu->arch.time_page = NULL;
703 }
704
705 kvm_write_guest_time(vcpu);
706 break;
707 }
15c4a640 708 default:
565f1fbd 709 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 710 return 1;
711 }
712 return 0;
713}
714EXPORT_SYMBOL_GPL(kvm_set_msr_common);
715
716
717/*
718 * Reads an msr value (of 'msr_index') into 'pdata'.
719 * Returns 0 on success, non-0 otherwise.
720 * Assumes vcpu_load() was already called.
721 */
722int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
723{
724 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
725}
726
9ba075a6
AK		 727static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
728{
729 if (!msr_mtrr_valid(msr))
730 return 1;
731
732 *pdata = vcpu->arch.mtrr[msr - 0x200];
733 return 0;
734}
735
15c4a640
CO		 736int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
737{
738 u64 data;
739
740 switch (msr) {
741 case 0xc0010010: /* SYSCFG */
742 case 0xc0010015: /* HWCR */
743 case MSR_IA32_PLATFORM_ID:
744 case MSR_IA32_P5_MC_ADDR:
745 case MSR_IA32_P5_MC_TYPE:
746 case MSR_IA32_MC0_CTL:
747 case MSR_IA32_MCG_STATUS:
748 case MSR_IA32_MCG_CAP:
c7ac679c 749 case MSR_IA32_MCG_CTL:
15c4a640
CO		 750 case MSR_IA32_MC0_MISC:
751 case MSR_IA32_MC0_MISC+4:
752 case MSR_IA32_MC0_MISC+8:
753 case MSR_IA32_MC0_MISC+12:
754 case MSR_IA32_MC0_MISC+16:
755 case MSR_IA32_UCODE_REV:
15c4a640 756 case MSR_IA32_EBL_CR_POWERON:
15c4a640
CO		 757 data = 0;
758 break;
9ba075a6
AK		 759 case MSR_MTRRcap:
760 data = 0x500 | KVM_NR_VAR_MTRR;
761 break;
762 case 0x200 ... 0x2ff:
763 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 764 case 0xcd: /* fsb frequency */
765 data = 3;
766 break;
767 case MSR_IA32_APICBASE:
768 data = kvm_get_apic_base(vcpu);
769 break;
770 case MSR_IA32_MISC_ENABLE:
ad312c7c 771 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 772 break;
847f0ad8
AG		 773 case MSR_IA32_PERF_STATUS:
774 /* TSC increment by tick */
775 data = 1000ULL;
776 /* CPU multiplier */
777 data |= (((uint64_t)4ULL) << 40);
778 break;
15c4a640 779 case MSR_EFER:
ad312c7c 780 data = vcpu->arch.shadow_efer;
15c4a640 781 break;
18068523
GOC		 782 case MSR_KVM_WALL_CLOCK:
783 data = vcpu->kvm->arch.wall_clock;
784 break;
785 case MSR_KVM_SYSTEM_TIME:
786 data = vcpu->arch.time;
787 break;
15c4a640
CO		 788 default:
789 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
790 return 1;
791 }
792 *pdata = data;
793 return 0;
794}
795EXPORT_SYMBOL_GPL(kvm_get_msr_common);
796
313a3dc7
CO		 797/*
798 * Read or write a bunch of msrs. All parameters are kernel addresses.
799 *
800 * @return number of msrs set successfully.
801 */
802static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
803 struct kvm_msr_entry *entries,
804 int (*do_msr)(struct kvm_vcpu *vcpu,
805 unsigned index, u64 *data))
806{
807 int i;
808
809 vcpu_load(vcpu);
810
3200f405 811 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 812 for (i = 0; i < msrs->nmsrs; ++i)
813 if (do_msr(vcpu, entries[i].index, &entries[i].data))
814 break;
3200f405 815 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 816
817 vcpu_put(vcpu);
818
819 return i;
820}
821
822/*
823 * Read or write a bunch of msrs. Parameters are user addresses.
824 *
825 * @return number of msrs set successfully.
826 */
827static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
828 int (*do_msr)(struct kvm_vcpu *vcpu,
829 unsigned index, u64 *data),
830 int writeback)
831{
832 struct kvm_msrs msrs;
833 struct kvm_msr_entry *entries;
834 int r, n;
835 unsigned size;
836
837 r = -EFAULT;
838 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
839 goto out;
840
841 r = -E2BIG;
842 if (msrs.nmsrs >= MAX_IO_MSRS)
843 goto out;
844
845 r = -ENOMEM;
846 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
847 entries = vmalloc(size);
848 if (!entries)
849 goto out;
850
851 r = -EFAULT;
852 if (copy_from_user(entries, user_msrs->entries, size))
853 goto out_free;
854
855 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
856 if (r < 0)
857 goto out_free;
858
859 r = -EFAULT;
860 if (writeback && copy_to_user(user_msrs->entries, entries, size))
861 goto out_free;
862
863 r = n;
864
865out_free:
866 vfree(entries);
867out:
868 return r;
869}
870
018d00d2
ZX		 871int kvm_dev_ioctl_check_extension(long ext)
872{
873 int r;
874
875 switch (ext) {
876 case KVM_CAP_IRQCHIP:
877 case KVM_CAP_HLT:
878 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
879 case KVM_CAP_USER_MEMORY:
880 case KVM_CAP_SET_TSS_ADDR:
07716717 881 case KVM_CAP_EXT_CPUID:
18068523 882 case KVM_CAP_CLOCKSOURCE:
7837699f 883 case KVM_CAP_PIT:
a28e4f5a 884 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 885 case KVM_CAP_MP_STATE:
018d00d2
ZX		 886 r = 1;
887 break;
542472b5
LV		 888 case KVM_CAP_COALESCED_MMIO:
889 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
890 break;
774ead3a
AK		 891 case KVM_CAP_VAPIC:
892 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
893 break;
f725230a
AK		 894 case KVM_CAP_NR_VCPUS:
895 r = KVM_MAX_VCPUS;
896 break;
a988b910
AK		 897 case KVM_CAP_NR_MEMSLOTS:
898 r = KVM_MEMORY_SLOTS;
899 break;
2f333bcb
MT		 900 case KVM_CAP_PV_MMU:
901 r = !tdp_enabled;
902 break;
018d00d2
ZX		 903 default:
904 r = 0;
905 break;
906 }
907 return r;
908
909}
910
043405e1
CO		 911long kvm_arch_dev_ioctl(struct file *filp,
912 unsigned int ioctl, unsigned long arg)
913{
914 void __user *argp = (void __user *)arg;
915 long r;
916
917 switch (ioctl) {
918 case KVM_GET_MSR_INDEX_LIST: {
919 struct kvm_msr_list __user *user_msr_list = argp;
920 struct kvm_msr_list msr_list;
921 unsigned n;
922
923 r = -EFAULT;
924 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
925 goto out;
926 n = msr_list.nmsrs;
927 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
928 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
929 goto out;
930 r = -E2BIG;
931 if (n < num_msrs_to_save)
932 goto out;
933 r = -EFAULT;
934 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
935 num_msrs_to_save * sizeof(u32)))
936 goto out;
937 if (copy_to_user(user_msr_list->indices
938 + num_msrs_to_save * sizeof(u32),
939 &emulated_msrs,
940 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
941 goto out;
942 r = 0;
943 break;
944 }
674eea0f
AK		 945 case KVM_GET_SUPPORTED_CPUID: {
946 struct kvm_cpuid2 __user *cpuid_arg = argp;
947 struct kvm_cpuid2 cpuid;
948
949 r = -EFAULT;
950 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
951 goto out;
952 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
953 cpuid_arg->entries);
954 if (r)
955 goto out;
956
957 r = -EFAULT;
958 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
959 goto out;
960 r = 0;
961 break;
962 }
043405e1
CO		 963 default:
964 r = -EINVAL;
965 }
966out:
967 return r;
968}
969
313a3dc7
CO		 970void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
971{
972 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 973 kvm_write_guest_time(vcpu);
313a3dc7
CO		 974}
975
976void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
977{
978 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 979 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 980}
981
07716717 982static int is_efer_nx(void)
313a3dc7
CO		 983{
984 u64 efer;
313a3dc7
CO		 985
986 rdmsrl(MSR_EFER, efer);
07716717
DK		 987 return efer & EFER_NX;
988}
989
990static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
991{
992 int i;
993 struct kvm_cpuid_entry2 *e, *entry;
994
313a3dc7 995 entry = NULL;
ad312c7c
ZX		 996 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
997 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 998 if (e->function == 0x80000001) {
999 entry = e;
1000 break;
1001 }
1002 }
07716717 1003 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1004 entry->edx &= ~(1 << 20);
1005 printk(KERN_INFO "kvm: guest NX capability removed\n");
1006 }
1007}
1008
07716717 1009/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1010static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1011 struct kvm_cpuid *cpuid,
1012 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1013{
1014 int r, i;
1015 struct kvm_cpuid_entry *cpuid_entries;
1016
1017 r = -E2BIG;
1018 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1019 goto out;
1020 r = -ENOMEM;
1021 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1022 if (!cpuid_entries)
1023 goto out;
1024 r = -EFAULT;
1025 if (copy_from_user(cpuid_entries, entries,
1026 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1027 goto out_free;
1028 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1029 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1030 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1031 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1032 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1033 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1034 vcpu->arch.cpuid_entries[i].index = 0;
1035 vcpu->arch.cpuid_entries[i].flags = 0;
1036 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1037 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1038 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1039 }
1040 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1041 cpuid_fix_nx_cap(vcpu);
1042 r = 0;
1043
1044out_free:
1045 vfree(cpuid_entries);
1046out:
1047 return r;
1048}
1049
1050static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1051 struct kvm_cpuid2 *cpuid,
1052 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1053{
1054 int r;
1055
1056 r = -E2BIG;
1057 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1058 goto out;
1059 r = -EFAULT;
ad312c7c 1060 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1061 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1062 goto out;
ad312c7c 1063 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1064 return 0;
1065
1066out:
1067 return r;
1068}
1069
07716717
DK		 1070static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1071 struct kvm_cpuid2 *cpuid,
1072 struct kvm_cpuid_entry2 __user *entries)
1073{
1074 int r;
1075
1076 r = -E2BIG;
ad312c7c 1077 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1078 goto out;
1079 r = -EFAULT;
ad312c7c
ZX		 1080 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1081 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1082 goto out;
1083 return 0;
1084
1085out:
ad312c7c 1086 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1087 return r;
1088}
1089
1090static inline u32 bit(int bitno)
1091{
1092 return 1 << (bitno & 31);
1093}
1094
1095static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1096 u32 index)
1097{
1098 entry->function = function;
1099 entry->index = index;
1100 cpuid_count(entry->function, entry->index,
1101 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1102 entry->flags = 0;
1103}
1104
1105static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1106 u32 index, int *nent, int maxnent)
1107{
1108 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1109 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1110 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1111 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1112 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1113 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1114 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1115 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1116 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1117 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1118 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1119 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1120 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1121 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1122 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1123 bit(X86_FEATURE_PGE) |
1124 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1125 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1126 bit(X86_FEATURE_SYSCALL) |
1127 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1128#ifdef CONFIG_X86_64
1129 bit(X86_FEATURE_LM) |
1130#endif
1131 bit(X86_FEATURE_MMXEXT) |
1132 bit(X86_FEATURE_3DNOWEXT) |
1133 bit(X86_FEATURE_3DNOW);
1134 const u32 kvm_supported_word3_x86_features =
1135 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1136 const u32 kvm_supported_word6_x86_features =
1137 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY);
1138
1139 /* all func 2 cpuid_count() should be called on the same cpu */
1140 get_cpu();
1141 do_cpuid_1_ent(entry, function, index);
1142 ++*nent;
1143
1144 switch (function) {
1145 case 0:
1146 entry->eax = min(entry->eax, (u32)0xb);
1147 break;
1148 case 1:
1149 entry->edx &= kvm_supported_word0_x86_features;
1150 entry->ecx &= kvm_supported_word3_x86_features;
1151 break;
1152 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1153 * may return different values. This forces us to get_cpu() before
1154 * issuing the first command, and also to emulate this annoying behavior
1155 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1156 case 2: {
1157 int t, times = entry->eax & 0xff;
1158
1159 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1160 for (t = 1; t < times && *nent < maxnent; ++t) {
1161 do_cpuid_1_ent(&entry[t], function, 0);
1162 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1163 ++*nent;
1164 }
1165 break;
1166 }
1167 /* function 4 and 0xb have additional index. */
1168 case 4: {
14af3f3c 1169 int i, cache_type;
07716717
DK		 1170
1171 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1172 /* read more entries until cache_type is zero */
14af3f3c
HH		 1173 for (i = 1; *nent < maxnent; ++i) {
1174 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1175 if (!cache_type)
1176 break;
14af3f3c
HH		 1177 do_cpuid_1_ent(&entry[i], function, i);
1178 entry[i].flags |=
07716717
DK		 1179 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1180 ++*nent;
1181 }
1182 break;
1183 }
1184 case 0xb: {
14af3f3c 1185 int i, level_type;
07716717
DK		 1186
1187 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1188 /* read more entries until level_type is zero */
14af3f3c
HH		 1189 for (i = 1; *nent < maxnent; ++i) {
1190 level_type = entry[i - 1].ecx & 0xff;
07716717
DK		 1191 if (!level_type)
1192 break;
14af3f3c
HH		 1193 do_cpuid_1_ent(&entry[i], function, i);
1194 entry[i].flags |=
07716717
DK		 1195 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1196 ++*nent;
1197 }
1198 break;
1199 }
1200 case 0x80000000:
1201 entry->eax = min(entry->eax, 0x8000001a);
1202 break;
1203 case 0x80000001:
1204 entry->edx &= kvm_supported_word1_x86_features;
1205 entry->ecx &= kvm_supported_word6_x86_features;
1206 break;
1207 }
1208 put_cpu();
1209}
1210
674eea0f 1211static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1212 struct kvm_cpuid_entry2 __user *entries)
1213{
1214 struct kvm_cpuid_entry2 *cpuid_entries;
1215 int limit, nent = 0, r = -E2BIG;
1216 u32 func;
1217
1218 if (cpuid->nent < 1)
1219 goto out;
1220 r = -ENOMEM;
1221 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1222 if (!cpuid_entries)
1223 goto out;
1224
1225 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1226 limit = cpuid_entries[0].eax;
1227 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1228 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1229 &nent, cpuid->nent);
1230 r = -E2BIG;
1231 if (nent >= cpuid->nent)
1232 goto out_free;
1233
1234 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1235 limit = cpuid_entries[nent - 1].eax;
1236 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1237 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1238 &nent, cpuid->nent);
1239 r = -EFAULT;
1240 if (copy_to_user(entries, cpuid_entries,
1241 nent * sizeof(struct kvm_cpuid_entry2)))
1242 goto out_free;
1243 cpuid->nent = nent;
1244 r = 0;
1245
1246out_free:
1247 vfree(cpuid_entries);
1248out:
1249 return r;
1250}
1251
313a3dc7
CO		 1252static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1253 struct kvm_lapic_state *s)
1254{
1255 vcpu_load(vcpu);
ad312c7c 1256 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1257 vcpu_put(vcpu);
1258
1259 return 0;
1260}
1261
1262static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1263 struct kvm_lapic_state *s)
1264{
1265 vcpu_load(vcpu);
ad312c7c 1266 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1267 kvm_apic_post_state_restore(vcpu);
1268 vcpu_put(vcpu);
1269
1270 return 0;
1271}
1272
f77bc6a4
ZX		 1273static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1274 struct kvm_interrupt *irq)
1275{
1276 if (irq->irq < 0 || irq->irq >= 256)
1277 return -EINVAL;
1278 if (irqchip_in_kernel(vcpu->kvm))
1279 return -ENXIO;
1280 vcpu_load(vcpu);
1281
ad312c7c
ZX		 1282 set_bit(irq->irq, vcpu->arch.irq_pending);
1283 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1284
1285 vcpu_put(vcpu);
1286
1287 return 0;
1288}
1289
b209749f
AK		 1290static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1291 struct kvm_tpr_access_ctl *tac)
1292{
1293 if (tac->flags)
1294 return -EINVAL;
1295 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1296 return 0;
1297}
1298
313a3dc7
CO		 1299long kvm_arch_vcpu_ioctl(struct file *filp,
1300 unsigned int ioctl, unsigned long arg)
1301{
1302 struct kvm_vcpu *vcpu = filp->private_data;
1303 void __user *argp = (void __user *)arg;
1304 int r;
1305
1306 switch (ioctl) {
1307 case KVM_GET_LAPIC: {
1308 struct kvm_lapic_state lapic;
1309
1310 memset(&lapic, 0, sizeof lapic);
1311 r = kvm_vcpu_ioctl_get_lapic(vcpu, &lapic);
1312 if (r)
1313 goto out;
1314 r = -EFAULT;
1315 if (copy_to_user(argp, &lapic, sizeof lapic))
1316 goto out;
1317 r = 0;
1318 break;
1319 }
1320 case KVM_SET_LAPIC: {
1321 struct kvm_lapic_state lapic;
1322
1323 r = -EFAULT;
1324 if (copy_from_user(&lapic, argp, sizeof lapic))
1325 goto out;
1326 r = kvm_vcpu_ioctl_set_lapic(vcpu, &lapic);;
1327 if (r)
1328 goto out;
1329 r = 0;
1330 break;
1331 }
f77bc6a4
ZX		 1332 case KVM_INTERRUPT: {
1333 struct kvm_interrupt irq;
1334
1335 r = -EFAULT;
1336 if (copy_from_user(&irq, argp, sizeof irq))
1337 goto out;
1338 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1339 if (r)
1340 goto out;
1341 r = 0;
1342 break;
1343 }
313a3dc7
CO		 1344 case KVM_SET_CPUID: {
1345 struct kvm_cpuid __user *cpuid_arg = argp;
1346 struct kvm_cpuid cpuid;
1347
1348 r = -EFAULT;
1349 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1350 goto out;
1351 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1352 if (r)
1353 goto out;
1354 break;
1355 }
07716717
DK		 1356 case KVM_SET_CPUID2: {
1357 struct kvm_cpuid2 __user *cpuid_arg = argp;
1358 struct kvm_cpuid2 cpuid;
1359
1360 r = -EFAULT;
1361 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1362 goto out;
1363 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1364 cpuid_arg->entries);
1365 if (r)
1366 goto out;
1367 break;
1368 }
1369 case KVM_GET_CPUID2: {
1370 struct kvm_cpuid2 __user *cpuid_arg = argp;
1371 struct kvm_cpuid2 cpuid;
1372
1373 r = -EFAULT;
1374 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1375 goto out;
1376 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1377 cpuid_arg->entries);
1378 if (r)
1379 goto out;
1380 r = -EFAULT;
1381 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1382 goto out;
1383 r = 0;
1384 break;
1385 }
313a3dc7
CO		 1386 case KVM_GET_MSRS:
1387 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1388 break;
1389 case KVM_SET_MSRS:
1390 r = msr_io(vcpu, argp, do_set_msr, 0);
1391 break;
b209749f
AK		 1392 case KVM_TPR_ACCESS_REPORTING: {
1393 struct kvm_tpr_access_ctl tac;
1394
1395 r = -EFAULT;
1396 if (copy_from_user(&tac, argp, sizeof tac))
1397 goto out;
1398 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1399 if (r)
1400 goto out;
1401 r = -EFAULT;
1402 if (copy_to_user(argp, &tac, sizeof tac))
1403 goto out;
1404 r = 0;
1405 break;
1406 };
b93463aa
AK		 1407 case KVM_SET_VAPIC_ADDR: {
1408 struct kvm_vapic_addr va;
1409
1410 r = -EINVAL;
1411 if (!irqchip_in_kernel(vcpu->kvm))
1412 goto out;
1413 r = -EFAULT;
1414 if (copy_from_user(&va, argp, sizeof va))
1415 goto out;
1416 r = 0;
1417 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1418 break;
1419 }
313a3dc7
CO		 1420 default:
1421 r = -EINVAL;
1422 }
1423out:
1424 return r;
1425}
1426
1fe779f8
CO		 1427static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1428{
1429 int ret;
1430
1431 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1432 return -1;
1433 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1434 return ret;
1435}
1436
1437static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1438 u32 kvm_nr_mmu_pages)
1439{
1440 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1441 return -EINVAL;
1442
72dc67a6 1443 down_write(&kvm->slots_lock);
1fe779f8
CO		 1444
1445 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1446 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1447
72dc67a6 1448 up_write(&kvm->slots_lock);
1fe779f8
CO		 1449 return 0;
1450}
1451
1452static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1453{
f05e70ac 1454 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1455}
1456
e9f85cde
ZX		 1457gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1458{
1459 int i;
1460 struct kvm_mem_alias *alias;
1461
d69fb81f
ZX		 1462 for (i = 0; i < kvm->arch.naliases; ++i) {
1463 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1464 if (gfn >= alias->base_gfn
1465 && gfn < alias->base_gfn + alias->npages)
1466 return alias->target_gfn + gfn - alias->base_gfn;
1467 }
1468 return gfn;
1469}
1470
1fe779f8
CO		 1471/*
1472 * Set a new alias region. Aliases map a portion of physical memory into
1473 * another portion. This is useful for memory windows, for example the PC
1474 * VGA region.
1475 */
1476static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1477 struct kvm_memory_alias *alias)
1478{
1479 int r, n;
1480 struct kvm_mem_alias *p;
1481
1482 r = -EINVAL;
1483 /* General sanity checks */
1484 if (alias->memory_size & (PAGE_SIZE - 1))
1485 goto out;
1486 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1487 goto out;
1488 if (alias->slot >= KVM_ALIAS_SLOTS)
1489 goto out;
1490 if (alias->guest_phys_addr + alias->memory_size
1491 < alias->guest_phys_addr)
1492 goto out;
1493 if (alias->target_phys_addr + alias->memory_size
1494 < alias->target_phys_addr)
1495 goto out;
1496
72dc67a6 1497 down_write(&kvm->slots_lock);
1fe779f8 1498
d69fb81f 1499 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1500 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1501 p->npages = alias->memory_size >> PAGE_SHIFT;
1502 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1503
1504 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1505 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1506 break;
d69fb81f 1507 kvm->arch.naliases = n;
1fe779f8
CO		 1508
1509 kvm_mmu_zap_all(kvm);
1510
72dc67a6 1511 up_write(&kvm->slots_lock);
1fe779f8
CO		 1512
1513 return 0;
1514
1515out:
1516 return r;
1517}
1518
1519static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1520{
1521 int r;
1522
1523 r = 0;
1524 switch (chip->chip_id) {
1525 case KVM_IRQCHIP_PIC_MASTER:
1526 memcpy(&chip->chip.pic,
1527 &pic_irqchip(kvm)->pics[0],
1528 sizeof(struct kvm_pic_state));
1529 break;
1530 case KVM_IRQCHIP_PIC_SLAVE:
1531 memcpy(&chip->chip.pic,
1532 &pic_irqchip(kvm)->pics[1],
1533 sizeof(struct kvm_pic_state));
1534 break;
1535 case KVM_IRQCHIP_IOAPIC:
1536 memcpy(&chip->chip.ioapic,
1537 ioapic_irqchip(kvm),
1538 sizeof(struct kvm_ioapic_state));
1539 break;
1540 default:
1541 r = -EINVAL;
1542 break;
1543 }
1544 return r;
1545}
1546
1547static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1548{
1549 int r;
1550
1551 r = 0;
1552 switch (chip->chip_id) {
1553 case KVM_IRQCHIP_PIC_MASTER:
1554 memcpy(&pic_irqchip(kvm)->pics[0],
1555 &chip->chip.pic,
1556 sizeof(struct kvm_pic_state));
1557 break;
1558 case KVM_IRQCHIP_PIC_SLAVE:
1559 memcpy(&pic_irqchip(kvm)->pics[1],
1560 &chip->chip.pic,
1561 sizeof(struct kvm_pic_state));
1562 break;
1563 case KVM_IRQCHIP_IOAPIC:
1564 memcpy(ioapic_irqchip(kvm),
1565 &chip->chip.ioapic,
1566 sizeof(struct kvm_ioapic_state));
1567 break;
1568 default:
1569 r = -EINVAL;
1570 break;
1571 }
1572 kvm_pic_update_irq(pic_irqchip(kvm));
1573 return r;
1574}
1575
e0f63cb9
SY		 1576static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1577{
1578 int r = 0;
1579
1580 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1581 return r;
1582}
1583
1584static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1585{
1586 int r = 0;
1587
1588 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1589 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1590 return r;
1591}
1592
5bb064dc
ZX		 1593/*
1594 * Get (and clear) the dirty memory log for a memory slot.
1595 */
1596int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1597 struct kvm_dirty_log *log)
1598{
1599 int r;
1600 int n;
1601 struct kvm_memory_slot *memslot;
1602 int is_dirty = 0;
1603
72dc67a6 1604 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1605
1606 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1607 if (r)
1608 goto out;
1609
1610 /* If nothing is dirty, don't bother messing with page tables. */
1611 if (is_dirty) {
1612 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1613 kvm_flush_remote_tlbs(kvm);
1614 memslot = &kvm->memslots[log->slot];
1615 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1616 memset(memslot->dirty_bitmap, 0, n);
1617 }
1618 r = 0;
1619out:
72dc67a6 1620 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1621 return r;
1622}
1623
1fe779f8
CO		 1624long kvm_arch_vm_ioctl(struct file *filp,
1625 unsigned int ioctl, unsigned long arg)
1626{
1627 struct kvm *kvm = filp->private_data;
1628 void __user *argp = (void __user *)arg;
1629 int r = -EINVAL;
1630
1631 switch (ioctl) {
1632 case KVM_SET_TSS_ADDR:
1633 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1634 if (r < 0)
1635 goto out;
1636 break;
1637 case KVM_SET_MEMORY_REGION: {
1638 struct kvm_memory_region kvm_mem;
1639 struct kvm_userspace_memory_region kvm_userspace_mem;
1640
1641 r = -EFAULT;
1642 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1643 goto out;
1644 kvm_userspace_mem.slot = kvm_mem.slot;
1645 kvm_userspace_mem.flags = kvm_mem.flags;
1646 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1647 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1648 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1649 if (r)
1650 goto out;
1651 break;
1652 }
1653 case KVM_SET_NR_MMU_PAGES:
1654 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1655 if (r)
1656 goto out;
1657 break;
1658 case KVM_GET_NR_MMU_PAGES:
1659 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1660 break;
1661 case KVM_SET_MEMORY_ALIAS: {
1662 struct kvm_memory_alias alias;
1663
1664 r = -EFAULT;
1665 if (copy_from_user(&alias, argp, sizeof alias))
1666 goto out;
1667 r = kvm_vm_ioctl_set_memory_alias(kvm, &alias);
1668 if (r)
1669 goto out;
1670 break;
1671 }
1672 case KVM_CREATE_IRQCHIP:
1673 r = -ENOMEM;
d7deeeb0
ZX		 1674 kvm->arch.vpic = kvm_create_pic(kvm);
1675 if (kvm->arch.vpic) {
1fe779f8
CO		 1676 r = kvm_ioapic_init(kvm);
1677 if (r) {
d7deeeb0
ZX		 1678 kfree(kvm->arch.vpic);
1679 kvm->arch.vpic = NULL;
1fe779f8
CO		 1680 goto out;
1681 }
1682 } else
1683 goto out;
1684 break;
7837699f
SY		 1685 case KVM_CREATE_PIT:
1686 r = -ENOMEM;
1687 kvm->arch.vpit = kvm_create_pit(kvm);
1688 if (kvm->arch.vpit)
1689 r = 0;
1690 break;
1fe779f8
CO		 1691 case KVM_IRQ_LINE: {
1692 struct kvm_irq_level irq_event;
1693
1694 r = -EFAULT;
1695 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1696 goto out;
1697 if (irqchip_in_kernel(kvm)) {
1698 mutex_lock(&kvm->lock);
1699 if (irq_event.irq < 16)
1700 kvm_pic_set_irq(pic_irqchip(kvm),
1701 irq_event.irq,
1702 irq_event.level);
d7deeeb0 1703 kvm_ioapic_set_irq(kvm->arch.vioapic,
1fe779f8
CO		 1704 irq_event.irq,
1705 irq_event.level);
1706 mutex_unlock(&kvm->lock);
1707 r = 0;
1708 }
1709 break;
1710 }
1711 case KVM_GET_IRQCHIP: {
1712 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1713 struct kvm_irqchip chip;
1714
1715 r = -EFAULT;
1716 if (copy_from_user(&chip, argp, sizeof chip))
1717 goto out;
1718 r = -ENXIO;
1719 if (!irqchip_in_kernel(kvm))
1720 goto out;
1721 r = kvm_vm_ioctl_get_irqchip(kvm, &chip);
1722 if (r)
1723 goto out;
1724 r = -EFAULT;
1725 if (copy_to_user(argp, &chip, sizeof chip))
1726 goto out;
1727 r = 0;
1728 break;
1729 }
1730 case KVM_SET_IRQCHIP: {
1731 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1732 struct kvm_irqchip chip;
1733
1734 r = -EFAULT;
1735 if (copy_from_user(&chip, argp, sizeof chip))
1736 goto out;
1737 r = -ENXIO;
1738 if (!irqchip_in_kernel(kvm))
1739 goto out;
1740 r = kvm_vm_ioctl_set_irqchip(kvm, &chip);
1741 if (r)
1742 goto out;
1743 r = 0;
1744 break;
1745 }
e0f63cb9
SY		 1746 case KVM_GET_PIT: {
1747 struct kvm_pit_state ps;
1748 r = -EFAULT;
1749 if (copy_from_user(&ps, argp, sizeof ps))
1750 goto out;
1751 r = -ENXIO;
1752 if (!kvm->arch.vpit)
1753 goto out;
1754 r = kvm_vm_ioctl_get_pit(kvm, &ps);
1755 if (r)
1756 goto out;
1757 r = -EFAULT;
1758 if (copy_to_user(argp, &ps, sizeof ps))
1759 goto out;
1760 r = 0;
1761 break;
1762 }
1763 case KVM_SET_PIT: {
1764 struct kvm_pit_state ps;
1765 r = -EFAULT;
1766 if (copy_from_user(&ps, argp, sizeof ps))
1767 goto out;
1768 r = -ENXIO;
1769 if (!kvm->arch.vpit)
1770 goto out;
1771 r = kvm_vm_ioctl_set_pit(kvm, &ps);
1772 if (r)
1773 goto out;
1774 r = 0;
1775 break;
1776 }
1fe779f8
CO		 1777 default:
1778 ;
1779 }
1780out:
1781 return r;
1782}
1783
a16b043c 1784static void kvm_init_msr_list(void)
043405e1
CO		 1785{
1786 u32 dummy[2];
1787 unsigned i, j;
1788
1789 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1790 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1791 continue;
1792 if (j < i)
1793 msrs_to_save[j] = msrs_to_save[i];
1794 j++;
1795 }
1796 num_msrs_to_save = j;
1797}
1798
bbd9b64e
CO		 1799/*
1800 * Only apic need an MMIO device hook, so shortcut now..
1801 */
1802static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1803 gpa_t addr, int len,
1804 int is_write)
bbd9b64e
CO		 1805{
1806 struct kvm_io_device *dev;
1807
ad312c7c
ZX		 1808 if (vcpu->arch.apic) {
1809 dev = &vcpu->arch.apic->dev;
92760499 1810 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 1811 return dev;
1812 }
1813 return NULL;
1814}
1815
1816
1817static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1818 gpa_t addr, int len,
1819 int is_write)
bbd9b64e
CO		 1820{
1821 struct kvm_io_device *dev;
1822
92760499 1823 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 1824 if (dev == NULL)
92760499
LV		 1825 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
1826 is_write);
bbd9b64e
CO		 1827 return dev;
1828}
1829
1830int emulator_read_std(unsigned long addr,
1831 void *val,
1832 unsigned int bytes,
1833 struct kvm_vcpu *vcpu)
1834{
1835 void *data = val;
10589a46 1836 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 1837
1838 while (bytes) {
ad312c7c 1839 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1840 unsigned offset = addr & (PAGE_SIZE-1);
1841 unsigned tocopy = min(bytes, (unsigned)PAGE_SIZE - offset);
1842 int ret;
1843
10589a46
MT		 1844 if (gpa == UNMAPPED_GVA) {
1845 r = X86EMUL_PROPAGATE_FAULT;
1846 goto out;
1847 }
bbd9b64e 1848 ret = kvm_read_guest(vcpu->kvm, gpa, data, tocopy);
10589a46
MT		 1849 if (ret < 0) {
1850 r = X86EMUL_UNHANDLEABLE;
1851 goto out;
1852 }
bbd9b64e
CO		 1853
1854 bytes -= tocopy;
1855 data += tocopy;
1856 addr += tocopy;
1857 }
10589a46 1858out:
10589a46 1859 return r;
bbd9b64e
CO		 1860}
1861EXPORT_SYMBOL_GPL(emulator_read_std);
1862
bbd9b64e
CO		 1863static int emulator_read_emulated(unsigned long addr,
1864 void *val,
1865 unsigned int bytes,
1866 struct kvm_vcpu *vcpu)
1867{
1868 struct kvm_io_device *mmio_dev;
1869 gpa_t gpa;
1870
1871 if (vcpu->mmio_read_completed) {
1872 memcpy(val, vcpu->mmio_data, bytes);
1873 vcpu->mmio_read_completed = 0;
1874 return X86EMUL_CONTINUE;
1875 }
1876
ad312c7c 1877 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1878
1879 /* For APIC access vmexit */
1880 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1881 goto mmio;
1882
1883 if (emulator_read_std(addr, val, bytes, vcpu)
1884 == X86EMUL_CONTINUE)
1885 return X86EMUL_CONTINUE;
1886 if (gpa == UNMAPPED_GVA)
1887 return X86EMUL_PROPAGATE_FAULT;
1888
1889mmio:
1890 /*
1891 * Is this MMIO handled locally?
1892 */
10589a46 1893 mutex_lock(&vcpu->kvm->lock);
92760499 1894 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 1895 if (mmio_dev) {
1896 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 1897 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1898 return X86EMUL_CONTINUE;
1899 }
10589a46 1900 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1901
1902 vcpu->mmio_needed = 1;
1903 vcpu->mmio_phys_addr = gpa;
1904 vcpu->mmio_size = bytes;
1905 vcpu->mmio_is_write = 0;
1906
1907 return X86EMUL_UNHANDLEABLE;
1908}
1909
3200f405 1910int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 1911 const void *val, int bytes)
bbd9b64e
CO		 1912{
1913 int ret;
1914
1915 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 1916 if (ret < 0)
bbd9b64e
CO		 1917 return 0;
1918 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
1919 return 1;
1920}
1921
1922static int emulator_write_emulated_onepage(unsigned long addr,
1923 const void *val,
1924 unsigned int bytes,
1925 struct kvm_vcpu *vcpu)
1926{
1927 struct kvm_io_device *mmio_dev;
10589a46
MT		 1928 gpa_t gpa;
1929
10589a46 1930 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1931
1932 if (gpa == UNMAPPED_GVA) {
c3c91fee 1933 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 1934 return X86EMUL_PROPAGATE_FAULT;
1935 }
1936
1937 /* For APIC access vmexit */
1938 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1939 goto mmio;
1940
1941 if (emulator_write_phys(vcpu, gpa, val, bytes))
1942 return X86EMUL_CONTINUE;
1943
1944mmio:
1945 /*
1946 * Is this MMIO handled locally?
1947 */
10589a46 1948 mutex_lock(&vcpu->kvm->lock);
92760499 1949 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 1950 if (mmio_dev) {
1951 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 1952 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1953 return X86EMUL_CONTINUE;
1954 }
10589a46 1955 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1956
1957 vcpu->mmio_needed = 1;
1958 vcpu->mmio_phys_addr = gpa;
1959 vcpu->mmio_size = bytes;
1960 vcpu->mmio_is_write = 1;
1961 memcpy(vcpu->mmio_data, val, bytes);
1962
1963 return X86EMUL_CONTINUE;
1964}
1965
1966int emulator_write_emulated(unsigned long addr,
1967 const void *val,
1968 unsigned int bytes,
1969 struct kvm_vcpu *vcpu)
1970{
1971 /* Crossing a page boundary? */
1972 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
1973 int rc, now;
1974
1975 now = -addr & ~PAGE_MASK;
1976 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
1977 if (rc != X86EMUL_CONTINUE)
1978 return rc;
1979 addr += now;
1980 val += now;
1981 bytes -= now;
1982 }
1983 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
1984}
1985EXPORT_SYMBOL_GPL(emulator_write_emulated);
1986
1987static int emulator_cmpxchg_emulated(unsigned long addr,
1988 const void *old,
1989 const void *new,
1990 unsigned int bytes,
1991 struct kvm_vcpu *vcpu)
1992{
1993 static int reported;
1994
1995 if (!reported) {
1996 reported = 1;
1997 printk(KERN_WARNING "kvm: emulating exchange as write\n");
1998 }
2bacc55c
MT		 1999#ifndef CONFIG_X86_64
2000 /* guests cmpxchg8b have to be emulated atomically */
2001 if (bytes == 8) {
10589a46 2002 gpa_t gpa;
2bacc55c 2003 struct page *page;
c0b49b0d 2004 char *kaddr;
2bacc55c
MT		 2005 u64 val;
2006
10589a46
MT		 2007 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2008
2bacc55c
MT		 2009 if (gpa == UNMAPPED_GVA ||
2010 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2011 goto emul_write;
2012
2013 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2014 goto emul_write;
2015
2016 val = *(u64 *)new;
72dc67a6
IE		 2017
2018 down_read(&current->mm->mmap_sem);
2bacc55c 2019 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 2020 up_read(&current->mm->mmap_sem);
2021
c0b49b0d
AM		 2022 kaddr = kmap_atomic(page, KM_USER0);
2023 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2024 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2025 kvm_release_page_dirty(page);
2026 }
3200f405 2027emul_write:
2bacc55c
MT		 2028#endif
2029
bbd9b64e
CO		 2030 return emulator_write_emulated(addr, new, bytes, vcpu);
2031}
2032
2033static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2034{
2035 return kvm_x86_ops->get_segment_base(vcpu, seg);
2036}
2037
2038int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2039{
2040 return X86EMUL_CONTINUE;
2041}
2042
2043int emulate_clts(struct kvm_vcpu *vcpu)
2044{
54e445ca 2045 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2046 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2047 return X86EMUL_CONTINUE;
2048}
2049
2050int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2051{
2052 struct kvm_vcpu *vcpu = ctxt->vcpu;
2053
2054 switch (dr) {
2055 case 0 ... 3:
2056 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2057 return X86EMUL_CONTINUE;
2058 default:
b8688d51 2059 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2060 return X86EMUL_UNHANDLEABLE;
2061 }
2062}
2063
2064int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2065{
2066 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2067 int exception;
2068
2069 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2070 if (exception) {
2071 /* FIXME: better handling */
2072 return X86EMUL_UNHANDLEABLE;
2073 }
2074 return X86EMUL_CONTINUE;
2075}
2076
2077void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2078{
bbd9b64e 2079 u8 opcodes[4];
ad312c7c 2080 unsigned long rip = vcpu->arch.rip;
bbd9b64e
CO		 2081 unsigned long rip_linear;
2082
f76c710d 2083 if (!printk_ratelimit())
bbd9b64e
CO		 2084 return;
2085
25be4608
GC		 2086 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2087
bbd9b64e
CO		 2088 emulator_read_std(rip_linear, (void *)opcodes, 4, vcpu);
2089
2090 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2091 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2092}
2093EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2094
14af3f3c 2095static struct x86_emulate_ops emulate_ops = {
bbd9b64e 2096 .read_std = emulator_read_std,
bbd9b64e
CO		 2097 .read_emulated = emulator_read_emulated,
2098 .write_emulated = emulator_write_emulated,
2099 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2100};
2101
2102int emulate_instruction(struct kvm_vcpu *vcpu,
2103 struct kvm_run *run,
2104 unsigned long cr2,
2105 u16 error_code,
571008da 2106 int emulation_type)
bbd9b64e
CO		 2107{
2108 int r;
571008da 2109 struct decode_cache *c;
bbd9b64e 2110
ad312c7c 2111 vcpu->arch.mmio_fault_cr2 = cr2;
bbd9b64e
CO		 2112 kvm_x86_ops->cache_regs(vcpu);
2113
2114 vcpu->mmio_is_write = 0;
ad312c7c 2115 vcpu->arch.pio.string = 0;
bbd9b64e 2116
571008da 2117 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2118 int cs_db, cs_l;
2119 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2120
ad312c7c
ZX		 2121 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2122 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2123 vcpu->arch.emulate_ctxt.mode =
2124 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2125 ? X86EMUL_MODE_REAL : cs_l
2126 ? X86EMUL_MODE_PROT64 : cs_db
2127 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2128
ad312c7c 2129 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2130
2131 /* Reject the instructions other than VMCALL/VMMCALL when
2132 * try to emulate invalid opcode */
2133 c = &vcpu->arch.emulate_ctxt.decode;
2134 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2135 (!(c->twobyte && c->b == 0x01 &&
2136 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2137 c->modrm_mod == 3 && c->modrm_rm == 1)))
2138 return EMULATE_FAIL;
2139
f2b5756b 2140 ++vcpu->stat.insn_emulation;
bbd9b64e 2141 if (r) {
f2b5756b 2142 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2143 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2144 return EMULATE_DONE;
2145 return EMULATE_FAIL;
2146 }
2147 }
2148
ad312c7c 2149 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2150
ad312c7c 2151 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2152 return EMULATE_DO_MMIO;
2153
2154 if ((r || vcpu->mmio_is_write) && run) {
2155 run->exit_reason = KVM_EXIT_MMIO;
2156 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2157 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2158 run->mmio.len = vcpu->mmio_size;
2159 run->mmio.is_write = vcpu->mmio_is_write;
2160 }
2161
2162 if (r) {
2163 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2164 return EMULATE_DONE;
2165 if (!vcpu->mmio_needed) {
2166 kvm_report_emulation_failure(vcpu, "mmio");
2167 return EMULATE_FAIL;
2168 }
2169 return EMULATE_DO_MMIO;
2170 }
2171
2172 kvm_x86_ops->decache_regs(vcpu);
ad312c7c 2173 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2174
2175 if (vcpu->mmio_is_write) {
2176 vcpu->mmio_needed = 0;
2177 return EMULATE_DO_MMIO;
2178 }
2179
2180 return EMULATE_DONE;
2181}
2182EXPORT_SYMBOL_GPL(emulate_instruction);
2183
de7d789a
CO		 2184static void free_pio_guest_pages(struct kvm_vcpu *vcpu)
2185{
2186 int i;
2187
ad312c7c
ZX		 2188 for (i = 0; i < ARRAY_SIZE(vcpu->arch.pio.guest_pages); ++i)
2189 if (vcpu->arch.pio.guest_pages[i]) {
2190 kvm_release_page_dirty(vcpu->arch.pio.guest_pages[i]);
2191 vcpu->arch.pio.guest_pages[i] = NULL;
de7d789a
CO		 2192 }
2193}
2194
2195static int pio_copy_data(struct kvm_vcpu *vcpu)
2196{
ad312c7c 2197 void *p = vcpu->arch.pio_data;
de7d789a
CO		 2198 void *q;
2199 unsigned bytes;
ad312c7c 2200 int nr_pages = vcpu->arch.pio.guest_pages[1] ? 2 : 1;
de7d789a 2201
ad312c7c 2202 q = vmap(vcpu->arch.pio.guest_pages, nr_pages, VM_READ|VM_WRITE,
de7d789a
CO		 2203 PAGE_KERNEL);
2204 if (!q) {
2205 free_pio_guest_pages(vcpu);
2206 return -ENOMEM;
2207 }
ad312c7c
ZX		 2208 q += vcpu->arch.pio.guest_page_offset;
2209 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2210 if (vcpu->arch.pio.in)
de7d789a
CO		 2211 memcpy(q, p, bytes);
2212 else
2213 memcpy(p, q, bytes);
ad312c7c 2214 q -= vcpu->arch.pio.guest_page_offset;
de7d789a
CO		 2215 vunmap(q);
2216 free_pio_guest_pages(vcpu);
2217 return 0;
2218}
2219
2220int complete_pio(struct kvm_vcpu *vcpu)
2221{
ad312c7c 2222 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2223 long delta;
2224 int r;
2225
2226 kvm_x86_ops->cache_regs(vcpu);
2227
2228 if (!io->string) {
2229 if (io->in)
ad312c7c 2230 memcpy(&vcpu->arch.regs[VCPU_REGS_RAX], vcpu->arch.pio_data,
de7d789a
CO		 2231 io->size);
2232 } else {
2233 if (io->in) {
2234 r = pio_copy_data(vcpu);
2235 if (r) {
2236 kvm_x86_ops->cache_regs(vcpu);
2237 return r;
2238 }
2239 }
2240
2241 delta = 1;
2242 if (io->rep) {
2243 delta *= io->cur_count;
2244 /*
2245 * The size of the register should really depend on
2246 * current address size.
2247 */
ad312c7c 2248 vcpu->arch.regs[VCPU_REGS_RCX] -= delta;
de7d789a
CO		 2249 }
2250 if (io->down)
2251 delta = -delta;
2252 delta *= io->size;
2253 if (io->in)
ad312c7c 2254 vcpu->arch.regs[VCPU_REGS_RDI] += delta;
de7d789a 2255 else
ad312c7c 2256 vcpu->arch.regs[VCPU_REGS_RSI] += delta;
de7d789a
CO		 2257 }
2258
2259 kvm_x86_ops->decache_regs(vcpu);
2260
2261 io->count -= io->cur_count;
2262 io->cur_count = 0;
2263
2264 return 0;
2265}
2266
2267static void kernel_pio(struct kvm_io_device *pio_dev,
2268 struct kvm_vcpu *vcpu,
2269 void *pd)
2270{
2271 /* TODO: String I/O for in kernel device */
2272
2273 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2274 if (vcpu->arch.pio.in)
2275 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2276 vcpu->arch.pio.size,
de7d789a
CO		 2277 pd);
2278 else
ad312c7c
ZX		 2279 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2280 vcpu->arch.pio.size,
de7d789a
CO		 2281 pd);
2282 mutex_unlock(&vcpu->kvm->lock);
2283}
2284
2285static void pio_string_write(struct kvm_io_device *pio_dev,
2286 struct kvm_vcpu *vcpu)
2287{
ad312c7c
ZX		 2288 struct kvm_pio_request *io = &vcpu->arch.pio;
2289 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2290 int i;
2291
2292 mutex_lock(&vcpu->kvm->lock);
2293 for (i = 0; i < io->cur_count; i++) {
2294 kvm_iodevice_write(pio_dev, io->port,
2295 io->size,
2296 pd);
2297 pd += io->size;
2298 }
2299 mutex_unlock(&vcpu->kvm->lock);
2300}
2301
2302static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2303 gpa_t addr, int len,
2304 int is_write)
de7d789a 2305{
92760499 2306 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2307}
2308
2309int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2310 int size, unsigned port)
2311{
2312 struct kvm_io_device *pio_dev;
2313
2314 vcpu->run->exit_reason = KVM_EXIT_IO;
2315 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2316 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2317 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2318 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2319 vcpu->run->io.port = vcpu->arch.pio.port = port;
2320 vcpu->arch.pio.in = in;
2321 vcpu->arch.pio.string = 0;
2322 vcpu->arch.pio.down = 0;
2323 vcpu->arch.pio.guest_page_offset = 0;
2324 vcpu->arch.pio.rep = 0;
de7d789a 2325
2714d1d3
FEL		 2326 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2327 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2328 handler);
2329 else
2330 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2331 handler);
2332
de7d789a 2333 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2334 memcpy(vcpu->arch.pio_data, &vcpu->arch.regs[VCPU_REGS_RAX], 4);
de7d789a
CO		 2335
2336 kvm_x86_ops->skip_emulated_instruction(vcpu);
2337
92760499 2338 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2339 if (pio_dev) {
ad312c7c 2340 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2341 complete_pio(vcpu);
2342 return 1;
2343 }
2344 return 0;
2345}
2346EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2347
2348int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2349 int size, unsigned long count, int down,
2350 gva_t address, int rep, unsigned port)
2351{
2352 unsigned now, in_page;
2353 int i, ret = 0;
2354 int nr_pages = 1;
2355 struct page *page;
2356 struct kvm_io_device *pio_dev;
2357
2358 vcpu->run->exit_reason = KVM_EXIT_IO;
2359 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2360 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2361 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2362 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2363 vcpu->run->io.port = vcpu->arch.pio.port = port;
2364 vcpu->arch.pio.in = in;
2365 vcpu->arch.pio.string = 1;
2366 vcpu->arch.pio.down = down;
2367 vcpu->arch.pio.guest_page_offset = offset_in_page(address);
2368 vcpu->arch.pio.rep = rep;
de7d789a 2369
2714d1d3
FEL		 2370 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2371 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2372 handler);
2373 else
2374 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2375 handler);
2376
de7d789a
CO		 2377 if (!count) {
2378 kvm_x86_ops->skip_emulated_instruction(vcpu);
2379 return 1;
2380 }
2381
2382 if (!down)
2383 in_page = PAGE_SIZE - offset_in_page(address);
2384 else
2385 in_page = offset_in_page(address) + size;
2386 now = min(count, (unsigned long)in_page / size);
2387 if (!now) {
2388 /*
2389 * String I/O straddles page boundary. Pin two guest pages
2390 * so that we satisfy atomicity constraints. Do just one
2391 * transaction to avoid complexity.
2392 */
2393 nr_pages = 2;
2394 now = 1;
2395 }
2396 if (down) {
2397 /*
2398 * String I/O in reverse. Yuck. Kill the guest, fix later.
2399 */
2400 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2401 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2402 return 1;
2403 }
2404 vcpu->run->io.count = now;
ad312c7c 2405 vcpu->arch.pio.cur_count = now;
de7d789a 2406
ad312c7c 2407 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2408 kvm_x86_ops->skip_emulated_instruction(vcpu);
2409
2410 for (i = 0; i < nr_pages; ++i) {
de7d789a 2411 page = gva_to_page(vcpu, address + i * PAGE_SIZE);
ad312c7c 2412 vcpu->arch.pio.guest_pages[i] = page;
de7d789a 2413 if (!page) {
c1a5d4f9 2414 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2415 free_pio_guest_pages(vcpu);
2416 return 1;
2417 }
2418 }
2419
92760499
LV		 2420 pio_dev = vcpu_find_pio_dev(vcpu, port,
2421 vcpu->arch.pio.cur_count,
2422 !vcpu->arch.pio.in);
ad312c7c 2423 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2424 /* string PIO write */
2425 ret = pio_copy_data(vcpu);
2426 if (ret >= 0 && pio_dev) {
2427 pio_string_write(pio_dev, vcpu);
2428 complete_pio(vcpu);
ad312c7c 2429 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2430 ret = 1;
2431 }
2432 } else if (pio_dev)
2433 pr_unimpl(vcpu, "no string pio read support yet, "
2434 "port %x size %d count %ld\n",
2435 port, size, count);
2436
2437 return ret;
2438}
2439EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2440
f8c16bba 2441int kvm_arch_init(void *opaque)
043405e1 2442{
56c6d28a 2443 int r;
f8c16bba
ZX		 2444 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2445
f8c16bba
ZX		 2446 if (kvm_x86_ops) {
2447 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2448 r = -EEXIST;
2449 goto out;
f8c16bba
ZX		 2450 }
2451
2452 if (!ops->cpu_has_kvm_support()) {
2453 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2454 r = -EOPNOTSUPP;
2455 goto out;
f8c16bba
ZX		 2456 }
2457 if (ops->disabled_by_bios()) {
2458 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2459 r = -EOPNOTSUPP;
2460 goto out;
f8c16bba
ZX		 2461 }
2462
97db56ce
AK		 2463 r = kvm_mmu_module_init();
2464 if (r)
2465 goto out;
2466
2467 kvm_init_msr_list();
2468
f8c16bba 2469 kvm_x86_ops = ops;
56c6d28a 2470 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2471 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2472 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
2473 PT_DIRTY_MASK, PT64_NX_MASK, 0);
f8c16bba 2474 return 0;
56c6d28a
ZX		 2475
2476out:
56c6d28a 2477 return r;
043405e1 2478}
8776e519 2479
f8c16bba
ZX		 2480void kvm_arch_exit(void)
2481{
2482 kvm_x86_ops = NULL;
56c6d28a
ZX		 2483 kvm_mmu_module_exit();
2484}
f8c16bba 2485
8776e519
HB		 2486int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2487{
2488 ++vcpu->stat.halt_exits;
2714d1d3 2489 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2490 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2491 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
3200f405 2492 up_read(&vcpu->kvm->slots_lock);
8776e519 2493 kvm_vcpu_block(vcpu);
3200f405 2494 down_read(&vcpu->kvm->slots_lock);
a4535290 2495 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
8776e519
HB		 2496 return -EINTR;
2497 return 1;
2498 } else {
2499 vcpu->run->exit_reason = KVM_EXIT_HLT;
2500 return 0;
2501 }
2502}
2503EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2504
2f333bcb
MT		 2505static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2506 unsigned long a1)
2507{
2508 if (is_long_mode(vcpu))
2509 return a0;
2510 else
2511 return a0 | ((gpa_t)a1 << 32);
2512}
2513
8776e519
HB		 2514int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2515{
2516 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2517 int r = 1;
8776e519
HB		 2518
2519 kvm_x86_ops->cache_regs(vcpu);
2520
ad312c7c
ZX		 2521 nr = vcpu->arch.regs[VCPU_REGS_RAX];
2522 a0 = vcpu->arch.regs[VCPU_REGS_RBX];
2523 a1 = vcpu->arch.regs[VCPU_REGS_RCX];
2524 a2 = vcpu->arch.regs[VCPU_REGS_RDX];
2525 a3 = vcpu->arch.regs[VCPU_REGS_RSI];
8776e519 2526
2714d1d3
FEL		 2527 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2528
8776e519
HB		 2529 if (!is_long_mode(vcpu)) {
2530 nr &= 0xFFFFFFFF;
2531 a0 &= 0xFFFFFFFF;
2532 a1 &= 0xFFFFFFFF;
2533 a2 &= 0xFFFFFFFF;
2534 a3 &= 0xFFFFFFFF;
2535 }
2536
2537 switch (nr) {
b93463aa
AK		 2538 case KVM_HC_VAPIC_POLL_IRQ:
2539 ret = 0;
2540 break;
2f333bcb
MT		 2541 case KVM_HC_MMU_OP:
2542 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2543 break;
8776e519
HB		 2544 default:
2545 ret = -KVM_ENOSYS;
2546 break;
2547 }
ad312c7c 2548 vcpu->arch.regs[VCPU_REGS_RAX] = ret;
8776e519 2549 kvm_x86_ops->decache_regs(vcpu);
f11c3a8d 2550 ++vcpu->stat.hypercalls;
2f333bcb 2551 return r;
8776e519
HB		 2552}
2553EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2554
2555int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2556{
2557 char instruction[3];
2558 int ret = 0;
2559
8776e519
HB		 2560
2561 /*
2562 * Blow out the MMU to ensure that no other VCPU has an active mapping
2563 * to ensure that the updated hypercall appears atomically across all
2564 * VCPUs.
2565 */
2566 kvm_mmu_zap_all(vcpu->kvm);
2567
2568 kvm_x86_ops->cache_regs(vcpu);
2569 kvm_x86_ops->patch_hypercall(vcpu, instruction);
ad312c7c 2570 if (emulator_write_emulated(vcpu->arch.rip, instruction, 3, vcpu)
8776e519
HB		 2571 != X86EMUL_CONTINUE)
2572 ret = -EFAULT;
2573
8776e519
HB		 2574 return ret;
2575}
2576
2577static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2578{
2579 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2580}
2581
2582void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2583{
2584 struct descriptor_table dt = { limit, base };
2585
2586 kvm_x86_ops->set_gdt(vcpu, &dt);
2587}
2588
2589void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2590{
2591 struct descriptor_table dt = { limit, base };
2592
2593 kvm_x86_ops->set_idt(vcpu, &dt);
2594}
2595
2596void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2597 unsigned long *rflags)
2598{
2d3ad1f4 2599 kvm_lmsw(vcpu, msw);
8776e519
HB		 2600 *rflags = kvm_x86_ops->get_rflags(vcpu);
2601}
2602
2603unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2604{
54e445ca
JR		 2605 unsigned long value;
2606
8776e519
HB		 2607 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2608 switch (cr) {
2609 case 0:
54e445ca
JR		 2610 value = vcpu->arch.cr0;
2611 break;
8776e519 2612 case 2:
54e445ca
JR		 2613 value = vcpu->arch.cr2;
2614 break;
8776e519 2615 case 3:
54e445ca
JR		 2616 value = vcpu->arch.cr3;
2617 break;
8776e519 2618 case 4:
54e445ca
JR		 2619 value = vcpu->arch.cr4;
2620 break;
152ff9be 2621 case 8:
54e445ca
JR		 2622 value = kvm_get_cr8(vcpu);
2623 break;
8776e519 2624 default:
b8688d51 2625 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2626 return 0;
2627 }
54e445ca
JR		 2628 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2629 (u32)((u64)value >> 32), handler);
2630
2631 return value;
8776e519
HB		 2632}
2633
2634void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2635 unsigned long *rflags)
2636{
54e445ca
JR		 2637 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2638 (u32)((u64)val >> 32), handler);
2639
8776e519
HB		 2640 switch (cr) {
2641 case 0:
2d3ad1f4 2642 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2643 *rflags = kvm_x86_ops->get_rflags(vcpu);
2644 break;
2645 case 2:
ad312c7c 2646 vcpu->arch.cr2 = val;
8776e519
HB		 2647 break;
2648 case 3:
2d3ad1f4 2649 kvm_set_cr3(vcpu, val);
8776e519
HB		 2650 break;
2651 case 4:
2d3ad1f4 2652 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2653 break;
152ff9be 2654 case 8:
2d3ad1f4 2655 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2656 break;
8776e519 2657 default:
b8688d51 2658 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2659 }
2660}
2661
07716717
DK		 2662static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2663{
ad312c7c
ZX		 2664 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2665 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2666
2667 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2668 /* when no next entry is found, the current entry[i] is reselected */
2669 for (j = i + 1; j == i; j = (j + 1) % nent) {
ad312c7c 2670 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2671 if (ej->function == e->function) {
2672 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2673 return j;
2674 }
2675 }
2676 return 0; /* silence gcc, even though control never reaches here */
2677}
2678
2679/* find an entry with matching function, matching index (if needed), and that
2680 * should be read next (if it's stateful) */
2681static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2682 u32 function, u32 index)
2683{
2684 if (e->function != function)
2685 return 0;
2686 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2687 return 0;
2688 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
2689 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
2690 return 0;
2691 return 1;
2692}
2693
8776e519
HB		 2694void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2695{
2696 int i;
07716717
DK		 2697 u32 function, index;
2698 struct kvm_cpuid_entry2 *e, *best;
8776e519
HB		 2699
2700 kvm_x86_ops->cache_regs(vcpu);
ad312c7c
ZX		 2701 function = vcpu->arch.regs[VCPU_REGS_RAX];
2702 index = vcpu->arch.regs[VCPU_REGS_RCX];
2703 vcpu->arch.regs[VCPU_REGS_RAX] = 0;
2704 vcpu->arch.regs[VCPU_REGS_RBX] = 0;
2705 vcpu->arch.regs[VCPU_REGS_RCX] = 0;
2706 vcpu->arch.regs[VCPU_REGS_RDX] = 0;
8776e519 2707 best = NULL;
ad312c7c
ZX		 2708 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2709 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2710 if (is_matching_cpuid_entry(e, function, index)) {
2711 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2712 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2713 best = e;
2714 break;
2715 }
2716 /*
2717 * Both basic or both extended?
2718 */
2719 if (((e->function ^ function) & 0x80000000) == 0)
2720 if (!best || e->function > best->function)
2721 best = e;
2722 }
2723 if (best) {
ad312c7c
ZX		 2724 vcpu->arch.regs[VCPU_REGS_RAX] = best->eax;
2725 vcpu->arch.regs[VCPU_REGS_RBX] = best->ebx;
2726 vcpu->arch.regs[VCPU_REGS_RCX] = best->ecx;
2727 vcpu->arch.regs[VCPU_REGS_RDX] = best->edx;
8776e519
HB		 2728 }
2729 kvm_x86_ops->decache_regs(vcpu);
2730 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3
FEL		 2731 KVMTRACE_5D(CPUID, vcpu, function,
2732 (u32)vcpu->arch.regs[VCPU_REGS_RAX],
2733 (u32)vcpu->arch.regs[VCPU_REGS_RBX],
2734 (u32)vcpu->arch.regs[VCPU_REGS_RCX],
2735 (u32)vcpu->arch.regs[VCPU_REGS_RDX], handler);
8776e519
HB		 2736}
2737EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2738
b6c7a5dc
HB		 2739/*
2740 * Check if userspace requested an interrupt window, and that the
2741 * interrupt window is open.
2742 *
2743 * No need to exit to userspace if we already have an interrupt queued.
2744 */
2745static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2746 struct kvm_run *kvm_run)
2747{
ad312c7c 2748 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2749 kvm_run->request_interrupt_window &&
ad312c7c 2750 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2751 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2752}
2753
2754static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2755 struct kvm_run *kvm_run)
2756{
2757 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 2758 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc
HB		 2759 kvm_run->apic_base = kvm_get_apic_base(vcpu);
2760 if (irqchip_in_kernel(vcpu->kvm))
2761 kvm_run->ready_for_interrupt_injection = 1;
2762 else
2763 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2764 (vcpu->arch.interrupt_window_open &&
2765 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 2766}
2767
b93463aa
AK		 2768static void vapic_enter(struct kvm_vcpu *vcpu)
2769{
2770 struct kvm_lapic *apic = vcpu->arch.apic;
2771 struct page *page;
2772
2773 if (!apic || !apic->vapic_addr)
2774 return;
2775
10589a46 2776 down_read(&current->mm->mmap_sem);
b93463aa 2777 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
10589a46 2778 up_read(&current->mm->mmap_sem);
72dc67a6
IE		 2779
2780 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2781}
2782
2783static void vapic_exit(struct kvm_vcpu *vcpu)
2784{
2785 struct kvm_lapic *apic = vcpu->arch.apic;
2786
2787 if (!apic || !apic->vapic_addr)
2788 return;
2789
f8b78fa3 2790 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2791 kvm_release_page_dirty(apic->vapic_page);
2792 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 2793 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2794}
2795
b6c7a5dc
HB		 2796static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2797{
2798 int r;
2799
a4535290 2800 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
b6c7a5dc 2801 pr_debug("vcpu %d received sipi with vector # %x\n",
ad312c7c 2802 vcpu->vcpu_id, vcpu->arch.sipi_vector);
b6c7a5dc
HB		 2803 kvm_lapic_reset(vcpu);
2804 r = kvm_x86_ops->vcpu_reset(vcpu);
2805 if (r)
2806 return r;
a4535290 2807 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 2808 }
2809
3200f405 2810 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2811 vapic_enter(vcpu);
2812
b6c7a5dc
HB		 2813preempted:
2814 if (vcpu->guest_debug.enabled)
2815 kvm_x86_ops->guest_debug_pre(vcpu);
2816
2817again:
2e53d63a
MT		 2818 if (vcpu->requests)
2819 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
2820 kvm_mmu_unload(vcpu);
2821
b6c7a5dc
HB		 2822 r = kvm_mmu_reload(vcpu);
2823 if (unlikely(r))
2824 goto out;
2825
2f52d58c
AK		 2826 if (vcpu->requests) {
2827 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 2828 __kvm_migrate_timers(vcpu);
d4acf7e7
MT		 2829 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
2830 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 2831 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
2832 &vcpu->requests)) {
2833 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
2834 r = 0;
2835 goto out;
2836 }
71c4dfaf
JR		 2837 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
2838 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2839 r = 0;
2840 goto out;
2841 }
2f52d58c 2842 }
b93463aa 2843
06e05645 2844 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 2845 kvm_inject_pending_timer_irqs(vcpu);
2846
2847 preempt_disable();
2848
2849 kvm_x86_ops->prepare_guest_switch(vcpu);
2850 kvm_load_guest_fpu(vcpu);
2851
2852 local_irq_disable();
2853
d4acf7e7 2854 if (vcpu->requests || need_resched()) {
6c142801
AK		 2855 local_irq_enable();
2856 preempt_enable();
2857 r = 1;
2858 goto out;
2859 }
2860
b6c7a5dc
HB		 2861 if (signal_pending(current)) {
2862 local_irq_enable();
2863 preempt_enable();
2864 r = -EINTR;
2865 kvm_run->exit_reason = KVM_EXIT_INTR;
2866 ++vcpu->stat.signal_exits;
2867 goto out;
2868 }
2869
e9571ed5
MT		 2870 vcpu->guest_mode = 1;
2871 /*
2872 * Make sure that guest_mode assignment won't happen after
2873 * testing the pending IRQ vector bitmap.
2874 */
2875 smp_wmb();
2876
ad312c7c 2877 if (vcpu->arch.exception.pending)
298101da
AK		 2878 __queue_exception(vcpu);
2879 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2880 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 2881 else
b6c7a5dc
HB		 2882 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
2883
b93463aa
AK		 2884 kvm_lapic_sync_to_vapic(vcpu);
2885
3200f405
MT		 2886 up_read(&vcpu->kvm->slots_lock);
2887
b6c7a5dc
HB		 2888 kvm_guest_enter();
2889
b6c7a5dc 2890
2714d1d3 2891 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 2892 kvm_x86_ops->run(vcpu, kvm_run);
2893
2894 vcpu->guest_mode = 0;
2895 local_irq_enable();
2896
2897 ++vcpu->stat.exits;
2898
2899 /*
2900 * We must have an instruction between local_irq_enable() and
2901 * kvm_guest_exit(), so the timer interrupt isn't delayed by
2902 * the interrupt shadow. The stat.exits increment will do nicely.
2903 * But we need to prevent reordering, hence this barrier():
2904 */
2905 barrier();
2906
2907 kvm_guest_exit();
2908
2909 preempt_enable();
2910
3200f405
MT		 2911 down_read(&vcpu->kvm->slots_lock);
2912
b6c7a5dc
HB		 2913 /*
2914 * Profile KVM exit RIPs:
2915 */
2916 if (unlikely(prof_on == KVM_PROFILING)) {
2917 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2918 profile_hit(KVM_PROFILING, (void *)vcpu->arch.rip);
b6c7a5dc
HB		 2919 }
2920
ad312c7c
ZX		 2921 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
2922 vcpu->arch.exception.pending = false;
298101da 2923
b93463aa
AK		 2924 kvm_lapic_sync_from_vapic(vcpu);
2925
b6c7a5dc
HB		 2926 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
2927
2928 if (r > 0) {
2929 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2930 r = -EINTR;
2931 kvm_run->exit_reason = KVM_EXIT_INTR;
2932 ++vcpu->stat.request_irq_exits;
2933 goto out;
2934 }
e1beb1d3 2935 if (!need_resched())
b6c7a5dc 2936 goto again;
b6c7a5dc
HB		 2937 }
2938
2939out:
3200f405 2940 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2941 if (r > 0) {
2942 kvm_resched(vcpu);
3200f405 2943 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2944 goto preempted;
2945 }
2946
2947 post_kvm_run_save(vcpu, kvm_run);
2948
b93463aa
AK		 2949 vapic_exit(vcpu);
2950
b6c7a5dc
HB		 2951 return r;
2952}
2953
2954int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2955{
2956 int r;
2957 sigset_t sigsaved;
2958
2959 vcpu_load(vcpu);
2960
ac9f6dc0
AK		 2961 if (vcpu->sigset_active)
2962 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
2963
a4535290 2964 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 2965 kvm_vcpu_block(vcpu);
ac9f6dc0
AK		 2966 r = -EAGAIN;
2967 goto out;
b6c7a5dc
HB		 2968 }
2969
b6c7a5dc
HB		 2970 /* re-sync apic's tpr */
2971 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 2972 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 2973
ad312c7c 2974 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 2975 r = complete_pio(vcpu);
2976 if (r)
2977 goto out;
2978 }
2979#if CONFIG_HAS_IOMEM
2980 if (vcpu->mmio_needed) {
2981 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
2982 vcpu->mmio_read_completed = 1;
2983 vcpu->mmio_needed = 0;
3200f405
MT		 2984
2985 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 2986 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 2987 vcpu->arch.mmio_fault_cr2, 0,
2988 EMULTYPE_NO_DECODE);
3200f405 2989 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2990 if (r == EMULATE_DO_MMIO) {
2991 /*
2992 * Read-modify-write. Back to userspace.
2993 */
2994 r = 0;
2995 goto out;
2996 }
2997 }
2998#endif
2999 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) {
3000 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 3001 vcpu->arch.regs[VCPU_REGS_RAX] = kvm_run->hypercall.ret;
b6c7a5dc
HB		 3002 kvm_x86_ops->decache_regs(vcpu);
3003 }
3004
3005 r = __vcpu_run(vcpu, kvm_run);
3006
3007out:
3008 if (vcpu->sigset_active)
3009 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3010
3011 vcpu_put(vcpu);
3012 return r;
3013}
3014
3015int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3016{
3017 vcpu_load(vcpu);
3018
3019 kvm_x86_ops->cache_regs(vcpu);
3020
ad312c7c
ZX		 3021 regs->rax = vcpu->arch.regs[VCPU_REGS_RAX];
3022 regs->rbx = vcpu->arch.regs[VCPU_REGS_RBX];
3023 regs->rcx = vcpu->arch.regs[VCPU_REGS_RCX];
3024 regs->rdx = vcpu->arch.regs[VCPU_REGS_RDX];
3025 regs->rsi = vcpu->arch.regs[VCPU_REGS_RSI];
3026 regs->rdi = vcpu->arch.regs[VCPU_REGS_RDI];
3027 regs->rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3028 regs->rbp = vcpu->arch.regs[VCPU_REGS_RBP];
b6c7a5dc 3029#ifdef CONFIG_X86_64
ad312c7c
ZX		 3030 regs->r8 = vcpu->arch.regs[VCPU_REGS_R8];
3031 regs->r9 = vcpu->arch.regs[VCPU_REGS_R9];
3032 regs->r10 = vcpu->arch.regs[VCPU_REGS_R10];
3033 regs->r11 = vcpu->arch.regs[VCPU_REGS_R11];
3034 regs->r12 = vcpu->arch.regs[VCPU_REGS_R12];
3035 regs->r13 = vcpu->arch.regs[VCPU_REGS_R13];
3036 regs->r14 = vcpu->arch.regs[VCPU_REGS_R14];
3037 regs->r15 = vcpu->arch.regs[VCPU_REGS_R15];
b6c7a5dc
HB		 3038#endif
3039
ad312c7c 3040 regs->rip = vcpu->arch.rip;
b6c7a5dc
HB		 3041 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3042
3043 /*
3044 * Don't leak debug flags in case they were set for guest debugging
3045 */
3046 if (vcpu->guest_debug.enabled && vcpu->guest_debug.singlestep)
3047 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3048
3049 vcpu_put(vcpu);
3050
3051 return 0;
3052}
3053
3054int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3055{
3056 vcpu_load(vcpu);
3057
ad312c7c
ZX		 3058 vcpu->arch.regs[VCPU_REGS_RAX] = regs->rax;
3059 vcpu->arch.regs[VCPU_REGS_RBX] = regs->rbx;
3060 vcpu->arch.regs[VCPU_REGS_RCX] = regs->rcx;
3061 vcpu->arch.regs[VCPU_REGS_RDX] = regs->rdx;
3062 vcpu->arch.regs[VCPU_REGS_RSI] = regs->rsi;
3063 vcpu->arch.regs[VCPU_REGS_RDI] = regs->rdi;
3064 vcpu->arch.regs[VCPU_REGS_RSP] = regs->rsp;
3065 vcpu->arch.regs[VCPU_REGS_RBP] = regs->rbp;
b6c7a5dc 3066#ifdef CONFIG_X86_64
ad312c7c
ZX		 3067 vcpu->arch.regs[VCPU_REGS_R8] = regs->r8;
3068 vcpu->arch.regs[VCPU_REGS_R9] = regs->r9;
3069 vcpu->arch.regs[VCPU_REGS_R10] = regs->r10;
3070 vcpu->arch.regs[VCPU_REGS_R11] = regs->r11;
3071 vcpu->arch.regs[VCPU_REGS_R12] = regs->r12;
3072 vcpu->arch.regs[VCPU_REGS_R13] = regs->r13;
3073 vcpu->arch.regs[VCPU_REGS_R14] = regs->r14;
3074 vcpu->arch.regs[VCPU_REGS_R15] = regs->r15;
b6c7a5dc
HB		 3075#endif
3076
ad312c7c 3077 vcpu->arch.rip = regs->rip;
b6c7a5dc
HB		 3078 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3079
3080 kvm_x86_ops->decache_regs(vcpu);
3081
b4f14abd
JK		 3082 vcpu->arch.exception.pending = false;
3083
b6c7a5dc
HB		 3084 vcpu_put(vcpu);
3085
3086 return 0;
3087}
3088
3e6e0aab
GT		 3089void kvm_get_segment(struct kvm_vcpu *vcpu,
3090 struct kvm_segment *var, int seg)
b6c7a5dc 3091{
14af3f3c 3092 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3093}
3094
3095void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3096{
3097 struct kvm_segment cs;
3098
3e6e0aab 3099 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3100 *db = cs.db;
3101 *l = cs.l;
3102}
3103EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3104
3105int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3106 struct kvm_sregs *sregs)
3107{
3108 struct descriptor_table dt;
3109 int pending_vec;
3110
3111 vcpu_load(vcpu);
3112
3e6e0aab
GT		 3113 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3114 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3115 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3116 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3117 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3118 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3119
3e6e0aab
GT		 3120 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3121 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3122
3123 kvm_x86_ops->get_idt(vcpu, &dt);
3124 sregs->idt.limit = dt.limit;
3125 sregs->idt.base = dt.base;
3126 kvm_x86_ops->get_gdt(vcpu, &dt);
3127 sregs->gdt.limit = dt.limit;
3128 sregs->gdt.base = dt.base;
3129
3130 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3131 sregs->cr0 = vcpu->arch.cr0;
3132 sregs->cr2 = vcpu->arch.cr2;
3133 sregs->cr3 = vcpu->arch.cr3;
3134 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3135 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3136 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3137 sregs->apic_base = kvm_get_apic_base(vcpu);
3138
3139 if (irqchip_in_kernel(vcpu->kvm)) {
3140 memset(sregs->interrupt_bitmap, 0,
3141 sizeof sregs->interrupt_bitmap);
3142 pending_vec = kvm_x86_ops->get_irq(vcpu);
3143 if (pending_vec >= 0)
3144 set_bit(pending_vec,
3145 (unsigned long *)sregs->interrupt_bitmap);
3146 } else
ad312c7c 3147 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3148 sizeof sregs->interrupt_bitmap);
3149
3150 vcpu_put(vcpu);
3151
3152 return 0;
3153}
3154
62d9f0db
MT		 3155int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3156 struct kvm_mp_state *mp_state)
3157{
3158 vcpu_load(vcpu);
3159 mp_state->mp_state = vcpu->arch.mp_state;
3160 vcpu_put(vcpu);
3161 return 0;
3162}
3163
3164int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3165 struct kvm_mp_state *mp_state)
3166{
3167 vcpu_load(vcpu);
3168 vcpu->arch.mp_state = mp_state->mp_state;
3169 vcpu_put(vcpu);
3170 return 0;
3171}
3172
3e6e0aab 3173static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3174 struct kvm_segment *var, int seg)
3175{
14af3f3c 3176 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3177}
3178
37817f29
IE		 3179static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3180 struct kvm_segment *kvm_desct)
3181{
3182 kvm_desct->base = seg_desc->base0;
3183 kvm_desct->base |= seg_desc->base1 << 16;
3184 kvm_desct->base |= seg_desc->base2 << 24;
3185 kvm_desct->limit = seg_desc->limit0;
3186 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3187 if (seg_desc->g) {
3188 kvm_desct->limit <<= 12;
3189 kvm_desct->limit |= 0xfff;
3190 }
37817f29
IE		 3191 kvm_desct->selector = selector;
3192 kvm_desct->type = seg_desc->type;
3193 kvm_desct->present = seg_desc->p;
3194 kvm_desct->dpl = seg_desc->dpl;
3195 kvm_desct->db = seg_desc->d;
3196 kvm_desct->s = seg_desc->s;
3197 kvm_desct->l = seg_desc->l;
3198 kvm_desct->g = seg_desc->g;
3199 kvm_desct->avl = seg_desc->avl;
3200 if (!selector)
3201 kvm_desct->unusable = 1;
3202 else
3203 kvm_desct->unusable = 0;
3204 kvm_desct->padding = 0;
3205}
3206
3207static void get_segment_descritptor_dtable(struct kvm_vcpu *vcpu,
3208 u16 selector,
3209 struct descriptor_table *dtable)
3210{
3211 if (selector & 1 << 2) {
3212 struct kvm_segment kvm_seg;
3213
3e6e0aab 3214 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3215
3216 if (kvm_seg.unusable)
3217 dtable->limit = 0;
3218 else
3219 dtable->limit = kvm_seg.limit;
3220 dtable->base = kvm_seg.base;
3221 }
3222 else
3223 kvm_x86_ops->get_gdt(vcpu, dtable);
3224}
3225
3226/* allowed just for 8 bytes segments */
3227static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3228 struct desc_struct *seg_desc)
3229{
98899aa0 3230 gpa_t gpa;
37817f29
IE		 3231 struct descriptor_table dtable;
3232 u16 index = selector >> 3;
3233
3234 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3235
3236 if (dtable.limit < index * 8 + 7) {
3237 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3238 return 1;
3239 }
98899aa0
MT		 3240 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3241 gpa += index * 8;
3242 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3243}
3244
3245/* allowed just for 8 bytes segments */
3246static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3247 struct desc_struct *seg_desc)
3248{
98899aa0 3249 gpa_t gpa;
37817f29
IE		 3250 struct descriptor_table dtable;
3251 u16 index = selector >> 3;
3252
3253 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3254
3255 if (dtable.limit < index * 8 + 7)
3256 return 1;
98899aa0
MT		 3257 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3258 gpa += index * 8;
3259 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3260}
3261
3262static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3263 struct desc_struct *seg_desc)
3264{
3265 u32 base_addr;
3266
3267 base_addr = seg_desc->base0;
3268 base_addr |= (seg_desc->base1 << 16);
3269 base_addr |= (seg_desc->base2 << 24);
3270
98899aa0 3271 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3272}
3273
37817f29
IE		 3274static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3275{
3276 struct kvm_segment kvm_seg;
3277
3e6e0aab 3278 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3279 return kvm_seg.selector;
3280}
3281
3282static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3283 u16 selector,
3284 struct kvm_segment *kvm_seg)
3285{
3286 struct desc_struct seg_desc;
3287
3288 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3289 return 1;
3290 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3291 return 0;
3292}
3293
3e6e0aab
GT		 3294int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3295 int type_bits, int seg)
37817f29
IE		 3296{
3297 struct kvm_segment kvm_seg;
3298
3299 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3300 return 1;
3301 kvm_seg.type |= type_bits;
3302
3303 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3304 seg != VCPU_SREG_LDTR)
3305 if (!kvm_seg.s)
3306 kvm_seg.unusable = 1;
3307
3e6e0aab 3308 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3309 return 0;
3310}
3311
3312static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3313 struct tss_segment_32 *tss)
3314{
3315 tss->cr3 = vcpu->arch.cr3;
3316 tss->eip = vcpu->arch.rip;
3317 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
3318 tss->eax = vcpu->arch.regs[VCPU_REGS_RAX];
3319 tss->ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3320 tss->edx = vcpu->arch.regs[VCPU_REGS_RDX];
3321 tss->ebx = vcpu->arch.regs[VCPU_REGS_RBX];
3322 tss->esp = vcpu->arch.regs[VCPU_REGS_RSP];
3323 tss->ebp = vcpu->arch.regs[VCPU_REGS_RBP];
3324 tss->esi = vcpu->arch.regs[VCPU_REGS_RSI];
3325 tss->edi = vcpu->arch.regs[VCPU_REGS_RDI];
3326
3327 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3328 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3329 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3330 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3331 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3332 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3333 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3334 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3335}
3336
3337static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3338 struct tss_segment_32 *tss)
3339{
3340 kvm_set_cr3(vcpu, tss->cr3);
3341
3342 vcpu->arch.rip = tss->eip;
3343 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3344
3345 vcpu->arch.regs[VCPU_REGS_RAX] = tss->eax;
3346 vcpu->arch.regs[VCPU_REGS_RCX] = tss->ecx;
3347 vcpu->arch.regs[VCPU_REGS_RDX] = tss->edx;
3348 vcpu->arch.regs[VCPU_REGS_RBX] = tss->ebx;
3349 vcpu->arch.regs[VCPU_REGS_RSP] = tss->esp;
3350 vcpu->arch.regs[VCPU_REGS_RBP] = tss->ebp;
3351 vcpu->arch.regs[VCPU_REGS_RSI] = tss->esi;
3352 vcpu->arch.regs[VCPU_REGS_RDI] = tss->edi;
3353
3e6e0aab 3354 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3355 return 1;
3356
3e6e0aab 3357 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3358 return 1;
3359
3e6e0aab 3360 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3361 return 1;
3362
3e6e0aab 3363 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3364 return 1;
3365
3e6e0aab 3366 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3367 return 1;
3368
3e6e0aab 3369 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3370 return 1;
3371
3e6e0aab 3372 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3373 return 1;
3374 return 0;
3375}
3376
3377static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3378 struct tss_segment_16 *tss)
3379{
3380 tss->ip = vcpu->arch.rip;
3381 tss->flag = kvm_x86_ops->get_rflags(vcpu);
3382 tss->ax = vcpu->arch.regs[VCPU_REGS_RAX];
3383 tss->cx = vcpu->arch.regs[VCPU_REGS_RCX];
3384 tss->dx = vcpu->arch.regs[VCPU_REGS_RDX];
3385 tss->bx = vcpu->arch.regs[VCPU_REGS_RBX];
3386 tss->sp = vcpu->arch.regs[VCPU_REGS_RSP];
3387 tss->bp = vcpu->arch.regs[VCPU_REGS_RBP];
3388 tss->si = vcpu->arch.regs[VCPU_REGS_RSI];
3389 tss->di = vcpu->arch.regs[VCPU_REGS_RDI];
3390
3391 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3392 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3393 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3394 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3395 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3396 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3397}
3398
3399static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3400 struct tss_segment_16 *tss)
3401{
3402 vcpu->arch.rip = tss->ip;
3403 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
3404 vcpu->arch.regs[VCPU_REGS_RAX] = tss->ax;
3405 vcpu->arch.regs[VCPU_REGS_RCX] = tss->cx;
3406 vcpu->arch.regs[VCPU_REGS_RDX] = tss->dx;
3407 vcpu->arch.regs[VCPU_REGS_RBX] = tss->bx;
3408 vcpu->arch.regs[VCPU_REGS_RSP] = tss->sp;
3409 vcpu->arch.regs[VCPU_REGS_RBP] = tss->bp;
3410 vcpu->arch.regs[VCPU_REGS_RSI] = tss->si;
3411 vcpu->arch.regs[VCPU_REGS_RDI] = tss->di;
3412
3e6e0aab 3413 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3414 return 1;
3415
3e6e0aab 3416 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3417 return 1;
3418
3e6e0aab 3419 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3420 return 1;
3421
3e6e0aab 3422 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3423 return 1;
3424
3e6e0aab 3425 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3426 return 1;
3427 return 0;
3428}
3429
8b2cf73c 3430static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3431 u32 old_tss_base,
37817f29
IE		 3432 struct desc_struct *nseg_desc)
3433{
3434 struct tss_segment_16 tss_segment_16;
3435 int ret = 0;
3436
34198bf8
MT		 3437 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3438 sizeof tss_segment_16))
37817f29
IE		 3439 goto out;
3440
3441 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3442
34198bf8
MT		 3443 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3444 sizeof tss_segment_16))
37817f29 3445 goto out;
34198bf8
MT		 3446
3447 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3448 &tss_segment_16, sizeof tss_segment_16))
3449 goto out;
3450
37817f29
IE		 3451 if (load_state_from_tss16(vcpu, &tss_segment_16))
3452 goto out;
3453
3454 ret = 1;
3455out:
3456 return ret;
3457}
3458
8b2cf73c 3459static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3460 u32 old_tss_base,
37817f29
IE		 3461 struct desc_struct *nseg_desc)
3462{
3463 struct tss_segment_32 tss_segment_32;
3464 int ret = 0;
3465
34198bf8
MT		 3466 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3467 sizeof tss_segment_32))
37817f29
IE		 3468 goto out;
3469
3470 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3471
34198bf8
MT		 3472 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3473 sizeof tss_segment_32))
3474 goto out;
3475
3476 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3477 &tss_segment_32, sizeof tss_segment_32))
37817f29 3478 goto out;
34198bf8 3479
37817f29
IE		 3480 if (load_state_from_tss32(vcpu, &tss_segment_32))
3481 goto out;
3482
3483 ret = 1;
3484out:
3485 return ret;
3486}
3487
3488int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3489{
3490 struct kvm_segment tr_seg;
3491 struct desc_struct cseg_desc;
3492 struct desc_struct nseg_desc;
3493 int ret = 0;
34198bf8
MT		 3494 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3495 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3496
34198bf8 3497 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3498
34198bf8
MT		 3499 /* FIXME: Handle errors. Failure to read either TSS or their
3500 * descriptors should generate a pagefault.
3501 */
37817f29
IE		 3502 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3503 goto out;
3504
34198bf8 3505 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3506 goto out;
3507
37817f29
IE		 3508 if (reason != TASK_SWITCH_IRET) {
3509 int cpl;
3510
3511 cpl = kvm_x86_ops->get_cpl(vcpu);
3512 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3513 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3514 return 1;
3515 }
3516 }
3517
3518 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3519 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3520 return 1;
3521 }
3522
3523 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3524 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3525 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3526 }
3527
3528 if (reason == TASK_SWITCH_IRET) {
3529 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3530 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3531 }
3532
3533 kvm_x86_ops->skip_emulated_instruction(vcpu);
3534 kvm_x86_ops->cache_regs(vcpu);
3535
3536 if (nseg_desc.type & 8)
34198bf8 3537 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3538 &nseg_desc);
3539 else
34198bf8 3540 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3541 &nseg_desc);
3542
3543 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3544 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3545 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3546 }
3547
3548 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3549 nseg_desc.type |= (1 << 1);
37817f29
IE		 3550 save_guest_segment_descriptor(vcpu, tss_selector,
3551 &nseg_desc);
3552 }
3553
3554 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3555 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3556 tr_seg.type = 11;
3e6e0aab 3557 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29
IE		 3558out:
3559 kvm_x86_ops->decache_regs(vcpu);
3560 return ret;
3561}
3562EXPORT_SYMBOL_GPL(kvm_task_switch);
3563
b6c7a5dc
HB		 3564int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3565 struct kvm_sregs *sregs)
3566{
3567 int mmu_reset_needed = 0;
3568 int i, pending_vec, max_bits;
3569 struct descriptor_table dt;
3570
3571 vcpu_load(vcpu);
3572
3573 dt.limit = sregs->idt.limit;
3574 dt.base = sregs->idt.base;
3575 kvm_x86_ops->set_idt(vcpu, &dt);
3576 dt.limit = sregs->gdt.limit;
3577 dt.base = sregs->gdt.base;
3578 kvm_x86_ops->set_gdt(vcpu, &dt);
3579
ad312c7c
ZX		 3580 vcpu->arch.cr2 = sregs->cr2;
3581 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3582 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3583
2d3ad1f4 3584 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3585
ad312c7c 3586 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3587 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3588 kvm_set_apic_base(vcpu, sregs->apic_base);
3589
3590 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3591
ad312c7c 3592 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3593 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3594 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3595
ad312c7c 3596 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3597 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3598 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3599 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3600
3601 if (mmu_reset_needed)
3602 kvm_mmu_reset_context(vcpu);
3603
3604 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3605 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3606 sizeof vcpu->arch.irq_pending);
3607 vcpu->arch.irq_summary = 0;
3608 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3609 if (vcpu->arch.irq_pending[i])
3610 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3611 } else {
3612 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3613 pending_vec = find_first_bit(
3614 (const unsigned long *)sregs->interrupt_bitmap,
3615 max_bits);
3616 /* Only pending external irq is handled here */
3617 if (pending_vec < max_bits) {
3618 kvm_x86_ops->set_irq(vcpu, pending_vec);
3619 pr_debug("Set back pending irq %d\n",
3620 pending_vec);
3621 }
3622 }
3623
3e6e0aab
GT		 3624 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3625 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3626 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3627 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3628 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3629 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3630
3e6e0aab
GT		 3631 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3632 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3633
3634 vcpu_put(vcpu);
3635
3636 return 0;
3637}
3638
3639int kvm_arch_vcpu_ioctl_debug_guest(struct kvm_vcpu *vcpu,
3640 struct kvm_debug_guest *dbg)
3641{
3642 int r;
3643
3644 vcpu_load(vcpu);
3645
3646 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3647
3648 vcpu_put(vcpu);
3649
3650 return r;
3651}
3652
d0752060
HB		 3653/*
3654 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3655 * we have asm/x86/processor.h
3656 */
3657struct fxsave {
3658 u16 cwd;
3659 u16 swd;
3660 u16 twd;
3661 u16 fop;
3662 u64 rip;
3663 u64 rdp;
3664 u32 mxcsr;
3665 u32 mxcsr_mask;
3666 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3667#ifdef CONFIG_X86_64
3668 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3669#else
3670 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3671#endif
3672};
3673
8b006791
ZX		 3674/*
3675 * Translate a guest virtual address to a guest physical address.
3676 */
3677int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3678 struct kvm_translation *tr)
3679{
3680 unsigned long vaddr = tr->linear_address;
3681 gpa_t gpa;
3682
3683 vcpu_load(vcpu);
72dc67a6 3684 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3685 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3686 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3687 tr->physical_address = gpa;
3688 tr->valid = gpa != UNMAPPED_GVA;
3689 tr->writeable = 1;
3690 tr->usermode = 0;
8b006791
ZX		 3691 vcpu_put(vcpu);
3692
3693 return 0;
3694}
3695
d0752060
HB		 3696int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3697{
ad312c7c 3698 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3699
3700 vcpu_load(vcpu);
3701
3702 memcpy(fpu->fpr, fxsave->st_space, 128);
3703 fpu->fcw = fxsave->cwd;
3704 fpu->fsw = fxsave->swd;
3705 fpu->ftwx = fxsave->twd;
3706 fpu->last_opcode = fxsave->fop;
3707 fpu->last_ip = fxsave->rip;
3708 fpu->last_dp = fxsave->rdp;
3709 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3710
3711 vcpu_put(vcpu);
3712
3713 return 0;
3714}
3715
3716int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3717{
ad312c7c 3718 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3719
3720 vcpu_load(vcpu);
3721
3722 memcpy(fxsave->st_space, fpu->fpr, 128);
3723 fxsave->cwd = fpu->fcw;
3724 fxsave->swd = fpu->fsw;
3725 fxsave->twd = fpu->ftwx;
3726 fxsave->fop = fpu->last_opcode;
3727 fxsave->rip = fpu->last_ip;
3728 fxsave->rdp = fpu->last_dp;
3729 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3730
3731 vcpu_put(vcpu);
3732
3733 return 0;
3734}
3735
3736void fx_init(struct kvm_vcpu *vcpu)
3737{
3738 unsigned after_mxcsr_mask;
3739
bc1a34f1
AA		 3740 /*
3741 * Touch the fpu the first time in non atomic context as if
3742 * this is the first fpu instruction the exception handler
3743 * will fire before the instruction returns and it'll have to
3744 * allocate ram with GFP_KERNEL.
3745 */
3746 if (!used_math())
d6e88aec 3747 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 3748
d0752060
HB		 3749 /* Initialize guest FPU by resetting ours and saving into guest's */
3750 preempt_disable();
d6e88aec
AK		 3751 kvm_fx_save(&vcpu->arch.host_fx_image);
3752 kvm_fx_finit();
3753 kvm_fx_save(&vcpu->arch.guest_fx_image);
3754 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 3755 preempt_enable();
3756
ad312c7c 3757 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 3758 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 3759 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
3760 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 3761 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
3762}
3763EXPORT_SYMBOL_GPL(fx_init);
3764
3765void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
3766{
3767 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
3768 return;
3769
3770 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 3771 kvm_fx_save(&vcpu->arch.host_fx_image);
3772 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 3773}
3774EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
3775
3776void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
3777{
3778 if (!vcpu->guest_fpu_loaded)
3779 return;
3780
3781 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 3782 kvm_fx_save(&vcpu->arch.guest_fx_image);
3783 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 3784 ++vcpu->stat.fpu_reload;
d0752060
HB		 3785}
3786EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 3787
3788void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
3789{
3790 kvm_x86_ops->vcpu_free(vcpu);
3791}
3792
3793struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
3794 unsigned int id)
3795{
26e5215f
AK		 3796 return kvm_x86_ops->vcpu_create(kvm, id);
3797}
e9b11c17 3798
26e5215f
AK		 3799int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
3800{
3801 int r;
e9b11c17
ZX		 3802
3803 /* We do fxsave: this must be aligned. */
ad312c7c 3804 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17
ZX		 3805
3806 vcpu_load(vcpu);
3807 r = kvm_arch_vcpu_reset(vcpu);
3808 if (r == 0)
3809 r = kvm_mmu_setup(vcpu);
3810 vcpu_put(vcpu);
3811 if (r < 0)
3812 goto free_vcpu;
3813
26e5215f 3814 return 0;
e9b11c17
ZX		 3815free_vcpu:
3816 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 3817 return r;
e9b11c17
ZX		 3818}
3819
d40ccc62 3820void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 3821{
3822 vcpu_load(vcpu);
3823 kvm_mmu_unload(vcpu);
3824 vcpu_put(vcpu);
3825
3826 kvm_x86_ops->vcpu_free(vcpu);
3827}
3828
3829int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
3830{
3831 return kvm_x86_ops->vcpu_reset(vcpu);
3832}
3833
3834void kvm_arch_hardware_enable(void *garbage)
3835{
3836 kvm_x86_ops->hardware_enable(garbage);
3837}
3838
3839void kvm_arch_hardware_disable(void *garbage)
3840{
3841 kvm_x86_ops->hardware_disable(garbage);
3842}
3843
3844int kvm_arch_hardware_setup(void)
3845{
3846 return kvm_x86_ops->hardware_setup();
3847}
3848
3849void kvm_arch_hardware_unsetup(void)
3850{
3851 kvm_x86_ops->hardware_unsetup();
3852}
3853
3854void kvm_arch_check_processor_compat(void *rtn)
3855{
3856 kvm_x86_ops->check_processor_compatibility(rtn);
3857}
3858
3859int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
3860{
3861 struct page *page;
3862 struct kvm *kvm;
3863 int r;
3864
3865 BUG_ON(vcpu->kvm == NULL);
3866 kvm = vcpu->kvm;
3867
ad312c7c 3868 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 3869 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 3870 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 3871 else
a4535290 3872 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 3873
3874 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
3875 if (!page) {
3876 r = -ENOMEM;
3877 goto fail;
3878 }
ad312c7c 3879 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 3880
3881 r = kvm_mmu_create(vcpu);
3882 if (r < 0)
3883 goto fail_free_pio_data;
3884
3885 if (irqchip_in_kernel(kvm)) {
3886 r = kvm_create_lapic(vcpu);
3887 if (r < 0)
3888 goto fail_mmu_destroy;
3889 }
3890
3891 return 0;
3892
3893fail_mmu_destroy:
3894 kvm_mmu_destroy(vcpu);
3895fail_free_pio_data:
ad312c7c 3896 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 3897fail:
3898 return r;
3899}
3900
3901void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
3902{
3903 kvm_free_lapic(vcpu);
3200f405 3904 down_read(&vcpu->kvm->slots_lock);
e9b11c17 3905 kvm_mmu_destroy(vcpu);
3200f405 3906 up_read(&vcpu->kvm->slots_lock);
ad312c7c 3907 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 3908}
d19a9cd2
ZX		 3909
3910struct kvm *kvm_arch_create_vm(void)
3911{
3912 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
3913
3914 if (!kvm)
3915 return ERR_PTR(-ENOMEM);
3916
f05e70ac 3917 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
d19a9cd2
ZX		 3918
3919 return kvm;
3920}
3921
3922static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
3923{
3924 vcpu_load(vcpu);
3925 kvm_mmu_unload(vcpu);
3926 vcpu_put(vcpu);
3927}
3928
3929static void kvm_free_vcpus(struct kvm *kvm)
3930{
3931 unsigned int i;
3932
3933 /*
3934 * Unpin any mmu pages first.
3935 */
3936 for (i = 0; i < KVM_MAX_VCPUS; ++i)
3937 if (kvm->vcpus[i])
3938 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
3939 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
3940 if (kvm->vcpus[i]) {
3941 kvm_arch_vcpu_free(kvm->vcpus[i]);
3942 kvm->vcpus[i] = NULL;
3943 }
3944 }
3945
3946}
3947
3948void kvm_arch_destroy_vm(struct kvm *kvm)
3949{
7837699f 3950 kvm_free_pit(kvm);
d7deeeb0
ZX		 3951 kfree(kvm->arch.vpic);
3952 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 3953 kvm_free_vcpus(kvm);
3954 kvm_free_physmem(kvm);
3d45830c
AK		 3955 if (kvm->arch.apic_access_page)
3956 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 3957 if (kvm->arch.ept_identity_pagetable)
3958 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 3959 kfree(kvm);
3960}
0de10343
ZX		 3961
3962int kvm_arch_set_memory_region(struct kvm *kvm,
3963 struct kvm_userspace_memory_region *mem,
3964 struct kvm_memory_slot old,
3965 int user_alloc)
3966{
3967 int npages = mem->memory_size >> PAGE_SHIFT;
3968 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
3969
3970 /*To keep backward compatibility with older userspace,
3971 *x86 needs to hanlde !user_alloc case.
3972 */
3973 if (!user_alloc) {
3974 if (npages && !old.rmap) {
72dc67a6 3975 down_write(&current->mm->mmap_sem);
0de10343
ZX		 3976 memslot->userspace_addr = do_mmap(NULL, 0,
3977 npages * PAGE_SIZE,
3978 PROT_READ | PROT_WRITE,
3979 MAP_SHARED | MAP_ANONYMOUS,
3980 0);
72dc67a6 3981 up_write(&current->mm->mmap_sem);
0de10343
ZX		 3982
3983 if (IS_ERR((void *)memslot->userspace_addr))
3984 return PTR_ERR((void *)memslot->userspace_addr);
3985 } else {
3986 if (!old.user_alloc && old.rmap) {
3987 int ret;
3988
72dc67a6 3989 down_write(&current->mm->mmap_sem);
0de10343
ZX		 3990 ret = do_munmap(current->mm, old.userspace_addr,
3991 old.npages * PAGE_SIZE);
72dc67a6 3992 up_write(&current->mm->mmap_sem);
0de10343
ZX		 3993 if (ret < 0)
3994 printk(KERN_WARNING
3995 "kvm_vm_ioctl_set_memory_region: "
3996 "failed to munmap memory\n");
3997 }
3998 }
3999 }
4000
f05e70ac 4001 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4002 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4003 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4004 }
4005
4006 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4007 kvm_flush_remote_tlbs(kvm);
4008
4009 return 0;
4010}
1d737c8a 4011
34d4cb8f
MT		 4012void kvm_arch_flush_shadow(struct kvm *kvm)
4013{
4014 kvm_mmu_zap_all(kvm);
4015}
4016
1d737c8a
ZX		 4017int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4018{
a4535290
AK		 4019 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
4020 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED;
1d737c8a 4021}
5736199a
ZX		 4022
4023static void vcpu_kick_intr(void *info)
4024{
4025#ifdef DEBUG
4026 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4027 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4028#endif
4029}
4030
4031void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4032{
4033 int ipi_pcpu = vcpu->cpu;
e9571ed5 4034 int cpu = get_cpu();
5736199a
ZX		 4035
4036 if (waitqueue_active(&vcpu->wq)) {
4037 wake_up_interruptible(&vcpu->wq);
4038 ++vcpu->stat.halt_wakeup;
4039 }
e9571ed5
MT		 4040 /*
4041 * We may be called synchronously with irqs disabled in guest mode,
4042 * So need not to call smp_call_function_single() in that case.
4043 */
4044 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4045 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4046 put_cpu();
5736199a 4047}
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