]>
Commit | Line | Data |
---|---|---|
043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
313a3dc7 | 29 | |
18068523 | 30 | #include <linux/clocksource.h> |
4d5c5d0f | 31 | #include <linux/interrupt.h> |
313a3dc7 CO |
32 | #include <linux/kvm.h> |
33 | #include <linux/fs.h> | |
34 | #include <linux/vmalloc.h> | |
5fb76f9b | 35 | #include <linux/module.h> |
0de10343 | 36 | #include <linux/mman.h> |
2bacc55c | 37 | #include <linux/highmem.h> |
19de40a8 | 38 | #include <linux/iommu.h> |
62c476c7 | 39 | #include <linux/intel-iommu.h> |
c8076604 | 40 | #include <linux/cpufreq.h> |
18863bdd | 41 | #include <linux/user-return-notifier.h> |
a983fb23 | 42 | #include <linux/srcu.h> |
5a0e3ad6 | 43 | #include <linux/slab.h> |
ff9d07a0 | 44 | #include <linux/perf_event.h> |
7bee342a | 45 | #include <linux/uaccess.h> |
af585b92 | 46 | #include <linux/hash.h> |
aec51dc4 | 47 | #include <trace/events/kvm.h> |
2ed152af | 48 | |
229456fc MT |
49 | #define CREATE_TRACE_POINTS |
50 | #include "trace.h" | |
043405e1 | 51 | |
24f1e32c | 52 | #include <asm/debugreg.h> |
d825ed0a | 53 | #include <asm/msr.h> |
a5f61300 | 54 | #include <asm/desc.h> |
0bed3b56 | 55 | #include <asm/mtrr.h> |
890ca9ae | 56 | #include <asm/mce.h> |
7cf30855 | 57 | #include <asm/i387.h> |
98918833 | 58 | #include <asm/xcr.h> |
1d5f066e | 59 | #include <asm/pvclock.h> |
217fc9cf | 60 | #include <asm/div64.h> |
043405e1 | 61 | |
313a3dc7 | 62 | #define MAX_IO_MSRS 256 |
a03490ed CO |
63 | #define CR0_RESERVED_BITS \ |
64 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
65 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
66 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
67 | #define CR4_RESERVED_BITS \ | |
68 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
69 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
70 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
2acf923e | 71 | | X86_CR4_OSXSAVE \ |
a03490ed CO |
72 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) |
73 | ||
74 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
890ca9ae HY |
75 | |
76 | #define KVM_MAX_MCE_BANKS 32 | |
5854dbca | 77 | #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) |
890ca9ae | 78 | |
50a37eb4 JR |
79 | /* EFER defaults: |
80 | * - enable syscall per default because its emulated by KVM | |
81 | * - enable LME and LMA per default on 64 bit KVM | |
82 | */ | |
83 | #ifdef CONFIG_X86_64 | |
84 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL; | |
85 | #else | |
86 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL; | |
87 | #endif | |
313a3dc7 | 88 | |
ba1389b7 AK |
89 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
90 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 91 | |
cb142eb7 | 92 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
674eea0f AK |
93 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
94 | struct kvm_cpuid_entry2 __user *entries); | |
95 | ||
97896d04 | 96 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 97 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 98 | |
ed85c068 AP |
99 | int ignore_msrs = 0; |
100 | module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
101 | ||
18863bdd AK |
102 | #define KVM_NR_SHARED_MSRS 16 |
103 | ||
104 | struct kvm_shared_msrs_global { | |
105 | int nr; | |
2bf78fa7 | 106 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
107 | }; |
108 | ||
109 | struct kvm_shared_msrs { | |
110 | struct user_return_notifier urn; | |
111 | bool registered; | |
2bf78fa7 SY |
112 | struct kvm_shared_msr_values { |
113 | u64 host; | |
114 | u64 curr; | |
115 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
116 | }; |
117 | ||
118 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
119 | static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs); | |
120 | ||
417bc304 | 121 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
122 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
123 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
124 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
125 | { "invlpg", VCPU_STAT(invlpg) }, | |
126 | { "exits", VCPU_STAT(exits) }, | |
127 | { "io_exits", VCPU_STAT(io_exits) }, | |
128 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
129 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
130 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 131 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 AK |
132 | { "halt_exits", VCPU_STAT(halt_exits) }, |
133 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 134 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
135 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
136 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
137 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
138 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
139 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
140 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
141 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 142 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 143 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
144 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
145 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
146 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
147 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
148 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
149 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 150 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 151 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 152 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 153 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
154 | { NULL } |
155 | }; | |
156 | ||
2acf923e DC |
157 | u64 __read_mostly host_xcr0; |
158 | ||
af585b92 GN |
159 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
160 | { | |
161 | int i; | |
162 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
163 | vcpu->arch.apf.gfns[i] = ~0; | |
164 | } | |
165 | ||
18863bdd AK |
166 | static void kvm_on_user_return(struct user_return_notifier *urn) |
167 | { | |
168 | unsigned slot; | |
18863bdd AK |
169 | struct kvm_shared_msrs *locals |
170 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 171 | struct kvm_shared_msr_values *values; |
18863bdd AK |
172 | |
173 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
174 | values = &locals->values[slot]; |
175 | if (values->host != values->curr) { | |
176 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
177 | values->curr = values->host; | |
18863bdd AK |
178 | } |
179 | } | |
180 | locals->registered = false; | |
181 | user_return_notifier_unregister(urn); | |
182 | } | |
183 | ||
2bf78fa7 | 184 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 185 | { |
2bf78fa7 | 186 | struct kvm_shared_msrs *smsr; |
18863bdd AK |
187 | u64 value; |
188 | ||
2bf78fa7 SY |
189 | smsr = &__get_cpu_var(shared_msrs); |
190 | /* only read, and nobody should modify it at this time, | |
191 | * so don't need lock */ | |
192 | if (slot >= shared_msrs_global.nr) { | |
193 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
194 | return; | |
195 | } | |
196 | rdmsrl_safe(msr, &value); | |
197 | smsr->values[slot].host = value; | |
198 | smsr->values[slot].curr = value; | |
199 | } | |
200 | ||
201 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
202 | { | |
18863bdd AK |
203 | if (slot >= shared_msrs_global.nr) |
204 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
205 | shared_msrs_global.msrs[slot] = msr; |
206 | /* we need ensured the shared_msr_global have been updated */ | |
207 | smp_wmb(); | |
18863bdd AK |
208 | } |
209 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
210 | ||
211 | static void kvm_shared_msr_cpu_online(void) | |
212 | { | |
213 | unsigned i; | |
18863bdd AK |
214 | |
215 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 216 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
217 | } |
218 | ||
d5696725 | 219 | void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd AK |
220 | { |
221 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
222 | ||
2bf78fa7 | 223 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
18863bdd | 224 | return; |
2bf78fa7 SY |
225 | smsr->values[slot].curr = value; |
226 | wrmsrl(shared_msrs_global.msrs[slot], value); | |
18863bdd AK |
227 | if (!smsr->registered) { |
228 | smsr->urn.on_user_return = kvm_on_user_return; | |
229 | user_return_notifier_register(&smsr->urn); | |
230 | smsr->registered = true; | |
231 | } | |
232 | } | |
233 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
234 | ||
3548bab5 AK |
235 | static void drop_user_return_notifiers(void *ignore) |
236 | { | |
237 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
238 | ||
239 | if (smsr->registered) | |
240 | kvm_on_user_return(&smsr->urn); | |
241 | } | |
242 | ||
6866b83e CO |
243 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
244 | { | |
245 | if (irqchip_in_kernel(vcpu->kvm)) | |
ad312c7c | 246 | return vcpu->arch.apic_base; |
6866b83e | 247 | else |
ad312c7c | 248 | return vcpu->arch.apic_base; |
6866b83e CO |
249 | } |
250 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
251 | ||
252 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
253 | { | |
254 | /* TODO: reserve bits check */ | |
255 | if (irqchip_in_kernel(vcpu->kvm)) | |
256 | kvm_lapic_set_base(vcpu, data); | |
257 | else | |
ad312c7c | 258 | vcpu->arch.apic_base = data; |
6866b83e CO |
259 | } |
260 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
261 | ||
3fd28fce ED |
262 | #define EXCPT_BENIGN 0 |
263 | #define EXCPT_CONTRIBUTORY 1 | |
264 | #define EXCPT_PF 2 | |
265 | ||
266 | static int exception_class(int vector) | |
267 | { | |
268 | switch (vector) { | |
269 | case PF_VECTOR: | |
270 | return EXCPT_PF; | |
271 | case DE_VECTOR: | |
272 | case TS_VECTOR: | |
273 | case NP_VECTOR: | |
274 | case SS_VECTOR: | |
275 | case GP_VECTOR: | |
276 | return EXCPT_CONTRIBUTORY; | |
277 | default: | |
278 | break; | |
279 | } | |
280 | return EXCPT_BENIGN; | |
281 | } | |
282 | ||
283 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, | |
ce7ddec4 JR |
284 | unsigned nr, bool has_error, u32 error_code, |
285 | bool reinject) | |
3fd28fce ED |
286 | { |
287 | u32 prev_nr; | |
288 | int class1, class2; | |
289 | ||
3842d135 AK |
290 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
291 | ||
3fd28fce ED |
292 | if (!vcpu->arch.exception.pending) { |
293 | queue: | |
294 | vcpu->arch.exception.pending = true; | |
295 | vcpu->arch.exception.has_error_code = has_error; | |
296 | vcpu->arch.exception.nr = nr; | |
297 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 298 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
299 | return; |
300 | } | |
301 | ||
302 | /* to check exception */ | |
303 | prev_nr = vcpu->arch.exception.nr; | |
304 | if (prev_nr == DF_VECTOR) { | |
305 | /* triple fault -> shutdown */ | |
a8eeb04a | 306 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
307 | return; |
308 | } | |
309 | class1 = exception_class(prev_nr); | |
310 | class2 = exception_class(nr); | |
311 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
312 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
313 | /* generate double fault per SDM Table 5-5 */ | |
314 | vcpu->arch.exception.pending = true; | |
315 | vcpu->arch.exception.has_error_code = true; | |
316 | vcpu->arch.exception.nr = DF_VECTOR; | |
317 | vcpu->arch.exception.error_code = 0; | |
318 | } else | |
319 | /* replace previous exception with a new one in a hope | |
320 | that instruction re-execution will regenerate lost | |
321 | exception */ | |
322 | goto queue; | |
323 | } | |
324 | ||
298101da AK |
325 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
326 | { | |
ce7ddec4 | 327 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
328 | } |
329 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
330 | ||
ce7ddec4 JR |
331 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
332 | { | |
333 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
334 | } | |
335 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
336 | ||
db8fcefa | 337 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 338 | { |
db8fcefa AP |
339 | if (err) |
340 | kvm_inject_gp(vcpu, 0); | |
341 | else | |
342 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
343 | } | |
344 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 345 | |
6389ee94 | 346 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
347 | { |
348 | ++vcpu->stat.pf_guest; | |
6389ee94 AK |
349 | vcpu->arch.cr2 = fault->address; |
350 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); | |
c3c91fee AK |
351 | } |
352 | ||
6389ee94 | 353 | void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 354 | { |
6389ee94 AK |
355 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
356 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 357 | else |
6389ee94 | 358 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
d4f8cf66 JR |
359 | } |
360 | ||
3419ffc8 SY |
361 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
362 | { | |
f8636849 | 363 | kvm_make_request(KVM_REQ_NMI, vcpu); |
3842d135 | 364 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3419ffc8 SY |
365 | } |
366 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
367 | ||
298101da AK |
368 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
369 | { | |
ce7ddec4 | 370 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
371 | } |
372 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
373 | ||
ce7ddec4 JR |
374 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
375 | { | |
376 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
377 | } | |
378 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
379 | ||
0a79b009 AK |
380 | /* |
381 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
382 | * a #GP and return false. | |
383 | */ | |
384 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 385 | { |
0a79b009 AK |
386 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
387 | return true; | |
388 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
389 | return false; | |
298101da | 390 | } |
0a79b009 | 391 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 392 | |
ec92fe44 JR |
393 | /* |
394 | * This function will be used to read from the physical memory of the currently | |
395 | * running guest. The difference to kvm_read_guest_page is that this function | |
396 | * can read from guest physical or from the guest's guest physical memory. | |
397 | */ | |
398 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
399 | gfn_t ngfn, void *data, int offset, int len, | |
400 | u32 access) | |
401 | { | |
402 | gfn_t real_gfn; | |
403 | gpa_t ngpa; | |
404 | ||
405 | ngpa = gfn_to_gpa(ngfn); | |
406 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access); | |
407 | if (real_gfn == UNMAPPED_GVA) | |
408 | return -EFAULT; | |
409 | ||
410 | real_gfn = gpa_to_gfn(real_gfn); | |
411 | ||
412 | return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); | |
413 | } | |
414 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
415 | ||
3d06b8bf JR |
416 | int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
417 | void *data, int offset, int len, u32 access) | |
418 | { | |
419 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
420 | data, offset, len, access); | |
421 | } | |
422 | ||
a03490ed CO |
423 | /* |
424 | * Load the pae pdptrs. Return true is they are all valid. | |
425 | */ | |
ff03a073 | 426 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
427 | { |
428 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
429 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
430 | int i; | |
431 | int ret; | |
ff03a073 | 432 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 433 | |
ff03a073 JR |
434 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
435 | offset * sizeof(u64), sizeof(pdpte), | |
436 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
437 | if (ret < 0) { |
438 | ret = 0; | |
439 | goto out; | |
440 | } | |
441 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 442 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 443 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
444 | ret = 0; |
445 | goto out; | |
446 | } | |
447 | } | |
448 | ret = 1; | |
449 | ||
ff03a073 | 450 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
451 | __set_bit(VCPU_EXREG_PDPTR, |
452 | (unsigned long *)&vcpu->arch.regs_avail); | |
453 | __set_bit(VCPU_EXREG_PDPTR, | |
454 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 455 | out: |
a03490ed CO |
456 | |
457 | return ret; | |
458 | } | |
cc4b6871 | 459 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 460 | |
d835dfec AK |
461 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
462 | { | |
ff03a073 | 463 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 464 | bool changed = true; |
3d06b8bf JR |
465 | int offset; |
466 | gfn_t gfn; | |
d835dfec AK |
467 | int r; |
468 | ||
469 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
470 | return false; | |
471 | ||
6de4f3ad AK |
472 | if (!test_bit(VCPU_EXREG_PDPTR, |
473 | (unsigned long *)&vcpu->arch.regs_avail)) | |
474 | return true; | |
475 | ||
9f8fe504 AK |
476 | gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; |
477 | offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
478 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
479 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
480 | if (r < 0) |
481 | goto out; | |
ff03a073 | 482 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 483 | out: |
d835dfec AK |
484 | |
485 | return changed; | |
486 | } | |
487 | ||
49a9b07e | 488 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 489 | { |
aad82703 SY |
490 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
491 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | | |
492 | X86_CR0_CD | X86_CR0_NW; | |
493 | ||
f9a48e6a AK |
494 | cr0 |= X86_CR0_ET; |
495 | ||
ab344828 | 496 | #ifdef CONFIG_X86_64 |
0f12244f GN |
497 | if (cr0 & 0xffffffff00000000UL) |
498 | return 1; | |
ab344828 GN |
499 | #endif |
500 | ||
501 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 502 | |
0f12244f GN |
503 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
504 | return 1; | |
a03490ed | 505 | |
0f12244f GN |
506 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
507 | return 1; | |
a03490ed CO |
508 | |
509 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
510 | #ifdef CONFIG_X86_64 | |
f6801dff | 511 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
512 | int cs_db, cs_l; |
513 | ||
0f12244f GN |
514 | if (!is_pae(vcpu)) |
515 | return 1; | |
a03490ed | 516 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
517 | if (cs_l) |
518 | return 1; | |
a03490ed CO |
519 | } else |
520 | #endif | |
ff03a073 | 521 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 522 | kvm_read_cr3(vcpu))) |
0f12244f | 523 | return 1; |
a03490ed CO |
524 | } |
525 | ||
526 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
a03490ed | 527 | |
e5f3f027 XG |
528 | if ((cr0 ^ old_cr0) & X86_CR0_PG) |
529 | kvm_clear_async_pf_completion_queue(vcpu); | |
530 | ||
aad82703 SY |
531 | if ((cr0 ^ old_cr0) & update_bits) |
532 | kvm_mmu_reset_context(vcpu); | |
0f12244f GN |
533 | return 0; |
534 | } | |
2d3ad1f4 | 535 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 536 | |
2d3ad1f4 | 537 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 538 | { |
49a9b07e | 539 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 540 | } |
2d3ad1f4 | 541 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 542 | |
2acf923e DC |
543 | int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
544 | { | |
545 | u64 xcr0; | |
546 | ||
547 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
548 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
549 | return 1; | |
550 | xcr0 = xcr; | |
551 | if (kvm_x86_ops->get_cpl(vcpu) != 0) | |
552 | return 1; | |
553 | if (!(xcr0 & XSTATE_FP)) | |
554 | return 1; | |
555 | if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) | |
556 | return 1; | |
557 | if (xcr0 & ~host_xcr0) | |
558 | return 1; | |
559 | vcpu->arch.xcr0 = xcr0; | |
560 | vcpu->guest_xcr0_loaded = 0; | |
561 | return 0; | |
562 | } | |
563 | ||
564 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
565 | { | |
566 | if (__kvm_set_xcr(vcpu, index, xcr)) { | |
567 | kvm_inject_gp(vcpu, 0); | |
568 | return 1; | |
569 | } | |
570 | return 0; | |
571 | } | |
572 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
573 | ||
574 | static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu) | |
575 | { | |
576 | struct kvm_cpuid_entry2 *best; | |
577 | ||
578 | best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
579 | return best && (best->ecx & bit(X86_FEATURE_XSAVE)); | |
580 | } | |
581 | ||
582 | static void update_cpuid(struct kvm_vcpu *vcpu) | |
583 | { | |
584 | struct kvm_cpuid_entry2 *best; | |
585 | ||
586 | best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
587 | if (!best) | |
588 | return; | |
589 | ||
590 | /* Update OSXSAVE bit */ | |
591 | if (cpu_has_xsave && best->function == 0x1) { | |
592 | best->ecx &= ~(bit(X86_FEATURE_OSXSAVE)); | |
593 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) | |
594 | best->ecx |= bit(X86_FEATURE_OSXSAVE); | |
595 | } | |
596 | } | |
597 | ||
a83b29c6 | 598 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 599 | { |
fc78f519 | 600 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
a2edf57f AK |
601 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE; |
602 | ||
0f12244f GN |
603 | if (cr4 & CR4_RESERVED_BITS) |
604 | return 1; | |
a03490ed | 605 | |
2acf923e DC |
606 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
607 | return 1; | |
608 | ||
a03490ed | 609 | if (is_long_mode(vcpu)) { |
0f12244f GN |
610 | if (!(cr4 & X86_CR4_PAE)) |
611 | return 1; | |
a2edf57f AK |
612 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
613 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
614 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
615 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
616 | return 1; |
617 | ||
618 | if (cr4 & X86_CR4_VMXE) | |
619 | return 1; | |
a03490ed | 620 | |
a03490ed | 621 | kvm_x86_ops->set_cr4(vcpu, cr4); |
62ad0755 | 622 | |
aad82703 SY |
623 | if ((cr4 ^ old_cr4) & pdptr_bits) |
624 | kvm_mmu_reset_context(vcpu); | |
0f12244f | 625 | |
2acf923e DC |
626 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) |
627 | update_cpuid(vcpu); | |
628 | ||
0f12244f GN |
629 | return 0; |
630 | } | |
2d3ad1f4 | 631 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 632 | |
2390218b | 633 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 634 | { |
9f8fe504 | 635 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
0ba73cda | 636 | kvm_mmu_sync_roots(vcpu); |
d835dfec | 637 | kvm_mmu_flush_tlb(vcpu); |
0f12244f | 638 | return 0; |
d835dfec AK |
639 | } |
640 | ||
a03490ed | 641 | if (is_long_mode(vcpu)) { |
0f12244f GN |
642 | if (cr3 & CR3_L_MODE_RESERVED_BITS) |
643 | return 1; | |
a03490ed CO |
644 | } else { |
645 | if (is_pae(vcpu)) { | |
0f12244f GN |
646 | if (cr3 & CR3_PAE_RESERVED_BITS) |
647 | return 1; | |
ff03a073 JR |
648 | if (is_paging(vcpu) && |
649 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
0f12244f | 650 | return 1; |
a03490ed CO |
651 | } |
652 | /* | |
653 | * We don't check reserved bits in nonpae mode, because | |
654 | * this isn't enforced, and VMware depends on this. | |
655 | */ | |
656 | } | |
657 | ||
a03490ed CO |
658 | /* |
659 | * Does the new cr3 value map to physical memory? (Note, we | |
660 | * catch an invalid cr3 even in real-mode, because it would | |
661 | * cause trouble later on when we turn on paging anyway.) | |
662 | * | |
663 | * A real CPU would silently accept an invalid cr3 and would | |
664 | * attempt to use it - with largely undefined (and often hard | |
665 | * to debug) behavior on the guest side. | |
666 | */ | |
667 | if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT))) | |
0f12244f GN |
668 | return 1; |
669 | vcpu->arch.cr3 = cr3; | |
aff48baa | 670 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
0f12244f GN |
671 | vcpu->arch.mmu.new_cr3(vcpu); |
672 | return 0; | |
673 | } | |
2d3ad1f4 | 674 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 675 | |
eea1cff9 | 676 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 677 | { |
0f12244f GN |
678 | if (cr8 & CR8_RESERVED_BITS) |
679 | return 1; | |
a03490ed CO |
680 | if (irqchip_in_kernel(vcpu->kvm)) |
681 | kvm_lapic_set_tpr(vcpu, cr8); | |
682 | else | |
ad312c7c | 683 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
684 | return 0; |
685 | } | |
2d3ad1f4 | 686 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 687 | |
2d3ad1f4 | 688 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
689 | { |
690 | if (irqchip_in_kernel(vcpu->kvm)) | |
691 | return kvm_lapic_get_cr8(vcpu); | |
692 | else | |
ad312c7c | 693 | return vcpu->arch.cr8; |
a03490ed | 694 | } |
2d3ad1f4 | 695 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 696 | |
338dbc97 | 697 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
698 | { |
699 | switch (dr) { | |
700 | case 0 ... 3: | |
701 | vcpu->arch.db[dr] = val; | |
702 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
703 | vcpu->arch.eff_db[dr] = val; | |
704 | break; | |
705 | case 4: | |
338dbc97 GN |
706 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
707 | return 1; /* #UD */ | |
020df079 GN |
708 | /* fall through */ |
709 | case 6: | |
338dbc97 GN |
710 | if (val & 0xffffffff00000000ULL) |
711 | return -1; /* #GP */ | |
020df079 GN |
712 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1; |
713 | break; | |
714 | case 5: | |
338dbc97 GN |
715 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
716 | return 1; /* #UD */ | |
020df079 GN |
717 | /* fall through */ |
718 | default: /* 7 */ | |
338dbc97 GN |
719 | if (val & 0xffffffff00000000ULL) |
720 | return -1; /* #GP */ | |
020df079 GN |
721 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
722 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
723 | kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7); | |
724 | vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK); | |
725 | } | |
726 | break; | |
727 | } | |
728 | ||
729 | return 0; | |
730 | } | |
338dbc97 GN |
731 | |
732 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
733 | { | |
734 | int res; | |
735 | ||
736 | res = __kvm_set_dr(vcpu, dr, val); | |
737 | if (res > 0) | |
738 | kvm_queue_exception(vcpu, UD_VECTOR); | |
739 | else if (res < 0) | |
740 | kvm_inject_gp(vcpu, 0); | |
741 | ||
742 | return res; | |
743 | } | |
020df079 GN |
744 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
745 | ||
338dbc97 | 746 | static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
747 | { |
748 | switch (dr) { | |
749 | case 0 ... 3: | |
750 | *val = vcpu->arch.db[dr]; | |
751 | break; | |
752 | case 4: | |
338dbc97 | 753 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 754 | return 1; |
020df079 GN |
755 | /* fall through */ |
756 | case 6: | |
757 | *val = vcpu->arch.dr6; | |
758 | break; | |
759 | case 5: | |
338dbc97 | 760 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 761 | return 1; |
020df079 GN |
762 | /* fall through */ |
763 | default: /* 7 */ | |
764 | *val = vcpu->arch.dr7; | |
765 | break; | |
766 | } | |
767 | ||
768 | return 0; | |
769 | } | |
338dbc97 GN |
770 | |
771 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) | |
772 | { | |
773 | if (_kvm_get_dr(vcpu, dr, val)) { | |
774 | kvm_queue_exception(vcpu, UD_VECTOR); | |
775 | return 1; | |
776 | } | |
777 | return 0; | |
778 | } | |
020df079 GN |
779 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
780 | ||
043405e1 CO |
781 | /* |
782 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
783 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
784 | * | |
785 | * This list is modified at module load time to reflect the | |
e3267cbb GC |
786 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
787 | * kvm-specific. Those are put in the beginning of the list. | |
043405e1 | 788 | */ |
e3267cbb | 789 | |
344d9588 | 790 | #define KVM_SAVE_MSRS_BEGIN 8 |
043405e1 | 791 | static u32 msrs_to_save[] = { |
e3267cbb | 792 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
11c6bffa | 793 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, |
55cd8e5a | 794 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, |
344d9588 | 795 | HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, |
043405e1 | 796 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 797 | MSR_STAR, |
043405e1 CO |
798 | #ifdef CONFIG_X86_64 |
799 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
800 | #endif | |
e90aa41e | 801 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA |
043405e1 CO |
802 | }; |
803 | ||
804 | static unsigned num_msrs_to_save; | |
805 | ||
806 | static u32 emulated_msrs[] = { | |
807 | MSR_IA32_MISC_ENABLE, | |
908e75f3 AK |
808 | MSR_IA32_MCG_STATUS, |
809 | MSR_IA32_MCG_CTL, | |
043405e1 CO |
810 | }; |
811 | ||
b69e8cae | 812 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 813 | { |
aad82703 SY |
814 | u64 old_efer = vcpu->arch.efer; |
815 | ||
b69e8cae RJ |
816 | if (efer & efer_reserved_bits) |
817 | return 1; | |
15c4a640 CO |
818 | |
819 | if (is_paging(vcpu) | |
b69e8cae RJ |
820 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) |
821 | return 1; | |
15c4a640 | 822 | |
1b2fd70c AG |
823 | if (efer & EFER_FFXSR) { |
824 | struct kvm_cpuid_entry2 *feat; | |
825 | ||
826 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae RJ |
827 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
828 | return 1; | |
1b2fd70c AG |
829 | } |
830 | ||
d8017474 AG |
831 | if (efer & EFER_SVME) { |
832 | struct kvm_cpuid_entry2 *feat; | |
833 | ||
834 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae RJ |
835 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
836 | return 1; | |
d8017474 AG |
837 | } |
838 | ||
15c4a640 | 839 | efer &= ~EFER_LMA; |
f6801dff | 840 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 841 | |
a3d204e2 SY |
842 | kvm_x86_ops->set_efer(vcpu, efer); |
843 | ||
9645bb56 | 844 | vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled; |
b69e8cae | 845 | |
aad82703 SY |
846 | /* Update reserved bits */ |
847 | if ((efer ^ old_efer) & EFER_NX) | |
848 | kvm_mmu_reset_context(vcpu); | |
849 | ||
b69e8cae | 850 | return 0; |
15c4a640 CO |
851 | } |
852 | ||
f2b4b7dd JR |
853 | void kvm_enable_efer_bits(u64 mask) |
854 | { | |
855 | efer_reserved_bits &= ~mask; | |
856 | } | |
857 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
858 | ||
859 | ||
15c4a640 CO |
860 | /* |
861 | * Writes msr value into into the appropriate "register". | |
862 | * Returns 0 on success, non-0 otherwise. | |
863 | * Assumes vcpu_load() was already called. | |
864 | */ | |
865 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
866 | { | |
867 | return kvm_x86_ops->set_msr(vcpu, msr_index, data); | |
868 | } | |
869 | ||
313a3dc7 CO |
870 | /* |
871 | * Adapt set_msr() to msr_io()'s calling convention | |
872 | */ | |
873 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
874 | { | |
875 | return kvm_set_msr(vcpu, index, *data); | |
876 | } | |
877 | ||
18068523 GOC |
878 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
879 | { | |
9ed3c444 AK |
880 | int version; |
881 | int r; | |
50d0a0f9 | 882 | struct pvclock_wall_clock wc; |
923de3cf | 883 | struct timespec boot; |
18068523 GOC |
884 | |
885 | if (!wall_clock) | |
886 | return; | |
887 | ||
9ed3c444 AK |
888 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
889 | if (r) | |
890 | return; | |
891 | ||
892 | if (version & 1) | |
893 | ++version; /* first time write, random junk */ | |
894 | ||
895 | ++version; | |
18068523 | 896 | |
18068523 GOC |
897 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
898 | ||
50d0a0f9 GH |
899 | /* |
900 | * The guest calculates current wall clock time by adding | |
34c238a1 | 901 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
902 | * wall clock specified here. guest system time equals host |
903 | * system time for us, thus we must fill in host boot time here. | |
904 | */ | |
923de3cf | 905 | getboottime(&boot); |
50d0a0f9 GH |
906 | |
907 | wc.sec = boot.tv_sec; | |
908 | wc.nsec = boot.tv_nsec; | |
909 | wc.version = version; | |
18068523 GOC |
910 | |
911 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
912 | ||
913 | version++; | |
914 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
915 | } |
916 | ||
50d0a0f9 GH |
917 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
918 | { | |
919 | uint32_t quotient, remainder; | |
920 | ||
921 | /* Don't try to replace with do_div(), this one calculates | |
922 | * "(dividend << 32) / divisor" */ | |
923 | __asm__ ( "divl %4" | |
924 | : "=a" (quotient), "=d" (remainder) | |
925 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
926 | return quotient; | |
927 | } | |
928 | ||
5f4e3f88 ZA |
929 | static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, |
930 | s8 *pshift, u32 *pmultiplier) | |
50d0a0f9 | 931 | { |
5f4e3f88 | 932 | uint64_t scaled64; |
50d0a0f9 GH |
933 | int32_t shift = 0; |
934 | uint64_t tps64; | |
935 | uint32_t tps32; | |
936 | ||
5f4e3f88 ZA |
937 | tps64 = base_khz * 1000LL; |
938 | scaled64 = scaled_khz * 1000LL; | |
50933623 | 939 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
940 | tps64 >>= 1; |
941 | shift--; | |
942 | } | |
943 | ||
944 | tps32 = (uint32_t)tps64; | |
50933623 JK |
945 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
946 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
947 | scaled64 >>= 1; |
948 | else | |
949 | tps32 <<= 1; | |
50d0a0f9 GH |
950 | shift++; |
951 | } | |
952 | ||
5f4e3f88 ZA |
953 | *pshift = shift; |
954 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 | 955 | |
5f4e3f88 ZA |
956 | pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", |
957 | __func__, base_khz, scaled_khz, shift, *pmultiplier); | |
50d0a0f9 GH |
958 | } |
959 | ||
759379dd ZA |
960 | static inline u64 get_kernel_ns(void) |
961 | { | |
962 | struct timespec ts; | |
963 | ||
964 | WARN_ON(preemptible()); | |
965 | ktime_get_ts(&ts); | |
966 | monotonic_to_bootbased(&ts); | |
967 | return timespec_to_ns(&ts); | |
50d0a0f9 GH |
968 | } |
969 | ||
c8076604 | 970 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
c285545f | 971 | unsigned long max_tsc_khz; |
c8076604 | 972 | |
8cfdc000 ZA |
973 | static inline int kvm_tsc_changes_freq(void) |
974 | { | |
975 | int cpu = get_cpu(); | |
976 | int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) && | |
977 | cpufreq_quick_get(cpu) != 0; | |
978 | put_cpu(); | |
979 | return ret; | |
980 | } | |
981 | ||
759379dd ZA |
982 | static inline u64 nsec_to_cycles(u64 nsec) |
983 | { | |
217fc9cf AK |
984 | u64 ret; |
985 | ||
759379dd ZA |
986 | WARN_ON(preemptible()); |
987 | if (kvm_tsc_changes_freq()) | |
988 | printk_once(KERN_WARNING | |
989 | "kvm: unreliable cycle conversion on adjustable rate TSC\n"); | |
0a3aee0d | 990 | ret = nsec * __this_cpu_read(cpu_tsc_khz); |
217fc9cf AK |
991 | do_div(ret, USEC_PER_SEC); |
992 | return ret; | |
759379dd ZA |
993 | } |
994 | ||
c285545f ZA |
995 | static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz) |
996 | { | |
997 | /* Compute a scale to convert nanoseconds in TSC cycles */ | |
998 | kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, | |
999 | &kvm->arch.virtual_tsc_shift, | |
1000 | &kvm->arch.virtual_tsc_mult); | |
1001 | kvm->arch.virtual_tsc_khz = this_tsc_khz; | |
1002 | } | |
1003 | ||
1004 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1005 | { | |
1006 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec, | |
1007 | vcpu->kvm->arch.virtual_tsc_mult, | |
1008 | vcpu->kvm->arch.virtual_tsc_shift); | |
1009 | tsc += vcpu->arch.last_tsc_write; | |
1010 | return tsc; | |
1011 | } | |
1012 | ||
99e3e30a ZA |
1013 | void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data) |
1014 | { | |
1015 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1016 | u64 offset, ns, elapsed; |
99e3e30a | 1017 | unsigned long flags; |
46543ba4 | 1018 | s64 sdiff; |
99e3e30a ZA |
1019 | |
1020 | spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); | |
1021 | offset = data - native_read_tsc(); | |
759379dd | 1022 | ns = get_kernel_ns(); |
f38e098f | 1023 | elapsed = ns - kvm->arch.last_tsc_nsec; |
46543ba4 ZA |
1024 | sdiff = data - kvm->arch.last_tsc_write; |
1025 | if (sdiff < 0) | |
1026 | sdiff = -sdiff; | |
f38e098f ZA |
1027 | |
1028 | /* | |
46543ba4 | 1029 | * Special case: close write to TSC within 5 seconds of |
f38e098f | 1030 | * another CPU is interpreted as an attempt to synchronize |
46543ba4 ZA |
1031 | * The 5 seconds is to accomodate host load / swapping as |
1032 | * well as any reset of TSC during the boot process. | |
f38e098f ZA |
1033 | * |
1034 | * In that case, for a reliable TSC, we can match TSC offsets, | |
46543ba4 | 1035 | * or make a best guest using elapsed value. |
f38e098f | 1036 | */ |
46543ba4 ZA |
1037 | if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) && |
1038 | elapsed < 5ULL * NSEC_PER_SEC) { | |
f38e098f ZA |
1039 | if (!check_tsc_unstable()) { |
1040 | offset = kvm->arch.last_tsc_offset; | |
1041 | pr_debug("kvm: matched tsc offset for %llu\n", data); | |
1042 | } else { | |
759379dd ZA |
1043 | u64 delta = nsec_to_cycles(elapsed); |
1044 | offset += delta; | |
1045 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); | |
f38e098f ZA |
1046 | } |
1047 | ns = kvm->arch.last_tsc_nsec; | |
1048 | } | |
1049 | kvm->arch.last_tsc_nsec = ns; | |
1050 | kvm->arch.last_tsc_write = data; | |
1051 | kvm->arch.last_tsc_offset = offset; | |
99e3e30a ZA |
1052 | kvm_x86_ops->write_tsc_offset(vcpu, offset); |
1053 | spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
1054 | ||
1055 | /* Reset of TSC must disable overshoot protection below */ | |
1056 | vcpu->arch.hv_clock.tsc_timestamp = 0; | |
c285545f ZA |
1057 | vcpu->arch.last_tsc_write = data; |
1058 | vcpu->arch.last_tsc_nsec = ns; | |
99e3e30a ZA |
1059 | } |
1060 | EXPORT_SYMBOL_GPL(kvm_write_tsc); | |
1061 | ||
34c238a1 | 1062 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 1063 | { |
18068523 GOC |
1064 | unsigned long flags; |
1065 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
1066 | void *shared_kaddr; | |
463656c0 | 1067 | unsigned long this_tsc_khz; |
1d5f066e ZA |
1068 | s64 kernel_ns, max_kernel_ns; |
1069 | u64 tsc_timestamp; | |
18068523 | 1070 | |
18068523 GOC |
1071 | /* Keep irq disabled to prevent changes to the clock */ |
1072 | local_irq_save(flags); | |
1d5f066e | 1073 | kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp); |
759379dd | 1074 | kernel_ns = get_kernel_ns(); |
0a3aee0d | 1075 | this_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
18068523 | 1076 | |
8cfdc000 | 1077 | if (unlikely(this_tsc_khz == 0)) { |
c285545f | 1078 | local_irq_restore(flags); |
34c238a1 | 1079 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
8cfdc000 ZA |
1080 | return 1; |
1081 | } | |
18068523 | 1082 | |
c285545f ZA |
1083 | /* |
1084 | * We may have to catch up the TSC to match elapsed wall clock | |
1085 | * time for two reasons, even if kvmclock is used. | |
1086 | * 1) CPU could have been running below the maximum TSC rate | |
1087 | * 2) Broken TSC compensation resets the base at each VCPU | |
1088 | * entry to avoid unknown leaps of TSC even when running | |
1089 | * again on the same CPU. This may cause apparent elapsed | |
1090 | * time to disappear, and the guest to stand still or run | |
1091 | * very slowly. | |
1092 | */ | |
1093 | if (vcpu->tsc_catchup) { | |
1094 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
1095 | if (tsc > tsc_timestamp) { | |
1096 | kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp); | |
1097 | tsc_timestamp = tsc; | |
1098 | } | |
50d0a0f9 GH |
1099 | } |
1100 | ||
18068523 GOC |
1101 | local_irq_restore(flags); |
1102 | ||
c285545f ZA |
1103 | if (!vcpu->time_page) |
1104 | return 0; | |
18068523 | 1105 | |
1d5f066e ZA |
1106 | /* |
1107 | * Time as measured by the TSC may go backwards when resetting the base | |
1108 | * tsc_timestamp. The reason for this is that the TSC resolution is | |
1109 | * higher than the resolution of the other clock scales. Thus, many | |
1110 | * possible measurments of the TSC correspond to one measurement of any | |
1111 | * other clock, and so a spread of values is possible. This is not a | |
1112 | * problem for the computation of the nanosecond clock; with TSC rates | |
1113 | * around 1GHZ, there can only be a few cycles which correspond to one | |
1114 | * nanosecond value, and any path through this code will inevitably | |
1115 | * take longer than that. However, with the kernel_ns value itself, | |
1116 | * the precision may be much lower, down to HZ granularity. If the | |
1117 | * first sampling of TSC against kernel_ns ends in the low part of the | |
1118 | * range, and the second in the high end of the range, we can get: | |
1119 | * | |
1120 | * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new | |
1121 | * | |
1122 | * As the sampling errors potentially range in the thousands of cycles, | |
1123 | * it is possible such a time value has already been observed by the | |
1124 | * guest. To protect against this, we must compute the system time as | |
1125 | * observed by the guest and ensure the new system time is greater. | |
1126 | */ | |
1127 | max_kernel_ns = 0; | |
1128 | if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) { | |
1129 | max_kernel_ns = vcpu->last_guest_tsc - | |
1130 | vcpu->hv_clock.tsc_timestamp; | |
1131 | max_kernel_ns = pvclock_scale_delta(max_kernel_ns, | |
1132 | vcpu->hv_clock.tsc_to_system_mul, | |
1133 | vcpu->hv_clock.tsc_shift); | |
1134 | max_kernel_ns += vcpu->last_kernel_ns; | |
1135 | } | |
afbcf7ab | 1136 | |
e48672fa | 1137 | if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { |
5f4e3f88 ZA |
1138 | kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, |
1139 | &vcpu->hv_clock.tsc_shift, | |
1140 | &vcpu->hv_clock.tsc_to_system_mul); | |
e48672fa | 1141 | vcpu->hw_tsc_khz = this_tsc_khz; |
8cfdc000 ZA |
1142 | } |
1143 | ||
1d5f066e ZA |
1144 | if (max_kernel_ns > kernel_ns) |
1145 | kernel_ns = max_kernel_ns; | |
1146 | ||
8cfdc000 | 1147 | /* With all the info we got, fill in the values */ |
1d5f066e | 1148 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 1149 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
1d5f066e | 1150 | vcpu->last_kernel_ns = kernel_ns; |
28e4639a | 1151 | vcpu->last_guest_tsc = tsc_timestamp; |
371bcf64 GC |
1152 | vcpu->hv_clock.flags = 0; |
1153 | ||
18068523 GOC |
1154 | /* |
1155 | * The interface expects us to write an even number signaling that the | |
1156 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 1157 | * state, we just increase by 2 at the end. |
18068523 | 1158 | */ |
50d0a0f9 | 1159 | vcpu->hv_clock.version += 2; |
18068523 GOC |
1160 | |
1161 | shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0); | |
1162 | ||
1163 | memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock, | |
50d0a0f9 | 1164 | sizeof(vcpu->hv_clock)); |
18068523 GOC |
1165 | |
1166 | kunmap_atomic(shared_kaddr, KM_USER0); | |
1167 | ||
1168 | mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT); | |
8cfdc000 | 1169 | return 0; |
c8076604 GH |
1170 | } |
1171 | ||
9ba075a6 AK |
1172 | static bool msr_mtrr_valid(unsigned msr) |
1173 | { | |
1174 | switch (msr) { | |
1175 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
1176 | case MSR_MTRRfix64K_00000: | |
1177 | case MSR_MTRRfix16K_80000: | |
1178 | case MSR_MTRRfix16K_A0000: | |
1179 | case MSR_MTRRfix4K_C0000: | |
1180 | case MSR_MTRRfix4K_C8000: | |
1181 | case MSR_MTRRfix4K_D0000: | |
1182 | case MSR_MTRRfix4K_D8000: | |
1183 | case MSR_MTRRfix4K_E0000: | |
1184 | case MSR_MTRRfix4K_E8000: | |
1185 | case MSR_MTRRfix4K_F0000: | |
1186 | case MSR_MTRRfix4K_F8000: | |
1187 | case MSR_MTRRdefType: | |
1188 | case MSR_IA32_CR_PAT: | |
1189 | return true; | |
1190 | case 0x2f8: | |
1191 | return true; | |
1192 | } | |
1193 | return false; | |
1194 | } | |
1195 | ||
d6289b93 MT |
1196 | static bool valid_pat_type(unsigned t) |
1197 | { | |
1198 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
1199 | } | |
1200 | ||
1201 | static bool valid_mtrr_type(unsigned t) | |
1202 | { | |
1203 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
1204 | } | |
1205 | ||
1206 | static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1207 | { | |
1208 | int i; | |
1209 | ||
1210 | if (!msr_mtrr_valid(msr)) | |
1211 | return false; | |
1212 | ||
1213 | if (msr == MSR_IA32_CR_PAT) { | |
1214 | for (i = 0; i < 8; i++) | |
1215 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
1216 | return false; | |
1217 | return true; | |
1218 | } else if (msr == MSR_MTRRdefType) { | |
1219 | if (data & ~0xcff) | |
1220 | return false; | |
1221 | return valid_mtrr_type(data & 0xff); | |
1222 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
1223 | for (i = 0; i < 8 ; i++) | |
1224 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
1225 | return false; | |
1226 | return true; | |
1227 | } | |
1228 | ||
1229 | /* variable MTRRs */ | |
1230 | return valid_mtrr_type(data & 0xff); | |
1231 | } | |
1232 | ||
9ba075a6 AK |
1233 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1234 | { | |
0bed3b56 SY |
1235 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1236 | ||
d6289b93 | 1237 | if (!mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
1238 | return 1; |
1239 | ||
0bed3b56 SY |
1240 | if (msr == MSR_MTRRdefType) { |
1241 | vcpu->arch.mtrr_state.def_type = data; | |
1242 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
1243 | } else if (msr == MSR_MTRRfix64K_00000) | |
1244 | p[0] = data; | |
1245 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1246 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
1247 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1248 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
1249 | else if (msr == MSR_IA32_CR_PAT) | |
1250 | vcpu->arch.pat = data; | |
1251 | else { /* Variable MTRRs */ | |
1252 | int idx, is_mtrr_mask; | |
1253 | u64 *pt; | |
1254 | ||
1255 | idx = (msr - 0x200) / 2; | |
1256 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1257 | if (!is_mtrr_mask) | |
1258 | pt = | |
1259 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1260 | else | |
1261 | pt = | |
1262 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1263 | *pt = data; | |
1264 | } | |
1265 | ||
1266 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
1267 | return 0; |
1268 | } | |
15c4a640 | 1269 | |
890ca9ae | 1270 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1271 | { |
890ca9ae HY |
1272 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1273 | unsigned bank_num = mcg_cap & 0xff; | |
1274 | ||
15c4a640 | 1275 | switch (msr) { |
15c4a640 | 1276 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1277 | vcpu->arch.mcg_status = data; |
15c4a640 | 1278 | break; |
c7ac679c | 1279 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1280 | if (!(mcg_cap & MCG_CTL_P)) |
1281 | return 1; | |
1282 | if (data != 0 && data != ~(u64)0) | |
1283 | return -1; | |
1284 | vcpu->arch.mcg_ctl = data; | |
1285 | break; | |
1286 | default: | |
1287 | if (msr >= MSR_IA32_MC0_CTL && | |
1288 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1289 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
114be429 AP |
1290 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1291 | * some Linux kernels though clear bit 10 in bank 4 to | |
1292 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1293 | * this to avoid an uncatched #GP in the guest | |
1294 | */ | |
890ca9ae | 1295 | if ((offset & 0x3) == 0 && |
114be429 | 1296 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
1297 | return -1; |
1298 | vcpu->arch.mce_banks[offset] = data; | |
1299 | break; | |
1300 | } | |
1301 | return 1; | |
1302 | } | |
1303 | return 0; | |
1304 | } | |
1305 | ||
ffde22ac ES |
1306 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
1307 | { | |
1308 | struct kvm *kvm = vcpu->kvm; | |
1309 | int lm = is_long_mode(vcpu); | |
1310 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1311 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1312 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1313 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1314 | u32 page_num = data & ~PAGE_MASK; | |
1315 | u64 page_addr = data & PAGE_MASK; | |
1316 | u8 *page; | |
1317 | int r; | |
1318 | ||
1319 | r = -E2BIG; | |
1320 | if (page_num >= blob_size) | |
1321 | goto out; | |
1322 | r = -ENOMEM; | |
1323 | page = kzalloc(PAGE_SIZE, GFP_KERNEL); | |
1324 | if (!page) | |
1325 | goto out; | |
1326 | r = -EFAULT; | |
1327 | if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE)) | |
1328 | goto out_free; | |
1329 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) | |
1330 | goto out_free; | |
1331 | r = 0; | |
1332 | out_free: | |
1333 | kfree(page); | |
1334 | out: | |
1335 | return r; | |
1336 | } | |
1337 | ||
55cd8e5a GN |
1338 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
1339 | { | |
1340 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
1341 | } | |
1342 | ||
1343 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
1344 | { | |
1345 | bool r = false; | |
1346 | switch (msr) { | |
1347 | case HV_X64_MSR_GUEST_OS_ID: | |
1348 | case HV_X64_MSR_HYPERCALL: | |
1349 | r = true; | |
1350 | break; | |
1351 | } | |
1352 | ||
1353 | return r; | |
1354 | } | |
1355 | ||
1356 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1357 | { | |
1358 | struct kvm *kvm = vcpu->kvm; | |
1359 | ||
1360 | switch (msr) { | |
1361 | case HV_X64_MSR_GUEST_OS_ID: | |
1362 | kvm->arch.hv_guest_os_id = data; | |
1363 | /* setting guest os id to zero disables hypercall page */ | |
1364 | if (!kvm->arch.hv_guest_os_id) | |
1365 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
1366 | break; | |
1367 | case HV_X64_MSR_HYPERCALL: { | |
1368 | u64 gfn; | |
1369 | unsigned long addr; | |
1370 | u8 instructions[4]; | |
1371 | ||
1372 | /* if guest os id is not set hypercall should remain disabled */ | |
1373 | if (!kvm->arch.hv_guest_os_id) | |
1374 | break; | |
1375 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
1376 | kvm->arch.hv_hypercall = data; | |
1377 | break; | |
1378 | } | |
1379 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
1380 | addr = gfn_to_hva(kvm, gfn); | |
1381 | if (kvm_is_error_hva(addr)) | |
1382 | return 1; | |
1383 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
1384 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
1385 | if (copy_to_user((void __user *)addr, instructions, 4)) | |
1386 | return 1; | |
1387 | kvm->arch.hv_hypercall = data; | |
1388 | break; | |
1389 | } | |
1390 | default: | |
1391 | pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1392 | "data 0x%llx\n", msr, data); | |
1393 | return 1; | |
1394 | } | |
1395 | return 0; | |
1396 | } | |
1397 | ||
1398 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1399 | { | |
10388a07 GN |
1400 | switch (msr) { |
1401 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
1402 | unsigned long addr; | |
55cd8e5a | 1403 | |
10388a07 GN |
1404 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
1405 | vcpu->arch.hv_vapic = data; | |
1406 | break; | |
1407 | } | |
1408 | addr = gfn_to_hva(vcpu->kvm, data >> | |
1409 | HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT); | |
1410 | if (kvm_is_error_hva(addr)) | |
1411 | return 1; | |
1412 | if (clear_user((void __user *)addr, PAGE_SIZE)) | |
1413 | return 1; | |
1414 | vcpu->arch.hv_vapic = data; | |
1415 | break; | |
1416 | } | |
1417 | case HV_X64_MSR_EOI: | |
1418 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
1419 | case HV_X64_MSR_ICR: | |
1420 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
1421 | case HV_X64_MSR_TPR: | |
1422 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
1423 | default: | |
1424 | pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1425 | "data 0x%llx\n", msr, data); | |
1426 | return 1; | |
1427 | } | |
1428 | ||
1429 | return 0; | |
55cd8e5a GN |
1430 | } |
1431 | ||
344d9588 GN |
1432 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
1433 | { | |
1434 | gpa_t gpa = data & ~0x3f; | |
1435 | ||
6adba527 GN |
1436 | /* Bits 2:5 are resrved, Should be zero */ |
1437 | if (data & 0x3c) | |
344d9588 GN |
1438 | return 1; |
1439 | ||
1440 | vcpu->arch.apf.msr_val = data; | |
1441 | ||
1442 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
1443 | kvm_clear_async_pf_completion_queue(vcpu); | |
1444 | kvm_async_pf_hash_reset(vcpu); | |
1445 | return 0; | |
1446 | } | |
1447 | ||
1448 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa)) | |
1449 | return 1; | |
1450 | ||
6adba527 | 1451 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
344d9588 GN |
1452 | kvm_async_pf_wakeup_all(vcpu); |
1453 | return 0; | |
1454 | } | |
1455 | ||
12f9a48f GC |
1456 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
1457 | { | |
1458 | if (vcpu->arch.time_page) { | |
1459 | kvm_release_page_dirty(vcpu->arch.time_page); | |
1460 | vcpu->arch.time_page = NULL; | |
1461 | } | |
1462 | } | |
1463 | ||
15c4a640 CO |
1464 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1465 | { | |
1466 | switch (msr) { | |
15c4a640 | 1467 | case MSR_EFER: |
b69e8cae | 1468 | return set_efer(vcpu, data); |
8f1589d9 AP |
1469 | case MSR_K7_HWCR: |
1470 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 1471 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
8f1589d9 AP |
1472 | if (data != 0) { |
1473 | pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", | |
1474 | data); | |
1475 | return 1; | |
1476 | } | |
15c4a640 | 1477 | break; |
f7c6d140 AP |
1478 | case MSR_FAM10H_MMIO_CONF_BASE: |
1479 | if (data != 0) { | |
1480 | pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " | |
1481 | "0x%llx\n", data); | |
1482 | return 1; | |
1483 | } | |
15c4a640 | 1484 | break; |
c323c0e5 | 1485 | case MSR_AMD64_NB_CFG: |
c7ac679c | 1486 | break; |
b5e2fec0 AG |
1487 | case MSR_IA32_DEBUGCTLMSR: |
1488 | if (!data) { | |
1489 | /* We support the non-activated case already */ | |
1490 | break; | |
1491 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
1492 | /* Values other than LBR and BTF are vendor-specific, | |
1493 | thus reserved and should throw a #GP */ | |
1494 | return 1; | |
1495 | } | |
1496 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
1497 | __func__, data); | |
1498 | break; | |
15c4a640 CO |
1499 | case MSR_IA32_UCODE_REV: |
1500 | case MSR_IA32_UCODE_WRITE: | |
61a6bd67 | 1501 | case MSR_VM_HSAVE_PA: |
6098ca93 | 1502 | case MSR_AMD64_PATCH_LOADER: |
15c4a640 | 1503 | break; |
9ba075a6 AK |
1504 | case 0x200 ... 0x2ff: |
1505 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 CO |
1506 | case MSR_IA32_APICBASE: |
1507 | kvm_set_apic_base(vcpu, data); | |
1508 | break; | |
0105d1a5 GN |
1509 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1510 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
15c4a640 | 1511 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1512 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 1513 | break; |
11c6bffa | 1514 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
1515 | case MSR_KVM_WALL_CLOCK: |
1516 | vcpu->kvm->arch.wall_clock = data; | |
1517 | kvm_write_wall_clock(vcpu->kvm, data); | |
1518 | break; | |
11c6bffa | 1519 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 1520 | case MSR_KVM_SYSTEM_TIME: { |
12f9a48f | 1521 | kvmclock_reset(vcpu); |
18068523 GOC |
1522 | |
1523 | vcpu->arch.time = data; | |
c285545f | 1524 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
18068523 GOC |
1525 | |
1526 | /* we verify if the enable bit is set... */ | |
1527 | if (!(data & 1)) | |
1528 | break; | |
1529 | ||
1530 | /* ...but clean it before doing the actual write */ | |
1531 | vcpu->arch.time_offset = data & ~(PAGE_MASK | 1); | |
1532 | ||
18068523 GOC |
1533 | vcpu->arch.time_page = |
1534 | gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT); | |
18068523 GOC |
1535 | |
1536 | if (is_error_page(vcpu->arch.time_page)) { | |
1537 | kvm_release_page_clean(vcpu->arch.time_page); | |
1538 | vcpu->arch.time_page = NULL; | |
1539 | } | |
18068523 GOC |
1540 | break; |
1541 | } | |
344d9588 GN |
1542 | case MSR_KVM_ASYNC_PF_EN: |
1543 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
1544 | return 1; | |
1545 | break; | |
890ca9ae HY |
1546 | case MSR_IA32_MCG_CTL: |
1547 | case MSR_IA32_MCG_STATUS: | |
1548 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1549 | return set_msr_mce(vcpu, msr, data); | |
71db6023 AP |
1550 | |
1551 | /* Performance counters are not protected by a CPUID bit, | |
1552 | * so we should check all of them in the generic path for the sake of | |
1553 | * cross vendor migration. | |
1554 | * Writing a zero into the event select MSRs disables them, | |
1555 | * which we perfectly emulate ;-). Any other value should be at least | |
1556 | * reported, some guests depend on them. | |
1557 | */ | |
1558 | case MSR_P6_EVNTSEL0: | |
1559 | case MSR_P6_EVNTSEL1: | |
1560 | case MSR_K7_EVNTSEL0: | |
1561 | case MSR_K7_EVNTSEL1: | |
1562 | case MSR_K7_EVNTSEL2: | |
1563 | case MSR_K7_EVNTSEL3: | |
1564 | if (data != 0) | |
1565 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1566 | "0x%x data 0x%llx\n", msr, data); | |
1567 | break; | |
1568 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
1569 | * so we ignore writes to make it happy. | |
1570 | */ | |
1571 | case MSR_P6_PERFCTR0: | |
1572 | case MSR_P6_PERFCTR1: | |
1573 | case MSR_K7_PERFCTR0: | |
1574 | case MSR_K7_PERFCTR1: | |
1575 | case MSR_K7_PERFCTR2: | |
1576 | case MSR_K7_PERFCTR3: | |
1577 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1578 | "0x%x data 0x%llx\n", msr, data); | |
1579 | break; | |
84e0cefa JS |
1580 | case MSR_K7_CLK_CTL: |
1581 | /* | |
1582 | * Ignore all writes to this no longer documented MSR. | |
1583 | * Writes are only relevant for old K7 processors, | |
1584 | * all pre-dating SVM, but a recommended workaround from | |
1585 | * AMD for these chips. It is possible to speicify the | |
1586 | * affected processor models on the command line, hence | |
1587 | * the need to ignore the workaround. | |
1588 | */ | |
1589 | break; | |
55cd8e5a GN |
1590 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1591 | if (kvm_hv_msr_partition_wide(msr)) { | |
1592 | int r; | |
1593 | mutex_lock(&vcpu->kvm->lock); | |
1594 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
1595 | mutex_unlock(&vcpu->kvm->lock); | |
1596 | return r; | |
1597 | } else | |
1598 | return set_msr_hyperv(vcpu, msr, data); | |
1599 | break; | |
91c9c3ed | 1600 | case MSR_IA32_BBL_CR_CTL3: |
1601 | /* Drop writes to this legacy MSR -- see rdmsr | |
1602 | * counterpart for further detail. | |
1603 | */ | |
1604 | pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); | |
1605 | break; | |
15c4a640 | 1606 | default: |
ffde22ac ES |
1607 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
1608 | return xen_hvm_config(vcpu, data); | |
ed85c068 AP |
1609 | if (!ignore_msrs) { |
1610 | pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", | |
1611 | msr, data); | |
1612 | return 1; | |
1613 | } else { | |
1614 | pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", | |
1615 | msr, data); | |
1616 | break; | |
1617 | } | |
15c4a640 CO |
1618 | } |
1619 | return 0; | |
1620 | } | |
1621 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
1622 | ||
1623 | ||
1624 | /* | |
1625 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1626 | * Returns 0 on success, non-0 otherwise. | |
1627 | * Assumes vcpu_load() was already called. | |
1628 | */ | |
1629 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1630 | { | |
1631 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
1632 | } | |
1633 | ||
9ba075a6 AK |
1634 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1635 | { | |
0bed3b56 SY |
1636 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1637 | ||
9ba075a6 AK |
1638 | if (!msr_mtrr_valid(msr)) |
1639 | return 1; | |
1640 | ||
0bed3b56 SY |
1641 | if (msr == MSR_MTRRdefType) |
1642 | *pdata = vcpu->arch.mtrr_state.def_type + | |
1643 | (vcpu->arch.mtrr_state.enabled << 10); | |
1644 | else if (msr == MSR_MTRRfix64K_00000) | |
1645 | *pdata = p[0]; | |
1646 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1647 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
1648 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1649 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
1650 | else if (msr == MSR_IA32_CR_PAT) | |
1651 | *pdata = vcpu->arch.pat; | |
1652 | else { /* Variable MTRRs */ | |
1653 | int idx, is_mtrr_mask; | |
1654 | u64 *pt; | |
1655 | ||
1656 | idx = (msr - 0x200) / 2; | |
1657 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1658 | if (!is_mtrr_mask) | |
1659 | pt = | |
1660 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1661 | else | |
1662 | pt = | |
1663 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1664 | *pdata = *pt; | |
1665 | } | |
1666 | ||
9ba075a6 AK |
1667 | return 0; |
1668 | } | |
1669 | ||
890ca9ae | 1670 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
1671 | { |
1672 | u64 data; | |
890ca9ae HY |
1673 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1674 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
1675 | |
1676 | switch (msr) { | |
15c4a640 CO |
1677 | case MSR_IA32_P5_MC_ADDR: |
1678 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
1679 | data = 0; |
1680 | break; | |
15c4a640 | 1681 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
1682 | data = vcpu->arch.mcg_cap; |
1683 | break; | |
c7ac679c | 1684 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1685 | if (!(mcg_cap & MCG_CTL_P)) |
1686 | return 1; | |
1687 | data = vcpu->arch.mcg_ctl; | |
1688 | break; | |
1689 | case MSR_IA32_MCG_STATUS: | |
1690 | data = vcpu->arch.mcg_status; | |
1691 | break; | |
1692 | default: | |
1693 | if (msr >= MSR_IA32_MC0_CTL && | |
1694 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1695 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
1696 | data = vcpu->arch.mce_banks[offset]; | |
1697 | break; | |
1698 | } | |
1699 | return 1; | |
1700 | } | |
1701 | *pdata = data; | |
1702 | return 0; | |
1703 | } | |
1704 | ||
55cd8e5a GN |
1705 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1706 | { | |
1707 | u64 data = 0; | |
1708 | struct kvm *kvm = vcpu->kvm; | |
1709 | ||
1710 | switch (msr) { | |
1711 | case HV_X64_MSR_GUEST_OS_ID: | |
1712 | data = kvm->arch.hv_guest_os_id; | |
1713 | break; | |
1714 | case HV_X64_MSR_HYPERCALL: | |
1715 | data = kvm->arch.hv_hypercall; | |
1716 | break; | |
1717 | default: | |
1718 | pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
1719 | return 1; | |
1720 | } | |
1721 | ||
1722 | *pdata = data; | |
1723 | return 0; | |
1724 | } | |
1725 | ||
1726 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
1727 | { | |
1728 | u64 data = 0; | |
1729 | ||
1730 | switch (msr) { | |
1731 | case HV_X64_MSR_VP_INDEX: { | |
1732 | int r; | |
1733 | struct kvm_vcpu *v; | |
1734 | kvm_for_each_vcpu(r, v, vcpu->kvm) | |
1735 | if (v == vcpu) | |
1736 | data = r; | |
1737 | break; | |
1738 | } | |
10388a07 GN |
1739 | case HV_X64_MSR_EOI: |
1740 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
1741 | case HV_X64_MSR_ICR: | |
1742 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
1743 | case HV_X64_MSR_TPR: | |
1744 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
55cd8e5a GN |
1745 | default: |
1746 | pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
1747 | return 1; | |
1748 | } | |
1749 | *pdata = data; | |
1750 | return 0; | |
1751 | } | |
1752 | ||
890ca9ae HY |
1753 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1754 | { | |
1755 | u64 data; | |
1756 | ||
1757 | switch (msr) { | |
890ca9ae | 1758 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 1759 | case MSR_IA32_UCODE_REV: |
15c4a640 | 1760 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
1761 | case MSR_IA32_DEBUGCTLMSR: |
1762 | case MSR_IA32_LASTBRANCHFROMIP: | |
1763 | case MSR_IA32_LASTBRANCHTOIP: | |
1764 | case MSR_IA32_LASTINTFROMIP: | |
1765 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
1766 | case MSR_K8_SYSCFG: |
1767 | case MSR_K7_HWCR: | |
61a6bd67 | 1768 | case MSR_VM_HSAVE_PA: |
1f3ee616 AS |
1769 | case MSR_P6_PERFCTR0: |
1770 | case MSR_P6_PERFCTR1: | |
7fe29e0f AS |
1771 | case MSR_P6_EVNTSEL0: |
1772 | case MSR_P6_EVNTSEL1: | |
9e699624 | 1773 | case MSR_K7_EVNTSEL0: |
1f3ee616 | 1774 | case MSR_K7_PERFCTR0: |
1fdbd48c | 1775 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 1776 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 1777 | case MSR_FAM10H_MMIO_CONF_BASE: |
15c4a640 CO |
1778 | data = 0; |
1779 | break; | |
9ba075a6 AK |
1780 | case MSR_MTRRcap: |
1781 | data = 0x500 | KVM_NR_VAR_MTRR; | |
1782 | break; | |
1783 | case 0x200 ... 0x2ff: | |
1784 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
1785 | case 0xcd: /* fsb frequency */ |
1786 | data = 3; | |
1787 | break; | |
7b914098 JS |
1788 | /* |
1789 | * MSR_EBC_FREQUENCY_ID | |
1790 | * Conservative value valid for even the basic CPU models. | |
1791 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
1792 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
1793 | * and 266MHz for model 3, or 4. Set Core Clock | |
1794 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
1795 | * 31:24) even though these are only valid for CPU | |
1796 | * models > 2, however guests may end up dividing or | |
1797 | * multiplying by zero otherwise. | |
1798 | */ | |
1799 | case MSR_EBC_FREQUENCY_ID: | |
1800 | data = 1 << 24; | |
1801 | break; | |
15c4a640 CO |
1802 | case MSR_IA32_APICBASE: |
1803 | data = kvm_get_apic_base(vcpu); | |
1804 | break; | |
0105d1a5 GN |
1805 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1806 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
1807 | break; | |
15c4a640 | 1808 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1809 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 1810 | break; |
847f0ad8 AG |
1811 | case MSR_IA32_PERF_STATUS: |
1812 | /* TSC increment by tick */ | |
1813 | data = 1000ULL; | |
1814 | /* CPU multiplier */ | |
1815 | data |= (((uint64_t)4ULL) << 40); | |
1816 | break; | |
15c4a640 | 1817 | case MSR_EFER: |
f6801dff | 1818 | data = vcpu->arch.efer; |
15c4a640 | 1819 | break; |
18068523 | 1820 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 1821 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
1822 | data = vcpu->kvm->arch.wall_clock; |
1823 | break; | |
1824 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 1825 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 GOC |
1826 | data = vcpu->arch.time; |
1827 | break; | |
344d9588 GN |
1828 | case MSR_KVM_ASYNC_PF_EN: |
1829 | data = vcpu->arch.apf.msr_val; | |
1830 | break; | |
890ca9ae HY |
1831 | case MSR_IA32_P5_MC_ADDR: |
1832 | case MSR_IA32_P5_MC_TYPE: | |
1833 | case MSR_IA32_MCG_CAP: | |
1834 | case MSR_IA32_MCG_CTL: | |
1835 | case MSR_IA32_MCG_STATUS: | |
1836 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1837 | return get_msr_mce(vcpu, msr, pdata); | |
84e0cefa JS |
1838 | case MSR_K7_CLK_CTL: |
1839 | /* | |
1840 | * Provide expected ramp-up count for K7. All other | |
1841 | * are set to zero, indicating minimum divisors for | |
1842 | * every field. | |
1843 | * | |
1844 | * This prevents guest kernels on AMD host with CPU | |
1845 | * type 6, model 8 and higher from exploding due to | |
1846 | * the rdmsr failing. | |
1847 | */ | |
1848 | data = 0x20000000; | |
1849 | break; | |
55cd8e5a GN |
1850 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1851 | if (kvm_hv_msr_partition_wide(msr)) { | |
1852 | int r; | |
1853 | mutex_lock(&vcpu->kvm->lock); | |
1854 | r = get_msr_hyperv_pw(vcpu, msr, pdata); | |
1855 | mutex_unlock(&vcpu->kvm->lock); | |
1856 | return r; | |
1857 | } else | |
1858 | return get_msr_hyperv(vcpu, msr, pdata); | |
1859 | break; | |
91c9c3ed | 1860 | case MSR_IA32_BBL_CR_CTL3: |
1861 | /* This legacy MSR exists but isn't fully documented in current | |
1862 | * silicon. It is however accessed by winxp in very narrow | |
1863 | * scenarios where it sets bit #19, itself documented as | |
1864 | * a "reserved" bit. Best effort attempt to source coherent | |
1865 | * read data here should the balance of the register be | |
1866 | * interpreted by the guest: | |
1867 | * | |
1868 | * L2 cache control register 3: 64GB range, 256KB size, | |
1869 | * enabled, latency 0x1, configured | |
1870 | */ | |
1871 | data = 0xbe702111; | |
1872 | break; | |
15c4a640 | 1873 | default: |
ed85c068 AP |
1874 | if (!ignore_msrs) { |
1875 | pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); | |
1876 | return 1; | |
1877 | } else { | |
1878 | pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); | |
1879 | data = 0; | |
1880 | } | |
1881 | break; | |
15c4a640 CO |
1882 | } |
1883 | *pdata = data; | |
1884 | return 0; | |
1885 | } | |
1886 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
1887 | ||
313a3dc7 CO |
1888 | /* |
1889 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
1890 | * | |
1891 | * @return number of msrs set successfully. | |
1892 | */ | |
1893 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
1894 | struct kvm_msr_entry *entries, | |
1895 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1896 | unsigned index, u64 *data)) | |
1897 | { | |
f656ce01 | 1898 | int i, idx; |
313a3dc7 | 1899 | |
f656ce01 | 1900 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
1901 | for (i = 0; i < msrs->nmsrs; ++i) |
1902 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
1903 | break; | |
f656ce01 | 1904 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 1905 | |
313a3dc7 CO |
1906 | return i; |
1907 | } | |
1908 | ||
1909 | /* | |
1910 | * Read or write a bunch of msrs. Parameters are user addresses. | |
1911 | * | |
1912 | * @return number of msrs set successfully. | |
1913 | */ | |
1914 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
1915 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1916 | unsigned index, u64 *data), | |
1917 | int writeback) | |
1918 | { | |
1919 | struct kvm_msrs msrs; | |
1920 | struct kvm_msr_entry *entries; | |
1921 | int r, n; | |
1922 | unsigned size; | |
1923 | ||
1924 | r = -EFAULT; | |
1925 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
1926 | goto out; | |
1927 | ||
1928 | r = -E2BIG; | |
1929 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
1930 | goto out; | |
1931 | ||
1932 | r = -ENOMEM; | |
1933 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; | |
7a73c028 | 1934 | entries = kmalloc(size, GFP_KERNEL); |
313a3dc7 CO |
1935 | if (!entries) |
1936 | goto out; | |
1937 | ||
1938 | r = -EFAULT; | |
1939 | if (copy_from_user(entries, user_msrs->entries, size)) | |
1940 | goto out_free; | |
1941 | ||
1942 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
1943 | if (r < 0) | |
1944 | goto out_free; | |
1945 | ||
1946 | r = -EFAULT; | |
1947 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
1948 | goto out_free; | |
1949 | ||
1950 | r = n; | |
1951 | ||
1952 | out_free: | |
7a73c028 | 1953 | kfree(entries); |
313a3dc7 CO |
1954 | out: |
1955 | return r; | |
1956 | } | |
1957 | ||
018d00d2 ZX |
1958 | int kvm_dev_ioctl_check_extension(long ext) |
1959 | { | |
1960 | int r; | |
1961 | ||
1962 | switch (ext) { | |
1963 | case KVM_CAP_IRQCHIP: | |
1964 | case KVM_CAP_HLT: | |
1965 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 1966 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 1967 | case KVM_CAP_EXT_CPUID: |
c8076604 | 1968 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 1969 | case KVM_CAP_PIT: |
a28e4f5a | 1970 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 1971 | case KVM_CAP_MP_STATE: |
ed848624 | 1972 | case KVM_CAP_SYNC_MMU: |
a355c85c | 1973 | case KVM_CAP_USER_NMI: |
52d939a0 | 1974 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 1975 | case KVM_CAP_IRQ_INJECT_STATUS: |
e56d532f | 1976 | case KVM_CAP_ASSIGN_DEV_IRQ: |
721eecbf | 1977 | case KVM_CAP_IRQFD: |
d34e6b17 | 1978 | case KVM_CAP_IOEVENTFD: |
c5ff41ce | 1979 | case KVM_CAP_PIT2: |
e9f42757 | 1980 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 1981 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 1982 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 1983 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 1984 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 1985 | case KVM_CAP_HYPERV: |
10388a07 | 1986 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 1987 | case KVM_CAP_HYPERV_SPIN: |
ab9f4ecb | 1988 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 1989 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 1990 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 1991 | case KVM_CAP_XSAVE: |
344d9588 | 1992 | case KVM_CAP_ASYNC_PF: |
018d00d2 ZX |
1993 | r = 1; |
1994 | break; | |
542472b5 LV |
1995 | case KVM_CAP_COALESCED_MMIO: |
1996 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
1997 | break; | |
774ead3a AK |
1998 | case KVM_CAP_VAPIC: |
1999 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
2000 | break; | |
f725230a AK |
2001 | case KVM_CAP_NR_VCPUS: |
2002 | r = KVM_MAX_VCPUS; | |
2003 | break; | |
a988b910 AK |
2004 | case KVM_CAP_NR_MEMSLOTS: |
2005 | r = KVM_MEMORY_SLOTS; | |
2006 | break; | |
a68a6a72 MT |
2007 | case KVM_CAP_PV_MMU: /* obsolete */ |
2008 | r = 0; | |
2f333bcb | 2009 | break; |
62c476c7 | 2010 | case KVM_CAP_IOMMU: |
19de40a8 | 2011 | r = iommu_found(); |
62c476c7 | 2012 | break; |
890ca9ae HY |
2013 | case KVM_CAP_MCE: |
2014 | r = KVM_MAX_MCE_BANKS; | |
2015 | break; | |
2d5b5a66 SY |
2016 | case KVM_CAP_XCRS: |
2017 | r = cpu_has_xsave; | |
2018 | break; | |
018d00d2 ZX |
2019 | default: |
2020 | r = 0; | |
2021 | break; | |
2022 | } | |
2023 | return r; | |
2024 | ||
2025 | } | |
2026 | ||
043405e1 CO |
2027 | long kvm_arch_dev_ioctl(struct file *filp, |
2028 | unsigned int ioctl, unsigned long arg) | |
2029 | { | |
2030 | void __user *argp = (void __user *)arg; | |
2031 | long r; | |
2032 | ||
2033 | switch (ioctl) { | |
2034 | case KVM_GET_MSR_INDEX_LIST: { | |
2035 | struct kvm_msr_list __user *user_msr_list = argp; | |
2036 | struct kvm_msr_list msr_list; | |
2037 | unsigned n; | |
2038 | ||
2039 | r = -EFAULT; | |
2040 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2041 | goto out; | |
2042 | n = msr_list.nmsrs; | |
2043 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
2044 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
2045 | goto out; | |
2046 | r = -E2BIG; | |
e125e7b6 | 2047 | if (n < msr_list.nmsrs) |
043405e1 CO |
2048 | goto out; |
2049 | r = -EFAULT; | |
2050 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2051 | num_msrs_to_save * sizeof(u32))) | |
2052 | goto out; | |
e125e7b6 | 2053 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
2054 | &emulated_msrs, |
2055 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
2056 | goto out; | |
2057 | r = 0; | |
2058 | break; | |
2059 | } | |
674eea0f AK |
2060 | case KVM_GET_SUPPORTED_CPUID: { |
2061 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2062 | struct kvm_cpuid2 cpuid; | |
2063 | ||
2064 | r = -EFAULT; | |
2065 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2066 | goto out; | |
2067 | r = kvm_dev_ioctl_get_supported_cpuid(&cpuid, | |
19355475 | 2068 | cpuid_arg->entries); |
674eea0f AK |
2069 | if (r) |
2070 | goto out; | |
2071 | ||
2072 | r = -EFAULT; | |
2073 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2074 | goto out; | |
2075 | r = 0; | |
2076 | break; | |
2077 | } | |
890ca9ae HY |
2078 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
2079 | u64 mce_cap; | |
2080 | ||
2081 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
2082 | r = -EFAULT; | |
2083 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
2084 | goto out; | |
2085 | r = 0; | |
2086 | break; | |
2087 | } | |
043405e1 CO |
2088 | default: |
2089 | r = -EINVAL; | |
2090 | } | |
2091 | out: | |
2092 | return r; | |
2093 | } | |
2094 | ||
f5f48ee1 SY |
2095 | static void wbinvd_ipi(void *garbage) |
2096 | { | |
2097 | wbinvd(); | |
2098 | } | |
2099 | ||
2100 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
2101 | { | |
2102 | return vcpu->kvm->arch.iommu_domain && | |
2103 | !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY); | |
2104 | } | |
2105 | ||
313a3dc7 CO |
2106 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
2107 | { | |
f5f48ee1 SY |
2108 | /* Address WBINVD may be executed by guest */ |
2109 | if (need_emulate_wbinvd(vcpu)) { | |
2110 | if (kvm_x86_ops->has_wbinvd_exit()) | |
2111 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
2112 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
2113 | smp_call_function_single(vcpu->cpu, | |
2114 | wbinvd_ipi, NULL, 1); | |
2115 | } | |
2116 | ||
313a3dc7 | 2117 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
48434c20 | 2118 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { |
e48672fa ZA |
2119 | /* Make sure TSC doesn't go backwards */ |
2120 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : | |
2121 | native_read_tsc() - vcpu->arch.last_host_tsc; | |
2122 | if (tsc_delta < 0) | |
2123 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
c285545f | 2124 | if (check_tsc_unstable()) { |
e48672fa | 2125 | kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta); |
c285545f ZA |
2126 | vcpu->arch.tsc_catchup = 1; |
2127 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
2128 | } | |
2129 | if (vcpu->cpu != cpu) | |
2130 | kvm_migrate_timers(vcpu); | |
e48672fa | 2131 | vcpu->cpu = cpu; |
6b7d7e76 | 2132 | } |
313a3dc7 CO |
2133 | } |
2134 | ||
2135 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
2136 | { | |
02daab21 | 2137 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 2138 | kvm_put_guest_fpu(vcpu); |
e48672fa | 2139 | vcpu->arch.last_host_tsc = native_read_tsc(); |
313a3dc7 CO |
2140 | } |
2141 | ||
07716717 | 2142 | static int is_efer_nx(void) |
313a3dc7 | 2143 | { |
e286e86e | 2144 | unsigned long long efer = 0; |
313a3dc7 | 2145 | |
e286e86e | 2146 | rdmsrl_safe(MSR_EFER, &efer); |
07716717 DK |
2147 | return efer & EFER_NX; |
2148 | } | |
2149 | ||
2150 | static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) | |
2151 | { | |
2152 | int i; | |
2153 | struct kvm_cpuid_entry2 *e, *entry; | |
2154 | ||
313a3dc7 | 2155 | entry = NULL; |
ad312c7c ZX |
2156 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
2157 | e = &vcpu->arch.cpuid_entries[i]; | |
313a3dc7 CO |
2158 | if (e->function == 0x80000001) { |
2159 | entry = e; | |
2160 | break; | |
2161 | } | |
2162 | } | |
07716717 | 2163 | if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) { |
313a3dc7 CO |
2164 | entry->edx &= ~(1 << 20); |
2165 | printk(KERN_INFO "kvm: guest NX capability removed\n"); | |
2166 | } | |
2167 | } | |
2168 | ||
07716717 | 2169 | /* when an old userspace process fills a new kernel module */ |
313a3dc7 CO |
2170 | static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, |
2171 | struct kvm_cpuid *cpuid, | |
2172 | struct kvm_cpuid_entry __user *entries) | |
07716717 DK |
2173 | { |
2174 | int r, i; | |
2175 | struct kvm_cpuid_entry *cpuid_entries; | |
2176 | ||
2177 | r = -E2BIG; | |
2178 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
2179 | goto out; | |
2180 | r = -ENOMEM; | |
2181 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent); | |
2182 | if (!cpuid_entries) | |
2183 | goto out; | |
2184 | r = -EFAULT; | |
2185 | if (copy_from_user(cpuid_entries, entries, | |
2186 | cpuid->nent * sizeof(struct kvm_cpuid_entry))) | |
2187 | goto out_free; | |
2188 | for (i = 0; i < cpuid->nent; i++) { | |
ad312c7c ZX |
2189 | vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; |
2190 | vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; | |
2191 | vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx; | |
2192 | vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx; | |
2193 | vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx; | |
2194 | vcpu->arch.cpuid_entries[i].index = 0; | |
2195 | vcpu->arch.cpuid_entries[i].flags = 0; | |
2196 | vcpu->arch.cpuid_entries[i].padding[0] = 0; | |
2197 | vcpu->arch.cpuid_entries[i].padding[1] = 0; | |
2198 | vcpu->arch.cpuid_entries[i].padding[2] = 0; | |
2199 | } | |
2200 | vcpu->arch.cpuid_nent = cpuid->nent; | |
07716717 DK |
2201 | cpuid_fix_nx_cap(vcpu); |
2202 | r = 0; | |
fc61b800 | 2203 | kvm_apic_set_version(vcpu); |
0e851880 | 2204 | kvm_x86_ops->cpuid_update(vcpu); |
2acf923e | 2205 | update_cpuid(vcpu); |
07716717 DK |
2206 | |
2207 | out_free: | |
2208 | vfree(cpuid_entries); | |
2209 | out: | |
2210 | return r; | |
2211 | } | |
2212 | ||
2213 | static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, | |
19355475 AS |
2214 | struct kvm_cpuid2 *cpuid, |
2215 | struct kvm_cpuid_entry2 __user *entries) | |
313a3dc7 CO |
2216 | { |
2217 | int r; | |
2218 | ||
2219 | r = -E2BIG; | |
2220 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
2221 | goto out; | |
2222 | r = -EFAULT; | |
ad312c7c | 2223 | if (copy_from_user(&vcpu->arch.cpuid_entries, entries, |
07716717 | 2224 | cpuid->nent * sizeof(struct kvm_cpuid_entry2))) |
313a3dc7 | 2225 | goto out; |
ad312c7c | 2226 | vcpu->arch.cpuid_nent = cpuid->nent; |
fc61b800 | 2227 | kvm_apic_set_version(vcpu); |
0e851880 | 2228 | kvm_x86_ops->cpuid_update(vcpu); |
2acf923e | 2229 | update_cpuid(vcpu); |
313a3dc7 CO |
2230 | return 0; |
2231 | ||
2232 | out: | |
2233 | return r; | |
2234 | } | |
2235 | ||
07716717 | 2236 | static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, |
19355475 AS |
2237 | struct kvm_cpuid2 *cpuid, |
2238 | struct kvm_cpuid_entry2 __user *entries) | |
07716717 DK |
2239 | { |
2240 | int r; | |
2241 | ||
2242 | r = -E2BIG; | |
ad312c7c | 2243 | if (cpuid->nent < vcpu->arch.cpuid_nent) |
07716717 DK |
2244 | goto out; |
2245 | r = -EFAULT; | |
ad312c7c | 2246 | if (copy_to_user(entries, &vcpu->arch.cpuid_entries, |
19355475 | 2247 | vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
2248 | goto out; |
2249 | return 0; | |
2250 | ||
2251 | out: | |
ad312c7c | 2252 | cpuid->nent = vcpu->arch.cpuid_nent; |
07716717 DK |
2253 | return r; |
2254 | } | |
2255 | ||
945ee35e AK |
2256 | static void cpuid_mask(u32 *word, int wordnum) |
2257 | { | |
2258 | *word &= boot_cpu_data.x86_capability[wordnum]; | |
2259 | } | |
2260 | ||
07716717 | 2261 | static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
19355475 | 2262 | u32 index) |
07716717 DK |
2263 | { |
2264 | entry->function = function; | |
2265 | entry->index = index; | |
2266 | cpuid_count(entry->function, entry->index, | |
19355475 | 2267 | &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); |
07716717 DK |
2268 | entry->flags = 0; |
2269 | } | |
2270 | ||
7faa4ee1 AK |
2271 | #define F(x) bit(X86_FEATURE_##x) |
2272 | ||
07716717 DK |
2273 | static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
2274 | u32 index, int *nent, int maxnent) | |
2275 | { | |
7faa4ee1 | 2276 | unsigned f_nx = is_efer_nx() ? F(NX) : 0; |
07716717 | 2277 | #ifdef CONFIG_X86_64 |
17cc3935 SY |
2278 | unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL) |
2279 | ? F(GBPAGES) : 0; | |
7faa4ee1 AK |
2280 | unsigned f_lm = F(LM); |
2281 | #else | |
17cc3935 | 2282 | unsigned f_gbpages = 0; |
7faa4ee1 | 2283 | unsigned f_lm = 0; |
07716717 | 2284 | #endif |
4e47c7a6 | 2285 | unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0; |
7faa4ee1 AK |
2286 | |
2287 | /* cpuid 1.edx */ | |
2288 | const u32 kvm_supported_word0_x86_features = | |
2289 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
2290 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
2291 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | | |
2292 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
2293 | F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) | | |
2294 | 0 /* Reserved, DS, ACPI */ | F(MMX) | | |
2295 | F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | | |
2296 | 0 /* HTT, TM, Reserved, PBE */; | |
2297 | /* cpuid 0x80000001.edx */ | |
2298 | const u32 kvm_supported_word1_x86_features = | |
2299 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
2300 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
2301 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | | |
2302 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
2303 | F(PAT) | F(PSE36) | 0 /* Reserved */ | | |
2304 | f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | | |
4e47c7a6 | 2305 | F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp | |
7faa4ee1 AK |
2306 | 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW); |
2307 | /* cpuid 1.ecx */ | |
2308 | const u32 kvm_supported_word4_x86_features = | |
6c3f6041 | 2309 | F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | |
d149c731 AK |
2310 | 0 /* DS-CPL, VMX, SMX, EST */ | |
2311 | 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | | |
2312 | 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ | | |
2313 | 0 /* Reserved, DCA */ | F(XMM4_1) | | |
0105d1a5 | 2314 | F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | |
6d886fd0 AP |
2315 | 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | |
2316 | F(F16C); | |
7faa4ee1 | 2317 | /* cpuid 0x80000001.ecx */ |
07716717 | 2318 | const u32 kvm_supported_word6_x86_features = |
4c62a2dc | 2319 | F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | |
7faa4ee1 | 2320 | F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | |
7ef8aa72 | 2321 | F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) | |
6d886fd0 | 2322 | 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM); |
07716717 | 2323 | |
19355475 | 2324 | /* all calls to cpuid_count() should be made on the same cpu */ |
07716717 DK |
2325 | get_cpu(); |
2326 | do_cpuid_1_ent(entry, function, index); | |
2327 | ++*nent; | |
2328 | ||
2329 | switch (function) { | |
2330 | case 0: | |
2acf923e | 2331 | entry->eax = min(entry->eax, (u32)0xd); |
07716717 DK |
2332 | break; |
2333 | case 1: | |
2334 | entry->edx &= kvm_supported_word0_x86_features; | |
945ee35e | 2335 | cpuid_mask(&entry->edx, 0); |
7faa4ee1 | 2336 | entry->ecx &= kvm_supported_word4_x86_features; |
945ee35e | 2337 | cpuid_mask(&entry->ecx, 4); |
0d1de2d9 GN |
2338 | /* we support x2apic emulation even if host does not support |
2339 | * it since we emulate x2apic in software */ | |
2340 | entry->ecx |= F(X2APIC); | |
07716717 DK |
2341 | break; |
2342 | /* function 2 entries are STATEFUL. That is, repeated cpuid commands | |
2343 | * may return different values. This forces us to get_cpu() before | |
2344 | * issuing the first command, and also to emulate this annoying behavior | |
2345 | * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */ | |
2346 | case 2: { | |
2347 | int t, times = entry->eax & 0xff; | |
2348 | ||
2349 | entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
0fdf8e59 | 2350 | entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; |
07716717 DK |
2351 | for (t = 1; t < times && *nent < maxnent; ++t) { |
2352 | do_cpuid_1_ent(&entry[t], function, 0); | |
2353 | entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
2354 | ++*nent; | |
2355 | } | |
2356 | break; | |
2357 | } | |
2358 | /* function 4 and 0xb have additional index. */ | |
2359 | case 4: { | |
14af3f3c | 2360 | int i, cache_type; |
07716717 DK |
2361 | |
2362 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2363 | /* read more entries until cache_type is zero */ | |
14af3f3c HH |
2364 | for (i = 1; *nent < maxnent; ++i) { |
2365 | cache_type = entry[i - 1].eax & 0x1f; | |
07716717 DK |
2366 | if (!cache_type) |
2367 | break; | |
14af3f3c HH |
2368 | do_cpuid_1_ent(&entry[i], function, i); |
2369 | entry[i].flags |= | |
07716717 DK |
2370 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
2371 | ++*nent; | |
2372 | } | |
2373 | break; | |
2374 | } | |
2375 | case 0xb: { | |
14af3f3c | 2376 | int i, level_type; |
07716717 DK |
2377 | |
2378 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2379 | /* read more entries until level_type is zero */ | |
14af3f3c | 2380 | for (i = 1; *nent < maxnent; ++i) { |
0853d2c1 | 2381 | level_type = entry[i - 1].ecx & 0xff00; |
07716717 DK |
2382 | if (!level_type) |
2383 | break; | |
14af3f3c HH |
2384 | do_cpuid_1_ent(&entry[i], function, i); |
2385 | entry[i].flags |= | |
07716717 DK |
2386 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
2387 | ++*nent; | |
2388 | } | |
2389 | break; | |
2390 | } | |
2acf923e DC |
2391 | case 0xd: { |
2392 | int i; | |
2393 | ||
2394 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2395 | for (i = 1; *nent < maxnent; ++i) { | |
2396 | if (entry[i - 1].eax == 0 && i != 2) | |
2397 | break; | |
2398 | do_cpuid_1_ent(&entry[i], function, i); | |
2399 | entry[i].flags |= | |
2400 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2401 | ++*nent; | |
2402 | } | |
2403 | break; | |
2404 | } | |
84478c82 GC |
2405 | case KVM_CPUID_SIGNATURE: { |
2406 | char signature[12] = "KVMKVMKVM\0\0"; | |
2407 | u32 *sigptr = (u32 *)signature; | |
2408 | entry->eax = 0; | |
2409 | entry->ebx = sigptr[0]; | |
2410 | entry->ecx = sigptr[1]; | |
2411 | entry->edx = sigptr[2]; | |
2412 | break; | |
2413 | } | |
2414 | case KVM_CPUID_FEATURES: | |
2415 | entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | | |
2416 | (1 << KVM_FEATURE_NOP_IO_DELAY) | | |
371bcf64 GC |
2417 | (1 << KVM_FEATURE_CLOCKSOURCE2) | |
2418 | (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT); | |
84478c82 GC |
2419 | entry->ebx = 0; |
2420 | entry->ecx = 0; | |
2421 | entry->edx = 0; | |
2422 | break; | |
07716717 DK |
2423 | case 0x80000000: |
2424 | entry->eax = min(entry->eax, 0x8000001a); | |
2425 | break; | |
2426 | case 0x80000001: | |
2427 | entry->edx &= kvm_supported_word1_x86_features; | |
945ee35e | 2428 | cpuid_mask(&entry->edx, 1); |
07716717 | 2429 | entry->ecx &= kvm_supported_word6_x86_features; |
945ee35e | 2430 | cpuid_mask(&entry->ecx, 6); |
07716717 DK |
2431 | break; |
2432 | } | |
d4330ef2 JR |
2433 | |
2434 | kvm_x86_ops->set_supported_cpuid(function, entry); | |
2435 | ||
07716717 DK |
2436 | put_cpu(); |
2437 | } | |
2438 | ||
7faa4ee1 AK |
2439 | #undef F |
2440 | ||
674eea0f | 2441 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
19355475 | 2442 | struct kvm_cpuid_entry2 __user *entries) |
07716717 DK |
2443 | { |
2444 | struct kvm_cpuid_entry2 *cpuid_entries; | |
2445 | int limit, nent = 0, r = -E2BIG; | |
2446 | u32 func; | |
2447 | ||
2448 | if (cpuid->nent < 1) | |
2449 | goto out; | |
6a544355 AK |
2450 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
2451 | cpuid->nent = KVM_MAX_CPUID_ENTRIES; | |
07716717 DK |
2452 | r = -ENOMEM; |
2453 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent); | |
2454 | if (!cpuid_entries) | |
2455 | goto out; | |
2456 | ||
2457 | do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent); | |
2458 | limit = cpuid_entries[0].eax; | |
2459 | for (func = 1; func <= limit && nent < cpuid->nent; ++func) | |
2460 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 2461 | &nent, cpuid->nent); |
07716717 DK |
2462 | r = -E2BIG; |
2463 | if (nent >= cpuid->nent) | |
2464 | goto out_free; | |
2465 | ||
2466 | do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent); | |
2467 | limit = cpuid_entries[nent - 1].eax; | |
2468 | for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func) | |
2469 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 2470 | &nent, cpuid->nent); |
84478c82 GC |
2471 | |
2472 | ||
2473 | ||
2474 | r = -E2BIG; | |
2475 | if (nent >= cpuid->nent) | |
2476 | goto out_free; | |
2477 | ||
2478 | do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent, | |
2479 | cpuid->nent); | |
2480 | ||
2481 | r = -E2BIG; | |
2482 | if (nent >= cpuid->nent) | |
2483 | goto out_free; | |
2484 | ||
2485 | do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent, | |
2486 | cpuid->nent); | |
2487 | ||
cb007648 MM |
2488 | r = -E2BIG; |
2489 | if (nent >= cpuid->nent) | |
2490 | goto out_free; | |
2491 | ||
07716717 DK |
2492 | r = -EFAULT; |
2493 | if (copy_to_user(entries, cpuid_entries, | |
19355475 | 2494 | nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
2495 | goto out_free; |
2496 | cpuid->nent = nent; | |
2497 | r = 0; | |
2498 | ||
2499 | out_free: | |
2500 | vfree(cpuid_entries); | |
2501 | out: | |
2502 | return r; | |
2503 | } | |
2504 | ||
313a3dc7 CO |
2505 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
2506 | struct kvm_lapic_state *s) | |
2507 | { | |
ad312c7c | 2508 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
2509 | |
2510 | return 0; | |
2511 | } | |
2512 | ||
2513 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2514 | struct kvm_lapic_state *s) | |
2515 | { | |
ad312c7c | 2516 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); |
313a3dc7 | 2517 | kvm_apic_post_state_restore(vcpu); |
cb142eb7 | 2518 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2519 | |
2520 | return 0; | |
2521 | } | |
2522 | ||
f77bc6a4 ZX |
2523 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
2524 | struct kvm_interrupt *irq) | |
2525 | { | |
2526 | if (irq->irq < 0 || irq->irq >= 256) | |
2527 | return -EINVAL; | |
2528 | if (irqchip_in_kernel(vcpu->kvm)) | |
2529 | return -ENXIO; | |
f77bc6a4 | 2530 | |
66fd3f7f | 2531 | kvm_queue_interrupt(vcpu, irq->irq, false); |
3842d135 | 2532 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 | 2533 | |
f77bc6a4 ZX |
2534 | return 0; |
2535 | } | |
2536 | ||
c4abb7c9 JK |
2537 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
2538 | { | |
c4abb7c9 | 2539 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
2540 | |
2541 | return 0; | |
2542 | } | |
2543 | ||
b209749f AK |
2544 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
2545 | struct kvm_tpr_access_ctl *tac) | |
2546 | { | |
2547 | if (tac->flags) | |
2548 | return -EINVAL; | |
2549 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2550 | return 0; | |
2551 | } | |
2552 | ||
890ca9ae HY |
2553 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
2554 | u64 mcg_cap) | |
2555 | { | |
2556 | int r; | |
2557 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2558 | ||
2559 | r = -EINVAL; | |
a9e38c3e | 2560 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
2561 | goto out; |
2562 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2563 | goto out; | |
2564 | r = 0; | |
2565 | vcpu->arch.mcg_cap = mcg_cap; | |
2566 | /* Init IA32_MCG_CTL to all 1s */ | |
2567 | if (mcg_cap & MCG_CTL_P) | |
2568 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2569 | /* Init IA32_MCi_CTL to all 1s */ | |
2570 | for (bank = 0; bank < bank_num; bank++) | |
2571 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2572 | out: | |
2573 | return r; | |
2574 | } | |
2575 | ||
2576 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2577 | struct kvm_x86_mce *mce) | |
2578 | { | |
2579 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2580 | unsigned bank_num = mcg_cap & 0xff; | |
2581 | u64 *banks = vcpu->arch.mce_banks; | |
2582 | ||
2583 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
2584 | return -EINVAL; | |
2585 | /* | |
2586 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
2587 | * reporting is disabled | |
2588 | */ | |
2589 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
2590 | vcpu->arch.mcg_ctl != ~(u64)0) | |
2591 | return 0; | |
2592 | banks += 4 * mce->bank; | |
2593 | /* | |
2594 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
2595 | * reporting is disabled for the bank | |
2596 | */ | |
2597 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
2598 | return 0; | |
2599 | if (mce->status & MCI_STATUS_UC) { | |
2600 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 2601 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 2602 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
2603 | return 0; |
2604 | } | |
2605 | if (banks[1] & MCI_STATUS_VAL) | |
2606 | mce->status |= MCI_STATUS_OVER; | |
2607 | banks[2] = mce->addr; | |
2608 | banks[3] = mce->misc; | |
2609 | vcpu->arch.mcg_status = mce->mcg_status; | |
2610 | banks[1] = mce->status; | |
2611 | kvm_queue_exception(vcpu, MC_VECTOR); | |
2612 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
2613 | || !(banks[1] & MCI_STATUS_UC)) { | |
2614 | if (banks[1] & MCI_STATUS_VAL) | |
2615 | mce->status |= MCI_STATUS_OVER; | |
2616 | banks[2] = mce->addr; | |
2617 | banks[3] = mce->misc; | |
2618 | banks[1] = mce->status; | |
2619 | } else | |
2620 | banks[1] |= MCI_STATUS_OVER; | |
2621 | return 0; | |
2622 | } | |
2623 | ||
3cfc3092 JK |
2624 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
2625 | struct kvm_vcpu_events *events) | |
2626 | { | |
03b82a30 JK |
2627 | events->exception.injected = |
2628 | vcpu->arch.exception.pending && | |
2629 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
2630 | events->exception.nr = vcpu->arch.exception.nr; |
2631 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
97e69aa6 | 2632 | events->exception.pad = 0; |
3cfc3092 JK |
2633 | events->exception.error_code = vcpu->arch.exception.error_code; |
2634 | ||
03b82a30 JK |
2635 | events->interrupt.injected = |
2636 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 2637 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 2638 | events->interrupt.soft = 0; |
48005f64 JK |
2639 | events->interrupt.shadow = |
2640 | kvm_x86_ops->get_interrupt_shadow(vcpu, | |
2641 | KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI); | |
3cfc3092 JK |
2642 | |
2643 | events->nmi.injected = vcpu->arch.nmi_injected; | |
2644 | events->nmi.pending = vcpu->arch.nmi_pending; | |
2645 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); | |
97e69aa6 | 2646 | events->nmi.pad = 0; |
3cfc3092 JK |
2647 | |
2648 | events->sipi_vector = vcpu->arch.sipi_vector; | |
2649 | ||
dab4b911 | 2650 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2651 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2652 | | KVM_VCPUEVENT_VALID_SHADOW); | |
97e69aa6 | 2653 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
2654 | } |
2655 | ||
2656 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
2657 | struct kvm_vcpu_events *events) | |
2658 | { | |
dab4b911 | 2659 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2660 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2661 | | KVM_VCPUEVENT_VALID_SHADOW)) | |
3cfc3092 JK |
2662 | return -EINVAL; |
2663 | ||
3cfc3092 JK |
2664 | vcpu->arch.exception.pending = events->exception.injected; |
2665 | vcpu->arch.exception.nr = events->exception.nr; | |
2666 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
2667 | vcpu->arch.exception.error_code = events->exception.error_code; | |
2668 | ||
2669 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
2670 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
2671 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
2672 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
2673 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
2674 | events->interrupt.shadow); | |
3cfc3092 JK |
2675 | |
2676 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
2677 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
2678 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
2679 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
2680 | ||
dab4b911 JK |
2681 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR) |
2682 | vcpu->arch.sipi_vector = events->sipi_vector; | |
3cfc3092 | 2683 | |
3842d135 AK |
2684 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2685 | ||
3cfc3092 JK |
2686 | return 0; |
2687 | } | |
2688 | ||
a1efbe77 JK |
2689 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
2690 | struct kvm_debugregs *dbgregs) | |
2691 | { | |
a1efbe77 JK |
2692 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
2693 | dbgregs->dr6 = vcpu->arch.dr6; | |
2694 | dbgregs->dr7 = vcpu->arch.dr7; | |
2695 | dbgregs->flags = 0; | |
97e69aa6 | 2696 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
2697 | } |
2698 | ||
2699 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
2700 | struct kvm_debugregs *dbgregs) | |
2701 | { | |
2702 | if (dbgregs->flags) | |
2703 | return -EINVAL; | |
2704 | ||
a1efbe77 JK |
2705 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
2706 | vcpu->arch.dr6 = dbgregs->dr6; | |
2707 | vcpu->arch.dr7 = dbgregs->dr7; | |
2708 | ||
a1efbe77 JK |
2709 | return 0; |
2710 | } | |
2711 | ||
2d5b5a66 SY |
2712 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
2713 | struct kvm_xsave *guest_xsave) | |
2714 | { | |
2715 | if (cpu_has_xsave) | |
2716 | memcpy(guest_xsave->region, | |
2717 | &vcpu->arch.guest_fpu.state->xsave, | |
f45755b8 | 2718 | xstate_size); |
2d5b5a66 SY |
2719 | else { |
2720 | memcpy(guest_xsave->region, | |
2721 | &vcpu->arch.guest_fpu.state->fxsave, | |
2722 | sizeof(struct i387_fxsave_struct)); | |
2723 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = | |
2724 | XSTATE_FPSSE; | |
2725 | } | |
2726 | } | |
2727 | ||
2728 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
2729 | struct kvm_xsave *guest_xsave) | |
2730 | { | |
2731 | u64 xstate_bv = | |
2732 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
2733 | ||
2734 | if (cpu_has_xsave) | |
2735 | memcpy(&vcpu->arch.guest_fpu.state->xsave, | |
f45755b8 | 2736 | guest_xsave->region, xstate_size); |
2d5b5a66 SY |
2737 | else { |
2738 | if (xstate_bv & ~XSTATE_FPSSE) | |
2739 | return -EINVAL; | |
2740 | memcpy(&vcpu->arch.guest_fpu.state->fxsave, | |
2741 | guest_xsave->region, sizeof(struct i387_fxsave_struct)); | |
2742 | } | |
2743 | return 0; | |
2744 | } | |
2745 | ||
2746 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
2747 | struct kvm_xcrs *guest_xcrs) | |
2748 | { | |
2749 | if (!cpu_has_xsave) { | |
2750 | guest_xcrs->nr_xcrs = 0; | |
2751 | return; | |
2752 | } | |
2753 | ||
2754 | guest_xcrs->nr_xcrs = 1; | |
2755 | guest_xcrs->flags = 0; | |
2756 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
2757 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
2758 | } | |
2759 | ||
2760 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
2761 | struct kvm_xcrs *guest_xcrs) | |
2762 | { | |
2763 | int i, r = 0; | |
2764 | ||
2765 | if (!cpu_has_xsave) | |
2766 | return -EINVAL; | |
2767 | ||
2768 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
2769 | return -EINVAL; | |
2770 | ||
2771 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
2772 | /* Only support XCR0 currently */ | |
2773 | if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) { | |
2774 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, | |
2775 | guest_xcrs->xcrs[0].value); | |
2776 | break; | |
2777 | } | |
2778 | if (r) | |
2779 | r = -EINVAL; | |
2780 | return r; | |
2781 | } | |
2782 | ||
313a3dc7 CO |
2783 | long kvm_arch_vcpu_ioctl(struct file *filp, |
2784 | unsigned int ioctl, unsigned long arg) | |
2785 | { | |
2786 | struct kvm_vcpu *vcpu = filp->private_data; | |
2787 | void __user *argp = (void __user *)arg; | |
2788 | int r; | |
d1ac91d8 AK |
2789 | union { |
2790 | struct kvm_lapic_state *lapic; | |
2791 | struct kvm_xsave *xsave; | |
2792 | struct kvm_xcrs *xcrs; | |
2793 | void *buffer; | |
2794 | } u; | |
2795 | ||
2796 | u.buffer = NULL; | |
313a3dc7 CO |
2797 | switch (ioctl) { |
2798 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
2799 | r = -EINVAL; |
2800 | if (!vcpu->arch.apic) | |
2801 | goto out; | |
d1ac91d8 | 2802 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 2803 | |
b772ff36 | 2804 | r = -ENOMEM; |
d1ac91d8 | 2805 | if (!u.lapic) |
b772ff36 | 2806 | goto out; |
d1ac91d8 | 2807 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
2808 | if (r) |
2809 | goto out; | |
2810 | r = -EFAULT; | |
d1ac91d8 | 2811 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
2812 | goto out; |
2813 | r = 0; | |
2814 | break; | |
2815 | } | |
2816 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
2817 | r = -EINVAL; |
2818 | if (!vcpu->arch.apic) | |
2819 | goto out; | |
d1ac91d8 | 2820 | u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
b772ff36 | 2821 | r = -ENOMEM; |
d1ac91d8 | 2822 | if (!u.lapic) |
b772ff36 | 2823 | goto out; |
313a3dc7 | 2824 | r = -EFAULT; |
d1ac91d8 | 2825 | if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state))) |
313a3dc7 | 2826 | goto out; |
d1ac91d8 | 2827 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
2828 | if (r) |
2829 | goto out; | |
2830 | r = 0; | |
2831 | break; | |
2832 | } | |
f77bc6a4 ZX |
2833 | case KVM_INTERRUPT: { |
2834 | struct kvm_interrupt irq; | |
2835 | ||
2836 | r = -EFAULT; | |
2837 | if (copy_from_user(&irq, argp, sizeof irq)) | |
2838 | goto out; | |
2839 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
2840 | if (r) | |
2841 | goto out; | |
2842 | r = 0; | |
2843 | break; | |
2844 | } | |
c4abb7c9 JK |
2845 | case KVM_NMI: { |
2846 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
2847 | if (r) | |
2848 | goto out; | |
2849 | r = 0; | |
2850 | break; | |
2851 | } | |
313a3dc7 CO |
2852 | case KVM_SET_CPUID: { |
2853 | struct kvm_cpuid __user *cpuid_arg = argp; | |
2854 | struct kvm_cpuid cpuid; | |
2855 | ||
2856 | r = -EFAULT; | |
2857 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2858 | goto out; | |
2859 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
2860 | if (r) | |
2861 | goto out; | |
2862 | break; | |
2863 | } | |
07716717 DK |
2864 | case KVM_SET_CPUID2: { |
2865 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2866 | struct kvm_cpuid2 cpuid; | |
2867 | ||
2868 | r = -EFAULT; | |
2869 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2870 | goto out; | |
2871 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 2872 | cpuid_arg->entries); |
07716717 DK |
2873 | if (r) |
2874 | goto out; | |
2875 | break; | |
2876 | } | |
2877 | case KVM_GET_CPUID2: { | |
2878 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2879 | struct kvm_cpuid2 cpuid; | |
2880 | ||
2881 | r = -EFAULT; | |
2882 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2883 | goto out; | |
2884 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 2885 | cpuid_arg->entries); |
07716717 DK |
2886 | if (r) |
2887 | goto out; | |
2888 | r = -EFAULT; | |
2889 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2890 | goto out; | |
2891 | r = 0; | |
2892 | break; | |
2893 | } | |
313a3dc7 CO |
2894 | case KVM_GET_MSRS: |
2895 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
2896 | break; | |
2897 | case KVM_SET_MSRS: | |
2898 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
2899 | break; | |
b209749f AK |
2900 | case KVM_TPR_ACCESS_REPORTING: { |
2901 | struct kvm_tpr_access_ctl tac; | |
2902 | ||
2903 | r = -EFAULT; | |
2904 | if (copy_from_user(&tac, argp, sizeof tac)) | |
2905 | goto out; | |
2906 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
2907 | if (r) | |
2908 | goto out; | |
2909 | r = -EFAULT; | |
2910 | if (copy_to_user(argp, &tac, sizeof tac)) | |
2911 | goto out; | |
2912 | r = 0; | |
2913 | break; | |
2914 | }; | |
b93463aa AK |
2915 | case KVM_SET_VAPIC_ADDR: { |
2916 | struct kvm_vapic_addr va; | |
2917 | ||
2918 | r = -EINVAL; | |
2919 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2920 | goto out; | |
2921 | r = -EFAULT; | |
2922 | if (copy_from_user(&va, argp, sizeof va)) | |
2923 | goto out; | |
2924 | r = 0; | |
2925 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
2926 | break; | |
2927 | } | |
890ca9ae HY |
2928 | case KVM_X86_SETUP_MCE: { |
2929 | u64 mcg_cap; | |
2930 | ||
2931 | r = -EFAULT; | |
2932 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
2933 | goto out; | |
2934 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
2935 | break; | |
2936 | } | |
2937 | case KVM_X86_SET_MCE: { | |
2938 | struct kvm_x86_mce mce; | |
2939 | ||
2940 | r = -EFAULT; | |
2941 | if (copy_from_user(&mce, argp, sizeof mce)) | |
2942 | goto out; | |
2943 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
2944 | break; | |
2945 | } | |
3cfc3092 JK |
2946 | case KVM_GET_VCPU_EVENTS: { |
2947 | struct kvm_vcpu_events events; | |
2948 | ||
2949 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
2950 | ||
2951 | r = -EFAULT; | |
2952 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
2953 | break; | |
2954 | r = 0; | |
2955 | break; | |
2956 | } | |
2957 | case KVM_SET_VCPU_EVENTS: { | |
2958 | struct kvm_vcpu_events events; | |
2959 | ||
2960 | r = -EFAULT; | |
2961 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
2962 | break; | |
2963 | ||
2964 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
2965 | break; | |
2966 | } | |
a1efbe77 JK |
2967 | case KVM_GET_DEBUGREGS: { |
2968 | struct kvm_debugregs dbgregs; | |
2969 | ||
2970 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
2971 | ||
2972 | r = -EFAULT; | |
2973 | if (copy_to_user(argp, &dbgregs, | |
2974 | sizeof(struct kvm_debugregs))) | |
2975 | break; | |
2976 | r = 0; | |
2977 | break; | |
2978 | } | |
2979 | case KVM_SET_DEBUGREGS: { | |
2980 | struct kvm_debugregs dbgregs; | |
2981 | ||
2982 | r = -EFAULT; | |
2983 | if (copy_from_user(&dbgregs, argp, | |
2984 | sizeof(struct kvm_debugregs))) | |
2985 | break; | |
2986 | ||
2987 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
2988 | break; | |
2989 | } | |
2d5b5a66 | 2990 | case KVM_GET_XSAVE: { |
d1ac91d8 | 2991 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 2992 | r = -ENOMEM; |
d1ac91d8 | 2993 | if (!u.xsave) |
2d5b5a66 SY |
2994 | break; |
2995 | ||
d1ac91d8 | 2996 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
2997 | |
2998 | r = -EFAULT; | |
d1ac91d8 | 2999 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
3000 | break; |
3001 | r = 0; | |
3002 | break; | |
3003 | } | |
3004 | case KVM_SET_XSAVE: { | |
d1ac91d8 | 3005 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 3006 | r = -ENOMEM; |
d1ac91d8 | 3007 | if (!u.xsave) |
2d5b5a66 SY |
3008 | break; |
3009 | ||
3010 | r = -EFAULT; | |
d1ac91d8 | 3011 | if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
3012 | break; |
3013 | ||
d1ac91d8 | 3014 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3015 | break; |
3016 | } | |
3017 | case KVM_GET_XCRS: { | |
d1ac91d8 | 3018 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 3019 | r = -ENOMEM; |
d1ac91d8 | 3020 | if (!u.xcrs) |
2d5b5a66 SY |
3021 | break; |
3022 | ||
d1ac91d8 | 3023 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3024 | |
3025 | r = -EFAULT; | |
d1ac91d8 | 3026 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
3027 | sizeof(struct kvm_xcrs))) |
3028 | break; | |
3029 | r = 0; | |
3030 | break; | |
3031 | } | |
3032 | case KVM_SET_XCRS: { | |
d1ac91d8 | 3033 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 3034 | r = -ENOMEM; |
d1ac91d8 | 3035 | if (!u.xcrs) |
2d5b5a66 SY |
3036 | break; |
3037 | ||
3038 | r = -EFAULT; | |
d1ac91d8 | 3039 | if (copy_from_user(u.xcrs, argp, |
2d5b5a66 SY |
3040 | sizeof(struct kvm_xcrs))) |
3041 | break; | |
3042 | ||
d1ac91d8 | 3043 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3044 | break; |
3045 | } | |
313a3dc7 CO |
3046 | default: |
3047 | r = -EINVAL; | |
3048 | } | |
3049 | out: | |
d1ac91d8 | 3050 | kfree(u.buffer); |
313a3dc7 CO |
3051 | return r; |
3052 | } | |
3053 | ||
1fe779f8 CO |
3054 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
3055 | { | |
3056 | int ret; | |
3057 | ||
3058 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
3059 | return -1; | |
3060 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); | |
3061 | return ret; | |
3062 | } | |
3063 | ||
b927a3ce SY |
3064 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
3065 | u64 ident_addr) | |
3066 | { | |
3067 | kvm->arch.ept_identity_map_addr = ident_addr; | |
3068 | return 0; | |
3069 | } | |
3070 | ||
1fe779f8 CO |
3071 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
3072 | u32 kvm_nr_mmu_pages) | |
3073 | { | |
3074 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
3075 | return -EINVAL; | |
3076 | ||
79fac95e | 3077 | mutex_lock(&kvm->slots_lock); |
7c8a83b7 | 3078 | spin_lock(&kvm->mmu_lock); |
1fe779f8 CO |
3079 | |
3080 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 3081 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 3082 | |
7c8a83b7 | 3083 | spin_unlock(&kvm->mmu_lock); |
79fac95e | 3084 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
3085 | return 0; |
3086 | } | |
3087 | ||
3088 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
3089 | { | |
39de71ec | 3090 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
3091 | } |
3092 | ||
1fe779f8 CO |
3093 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
3094 | { | |
3095 | int r; | |
3096 | ||
3097 | r = 0; | |
3098 | switch (chip->chip_id) { | |
3099 | case KVM_IRQCHIP_PIC_MASTER: | |
3100 | memcpy(&chip->chip.pic, | |
3101 | &pic_irqchip(kvm)->pics[0], | |
3102 | sizeof(struct kvm_pic_state)); | |
3103 | break; | |
3104 | case KVM_IRQCHIP_PIC_SLAVE: | |
3105 | memcpy(&chip->chip.pic, | |
3106 | &pic_irqchip(kvm)->pics[1], | |
3107 | sizeof(struct kvm_pic_state)); | |
3108 | break; | |
3109 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3110 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3111 | break; |
3112 | default: | |
3113 | r = -EINVAL; | |
3114 | break; | |
3115 | } | |
3116 | return r; | |
3117 | } | |
3118 | ||
3119 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
3120 | { | |
3121 | int r; | |
3122 | ||
3123 | r = 0; | |
3124 | switch (chip->chip_id) { | |
3125 | case KVM_IRQCHIP_PIC_MASTER: | |
f4f51050 | 3126 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3127 | memcpy(&pic_irqchip(kvm)->pics[0], |
3128 | &chip->chip.pic, | |
3129 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3130 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3131 | break; |
3132 | case KVM_IRQCHIP_PIC_SLAVE: | |
f4f51050 | 3133 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3134 | memcpy(&pic_irqchip(kvm)->pics[1], |
3135 | &chip->chip.pic, | |
3136 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3137 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3138 | break; |
3139 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3140 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3141 | break; |
3142 | default: | |
3143 | r = -EINVAL; | |
3144 | break; | |
3145 | } | |
3146 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
3147 | return r; | |
3148 | } | |
3149 | ||
e0f63cb9 SY |
3150 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
3151 | { | |
3152 | int r = 0; | |
3153 | ||
894a9c55 | 3154 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3155 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 3156 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3157 | return r; |
3158 | } | |
3159 | ||
3160 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3161 | { | |
3162 | int r = 0; | |
3163 | ||
894a9c55 | 3164 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3165 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
3166 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
3167 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3168 | return r; | |
3169 | } | |
3170 | ||
3171 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3172 | { | |
3173 | int r = 0; | |
3174 | ||
3175 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3176 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3177 | sizeof(ps->channels)); | |
3178 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3179 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 3180 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
e9f42757 BK |
3181 | return r; |
3182 | } | |
3183 | ||
3184 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3185 | { | |
3186 | int r = 0, start = 0; | |
3187 | u32 prev_legacy, cur_legacy; | |
3188 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3189 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3190 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3191 | if (!prev_legacy && cur_legacy) | |
3192 | start = 1; | |
3193 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
3194 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
3195 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
3196 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 3197 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3198 | return r; |
3199 | } | |
3200 | ||
52d939a0 MT |
3201 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
3202 | struct kvm_reinject_control *control) | |
3203 | { | |
3204 | if (!kvm->arch.vpit) | |
3205 | return -ENXIO; | |
894a9c55 | 3206 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 | 3207 | kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject; |
894a9c55 | 3208 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
3209 | return 0; |
3210 | } | |
3211 | ||
5bb064dc ZX |
3212 | /* |
3213 | * Get (and clear) the dirty memory log for a memory slot. | |
3214 | */ | |
3215 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, | |
3216 | struct kvm_dirty_log *log) | |
3217 | { | |
87bf6e7d | 3218 | int r, i; |
5bb064dc | 3219 | struct kvm_memory_slot *memslot; |
87bf6e7d | 3220 | unsigned long n; |
b050b015 | 3221 | unsigned long is_dirty = 0; |
5bb064dc | 3222 | |
79fac95e | 3223 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 3224 | |
b050b015 MT |
3225 | r = -EINVAL; |
3226 | if (log->slot >= KVM_MEMORY_SLOTS) | |
3227 | goto out; | |
3228 | ||
3229 | memslot = &kvm->memslots->memslots[log->slot]; | |
3230 | r = -ENOENT; | |
3231 | if (!memslot->dirty_bitmap) | |
3232 | goto out; | |
3233 | ||
87bf6e7d | 3234 | n = kvm_dirty_bitmap_bytes(memslot); |
b050b015 | 3235 | |
b050b015 MT |
3236 | for (i = 0; !is_dirty && i < n/sizeof(long); i++) |
3237 | is_dirty = memslot->dirty_bitmap[i]; | |
5bb064dc ZX |
3238 | |
3239 | /* If nothing is dirty, don't bother messing with page tables. */ | |
3240 | if (is_dirty) { | |
b050b015 | 3241 | struct kvm_memslots *slots, *old_slots; |
914ebccd | 3242 | unsigned long *dirty_bitmap; |
b050b015 | 3243 | |
515a0127 TY |
3244 | dirty_bitmap = memslot->dirty_bitmap_head; |
3245 | if (memslot->dirty_bitmap == dirty_bitmap) | |
3246 | dirty_bitmap += n / sizeof(long); | |
914ebccd | 3247 | memset(dirty_bitmap, 0, n); |
b050b015 | 3248 | |
914ebccd TY |
3249 | r = -ENOMEM; |
3250 | slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL); | |
515a0127 | 3251 | if (!slots) |
914ebccd | 3252 | goto out; |
b050b015 MT |
3253 | memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots)); |
3254 | slots->memslots[log->slot].dirty_bitmap = dirty_bitmap; | |
49c7754c | 3255 | slots->generation++; |
b050b015 MT |
3256 | |
3257 | old_slots = kvm->memslots; | |
3258 | rcu_assign_pointer(kvm->memslots, slots); | |
3259 | synchronize_srcu_expedited(&kvm->srcu); | |
3260 | dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap; | |
3261 | kfree(old_slots); | |
914ebccd | 3262 | |
edde99ce MT |
3263 | spin_lock(&kvm->mmu_lock); |
3264 | kvm_mmu_slot_remove_write_access(kvm, log->slot); | |
3265 | spin_unlock(&kvm->mmu_lock); | |
3266 | ||
914ebccd | 3267 | r = -EFAULT; |
515a0127 | 3268 | if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) |
914ebccd | 3269 | goto out; |
914ebccd TY |
3270 | } else { |
3271 | r = -EFAULT; | |
3272 | if (clear_user(log->dirty_bitmap, n)) | |
3273 | goto out; | |
5bb064dc | 3274 | } |
b050b015 | 3275 | |
5bb064dc ZX |
3276 | r = 0; |
3277 | out: | |
79fac95e | 3278 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
3279 | return r; |
3280 | } | |
3281 | ||
1fe779f8 CO |
3282 | long kvm_arch_vm_ioctl(struct file *filp, |
3283 | unsigned int ioctl, unsigned long arg) | |
3284 | { | |
3285 | struct kvm *kvm = filp->private_data; | |
3286 | void __user *argp = (void __user *)arg; | |
367e1319 | 3287 | int r = -ENOTTY; |
f0d66275 DH |
3288 | /* |
3289 | * This union makes it completely explicit to gcc-3.x | |
3290 | * that these two variables' stack usage should be | |
3291 | * combined, not added together. | |
3292 | */ | |
3293 | union { | |
3294 | struct kvm_pit_state ps; | |
e9f42757 | 3295 | struct kvm_pit_state2 ps2; |
c5ff41ce | 3296 | struct kvm_pit_config pit_config; |
f0d66275 | 3297 | } u; |
1fe779f8 CO |
3298 | |
3299 | switch (ioctl) { | |
3300 | case KVM_SET_TSS_ADDR: | |
3301 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
3302 | if (r < 0) | |
3303 | goto out; | |
3304 | break; | |
b927a3ce SY |
3305 | case KVM_SET_IDENTITY_MAP_ADDR: { |
3306 | u64 ident_addr; | |
3307 | ||
3308 | r = -EFAULT; | |
3309 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
3310 | goto out; | |
3311 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
3312 | if (r < 0) | |
3313 | goto out; | |
3314 | break; | |
3315 | } | |
1fe779f8 CO |
3316 | case KVM_SET_NR_MMU_PAGES: |
3317 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
3318 | if (r) | |
3319 | goto out; | |
3320 | break; | |
3321 | case KVM_GET_NR_MMU_PAGES: | |
3322 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
3323 | break; | |
3ddea128 MT |
3324 | case KVM_CREATE_IRQCHIP: { |
3325 | struct kvm_pic *vpic; | |
3326 | ||
3327 | mutex_lock(&kvm->lock); | |
3328 | r = -EEXIST; | |
3329 | if (kvm->arch.vpic) | |
3330 | goto create_irqchip_unlock; | |
1fe779f8 | 3331 | r = -ENOMEM; |
3ddea128 MT |
3332 | vpic = kvm_create_pic(kvm); |
3333 | if (vpic) { | |
1fe779f8 CO |
3334 | r = kvm_ioapic_init(kvm); |
3335 | if (r) { | |
175504cd | 3336 | mutex_lock(&kvm->slots_lock); |
72bb2fcd WY |
3337 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, |
3338 | &vpic->dev); | |
175504cd | 3339 | mutex_unlock(&kvm->slots_lock); |
3ddea128 MT |
3340 | kfree(vpic); |
3341 | goto create_irqchip_unlock; | |
1fe779f8 CO |
3342 | } |
3343 | } else | |
3ddea128 MT |
3344 | goto create_irqchip_unlock; |
3345 | smp_wmb(); | |
3346 | kvm->arch.vpic = vpic; | |
3347 | smp_wmb(); | |
399ec807 AK |
3348 | r = kvm_setup_default_irq_routing(kvm); |
3349 | if (r) { | |
175504cd | 3350 | mutex_lock(&kvm->slots_lock); |
3ddea128 | 3351 | mutex_lock(&kvm->irq_lock); |
72bb2fcd WY |
3352 | kvm_ioapic_destroy(kvm); |
3353 | kvm_destroy_pic(kvm); | |
3ddea128 | 3354 | mutex_unlock(&kvm->irq_lock); |
175504cd | 3355 | mutex_unlock(&kvm->slots_lock); |
399ec807 | 3356 | } |
3ddea128 MT |
3357 | create_irqchip_unlock: |
3358 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 3359 | break; |
3ddea128 | 3360 | } |
7837699f | 3361 | case KVM_CREATE_PIT: |
c5ff41ce JK |
3362 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
3363 | goto create_pit; | |
3364 | case KVM_CREATE_PIT2: | |
3365 | r = -EFAULT; | |
3366 | if (copy_from_user(&u.pit_config, argp, | |
3367 | sizeof(struct kvm_pit_config))) | |
3368 | goto out; | |
3369 | create_pit: | |
79fac95e | 3370 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
3371 | r = -EEXIST; |
3372 | if (kvm->arch.vpit) | |
3373 | goto create_pit_unlock; | |
7837699f | 3374 | r = -ENOMEM; |
c5ff41ce | 3375 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
3376 | if (kvm->arch.vpit) |
3377 | r = 0; | |
269e05e4 | 3378 | create_pit_unlock: |
79fac95e | 3379 | mutex_unlock(&kvm->slots_lock); |
7837699f | 3380 | break; |
4925663a | 3381 | case KVM_IRQ_LINE_STATUS: |
1fe779f8 CO |
3382 | case KVM_IRQ_LINE: { |
3383 | struct kvm_irq_level irq_event; | |
3384 | ||
3385 | r = -EFAULT; | |
3386 | if (copy_from_user(&irq_event, argp, sizeof irq_event)) | |
3387 | goto out; | |
160d2f6c | 3388 | r = -ENXIO; |
1fe779f8 | 3389 | if (irqchip_in_kernel(kvm)) { |
4925663a | 3390 | __s32 status; |
4925663a GN |
3391 | status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, |
3392 | irq_event.irq, irq_event.level); | |
4925663a | 3393 | if (ioctl == KVM_IRQ_LINE_STATUS) { |
160d2f6c | 3394 | r = -EFAULT; |
4925663a GN |
3395 | irq_event.status = status; |
3396 | if (copy_to_user(argp, &irq_event, | |
3397 | sizeof irq_event)) | |
3398 | goto out; | |
3399 | } | |
1fe779f8 CO |
3400 | r = 0; |
3401 | } | |
3402 | break; | |
3403 | } | |
3404 | case KVM_GET_IRQCHIP: { | |
3405 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 3406 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 3407 | |
f0d66275 DH |
3408 | r = -ENOMEM; |
3409 | if (!chip) | |
1fe779f8 | 3410 | goto out; |
f0d66275 DH |
3411 | r = -EFAULT; |
3412 | if (copy_from_user(chip, argp, sizeof *chip)) | |
3413 | goto get_irqchip_out; | |
1fe779f8 CO |
3414 | r = -ENXIO; |
3415 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3416 | goto get_irqchip_out; |
3417 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 3418 | if (r) |
f0d66275 | 3419 | goto get_irqchip_out; |
1fe779f8 | 3420 | r = -EFAULT; |
f0d66275 DH |
3421 | if (copy_to_user(argp, chip, sizeof *chip)) |
3422 | goto get_irqchip_out; | |
1fe779f8 | 3423 | r = 0; |
f0d66275 DH |
3424 | get_irqchip_out: |
3425 | kfree(chip); | |
3426 | if (r) | |
3427 | goto out; | |
1fe779f8 CO |
3428 | break; |
3429 | } | |
3430 | case KVM_SET_IRQCHIP: { | |
3431 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 3432 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 3433 | |
f0d66275 DH |
3434 | r = -ENOMEM; |
3435 | if (!chip) | |
1fe779f8 | 3436 | goto out; |
f0d66275 DH |
3437 | r = -EFAULT; |
3438 | if (copy_from_user(chip, argp, sizeof *chip)) | |
3439 | goto set_irqchip_out; | |
1fe779f8 CO |
3440 | r = -ENXIO; |
3441 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3442 | goto set_irqchip_out; |
3443 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 3444 | if (r) |
f0d66275 | 3445 | goto set_irqchip_out; |
1fe779f8 | 3446 | r = 0; |
f0d66275 DH |
3447 | set_irqchip_out: |
3448 | kfree(chip); | |
3449 | if (r) | |
3450 | goto out; | |
1fe779f8 CO |
3451 | break; |
3452 | } | |
e0f63cb9 | 3453 | case KVM_GET_PIT: { |
e0f63cb9 | 3454 | r = -EFAULT; |
f0d66275 | 3455 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3456 | goto out; |
3457 | r = -ENXIO; | |
3458 | if (!kvm->arch.vpit) | |
3459 | goto out; | |
f0d66275 | 3460 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
3461 | if (r) |
3462 | goto out; | |
3463 | r = -EFAULT; | |
f0d66275 | 3464 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3465 | goto out; |
3466 | r = 0; | |
3467 | break; | |
3468 | } | |
3469 | case KVM_SET_PIT: { | |
e0f63cb9 | 3470 | r = -EFAULT; |
f0d66275 | 3471 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
3472 | goto out; |
3473 | r = -ENXIO; | |
3474 | if (!kvm->arch.vpit) | |
3475 | goto out; | |
f0d66275 | 3476 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
3477 | if (r) |
3478 | goto out; | |
3479 | r = 0; | |
3480 | break; | |
3481 | } | |
e9f42757 BK |
3482 | case KVM_GET_PIT2: { |
3483 | r = -ENXIO; | |
3484 | if (!kvm->arch.vpit) | |
3485 | goto out; | |
3486 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
3487 | if (r) | |
3488 | goto out; | |
3489 | r = -EFAULT; | |
3490 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
3491 | goto out; | |
3492 | r = 0; | |
3493 | break; | |
3494 | } | |
3495 | case KVM_SET_PIT2: { | |
3496 | r = -EFAULT; | |
3497 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
3498 | goto out; | |
3499 | r = -ENXIO; | |
3500 | if (!kvm->arch.vpit) | |
3501 | goto out; | |
3502 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
3503 | if (r) | |
3504 | goto out; | |
3505 | r = 0; | |
3506 | break; | |
3507 | } | |
52d939a0 MT |
3508 | case KVM_REINJECT_CONTROL: { |
3509 | struct kvm_reinject_control control; | |
3510 | r = -EFAULT; | |
3511 | if (copy_from_user(&control, argp, sizeof(control))) | |
3512 | goto out; | |
3513 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
3514 | if (r) | |
3515 | goto out; | |
3516 | r = 0; | |
3517 | break; | |
3518 | } | |
ffde22ac ES |
3519 | case KVM_XEN_HVM_CONFIG: { |
3520 | r = -EFAULT; | |
3521 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
3522 | sizeof(struct kvm_xen_hvm_config))) | |
3523 | goto out; | |
3524 | r = -EINVAL; | |
3525 | if (kvm->arch.xen_hvm_config.flags) | |
3526 | goto out; | |
3527 | r = 0; | |
3528 | break; | |
3529 | } | |
afbcf7ab | 3530 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
3531 | struct kvm_clock_data user_ns; |
3532 | u64 now_ns; | |
3533 | s64 delta; | |
3534 | ||
3535 | r = -EFAULT; | |
3536 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
3537 | goto out; | |
3538 | ||
3539 | r = -EINVAL; | |
3540 | if (user_ns.flags) | |
3541 | goto out; | |
3542 | ||
3543 | r = 0; | |
395c6b0a | 3544 | local_irq_disable(); |
759379dd | 3545 | now_ns = get_kernel_ns(); |
afbcf7ab | 3546 | delta = user_ns.clock - now_ns; |
395c6b0a | 3547 | local_irq_enable(); |
afbcf7ab GC |
3548 | kvm->arch.kvmclock_offset = delta; |
3549 | break; | |
3550 | } | |
3551 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
3552 | struct kvm_clock_data user_ns; |
3553 | u64 now_ns; | |
3554 | ||
395c6b0a | 3555 | local_irq_disable(); |
759379dd | 3556 | now_ns = get_kernel_ns(); |
afbcf7ab | 3557 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; |
395c6b0a | 3558 | local_irq_enable(); |
afbcf7ab | 3559 | user_ns.flags = 0; |
97e69aa6 | 3560 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
3561 | |
3562 | r = -EFAULT; | |
3563 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
3564 | goto out; | |
3565 | r = 0; | |
3566 | break; | |
3567 | } | |
3568 | ||
1fe779f8 CO |
3569 | default: |
3570 | ; | |
3571 | } | |
3572 | out: | |
3573 | return r; | |
3574 | } | |
3575 | ||
a16b043c | 3576 | static void kvm_init_msr_list(void) |
043405e1 CO |
3577 | { |
3578 | u32 dummy[2]; | |
3579 | unsigned i, j; | |
3580 | ||
e3267cbb GC |
3581 | /* skip the first msrs in the list. KVM-specific */ |
3582 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
043405e1 CO |
3583 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
3584 | continue; | |
3585 | if (j < i) | |
3586 | msrs_to_save[j] = msrs_to_save[i]; | |
3587 | j++; | |
3588 | } | |
3589 | num_msrs_to_save = j; | |
3590 | } | |
3591 | ||
bda9020e MT |
3592 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
3593 | const void *v) | |
bbd9b64e | 3594 | { |
bda9020e MT |
3595 | if (vcpu->arch.apic && |
3596 | !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v)) | |
3597 | return 0; | |
bbd9b64e | 3598 | |
e93f8a0f | 3599 | return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v); |
bbd9b64e CO |
3600 | } |
3601 | ||
bda9020e | 3602 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 3603 | { |
bda9020e MT |
3604 | if (vcpu->arch.apic && |
3605 | !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v)) | |
3606 | return 0; | |
bbd9b64e | 3607 | |
e93f8a0f | 3608 | return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v); |
bbd9b64e CO |
3609 | } |
3610 | ||
2dafc6c2 GN |
3611 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
3612 | struct kvm_segment *var, int seg) | |
3613 | { | |
3614 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
3615 | } | |
3616 | ||
3617 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
3618 | struct kvm_segment *var, int seg) | |
3619 | { | |
3620 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
3621 | } | |
3622 | ||
c30a358d JR |
3623 | static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
3624 | { | |
3625 | return gpa; | |
3626 | } | |
3627 | ||
02f59dc9 JR |
3628 | static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
3629 | { | |
3630 | gpa_t t_gpa; | |
ab9ae313 | 3631 | struct x86_exception exception; |
02f59dc9 JR |
3632 | |
3633 | BUG_ON(!mmu_is_nested(vcpu)); | |
3634 | ||
3635 | /* NPT walks are always user-walks */ | |
3636 | access |= PFERR_USER_MASK; | |
ab9ae313 | 3637 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception); |
02f59dc9 JR |
3638 | |
3639 | return t_gpa; | |
3640 | } | |
3641 | ||
ab9ae313 AK |
3642 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
3643 | struct x86_exception *exception) | |
1871c602 GN |
3644 | { |
3645 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 3646 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3647 | } |
3648 | ||
ab9ae313 AK |
3649 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
3650 | struct x86_exception *exception) | |
1871c602 GN |
3651 | { |
3652 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3653 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 3654 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3655 | } |
3656 | ||
ab9ae313 AK |
3657 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
3658 | struct x86_exception *exception) | |
1871c602 GN |
3659 | { |
3660 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3661 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 3662 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3663 | } |
3664 | ||
3665 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
3666 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
3667 | struct x86_exception *exception) | |
1871c602 | 3668 | { |
ab9ae313 | 3669 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
3670 | } |
3671 | ||
3672 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
3673 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 3674 | struct x86_exception *exception) |
bbd9b64e CO |
3675 | { |
3676 | void *data = val; | |
10589a46 | 3677 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
3678 | |
3679 | while (bytes) { | |
14dfe855 | 3680 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 3681 | exception); |
bbd9b64e | 3682 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 3683 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
3684 | int ret; |
3685 | ||
bcc55cba | 3686 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 3687 | return X86EMUL_PROPAGATE_FAULT; |
77c2002e | 3688 | ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); |
10589a46 | 3689 | if (ret < 0) { |
c3cd7ffa | 3690 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
3691 | goto out; |
3692 | } | |
bbd9b64e | 3693 | |
77c2002e IE |
3694 | bytes -= toread; |
3695 | data += toread; | |
3696 | addr += toread; | |
bbd9b64e | 3697 | } |
10589a46 | 3698 | out: |
10589a46 | 3699 | return r; |
bbd9b64e | 3700 | } |
77c2002e | 3701 | |
1871c602 GN |
3702 | /* used for instruction fetching */ |
3703 | static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes, | |
bcc55cba AK |
3704 | struct kvm_vcpu *vcpu, |
3705 | struct x86_exception *exception) | |
1871c602 GN |
3706 | { |
3707 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3708 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, | |
bcc55cba AK |
3709 | access | PFERR_FETCH_MASK, |
3710 | exception); | |
1871c602 GN |
3711 | } |
3712 | ||
3713 | static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes, | |
bcc55cba AK |
3714 | struct kvm_vcpu *vcpu, |
3715 | struct x86_exception *exception) | |
1871c602 GN |
3716 | { |
3717 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3718 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, | |
bcc55cba | 3719 | exception); |
1871c602 GN |
3720 | } |
3721 | ||
3722 | static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes, | |
bcc55cba AK |
3723 | struct kvm_vcpu *vcpu, |
3724 | struct x86_exception *exception) | |
1871c602 | 3725 | { |
bcc55cba | 3726 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); |
1871c602 GN |
3727 | } |
3728 | ||
7972995b | 3729 | static int kvm_write_guest_virt_system(gva_t addr, void *val, |
2dafc6c2 | 3730 | unsigned int bytes, |
7972995b | 3731 | struct kvm_vcpu *vcpu, |
bcc55cba | 3732 | struct x86_exception *exception) |
77c2002e IE |
3733 | { |
3734 | void *data = val; | |
3735 | int r = X86EMUL_CONTINUE; | |
3736 | ||
3737 | while (bytes) { | |
14dfe855 JR |
3738 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
3739 | PFERR_WRITE_MASK, | |
ab9ae313 | 3740 | exception); |
77c2002e IE |
3741 | unsigned offset = addr & (PAGE_SIZE-1); |
3742 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
3743 | int ret; | |
3744 | ||
bcc55cba | 3745 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 3746 | return X86EMUL_PROPAGATE_FAULT; |
77c2002e IE |
3747 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); |
3748 | if (ret < 0) { | |
c3cd7ffa | 3749 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
3750 | goto out; |
3751 | } | |
3752 | ||
3753 | bytes -= towrite; | |
3754 | data += towrite; | |
3755 | addr += towrite; | |
3756 | } | |
3757 | out: | |
3758 | return r; | |
3759 | } | |
3760 | ||
bbd9b64e CO |
3761 | static int emulator_read_emulated(unsigned long addr, |
3762 | void *val, | |
3763 | unsigned int bytes, | |
bcc55cba | 3764 | struct x86_exception *exception, |
bbd9b64e CO |
3765 | struct kvm_vcpu *vcpu) |
3766 | { | |
bbd9b64e CO |
3767 | gpa_t gpa; |
3768 | ||
3769 | if (vcpu->mmio_read_completed) { | |
3770 | memcpy(val, vcpu->mmio_data, bytes); | |
aec51dc4 AK |
3771 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
3772 | vcpu->mmio_phys_addr, *(u64 *)val); | |
bbd9b64e CO |
3773 | vcpu->mmio_read_completed = 0; |
3774 | return X86EMUL_CONTINUE; | |
3775 | } | |
3776 | ||
ab9ae313 | 3777 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception); |
1871c602 | 3778 | |
8fe681e9 | 3779 | if (gpa == UNMAPPED_GVA) |
1871c602 | 3780 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
3781 | |
3782 | /* For APIC access vmexit */ | |
3783 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3784 | goto mmio; | |
3785 | ||
bcc55cba AK |
3786 | if (kvm_read_guest_virt(addr, val, bytes, vcpu, exception) |
3787 | == X86EMUL_CONTINUE) | |
bbd9b64e | 3788 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
3789 | |
3790 | mmio: | |
3791 | /* | |
3792 | * Is this MMIO handled locally? | |
3793 | */ | |
aec51dc4 AK |
3794 | if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) { |
3795 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val); | |
bbd9b64e CO |
3796 | return X86EMUL_CONTINUE; |
3797 | } | |
aec51dc4 AK |
3798 | |
3799 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
bbd9b64e CO |
3800 | |
3801 | vcpu->mmio_needed = 1; | |
411c35b7 GN |
3802 | vcpu->run->exit_reason = KVM_EXIT_MMIO; |
3803 | vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa; | |
3804 | vcpu->run->mmio.len = vcpu->mmio_size = bytes; | |
3805 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0; | |
bbd9b64e | 3806 | |
c3cd7ffa | 3807 | return X86EMUL_IO_NEEDED; |
bbd9b64e CO |
3808 | } |
3809 | ||
3200f405 | 3810 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 3811 | const void *val, int bytes) |
bbd9b64e CO |
3812 | { |
3813 | int ret; | |
3814 | ||
3815 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 3816 | if (ret < 0) |
bbd9b64e | 3817 | return 0; |
ad218f85 | 3818 | kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1); |
bbd9b64e CO |
3819 | return 1; |
3820 | } | |
3821 | ||
3822 | static int emulator_write_emulated_onepage(unsigned long addr, | |
3823 | const void *val, | |
3824 | unsigned int bytes, | |
bcc55cba | 3825 | struct x86_exception *exception, |
bbd9b64e CO |
3826 | struct kvm_vcpu *vcpu) |
3827 | { | |
10589a46 MT |
3828 | gpa_t gpa; |
3829 | ||
ab9ae313 | 3830 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception); |
bbd9b64e | 3831 | |
8fe681e9 | 3832 | if (gpa == UNMAPPED_GVA) |
bbd9b64e | 3833 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
3834 | |
3835 | /* For APIC access vmexit */ | |
3836 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3837 | goto mmio; | |
3838 | ||
3839 | if (emulator_write_phys(vcpu, gpa, val, bytes)) | |
3840 | return X86EMUL_CONTINUE; | |
3841 | ||
3842 | mmio: | |
aec51dc4 | 3843 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); |
bbd9b64e CO |
3844 | /* |
3845 | * Is this MMIO handled locally? | |
3846 | */ | |
bda9020e | 3847 | if (!vcpu_mmio_write(vcpu, gpa, bytes, val)) |
bbd9b64e | 3848 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
3849 | |
3850 | vcpu->mmio_needed = 1; | |
411c35b7 GN |
3851 | vcpu->run->exit_reason = KVM_EXIT_MMIO; |
3852 | vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa; | |
3853 | vcpu->run->mmio.len = vcpu->mmio_size = bytes; | |
3854 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1; | |
3855 | memcpy(vcpu->run->mmio.data, val, bytes); | |
bbd9b64e CO |
3856 | |
3857 | return X86EMUL_CONTINUE; | |
3858 | } | |
3859 | ||
3860 | int emulator_write_emulated(unsigned long addr, | |
8f6abd06 GN |
3861 | const void *val, |
3862 | unsigned int bytes, | |
bcc55cba | 3863 | struct x86_exception *exception, |
8f6abd06 | 3864 | struct kvm_vcpu *vcpu) |
bbd9b64e CO |
3865 | { |
3866 | /* Crossing a page boundary? */ | |
3867 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
3868 | int rc, now; | |
3869 | ||
3870 | now = -addr & ~PAGE_MASK; | |
bcc55cba | 3871 | rc = emulator_write_emulated_onepage(addr, val, now, exception, |
8fe681e9 | 3872 | vcpu); |
bbd9b64e CO |
3873 | if (rc != X86EMUL_CONTINUE) |
3874 | return rc; | |
3875 | addr += now; | |
3876 | val += now; | |
3877 | bytes -= now; | |
3878 | } | |
bcc55cba | 3879 | return emulator_write_emulated_onepage(addr, val, bytes, exception, |
8fe681e9 | 3880 | vcpu); |
bbd9b64e | 3881 | } |
bbd9b64e | 3882 | |
daea3e73 AK |
3883 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
3884 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
3885 | ||
3886 | #ifdef CONFIG_X86_64 | |
3887 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
3888 | #else | |
3889 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 3890 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
3891 | #endif |
3892 | ||
bbd9b64e CO |
3893 | static int emulator_cmpxchg_emulated(unsigned long addr, |
3894 | const void *old, | |
3895 | const void *new, | |
3896 | unsigned int bytes, | |
bcc55cba | 3897 | struct x86_exception *exception, |
bbd9b64e CO |
3898 | struct kvm_vcpu *vcpu) |
3899 | { | |
daea3e73 AK |
3900 | gpa_t gpa; |
3901 | struct page *page; | |
3902 | char *kaddr; | |
3903 | bool exchanged; | |
2bacc55c | 3904 | |
daea3e73 AK |
3905 | /* guests cmpxchg8b have to be emulated atomically */ |
3906 | if (bytes > 8 || (bytes & (bytes - 1))) | |
3907 | goto emul_write; | |
10589a46 | 3908 | |
daea3e73 | 3909 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 3910 | |
daea3e73 AK |
3911 | if (gpa == UNMAPPED_GVA || |
3912 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3913 | goto emul_write; | |
2bacc55c | 3914 | |
daea3e73 AK |
3915 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
3916 | goto emul_write; | |
72dc67a6 | 3917 | |
daea3e73 | 3918 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
c19b8bd6 WY |
3919 | if (is_error_page(page)) { |
3920 | kvm_release_page_clean(page); | |
3921 | goto emul_write; | |
3922 | } | |
72dc67a6 | 3923 | |
daea3e73 AK |
3924 | kaddr = kmap_atomic(page, KM_USER0); |
3925 | kaddr += offset_in_page(gpa); | |
3926 | switch (bytes) { | |
3927 | case 1: | |
3928 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
3929 | break; | |
3930 | case 2: | |
3931 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
3932 | break; | |
3933 | case 4: | |
3934 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
3935 | break; | |
3936 | case 8: | |
3937 | exchanged = CMPXCHG64(kaddr, old, new); | |
3938 | break; | |
3939 | default: | |
3940 | BUG(); | |
2bacc55c | 3941 | } |
daea3e73 AK |
3942 | kunmap_atomic(kaddr, KM_USER0); |
3943 | kvm_release_page_dirty(page); | |
3944 | ||
3945 | if (!exchanged) | |
3946 | return X86EMUL_CMPXCHG_FAILED; | |
3947 | ||
8f6abd06 GN |
3948 | kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1); |
3949 | ||
3950 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 3951 | |
3200f405 | 3952 | emul_write: |
daea3e73 | 3953 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 3954 | |
bcc55cba | 3955 | return emulator_write_emulated(addr, new, bytes, exception, vcpu); |
bbd9b64e CO |
3956 | } |
3957 | ||
cf8f70bf GN |
3958 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
3959 | { | |
3960 | /* TODO: String I/O for in kernel device */ | |
3961 | int r; | |
3962 | ||
3963 | if (vcpu->arch.pio.in) | |
3964 | r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, | |
3965 | vcpu->arch.pio.size, pd); | |
3966 | else | |
3967 | r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, | |
3968 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
3969 | pd); | |
3970 | return r; | |
3971 | } | |
3972 | ||
3973 | ||
3974 | static int emulator_pio_in_emulated(int size, unsigned short port, void *val, | |
3975 | unsigned int count, struct kvm_vcpu *vcpu) | |
3976 | { | |
7972995b | 3977 | if (vcpu->arch.pio.count) |
cf8f70bf GN |
3978 | goto data_avail; |
3979 | ||
61cfab2e | 3980 | trace_kvm_pio(0, port, size, count); |
cf8f70bf GN |
3981 | |
3982 | vcpu->arch.pio.port = port; | |
3983 | vcpu->arch.pio.in = 1; | |
7972995b | 3984 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
3985 | vcpu->arch.pio.size = size; |
3986 | ||
3987 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
3988 | data_avail: | |
3989 | memcpy(val, vcpu->arch.pio_data, size * count); | |
7972995b | 3990 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
3991 | return 1; |
3992 | } | |
3993 | ||
3994 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
3995 | vcpu->run->io.direction = KVM_EXIT_IO_IN; | |
3996 | vcpu->run->io.size = size; | |
3997 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
3998 | vcpu->run->io.count = count; | |
3999 | vcpu->run->io.port = port; | |
4000 | ||
4001 | return 0; | |
4002 | } | |
4003 | ||
4004 | static int emulator_pio_out_emulated(int size, unsigned short port, | |
4005 | const void *val, unsigned int count, | |
4006 | struct kvm_vcpu *vcpu) | |
4007 | { | |
61cfab2e | 4008 | trace_kvm_pio(1, port, size, count); |
cf8f70bf GN |
4009 | |
4010 | vcpu->arch.pio.port = port; | |
4011 | vcpu->arch.pio.in = 0; | |
7972995b | 4012 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
4013 | vcpu->arch.pio.size = size; |
4014 | ||
4015 | memcpy(vcpu->arch.pio_data, val, size * count); | |
4016 | ||
4017 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 4018 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4019 | return 1; |
4020 | } | |
4021 | ||
4022 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
4023 | vcpu->run->io.direction = KVM_EXIT_IO_OUT; | |
4024 | vcpu->run->io.size = size; | |
4025 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
4026 | vcpu->run->io.count = count; | |
4027 | vcpu->run->io.port = port; | |
4028 | ||
4029 | return 0; | |
4030 | } | |
4031 | ||
bbd9b64e CO |
4032 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4033 | { | |
4034 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
4035 | } | |
4036 | ||
4037 | int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
4038 | { | |
a7052897 | 4039 | kvm_mmu_invlpg(vcpu, address); |
bbd9b64e CO |
4040 | return X86EMUL_CONTINUE; |
4041 | } | |
4042 | ||
f5f48ee1 SY |
4043 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) |
4044 | { | |
4045 | if (!need_emulate_wbinvd(vcpu)) | |
4046 | return X86EMUL_CONTINUE; | |
4047 | ||
4048 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
4049 | int cpu = get_cpu(); |
4050 | ||
4051 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
4052 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
4053 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 4054 | put_cpu(); |
f5f48ee1 | 4055 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
4056 | } else |
4057 | wbinvd(); | |
f5f48ee1 SY |
4058 | return X86EMUL_CONTINUE; |
4059 | } | |
4060 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); | |
4061 | ||
bbd9b64e CO |
4062 | int emulate_clts(struct kvm_vcpu *vcpu) |
4063 | { | |
4d4ec087 | 4064 | kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); |
6b52d186 | 4065 | kvm_x86_ops->fpu_activate(vcpu); |
bbd9b64e CO |
4066 | return X86EMUL_CONTINUE; |
4067 | } | |
4068 | ||
35aa5375 | 4069 | int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu) |
bbd9b64e | 4070 | { |
338dbc97 | 4071 | return _kvm_get_dr(vcpu, dr, dest); |
bbd9b64e CO |
4072 | } |
4073 | ||
35aa5375 | 4074 | int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu) |
bbd9b64e | 4075 | { |
338dbc97 GN |
4076 | |
4077 | return __kvm_set_dr(vcpu, dr, value); | |
bbd9b64e CO |
4078 | } |
4079 | ||
52a46617 | 4080 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 4081 | { |
52a46617 | 4082 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
4083 | } |
4084 | ||
52a46617 | 4085 | static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu) |
bbd9b64e | 4086 | { |
52a46617 GN |
4087 | unsigned long value; |
4088 | ||
4089 | switch (cr) { | |
4090 | case 0: | |
4091 | value = kvm_read_cr0(vcpu); | |
4092 | break; | |
4093 | case 2: | |
4094 | value = vcpu->arch.cr2; | |
4095 | break; | |
4096 | case 3: | |
9f8fe504 | 4097 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
4098 | break; |
4099 | case 4: | |
4100 | value = kvm_read_cr4(vcpu); | |
4101 | break; | |
4102 | case 8: | |
4103 | value = kvm_get_cr8(vcpu); | |
4104 | break; | |
4105 | default: | |
4106 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); | |
4107 | return 0; | |
4108 | } | |
4109 | ||
4110 | return value; | |
4111 | } | |
4112 | ||
0f12244f | 4113 | static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu) |
52a46617 | 4114 | { |
0f12244f GN |
4115 | int res = 0; |
4116 | ||
52a46617 GN |
4117 | switch (cr) { |
4118 | case 0: | |
49a9b07e | 4119 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
4120 | break; |
4121 | case 2: | |
4122 | vcpu->arch.cr2 = val; | |
4123 | break; | |
4124 | case 3: | |
2390218b | 4125 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
4126 | break; |
4127 | case 4: | |
a83b29c6 | 4128 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
4129 | break; |
4130 | case 8: | |
eea1cff9 | 4131 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
4132 | break; |
4133 | default: | |
4134 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); | |
0f12244f | 4135 | res = -1; |
52a46617 | 4136 | } |
0f12244f GN |
4137 | |
4138 | return res; | |
52a46617 GN |
4139 | } |
4140 | ||
9c537244 GN |
4141 | static int emulator_get_cpl(struct kvm_vcpu *vcpu) |
4142 | { | |
4143 | return kvm_x86_ops->get_cpl(vcpu); | |
4144 | } | |
4145 | ||
2dafc6c2 GN |
4146 | static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu) |
4147 | { | |
4148 | kvm_x86_ops->get_gdt(vcpu, dt); | |
4149 | } | |
4150 | ||
160ce1f1 MG |
4151 | static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu) |
4152 | { | |
4153 | kvm_x86_ops->get_idt(vcpu, dt); | |
4154 | } | |
4155 | ||
5951c442 GN |
4156 | static unsigned long emulator_get_cached_segment_base(int seg, |
4157 | struct kvm_vcpu *vcpu) | |
4158 | { | |
4159 | return get_segment_base(vcpu, seg); | |
4160 | } | |
4161 | ||
2dafc6c2 GN |
4162 | static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg, |
4163 | struct kvm_vcpu *vcpu) | |
4164 | { | |
4165 | struct kvm_segment var; | |
4166 | ||
4167 | kvm_get_segment(vcpu, &var, seg); | |
4168 | ||
4169 | if (var.unusable) | |
4170 | return false; | |
4171 | ||
4172 | if (var.g) | |
4173 | var.limit >>= 12; | |
4174 | set_desc_limit(desc, var.limit); | |
4175 | set_desc_base(desc, (unsigned long)var.base); | |
4176 | desc->type = var.type; | |
4177 | desc->s = var.s; | |
4178 | desc->dpl = var.dpl; | |
4179 | desc->p = var.present; | |
4180 | desc->avl = var.avl; | |
4181 | desc->l = var.l; | |
4182 | desc->d = var.db; | |
4183 | desc->g = var.g; | |
4184 | ||
4185 | return true; | |
4186 | } | |
4187 | ||
4188 | static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg, | |
4189 | struct kvm_vcpu *vcpu) | |
4190 | { | |
4191 | struct kvm_segment var; | |
4192 | ||
4193 | /* needed to preserve selector */ | |
4194 | kvm_get_segment(vcpu, &var, seg); | |
4195 | ||
4196 | var.base = get_desc_base(desc); | |
4197 | var.limit = get_desc_limit(desc); | |
4198 | if (desc->g) | |
4199 | var.limit = (var.limit << 12) | 0xfff; | |
4200 | var.type = desc->type; | |
4201 | var.present = desc->p; | |
4202 | var.dpl = desc->dpl; | |
4203 | var.db = desc->d; | |
4204 | var.s = desc->s; | |
4205 | var.l = desc->l; | |
4206 | var.g = desc->g; | |
4207 | var.avl = desc->avl; | |
4208 | var.present = desc->p; | |
4209 | var.unusable = !var.present; | |
4210 | var.padding = 0; | |
4211 | ||
4212 | kvm_set_segment(vcpu, &var, seg); | |
4213 | return; | |
4214 | } | |
4215 | ||
4216 | static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu) | |
4217 | { | |
4218 | struct kvm_segment kvm_seg; | |
4219 | ||
4220 | kvm_get_segment(vcpu, &kvm_seg, seg); | |
4221 | return kvm_seg.selector; | |
4222 | } | |
4223 | ||
4224 | static void emulator_set_segment_selector(u16 sel, int seg, | |
4225 | struct kvm_vcpu *vcpu) | |
4226 | { | |
4227 | struct kvm_segment kvm_seg; | |
4228 | ||
4229 | kvm_get_segment(vcpu, &kvm_seg, seg); | |
4230 | kvm_seg.selector = sel; | |
4231 | kvm_set_segment(vcpu, &kvm_seg, seg); | |
4232 | } | |
4233 | ||
14af3f3c | 4234 | static struct x86_emulate_ops emulate_ops = { |
1871c602 | 4235 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 4236 | .write_std = kvm_write_guest_virt_system, |
1871c602 | 4237 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
4238 | .read_emulated = emulator_read_emulated, |
4239 | .write_emulated = emulator_write_emulated, | |
4240 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
cf8f70bf GN |
4241 | .pio_in_emulated = emulator_pio_in_emulated, |
4242 | .pio_out_emulated = emulator_pio_out_emulated, | |
2dafc6c2 GN |
4243 | .get_cached_descriptor = emulator_get_cached_descriptor, |
4244 | .set_cached_descriptor = emulator_set_cached_descriptor, | |
4245 | .get_segment_selector = emulator_get_segment_selector, | |
4246 | .set_segment_selector = emulator_set_segment_selector, | |
5951c442 | 4247 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 4248 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 4249 | .get_idt = emulator_get_idt, |
52a46617 GN |
4250 | .get_cr = emulator_get_cr, |
4251 | .set_cr = emulator_set_cr, | |
9c537244 | 4252 | .cpl = emulator_get_cpl, |
35aa5375 GN |
4253 | .get_dr = emulator_get_dr, |
4254 | .set_dr = emulator_set_dr, | |
3fb1b5db GN |
4255 | .set_msr = kvm_set_msr, |
4256 | .get_msr = kvm_get_msr, | |
bbd9b64e CO |
4257 | }; |
4258 | ||
5fdbf976 MT |
4259 | static void cache_all_regs(struct kvm_vcpu *vcpu) |
4260 | { | |
4261 | kvm_register_read(vcpu, VCPU_REGS_RAX); | |
4262 | kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4263 | kvm_register_read(vcpu, VCPU_REGS_RIP); | |
4264 | vcpu->arch.regs_dirty = ~0; | |
4265 | } | |
4266 | ||
95cb2295 GN |
4267 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
4268 | { | |
4269 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask); | |
4270 | /* | |
4271 | * an sti; sti; sequence only disable interrupts for the first | |
4272 | * instruction. So, if the last instruction, be it emulated or | |
4273 | * not, left the system with the INT_STI flag enabled, it | |
4274 | * means that the last instruction is an sti. We should not | |
4275 | * leave the flag on in this case. The same goes for mov ss | |
4276 | */ | |
4277 | if (!(int_shadow & mask)) | |
4278 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); | |
4279 | } | |
4280 | ||
54b8486f GN |
4281 | static void inject_emulated_exception(struct kvm_vcpu *vcpu) |
4282 | { | |
4283 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 4284 | if (ctxt->exception.vector == PF_VECTOR) |
6389ee94 | 4285 | kvm_propagate_fault(vcpu, &ctxt->exception); |
da9cb575 AK |
4286 | else if (ctxt->exception.error_code_valid) |
4287 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, | |
4288 | ctxt->exception.error_code); | |
54b8486f | 4289 | else |
da9cb575 | 4290 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
54b8486f GN |
4291 | } |
4292 | ||
8ec4722d MG |
4293 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
4294 | { | |
4295 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; | |
4296 | int cs_db, cs_l; | |
4297 | ||
4298 | cache_all_regs(vcpu); | |
4299 | ||
4300 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
4301 | ||
4302 | vcpu->arch.emulate_ctxt.vcpu = vcpu; | |
4303 | vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu); | |
4304 | vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu); | |
4305 | vcpu->arch.emulate_ctxt.mode = | |
4306 | (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
4307 | (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM) | |
4308 | ? X86EMUL_MODE_VM86 : cs_l | |
4309 | ? X86EMUL_MODE_PROT64 : cs_db | |
4310 | ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; | |
4311 | memset(c, 0, sizeof(struct decode_cache)); | |
4312 | memcpy(c->regs, vcpu->arch.regs, sizeof c->regs); | |
4313 | } | |
4314 | ||
63995653 MG |
4315 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq) |
4316 | { | |
4317 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; | |
4318 | int ret; | |
4319 | ||
4320 | init_emulate_ctxt(vcpu); | |
4321 | ||
4322 | vcpu->arch.emulate_ctxt.decode.op_bytes = 2; | |
4323 | vcpu->arch.emulate_ctxt.decode.ad_bytes = 2; | |
4324 | vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip; | |
4325 | ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq); | |
4326 | ||
4327 | if (ret != X86EMUL_CONTINUE) | |
4328 | return EMULATE_FAIL; | |
4329 | ||
4330 | vcpu->arch.emulate_ctxt.eip = c->eip; | |
4331 | memcpy(vcpu->arch.regs, c->regs, sizeof c->regs); | |
4332 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip); | |
4333 | kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); | |
4334 | ||
4335 | if (irq == NMI_VECTOR) | |
4336 | vcpu->arch.nmi_pending = false; | |
4337 | else | |
4338 | vcpu->arch.interrupt.pending = false; | |
4339 | ||
4340 | return EMULATE_DONE; | |
4341 | } | |
4342 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
4343 | ||
6d77dbfc GN |
4344 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
4345 | { | |
fc3a9157 JR |
4346 | int r = EMULATE_DONE; |
4347 | ||
6d77dbfc GN |
4348 | ++vcpu->stat.insn_emulation_fail; |
4349 | trace_kvm_emulate_insn_failed(vcpu); | |
fc3a9157 JR |
4350 | if (!is_guest_mode(vcpu)) { |
4351 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
4352 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
4353 | vcpu->run->internal.ndata = 0; | |
4354 | r = EMULATE_FAIL; | |
4355 | } | |
6d77dbfc | 4356 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
4357 | |
4358 | return r; | |
6d77dbfc GN |
4359 | } |
4360 | ||
a6f177ef GN |
4361 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva) |
4362 | { | |
4363 | gpa_t gpa; | |
4364 | ||
68be0803 GN |
4365 | if (tdp_enabled) |
4366 | return false; | |
4367 | ||
a6f177ef GN |
4368 | /* |
4369 | * if emulation was due to access to shadowed page table | |
4370 | * and it failed try to unshadow page and re-entetr the | |
4371 | * guest to let CPU execute the instruction. | |
4372 | */ | |
4373 | if (kvm_mmu_unprotect_page_virt(vcpu, gva)) | |
4374 | return true; | |
4375 | ||
4376 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL); | |
4377 | ||
4378 | if (gpa == UNMAPPED_GVA) | |
4379 | return true; /* let cpu generate fault */ | |
4380 | ||
4381 | if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT))) | |
4382 | return true; | |
4383 | ||
4384 | return false; | |
4385 | } | |
4386 | ||
51d8b661 AP |
4387 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
4388 | unsigned long cr2, | |
dc25e89e AP |
4389 | int emulation_type, |
4390 | void *insn, | |
4391 | int insn_len) | |
bbd9b64e | 4392 | { |
95cb2295 | 4393 | int r; |
4d2179e1 | 4394 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; |
bbd9b64e | 4395 | |
26eef70c | 4396 | kvm_clear_exception_queue(vcpu); |
ad312c7c | 4397 | vcpu->arch.mmio_fault_cr2 = cr2; |
5fdbf976 | 4398 | /* |
56e82318 | 4399 | * TODO: fix emulate.c to use guest_read/write_register |
5fdbf976 MT |
4400 | * instead of direct ->regs accesses, can save hundred cycles |
4401 | * on Intel for instructions that don't read/change RSP, for | |
4402 | * for example. | |
4403 | */ | |
4404 | cache_all_regs(vcpu); | |
bbd9b64e | 4405 | |
571008da | 4406 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 4407 | init_emulate_ctxt(vcpu); |
95cb2295 | 4408 | vcpu->arch.emulate_ctxt.interruptibility = 0; |
da9cb575 | 4409 | vcpu->arch.emulate_ctxt.have_exception = false; |
4fc40f07 | 4410 | vcpu->arch.emulate_ctxt.perm_ok = false; |
bbd9b64e | 4411 | |
4005996e AK |
4412 | vcpu->arch.emulate_ctxt.only_vendor_specific_insn |
4413 | = emulation_type & EMULTYPE_TRAP_UD; | |
4414 | ||
dc25e89e | 4415 | r = x86_decode_insn(&vcpu->arch.emulate_ctxt, insn, insn_len); |
bbd9b64e | 4416 | |
e46479f8 | 4417 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 4418 | ++vcpu->stat.insn_emulation; |
bbd9b64e | 4419 | if (r) { |
4005996e AK |
4420 | if (emulation_type & EMULTYPE_TRAP_UD) |
4421 | return EMULATE_FAIL; | |
a6f177ef | 4422 | if (reexecute_instruction(vcpu, cr2)) |
bbd9b64e | 4423 | return EMULATE_DONE; |
6d77dbfc GN |
4424 | if (emulation_type & EMULTYPE_SKIP) |
4425 | return EMULATE_FAIL; | |
4426 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
4427 | } |
4428 | } | |
4429 | ||
ba8afb6b GN |
4430 | if (emulation_type & EMULTYPE_SKIP) { |
4431 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip); | |
4432 | return EMULATE_DONE; | |
4433 | } | |
4434 | ||
4d2179e1 GN |
4435 | /* this is needed for vmware backdor interface to work since it |
4436 | changes registers values during IO operation */ | |
4437 | memcpy(c->regs, vcpu->arch.regs, sizeof c->regs); | |
4438 | ||
5cd21917 | 4439 | restart: |
9aabc88f | 4440 | r = x86_emulate_insn(&vcpu->arch.emulate_ctxt); |
bbd9b64e | 4441 | |
d2ddd1c4 | 4442 | if (r == EMULATION_FAILED) { |
a6f177ef | 4443 | if (reexecute_instruction(vcpu, cr2)) |
c3cd7ffa GN |
4444 | return EMULATE_DONE; |
4445 | ||
6d77dbfc | 4446 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
4447 | } |
4448 | ||
da9cb575 | 4449 | if (vcpu->arch.emulate_ctxt.have_exception) { |
54b8486f | 4450 | inject_emulated_exception(vcpu); |
d2ddd1c4 GN |
4451 | r = EMULATE_DONE; |
4452 | } else if (vcpu->arch.pio.count) { | |
3457e419 GN |
4453 | if (!vcpu->arch.pio.in) |
4454 | vcpu->arch.pio.count = 0; | |
e85d28f8 GN |
4455 | r = EMULATE_DO_MMIO; |
4456 | } else if (vcpu->mmio_needed) { | |
3457e419 GN |
4457 | if (vcpu->mmio_is_write) |
4458 | vcpu->mmio_needed = 0; | |
e85d28f8 | 4459 | r = EMULATE_DO_MMIO; |
d2ddd1c4 | 4460 | } else if (r == EMULATION_RESTART) |
5cd21917 | 4461 | goto restart; |
d2ddd1c4 GN |
4462 | else |
4463 | r = EMULATE_DONE; | |
f850e2e6 | 4464 | |
e85d28f8 GN |
4465 | toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility); |
4466 | kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); | |
3842d135 | 4467 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e85d28f8 GN |
4468 | memcpy(vcpu->arch.regs, c->regs, sizeof c->regs); |
4469 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip); | |
4470 | ||
4471 | return r; | |
de7d789a | 4472 | } |
51d8b661 | 4473 | EXPORT_SYMBOL_GPL(x86_emulate_instruction); |
de7d789a | 4474 | |
cf8f70bf | 4475 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 4476 | { |
cf8f70bf GN |
4477 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4478 | int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu); | |
4479 | /* do not return to emulator after return from userspace */ | |
7972995b | 4480 | vcpu->arch.pio.count = 0; |
de7d789a CO |
4481 | return ret; |
4482 | } | |
cf8f70bf | 4483 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 4484 | |
8cfdc000 ZA |
4485 | static void tsc_bad(void *info) |
4486 | { | |
0a3aee0d | 4487 | __this_cpu_write(cpu_tsc_khz, 0); |
8cfdc000 ZA |
4488 | } |
4489 | ||
4490 | static void tsc_khz_changed(void *data) | |
c8076604 | 4491 | { |
8cfdc000 ZA |
4492 | struct cpufreq_freqs *freq = data; |
4493 | unsigned long khz = 0; | |
4494 | ||
4495 | if (data) | |
4496 | khz = freq->new; | |
4497 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
4498 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
4499 | if (!khz) | |
4500 | khz = tsc_khz; | |
0a3aee0d | 4501 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
4502 | } |
4503 | ||
c8076604 GH |
4504 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
4505 | void *data) | |
4506 | { | |
4507 | struct cpufreq_freqs *freq = data; | |
4508 | struct kvm *kvm; | |
4509 | struct kvm_vcpu *vcpu; | |
4510 | int i, send_ipi = 0; | |
4511 | ||
8cfdc000 ZA |
4512 | /* |
4513 | * We allow guests to temporarily run on slowing clocks, | |
4514 | * provided we notify them after, or to run on accelerating | |
4515 | * clocks, provided we notify them before. Thus time never | |
4516 | * goes backwards. | |
4517 | * | |
4518 | * However, we have a problem. We can't atomically update | |
4519 | * the frequency of a given CPU from this function; it is | |
4520 | * merely a notifier, which can be called from any CPU. | |
4521 | * Changing the TSC frequency at arbitrary points in time | |
4522 | * requires a recomputation of local variables related to | |
4523 | * the TSC for each VCPU. We must flag these local variables | |
4524 | * to be updated and be sure the update takes place with the | |
4525 | * new frequency before any guests proceed. | |
4526 | * | |
4527 | * Unfortunately, the combination of hotplug CPU and frequency | |
4528 | * change creates an intractable locking scenario; the order | |
4529 | * of when these callouts happen is undefined with respect to | |
4530 | * CPU hotplug, and they can race with each other. As such, | |
4531 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
4532 | * undefined; you can actually have a CPU frequency change take | |
4533 | * place in between the computation of X and the setting of the | |
4534 | * variable. To protect against this problem, all updates of | |
4535 | * the per_cpu tsc_khz variable are done in an interrupt | |
4536 | * protected IPI, and all callers wishing to update the value | |
4537 | * must wait for a synchronous IPI to complete (which is trivial | |
4538 | * if the caller is on the CPU already). This establishes the | |
4539 | * necessary total order on variable updates. | |
4540 | * | |
4541 | * Note that because a guest time update may take place | |
4542 | * anytime after the setting of the VCPU's request bit, the | |
4543 | * correct TSC value must be set before the request. However, | |
4544 | * to ensure the update actually makes it to any guest which | |
4545 | * starts running in hardware virtualization between the set | |
4546 | * and the acquisition of the spinlock, we must also ping the | |
4547 | * CPU after setting the request bit. | |
4548 | * | |
4549 | */ | |
4550 | ||
c8076604 GH |
4551 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
4552 | return 0; | |
4553 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
4554 | return 0; | |
8cfdc000 ZA |
4555 | |
4556 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 | 4557 | |
e935b837 | 4558 | raw_spin_lock(&kvm_lock); |
c8076604 | 4559 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 4560 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
4561 | if (vcpu->cpu != freq->cpu) |
4562 | continue; | |
c285545f | 4563 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c8076604 | 4564 | if (vcpu->cpu != smp_processor_id()) |
8cfdc000 | 4565 | send_ipi = 1; |
c8076604 GH |
4566 | } |
4567 | } | |
e935b837 | 4568 | raw_spin_unlock(&kvm_lock); |
c8076604 GH |
4569 | |
4570 | if (freq->old < freq->new && send_ipi) { | |
4571 | /* | |
4572 | * We upscale the frequency. Must make the guest | |
4573 | * doesn't see old kvmclock values while running with | |
4574 | * the new frequency, otherwise we risk the guest sees | |
4575 | * time go backwards. | |
4576 | * | |
4577 | * In case we update the frequency for another cpu | |
4578 | * (which might be in guest context) send an interrupt | |
4579 | * to kick the cpu out of guest context. Next time | |
4580 | * guest context is entered kvmclock will be updated, | |
4581 | * so the guest will not see stale values. | |
4582 | */ | |
8cfdc000 | 4583 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
4584 | } |
4585 | return 0; | |
4586 | } | |
4587 | ||
4588 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
4589 | .notifier_call = kvmclock_cpufreq_notifier |
4590 | }; | |
4591 | ||
4592 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
4593 | unsigned long action, void *hcpu) | |
4594 | { | |
4595 | unsigned int cpu = (unsigned long)hcpu; | |
4596 | ||
4597 | switch (action) { | |
4598 | case CPU_ONLINE: | |
4599 | case CPU_DOWN_FAILED: | |
4600 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
4601 | break; | |
4602 | case CPU_DOWN_PREPARE: | |
4603 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
4604 | break; | |
4605 | } | |
4606 | return NOTIFY_OK; | |
4607 | } | |
4608 | ||
4609 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
4610 | .notifier_call = kvmclock_cpu_notifier, | |
4611 | .priority = -INT_MAX | |
c8076604 GH |
4612 | }; |
4613 | ||
b820cc0c ZA |
4614 | static void kvm_timer_init(void) |
4615 | { | |
4616 | int cpu; | |
4617 | ||
c285545f | 4618 | max_tsc_khz = tsc_khz; |
8cfdc000 | 4619 | register_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
b820cc0c | 4620 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
4621 | #ifdef CONFIG_CPU_FREQ |
4622 | struct cpufreq_policy policy; | |
4623 | memset(&policy, 0, sizeof(policy)); | |
3e26f230 AK |
4624 | cpu = get_cpu(); |
4625 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
4626 | if (policy.cpuinfo.max_freq) |
4627 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 4628 | put_cpu(); |
c285545f | 4629 | #endif |
b820cc0c ZA |
4630 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
4631 | CPUFREQ_TRANSITION_NOTIFIER); | |
4632 | } | |
c285545f | 4633 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); |
8cfdc000 ZA |
4634 | for_each_online_cpu(cpu) |
4635 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
b820cc0c ZA |
4636 | } |
4637 | ||
ff9d07a0 ZY |
4638 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
4639 | ||
4640 | static int kvm_is_in_guest(void) | |
4641 | { | |
4642 | return percpu_read(current_vcpu) != NULL; | |
4643 | } | |
4644 | ||
4645 | static int kvm_is_user_mode(void) | |
4646 | { | |
4647 | int user_mode = 3; | |
dcf46b94 | 4648 | |
ff9d07a0 ZY |
4649 | if (percpu_read(current_vcpu)) |
4650 | user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu)); | |
dcf46b94 | 4651 | |
ff9d07a0 ZY |
4652 | return user_mode != 0; |
4653 | } | |
4654 | ||
4655 | static unsigned long kvm_get_guest_ip(void) | |
4656 | { | |
4657 | unsigned long ip = 0; | |
dcf46b94 | 4658 | |
ff9d07a0 ZY |
4659 | if (percpu_read(current_vcpu)) |
4660 | ip = kvm_rip_read(percpu_read(current_vcpu)); | |
dcf46b94 | 4661 | |
ff9d07a0 ZY |
4662 | return ip; |
4663 | } | |
4664 | ||
4665 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
4666 | .is_in_guest = kvm_is_in_guest, | |
4667 | .is_user_mode = kvm_is_user_mode, | |
4668 | .get_guest_ip = kvm_get_guest_ip, | |
4669 | }; | |
4670 | ||
4671 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
4672 | { | |
4673 | percpu_write(current_vcpu, vcpu); | |
4674 | } | |
4675 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
4676 | ||
4677 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
4678 | { | |
4679 | percpu_write(current_vcpu, NULL); | |
4680 | } | |
4681 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
4682 | ||
f8c16bba | 4683 | int kvm_arch_init(void *opaque) |
043405e1 | 4684 | { |
b820cc0c | 4685 | int r; |
f8c16bba ZX |
4686 | struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque; |
4687 | ||
f8c16bba ZX |
4688 | if (kvm_x86_ops) { |
4689 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
4690 | r = -EEXIST; |
4691 | goto out; | |
f8c16bba ZX |
4692 | } |
4693 | ||
4694 | if (!ops->cpu_has_kvm_support()) { | |
4695 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
4696 | r = -EOPNOTSUPP; |
4697 | goto out; | |
f8c16bba ZX |
4698 | } |
4699 | if (ops->disabled_by_bios()) { | |
4700 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
4701 | r = -EOPNOTSUPP; |
4702 | goto out; | |
f8c16bba ZX |
4703 | } |
4704 | ||
97db56ce AK |
4705 | r = kvm_mmu_module_init(); |
4706 | if (r) | |
4707 | goto out; | |
4708 | ||
4709 | kvm_init_msr_list(); | |
4710 | ||
f8c16bba | 4711 | kvm_x86_ops = ops; |
56c6d28a | 4712 | kvm_mmu_set_nonpresent_ptes(0ull, 0ull); |
7b52345e | 4713 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
4b12f0de | 4714 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 4715 | |
b820cc0c | 4716 | kvm_timer_init(); |
c8076604 | 4717 | |
ff9d07a0 ZY |
4718 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
4719 | ||
2acf923e DC |
4720 | if (cpu_has_xsave) |
4721 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
4722 | ||
f8c16bba | 4723 | return 0; |
56c6d28a ZX |
4724 | |
4725 | out: | |
56c6d28a | 4726 | return r; |
043405e1 | 4727 | } |
8776e519 | 4728 | |
f8c16bba ZX |
4729 | void kvm_arch_exit(void) |
4730 | { | |
ff9d07a0 ZY |
4731 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
4732 | ||
888d256e JK |
4733 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
4734 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
4735 | CPUFREQ_TRANSITION_NOTIFIER); | |
8cfdc000 | 4736 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
f8c16bba | 4737 | kvm_x86_ops = NULL; |
56c6d28a ZX |
4738 | kvm_mmu_module_exit(); |
4739 | } | |
f8c16bba | 4740 | |
8776e519 HB |
4741 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
4742 | { | |
4743 | ++vcpu->stat.halt_exits; | |
4744 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 4745 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
4746 | return 1; |
4747 | } else { | |
4748 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
4749 | return 0; | |
4750 | } | |
4751 | } | |
4752 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
4753 | ||
2f333bcb MT |
4754 | static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0, |
4755 | unsigned long a1) | |
4756 | { | |
4757 | if (is_long_mode(vcpu)) | |
4758 | return a0; | |
4759 | else | |
4760 | return a0 | ((gpa_t)a1 << 32); | |
4761 | } | |
4762 | ||
55cd8e5a GN |
4763 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
4764 | { | |
4765 | u64 param, ingpa, outgpa, ret; | |
4766 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
4767 | bool fast, longmode; | |
4768 | int cs_db, cs_l; | |
4769 | ||
4770 | /* | |
4771 | * hypercall generates UD from non zero cpl and real mode | |
4772 | * per HYPER-V spec | |
4773 | */ | |
3eeb3288 | 4774 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { |
55cd8e5a GN |
4775 | kvm_queue_exception(vcpu, UD_VECTOR); |
4776 | return 0; | |
4777 | } | |
4778 | ||
4779 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
4780 | longmode = is_long_mode(vcpu) && cs_l == 1; | |
4781 | ||
4782 | if (!longmode) { | |
ccd46936 GN |
4783 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
4784 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
4785 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
4786 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
4787 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
4788 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
4789 | } |
4790 | #ifdef CONFIG_X86_64 | |
4791 | else { | |
4792 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4793 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4794 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
4795 | } | |
4796 | #endif | |
4797 | ||
4798 | code = param & 0xffff; | |
4799 | fast = (param >> 16) & 0x1; | |
4800 | rep_cnt = (param >> 32) & 0xfff; | |
4801 | rep_idx = (param >> 48) & 0xfff; | |
4802 | ||
4803 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
4804 | ||
c25bc163 GN |
4805 | switch (code) { |
4806 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
4807 | kvm_vcpu_on_spin(vcpu); | |
4808 | break; | |
4809 | default: | |
4810 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
4811 | break; | |
4812 | } | |
55cd8e5a GN |
4813 | |
4814 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
4815 | if (longmode) { | |
4816 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
4817 | } else { | |
4818 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
4819 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
4820 | } | |
4821 | ||
4822 | return 1; | |
4823 | } | |
4824 | ||
8776e519 HB |
4825 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
4826 | { | |
4827 | unsigned long nr, a0, a1, a2, a3, ret; | |
2f333bcb | 4828 | int r = 1; |
8776e519 | 4829 | |
55cd8e5a GN |
4830 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
4831 | return kvm_hv_hypercall(vcpu); | |
4832 | ||
5fdbf976 MT |
4833 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4834 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4835 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4836 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4837 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 4838 | |
229456fc | 4839 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 4840 | |
8776e519 HB |
4841 | if (!is_long_mode(vcpu)) { |
4842 | nr &= 0xFFFFFFFF; | |
4843 | a0 &= 0xFFFFFFFF; | |
4844 | a1 &= 0xFFFFFFFF; | |
4845 | a2 &= 0xFFFFFFFF; | |
4846 | a3 &= 0xFFFFFFFF; | |
4847 | } | |
4848 | ||
07708c4a JK |
4849 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
4850 | ret = -KVM_EPERM; | |
4851 | goto out; | |
4852 | } | |
4853 | ||
8776e519 | 4854 | switch (nr) { |
b93463aa AK |
4855 | case KVM_HC_VAPIC_POLL_IRQ: |
4856 | ret = 0; | |
4857 | break; | |
2f333bcb MT |
4858 | case KVM_HC_MMU_OP: |
4859 | r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret); | |
4860 | break; | |
8776e519 HB |
4861 | default: |
4862 | ret = -KVM_ENOSYS; | |
4863 | break; | |
4864 | } | |
07708c4a | 4865 | out: |
5fdbf976 | 4866 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 4867 | ++vcpu->stat.hypercalls; |
2f333bcb | 4868 | return r; |
8776e519 HB |
4869 | } |
4870 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
4871 | ||
4872 | int kvm_fix_hypercall(struct kvm_vcpu *vcpu) | |
4873 | { | |
4874 | char instruction[3]; | |
5fdbf976 | 4875 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 4876 | |
8776e519 HB |
4877 | /* |
4878 | * Blow out the MMU to ensure that no other VCPU has an active mapping | |
4879 | * to ensure that the updated hypercall appears atomically across all | |
4880 | * VCPUs. | |
4881 | */ | |
4882 | kvm_mmu_zap_all(vcpu->kvm); | |
4883 | ||
8776e519 | 4884 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 4885 | |
8fe681e9 | 4886 | return emulator_write_emulated(rip, instruction, 3, NULL, vcpu); |
8776e519 HB |
4887 | } |
4888 | ||
8776e519 HB |
4889 | void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) |
4890 | { | |
89a27f4d | 4891 | struct desc_ptr dt = { limit, base }; |
8776e519 HB |
4892 | |
4893 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
4894 | } | |
4895 | ||
4896 | void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
4897 | { | |
89a27f4d | 4898 | struct desc_ptr dt = { limit, base }; |
8776e519 HB |
4899 | |
4900 | kvm_x86_ops->set_idt(vcpu, &dt); | |
4901 | } | |
4902 | ||
07716717 DK |
4903 | static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i) |
4904 | { | |
ad312c7c ZX |
4905 | struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i]; |
4906 | int j, nent = vcpu->arch.cpuid_nent; | |
07716717 DK |
4907 | |
4908 | e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT; | |
4909 | /* when no next entry is found, the current entry[i] is reselected */ | |
0fdf8e59 | 4910 | for (j = i + 1; ; j = (j + 1) % nent) { |
ad312c7c | 4911 | struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j]; |
07716717 DK |
4912 | if (ej->function == e->function) { |
4913 | ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; | |
4914 | return j; | |
4915 | } | |
4916 | } | |
4917 | return 0; /* silence gcc, even though control never reaches here */ | |
4918 | } | |
4919 | ||
4920 | /* find an entry with matching function, matching index (if needed), and that | |
4921 | * should be read next (if it's stateful) */ | |
4922 | static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e, | |
4923 | u32 function, u32 index) | |
4924 | { | |
4925 | if (e->function != function) | |
4926 | return 0; | |
4927 | if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index) | |
4928 | return 0; | |
4929 | if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) && | |
19355475 | 4930 | !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT)) |
07716717 DK |
4931 | return 0; |
4932 | return 1; | |
4933 | } | |
4934 | ||
d8017474 AG |
4935 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, |
4936 | u32 function, u32 index) | |
8776e519 HB |
4937 | { |
4938 | int i; | |
d8017474 | 4939 | struct kvm_cpuid_entry2 *best = NULL; |
8776e519 | 4940 | |
ad312c7c | 4941 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
d8017474 AG |
4942 | struct kvm_cpuid_entry2 *e; |
4943 | ||
ad312c7c | 4944 | e = &vcpu->arch.cpuid_entries[i]; |
07716717 DK |
4945 | if (is_matching_cpuid_entry(e, function, index)) { |
4946 | if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) | |
4947 | move_to_next_stateful_cpuid_entry(vcpu, i); | |
8776e519 HB |
4948 | best = e; |
4949 | break; | |
4950 | } | |
4951 | /* | |
4952 | * Both basic or both extended? | |
4953 | */ | |
4954 | if (((e->function ^ function) & 0x80000000) == 0) | |
4955 | if (!best || e->function > best->function) | |
4956 | best = e; | |
4957 | } | |
d8017474 AG |
4958 | return best; |
4959 | } | |
0e851880 | 4960 | EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); |
d8017474 | 4961 | |
82725b20 DE |
4962 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu) |
4963 | { | |
4964 | struct kvm_cpuid_entry2 *best; | |
4965 | ||
f7a71197 AK |
4966 | best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); |
4967 | if (!best || best->eax < 0x80000008) | |
4968 | goto not_found; | |
82725b20 DE |
4969 | best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); |
4970 | if (best) | |
4971 | return best->eax & 0xff; | |
f7a71197 | 4972 | not_found: |
82725b20 DE |
4973 | return 36; |
4974 | } | |
4975 | ||
d8017474 AG |
4976 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu) |
4977 | { | |
4978 | u32 function, index; | |
4979 | struct kvm_cpuid_entry2 *best; | |
4980 | ||
4981 | function = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
4982 | index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4983 | kvm_register_write(vcpu, VCPU_REGS_RAX, 0); | |
4984 | kvm_register_write(vcpu, VCPU_REGS_RBX, 0); | |
4985 | kvm_register_write(vcpu, VCPU_REGS_RCX, 0); | |
4986 | kvm_register_write(vcpu, VCPU_REGS_RDX, 0); | |
4987 | best = kvm_find_cpuid_entry(vcpu, function, index); | |
8776e519 | 4988 | if (best) { |
5fdbf976 MT |
4989 | kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax); |
4990 | kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx); | |
4991 | kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx); | |
4992 | kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx); | |
8776e519 | 4993 | } |
8776e519 | 4994 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
229456fc MT |
4995 | trace_kvm_cpuid(function, |
4996 | kvm_register_read(vcpu, VCPU_REGS_RAX), | |
4997 | kvm_register_read(vcpu, VCPU_REGS_RBX), | |
4998 | kvm_register_read(vcpu, VCPU_REGS_RCX), | |
4999 | kvm_register_read(vcpu, VCPU_REGS_RDX)); | |
8776e519 HB |
5000 | } |
5001 | EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); | |
d0752060 | 5002 | |
b6c7a5dc HB |
5003 | /* |
5004 | * Check if userspace requested an interrupt window, and that the | |
5005 | * interrupt window is open. | |
5006 | * | |
5007 | * No need to exit to userspace if we already have an interrupt queued. | |
5008 | */ | |
851ba692 | 5009 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 5010 | { |
8061823a | 5011 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 5012 | vcpu->run->request_interrupt_window && |
5df56646 | 5013 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
5014 | } |
5015 | ||
851ba692 | 5016 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 5017 | { |
851ba692 AK |
5018 | struct kvm_run *kvm_run = vcpu->run; |
5019 | ||
91586a3b | 5020 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
2d3ad1f4 | 5021 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 5022 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 5023 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 5024 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 5025 | else |
b6c7a5dc | 5026 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
5027 | kvm_arch_interrupt_allowed(vcpu) && |
5028 | !kvm_cpu_has_interrupt(vcpu) && | |
5029 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
5030 | } |
5031 | ||
b93463aa AK |
5032 | static void vapic_enter(struct kvm_vcpu *vcpu) |
5033 | { | |
5034 | struct kvm_lapic *apic = vcpu->arch.apic; | |
5035 | struct page *page; | |
5036 | ||
5037 | if (!apic || !apic->vapic_addr) | |
5038 | return; | |
5039 | ||
5040 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
72dc67a6 IE |
5041 | |
5042 | vcpu->arch.apic->vapic_page = page; | |
b93463aa AK |
5043 | } |
5044 | ||
5045 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
5046 | { | |
5047 | struct kvm_lapic *apic = vcpu->arch.apic; | |
f656ce01 | 5048 | int idx; |
b93463aa AK |
5049 | |
5050 | if (!apic || !apic->vapic_addr) | |
5051 | return; | |
5052 | ||
f656ce01 | 5053 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
b93463aa AK |
5054 | kvm_release_page_dirty(apic->vapic_page); |
5055 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
f656ce01 | 5056 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
5057 | } |
5058 | ||
95ba8273 GN |
5059 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
5060 | { | |
5061 | int max_irr, tpr; | |
5062 | ||
5063 | if (!kvm_x86_ops->update_cr8_intercept) | |
5064 | return; | |
5065 | ||
88c808fd AK |
5066 | if (!vcpu->arch.apic) |
5067 | return; | |
5068 | ||
8db3baa2 GN |
5069 | if (!vcpu->arch.apic->vapic_addr) |
5070 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
5071 | else | |
5072 | max_irr = -1; | |
95ba8273 GN |
5073 | |
5074 | if (max_irr != -1) | |
5075 | max_irr >>= 4; | |
5076 | ||
5077 | tpr = kvm_lapic_get_cr8(vcpu); | |
5078 | ||
5079 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
5080 | } | |
5081 | ||
851ba692 | 5082 | static void inject_pending_event(struct kvm_vcpu *vcpu) |
95ba8273 GN |
5083 | { |
5084 | /* try to reinject previous events if any */ | |
b59bb7bd | 5085 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
5086 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
5087 | vcpu->arch.exception.has_error_code, | |
5088 | vcpu->arch.exception.error_code); | |
b59bb7bd GN |
5089 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
5090 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
5091 | vcpu->arch.exception.error_code, |
5092 | vcpu->arch.exception.reinject); | |
b59bb7bd GN |
5093 | return; |
5094 | } | |
5095 | ||
95ba8273 GN |
5096 | if (vcpu->arch.nmi_injected) { |
5097 | kvm_x86_ops->set_nmi(vcpu); | |
5098 | return; | |
5099 | } | |
5100 | ||
5101 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 5102 | kvm_x86_ops->set_irq(vcpu); |
95ba8273 GN |
5103 | return; |
5104 | } | |
5105 | ||
5106 | /* try to inject new event if pending */ | |
5107 | if (vcpu->arch.nmi_pending) { | |
5108 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
5109 | vcpu->arch.nmi_pending = false; | |
5110 | vcpu->arch.nmi_injected = true; | |
5111 | kvm_x86_ops->set_nmi(vcpu); | |
5112 | } | |
5113 | } else if (kvm_cpu_has_interrupt(vcpu)) { | |
5114 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { | |
66fd3f7f GN |
5115 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
5116 | false); | |
5117 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
5118 | } |
5119 | } | |
5120 | } | |
5121 | ||
2acf923e DC |
5122 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
5123 | { | |
5124 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
5125 | !vcpu->guest_xcr0_loaded) { | |
5126 | /* kvm_set_xcr() also depends on this */ | |
5127 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
5128 | vcpu->guest_xcr0_loaded = 1; | |
5129 | } | |
5130 | } | |
5131 | ||
5132 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
5133 | { | |
5134 | if (vcpu->guest_xcr0_loaded) { | |
5135 | if (vcpu->arch.xcr0 != host_xcr0) | |
5136 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
5137 | vcpu->guest_xcr0_loaded = 0; | |
5138 | } | |
5139 | } | |
5140 | ||
851ba692 | 5141 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
5142 | { |
5143 | int r; | |
6a8b1d13 | 5144 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 5145 | vcpu->run->request_interrupt_window; |
b6c7a5dc | 5146 | |
3e007509 | 5147 | if (vcpu->requests) { |
a8eeb04a | 5148 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 5149 | kvm_mmu_unload(vcpu); |
a8eeb04a | 5150 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 5151 | __kvm_migrate_timers(vcpu); |
34c238a1 ZA |
5152 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
5153 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
5154 | if (unlikely(r)) |
5155 | goto out; | |
5156 | } | |
a8eeb04a | 5157 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 5158 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 5159 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
d4acf7e7 | 5160 | kvm_x86_ops->tlb_flush(vcpu); |
a8eeb04a | 5161 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 5162 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
5163 | r = 0; |
5164 | goto out; | |
5165 | } | |
a8eeb04a | 5166 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 5167 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
5168 | r = 0; |
5169 | goto out; | |
5170 | } | |
a8eeb04a | 5171 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
5172 | vcpu->fpu_active = 0; |
5173 | kvm_x86_ops->fpu_deactivate(vcpu); | |
5174 | } | |
af585b92 GN |
5175 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
5176 | /* Page is swapped out. Do synthetic halt */ | |
5177 | vcpu->arch.apf.halted = true; | |
5178 | r = 1; | |
5179 | goto out; | |
5180 | } | |
f8636849 AK |
5181 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
5182 | vcpu->arch.nmi_pending = true; | |
2f52d58c | 5183 | } |
b93463aa | 5184 | |
3e007509 AK |
5185 | r = kvm_mmu_reload(vcpu); |
5186 | if (unlikely(r)) | |
5187 | goto out; | |
5188 | ||
b463a6f7 AK |
5189 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
5190 | inject_pending_event(vcpu); | |
5191 | ||
5192 | /* enable NMI/IRQ window open exits if needed */ | |
5193 | if (vcpu->arch.nmi_pending) | |
5194 | kvm_x86_ops->enable_nmi_window(vcpu); | |
5195 | else if (kvm_cpu_has_interrupt(vcpu) || req_int_win) | |
5196 | kvm_x86_ops->enable_irq_window(vcpu); | |
5197 | ||
5198 | if (kvm_lapic_enabled(vcpu)) { | |
5199 | update_cr8_intercept(vcpu); | |
5200 | kvm_lapic_sync_to_vapic(vcpu); | |
5201 | } | |
5202 | } | |
5203 | ||
b6c7a5dc HB |
5204 | preempt_disable(); |
5205 | ||
5206 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
5207 | if (vcpu->fpu_active) |
5208 | kvm_load_guest_fpu(vcpu); | |
2acf923e | 5209 | kvm_load_guest_xcr0(vcpu); |
b6c7a5dc | 5210 | |
6b7e2d09 XG |
5211 | vcpu->mode = IN_GUEST_MODE; |
5212 | ||
5213 | /* We should set ->mode before check ->requests, | |
5214 | * see the comment in make_all_cpus_request. | |
5215 | */ | |
5216 | smp_mb(); | |
b6c7a5dc | 5217 | |
d94e1dc9 | 5218 | local_irq_disable(); |
32f88400 | 5219 | |
6b7e2d09 | 5220 | if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests |
d94e1dc9 | 5221 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 5222 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 5223 | smp_wmb(); |
6c142801 AK |
5224 | local_irq_enable(); |
5225 | preempt_enable(); | |
b463a6f7 | 5226 | kvm_x86_ops->cancel_injection(vcpu); |
6c142801 AK |
5227 | r = 1; |
5228 | goto out; | |
5229 | } | |
5230 | ||
f656ce01 | 5231 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
3200f405 | 5232 | |
b6c7a5dc HB |
5233 | kvm_guest_enter(); |
5234 | ||
42dbaa5a | 5235 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
5236 | set_debugreg(0, 7); |
5237 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
5238 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
5239 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
5240 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
5241 | } | |
b6c7a5dc | 5242 | |
229456fc | 5243 | trace_kvm_entry(vcpu->vcpu_id); |
851ba692 | 5244 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 5245 | |
24f1e32c FW |
5246 | /* |
5247 | * If the guest has used debug registers, at least dr7 | |
5248 | * will be disabled while returning to the host. | |
5249 | * If we don't have active breakpoints in the host, we don't | |
5250 | * care about the messed up debug address registers. But if | |
5251 | * we have some of them active, restore the old state. | |
5252 | */ | |
59d8eb53 | 5253 | if (hw_breakpoint_active()) |
24f1e32c | 5254 | hw_breakpoint_restore(); |
42dbaa5a | 5255 | |
1d5f066e ZA |
5256 | kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc); |
5257 | ||
6b7e2d09 | 5258 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 5259 | smp_wmb(); |
b6c7a5dc HB |
5260 | local_irq_enable(); |
5261 | ||
5262 | ++vcpu->stat.exits; | |
5263 | ||
5264 | /* | |
5265 | * We must have an instruction between local_irq_enable() and | |
5266 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
5267 | * the interrupt shadow. The stat.exits increment will do nicely. | |
5268 | * But we need to prevent reordering, hence this barrier(): | |
5269 | */ | |
5270 | barrier(); | |
5271 | ||
5272 | kvm_guest_exit(); | |
5273 | ||
5274 | preempt_enable(); | |
5275 | ||
f656ce01 | 5276 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 5277 | |
b6c7a5dc HB |
5278 | /* |
5279 | * Profile KVM exit RIPs: | |
5280 | */ | |
5281 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
5282 | unsigned long rip = kvm_rip_read(vcpu); |
5283 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
5284 | } |
5285 | ||
298101da | 5286 | |
b93463aa AK |
5287 | kvm_lapic_sync_from_vapic(vcpu); |
5288 | ||
851ba692 | 5289 | r = kvm_x86_ops->handle_exit(vcpu); |
d7690175 MT |
5290 | out: |
5291 | return r; | |
5292 | } | |
b6c7a5dc | 5293 | |
09cec754 | 5294 | |
851ba692 | 5295 | static int __vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
5296 | { |
5297 | int r; | |
f656ce01 | 5298 | struct kvm *kvm = vcpu->kvm; |
d7690175 MT |
5299 | |
5300 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) { | |
1b10bf31 JK |
5301 | pr_debug("vcpu %d received sipi with vector # %x\n", |
5302 | vcpu->vcpu_id, vcpu->arch.sipi_vector); | |
d7690175 | 5303 | kvm_lapic_reset(vcpu); |
5f179287 | 5304 | r = kvm_arch_vcpu_reset(vcpu); |
d7690175 MT |
5305 | if (r) |
5306 | return r; | |
5307 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
b6c7a5dc HB |
5308 | } |
5309 | ||
f656ce01 | 5310 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 MT |
5311 | vapic_enter(vcpu); |
5312 | ||
5313 | r = 1; | |
5314 | while (r > 0) { | |
af585b92 GN |
5315 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
5316 | !vcpu->arch.apf.halted) | |
851ba692 | 5317 | r = vcpu_enter_guest(vcpu); |
d7690175 | 5318 | else { |
f656ce01 | 5319 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
d7690175 | 5320 | kvm_vcpu_block(vcpu); |
f656ce01 | 5321 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
a8eeb04a | 5322 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
09cec754 GN |
5323 | { |
5324 | switch(vcpu->arch.mp_state) { | |
5325 | case KVM_MP_STATE_HALTED: | |
d7690175 | 5326 | vcpu->arch.mp_state = |
09cec754 GN |
5327 | KVM_MP_STATE_RUNNABLE; |
5328 | case KVM_MP_STATE_RUNNABLE: | |
af585b92 | 5329 | vcpu->arch.apf.halted = false; |
09cec754 GN |
5330 | break; |
5331 | case KVM_MP_STATE_SIPI_RECEIVED: | |
5332 | default: | |
5333 | r = -EINTR; | |
5334 | break; | |
5335 | } | |
5336 | } | |
d7690175 MT |
5337 | } |
5338 | ||
09cec754 GN |
5339 | if (r <= 0) |
5340 | break; | |
5341 | ||
5342 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
5343 | if (kvm_cpu_has_pending_timer(vcpu)) | |
5344 | kvm_inject_pending_timer_irqs(vcpu); | |
5345 | ||
851ba692 | 5346 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 5347 | r = -EINTR; |
851ba692 | 5348 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
5349 | ++vcpu->stat.request_irq_exits; |
5350 | } | |
af585b92 GN |
5351 | |
5352 | kvm_check_async_pf_completion(vcpu); | |
5353 | ||
09cec754 GN |
5354 | if (signal_pending(current)) { |
5355 | r = -EINTR; | |
851ba692 | 5356 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
5357 | ++vcpu->stat.signal_exits; |
5358 | } | |
5359 | if (need_resched()) { | |
f656ce01 | 5360 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
09cec754 | 5361 | kvm_resched(vcpu); |
f656ce01 | 5362 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 5363 | } |
b6c7a5dc HB |
5364 | } |
5365 | ||
f656ce01 | 5366 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc | 5367 | |
b93463aa AK |
5368 | vapic_exit(vcpu); |
5369 | ||
b6c7a5dc HB |
5370 | return r; |
5371 | } | |
5372 | ||
5373 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
5374 | { | |
5375 | int r; | |
5376 | sigset_t sigsaved; | |
5377 | ||
e5c30142 AK |
5378 | if (!tsk_used_math(current) && init_fpu(current)) |
5379 | return -ENOMEM; | |
5380 | ||
ac9f6dc0 AK |
5381 | if (vcpu->sigset_active) |
5382 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
5383 | ||
a4535290 | 5384 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 5385 | kvm_vcpu_block(vcpu); |
d7690175 | 5386 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
5387 | r = -EAGAIN; |
5388 | goto out; | |
b6c7a5dc HB |
5389 | } |
5390 | ||
b6c7a5dc | 5391 | /* re-sync apic's tpr */ |
eea1cff9 AP |
5392 | if (!irqchip_in_kernel(vcpu->kvm)) { |
5393 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { | |
5394 | r = -EINVAL; | |
5395 | goto out; | |
5396 | } | |
5397 | } | |
b6c7a5dc | 5398 | |
d2ddd1c4 | 5399 | if (vcpu->arch.pio.count || vcpu->mmio_needed) { |
92bf9748 GN |
5400 | if (vcpu->mmio_needed) { |
5401 | memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); | |
5402 | vcpu->mmio_read_completed = 1; | |
5403 | vcpu->mmio_needed = 0; | |
b6c7a5dc | 5404 | } |
f656ce01 | 5405 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
51d8b661 | 5406 | r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
f656ce01 | 5407 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
6d77dbfc | 5408 | if (r != EMULATE_DONE) { |
b6c7a5dc HB |
5409 | r = 0; |
5410 | goto out; | |
5411 | } | |
5412 | } | |
5fdbf976 MT |
5413 | if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) |
5414 | kvm_register_write(vcpu, VCPU_REGS_RAX, | |
5415 | kvm_run->hypercall.ret); | |
b6c7a5dc | 5416 | |
851ba692 | 5417 | r = __vcpu_run(vcpu); |
b6c7a5dc HB |
5418 | |
5419 | out: | |
f1d86e46 | 5420 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
5421 | if (vcpu->sigset_active) |
5422 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
5423 | ||
b6c7a5dc HB |
5424 | return r; |
5425 | } | |
5426 | ||
5427 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
5428 | { | |
5fdbf976 MT |
5429 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5430 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5431 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5432 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5433 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
5434 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
5435 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
5436 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 5437 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
5438 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
5439 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
5440 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
5441 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
5442 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
5443 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
5444 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
5445 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
5446 | #endif |
5447 | ||
5fdbf976 | 5448 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 5449 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 5450 | |
b6c7a5dc HB |
5451 | return 0; |
5452 | } | |
5453 | ||
5454 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
5455 | { | |
5fdbf976 MT |
5456 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
5457 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
5458 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
5459 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
5460 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
5461 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
5462 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
5463 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 5464 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
5465 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
5466 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
5467 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
5468 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
5469 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
5470 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
5471 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
5472 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
5473 | #endif |
5474 | ||
5fdbf976 | 5475 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 5476 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 5477 | |
b4f14abd JK |
5478 | vcpu->arch.exception.pending = false; |
5479 | ||
3842d135 AK |
5480 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5481 | ||
b6c7a5dc HB |
5482 | return 0; |
5483 | } | |
5484 | ||
b6c7a5dc HB |
5485 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
5486 | { | |
5487 | struct kvm_segment cs; | |
5488 | ||
3e6e0aab | 5489 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
5490 | *db = cs.db; |
5491 | *l = cs.l; | |
5492 | } | |
5493 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
5494 | ||
5495 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
5496 | struct kvm_sregs *sregs) | |
5497 | { | |
89a27f4d | 5498 | struct desc_ptr dt; |
b6c7a5dc | 5499 | |
3e6e0aab GT |
5500 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5501 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5502 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5503 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5504 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5505 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5506 | |
3e6e0aab GT |
5507 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5508 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
5509 | |
5510 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
5511 | sregs->idt.limit = dt.size; |
5512 | sregs->idt.base = dt.address; | |
b6c7a5dc | 5513 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
5514 | sregs->gdt.limit = dt.size; |
5515 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 5516 | |
4d4ec087 | 5517 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 5518 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 5519 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 5520 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 5521 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 5522 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
5523 | sregs->apic_base = kvm_get_apic_base(vcpu); |
5524 | ||
923c61bb | 5525 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 5526 | |
36752c9b | 5527 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
5528 | set_bit(vcpu->arch.interrupt.nr, |
5529 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 5530 | |
b6c7a5dc HB |
5531 | return 0; |
5532 | } | |
5533 | ||
62d9f0db MT |
5534 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
5535 | struct kvm_mp_state *mp_state) | |
5536 | { | |
62d9f0db | 5537 | mp_state->mp_state = vcpu->arch.mp_state; |
62d9f0db MT |
5538 | return 0; |
5539 | } | |
5540 | ||
5541 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
5542 | struct kvm_mp_state *mp_state) | |
5543 | { | |
62d9f0db | 5544 | vcpu->arch.mp_state = mp_state->mp_state; |
3842d135 | 5545 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
62d9f0db MT |
5546 | return 0; |
5547 | } | |
5548 | ||
e269fb21 JK |
5549 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason, |
5550 | bool has_error_code, u32 error_code) | |
b6c7a5dc | 5551 | { |
4d2179e1 | 5552 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; |
8ec4722d | 5553 | int ret; |
e01c2426 | 5554 | |
8ec4722d | 5555 | init_emulate_ctxt(vcpu); |
c697518a | 5556 | |
9aabc88f | 5557 | ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, |
e269fb21 JK |
5558 | tss_selector, reason, has_error_code, |
5559 | error_code); | |
c697518a | 5560 | |
c697518a | 5561 | if (ret) |
19d04437 | 5562 | return EMULATE_FAIL; |
37817f29 | 5563 | |
4d2179e1 | 5564 | memcpy(vcpu->arch.regs, c->regs, sizeof c->regs); |
95c55886 | 5565 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip); |
19d04437 | 5566 | kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); |
3842d135 | 5567 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 5568 | return EMULATE_DONE; |
37817f29 IE |
5569 | } |
5570 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
5571 | ||
b6c7a5dc HB |
5572 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
5573 | struct kvm_sregs *sregs) | |
5574 | { | |
5575 | int mmu_reset_needed = 0; | |
63f42e02 | 5576 | int pending_vec, max_bits, idx; |
89a27f4d | 5577 | struct desc_ptr dt; |
b6c7a5dc | 5578 | |
89a27f4d GN |
5579 | dt.size = sregs->idt.limit; |
5580 | dt.address = sregs->idt.base; | |
b6c7a5dc | 5581 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
5582 | dt.size = sregs->gdt.limit; |
5583 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
5584 | kvm_x86_ops->set_gdt(vcpu, &dt); |
5585 | ||
ad312c7c | 5586 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 5587 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 5588 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 5589 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 5590 | |
2d3ad1f4 | 5591 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 5592 | |
f6801dff | 5593 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 5594 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc HB |
5595 | kvm_set_apic_base(vcpu, sregs->apic_base); |
5596 | ||
4d4ec087 | 5597 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 5598 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 5599 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 5600 | |
fc78f519 | 5601 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 5602 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
3ea3aa8c SY |
5603 | if (sregs->cr4 & X86_CR4_OSXSAVE) |
5604 | update_cpuid(vcpu); | |
63f42e02 XG |
5605 | |
5606 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
7c93be44 | 5607 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
9f8fe504 | 5608 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
5609 | mmu_reset_needed = 1; |
5610 | } | |
63f42e02 | 5611 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
5612 | |
5613 | if (mmu_reset_needed) | |
5614 | kvm_mmu_reset_context(vcpu); | |
5615 | ||
923c61bb GN |
5616 | max_bits = (sizeof sregs->interrupt_bitmap) << 3; |
5617 | pending_vec = find_first_bit( | |
5618 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
5619 | if (pending_vec < max_bits) { | |
66fd3f7f | 5620 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 5621 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
5622 | } |
5623 | ||
3e6e0aab GT |
5624 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5625 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5626 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5627 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5628 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5629 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5630 | |
3e6e0aab GT |
5631 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5632 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 5633 | |
5f0269f5 ME |
5634 | update_cr8_intercept(vcpu); |
5635 | ||
9c3e4aab | 5636 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 5637 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 5638 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 5639 | !is_protmode(vcpu)) |
9c3e4aab MT |
5640 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
5641 | ||
3842d135 AK |
5642 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5643 | ||
b6c7a5dc HB |
5644 | return 0; |
5645 | } | |
5646 | ||
d0bfb940 JK |
5647 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
5648 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 5649 | { |
355be0b9 | 5650 | unsigned long rflags; |
ae675ef0 | 5651 | int i, r; |
b6c7a5dc | 5652 | |
4f926bf2 JK |
5653 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
5654 | r = -EBUSY; | |
5655 | if (vcpu->arch.exception.pending) | |
2122ff5e | 5656 | goto out; |
4f926bf2 JK |
5657 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
5658 | kvm_queue_exception(vcpu, DB_VECTOR); | |
5659 | else | |
5660 | kvm_queue_exception(vcpu, BP_VECTOR); | |
5661 | } | |
5662 | ||
91586a3b JK |
5663 | /* |
5664 | * Read rflags as long as potentially injected trace flags are still | |
5665 | * filtered out. | |
5666 | */ | |
5667 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
5668 | |
5669 | vcpu->guest_debug = dbg->control; | |
5670 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
5671 | vcpu->guest_debug = 0; | |
5672 | ||
5673 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
5674 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
5675 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
5676 | vcpu->arch.switch_db_regs = | |
5677 | (dbg->arch.debugreg[7] & DR7_BP_EN_MASK); | |
5678 | } else { | |
5679 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
5680 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
5681 | vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK); | |
5682 | } | |
5683 | ||
f92653ee JK |
5684 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
5685 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
5686 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 5687 | |
91586a3b JK |
5688 | /* |
5689 | * Trigger an rflags update that will inject or remove the trace | |
5690 | * flags. | |
5691 | */ | |
5692 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 5693 | |
355be0b9 | 5694 | kvm_x86_ops->set_guest_debug(vcpu, dbg); |
b6c7a5dc | 5695 | |
4f926bf2 | 5696 | r = 0; |
d0bfb940 | 5697 | |
2122ff5e | 5698 | out: |
b6c7a5dc HB |
5699 | |
5700 | return r; | |
5701 | } | |
5702 | ||
8b006791 ZX |
5703 | /* |
5704 | * Translate a guest virtual address to a guest physical address. | |
5705 | */ | |
5706 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
5707 | struct kvm_translation *tr) | |
5708 | { | |
5709 | unsigned long vaddr = tr->linear_address; | |
5710 | gpa_t gpa; | |
f656ce01 | 5711 | int idx; |
8b006791 | 5712 | |
f656ce01 | 5713 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 5714 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 5715 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
5716 | tr->physical_address = gpa; |
5717 | tr->valid = gpa != UNMAPPED_GVA; | |
5718 | tr->writeable = 1; | |
5719 | tr->usermode = 0; | |
8b006791 ZX |
5720 | |
5721 | return 0; | |
5722 | } | |
5723 | ||
d0752060 HB |
5724 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
5725 | { | |
98918833 SY |
5726 | struct i387_fxsave_struct *fxsave = |
5727 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 5728 | |
d0752060 HB |
5729 | memcpy(fpu->fpr, fxsave->st_space, 128); |
5730 | fpu->fcw = fxsave->cwd; | |
5731 | fpu->fsw = fxsave->swd; | |
5732 | fpu->ftwx = fxsave->twd; | |
5733 | fpu->last_opcode = fxsave->fop; | |
5734 | fpu->last_ip = fxsave->rip; | |
5735 | fpu->last_dp = fxsave->rdp; | |
5736 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
5737 | ||
d0752060 HB |
5738 | return 0; |
5739 | } | |
5740 | ||
5741 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
5742 | { | |
98918833 SY |
5743 | struct i387_fxsave_struct *fxsave = |
5744 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 5745 | |
d0752060 HB |
5746 | memcpy(fxsave->st_space, fpu->fpr, 128); |
5747 | fxsave->cwd = fpu->fcw; | |
5748 | fxsave->swd = fpu->fsw; | |
5749 | fxsave->twd = fpu->ftwx; | |
5750 | fxsave->fop = fpu->last_opcode; | |
5751 | fxsave->rip = fpu->last_ip; | |
5752 | fxsave->rdp = fpu->last_dp; | |
5753 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
5754 | ||
d0752060 HB |
5755 | return 0; |
5756 | } | |
5757 | ||
10ab25cd | 5758 | int fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 5759 | { |
10ab25cd JK |
5760 | int err; |
5761 | ||
5762 | err = fpu_alloc(&vcpu->arch.guest_fpu); | |
5763 | if (err) | |
5764 | return err; | |
5765 | ||
98918833 | 5766 | fpu_finit(&vcpu->arch.guest_fpu); |
d0752060 | 5767 | |
2acf923e DC |
5768 | /* |
5769 | * Ensure guest xcr0 is valid for loading | |
5770 | */ | |
5771 | vcpu->arch.xcr0 = XSTATE_FP; | |
5772 | ||
ad312c7c | 5773 | vcpu->arch.cr0 |= X86_CR0_ET; |
10ab25cd JK |
5774 | |
5775 | return 0; | |
d0752060 HB |
5776 | } |
5777 | EXPORT_SYMBOL_GPL(fx_init); | |
5778 | ||
98918833 SY |
5779 | static void fx_free(struct kvm_vcpu *vcpu) |
5780 | { | |
5781 | fpu_free(&vcpu->arch.guest_fpu); | |
5782 | } | |
5783 | ||
d0752060 HB |
5784 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) |
5785 | { | |
2608d7a1 | 5786 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
5787 | return; |
5788 | ||
2acf923e DC |
5789 | /* |
5790 | * Restore all possible states in the guest, | |
5791 | * and assume host would use all available bits. | |
5792 | * Guest xcr0 would be loaded later. | |
5793 | */ | |
5794 | kvm_put_guest_xcr0(vcpu); | |
d0752060 | 5795 | vcpu->guest_fpu_loaded = 1; |
7cf30855 | 5796 | unlazy_fpu(current); |
98918833 | 5797 | fpu_restore_checking(&vcpu->arch.guest_fpu); |
0c04851c | 5798 | trace_kvm_fpu(1); |
d0752060 | 5799 | } |
d0752060 HB |
5800 | |
5801 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
5802 | { | |
2acf923e DC |
5803 | kvm_put_guest_xcr0(vcpu); |
5804 | ||
d0752060 HB |
5805 | if (!vcpu->guest_fpu_loaded) |
5806 | return; | |
5807 | ||
5808 | vcpu->guest_fpu_loaded = 0; | |
98918833 | 5809 | fpu_save_init(&vcpu->arch.guest_fpu); |
f096ed85 | 5810 | ++vcpu->stat.fpu_reload; |
a8eeb04a | 5811 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); |
0c04851c | 5812 | trace_kvm_fpu(0); |
d0752060 | 5813 | } |
e9b11c17 ZX |
5814 | |
5815 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
5816 | { | |
12f9a48f | 5817 | kvmclock_reset(vcpu); |
7f1ea208 | 5818 | |
f5f48ee1 | 5819 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
98918833 | 5820 | fx_free(vcpu); |
e9b11c17 ZX |
5821 | kvm_x86_ops->vcpu_free(vcpu); |
5822 | } | |
5823 | ||
5824 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
5825 | unsigned int id) | |
5826 | { | |
6755bae8 ZA |
5827 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
5828 | printk_once(KERN_WARNING | |
5829 | "kvm: SMP vm created on host with unstable TSC; " | |
5830 | "guest TSC will not be reliable\n"); | |
26e5215f AK |
5831 | return kvm_x86_ops->vcpu_create(kvm, id); |
5832 | } | |
e9b11c17 | 5833 | |
26e5215f AK |
5834 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
5835 | { | |
5836 | int r; | |
e9b11c17 | 5837 | |
0bed3b56 | 5838 | vcpu->arch.mtrr_state.have_fixed = 1; |
e9b11c17 ZX |
5839 | vcpu_load(vcpu); |
5840 | r = kvm_arch_vcpu_reset(vcpu); | |
5841 | if (r == 0) | |
5842 | r = kvm_mmu_setup(vcpu); | |
5843 | vcpu_put(vcpu); | |
5844 | if (r < 0) | |
5845 | goto free_vcpu; | |
5846 | ||
26e5215f | 5847 | return 0; |
e9b11c17 ZX |
5848 | free_vcpu: |
5849 | kvm_x86_ops->vcpu_free(vcpu); | |
26e5215f | 5850 | return r; |
e9b11c17 ZX |
5851 | } |
5852 | ||
d40ccc62 | 5853 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 5854 | { |
344d9588 GN |
5855 | vcpu->arch.apf.msr_val = 0; |
5856 | ||
e9b11c17 ZX |
5857 | vcpu_load(vcpu); |
5858 | kvm_mmu_unload(vcpu); | |
5859 | vcpu_put(vcpu); | |
5860 | ||
98918833 | 5861 | fx_free(vcpu); |
e9b11c17 ZX |
5862 | kvm_x86_ops->vcpu_free(vcpu); |
5863 | } | |
5864 | ||
5865 | int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu) | |
5866 | { | |
448fa4a9 JK |
5867 | vcpu->arch.nmi_pending = false; |
5868 | vcpu->arch.nmi_injected = false; | |
5869 | ||
42dbaa5a JK |
5870 | vcpu->arch.switch_db_regs = 0; |
5871 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); | |
5872 | vcpu->arch.dr6 = DR6_FIXED_1; | |
5873 | vcpu->arch.dr7 = DR7_FIXED_1; | |
5874 | ||
3842d135 | 5875 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 5876 | vcpu->arch.apf.msr_val = 0; |
3842d135 | 5877 | |
12f9a48f GC |
5878 | kvmclock_reset(vcpu); |
5879 | ||
af585b92 GN |
5880 | kvm_clear_async_pf_completion_queue(vcpu); |
5881 | kvm_async_pf_hash_reset(vcpu); | |
5882 | vcpu->arch.apf.halted = false; | |
3842d135 | 5883 | |
e9b11c17 ZX |
5884 | return kvm_x86_ops->vcpu_reset(vcpu); |
5885 | } | |
5886 | ||
10474ae8 | 5887 | int kvm_arch_hardware_enable(void *garbage) |
e9b11c17 | 5888 | { |
ca84d1a2 ZA |
5889 | struct kvm *kvm; |
5890 | struct kvm_vcpu *vcpu; | |
5891 | int i; | |
18863bdd AK |
5892 | |
5893 | kvm_shared_msr_cpu_online(); | |
ca84d1a2 ZA |
5894 | list_for_each_entry(kvm, &vm_list, vm_list) |
5895 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5896 | if (vcpu->cpu == smp_processor_id()) | |
c285545f | 5897 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
10474ae8 | 5898 | return kvm_x86_ops->hardware_enable(garbage); |
e9b11c17 ZX |
5899 | } |
5900 | ||
5901 | void kvm_arch_hardware_disable(void *garbage) | |
5902 | { | |
5903 | kvm_x86_ops->hardware_disable(garbage); | |
3548bab5 | 5904 | drop_user_return_notifiers(garbage); |
e9b11c17 ZX |
5905 | } |
5906 | ||
5907 | int kvm_arch_hardware_setup(void) | |
5908 | { | |
5909 | return kvm_x86_ops->hardware_setup(); | |
5910 | } | |
5911 | ||
5912 | void kvm_arch_hardware_unsetup(void) | |
5913 | { | |
5914 | kvm_x86_ops->hardware_unsetup(); | |
5915 | } | |
5916 | ||
5917 | void kvm_arch_check_processor_compat(void *rtn) | |
5918 | { | |
5919 | kvm_x86_ops->check_processor_compatibility(rtn); | |
5920 | } | |
5921 | ||
5922 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) | |
5923 | { | |
5924 | struct page *page; | |
5925 | struct kvm *kvm; | |
5926 | int r; | |
5927 | ||
5928 | BUG_ON(vcpu->kvm == NULL); | |
5929 | kvm = vcpu->kvm; | |
5930 | ||
9aabc88f | 5931 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
14dfe855 | 5932 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; |
ad312c7c | 5933 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
c30a358d | 5934 | vcpu->arch.mmu.translate_gpa = translate_gpa; |
02f59dc9 | 5935 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; |
c5af89b6 | 5936 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) |
a4535290 | 5937 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 5938 | else |
a4535290 | 5939 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
5940 | |
5941 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
5942 | if (!page) { | |
5943 | r = -ENOMEM; | |
5944 | goto fail; | |
5945 | } | |
ad312c7c | 5946 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 5947 | |
c285545f ZA |
5948 | if (!kvm->arch.virtual_tsc_khz) |
5949 | kvm_arch_set_tsc_khz(kvm, max_tsc_khz); | |
5950 | ||
e9b11c17 ZX |
5951 | r = kvm_mmu_create(vcpu); |
5952 | if (r < 0) | |
5953 | goto fail_free_pio_data; | |
5954 | ||
5955 | if (irqchip_in_kernel(kvm)) { | |
5956 | r = kvm_create_lapic(vcpu); | |
5957 | if (r < 0) | |
5958 | goto fail_mmu_destroy; | |
5959 | } | |
5960 | ||
890ca9ae HY |
5961 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
5962 | GFP_KERNEL); | |
5963 | if (!vcpu->arch.mce_banks) { | |
5964 | r = -ENOMEM; | |
443c39bc | 5965 | goto fail_free_lapic; |
890ca9ae HY |
5966 | } |
5967 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
5968 | ||
f5f48ee1 SY |
5969 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) |
5970 | goto fail_free_mce_banks; | |
5971 | ||
af585b92 GN |
5972 | kvm_async_pf_hash_reset(vcpu); |
5973 | ||
e9b11c17 | 5974 | return 0; |
f5f48ee1 SY |
5975 | fail_free_mce_banks: |
5976 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
5977 | fail_free_lapic: |
5978 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
5979 | fail_mmu_destroy: |
5980 | kvm_mmu_destroy(vcpu); | |
5981 | fail_free_pio_data: | |
ad312c7c | 5982 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
5983 | fail: |
5984 | return r; | |
5985 | } | |
5986 | ||
5987 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
5988 | { | |
f656ce01 MT |
5989 | int idx; |
5990 | ||
36cb93fd | 5991 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 5992 | kvm_free_lapic(vcpu); |
f656ce01 | 5993 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 5994 | kvm_mmu_destroy(vcpu); |
f656ce01 | 5995 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 5996 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 | 5997 | } |
d19a9cd2 | 5998 | |
d89f5eff | 5999 | int kvm_arch_init_vm(struct kvm *kvm) |
d19a9cd2 | 6000 | { |
f05e70ac | 6001 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 6002 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
d19a9cd2 | 6003 | |
5550af4d SY |
6004 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
6005 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
6006 | ||
99e3e30a | 6007 | spin_lock_init(&kvm->arch.tsc_write_lock); |
53f658b3 | 6008 | |
d89f5eff | 6009 | return 0; |
d19a9cd2 ZX |
6010 | } |
6011 | ||
6012 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
6013 | { | |
6014 | vcpu_load(vcpu); | |
6015 | kvm_mmu_unload(vcpu); | |
6016 | vcpu_put(vcpu); | |
6017 | } | |
6018 | ||
6019 | static void kvm_free_vcpus(struct kvm *kvm) | |
6020 | { | |
6021 | unsigned int i; | |
988a2cae | 6022 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
6023 | |
6024 | /* | |
6025 | * Unpin any mmu pages first. | |
6026 | */ | |
af585b92 GN |
6027 | kvm_for_each_vcpu(i, vcpu, kvm) { |
6028 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 6029 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 6030 | } |
988a2cae GN |
6031 | kvm_for_each_vcpu(i, vcpu, kvm) |
6032 | kvm_arch_vcpu_free(vcpu); | |
6033 | ||
6034 | mutex_lock(&kvm->lock); | |
6035 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
6036 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 6037 | |
988a2cae GN |
6038 | atomic_set(&kvm->online_vcpus, 0); |
6039 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
6040 | } |
6041 | ||
ad8ba2cd SY |
6042 | void kvm_arch_sync_events(struct kvm *kvm) |
6043 | { | |
ba4cef31 | 6044 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 6045 | kvm_free_pit(kvm); |
ad8ba2cd SY |
6046 | } |
6047 | ||
d19a9cd2 ZX |
6048 | void kvm_arch_destroy_vm(struct kvm *kvm) |
6049 | { | |
6eb55818 | 6050 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
6051 | kfree(kvm->arch.vpic); |
6052 | kfree(kvm->arch.vioapic); | |
d19a9cd2 | 6053 | kvm_free_vcpus(kvm); |
3d45830c AK |
6054 | if (kvm->arch.apic_access_page) |
6055 | put_page(kvm->arch.apic_access_page); | |
b7ebfb05 SY |
6056 | if (kvm->arch.ept_identity_pagetable) |
6057 | put_page(kvm->arch.ept_identity_pagetable); | |
d19a9cd2 | 6058 | } |
0de10343 | 6059 | |
f7784b8e MT |
6060 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
6061 | struct kvm_memory_slot *memslot, | |
0de10343 | 6062 | struct kvm_memory_slot old, |
f7784b8e | 6063 | struct kvm_userspace_memory_region *mem, |
0de10343 ZX |
6064 | int user_alloc) |
6065 | { | |
f7784b8e | 6066 | int npages = memslot->npages; |
7ac77099 AK |
6067 | int map_flags = MAP_PRIVATE | MAP_ANONYMOUS; |
6068 | ||
6069 | /* Prevent internal slot pages from being moved by fork()/COW. */ | |
6070 | if (memslot->id >= KVM_MEMORY_SLOTS) | |
6071 | map_flags = MAP_SHARED | MAP_ANONYMOUS; | |
0de10343 ZX |
6072 | |
6073 | /*To keep backward compatibility with older userspace, | |
6074 | *x86 needs to hanlde !user_alloc case. | |
6075 | */ | |
6076 | if (!user_alloc) { | |
6077 | if (npages && !old.rmap) { | |
604b38ac AA |
6078 | unsigned long userspace_addr; |
6079 | ||
72dc67a6 | 6080 | down_write(¤t->mm->mmap_sem); |
604b38ac AA |
6081 | userspace_addr = do_mmap(NULL, 0, |
6082 | npages * PAGE_SIZE, | |
6083 | PROT_READ | PROT_WRITE, | |
7ac77099 | 6084 | map_flags, |
604b38ac | 6085 | 0); |
72dc67a6 | 6086 | up_write(¤t->mm->mmap_sem); |
0de10343 | 6087 | |
604b38ac AA |
6088 | if (IS_ERR((void *)userspace_addr)) |
6089 | return PTR_ERR((void *)userspace_addr); | |
6090 | ||
604b38ac | 6091 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
6092 | } |
6093 | } | |
6094 | ||
f7784b8e MT |
6095 | |
6096 | return 0; | |
6097 | } | |
6098 | ||
6099 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
6100 | struct kvm_userspace_memory_region *mem, | |
6101 | struct kvm_memory_slot old, | |
6102 | int user_alloc) | |
6103 | { | |
6104 | ||
6105 | int npages = mem->memory_size >> PAGE_SHIFT; | |
6106 | ||
6107 | if (!user_alloc && !old.user_alloc && old.rmap && !npages) { | |
6108 | int ret; | |
6109 | ||
6110 | down_write(¤t->mm->mmap_sem); | |
6111 | ret = do_munmap(current->mm, old.userspace_addr, | |
6112 | old.npages * PAGE_SIZE); | |
6113 | up_write(¤t->mm->mmap_sem); | |
6114 | if (ret < 0) | |
6115 | printk(KERN_WARNING | |
6116 | "kvm_vm_ioctl_set_memory_region: " | |
6117 | "failed to munmap memory\n"); | |
6118 | } | |
6119 | ||
7c8a83b7 | 6120 | spin_lock(&kvm->mmu_lock); |
f05e70ac | 6121 | if (!kvm->arch.n_requested_mmu_pages) { |
0de10343 ZX |
6122 | unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); |
6123 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); | |
6124 | } | |
6125 | ||
6126 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); | |
7c8a83b7 | 6127 | spin_unlock(&kvm->mmu_lock); |
0de10343 | 6128 | } |
1d737c8a | 6129 | |
34d4cb8f MT |
6130 | void kvm_arch_flush_shadow(struct kvm *kvm) |
6131 | { | |
6132 | kvm_mmu_zap_all(kvm); | |
8986ecc0 | 6133 | kvm_reload_remote_mmus(kvm); |
34d4cb8f MT |
6134 | } |
6135 | ||
1d737c8a ZX |
6136 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
6137 | { | |
af585b92 GN |
6138 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
6139 | !vcpu->arch.apf.halted) | |
6140 | || !list_empty_careful(&vcpu->async_pf.done) | |
a1b37100 GN |
6141 | || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED |
6142 | || vcpu->arch.nmi_pending || | |
6143 | (kvm_arch_interrupt_allowed(vcpu) && | |
6144 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 6145 | } |
5736199a | 6146 | |
5736199a ZX |
6147 | void kvm_vcpu_kick(struct kvm_vcpu *vcpu) |
6148 | { | |
32f88400 MT |
6149 | int me; |
6150 | int cpu = vcpu->cpu; | |
5736199a ZX |
6151 | |
6152 | if (waitqueue_active(&vcpu->wq)) { | |
6153 | wake_up_interruptible(&vcpu->wq); | |
6154 | ++vcpu->stat.halt_wakeup; | |
6155 | } | |
32f88400 MT |
6156 | |
6157 | me = get_cpu(); | |
6158 | if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu)) | |
6b7e2d09 | 6159 | if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE) |
32f88400 | 6160 | smp_send_reschedule(cpu); |
e9571ed5 | 6161 | put_cpu(); |
5736199a | 6162 | } |
78646121 GN |
6163 | |
6164 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
6165 | { | |
6166 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
6167 | } | |
229456fc | 6168 | |
f92653ee JK |
6169 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
6170 | { | |
6171 | unsigned long current_rip = kvm_rip_read(vcpu) + | |
6172 | get_segment_base(vcpu, VCPU_SREG_CS); | |
6173 | ||
6174 | return current_rip == linear_rip; | |
6175 | } | |
6176 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
6177 | ||
94fe45da JK |
6178 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
6179 | { | |
6180 | unsigned long rflags; | |
6181 | ||
6182 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
6183 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 6184 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
6185 | return rflags; |
6186 | } | |
6187 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
6188 | ||
6189 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
6190 | { | |
6191 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 6192 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 6193 | rflags |= X86_EFLAGS_TF; |
94fe45da | 6194 | kvm_x86_ops->set_rflags(vcpu, rflags); |
3842d135 | 6195 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
6196 | } |
6197 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
6198 | ||
56028d08 GN |
6199 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
6200 | { | |
6201 | int r; | |
6202 | ||
fb67e14f | 6203 | if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || |
c4806acd | 6204 | is_error_page(work->page)) |
56028d08 GN |
6205 | return; |
6206 | ||
6207 | r = kvm_mmu_reload(vcpu); | |
6208 | if (unlikely(r)) | |
6209 | return; | |
6210 | ||
fb67e14f XG |
6211 | if (!vcpu->arch.mmu.direct_map && |
6212 | work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) | |
6213 | return; | |
6214 | ||
56028d08 GN |
6215 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); |
6216 | } | |
6217 | ||
af585b92 GN |
6218 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
6219 | { | |
6220 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
6221 | } | |
6222 | ||
6223 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
6224 | { | |
6225 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
6226 | } | |
6227 | ||
6228 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6229 | { | |
6230 | u32 key = kvm_async_pf_hash_fn(gfn); | |
6231 | ||
6232 | while (vcpu->arch.apf.gfns[key] != ~0) | |
6233 | key = kvm_async_pf_next_probe(key); | |
6234 | ||
6235 | vcpu->arch.apf.gfns[key] = gfn; | |
6236 | } | |
6237 | ||
6238 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6239 | { | |
6240 | int i; | |
6241 | u32 key = kvm_async_pf_hash_fn(gfn); | |
6242 | ||
6243 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
6244 | (vcpu->arch.apf.gfns[key] != gfn && |
6245 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
6246 | key = kvm_async_pf_next_probe(key); |
6247 | ||
6248 | return key; | |
6249 | } | |
6250 | ||
6251 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6252 | { | |
6253 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
6254 | } | |
6255 | ||
6256 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6257 | { | |
6258 | u32 i, j, k; | |
6259 | ||
6260 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
6261 | while (true) { | |
6262 | vcpu->arch.apf.gfns[i] = ~0; | |
6263 | do { | |
6264 | j = kvm_async_pf_next_probe(j); | |
6265 | if (vcpu->arch.apf.gfns[j] == ~0) | |
6266 | return; | |
6267 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
6268 | /* | |
6269 | * k lies cyclically in ]i,j] | |
6270 | * | i.k.j | | |
6271 | * |....j i.k.| or |.k..j i...| | |
6272 | */ | |
6273 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
6274 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
6275 | i = j; | |
6276 | } | |
6277 | } | |
6278 | ||
7c90705b GN |
6279 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
6280 | { | |
6281 | ||
6282 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
6283 | sizeof(val)); | |
6284 | } | |
6285 | ||
af585b92 GN |
6286 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
6287 | struct kvm_async_pf *work) | |
6288 | { | |
6389ee94 AK |
6289 | struct x86_exception fault; |
6290 | ||
7c90705b | 6291 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 6292 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b GN |
6293 | |
6294 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
fc5f06fa GN |
6295 | (vcpu->arch.apf.send_user_only && |
6296 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7c90705b GN |
6297 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
6298 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
6299 | fault.vector = PF_VECTOR; |
6300 | fault.error_code_valid = true; | |
6301 | fault.error_code = 0; | |
6302 | fault.nested_page_fault = false; | |
6303 | fault.address = work->arch.token; | |
6304 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 6305 | } |
af585b92 GN |
6306 | } |
6307 | ||
6308 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
6309 | struct kvm_async_pf *work) | |
6310 | { | |
6389ee94 AK |
6311 | struct x86_exception fault; |
6312 | ||
7c90705b GN |
6313 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
6314 | if (is_error_page(work->page)) | |
6315 | work->arch.token = ~0; /* broadcast wakeup */ | |
6316 | else | |
6317 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
6318 | ||
6319 | if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && | |
6320 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
6389ee94 AK |
6321 | fault.vector = PF_VECTOR; |
6322 | fault.error_code_valid = true; | |
6323 | fault.error_code = 0; | |
6324 | fault.nested_page_fault = false; | |
6325 | fault.address = work->arch.token; | |
6326 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 6327 | } |
e6d53e3b | 6328 | vcpu->arch.apf.halted = false; |
7c90705b GN |
6329 | } |
6330 | ||
6331 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
6332 | { | |
6333 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
6334 | return true; | |
6335 | else | |
6336 | return !kvm_event_needs_reinjection(vcpu) && | |
6337 | kvm_x86_ops->interrupt_allowed(vcpu); | |
af585b92 GN |
6338 | } |
6339 | ||
229456fc MT |
6340 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
6341 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
6342 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
6343 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
6344 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 6345 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 6346 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 6347 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 6348 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 6349 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 6350 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 6351 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |