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KVM/x86: Move X86_CR4_OSXSAVE check into kvm_valid_sregs()
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 141EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 142
52004014
FW		 143static bool __read_mostly vector_hashing = true;
144module_param(vector_hashing, bool, S_IRUGO);
145
c4ae60e4
LA		 146bool __read_mostly enable_vmware_backdoor = false;
147module_param(enable_vmware_backdoor, bool, S_IRUGO);
148EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149
6c86eedc
WL		 150static bool __read_mostly force_emulation_prefix = false;
151module_param(force_emulation_prefix, bool, S_IRUGO);
152
18863bdd
AK		 153#define KVM_NR_SHARED_MSRS 16
154
155struct kvm_shared_msrs_global {
156 int nr;
2bf78fa7 157 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 158};
159
160struct kvm_shared_msrs {
161 struct user_return_notifier urn;
162 bool registered;
2bf78fa7
SY		 163 struct kvm_shared_msr_values {
164 u64 host;
165 u64 curr;
166 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 167};
168
169static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 170static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 171
417bc304 172struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 183 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 188 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 195 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 196 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 197 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 198 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
199 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
200 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
201 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
202 { "mmu_flooded", VM_STAT(mmu_flooded) },
203 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 204 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 205 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 206 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 207 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 208 { "max_mmu_page_hash_collisions",
209 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 210 { NULL }
211};
212
2acf923e
DC		 213u64 __read_mostly host_xcr0;
214
b6785def 215static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 216
af585b92
GN		 217static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
218{
219 int i;
220 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
221 vcpu->arch.apf.gfns[i] = ~0;
222}
223
18863bdd
AK		 224static void kvm_on_user_return(struct user_return_notifier *urn)
225{
226 unsigned slot;
18863bdd
AK		 227 struct kvm_shared_msrs *locals
228 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 229 struct kvm_shared_msr_values *values;
1650b4eb
IA		 230 unsigned long flags;
231
232 /*
233 * Disabling irqs at this point since the following code could be
234 * interrupted and executed through kvm_arch_hardware_disable()
235 */
236 local_irq_save(flags);
237 if (locals->registered) {
238 locals->registered = false;
239 user_return_notifier_unregister(urn);
240 }
241 local_irq_restore(flags);
18863bdd 242 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 243 values = &locals->values[slot];
244 if (values->host != values->curr) {
245 wrmsrl(shared_msrs_global.msrs[slot], values->host);
246 values->curr = values->host;
18863bdd
AK		 247 }
248 }
18863bdd
AK		 249}
250
2bf78fa7 251static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 252{
18863bdd 253 u64 value;
013f6a5d
MT		 254 unsigned int cpu = smp_processor_id();
255 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 256
2bf78fa7
SY		 257 /* only read, and nobody should modify it at this time,
258 * so don't need lock */
259 if (slot >= shared_msrs_global.nr) {
260 printk(KERN_ERR "kvm: invalid MSR slot!");
261 return;
262 }
263 rdmsrl_safe(msr, &value);
264 smsr->values[slot].host = value;
265 smsr->values[slot].curr = value;
266}
267
268void kvm_define_shared_msr(unsigned slot, u32 msr)
269{
0123be42 270 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 271 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 272 if (slot >= shared_msrs_global.nr)
273 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 274}
275EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
276
277static void kvm_shared_msr_cpu_online(void)
278{
279 unsigned i;
18863bdd
AK		 280
281 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 282 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 283}
284
8b3c3104 285int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 286{
013f6a5d
MT		 287 unsigned int cpu = smp_processor_id();
288 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 289 int err;
18863bdd 290
2bf78fa7 291 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 292 return 0;
2bf78fa7 293 smsr->values[slot].curr = value;
8b3c3104
AH		 294 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
295 if (err)
296 return 1;
297
18863bdd
AK		 298 if (!smsr->registered) {
299 smsr->urn.on_user_return = kvm_on_user_return;
300 user_return_notifier_register(&smsr->urn);
301 smsr->registered = true;
302 }
8b3c3104 303 return 0;
18863bdd
AK		 304}
305EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
306
13a34e06 307static void drop_user_return_notifiers(void)
3548bab5 308{
013f6a5d
MT		 309 unsigned int cpu = smp_processor_id();
310 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 311
312 if (smsr->registered)
313 kvm_on_user_return(&smsr->urn);
314}
315
6866b83e
CO		 316u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
317{
8a5a87d9 318 return vcpu->arch.apic_base;
6866b83e
CO		 319}
320EXPORT_SYMBOL_GPL(kvm_get_apic_base);
321
58871649
JM		 322enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
323{
324 return kvm_apic_mode(kvm_get_apic_base(vcpu));
325}
326EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
327
58cb628d
JK		 328int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
329{
58871649
JM		 330 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
331 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 332 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
333 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 334
58871649 335 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 336 return 1;
58871649
JM		 337 if (!msr_info->host_initiated) {
338 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
339 return 1;
340 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
341 return 1;
342 }
58cb628d
JK		 343
344 kvm_lapic_set_base(vcpu, msr_info->data);
345 return 0;
6866b83e
CO		 346}
347EXPORT_SYMBOL_GPL(kvm_set_apic_base);
348
2605fc21 349asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 350{
351 /* Fault while not rebooting. We want the trace. */
352 BUG();
353}
354EXPORT_SYMBOL_GPL(kvm_spurious_fault);
355
3fd28fce
ED		 356#define EXCPT_BENIGN 0
357#define EXCPT_CONTRIBUTORY 1
358#define EXCPT_PF 2
359
360static int exception_class(int vector)
361{
362 switch (vector) {
363 case PF_VECTOR:
364 return EXCPT_PF;
365 case DE_VECTOR:
366 case TS_VECTOR:
367 case NP_VECTOR:
368 case SS_VECTOR:
369 case GP_VECTOR:
370 return EXCPT_CONTRIBUTORY;
371 default:
372 break;
373 }
374 return EXCPT_BENIGN;
375}
376
d6e8c854
NA		 377#define EXCPT_FAULT 0
378#define EXCPT_TRAP 1
379#define EXCPT_ABORT 2
380#define EXCPT_INTERRUPT 3
381
382static int exception_type(int vector)
383{
384 unsigned int mask;
385
386 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
387 return EXCPT_INTERRUPT;
388
389 mask = 1 << vector;
390
391 /* #DB is trap, as instruction watchpoints are handled elsewhere */
392 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
393 return EXCPT_TRAP;
394
395 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
396 return EXCPT_ABORT;
397
398 /* Reserved exceptions will result in fault */
399 return EXCPT_FAULT;
400}
401
3fd28fce 402static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 403 unsigned nr, bool has_error, u32 error_code,
404 bool reinject)
3fd28fce
ED		 405{
406 u32 prev_nr;
407 int class1, class2;
408
3842d135
AK		 409 kvm_make_request(KVM_REQ_EVENT, vcpu);
410
664f8e26 411 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 412 queue:
3ffb2468
NA		 413 if (has_error && !is_protmode(vcpu))
414 has_error = false;
664f8e26
WL		 415 if (reinject) {
416 /*
417 * On vmentry, vcpu->arch.exception.pending is only
418 * true if an event injection was blocked by
419 * nested_run_pending. In that case, however,
420 * vcpu_enter_guest requests an immediate exit,
421 * and the guest shouldn't proceed far enough to
422 * need reinjection.
423 */
424 WARN_ON_ONCE(vcpu->arch.exception.pending);
425 vcpu->arch.exception.injected = true;
426 } else {
427 vcpu->arch.exception.pending = true;
428 vcpu->arch.exception.injected = false;
429 }
3fd28fce
ED		 430 vcpu->arch.exception.has_error_code = has_error;
431 vcpu->arch.exception.nr = nr;
432 vcpu->arch.exception.error_code = error_code;
433 return;
434 }
435
436 /* to check exception */
437 prev_nr = vcpu->arch.exception.nr;
438 if (prev_nr == DF_VECTOR) {
439 /* triple fault -> shutdown */
a8eeb04a 440 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 441 return;
442 }
443 class1 = exception_class(prev_nr);
444 class2 = exception_class(nr);
445 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
446 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 447 /*
448 * Generate double fault per SDM Table 5-5. Set
449 * exception.pending = true so that the double fault
450 * can trigger a nested vmexit.
451 */
3fd28fce 452 vcpu->arch.exception.pending = true;
664f8e26 453 vcpu->arch.exception.injected = false;
3fd28fce
ED		 454 vcpu->arch.exception.has_error_code = true;
455 vcpu->arch.exception.nr = DF_VECTOR;
456 vcpu->arch.exception.error_code = 0;
457 } else
458 /* replace previous exception with a new one in a hope
459 that instruction re-execution will regenerate lost
460 exception */
461 goto queue;
462}
463
298101da
AK		 464void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
465{
ce7ddec4 466 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 467}
468EXPORT_SYMBOL_GPL(kvm_queue_exception);
469
ce7ddec4
JR		 470void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
471{
472 kvm_multiple_exception(vcpu, nr, false, 0, true);
473}
474EXPORT_SYMBOL_GPL(kvm_requeue_exception);
475
6affcbed 476int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 477{
db8fcefa
AP		 478 if (err)
479 kvm_inject_gp(vcpu, 0);
480 else
6affcbed
KH		 481 return kvm_skip_emulated_instruction(vcpu);
482
483 return 1;
db8fcefa
AP		 484}
485EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 486
6389ee94 487void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 488{
489 ++vcpu->stat.pf_guest;
adfe20fb
WL		 490 vcpu->arch.exception.nested_apf =
491 is_guest_mode(vcpu) && fault->async_page_fault;
492 if (vcpu->arch.exception.nested_apf)
493 vcpu->arch.apf.nested_apf_token = fault->address;
494 else
495 vcpu->arch.cr2 = fault->address;
6389ee94 496 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 497}
27d6c865 498EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 499
ef54bcfe 500static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 501{
6389ee94
AK		 502 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
503 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 504 else
6389ee94 505 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 506
507 return fault->nested_page_fault;
d4f8cf66
JR		 508}
509
3419ffc8
SY		 510void kvm_inject_nmi(struct kvm_vcpu *vcpu)
511{
7460fb4a
AK		 512 atomic_inc(&vcpu->arch.nmi_queued);
513 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 514}
515EXPORT_SYMBOL_GPL(kvm_inject_nmi);
516
298101da
AK		 517void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
518{
ce7ddec4 519 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 520}
521EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
522
ce7ddec4
JR		 523void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
524{
525 kvm_multiple_exception(vcpu, nr, true, error_code, true);
526}
527EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
528
0a79b009
AK		 529/*
530 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
531 * a #GP and return false.
532 */
533bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 534{
0a79b009
AK		 535 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
536 return true;
537 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
538 return false;
298101da 539}
0a79b009 540EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 541
16f8a6f9
NA		 542bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
543{
544 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
545 return true;
546
547 kvm_queue_exception(vcpu, UD_VECTOR);
548 return false;
549}
550EXPORT_SYMBOL_GPL(kvm_require_dr);
551
ec92fe44
JR		 552/*
553 * This function will be used to read from the physical memory of the currently
54bf36aa 554 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 555 * can read from guest physical or from the guest's guest physical memory.
556 */
557int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
558 gfn_t ngfn, void *data, int offset, int len,
559 u32 access)
560{
54987b7a 561 struct x86_exception exception;
ec92fe44
JR		 562 gfn_t real_gfn;
563 gpa_t ngpa;
564
565 ngpa = gfn_to_gpa(ngfn);
54987b7a 566 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 567 if (real_gfn == UNMAPPED_GVA)
568 return -EFAULT;
569
570 real_gfn = gpa_to_gfn(real_gfn);
571
54bf36aa 572 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 573}
574EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
575
69b0049a 576static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 577 void *data, int offset, int len, u32 access)
578{
579 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
580 data, offset, len, access);
581}
582
a03490ed
CO		 583/*
584 * Load the pae pdptrs. Return true is they are all valid.
585 */
ff03a073 586int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 587{
588 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
589 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
590 int i;
591 int ret;
ff03a073 592 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 593
ff03a073
JR		 594 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
595 offset * sizeof(u64), sizeof(pdpte),
596 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 597 if (ret < 0) {
598 ret = 0;
599 goto out;
600 }
601 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 602 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 603 (pdpte[i] &
604 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 605 ret = 0;
606 goto out;
607 }
608 }
609 ret = 1;
610
ff03a073 611 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 612 __set_bit(VCPU_EXREG_PDPTR,
613 (unsigned long *)&vcpu->arch.regs_avail);
614 __set_bit(VCPU_EXREG_PDPTR,
615 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 616out:
a03490ed
CO		 617
618 return ret;
619}
cc4b6871 620EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 621
9ed38ffa 622bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 623{
ff03a073 624 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 625 bool changed = true;
3d06b8bf
JR		 626 int offset;
627 gfn_t gfn;
d835dfec
AK		 628 int r;
629
630 if (is_long_mode(vcpu) || !is_pae(vcpu))
631 return false;
632
6de4f3ad
AK		 633 if (!test_bit(VCPU_EXREG_PDPTR,
634 (unsigned long *)&vcpu->arch.regs_avail))
635 return true;
636
a512177e
PB		 637 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
638 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 639 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
640 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 641 if (r < 0)
642 goto out;
ff03a073 643 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 644out:
d835dfec
AK		 645
646 return changed;
647}
9ed38ffa 648EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 649
49a9b07e 650int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 651{
aad82703 652 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 653 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 654
f9a48e6a
AK		 655 cr0 |= X86_CR0_ET;
656
ab344828 657#ifdef CONFIG_X86_64
0f12244f
GN		 658 if (cr0 & 0xffffffff00000000UL)
659 return 1;
ab344828
GN		 660#endif
661
662 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 663
0f12244f
GN		 664 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
665 return 1;
a03490ed 666
0f12244f
GN		 667 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
668 return 1;
a03490ed
CO		 669
670 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
671#ifdef CONFIG_X86_64
f6801dff 672 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 673 int cs_db, cs_l;
674
0f12244f
GN		 675 if (!is_pae(vcpu))
676 return 1;
a03490ed 677 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 678 if (cs_l)
679 return 1;
a03490ed
CO		 680 } else
681#endif
ff03a073 682 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 683 kvm_read_cr3(vcpu)))
0f12244f 684 return 1;
a03490ed
CO		 685 }
686
ad756a16
MJ		 687 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
688 return 1;
689
a03490ed 690 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 691
d170c419 692 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 693 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 694 kvm_async_pf_hash_reset(vcpu);
695 }
e5f3f027 696
aad82703
SY		 697 if ((cr0 ^ old_cr0) & update_bits)
698 kvm_mmu_reset_context(vcpu);
b18d5431 699
879ae188
LE		 700 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
701 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
702 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 703 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
704
0f12244f
GN		 705 return 0;
706}
2d3ad1f4 707EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 708
2d3ad1f4 709void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 710{
49a9b07e 711 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 712}
2d3ad1f4 713EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 714
42bdf991
MT		 715static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
716{
717 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
718 !vcpu->guest_xcr0_loaded) {
719 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 720 if (vcpu->arch.xcr0 != host_xcr0)
721 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 722 vcpu->guest_xcr0_loaded = 1;
723 }
724}
725
726static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
727{
728 if (vcpu->guest_xcr0_loaded) {
729 if (vcpu->arch.xcr0 != host_xcr0)
730 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
731 vcpu->guest_xcr0_loaded = 0;
732 }
733}
734
69b0049a 735static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 736{
56c103ec
LJ		 737 u64 xcr0 = xcr;
738 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 739 u64 valid_bits;
2acf923e
DC		 740
741 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
742 if (index != XCR_XFEATURE_ENABLED_MASK)
743 return 1;
d91cab78 744 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 745 return 1;
d91cab78 746 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 747 return 1;
46c34cb0
PB		 748
749 /*
750 * Do not allow the guest to set bits that we do not support
751 * saving. However, xcr0 bit 0 is always set, even if the
752 * emulated CPU does not support XSAVE (see fx_init).
753 */
d91cab78 754 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 755 if (xcr0 & ~valid_bits)
2acf923e 756 return 1;
46c34cb0 757
d91cab78
DH		 758 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
759 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 760 return 1;
761
d91cab78
DH		 762 if (xcr0 & XFEATURE_MASK_AVX512) {
763 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 764 return 1;
d91cab78 765 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 766 return 1;
767 }
2acf923e 768 vcpu->arch.xcr0 = xcr0;
56c103ec 769
d91cab78 770 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 771 kvm_update_cpuid(vcpu);
2acf923e
DC		 772 return 0;
773}
774
775int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
776{
764bcbc5
Z		 777 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
778 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 779 kvm_inject_gp(vcpu, 0);
780 return 1;
781 }
782 return 0;
783}
784EXPORT_SYMBOL_GPL(kvm_set_xcr);
785
a83b29c6 786int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 787{
fc78f519 788 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 789 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 790 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 791
0f12244f
GN		 792 if (cr4 & CR4_RESERVED_BITS)
793 return 1;
a03490ed 794
d6321d49 795 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 796 return 1;
797
d6321d49 798 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 799 return 1;
800
d6321d49 801 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 802 return 1;
803
d6321d49 804 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 805 return 1;
806
d6321d49 807 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 808 return 1;
809
fd8cb433 810 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 811 return 1;
812
ae3e61e1
PB		 813 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
814 return 1;
815
a03490ed 816 if (is_long_mode(vcpu)) {
0f12244f
GN		 817 if (!(cr4 & X86_CR4_PAE))
818 return 1;
a2edf57f
AK		 819 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
820 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 821 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
822 kvm_read_cr3(vcpu)))
0f12244f
GN		 823 return 1;
824
ad756a16 825 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 826 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 827 return 1;
828
829 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
830 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
831 return 1;
832 }
833
5e1746d6 834 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 835 return 1;
a03490ed 836
ad756a16
MJ		 837 if (((cr4 ^ old_cr4) & pdptr_bits) ||
838 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 839 kvm_mmu_reset_context(vcpu);
0f12244f 840
b9baba86 841 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 842 kvm_update_cpuid(vcpu);
2acf923e 843
0f12244f
GN		 844 return 0;
845}
2d3ad1f4 846EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 847
2390218b 848int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 849{
ade61e28 850 bool skip_tlb_flush = false;
ac146235 851#ifdef CONFIG_X86_64
c19986fe
JS		 852 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
853
ade61e28 854 if (pcid_enabled) {
208320ba
JS		 855 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
856 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 857 }
ac146235 858#endif
9d88fca7 859
9f8fe504 860 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 861 if (!skip_tlb_flush) {
862 kvm_mmu_sync_roots(vcpu);
ade61e28 863 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 864 }
0f12244f 865 return 0;
d835dfec
AK		 866 }
867
d1cd3ce9 868 if (is_long_mode(vcpu) &&
a780a3ea 869 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 870 return 1;
871 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 872 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 873 return 1;
a03490ed 874
ade61e28 875 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 876 vcpu->arch.cr3 = cr3;
aff48baa 877 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 878
0f12244f
GN		 879 return 0;
880}
2d3ad1f4 881EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 882
eea1cff9 883int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 884{
0f12244f
GN		 885 if (cr8 & CR8_RESERVED_BITS)
886 return 1;
35754c98 887 if (lapic_in_kernel(vcpu))
a03490ed
CO		 888 kvm_lapic_set_tpr(vcpu, cr8);
889 else
ad312c7c 890 vcpu->arch.cr8 = cr8;
0f12244f
GN		 891 return 0;
892}
2d3ad1f4 893EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 894
2d3ad1f4 895unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 896{
35754c98 897 if (lapic_in_kernel(vcpu))
a03490ed
CO		 898 return kvm_lapic_get_cr8(vcpu);
899 else
ad312c7c 900 return vcpu->arch.cr8;
a03490ed 901}
2d3ad1f4 902EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 903
ae561ede
NA		 904static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
905{
906 int i;
907
908 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
909 for (i = 0; i < KVM_NR_DB_REGS; i++)
910 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
911 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
912 }
913}
914
73aaf249
JK		 915static void kvm_update_dr6(struct kvm_vcpu *vcpu)
916{
917 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
918 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
919}
920
c8639010
JK		 921static void kvm_update_dr7(struct kvm_vcpu *vcpu)
922{
923 unsigned long dr7;
924
925 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
926 dr7 = vcpu->arch.guest_debug_dr7;
927 else
928 dr7 = vcpu->arch.dr7;
929 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 930 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
931 if (dr7 & DR7_BP_EN_MASK)
932 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 933}
934
6f43ed01
NA		 935static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
936{
937 u64 fixed = DR6_FIXED_1;
938
d6321d49 939 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 940 fixed |= DR6_RTM;
941 return fixed;
942}
943
338dbc97 944static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 945{
946 switch (dr) {
947 case 0 ... 3:
948 vcpu->arch.db[dr] = val;
949 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
950 vcpu->arch.eff_db[dr] = val;
951 break;
952 case 4:
020df079
GN		 953 /* fall through */
954 case 6:
338dbc97
GN		 955 if (val & 0xffffffff00000000ULL)
956 return -1; /* #GP */
6f43ed01 957 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 958 kvm_update_dr6(vcpu);
020df079
GN		 959 break;
960 case 5:
020df079
GN		 961 /* fall through */
962 default: /* 7 */
338dbc97
GN		 963 if (val & 0xffffffff00000000ULL)
964 return -1; /* #GP */
020df079 965 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 966 kvm_update_dr7(vcpu);
020df079
GN		 967 break;
968 }
969
970 return 0;
971}
338dbc97
GN		 972
973int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
974{
16f8a6f9 975 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 976 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 977 return 1;
978 }
979 return 0;
338dbc97 980}
020df079
GN		 981EXPORT_SYMBOL_GPL(kvm_set_dr);
982
16f8a6f9 983int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 984{
985 switch (dr) {
986 case 0 ... 3:
987 *val = vcpu->arch.db[dr];
988 break;
989 case 4:
020df079
GN		 990 /* fall through */
991 case 6:
73aaf249
JK		 992 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
993 *val = vcpu->arch.dr6;
994 else
995 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 996 break;
997 case 5:
020df079
GN		 998 /* fall through */
999 default: /* 7 */
1000 *val = vcpu->arch.dr7;
1001 break;
1002 }
338dbc97
GN		 1003 return 0;
1004}
020df079
GN		 1005EXPORT_SYMBOL_GPL(kvm_get_dr);
1006
022cd0e8
AK		 1007bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1008{
1009 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1010 u64 data;
1011 int err;
1012
c6702c9d 1013 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1014 if (err)
1015 return err;
1016 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1017 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1018 return err;
1019}
1020EXPORT_SYMBOL_GPL(kvm_rdpmc);
1021
043405e1
CO		 1022/*
1023 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1024 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1025 *
1026 * This list is modified at module load time to reflect the
e3267cbb 1027 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1028 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1029 * may depend on host virtualization features rather than host cpu features.
043405e1 1030 */
e3267cbb 1031
043405e1
CO		 1032static u32 msrs_to_save[] = {
1033 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1034 MSR_STAR,
043405e1
CO		 1035#ifdef CONFIG_X86_64
1036 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1037#endif
b3897a49 1038 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1039 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1040 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1041};
1042
1043static unsigned num_msrs_to_save;
1044
62ef68bb
PB		 1045static u32 emulated_msrs[] = {
1046 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1047 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1048 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1049 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1050 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1051 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1052 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1053 HV_X64_MSR_RESET,
11c4b1ca 1054 HV_X64_MSR_VP_INDEX,
9eec50b8 1055 HV_X64_MSR_VP_RUNTIME,
5c919412 1056 HV_X64_MSR_SCONTROL,
1f4b34f8 1057 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1058 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1059 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1060 HV_X64_MSR_TSC_EMULATION_STATUS,
1061
1062 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1063 MSR_KVM_PV_EOI_EN,
1064
ba904635 1065 MSR_IA32_TSC_ADJUST,
a3e06bbe 1066 MSR_IA32_TSCDEADLINE,
043405e1 1067 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1068 MSR_IA32_MCG_STATUS,
1069 MSR_IA32_MCG_CTL,
c45dcc71 1070 MSR_IA32_MCG_EXT_CTL,
64d60670 1071 MSR_IA32_SMBASE,
52797bf9 1072 MSR_SMI_COUNT,
db2336a8
KH		 1073 MSR_PLATFORM_INFO,
1074 MSR_MISC_FEATURES_ENABLES,
bc226f07 1075 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1076};
1077
62ef68bb
PB		 1078static unsigned num_emulated_msrs;
1079
801e459a
TL		 1080/*
1081 * List of msr numbers which are used to expose MSR-based features that
1082 * can be used by a hypervisor to validate requested CPU features.
1083 */
1084static u32 msr_based_features[] = {
1389309c
PB		 1085 MSR_IA32_VMX_BASIC,
1086 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1087 MSR_IA32_VMX_PINBASED_CTLS,
1088 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1089 MSR_IA32_VMX_PROCBASED_CTLS,
1090 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1091 MSR_IA32_VMX_EXIT_CTLS,
1092 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1093 MSR_IA32_VMX_ENTRY_CTLS,
1094 MSR_IA32_VMX_MISC,
1095 MSR_IA32_VMX_CR0_FIXED0,
1096 MSR_IA32_VMX_CR0_FIXED1,
1097 MSR_IA32_VMX_CR4_FIXED0,
1098 MSR_IA32_VMX_CR4_FIXED1,
1099 MSR_IA32_VMX_VMCS_ENUM,
1100 MSR_IA32_VMX_PROCBASED_CTLS2,
1101 MSR_IA32_VMX_EPT_VPID_CAP,
1102 MSR_IA32_VMX_VMFUNC,
1103
d1d93fa9 1104 MSR_F10H_DECFG,
518e7b94 1105 MSR_IA32_UCODE_REV,
cd283252 1106 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1107};
1108
1109static unsigned int num_msr_based_features;
1110
66421c1e
WL		 1111static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1112{
1113 switch (msr->index) {
518e7b94 1114 case MSR_IA32_UCODE_REV:
cd283252
PB		 1115 case MSR_IA32_ARCH_CAPABILITIES:
1116 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1117 break;
66421c1e
WL		 1118 default:
1119 if (kvm_x86_ops->get_msr_feature(msr))
1120 return 1;
1121 }
1122 return 0;
1123}
1124
801e459a
TL		 1125static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1126{
1127 struct kvm_msr_entry msr;
66421c1e 1128 int r;
801e459a
TL		 1129
1130 msr.index = index;
66421c1e
WL		 1131 r = kvm_get_msr_feature(&msr);
1132 if (r)
1133 return r;
801e459a
TL		 1134
1135 *data = msr.data;
1136
1137 return 0;
1138}
1139
384bb783 1140bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1141{
b69e8cae 1142 if (efer & efer_reserved_bits)
384bb783 1143 return false;
15c4a640 1144
1b4d56b8 1145 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1146 return false;
1b2fd70c 1147
1b4d56b8 1148 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1149 return false;
d8017474 1150
384bb783
JK		 1151 return true;
1152}
1153EXPORT_SYMBOL_GPL(kvm_valid_efer);
1154
1155static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1156{
1157 u64 old_efer = vcpu->arch.efer;
1158
1159 if (!kvm_valid_efer(vcpu, efer))
1160 return 1;
1161
1162 if (is_paging(vcpu)
1163 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1164 return 1;
1165
15c4a640 1166 efer &= ~EFER_LMA;
f6801dff 1167 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1168
a3d204e2
SY		 1169 kvm_x86_ops->set_efer(vcpu, efer);
1170
aad82703
SY		 1171 /* Update reserved bits */
1172 if ((efer ^ old_efer) & EFER_NX)
1173 kvm_mmu_reset_context(vcpu);
1174
b69e8cae 1175 return 0;
15c4a640
CO		 1176}
1177
f2b4b7dd
JR		 1178void kvm_enable_efer_bits(u64 mask)
1179{
1180 efer_reserved_bits &= ~mask;
1181}
1182EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1183
15c4a640
CO		 1184/*
1185 * Writes msr value into into the appropriate "register".
1186 * Returns 0 on success, non-0 otherwise.
1187 * Assumes vcpu_load() was already called.
1188 */
8fe8ab46 1189int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1190{
854e8bb1
NA		 1191 switch (msr->index) {
1192 case MSR_FS_BASE:
1193 case MSR_GS_BASE:
1194 case MSR_KERNEL_GS_BASE:
1195 case MSR_CSTAR:
1196 case MSR_LSTAR:
fd8cb433 1197 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1198 return 1;
1199 break;
1200 case MSR_IA32_SYSENTER_EIP:
1201 case MSR_IA32_SYSENTER_ESP:
1202 /*
1203 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1204 * non-canonical address is written on Intel but not on
1205 * AMD (which ignores the top 32-bits, because it does
1206 * not implement 64-bit SYSENTER).
1207 *
1208 * 64-bit code should hence be able to write a non-canonical
1209 * value on AMD. Making the address canonical ensures that
1210 * vmentry does not fail on Intel after writing a non-canonical
1211 * value, and that something deterministic happens if the guest
1212 * invokes 64-bit SYSENTER.
1213 */
fd8cb433 1214 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1215 }
8fe8ab46 1216 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1217}
854e8bb1 1218EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1219
313a3dc7
CO		 1220/*
1221 * Adapt set_msr() to msr_io()'s calling convention
1222 */
609e36d3
PB		 1223static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1224{
1225 struct msr_data msr;
1226 int r;
1227
1228 msr.index = index;
1229 msr.host_initiated = true;
1230 r = kvm_get_msr(vcpu, &msr);
1231 if (r)
1232 return r;
1233
1234 *data = msr.data;
1235 return 0;
1236}
1237
313a3dc7
CO		 1238static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1239{
8fe8ab46
WA		 1240 struct msr_data msr;
1241
1242 msr.data = *data;
1243 msr.index = index;
1244 msr.host_initiated = true;
1245 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1246}
1247
16e8d74d
MT		 1248#ifdef CONFIG_X86_64
1249struct pvclock_gtod_data {
1250 seqcount_t seq;
1251
1252 struct { /* extract of a clocksource struct */
1253 int vclock_mode;
a5a1d1c2
TG		 1254 u64 cycle_last;
1255 u64 mask;
16e8d74d
MT		 1256 u32 mult;
1257 u32 shift;
1258 } clock;
1259
cbcf2dd3
TG		 1260 u64 boot_ns;
1261 u64 nsec_base;
55dd00a7 1262 u64 wall_time_sec;
16e8d74d
MT		 1263};
1264
1265static struct pvclock_gtod_data pvclock_gtod_data;
1266
1267static void update_pvclock_gtod(struct timekeeper *tk)
1268{
1269 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1270 u64 boot_ns;
1271
876e7881 1272 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1273
1274 write_seqcount_begin(&vdata->seq);
1275
1276 /* copy pvclock gtod data */
876e7881
PZ		 1277 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1278 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1279 vdata->clock.mask = tk->tkr_mono.mask;
1280 vdata->clock.mult = tk->tkr_mono.mult;
1281 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1282
cbcf2dd3 1283 vdata->boot_ns = boot_ns;
876e7881 1284 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1285
55dd00a7
MT		 1286 vdata->wall_time_sec = tk->xtime_sec;
1287
16e8d74d
MT		 1288 write_seqcount_end(&vdata->seq);
1289}
1290#endif
1291
bab5bb39
NK		 1292void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1293{
1294 /*
1295 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1296 * vcpu_enter_guest. This function is only called from
1297 * the physical CPU that is running vcpu.
1298 */
1299 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1300}
16e8d74d 1301
18068523
GOC		 1302static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1303{
9ed3c444
AK		 1304 int version;
1305 int r;
50d0a0f9 1306 struct pvclock_wall_clock wc;
87aeb54f 1307 struct timespec64 boot;
18068523
GOC		 1308
1309 if (!wall_clock)
1310 return;
1311
9ed3c444
AK		 1312 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1313 if (r)
1314 return;
1315
1316 if (version & 1)
1317 ++version; /* first time write, random junk */
1318
1319 ++version;
18068523 1320
1dab1345
NK		 1321 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1322 return;
18068523 1323
50d0a0f9
GH		 1324 /*
1325 * The guest calculates current wall clock time by adding
34c238a1 1326 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1327 * wall clock specified here. guest system time equals host
1328 * system time for us, thus we must fill in host boot time here.
1329 */
87aeb54f 1330 getboottime64(&boot);
50d0a0f9 1331
4b648665 1332 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1333 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1334 boot = timespec64_sub(boot, ts);
4b648665 1335 }
87aeb54f 1336 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1337 wc.nsec = boot.tv_nsec;
1338 wc.version = version;
18068523
GOC		 1339
1340 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1341
1342 version++;
1343 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1344}
1345
50d0a0f9
GH		 1346static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1347{
b51012de
PB		 1348 do_shl32_div32(dividend, divisor);
1349 return dividend;
50d0a0f9
GH		 1350}
1351
3ae13faa 1352static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1353 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1354{
5f4e3f88 1355 uint64_t scaled64;
50d0a0f9
GH		 1356 int32_t shift = 0;
1357 uint64_t tps64;
1358 uint32_t tps32;
1359
3ae13faa
PB		 1360 tps64 = base_hz;
1361 scaled64 = scaled_hz;
50933623 1362 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1363 tps64 >>= 1;
1364 shift--;
1365 }
1366
1367 tps32 = (uint32_t)tps64;
50933623
JK		 1368 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1369 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1370 scaled64 >>= 1;
1371 else
1372 tps32 <<= 1;
50d0a0f9
GH		 1373 shift++;
1374 }
1375
5f4e3f88
ZA		 1376 *pshift = shift;
1377 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1378
3ae13faa
PB		 1379 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1380 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1381}
1382
d828199e 1383#ifdef CONFIG_X86_64
16e8d74d 1384static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1385#endif
16e8d74d 1386
c8076604 1387static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1388static unsigned long max_tsc_khz;
c8076604 1389
cc578287 1390static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1391{
cc578287
ZA		 1392 u64 v = (u64)khz * (1000000 + ppm);
1393 do_div(v, 1000000);
1394 return v;
1e993611
JR		 1395}
1396
381d585c
HZ		 1397static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1398{
1399 u64 ratio;
1400
1401 /* Guest TSC same frequency as host TSC? */
1402 if (!scale) {
1403 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1404 return 0;
1405 }
1406
1407 /* TSC scaling supported? */
1408 if (!kvm_has_tsc_control) {
1409 if (user_tsc_khz > tsc_khz) {
1410 vcpu->arch.tsc_catchup = 1;
1411 vcpu->arch.tsc_always_catchup = 1;
1412 return 0;
1413 } else {
1414 WARN(1, "user requested TSC rate below hardware speed\n");
1415 return -1;
1416 }
1417 }
1418
1419 /* TSC scaling required - calculate ratio */
1420 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1421 user_tsc_khz, tsc_khz);
1422
1423 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1424 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1425 user_tsc_khz);
1426 return -1;
1427 }
1428
1429 vcpu->arch.tsc_scaling_ratio = ratio;
1430 return 0;
1431}
1432
4941b8cb 1433static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1434{
cc578287
ZA		 1435 u32 thresh_lo, thresh_hi;
1436 int use_scaling = 0;
217fc9cf 1437
03ba32ca 1438 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1439 if (user_tsc_khz == 0) {
ad721883
HZ		 1440 /* set tsc_scaling_ratio to a safe value */
1441 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1442 return -1;
ad721883 1443 }
03ba32ca 1444
c285545f 1445 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1446 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1447 &vcpu->arch.virtual_tsc_shift,
1448 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1449 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1450
1451 /*
1452 * Compute the variation in TSC rate which is acceptable
1453 * within the range of tolerance and decide if the
1454 * rate being applied is within that bounds of the hardware
1455 * rate. If so, no scaling or compensation need be done.
1456 */
1457 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1458 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1459 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1460 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1461 use_scaling = 1;
1462 }
4941b8cb 1463 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1464}
1465
1466static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1467{
e26101b1 1468 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1469 vcpu->arch.virtual_tsc_mult,
1470 vcpu->arch.virtual_tsc_shift);
e26101b1 1471 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1472 return tsc;
1473}
1474
b0c39dc6
VK		 1475static inline int gtod_is_based_on_tsc(int mode)
1476{
1477 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1478}
1479
69b0049a 1480static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1481{
1482#ifdef CONFIG_X86_64
1483 bool vcpus_matched;
b48aa97e
MT		 1484 struct kvm_arch *ka = &vcpu->kvm->arch;
1485 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1486
1487 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1488 atomic_read(&vcpu->kvm->online_vcpus));
1489
7f187922
MT		 1490 /*
1491 * Once the masterclock is enabled, always perform request in
1492 * order to update it.
1493 *
1494 * In order to enable masterclock, the host clocksource must be TSC
1495 * and the vcpus need to have matched TSCs. When that happens,
1496 * perform request to enable masterclock.
1497 */
1498 if (ka->use_master_clock ||
b0c39dc6 1499 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1500 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1501
1502 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1503 atomic_read(&vcpu->kvm->online_vcpus),
1504 ka->use_master_clock, gtod->clock.vclock_mode);
1505#endif
1506}
1507
ba904635
WA		 1508static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1509{
e79f245d 1510 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1511 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1512}
1513
35181e86
HZ		 1514/*
1515 * Multiply tsc by a fixed point number represented by ratio.
1516 *
1517 * The most significant 64-N bits (mult) of ratio represent the
1518 * integral part of the fixed point number; the remaining N bits
1519 * (frac) represent the fractional part, ie. ratio represents a fixed
1520 * point number (mult + frac * 2^(-N)).
1521 *
1522 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1523 */
1524static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1525{
1526 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1527}
1528
1529u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1530{
1531 u64 _tsc = tsc;
1532 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1533
1534 if (ratio != kvm_default_tsc_scaling_ratio)
1535 _tsc = __scale_tsc(ratio, tsc);
1536
1537 return _tsc;
1538}
1539EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1540
07c1419a
HZ		 1541static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1542{
1543 u64 tsc;
1544
1545 tsc = kvm_scale_tsc(vcpu, rdtsc());
1546
1547 return target_tsc - tsc;
1548}
1549
4ba76538
HZ		 1550u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1551{
e79f245d
KA		 1552 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1553
1554 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1555}
1556EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1557
a545ab6a
LC		 1558static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1559{
1560 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1561 vcpu->arch.tsc_offset = offset;
1562}
1563
b0c39dc6
VK		 1564static inline bool kvm_check_tsc_unstable(void)
1565{
1566#ifdef CONFIG_X86_64
1567 /*
1568 * TSC is marked unstable when we're running on Hyper-V,
1569 * 'TSC page' clocksource is good.
1570 */
1571 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1572 return false;
1573#endif
1574 return check_tsc_unstable();
1575}
1576
8fe8ab46 1577void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1578{
1579 struct kvm *kvm = vcpu->kvm;
f38e098f 1580 u64 offset, ns, elapsed;
99e3e30a 1581 unsigned long flags;
b48aa97e 1582 bool matched;
0d3da0d2 1583 bool already_matched;
8fe8ab46 1584 u64 data = msr->data;
c5e8ec8e 1585 bool synchronizing = false;
99e3e30a 1586
038f8c11 1587 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1588 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1589 ns = ktime_get_boot_ns();
f38e098f 1590 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1591
03ba32ca 1592 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1593 if (data == 0 && msr->host_initiated) {
1594 /*
1595 * detection of vcpu initialization -- need to sync
1596 * with other vCPUs. This particularly helps to keep
1597 * kvm_clock stable after CPU hotplug
1598 */
1599 synchronizing = true;
1600 } else {
1601 u64 tsc_exp = kvm->arch.last_tsc_write +
1602 nsec_to_cycles(vcpu, elapsed);
1603 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1604 /*
1605 * Special case: TSC write with a small delta (1 second)
1606 * of virtual cycle time against real time is
1607 * interpreted as an attempt to synchronize the CPU.
1608 */
1609 synchronizing = data < tsc_exp + tsc_hz &&
1610 data + tsc_hz > tsc_exp;
1611 }
c5e8ec8e 1612 }
f38e098f
ZA		 1613
1614 /*
5d3cb0f6
ZA		 1615 * For a reliable TSC, we can match TSC offsets, and for an unstable
1616 * TSC, we add elapsed time in this computation. We could let the
1617 * compensation code attempt to catch up if we fall behind, but
1618 * it's better to try to match offsets from the beginning.
1619 */
c5e8ec8e 1620 if (synchronizing &&
5d3cb0f6 1621 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1622 if (!kvm_check_tsc_unstable()) {
e26101b1 1623 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1624 pr_debug("kvm: matched tsc offset for %llu\n", data);
1625 } else {
857e4099 1626 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1627 data += delta;
07c1419a 1628 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1629 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1630 }
b48aa97e 1631 matched = true;
0d3da0d2 1632 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1633 } else {
1634 /*
1635 * We split periods of matched TSC writes into generations.
1636 * For each generation, we track the original measured
1637 * nanosecond time, offset, and write, so if TSCs are in
1638 * sync, we can match exact offset, and if not, we can match
4a969980 1639 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1640 *
1641 * These values are tracked in kvm->arch.cur_xxx variables.
1642 */
1643 kvm->arch.cur_tsc_generation++;
1644 kvm->arch.cur_tsc_nsec = ns;
1645 kvm->arch.cur_tsc_write = data;
1646 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1647 matched = false;
0d3da0d2 1648 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1649 kvm->arch.cur_tsc_generation, data);
f38e098f 1650 }
e26101b1
ZA		 1651
1652 /*
1653 * We also track th most recent recorded KHZ, write and time to
1654 * allow the matching interval to be extended at each write.
1655 */
f38e098f
ZA		 1656 kvm->arch.last_tsc_nsec = ns;
1657 kvm->arch.last_tsc_write = data;
5d3cb0f6 1658 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1659
b183aa58 1660 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1661
1662 /* Keep track of which generation this VCPU has synchronized to */
1663 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1664 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1665 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1666
d6321d49 1667 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1668 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1669
a545ab6a 1670 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1671 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1672
1673 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1674 if (!matched) {
b48aa97e 1675 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1676 } else if (!already_matched) {
1677 kvm->arch.nr_vcpus_matched_tsc++;
1678 }
b48aa97e
MT		 1679
1680 kvm_track_tsc_matching(vcpu);
1681 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1682}
e26101b1 1683
99e3e30a
ZA		 1684EXPORT_SYMBOL_GPL(kvm_write_tsc);
1685
58ea6767
HZ		 1686static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1687 s64 adjustment)
1688{
ea26e4ec 1689 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1690}
1691
1692static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1693{
1694 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1695 WARN_ON(adjustment < 0);
1696 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1697 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1698}
1699
d828199e
MT		 1700#ifdef CONFIG_X86_64
1701
a5a1d1c2 1702static u64 read_tsc(void)
d828199e 1703{
a5a1d1c2 1704 u64 ret = (u64)rdtsc_ordered();
03b9730b 1705 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1706
1707 if (likely(ret >= last))
1708 return ret;
1709
1710 /*
1711 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1712 * predictable (it's just a function of time and the likely is
d828199e
MT		 1713 * very likely) and there's a data dependence, so force GCC
1714 * to generate a branch instead. I don't barrier() because
1715 * we don't actually need a barrier, and if this function
1716 * ever gets inlined it will generate worse code.
1717 */
1718 asm volatile ("");
1719 return last;
1720}
1721
b0c39dc6 1722static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1723{
1724 long v;
1725 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1726 u64 tsc_pg_val;
1727
1728 switch (gtod->clock.vclock_mode) {
1729 case VCLOCK_HVCLOCK:
1730 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1731 tsc_timestamp);
1732 if (tsc_pg_val != U64_MAX) {
1733 /* TSC page valid */
1734 *mode = VCLOCK_HVCLOCK;
1735 v = (tsc_pg_val - gtod->clock.cycle_last) &
1736 gtod->clock.mask;
1737 } else {
1738 /* TSC page invalid */
1739 *mode = VCLOCK_NONE;
1740 }
1741 break;
1742 case VCLOCK_TSC:
1743 *mode = VCLOCK_TSC;
1744 *tsc_timestamp = read_tsc();
1745 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1746 gtod->clock.mask;
1747 break;
1748 default:
1749 *mode = VCLOCK_NONE;
1750 }
d828199e 1751
b0c39dc6
VK		 1752 if (*mode == VCLOCK_NONE)
1753 *tsc_timestamp = v = 0;
d828199e 1754
d828199e
MT		 1755 return v * gtod->clock.mult;
1756}
1757
b0c39dc6 1758static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1759{
cbcf2dd3 1760 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1761 unsigned long seq;
d828199e 1762 int mode;
cbcf2dd3 1763 u64 ns;
d828199e 1764
d828199e
MT		 1765 do {
1766 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1767 ns = gtod->nsec_base;
b0c39dc6 1768 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1769 ns >>= gtod->clock.shift;
cbcf2dd3 1770 ns += gtod->boot_ns;
d828199e 1771 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1772 *t = ns;
d828199e
MT		 1773
1774 return mode;
1775}
1776
899a31f5 1777static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1778{
1779 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1780 unsigned long seq;
1781 int mode;
1782 u64 ns;
1783
1784 do {
1785 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1786 ts->tv_sec = gtod->wall_time_sec;
1787 ns = gtod->nsec_base;
b0c39dc6 1788 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1789 ns >>= gtod->clock.shift;
1790 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1791
1792 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1793 ts->tv_nsec = ns;
1794
1795 return mode;
1796}
1797
b0c39dc6
VK		 1798/* returns true if host is using TSC based clocksource */
1799static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1800{
d828199e 1801 /* checked again under seqlock below */
b0c39dc6 1802 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1803 return false;
1804
b0c39dc6
VK		 1805 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1806 tsc_timestamp));
d828199e 1807}
55dd00a7 1808
b0c39dc6 1809/* returns true if host is using TSC based clocksource */
899a31f5 1810static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1811 u64 *tsc_timestamp)
55dd00a7
MT		 1812{
1813 /* checked again under seqlock below */
b0c39dc6 1814 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1815 return false;
1816
b0c39dc6 1817 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1818}
d828199e
MT		 1819#endif
1820
1821/*
1822 *
b48aa97e
MT		 1823 * Assuming a stable TSC across physical CPUS, and a stable TSC
1824 * across virtual CPUs, the following condition is possible.
1825 * Each numbered line represents an event visible to both
d828199e
MT		 1826 * CPUs at the next numbered event.
1827 *
1828 * "timespecX" represents host monotonic time. "tscX" represents
1829 * RDTSC value.
1830 *
1831 * VCPU0 on CPU0 | VCPU1 on CPU1
1832 *
1833 * 1. read timespec0,tsc0
1834 * 2. | timespec1 = timespec0 + N
1835 * | tsc1 = tsc0 + M
1836 * 3. transition to guest | transition to guest
1837 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1838 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1839 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1840 *
1841 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1842 *
1843 * - ret0 < ret1
1844 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1845 * ...
1846 * - 0 < N - M => M < N
1847 *
1848 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1849 * always the case (the difference between two distinct xtime instances
1850 * might be smaller then the difference between corresponding TSC reads,
1851 * when updating guest vcpus pvclock areas).
1852 *
1853 * To avoid that problem, do not allow visibility of distinct
1854 * system_timestamp/tsc_timestamp values simultaneously: use a master
1855 * copy of host monotonic time values. Update that master copy
1856 * in lockstep.
1857 *
b48aa97e 1858 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1859 *
1860 */
1861
1862static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1863{
1864#ifdef CONFIG_X86_64
1865 struct kvm_arch *ka = &kvm->arch;
1866 int vclock_mode;
b48aa97e
MT		 1867 bool host_tsc_clocksource, vcpus_matched;
1868
1869 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1870 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1871
1872 /*
1873 * If the host uses TSC clock, then passthrough TSC as stable
1874 * to the guest.
1875 */
b48aa97e 1876 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1877 &ka->master_kernel_ns,
1878 &ka->master_cycle_now);
1879
16a96021 1880 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1881 && !ka->backwards_tsc_observed
54750f2c 1882 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1883
d828199e
MT		 1884 if (ka->use_master_clock)
1885 atomic_set(&kvm_guest_has_master_clock, 1);
1886
1887 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1888 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1889 vcpus_matched);
d828199e
MT		 1890#endif
1891}
1892
2860c4b1
PB		 1893void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1894{
1895 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1896}
1897
2e762ff7
MT		 1898static void kvm_gen_update_masterclock(struct kvm *kvm)
1899{
1900#ifdef CONFIG_X86_64
1901 int i;
1902 struct kvm_vcpu *vcpu;
1903 struct kvm_arch *ka = &kvm->arch;
1904
1905 spin_lock(&ka->pvclock_gtod_sync_lock);
1906 kvm_make_mclock_inprogress_request(kvm);
1907 /* no guest entries from this point */
1908 pvclock_update_vm_gtod_copy(kvm);
1909
1910 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1911 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1912
1913 /* guest entries allowed */
1914 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1915 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1916
1917 spin_unlock(&ka->pvclock_gtod_sync_lock);
1918#endif
1919}
1920
e891a32e 1921u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1922{
108b249c 1923 struct kvm_arch *ka = &kvm->arch;
8b953440 1924 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1925 u64 ret;
108b249c 1926
8b953440
PB		 1927 spin_lock(&ka->pvclock_gtod_sync_lock);
1928 if (!ka->use_master_clock) {
1929 spin_unlock(&ka->pvclock_gtod_sync_lock);
1930 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1931 }
1932
8b953440
PB		 1933 hv_clock.tsc_timestamp = ka->master_cycle_now;
1934 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1935 spin_unlock(&ka->pvclock_gtod_sync_lock);
1936
e2c2206a
WL		 1937 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1938 get_cpu();
1939
e70b57a6
WL		 1940 if (__this_cpu_read(cpu_tsc_khz)) {
1941 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1942 &hv_clock.tsc_shift,
1943 &hv_clock.tsc_to_system_mul);
1944 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1945 } else
1946 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1947
1948 put_cpu();
1949
1950 return ret;
108b249c
PB		 1951}
1952
0d6dd2ff
PB		 1953static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1954{
1955 struct kvm_vcpu_arch *vcpu = &v->arch;
1956 struct pvclock_vcpu_time_info guest_hv_clock;
1957
4e335d9e 1958 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1959 &guest_hv_clock, sizeof(guest_hv_clock))))
1960 return;
1961
1962 /* This VCPU is paused, but it's legal for a guest to read another
1963 * VCPU's kvmclock, so we really have to follow the specification where
1964 * it says that version is odd if data is being modified, and even after
1965 * it is consistent.
1966 *
1967 * Version field updates must be kept separate. This is because
1968 * kvm_write_guest_cached might use a "rep movs" instruction, and
1969 * writes within a string instruction are weakly ordered. So there
1970 * are three writes overall.
1971 *
1972 * As a small optimization, only write the version field in the first
1973 * and third write. The vcpu->pv_time cache is still valid, because the
1974 * version field is the first in the struct.
1975 */
1976 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1977
51c4b8bb
LA		 1978 if (guest_hv_clock.version & 1)
1979 ++guest_hv_clock.version; /* first time write, random junk */
1980
0d6dd2ff 1981 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1982 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1983 &vcpu->hv_clock,
1984 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1985
1986 smp_wmb();
1987
1988 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1989 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1990
1991 if (vcpu->pvclock_set_guest_stopped_request) {
1992 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1993 vcpu->pvclock_set_guest_stopped_request = false;
1994 }
1995
1996 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1997
4e335d9e
PB		 1998 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1999 &vcpu->hv_clock,
2000 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2001
2002 smp_wmb();
2003
2004 vcpu->hv_clock.version++;
4e335d9e
PB		 2005 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2006 &vcpu->hv_clock,
2007 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2008}
2009
34c238a1 2010static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2011{
78db6a50 2012 unsigned long flags, tgt_tsc_khz;
18068523 2013 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2014 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2015 s64 kernel_ns;
d828199e 2016 u64 tsc_timestamp, host_tsc;
51d59c6b 2017 u8 pvclock_flags;
d828199e
MT		 2018 bool use_master_clock;
2019
2020 kernel_ns = 0;
2021 host_tsc = 0;
18068523 2022
d828199e
MT		 2023 /*
2024 * If the host uses TSC clock, then passthrough TSC as stable
2025 * to the guest.
2026 */
2027 spin_lock(&ka->pvclock_gtod_sync_lock);
2028 use_master_clock = ka->use_master_clock;
2029 if (use_master_clock) {
2030 host_tsc = ka->master_cycle_now;
2031 kernel_ns = ka->master_kernel_ns;
2032 }
2033 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2034
2035 /* Keep irq disabled to prevent changes to the clock */
2036 local_irq_save(flags);
78db6a50
PB		 2037 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2038 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2039 local_irq_restore(flags);
2040 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2041 return 1;
2042 }
d828199e 2043 if (!use_master_clock) {
4ea1636b 2044 host_tsc = rdtsc();
108b249c 2045 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2046 }
2047
4ba76538 2048 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2049
c285545f
ZA		 2050 /*
2051 * We may have to catch up the TSC to match elapsed wall clock
2052 * time for two reasons, even if kvmclock is used.
2053 * 1) CPU could have been running below the maximum TSC rate
2054 * 2) Broken TSC compensation resets the base at each VCPU
2055 * entry to avoid unknown leaps of TSC even when running
2056 * again on the same CPU. This may cause apparent elapsed
2057 * time to disappear, and the guest to stand still or run
2058 * very slowly.
2059 */
2060 if (vcpu->tsc_catchup) {
2061 u64 tsc = compute_guest_tsc(v, kernel_ns);
2062 if (tsc > tsc_timestamp) {
f1e2b260 2063 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2064 tsc_timestamp = tsc;
2065 }
50d0a0f9
GH		 2066 }
2067
18068523
GOC		 2068 local_irq_restore(flags);
2069
0d6dd2ff 2070 /* With all the info we got, fill in the values */
18068523 2071
78db6a50
PB		 2072 if (kvm_has_tsc_control)
2073 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2074
2075 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2076 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2077 &vcpu->hv_clock.tsc_shift,
2078 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2079 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2080 }
2081
1d5f066e 2082 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2083 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2084 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2085
d828199e 2086 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2087 pvclock_flags = 0;
d828199e
MT		 2088 if (use_master_clock)
2089 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2090
78c0337a
MT		 2091 vcpu->hv_clock.flags = pvclock_flags;
2092
095cf55d
PB		 2093 if (vcpu->pv_time_enabled)
2094 kvm_setup_pvclock_page(v);
2095 if (v == kvm_get_vcpu(v->kvm, 0))
2096 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2097 return 0;
c8076604
GH		 2098}
2099
0061d53d
MT		 2100/*
2101 * kvmclock updates which are isolated to a given vcpu, such as
2102 * vcpu->cpu migration, should not allow system_timestamp from
2103 * the rest of the vcpus to remain static. Otherwise ntp frequency
2104 * correction applies to one vcpu's system_timestamp but not
2105 * the others.
2106 *
2107 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2108 * We need to rate-limit these requests though, as they can
2109 * considerably slow guests that have a large number of vcpus.
2110 * The time for a remote vcpu to update its kvmclock is bound
2111 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2112 */
2113
7e44e449
AJ		 2114#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2115
2116static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2117{
2118 int i;
7e44e449
AJ		 2119 struct delayed_work *dwork = to_delayed_work(work);
2120 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2121 kvmclock_update_work);
2122 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2123 struct kvm_vcpu *vcpu;
2124
2125 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2126 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2127 kvm_vcpu_kick(vcpu);
2128 }
2129}
2130
7e44e449
AJ		 2131static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2132{
2133 struct kvm *kvm = v->kvm;
2134
105b21bb 2135 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2136 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2137 KVMCLOCK_UPDATE_DELAY);
2138}
2139
332967a3
AJ		 2140#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2141
2142static void kvmclock_sync_fn(struct work_struct *work)
2143{
2144 struct delayed_work *dwork = to_delayed_work(work);
2145 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2146 kvmclock_sync_work);
2147 struct kvm *kvm = container_of(ka, struct kvm, arch);
2148
630994b3
MT		 2149 if (!kvmclock_periodic_sync)
2150 return;
2151
332967a3
AJ		 2152 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2153 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2154 KVMCLOCK_SYNC_PERIOD);
2155}
2156
9ffd986c 2157static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2158{
890ca9ae
HY		 2159 u64 mcg_cap = vcpu->arch.mcg_cap;
2160 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2161 u32 msr = msr_info->index;
2162 u64 data = msr_info->data;
890ca9ae 2163
15c4a640 2164 switch (msr) {
15c4a640 2165 case MSR_IA32_MCG_STATUS:
890ca9ae 2166 vcpu->arch.mcg_status = data;
15c4a640 2167 break;
c7ac679c 2168 case MSR_IA32_MCG_CTL:
44883f01
PB		 2169 if (!(mcg_cap & MCG_CTL_P) &&
2170 (data || !msr_info->host_initiated))
890ca9ae
HY		 2171 return 1;
2172 if (data != 0 && data != ~(u64)0)
44883f01 2173 return 1;
890ca9ae
HY		 2174 vcpu->arch.mcg_ctl = data;
2175 break;
2176 default:
2177 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2178 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2179 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2180 /* only 0 or all 1s can be written to IA32_MCi_CTL
2181 * some Linux kernels though clear bit 10 in bank 4 to
2182 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2183 * this to avoid an uncatched #GP in the guest
2184 */
890ca9ae 2185 if ((offset & 0x3) == 0 &&
114be429 2186 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2187 return -1;
9ffd986c
WL		 2188 if (!msr_info->host_initiated &&
2189 (offset & 0x3) == 1 && data != 0)
2190 return -1;
890ca9ae
HY		 2191 vcpu->arch.mce_banks[offset] = data;
2192 break;
2193 }
2194 return 1;
2195 }
2196 return 0;
2197}
2198
ffde22ac
ES		 2199static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2200{
2201 struct kvm *kvm = vcpu->kvm;
2202 int lm = is_long_mode(vcpu);
2203 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2204 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2205 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2206 : kvm->arch.xen_hvm_config.blob_size_32;
2207 u32 page_num = data & ~PAGE_MASK;
2208 u64 page_addr = data & PAGE_MASK;
2209 u8 *page;
2210 int r;
2211
2212 r = -E2BIG;
2213 if (page_num >= blob_size)
2214 goto out;
2215 r = -ENOMEM;
ff5c2c03
SL		 2216 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2217 if (IS_ERR(page)) {
2218 r = PTR_ERR(page);
ffde22ac 2219 goto out;
ff5c2c03 2220 }
54bf36aa 2221 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2222 goto out_free;
2223 r = 0;
2224out_free:
2225 kfree(page);
2226out:
2227 return r;
2228}
2229
344d9588
GN		 2230static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2231{
2232 gpa_t gpa = data & ~0x3f;
2233
52a5c155
WL		 2234 /* Bits 3:5 are reserved, Should be zero */
2235 if (data & 0x38)
344d9588
GN		 2236 return 1;
2237
2238 vcpu->arch.apf.msr_val = data;
2239
2240 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2241 kvm_clear_async_pf_completion_queue(vcpu);
2242 kvm_async_pf_hash_reset(vcpu);
2243 return 0;
2244 }
2245
4e335d9e 2246 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2247 sizeof(u32)))
344d9588
GN		 2248 return 1;
2249
6adba527 2250 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2251 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2252 kvm_async_pf_wakeup_all(vcpu);
2253 return 0;
2254}
2255
12f9a48f
GC		 2256static void kvmclock_reset(struct kvm_vcpu *vcpu)
2257{
0b79459b 2258 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2259}
2260
f38a7b75
WL		 2261static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2262{
2263 ++vcpu->stat.tlb_flush;
2264 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2265}
2266
c9aaa895
GC		 2267static void record_steal_time(struct kvm_vcpu *vcpu)
2268{
2269 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2270 return;
2271
4e335d9e 2272 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2273 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2274 return;
2275
f38a7b75
WL		 2276 /*
2277 * Doing a TLB flush here, on the guest's behalf, can avoid
2278 * expensive IPIs.
2279 */
2280 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2281 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2282
35f3fae1
WL		 2283 if (vcpu->arch.st.steal.version & 1)
2284 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2285
2286 vcpu->arch.st.steal.version += 1;
2287
4e335d9e 2288 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2289 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2290
2291 smp_wmb();
2292
c54cdf14
LC		 2293 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2294 vcpu->arch.st.last_steal;
2295 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2296
4e335d9e 2297 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2298 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2299
2300 smp_wmb();
2301
2302 vcpu->arch.st.steal.version += 1;
c9aaa895 2303
4e335d9e 2304 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2305 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2306}
2307
8fe8ab46 2308int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2309{
5753785f 2310 bool pr = false;
8fe8ab46
WA		 2311 u32 msr = msr_info->index;
2312 u64 data = msr_info->data;
5753785f 2313
15c4a640 2314 switch (msr) {
2e32b719 2315 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2316 case MSR_IA32_UCODE_WRITE:
2317 case MSR_VM_HSAVE_PA:
2318 case MSR_AMD64_PATCH_LOADER:
2319 case MSR_AMD64_BU_CFG2:
405a353a 2320 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2321 break;
2322
518e7b94
WL		 2323 case MSR_IA32_UCODE_REV:
2324 if (msr_info->host_initiated)
2325 vcpu->arch.microcode_version = data;
2326 break;
15c4a640 2327 case MSR_EFER:
b69e8cae 2328 return set_efer(vcpu, data);
8f1589d9
AP		 2329 case MSR_K7_HWCR:
2330 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2331 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2332 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2333 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2334 if (data != 0) {
a737f256
CD		 2335 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2336 data);
8f1589d9
AP		 2337 return 1;
2338 }
15c4a640 2339 break;
f7c6d140
AP		 2340 case MSR_FAM10H_MMIO_CONF_BASE:
2341 if (data != 0) {
a737f256
CD		 2342 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2343 "0x%llx\n", data);
f7c6d140
AP		 2344 return 1;
2345 }
15c4a640 2346 break;
b5e2fec0
AG		 2347 case MSR_IA32_DEBUGCTLMSR:
2348 if (!data) {
2349 /* We support the non-activated case already */
2350 break;
2351 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2352 /* Values other than LBR and BTF are vendor-specific,
2353 thus reserved and should throw a #GP */
2354 return 1;
2355 }
a737f256
CD		 2356 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2357 __func__, data);
b5e2fec0 2358 break;
9ba075a6 2359 case 0x200 ... 0x2ff:
ff53604b 2360 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2361 case MSR_IA32_APICBASE:
58cb628d 2362 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2363 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2364 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2365 case MSR_IA32_TSCDEADLINE:
2366 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2367 break;
ba904635 2368 case MSR_IA32_TSC_ADJUST:
d6321d49 2369 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2370 if (!msr_info->host_initiated) {
d913b904 2371 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2372 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2373 }
2374 vcpu->arch.ia32_tsc_adjust_msr = data;
2375 }
2376 break;
15c4a640 2377 case MSR_IA32_MISC_ENABLE:
ad312c7c 2378 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2379 break;
64d60670
PB		 2380 case MSR_IA32_SMBASE:
2381 if (!msr_info->host_initiated)
2382 return 1;
2383 vcpu->arch.smbase = data;
2384 break;
dd259935
PB		 2385 case MSR_IA32_TSC:
2386 kvm_write_tsc(vcpu, msr_info);
2387 break;
52797bf9
LA		 2388 case MSR_SMI_COUNT:
2389 if (!msr_info->host_initiated)
2390 return 1;
2391 vcpu->arch.smi_count = data;
2392 break;
11c6bffa 2393 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2394 case MSR_KVM_WALL_CLOCK:
2395 vcpu->kvm->arch.wall_clock = data;
2396 kvm_write_wall_clock(vcpu->kvm, data);
2397 break;
11c6bffa 2398 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2399 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2400 struct kvm_arch *ka = &vcpu->kvm->arch;
2401
12f9a48f 2402 kvmclock_reset(vcpu);
18068523 2403
54750f2c
MT		 2404 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2405 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2406
2407 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2408 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2409
2410 ka->boot_vcpu_runs_old_kvmclock = tmp;
2411 }
2412
18068523 2413 vcpu->arch.time = data;
0061d53d 2414 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2415
2416 /* we verify if the enable bit is set... */
2417 if (!(data & 1))
2418 break;
2419
4e335d9e 2420 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2421 &vcpu->arch.pv_time, data & ~1ULL,
2422 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2423 vcpu->arch.pv_time_enabled = false;
2424 else
2425 vcpu->arch.pv_time_enabled = true;
32cad84f 2426
18068523
GOC		 2427 break;
2428 }
344d9588
GN		 2429 case MSR_KVM_ASYNC_PF_EN:
2430 if (kvm_pv_enable_async_pf(vcpu, data))
2431 return 1;
2432 break;
c9aaa895
GC		 2433 case MSR_KVM_STEAL_TIME:
2434
2435 if (unlikely(!sched_info_on()))
2436 return 1;
2437
2438 if (data & KVM_STEAL_RESERVED_MASK)
2439 return 1;
2440
4e335d9e 2441 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2442 data & KVM_STEAL_VALID_BITS,
2443 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2444 return 1;
2445
2446 vcpu->arch.st.msr_val = data;
2447
2448 if (!(data & KVM_MSR_ENABLED))
2449 break;
2450
c9aaa895
GC		 2451 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2452
2453 break;
ae7a2a3f
MT		 2454 case MSR_KVM_PV_EOI_EN:
2455 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2456 return 1;
2457 break;
c9aaa895 2458
890ca9ae
HY		 2459 case MSR_IA32_MCG_CTL:
2460 case MSR_IA32_MCG_STATUS:
81760dcc 2461 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2462 return set_msr_mce(vcpu, msr_info);
71db6023 2463
6912ac32
WH		 2464 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2465 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2466 pr = true; /* fall through */
2467 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2468 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2469 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2470 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2471
2472 if (pr || data != 0)
a737f256
CD		 2473 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2474 "0x%x data 0x%llx\n", msr, data);
5753785f 2475 break;
84e0cefa
JS		 2476 case MSR_K7_CLK_CTL:
2477 /*
2478 * Ignore all writes to this no longer documented MSR.
2479 * Writes are only relevant for old K7 processors,
2480 * all pre-dating SVM, but a recommended workaround from
4a969980 2481 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2482 * affected processor models on the command line, hence
2483 * the need to ignore the workaround.
2484 */
2485 break;
55cd8e5a 2486 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2487 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2488 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2489 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2490 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2491 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2492 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2493 return kvm_hv_set_msr_common(vcpu, msr, data,
2494 msr_info->host_initiated);
91c9c3ed 2495 case MSR_IA32_BBL_CR_CTL3:
2496 /* Drop writes to this legacy MSR -- see rdmsr
2497 * counterpart for further detail.
2498 */
fab0aa3b
EM		 2499 if (report_ignored_msrs)
2500 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2501 msr, data);
91c9c3ed 2502 break;
2b036c6b 2503 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2504 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2505 return 1;
2506 vcpu->arch.osvw.length = data;
2507 break;
2508 case MSR_AMD64_OSVW_STATUS:
d6321d49 2509 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2510 return 1;
2511 vcpu->arch.osvw.status = data;
2512 break;
db2336a8
KH		 2513 case MSR_PLATFORM_INFO:
2514 if (!msr_info->host_initiated ||
2515 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2516 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2517 cpuid_fault_enabled(vcpu)))
2518 return 1;
2519 vcpu->arch.msr_platform_info = data;
2520 break;
2521 case MSR_MISC_FEATURES_ENABLES:
2522 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2523 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2524 !supports_cpuid_fault(vcpu)))
2525 return 1;
2526 vcpu->arch.msr_misc_features_enables = data;
2527 break;
15c4a640 2528 default:
ffde22ac
ES		 2529 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2530 return xen_hvm_config(vcpu, data);
c6702c9d 2531 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2532 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2533 if (!ignore_msrs) {
ae0f5499 2534 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2535 msr, data);
ed85c068
AP		 2536 return 1;
2537 } else {
fab0aa3b
EM		 2538 if (report_ignored_msrs)
2539 vcpu_unimpl(vcpu,
2540 "ignored wrmsr: 0x%x data 0x%llx\n",
2541 msr, data);
ed85c068
AP		 2542 break;
2543 }
15c4a640
CO		 2544 }
2545 return 0;
2546}
2547EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2548
2549
2550/*
2551 * Reads an msr value (of 'msr_index') into 'pdata'.
2552 * Returns 0 on success, non-0 otherwise.
2553 * Assumes vcpu_load() was already called.
2554 */
609e36d3 2555int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2556{
609e36d3 2557 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2558}
ff651cb6 2559EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2560
44883f01 2561static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2562{
2563 u64 data;
890ca9ae
HY		 2564 u64 mcg_cap = vcpu->arch.mcg_cap;
2565 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2566
2567 switch (msr) {
15c4a640
CO		 2568 case MSR_IA32_P5_MC_ADDR:
2569 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2570 data = 0;
2571 break;
15c4a640 2572 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2573 data = vcpu->arch.mcg_cap;
2574 break;
c7ac679c 2575 case MSR_IA32_MCG_CTL:
44883f01 2576 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2577 return 1;
2578 data = vcpu->arch.mcg_ctl;
2579 break;
2580 case MSR_IA32_MCG_STATUS:
2581 data = vcpu->arch.mcg_status;
2582 break;
2583 default:
2584 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2585 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2586 u32 offset = msr - MSR_IA32_MC0_CTL;
2587 data = vcpu->arch.mce_banks[offset];
2588 break;
2589 }
2590 return 1;
2591 }
2592 *pdata = data;
2593 return 0;
2594}
2595
609e36d3 2596int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2597{
609e36d3 2598 switch (msr_info->index) {
890ca9ae 2599 case MSR_IA32_PLATFORM_ID:
15c4a640 2600 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2601 case MSR_IA32_DEBUGCTLMSR:
2602 case MSR_IA32_LASTBRANCHFROMIP:
2603 case MSR_IA32_LASTBRANCHTOIP:
2604 case MSR_IA32_LASTINTFROMIP:
2605 case MSR_IA32_LASTINTTOIP:
60af2ecd 2606 case MSR_K8_SYSCFG:
3afb1121
PB		 2607 case MSR_K8_TSEG_ADDR:
2608 case MSR_K8_TSEG_MASK:
60af2ecd 2609 case MSR_K7_HWCR:
61a6bd67 2610 case MSR_VM_HSAVE_PA:
1fdbd48c 2611 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2612 case MSR_AMD64_NB_CFG:
f7c6d140 2613 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2614 case MSR_AMD64_BU_CFG2:
0c2df2a1 2615 case MSR_IA32_PERF_CTL:
405a353a 2616 case MSR_AMD64_DC_CFG:
609e36d3 2617 msr_info->data = 0;
15c4a640 2618 break;
c51eb52b 2619 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2620 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2621 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2622 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2623 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2624 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2625 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2626 msr_info->data = 0;
5753785f 2627 break;
742bc670 2628 case MSR_IA32_UCODE_REV:
518e7b94 2629 msr_info->data = vcpu->arch.microcode_version;
742bc670 2630 break;
dd259935
PB		 2631 case MSR_IA32_TSC:
2632 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2633 break;
9ba075a6 2634 case MSR_MTRRcap:
9ba075a6 2635 case 0x200 ... 0x2ff:
ff53604b 2636 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2637 case 0xcd: /* fsb frequency */
609e36d3 2638 msr_info->data = 3;
15c4a640 2639 break;
7b914098
JS		 2640 /*
2641 * MSR_EBC_FREQUENCY_ID
2642 * Conservative value valid for even the basic CPU models.
2643 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2644 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2645 * and 266MHz for model 3, or 4. Set Core Clock
2646 * Frequency to System Bus Frequency Ratio to 1 (bits
2647 * 31:24) even though these are only valid for CPU
2648 * models > 2, however guests may end up dividing or
2649 * multiplying by zero otherwise.
2650 */
2651 case MSR_EBC_FREQUENCY_ID:
609e36d3 2652 msr_info->data = 1 << 24;
7b914098 2653 break;
15c4a640 2654 case MSR_IA32_APICBASE:
609e36d3 2655 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2656 break;
0105d1a5 2657 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2658 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2659 break;
a3e06bbe 2660 case MSR_IA32_TSCDEADLINE:
609e36d3 2661 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2662 break;
ba904635 2663 case MSR_IA32_TSC_ADJUST:
609e36d3 2664 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2665 break;
15c4a640 2666 case MSR_IA32_MISC_ENABLE:
609e36d3 2667 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2668 break;
64d60670
PB		 2669 case MSR_IA32_SMBASE:
2670 if (!msr_info->host_initiated)
2671 return 1;
2672 msr_info->data = vcpu->arch.smbase;
15c4a640 2673 break;
52797bf9
LA		 2674 case MSR_SMI_COUNT:
2675 msr_info->data = vcpu->arch.smi_count;
2676 break;
847f0ad8
AG		 2677 case MSR_IA32_PERF_STATUS:
2678 /* TSC increment by tick */
609e36d3 2679 msr_info->data = 1000ULL;
847f0ad8 2680 /* CPU multiplier */
b0996ae4 2681 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2682 break;
15c4a640 2683 case MSR_EFER:
609e36d3 2684 msr_info->data = vcpu->arch.efer;
15c4a640 2685 break;
18068523 2686 case MSR_KVM_WALL_CLOCK:
11c6bffa 2687 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2688 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2689 break;
2690 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2691 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2692 msr_info->data = vcpu->arch.time;
18068523 2693 break;
344d9588 2694 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2695 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2696 break;
c9aaa895 2697 case MSR_KVM_STEAL_TIME:
609e36d3 2698 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2699 break;
1d92128f 2700 case MSR_KVM_PV_EOI_EN:
609e36d3 2701 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2702 break;
890ca9ae
HY		 2703 case MSR_IA32_P5_MC_ADDR:
2704 case MSR_IA32_P5_MC_TYPE:
2705 case MSR_IA32_MCG_CAP:
2706 case MSR_IA32_MCG_CTL:
2707 case MSR_IA32_MCG_STATUS:
81760dcc 2708 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2709 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2710 msr_info->host_initiated);
84e0cefa
JS		 2711 case MSR_K7_CLK_CTL:
2712 /*
2713 * Provide expected ramp-up count for K7. All other
2714 * are set to zero, indicating minimum divisors for
2715 * every field.
2716 *
2717 * This prevents guest kernels on AMD host with CPU
2718 * type 6, model 8 and higher from exploding due to
2719 * the rdmsr failing.
2720 */
609e36d3 2721 msr_info->data = 0x20000000;
84e0cefa 2722 break;
55cd8e5a 2723 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2724 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2725 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2726 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2727 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2728 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2729 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2730 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2731 msr_info->index, &msr_info->data,
2732 msr_info->host_initiated);
55cd8e5a 2733 break;
91c9c3ed 2734 case MSR_IA32_BBL_CR_CTL3:
2735 /* This legacy MSR exists but isn't fully documented in current
2736 * silicon. It is however accessed by winxp in very narrow
2737 * scenarios where it sets bit #19, itself documented as
2738 * a "reserved" bit. Best effort attempt to source coherent
2739 * read data here should the balance of the register be
2740 * interpreted by the guest:
2741 *
2742 * L2 cache control register 3: 64GB range, 256KB size,
2743 * enabled, latency 0x1, configured
2744 */
609e36d3 2745 msr_info->data = 0xbe702111;
91c9c3ed 2746 break;
2b036c6b 2747 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2748 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2749 return 1;
609e36d3 2750 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2751 break;
2752 case MSR_AMD64_OSVW_STATUS:
d6321d49 2753 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2754 return 1;
609e36d3 2755 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2756 break;
db2336a8
KH		 2757 case MSR_PLATFORM_INFO:
2758 msr_info->data = vcpu->arch.msr_platform_info;
2759 break;
2760 case MSR_MISC_FEATURES_ENABLES:
2761 msr_info->data = vcpu->arch.msr_misc_features_enables;
2762 break;
15c4a640 2763 default:
c6702c9d 2764 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2765 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2766 if (!ignore_msrs) {
ae0f5499
BD		 2767 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2768 msr_info->index);
ed85c068
AP		 2769 return 1;
2770 } else {
fab0aa3b
EM		 2771 if (report_ignored_msrs)
2772 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2773 msr_info->index);
609e36d3 2774 msr_info->data = 0;
ed85c068
AP		 2775 }
2776 break;
15c4a640 2777 }
15c4a640
CO		 2778 return 0;
2779}
2780EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2781
313a3dc7
CO		 2782/*
2783 * Read or write a bunch of msrs. All parameters are kernel addresses.
2784 *
2785 * @return number of msrs set successfully.
2786 */
2787static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2788 struct kvm_msr_entry *entries,
2789 int (*do_msr)(struct kvm_vcpu *vcpu,
2790 unsigned index, u64 *data))
2791{
801e459a 2792 int i;
313a3dc7 2793
313a3dc7
CO		 2794 for (i = 0; i < msrs->nmsrs; ++i)
2795 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2796 break;
2797
313a3dc7
CO		 2798 return i;
2799}
2800
2801/*
2802 * Read or write a bunch of msrs. Parameters are user addresses.
2803 *
2804 * @return number of msrs set successfully.
2805 */
2806static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2807 int (*do_msr)(struct kvm_vcpu *vcpu,
2808 unsigned index, u64 *data),
2809 int writeback)
2810{
2811 struct kvm_msrs msrs;
2812 struct kvm_msr_entry *entries;
2813 int r, n;
2814 unsigned size;
2815
2816 r = -EFAULT;
2817 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2818 goto out;
2819
2820 r = -E2BIG;
2821 if (msrs.nmsrs >= MAX_IO_MSRS)
2822 goto out;
2823
313a3dc7 2824 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2825 entries = memdup_user(user_msrs->entries, size);
2826 if (IS_ERR(entries)) {
2827 r = PTR_ERR(entries);
313a3dc7 2828 goto out;
ff5c2c03 2829 }
313a3dc7
CO		 2830
2831 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2832 if (r < 0)
2833 goto out_free;
2834
2835 r = -EFAULT;
2836 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2837 goto out_free;
2838
2839 r = n;
2840
2841out_free:
7a73c028 2842 kfree(entries);
313a3dc7
CO		 2843out:
2844 return r;
2845}
2846
4d5422ce
WL		 2847static inline bool kvm_can_mwait_in_guest(void)
2848{
2849 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2850 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2851 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2852}
2853
784aa3d7 2854int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2855{
4d5422ce 2856 int r = 0;
018d00d2
ZX		 2857
2858 switch (ext) {
2859 case KVM_CAP_IRQCHIP:
2860 case KVM_CAP_HLT:
2861 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2862 case KVM_CAP_SET_TSS_ADDR:
07716717 2863 case KVM_CAP_EXT_CPUID:
9c15bb1d 2864 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2865 case KVM_CAP_CLOCKSOURCE:
7837699f 2866 case KVM_CAP_PIT:
a28e4f5a 2867 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2868 case KVM_CAP_MP_STATE:
ed848624 2869 case KVM_CAP_SYNC_MMU:
a355c85c 2870 case KVM_CAP_USER_NMI:
52d939a0 2871 case KVM_CAP_REINJECT_CONTROL:
4925663a 2872 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2873 case KVM_CAP_IOEVENTFD:
f848a5a8 2874 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2875 case KVM_CAP_PIT2:
e9f42757 2876 case KVM_CAP_PIT_STATE2:
b927a3ce 2877 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2878 case KVM_CAP_XEN_HVM:
3cfc3092 2879 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2880 case KVM_CAP_HYPERV:
10388a07 2881 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2882 case KVM_CAP_HYPERV_SPIN:
5c919412 2883 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2884 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2885 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2886 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 2887 case KVM_CAP_HYPERV_TLBFLUSH:
ab9f4ecb 2888 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2889 case KVM_CAP_DEBUGREGS:
d2be1651 2890 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2891 case KVM_CAP_XSAVE:
344d9588 2892 case KVM_CAP_ASYNC_PF:
92a1f12d 2893 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2894 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2895 case KVM_CAP_READONLY_MEM:
5f66b620 2896 case KVM_CAP_HYPERV_TIME:
100943c5 2897 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2898 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2899 case KVM_CAP_ENABLE_CAP_VM:
2900 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2901 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2902 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2903 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2904 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2905 r = 1;
2906 break;
01643c51
KH		 2907 case KVM_CAP_SYNC_REGS:
2908 r = KVM_SYNC_X86_VALID_FIELDS;
2909 break;
e3fd9a93
PB		 2910 case KVM_CAP_ADJUST_CLOCK:
2911 r = KVM_CLOCK_TSC_STABLE;
2912 break;
4d5422ce 2913 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 2914 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2915 if(kvm_can_mwait_in_guest())
2916 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2917 break;
6d396b55
PB		 2918 case KVM_CAP_X86_SMM:
2919 /* SMBASE is usually relocated above 1M on modern chipsets,
2920 * and SMM handlers might indeed rely on 4G segment limits,
2921 * so do not report SMM to be available if real mode is
2922 * emulated via vm86 mode. Still, do not go to great lengths
2923 * to avoid userspace's usage of the feature, because it is a
2924 * fringe case that is not enabled except via specific settings
2925 * of the module parameters.
2926 */
bc226f07 2927 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 2928 break;
774ead3a
AK		 2929 case KVM_CAP_VAPIC:
2930 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2931 break;
f725230a 2932 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2933 r = KVM_SOFT_MAX_VCPUS;
2934 break;
2935 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2936 r = KVM_MAX_VCPUS;
2937 break;
a988b910 2938 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2939 r = KVM_USER_MEM_SLOTS;
a988b910 2940 break;
a68a6a72
MT		 2941 case KVM_CAP_PV_MMU: /* obsolete */
2942 r = 0;
2f333bcb 2943 break;
890ca9ae
HY		 2944 case KVM_CAP_MCE:
2945 r = KVM_MAX_MCE_BANKS;
2946 break;
2d5b5a66 2947 case KVM_CAP_XCRS:
d366bf7e 2948 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2949 break;
92a1f12d
JR		 2950 case KVM_CAP_TSC_CONTROL:
2951 r = kvm_has_tsc_control;
2952 break;
37131313
RK		 2953 case KVM_CAP_X2APIC_API:
2954 r = KVM_X2APIC_API_VALID_FLAGS;
2955 break;
8fcc4b59
JM		 2956 case KVM_CAP_NESTED_STATE:
2957 r = kvm_x86_ops->get_nested_state ?
2958 kvm_x86_ops->get_nested_state(NULL, 0, 0) : 0;
2959 break;
018d00d2 2960 default:
018d00d2
ZX		 2961 break;
2962 }
2963 return r;
2964
2965}
2966
043405e1
CO		 2967long kvm_arch_dev_ioctl(struct file *filp,
2968 unsigned int ioctl, unsigned long arg)
2969{
2970 void __user *argp = (void __user *)arg;
2971 long r;
2972
2973 switch (ioctl) {
2974 case KVM_GET_MSR_INDEX_LIST: {
2975 struct kvm_msr_list __user *user_msr_list = argp;
2976 struct kvm_msr_list msr_list;
2977 unsigned n;
2978
2979 r = -EFAULT;
2980 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2981 goto out;
2982 n = msr_list.nmsrs;
62ef68bb 2983 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2984 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2985 goto out;
2986 r = -E2BIG;
e125e7b6 2987 if (n < msr_list.nmsrs)
043405e1
CO		 2988 goto out;
2989 r = -EFAULT;
2990 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2991 num_msrs_to_save * sizeof(u32)))
2992 goto out;
e125e7b6 2993 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2994 &emulated_msrs,
62ef68bb 2995 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2996 goto out;
2997 r = 0;
2998 break;
2999 }
9c15bb1d
BP		 3000 case KVM_GET_SUPPORTED_CPUID:
3001 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3002 struct kvm_cpuid2 __user *cpuid_arg = argp;
3003 struct kvm_cpuid2 cpuid;
3004
3005 r = -EFAULT;
3006 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3007 goto out;
9c15bb1d
BP		 3008
3009 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3010 ioctl);
674eea0f
AK		 3011 if (r)
3012 goto out;
3013
3014 r = -EFAULT;
3015 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3016 goto out;
3017 r = 0;
3018 break;
3019 }
890ca9ae 3020 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3021 r = -EFAULT;
c45dcc71
AR		 3022 if (copy_to_user(argp, &kvm_mce_cap_supported,
3023 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3024 goto out;
3025 r = 0;
3026 break;
801e459a
TL		 3027 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3028 struct kvm_msr_list __user *user_msr_list = argp;
3029 struct kvm_msr_list msr_list;
3030 unsigned int n;
3031
3032 r = -EFAULT;
3033 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3034 goto out;
3035 n = msr_list.nmsrs;
3036 msr_list.nmsrs = num_msr_based_features;
3037 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3038 goto out;
3039 r = -E2BIG;
3040 if (n < msr_list.nmsrs)
3041 goto out;
3042 r = -EFAULT;
3043 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3044 num_msr_based_features * sizeof(u32)))
3045 goto out;
3046 r = 0;
3047 break;
3048 }
3049 case KVM_GET_MSRS:
3050 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3051 break;
890ca9ae 3052 }
043405e1
CO		 3053 default:
3054 r = -EINVAL;
3055 }
3056out:
3057 return r;
3058}
3059
f5f48ee1
SY		 3060static void wbinvd_ipi(void *garbage)
3061{
3062 wbinvd();
3063}
3064
3065static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3066{
e0f0bbc5 3067 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3068}
3069
313a3dc7
CO		 3070void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3071{
f5f48ee1
SY		 3072 /* Address WBINVD may be executed by guest */
3073 if (need_emulate_wbinvd(vcpu)) {
3074 if (kvm_x86_ops->has_wbinvd_exit())
3075 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3076 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3077 smp_call_function_single(vcpu->cpu,
3078 wbinvd_ipi, NULL, 1);
3079 }
3080
313a3dc7 3081 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3082
0dd6a6ed
ZA		 3083 /* Apply any externally detected TSC adjustments (due to suspend) */
3084 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3085 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3086 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3087 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3088 }
8f6055cb 3089
b0c39dc6 3090 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3091 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3092 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3093 if (tsc_delta < 0)
3094 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3095
b0c39dc6 3096 if (kvm_check_tsc_unstable()) {
07c1419a 3097 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3098 vcpu->arch.last_guest_tsc);
a545ab6a 3099 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3100 vcpu->arch.tsc_catchup = 1;
c285545f 3101 }
a749e247
PB		 3102
3103 if (kvm_lapic_hv_timer_in_use(vcpu))
3104 kvm_lapic_restart_hv_timer(vcpu);
3105
d98d07ca
MT		 3106 /*
3107 * On a host with synchronized TSC, there is no need to update
3108 * kvmclock on vcpu->cpu migration
3109 */
3110 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3111 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3112 if (vcpu->cpu != cpu)
1bd2009e 3113 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3114 vcpu->cpu = cpu;
6b7d7e76 3115 }
c9aaa895 3116
c9aaa895 3117 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3118}
3119
0b9f6c46
PX		 3120static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3121{
3122 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3123 return;
3124
fa55eedd 3125 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3126
4e335d9e 3127 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3128 &vcpu->arch.st.steal.preempted,
3129 offsetof(struct kvm_steal_time, preempted),
3130 sizeof(vcpu->arch.st.steal.preempted));
3131}
3132
313a3dc7
CO		 3133void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3134{
cc0d907c 3135 int idx;
de63ad4c
LM		 3136
3137 if (vcpu->preempted)
3138 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3139
931f261b
AA		 3140 /*
3141 * Disable page faults because we're in atomic context here.
3142 * kvm_write_guest_offset_cached() would call might_fault()
3143 * that relies on pagefault_disable() to tell if there's a
3144 * bug. NOTE: the write to guest memory may not go through if
3145 * during postcopy live migration or if there's heavy guest
3146 * paging.
3147 */
3148 pagefault_disable();
cc0d907c
AA		 3149 /*
3150 * kvm_memslots() will be called by
3151 * kvm_write_guest_offset_cached() so take the srcu lock.
3152 */
3153 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3154 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3155 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3156 pagefault_enable();
02daab21 3157 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3158 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3159 /*
3160 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3161 * on every vmexit, but if not, we might have a stale dr6 from the
3162 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3163 */
3164 set_debugreg(0, 6);
313a3dc7
CO		 3165}
3166
313a3dc7
CO		 3167static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3168 struct kvm_lapic_state *s)
3169{
fa59cc00 3170 if (vcpu->arch.apicv_active)
d62caabb
AS		 3171 kvm_x86_ops->sync_pir_to_irr(vcpu);
3172
a92e2543 3173 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3174}
3175
3176static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3177 struct kvm_lapic_state *s)
3178{
a92e2543
RK		 3179 int r;
3180
3181 r = kvm_apic_set_state(vcpu, s);
3182 if (r)
3183 return r;
cb142eb7 3184 update_cr8_intercept(vcpu);
313a3dc7
CO		 3185
3186 return 0;
3187}
3188
127a457a
MG		 3189static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3190{
3191 return (!lapic_in_kernel(vcpu) ||
3192 kvm_apic_accept_pic_intr(vcpu));
3193}
3194
782d422b
MG		 3195/*
3196 * if userspace requested an interrupt window, check that the
3197 * interrupt window is open.
3198 *
3199 * No need to exit to userspace if we already have an interrupt queued.
3200 */
3201static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3202{
3203 return kvm_arch_interrupt_allowed(vcpu) &&
3204 !kvm_cpu_has_interrupt(vcpu) &&
3205 !kvm_event_needs_reinjection(vcpu) &&
3206 kvm_cpu_accept_dm_intr(vcpu);
3207}
3208
f77bc6a4
ZX		 3209static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3210 struct kvm_interrupt *irq)
3211{
02cdb50f 3212 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3213 return -EINVAL;
1c1a9ce9
SR		 3214
3215 if (!irqchip_in_kernel(vcpu->kvm)) {
3216 kvm_queue_interrupt(vcpu, irq->irq, false);
3217 kvm_make_request(KVM_REQ_EVENT, vcpu);
3218 return 0;
3219 }
3220
3221 /*
3222 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3223 * fail for in-kernel 8259.
3224 */
3225 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3226 return -ENXIO;
f77bc6a4 3227
1c1a9ce9
SR		 3228 if (vcpu->arch.pending_external_vector != -1)
3229 return -EEXIST;
f77bc6a4 3230
1c1a9ce9 3231 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3232 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3233 return 0;
3234}
3235
c4abb7c9
JK		 3236static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3237{
c4abb7c9 3238 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3239
3240 return 0;
3241}
3242
f077825a
PB		 3243static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3244{
64d60670
PB		 3245 kvm_make_request(KVM_REQ_SMI, vcpu);
3246
f077825a
PB		 3247 return 0;
3248}
3249
b209749f
AK		 3250static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3251 struct kvm_tpr_access_ctl *tac)
3252{
3253 if (tac->flags)
3254 return -EINVAL;
3255 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3256 return 0;
3257}
3258
890ca9ae
HY		 3259static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3260 u64 mcg_cap)
3261{
3262 int r;
3263 unsigned bank_num = mcg_cap & 0xff, bank;
3264
3265 r = -EINVAL;
a9e38c3e 3266 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3267 goto out;
c45dcc71 3268 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3269 goto out;
3270 r = 0;
3271 vcpu->arch.mcg_cap = mcg_cap;
3272 /* Init IA32_MCG_CTL to all 1s */
3273 if (mcg_cap & MCG_CTL_P)
3274 vcpu->arch.mcg_ctl = ~(u64)0;
3275 /* Init IA32_MCi_CTL to all 1s */
3276 for (bank = 0; bank < bank_num; bank++)
3277 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3278
3279 if (kvm_x86_ops->setup_mce)
3280 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3281out:
3282 return r;
3283}
3284
3285static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3286 struct kvm_x86_mce *mce)
3287{
3288 u64 mcg_cap = vcpu->arch.mcg_cap;
3289 unsigned bank_num = mcg_cap & 0xff;
3290 u64 *banks = vcpu->arch.mce_banks;
3291
3292 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3293 return -EINVAL;
3294 /*
3295 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3296 * reporting is disabled
3297 */
3298 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3299 vcpu->arch.mcg_ctl != ~(u64)0)
3300 return 0;
3301 banks += 4 * mce->bank;
3302 /*
3303 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3304 * reporting is disabled for the bank
3305 */
3306 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3307 return 0;
3308 if (mce->status & MCI_STATUS_UC) {
3309 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3310 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3311 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3312 return 0;
3313 }
3314 if (banks[1] & MCI_STATUS_VAL)
3315 mce->status |= MCI_STATUS_OVER;
3316 banks[2] = mce->addr;
3317 banks[3] = mce->misc;
3318 vcpu->arch.mcg_status = mce->mcg_status;
3319 banks[1] = mce->status;
3320 kvm_queue_exception(vcpu, MC_VECTOR);
3321 } else if (!(banks[1] & MCI_STATUS_VAL)
3322 || !(banks[1] & MCI_STATUS_UC)) {
3323 if (banks[1] & MCI_STATUS_VAL)
3324 mce->status |= MCI_STATUS_OVER;
3325 banks[2] = mce->addr;
3326 banks[3] = mce->misc;
3327 banks[1] = mce->status;
3328 } else
3329 banks[1] |= MCI_STATUS_OVER;
3330 return 0;
3331}
3332
3cfc3092
JK		 3333static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3334 struct kvm_vcpu_events *events)
3335{
7460fb4a 3336 process_nmi(vcpu);
664f8e26
WL		 3337 /*
3338 * FIXME: pass injected and pending separately. This is only
3339 * needed for nested virtualization, whose state cannot be
3340 * migrated yet. For now we can combine them.
3341 */
03b82a30 3342 events->exception.injected =
664f8e26
WL		 3343 (vcpu->arch.exception.pending ||
3344 vcpu->arch.exception.injected) &&
03b82a30 3345 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3346 events->exception.nr = vcpu->arch.exception.nr;
3347 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3348 events->exception.pad = 0;
3cfc3092
JK		 3349 events->exception.error_code = vcpu->arch.exception.error_code;
3350
03b82a30 3351 events->interrupt.injected =
04140b41 3352 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3353 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3354 events->interrupt.soft = 0;
37ccdcbe 3355 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3356
3357 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3358 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3359 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3360 events->nmi.pad = 0;
3cfc3092 3361
66450a21 3362 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3363
f077825a
PB		 3364 events->smi.smm = is_smm(vcpu);
3365 events->smi.pending = vcpu->arch.smi_pending;
3366 events->smi.smm_inside_nmi =
3367 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3368 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3369
dab4b911 3370 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3371 | KVM_VCPUEVENT_VALID_SHADOW
3372 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3373 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3374}
3375
6ef4e07e
XG		 3376static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3377
3cfc3092
JK		 3378static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3379 struct kvm_vcpu_events *events)
3380{
dab4b911 3381 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3382 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3383 | KVM_VCPUEVENT_VALID_SHADOW
3384 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3385 return -EINVAL;
3386
78e546c8 3387 if (events->exception.injected &&
28d06353
JM		 3388 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3389 is_guest_mode(vcpu)))
78e546c8
PB		 3390 return -EINVAL;
3391
28bf2888
DH		 3392 /* INITs are latched while in SMM */
3393 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3394 (events->smi.smm || events->smi.pending) &&
3395 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3396 return -EINVAL;
3397
7460fb4a 3398 process_nmi(vcpu);
664f8e26 3399 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3400 vcpu->arch.exception.pending = events->exception.injected;
3401 vcpu->arch.exception.nr = events->exception.nr;
3402 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3403 vcpu->arch.exception.error_code = events->exception.error_code;
3404
04140b41 3405 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3406 vcpu->arch.interrupt.nr = events->interrupt.nr;
3407 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3408 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3409 kvm_x86_ops->set_interrupt_shadow(vcpu,
3410 events->interrupt.shadow);
3cfc3092
JK		 3411
3412 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3413 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3414 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3415 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3416
66450a21 3417 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3418 lapic_in_kernel(vcpu))
66450a21 3419 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3420
f077825a 3421 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3422 u32 hflags = vcpu->arch.hflags;
f077825a 3423 if (events->smi.smm)
6ef4e07e 3424 hflags |= HF_SMM_MASK;
f077825a 3425 else
6ef4e07e
XG		 3426 hflags &= ~HF_SMM_MASK;
3427 kvm_set_hflags(vcpu, hflags);
3428
f077825a 3429 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3430
3431 if (events->smi.smm) {
3432 if (events->smi.smm_inside_nmi)
3433 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3434 else
f4ef1910
WL		 3435 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3436 if (lapic_in_kernel(vcpu)) {
3437 if (events->smi.latched_init)
3438 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3439 else
3440 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3441 }
f077825a
PB		 3442 }
3443 }
3444
3842d135
AK		 3445 kvm_make_request(KVM_REQ_EVENT, vcpu);
3446
3cfc3092
JK		 3447 return 0;
3448}
3449
a1efbe77
JK		 3450static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3451 struct kvm_debugregs *dbgregs)
3452{
73aaf249
JK		 3453 unsigned long val;
3454
a1efbe77 3455 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3456 kvm_get_dr(vcpu, 6, &val);
73aaf249 3457 dbgregs->dr6 = val;
a1efbe77
JK		 3458 dbgregs->dr7 = vcpu->arch.dr7;
3459 dbgregs->flags = 0;
97e69aa6 3460 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3461}
3462
3463static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3464 struct kvm_debugregs *dbgregs)
3465{
3466 if (dbgregs->flags)
3467 return -EINVAL;
3468
d14bdb55
PB		 3469 if (dbgregs->dr6 & ~0xffffffffull)
3470 return -EINVAL;
3471 if (dbgregs->dr7 & ~0xffffffffull)
3472 return -EINVAL;
3473
a1efbe77 3474 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3475 kvm_update_dr0123(vcpu);
a1efbe77 3476 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3477 kvm_update_dr6(vcpu);
a1efbe77 3478 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3479 kvm_update_dr7(vcpu);
a1efbe77 3480
a1efbe77
JK		 3481 return 0;
3482}
3483
df1daba7
PB		 3484#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3485
3486static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3487{
c47ada30 3488 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3489 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3490 u64 valid;
3491
3492 /*
3493 * Copy legacy XSAVE area, to avoid complications with CPUID
3494 * leaves 0 and 1 in the loop below.
3495 */
3496 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3497
3498 /* Set XSTATE_BV */
00c87e9a 3499 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3500 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3501
3502 /*
3503 * Copy each region from the possibly compacted offset to the
3504 * non-compacted offset.
3505 */
d91cab78 3506 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3507 while (valid) {
3508 u64 feature = valid & -valid;
3509 int index = fls64(feature) - 1;
3510 void *src = get_xsave_addr(xsave, feature);
3511
3512 if (src) {
3513 u32 size, offset, ecx, edx;
3514 cpuid_count(XSTATE_CPUID, index,
3515 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3516 if (feature == XFEATURE_MASK_PKRU)
3517 memcpy(dest + offset, &vcpu->arch.pkru,
3518 sizeof(vcpu->arch.pkru));
3519 else
3520 memcpy(dest + offset, src, size);
3521
df1daba7
PB		 3522 }
3523
3524 valid -= feature;
3525 }
3526}
3527
3528static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3529{
c47ada30 3530 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3531 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3532 u64 valid;
3533
3534 /*
3535 * Copy legacy XSAVE area, to avoid complications with CPUID
3536 * leaves 0 and 1 in the loop below.
3537 */
3538 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3539
3540 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3541 xsave->header.xfeatures = xstate_bv;
782511b0 3542 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3543 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3544
3545 /*
3546 * Copy each region from the non-compacted offset to the
3547 * possibly compacted offset.
3548 */
d91cab78 3549 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3550 while (valid) {
3551 u64 feature = valid & -valid;
3552 int index = fls64(feature) - 1;
3553 void *dest = get_xsave_addr(xsave, feature);
3554
3555 if (dest) {
3556 u32 size, offset, ecx, edx;
3557 cpuid_count(XSTATE_CPUID, index,
3558 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3559 if (feature == XFEATURE_MASK_PKRU)
3560 memcpy(&vcpu->arch.pkru, src + offset,
3561 sizeof(vcpu->arch.pkru));
3562 else
3563 memcpy(dest, src + offset, size);
ee4100da 3564 }
df1daba7
PB		 3565
3566 valid -= feature;
3567 }
3568}
3569
2d5b5a66
SY		 3570static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3571 struct kvm_xsave *guest_xsave)
3572{
d366bf7e 3573 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3574 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3575 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3576 } else {
2d5b5a66 3577 memcpy(guest_xsave->region,
7366ed77 3578 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3579 sizeof(struct fxregs_state));
2d5b5a66 3580 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3581 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3582 }
3583}
3584
a575813b
WL		 3585#define XSAVE_MXCSR_OFFSET 24
3586
2d5b5a66
SY		 3587static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3588 struct kvm_xsave *guest_xsave)
3589{
3590 u64 xstate_bv =
3591 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3592 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3593
d366bf7e 3594 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3595 /*
3596 * Here we allow setting states that are not present in
3597 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3598 * with old userspace.
3599 */
a575813b
WL		 3600 if (xstate_bv & ~kvm_supported_xcr0() ||
3601 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3602 return -EINVAL;
df1daba7 3603 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3604 } else {
a575813b
WL		 3605 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3606 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3607 return -EINVAL;
7366ed77 3608 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3609 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3610 }
3611 return 0;
3612}
3613
3614static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3615 struct kvm_xcrs *guest_xcrs)
3616{
d366bf7e 3617 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3618 guest_xcrs->nr_xcrs = 0;
3619 return;
3620 }
3621
3622 guest_xcrs->nr_xcrs = 1;
3623 guest_xcrs->flags = 0;
3624 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3625 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3626}
3627
3628static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3629 struct kvm_xcrs *guest_xcrs)
3630{
3631 int i, r = 0;
3632
d366bf7e 3633 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3634 return -EINVAL;
3635
3636 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3637 return -EINVAL;
3638
3639 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3640 /* Only support XCR0 currently */
c67a04cb 3641 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3642 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3643 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3644 break;
3645 }
3646 if (r)
3647 r = -EINVAL;
3648 return r;
3649}
3650
1c0b28c2
EM		 3651/*
3652 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3653 * stopped by the hypervisor. This function will be called from the host only.
3654 * EINVAL is returned when the host attempts to set the flag for a guest that
3655 * does not support pv clocks.
3656 */
3657static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3658{
0b79459b 3659 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3660 return -EINVAL;
51d59c6b 3661 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3662 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3663 return 0;
3664}
3665
5c919412
AS		 3666static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3667 struct kvm_enable_cap *cap)
3668{
3669 if (cap->flags)
3670 return -EINVAL;
3671
3672 switch (cap->cap) {
efc479e6
RK		 3673 case KVM_CAP_HYPERV_SYNIC2:
3674 if (cap->args[0])
3675 return -EINVAL;
5c919412 3676 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3677 if (!irqchip_in_kernel(vcpu->kvm))
3678 return -EINVAL;
efc479e6
RK		 3679 return kvm_hv_activate_synic(vcpu, cap->cap ==
3680 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3681 default:
3682 return -EINVAL;
3683 }
3684}
3685
313a3dc7
CO		 3686long kvm_arch_vcpu_ioctl(struct file *filp,
3687 unsigned int ioctl, unsigned long arg)
3688{
3689 struct kvm_vcpu *vcpu = filp->private_data;
3690 void __user *argp = (void __user *)arg;
3691 int r;
d1ac91d8
AK		 3692 union {
3693 struct kvm_lapic_state *lapic;
3694 struct kvm_xsave *xsave;
3695 struct kvm_xcrs *xcrs;
3696 void *buffer;
3697 } u;
3698
9b062471
CD		 3699 vcpu_load(vcpu);
3700
d1ac91d8 3701 u.buffer = NULL;
313a3dc7
CO		 3702 switch (ioctl) {
3703 case KVM_GET_LAPIC: {
2204ae3c 3704 r = -EINVAL;
bce87cce 3705 if (!lapic_in_kernel(vcpu))
2204ae3c 3706 goto out;
d1ac91d8 3707 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3708
b772ff36 3709 r = -ENOMEM;
d1ac91d8 3710 if (!u.lapic)
b772ff36 3711 goto out;
d1ac91d8 3712 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3713 if (r)
3714 goto out;
3715 r = -EFAULT;
d1ac91d8 3716 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3717 goto out;
3718 r = 0;
3719 break;
3720 }
3721 case KVM_SET_LAPIC: {
2204ae3c 3722 r = -EINVAL;
bce87cce 3723 if (!lapic_in_kernel(vcpu))
2204ae3c 3724 goto out;
ff5c2c03 3725 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3726 if (IS_ERR(u.lapic)) {
3727 r = PTR_ERR(u.lapic);
3728 goto out_nofree;
3729 }
ff5c2c03 3730
d1ac91d8 3731 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3732 break;
3733 }
f77bc6a4
ZX		 3734 case KVM_INTERRUPT: {
3735 struct kvm_interrupt irq;
3736
3737 r = -EFAULT;
3738 if (copy_from_user(&irq, argp, sizeof irq))
3739 goto out;
3740 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3741 break;
3742 }
c4abb7c9
JK		 3743 case KVM_NMI: {
3744 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3745 break;
3746 }
f077825a
PB		 3747 case KVM_SMI: {
3748 r = kvm_vcpu_ioctl_smi(vcpu);
3749 break;
3750 }
313a3dc7
CO		 3751 case KVM_SET_CPUID: {
3752 struct kvm_cpuid __user *cpuid_arg = argp;
3753 struct kvm_cpuid cpuid;
3754
3755 r = -EFAULT;
3756 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3757 goto out;
3758 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3759 break;
3760 }
07716717
DK		 3761 case KVM_SET_CPUID2: {
3762 struct kvm_cpuid2 __user *cpuid_arg = argp;
3763 struct kvm_cpuid2 cpuid;
3764
3765 r = -EFAULT;
3766 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3767 goto out;
3768 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3769 cpuid_arg->entries);
07716717
DK		 3770 break;
3771 }
3772 case KVM_GET_CPUID2: {
3773 struct kvm_cpuid2 __user *cpuid_arg = argp;
3774 struct kvm_cpuid2 cpuid;
3775
3776 r = -EFAULT;
3777 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3778 goto out;
3779 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3780 cpuid_arg->entries);
07716717
DK		 3781 if (r)
3782 goto out;
3783 r = -EFAULT;
3784 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3785 goto out;
3786 r = 0;
3787 break;
3788 }
801e459a
TL		 3789 case KVM_GET_MSRS: {
3790 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3791 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3792 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3793 break;
801e459a
TL		 3794 }
3795 case KVM_SET_MSRS: {
3796 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3797 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3798 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3799 break;
801e459a 3800 }
b209749f
AK		 3801 case KVM_TPR_ACCESS_REPORTING: {
3802 struct kvm_tpr_access_ctl tac;
3803
3804 r = -EFAULT;
3805 if (copy_from_user(&tac, argp, sizeof tac))
3806 goto out;
3807 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3808 if (r)
3809 goto out;
3810 r = -EFAULT;
3811 if (copy_to_user(argp, &tac, sizeof tac))
3812 goto out;
3813 r = 0;
3814 break;
3815 };
b93463aa
AK		 3816 case KVM_SET_VAPIC_ADDR: {
3817 struct kvm_vapic_addr va;
7301d6ab 3818 int idx;
b93463aa
AK		 3819
3820 r = -EINVAL;
35754c98 3821 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3822 goto out;
3823 r = -EFAULT;
3824 if (copy_from_user(&va, argp, sizeof va))
3825 goto out;
7301d6ab 3826 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3827 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3828 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3829 break;
3830 }
890ca9ae
HY		 3831 case KVM_X86_SETUP_MCE: {
3832 u64 mcg_cap;
3833
3834 r = -EFAULT;
3835 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3836 goto out;
3837 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3838 break;
3839 }
3840 case KVM_X86_SET_MCE: {
3841 struct kvm_x86_mce mce;
3842
3843 r = -EFAULT;
3844 if (copy_from_user(&mce, argp, sizeof mce))
3845 goto out;
3846 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3847 break;
3848 }
3cfc3092
JK		 3849 case KVM_GET_VCPU_EVENTS: {
3850 struct kvm_vcpu_events events;
3851
3852 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3853
3854 r = -EFAULT;
3855 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3856 break;
3857 r = 0;
3858 break;
3859 }
3860 case KVM_SET_VCPU_EVENTS: {
3861 struct kvm_vcpu_events events;
3862
3863 r = -EFAULT;
3864 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3865 break;
3866
3867 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3868 break;
3869 }
a1efbe77
JK		 3870 case KVM_GET_DEBUGREGS: {
3871 struct kvm_debugregs dbgregs;
3872
3873 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3874
3875 r = -EFAULT;
3876 if (copy_to_user(argp, &dbgregs,
3877 sizeof(struct kvm_debugregs)))
3878 break;
3879 r = 0;
3880 break;
3881 }
3882 case KVM_SET_DEBUGREGS: {
3883 struct kvm_debugregs dbgregs;
3884
3885 r = -EFAULT;
3886 if (copy_from_user(&dbgregs, argp,
3887 sizeof(struct kvm_debugregs)))
3888 break;
3889
3890 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3891 break;
3892 }
2d5b5a66 3893 case KVM_GET_XSAVE: {
d1ac91d8 3894 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3895 r = -ENOMEM;
d1ac91d8 3896 if (!u.xsave)
2d5b5a66
SY		 3897 break;
3898
d1ac91d8 3899 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3900
3901 r = -EFAULT;
d1ac91d8 3902 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3903 break;
3904 r = 0;
3905 break;
3906 }
3907 case KVM_SET_XSAVE: {
ff5c2c03 3908 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3909 if (IS_ERR(u.xsave)) {
3910 r = PTR_ERR(u.xsave);
3911 goto out_nofree;
3912 }
2d5b5a66 3913
d1ac91d8 3914 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3915 break;
3916 }
3917 case KVM_GET_XCRS: {
d1ac91d8 3918 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3919 r = -ENOMEM;
d1ac91d8 3920 if (!u.xcrs)
2d5b5a66
SY		 3921 break;
3922
d1ac91d8 3923 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3924
3925 r = -EFAULT;
d1ac91d8 3926 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3927 sizeof(struct kvm_xcrs)))
3928 break;
3929 r = 0;
3930 break;
3931 }
3932 case KVM_SET_XCRS: {
ff5c2c03 3933 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3934 if (IS_ERR(u.xcrs)) {
3935 r = PTR_ERR(u.xcrs);
3936 goto out_nofree;
3937 }
2d5b5a66 3938
d1ac91d8 3939 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3940 break;
3941 }
92a1f12d
JR		 3942 case KVM_SET_TSC_KHZ: {
3943 u32 user_tsc_khz;
3944
3945 r = -EINVAL;
92a1f12d
JR		 3946 user_tsc_khz = (u32)arg;
3947
3948 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3949 goto out;
3950
cc578287
ZA		 3951 if (user_tsc_khz == 0)
3952 user_tsc_khz = tsc_khz;
3953
381d585c
HZ		 3954 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3955 r = 0;
92a1f12d 3956
92a1f12d
JR		 3957 goto out;
3958 }
3959 case KVM_GET_TSC_KHZ: {
cc578287 3960 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3961 goto out;
3962 }
1c0b28c2
EM		 3963 case KVM_KVMCLOCK_CTRL: {
3964 r = kvm_set_guest_paused(vcpu);
3965 goto out;
3966 }
5c919412
AS		 3967 case KVM_ENABLE_CAP: {
3968 struct kvm_enable_cap cap;
3969
3970 r = -EFAULT;
3971 if (copy_from_user(&cap, argp, sizeof(cap)))
3972 goto out;
3973 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3974 break;
3975 }
8fcc4b59
JM		 3976 case KVM_GET_NESTED_STATE: {
3977 struct kvm_nested_state __user *user_kvm_nested_state = argp;
3978 u32 user_data_size;
3979
3980 r = -EINVAL;
3981 if (!kvm_x86_ops->get_nested_state)
3982 break;
3983
3984 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
3985 if (get_user(user_data_size, &user_kvm_nested_state->size))
3986 return -EFAULT;
3987
3988 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
3989 user_data_size);
3990 if (r < 0)
3991 return r;
3992
3993 if (r > user_data_size) {
3994 if (put_user(r, &user_kvm_nested_state->size))
3995 return -EFAULT;
3996 return -E2BIG;
3997 }
3998 r = 0;
3999 break;
4000 }
4001 case KVM_SET_NESTED_STATE: {
4002 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4003 struct kvm_nested_state kvm_state;
4004
4005 r = -EINVAL;
4006 if (!kvm_x86_ops->set_nested_state)
4007 break;
4008
4009 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4010 return -EFAULT;
4011
4012 if (kvm_state.size < sizeof(kvm_state))
4013 return -EINVAL;
4014
4015 if (kvm_state.flags &
4016 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE))
4017 return -EINVAL;
4018
4019 /* nested_run_pending implies guest_mode. */
4020 if (kvm_state.flags == KVM_STATE_NESTED_RUN_PENDING)
4021 return -EINVAL;
4022
4023 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4024 break;
4025 }
313a3dc7
CO		 4026 default:
4027 r = -EINVAL;
4028 }
4029out:
d1ac91d8 4030 kfree(u.buffer);
9b062471
CD		 4031out_nofree:
4032 vcpu_put(vcpu);
313a3dc7
CO		 4033 return r;
4034}
4035
1499fa80 4036vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4037{
4038 return VM_FAULT_SIGBUS;
4039}
4040
1fe779f8
CO		 4041static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4042{
4043 int ret;
4044
4045 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4046 return -EINVAL;
1fe779f8
CO		 4047 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4048 return ret;
4049}
4050
b927a3ce
SY		 4051static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4052 u64 ident_addr)
4053{
2ac52ab8 4054 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4055}
4056
1fe779f8
CO		 4057static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4058 u32 kvm_nr_mmu_pages)
4059{
4060 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4061 return -EINVAL;
4062
79fac95e 4063 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4064
4065 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4066 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4067
79fac95e 4068 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4069 return 0;
4070}
4071
4072static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4073{
39de71ec 4074 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4075}
4076
1fe779f8
CO		 4077static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4078{
90bca052 4079 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4080 int r;
4081
4082 r = 0;
4083 switch (chip->chip_id) {
4084 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4085 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4086 sizeof(struct kvm_pic_state));
4087 break;
4088 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4089 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4090 sizeof(struct kvm_pic_state));
4091 break;
4092 case KVM_IRQCHIP_IOAPIC:
33392b49 4093 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4094 break;
4095 default:
4096 r = -EINVAL;
4097 break;
4098 }
4099 return r;
4100}
4101
4102static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4103{
90bca052 4104 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4105 int r;
4106
4107 r = 0;
4108 switch (chip->chip_id) {
4109 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4110 spin_lock(&pic->lock);
4111 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4112 sizeof(struct kvm_pic_state));
90bca052 4113 spin_unlock(&pic->lock);
1fe779f8
CO		 4114 break;
4115 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4116 spin_lock(&pic->lock);
4117 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4118 sizeof(struct kvm_pic_state));
90bca052 4119 spin_unlock(&pic->lock);
1fe779f8
CO		 4120 break;
4121 case KVM_IRQCHIP_IOAPIC:
33392b49 4122 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4123 break;
4124 default:
4125 r = -EINVAL;
4126 break;
4127 }
90bca052 4128 kvm_pic_update_irq(pic);
1fe779f8
CO		 4129 return r;
4130}
4131
e0f63cb9
SY		 4132static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4133{
34f3941c
RK		 4134 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4135
4136 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4137
4138 mutex_lock(&kps->lock);
4139 memcpy(ps, &kps->channels, sizeof(*ps));
4140 mutex_unlock(&kps->lock);
2da29bcc 4141 return 0;
e0f63cb9
SY		 4142}
4143
4144static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4145{
0185604c 4146 int i;
09edea72
RK		 4147 struct kvm_pit *pit = kvm->arch.vpit;
4148
4149 mutex_lock(&pit->pit_state.lock);
34f3941c 4150 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4151 for (i = 0; i < 3; i++)
09edea72
RK		 4152 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4153 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4154 return 0;
e9f42757
BK		 4155}
4156
4157static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4158{
e9f42757
BK		 4159 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4160 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4161 sizeof(ps->channels));
4162 ps->flags = kvm->arch.vpit->pit_state.flags;
4163 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4164 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4165 return 0;
e9f42757
BK		 4166}
4167
4168static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4169{
2da29bcc 4170 int start = 0;
0185604c 4171 int i;
e9f42757 4172 u32 prev_legacy, cur_legacy;
09edea72
RK		 4173 struct kvm_pit *pit = kvm->arch.vpit;
4174
4175 mutex_lock(&pit->pit_state.lock);
4176 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4177 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4178 if (!prev_legacy && cur_legacy)
4179 start = 1;
09edea72
RK		 4180 memcpy(&pit->pit_state.channels, &ps->channels,
4181 sizeof(pit->pit_state.channels));
4182 pit->pit_state.flags = ps->flags;
0185604c 4183 for (i = 0; i < 3; i++)
09edea72 4184 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4185 start && i == 0);
09edea72 4186 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4187 return 0;
e0f63cb9
SY		 4188}
4189
52d939a0
MT		 4190static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4191 struct kvm_reinject_control *control)
4192{
71474e2f
RK		 4193 struct kvm_pit *pit = kvm->arch.vpit;
4194
4195 if (!pit)
52d939a0 4196 return -ENXIO;
b39c90b6 4197
71474e2f
RK		 4198 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4199 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4200 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4201 */
4202 mutex_lock(&pit->pit_state.lock);
4203 kvm_pit_set_reinject(pit, control->pit_reinject);
4204 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4205
52d939a0
MT		 4206 return 0;
4207}
4208
95d4c16c 4209/**
60c34612
TY		 4210 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4211 * @kvm: kvm instance
4212 * @log: slot id and address to which we copy the log
95d4c16c 4213 *
e108ff2f
PB		 4214 * Steps 1-4 below provide general overview of dirty page logging. See
4215 * kvm_get_dirty_log_protect() function description for additional details.
4216 *
4217 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4218 * always flush the TLB (step 4) even if previous step failed and the dirty
4219 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4220 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4221 * writes will be marked dirty for next log read.
95d4c16c 4222 *
60c34612
TY		 4223 * 1. Take a snapshot of the bit and clear it if needed.
4224 * 2. Write protect the corresponding page.
e108ff2f
PB		 4225 * 3. Copy the snapshot to the userspace.
4226 * 4. Flush TLB's if needed.
5bb064dc 4227 */
60c34612 4228int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4229{
60c34612 4230 bool is_dirty = false;
e108ff2f 4231 int r;
5bb064dc 4232
79fac95e 4233 mutex_lock(&kvm->slots_lock);
5bb064dc 4234
88178fd4
KH		 4235 /*
4236 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4237 */
4238 if (kvm_x86_ops->flush_log_dirty)
4239 kvm_x86_ops->flush_log_dirty(kvm);
4240
e108ff2f 4241 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4242
4243 /*
4244 * All the TLBs can be flushed out of mmu lock, see the comments in
4245 * kvm_mmu_slot_remove_write_access().
4246 */
e108ff2f 4247 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4248 if (is_dirty)
4249 kvm_flush_remote_tlbs(kvm);
4250
79fac95e 4251 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4252 return r;
4253}
4254
aa2fbe6d
YZ		 4255int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4256 bool line_status)
23d43cf9
CD		 4257{
4258 if (!irqchip_in_kernel(kvm))
4259 return -ENXIO;
4260
4261 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4262 irq_event->irq, irq_event->level,
4263 line_status);
23d43cf9
CD		 4264 return 0;
4265}
4266
90de4a18
NA		 4267static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4268 struct kvm_enable_cap *cap)
4269{
4270 int r;
4271
4272 if (cap->flags)
4273 return -EINVAL;
4274
4275 switch (cap->cap) {
4276 case KVM_CAP_DISABLE_QUIRKS:
4277 kvm->arch.disabled_quirks = cap->args[0];
4278 r = 0;
4279 break;
49df6397
SR		 4280 case KVM_CAP_SPLIT_IRQCHIP: {
4281 mutex_lock(&kvm->lock);
b053b2ae
SR		 4282 r = -EINVAL;
4283 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4284 goto split_irqchip_unlock;
49df6397
SR		 4285 r = -EEXIST;
4286 if (irqchip_in_kernel(kvm))
4287 goto split_irqchip_unlock;
557abc40 4288 if (kvm->created_vcpus)
49df6397
SR		 4289 goto split_irqchip_unlock;
4290 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4291 if (r)
49df6397
SR		 4292 goto split_irqchip_unlock;
4293 /* Pairs with irqchip_in_kernel. */
4294 smp_wmb();
49776faf 4295 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4296 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4297 r = 0;
4298split_irqchip_unlock:
4299 mutex_unlock(&kvm->lock);
4300 break;
4301 }
37131313
RK		 4302 case KVM_CAP_X2APIC_API:
4303 r = -EINVAL;
4304 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4305 break;
4306
4307 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4308 kvm->arch.x2apic_format = true;
c519265f
RK		 4309 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4310 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4311
4312 r = 0;
4313 break;
4d5422ce
WL		 4314 case KVM_CAP_X86_DISABLE_EXITS:
4315 r = -EINVAL;
4316 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4317 break;
4318
4319 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4320 kvm_can_mwait_in_guest())
4321 kvm->arch.mwait_in_guest = true;
766d3571 4322 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4323 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4324 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4325 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4326 r = 0;
4327 break;
90de4a18
NA		 4328 default:
4329 r = -EINVAL;
4330 break;
4331 }
4332 return r;
4333}
4334
1fe779f8
CO		 4335long kvm_arch_vm_ioctl(struct file *filp,
4336 unsigned int ioctl, unsigned long arg)
4337{
4338 struct kvm *kvm = filp->private_data;
4339 void __user *argp = (void __user *)arg;
367e1319 4340 int r = -ENOTTY;
f0d66275
DH		 4341 /*
4342 * This union makes it completely explicit to gcc-3.x
4343 * that these two variables' stack usage should be
4344 * combined, not added together.
4345 */
4346 union {
4347 struct kvm_pit_state ps;
e9f42757 4348 struct kvm_pit_state2 ps2;
c5ff41ce 4349 struct kvm_pit_config pit_config;
f0d66275 4350 } u;
1fe779f8
CO		 4351
4352 switch (ioctl) {
4353 case KVM_SET_TSS_ADDR:
4354 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4355 break;
b927a3ce
SY		 4356 case KVM_SET_IDENTITY_MAP_ADDR: {
4357 u64 ident_addr;
4358
1af1ac91
DH		 4359 mutex_lock(&kvm->lock);
4360 r = -EINVAL;
4361 if (kvm->created_vcpus)
4362 goto set_identity_unlock;
b927a3ce
SY		 4363 r = -EFAULT;
4364 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4365 goto set_identity_unlock;
b927a3ce 4366 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4367set_identity_unlock:
4368 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4369 break;
4370 }
1fe779f8
CO		 4371 case KVM_SET_NR_MMU_PAGES:
4372 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4373 break;
4374 case KVM_GET_NR_MMU_PAGES:
4375 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4376 break;
3ddea128 4377 case KVM_CREATE_IRQCHIP: {
3ddea128 4378 mutex_lock(&kvm->lock);
09941366 4379
3ddea128 4380 r = -EEXIST;
35e6eaa3 4381 if (irqchip_in_kernel(kvm))
3ddea128 4382 goto create_irqchip_unlock;
09941366 4383
3e515705 4384 r = -EINVAL;
557abc40 4385 if (kvm->created_vcpus)
3e515705 4386 goto create_irqchip_unlock;
09941366
RK		 4387
4388 r = kvm_pic_init(kvm);
4389 if (r)
3ddea128 4390 goto create_irqchip_unlock;
09941366
RK		 4391
4392 r = kvm_ioapic_init(kvm);
4393 if (r) {
09941366 4394 kvm_pic_destroy(kvm);
3ddea128 4395 goto create_irqchip_unlock;
09941366
RK		 4396 }
4397
399ec807
AK		 4398 r = kvm_setup_default_irq_routing(kvm);
4399 if (r) {
72bb2fcd 4400 kvm_ioapic_destroy(kvm);
09941366 4401 kvm_pic_destroy(kvm);
71ba994c 4402 goto create_irqchip_unlock;
399ec807 4403 }
49776faf 4404 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4405 smp_wmb();
49776faf 4406 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4407 create_irqchip_unlock:
4408 mutex_unlock(&kvm->lock);
1fe779f8 4409 break;
3ddea128 4410 }
7837699f 4411 case KVM_CREATE_PIT:
c5ff41ce
JK		 4412 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4413 goto create_pit;
4414 case KVM_CREATE_PIT2:
4415 r = -EFAULT;
4416 if (copy_from_user(&u.pit_config, argp,
4417 sizeof(struct kvm_pit_config)))
4418 goto out;
4419 create_pit:
250715a6 4420 mutex_lock(&kvm->lock);
269e05e4
AK		 4421 r = -EEXIST;
4422 if (kvm->arch.vpit)
4423 goto create_pit_unlock;
7837699f 4424 r = -ENOMEM;
c5ff41ce 4425 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4426 if (kvm->arch.vpit)
4427 r = 0;
269e05e4 4428 create_pit_unlock:
250715a6 4429 mutex_unlock(&kvm->lock);
7837699f 4430 break;
1fe779f8
CO		 4431 case KVM_GET_IRQCHIP: {
4432 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4433 struct kvm_irqchip *chip;
1fe779f8 4434
ff5c2c03
SL		 4435 chip = memdup_user(argp, sizeof(*chip));
4436 if (IS_ERR(chip)) {
4437 r = PTR_ERR(chip);
1fe779f8 4438 goto out;
ff5c2c03
SL		 4439 }
4440
1fe779f8 4441 r = -ENXIO;
826da321 4442 if (!irqchip_kernel(kvm))
f0d66275
DH		 4443 goto get_irqchip_out;
4444 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4445 if (r)
f0d66275 4446 goto get_irqchip_out;
1fe779f8 4447 r = -EFAULT;
f0d66275
DH		 4448 if (copy_to_user(argp, chip, sizeof *chip))
4449 goto get_irqchip_out;
1fe779f8 4450 r = 0;
f0d66275
DH		 4451 get_irqchip_out:
4452 kfree(chip);
1fe779f8
CO		 4453 break;
4454 }
4455 case KVM_SET_IRQCHIP: {
4456 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4457 struct kvm_irqchip *chip;
1fe779f8 4458
ff5c2c03
SL		 4459 chip = memdup_user(argp, sizeof(*chip));
4460 if (IS_ERR(chip)) {
4461 r = PTR_ERR(chip);
1fe779f8 4462 goto out;
ff5c2c03
SL		 4463 }
4464
1fe779f8 4465 r = -ENXIO;
826da321 4466 if (!irqchip_kernel(kvm))
f0d66275
DH		 4467 goto set_irqchip_out;
4468 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4469 if (r)
f0d66275 4470 goto set_irqchip_out;
1fe779f8 4471 r = 0;
f0d66275
DH		 4472 set_irqchip_out:
4473 kfree(chip);
1fe779f8
CO		 4474 break;
4475 }
e0f63cb9 4476 case KVM_GET_PIT: {
e0f63cb9 4477 r = -EFAULT;
f0d66275 4478 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4479 goto out;
4480 r = -ENXIO;
4481 if (!kvm->arch.vpit)
4482 goto out;
f0d66275 4483 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4484 if (r)
4485 goto out;
4486 r = -EFAULT;
f0d66275 4487 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4488 goto out;
4489 r = 0;
4490 break;
4491 }
4492 case KVM_SET_PIT: {
e0f63cb9 4493 r = -EFAULT;
f0d66275 4494 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4495 goto out;
4496 r = -ENXIO;
4497 if (!kvm->arch.vpit)
4498 goto out;
f0d66275 4499 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4500 break;
4501 }
e9f42757
BK		 4502 case KVM_GET_PIT2: {
4503 r = -ENXIO;
4504 if (!kvm->arch.vpit)
4505 goto out;
4506 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4507 if (r)
4508 goto out;
4509 r = -EFAULT;
4510 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4511 goto out;
4512 r = 0;
4513 break;
4514 }
4515 case KVM_SET_PIT2: {
4516 r = -EFAULT;
4517 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4518 goto out;
4519 r = -ENXIO;
4520 if (!kvm->arch.vpit)
4521 goto out;
4522 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4523 break;
4524 }
52d939a0
MT		 4525 case KVM_REINJECT_CONTROL: {
4526 struct kvm_reinject_control control;
4527 r = -EFAULT;
4528 if (copy_from_user(&control, argp, sizeof(control)))
4529 goto out;
4530 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4531 break;
4532 }
d71ba788
PB		 4533 case KVM_SET_BOOT_CPU_ID:
4534 r = 0;
4535 mutex_lock(&kvm->lock);
557abc40 4536 if (kvm->created_vcpus)
d71ba788
PB		 4537 r = -EBUSY;
4538 else
4539 kvm->arch.bsp_vcpu_id = arg;
4540 mutex_unlock(&kvm->lock);
4541 break;
ffde22ac 4542 case KVM_XEN_HVM_CONFIG: {
51776043 4543 struct kvm_xen_hvm_config xhc;
ffde22ac 4544 r = -EFAULT;
51776043 4545 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4546 goto out;
4547 r = -EINVAL;
51776043 4548 if (xhc.flags)
ffde22ac 4549 goto out;
51776043 4550 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4551 r = 0;
4552 break;
4553 }
afbcf7ab 4554 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4555 struct kvm_clock_data user_ns;
4556 u64 now_ns;
afbcf7ab
GC		 4557
4558 r = -EFAULT;
4559 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4560 goto out;
4561
4562 r = -EINVAL;
4563 if (user_ns.flags)
4564 goto out;
4565
4566 r = 0;
0bc48bea
RK		 4567 /*
4568 * TODO: userspace has to take care of races with VCPU_RUN, so
4569 * kvm_gen_update_masterclock() can be cut down to locked
4570 * pvclock_update_vm_gtod_copy().
4571 */
4572 kvm_gen_update_masterclock(kvm);
e891a32e 4573 now_ns = get_kvmclock_ns(kvm);
108b249c 4574 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4575 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4576 break;
4577 }
4578 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4579 struct kvm_clock_data user_ns;
4580 u64 now_ns;
4581
e891a32e 4582 now_ns = get_kvmclock_ns(kvm);
108b249c 4583 user_ns.clock = now_ns;
e3fd9a93 4584 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4585 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4586
4587 r = -EFAULT;
4588 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4589 goto out;
4590 r = 0;
4591 break;
4592 }
90de4a18
NA		 4593 case KVM_ENABLE_CAP: {
4594 struct kvm_enable_cap cap;
afbcf7ab 4595
90de4a18
NA		 4596 r = -EFAULT;
4597 if (copy_from_user(&cap, argp, sizeof(cap)))
4598 goto out;
4599 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4600 break;
4601 }
5acc5c06
BS		 4602 case KVM_MEMORY_ENCRYPT_OP: {
4603 r = -ENOTTY;
4604 if (kvm_x86_ops->mem_enc_op)
4605 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4606 break;
4607 }
69eaedee
BS		 4608 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4609 struct kvm_enc_region region;
4610
4611 r = -EFAULT;
4612 if (copy_from_user(&region, argp, sizeof(region)))
4613 goto out;
4614
4615 r = -ENOTTY;
4616 if (kvm_x86_ops->mem_enc_reg_region)
4617 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4618 break;
4619 }
4620 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4621 struct kvm_enc_region region;
4622
4623 r = -EFAULT;
4624 if (copy_from_user(&region, argp, sizeof(region)))
4625 goto out;
4626
4627 r = -ENOTTY;
4628 if (kvm_x86_ops->mem_enc_unreg_region)
4629 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4630 break;
4631 }
faeb7833
RK		 4632 case KVM_HYPERV_EVENTFD: {
4633 struct kvm_hyperv_eventfd hvevfd;
4634
4635 r = -EFAULT;
4636 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4637 goto out;
4638 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4639 break;
4640 }
1fe779f8 4641 default:
ad6260da 4642 r = -ENOTTY;
1fe779f8
CO		 4643 }
4644out:
4645 return r;
4646}
4647
a16b043c 4648static void kvm_init_msr_list(void)
043405e1
CO		 4649{
4650 u32 dummy[2];
4651 unsigned i, j;
4652
62ef68bb 4653 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4654 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4655 continue;
93c4adc7
PB		 4656
4657 /*
4658 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4659 * to the guests in some cases.
93c4adc7
PB		 4660 */
4661 switch (msrs_to_save[i]) {
4662 case MSR_IA32_BNDCFGS:
4663 if (!kvm_x86_ops->mpx_supported())
4664 continue;
4665 break;
9dbe6cf9
PB		 4666 case MSR_TSC_AUX:
4667 if (!kvm_x86_ops->rdtscp_supported())
4668 continue;
4669 break;
93c4adc7
PB		 4670 default:
4671 break;
4672 }
4673
043405e1
CO		 4674 if (j < i)
4675 msrs_to_save[j] = msrs_to_save[i];
4676 j++;
4677 }
4678 num_msrs_to_save = j;
62ef68bb
PB		 4679
4680 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4681 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4682 continue;
62ef68bb
PB		 4683
4684 if (j < i)
4685 emulated_msrs[j] = emulated_msrs[i];
4686 j++;
4687 }
4688 num_emulated_msrs = j;
801e459a
TL		 4689
4690 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4691 struct kvm_msr_entry msr;
4692
4693 msr.index = msr_based_features[i];
66421c1e 4694 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4695 continue;
4696
4697 if (j < i)
4698 msr_based_features[j] = msr_based_features[i];
4699 j++;
4700 }
4701 num_msr_based_features = j;
043405e1
CO		 4702}
4703
bda9020e
MT		 4704static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4705 const void *v)
bbd9b64e 4706{
70252a10
AK		 4707 int handled = 0;
4708 int n;
4709
4710 do {
4711 n = min(len, 8);
bce87cce 4712 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4713 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4714 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4715 break;
4716 handled += n;
4717 addr += n;
4718 len -= n;
4719 v += n;
4720 } while (len);
bbd9b64e 4721
70252a10 4722 return handled;
bbd9b64e
CO		 4723}
4724
bda9020e 4725static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4726{
70252a10
AK		 4727 int handled = 0;
4728 int n;
4729
4730 do {
4731 n = min(len, 8);
bce87cce 4732 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4733 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4734 addr, n, v))
4735 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4736 break;
e39d200f 4737 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4738 handled += n;
4739 addr += n;
4740 len -= n;
4741 v += n;
4742 } while (len);
bbd9b64e 4743
70252a10 4744 return handled;
bbd9b64e
CO		 4745}
4746
2dafc6c2
GN		 4747static void kvm_set_segment(struct kvm_vcpu *vcpu,
4748 struct kvm_segment *var, int seg)
4749{
4750 kvm_x86_ops->set_segment(vcpu, var, seg);
4751}
4752
4753void kvm_get_segment(struct kvm_vcpu *vcpu,
4754 struct kvm_segment *var, int seg)
4755{
4756 kvm_x86_ops->get_segment(vcpu, var, seg);
4757}
4758
54987b7a
PB		 4759gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4760 struct x86_exception *exception)
02f59dc9
JR		 4761{
4762 gpa_t t_gpa;
02f59dc9
JR		 4763
4764 BUG_ON(!mmu_is_nested(vcpu));
4765
4766 /* NPT walks are always user-walks */
4767 access |= PFERR_USER_MASK;
54987b7a 4768 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4769
4770 return t_gpa;
4771}
4772
ab9ae313
AK		 4773gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4774 struct x86_exception *exception)
1871c602
GN		 4775{
4776 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4777 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4778}
4779
ab9ae313
AK		 4780 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4781 struct x86_exception *exception)
1871c602
GN		 4782{
4783 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4784 access |= PFERR_FETCH_MASK;
ab9ae313 4785 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4786}
4787
ab9ae313
AK		 4788gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4789 struct x86_exception *exception)
1871c602
GN		 4790{
4791 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4792 access |= PFERR_WRITE_MASK;
ab9ae313 4793 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4794}
4795
4796/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4797gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4798 struct x86_exception *exception)
1871c602 4799{
ab9ae313 4800 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4801}
4802
4803static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4804 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4805 struct x86_exception *exception)
bbd9b64e
CO		 4806{
4807 void *data = val;
10589a46 4808 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4809
4810 while (bytes) {
14dfe855 4811 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4812 exception);
bbd9b64e 4813 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4814 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4815 int ret;
4816
bcc55cba 4817 if (gpa == UNMAPPED_GVA)
ab9ae313 4818 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4819 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4820 offset, toread);
10589a46 4821 if (ret < 0) {
c3cd7ffa 4822 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4823 goto out;
4824 }
bbd9b64e 4825
77c2002e
IE		 4826 bytes -= toread;
4827 data += toread;
4828 addr += toread;
bbd9b64e 4829 }
10589a46 4830out:
10589a46 4831 return r;
bbd9b64e 4832}
77c2002e 4833
1871c602 4834/* used for instruction fetching */
0f65dd70
AK		 4835static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4836 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4837 struct x86_exception *exception)
1871c602 4838{
0f65dd70 4839 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4840 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4841 unsigned offset;
4842 int ret;
0f65dd70 4843
44583cba
PB		 4844 /* Inline kvm_read_guest_virt_helper for speed. */
4845 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4846 exception);
4847 if (unlikely(gpa == UNMAPPED_GVA))
4848 return X86EMUL_PROPAGATE_FAULT;
4849
4850 offset = addr & (PAGE_SIZE-1);
4851 if (WARN_ON(offset + bytes > PAGE_SIZE))
4852 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4853 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4854 offset, bytes);
44583cba
PB		 4855 if (unlikely(ret < 0))
4856 return X86EMUL_IO_NEEDED;
4857
4858 return X86EMUL_CONTINUE;
1871c602
GN		 4859}
4860
ce14e868 4861int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 4862 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4863 struct x86_exception *exception)
1871c602
GN		 4864{
4865 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4866
1871c602 4867 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4868 exception);
1871c602 4869}
064aea77 4870EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4871
ce14e868
PB		 4872static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
4873 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 4874 struct x86_exception *exception, bool system)
1871c602 4875{
0f65dd70 4876 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 4877 u32 access = 0;
4878
4879 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4880 access |= PFERR_USER_MASK;
4881
4882 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 4883}
4884
7a036a6f
RK		 4885static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4886 unsigned long addr, void *val, unsigned int bytes)
4887{
4888 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4889 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4890
4891 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4892}
4893
ce14e868
PB		 4894static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4895 struct kvm_vcpu *vcpu, u32 access,
4896 struct x86_exception *exception)
77c2002e
IE		 4897{
4898 void *data = val;
4899 int r = X86EMUL_CONTINUE;
4900
4901 while (bytes) {
14dfe855 4902 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 4903 access,
ab9ae313 4904 exception);
77c2002e
IE		 4905 unsigned offset = addr & (PAGE_SIZE-1);
4906 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4907 int ret;
4908
bcc55cba 4909 if (gpa == UNMAPPED_GVA)
ab9ae313 4910 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4911 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4912 if (ret < 0) {
c3cd7ffa 4913 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4914 goto out;
4915 }
4916
4917 bytes -= towrite;
4918 data += towrite;
4919 addr += towrite;
4920 }
4921out:
4922 return r;
4923}
ce14e868
PB		 4924
4925static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 4926 unsigned int bytes, struct x86_exception *exception,
4927 bool system)
ce14e868
PB		 4928{
4929 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 4930 u32 access = PFERR_WRITE_MASK;
4931
4932 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4933 access |= PFERR_USER_MASK;
ce14e868
PB		 4934
4935 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 4936 access, exception);
ce14e868
PB		 4937}
4938
4939int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
4940 unsigned int bytes, struct x86_exception *exception)
4941{
4942 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4943 PFERR_WRITE_MASK, exception);
4944}
6a4d7550 4945EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4946
082d06ed
WL		 4947int handle_ud(struct kvm_vcpu *vcpu)
4948{
6c86eedc 4949 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 4950 enum emulation_result er;
6c86eedc
WL		 4951 char sig[5]; /* ud2; .ascii "kvm" */
4952 struct x86_exception e;
4953
4954 if (force_emulation_prefix &&
3c9fa24c
PB		 4955 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
4956 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 4957 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
4958 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
4959 emul_type = 0;
4960 }
082d06ed 4961
6c86eedc 4962 er = emulate_instruction(vcpu, emul_type);
082d06ed
WL		 4963 if (er == EMULATE_USER_EXIT)
4964 return 0;
4965 if (er != EMULATE_DONE)
4966 kvm_queue_exception(vcpu, UD_VECTOR);
4967 return 1;
4968}
4969EXPORT_SYMBOL_GPL(handle_ud);
4970
0f89b207
TL		 4971static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4972 gpa_t gpa, bool write)
4973{
4974 /* For APIC access vmexit */
4975 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4976 return 1;
4977
4978 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4979 trace_vcpu_match_mmio(gva, gpa, write, true);
4980 return 1;
4981 }
4982
4983 return 0;
4984}
4985
af7cc7d1
XG		 4986static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4987 gpa_t *gpa, struct x86_exception *exception,
4988 bool write)
4989{
97d64b78
AK		 4990 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4991 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4992
be94f6b7
HH		 4993 /*
4994 * currently PKRU is only applied to ept enabled guest so
4995 * there is no pkey in EPT page table for L1 guest or EPT
4996 * shadow page table for L2 guest.
4997 */
97d64b78 4998 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4999 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5000 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5001 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5002 (gva & (PAGE_SIZE - 1));
4f022648 5003 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5004 return 1;
5005 }
5006
af7cc7d1
XG		 5007 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5008
5009 if (*gpa == UNMAPPED_GVA)
5010 return -1;
5011
0f89b207 5012 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5013}
5014
3200f405 5015int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5016 const void *val, int bytes)
bbd9b64e
CO		 5017{
5018 int ret;
5019
54bf36aa 5020 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5021 if (ret < 0)
bbd9b64e 5022 return 0;
0eb05bf2 5023 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5024 return 1;
5025}
5026
77d197b2
XG		 5027struct read_write_emulator_ops {
5028 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5029 int bytes);
5030 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5031 void *val, int bytes);
5032 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5033 int bytes, void *val);
5034 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5035 void *val, int bytes);
5036 bool write;
5037};
5038
5039static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5040{
5041 if (vcpu->mmio_read_completed) {
77d197b2 5042 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5043 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5044 vcpu->mmio_read_completed = 0;
5045 return 1;
5046 }
5047
5048 return 0;
5049}
5050
5051static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5052 void *val, int bytes)
5053{
54bf36aa 5054 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5055}
5056
5057static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5058 void *val, int bytes)
5059{
5060 return emulator_write_phys(vcpu, gpa, val, bytes);
5061}
5062
5063static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5064{
e39d200f 5065 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5066 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5067}
5068
5069static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5070 void *val, int bytes)
5071{
e39d200f 5072 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5073 return X86EMUL_IO_NEEDED;
5074}
5075
5076static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5077 void *val, int bytes)
5078{
f78146b0
AK		 5079 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5080
87da7e66 5081 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5082 return X86EMUL_CONTINUE;
5083}
5084
0fbe9b0b 5085static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5086 .read_write_prepare = read_prepare,
5087 .read_write_emulate = read_emulate,
5088 .read_write_mmio = vcpu_mmio_read,
5089 .read_write_exit_mmio = read_exit_mmio,
5090};
5091
0fbe9b0b 5092static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5093 .read_write_emulate = write_emulate,
5094 .read_write_mmio = write_mmio,
5095 .read_write_exit_mmio = write_exit_mmio,
5096 .write = true,
5097};
5098
22388a3c
XG		 5099static int emulator_read_write_onepage(unsigned long addr, void *val,
5100 unsigned int bytes,
5101 struct x86_exception *exception,
5102 struct kvm_vcpu *vcpu,
0fbe9b0b 5103 const struct read_write_emulator_ops *ops)
bbd9b64e 5104{
af7cc7d1
XG		 5105 gpa_t gpa;
5106 int handled, ret;
22388a3c 5107 bool write = ops->write;
f78146b0 5108 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5109 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5110
5111 /*
5112 * If the exit was due to a NPF we may already have a GPA.
5113 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5114 * Note, this cannot be used on string operations since string
5115 * operation using rep will only have the initial GPA from the NPF
5116 * occurred.
5117 */
5118 if (vcpu->arch.gpa_available &&
5119 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5120 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5121 gpa = vcpu->arch.gpa_val;
5122 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5123 } else {
5124 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5125 if (ret < 0)
5126 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5127 }
10589a46 5128
618232e2 5129 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5130 return X86EMUL_CONTINUE;
5131
bbd9b64e
CO		 5132 /*
5133 * Is this MMIO handled locally?
5134 */
22388a3c 5135 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5136 if (handled == bytes)
bbd9b64e 5137 return X86EMUL_CONTINUE;
bbd9b64e 5138
70252a10
AK		 5139 gpa += handled;
5140 bytes -= handled;
5141 val += handled;
5142
87da7e66
XG		 5143 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5144 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5145 frag->gpa = gpa;
5146 frag->data = val;
5147 frag->len = bytes;
f78146b0 5148 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5149}
5150
52eb5a6d
XL		 5151static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5152 unsigned long addr,
22388a3c
XG		 5153 void *val, unsigned int bytes,
5154 struct x86_exception *exception,
0fbe9b0b 5155 const struct read_write_emulator_ops *ops)
bbd9b64e 5156{
0f65dd70 5157 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5158 gpa_t gpa;
5159 int rc;
5160
5161 if (ops->read_write_prepare &&
5162 ops->read_write_prepare(vcpu, val, bytes))
5163 return X86EMUL_CONTINUE;
5164
5165 vcpu->mmio_nr_fragments = 0;
0f65dd70 5166
bbd9b64e
CO		 5167 /* Crossing a page boundary? */
5168 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5169 int now;
bbd9b64e
CO		 5170
5171 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5172 rc = emulator_read_write_onepage(addr, val, now, exception,
5173 vcpu, ops);
5174
bbd9b64e
CO		 5175 if (rc != X86EMUL_CONTINUE)
5176 return rc;
5177 addr += now;
bac15531
NA		 5178 if (ctxt->mode != X86EMUL_MODE_PROT64)
5179 addr = (u32)addr;
bbd9b64e
CO		 5180 val += now;
5181 bytes -= now;
5182 }
22388a3c 5183
f78146b0
AK		 5184 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5185 vcpu, ops);
5186 if (rc != X86EMUL_CONTINUE)
5187 return rc;
5188
5189 if (!vcpu->mmio_nr_fragments)
5190 return rc;
5191
5192 gpa = vcpu->mmio_fragments[0].gpa;
5193
5194 vcpu->mmio_needed = 1;
5195 vcpu->mmio_cur_fragment = 0;
5196
87da7e66 5197 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5198 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5199 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5200 vcpu->run->mmio.phys_addr = gpa;
5201
5202 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5203}
5204
5205static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5206 unsigned long addr,
5207 void *val,
5208 unsigned int bytes,
5209 struct x86_exception *exception)
5210{
5211 return emulator_read_write(ctxt, addr, val, bytes,
5212 exception, &read_emultor);
5213}
5214
52eb5a6d 5215static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5216 unsigned long addr,
5217 const void *val,
5218 unsigned int bytes,
5219 struct x86_exception *exception)
5220{
5221 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5222 exception, &write_emultor);
bbd9b64e 5223}
bbd9b64e 5224
daea3e73
AK		 5225#define CMPXCHG_TYPE(t, ptr, old, new) \
5226 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5227
5228#ifdef CONFIG_X86_64
5229# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5230#else
5231# define CMPXCHG64(ptr, old, new) \
9749a6c0 5232 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5233#endif
5234
0f65dd70
AK		 5235static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5236 unsigned long addr,
bbd9b64e
CO		 5237 const void *old,
5238 const void *new,
5239 unsigned int bytes,
0f65dd70 5240 struct x86_exception *exception)
bbd9b64e 5241{
0f65dd70 5242 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5243 gpa_t gpa;
5244 struct page *page;
5245 char *kaddr;
5246 bool exchanged;
2bacc55c 5247
daea3e73
AK		 5248 /* guests cmpxchg8b have to be emulated atomically */
5249 if (bytes > 8 || (bytes & (bytes - 1)))
5250 goto emul_write;
10589a46 5251
daea3e73 5252 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5253
daea3e73
AK		 5254 if (gpa == UNMAPPED_GVA ||
5255 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5256 goto emul_write;
2bacc55c 5257
daea3e73
AK		 5258 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5259 goto emul_write;
72dc67a6 5260
54bf36aa 5261 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5262 if (is_error_page(page))
c19b8bd6 5263 goto emul_write;
72dc67a6 5264
8fd75e12 5265 kaddr = kmap_atomic(page);
daea3e73
AK		 5266 kaddr += offset_in_page(gpa);
5267 switch (bytes) {
5268 case 1:
5269 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5270 break;
5271 case 2:
5272 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5273 break;
5274 case 4:
5275 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5276 break;
5277 case 8:
5278 exchanged = CMPXCHG64(kaddr, old, new);
5279 break;
5280 default:
5281 BUG();
2bacc55c 5282 }
8fd75e12 5283 kunmap_atomic(kaddr);
daea3e73
AK		 5284 kvm_release_page_dirty(page);
5285
5286 if (!exchanged)
5287 return X86EMUL_CMPXCHG_FAILED;
5288
54bf36aa 5289 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5290 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5291
5292 return X86EMUL_CONTINUE;
4a5f48f6 5293
3200f405 5294emul_write:
daea3e73 5295 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5296
0f65dd70 5297 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5298}
5299
cf8f70bf
GN		 5300static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5301{
cbfc6c91 5302 int r = 0, i;
cf8f70bf 5303
cbfc6c91
WL		 5304 for (i = 0; i < vcpu->arch.pio.count; i++) {
5305 if (vcpu->arch.pio.in)
5306 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5307 vcpu->arch.pio.size, pd);
5308 else
5309 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5310 vcpu->arch.pio.port, vcpu->arch.pio.size,
5311 pd);
5312 if (r)
5313 break;
5314 pd += vcpu->arch.pio.size;
5315 }
cf8f70bf
GN		 5316 return r;
5317}
5318
6f6fbe98
XG		 5319static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5320 unsigned short port, void *val,
5321 unsigned int count, bool in)
cf8f70bf 5322{
cf8f70bf 5323 vcpu->arch.pio.port = port;
6f6fbe98 5324 vcpu->arch.pio.in = in;
7972995b 5325 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5326 vcpu->arch.pio.size = size;
5327
5328 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5329 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5330 return 1;
5331 }
5332
5333 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5334 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5335 vcpu->run->io.size = size;
5336 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5337 vcpu->run->io.count = count;
5338 vcpu->run->io.port = port;
5339
5340 return 0;
5341}
5342
6f6fbe98
XG		 5343static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5344 int size, unsigned short port, void *val,
5345 unsigned int count)
cf8f70bf 5346{
ca1d4a9e 5347 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5348 int ret;
ca1d4a9e 5349
6f6fbe98
XG		 5350 if (vcpu->arch.pio.count)
5351 goto data_avail;
cf8f70bf 5352
cbfc6c91
WL		 5353 memset(vcpu->arch.pio_data, 0, size * count);
5354
6f6fbe98
XG		 5355 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5356 if (ret) {
5357data_avail:
5358 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5359 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5360 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5361 return 1;
5362 }
5363
cf8f70bf
GN		 5364 return 0;
5365}
5366
6f6fbe98
XG		 5367static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5368 int size, unsigned short port,
5369 const void *val, unsigned int count)
5370{
5371 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5372
5373 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5374 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5375 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5376}
5377
bbd9b64e
CO		 5378static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5379{
5380 return kvm_x86_ops->get_segment_base(vcpu, seg);
5381}
5382
3cb16fe7 5383static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5384{
3cb16fe7 5385 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5386}
5387
ae6a2375 5388static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5389{
5390 if (!need_emulate_wbinvd(vcpu))
5391 return X86EMUL_CONTINUE;
5392
5393 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5394 int cpu = get_cpu();
5395
5396 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5397 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5398 wbinvd_ipi, NULL, 1);
2eec7343 5399 put_cpu();
f5f48ee1 5400 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5401 } else
5402 wbinvd();
f5f48ee1
SY		 5403 return X86EMUL_CONTINUE;
5404}
5cb56059
JS		 5405
5406int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5407{
6affcbed
KH		 5408 kvm_emulate_wbinvd_noskip(vcpu);
5409 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5410}
f5f48ee1
SY		 5411EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5412
5cb56059
JS		 5413
5414
bcaf5cc5
AK		 5415static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5416{
5cb56059 5417 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5418}
5419
52eb5a6d
XL		 5420static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5421 unsigned long *dest)
bbd9b64e 5422{
16f8a6f9 5423 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5424}
5425
52eb5a6d
XL		 5426static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5427 unsigned long value)
bbd9b64e 5428{
338dbc97 5429
717746e3 5430 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5431}
5432
52a46617 5433static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5434{
52a46617 5435 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5436}
5437
717746e3 5438static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5439{
717746e3 5440 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5441 unsigned long value;
5442
5443 switch (cr) {
5444 case 0:
5445 value = kvm_read_cr0(vcpu);
5446 break;
5447 case 2:
5448 value = vcpu->arch.cr2;
5449 break;
5450 case 3:
9f8fe504 5451 value = kvm_read_cr3(vcpu);
52a46617
GN		 5452 break;
5453 case 4:
5454 value = kvm_read_cr4(vcpu);
5455 break;
5456 case 8:
5457 value = kvm_get_cr8(vcpu);
5458 break;
5459 default:
a737f256 5460 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5461 return 0;
5462 }
5463
5464 return value;
5465}
5466
717746e3 5467static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5468{
717746e3 5469 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5470 int res = 0;
5471
52a46617
GN		 5472 switch (cr) {
5473 case 0:
49a9b07e 5474 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5475 break;
5476 case 2:
5477 vcpu->arch.cr2 = val;
5478 break;
5479 case 3:
2390218b 5480 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5481 break;
5482 case 4:
a83b29c6 5483 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5484 break;
5485 case 8:
eea1cff9 5486 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5487 break;
5488 default:
a737f256 5489 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5490 res = -1;
52a46617 5491 }
0f12244f
GN		 5492
5493 return res;
52a46617
GN		 5494}
5495
717746e3 5496static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5497{
717746e3 5498 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5499}
5500
4bff1e86 5501static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5502{
4bff1e86 5503 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5504}
5505
4bff1e86 5506static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5507{
4bff1e86 5508 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5509}
5510
1ac9d0cf
AK		 5511static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5512{
5513 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5514}
5515
5516static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5517{
5518 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5519}
5520
4bff1e86
AK		 5521static unsigned long emulator_get_cached_segment_base(
5522 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5523{
4bff1e86 5524 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5525}
5526
1aa36616
AK		 5527static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5528 struct desc_struct *desc, u32 *base3,
5529 int seg)
2dafc6c2
GN		 5530{
5531 struct kvm_segment var;
5532
4bff1e86 5533 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5534 *selector = var.selector;
2dafc6c2 5535
378a8b09
GN		 5536 if (var.unusable) {
5537 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5538 if (base3)
5539 *base3 = 0;
2dafc6c2 5540 return false;
378a8b09 5541 }
2dafc6c2
GN		 5542
5543 if (var.g)
5544 var.limit >>= 12;
5545 set_desc_limit(desc, var.limit);
5546 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5547#ifdef CONFIG_X86_64
5548 if (base3)
5549 *base3 = var.base >> 32;
5550#endif
2dafc6c2
GN		 5551 desc->type = var.type;
5552 desc->s = var.s;
5553 desc->dpl = var.dpl;
5554 desc->p = var.present;
5555 desc->avl = var.avl;
5556 desc->l = var.l;
5557 desc->d = var.db;
5558 desc->g = var.g;
5559
5560 return true;
5561}
5562
1aa36616
AK		 5563static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5564 struct desc_struct *desc, u32 base3,
5565 int seg)
2dafc6c2 5566{
4bff1e86 5567 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5568 struct kvm_segment var;
5569
1aa36616 5570 var.selector = selector;
2dafc6c2 5571 var.base = get_desc_base(desc);
5601d05b
GN		 5572#ifdef CONFIG_X86_64
5573 var.base |= ((u64)base3) << 32;
5574#endif
2dafc6c2
GN		 5575 var.limit = get_desc_limit(desc);
5576 if (desc->g)
5577 var.limit = (var.limit << 12) | 0xfff;
5578 var.type = desc->type;
2dafc6c2
GN		 5579 var.dpl = desc->dpl;
5580 var.db = desc->d;
5581 var.s = desc->s;
5582 var.l = desc->l;
5583 var.g = desc->g;
5584 var.avl = desc->avl;
5585 var.present = desc->p;
5586 var.unusable = !var.present;
5587 var.padding = 0;
5588
5589 kvm_set_segment(vcpu, &var, seg);
5590 return;
5591}
5592
717746e3
AK		 5593static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5594 u32 msr_index, u64 *pdata)
5595{
609e36d3
PB		 5596 struct msr_data msr;
5597 int r;
5598
5599 msr.index = msr_index;
5600 msr.host_initiated = false;
5601 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5602 if (r)
5603 return r;
5604
5605 *pdata = msr.data;
5606 return 0;
717746e3
AK		 5607}
5608
5609static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5610 u32 msr_index, u64 data)
5611{
8fe8ab46
WA		 5612 struct msr_data msr;
5613
5614 msr.data = data;
5615 msr.index = msr_index;
5616 msr.host_initiated = false;
5617 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5618}
5619
64d60670
PB		 5620static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5621{
5622 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5623
5624 return vcpu->arch.smbase;
5625}
5626
5627static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5628{
5629 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5630
5631 vcpu->arch.smbase = smbase;
5632}
5633
67f4d428
NA		 5634static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5635 u32 pmc)
5636{
c6702c9d 5637 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5638}
5639
222d21aa
AK		 5640static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5641 u32 pmc, u64 *pdata)
5642{
c6702c9d 5643 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5644}
5645
6c3287f7
AK		 5646static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5647{
5648 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5649}
5650
2953538e 5651static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5652 struct x86_instruction_info *info,
c4f035c6
AK		 5653 enum x86_intercept_stage stage)
5654{
2953538e 5655 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5656}
5657
e911eb3b
YZ		 5658static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5659 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5660{
e911eb3b 5661 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5662}
5663
dd856efa
AK		 5664static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5665{
5666 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5667}
5668
5669static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5670{
5671 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5672}
5673
801806d9
NA		 5674static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5675{
5676 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5677}
5678
6ed071f0
LP		 5679static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5680{
5681 return emul_to_vcpu(ctxt)->arch.hflags;
5682}
5683
5684static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5685{
5686 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5687}
5688
0234bf88
LP		 5689static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5690{
5691 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5692}
5693
0225fb50 5694static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5695 .read_gpr = emulator_read_gpr,
5696 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5697 .read_std = emulator_read_std,
5698 .write_std = emulator_write_std,
7a036a6f 5699 .read_phys = kvm_read_guest_phys_system,
1871c602 5700 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5701 .read_emulated = emulator_read_emulated,
5702 .write_emulated = emulator_write_emulated,
5703 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5704 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5705 .pio_in_emulated = emulator_pio_in_emulated,
5706 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5707 .get_segment = emulator_get_segment,
5708 .set_segment = emulator_set_segment,
5951c442 5709 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5710 .get_gdt = emulator_get_gdt,
160ce1f1 5711 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5712 .set_gdt = emulator_set_gdt,
5713 .set_idt = emulator_set_idt,
52a46617
GN		 5714 .get_cr = emulator_get_cr,
5715 .set_cr = emulator_set_cr,
9c537244 5716 .cpl = emulator_get_cpl,
35aa5375
GN		 5717 .get_dr = emulator_get_dr,
5718 .set_dr = emulator_set_dr,
64d60670
PB		 5719 .get_smbase = emulator_get_smbase,
5720 .set_smbase = emulator_set_smbase,
717746e3
AK		 5721 .set_msr = emulator_set_msr,
5722 .get_msr = emulator_get_msr,
67f4d428 5723 .check_pmc = emulator_check_pmc,
222d21aa 5724 .read_pmc = emulator_read_pmc,
6c3287f7 5725 .halt = emulator_halt,
bcaf5cc5 5726 .wbinvd = emulator_wbinvd,
d6aa1000 5727 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5728 .intercept = emulator_intercept,
bdb42f5a 5729 .get_cpuid = emulator_get_cpuid,
801806d9 5730 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5731 .get_hflags = emulator_get_hflags,
5732 .set_hflags = emulator_set_hflags,
0234bf88 5733 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5734};
5735
95cb2295
GN		 5736static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5737{
37ccdcbe 5738 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5739 /*
5740 * an sti; sti; sequence only disable interrupts for the first
5741 * instruction. So, if the last instruction, be it emulated or
5742 * not, left the system with the INT_STI flag enabled, it
5743 * means that the last instruction is an sti. We should not
5744 * leave the flag on in this case. The same goes for mov ss
5745 */
37ccdcbe
PB		 5746 if (int_shadow & mask)
5747 mask = 0;
6addfc42 5748 if (unlikely(int_shadow || mask)) {
95cb2295 5749 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5750 if (!mask)
5751 kvm_make_request(KVM_REQ_EVENT, vcpu);
5752 }
95cb2295
GN		 5753}
5754
ef54bcfe 5755static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5756{
5757 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5758 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5759 return kvm_propagate_fault(vcpu, &ctxt->exception);
5760
5761 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5762 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5763 ctxt->exception.error_code);
54b8486f 5764 else
da9cb575 5765 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5766 return false;
54b8486f
GN		 5767}
5768
8ec4722d
MG		 5769static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5770{
adf52235 5771 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5772 int cs_db, cs_l;
5773
8ec4722d
MG		 5774 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5775
adf52235 5776 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5777 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5778
adf52235
TY		 5779 ctxt->eip = kvm_rip_read(vcpu);
5780 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5781 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5782 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5783 cs_db ? X86EMUL_MODE_PROT32 :
5784 X86EMUL_MODE_PROT16;
a584539b 5785 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5786 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5787 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5788
dd856efa 5789 init_decode_cache(ctxt);
7ae441ea 5790 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5791}
5792
71f9833b 5793int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5794{
9d74191a 5795 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5796 int ret;
5797
5798 init_emulate_ctxt(vcpu);
5799
9dac77fa
AK		 5800 ctxt->op_bytes = 2;
5801 ctxt->ad_bytes = 2;
5802 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5803 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5804
5805 if (ret != X86EMUL_CONTINUE)
5806 return EMULATE_FAIL;
5807
9dac77fa 5808 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5809 kvm_rip_write(vcpu, ctxt->eip);
5810 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5811
63995653
MG		 5812 return EMULATE_DONE;
5813}
5814EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5815
e2366171 5816static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5817{
fc3a9157
JR		 5818 int r = EMULATE_DONE;
5819
6d77dbfc
GN		 5820 ++vcpu->stat.insn_emulation_fail;
5821 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5822
5823 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5824 return EMULATE_FAIL;
5825
a2b9e6c1 5826 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5827 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5828 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5829 vcpu->run->internal.ndata = 0;
1f4dcb3b 5830 r = EMULATE_USER_EXIT;
fc3a9157 5831 }
e2366171 5832
6d77dbfc 5833 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5834
5835 return r;
6d77dbfc
GN		 5836}
5837
93c05d3e 5838static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5839 bool write_fault_to_shadow_pgtable,
5840 int emulation_type)
a6f177ef 5841{
95b3cf69 5842 gpa_t gpa = cr2;
ba049e93 5843 kvm_pfn_t pfn;
a6f177ef 5844
991eebf9
GN		 5845 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5846 return false;
5847
95b3cf69
XG		 5848 if (!vcpu->arch.mmu.direct_map) {
5849 /*
5850 * Write permission should be allowed since only
5851 * write access need to be emulated.
5852 */
5853 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5854
95b3cf69
XG		 5855 /*
5856 * If the mapping is invalid in guest, let cpu retry
5857 * it to generate fault.
5858 */
5859 if (gpa == UNMAPPED_GVA)
5860 return true;
5861 }
a6f177ef 5862
8e3d9d06
XG		 5863 /*
5864 * Do not retry the unhandleable instruction if it faults on the
5865 * readonly host memory, otherwise it will goto a infinite loop:
5866 * retry instruction -> write #PF -> emulation fail -> retry
5867 * instruction -> ...
5868 */
5869 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5870
5871 /*
5872 * If the instruction failed on the error pfn, it can not be fixed,
5873 * report the error to userspace.
5874 */
5875 if (is_error_noslot_pfn(pfn))
5876 return false;
5877
5878 kvm_release_pfn_clean(pfn);
5879
5880 /* The instructions are well-emulated on direct mmu. */
5881 if (vcpu->arch.mmu.direct_map) {
5882 unsigned int indirect_shadow_pages;
5883
5884 spin_lock(&vcpu->kvm->mmu_lock);
5885 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5886 spin_unlock(&vcpu->kvm->mmu_lock);
5887
5888 if (indirect_shadow_pages)
5889 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5890
a6f177ef 5891 return true;
8e3d9d06 5892 }
a6f177ef 5893
95b3cf69
XG		 5894 /*
5895 * if emulation was due to access to shadowed page table
5896 * and it failed try to unshadow page and re-enter the
5897 * guest to let CPU execute the instruction.
5898 */
5899 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5900
5901 /*
5902 * If the access faults on its page table, it can not
5903 * be fixed by unprotecting shadow page and it should
5904 * be reported to userspace.
5905 */
5906 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5907}
5908
1cb3f3ae
XG		 5909static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5910 unsigned long cr2, int emulation_type)
5911{
5912 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5913 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5914
5915 last_retry_eip = vcpu->arch.last_retry_eip;
5916 last_retry_addr = vcpu->arch.last_retry_addr;
5917
5918 /*
5919 * If the emulation is caused by #PF and it is non-page_table
5920 * writing instruction, it means the VM-EXIT is caused by shadow
5921 * page protected, we can zap the shadow page and retry this
5922 * instruction directly.
5923 *
5924 * Note: if the guest uses a non-page-table modifying instruction
5925 * on the PDE that points to the instruction, then we will unmap
5926 * the instruction and go to an infinite loop. So, we cache the
5927 * last retried eip and the last fault address, if we meet the eip
5928 * and the address again, we can break out of the potential infinite
5929 * loop.
5930 */
5931 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5932
5933 if (!(emulation_type & EMULTYPE_RETRY))
5934 return false;
5935
5936 if (x86_page_table_writing_insn(ctxt))
5937 return false;
5938
5939 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5940 return false;
5941
5942 vcpu->arch.last_retry_eip = ctxt->eip;
5943 vcpu->arch.last_retry_addr = cr2;
5944
5945 if (!vcpu->arch.mmu.direct_map)
5946 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5947
22368028 5948 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5949
5950 return true;
5951}
5952
716d51ab
GN		 5953static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5954static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5955
64d60670 5956static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5957{
64d60670 5958 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5959 /* This is a good place to trace that we are exiting SMM. */
5960 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5961
c43203ca
PB		 5962 /* Process a latched INIT or SMI, if any. */
5963 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5964 }
699023e2
PB		 5965
5966 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5967}
5968
5969static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5970{
5971 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5972
a584539b 5973 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5974
5975 if (changed & HF_SMM_MASK)
5976 kvm_smm_changed(vcpu);
a584539b
PB		 5977}
5978
4a1e10d5
PB		 5979static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5980 unsigned long *db)
5981{
5982 u32 dr6 = 0;
5983 int i;
5984 u32 enable, rwlen;
5985
5986 enable = dr7;
5987 rwlen = dr7 >> 16;
5988 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5989 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5990 dr6 |= (1 << i);
5991 return dr6;
5992}
5993
c8401dda 5994static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5995{
5996 struct kvm_run *kvm_run = vcpu->run;
5997
c8401dda
PB		 5998 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5999 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6000 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6001 kvm_run->debug.arch.exception = DB_VECTOR;
6002 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6003 *r = EMULATE_USER_EXIT;
6004 } else {
6005 /*
6006 * "Certain debug exceptions may clear bit 0-3. The
6007 * remaining contents of the DR6 register are never
6008 * cleared by the processor".
6009 */
6010 vcpu->arch.dr6 &= ~15;
6011 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
6012 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 6013 }
6014}
6015
6affcbed
KH		 6016int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6017{
6018 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6019 int r = EMULATE_DONE;
6020
6021 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6022
6023 /*
6024 * rflags is the old, "raw" value of the flags. The new value has
6025 * not been saved yet.
6026 *
6027 * This is correct even for TF set by the guest, because "the
6028 * processor will not generate this exception after the instruction
6029 * that sets the TF flag".
6030 */
6031 if (unlikely(rflags & X86_EFLAGS_TF))
6032 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6033 return r == EMULATE_DONE;
6034}
6035EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6036
4a1e10d5
PB		 6037static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6038{
4a1e10d5
PB		 6039 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6040 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6041 struct kvm_run *kvm_run = vcpu->run;
6042 unsigned long eip = kvm_get_linear_rip(vcpu);
6043 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6044 vcpu->arch.guest_debug_dr7,
6045 vcpu->arch.eff_db);
6046
6047 if (dr6 != 0) {
6f43ed01 6048 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6049 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6050 kvm_run->debug.arch.exception = DB_VECTOR;
6051 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6052 *r = EMULATE_USER_EXIT;
6053 return true;
6054 }
6055 }
6056
4161a569
NA		 6057 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6058 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6059 unsigned long eip = kvm_get_linear_rip(vcpu);
6060 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6061 vcpu->arch.dr7,
6062 vcpu->arch.db);
6063
6064 if (dr6 != 0) {
6065 vcpu->arch.dr6 &= ~15;
6f43ed01 6066 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6067 kvm_queue_exception(vcpu, DB_VECTOR);
6068 *r = EMULATE_DONE;
6069 return true;
6070 }
6071 }
6072
6073 return false;
6074}
6075
04789b66
LA		 6076static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6077{
2d7921c4
AM		 6078 switch (ctxt->opcode_len) {
6079 case 1:
6080 switch (ctxt->b) {
6081 case 0xe4: /* IN */
6082 case 0xe5:
6083 case 0xec:
6084 case 0xed:
6085 case 0xe6: /* OUT */
6086 case 0xe7:
6087 case 0xee:
6088 case 0xef:
6089 case 0x6c: /* INS */
6090 case 0x6d:
6091 case 0x6e: /* OUTS */
6092 case 0x6f:
6093 return true;
6094 }
6095 break;
6096 case 2:
6097 switch (ctxt->b) {
6098 case 0x33: /* RDPMC */
6099 return true;
6100 }
6101 break;
04789b66
LA		 6102 }
6103
6104 return false;
6105}
6106
51d8b661
AP		 6107int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6108 unsigned long cr2,
dc25e89e
AP		 6109 int emulation_type,
6110 void *insn,
6111 int insn_len)
bbd9b64e 6112{
95cb2295 6113 int r;
9d74191a 6114 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6115 bool writeback = true;
93c05d3e 6116 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6117
93c05d3e
XG		 6118 /*
6119 * Clear write_fault_to_shadow_pgtable here to ensure it is
6120 * never reused.
6121 */
6122 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6123 kvm_clear_exception_queue(vcpu);
8d7d8102 6124
571008da 6125 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6126 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6127
6128 /*
6129 * We will reenter on the same instruction since
6130 * we do not set complete_userspace_io. This does not
6131 * handle watchpoints yet, those would be handled in
6132 * the emulate_ops.
6133 */
d391f120
VK		 6134 if (!(emulation_type & EMULTYPE_SKIP) &&
6135 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6136 return r;
6137
9d74191a
TY		 6138 ctxt->interruptibility = 0;
6139 ctxt->have_exception = false;
e0ad0b47 6140 ctxt->exception.vector = -1;
9d74191a 6141 ctxt->perm_ok = false;
bbd9b64e 6142
b51e974f 6143 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6144
9d74191a 6145 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6146
e46479f8 6147 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6148 ++vcpu->stat.insn_emulation;
1d2887e2 6149 if (r != EMULATION_OK) {
4005996e
AK		 6150 if (emulation_type & EMULTYPE_TRAP_UD)
6151 return EMULATE_FAIL;
991eebf9
GN		 6152 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6153 emulation_type))
bbd9b64e 6154 return EMULATE_DONE;
6ea6e843
PB		 6155 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6156 return EMULATE_DONE;
6d77dbfc
GN		 6157 if (emulation_type & EMULTYPE_SKIP)
6158 return EMULATE_FAIL;
e2366171 6159 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6160 }
6161 }
6162
04789b66
LA		 6163 if ((emulation_type & EMULTYPE_VMWARE) &&
6164 !is_vmware_backdoor_opcode(ctxt))
6165 return EMULATE_FAIL;
6166
ba8afb6b 6167 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6168 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6169 if (ctxt->eflags & X86_EFLAGS_RF)
6170 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6171 return EMULATE_DONE;
6172 }
6173
1cb3f3ae
XG		 6174 if (retry_instruction(ctxt, cr2, emulation_type))
6175 return EMULATE_DONE;
6176
7ae441ea 6177 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6178 changes registers values during IO operation */
7ae441ea
GN		 6179 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6180 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6181 emulator_invalidate_register_cache(ctxt);
7ae441ea 6182 }
4d2179e1 6183
5cd21917 6184restart:
0f89b207
TL		 6185 /* Save the faulting GPA (cr2) in the address field */
6186 ctxt->exception.address = cr2;
6187
9d74191a 6188 r = x86_emulate_insn(ctxt);
bbd9b64e 6189
775fde86
JR		 6190 if (r == EMULATION_INTERCEPTED)
6191 return EMULATE_DONE;
6192
d2ddd1c4 6193 if (r == EMULATION_FAILED) {
991eebf9
GN		 6194 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6195 emulation_type))
c3cd7ffa
GN		 6196 return EMULATE_DONE;
6197
e2366171 6198 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6199 }
6200
9d74191a 6201 if (ctxt->have_exception) {
d2ddd1c4 6202 r = EMULATE_DONE;
ef54bcfe
PB		 6203 if (inject_emulated_exception(vcpu))
6204 return r;
d2ddd1c4 6205 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6206 if (!vcpu->arch.pio.in) {
6207 /* FIXME: return into emulator if single-stepping. */
3457e419 6208 vcpu->arch.pio.count = 0;
0912c977 6209 } else {
7ae441ea 6210 writeback = false;
716d51ab
GN		 6211 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6212 }
ac0a48c3 6213 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6214 } else if (vcpu->mmio_needed) {
6215 if (!vcpu->mmio_is_write)
6216 writeback = false;
ac0a48c3 6217 r = EMULATE_USER_EXIT;
716d51ab 6218 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6219 } else if (r == EMULATION_RESTART)
5cd21917 6220 goto restart;
d2ddd1c4
GN		 6221 else
6222 r = EMULATE_DONE;
f850e2e6 6223
7ae441ea 6224 if (writeback) {
6addfc42 6225 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6226 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6227 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6228 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6229 if (r == EMULATE_DONE &&
6230 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6231 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6232 if (!ctxt->have_exception ||
6233 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6234 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6235
6236 /*
6237 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6238 * do nothing, and it will be requested again as soon as
6239 * the shadow expires. But we still need to check here,
6240 * because POPF has no interrupt shadow.
6241 */
6242 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6243 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6244 } else
6245 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6246
6247 return r;
de7d789a 6248}
51d8b661 6249EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6250
dca7f128
SC		 6251static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6252 unsigned short port)
de7d789a 6253{
cf8f70bf 6254 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6255 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6256 size, port, &val, 1);
cf8f70bf 6257 /* do not return to emulator after return from userspace */
7972995b 6258 vcpu->arch.pio.count = 0;
de7d789a
CO		 6259 return ret;
6260}
de7d789a 6261
8370c3d0
TL		 6262static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6263{
6264 unsigned long val;
6265
6266 /* We should only ever be called with arch.pio.count equal to 1 */
6267 BUG_ON(vcpu->arch.pio.count != 1);
6268
6269 /* For size less than 4 we merge, else we zero extend */
6270 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6271 : 0;
6272
6273 /*
6274 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6275 * the copy and tracing
6276 */
6277 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6278 vcpu->arch.pio.port, &val, 1);
6279 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6280
6281 return 1;
6282}
6283
dca7f128
SC		 6284static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6285 unsigned short port)
8370c3d0
TL		 6286{
6287 unsigned long val;
6288 int ret;
6289
6290 /* For size less than 4 we merge, else we zero extend */
6291 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6292
6293 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6294 &val, 1);
6295 if (ret) {
6296 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6297 return ret;
6298 }
6299
6300 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6301
6302 return 0;
6303}
dca7f128
SC		 6304
6305int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6306{
6307 int ret = kvm_skip_emulated_instruction(vcpu);
6308
6309 /*
6310 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6311 * KVM_EXIT_DEBUG here.
6312 */
6313 if (in)
6314 return kvm_fast_pio_in(vcpu, size, port) && ret;
6315 else
6316 return kvm_fast_pio_out(vcpu, size, port) && ret;
6317}
6318EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6319
251a5fd6 6320static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6321{
0a3aee0d 6322 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6323 return 0;
8cfdc000
ZA		 6324}
6325
6326static void tsc_khz_changed(void *data)
c8076604 6327{
8cfdc000
ZA		 6328 struct cpufreq_freqs *freq = data;
6329 unsigned long khz = 0;
6330
6331 if (data)
6332 khz = freq->new;
6333 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6334 khz = cpufreq_quick_get(raw_smp_processor_id());
6335 if (!khz)
6336 khz = tsc_khz;
0a3aee0d 6337 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6338}
6339
5fa4ec9c 6340#ifdef CONFIG_X86_64
0092e434
VK		 6341static void kvm_hyperv_tsc_notifier(void)
6342{
0092e434
VK		 6343 struct kvm *kvm;
6344 struct kvm_vcpu *vcpu;
6345 int cpu;
6346
6347 spin_lock(&kvm_lock);
6348 list_for_each_entry(kvm, &vm_list, vm_list)
6349 kvm_make_mclock_inprogress_request(kvm);
6350
6351 hyperv_stop_tsc_emulation();
6352
6353 /* TSC frequency always matches when on Hyper-V */
6354 for_each_present_cpu(cpu)
6355 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6356 kvm_max_guest_tsc_khz = tsc_khz;
6357
6358 list_for_each_entry(kvm, &vm_list, vm_list) {
6359 struct kvm_arch *ka = &kvm->arch;
6360
6361 spin_lock(&ka->pvclock_gtod_sync_lock);
6362
6363 pvclock_update_vm_gtod_copy(kvm);
6364
6365 kvm_for_each_vcpu(cpu, vcpu, kvm)
6366 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6367
6368 kvm_for_each_vcpu(cpu, vcpu, kvm)
6369 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6370
6371 spin_unlock(&ka->pvclock_gtod_sync_lock);
6372 }
6373 spin_unlock(&kvm_lock);
0092e434 6374}
5fa4ec9c 6375#endif
0092e434 6376
c8076604
GH		 6377static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6378 void *data)
6379{
6380 struct cpufreq_freqs *freq = data;
6381 struct kvm *kvm;
6382 struct kvm_vcpu *vcpu;
6383 int i, send_ipi = 0;
6384
8cfdc000
ZA		 6385 /*
6386 * We allow guests to temporarily run on slowing clocks,
6387 * provided we notify them after, or to run on accelerating
6388 * clocks, provided we notify them before. Thus time never
6389 * goes backwards.
6390 *
6391 * However, we have a problem. We can't atomically update
6392 * the frequency of a given CPU from this function; it is
6393 * merely a notifier, which can be called from any CPU.
6394 * Changing the TSC frequency at arbitrary points in time
6395 * requires a recomputation of local variables related to
6396 * the TSC for each VCPU. We must flag these local variables
6397 * to be updated and be sure the update takes place with the
6398 * new frequency before any guests proceed.
6399 *
6400 * Unfortunately, the combination of hotplug CPU and frequency
6401 * change creates an intractable locking scenario; the order
6402 * of when these callouts happen is undefined with respect to
6403 * CPU hotplug, and they can race with each other. As such,
6404 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6405 * undefined; you can actually have a CPU frequency change take
6406 * place in between the computation of X and the setting of the
6407 * variable. To protect against this problem, all updates of
6408 * the per_cpu tsc_khz variable are done in an interrupt
6409 * protected IPI, and all callers wishing to update the value
6410 * must wait for a synchronous IPI to complete (which is trivial
6411 * if the caller is on the CPU already). This establishes the
6412 * necessary total order on variable updates.
6413 *
6414 * Note that because a guest time update may take place
6415 * anytime after the setting of the VCPU's request bit, the
6416 * correct TSC value must be set before the request. However,
6417 * to ensure the update actually makes it to any guest which
6418 * starts running in hardware virtualization between the set
6419 * and the acquisition of the spinlock, we must also ping the
6420 * CPU after setting the request bit.
6421 *
6422 */
6423
c8076604
GH		 6424 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6425 return 0;
6426 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6427 return 0;
8cfdc000
ZA		 6428
6429 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6430
2f303b74 6431 spin_lock(&kvm_lock);
c8076604 6432 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6433 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6434 if (vcpu->cpu != freq->cpu)
6435 continue;
c285545f 6436 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6437 if (vcpu->cpu != smp_processor_id())
8cfdc000 6438 send_ipi = 1;
c8076604
GH		 6439 }
6440 }
2f303b74 6441 spin_unlock(&kvm_lock);
c8076604
GH		 6442
6443 if (freq->old < freq->new && send_ipi) {
6444 /*
6445 * We upscale the frequency. Must make the guest
6446 * doesn't see old kvmclock values while running with
6447 * the new frequency, otherwise we risk the guest sees
6448 * time go backwards.
6449 *
6450 * In case we update the frequency for another cpu
6451 * (which might be in guest context) send an interrupt
6452 * to kick the cpu out of guest context. Next time
6453 * guest context is entered kvmclock will be updated,
6454 * so the guest will not see stale values.
6455 */
8cfdc000 6456 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6457 }
6458 return 0;
6459}
6460
6461static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6462 .notifier_call = kvmclock_cpufreq_notifier
6463};
6464
251a5fd6 6465static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6466{
251a5fd6
SAS		 6467 tsc_khz_changed(NULL);
6468 return 0;
8cfdc000
ZA		 6469}
6470
b820cc0c
ZA		 6471static void kvm_timer_init(void)
6472{
c285545f 6473 max_tsc_khz = tsc_khz;
460dd42e 6474
b820cc0c 6475 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6476#ifdef CONFIG_CPU_FREQ
6477 struct cpufreq_policy policy;
758f588d
BP		 6478 int cpu;
6479
c285545f 6480 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6481 cpu = get_cpu();
6482 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6483 if (policy.cpuinfo.max_freq)
6484 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6485 put_cpu();
c285545f 6486#endif
b820cc0c
ZA		 6487 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6488 CPUFREQ_TRANSITION_NOTIFIER);
6489 }
c285545f 6490 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6491
73c1b41e 6492 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6493 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6494}
6495
dd60d217
AK		 6496DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6497EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6498
f5132b01 6499int kvm_is_in_guest(void)
ff9d07a0 6500{
086c9855 6501 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6502}
6503
6504static int kvm_is_user_mode(void)
6505{
6506 int user_mode = 3;
dcf46b94 6507
086c9855
AS		 6508 if (__this_cpu_read(current_vcpu))
6509 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6510
ff9d07a0
ZY		 6511 return user_mode != 0;
6512}
6513
6514static unsigned long kvm_get_guest_ip(void)
6515{
6516 unsigned long ip = 0;
dcf46b94 6517
086c9855
AS		 6518 if (__this_cpu_read(current_vcpu))
6519 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6520
ff9d07a0
ZY		 6521 return ip;
6522}
6523
6524static struct perf_guest_info_callbacks kvm_guest_cbs = {
6525 .is_in_guest = kvm_is_in_guest,
6526 .is_user_mode = kvm_is_user_mode,
6527 .get_guest_ip = kvm_get_guest_ip,
6528};
6529
ce88decf
XG		 6530static void kvm_set_mmio_spte_mask(void)
6531{
6532 u64 mask;
6533 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6534
6535 /*
6536 * Set the reserved bits and the present bit of an paging-structure
6537 * entry to generate page fault with PFER.RSV = 1.
6538 */
885032b9 6539 /* Mask the reserved physical address bits. */
d1431483 6540 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6541
885032b9 6542 /* Set the present bit. */
ce88decf
XG		 6543 mask |= 1ull;
6544
6545#ifdef CONFIG_X86_64
6546 /*
6547 * If reserved bit is not supported, clear the present bit to disable
6548 * mmio page fault.
6549 */
6550 if (maxphyaddr == 52)
6551 mask &= ~1ull;
6552#endif
6553
dcdca5fe 6554 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6555}
6556
16e8d74d
MT		 6557#ifdef CONFIG_X86_64
6558static void pvclock_gtod_update_fn(struct work_struct *work)
6559{
d828199e
MT		 6560 struct kvm *kvm;
6561
6562 struct kvm_vcpu *vcpu;
6563 int i;
6564
2f303b74 6565 spin_lock(&kvm_lock);
d828199e
MT		 6566 list_for_each_entry(kvm, &vm_list, vm_list)
6567 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6568 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6569 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6570 spin_unlock(&kvm_lock);
16e8d74d
MT		 6571}
6572
6573static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6574
6575/*
6576 * Notification about pvclock gtod data update.
6577 */
6578static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6579 void *priv)
6580{
6581 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6582 struct timekeeper *tk = priv;
6583
6584 update_pvclock_gtod(tk);
6585
6586 /* disable master clock if host does not trust, or does not
b0c39dc6 6587 * use, TSC based clocksource.
16e8d74d 6588 */
b0c39dc6 6589 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6590 atomic_read(&kvm_guest_has_master_clock) != 0)
6591 queue_work(system_long_wq, &pvclock_gtod_work);
6592
6593 return 0;
6594}
6595
6596static struct notifier_block pvclock_gtod_notifier = {
6597 .notifier_call = pvclock_gtod_notify,
6598};
6599#endif
6600
f8c16bba 6601int kvm_arch_init(void *opaque)
043405e1 6602{
b820cc0c 6603 int r;
6b61edf7 6604 struct kvm_x86_ops *ops = opaque;
f8c16bba 6605
f8c16bba
ZX		 6606 if (kvm_x86_ops) {
6607 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6608 r = -EEXIST;
6609 goto out;
f8c16bba
ZX		 6610 }
6611
6612 if (!ops->cpu_has_kvm_support()) {
6613 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6614 r = -EOPNOTSUPP;
6615 goto out;
f8c16bba
ZX		 6616 }
6617 if (ops->disabled_by_bios()) {
6618 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6619 r = -EOPNOTSUPP;
6620 goto out;
f8c16bba
ZX		 6621 }
6622
013f6a5d
MT		 6623 r = -ENOMEM;
6624 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6625 if (!shared_msrs) {
6626 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6627 goto out;
6628 }
6629
97db56ce
AK		 6630 r = kvm_mmu_module_init();
6631 if (r)
013f6a5d 6632 goto out_free_percpu;
97db56ce 6633
ce88decf 6634 kvm_set_mmio_spte_mask();
97db56ce 6635
f8c16bba 6636 kvm_x86_ops = ops;
920c8377 6637
7b52345e 6638 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6639 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6640 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6641 kvm_timer_init();
c8076604 6642
ff9d07a0
ZY		 6643 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6644
d366bf7e 6645 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6646 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6647
c5cc421b 6648 kvm_lapic_init();
16e8d74d
MT		 6649#ifdef CONFIG_X86_64
6650 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6651
5fa4ec9c 6652 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6653 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6654#endif
6655
f8c16bba 6656 return 0;
56c6d28a 6657
013f6a5d
MT		 6658out_free_percpu:
6659 free_percpu(shared_msrs);
56c6d28a 6660out:
56c6d28a 6661 return r;
043405e1 6662}
8776e519 6663
f8c16bba
ZX		 6664void kvm_arch_exit(void)
6665{
0092e434 6666#ifdef CONFIG_X86_64
5fa4ec9c 6667 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6668 clear_hv_tscchange_cb();
6669#endif
cef84c30 6670 kvm_lapic_exit();
ff9d07a0
ZY		 6671 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6672
888d256e
JK		 6673 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6674 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6675 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6676 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6677#ifdef CONFIG_X86_64
6678 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6679#endif
f8c16bba 6680 kvm_x86_ops = NULL;
56c6d28a 6681 kvm_mmu_module_exit();
013f6a5d 6682 free_percpu(shared_msrs);
56c6d28a 6683}
f8c16bba 6684
5cb56059 6685int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6686{
6687 ++vcpu->stat.halt_exits;
35754c98 6688 if (lapic_in_kernel(vcpu)) {
a4535290 6689 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6690 return 1;
6691 } else {
6692 vcpu->run->exit_reason = KVM_EXIT_HLT;
6693 return 0;
6694 }
6695}
5cb56059
JS		 6696EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6697
6698int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6699{
6affcbed
KH		 6700 int ret = kvm_skip_emulated_instruction(vcpu);
6701 /*
6702 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6703 * KVM_EXIT_DEBUG here.
6704 */
6705 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6706}
8776e519
HB		 6707EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6708
8ef81a9a 6709#ifdef CONFIG_X86_64
55dd00a7
MT		 6710static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6711 unsigned long clock_type)
6712{
6713 struct kvm_clock_pairing clock_pairing;
899a31f5 6714 struct timespec64 ts;
80fbd89c 6715 u64 cycle;
55dd00a7
MT		 6716 int ret;
6717
6718 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6719 return -KVM_EOPNOTSUPP;
6720
6721 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6722 return -KVM_EOPNOTSUPP;
6723
6724 clock_pairing.sec = ts.tv_sec;
6725 clock_pairing.nsec = ts.tv_nsec;
6726 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6727 clock_pairing.flags = 0;
6728
6729 ret = 0;
6730 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6731 sizeof(struct kvm_clock_pairing)))
6732 ret = -KVM_EFAULT;
6733
6734 return ret;
6735}
8ef81a9a 6736#endif
55dd00a7 6737
6aef266c
SV		 6738/*
6739 * kvm_pv_kick_cpu_op: Kick a vcpu.
6740 *
6741 * @apicid - apicid of vcpu to be kicked.
6742 */
6743static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6744{
24d2166b 6745 struct kvm_lapic_irq lapic_irq;
6aef266c 6746
24d2166b
R		 6747 lapic_irq.shorthand = 0;
6748 lapic_irq.dest_mode = 0;
ebd28fcb 6749 lapic_irq.level = 0;
24d2166b 6750 lapic_irq.dest_id = apicid;
93bbf0b8 6751 lapic_irq.msi_redir_hint = false;
6aef266c 6752
24d2166b 6753 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6754 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6755}
6756
d62caabb
AS		 6757void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6758{
6759 vcpu->arch.apicv_active = false;
6760 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6761}
6762
8776e519
HB		 6763int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6764{
6765 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6766 int op_64_bit;
8776e519 6767
696ca779
RK		 6768 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6769 return kvm_hv_hypercall(vcpu);
55cd8e5a 6770
5fdbf976
MT		 6771 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6772 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6773 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6774 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6775 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6776
229456fc 6777 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6778
a449c7aa
NA		 6779 op_64_bit = is_64_bit_mode(vcpu);
6780 if (!op_64_bit) {
8776e519
HB		 6781 nr &= 0xFFFFFFFF;
6782 a0 &= 0xFFFFFFFF;
6783 a1 &= 0xFFFFFFFF;
6784 a2 &= 0xFFFFFFFF;
6785 a3 &= 0xFFFFFFFF;
6786 }
6787
07708c4a
JK		 6788 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6789 ret = -KVM_EPERM;
696ca779 6790 goto out;
07708c4a
JK		 6791 }
6792
8776e519 6793 switch (nr) {
b93463aa
AK		 6794 case KVM_HC_VAPIC_POLL_IRQ:
6795 ret = 0;
6796 break;
6aef266c
SV		 6797 case KVM_HC_KICK_CPU:
6798 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6799 ret = 0;
6800 break;
8ef81a9a 6801#ifdef CONFIG_X86_64
55dd00a7
MT		 6802 case KVM_HC_CLOCK_PAIRING:
6803 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6804 break;
8ef81a9a 6805#endif
8776e519
HB		 6806 default:
6807 ret = -KVM_ENOSYS;
6808 break;
6809 }
696ca779 6810out:
a449c7aa
NA		 6811 if (!op_64_bit)
6812 ret = (u32)ret;
5fdbf976 6813 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 6814
f11c3a8d 6815 ++vcpu->stat.hypercalls;
6356ee0c 6816 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6817}
6818EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6819
b6785def 6820static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6821{
d6aa1000 6822 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6823 char instruction[3];
5fdbf976 6824 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6825
8776e519 6826 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6827
ce2e852e
DV		 6828 return emulator_write_emulated(ctxt, rip, instruction, 3,
6829 &ctxt->exception);
8776e519
HB		 6830}
6831
851ba692 6832static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6833{
782d422b
MG		 6834 return vcpu->run->request_interrupt_window &&
6835 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6836}
6837
851ba692 6838static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6839{
851ba692
AK		 6840 struct kvm_run *kvm_run = vcpu->run;
6841
91586a3b 6842 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6843 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6844 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6845 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6846 kvm_run->ready_for_interrupt_injection =
6847 pic_in_kernel(vcpu->kvm) ||
782d422b 6848 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6849}
6850
95ba8273
GN		 6851static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6852{
6853 int max_irr, tpr;
6854
6855 if (!kvm_x86_ops->update_cr8_intercept)
6856 return;
6857
bce87cce 6858 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6859 return;
6860
d62caabb
AS		 6861 if (vcpu->arch.apicv_active)
6862 return;
6863
8db3baa2
GN		 6864 if (!vcpu->arch.apic->vapic_addr)
6865 max_irr = kvm_lapic_find_highest_irr(vcpu);
6866 else
6867 max_irr = -1;
95ba8273
GN		 6868
6869 if (max_irr != -1)
6870 max_irr >>= 4;
6871
6872 tpr = kvm_lapic_get_cr8(vcpu);
6873
6874 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6875}
6876
b6b8a145 6877static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6878{
b6b8a145
JK		 6879 int r;
6880
95ba8273 6881 /* try to reinject previous events if any */
664f8e26 6882
1a680e35
LA		 6883 if (vcpu->arch.exception.injected)
6884 kvm_x86_ops->queue_exception(vcpu);
664f8e26 6885 /*
a042c26f
LA		 6886 * Do not inject an NMI or interrupt if there is a pending
6887 * exception. Exceptions and interrupts are recognized at
6888 * instruction boundaries, i.e. the start of an instruction.
6889 * Trap-like exceptions, e.g. #DB, have higher priority than
6890 * NMIs and interrupts, i.e. traps are recognized before an
6891 * NMI/interrupt that's pending on the same instruction.
6892 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6893 * priority, but are only generated (pended) during instruction
6894 * execution, i.e. a pending fault-like exception means the
6895 * fault occurred on the *previous* instruction and must be
6896 * serviced prior to recognizing any new events in order to
6897 * fully complete the previous instruction.
664f8e26 6898 */
1a680e35
LA		 6899 else if (!vcpu->arch.exception.pending) {
6900 if (vcpu->arch.nmi_injected)
664f8e26 6901 kvm_x86_ops->set_nmi(vcpu);
1a680e35 6902 else if (vcpu->arch.interrupt.injected)
664f8e26 6903 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 6904 }
6905
1a680e35
LA		 6906 /*
6907 * Call check_nested_events() even if we reinjected a previous event
6908 * in order for caller to determine if it should require immediate-exit
6909 * from L2 to L1 due to pending L1 events which require exit
6910 * from L2 to L1.
6911 */
664f8e26
WL		 6912 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6913 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6914 if (r != 0)
6915 return r;
6916 }
6917
6918 /* try to inject new event if pending */
b59bb7bd 6919 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6920 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6921 vcpu->arch.exception.has_error_code,
6922 vcpu->arch.exception.error_code);
d6e8c854 6923
1a680e35 6924 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 6925 vcpu->arch.exception.pending = false;
6926 vcpu->arch.exception.injected = true;
6927
d6e8c854
NA		 6928 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6929 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6930 X86_EFLAGS_RF);
6931
6bdf0662
NA		 6932 if (vcpu->arch.exception.nr == DB_VECTOR &&
6933 (vcpu->arch.dr7 & DR7_GD)) {
6934 vcpu->arch.dr7 &= ~DR7_GD;
6935 kvm_update_dr7(vcpu);
6936 }
6937
cfcd20e5 6938 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 6939 }
6940
6941 /* Don't consider new event if we re-injected an event */
6942 if (kvm_event_needs_reinjection(vcpu))
6943 return 0;
6944
6945 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
6946 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6947 vcpu->arch.smi_pending = false;
52797bf9 6948 ++vcpu->arch.smi_count;
ee2cd4b7 6949 enter_smm(vcpu);
c43203ca 6950 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6951 --vcpu->arch.nmi_pending;
6952 vcpu->arch.nmi_injected = true;
6953 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6954 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6955 /*
6956 * Because interrupts can be injected asynchronously, we are
6957 * calling check_nested_events again here to avoid a race condition.
6958 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6959 * proposal and current concerns. Perhaps we should be setting
6960 * KVM_REQ_EVENT only on certain events and not unconditionally?
6961 */
6962 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6963 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6964 if (r != 0)
6965 return r;
6966 }
95ba8273 6967 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6968 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6969 false);
6970 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6971 }
6972 }
ee2cd4b7 6973
b6b8a145 6974 return 0;
95ba8273
GN		 6975}
6976
7460fb4a
AK		 6977static void process_nmi(struct kvm_vcpu *vcpu)
6978{
6979 unsigned limit = 2;
6980
6981 /*
6982 * x86 is limited to one NMI running, and one NMI pending after it.
6983 * If an NMI is already in progress, limit further NMIs to just one.
6984 * Otherwise, allow two (and we'll inject the first one immediately).
6985 */
6986 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6987 limit = 1;
6988
6989 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6990 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6991 kvm_make_request(KVM_REQ_EVENT, vcpu);
6992}
6993
ee2cd4b7 6994static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6995{
6996 u32 flags = 0;
6997 flags |= seg->g << 23;
6998 flags |= seg->db << 22;
6999 flags |= seg->l << 21;
7000 flags |= seg->avl << 20;
7001 flags |= seg->present << 15;
7002 flags |= seg->dpl << 13;
7003 flags |= seg->s << 12;
7004 flags |= seg->type << 8;
7005 return flags;
7006}
7007
ee2cd4b7 7008static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7009{
7010 struct kvm_segment seg;
7011 int offset;
7012
7013 kvm_get_segment(vcpu, &seg, n);
7014 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7015
7016 if (n < 3)
7017 offset = 0x7f84 + n * 12;
7018 else
7019 offset = 0x7f2c + (n - 3) * 12;
7020
7021 put_smstate(u32, buf, offset + 8, seg.base);
7022 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7023 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7024}
7025
efbb288a 7026#ifdef CONFIG_X86_64
ee2cd4b7 7027static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7028{
7029 struct kvm_segment seg;
7030 int offset;
7031 u16 flags;
7032
7033 kvm_get_segment(vcpu, &seg, n);
7034 offset = 0x7e00 + n * 16;
7035
ee2cd4b7 7036 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7037 put_smstate(u16, buf, offset, seg.selector);
7038 put_smstate(u16, buf, offset + 2, flags);
7039 put_smstate(u32, buf, offset + 4, seg.limit);
7040 put_smstate(u64, buf, offset + 8, seg.base);
7041}
efbb288a 7042#endif
660a5d51 7043
ee2cd4b7 7044static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7045{
7046 struct desc_ptr dt;
7047 struct kvm_segment seg;
7048 unsigned long val;
7049 int i;
7050
7051 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7052 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7053 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7054 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7055
7056 for (i = 0; i < 8; i++)
7057 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7058
7059 kvm_get_dr(vcpu, 6, &val);
7060 put_smstate(u32, buf, 0x7fcc, (u32)val);
7061 kvm_get_dr(vcpu, 7, &val);
7062 put_smstate(u32, buf, 0x7fc8, (u32)val);
7063
7064 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7065 put_smstate(u32, buf, 0x7fc4, seg.selector);
7066 put_smstate(u32, buf, 0x7f64, seg.base);
7067 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7068 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7069
7070 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7071 put_smstate(u32, buf, 0x7fc0, seg.selector);
7072 put_smstate(u32, buf, 0x7f80, seg.base);
7073 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7074 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7075
7076 kvm_x86_ops->get_gdt(vcpu, &dt);
7077 put_smstate(u32, buf, 0x7f74, dt.address);
7078 put_smstate(u32, buf, 0x7f70, dt.size);
7079
7080 kvm_x86_ops->get_idt(vcpu, &dt);
7081 put_smstate(u32, buf, 0x7f58, dt.address);
7082 put_smstate(u32, buf, 0x7f54, dt.size);
7083
7084 for (i = 0; i < 6; i++)
ee2cd4b7 7085 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7086
7087 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7088
7089 /* revision id */
7090 put_smstate(u32, buf, 0x7efc, 0x00020000);
7091 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7092}
7093
ee2cd4b7 7094static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7095{
7096#ifdef CONFIG_X86_64
7097 struct desc_ptr dt;
7098 struct kvm_segment seg;
7099 unsigned long val;
7100 int i;
7101
7102 for (i = 0; i < 16; i++)
7103 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7104
7105 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7106 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7107
7108 kvm_get_dr(vcpu, 6, &val);
7109 put_smstate(u64, buf, 0x7f68, val);
7110 kvm_get_dr(vcpu, 7, &val);
7111 put_smstate(u64, buf, 0x7f60, val);
7112
7113 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7114 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7115 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7116
7117 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7118
7119 /* revision id */
7120 put_smstate(u32, buf, 0x7efc, 0x00020064);
7121
7122 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7123
7124 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7125 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7126 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7127 put_smstate(u32, buf, 0x7e94, seg.limit);
7128 put_smstate(u64, buf, 0x7e98, seg.base);
7129
7130 kvm_x86_ops->get_idt(vcpu, &dt);
7131 put_smstate(u32, buf, 0x7e84, dt.size);
7132 put_smstate(u64, buf, 0x7e88, dt.address);
7133
7134 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7135 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7136 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7137 put_smstate(u32, buf, 0x7e74, seg.limit);
7138 put_smstate(u64, buf, 0x7e78, seg.base);
7139
7140 kvm_x86_ops->get_gdt(vcpu, &dt);
7141 put_smstate(u32, buf, 0x7e64, dt.size);
7142 put_smstate(u64, buf, 0x7e68, dt.address);
7143
7144 for (i = 0; i < 6; i++)
ee2cd4b7 7145 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7146#else
7147 WARN_ON_ONCE(1);
7148#endif
7149}
7150
ee2cd4b7 7151static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7152{
660a5d51 7153 struct kvm_segment cs, ds;
18c3626e 7154 struct desc_ptr dt;
660a5d51
PB		 7155 char buf[512];
7156 u32 cr0;
7157
660a5d51 7158 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7159 memset(buf, 0, 512);
d6321d49 7160 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7161 enter_smm_save_state_64(vcpu, buf);
660a5d51 7162 else
ee2cd4b7 7163 enter_smm_save_state_32(vcpu, buf);
660a5d51 7164
0234bf88
LP		 7165 /*
7166 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7167 * vCPU state (e.g. leave guest mode) after we've saved the state into
7168 * the SMM state-save area.
7169 */
7170 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7171
7172 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7173 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7174
7175 if (kvm_x86_ops->get_nmi_mask(vcpu))
7176 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7177 else
7178 kvm_x86_ops->set_nmi_mask(vcpu, true);
7179
7180 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7181 kvm_rip_write(vcpu, 0x8000);
7182
7183 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7184 kvm_x86_ops->set_cr0(vcpu, cr0);
7185 vcpu->arch.cr0 = cr0;
7186
7187 kvm_x86_ops->set_cr4(vcpu, 0);
7188
18c3626e
PB		 7189 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7190 dt.address = dt.size = 0;
7191 kvm_x86_ops->set_idt(vcpu, &dt);
7192
660a5d51
PB		 7193 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7194
7195 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7196 cs.base = vcpu->arch.smbase;
7197
7198 ds.selector = 0;
7199 ds.base = 0;
7200
7201 cs.limit = ds.limit = 0xffffffff;
7202 cs.type = ds.type = 0x3;
7203 cs.dpl = ds.dpl = 0;
7204 cs.db = ds.db = 0;
7205 cs.s = ds.s = 1;
7206 cs.l = ds.l = 0;
7207 cs.g = ds.g = 1;
7208 cs.avl = ds.avl = 0;
7209 cs.present = ds.present = 1;
7210 cs.unusable = ds.unusable = 0;
7211 cs.padding = ds.padding = 0;
7212
7213 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7214 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7215 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7216 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7217 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7218 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7219
d6321d49 7220 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7221 kvm_x86_ops->set_efer(vcpu, 0);
7222
7223 kvm_update_cpuid(vcpu);
7224 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7225}
7226
ee2cd4b7 7227static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7228{
7229 vcpu->arch.smi_pending = true;
7230 kvm_make_request(KVM_REQ_EVENT, vcpu);
7231}
7232
2860c4b1
PB		 7233void kvm_make_scan_ioapic_request(struct kvm *kvm)
7234{
7235 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7236}
7237
3d81bc7e 7238static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7239{
3d81bc7e
YZ		 7240 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7241 return;
c7c9c56c 7242
6308630b 7243 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7244
b053b2ae 7245 if (irqchip_split(vcpu->kvm))
6308630b 7246 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7247 else {
fa59cc00 7248 if (vcpu->arch.apicv_active)
d62caabb 7249 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7250 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7251 }
e40ff1d6
LA		 7252
7253 if (is_guest_mode(vcpu))
7254 vcpu->arch.load_eoi_exitmap_pending = true;
7255 else
7256 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7257}
7258
7259static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7260{
7261 u64 eoi_exit_bitmap[4];
7262
7263 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7264 return;
7265
5c919412
AS		 7266 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7267 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7268 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7269}
7270
b1394e74
RK		 7271void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7272 unsigned long start, unsigned long end)
7273{
7274 unsigned long apic_address;
7275
7276 /*
7277 * The physical address of apic access page is stored in the VMCS.
7278 * Update it when it becomes invalid.
7279 */
7280 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7281 if (start <= apic_address && apic_address < end)
7282 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7283}
7284
4256f43f
TC		 7285void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7286{
c24ae0dc
TC		 7287 struct page *page = NULL;
7288
35754c98 7289 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7290 return;
7291
4256f43f
TC		 7292 if (!kvm_x86_ops->set_apic_access_page_addr)
7293 return;
7294
c24ae0dc 7295 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7296 if (is_error_page(page))
7297 return;
c24ae0dc
TC		 7298 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7299
7300 /*
7301 * Do not pin apic access page in memory, the MMU notifier
7302 * will call us again if it is migrated or swapped out.
7303 */
7304 put_page(page);
4256f43f
TC		 7305}
7306EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7307
9357d939 7308/*
362c698f 7309 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7310 * exiting to the userspace. Otherwise, the value will be returned to the
7311 * userspace.
7312 */
851ba692 7313static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7314{
7315 int r;
62a193ed
MG		 7316 bool req_int_win =
7317 dm_request_for_irq_injection(vcpu) &&
7318 kvm_cpu_accept_dm_intr(vcpu);
7319
730dca42 7320 bool req_immediate_exit = false;
b6c7a5dc 7321
2fa6e1e1 7322 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7323 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7324 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7325 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7326 kvm_mmu_unload(vcpu);
a8eeb04a 7327 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7328 __kvm_migrate_timers(vcpu);
d828199e
MT		 7329 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7330 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7331 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7332 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7333 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7334 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7335 if (unlikely(r))
7336 goto out;
7337 }
a8eeb04a 7338 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7339 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7340 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7341 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7342 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7343 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7344 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7345 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7346 r = 0;
7347 goto out;
7348 }
a8eeb04a 7349 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7350 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7351 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7352 r = 0;
7353 goto out;
7354 }
af585b92
GN		 7355 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7356 /* Page is swapped out. Do synthetic halt */
7357 vcpu->arch.apf.halted = true;
7358 r = 1;
7359 goto out;
7360 }
c9aaa895
GC		 7361 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7362 record_steal_time(vcpu);
64d60670
PB		 7363 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7364 process_smi(vcpu);
7460fb4a
AK		 7365 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7366 process_nmi(vcpu);
f5132b01 7367 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7368 kvm_pmu_handle_event(vcpu);
f5132b01 7369 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7370 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7371 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7372 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7373 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7374 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7375 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7376 vcpu->run->eoi.vector =
7377 vcpu->arch.pending_ioapic_eoi;
7378 r = 0;
7379 goto out;
7380 }
7381 }
3d81bc7e
YZ		 7382 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7383 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7384 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7385 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7386 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7387 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7388 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7389 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7390 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7391 r = 0;
7392 goto out;
7393 }
e516cebb
AS		 7394 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7395 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7396 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7397 r = 0;
7398 goto out;
7399 }
db397571
AS		 7400 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7401 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7402 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7403 r = 0;
7404 goto out;
7405 }
f3b138c5
AS		 7406
7407 /*
7408 * KVM_REQ_HV_STIMER has to be processed after
7409 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7410 * depend on the guest clock being up-to-date
7411 */
1f4b34f8
AS		 7412 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7413 kvm_hv_process_stimers(vcpu);
2f52d58c 7414 }
b93463aa 7415
b463a6f7 7416 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7417 ++vcpu->stat.req_event;
66450a21
JK		 7418 kvm_apic_accept_events(vcpu);
7419 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7420 r = 1;
7421 goto out;
7422 }
7423
b6b8a145
JK		 7424 if (inject_pending_event(vcpu, req_int_win) != 0)
7425 req_immediate_exit = true;
321c5658 7426 else {
cc3d967f 7427 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7428 *
cc3d967f
LP		 7429 * SMIs have three cases:
7430 * 1) They can be nested, and then there is nothing to
7431 * do here because RSM will cause a vmexit anyway.
7432 * 2) There is an ISA-specific reason why SMI cannot be
7433 * injected, and the moment when this changes can be
7434 * intercepted.
7435 * 3) Or the SMI can be pending because
7436 * inject_pending_event has completed the injection
7437 * of an IRQ or NMI from the previous vmexit, and
7438 * then we request an immediate exit to inject the
7439 * SMI.
c43203ca
PB		 7440 */
7441 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7442 if (!kvm_x86_ops->enable_smi_window(vcpu))
7443 req_immediate_exit = true;
321c5658
YS		 7444 if (vcpu->arch.nmi_pending)
7445 kvm_x86_ops->enable_nmi_window(vcpu);
7446 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7447 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7448 WARN_ON(vcpu->arch.exception.pending);
321c5658 7449 }
b463a6f7
AK		 7450
7451 if (kvm_lapic_enabled(vcpu)) {
7452 update_cr8_intercept(vcpu);
7453 kvm_lapic_sync_to_vapic(vcpu);
7454 }
7455 }
7456
d8368af8
AK		 7457 r = kvm_mmu_reload(vcpu);
7458 if (unlikely(r)) {
d905c069 7459 goto cancel_injection;
d8368af8
AK		 7460 }
7461
b6c7a5dc
HB		 7462 preempt_disable();
7463
7464 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7465
7466 /*
7467 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7468 * IPI are then delayed after guest entry, which ensures that they
7469 * result in virtual interrupt delivery.
7470 */
7471 local_irq_disable();
6b7e2d09
XG		 7472 vcpu->mode = IN_GUEST_MODE;
7473
01b71917
MT		 7474 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7475
0f127d12 7476 /*
b95234c8 7477 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7478 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7479 *
7480 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7481 * pairs with the memory barrier implicit in pi_test_and_set_on
7482 * (see vmx_deliver_posted_interrupt).
7483 *
7484 * 3) This also orders the write to mode from any reads to the page
7485 * tables done while the VCPU is running. Please see the comment
7486 * in kvm_flush_remote_tlbs.
6b7e2d09 7487 */
01b71917 7488 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7489
b95234c8
PB		 7490 /*
7491 * This handles the case where a posted interrupt was
7492 * notified with kvm_vcpu_kick.
7493 */
fa59cc00
LA		 7494 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7495 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7496
2fa6e1e1 7497 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7498 || need_resched() || signal_pending(current)) {
6b7e2d09 7499 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7500 smp_wmb();
6c142801
AK		 7501 local_irq_enable();
7502 preempt_enable();
01b71917 7503 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7504 r = 1;
d905c069 7505 goto cancel_injection;
6c142801
AK		 7506 }
7507
fc5b7f3b
DM		 7508 kvm_load_guest_xcr0(vcpu);
7509
c43203ca
PB		 7510 if (req_immediate_exit) {
7511 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7512 smp_send_reschedule(vcpu->cpu);
c43203ca 7513 }
d6185f20 7514
8b89fe1f 7515 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7516 if (lapic_timer_advance_ns)
7517 wait_lapic_expire(vcpu);
6edaa530 7518 guest_enter_irqoff();
b6c7a5dc 7519
42dbaa5a 7520 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7521 set_debugreg(0, 7);
7522 set_debugreg(vcpu->arch.eff_db[0], 0);
7523 set_debugreg(vcpu->arch.eff_db[1], 1);
7524 set_debugreg(vcpu->arch.eff_db[2], 2);
7525 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7526 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7527 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7528 }
b6c7a5dc 7529
851ba692 7530 kvm_x86_ops->run(vcpu);
b6c7a5dc 7531
c77fb5fe
PB		 7532 /*
7533 * Do this here before restoring debug registers on the host. And
7534 * since we do this before handling the vmexit, a DR access vmexit
7535 * can (a) read the correct value of the debug registers, (b) set
7536 * KVM_DEBUGREG_WONT_EXIT again.
7537 */
7538 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7539 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7540 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7541 kvm_update_dr0123(vcpu);
7542 kvm_update_dr6(vcpu);
7543 kvm_update_dr7(vcpu);
7544 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7545 }
7546
24f1e32c
FW		 7547 /*
7548 * If the guest has used debug registers, at least dr7
7549 * will be disabled while returning to the host.
7550 * If we don't have active breakpoints in the host, we don't
7551 * care about the messed up debug address registers. But if
7552 * we have some of them active, restore the old state.
7553 */
59d8eb53 7554 if (hw_breakpoint_active())
24f1e32c 7555 hw_breakpoint_restore();
42dbaa5a 7556
4ba76538 7557 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7558
6b7e2d09 7559 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7560 smp_wmb();
a547c6db 7561
fc5b7f3b
DM		 7562 kvm_put_guest_xcr0(vcpu);
7563
dd60d217 7564 kvm_before_interrupt(vcpu);
a547c6db 7565 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7566 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7567
7568 ++vcpu->stat.exits;
7569
f2485b3e 7570 guest_exit_irqoff();
b6c7a5dc 7571
f2485b3e 7572 local_irq_enable();
b6c7a5dc
HB		 7573 preempt_enable();
7574
f656ce01 7575 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7576
b6c7a5dc
HB		 7577 /*
7578 * Profile KVM exit RIPs:
7579 */
7580 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7581 unsigned long rip = kvm_rip_read(vcpu);
7582 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7583 }
7584
cc578287
ZA		 7585 if (unlikely(vcpu->arch.tsc_always_catchup))
7586 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7587
5cfb1d5a
MT		 7588 if (vcpu->arch.apic_attention)
7589 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7590
618232e2 7591 vcpu->arch.gpa_available = false;
851ba692 7592 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7593 return r;
7594
7595cancel_injection:
7596 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7597 if (unlikely(vcpu->arch.apic_attention))
7598 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7599out:
7600 return r;
7601}
b6c7a5dc 7602
362c698f
PB		 7603static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7604{
bf9f6ac8
FW		 7605 if (!kvm_arch_vcpu_runnable(vcpu) &&
7606 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7607 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7608 kvm_vcpu_block(vcpu);
7609 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7610
7611 if (kvm_x86_ops->post_block)
7612 kvm_x86_ops->post_block(vcpu);
7613
9c8fd1ba
PB		 7614 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7615 return 1;
7616 }
362c698f
PB		 7617
7618 kvm_apic_accept_events(vcpu);
7619 switch(vcpu->arch.mp_state) {
7620 case KVM_MP_STATE_HALTED:
7621 vcpu->arch.pv.pv_unhalted = false;
7622 vcpu->arch.mp_state =
7623 KVM_MP_STATE_RUNNABLE;
7624 case KVM_MP_STATE_RUNNABLE:
7625 vcpu->arch.apf.halted = false;
7626 break;
7627 case KVM_MP_STATE_INIT_RECEIVED:
7628 break;
7629 default:
7630 return -EINTR;
7631 break;
7632 }
7633 return 1;
7634}
09cec754 7635
5d9bc648
PB		 7636static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7637{
0ad3bed6
PB		 7638 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7639 kvm_x86_ops->check_nested_events(vcpu, false);
7640
5d9bc648
PB		 7641 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7642 !vcpu->arch.apf.halted);
7643}
7644
362c698f 7645static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7646{
7647 int r;
f656ce01 7648 struct kvm *kvm = vcpu->kvm;
d7690175 7649
f656ce01 7650 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7651
362c698f 7652 for (;;) {
58f800d5 7653 if (kvm_vcpu_running(vcpu)) {
851ba692 7654 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7655 } else {
362c698f 7656 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7657 }
7658
09cec754
GN		 7659 if (r <= 0)
7660 break;
7661
72875d8a 7662 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7663 if (kvm_cpu_has_pending_timer(vcpu))
7664 kvm_inject_pending_timer_irqs(vcpu);
7665
782d422b
MG		 7666 if (dm_request_for_irq_injection(vcpu) &&
7667 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7668 r = 0;
7669 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7670 ++vcpu->stat.request_irq_exits;
362c698f 7671 break;
09cec754 7672 }
af585b92
GN		 7673
7674 kvm_check_async_pf_completion(vcpu);
7675
09cec754
GN		 7676 if (signal_pending(current)) {
7677 r = -EINTR;
851ba692 7678 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7679 ++vcpu->stat.signal_exits;
362c698f 7680 break;
09cec754
GN		 7681 }
7682 if (need_resched()) {
f656ce01 7683 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7684 cond_resched();
f656ce01 7685 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7686 }
b6c7a5dc
HB		 7687 }
7688
f656ce01 7689 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7690
7691 return r;
7692}
7693
716d51ab
GN		 7694static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7695{
7696 int r;
7697 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7698 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7699 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7700 if (r != EMULATE_DONE)
7701 return 0;
7702 return 1;
7703}
7704
7705static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7706{
7707 BUG_ON(!vcpu->arch.pio.count);
7708
7709 return complete_emulated_io(vcpu);
7710}
7711
f78146b0
AK		 7712/*
7713 * Implements the following, as a state machine:
7714 *
7715 * read:
7716 * for each fragment
87da7e66
XG		 7717 * for each mmio piece in the fragment
7718 * write gpa, len
7719 * exit
7720 * copy data
f78146b0
AK		 7721 * execute insn
7722 *
7723 * write:
7724 * for each fragment
87da7e66
XG		 7725 * for each mmio piece in the fragment
7726 * write gpa, len
7727 * copy data
7728 * exit
f78146b0 7729 */
716d51ab 7730static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7731{
7732 struct kvm_run *run = vcpu->run;
f78146b0 7733 struct kvm_mmio_fragment *frag;
87da7e66 7734 unsigned len;
5287f194 7735
716d51ab 7736 BUG_ON(!vcpu->mmio_needed);
5287f194 7737
716d51ab 7738 /* Complete previous fragment */
87da7e66
XG		 7739 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7740 len = min(8u, frag->len);
716d51ab 7741 if (!vcpu->mmio_is_write)
87da7e66
XG		 7742 memcpy(frag->data, run->mmio.data, len);
7743
7744 if (frag->len <= 8) {
7745 /* Switch to the next fragment. */
7746 frag++;
7747 vcpu->mmio_cur_fragment++;
7748 } else {
7749 /* Go forward to the next mmio piece. */
7750 frag->data += len;
7751 frag->gpa += len;
7752 frag->len -= len;
7753 }
7754
a08d3b3b 7755 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7756 vcpu->mmio_needed = 0;
0912c977
PB		 7757
7758 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7759 if (vcpu->mmio_is_write)
716d51ab
GN		 7760 return 1;
7761 vcpu->mmio_read_completed = 1;
7762 return complete_emulated_io(vcpu);
7763 }
87da7e66 7764
716d51ab
GN		 7765 run->exit_reason = KVM_EXIT_MMIO;
7766 run->mmio.phys_addr = frag->gpa;
7767 if (vcpu->mmio_is_write)
87da7e66
XG		 7768 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7769 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7770 run->mmio.is_write = vcpu->mmio_is_write;
7771 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7772 return 0;
5287f194
AK		 7773}
7774
b6c7a5dc
HB		 7775int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7776{
7777 int r;
b6c7a5dc 7778
accb757d 7779 vcpu_load(vcpu);
20b7035c 7780 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7781 kvm_load_guest_fpu(vcpu);
7782
a4535290 7783 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7784 if (kvm_run->immediate_exit) {
7785 r = -EINTR;
7786 goto out;
7787 }
b6c7a5dc 7788 kvm_vcpu_block(vcpu);
66450a21 7789 kvm_apic_accept_events(vcpu);
72875d8a 7790 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7791 r = -EAGAIN;
a0595000
JS		 7792 if (signal_pending(current)) {
7793 r = -EINTR;
7794 vcpu->run->exit_reason = KVM_EXIT_INTR;
7795 ++vcpu->stat.signal_exits;
7796 }
ac9f6dc0 7797 goto out;
b6c7a5dc
HB		 7798 }
7799
01643c51
KH		 7800 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7801 r = -EINVAL;
7802 goto out;
7803 }
7804
7805 if (vcpu->run->kvm_dirty_regs) {
7806 r = sync_regs(vcpu);
7807 if (r != 0)
7808 goto out;
7809 }
7810
b6c7a5dc 7811 /* re-sync apic's tpr */
35754c98 7812 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7813 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7814 r = -EINVAL;
7815 goto out;
7816 }
7817 }
b6c7a5dc 7818
716d51ab
GN		 7819 if (unlikely(vcpu->arch.complete_userspace_io)) {
7820 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7821 vcpu->arch.complete_userspace_io = NULL;
7822 r = cui(vcpu);
7823 if (r <= 0)
5663d8f9 7824 goto out;
716d51ab
GN		 7825 } else
7826 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7827
460df4c1
PB		 7828 if (kvm_run->immediate_exit)
7829 r = -EINTR;
7830 else
7831 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7832
7833out:
5663d8f9 7834 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7835 if (vcpu->run->kvm_valid_regs)
7836 store_regs(vcpu);
f1d86e46 7837 post_kvm_run_save(vcpu);
20b7035c 7838 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7839
accb757d 7840 vcpu_put(vcpu);
b6c7a5dc
HB		 7841 return r;
7842}
7843
01643c51 7844static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7845{
7ae441ea
GN		 7846 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7847 /*
7848 * We are here if userspace calls get_regs() in the middle of
7849 * instruction emulation. Registers state needs to be copied
4a969980 7850 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7851 * that usually, but some bad designed PV devices (vmware
7852 * backdoor interface) need this to work
7853 */
dd856efa 7854 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7855 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7856 }
5fdbf976
MT		 7857 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7858 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7859 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7860 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7861 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7862 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7863 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7864 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7865#ifdef CONFIG_X86_64
5fdbf976
MT		 7866 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7867 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7868 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7869 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7870 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7871 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7872 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7873 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7874#endif
7875
5fdbf976 7876 regs->rip = kvm_rip_read(vcpu);
91586a3b 7877 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7878}
b6c7a5dc 7879
01643c51
KH		 7880int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7881{
7882 vcpu_load(vcpu);
7883 __get_regs(vcpu, regs);
1fc9b76b 7884 vcpu_put(vcpu);
b6c7a5dc
HB		 7885 return 0;
7886}
7887
01643c51 7888static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7889{
7ae441ea
GN		 7890 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7891 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7892
5fdbf976
MT		 7893 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7894 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7895 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7896 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7897 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7898 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7899 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7900 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7901#ifdef CONFIG_X86_64
5fdbf976
MT		 7902 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7903 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7904 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7905 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7906 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7907 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7908 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7909 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7910#endif
7911
5fdbf976 7912 kvm_rip_write(vcpu, regs->rip);
d73235d1 7913 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7914
b4f14abd
JK		 7915 vcpu->arch.exception.pending = false;
7916
3842d135 7917 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7918}
3842d135 7919
01643c51
KH		 7920int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7921{
7922 vcpu_load(vcpu);
7923 __set_regs(vcpu, regs);
875656fe 7924 vcpu_put(vcpu);
b6c7a5dc
HB		 7925 return 0;
7926}
7927
b6c7a5dc
HB		 7928void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7929{
7930 struct kvm_segment cs;
7931
3e6e0aab 7932 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7933 *db = cs.db;
7934 *l = cs.l;
7935}
7936EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7937
01643c51 7938static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7939{
89a27f4d 7940 struct desc_ptr dt;
b6c7a5dc 7941
3e6e0aab
GT		 7942 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7943 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7944 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7945 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7946 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7947 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7948
3e6e0aab
GT		 7949 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7950 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7951
7952 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7953 sregs->idt.limit = dt.size;
7954 sregs->idt.base = dt.address;
b6c7a5dc 7955 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7956 sregs->gdt.limit = dt.size;
7957 sregs->gdt.base = dt.address;
b6c7a5dc 7958
4d4ec087 7959 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7960 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7961 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7962 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7963 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7964 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7965 sregs->apic_base = kvm_get_apic_base(vcpu);
7966
923c61bb 7967 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7968
04140b41 7969 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7970 set_bit(vcpu->arch.interrupt.nr,
7971 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7972}
16d7a191 7973
01643c51
KH		 7974int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7975 struct kvm_sregs *sregs)
7976{
7977 vcpu_load(vcpu);
7978 __get_sregs(vcpu, sregs);
bcdec41c 7979 vcpu_put(vcpu);
b6c7a5dc
HB		 7980 return 0;
7981}
7982
62d9f0db
MT		 7983int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7984 struct kvm_mp_state *mp_state)
7985{
fd232561
CD		 7986 vcpu_load(vcpu);
7987
66450a21 7988 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7989 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7990 vcpu->arch.pv.pv_unhalted)
7991 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7992 else
7993 mp_state->mp_state = vcpu->arch.mp_state;
7994
fd232561 7995 vcpu_put(vcpu);
62d9f0db
MT		 7996 return 0;
7997}
7998
7999int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8000 struct kvm_mp_state *mp_state)
8001{
e83dff5e
CD		 8002 int ret = -EINVAL;
8003
8004 vcpu_load(vcpu);
8005
bce87cce 8006 if (!lapic_in_kernel(vcpu) &&
66450a21 8007 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8008 goto out;
66450a21 8009
28bf2888
DH		 8010 /* INITs are latched while in SMM */
8011 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8012 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8013 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8014 goto out;
28bf2888 8015
66450a21
JK		 8016 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8017 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8018 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8019 } else
8020 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8021 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8022
8023 ret = 0;
8024out:
8025 vcpu_put(vcpu);
8026 return ret;
62d9f0db
MT		 8027}
8028
7f3d35fd
KW		 8029int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8030 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8031{
9d74191a 8032 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8033 int ret;
e01c2426 8034
8ec4722d 8035 init_emulate_ctxt(vcpu);
c697518a 8036
7f3d35fd 8037 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8038 has_error_code, error_code);
c697518a 8039
c697518a 8040 if (ret)
19d04437 8041 return EMULATE_FAIL;
37817f29 8042
9d74191a
TY		 8043 kvm_rip_write(vcpu, ctxt->eip);
8044 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8045 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8046 return EMULATE_DONE;
37817f29
IE		 8047}
8048EXPORT_SYMBOL_GPL(kvm_task_switch);
8049
3140c156 8050static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8051{
74fec5b9
TL		 8052 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8053 (sregs->cr4 & X86_CR4_OSXSAVE))
8054 return -EINVAL;
8055
37b95951 8056 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8057 /*
8058 * When EFER.LME and CR0.PG are set, the processor is in
8059 * 64-bit mode (though maybe in a 32-bit code segment).
8060 * CR4.PAE and EFER.LMA must be set.
8061 */
37b95951 8062 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8063 || !(sregs->efer & EFER_LMA))
8064 return -EINVAL;
8065 } else {
8066 /*
8067 * Not in 64-bit mode: EFER.LMA is clear and the code
8068 * segment cannot be 64-bit.
8069 */
8070 if (sregs->efer & EFER_LMA || sregs->cs.l)
8071 return -EINVAL;
8072 }
8073
8074 return 0;
8075}
8076
01643c51 8077static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8078{
58cb628d 8079 struct msr_data apic_base_msr;
b6c7a5dc 8080 int mmu_reset_needed = 0;
c4d21882 8081 int cpuid_update_needed = 0;
63f42e02 8082 int pending_vec, max_bits, idx;
89a27f4d 8083 struct desc_ptr dt;
b4ef9d4e
CD		 8084 int ret = -EINVAL;
8085
f2981033 8086 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8087 goto out;
f2981033 8088
d3802286
JM		 8089 apic_base_msr.data = sregs->apic_base;
8090 apic_base_msr.host_initiated = true;
8091 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8092 goto out;
6d1068b3 8093
89a27f4d
GN		 8094 dt.size = sregs->idt.limit;
8095 dt.address = sregs->idt.base;
b6c7a5dc 8096 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8097 dt.size = sregs->gdt.limit;
8098 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8099 kvm_x86_ops->set_gdt(vcpu, &dt);
8100
ad312c7c 8101 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8102 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8103 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8104 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8105
2d3ad1f4 8106 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8107
f6801dff 8108 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8109 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8110
4d4ec087 8111 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8112 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8113 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8114
fc78f519 8115 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8116 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8117 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8118 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8119 if (cpuid_update_needed)
00b27a3e 8120 kvm_update_cpuid(vcpu);
63f42e02
XG		 8121
8122 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 8123 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 8124 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8125 mmu_reset_needed = 1;
8126 }
63f42e02 8127 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8128
8129 if (mmu_reset_needed)
8130 kvm_mmu_reset_context(vcpu);
8131
a50abc3b 8132 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8133 pending_vec = find_first_bit(
8134 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8135 if (pending_vec < max_bits) {
66fd3f7f 8136 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8137 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8138 }
8139
3e6e0aab
GT		 8140 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8141 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8142 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8143 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8144 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8145 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8146
3e6e0aab
GT		 8147 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8148 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8149
5f0269f5
ME		 8150 update_cr8_intercept(vcpu);
8151
9c3e4aab 8152 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8153 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8154 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8155 !is_protmode(vcpu))
9c3e4aab
MT		 8156 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8157
3842d135
AK		 8158 kvm_make_request(KVM_REQ_EVENT, vcpu);
8159
b4ef9d4e
CD		 8160 ret = 0;
8161out:
01643c51
KH		 8162 return ret;
8163}
8164
8165int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8166 struct kvm_sregs *sregs)
8167{
8168 int ret;
8169
8170 vcpu_load(vcpu);
8171 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8172 vcpu_put(vcpu);
8173 return ret;
b6c7a5dc
HB		 8174}
8175
d0bfb940
JK		 8176int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8177 struct kvm_guest_debug *dbg)
b6c7a5dc 8178{
355be0b9 8179 unsigned long rflags;
ae675ef0 8180 int i, r;
b6c7a5dc 8181
66b56562
CD		 8182 vcpu_load(vcpu);
8183
4f926bf2
JK		 8184 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8185 r = -EBUSY;
8186 if (vcpu->arch.exception.pending)
2122ff5e 8187 goto out;
4f926bf2
JK		 8188 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8189 kvm_queue_exception(vcpu, DB_VECTOR);
8190 else
8191 kvm_queue_exception(vcpu, BP_VECTOR);
8192 }
8193
91586a3b
JK		 8194 /*
8195 * Read rflags as long as potentially injected trace flags are still
8196 * filtered out.
8197 */
8198 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8199
8200 vcpu->guest_debug = dbg->control;
8201 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8202 vcpu->guest_debug = 0;
8203
8204 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8205 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8206 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8207 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8208 } else {
8209 for (i = 0; i < KVM_NR_DB_REGS; i++)
8210 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8211 }
c8639010 8212 kvm_update_dr7(vcpu);
ae675ef0 8213
f92653ee
JK		 8214 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8215 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8216 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8217
91586a3b
JK		 8218 /*
8219 * Trigger an rflags update that will inject or remove the trace
8220 * flags.
8221 */
8222 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8223
a96036b8 8224 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8225
4f926bf2 8226 r = 0;
d0bfb940 8227
2122ff5e 8228out:
66b56562 8229 vcpu_put(vcpu);
b6c7a5dc
HB		 8230 return r;
8231}
8232
8b006791
ZX		 8233/*
8234 * Translate a guest virtual address to a guest physical address.
8235 */
8236int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8237 struct kvm_translation *tr)
8238{
8239 unsigned long vaddr = tr->linear_address;
8240 gpa_t gpa;
f656ce01 8241 int idx;
8b006791 8242
1da5b61d
CD		 8243 vcpu_load(vcpu);
8244
f656ce01 8245 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8246 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8247 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8248 tr->physical_address = gpa;
8249 tr->valid = gpa != UNMAPPED_GVA;
8250 tr->writeable = 1;
8251 tr->usermode = 0;
8b006791 8252
1da5b61d 8253 vcpu_put(vcpu);
8b006791
ZX		 8254 return 0;
8255}
8256
d0752060
HB		 8257int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8258{
1393123e 8259 struct fxregs_state *fxsave;
d0752060 8260
1393123e 8261 vcpu_load(vcpu);
d0752060 8262
1393123e 8263 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8264 memcpy(fpu->fpr, fxsave->st_space, 128);
8265 fpu->fcw = fxsave->cwd;
8266 fpu->fsw = fxsave->swd;
8267 fpu->ftwx = fxsave->twd;
8268 fpu->last_opcode = fxsave->fop;
8269 fpu->last_ip = fxsave->rip;
8270 fpu->last_dp = fxsave->rdp;
8271 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8272
1393123e 8273 vcpu_put(vcpu);
d0752060
HB		 8274 return 0;
8275}
8276
8277int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8278{
6a96bc7f
CD		 8279 struct fxregs_state *fxsave;
8280
8281 vcpu_load(vcpu);
8282
8283 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8284
d0752060
HB		 8285 memcpy(fxsave->st_space, fpu->fpr, 128);
8286 fxsave->cwd = fpu->fcw;
8287 fxsave->swd = fpu->fsw;
8288 fxsave->twd = fpu->ftwx;
8289 fxsave->fop = fpu->last_opcode;
8290 fxsave->rip = fpu->last_ip;
8291 fxsave->rdp = fpu->last_dp;
8292 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8293
6a96bc7f 8294 vcpu_put(vcpu);
d0752060
HB		 8295 return 0;
8296}
8297
01643c51
KH		 8298static void store_regs(struct kvm_vcpu *vcpu)
8299{
8300 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8301
8302 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8303 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8304
8305 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8306 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8307
8308 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8309 kvm_vcpu_ioctl_x86_get_vcpu_events(
8310 vcpu, &vcpu->run->s.regs.events);
8311}
8312
8313static int sync_regs(struct kvm_vcpu *vcpu)
8314{
8315 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8316 return -EINVAL;
8317
8318 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8319 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8320 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8321 }
8322 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8323 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8324 return -EINVAL;
8325 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8326 }
8327 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8328 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8329 vcpu, &vcpu->run->s.regs.events))
8330 return -EINVAL;
8331 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8332 }
8333
8334 return 0;
8335}
8336
0ee6a517 8337static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8338{
bf935b0b 8339 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8340 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8341 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8342 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8343
2acf923e
DC		 8344 /*
8345 * Ensure guest xcr0 is valid for loading
8346 */
d91cab78 8347 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8348
ad312c7c 8349 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8350}
d0752060 8351
f775b13e 8352/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8353void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8354{
f775b13e
RR		 8355 preempt_disable();
8356 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8357 /* PKRU is separately restored in kvm_x86_ops->run. */
8358 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8359 ~XFEATURE_MASK_PKRU);
f775b13e 8360 preempt_enable();
0c04851c 8361 trace_kvm_fpu(1);
d0752060 8362}
d0752060 8363
f775b13e 8364/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8365void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8366{
f775b13e 8367 preempt_disable();
4f836347 8368 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8369 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8370 preempt_enable();
f096ed85 8371 ++vcpu->stat.fpu_reload;
0c04851c 8372 trace_kvm_fpu(0);
d0752060 8373}
e9b11c17
ZX		 8374
8375void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8376{
bd768e14
IY		 8377 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8378
12f9a48f 8379 kvmclock_reset(vcpu);
7f1ea208 8380
e9b11c17 8381 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8382 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8383}
8384
8385struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8386 unsigned int id)
8387{
c447e76b
LL		 8388 struct kvm_vcpu *vcpu;
8389
b0c39dc6 8390 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8391 printk_once(KERN_WARNING
8392 "kvm: SMP vm created on host with unstable TSC; "
8393 "guest TSC will not be reliable\n");
c447e76b
LL		 8394
8395 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8396
c447e76b 8397 return vcpu;
26e5215f 8398}
e9b11c17 8399
26e5215f
AK		 8400int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8401{
19efffa2 8402 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8403 vcpu_load(vcpu);
d28bc9dd 8404 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8405 kvm_mmu_setup(vcpu);
e9b11c17 8406 vcpu_put(vcpu);
ec7660cc 8407 return 0;
e9b11c17
ZX		 8408}
8409
31928aa5 8410void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8411{
8fe8ab46 8412 struct msr_data msr;
332967a3 8413 struct kvm *kvm = vcpu->kvm;
42897d86 8414
d3457c87
RK		 8415 kvm_hv_vcpu_postcreate(vcpu);
8416
ec7660cc 8417 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8418 return;
ec7660cc 8419 vcpu_load(vcpu);
8fe8ab46
WA		 8420 msr.data = 0x0;
8421 msr.index = MSR_IA32_TSC;
8422 msr.host_initiated = true;
8423 kvm_write_tsc(vcpu, &msr);
42897d86 8424 vcpu_put(vcpu);
ec7660cc 8425 mutex_unlock(&vcpu->mutex);
42897d86 8426
630994b3
MT		 8427 if (!kvmclock_periodic_sync)
8428 return;
8429
332967a3
AJ		 8430 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8431 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8432}
8433
d40ccc62 8434void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8435{
344d9588
GN		 8436 vcpu->arch.apf.msr_val = 0;
8437
ec7660cc 8438 vcpu_load(vcpu);
e9b11c17
ZX		 8439 kvm_mmu_unload(vcpu);
8440 vcpu_put(vcpu);
8441
8442 kvm_x86_ops->vcpu_free(vcpu);
8443}
8444
d28bc9dd 8445void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8446{
b7e31be3
RK		 8447 kvm_lapic_reset(vcpu, init_event);
8448
e69fab5d
PB		 8449 vcpu->arch.hflags = 0;
8450
c43203ca 8451 vcpu->arch.smi_pending = 0;
52797bf9 8452 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8453 atomic_set(&vcpu->arch.nmi_queued, 0);
8454 vcpu->arch.nmi_pending = 0;
448fa4a9 8455 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8456 kvm_clear_interrupt_queue(vcpu);
8457 kvm_clear_exception_queue(vcpu);
664f8e26 8458 vcpu->arch.exception.pending = false;
448fa4a9 8459
42dbaa5a 8460 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8461 kvm_update_dr0123(vcpu);
6f43ed01 8462 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8463 kvm_update_dr6(vcpu);
42dbaa5a 8464 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8465 kvm_update_dr7(vcpu);
42dbaa5a 8466
1119022c
NA		 8467 vcpu->arch.cr2 = 0;
8468
3842d135 8469 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8470 vcpu->arch.apf.msr_val = 0;
c9aaa895 8471 vcpu->arch.st.msr_val = 0;
3842d135 8472
12f9a48f
GC		 8473 kvmclock_reset(vcpu);
8474
af585b92
GN		 8475 kvm_clear_async_pf_completion_queue(vcpu);
8476 kvm_async_pf_hash_reset(vcpu);
8477 vcpu->arch.apf.halted = false;
3842d135 8478
a554d207
WL		 8479 if (kvm_mpx_supported()) {
8480 void *mpx_state_buffer;
8481
8482 /*
8483 * To avoid have the INIT path from kvm_apic_has_events() that be
8484 * called with loaded FPU and does not let userspace fix the state.
8485 */
f775b13e
RR		 8486 if (init_event)
8487 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8488 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8489 XFEATURE_MASK_BNDREGS);
8490 if (mpx_state_buffer)
8491 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8492 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8493 XFEATURE_MASK_BNDCSR);
8494 if (mpx_state_buffer)
8495 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8496 if (init_event)
8497 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8498 }
8499
64d60670 8500 if (!init_event) {
d28bc9dd 8501 kvm_pmu_reset(vcpu);
64d60670 8502 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8503
8504 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8505 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8506
8507 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8508 }
f5132b01 8509
66f7b72e
JS		 8510 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8511 vcpu->arch.regs_avail = ~0;
8512 vcpu->arch.regs_dirty = ~0;
8513
a554d207
WL		 8514 vcpu->arch.ia32_xss = 0;
8515
d28bc9dd 8516 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8517}
8518
2b4a273b 8519void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8520{
8521 struct kvm_segment cs;
8522
8523 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8524 cs.selector = vector << 8;
8525 cs.base = vector << 12;
8526 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8527 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8528}
8529
13a34e06 8530int kvm_arch_hardware_enable(void)
e9b11c17 8531{
ca84d1a2
ZA		 8532 struct kvm *kvm;
8533 struct kvm_vcpu *vcpu;
8534 int i;
0dd6a6ed
ZA		 8535 int ret;
8536 u64 local_tsc;
8537 u64 max_tsc = 0;
8538 bool stable, backwards_tsc = false;
18863bdd
AK		 8539
8540 kvm_shared_msr_cpu_online();
13a34e06 8541 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8542 if (ret != 0)
8543 return ret;
8544
4ea1636b 8545 local_tsc = rdtsc();
b0c39dc6 8546 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8547 list_for_each_entry(kvm, &vm_list, vm_list) {
8548 kvm_for_each_vcpu(i, vcpu, kvm) {
8549 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8550 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8551 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8552 backwards_tsc = true;
8553 if (vcpu->arch.last_host_tsc > max_tsc)
8554 max_tsc = vcpu->arch.last_host_tsc;
8555 }
8556 }
8557 }
8558
8559 /*
8560 * Sometimes, even reliable TSCs go backwards. This happens on
8561 * platforms that reset TSC during suspend or hibernate actions, but
8562 * maintain synchronization. We must compensate. Fortunately, we can
8563 * detect that condition here, which happens early in CPU bringup,
8564 * before any KVM threads can be running. Unfortunately, we can't
8565 * bring the TSCs fully up to date with real time, as we aren't yet far
8566 * enough into CPU bringup that we know how much real time has actually
108b249c 8567 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8568 * variables that haven't been updated yet.
8569 *
8570 * So we simply find the maximum observed TSC above, then record the
8571 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8572 * the adjustment will be applied. Note that we accumulate
8573 * adjustments, in case multiple suspend cycles happen before some VCPU
8574 * gets a chance to run again. In the event that no KVM threads get a
8575 * chance to run, we will miss the entire elapsed period, as we'll have
8576 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8577 * loose cycle time. This isn't too big a deal, since the loss will be
8578 * uniform across all VCPUs (not to mention the scenario is extremely
8579 * unlikely). It is possible that a second hibernate recovery happens
8580 * much faster than a first, causing the observed TSC here to be
8581 * smaller; this would require additional padding adjustment, which is
8582 * why we set last_host_tsc to the local tsc observed here.
8583 *
8584 * N.B. - this code below runs only on platforms with reliable TSC,
8585 * as that is the only way backwards_tsc is set above. Also note
8586 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8587 * have the same delta_cyc adjustment applied if backwards_tsc
8588 * is detected. Note further, this adjustment is only done once,
8589 * as we reset last_host_tsc on all VCPUs to stop this from being
8590 * called multiple times (one for each physical CPU bringup).
8591 *
4a969980 8592 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8593 * will be compensated by the logic in vcpu_load, which sets the TSC to
8594 * catchup mode. This will catchup all VCPUs to real time, but cannot
8595 * guarantee that they stay in perfect synchronization.
8596 */
8597 if (backwards_tsc) {
8598 u64 delta_cyc = max_tsc - local_tsc;
8599 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8600 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8601 kvm_for_each_vcpu(i, vcpu, kvm) {
8602 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8603 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8604 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8605 }
8606
8607 /*
8608 * We have to disable TSC offset matching.. if you were
8609 * booting a VM while issuing an S4 host suspend....
8610 * you may have some problem. Solving this issue is
8611 * left as an exercise to the reader.
8612 */
8613 kvm->arch.last_tsc_nsec = 0;
8614 kvm->arch.last_tsc_write = 0;
8615 }
8616
8617 }
8618 return 0;
e9b11c17
ZX		 8619}
8620
13a34e06 8621void kvm_arch_hardware_disable(void)
e9b11c17 8622{
13a34e06
RK		 8623 kvm_x86_ops->hardware_disable();
8624 drop_user_return_notifiers();
e9b11c17
ZX		 8625}
8626
8627int kvm_arch_hardware_setup(void)
8628{
9e9c3fe4
NA		 8629 int r;
8630
8631 r = kvm_x86_ops->hardware_setup();
8632 if (r != 0)
8633 return r;
8634
35181e86
HZ		 8635 if (kvm_has_tsc_control) {
8636 /*
8637 * Make sure the user can only configure tsc_khz values that
8638 * fit into a signed integer.
273ba457 8639 * A min value is not calculated because it will always
35181e86
HZ		 8640 * be 1 on all machines.
8641 */
8642 u64 max = min(0x7fffffffULL,
8643 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8644 kvm_max_guest_tsc_khz = max;
8645
ad721883 8646 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8647 }
ad721883 8648
9e9c3fe4
NA		 8649 kvm_init_msr_list();
8650 return 0;
e9b11c17
ZX		 8651}
8652
8653void kvm_arch_hardware_unsetup(void)
8654{
8655 kvm_x86_ops->hardware_unsetup();
8656}
8657
8658void kvm_arch_check_processor_compat(void *rtn)
8659{
8660 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8661}
8662
8663bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8664{
8665 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8666}
8667EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8668
8669bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8670{
8671 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8672}
8673
54e9818f 8674struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8675EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8676
e9b11c17
ZX		 8677int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8678{
8679 struct page *page;
e9b11c17
ZX		 8680 int r;
8681
b2a05fef 8682 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8683 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8684 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8685 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8686 else
a4535290 8687 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8688
8689 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8690 if (!page) {
8691 r = -ENOMEM;
8692 goto fail;
8693 }
ad312c7c 8694 vcpu->arch.pio_data = page_address(page);
e9b11c17 8695
cc578287 8696 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8697
e9b11c17
ZX		 8698 r = kvm_mmu_create(vcpu);
8699 if (r < 0)
8700 goto fail_free_pio_data;
8701
26de7988 8702 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8703 r = kvm_create_lapic(vcpu);
8704 if (r < 0)
8705 goto fail_mmu_destroy;
54e9818f
GN		 8706 } else
8707 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8708
890ca9ae
HY		 8709 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8710 GFP_KERNEL);
8711 if (!vcpu->arch.mce_banks) {
8712 r = -ENOMEM;
443c39bc 8713 goto fail_free_lapic;
890ca9ae
HY		 8714 }
8715 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8716
f1797359
WY		 8717 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8718 r = -ENOMEM;
f5f48ee1 8719 goto fail_free_mce_banks;
f1797359 8720 }
f5f48ee1 8721
0ee6a517 8722 fx_init(vcpu);
66f7b72e 8723
4344ee98 8724 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8725
5a4f55cd
EK		 8726 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8727
74545705
RK		 8728 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8729
af585b92 8730 kvm_async_pf_hash_reset(vcpu);
f5132b01 8731 kvm_pmu_init(vcpu);
af585b92 8732
1c1a9ce9 8733 vcpu->arch.pending_external_vector = -1;
de63ad4c 8734 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8735
5c919412
AS		 8736 kvm_hv_vcpu_init(vcpu);
8737
e9b11c17 8738 return 0;
0ee6a517 8739
f5f48ee1
SY		 8740fail_free_mce_banks:
8741 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8742fail_free_lapic:
8743 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8744fail_mmu_destroy:
8745 kvm_mmu_destroy(vcpu);
8746fail_free_pio_data:
ad312c7c 8747 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8748fail:
8749 return r;
8750}
8751
8752void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8753{
f656ce01
MT		 8754 int idx;
8755
1f4b34f8 8756 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8757 kvm_pmu_destroy(vcpu);
36cb93fd 8758 kfree(vcpu->arch.mce_banks);
e9b11c17 8759 kvm_free_lapic(vcpu);
f656ce01 8760 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8761 kvm_mmu_destroy(vcpu);
f656ce01 8762 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8763 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8764 if (!lapic_in_kernel(vcpu))
54e9818f 8765 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8766}
d19a9cd2 8767
e790d9ef
RK		 8768void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8769{
ae97a3b8 8770 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8771}
8772
e08b9637 8773int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8774{
e08b9637
CO		 8775 if (type)
8776 return -EINVAL;
8777
6ef768fa 8778 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8779 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8780 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8781 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8782 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8783
5550af4d
SY		 8784 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8785 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8786 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8787 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8788 &kvm->arch.irq_sources_bitmap);
5550af4d 8789
038f8c11 8790 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8791 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8792 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8793
108b249c 8794 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8795 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8796
7e44e449 8797 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8798 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8799
cbc0236a 8800 kvm_hv_init_vm(kvm);
0eb05bf2 8801 kvm_page_track_init(kvm);
13d268ca 8802 kvm_mmu_init_vm(kvm);
0eb05bf2 8803
03543133
SS		 8804 if (kvm_x86_ops->vm_init)
8805 return kvm_x86_ops->vm_init(kvm);
8806
d89f5eff 8807 return 0;
d19a9cd2
ZX		 8808}
8809
8810static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8811{
ec7660cc 8812 vcpu_load(vcpu);
d19a9cd2
ZX		 8813 kvm_mmu_unload(vcpu);
8814 vcpu_put(vcpu);
8815}
8816
8817static void kvm_free_vcpus(struct kvm *kvm)
8818{
8819 unsigned int i;
988a2cae 8820 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8821
8822 /*
8823 * Unpin any mmu pages first.
8824 */
af585b92
GN		 8825 kvm_for_each_vcpu(i, vcpu, kvm) {
8826 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8827 kvm_unload_vcpu_mmu(vcpu);
af585b92 8828 }
988a2cae
GN		 8829 kvm_for_each_vcpu(i, vcpu, kvm)
8830 kvm_arch_vcpu_free(vcpu);
8831
8832 mutex_lock(&kvm->lock);
8833 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8834 kvm->vcpus[i] = NULL;
d19a9cd2 8835
988a2cae
GN		 8836 atomic_set(&kvm->online_vcpus, 0);
8837 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8838}
8839
ad8ba2cd
SY		 8840void kvm_arch_sync_events(struct kvm *kvm)
8841{
332967a3 8842 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8843 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8844 kvm_free_pit(kvm);
ad8ba2cd
SY		 8845}
8846
1d8007bd 8847int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8848{
8849 int i, r;
25188b99 8850 unsigned long hva;
f0d648bd
PB		 8851 struct kvm_memslots *slots = kvm_memslots(kvm);
8852 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8853
8854 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8855 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8856 return -EINVAL;
9da0e4d5 8857
f0d648bd
PB		 8858 slot = id_to_memslot(slots, id);
8859 if (size) {
b21629da 8860 if (slot->npages)
f0d648bd
PB		 8861 return -EEXIST;
8862
8863 /*
8864 * MAP_SHARED to prevent internal slot pages from being moved
8865 * by fork()/COW.
8866 */
8867 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8868 MAP_SHARED | MAP_ANONYMOUS, 0);
8869 if (IS_ERR((void *)hva))
8870 return PTR_ERR((void *)hva);
8871 } else {
8872 if (!slot->npages)
8873 return 0;
8874
8875 hva = 0;
8876 }
8877
8878 old = *slot;
9da0e4d5 8879 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8880 struct kvm_userspace_memory_region m;
9da0e4d5 8881
1d8007bd
PB		 8882 m.slot = id | (i << 16);
8883 m.flags = 0;
8884 m.guest_phys_addr = gpa;
f0d648bd 8885 m.userspace_addr = hva;
1d8007bd 8886 m.memory_size = size;
9da0e4d5
PB		 8887 r = __kvm_set_memory_region(kvm, &m);
8888 if (r < 0)
8889 return r;
8890 }
8891
103c763c
EB		 8892 if (!size)
8893 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8894
9da0e4d5
PB		 8895 return 0;
8896}
8897EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8898
1d8007bd 8899int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8900{
8901 int r;
8902
8903 mutex_lock(&kvm->slots_lock);
1d8007bd 8904 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8905 mutex_unlock(&kvm->slots_lock);
8906
8907 return r;
8908}
8909EXPORT_SYMBOL_GPL(x86_set_memory_region);
8910
d19a9cd2
ZX		 8911void kvm_arch_destroy_vm(struct kvm *kvm)
8912{
27469d29
AH		 8913 if (current->mm == kvm->mm) {
8914 /*
8915 * Free memory regions allocated on behalf of userspace,
8916 * unless the the memory map has changed due to process exit
8917 * or fd copying.
8918 */
1d8007bd
PB		 8919 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8920 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8921 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8922 }
03543133
SS		 8923 if (kvm_x86_ops->vm_destroy)
8924 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8925 kvm_pic_destroy(kvm);
8926 kvm_ioapic_destroy(kvm);
d19a9cd2 8927 kvm_free_vcpus(kvm);
af1bae54 8928 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8929 kvm_mmu_uninit_vm(kvm);
2beb6dad 8930 kvm_page_track_cleanup(kvm);
cbc0236a 8931 kvm_hv_destroy_vm(kvm);
d19a9cd2 8932}
0de10343 8933
5587027c 8934void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8935 struct kvm_memory_slot *dont)
8936{
8937 int i;
8938
d89cc617
TY		 8939 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8940 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8941 kvfree(free->arch.rmap[i]);
d89cc617 8942 free->arch.rmap[i] = NULL;
77d11309 8943 }
d89cc617
TY		 8944 if (i == 0)
8945 continue;
8946
8947 if (!dont || free->arch.lpage_info[i - 1] !=
8948 dont->arch.lpage_info[i - 1]) {
548ef284 8949 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8950 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8951 }
8952 }
21ebbeda
XG		 8953
8954 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8955}
8956
5587027c
AK		 8957int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8958 unsigned long npages)
db3fe4eb
TY		 8959{
8960 int i;
8961
d89cc617 8962 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8963 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8964 unsigned long ugfn;
8965 int lpages;
d89cc617 8966 int level = i + 1;
db3fe4eb
TY		 8967
8968 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8969 slot->base_gfn, level) + 1;
8970
d89cc617 8971 slot->arch.rmap[i] =
778e1cdd
KC		 8972 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
8973 GFP_KERNEL);
d89cc617 8974 if (!slot->arch.rmap[i])
77d11309 8975 goto out_free;
d89cc617
TY		 8976 if (i == 0)
8977 continue;
77d11309 8978
778e1cdd 8979 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
92f94f1e 8980 if (!linfo)
db3fe4eb
TY		 8981 goto out_free;
8982
92f94f1e
XG		 8983 slot->arch.lpage_info[i - 1] = linfo;
8984
db3fe4eb 8985 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8986 linfo[0].disallow_lpage = 1;
db3fe4eb 8987 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8988 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8989 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8990 /*
8991 * If the gfn and userspace address are not aligned wrt each
8992 * other, or if explicitly asked to, disable large page
8993 * support for this slot
8994 */
8995 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8996 !kvm_largepages_enabled()) {
8997 unsigned long j;
8998
8999 for (j = 0; j < lpages; ++j)
92f94f1e 9000 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9001 }
9002 }
9003
21ebbeda
XG		 9004 if (kvm_page_track_create_memslot(slot, npages))
9005 goto out_free;
9006
db3fe4eb
TY		 9007 return 0;
9008
9009out_free:
d89cc617 9010 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9011 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9012 slot->arch.rmap[i] = NULL;
9013 if (i == 0)
9014 continue;
9015
548ef284 9016 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9017 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9018 }
9019 return -ENOMEM;
9020}
9021
15f46015 9022void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 9023{
e6dff7d1
TY		 9024 /*
9025 * memslots->generation has been incremented.
9026 * mmio generation may have reached its maximum value.
9027 */
54bf36aa 9028 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 9029}
9030
f7784b8e
MT		 9031int kvm_arch_prepare_memory_region(struct kvm *kvm,
9032 struct kvm_memory_slot *memslot,
09170a49 9033 const struct kvm_userspace_memory_region *mem,
7b6195a9 9034 enum kvm_mr_change change)
0de10343 9035{
f7784b8e
MT		 9036 return 0;
9037}
9038
88178fd4
KH		 9039static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9040 struct kvm_memory_slot *new)
9041{
9042 /* Still write protect RO slot */
9043 if (new->flags & KVM_MEM_READONLY) {
9044 kvm_mmu_slot_remove_write_access(kvm, new);
9045 return;
9046 }
9047
9048 /*
9049 * Call kvm_x86_ops dirty logging hooks when they are valid.
9050 *
9051 * kvm_x86_ops->slot_disable_log_dirty is called when:
9052 *
9053 * - KVM_MR_CREATE with dirty logging is disabled
9054 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9055 *
9056 * The reason is, in case of PML, we need to set D-bit for any slots
9057 * with dirty logging disabled in order to eliminate unnecessary GPA
9058 * logging in PML buffer (and potential PML buffer full VMEXT). This
9059 * guarantees leaving PML enabled during guest's lifetime won't have
9060 * any additonal overhead from PML when guest is running with dirty
9061 * logging disabled for memory slots.
9062 *
9063 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9064 * to dirty logging mode.
9065 *
9066 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9067 *
9068 * In case of write protect:
9069 *
9070 * Write protect all pages for dirty logging.
9071 *
9072 * All the sptes including the large sptes which point to this
9073 * slot are set to readonly. We can not create any new large
9074 * spte on this slot until the end of the logging.
9075 *
9076 * See the comments in fast_page_fault().
9077 */
9078 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9079 if (kvm_x86_ops->slot_enable_log_dirty)
9080 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9081 else
9082 kvm_mmu_slot_remove_write_access(kvm, new);
9083 } else {
9084 if (kvm_x86_ops->slot_disable_log_dirty)
9085 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9086 }
9087}
9088
f7784b8e 9089void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9090 const struct kvm_userspace_memory_region *mem,
8482644a 9091 const struct kvm_memory_slot *old,
f36f3f28 9092 const struct kvm_memory_slot *new,
8482644a 9093 enum kvm_mr_change change)
f7784b8e 9094{
8482644a 9095 int nr_mmu_pages = 0;
f7784b8e 9096
48c0e4e9
XG		 9097 if (!kvm->arch.n_requested_mmu_pages)
9098 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9099
48c0e4e9 9100 if (nr_mmu_pages)
0de10343 9101 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9102
3ea3b7fa
WL		 9103 /*
9104 * Dirty logging tracks sptes in 4k granularity, meaning that large
9105 * sptes have to be split. If live migration is successful, the guest
9106 * in the source machine will be destroyed and large sptes will be
9107 * created in the destination. However, if the guest continues to run
9108 * in the source machine (for example if live migration fails), small
9109 * sptes will remain around and cause bad performance.
9110 *
9111 * Scan sptes if dirty logging has been stopped, dropping those
9112 * which can be collapsed into a single large-page spte. Later
9113 * page faults will create the large-page sptes.
9114 */
9115 if ((change != KVM_MR_DELETE) &&
9116 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9117 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9118 kvm_mmu_zap_collapsible_sptes(kvm, new);
9119
c972f3b1 9120 /*
88178fd4 9121 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9122 *
88178fd4
KH		 9123 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9124 * been zapped so no dirty logging staff is needed for old slot. For
9125 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9126 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9127 *
9128 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9129 */
88178fd4 9130 if (change != KVM_MR_DELETE)
f36f3f28 9131 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9132}
1d737c8a 9133
2df72e9b 9134void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9135{
6ca18b69 9136 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9137}
9138
2df72e9b
MT		 9139void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9140 struct kvm_memory_slot *slot)
9141{
ae7cd873 9142 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9143}
9144
5d9bc648
PB		 9145static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9146{
9147 if (!list_empty_careful(&vcpu->async_pf.done))
9148 return true;
9149
9150 if (kvm_apic_has_events(vcpu))
9151 return true;
9152
9153 if (vcpu->arch.pv.pv_unhalted)
9154 return true;
9155
a5f01f8e
WL		 9156 if (vcpu->arch.exception.pending)
9157 return true;
9158
47a66eed
Z		 9159 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9160 (vcpu->arch.nmi_pending &&
9161 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9162 return true;
9163
47a66eed
Z		 9164 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9165 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9166 return true;
9167
5d9bc648
PB		 9168 if (kvm_arch_interrupt_allowed(vcpu) &&
9169 kvm_cpu_has_interrupt(vcpu))
9170 return true;
9171
1f4b34f8
AS		 9172 if (kvm_hv_has_stimer_pending(vcpu))
9173 return true;
9174
5d9bc648
PB		 9175 return false;
9176}
9177
1d737c8a
ZX		 9178int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9179{
5d9bc648 9180 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9181}
5736199a 9182
199b5763
LM		 9183bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9184{
de63ad4c 9185 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9186}
9187
b6d33834 9188int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9189{
b6d33834 9190 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9191}
78646121
GN		 9192
9193int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9194{
9195 return kvm_x86_ops->interrupt_allowed(vcpu);
9196}
229456fc 9197
82b32774 9198unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9199{
82b32774
NA		 9200 if (is_64_bit_mode(vcpu))
9201 return kvm_rip_read(vcpu);
9202 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9203 kvm_rip_read(vcpu));
9204}
9205EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9206
82b32774
NA		 9207bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9208{
9209 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9210}
9211EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9212
94fe45da
JK		 9213unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9214{
9215 unsigned long rflags;
9216
9217 rflags = kvm_x86_ops->get_rflags(vcpu);
9218 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9219 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9220 return rflags;
9221}
9222EXPORT_SYMBOL_GPL(kvm_get_rflags);
9223
6addfc42 9224static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9225{
9226 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9227 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9228 rflags |= X86_EFLAGS_TF;
94fe45da 9229 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9230}
9231
9232void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9233{
9234 __kvm_set_rflags(vcpu, rflags);
3842d135 9235 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9236}
9237EXPORT_SYMBOL_GPL(kvm_set_rflags);
9238
56028d08
GN		 9239void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9240{
9241 int r;
9242
fb67e14f 9243 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9244 work->wakeup_all)
56028d08
GN		 9245 return;
9246
9247 r = kvm_mmu_reload(vcpu);
9248 if (unlikely(r))
9249 return;
9250
fb67e14f
XG		 9251 if (!vcpu->arch.mmu.direct_map &&
9252 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9253 return;
9254
56028d08
GN		 9255 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9256}
9257
af585b92
GN		 9258static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9259{
9260 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9261}
9262
9263static inline u32 kvm_async_pf_next_probe(u32 key)
9264{
9265 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9266}
9267
9268static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9269{
9270 u32 key = kvm_async_pf_hash_fn(gfn);
9271
9272 while (vcpu->arch.apf.gfns[key] != ~0)
9273 key = kvm_async_pf_next_probe(key);
9274
9275 vcpu->arch.apf.gfns[key] = gfn;
9276}
9277
9278static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9279{
9280 int i;
9281 u32 key = kvm_async_pf_hash_fn(gfn);
9282
9283 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9284 (vcpu->arch.apf.gfns[key] != gfn &&
9285 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9286 key = kvm_async_pf_next_probe(key);
9287
9288 return key;
9289}
9290
9291bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9292{
9293 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9294}
9295
9296static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9297{
9298 u32 i, j, k;
9299
9300 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9301 while (true) {
9302 vcpu->arch.apf.gfns[i] = ~0;
9303 do {
9304 j = kvm_async_pf_next_probe(j);
9305 if (vcpu->arch.apf.gfns[j] == ~0)
9306 return;
9307 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9308 /*
9309 * k lies cyclically in ]i,j]
9310 * | i.k.j |
9311 * |....j i.k.| or |.k..j i...|
9312 */
9313 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9314 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9315 i = j;
9316 }
9317}
9318
7c90705b
GN		 9319static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9320{
4e335d9e
PB		 9321
9322 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9323 sizeof(val));
7c90705b
GN		 9324}
9325
9a6e7c39
WL		 9326static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9327{
9328
9329 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9330 sizeof(u32));
9331}
9332
af585b92
GN		 9333void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9334 struct kvm_async_pf *work)
9335{
6389ee94
AK		 9336 struct x86_exception fault;
9337
7c90705b 9338 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9339 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9340
9341 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9342 (vcpu->arch.apf.send_user_only &&
9343 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9344 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9345 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9346 fault.vector = PF_VECTOR;
9347 fault.error_code_valid = true;
9348 fault.error_code = 0;
9349 fault.nested_page_fault = false;
9350 fault.address = work->arch.token;
adfe20fb 9351 fault.async_page_fault = true;
6389ee94 9352 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9353 }
af585b92
GN		 9354}
9355
9356void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9357 struct kvm_async_pf *work)
9358{
6389ee94 9359 struct x86_exception fault;
9a6e7c39 9360 u32 val;
6389ee94 9361
f2e10669 9362 if (work->wakeup_all)
7c90705b
GN		 9363 work->arch.token = ~0; /* broadcast wakeup */
9364 else
9365 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9366 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9367
9a6e7c39
WL		 9368 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9369 !apf_get_user(vcpu, &val)) {
9370 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9371 vcpu->arch.exception.pending &&
9372 vcpu->arch.exception.nr == PF_VECTOR &&
9373 !apf_put_user(vcpu, 0)) {
9374 vcpu->arch.exception.injected = false;
9375 vcpu->arch.exception.pending = false;
9376 vcpu->arch.exception.nr = 0;
9377 vcpu->arch.exception.has_error_code = false;
9378 vcpu->arch.exception.error_code = 0;
9379 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9380 fault.vector = PF_VECTOR;
9381 fault.error_code_valid = true;
9382 fault.error_code = 0;
9383 fault.nested_page_fault = false;
9384 fault.address = work->arch.token;
9385 fault.async_page_fault = true;
9386 kvm_inject_page_fault(vcpu, &fault);
9387 }
7c90705b 9388 }
e6d53e3b 9389 vcpu->arch.apf.halted = false;
a4fa1635 9390 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9391}
9392
9393bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9394{
9395 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9396 return true;
9397 else
9bc1f09f 9398 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9399}
9400
5544eb9b
PB		 9401void kvm_arch_start_assignment(struct kvm *kvm)
9402{
9403 atomic_inc(&kvm->arch.assigned_device_count);
9404}
9405EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9406
9407void kvm_arch_end_assignment(struct kvm *kvm)
9408{
9409 atomic_dec(&kvm->arch.assigned_device_count);
9410}
9411EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9412
9413bool kvm_arch_has_assigned_device(struct kvm *kvm)
9414{
9415 return atomic_read(&kvm->arch.assigned_device_count);
9416}
9417EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9418
e0f0bbc5
AW		 9419void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9420{
9421 atomic_inc(&kvm->arch.noncoherent_dma_count);
9422}
9423EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9424
9425void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9426{
9427 atomic_dec(&kvm->arch.noncoherent_dma_count);
9428}
9429EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9430
9431bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9432{
9433 return atomic_read(&kvm->arch.noncoherent_dma_count);
9434}
9435EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9436
14717e20
AW		 9437bool kvm_arch_has_irq_bypass(void)
9438{
9439 return kvm_x86_ops->update_pi_irte != NULL;
9440}
9441
87276880
FW		 9442int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9443 struct irq_bypass_producer *prod)
9444{
9445 struct kvm_kernel_irqfd *irqfd =
9446 container_of(cons, struct kvm_kernel_irqfd, consumer);
9447
14717e20 9448 irqfd->producer = prod;
87276880 9449
14717e20
AW		 9450 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9451 prod->irq, irqfd->gsi, 1);
87276880
FW		 9452}
9453
9454void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9455 struct irq_bypass_producer *prod)
9456{
9457 int ret;
9458 struct kvm_kernel_irqfd *irqfd =
9459 container_of(cons, struct kvm_kernel_irqfd, consumer);
9460
87276880
FW		 9461 WARN_ON(irqfd->producer != prod);
9462 irqfd->producer = NULL;
9463
9464 /*
9465 * When producer of consumer is unregistered, we change back to
9466 * remapped mode, so we can re-use the current implementation
bb3541f1 9467 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9468 * int this case doesn't want to receive the interrupts.
9469 */
9470 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9471 if (ret)
9472 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9473 " fails: %d\n", irqfd->consumer.token, ret);
9474}
9475
9476int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9477 uint32_t guest_irq, bool set)
9478{
9479 if (!kvm_x86_ops->update_pi_irte)
9480 return -EINVAL;
9481
9482 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9483}
9484
52004014
FW		 9485bool kvm_vector_hashing_enabled(void)
9486{
9487 return vector_hashing;
9488}
9489EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9490
229456fc 9491EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9492EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9493EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9494EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9495EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9496EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9497EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9498EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9499EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9500EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9501EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9502EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9503EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9504EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9505EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9506EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9507EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9508EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9509EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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